From c1cb12789f1c9ecaf98b2d7e56da579dd8da5173 Mon Sep 17 00:00:00 2001 From: Akshay Gupta Date: Fri, 13 Jun 2025 12:54:18 +0530 Subject: [PATCH 1/5] misc: amd-apml: Create common header for sbtsi device Move out the sbtsi device structure to a common header file and add device matching helper function for I2C and I3C buses. This is required to add support for the APML Alert_L module which needs access to sbtsi device struct and device matching capability. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta --- drivers/misc/amd-apml/apml_sbtsi.c | 31 +++++++++++++++++++--------- drivers/misc/amd-apml/sbtsi-common.h | 22 ++++++++++++++++++++ 2 files changed, 43 insertions(+), 10 deletions(-) create mode 100644 drivers/misc/amd-apml/sbtsi-common.h diff --git a/drivers/misc/amd-apml/apml_sbtsi.c b/drivers/misc/amd-apml/apml_sbtsi.c index 36d29cad460b68..52029cc7866d9e 100644 --- a/drivers/misc/amd-apml/apml_sbtsi.c +++ b/drivers/misc/amd-apml/apml_sbtsi.c @@ -23,9 +23,9 @@ #include #include #include - #include +#include "sbtsi-common.h" /* * SB-TSI registers only support SMBus byte data access. "_INT" registers are * the integer part of a temperature value or limit, and "_DEC" registers are @@ -69,15 +69,6 @@ #define SBTSI_DEC_OFFSET 5 #define SBTSI_DEC_MASK 0x7 -struct apml_sbtsi_device { - struct miscdevice sbtsi_misc_dev; - struct i2c_client *client; - struct i3c_device *i3cdev; - struct regmap *regmap; - struct mutex lock; - u8 dev_static_addr; -} __packed; - /* * From SB-TSI spec: CPU temperature readings and limit registers encode the * temperature in increments of 0.125 from 0 to 255.875. The "high byte" @@ -639,6 +630,26 @@ static struct i2c_driver sbtsi_driver = { module_i3c_i2c_driver(sbtsi_i3c_driver, &sbtsi_driver) +int sbtsi_match_i3c(struct device *dev, const void *data) +{ + const struct device_node *node = (const struct device_node *)data; + + if (dev->of_node == node && dev->driver == &sbtsi_i3c_driver.driver) + return 1; + return 0; +} +EXPORT_SYMBOL_GPL(sbtsi_match_i3c); + +int sbtsi_match_i2c(struct device *dev, const void *data) +{ + const struct device_node *node = (const struct device_node *)data; + + if (dev->of_node == node && dev->driver == &sbtsi_driver.driver) + return 1; + return 0; +} +EXPORT_SYMBOL_GPL(sbtsi_match_i2c); + MODULE_AUTHOR("Kun Yi "); MODULE_DESCRIPTION("Hwmon driver for AMD SB-TSI emulated sensor"); MODULE_LICENSE("GPL"); diff --git a/drivers/misc/amd-apml/sbtsi-common.h b/drivers/misc/amd-apml/sbtsi-common.h new file mode 100644 index 00000000000000..24854981386275 --- /dev/null +++ b/drivers/misc/amd-apml/sbtsi-common.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * sbtsi-common.h - hwmon driver for a SBI Temperature Sensor Interface (SB-TSI) + * compliant AMD SoC temperature device. + * Also register to misc driver with an IOCTL. + * + * Copyright (c) 2020, Google Inc. + * Copyright (c) 2020, Kun Yi + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +struct apml_sbtsi_device { + struct miscdevice sbtsi_misc_dev; + struct i2c_client *client; + struct i3c_device *i3cdev; + struct regmap *regmap; + struct mutex lock; //lock for tsi devices + u8 dev_static_addr; +} __packed; + +int sbtsi_match_i2c(struct device *dev, const void *data); +int sbtsi_match_i3c(struct device *dev, const void *data); From a6950df07cb93488abd1095029380bd3954ed921 Mon Sep 17 00:00:00 2001 From: Akshay Gupta Date: Fri, 13 Jun 2025 12:53:26 +0530 Subject: [PATCH 2/5] misc: amd-apml: Add support for AMD APML Alert_L platform driver Processors from AMD provide APML ALERT_L for BMC users to monitor events. APML Alert_L is asserted in multiple events, - Machine Check Exception occurs within the system - The processor alerts the SBI on system fatal error event - Set by hardware as a result of a 0x71/0x72/0x73 command completion - Set by firmware to indicate the completion of a mailbox operation - High/Low Temperature Alert APML Alert_L module define uevents to notify registered userspace processes of the alert event. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Signed-off-by: sathya priya kumar --- drivers/misc/amd-apml/Kconfig | 16 ++ drivers/misc/amd-apml/Makefile | 1 + drivers/misc/amd-apml/apml_alertl.c | 380 ++++++++++++++++++++++++++++ drivers/misc/amd-apml/apml_alertl.h | 27 ++ include/uapi/linux/amd-apml.h | 32 ++- 5 files changed, 452 insertions(+), 4 deletions(-) create mode 100644 drivers/misc/amd-apml/apml_alertl.c create mode 100644 drivers/misc/amd-apml/apml_alertl.h diff --git a/drivers/misc/amd-apml/Kconfig b/drivers/misc/amd-apml/Kconfig index 6fed94971b0fb1..8a998afcd83e0f 100644 --- a/drivers/misc/amd-apml/Kconfig +++ b/drivers/misc/amd-apml/Kconfig @@ -24,3 +24,19 @@ config APML_SBTSI This driver can also be built as a module. If so, the module will be called apml_sbtsi. + +config APML_ALERTL + tristate "Emulated apml alertl interface driver over i3c bus" + depends on APML_SBRMI && APML_SBTSI + default n + help + This driver provides support for AMD APML Alert_L interface, + enabling alert notification from AMD SoCs to a BMC (Baseboard + Management Controller) over I2C/I3C bus. + + The driver monitors RAS and thermal events by handling alerts + from SBRMI and SBTSI devices, and reports these events to userspace + via uevents. Device configuration is managed via device tree bindings. + + This driver can also be built as a module. If so, the module will + be called apml_alertl.ko. diff --git a/drivers/misc/amd-apml/Makefile b/drivers/misc/amd-apml/Makefile index 7eef318915f122..864ea61baf6d2a 100644 --- a/drivers/misc/amd-apml/Makefile +++ b/drivers/misc/amd-apml/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_APML_SBRMI) += sbrmi.o sbrmi-common.o obj-$(CONFIG_APML_SBTSI) += apml_sbtsi.o +obj-$(CONFIG_APML_ALERTL) += apml_alertl.o diff --git a/drivers/misc/amd-apml/apml_alertl.c b/drivers/misc/amd-apml/apml_alertl.c new file mode 100644 index 00000000000000..8d8abee18a9bd6 --- /dev/null +++ b/drivers/misc/amd-apml/apml_alertl.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * apml_alertl.c - Alert_L driver for AMD APML devices + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "apml_alertl.h" + +#define DRIVER_NAME "apml_alertl" + +#define RAS_STATUS_REG 0x4C +#define RMI_STATUS_REG 0x2 +#define TSI_STATUS_REG 0x2 +#define RAS_ALERT_STATUS BIT(1) +#define RAS_ALERT_ASYNC BIT(3) + +#define MAX_SOC_LEN 11 +#define MAX_ERR_LEN 18 + +/* SBRMI and SBTSI static address for socket 0 and 1 */ +#define RMI_SOCK_0_DIE_0 0x3c +#define TSI_SOCK_0_DIE_0 0x4c +#define RMI_SOCK_1_DIE_0 0x38 +#define TSI_SOCK_1_DIE_0 0x48 + +MODULE_ALIAS("apml_alertl:" DRIVER_NAME); + +/* Map static address to socket and die index */ +static u8 static_addr_to_socket(u8 static_addr) +{ + /* + * [3:0] = Socket Index + * [7:4] = die Index + * Mapping: + * 0x3c, 0x4c -> Socket 0, die 0, + * 0x38, 0x48 -> Socket 1, die 0, + */ + switch (static_addr) { + case RMI_SOCK_0_DIE_0: + case TSI_SOCK_0_DIE_0: + return 0; + case RMI_SOCK_1_DIE_0: + case TSI_SOCK_1_DIE_0: + return 1; + default: + return 0xFF; + } +} + +/* Send a uevent to userspace for an APML alert */ +static int send_uevent(u8 static_address, u32 alert_src, struct device *dev) +{ + u8 soc_die_num; + char sock[MAX_SOC_LEN]; + char src[MAX_ERR_LEN]; + char *alert_source[] = { sock, src, NULL }; + + soc_die_num = static_addr_to_socket(static_address); + if (soc_die_num == 0xFF) + return -ENODEV; + + snprintf(sock, sizeof(sock), "Socket=0x%x", soc_die_num); + snprintf(src, sizeof(src), "Source=0x%x", alert_src); + + dev_dbg(dev, "Sending uevent: Sock:0x%x Src:0x%x\n", + soc_die_num, alert_src); + kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, alert_source); + return 0; +} + +/* Process and handle TSI alerts for all TSI devices */ +static void handle_tsi_alerts(struct apml_alertl_data *oob_adata) +{ + struct device *dev = oob_adata->dev; + struct apml_message msg = { 0 }; + int temp_status, ret, i; + + for (i = 0; i < oob_adata->num_of_tsi_devs; i++) { + temp_status = 0; + if (!oob_adata->tsi_dev[i] || !oob_adata->tsi_dev[i]->regmap) { + dev_dbg(dev, + "TSI device at index %d is NULL or regmap missing\n", + i); + continue; + } + + /* Read TSI Status register to identify the RAS error */ + msg.data_in.reg_in[REG_OFF_INDEX] = TSI_STATUS_REG; + + mutex_lock(&oob_adata->tsi_dev[i]->lock); + ret = regmap_read(oob_adata->tsi_dev[i]->regmap, + msg.data_in.reg_in[REG_OFF_INDEX], + &temp_status); + mutex_unlock(&oob_adata->tsi_dev[i]->lock); + + if (ret < 0) { + dev_dbg(dev, + "Failed to read temperature status of TSI device index %d\n", + i); + continue; + } + + if (!temp_status) + continue; + + ret = send_uevent(oob_adata->tsi_dev[i]->dev_static_addr, + temp_status << 24, dev); + if (ret) + dev_dbg(dev, + "Failed to send uevent for temperature alert TSI device index %d Err: %d\n", + i, ret); + } +} + +/* Process and handle RMI alerts for all RMI devices */ +static void handle_rmi_alerts(struct apml_alertl_data *oob_adata) +{ + struct device *dev = oob_adata->dev; + struct apml_message msg = { 0 }; + int ras_status, ret, i; + + for (i = 0; i < oob_adata->num_of_rmi_devs; i++) { + ras_status = 0; + if (!oob_adata->rmi_dev[i] || !oob_adata->rmi_dev[i]->regmap) { + dev_dbg(dev, + "RMI device at index %d is NULL or regmap missing\n", + i); + continue; + } + + /* Read RAS Status register to identify the RAS error */ + msg.data_in.reg_in[REG_OFF_INDEX] = RAS_STATUS_REG; + + mutex_lock(&oob_adata->rmi_dev[i]->lock); + ret = regmap_read(oob_adata->rmi_dev[i]->regmap, + msg.data_in.reg_in[REG_OFF_INDEX], + &ras_status); + mutex_unlock(&oob_adata->rmi_dev[i]->lock); + + if (ret < 0) { + dev_dbg(dev, "Failed to read RAS status of RMI device index %d\n", i); + continue; + } + + if (!ras_status) + continue; + + ret = send_uevent(oob_adata->rmi_dev[i]->dev_static_addr, ras_status, dev); + if (ret) + dev_dbg(dev, + "Failed to send uevent for RAS alert for device %d Err: %d\n", + i, ret); + + /* Clear the RMI Status and RAS Status register 0x4C */ + mutex_lock(&oob_adata->rmi_dev[i]->lock); + msg.data_in.reg_in[REG_OFF_INDEX] = RAS_STATUS_REG; + ret = regmap_write(oob_adata->rmi_dev[i]->regmap, + msg.data_in.reg_in[REG_OFF_INDEX], + ras_status); + if (ret < 0) + dev_dbg(dev, + "Could not clear RAS status register for device %d\n", + i); + + msg.data_in.reg_in[REG_OFF_INDEX] = RMI_STATUS_REG; + ret = regmap_write(oob_adata->rmi_dev[i]->regmap, + msg.data_in.reg_in[REG_OFF_INDEX], + RAS_ALERT_ASYNC); + mutex_unlock(&oob_adata->rmi_dev[i]->lock); + if (ret < 0) + dev_dbg(dev, + "Could not clear RMI status register at device %d\n", + i); + } +} + +/* Handles Alert_L interrupts by delegating to TSI and RMI alert handlers */ +static irqreturn_t alert_l_irq_thread_handler(int irq, void *dev_id) +{ + struct apml_alertl_data *oob_adata = (struct apml_alertl_data *)dev_id; + struct device *dev; + + dev = oob_adata->dev; + + handle_tsi_alerts(oob_adata); + handle_rmi_alerts(oob_adata); + + return IRQ_HANDLED; +} + +/* Retrieve APML device from device tree */ +static void *get_apml_dev_byphandle(struct device_node *dnode, + const char *phandle_name, + int index) +{ + struct device_node *d_node; + struct device *dev; + void *apml_dev; + + if (!phandle_name || !dnode) + return NULL; + + d_node = of_parse_phandle(dnode, phandle_name, index); + if (IS_ERR_OR_NULL(d_node)) { + pr_err("Failed to parse phandle '%s' at index %d\n", + phandle_name, index); + return NULL; + } + + if (strcmp(phandle_name, "sbrmi") == 0) { + dev = bus_find_device(&i3c_bus_type, NULL, d_node, sbrmi_match_i3c); + if (!dev) { + dev = bus_find_device(&i2c_bus_type, NULL, d_node, sbrmi_match_i2c); + if (IS_ERR_OR_NULL(dev)) { + of_node_put(d_node); + return NULL; + } + } + } else if (strcmp(phandle_name, "sbtsi") == 0) { + dev = bus_find_device(&i3c_bus_type, NULL, d_node, sbtsi_match_i3c); + if (!dev) { + dev = bus_find_device(&i2c_bus_type, NULL, d_node, sbtsi_match_i2c); + if (IS_ERR_OR_NULL(dev)) { + of_node_put(d_node); + return NULL; + } + } + } + + of_node_put(d_node); + apml_dev = dev_get_drvdata(dev); + if (IS_ERR_OR_NULL(apml_dev)) + return NULL; + + return apml_dev; +} + +static int apml_alertl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *dnode = dev->of_node; + struct apml_sbrmi_device **rmi_dev; + struct apml_sbtsi_device **tsi_dev; + struct apml_alertl_data *oob_alert; + struct gpio_desc *alertl_gpiod; + char *irq_name; + u32 irq_num; + u8 socket_num; + int ret, i; + + /* Allocate memory to oob_alert_data structure */ + oob_alert = devm_kzalloc(dev, sizeof(struct apml_alertl_data), + GFP_KERNEL); + if (!oob_alert) + return -ENOMEM; + + /* identify the number of devices associated with each RMI alert */ + oob_alert->num_of_rmi_devs = of_property_count_elems_of_size(dnode, "sbrmi", + sizeof(phandle)); + + /* identify the number of devices associated with each TSI alert */ + oob_alert->num_of_tsi_devs = of_property_count_elems_of_size(dnode, "sbtsi", + sizeof(phandle)); + + /* Allocate memory as per the number of RMI devices */ + rmi_dev = devm_kzalloc(dev, oob_alert->num_of_rmi_devs * sizeof(struct apml_sbrmi_device), + GFP_KERNEL); + if (!rmi_dev) + return -ENOMEM; + oob_alert->rmi_dev = rmi_dev; + + /* Allocate memory as per the number of TSI devices */ + tsi_dev = devm_kzalloc(dev, oob_alert->num_of_tsi_devs * sizeof(struct apml_sbtsi_device), + GFP_KERNEL); + if (!tsi_dev) + return -ENOMEM; + + oob_alert->tsi_dev = tsi_dev; + oob_alert->dev = dev; + + /* + * For each of the Alerts get the device associated + * Currently the ALert_L driver identification is only supported + * over I3C. We can add property in dts to identify the bus type + */ + for (i = 0; i < oob_alert->num_of_rmi_devs; i++) { + rmi_dev[i] = get_apml_dev_byphandle(pdev->dev.of_node, "sbrmi", i); + if (!rmi_dev[i]) { + dev_err(dev, "RMI device %d not found\n", i); + return -ENODEV; + } + } + + for (i = 0; i < oob_alert->num_of_tsi_devs; i++) { + tsi_dev[i] = get_apml_dev_byphandle(pdev->dev.of_node, "sbtsi", i); + if (!tsi_dev[i]) { + dev_err(dev, "TSI device %d not found\n", i); + return -ENODEV; + } + } + + /* Get the alert_l gpios, irq_number for the GPIO and register ISR*/ + alertl_gpiod = devm_gpiod_get(dev, NULL, GPIOD_IN); + if (IS_ERR(alertl_gpiod)) { + dev_err(&pdev->dev, "Unable to retrieve gpio\n"); + return PTR_ERR(alertl_gpiod); + } + + irq_num = gpiod_to_irq(alertl_gpiod); + if (irq_num < 0) { + dev_err(dev, "No corresponding IRQ for GPIO, error: %d\n", irq_num); + return irq_num; + } + + if (oob_alert->num_of_rmi_devs > 0 && oob_alert->rmi_dev[0]) + socket_num = static_addr_to_socket(oob_alert->rmi_dev[0]->dev_static_addr); + else if (oob_alert->num_of_tsi_devs > 0 && oob_alert->tsi_dev[0]) + socket_num = static_addr_to_socket(oob_alert->tsi_dev[0]->dev_static_addr); + + irq_name = devm_kasprintf(dev, GFP_KERNEL, "apml_irq%u", socket_num); + if (!irq_name) { + dev_dbg(dev, "Failed to allocate IRQ name\n"); + return -ENOMEM; + } + + dev_dbg(dev, "Register IRQ:%u\n", irq_num); + ret = devm_request_threaded_irq(dev, irq_num, + NULL, + (void *)alert_l_irq_thread_handler, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + irq_name, oob_alert); + if (ret) { + dev_dbg(dev, "Cannot register IRQ:%u\n", irq_num); + return ret; + } + + /* Set the platform data to pdev */ + platform_set_drvdata(pdev, oob_alert); + + return 0; +} + +static int apml_alertl_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id apml_alertl_dt_ids[] = { + {.compatible = "apml-alertl", }, + {}, +}; +MODULE_DEVICE_TABLE(of, apml_alertl_dt_ids); + +static struct platform_driver apml_alertl_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = of_match_ptr(apml_alertl_dt_ids), + }, + .probe = apml_alertl_probe, + .remove = apml_alertl_remove, +}; + +module_platform_driver(apml_alertl_driver); + +MODULE_AUTHOR("Akshay Gupta "); +MODULE_AUTHOR("Naveenkrishna Chatradhi "); +MODULE_DESCRIPTION("AMD APML ALERT_L Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/misc/amd-apml/apml_alertl.h b/drivers/misc/amd-apml/apml_alertl.h new file mode 100644 index 00000000000000..37568e8b9f5834 --- /dev/null +++ b/drivers/misc/amd-apml/apml_alertl.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _AMD_APML_ALERT_L__ +#define _AMD_APML_ALERT_L__ + +#include "sbrmi-common.h" +#include "sbtsi-common.h" + +/* APML_ALERTL Sends uevent to userspace for temparature + * alert and RAS (fatal and non-fatal) error, including + * environmental data such as socket/die and alertl source + * information. + */ + +struct apml_alertl_data { + struct apml_sbrmi_device **rmi_dev; + struct apml_sbtsi_device **tsi_dev; + struct device *dev; + atomic_t removed; + u8 num_of_rmi_devs; + u8 num_of_tsi_devs; +} __packed; + +#endif /*_AMD_APML_ALERT_L__*/ diff --git a/include/uapi/linux/amd-apml.h b/include/uapi/linux/amd-apml.h index d52f3a172faf83..cfcafe555b0383 100644 --- a/include/uapi/linux/amd-apml.h +++ b/include/uapi/linux/amd-apml.h @@ -1,17 +1,41 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * Copyright (C) 2021-2022 Advanced Micro Devices, Inc. + * Copyright (C) 2025 Advanced Micro Devices, Inc. */ #ifndef _AMD_APML_H_ #define _AMD_APML_H_ #include +#ifndef BIT +#define BIT(n) (1U << (n)) +#endif + /* - * Currently signal 33 to 64 are unused, - * using user signal number from that range + * APML RAS and Temperature alert source. Uevent + * returns 32 bit value which is sent to userspace. + * [23:0]: defined for RAS Alerts + * SBRMI RAS register 0x4C. RAS alert register bits(0-6) + * + * [31:24] : defined for Temperature Alerts + * SBTSI Temp register 0x02. socket temperature alert bits(3 & 4) + * + * Note: Additional Alert_L bit definition may be added in future + * for RAS alert extension + * */ -#define USR_SIGNAL 44 + +enum apml_alert_src { + APML_FATAL_ALERT = BIT(0), + APML_FCH_ALERT = BIT(1), + APML_RESET_CTRL_ALERT = BIT(2), + APML_MCA_ALERT = BIT(3), + APML_DRAM_CECC_ALERT = BIT(4), + APML_PCIE_ALERT = BIT(5), + APML_CPU_SHUTDOWN_ALERT = BIT(6), + APML_TEMP_LOW_ALERT = BIT(27), + APML_TEMP_HIGH_ALERT = BIT(28), +}; enum apml_protocol { APML_CPUID = 0x1000, From 4f956385e7a1ed86ef8598d0945932bc16baad15 Mon Sep 17 00:00:00 2001 From: sathya priya kumar Date: Tue, 1 Jul 2025 18:22:22 +0530 Subject: [PATCH 3/5] arm64: dts: aspeed: Alert_L changes for Morocco & Congo -Add alertl node for P1 and P2 host processor in Morocco platform. -Add alertl node for P1 host processor in Congo platform. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Signed-off-by: sathya priya kumar --- .../boot/dts/aspeed/aspeed-bmc-amd-congo.dts | 11 ++++++++++ .../dts/aspeed/aspeed-bmc-amd-morocco.dts | 20 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-congo.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-congo.dts index 4e64c2d5367e48..d2545615d3432a 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-congo.dts +++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-congo.dts @@ -907,6 +907,17 @@ #endif }; +/ { + /* Alert_L associated with socket 0 */ + alertl_sock0 { + compatible = "apml-alertl"; + status = "okay"; + gpios = <<pi0_gpio 20 GPIO_ACTIVE_LOW>; + sbrmi = <&sbrmi_p0_iod0>; + sbtsi = <&sbtsi_p0_iod0>; + }; +}; + #ifdef I3C_HUB #define JESD300_SPD_I3C_MODE(bus, index, addr) \ diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-morocco.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-morocco.dts index e983f1c7cc5c0b..5580fdd4222a2d 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-morocco.dts +++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-morocco.dts @@ -1015,6 +1015,26 @@ #endif }; +/ { + /* Alert_L associated with socket 0 */ + alertl_sock0 { + compatible = "apml-alertl"; + status = "okay"; + gpios = <<pi0_gpio 20 GPIO_ACTIVE_LOW>; + sbrmi = <&sbrmi_p0_iod0>; + sbtsi = <&sbtsi_p0_iod0>; + }; + + /* Alert_L associated with socket 1 */ + alertl_sock1 { + compatible = "apml-alertl"; + status = "okay"; + gpios = <<pi0_gpio 104 GPIO_ACTIVE_LOW>; + sbrmi = <&sbrmi_p1_iod0>; + sbtsi = <&sbtsi_p1_iod0>; + }; +}; + #ifdef I3C_HUB #define JESD300_SPD_I3C_MODE(bus, index, addr) \ From ba78da2014932ce60f3ec1f3bd6e521adbddde02 Mon Sep 17 00:00:00 2001 From: sathya priya kumar Date: Tue, 1 Jul 2025 18:26:26 +0530 Subject: [PATCH 4/5] arm64: dts: aspeed: Alert_L changes for Kenya & Nigeria -Add alertl node for P1 and P2 host processor in Nigeria platform. -Add alertl node for P1 host processor in Kenya platform. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Signed-off-by: sathya priya kumar --- .../boot/dts/aspeed/aspeed-bmc-amd-kenya.dts | 11 ++++++++++ .../dts/aspeed/aspeed-bmc-amd-nigeria.dts | 20 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-kenya.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-kenya.dts index 5568599635636b..39da8c6b9055d7 100755 --- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-kenya.dts +++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-kenya.dts @@ -597,6 +597,17 @@ #endif }; +/ { + /* Alert_L associated with socket 0 */ + alertl_sock0 { + compatible = "apml-alertl"; + status = "okay"; + gpios = <<pi0_gpio 20 GPIO_ACTIVE_LOW>; + sbrmi = <&sbrmi_p0_iod0>; + sbtsi = <&sbtsi_p0_iod0>; + }; +}; + #ifdef I3C_HUB #define JESD300_SPD_I3C_MODE(bus, index, addr) \ diff --git a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-nigeria.dts b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-nigeria.dts index f0f2d52b8ea363..6b657fe718fc37 100755 --- a/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-nigeria.dts +++ b/arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-nigeria.dts @@ -782,6 +782,26 @@ #endif }; +/ { + /* Alert_L associated with socket 0 */ + alertl_sock0 { + compatible = "apml-alertl"; + status = "okay"; + gpios = <<pi0_gpio 20 GPIO_ACTIVE_LOW>; + sbrmi = <&sbrmi_p0_iod0>; + sbtsi = <&sbtsi_p0_iod0>; + }; + + /* Alert_L associated with socket 1 */ + alertl_sock1 { + compatible = "apml-alertl"; + status = "okay"; + gpios = <<pi0_gpio 104 GPIO_ACTIVE_LOW>; + sbrmi = <&sbrmi_p1_iod0>; + sbtsi = <&sbtsi_p1_iod0>; + }; +}; + #ifdef I3C_HUB #define JESD300_SPD_I3C_MODE(bus, index, addr) \ From f92762f9fe35d1cf311f6eac302bb2da7792aab4 Mon Sep 17 00:00:00 2001 From: Akshay Gupta Date: Tue, 3 Jun 2025 10:25:25 +0000 Subject: [PATCH 5/5] dt-bindings: misc: apml-alertl: Add APML Alert_L bindings -Document device-tree bindings for APML Alert_L driver. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Signed-off-by: sathya priya kumar (cherry picked from commit 0f54429b0d8f9a2e935fa7c300601444ba54ea15) --- .../bindings/misc/amd,apml-alertl.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/amd,apml-alertl.yaml diff --git a/Documentation/devicetree/bindings/misc/amd,apml-alertl.yaml b/Documentation/devicetree/bindings/misc/amd,apml-alertl.yaml new file mode 100644 index 00000000000000..d28baa9c0d541f --- /dev/null +++ b/Documentation/devicetree/bindings/misc/amd,apml-alertl.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/amd,apml-alertl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: > + Sideband Remote Management Interface (SB-RMI) compliant + AMD APML Alert_L GPIO. + +maintainers: + - Akshay Gupta + +description: | + Processors from AMD provide APML ALERT_L for BMC users to + monitor events. + APML Alert_L is asserted in multiple events, + - Machine Check Exception occurs within the system + - The processor alerts the SBI on system fatal error event + - Set by hardware as a result of a 0x71/0x72/0x73 command completion + - Set by firmware to indicate the completion of a mailbox operation + - High/Low Temperature Alert + + APML Alert_L module define uevents to notify userspace of the + alert event. + +properties: + compatible: + const: apml-alertl + + gpio: + maxItems: 1 + description: | + GPIO specifier for APML Alert_L line. Specify GPIO controller, GPIO pin + and polarity. + + sbrmi: + $ref: /schemas/types.yaml#/definitions/phandle + description: ref amd,sbrmi.yaml + + sbtsi: + $ref: /schemas/types.yaml#/definitions/phandle + description: ref amd,sbtsi.yaml + +required: + - compatible + - gpio + - sbrmi + - sbtsi + +additionalProperties: false + +examples: + - | + /* Alert_L associated with Socket 0 */ + alertl_sock0 { + compatible = "apml-alertl"; + status = "okay"; + gpios = <<pi0_gpio 20 GPIO_ACTIVE_LOW>; + sbrmi = <&sbrmi_p0_iod0>; + sbtsi = <&sbtsi_p0_iod0>; + }; +...