diff --git a/nand2tetris/projects/5/CPU-external.out b/nand2tetris/projects/5/CPU-external.out new file mode 100644 index 0000000..5f205a0 --- /dev/null +++ b/nand2tetris/projects/5/CPU-external.out @@ -0,0 +1,97 @@ +|time | inM | instruction |reset| outM |writeM|address| pc | +| 0+ | 0|0011000000111001| 0 | 0| 0 | 0 | 0| +| 1 | 0|0011000000111001| 0 | 0| 0 | 12345 | 1| +| 1+ | 0|1110110000010000| 0 | 12345| 0 | 12345 | 1| +| 2 | 0|1110110000010000| 0 | 12345| 0 | 12345 | 2| +| 2+ | 0|0101101110100000| 0 | -1| 0 | 12345 | 2| +| 3 | 0|0101101110100000| 0 | -1| 0 | 23456 | 3| +| 3+ | 0|1110000111110000| 0 | 11111| 0 | 23456 | 3| +| 4 | 0|1110000111110000| 0 | 0| 0 | 11111 | 4| +| 4+ | 0|0000001111101011| 0 | -11111| 0 | 11111 | 4| +| 5 | 0|0000001111101011| 0 | -11111| 0 | 1003 | 5| +| 5+ | 0|1110001100001000| 0 | 11111| 1 | 1003 | 5| +| 6 | 0|1110001100001000| 0 | 11111| 1 | 1003 | 6| +| 6+ | 0|0000001111101100| 0 | -11111| 0 | 1003 | 6| +| 7 | 0|0000001111101100| 0 | -11111| 0 | 1004 | 7| +| 7+ | 0|1110001110011000| 0 | 11110| 1 | 1004 | 7| +| 8 | 0|1110001110011000| 0 | 11109| 1 | 1004 | 8| +| 8+ | 0|0000001111101000| 0 | -11110| 0 | 1004 | 8| +| 9 | 0|0000001111101000| 0 | -11110| 0 | 1000 | 9| +| 9+ | 11111|1111010011110000| 0 | -1| 0 | 1000 | 9| +| 10 | 11111|1111010011110000| 0 | -11112| 0 | 32767 | 10| +| 10+ | 11111|0000000000001110| 0 | -1| 0 | 32767 | 10| +| 11 | 11111|0000000000001110| 0 | 14| 0 | 14 | 11| +| 11+ | 11111|1110001100000100| 0 | -1| 0 | 14 | 11| +| 12 | 11111|1110001100000100| 0 | -1| 0 | 14 | 14| +| 12+ | 11111|0000001111100111| 0 | 1| 0 | 14 | 14| +| 13 | 11111|0000001111100111| 0 | 1| 0 | 999 | 15| +| 13+ | 11111|1111110111100000| 0 | 11112| 0 | 999 | 15| +| 14 | 11111|1111110111100000| 0 | 11112| 0 | 11112 | 16| +| 14+ | 11111|1110001100101000| 0 | -1| 1 | 11112 | 16| +| 15 | 11111|1110001100101000| 0 | -1| 1 | 32767 | 17| +| 15+ | 11111|0000000000010101| 0 | -1| 0 | 32767 | 17| +| 16 | 11111|0000000000010101| 0 | 21| 0 | 21 | 18| +| 16+ | 11111|1110011111000010| 0 | 0| 0 | 21 | 18| +| 17 | 11111|1110011111000010| 0 | 0| 0 | 21 | 21| +| 17+ | 11111|0000000000000010| 0 | 21| 0 | 21 | 21| +| 18 | 11111|0000000000000010| 0 | 2| 0 | 2 | 22| +| 18+ | 11111|1110000010111000| 0 | 1| 1 | 2 | 22| +| 19 | 11111|1110000010111000| 0 | 2| 1 | 1 | 23| +| 19+ | 11111|1111110111001000| 0 | 11112| 1 | 1 | 23| +| 20 | 11111|1111110111001000| 0 | 11112| 1 | 1 | 24| +| 20+ | 11111|1111110010101000| 0 | 11110| 1 | 1 | 24| +| 21 | 11111|1111110010101000| 0 | 11110| 1 | 11110 | 25| +| 21+ | 11111|0000001111101000| 0 | -1| 0 | 11110 | 25| +| 22 | 11111|0000001111101000| 0 | -1| 0 | 1000 | 26| +| 22+ | 11111|1110111010010000| 0 | -1| 0 | 1000 | 26| +| 23 | 11111|1110111010010000| 0 | -1| 0 | 1000 | 27| +| 23+ | 11111|1110001100000001| 0 | -1| 0 | 1000 | 27| +| 24 | 11111|1110001100000001| 0 | -1| 0 | 1000 | 28| +| 24+ | 11111|1110001100000010| 0 | -1| 0 | 1000 | 28| +| 25 | 11111|1110001100000010| 0 | -1| 0 | 1000 | 29| +| 25+ | 11111|1110001100000011| 0 | -1| 0 | 1000 | 29| +| 26 | 11111|1110001100000011| 0 | -1| 0 | 1000 | 30| +| 26+ | 11111|1110001100000100| 0 | -1| 0 | 1000 | 30| +| 27 | 11111|1110001100000100| 0 | -1| 0 | 1000 | 1000| +| 27+ | 11111|1110001100000101| 0 | -1| 0 | 1000 | 1000| +| 28 | 11111|1110001100000101| 0 | -1| 0 | 1000 | 1000| +| 28+ | 11111|1110001100000110| 0 | -1| 0 | 1000 | 1000| +| 29 | 11111|1110001100000110| 0 | -1| 0 | 1000 | 1000| +| 29+ | 11111|1110001100000111| 0 | -1| 0 | 1000 | 1000| +| 30 | 11111|1110001100000111| 0 | -1| 0 | 1000 | 1000| +| 30+ | 11111|1110101010010000| 0 | 0| 0 | 1000 | 1000| +| 31 | 11111|1110101010010000| 0 | 0| 0 | 1000 | 1001| +| 31+ | 11111|1110001100000001| 0 | 0| 0 | 1000 | 1001| +| 32 | 11111|1110001100000001| 0 | 0| 0 | 1000 | 1002| +| 32+ | 11111|1110001100000010| 0 | 0| 0 | 1000 | 1002| +| 33 | 11111|1110001100000010| 0 | 0| 0 | 1000 | 1000| +| 33+ | 11111|1110001100000011| 0 | 0| 0 | 1000 | 1000| +| 34 | 11111|1110001100000011| 0 | 0| 0 | 1000 | 1000| +| 34+ | 11111|1110001100000100| 0 | 0| 0 | 1000 | 1000| +| 35 | 11111|1110001100000100| 0 | 0| 0 | 1000 | 1001| +| 35+ | 11111|1110001100000101| 0 | 0| 0 | 1000 | 1001| +| 36 | 11111|1110001100000101| 0 | 0| 0 | 1000 | 1002| +| 36+ | 11111|1110001100000110| 0 | 0| 0 | 1000 | 1002| +| 37 | 11111|1110001100000110| 0 | 0| 0 | 1000 | 1000| +| 37+ | 11111|1110001100000111| 0 | 0| 0 | 1000 | 1000| +| 38 | 11111|1110001100000111| 0 | 0| 0 | 1000 | 1000| +| 38+ | 11111|1110111111010000| 0 | 1| 0 | 1000 | 1000| +| 39 | 11111|1110111111010000| 0 | 1| 0 | 1000 | 1001| +| 39+ | 11111|1110001100000001| 0 | 1| 0 | 1000 | 1001| +| 40 | 11111|1110001100000001| 0 | 1| 0 | 1000 | 1000| +| 40+ | 11111|1110001100000010| 0 | 1| 0 | 1000 | 1000| +| 41 | 11111|1110001100000010| 0 | 1| 0 | 1000 | 1001| +| 41+ | 11111|1110001100000011| 0 | 1| 0 | 1000 | 1001| +| 42 | 11111|1110001100000011| 0 | 1| 0 | 1000 | 1000| +| 42+ | 11111|1110001100000100| 0 | 1| 0 | 1000 | 1000| +| 43 | 11111|1110001100000100| 0 | 1| 0 | 1000 | 1001| +| 43+ | 11111|1110001100000101| 0 | 1| 0 | 1000 | 1001| +| 44 | 11111|1110001100000101| 0 | 1| 0 | 1000 | 1000| +| 44+ | 11111|1110001100000110| 0 | 1| 0 | 1000 | 1000| +| 45 | 11111|1110001100000110| 0 | 1| 0 | 1000 | 1001| +| 45+ | 11111|1110001100000111| 0 | 1| 0 | 1000 | 1001| +| 46 | 11111|1110001100000111| 0 | 1| 0 | 1000 | 1000| +| 46+ | 11111|1110001100000111| 1 | 1| 0 | 1000 | 1000| +| 47 | 11111|1110001100000111| 1 | 1| 0 | 1000 | 0| +| 47+ | 11111|0111111111111111| 0 | 1| 0 | 1000 | 0| +| 48 | 11111|0111111111111111| 0 | 1| 0 | 32767 | 1| diff --git a/nand2tetris/projects/5/CPU.hdl b/nand2tetris/projects/5/CPU.hdl index bc30e47..9f61460 100644 --- a/nand2tetris/projects/5/CPU.hdl +++ b/nand2tetris/projects/5/CPU.hdl @@ -32,5 +32,129 @@ CHIP CPU { pc[15]; // address of next instruction PARTS: - //// Replace this comment with your code. + + + // Instruction Mux + Mux16( + a = instruction, + b = ALUout, + sel = instruction[15], + out = MuxInstructionOut + ); + + And(a = instruction[15], + b = instruction[5], + out = loadAtmp); + Not(in = instruction[15], + out = notIns15); + Or(a = loadAtmp, + b = notIns15, + out = loadA); + +// And(a = instruction[15], +// b = instruction[5], +// out = loadA); + // A register + ARegister( + in = MuxInstructionOut, + load = loadA, + out = Aout, // ALU Mux and PC + out[0..14] = addressM + ); + + // ALU Mux + Mux16( + a = Aout, + b = inM, + sel = instruction[12], + out = MuxAMout + ); + + // DRegister load + And(a = instruction[15], + b = instruction[4], + out = loadDtmp); + Or(a = loadDtmp, + b = notIns15, + out = loadD); + + + // D register + DRegister( + in = ALUout, + load = loadDtmp, + out = Dout + ); + + // ALU + ALU( + x = Dout, + y = MuxAMout, + zx = instruction[11], + nx = instruction[10], + zy = instruction[9], + ny = instruction[8], + f = instruction[7], + no = instruction[6], + + out = outM, + out = ALUout, + zr = zr, + ng = ng + ); + + + + + + // Program Counter + + // Unnecessary? + Not(in = j, out = notj); + Not(in = reset, out = notreset); + And(a = notj, b = notreset, out = inc); + // End unnecessary? + + PC( + in = Aout, + inc = inc, + load = j, + reset = reset, + out[0..14] = pc + ); + + //--------------- + // Logic handling + + // j logic + // PC inc + + // 100 JLT + And(a = instruction[2], + b = ng, + out = JLT); + // 010 JEQ + And(a = instruction[1], + b = zr, + out = JEQ); + // 001 JGT + Or(a = ng, b = zr, out = ngZr); + Not(in = ngZr, out = NotNgZr); + And(a = instruction[0], + b = NotNgZr, + out = JGT); + + Or(a = JLT, + b = JEQ, + out = JLE); + Or(a = JGT, + b = JLE, + out = jout); + And(a = jout, + b = instruction[15], + out = j); + + + And(a = instruction[3], b = instruction[15], out = writeM); + } \ No newline at end of file diff --git a/nand2tetris/projects/5/CPU.out b/nand2tetris/projects/5/CPU.out new file mode 100644 index 0000000..2396ab5 --- /dev/null +++ b/nand2tetris/projects/5/CPU.out @@ -0,0 +1,97 @@ +|time | inM | instruction |reset| outM |writeM|address| pc |DRegister| +| 0+ | 0|0011000000111001| 0 | 0| 0 | 0 | 0| 0 | +| 1 | 0|0011000000111001| 0 | 0| 0 | 12345 | 1| 0 | +| 1+ | 0|1110110000010000| 0 | 12345| 0 | 12345 | 1| 12345 | +| 2 | 0|1110110000010000| 0 | 12345| 0 | 12345 | 2| 12345 | +| 2+ | 0|0101101110100000| 0 | -1| 0 | 12345 | 2| 12345 | +| 3 | 0|0101101110100000| 0 | -1| 0 | 23456 | 3| 12345 | +| 3+ | 0|1110000111110000| 0 | 11111| 0 | 23456 | 3| 11111 | +| 4 | 0|1110000111110000| 0 | 0| 0 | 11111 | 4| 11111 | +| 4+ | 0|0000001111101011| 0 | -11111| 0 | 11111 | 4| 11111 | +| 5 | 0|0000001111101011| 0 | -11111| 0 | 1003 | 5| 11111 | +| 5+ | 0|1110001100001000| 0 | 11111| 1 | 1003 | 5| 11111 | +| 6 | 0|1110001100001000| 0 | 11111| 1 | 1003 | 6| 11111 | +| 6+ | 0|0000001111101100| 0 | -11111| 0 | 1003 | 6| 11111 | +| 7 | 0|0000001111101100| 0 | -11111| 0 | 1004 | 7| 11111 | +| 7+ | 0|1110001110011000| 0 | 11110| 1 | 1004 | 7| 11110 | +| 8 | 0|1110001110011000| 0 | 11109| 1 | 1004 | 8| 11110 | +| 8+ | 0|0000001111101000| 0 | -11110| 0 | 1004 | 8| 11110 | +| 9 | 0|0000001111101000| 0 | -11110| 0 | 1000 | 9| 11110 | +| 9+ | 11111|1111010011110000| 0 | -1| 0 | 1000 | 9| -1 | +| 10 | 11111|1111010011110000| 0 | -11112| 0 | 32767 | 10| -1 | +| 10+ | 11111|0000000000001110| 0 | -1| 0 | 32767 | 10| -1 | +| 11 | 11111|0000000000001110| 0 | 14| 0 | 14 | 11| -1 | +| 11+ | 11111|1110001100000100| 0 | -1| 0 | 14 | 11| -1 | +| 12 | 11111|1110001100000100| 0 | -1| 0 | 14 | 14| -1 | +| 12+ | 11111|0000001111100111| 0 | 1| 0 | 14 | 14| -1 | +| 13 | 11111|0000001111100111| 0 | 1| 0 | 999 | 15| -1 | +| 13+ | 11111|1111110111100000| 0 | 11112| 0 | 999 | 15| -1 | +| 14 | 11111|1111110111100000| 0 | 11112| 0 | 11112 | 16| -1 | +| 14+ | 11111|1110001100101000| 0 | -1| 1 | 11112 | 16| -1 | +| 15 | 11111|1110001100101000| 0 | -1| 1 | 32767 | 17| -1 | +| 15+ | 11111|0000000000010101| 0 | -1| 0 | 32767 | 17| -1 | +| 16 | 11111|0000000000010101| 0 | 21| 0 | 21 | 18| -1 | +| 16+ | 11111|1110011111000010| 0 | 0| 0 | 21 | 18| -1 | +| 17 | 11111|1110011111000010| 0 | 0| 0 | 21 | 21| -1 | +| 17+ | 11111|0000000000000010| 0 | 21| 0 | 21 | 21| -1 | +| 18 | 11111|0000000000000010| 0 | 2| 0 | 2 | 22| -1 | +| 18+ | 11111|1110000010111000| 0 | 1| 1 | 2 | 22| 1 | +| 19 | 11111|1110000010111000| 0 | 2| 1 | 1 | 23| 1 | +| 19+ | 11111|1111110111001000| 0 | 11112| 1 | 1 | 23| 1 | +| 20 | 11111|1111110111001000| 0 | 11112| 1 | 1 | 24| 1 | +| 20+ | 11111|1111110010101000| 0 | 11110| 1 | 1 | 24| 1 | +| 21 | 11111|1111110010101000| 0 | 11110| 1 | 11110 | 25| 1 | +| 21+ | 11111|0000001111101000| 0 | -1| 0 | 11110 | 25| 1 | +| 22 | 11111|0000001111101000| 0 | -1| 0 | 1000 | 26| 1 | +| 22+ | 11111|1110111010010000| 0 | -1| 0 | 1000 | 26| -1 | +| 23 | 11111|1110111010010000| 0 | -1| 0 | 1000 | 27| -1 | +| 23+ | 11111|1110001100000001| 0 | -1| 0 | 1000 | 27| -1 | +| 24 | 11111|1110001100000001| 0 | -1| 0 | 1000 | 28| -1 | +| 24+ | 11111|1110001100000010| 0 | -1| 0 | 1000 | 28| -1 | +| 25 | 11111|1110001100000010| 0 | -1| 0 | 1000 | 29| -1 | +| 25+ | 11111|1110001100000011| 0 | -1| 0 | 1000 | 29| -1 | +| 26 | 11111|1110001100000011| 0 | -1| 0 | 1000 | 30| -1 | +| 26+ | 11111|1110001100000100| 0 | -1| 0 | 1000 | 30| -1 | +| 27 | 11111|1110001100000100| 0 | -1| 0 | 1000 | 1000| -1 | +| 27+ | 11111|1110001100000101| 0 | -1| 0 | 1000 | 1000| -1 | +| 28 | 11111|1110001100000101| 0 | -1| 0 | 1000 | 1000| -1 | +| 28+ | 11111|1110001100000110| 0 | -1| 0 | 1000 | 1000| -1 | +| 29 | 11111|1110001100000110| 0 | -1| 0 | 1000 | 1000| -1 | +| 29+ | 11111|1110001100000111| 0 | -1| 0 | 1000 | 1000| -1 | +| 30 | 11111|1110001100000111| 0 | -1| 0 | 1000 | 1000| -1 | +| 30+ | 11111|1110101010010000| 0 | 0| 0 | 1000 | 1000| 0 | +| 31 | 11111|1110101010010000| 0 | 0| 0 | 1000 | 1001| 0 | +| 31+ | 11111|1110001100000001| 0 | 0| 0 | 1000 | 1001| 0 | +| 32 | 11111|1110001100000001| 0 | 0| 0 | 1000 | 1002| 0 | +| 32+ | 11111|1110001100000010| 0 | 0| 0 | 1000 | 1002| 0 | +| 33 | 11111|1110001100000010| 0 | 0| 0 | 1000 | 1000| 0 | +| 33+ | 11111|1110001100000011| 0 | 0| 0 | 1000 | 1000| 0 | +| 34 | 11111|1110001100000011| 0 | 0| 0 | 1000 | 1000| 0 | +| 34+ | 11111|1110001100000100| 0 | 0| 0 | 1000 | 1000| 0 | +| 35 | 11111|1110001100000100| 0 | 0| 0 | 1000 | 1001| 0 | +| 35+ | 11111|1110001100000101| 0 | 0| 0 | 1000 | 1001| 0 | +| 36 | 11111|1110001100000101| 0 | 0| 0 | 1000 | 1002| 0 | +| 36+ | 11111|1110001100000110| 0 | 0| 0 | 1000 | 1002| 0 | +| 37 | 11111|1110001100000110| 0 | 0| 0 | 1000 | 1000| 0 | +| 37+ | 11111|1110001100000111| 0 | 0| 0 | 1000 | 1000| 0 | +| 38 | 11111|1110001100000111| 0 | 0| 0 | 1000 | 1000| 0 | +| 38+ | 11111|1110111111010000| 0 | 1| 0 | 1000 | 1000| 1 | +| 39 | 11111|1110111111010000| 0 | 1| 0 | 1000 | 1001| 1 | +| 39+ | 11111|1110001100000001| 0 | 1| 0 | 1000 | 1001| 1 | +| 40 | 11111|1110001100000001| 0 | 1| 0 | 1000 | 1000| 1 | +| 40+ | 11111|1110001100000010| 0 | 1| 0 | 1000 | 1000| 1 | +| 41 | 11111|1110001100000010| 0 | 1| 0 | 1000 | 1001| 1 | +| 41+ | 11111|1110001100000011| 0 | 1| 0 | 1000 | 1001| 1 | +| 42 | 11111|1110001100000011| 0 | 1| 0 | 1000 | 1000| 1 | +| 42+ | 11111|1110001100000100| 0 | 1| 0 | 1000 | 1000| 1 | +| 43 | 11111|1110001100000100| 0 | 1| 0 | 1000 | 1001| 1 | +| 43+ | 11111|1110001100000101| 0 | 1| 0 | 1000 | 1001| 1 | +| 44 | 11111|1110001100000101| 0 | 1| 0 | 1000 | 1000| 1 | +| 44+ | 11111|1110001100000110| 0 | 1| 0 | 1000 | 1000| 1 | +| 45 | 11111|1110001100000110| 0 | 1| 0 | 1000 | 1001| 1 | +| 45+ | 11111|1110001100000111| 0 | 1| 0 | 1000 | 1001| 1 | +| 46 | 11111|1110001100000111| 0 | 1| 0 | 1000 | 1000| 1 | +| 46+ | 11111|1110001100000111| 1 | 1| 0 | 1000 | 1000| 1 | +| 47 | 11111|1110001100000111| 1 | 1| 0 | 1000 | 0| 1 | +| 47+ | 11111|0111111111111111| 0 | 1| 0 | 1000 | 0| 1 | +| 48 | 11111|0111111111111111| 0 | 1| 0 | 32767 | 1| 1 | diff --git a/nand2tetris/projects/5/Computer.hdl b/nand2tetris/projects/5/Computer.hdl index b3cba91..28f17e4 100644 --- a/nand2tetris/projects/5/Computer.hdl +++ b/nand2tetris/projects/5/Computer.hdl @@ -18,5 +18,28 @@ CHIP Computer { IN reset; PARTS: - //// Replace this comment with your code. + + ROM32K( + address = pc, + out = instruction + ); + + CPU( + inM = memoryOut, + instruction = instruction, + reset = reset, + + // out + outM = outM, + writeM = writeM, + addressM = addressM, + pc = pc + ); + + Memory( + in = outM, + load = writeM, + address = addressM, + out = memoryOut + ); } diff --git a/nand2tetris/projects/5/ComputerAdd.out b/nand2tetris/projects/5/ComputerAdd.out new file mode 100644 index 0000000..d867a0c --- /dev/null +++ b/nand2tetris/projects/5/ComputerAdd.out @@ -0,0 +1,15 @@ +|time |reset|ARegister|DRegister|PC[]|RAM16K[0]|RAM16K[1]|RAM16K[2]| +| 0 | 0 | 0 | 0 | 0| 0 | 0 | 0 | +| 1 | 0 | 2 | 0 | 1| 0 | 0 | 0 | +| 2 | 0 | 2 | 2 | 2| 0 | 0 | 0 | +| 3 | 0 | 3 | 2 | 3| 0 | 0 | 0 | +| 4 | 0 | 3 | 5 | 4| 0 | 0 | 0 | +| 5 | 0 | 0 | 5 | 5| 0 | 0 | 0 | +| 6 | 0 | 0 | 5 | 6| 5 | 0 | 0 | +| 7 | 1 | 0 | 5 | 0| 0 | 0 | 0 | +| 8 | 0 | 2 | 5 | 1| 0 | 0 | 0 | +| 9 | 0 | 2 | 2 | 2| 0 | 0 | 0 | +| 10 | 0 | 3 | 2 | 3| 0 | 0 | 0 | +| 11 | 0 | 3 | 5 | 4| 0 | 0 | 0 | +| 12 | 0 | 0 | 5 | 5| 0 | 0 | 0 | +| 13 | 0 | 0 | 5 | 6| 5 | 0 | 0 | diff --git a/nand2tetris/projects/5/ComputerMax.out b/nand2tetris/projects/5/ComputerMax.out new file mode 100644 index 0000000..6673510 --- /dev/null +++ b/nand2tetris/projects/5/ComputerMax.out @@ -0,0 +1 @@ +|time |reset|ARegister|DRegister|PC[]|RAM16K[0]|RAM16K[1]|RAM16K[2]| diff --git a/nand2tetris/projects/5/ComputerRect.out b/nand2tetris/projects/5/ComputerRect.out new file mode 100644 index 0000000..5580fe0 --- /dev/null +++ b/nand2tetris/projects/5/ComputerRect.out @@ -0,0 +1 @@ +|time |ARegister|DRegister|PC[]|RAM16K[0]|RAM16K[1]|RAM16K[2]| diff --git a/nand2tetris/projects/5/Memory.hdl b/nand2tetris/projects/5/Memory.hdl index 79df0e2..71a621b 100644 --- a/nand2tetris/projects/5/Memory.hdl +++ b/nand2tetris/projects/5/Memory.hdl @@ -25,5 +25,53 @@ CHIP Memory { OUT out[16]; PARTS: - //// Replace this comment with your code. + + Not(in = address[13], out = notAddr13); + Not(in = address[14], out = notAddr14); + + // addrRAM -- if address bit 14 and 13 are 0, the address + // points at the RAM chip. + // If and only if the RAM chip is addressed and load = 1, then load the RAM. + And(a = load, b = notAddr14, out = addrRAM); + And(a = load, b = addrRAM, out = loadRAM); + + // addrScreen - if address bit 14 is 1 and 13 is 0, the address + // points at the screen chip. + // Iff the screen chip is addressed and load = 1 then load screen. + And(a = address[14], b = notAddr13, out = addrScreen); + And(a = load, b = addrScreen, out = loadScreen); + + // If address bit 14 and 13 are 1, keyboard is addressed. + // If other bits are also 1, input is invalid. + And(a = address[14], b = address[13], out = and1413); + + Or8Way(in = address[0..7], out = addr07); + Or8Way(in[0..4] = address[8..12], in[5..7] = false, out = addr812); + Or(a = addr07, b = addr812, out = OrAddrLsb); + Not(in = OrAddrLsb, out = NotOrAddrLsb); + + + RAM16K( + in = in, + load = loadRAM, + address = address[0..13], + out = outRAM + ); + + Screen( + in = in, + load = loadScreen, + address = address[0..12], + out = outScreen); + + Keyboard( + out = outKBD); + + Mux4Way16( + a = outRAM, // sel = 00 + b = outRAM, // sel = 01 + c = outScreen, // sel = 10 + d = outKBD, // sel = 11 + sel = address[13..14], + out = out); } \ No newline at end of file diff --git a/nand2tetris/projects/5/Memory.out b/nand2tetris/projects/5/Memory.out new file mode 100644 index 0000000..839a730 --- /dev/null +++ b/nand2tetris/projects/5/Memory.out @@ -0,0 +1,68 @@ +| in |load | address | out | +| 12345 | 1 | 010000000000000 | 0 | +| 12345 | 1 | 010000000000000 | 12345 | +| 12345 | 1 | 100000000000000 | 0 | +| 12345 | 1 | 100000000000000 | 12345 | +| -1 | 1 | 000000000000000 | 0 | +| -1 | 1 | 000000000000000 | -1 | +| 9999 | 0 | 000000000000000 | -1 | +| 9999 | 0 | 000000000000000 | -1 | +| 9999 | 0 | 010000000000000 | 12345 | +| 9999 | 0 | 100000000000000 | 12345 | +| 12345 | 1 | 000000000000000 | -1 | +| 12345 | 1 | 000000000000000 | 12345 | +| 12345 | 1 | 100000000000000 | 12345 | +| 12345 | 1 | 100000000000000 | 12345 | +| 2222 | 1 | 010000000000000 | 12345 | +| 2222 | 1 | 010000000000000 | 2222 | +| 9999 | 0 | 010000000000000 | 2222 | +| 9999 | 0 | 010000000000000 | 2222 | +| 9999 | 0 | 000000000000000 | 12345 | +| 9999 | 0 | 100000000000000 | 12345 | +| 9999 | 0 | 000000000000001 | 0 | +| 9999 | 0 | 000000000000010 | 0 | +| 9999 | 0 | 000000000000100 | 0 | +| 9999 | 0 | 000000000001000 | 0 | +| 9999 | 0 | 000000000010000 | 0 | +| 9999 | 0 | 000000000100000 | 0 | +| 9999 | 0 | 000000001000000 | 0 | +| 9999 | 0 | 000000010000000 | 0 | +| 9999 | 0 | 000000100000000 | 0 | +| 9999 | 0 | 000001000000000 | 0 | +| 9999 | 0 | 000010000000000 | 0 | +| 9999 | 0 | 000100000000000 | 0 | +| 9999 | 0 | 001000000000000 | 0 | +| 9999 | 0 | 010000000000000 | 2222 | +| 1234 | 1 | 001001000110100 | 0 | +| 1234 | 1 | 001001000110100 | 1234 | +| 1234 | 0 | 010001000110100 | 0 | +| 1234 | 0 | 110001000110100 | 0 | +| 2345 | 1 | 010001101000101 | 0 | +| 2345 | 1 | 010001101000101 | 2345 | +| 2345 | 0 | 000001101000101 | 0 | +| 2345 | 0 | 100001101000101 | 0 | +| 0 | 1 | 100000000000000 | 12345 | +| 0 | 1 | 100000000000000 | 0 | +| 0 | 1 | 110000000000000 | 75 | +| 12345 | 1 | 000111111001111 | 0 | +| 12345 | 1 | 000111111001111 | 12345 | +| 12345 | 1 | 010111111001111 | 0 | +| 12345 | 1 | 010111111001111 | 12345 | +| -1 | 1 | 100111111001111 | -1 | +| -1 | 1 | 101000001001111 | -1 | +| -1 | 1 | 000111111001111 | 12345 | +| -1 | 1 | 010111111001111 | 12345 | +| -1 | 0 | 100111111001110 | 0 | +| -1 | 0 | 100111111001101 | 0 | +| -1 | 0 | 100111111001011 | 0 | +| -1 | 0 | 100111111000111 | 0 | +| -1 | 0 | 100111111011111 | 0 | +| -1 | 0 | 100111111101111 | 0 | +| -1 | 0 | 100111110001111 | 0 | +| -1 | 0 | 100111101001111 | 0 | +| -1 | 0 | 100111011001111 | 0 | +| -1 | 0 | 100110111001111 | 0 | +| -1 | 0 | 100101111001111 | 0 | +| -1 | 0 | 100011111001111 | 0 | +| -1 | 0 | 101111111001111 | 0 | +| -1 | 0 | 110000000000000 | 89 | diff --git a/nand2tetris/projects/5/project5.zip b/nand2tetris/projects/5/project5.zip new file mode 100644 index 0000000..8500dc8 Binary files /dev/null and b/nand2tetris/projects/5/project5.zip differ