From d7a912a7f94d64923039a1f7d0fb6cce38554cab Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:18:07 +0530 Subject: [PATCH 01/33] Create analysis --- library/SubcircuitLibrary/SN74LS280/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/SN74LS280/analysis diff --git a/library/SubcircuitLibrary/SN74LS280/analysis b/library/SubcircuitLibrary/SN74LS280/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS280/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 50fc39ecc7ddaa9594699cd31d5a503e2f37e3bb Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:19:48 +0530 Subject: [PATCH 02/33] Add files via upload --- .../SN74LS280/SC_SN74LS280.cir | 62 + .../SN74LS280/SC_SN74LS280.cir.out | 143 ++ .../SN74LS280/SC_SN74LS280.pro | 73 ++ .../SN74LS280/SC_SN74LS280.sch | 1161 +++++++++++++++++ .../SN74LS280/SC_SN74LS280.sub | 137 ++ .../SN74LS280/SN74LS280_SC1-cache.lib | 97 ++ .../SN74LS280_SC1_Previous_Values.xml | 1 + 7 files changed, 1674 insertions(+) create mode 100644 library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.cir create mode 100644 library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.cir.out create mode 100644 library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.pro create mode 100644 library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.sch create mode 100644 library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.sub create mode 100644 library/SubcircuitLibrary/SN74LS280/SN74LS280_SC1-cache.lib create mode 100644 library/SubcircuitLibrary/SN74LS280/SN74LS280_SC1_Previous_Values.xml diff --git a/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.cir b/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.cir new file mode 100644 index 000000000..e122f9e2a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.cir @@ -0,0 +1,62 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_SN74LS280\SC_SN74LS280.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 15:06:53 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_X1-Pad4_ 3_and +X2 Net-_U11-Pad1_ Net-_U13-Pad1_ Net-_U12-Pad2_ Net-_X13-Pad2_ 3_and +X3 Net-_U12-Pad1_ Net-_U11-Pad1_ Net-_U13-Pad2_ Net-_X13-Pad3_ 3_and +X4 Net-_U13-Pad2_ Net-_U12-Pad2_ Net-_U11-Pad2_ Net-_X13-Pad4_ 3_and +X13 Net-_X1-Pad4_ Net-_X13-Pad2_ Net-_X13-Pad3_ Net-_X13-Pad4_ Net-_U20-Pad1_ 4_OR +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter +U2 Net-_U1-Pad8_ Net-_U11-Pad1_ d_inverter +U3 Net-_U1-Pad9_ Net-_U12-Pad1_ d_inverter +U4 Net-_U1-Pad10_ Net-_U13-Pad1_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +X5 Net-_U15-Pad1_ Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_X14-Pad1_ 3_and +X6 Net-_U14-Pad1_ Net-_U16-Pad1_ Net-_U15-Pad2_ Net-_X14-Pad2_ 3_and +X7 Net-_U15-Pad1_ Net-_U14-Pad1_ Net-_U16-Pad2_ Net-_X14-Pad3_ 3_and +X8 Net-_U16-Pad2_ Net-_U15-Pad2_ Net-_U14-Pad2_ Net-_X14-Pad4_ 3_and +X14 Net-_X14-Pad1_ Net-_X14-Pad2_ Net-_X14-Pad3_ Net-_X14-Pad4_ Net-_U21-Pad1_ 4_OR +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ d_inverter +U5 Net-_U1-Pad11_ Net-_U14-Pad1_ d_inverter +U6 Net-_U1-Pad12_ Net-_U15-Pad1_ d_inverter +U7 Net-_U1-Pad13_ Net-_U16-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +X9 Net-_U18-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad2_ Net-_X15-Pad1_ 3_and +X10 Net-_U17-Pad1_ Net-_U10-Pad2_ Net-_U18-Pad2_ Net-_X10-Pad4_ 3_and +X11 Net-_U18-Pad1_ Net-_U17-Pad1_ Net-_U19-Pad2_ Net-_X11-Pad4_ 3_and +X12 Net-_U19-Pad2_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_X12-Pad4_ 3_and +X15 Net-_X15-Pad1_ Net-_X10-Pad4_ Net-_X11-Pad4_ Net-_X12-Pad4_ Net-_U22-Pad1_ 4_OR +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ d_inverter +U8 Net-_U1-Pad1_ Net-_U17-Pad1_ d_inverter +U9 Net-_U1-Pad2_ Net-_U18-Pad1_ d_inverter +U10 Net-_U1-Pad4_ Net-_U10-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter +U19 Net-_U10-Pad2_ Net-_U19-Pad2_ d_inverter +X16 Net-_U21-Pad2_ Net-_U22-Pad2_ Net-_U23-Pad2_ Net-_X16-Pad4_ 3_and +X17 Net-_U20-Pad2_ Net-_U22-Pad2_ Net-_U24-Pad2_ Net-_X17-Pad4_ 3_and +X18 Net-_U20-Pad2_ Net-_U21-Pad2_ Net-_U25-Pad2_ Net-_X18-Pad4_ 3_and +X19 Net-_U23-Pad2_ Net-_U24-Pad2_ Net-_U25-Pad2_ Net-_X19-Pad4_ 3_and +X24 Net-_X16-Pad4_ Net-_X17-Pad4_ Net-_X18-Pad4_ Net-_X19-Pad4_ Net-_U26-Pad1_ 4_OR +U23 Net-_U20-Pad2_ Net-_U23-Pad2_ d_inverter +X20 Net-_U24-Pad2_ Net-_U25-Pad2_ Net-_U20-Pad2_ Net-_X20-Pad4_ 3_and +X21 Net-_U21-Pad2_ Net-_U23-Pad2_ Net-_U25-Pad2_ Net-_X21-Pad4_ 3_and +X22 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U22-Pad2_ Net-_X22-Pad4_ 3_and +X23 Net-_U21-Pad2_ Net-_U20-Pad2_ Net-_U22-Pad2_ Net-_X23-Pad4_ 3_and +X25 Net-_X20-Pad4_ Net-_X21-Pad4_ Net-_X22-Pad4_ Net-_X23-Pad4_ Net-_U27-Pad1_ 4_OR +U24 Net-_U21-Pad2_ Net-_U24-Pad2_ d_inverter +U26 Net-_U26-Pad1_ Net-_U1-Pad5_ d_inverter +U27 Net-_U27-Pad1_ Net-_U1-Pad6_ d_inverter +U25 Net-_U22-Pad2_ Net-_U25-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ ? Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.cir.out b/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.cir.out new file mode 100644 index 000000000..8e4e29faa --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.cir.out @@ -0,0 +1,143 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn74ls280\sc_sn74ls280.cir + +.include 3_and.sub +.include 4_OR.sub +x1 net-_u12-pad1_ net-_u13-pad1_ net-_u11-pad2_ net-_x1-pad4_ 3_and +x2 net-_u11-pad1_ net-_u13-pad1_ net-_u12-pad2_ net-_x13-pad2_ 3_and +x3 net-_u12-pad1_ net-_u11-pad1_ net-_u13-pad2_ net-_x13-pad3_ 3_and +x4 net-_u13-pad2_ net-_u12-pad2_ net-_u11-pad2_ net-_x13-pad4_ 3_and +x13 net-_x1-pad4_ net-_x13-pad2_ net-_x13-pad3_ net-_x13-pad4_ net-_u20-pad1_ 4_OR +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u2 net-_u1-pad8_ net-_u11-pad1_ d_inverter +* u3 net-_u1-pad9_ net-_u12-pad1_ d_inverter +* u4 net-_u1-pad10_ net-_u13-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +x5 net-_u15-pad1_ net-_u16-pad1_ net-_u14-pad2_ net-_x14-pad1_ 3_and +x6 net-_u14-pad1_ net-_u16-pad1_ net-_u15-pad2_ net-_x14-pad2_ 3_and +x7 net-_u15-pad1_ net-_u14-pad1_ net-_u16-pad2_ net-_x14-pad3_ 3_and +x8 net-_u16-pad2_ net-_u15-pad2_ net-_u14-pad2_ net-_x14-pad4_ 3_and +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x14-pad3_ net-_x14-pad4_ net-_u21-pad1_ 4_OR +* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u14-pad1_ d_inverter +* u6 net-_u1-pad12_ net-_u15-pad1_ d_inverter +* u7 net-_u1-pad13_ net-_u16-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +x9 net-_u18-pad1_ net-_u10-pad2_ net-_u17-pad2_ net-_x15-pad1_ 3_and +x10 net-_u17-pad1_ net-_u10-pad2_ net-_u18-pad2_ net-_x10-pad4_ 3_and +x11 net-_u18-pad1_ net-_u17-pad1_ net-_u19-pad2_ net-_x11-pad4_ 3_and +x12 net-_u19-pad2_ net-_u18-pad2_ net-_u17-pad2_ net-_x12-pad4_ 3_and +x15 net-_x15-pad1_ net-_x10-pad4_ net-_x11-pad4_ net-_x12-pad4_ net-_u22-pad1_ 4_OR +* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter +* u8 net-_u1-pad1_ net-_u17-pad1_ d_inverter +* u9 net-_u1-pad2_ net-_u18-pad1_ d_inverter +* u10 net-_u1-pad4_ net-_u10-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u10-pad2_ net-_u19-pad2_ d_inverter +x16 net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ net-_x16-pad4_ 3_and +x17 net-_u20-pad2_ net-_u22-pad2_ net-_u24-pad2_ net-_x17-pad4_ 3_and +x18 net-_u20-pad2_ net-_u21-pad2_ net-_u25-pad2_ net-_x18-pad4_ 3_and +x19 net-_u23-pad2_ net-_u24-pad2_ net-_u25-pad2_ net-_x19-pad4_ 3_and +x24 net-_x16-pad4_ net-_x17-pad4_ net-_x18-pad4_ net-_x19-pad4_ net-_u26-pad1_ 4_OR +* u23 net-_u20-pad2_ net-_u23-pad2_ d_inverter +x20 net-_u24-pad2_ net-_u25-pad2_ net-_u20-pad2_ net-_x20-pad4_ 3_and +x21 net-_u21-pad2_ net-_u23-pad2_ net-_u25-pad2_ net-_x21-pad4_ 3_and +x22 net-_u24-pad2_ net-_u23-pad2_ net-_u22-pad2_ net-_x22-pad4_ 3_and +x23 net-_u21-pad2_ net-_u20-pad2_ net-_u22-pad2_ net-_x23-pad4_ 3_and +x25 net-_x20-pad4_ net-_x21-pad4_ net-_x22-pad4_ net-_x23-pad4_ net-_u27-pad1_ 4_OR +* u24 net-_u21-pad2_ net-_u24-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u1-pad5_ d_inverter +* u27 net-_u27-pad1_ net-_u1-pad6_ d_inverter +* u25 net-_u22-pad2_ net-_u25-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ ? net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +a1 net-_u20-pad1_ net-_u20-pad2_ u20 +a2 net-_u1-pad8_ net-_u11-pad1_ u2 +a3 net-_u1-pad9_ net-_u12-pad1_ u3 +a4 net-_u1-pad10_ net-_u13-pad1_ u4 +a5 net-_u11-pad1_ net-_u11-pad2_ u11 +a6 net-_u12-pad1_ net-_u12-pad2_ u12 +a7 net-_u13-pad1_ net-_u13-pad2_ u13 +a8 net-_u21-pad1_ net-_u21-pad2_ u21 +a9 net-_u1-pad11_ net-_u14-pad1_ u5 +a10 net-_u1-pad12_ net-_u15-pad1_ u6 +a11 net-_u1-pad13_ net-_u16-pad1_ u7 +a12 net-_u14-pad1_ net-_u14-pad2_ u14 +a13 net-_u15-pad1_ net-_u15-pad2_ u15 +a14 net-_u16-pad1_ net-_u16-pad2_ u16 +a15 net-_u22-pad1_ net-_u22-pad2_ u22 +a16 net-_u1-pad1_ net-_u17-pad1_ u8 +a17 net-_u1-pad2_ net-_u18-pad1_ u9 +a18 net-_u1-pad4_ net-_u10-pad2_ u10 +a19 net-_u17-pad1_ net-_u17-pad2_ u17 +a20 net-_u18-pad1_ net-_u18-pad2_ u18 +a21 net-_u10-pad2_ net-_u19-pad2_ u19 +a22 net-_u20-pad2_ net-_u23-pad2_ u23 +a23 net-_u21-pad2_ net-_u24-pad2_ u24 +a24 net-_u26-pad1_ net-_u1-pad5_ u26 +a25 net-_u27-pad1_ net-_u1-pad6_ u27 +a26 net-_u22-pad2_ net-_u25-pad2_ u25 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.pro b/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.sch b/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.sch new file mode 100644 index 000000000..13baf1d0b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.sch @@ -0,0 +1,1161 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt 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5850 +Wire Wire Line + 7000 1800 8700 1800 +Connection ~ 7000 1700 +Wire Wire Line + 7000 2450 8700 2450 +Connection ~ 7000 1800 +Wire Wire Line + 7000 4050 8700 4050 +Connection ~ 7000 2450 +Wire Wire Line + 7000 5850 8700 5850 +Connection ~ 7000 4050 +Wire Wire Line + 8700 5950 7050 5950 +Wire Wire Line + 7050 1250 7050 6000 +Connection ~ 7050 6000 +Wire Wire Line + 8700 5350 7050 5350 +Connection ~ 7050 5950 +Wire Wire Line + 8700 1900 7050 1900 +Connection ~ 7050 5350 +Wire Wire Line + 8700 1250 7050 1250 +Connection ~ 7050 1900 +Wire Wire Line + 6950 1150 8700 1150 +Connection ~ 6950 3800 +Wire Wire Line + 6950 3800 6950 5750 +Wire Wire Line + 8700 2550 6950 2550 +Connection ~ 6950 2550 +Wire Wire Line + 8700 2000 8100 2000 +Wire Wire Line + 8100 2000 8100 5150 +Wire Wire Line + 8100 3150 8700 3150 +Wire Wire Line + 8700 2650 8350 2650 +Wire Wire Line + 8350 2650 8350 6000 +Wire Wire Line + 8350 3250 8700 3250 +Wire Wire Line + 8350 3950 8700 3950 +Connection ~ 8350 3250 +Wire Wire Line + 8350 4700 8700 4700 +Connection ~ 8350 3950 +Wire Wire Line + 8350 6000 7800 6000 +Connection ~ 8350 4700 +Wire Wire Line + 8100 4400 7700 4400 +Connection ~ 8100 3150 +Wire Wire Line + 8700 3850 8100 3850 +Connection ~ 8100 3850 +Wire Wire Line + 8100 5150 8700 5150 +Connection ~ 8100 4400 +Wire Wire Line + 7700 4600 8700 4600 +Connection ~ 7700 3050 +Wire Wire Line + 7700 5250 8700 5250 +Connection ~ 7700 4600 +Wire Wire Line + 6950 5750 8700 5750 +Connection ~ 6950 4500 +Wire Wire Line + 3900 1500 2200 1500 +Connection ~ 2200 1500 +Wire Wire Line + 3950 5800 2250 5800 +Connection ~ 2250 5800 +Wire Wire Line + 3950 3600 2250 3600 +Connection ~ 2250 3600 +Wire Wire Line + 6950 4500 8700 4500 +$Comp +L PORT U1 +U 1 1 68314B94 +P 950 5550 +F 0 "U1" H 1000 5650 30 0000 C CNN +F 1 "PORT" H 950 5550 30 0000 C CNN +F 2 "" H 950 5550 60 0000 C CNN +F 3 "" H 950 5550 60 0000 C CNN + 1 950 5550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68314DAB +P 950 6100 +F 0 "U1" H 1000 6200 30 0000 C CNN +F 1 "PORT" H 950 6100 30 0000 C CNN +F 2 "" H 950 6100 60 0000 C CNN +F 3 "" H 950 6100 60 0000 C CNN + 2 950 6100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68314E64 +P 950 7250 +F 0 "U1" H 1000 7350 30 0000 C CNN +F 1 "PORT" H 950 7250 30 0000 C CNN +F 2 "" H 950 7250 60 0000 C CNN +F 3 "" H 950 7250 60 0000 C CNN + 3 950 7250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68314F01 +P 950 6650 +F 0 "U1" H 1000 6750 30 0000 C CNN +F 1 "PORT" H 950 6650 30 0000 C CNN +F 2 "" H 950 6650 60 0000 C CNN +F 3 "" H 950 6650 60 0000 C CNN + 4 950 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68315AEE +P 10650 2900 +F 0 "U1" H 10700 3000 30 0000 C CNN +F 1 "PORT" H 10650 2900 30 0000 C CNN +F 2 "" H 10650 2900 60 0000 C CNN +F 3 "" H 10650 2900 60 0000 C CNN + 5 10650 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68315BA1 +P 10650 5600 +F 0 "U1" H 10700 5700 30 0000 C CNN +F 1 "PORT" H 10650 5600 30 0000 C CNN +F 2 "" H 10650 5600 60 0000 C CNN +F 3 "" H 10650 5600 60 0000 C CNN + 6 10650 5600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68315FD8 +P 950 750 +F 0 "U1" H 1000 850 30 0000 C CNN +F 1 "PORT" H 950 750 30 0000 C CNN +F 2 "" H 950 750 60 0000 C CNN +F 3 "" H 950 750 60 0000 C CNN + 7 950 750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 683160CB +P 900 1250 +F 0 "U1" H 950 1350 30 0000 C CNN +F 1 "PORT" H 900 1250 30 0000 C CNN +F 2 "" H 900 1250 60 0000 C CNN +F 3 "" H 900 1250 60 0000 C CNN + 8 900 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6831616C +P 900 1800 +F 0 "U1" H 950 1900 30 0000 C CNN +F 1 "PORT" H 900 1800 30 0000 C CNN +F 2 "" H 900 1800 60 0000 C CNN +F 3 "" H 900 1800 60 0000 C CNN + 9 900 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6831623B +P 900 2350 +F 0 "U1" H 950 2450 30 0000 C CNN +F 1 "PORT" H 900 2350 30 0000 C CNN +F 2 "" H 900 2350 60 0000 C CNN +F 3 "" H 900 2350 60 0000 C CNN + 10 900 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 683162EE +P 950 3350 +F 0 "U1" H 1000 3450 30 0000 C CNN +F 1 "PORT" H 950 3350 30 0000 C CNN +F 2 "" H 950 3350 60 0000 C CNN +F 3 "" H 950 3350 60 0000 C CNN + 11 950 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 68316715 +P 950 3900 +F 0 "U1" H 1000 4000 30 0000 C CNN +F 1 "PORT" H 950 3900 30 0000 C CNN +F 2 "" H 950 3900 60 0000 C CNN +F 3 "" H 950 3900 60 0000 C CNN + 12 950 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 683167DC +P 950 4450 +F 0 "U1" H 1000 4550 30 0000 C CNN +F 1 "PORT" H 950 4450 30 0000 C CNN +F 2 "" H 950 4450 60 0000 C CNN +F 3 "" H 950 4450 60 0000 C CNN + 13 950 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 68316895 +P 950 5000 +F 0 "U1" H 1000 5100 30 0000 C CNN +F 1 "PORT" H 950 5000 30 0000 C CNN +F 2 "" H 950 5000 60 0000 C CNN +F 3 "" H 950 5000 60 0000 C CNN + 14 950 5000 + 1 0 0 -1 +$EndComp +NoConn ~ 1200 5000 +NoConn ~ 1200 7250 +NoConn ~ 1200 750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.sub b/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.sub new file mode 100644 index 000000000..497d48644 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS280/SC_SN74LS280.sub @@ -0,0 +1,137 @@ +* Subcircuit SC_SN74LS280 +.subckt SC_SN74LS280 net-_u1-pad1_ net-_u1-pad2_ ? net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn74ls280\sc_sn74ls280.cir +.include 3_and.sub +.include 4_OR.sub +x1 net-_u12-pad1_ net-_u13-pad1_ net-_u11-pad2_ net-_x1-pad4_ 3_and +x2 net-_u11-pad1_ net-_u13-pad1_ net-_u12-pad2_ net-_x13-pad2_ 3_and +x3 net-_u12-pad1_ net-_u11-pad1_ net-_u13-pad2_ net-_x13-pad3_ 3_and +x4 net-_u13-pad2_ net-_u12-pad2_ net-_u11-pad2_ net-_x13-pad4_ 3_and +x13 net-_x1-pad4_ net-_x13-pad2_ net-_x13-pad3_ net-_x13-pad4_ net-_u20-pad1_ 4_OR +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u2 net-_u1-pad8_ net-_u11-pad1_ d_inverter +* u3 net-_u1-pad9_ net-_u12-pad1_ d_inverter +* u4 net-_u1-pad10_ net-_u13-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +x5 net-_u15-pad1_ net-_u16-pad1_ net-_u14-pad2_ net-_x14-pad1_ 3_and +x6 net-_u14-pad1_ net-_u16-pad1_ net-_u15-pad2_ net-_x14-pad2_ 3_and +x7 net-_u15-pad1_ net-_u14-pad1_ net-_u16-pad2_ net-_x14-pad3_ 3_and +x8 net-_u16-pad2_ net-_u15-pad2_ net-_u14-pad2_ net-_x14-pad4_ 3_and +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x14-pad3_ net-_x14-pad4_ net-_u21-pad1_ 4_OR +* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u14-pad1_ d_inverter +* u6 net-_u1-pad12_ net-_u15-pad1_ d_inverter +* u7 net-_u1-pad13_ net-_u16-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +x9 net-_u18-pad1_ net-_u10-pad2_ net-_u17-pad2_ net-_x15-pad1_ 3_and +x10 net-_u17-pad1_ net-_u10-pad2_ net-_u18-pad2_ net-_x10-pad4_ 3_and +x11 net-_u18-pad1_ net-_u17-pad1_ net-_u19-pad2_ net-_x11-pad4_ 3_and +x12 net-_u19-pad2_ net-_u18-pad2_ net-_u17-pad2_ net-_x12-pad4_ 3_and +x15 net-_x15-pad1_ net-_x10-pad4_ net-_x11-pad4_ net-_x12-pad4_ net-_u22-pad1_ 4_OR +* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter +* u8 net-_u1-pad1_ net-_u17-pad1_ d_inverter +* u9 net-_u1-pad2_ net-_u18-pad1_ d_inverter +* u10 net-_u1-pad4_ net-_u10-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u10-pad2_ net-_u19-pad2_ d_inverter +x16 net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ net-_x16-pad4_ 3_and +x17 net-_u20-pad2_ net-_u22-pad2_ net-_u24-pad2_ net-_x17-pad4_ 3_and +x18 net-_u20-pad2_ net-_u21-pad2_ net-_u25-pad2_ net-_x18-pad4_ 3_and +x19 net-_u23-pad2_ net-_u24-pad2_ net-_u25-pad2_ net-_x19-pad4_ 3_and +x24 net-_x16-pad4_ net-_x17-pad4_ net-_x18-pad4_ net-_x19-pad4_ net-_u26-pad1_ 4_OR +* u23 net-_u20-pad2_ net-_u23-pad2_ d_inverter +x20 net-_u24-pad2_ net-_u25-pad2_ net-_u20-pad2_ net-_x20-pad4_ 3_and +x21 net-_u21-pad2_ net-_u23-pad2_ net-_u25-pad2_ net-_x21-pad4_ 3_and +x22 net-_u24-pad2_ net-_u23-pad2_ net-_u22-pad2_ net-_x22-pad4_ 3_and +x23 net-_u21-pad2_ net-_u20-pad2_ net-_u22-pad2_ net-_x23-pad4_ 3_and +x25 net-_x20-pad4_ net-_x21-pad4_ net-_x22-pad4_ net-_x23-pad4_ net-_u27-pad1_ 4_OR +* u24 net-_u21-pad2_ net-_u24-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u1-pad5_ d_inverter +* u27 net-_u27-pad1_ net-_u1-pad6_ d_inverter +* u25 net-_u22-pad2_ net-_u25-pad2_ d_inverter +a1 net-_u20-pad1_ net-_u20-pad2_ u20 +a2 net-_u1-pad8_ net-_u11-pad1_ u2 +a3 net-_u1-pad9_ net-_u12-pad1_ u3 +a4 net-_u1-pad10_ net-_u13-pad1_ u4 +a5 net-_u11-pad1_ net-_u11-pad2_ u11 +a6 net-_u12-pad1_ net-_u12-pad2_ u12 +a7 net-_u13-pad1_ net-_u13-pad2_ u13 +a8 net-_u21-pad1_ net-_u21-pad2_ u21 +a9 net-_u1-pad11_ net-_u14-pad1_ u5 +a10 net-_u1-pad12_ net-_u15-pad1_ u6 +a11 net-_u1-pad13_ net-_u16-pad1_ u7 +a12 net-_u14-pad1_ net-_u14-pad2_ u14 +a13 net-_u15-pad1_ net-_u15-pad2_ u15 +a14 net-_u16-pad1_ net-_u16-pad2_ u16 +a15 net-_u22-pad1_ net-_u22-pad2_ u22 +a16 net-_u1-pad1_ net-_u17-pad1_ u8 +a17 net-_u1-pad2_ net-_u18-pad1_ u9 +a18 net-_u1-pad4_ net-_u10-pad2_ u10 +a19 net-_u17-pad1_ net-_u17-pad2_ u17 +a20 net-_u18-pad1_ net-_u18-pad2_ u18 +a21 net-_u10-pad2_ net-_u19-pad2_ u19 +a22 net-_u20-pad2_ net-_u23-pad2_ u23 +a23 net-_u21-pad2_ net-_u24-pad2_ u24 +a24 net-_u26-pad1_ net-_u1-pad5_ u26 +a25 net-_u27-pad1_ net-_u1-pad6_ u27 +a26 net-_u22-pad2_ net-_u25-pad2_ u25 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_SN74LS280 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS280/SN74LS280_SC1-cache.lib b/library/SubcircuitLibrary/SN74LS280/SN74LS280_SC1-cache.lib new file mode 100644 index 000000000..12a63729f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS280/SN74LS280_SC1-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS280/SN74LS280_SC1_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS280/SN74LS280_SC1_Previous_Values.xml new file mode 100644 index 000000000..d78b2c9aa --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS280/SN74LS280_SC1_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file From e566423975e69b20ee4299270b9c56be3491c69b Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:28:50 +0530 Subject: [PATCH 03/33] Create analysis --- library/SubcircuitLibrary/SN7480/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/SN7480/analysis diff --git a/library/SubcircuitLibrary/SN7480/analysis b/library/SubcircuitLibrary/SN7480/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/SN7480/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From d049526270aa7dd4bff3ce436ec471a748569593 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:30:09 +0530 Subject: [PATCH 04/33] Add files via upload --- .../SN7480/SC_7480_new-cache.lib | 150 +++++ .../SubcircuitLibrary/SN7480/SC_7480_new.cir | 33 + .../SN7480/SC_7480_new.cir.out | 93 +++ .../SubcircuitLibrary/SN7480/SC_7480_new.pro | 73 +++ .../SubcircuitLibrary/SN7480/SC_7480_new.sch | 610 ++++++++++++++++++ .../SubcircuitLibrary/SN7480/SC_7480_new.sub | 87 +++ .../SN7480/SC_7480_new_Previous_Values.xml | 1 + 7 files changed, 1047 insertions(+) create mode 100644 library/SubcircuitLibrary/SN7480/SC_7480_new-cache.lib create mode 100644 library/SubcircuitLibrary/SN7480/SC_7480_new.cir create mode 100644 library/SubcircuitLibrary/SN7480/SC_7480_new.cir.out create mode 100644 library/SubcircuitLibrary/SN7480/SC_7480_new.pro create mode 100644 library/SubcircuitLibrary/SN7480/SC_7480_new.sch create mode 100644 library/SubcircuitLibrary/SN7480/SC_7480_new.sub create mode 100644 library/SubcircuitLibrary/SN7480/SC_7480_new_Previous_Values.xml diff --git a/library/SubcircuitLibrary/SN7480/SC_7480_new-cache.lib b/library/SubcircuitLibrary/SN7480/SC_7480_new-cache.lib new file mode 100644 index 000000000..2857ddf4b --- /dev/null +++ b/library/SubcircuitLibrary/SN7480/SC_7480_new-cache.lib @@ -0,0 +1,150 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7480/SC_7480_new.cir b/library/SubcircuitLibrary/SN7480/SC_7480_new.cir new file mode 100644 index 000000000..6af45d173 --- /dev/null +++ b/library/SubcircuitLibrary/SN7480/SC_7480_new.cir @@ -0,0 +1,33 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_7480_new\SC_7480_new.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/28/25 13:19:54 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U2-Pad3_ d_nand +U4 Net-_U2-Pad3_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and +U15 Net-_U10-Pad3_ Net-_U1-Pad4_ Net-_U15-Pad3_ d_and +U16 Net-_U1-Pad4_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_and +U17 Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U17-Pad3_ d_and +X2 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_X1-Pad4_ Net-_U18-Pad1_ 4_OR +U18 Net-_U18-Pad1_ Net-_U1-Pad6_ d_inverter +U20 Net-_U1-Pad6_ Net-_U1-Pad5_ d_inverter +U12 Net-_U1-Pad3_ Net-_U10-Pad3_ Net-_U12-Pad3_ d_and +U13 Net-_U1-Pad3_ Net-_U11-Pad3_ Net-_U13-Pad3_ d_and +U14 Net-_U11-Pad3_ Net-_U10-Pad3_ Net-_U14-Pad3_ d_and +X3 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U14-Pad3_ ? Net-_U19-Pad1_ 4_OR +U19 Net-_U19-Pad1_ Net-_U1-Pad4_ d_inverter +U3 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U3-Pad3_ d_nand +U5 Net-_U3-Pad3_ Net-_U1-Pad1_ Net-_U5-Pad3_ d_and +X1 Net-_U11-Pad3_ Net-_U10-Pad3_ Net-_U1-Pad3_ Net-_X1-Pad4_ 3_and +U7 Net-_U1-Pad11_ Net-_U10-Pad2_ d_inverter +U9 Net-_U5-Pad3_ Net-_U11-Pad1_ d_inverter +U6 Net-_U1-Pad2_ Net-_U11-Pad2_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U8 Net-_U4-Pad3_ Net-_U10-Pad1_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN7480/SC_7480_new.cir.out b/library/SubcircuitLibrary/SN7480/SC_7480_new.cir.out new file mode 100644 index 000000000..bfd28cdcb --- /dev/null +++ b/library/SubcircuitLibrary/SN7480/SC_7480_new.cir.out @@ -0,0 +1,93 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_7480_new\sc_7480_new.cir + +.include 3_and.sub +.include 4_OR.sub +* u2 net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u15 net-_u10-pad3_ net-_u1-pad4_ net-_u15-pad3_ d_and +* u16 net-_u1-pad4_ net-_u11-pad3_ net-_u16-pad3_ d_and +* u17 net-_u1-pad4_ net-_u1-pad3_ net-_u17-pad3_ d_and +x2 net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_x1-pad4_ net-_u18-pad1_ 4_OR +* u18 net-_u18-pad1_ net-_u1-pad6_ d_inverter +* u20 net-_u1-pad6_ net-_u1-pad5_ d_inverter +* u12 net-_u1-pad3_ net-_u10-pad3_ net-_u12-pad3_ d_and +* u13 net-_u1-pad3_ net-_u11-pad3_ net-_u13-pad3_ d_and +* u14 net-_u11-pad3_ net-_u10-pad3_ net-_u14-pad3_ d_and +x3 net-_u12-pad3_ net-_u13-pad3_ net-_u14-pad3_ ? net-_u19-pad1_ 4_OR +* u19 net-_u19-pad1_ net-_u1-pad4_ d_inverter +* u3 net-_u1-pad12_ net-_u1-pad13_ net-_u3-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u1-pad1_ net-_u5-pad3_ d_and +x1 net-_u11-pad3_ net-_u10-pad3_ net-_u1-pad3_ net-_x1-pad4_ 3_and +* u7 net-_u1-pad11_ net-_u10-pad2_ d_inverter +* u9 net-_u5-pad3_ net-_u11-pad1_ d_inverter +* u6 net-_u1-pad2_ net-_u11-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u8 net-_u4-pad3_ net-_u10-pad1_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a3 [net-_u10-pad3_ net-_u1-pad4_ ] net-_u15-pad3_ u15 +a4 [net-_u1-pad4_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a5 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u17-pad3_ u17 +a6 net-_u18-pad1_ net-_u1-pad6_ u18 +a7 net-_u1-pad6_ net-_u1-pad5_ u20 +a8 [net-_u1-pad3_ net-_u10-pad3_ ] net-_u12-pad3_ u12 +a9 [net-_u1-pad3_ net-_u11-pad3_ ] net-_u13-pad3_ u13 +a10 [net-_u11-pad3_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a11 net-_u19-pad1_ net-_u1-pad4_ u19 +a12 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u3-pad3_ u3 +a13 [net-_u3-pad3_ net-_u1-pad1_ ] net-_u5-pad3_ u5 +a14 net-_u1-pad11_ net-_u10-pad2_ u7 +a15 net-_u5-pad3_ net-_u11-pad1_ u9 +a16 net-_u1-pad2_ net-_u11-pad2_ u6 +a17 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a18 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a19 net-_u4-pad3_ net-_u10-pad1_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7480/SC_7480_new.pro b/library/SubcircuitLibrary/SN7480/SC_7480_new.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN7480/SC_7480_new.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7480/SC_7480_new.sch b/library/SubcircuitLibrary/SN7480/SC_7480_new.sch new file mode 100644 index 000000000..4f4c8996d --- /dev/null +++ b/library/SubcircuitLibrary/SN7480/SC_7480_new.sch @@ -0,0 +1,610 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_7480-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 6836B7FD +P 3100 1800 +F 0 "U2" H 3100 1800 60 0000 C CNN +F 1 "d_nand" H 3150 1900 60 0000 C CNN +F 2 "" H 3100 1800 60 0000 C CNN +F 3 "" H 3100 1800 60 0000 C CNN + 1 3100 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 6836B7FE +P 4600 1800 +F 0 "U4" H 4600 1800 60 0000 C CNN +F 1 "d_and" H 4650 1900 60 0000 C CNN +F 2 "" H 4600 1800 60 0000 C CNN +F 3 "" H 4600 1800 60 0000 C CNN + 1 4600 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U15 +U 1 1 6836B7FF +P 7700 1800 +F 0 "U15" H 7700 1800 60 0000 C CNN +F 1 "d_and" H 7750 1900 60 0000 C CNN +F 2 "" H 7700 1800 60 0000 C CNN +F 3 "" H 7700 1800 60 0000 C CNN + 1 7700 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 6836B800 +P 7700 2300 +F 0 "U16" H 7700 2300 60 0000 C CNN +F 1 "d_and" H 7750 2400 60 0000 C CNN +F 2 "" H 7700 2300 60 0000 C CNN +F 3 "" H 7700 2300 60 0000 C CNN + 1 7700 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 6836B801 +P 7700 2750 +F 0 "U17" H 7700 2750 60 0000 C CNN +F 1 "d_and" H 7750 2850 60 0000 C CNN +F 2 "" H 7700 2750 60 0000 C CNN +F 3 "" H 7700 2750 60 0000 C CNN + 1 7700 2750 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X2 +U 1 1 6836B802 +P 8850 2400 +F 0 "X2" H 9000 2300 60 0000 C CNN +F 1 "4_OR" H 9000 2500 60 0000 C CNN +F 2 "" H 8850 2400 60 0000 C CNN +F 3 "" H 8850 2400 60 0000 C CNN + 1 8850 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 6836B803 +P 9700 2400 +F 0 "U18" H 9700 2300 60 0000 C CNN +F 1 "d_inverter" H 9700 2550 60 0000 C CNN +F 2 "" H 9750 2350 60 0000 C CNN +F 3 "" H 9750 2350 60 0000 C CNN + 1 9700 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 6836B804 +P 10450 2400 +F 0 "U20" H 10450 2300 60 0000 C CNN +F 1 "d_inverter" H 10450 2550 60 0000 C CNN +F 2 "" H 10500 2350 60 0000 C CNN +F 3 "" H 10500 2350 60 0000 C CNN + 1 10450 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 6836B805 +P 7650 3700 +F 0 "U12" H 7650 3700 60 0000 C CNN +F 1 "d_and" H 7700 3800 60 0000 C CNN +F 2 "" H 7650 3700 60 0000 C CNN +F 3 "" H 7650 3700 60 0000 C CNN + 1 7650 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 6836B806 +P 7650 4150 +F 0 "U13" H 7650 4150 60 0000 C CNN +F 1 "d_and" H 7700 4250 60 0000 C CNN +F 2 "" H 7650 4150 60 0000 C CNN +F 3 "" H 7650 4150 60 0000 C CNN + 1 7650 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 6836B807 +P 7650 4550 +F 0 "U14" H 7650 4550 60 0000 C CNN +F 1 "d_and" H 7700 4650 60 0000 C CNN +F 2 "" H 7650 4550 60 0000 C CNN +F 3 "" H 7650 4550 60 0000 C CNN + 1 7650 4550 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X3 +U 1 1 6836B808 +P 9000 3950 +F 0 "X3" H 9150 3850 60 0000 C CNN +F 1 "4_OR" H 9150 4050 60 0000 C CNN +F 2 "" H 9000 3950 60 0000 C CNN +F 3 "" H 9000 3950 60 0000 C CNN + 1 9000 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 6836B809 +P 9850 3950 +F 0 "U19" H 9850 3850 60 0000 C CNN +F 1 "d_inverter" H 9850 4100 60 0000 C CNN +F 2 "" H 9900 3900 60 0000 C CNN +F 3 "" H 9900 3900 60 0000 C CNN + 1 9850 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U3 +U 1 1 6836B80A +P 3200 3550 +F 0 "U3" H 3200 3550 60 0000 C CNN +F 1 "d_nand" H 3250 3650 60 0000 C CNN +F 2 "" H 3200 3550 60 0000 C CNN +F 3 "" H 3200 3550 60 0000 C CNN + 1 3200 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 6836B80B +P 4700 3550 +F 0 "U5" H 4700 3550 60 0000 C CNN +F 1 "d_and" H 4750 3650 60 0000 C CNN +F 2 "" H 4700 3550 60 0000 C CNN +F 3 "" H 4700 3550 60 0000 C CNN + 1 4700 3550 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 6836B80C +P 7650 3200 +F 0 "X1" H 7750 3150 60 0000 C CNN +F 1 "3_and" H 7800 3350 60 0000 C CNN +F 2 "" H 7650 3200 60 0000 C CNN +F 3 "" H 7650 3200 60 0000 C CNN + 1 7650 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3550 1750 4000 1750 +Wire Wire Line + 4000 1750 4000 1700 +Wire Wire Line + 4000 1700 4150 1700 +Wire Wire Line + 3650 3500 4100 3500 +Wire Wire Line + 4100 3500 4100 3450 +Wire Wire Line + 4100 3450 4250 3450 +Wire Wire Line + 6350 1750 7100 1750 +Wire Wire Line + 7100 1750 7100 1700 +Wire Wire Line + 7100 1700 7250 1700 +Wire Wire Line + 10150 2400 10000 2400 +Wire Wire Line + 8150 1750 8500 1750 +Wire Wire Line + 8500 1750 8500 2250 +Wire Wire Line + 8150 2250 8400 2250 +Wire Wire Line + 8400 2250 8400 2350 +Wire Wire Line + 8400 2350 8500 2350 +Wire Wire Line + 8500 2450 8150 2450 +Wire Wire Line + 8150 2450 8150 2700 +Wire Wire Line + 8500 2550 8500 3150 +Wire Wire Line + 8500 3150 8150 3150 +Wire Wire Line + 8100 3650 8450 3650 +Wire Wire Line + 8450 3650 8450 3800 +Wire Wire Line + 8450 3800 8650 3800 +Wire Wire Line + 8100 4100 8400 4100 +Wire Wire Line + 8400 4100 8400 3900 +Wire Wire Line + 8400 3900 8650 3900 +Wire Wire Line + 8100 4500 8500 4500 +Wire Wire Line + 8500 4500 8500 4000 +Wire Wire Line + 8500 4000 8650 4000 +Wire Wire Line + 7250 1800 6950 1800 +Wire Wire Line + 6950 1800 6950 3400 +Wire Wire Line + 6950 2200 7250 2200 +Wire Wire Line + 6950 2650 7250 2650 +Connection ~ 6950 2200 +Wire Wire Line + 10150 3950 10450 3950 +Wire Wire Line + 10450 3950 10450 4000 +Wire Wire Line + 10550 4000 10550 3400 +Wire Wire Line + 10550 3400 6950 3400 +Connection ~ 6950 2650 +Wire Wire Line + 7300 3050 6600 3050 +Wire Wire Line + 6600 3050 6600 3500 +Wire Wire Line + 6600 3500 6450 3500 +Wire Wire Line + 6550 1750 6550 4550 +Wire Wire Line + 6550 3150 7300 3150 +Connection ~ 6550 1750 +Wire Wire Line + 6550 3700 7200 3700 +Connection ~ 6550 3150 +Wire Wire Line + 6550 4550 7200 4550 +Connection ~ 6550 3700 +Wire Wire Line + 7250 2300 6850 2300 +Wire Wire Line + 6850 2300 6850 4450 +Connection ~ 6850 3050 +Wire Wire Line + 6850 4450 7200 4450 +Wire Wire Line + 7200 4150 6850 4150 +Connection ~ 6850 4150 +Wire Wire Line + 7200 3600 6950 3600 +Wire Wire Line + 6950 3600 6950 4050 +Wire Wire Line + 6200 4050 7200 4050 +Wire Wire Line + 7300 3250 7050 3250 +Wire Wire Line + 7050 2750 7050 3600 +Connection ~ 7050 3600 +Wire Wire Line + 7250 2750 7050 2750 +Connection ~ 7050 3250 +Wire Wire Line + 10450 4000 10550 4000 +Wire Wire Line + 10500 4900 10500 4000 +Connection ~ 10500 4000 +Connection ~ 6950 4050 +$Comp +L d_inverter U7 +U 1 1 6836B81C +P 5400 2200 +F 0 "U7" H 5400 2100 60 0000 C CNN +F 1 "d_inverter" H 5400 2350 60 0000 C CNN +F 2 "" H 5450 2150 60 0000 C CNN +F 3 "" H 5450 2150 60 0000 C CNN + 1 5400 2200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6836B81D +P 5500 3200 +F 0 "U9" H 5500 3100 60 0000 C CNN +F 1 "d_inverter" H 5500 3350 60 0000 C CNN +F 2 "" H 5550 3150 60 0000 C CNN +F 3 "" H 5550 3150 60 0000 C CNN + 1 5500 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6836B81E +P 5150 4050 +F 0 "U6" H 5150 3950 60 0000 C CNN +F 1 "d_inverter" H 5150 4200 60 0000 C CNN +F 2 "" H 5200 4000 60 0000 C CNN +F 3 "" H 5200 4000 60 0000 C CNN + 1 5150 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 1350 5150 1750 +Wire Wire Line + 5150 1750 5050 1750 +Wire Wire Line + 5200 3200 5200 3500 +Wire Wire Line + 5200 3500 5150 3500 +$Comp +L d_or U10 +U 1 1 6836B81F +P 5900 1800 +F 0 "U10" H 5900 1800 60 0000 C CNN +F 1 "d_or" H 5900 1900 60 0000 C CNN +F 2 "" H 5900 1800 60 0000 C CNN +F 3 "" H 5900 1800 60 0000 C CNN + 1 5900 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U11 +U 1 1 6836B820 +P 6000 3550 +F 0 "U11" H 6000 3550 60 0000 C CNN +F 1 "d_or" H 6000 3650 60 0000 C CNN +F 2 "" H 6000 3550 60 0000 C CNN +F 3 "" H 6000 3550 60 0000 C CNN + 1 6000 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5450 1700 5450 1550 +Wire Wire Line + 5450 1550 5750 1550 +Wire Wire Line + 5750 1550 5750 1350 +Wire Wire Line + 5450 1800 5450 2000 +Wire Wire Line + 5450 2000 5700 2000 +Wire Wire Line + 5700 2000 5700 2200 +Wire Wire Line + 5800 3200 5800 3350 +Wire Wire Line + 5800 3350 5550 3350 +Wire Wire Line + 5550 3350 5550 3450 +Wire Wire Line + 5550 3550 5550 4050 +Wire Wire Line + 5550 4050 5450 4050 +$Comp +L d_inverter U8 +U 1 1 6836B81B +P 5450 1350 +F 0 "U8" H 5450 1250 60 0000 C CNN +F 1 "d_inverter" H 5450 1500 60 0000 C CNN +F 2 "" H 5500 1300 60 0000 C CNN +F 3 "" H 5500 1300 60 0000 C CNN + 1 5450 1350 + 1 0 0 -1 +$EndComp +NoConn ~ 8650 4100 +$Comp +L PORT U1 +U 1 1 6836CCE5 +P 4250 3800 +F 0 "U1" H 4300 3900 30 0000 C CNN +F 1 "PORT" H 4250 3800 30 0000 C CNN +F 2 "" H 4250 3800 60 0000 C CNN +F 3 "" H 4250 3800 60 0000 C CNN + 1 4250 3800 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 6836CD70 +P 4600 4050 +F 0 "U1" H 4650 4150 30 0000 C CNN +F 1 "PORT" H 4600 4050 30 0000 C CNN +F 2 "" H 4600 4050 60 0000 C CNN +F 3 "" H 4600 4050 60 0000 C CNN + 2 4600 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6836CDBF +P 5950 4050 +F 0 "U1" H 6000 4150 30 0000 C CNN +F 1 "PORT" H 5950 4050 30 0000 C CNN +F 2 "" H 5950 4050 60 0000 C CNN +F 3 "" H 5950 4050 60 0000 C CNN + 3 5950 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6836CEC0 +P 10250 4900 +F 0 "U1" H 10300 5000 30 0000 C CNN +F 1 "PORT" H 10250 4900 30 0000 C CNN +F 2 "" H 10250 4900 60 0000 C CNN +F 3 "" H 10250 4900 60 0000 C CNN + 4 10250 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6836CF61 +P 11000 2400 +F 0 "U1" H 11050 2500 30 0000 C CNN +F 1 "PORT" H 11000 2400 30 0000 C CNN +F 2 "" H 11000 2400 60 0000 C CNN +F 3 "" H 11000 2400 60 0000 C CNN + 5 11000 2400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 6836CFDC +P 10100 2750 +F 0 "U1" H 10150 2850 30 0000 C CNN +F 1 "PORT" H 10100 2750 30 0000 C CNN +F 2 "" H 10100 2750 60 0000 C CNN +F 3 "" H 10100 2750 60 0000 C CNN + 6 10100 2750 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 6836D56D +P 2950 4600 +F 0 "U1" H 3000 4700 30 0000 C CNN +F 1 "PORT" H 2950 4600 30 0000 C CNN +F 2 "" H 2950 4600 60 0000 C CNN +F 3 "" H 2950 4600 60 0000 C CNN + 7 2950 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6836D5D2 +P 2400 1700 +F 0 "U1" H 2450 1800 30 0000 C CNN +F 1 "PORT" H 2400 1700 30 0000 C CNN +F 2 "" H 2400 1700 60 0000 C CNN +F 3 "" H 2400 1700 60 0000 C CNN + 8 2400 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6836D6B7 +P 2650 2050 +F 0 "U1" H 2700 2150 30 0000 C CNN +F 1 "PORT" H 2650 2050 30 0000 C CNN +F 2 "" H 2650 2050 60 0000 C CNN +F 3 "" H 2650 2050 60 0000 C CNN + 9 2650 2050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 6836D728 +P 4150 2050 +F 0 "U1" H 4200 2150 30 0000 C CNN +F 1 "PORT" H 4150 2050 30 0000 C CNN +F 2 "" H 4150 2050 60 0000 C CNN +F 3 "" H 4150 2050 60 0000 C CNN + 10 4150 2050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 6836D79D +P 4850 2200 +F 0 "U1" H 4900 2300 30 0000 C CNN +F 1 "PORT" H 4850 2200 30 0000 C CNN +F 2 "" H 4850 2200 60 0000 C CNN +F 3 "" H 4850 2200 60 0000 C CNN + 11 4850 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6836E026 +P 2500 3450 +F 0 "U1" H 2550 3550 30 0000 C CNN +F 1 "PORT" H 2500 3450 30 0000 C CNN +F 2 "" H 2500 3450 60 0000 C CNN +F 3 "" H 2500 3450 60 0000 C CNN + 12 2500 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6836E099 +P 2750 3800 +F 0 "U1" H 2800 3900 30 0000 C CNN +F 1 "PORT" H 2750 3800 30 0000 C CNN +F 2 "" H 2750 3800 60 0000 C CNN +F 3 "" H 2750 3800 60 0000 C CNN + 13 2750 3800 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 6836E181 +P 2950 4300 +F 0 "U1" H 3000 4400 30 0000 C CNN +F 1 "PORT" H 2950 4300 30 0000 C CNN +F 2 "" H 2950 4300 60 0000 C CNN +F 3 "" H 2950 4300 60 0000 C CNN + 14 2950 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10100 2500 10100 2400 +Connection ~ 10100 2400 +NoConn ~ 3200 4300 +NoConn ~ 3200 4600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7480/SC_7480_new.sub b/library/SubcircuitLibrary/SN7480/SC_7480_new.sub new file mode 100644 index 000000000..86e36349a --- /dev/null +++ b/library/SubcircuitLibrary/SN7480/SC_7480_new.sub @@ -0,0 +1,87 @@ +* Subcircuit SC_7480_new +.subckt SC_7480_new net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_7480_new\sc_7480_new.cir +.include 3_and.sub +.include 4_OR.sub +* u2 net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_nand +* u4 net-_u2-pad3_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u15 net-_u10-pad3_ net-_u1-pad4_ net-_u15-pad3_ d_and +* u16 net-_u1-pad4_ net-_u11-pad3_ net-_u16-pad3_ d_and +* u17 net-_u1-pad4_ net-_u1-pad3_ net-_u17-pad3_ d_and +x2 net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_x1-pad4_ net-_u18-pad1_ 4_OR +* u18 net-_u18-pad1_ net-_u1-pad6_ d_inverter +* u20 net-_u1-pad6_ net-_u1-pad5_ d_inverter +* u12 net-_u1-pad3_ net-_u10-pad3_ net-_u12-pad3_ d_and +* u13 net-_u1-pad3_ net-_u11-pad3_ net-_u13-pad3_ d_and +* u14 net-_u11-pad3_ net-_u10-pad3_ net-_u14-pad3_ d_and +x3 net-_u12-pad3_ net-_u13-pad3_ net-_u14-pad3_ ? net-_u19-pad1_ 4_OR +* u19 net-_u19-pad1_ net-_u1-pad4_ d_inverter +* u3 net-_u1-pad12_ net-_u1-pad13_ net-_u3-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u1-pad1_ net-_u5-pad3_ d_and +x1 net-_u11-pad3_ net-_u10-pad3_ net-_u1-pad3_ net-_x1-pad4_ 3_and +* u7 net-_u1-pad11_ net-_u10-pad2_ d_inverter +* u9 net-_u5-pad3_ net-_u11-pad1_ d_inverter +* u6 net-_u1-pad2_ net-_u11-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u8 net-_u4-pad3_ net-_u10-pad1_ d_inverter +a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a3 [net-_u10-pad3_ net-_u1-pad4_ ] net-_u15-pad3_ u15 +a4 [net-_u1-pad4_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a5 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u17-pad3_ u17 +a6 net-_u18-pad1_ net-_u1-pad6_ u18 +a7 net-_u1-pad6_ net-_u1-pad5_ u20 +a8 [net-_u1-pad3_ net-_u10-pad3_ ] net-_u12-pad3_ u12 +a9 [net-_u1-pad3_ net-_u11-pad3_ ] net-_u13-pad3_ u13 +a10 [net-_u11-pad3_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a11 net-_u19-pad1_ net-_u1-pad4_ u19 +a12 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u3-pad3_ u3 +a13 [net-_u3-pad3_ net-_u1-pad1_ ] net-_u5-pad3_ u5 +a14 net-_u1-pad11_ net-_u10-pad2_ u7 +a15 net-_u5-pad3_ net-_u11-pad1_ u9 +a16 net-_u1-pad2_ net-_u11-pad2_ u6 +a17 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a18 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a19 net-_u4-pad3_ net-_u10-pad1_ u8 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_7480_new \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7480/SC_7480_new_Previous_Values.xml b/library/SubcircuitLibrary/SN7480/SC_7480_new_Previous_Values.xml new file mode 100644 index 000000000..b9ff13bdd --- /dev/null +++ b/library/SubcircuitLibrary/SN7480/SC_7480_new_Previous_Values.xml @@ -0,0 +1 @@ +d_nandd_andd_andd_andd_andd_inverterd_inverterd_andd_andd_andd_inverterd_nandd_andd_inverterd_inverterd_inverterd_ord_ord_inverterC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file From 0e713b3c0a1d8d9524c43e0fceb7b5fd07ebced0 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:32:23 +0530 Subject: [PATCH 05/33] Create analysis --- library/SubcircuitLibrary/MC74HC595A/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/MC74HC595A/analysis diff --git a/library/SubcircuitLibrary/MC74HC595A/analysis b/library/SubcircuitLibrary/MC74HC595A/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC595A/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From db29574d47bcab2b098f1193cc12f0fbd63676bf Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:33:31 +0530 Subject: [PATCH 06/33] Add files via upload --- .../MC74HC595A/SC_MC74HC595A-cache.lib | 51 + .../MC74HC595A/SC_MC74HC595A.cir | 67 ++ .../MC74HC595A/SC_MC74HC595A.cir.out | 236 ++++ .../MC74HC595A/SC_MC74HC595A.pro | 73 ++ .../MC74HC595A/SC_MC74HC595A.sch | 1064 +++++++++++++++++ .../SC_MC74HC595A_Previous_Values.xml | 1 + 6 files changed, 1492 insertions(+) create mode 100644 library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A-cache.lib create mode 100644 library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.cir create mode 100644 library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.cir.out create mode 100644 library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.pro create mode 100644 library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.sch create mode 100644 library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A_Previous_Values.xml diff --git a/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A-cache.lib b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A-cache.lib new file mode 100644 index 000000000..d09cef252 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A-cache.lib @@ -0,0 +1,51 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.cir b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.cir new file mode 100644 index 000000000..dc78fb852 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.cir @@ -0,0 +1,67 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_MC74HC595A\SC_MC74HC595A.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/02/25 20:15:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ ? Net-_U16-Pad4_ Net-_U16-Pad5_ ? d_dff +U17 Net-_U16-Pad5_ Net-_U17-Pad2_ ? Net-_U16-Pad4_ Net-_U17-Pad5_ ? d_dff +U18 Net-_U17-Pad5_ Net-_U10-Pad2_ ? Net-_U16-Pad4_ Net-_U18-Pad5_ ? d_dff +U19 Net-_U18-Pad5_ Net-_U11-Pad2_ ? Net-_U16-Pad4_ Net-_U19-Pad5_ ? d_dff +U20 Net-_U19-Pad5_ Net-_U12-Pad2_ ? Net-_U16-Pad4_ Net-_U20-Pad5_ ? d_dff +U21 Net-_U20-Pad5_ Net-_U13-Pad2_ ? Net-_U16-Pad4_ Net-_U21-Pad5_ ? d_dff +U22 Net-_U21-Pad5_ Net-_U14-Pad2_ ? Net-_U16-Pad4_ Net-_U22-Pad5_ ? d_dff +U33 Net-_U16-Pad5_ Net-_U24-Pad2_ ? ? ? Net-_U33-Pad6_ d_dff +U35 Net-_U17-Pad5_ Net-_U26-Pad2_ ? ? ? Net-_U35-Pad6_ d_dff +U36 Net-_U18-Pad5_ Net-_U27-Pad2_ ? ? ? Net-_U36-Pad6_ d_dff +U37 Net-_U19-Pad5_ Net-_U28-Pad2_ ? ? ? Net-_U37-Pad6_ d_dff +U38 Net-_U20-Pad5_ Net-_U29-Pad2_ ? ? ? Net-_U38-Pad6_ d_dff +U39 Net-_U21-Pad5_ Net-_U30-Pad2_ ? ? ? Net-_U39-Pad6_ d_dff +U40 Net-_U22-Pad5_ Net-_U31-Pad2_ ? ? ? Net-_U40-Pad6_ d_dff +U4 Net-_U1-Pad13_ Net-_U4-Pad2_ d_inverter +U2 Net-_U1-Pad12_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad14_ Net-_U3-Pad2_ d_inverter +U7 Net-_U3-Pad2_ Net-_U16-Pad1_ d_inverter +U6 Net-_U1-Pad10_ Net-_U16-Pad4_ d_inverter +U5 Net-_U1-Pad11_ Net-_U10-Pad1_ d_inverter +U23 Net-_U22-Pad5_ Net-_U15-Pad2_ ? Net-_U16-Pad4_ Net-_U23-Pad5_ ? d_dff +U34 Net-_U23-Pad5_ Net-_U25-Pad2_ ? ? ? Net-_U34-Pad6_ d_dff +U32 Net-_U23-Pad5_ Net-_U32-Pad2_ d_inverter +U41 Net-_U32-Pad2_ Net-_U1-Pad9_ d_inverter +U8 Net-_U10-Pad1_ Net-_U16-Pad2_ d_inverter +U9 Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U10-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U10-Pad1_ Net-_U12-Pad2_ d_inverter +U13 Net-_U10-Pad1_ Net-_U13-Pad2_ d_inverter +U14 Net-_U10-Pad1_ Net-_U14-Pad2_ d_inverter +U15 Net-_U10-Pad1_ Net-_U15-Pad2_ d_inverter +U25 Net-_U2-Pad2_ Net-_U25-Pad2_ d_inverter +U50 Net-_U42-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad7_ d_tristate +U57 Net-_U49-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad6_ d_tristate +U43 Net-_U33-Pad6_ Net-_U43-Pad2_ d_inverter +U51 Net-_U43-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad15_ d_tristate +U44 Net-_U35-Pad6_ Net-_U44-Pad2_ d_inverter +U45 Net-_U36-Pad6_ Net-_U45-Pad2_ d_inverter +U46 Net-_U37-Pad6_ Net-_U46-Pad2_ d_inverter +U47 Net-_U38-Pad6_ Net-_U47-Pad2_ d_inverter +U48 Net-_U39-Pad6_ Net-_U48-Pad2_ d_inverter +U49 Net-_U40-Pad6_ Net-_U49-Pad2_ d_inverter +U42 Net-_U34-Pad6_ Net-_U42-Pad2_ d_inverter +U52 Net-_U44-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad1_ d_tristate +U53 Net-_U45-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad2_ d_tristate +U54 Net-_U46-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad3_ d_tristate +U55 Net-_U47-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad4_ d_tristate +U56 Net-_U48-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad5_ d_tristate +U24 Net-_U2-Pad2_ Net-_U24-Pad2_ d_inverter +U26 Net-_U2-Pad2_ Net-_U26-Pad2_ d_inverter +U27 Net-_U2-Pad2_ Net-_U27-Pad2_ d_inverter +U28 Net-_U2-Pad2_ Net-_U28-Pad2_ d_inverter +U29 Net-_U2-Pad2_ Net-_U29-Pad2_ d_inverter +U30 Net-_U2-Pad2_ Net-_U30-Pad2_ d_inverter +U31 Net-_U2-Pad2_ Net-_U31-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.cir.out b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.cir.out new file mode 100644 index 000000000..8b5b95908 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.cir.out @@ -0,0 +1,236 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_mc74hc595a\sc_mc74hc595a.cir + +* u16 net-_u16-pad1_ net-_u16-pad2_ ? net-_u16-pad4_ net-_u16-pad5_ ? d_dff +* u17 net-_u16-pad5_ net-_u17-pad2_ ? net-_u16-pad4_ net-_u17-pad5_ ? d_dff +* u18 net-_u17-pad5_ net-_u10-pad2_ ? net-_u16-pad4_ net-_u18-pad5_ ? d_dff +* u19 net-_u18-pad5_ net-_u11-pad2_ ? net-_u16-pad4_ net-_u19-pad5_ ? d_dff +* u20 net-_u19-pad5_ net-_u12-pad2_ ? net-_u16-pad4_ net-_u20-pad5_ ? d_dff +* u21 net-_u20-pad5_ net-_u13-pad2_ ? net-_u16-pad4_ net-_u21-pad5_ ? d_dff +* u22 net-_u21-pad5_ net-_u14-pad2_ ? net-_u16-pad4_ net-_u22-pad5_ ? d_dff +* u33 net-_u16-pad5_ net-_u24-pad2_ ? ? ? net-_u33-pad6_ d_dff +* u35 net-_u17-pad5_ net-_u26-pad2_ ? ? ? net-_u35-pad6_ d_dff +* u36 net-_u18-pad5_ net-_u27-pad2_ ? ? ? net-_u36-pad6_ d_dff +* u37 net-_u19-pad5_ net-_u28-pad2_ ? ? ? net-_u37-pad6_ d_dff +* u38 net-_u20-pad5_ net-_u29-pad2_ ? ? ? net-_u38-pad6_ d_dff +* u39 net-_u21-pad5_ net-_u30-pad2_ ? ? ? net-_u39-pad6_ d_dff +* u40 net-_u22-pad5_ net-_u31-pad2_ ? ? ? net-_u40-pad6_ d_dff +* u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad14_ net-_u3-pad2_ d_inverter +* u7 net-_u3-pad2_ net-_u16-pad1_ d_inverter +* u6 net-_u1-pad10_ net-_u16-pad4_ d_inverter +* u5 net-_u1-pad11_ net-_u10-pad1_ d_inverter +* u23 net-_u22-pad5_ net-_u15-pad2_ ? net-_u16-pad4_ net-_u23-pad5_ ? d_dff +* u34 net-_u23-pad5_ net-_u25-pad2_ ? ? ? net-_u34-pad6_ d_dff +* u32 net-_u23-pad5_ net-_u32-pad2_ d_inverter +* u41 net-_u32-pad2_ net-_u1-pad9_ d_inverter +* u8 net-_u10-pad1_ net-_u16-pad2_ d_inverter +* u9 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u10-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u10-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u10-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u10-pad1_ net-_u15-pad2_ d_inverter +* u25 net-_u2-pad2_ net-_u25-pad2_ d_inverter +* u50 net-_u42-pad2_ net-_u4-pad2_ net-_u1-pad7_ d_tristate +* u57 net-_u49-pad2_ net-_u4-pad2_ net-_u1-pad6_ d_tristate +* u43 net-_u33-pad6_ net-_u43-pad2_ d_inverter +* u51 net-_u43-pad2_ net-_u4-pad2_ net-_u1-pad15_ d_tristate +* u44 net-_u35-pad6_ net-_u44-pad2_ d_inverter +* u45 net-_u36-pad6_ net-_u45-pad2_ d_inverter +* u46 net-_u37-pad6_ net-_u46-pad2_ d_inverter +* u47 net-_u38-pad6_ net-_u47-pad2_ d_inverter +* u48 net-_u39-pad6_ net-_u48-pad2_ d_inverter +* u49 net-_u40-pad6_ net-_u49-pad2_ d_inverter +* u42 net-_u34-pad6_ net-_u42-pad2_ d_inverter +* u52 net-_u44-pad2_ net-_u4-pad2_ net-_u1-pad1_ d_tristate +* u53 net-_u45-pad2_ net-_u4-pad2_ net-_u1-pad2_ d_tristate +* u54 net-_u46-pad2_ net-_u4-pad2_ net-_u1-pad3_ d_tristate +* u55 net-_u47-pad2_ net-_u4-pad2_ net-_u1-pad4_ d_tristate +* u56 net-_u48-pad2_ net-_u4-pad2_ net-_u1-pad5_ d_tristate +* u24 net-_u2-pad2_ net-_u24-pad2_ d_inverter +* u26 net-_u2-pad2_ net-_u26-pad2_ d_inverter +* u27 net-_u2-pad2_ net-_u27-pad2_ d_inverter +* u28 net-_u2-pad2_ net-_u28-pad2_ d_inverter +* u29 net-_u2-pad2_ net-_u29-pad2_ d_inverter +* u30 net-_u2-pad2_ net-_u30-pad2_ d_inverter +* u31 net-_u2-pad2_ net-_u31-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 net-_u16-pad1_ net-_u16-pad2_ ? net-_u16-pad4_ net-_u16-pad5_ ? u16 +a2 net-_u16-pad5_ net-_u17-pad2_ ? net-_u16-pad4_ net-_u17-pad5_ ? u17 +a3 net-_u17-pad5_ net-_u10-pad2_ ? net-_u16-pad4_ net-_u18-pad5_ ? u18 +a4 net-_u18-pad5_ net-_u11-pad2_ ? net-_u16-pad4_ net-_u19-pad5_ ? u19 +a5 net-_u19-pad5_ net-_u12-pad2_ ? net-_u16-pad4_ net-_u20-pad5_ ? u20 +a6 net-_u20-pad5_ net-_u13-pad2_ ? net-_u16-pad4_ net-_u21-pad5_ ? u21 +a7 net-_u21-pad5_ net-_u14-pad2_ ? net-_u16-pad4_ net-_u22-pad5_ ? u22 +a8 net-_u16-pad5_ net-_u24-pad2_ ? ? ? net-_u33-pad6_ u33 +a9 net-_u17-pad5_ net-_u26-pad2_ ? ? ? net-_u35-pad6_ u35 +a10 net-_u18-pad5_ net-_u27-pad2_ ? ? ? net-_u36-pad6_ u36 +a11 net-_u19-pad5_ net-_u28-pad2_ ? ? ? net-_u37-pad6_ u37 +a12 net-_u20-pad5_ net-_u29-pad2_ ? ? ? net-_u38-pad6_ u38 +a13 net-_u21-pad5_ net-_u30-pad2_ ? ? ? net-_u39-pad6_ u39 +a14 net-_u22-pad5_ net-_u31-pad2_ ? ? ? net-_u40-pad6_ u40 +a15 net-_u1-pad13_ net-_u4-pad2_ u4 +a16 net-_u1-pad12_ net-_u2-pad2_ u2 +a17 net-_u1-pad14_ net-_u3-pad2_ u3 +a18 net-_u3-pad2_ net-_u16-pad1_ u7 +a19 net-_u1-pad10_ net-_u16-pad4_ u6 +a20 net-_u1-pad11_ net-_u10-pad1_ u5 +a21 net-_u22-pad5_ net-_u15-pad2_ ? net-_u16-pad4_ net-_u23-pad5_ ? u23 +a22 net-_u23-pad5_ net-_u25-pad2_ ? ? ? net-_u34-pad6_ u34 +a23 net-_u23-pad5_ net-_u32-pad2_ u32 +a24 net-_u32-pad2_ net-_u1-pad9_ u41 +a25 net-_u10-pad1_ net-_u16-pad2_ u8 +a26 net-_u10-pad1_ net-_u17-pad2_ u9 +a27 net-_u10-pad1_ net-_u10-pad2_ u10 +a28 net-_u10-pad1_ net-_u11-pad2_ u11 +a29 net-_u10-pad1_ net-_u12-pad2_ u12 +a30 net-_u10-pad1_ net-_u13-pad2_ u13 +a31 net-_u10-pad1_ net-_u14-pad2_ u14 +a32 net-_u10-pad1_ net-_u15-pad2_ u15 +a33 net-_u2-pad2_ net-_u25-pad2_ u25 +a34 net-_u42-pad2_ net-_u4-pad2_ net-_u1-pad7_ u50 +a35 net-_u49-pad2_ net-_u4-pad2_ net-_u1-pad6_ u57 +a36 net-_u33-pad6_ net-_u43-pad2_ u43 +a37 net-_u43-pad2_ net-_u4-pad2_ net-_u1-pad15_ u51 +a38 net-_u35-pad6_ net-_u44-pad2_ u44 +a39 net-_u36-pad6_ net-_u45-pad2_ u45 +a40 net-_u37-pad6_ net-_u46-pad2_ u46 +a41 net-_u38-pad6_ net-_u47-pad2_ u47 +a42 net-_u39-pad6_ net-_u48-pad2_ u48 +a43 net-_u40-pad6_ net-_u49-pad2_ u49 +a44 net-_u34-pad6_ net-_u42-pad2_ u42 +a45 net-_u44-pad2_ net-_u4-pad2_ net-_u1-pad1_ u52 +a46 net-_u45-pad2_ net-_u4-pad2_ net-_u1-pad2_ u53 +a47 net-_u46-pad2_ net-_u4-pad2_ net-_u1-pad3_ u54 +a48 net-_u47-pad2_ net-_u4-pad2_ net-_u1-pad4_ u55 +a49 net-_u48-pad2_ net-_u4-pad2_ net-_u1-pad5_ u56 +a50 net-_u2-pad2_ net-_u24-pad2_ u24 +a51 net-_u2-pad2_ net-_u26-pad2_ u26 +a52 net-_u2-pad2_ net-_u27-pad2_ u27 +a53 net-_u2-pad2_ net-_u28-pad2_ u28 +a54 net-_u2-pad2_ net-_u29-pad2_ u29 +a55 net-_u2-pad2_ net-_u30-pad2_ u30 +a56 net-_u2-pad2_ net-_u31-pad2_ u31 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u16 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u17 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u19 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u20 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u21 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u33 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u35 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u36 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u37 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u38 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u39 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u40 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u23 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u34 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u50 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u57 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u51 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u52 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u53 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u54 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u55 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u56 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.pro b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.sch b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.sch new file mode 100644 index 000000000..c2790eae6 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A.sch @@ -0,0 +1,1064 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_MC74HC595A-cache +EELAYER 25 0 +EELAYER END +$Descr A4 8268 11693 portrait +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U15 +U 1 1 683AB520 +P 3450 950 +F 0 "U15" H 3450 950 60 0000 C CNN +F 1 "d_dff" H 3450 1100 60 0000 C CNN +F 2 "" H 3450 950 60 0000 C CNN +F 3 "" H 3450 950 60 0000 C CNN + 1 3450 950 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U16 +U 1 1 683AB56F +P 3450 2450 +F 0 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0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 683E70DA +P 5100 5650 +F 0 "U27" H 5100 5550 60 0000 C CNN +F 1 "d_inverter" H 5100 5800 60 0000 C CNN +F 2 "" H 5150 5600 60 0000 C CNN +F 3 "" H 5150 5600 60 0000 C CNN + 1 5100 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U28 +U 1 1 683E7E4B +P 5100 7150 +F 0 "U28" H 5100 7050 60 0000 C CNN +F 1 "d_inverter" H 5100 7300 60 0000 C CNN +F 2 "" H 5150 7100 60 0000 C CNN +F 3 "" H 5150 7100 60 0000 C CNN + 1 5100 7150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 683E7EE4 +P 5100 8650 +F 0 "U29" H 5100 8550 60 0000 C CNN +F 1 "d_inverter" H 5100 8800 60 0000 C CNN +F 2 "" H 5150 8600 60 0000 C CNN +F 3 "" H 5150 8600 60 0000 C CNN + 1 5100 8650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 683E88B4 +P 5100 10350 +F 0 "U30" H 5100 10250 60 0000 C CNN +F 1 "d_inverter" H 5100 10500 60 0000 C CNN +F 2 "" H 5150 10300 60 0000 C CNN +F 3 "" H 5150 10300 60 0000 C CNN + 1 5100 10350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4750 -150 4750 12250 +Wire Wire Line + 4750 10350 4800 10350 +Wire Wire Line + 4750 8650 4800 8650 +Connection ~ 4750 10350 +Wire Wire Line + 4800 7150 4750 7150 +Connection ~ 4750 8650 +Wire Wire Line + 4800 5650 4750 5650 +Connection ~ 4750 7150 +Wire Wire Line + 4800 4200 4750 4200 +Connection ~ 4750 5650 +Wire Wire Line + 4800 2750 4750 2750 +Connection ~ 4750 4200 +Connection ~ 4750 2750 +Wire Wire Line + 1300 -150 4750 -150 +Connection ~ 4750 1250 +NoConn ~ 3450 300 +NoConn ~ 5900 300 +NoConn ~ 4000 1250 +NoConn ~ 5900 1550 +NoConn ~ 3450 1800 +NoConn ~ 4000 2750 +NoConn ~ 6500 2100 +NoConn ~ 5950 1800 +NoConn ~ 5950 3050 +NoConn ~ 3450 3250 +NoConn ~ 5950 3250 +NoConn ~ 6500 3550 +NoConn ~ 5950 4500 +NoConn ~ 5950 4700 +NoConn ~ 4000 4200 +NoConn ~ 6500 5000 +NoConn ~ 3450 4700 +NoConn ~ 4000 5650 +NoConn ~ 5950 5950 +NoConn ~ 3450 6200 +NoConn ~ 5950 6200 +NoConn ~ 6500 6500 +NoConn ~ 4000 7150 +NoConn ~ 5950 7450 +NoConn ~ 3450 7700 +NoConn ~ 4000 8650 +NoConn ~ 5950 7700 +NoConn ~ 6500 8000 +NoConn ~ 5950 8950 +NoConn ~ 3450 9400 +NoConn ~ 4000 10350 +NoConn ~ 5950 9400 +NoConn ~ 6500 9700 +NoConn ~ 5950 10650 +NoConn ~ 3450 11300 +NoConn ~ 5900 11300 +NoConn ~ 6450 11600 +NoConn ~ 4000 12250 +NoConn ~ 5900 12550 +$Comp +L PORT U1 +U 1 1 683F1FB5 +P 9350 2750 +F 0 "U1" H 9400 2850 30 0000 C CNN +F 1 "PORT" H 9350 2750 30 0000 C CNN +F 2 "" H 9350 2750 60 0000 C CNN +F 3 "" H 9350 2750 60 0000 C CNN + 1 9350 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 683F2583 +P 9350 4200 +F 0 "U1" H 9400 4300 30 0000 C CNN +F 1 "PORT" H 9350 4200 30 0000 C CNN +F 2 "" H 9350 4200 60 0000 C CNN +F 3 "" H 9350 4200 60 0000 C CNN + 2 9350 4200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 683F262E +P 9350 5650 +F 0 "U1" H 9400 5750 30 0000 C CNN +F 1 "PORT" H 9350 5650 30 0000 C CNN +F 2 "" H 9350 5650 60 0000 C CNN +F 3 "" H 9350 5650 60 0000 C CNN + 3 9350 5650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 683F2E74 +P 9350 7150 +F 0 "U1" H 9400 7250 30 0000 C CNN +F 1 "PORT" H 9350 7150 30 0000 C CNN +F 2 "" H 9350 7150 60 0000 C CNN +F 3 "" H 9350 7150 60 0000 C CNN + 4 9350 7150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 683F2F77 +P 9350 8650 +F 0 "U1" H 9400 8750 30 0000 C CNN +F 1 "PORT" H 9350 8650 30 0000 C CNN +F 2 "" H 9350 8650 60 0000 C CNN +F 3 "" H 9350 8650 60 0000 C CNN + 5 9350 8650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 683F385A +P 9350 10350 +F 0 "U1" H 9400 10450 30 0000 C CNN +F 1 "PORT" H 9350 10350 30 0000 C CNN +F 2 "" H 9350 10350 60 0000 C CNN +F 3 "" H 9350 10350 60 0000 C CNN + 6 9350 10350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 683F390F +P 9300 12250 +F 0 "U1" H 9350 12350 30 0000 C CNN +F 1 "PORT" H 9300 12250 30 0000 C CNN +F 2 "" H 9300 12250 60 0000 C CNN +F 3 "" H 9300 12250 60 0000 C CNN + 7 9300 12250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 683F40AC +P 950 10750 +F 0 "U1" H 1000 10850 30 0000 C CNN +F 1 "PORT" H 950 10750 30 0000 C CNN +F 2 "" H 950 10750 60 0000 C CNN +F 3 "" H 950 10750 60 0000 C CNN + 8 950 10750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 683F4179 +P 7250 13000 +F 0 "U1" H 7300 13100 30 0000 C CNN +F 1 "PORT" H 7250 13000 30 0000 C CNN +F 2 "" H 7250 13000 60 0000 C CNN +F 3 "" H 7250 13000 60 0000 C CNN + 9 7250 13000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 683F423A +P 1200 12550 +F 0 "U1" H 1250 12650 30 0000 C CNN +F 1 "PORT" H 1200 12550 30 0000 C CNN +F 2 "" H 1200 12550 60 0000 C CNN +F 3 "" H 1200 12550 60 0000 C CNN + 10 1200 12550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 683F435B +P 900 12250 +F 0 "U1" H 950 12350 30 0000 C CNN +F 1 "PORT" H 900 12250 30 0000 C CNN +F 2 "" H 900 12250 60 0000 C CNN +F 3 "" H 900 12250 60 0000 C CNN + 11 900 12250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 683F4A27 +P 450 -150 +F 0 "U1" H 500 -50 30 0000 C CNN +F 1 "PORT" H 450 -150 30 0000 C CNN +F 2 "" H 450 -150 60 0000 C CNN +F 3 "" H 450 -150 60 0000 C CNN + 12 450 -150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 683F4AF0 +P 500 -850 +F 0 "U1" H 550 -750 30 0000 C CNN +F 1 "PORT" H 500 -850 30 0000 C CNN +F 2 "" H 500 -850 60 0000 C CNN +F 3 "" H 500 -850 60 0000 C CNN + 13 500 -850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 683F4BB1 +P 450 600 +F 0 "U1" H 500 700 30 0000 C CNN +F 1 "PORT" H 450 600 30 0000 C CNN +F 2 "" H 450 600 60 0000 C CNN +F 3 "" H 450 600 60 0000 C CNN + 14 450 600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 683F5162 +P 9350 1250 +F 0 "U1" H 9400 1350 30 0000 C CNN +F 1 "PORT" H 9350 1250 30 0000 C CNN +F 2 "" H 9350 1250 60 0000 C CNN +F 3 "" H 9350 1250 60 0000 C CNN + 15 9350 1250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 683F6C3B +P 950 10400 +F 0 "U1" H 1000 10500 30 0000 C CNN +F 1 "PORT" H 950 10400 30 0000 C CNN +F 2 "" H 950 10400 60 0000 C CNN +F 3 "" H 950 10400 60 0000 C CNN + 16 950 10400 + 1 0 0 -1 +$EndComp +NoConn ~ 1200 10400 +NoConn ~ 1200 10750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A_Previous_Values.xml b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A_Previous_Values.xml new file mode 100644 index 000000000..fe8c1448f --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC595A/SC_MC74HC595A_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsmsd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_dffd_dffd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_tristated_tristated_inverterd_tristated_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_tristated_tristated_tristated_tristated_tristated_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverter \ No newline at end of file From 77a19ec1b29b438d5debd5721808f50faa797ff8 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:35:14 +0530 Subject: [PATCH 07/33] Create analysis --- library/SubcircuitLibrary/74HC4017/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/74HC4017/analysis diff --git a/library/SubcircuitLibrary/74HC4017/analysis b/library/SubcircuitLibrary/74HC4017/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4017/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From c3333e22c4fb9bf60aede1e98d1760f6511d23fa Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:37:28 +0530 Subject: [PATCH 08/33] Add files via upload --- .../74HC4017/SC_74HC4017-cache.lib | 145 ++++ .../74HC4017/SC_74HC4017.cir | 43 + .../74HC4017/SC_74HC4017.cir.out | 140 ++++ .../74HC4017/SC_74HC4017.pro | 73 ++ .../74HC4017/SC_74HC4017.sch | 762 ++++++++++++++++++ .../74HC4017/SC_74HC4017.sub | 134 +++ .../74HC4017/SC_74HC4017_Previous_Values.xml | 1 + 7 files changed, 1298 insertions(+) create mode 100644 library/SubcircuitLibrary/74HC4017/SC_74HC4017-cache.lib create mode 100644 library/SubcircuitLibrary/74HC4017/SC_74HC4017.cir create mode 100644 library/SubcircuitLibrary/74HC4017/SC_74HC4017.cir.out create mode 100644 library/SubcircuitLibrary/74HC4017/SC_74HC4017.pro create mode 100644 library/SubcircuitLibrary/74HC4017/SC_74HC4017.sch create mode 100644 library/SubcircuitLibrary/74HC4017/SC_74HC4017.sub create mode 100644 library/SubcircuitLibrary/74HC4017/SC_74HC4017_Previous_Values.xml diff --git a/library/SubcircuitLibrary/74HC4017/SC_74HC4017-cache.lib b/library/SubcircuitLibrary/74HC4017/SC_74HC4017-cache.lib new file mode 100644 index 000000000..8401faf10 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4017/SC_74HC4017-cache.lib @@ -0,0 +1,145 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74HC4017/SC_74HC4017.cir b/library/SubcircuitLibrary/74HC4017/SC_74HC4017.cir new file mode 100644 index 000000000..91c3e9528 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4017/SC_74HC4017.cir @@ -0,0 +1,43 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_74HC4017\SC_74HC4017.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/03/25 21:35:34 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U18 Net-_U12-Pad5_ Net-_U12-Pad2_ ? Net-_U12-Pad4_ Net-_U18-Pad5_ Net-_U10-Pad2_ d_dff +U24 Net-_U21-Pad3_ Net-_U12-Pad2_ ? Net-_U12-Pad4_ Net-_U10-Pad1_ Net-_U13-Pad1_ d_dff +U29 Net-_U10-Pad1_ Net-_U12-Pad2_ ? Net-_U12-Pad4_ Net-_U13-Pad2_ Net-_U15-Pad1_ d_dff +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ ? Net-_U12-Pad4_ Net-_U12-Pad5_ Net-_U12-Pad6_ d_dff +U33 Net-_U13-Pad2_ Net-_U12-Pad2_ ? Net-_U12-Pad4_ Net-_U15-Pad2_ Net-_U12-Pad1_ d_dff +U3 Net-_U1-Pad13_ Net-_U3-Pad2_ d_inverter +U2 Net-_U1-Pad14_ Net-_U2-Pad2_ d_buffer +U4 Net-_U1-Pad15_ Net-_U12-Pad4_ d_buffer +U11 Net-_U10-Pad3_ Net-_U1-Pad4_ d_buffer +U9 Net-_U8-Pad3_ Net-_U1-Pad2_ d_buffer +U6 Net-_U5-Pad3_ Net-_U1-Pad3_ d_buffer +U14 Net-_U13-Pad3_ Net-_U1-Pad7_ d_buffer +U16 Net-_U15-Pad3_ Net-_U1-Pad10_ d_buffer +U20 Net-_U19-Pad3_ Net-_U1-Pad1_ d_buffer +U23 Net-_U22-Pad3_ Net-_U1-Pad5_ d_buffer +U26 Net-_U25-Pad3_ Net-_U1-Pad6_ d_buffer +U28 Net-_U27-Pad3_ Net-_U1-Pad9_ d_buffer +U31 Net-_U30-Pad3_ Net-_U1-Pad11_ d_buffer +U32 Net-_U12-Pad1_ Net-_U1-Pad12_ d_buffer +U5 Net-_U12-Pad5_ Net-_U15-Pad2_ Net-_U5-Pad3_ d_nor +U8 Net-_U12-Pad6_ Net-_U18-Pad5_ Net-_U8-Pad3_ d_nor +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nor +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor +U19 Net-_U12-Pad1_ Net-_U12-Pad6_ Net-_U19-Pad3_ d_nor +U22 Net-_U10-Pad2_ Net-_U12-Pad5_ Net-_U22-Pad3_ d_nor +U25 Net-_U13-Pad1_ Net-_U18-Pad5_ Net-_U25-Pad3_ d_nor +U30 Net-_U12-Pad1_ Net-_U13-Pad2_ Net-_U30-Pad3_ d_nor +U27 Net-_U10-Pad1_ Net-_U15-Pad1_ Net-_U27-Pad3_ d_nor +U17 Net-_U10-Pad1_ Net-_U12-Pad5_ Net-_U17-Pad3_ d_or +U21 Net-_U17-Pad3_ Net-_U18-Pad5_ Net-_U21-Pad3_ d_and +U7 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U12-Pad2_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/74HC4017/SC_74HC4017.cir.out b/library/SubcircuitLibrary/74HC4017/SC_74HC4017.cir.out new file mode 100644 index 000000000..4c5ee301f --- /dev/null +++ b/library/SubcircuitLibrary/74HC4017/SC_74HC4017.cir.out @@ -0,0 +1,140 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_74hc4017\sc_74hc4017.cir + +* u18 net-_u12-pad5_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u18-pad5_ net-_u10-pad2_ d_dff +* u24 net-_u21-pad3_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u10-pad1_ net-_u13-pad1_ d_dff +* u29 net-_u10-pad1_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u13-pad2_ net-_u15-pad1_ d_dff +* u12 net-_u12-pad1_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u12-pad5_ net-_u12-pad6_ d_dff +* u33 net-_u13-pad2_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u15-pad2_ net-_u12-pad1_ d_dff +* u3 net-_u1-pad13_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad14_ net-_u2-pad2_ d_buffer +* u4 net-_u1-pad15_ net-_u12-pad4_ d_buffer +* u11 net-_u10-pad3_ net-_u1-pad4_ d_buffer +* u9 net-_u8-pad3_ net-_u1-pad2_ d_buffer +* u6 net-_u5-pad3_ net-_u1-pad3_ d_buffer +* u14 net-_u13-pad3_ net-_u1-pad7_ d_buffer +* u16 net-_u15-pad3_ net-_u1-pad10_ d_buffer +* u20 net-_u19-pad3_ net-_u1-pad1_ d_buffer +* u23 net-_u22-pad3_ net-_u1-pad5_ d_buffer +* u26 net-_u25-pad3_ net-_u1-pad6_ d_buffer +* u28 net-_u27-pad3_ net-_u1-pad9_ d_buffer +* u31 net-_u30-pad3_ net-_u1-pad11_ d_buffer +* u32 net-_u12-pad1_ net-_u1-pad12_ d_buffer +* u5 net-_u12-pad5_ net-_u15-pad2_ net-_u5-pad3_ d_nor +* u8 net-_u12-pad6_ net-_u18-pad5_ net-_u8-pad3_ d_nor +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u19 net-_u12-pad1_ net-_u12-pad6_ net-_u19-pad3_ d_nor +* u22 net-_u10-pad2_ net-_u12-pad5_ net-_u22-pad3_ d_nor +* u25 net-_u13-pad1_ net-_u18-pad5_ net-_u25-pad3_ d_nor +* u30 net-_u12-pad1_ net-_u13-pad2_ net-_u30-pad3_ d_nor +* u27 net-_u10-pad1_ net-_u15-pad1_ net-_u27-pad3_ d_nor +* u17 net-_u10-pad1_ net-_u12-pad5_ net-_u17-pad3_ d_or +* u21 net-_u17-pad3_ net-_u18-pad5_ net-_u21-pad3_ d_and +* u7 net-_u3-pad2_ net-_u2-pad2_ net-_u12-pad2_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 net-_u12-pad5_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u18-pad5_ net-_u10-pad2_ u18 +a2 net-_u21-pad3_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u10-pad1_ net-_u13-pad1_ u24 +a3 net-_u10-pad1_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u13-pad2_ net-_u15-pad1_ u29 +a4 net-_u12-pad1_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u12-pad5_ net-_u12-pad6_ u12 +a5 net-_u13-pad2_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u15-pad2_ net-_u12-pad1_ u33 +a6 net-_u1-pad13_ net-_u3-pad2_ u3 +a7 net-_u1-pad14_ net-_u2-pad2_ u2 +a8 net-_u1-pad15_ net-_u12-pad4_ u4 +a9 net-_u10-pad3_ net-_u1-pad4_ u11 +a10 net-_u8-pad3_ net-_u1-pad2_ u9 +a11 net-_u5-pad3_ net-_u1-pad3_ u6 +a12 net-_u13-pad3_ net-_u1-pad7_ u14 +a13 net-_u15-pad3_ net-_u1-pad10_ u16 +a14 net-_u19-pad3_ net-_u1-pad1_ u20 +a15 net-_u22-pad3_ net-_u1-pad5_ u23 +a16 net-_u25-pad3_ net-_u1-pad6_ u26 +a17 net-_u27-pad3_ net-_u1-pad9_ u28 +a18 net-_u30-pad3_ net-_u1-pad11_ u31 +a19 net-_u12-pad1_ net-_u1-pad12_ u32 +a20 [net-_u12-pad5_ net-_u15-pad2_ ] net-_u5-pad3_ u5 +a21 [net-_u12-pad6_ net-_u18-pad5_ ] net-_u8-pad3_ u8 +a22 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a23 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a24 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a25 [net-_u12-pad1_ net-_u12-pad6_ ] net-_u19-pad3_ u19 +a26 [net-_u10-pad2_ net-_u12-pad5_ ] net-_u22-pad3_ u22 +a27 [net-_u13-pad1_ net-_u18-pad5_ ] net-_u25-pad3_ u25 +a28 [net-_u12-pad1_ net-_u13-pad2_ ] net-_u30-pad3_ u30 +a29 [net-_u10-pad1_ net-_u15-pad1_ ] net-_u27-pad3_ u27 +a30 [net-_u10-pad1_ net-_u12-pad5_ ] net-_u17-pad3_ u17 +a31 [net-_u17-pad3_ net-_u18-pad5_ ] net-_u21-pad3_ u21 +a32 [net-_u3-pad2_ net-_u2-pad2_ ] net-_u12-pad2_ u7 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u29 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u33 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u9 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u16 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u28 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u32 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74HC4017/SC_74HC4017.pro b/library/SubcircuitLibrary/74HC4017/SC_74HC4017.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74HC4017/SC_74HC4017.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74HC4017/SC_74HC4017.sch b/library/SubcircuitLibrary/74HC4017/SC_74HC4017.sch new file mode 100644 index 000000000..07c9f07a8 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4017/SC_74HC4017.sch @@ -0,0 +1,762 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U18 +U 1 1 683F0E90 +P 5200 2100 +F 0 "U18" H 5200 2100 60 0000 C CNN +F 1 "d_dff" H 5200 2250 60 0000 C CNN +F 2 "" H 5200 2100 60 0000 C CNN +F 3 "" H 5200 2100 60 0000 C CNN + 1 5200 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U24 +U 1 1 683F0EDF +P 6900 2100 +F 0 "U24" H 6900 2100 60 0000 C CNN +F 1 "d_dff" H 6900 2250 60 0000 C CNN +F 2 "" H 6900 2100 60 0000 C CNN +F 3 "" H 6900 2100 60 0000 C CNN + 1 6900 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U29 +U 1 1 683F0F10 +P 8400 2100 +F 0 "U29" H 8400 2100 60 0000 C CNN +F 1 "d_dff" H 8400 2250 60 0000 C CNN +F 2 "" H 8400 2100 60 0000 C CNN +F 3 "" H 8400 2100 60 0000 C CNN + 1 8400 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U12 +U 1 1 683F0F49 +P 3750 2100 +F 0 "U12" H 3750 2100 60 0000 C CNN +F 1 "d_dff" H 3750 2250 60 0000 C CNN +F 2 "" H 3750 2100 60 0000 C CNN +F 3 "" H 3750 2100 60 0000 C CNN + 1 3750 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U33 +U 1 1 683F0F96 +P 9900 2100 +F 0 "U33" H 9900 2100 60 0000 C CNN +F 1 "d_dff" H 9900 2250 60 0000 C CNN +F 2 "" H 9900 2100 60 0000 C CNN +F 3 "" H 9900 2100 60 0000 C CNN + 1 9900 2100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 683F101F +P 1350 1500 +F 0 "U3" H 1350 1400 60 0000 C CNN +F 1 "d_inverter" H 1350 1650 60 0000 C CNN +F 2 "" H 1400 1450 60 0000 C CNN +F 3 "" H 1400 1450 60 0000 C CNN + 1 1350 1500 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U2 +U 1 1 683F10C4 +P 1150 2050 +F 0 "U2" H 1150 2000 60 0000 C CNN +F 1 "d_buffer" H 1150 2100 60 0000 C CNN +F 2 "" H 1150 2050 60 0000 C CNN +F 3 "" H 1150 2050 60 0000 C CNN + 1 1150 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U4 +U 1 1 683F1111 +P 1350 2700 +F 0 "U4" H 1350 2650 60 0000 C CNN +F 1 "d_buffer" H 1350 2750 60 0000 C CNN +F 2 "" H 1350 2700 60 0000 C CNN +F 3 "" H 1350 2700 60 0000 C CNN + 1 1350 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U11 +U 1 1 683F125A +P 3550 5400 +F 0 "U11" H 3550 5350 60 0000 C CNN +F 1 "d_buffer" H 3550 5450 60 0000 C CNN +F 2 "" H 3550 5400 60 0000 C CNN +F 3 "" H 3550 5400 60 0000 C CNN + 1 3550 5400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U9 +U 1 1 683F12B5 +P 2800 5400 +F 0 "U9" H 2800 5350 60 0000 C CNN +F 1 "d_buffer" H 2800 5450 60 0000 C CNN +F 2 "" H 2800 5400 60 0000 C CNN +F 3 "" H 2800 5400 60 0000 C CNN + 1 2800 5400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U6 +U 1 1 683F1300 +P 2050 5400 +F 0 "U6" H 2050 5350 60 0000 C CNN +F 1 "d_buffer" H 2050 5450 60 0000 C CNN +F 2 "" H 2050 5400 60 0000 C CNN +F 3 "" H 2050 5400 60 0000 C CNN + 1 2050 5400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U14 +U 1 1 683F1368 +P 4200 5400 +F 0 "U14" H 4200 5350 60 0000 C CNN +F 1 "d_buffer" H 4200 5450 60 0000 C CNN +F 2 "" H 4200 5400 60 0000 C CNN +F 3 "" H 4200 5400 60 0000 C CNN + 1 4200 5400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U16 +U 1 1 683F13AF +P 4900 5400 +F 0 "U16" H 4900 5350 60 0000 C CNN +F 1 "d_buffer" H 4900 5450 60 0000 C CNN +F 2 "" H 4900 5400 60 0000 C CNN +F 3 "" H 4900 5400 60 0000 C CNN + 1 4900 5400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U20 +U 1 1 683F1588 +P 5700 5400 +F 0 "U20" H 5700 5350 60 0000 C CNN +F 1 "d_buffer" H 5700 5450 60 0000 C CNN +F 2 "" H 5700 5400 60 0000 C CNN +F 3 "" H 5700 5400 60 0000 C CNN + 1 5700 5400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U23 +U 1 1 683F15D7 +P 6500 5400 +F 0 "U23" H 6500 5350 60 0000 C CNN +F 1 "d_buffer" H 6500 5450 60 0000 C CNN +F 2 "" H 6500 5400 60 0000 C CNN +F 3 "" H 6500 5400 60 0000 C CNN + 1 6500 5400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U26 +U 1 1 683F1626 +P 7250 5400 +F 0 "U26" H 7250 5350 60 0000 C CNN +F 1 "d_buffer" H 7250 5450 60 0000 C CNN +F 2 "" H 7250 5400 60 0000 C CNN +F 3 "" H 7250 5400 60 0000 C CNN + 1 7250 5400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U28 +U 1 1 683F1671 +P 7950 5400 +F 0 "U28" H 7950 5350 60 0000 C CNN +F 1 "d_buffer" H 7950 5450 60 0000 C CNN +F 2 "" H 7950 5400 60 0000 C CNN +F 3 "" H 7950 5400 60 0000 C CNN + 1 7950 5400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U31 +U 1 1 683F16BE +P 8750 5400 +F 0 "U31" H 8750 5350 60 0000 C CNN +F 1 "d_buffer" H 8750 5450 60 0000 C CNN +F 2 "" H 8750 5400 60 0000 C CNN +F 3 "" H 8750 5400 60 0000 C CNN + 1 8750 5400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U32 +U 1 1 683F1715 +P 9550 5400 +F 0 "U32" H 9550 5350 60 0000 C CNN +F 1 "d_buffer" H 9550 5450 60 0000 C CNN +F 2 "" H 9550 5400 60 0000 C CNN +F 3 "" H 9550 5400 60 0000 C CNN + 1 9550 5400 + 0 1 1 0 +$EndComp +$Comp +L d_nor U5 +U 1 1 683F1770 +P 2000 4450 +F 0 "U5" H 2000 4450 60 0000 C CNN +F 1 "d_nor" H 2050 4550 60 0000 C CNN +F 2 "" H 2000 4450 60 0000 C CNN +F 3 "" H 2000 4450 60 0000 C CNN + 1 2000 4450 + 0 1 1 0 +$EndComp +$Comp +L d_nor U8 +U 1 1 683F17E1 +P 2750 4450 +F 0 "U8" H 2750 4450 60 0000 C CNN +F 1 "d_nor" H 2800 4550 60 0000 C CNN +F 2 "" H 2750 4450 60 0000 C CNN +F 3 "" H 2750 4450 60 0000 C CNN + 1 2750 4450 + 0 1 1 0 +$EndComp +$Comp +L d_nor U10 +U 1 1 683F183E +P 3500 4450 +F 0 "U10" H 3500 4450 60 0000 C CNN +F 1 "d_nor" H 3550 4550 60 0000 C CNN +F 2 "" H 3500 4450 60 0000 C CNN +F 3 "" H 3500 4450 60 0000 C CNN + 1 3500 4450 + 0 1 1 0 +$EndComp +$Comp +L d_nor U13 +U 1 1 683F1895 +P 4150 4450 +F 0 "U13" H 4150 4450 60 0000 C CNN +F 1 "d_nor" H 4200 4550 60 0000 C CNN +F 2 "" H 4150 4450 60 0000 C CNN +F 3 "" H 4150 4450 60 0000 C CNN + 1 4150 4450 + 0 1 1 0 +$EndComp +$Comp +L d_nor U15 +U 1 1 683F18F2 +P 4850 4450 +F 0 "U15" H 4850 4450 60 0000 C CNN +F 1 "d_nor" H 4900 4550 60 0000 C CNN +F 2 "" H 4850 4450 60 0000 C CNN +F 3 "" H 4850 4450 60 0000 C CNN + 1 4850 4450 + 0 1 1 0 +$EndComp +$Comp +L d_nor U19 +U 1 1 683F1957 +P 5650 4450 +F 0 "U19" H 5650 4450 60 0000 C CNN +F 1 "d_nor" H 5700 4550 60 0000 C CNN +F 2 "" H 5650 4450 60 0000 C CNN +F 3 "" H 5650 4450 60 0000 C CNN + 1 5650 4450 + 0 1 1 0 +$EndComp +$Comp +L d_nor U22 +U 1 1 683F19AC +P 6450 4450 +F 0 "U22" H 6450 4450 60 0000 C CNN +F 1 "d_nor" H 6500 4550 60 0000 C CNN +F 2 "" H 6450 4450 60 0000 C CNN +F 3 "" H 6450 4450 60 0000 C CNN + 1 6450 4450 + 0 1 1 0 +$EndComp +$Comp +L d_nor U25 +U 1 1 683F1A13 +P 7200 4450 +F 0 "U25" H 7200 4450 60 0000 C CNN +F 1 "d_nor" H 7250 4550 60 0000 C CNN +F 2 "" H 7200 4450 60 0000 C CNN +F 3 "" H 7200 4450 60 0000 C CNN + 1 7200 4450 + 0 1 1 0 +$EndComp +$Comp +L d_nor U30 +U 1 1 683F1A80 +P 8700 4450 +F 0 "U30" H 8700 4450 60 0000 C CNN +F 1 "d_nor" H 8750 4550 60 0000 C CNN +F 2 "" H 8700 4450 60 0000 C CNN +F 3 "" H 8700 4450 60 0000 C CNN + 1 8700 4450 + 0 1 1 0 +$EndComp +$Comp +L d_nor U27 +U 1 1 683F1AF1 +P 7900 4450 +F 0 "U27" H 7900 4450 60 0000 C CNN +F 1 "d_nor" H 7950 4550 60 0000 C CNN +F 2 "" H 7900 4450 60 0000 C CNN +F 3 "" H 7900 4450 60 0000 C CNN + 1 7900 4450 + 0 1 1 0 +$EndComp +$Comp +L d_or U17 +U 1 1 683F1D13 +P 5150 900 +F 0 "U17" H 5150 900 60 0000 C CNN +F 1 "d_or" H 5150 1000 60 0000 C CNN +F 2 "" H 5150 900 60 0000 C CNN +F 3 "" H 5150 900 60 0000 C CNN + 1 5150 900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 683F1D96 +P 6450 950 +F 0 "U21" H 6450 950 60 0000 C CNN +F 1 "d_and" H 6500 1050 60 0000 C CNN +F 2 "" H 6450 950 60 0000 C CNN +F 3 "" H 6450 950 60 0000 C CNN + 1 6450 950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 683F1E4B +P 2400 1800 +F 0 "U7" H 2400 1800 60 0000 C CNN +F 1 "d_and" H 2450 1900 60 0000 C CNN +F 2 "" H 2400 1800 60 0000 C CNN +F 3 "" H 2400 1800 60 0000 C CNN + 1 2400 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8950 1750 9350 1750 +Connection ~ 7750 1750 +Wire Wire Line + 7750 600 7750 1750 +Wire Wire Line + 4600 600 7750 600 +Wire Wire Line + 4600 800 4600 600 +Wire Wire Line + 4700 800 4600 800 +Wire Wire Line + 7450 1750 7850 1750 +Wire Wire Line + 6350 1150 6350 1750 +Wire Wire Line + 6900 1150 6350 1150 +Wire Wire Line + 6900 900 6900 1150 +Wire Wire Line + 6000 1750 5750 1750 +Wire Wire Line + 6000 950 6000 3450 +Wire Wire Line + 5600 850 6000 850 +Connection ~ 4600 1750 +Wire Wire Line + 4600 900 4600 1750 +Wire Wire Line + 4700 900 4600 900 +Wire Wire Line + 4300 1750 4650 1750 +Connection ~ 3750 2700 +Connection ~ 5200 2700 +Connection ~ 6900 2700 +Connection ~ 8400 2700 +Wire Wire Line + 2000 2700 9900 2700 +Wire Wire Line + 2850 2400 3200 2400 +Wire Wire Line + 2850 1750 2850 3050 +Wire Wire Line + 1950 2050 1800 2050 +Wire Wire Line + 1950 1800 1950 2050 +Wire Wire Line + 1950 1500 1950 1700 +Wire Wire Line + 1650 1500 1950 1500 +Wire Wire Line + 3200 1750 3200 1250 +Wire Wire Line + 3200 1250 10650 1250 +Wire Wire Line + 10650 1250 10650 4500 +Wire Wire Line + 10650 2400 10450 2400 +Wire Wire Line + 10650 4500 9550 4500 +Wire Wire Line + 9550 4500 9550 4900 +Connection ~ 10650 2400 +Wire Wire Line + 2850 3050 9350 3050 +Wire Wire Line + 4650 3050 4650 2400 +Connection ~ 2850 2400 +Wire Wire Line + 6350 3050 6350 2400 +Connection ~ 4650 3050 +Wire Wire Line + 7850 3050 7850 2400 +Connection ~ 6350 3050 +Wire Wire Line + 9350 3050 9350 2400 +Connection ~ 7850 3050 +Wire Wire Line + 10450 1750 10450 3250 +Wire Wire Line + 10450 3250 2000 3250 +Wire Wire Line + 2000 3250 2000 4000 +Wire Wire Line + 4850 4000 4850 3850 +Wire Wire Line + 4850 3850 2000 3850 +Connection ~ 2000 3850 +Wire Wire Line + 7900 4000 7900 3850 +Wire Wire Line + 4950 3850 8950 3850 +Wire Wire Line + 4950 3850 4950 4000 +Wire Wire Line + 8950 3850 8950 2400 +Connection ~ 7900 3850 +Wire Wire Line + 8800 4000 10650 4000 +Connection ~ 10650 4000 +Wire Wire Line + 5750 4000 5750 3550 +Wire Wire Line + 5750 3550 8800 3550 +Wire Wire Line + 8800 3550 8800 4000 +Wire Wire Line + 6450 4000 6450 3700 +Wire Wire Line + 6450 3700 2100 3700 +Wire Wire Line + 2100 3700 2100 4000 +Wire Wire Line + 4450 1750 4450 3700 +Connection ~ 4450 3700 +Connection ~ 4450 1750 +Wire Wire Line + 7200 4000 7200 3450 +Wire Wire Line + 7200 3450 2750 3450 +Wire Wire Line + 2750 3450 2750 4000 +Connection ~ 6000 3450 +Connection ~ 6000 1750 +Wire Wire Line + 5650 4000 5650 3800 +Wire Wire Line + 5650 3800 2850 3800 +Wire Wire Line + 2850 3800 2850 4000 +Wire Wire Line + 4300 2400 4300 3800 +Connection ~ 4300 3800 +Wire Wire Line + 3500 4000 3500 3100 +Wire Wire Line + 3500 3100 6550 3100 +Wire Wire Line + 6550 3100 6550 4000 +Wire Wire Line + 5750 2400 5750 3100 +Connection ~ 5750 3100 +Wire Wire Line + 8000 4000 8000 3350 +Wire Wire Line + 8000 3350 3600 3350 +Wire Wire Line + 3600 3350 3600 4000 +Wire Wire Line + 7550 1750 7550 3350 +Connection ~ 7550 3350 +Connection ~ 7550 1750 +Wire Wire Line + 4150 4000 4150 2900 +Wire Wire Line + 4150 2900 9050 2900 +Wire Wire Line + 8700 2900 8700 4000 +Wire Wire Line + 9050 2900 9050 1750 +Connection ~ 8700 2900 +Connection ~ 9050 1750 +Wire Wire Line + 7300 4000 7300 3300 +Wire Wire Line + 4250 3300 7450 3300 +Wire Wire Line + 4250 3300 4250 4000 +Wire Wire Line + 7450 3300 7450 2400 +Connection ~ 7300 3300 +NoConn ~ 3750 1450 +NoConn ~ 5200 1450 +NoConn ~ 6900 1450 +NoConn ~ 8400 1450 +NoConn ~ 9900 1450 +$Comp +L PORT U1 +U 1 1 683F4D87 +P 5700 6300 +F 0 "U1" H 5750 6400 30 0000 C CNN +F 1 "PORT" H 5700 6300 30 0000 C CNN +F 2 "" H 5700 6300 60 0000 C CNN +F 3 "" H 5700 6300 60 0000 C CNN + 1 5700 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 683F4E79 +P 2800 6300 +F 0 "U1" H 2850 6400 30 0000 C CNN +F 1 "PORT" H 2800 6300 30 0000 C CNN +F 2 "" H 2800 6300 60 0000 C CNN +F 3 "" H 2800 6300 60 0000 C CNN + 2 2800 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 683F4F2E +P 2050 6300 +F 0 "U1" H 2100 6400 30 0000 C CNN +F 1 "PORT" H 2050 6300 30 0000 C CNN +F 2 "" H 2050 6300 60 0000 C CNN +F 3 "" H 2050 6300 60 0000 C CNN + 3 2050 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 683F4FA9 +P 3550 6300 +F 0 "U1" H 3600 6400 30 0000 C CNN +F 1 "PORT" H 3550 6300 30 0000 C CNN +F 2 "" H 3550 6300 60 0000 C CNN +F 3 "" H 3550 6300 60 0000 C CNN + 4 3550 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 683F5026 +P 6500 6300 +F 0 "U1" H 6550 6400 30 0000 C CNN +F 1 "PORT" H 6500 6300 30 0000 C CNN +F 2 "" H 6500 6300 60 0000 C CNN +F 3 "" H 6500 6300 60 0000 C CNN + 5 6500 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 683F50EC +P 7250 6300 +F 0 "U1" H 7300 6400 30 0000 C CNN +F 1 "PORT" H 7250 6300 30 0000 C CNN +F 2 "" H 7250 6300 60 0000 C CNN +F 3 "" H 7250 6300 60 0000 C CNN + 6 7250 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 683F5171 +P 4200 6300 +F 0 "U1" H 4250 6400 30 0000 C CNN +F 1 "PORT" H 4200 6300 30 0000 C CNN +F 2 "" H 4200 6300 60 0000 C CNN +F 3 "" H 4200 6300 60 0000 C CNN + 7 4200 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 683F5208 +P 1000 5550 +F 0 "U1" H 1050 5650 30 0000 C CNN +F 1 "PORT" H 1000 5550 30 0000 C CNN +F 2 "" H 1000 5550 60 0000 C CNN +F 3 "" H 1000 5550 60 0000 C CNN + 8 1000 5550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 683F5295 +P 7950 6300 +F 0 "U1" H 8000 6400 30 0000 C CNN +F 1 "PORT" H 7950 6300 30 0000 C CNN +F 2 "" H 7950 6300 60 0000 C CNN +F 3 "" H 7950 6300 60 0000 C CNN + 9 7950 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 683F5352 +P 4900 6300 +F 0 "U1" H 4950 6400 30 0000 C CNN +F 1 "PORT" H 4900 6300 30 0000 C CNN +F 2 "" H 4900 6300 60 0000 C CNN +F 3 "" H 4900 6300 60 0000 C CNN + 10 4900 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 683F53E3 +P 8750 6300 +F 0 "U1" H 8800 6400 30 0000 C CNN +F 1 "PORT" H 8750 6300 30 0000 C CNN +F 2 "" H 8750 6300 60 0000 C CNN +F 3 "" H 8750 6300 60 0000 C CNN + 11 8750 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 683F547E +P 9550 6300 +F 0 "U1" H 9600 6400 30 0000 C CNN +F 1 "PORT" H 9550 6300 30 0000 C CNN +F 2 "" H 9550 6300 60 0000 C CNN +F 3 "" H 9550 6300 60 0000 C CNN + 12 9550 6300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 683F550B +P 800 1500 +F 0 "U1" H 850 1600 30 0000 C CNN +F 1 "PORT" H 800 1500 30 0000 C CNN +F 2 "" H 800 1500 60 0000 C CNN +F 3 "" H 800 1500 60 0000 C CNN + 13 800 1500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 683F5608 +P 400 2050 +F 0 "U1" H 450 2150 30 0000 C CNN +F 1 "PORT" H 400 2050 30 0000 C CNN +F 2 "" H 400 2050 60 0000 C CNN +F 3 "" H 400 2050 60 0000 C CNN + 14 400 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 683F5699 +P 600 2700 +F 0 "U1" H 650 2800 30 0000 C CNN +F 1 "PORT" H 600 2700 30 0000 C CNN +F 2 "" H 600 2700 60 0000 C CNN +F 3 "" H 600 2700 60 0000 C CNN + 15 600 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 683F5812 +P 1000 5850 +F 0 "U1" H 1050 5950 30 0000 C CNN +F 1 "PORT" H 1000 5850 30 0000 C CNN +F 2 "" H 1000 5850 60 0000 C CNN +F 3 "" H 1000 5850 60 0000 C CNN + 16 1000 5850 + 1 0 0 -1 +$EndComp +NoConn ~ 1250 5550 +NoConn ~ 1250 5850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74HC4017/SC_74HC4017.sub b/library/SubcircuitLibrary/74HC4017/SC_74HC4017.sub new file mode 100644 index 000000000..aaf592829 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4017/SC_74HC4017.sub @@ -0,0 +1,134 @@ +* Subcircuit SC_74HC4017 +.subckt SC_74HC4017 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_74hc4017\sc_74hc4017.cir +* u18 net-_u12-pad5_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u18-pad5_ net-_u10-pad2_ d_dff +* u24 net-_u21-pad3_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u10-pad1_ net-_u13-pad1_ d_dff +* u29 net-_u10-pad1_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u13-pad2_ net-_u15-pad1_ d_dff +* u12 net-_u12-pad1_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u12-pad5_ net-_u12-pad6_ d_dff +* u33 net-_u13-pad2_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u15-pad2_ net-_u12-pad1_ d_dff +* u3 net-_u1-pad13_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad14_ net-_u2-pad2_ d_buffer +* u4 net-_u1-pad15_ net-_u12-pad4_ d_buffer +* u11 net-_u10-pad3_ net-_u1-pad4_ d_buffer +* u9 net-_u8-pad3_ net-_u1-pad2_ d_buffer +* u6 net-_u5-pad3_ net-_u1-pad3_ d_buffer +* u14 net-_u13-pad3_ net-_u1-pad7_ d_buffer +* u16 net-_u15-pad3_ net-_u1-pad10_ d_buffer +* u20 net-_u19-pad3_ net-_u1-pad1_ d_buffer +* u23 net-_u22-pad3_ net-_u1-pad5_ d_buffer +* u26 net-_u25-pad3_ net-_u1-pad6_ d_buffer +* u28 net-_u27-pad3_ net-_u1-pad9_ d_buffer +* u31 net-_u30-pad3_ net-_u1-pad11_ d_buffer +* u32 net-_u12-pad1_ net-_u1-pad12_ d_buffer +* u5 net-_u12-pad5_ net-_u15-pad2_ net-_u5-pad3_ d_nor +* u8 net-_u12-pad6_ net-_u18-pad5_ net-_u8-pad3_ d_nor +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u19 net-_u12-pad1_ net-_u12-pad6_ net-_u19-pad3_ d_nor +* u22 net-_u10-pad2_ net-_u12-pad5_ net-_u22-pad3_ d_nor +* u25 net-_u13-pad1_ net-_u18-pad5_ net-_u25-pad3_ d_nor +* u30 net-_u12-pad1_ net-_u13-pad2_ net-_u30-pad3_ d_nor +* u27 net-_u10-pad1_ net-_u15-pad1_ net-_u27-pad3_ d_nor +* u17 net-_u10-pad1_ net-_u12-pad5_ net-_u17-pad3_ d_or +* u21 net-_u17-pad3_ net-_u18-pad5_ net-_u21-pad3_ d_and +* u7 net-_u3-pad2_ net-_u2-pad2_ net-_u12-pad2_ d_and +a1 net-_u12-pad5_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u18-pad5_ net-_u10-pad2_ u18 +a2 net-_u21-pad3_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u10-pad1_ net-_u13-pad1_ u24 +a3 net-_u10-pad1_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u13-pad2_ net-_u15-pad1_ u29 +a4 net-_u12-pad1_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u12-pad5_ net-_u12-pad6_ u12 +a5 net-_u13-pad2_ net-_u12-pad2_ ? net-_u12-pad4_ net-_u15-pad2_ net-_u12-pad1_ u33 +a6 net-_u1-pad13_ net-_u3-pad2_ u3 +a7 net-_u1-pad14_ net-_u2-pad2_ u2 +a8 net-_u1-pad15_ net-_u12-pad4_ u4 +a9 net-_u10-pad3_ net-_u1-pad4_ u11 +a10 net-_u8-pad3_ net-_u1-pad2_ u9 +a11 net-_u5-pad3_ net-_u1-pad3_ u6 +a12 net-_u13-pad3_ net-_u1-pad7_ u14 +a13 net-_u15-pad3_ net-_u1-pad10_ u16 +a14 net-_u19-pad3_ net-_u1-pad1_ u20 +a15 net-_u22-pad3_ net-_u1-pad5_ u23 +a16 net-_u25-pad3_ net-_u1-pad6_ u26 +a17 net-_u27-pad3_ net-_u1-pad9_ u28 +a18 net-_u30-pad3_ net-_u1-pad11_ u31 +a19 net-_u12-pad1_ net-_u1-pad12_ u32 +a20 [net-_u12-pad5_ net-_u15-pad2_ ] net-_u5-pad3_ u5 +a21 [net-_u12-pad6_ net-_u18-pad5_ ] net-_u8-pad3_ u8 +a22 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a23 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a24 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a25 [net-_u12-pad1_ net-_u12-pad6_ ] net-_u19-pad3_ u19 +a26 [net-_u10-pad2_ net-_u12-pad5_ ] net-_u22-pad3_ u22 +a27 [net-_u13-pad1_ net-_u18-pad5_ ] net-_u25-pad3_ u25 +a28 [net-_u12-pad1_ net-_u13-pad2_ ] net-_u30-pad3_ u30 +a29 [net-_u10-pad1_ net-_u15-pad1_ ] net-_u27-pad3_ u27 +a30 [net-_u10-pad1_ net-_u12-pad5_ ] net-_u17-pad3_ u17 +a31 [net-_u17-pad3_ net-_u18-pad5_ ] net-_u21-pad3_ u21 +a32 [net-_u3-pad2_ net-_u2-pad2_ ] net-_u12-pad2_ u7 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u29 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u33 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u9 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u16 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u28 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u32 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_74HC4017 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HC4017/SC_74HC4017_Previous_Values.xml b/library/SubcircuitLibrary/74HC4017/SC_74HC4017_Previous_Values.xml new file mode 100644 index 000000000..f7504d716 --- /dev/null +++ b/library/SubcircuitLibrary/74HC4017/SC_74HC4017_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsmsd_dffd_dffd_dffd_dffd_dffd_inverterd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_ord_andd_and \ No newline at end of file From 1edc4b1992811ca339c4ae18c3b104b78fbccd00 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:40:18 +0530 Subject: [PATCH 09/33] Create analysis Octal Counter with 8 decoded Outputs --- library/SubcircuitLibrary/CD4022B/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/CD4022B/analysis diff --git a/library/SubcircuitLibrary/CD4022B/analysis b/library/SubcircuitLibrary/CD4022B/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/CD4022B/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 28890e6729a25ee6cdbc600eb4b26507c58fe93a Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:41:34 +0530 Subject: [PATCH 10/33] Add files via upload Octal Counter with 8 decoded Outputs --- .../CD4022B/SC_CD4022B-cache.lib | 129 +++ .../SubcircuitLibrary/CD4022B/SC_CD4022B.cir | 42 + .../CD4022B/SC_CD4022B.cir.out | 136 ++++ .../SubcircuitLibrary/CD4022B/SC_CD4022B.pro | 73 ++ .../SubcircuitLibrary/CD4022B/SC_CD4022B.sch | 743 ++++++++++++++++++ .../SubcircuitLibrary/CD4022B/SC_CD4022B.sub | 130 +++ .../CD4022B/SC_CD4022B_Previous_Values.xml | 1 + 7 files changed, 1254 insertions(+) create mode 100644 library/SubcircuitLibrary/CD4022B/SC_CD4022B-cache.lib create mode 100644 library/SubcircuitLibrary/CD4022B/SC_CD4022B.cir create mode 100644 library/SubcircuitLibrary/CD4022B/SC_CD4022B.cir.out create mode 100644 library/SubcircuitLibrary/CD4022B/SC_CD4022B.pro create mode 100644 library/SubcircuitLibrary/CD4022B/SC_CD4022B.sch create mode 100644 library/SubcircuitLibrary/CD4022B/SC_CD4022B.sub create mode 100644 library/SubcircuitLibrary/CD4022B/SC_CD4022B_Previous_Values.xml diff --git a/library/SubcircuitLibrary/CD4022B/SC_CD4022B-cache.lib b/library/SubcircuitLibrary/CD4022B/SC_CD4022B-cache.lib new file mode 100644 index 000000000..842abe6be --- /dev/null +++ b/library/SubcircuitLibrary/CD4022B/SC_CD4022B-cache.lib @@ -0,0 +1,129 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4022B/SC_CD4022B.cir b/library/SubcircuitLibrary/CD4022B/SC_CD4022B.cir new file mode 100644 index 000000000..2008fd5a7 --- /dev/null +++ b/library/SubcircuitLibrary/CD4022B/SC_CD4022B.cir @@ -0,0 +1,42 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_CD4022B\SC_CD4022B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/10/25 20:41:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U7 Net-_U16-Pad2_ Net-_U17-Pad2_ ? Net-_U17-Pad4_ Net-_U17-Pad1_ Net-_U13-Pad2_ d_dff +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ ? Net-_U17-Pad4_ Net-_U11-Pad1_ Net-_U17-Pad6_ d_dff +U23 Net-_U18-Pad3_ Net-_U17-Pad2_ ? Net-_U17-Pad4_ Net-_U16-Pad1_ Net-_U11-Pad2_ d_dff +U27 Net-_U16-Pad1_ Net-_U17-Pad2_ ? Net-_U17-Pad4_ Net-_U21-Pad2_ Net-_U16-Pad2_ d_dff +U2 Net-_U1-Pad15_ Net-_U2-Pad2_ d_inverter +U3 Net-_U2-Pad2_ Net-_U17-Pad4_ d_inverter +U9 Net-_U1-Pad13_ Net-_U14-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U13 Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U18 Net-_U17-Pad6_ Net-_U13-Pad3_ Net-_U18-Pad3_ d_nor +U5 Net-_U16-Pad2_ Net-_U13-Pad2_ Net-_U4-Pad1_ d_nand +U8 Net-_U17-Pad1_ Net-_U17-Pad6_ Net-_U6-Pad1_ d_nand +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad1_ d_nand +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U15-Pad1_ d_nand +U21 Net-_U17-Pad1_ Net-_U21-Pad2_ Net-_U19-Pad1_ d_nand +U24 Net-_U13-Pad2_ Net-_U11-Pad1_ Net-_U22-Pad1_ d_nand +U26 Net-_U17-Pad6_ Net-_U16-Pad1_ Net-_U25-Pad1_ d_nand +U29 Net-_U11-Pad2_ Net-_U21-Pad2_ Net-_U28-Pad1_ d_nand +U4 Net-_U4-Pad1_ Net-_U1-Pad2_ d_inverter +U6 Net-_U6-Pad1_ Net-_U1-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U1-Pad3_ d_inverter +U15 Net-_U15-Pad1_ Net-_U1-Pad7_ d_inverter +U19 Net-_U19-Pad1_ Net-_U1-Pad11_ d_inverter +U22 Net-_U22-Pad1_ Net-_U1-Pad4_ d_inverter +U25 Net-_U25-Pad1_ Net-_U1-Pad5_ d_inverter +U28 Net-_U28-Pad1_ Net-_U1-Pad10_ d_inverter +U30 Net-_U30-Pad1_ Net-_U1-Pad12_ d_inverter +U31 Net-_U31-Pad1_ Net-_U30-Pad1_ d_inverter +U32 Net-_U21-Pad2_ Net-_U31-Pad1_ d_inverter +U20 Net-_U12-Pad2_ Net-_U14-Pad2_ Net-_U17-Pad2_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? Net-_U1-Pad7_ ? ? Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U12 Net-_U1-Pad14_ Net-_U12-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/CD4022B/SC_CD4022B.cir.out b/library/SubcircuitLibrary/CD4022B/SC_CD4022B.cir.out new file mode 100644 index 000000000..835af62d0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4022B/SC_CD4022B.cir.out @@ -0,0 +1,136 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_cd4022b\sc_cd4022b.cir + +* u7 net-_u16-pad2_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u17-pad1_ net-_u13-pad2_ d_dff +* u17 net-_u17-pad1_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u11-pad1_ net-_u17-pad6_ d_dff +* u23 net-_u18-pad3_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u16-pad1_ net-_u11-pad2_ d_dff +* u27 net-_u16-pad1_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u21-pad2_ net-_u16-pad2_ d_dff +* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter +* u3 net-_u2-pad2_ net-_u17-pad4_ d_inverter +* u9 net-_u1-pad13_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u13 net-_u11-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u18 net-_u17-pad6_ net-_u13-pad3_ net-_u18-pad3_ d_nor +* u5 net-_u16-pad2_ net-_u13-pad2_ net-_u4-pad1_ d_nand +* u8 net-_u17-pad1_ net-_u17-pad6_ net-_u6-pad1_ d_nand +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad1_ d_nand +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u15-pad1_ d_nand +* u21 net-_u17-pad1_ net-_u21-pad2_ net-_u19-pad1_ d_nand +* u24 net-_u13-pad2_ net-_u11-pad1_ net-_u22-pad1_ d_nand +* u26 net-_u17-pad6_ net-_u16-pad1_ net-_u25-pad1_ d_nand +* u29 net-_u11-pad2_ net-_u21-pad2_ net-_u28-pad1_ d_nand +* u4 net-_u4-pad1_ net-_u1-pad2_ d_inverter +* u6 net-_u6-pad1_ net-_u1-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad3_ d_inverter +* u15 net-_u15-pad1_ net-_u1-pad7_ d_inverter +* u19 net-_u19-pad1_ net-_u1-pad11_ d_inverter +* u22 net-_u22-pad1_ net-_u1-pad4_ d_inverter +* u25 net-_u25-pad1_ net-_u1-pad5_ d_inverter +* u28 net-_u28-pad1_ net-_u1-pad10_ d_inverter +* u30 net-_u30-pad1_ net-_u1-pad12_ d_inverter +* u31 net-_u31-pad1_ net-_u30-pad1_ d_inverter +* u32 net-_u21-pad2_ net-_u31-pad1_ d_inverter +* u20 net-_u12-pad2_ net-_u14-pad2_ net-_u17-pad2_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? net-_u1-pad7_ ? ? net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u12 net-_u1-pad14_ net-_u12-pad2_ d_inverter +a1 net-_u16-pad2_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u17-pad1_ net-_u13-pad2_ u7 +a2 net-_u17-pad1_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u11-pad1_ net-_u17-pad6_ u17 +a3 net-_u18-pad3_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u16-pad1_ net-_u11-pad2_ u23 +a4 net-_u16-pad1_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u21-pad2_ net-_u16-pad2_ u27 +a5 net-_u1-pad15_ net-_u2-pad2_ u2 +a6 net-_u2-pad2_ net-_u17-pad4_ u3 +a7 net-_u1-pad13_ net-_u14-pad1_ u9 +a8 net-_u14-pad1_ net-_u14-pad2_ u14 +a9 [net-_u11-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a10 [net-_u17-pad6_ net-_u13-pad3_ ] net-_u18-pad3_ u18 +a11 [net-_u16-pad2_ net-_u13-pad2_ ] net-_u4-pad1_ u5 +a12 [net-_u17-pad1_ net-_u17-pad6_ ] net-_u6-pad1_ u8 +a13 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad1_ u11 +a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u15-pad1_ u16 +a15 [net-_u17-pad1_ net-_u21-pad2_ ] net-_u19-pad1_ u21 +a16 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u22-pad1_ u24 +a17 [net-_u17-pad6_ net-_u16-pad1_ ] net-_u25-pad1_ u26 +a18 [net-_u11-pad2_ net-_u21-pad2_ ] net-_u28-pad1_ u29 +a19 net-_u4-pad1_ net-_u1-pad2_ u4 +a20 net-_u6-pad1_ net-_u1-pad1_ u6 +a21 net-_u10-pad1_ net-_u1-pad3_ u10 +a22 net-_u15-pad1_ net-_u1-pad7_ u15 +a23 net-_u19-pad1_ net-_u1-pad11_ u19 +a24 net-_u22-pad1_ net-_u1-pad4_ u22 +a25 net-_u25-pad1_ net-_u1-pad5_ u25 +a26 net-_u28-pad1_ net-_u1-pad10_ u28 +a27 net-_u30-pad1_ net-_u1-pad12_ u30 +a28 net-_u31-pad1_ net-_u30-pad1_ u31 +a29 net-_u21-pad2_ net-_u31-pad1_ u32 +a30 [net-_u12-pad2_ net-_u14-pad2_ ] net-_u17-pad2_ u20 +a31 net-_u1-pad14_ net-_u12-pad2_ u12 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u17 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u23 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u27 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4022B/SC_CD4022B.pro b/library/SubcircuitLibrary/CD4022B/SC_CD4022B.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CD4022B/SC_CD4022B.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4022B/SC_CD4022B.sch b/library/SubcircuitLibrary/CD4022B/SC_CD4022B.sch new file mode 100644 index 000000000..3992ea26a --- /dev/null +++ b/library/SubcircuitLibrary/CD4022B/SC_CD4022B.sch @@ -0,0 +1,743 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U7 +U 1 1 6848332B +P 3300 4150 +F 0 "U7" H 3300 4150 60 0000 C CNN +F 1 "d_dff" H 3300 4300 60 0000 C CNN +F 2 "" H 3300 4150 60 0000 C CNN +F 3 "" H 3300 4150 60 0000 C CNN + 1 3300 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U17 +U 1 1 68483390 +P 4800 4150 +F 0 "U17" H 4800 4150 60 0000 C CNN +F 1 "d_dff" H 4800 4300 60 0000 C CNN +F 2 "" H 4800 4150 60 0000 C CNN +F 3 "" H 4800 4150 60 0000 C CNN + 1 4800 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U23 +U 1 1 684833D7 +P 6350 4150 +F 0 "U23" H 6350 4150 60 0000 C CNN +F 1 "d_dff" H 6350 4300 60 0000 C CNN +F 2 "" H 6350 4150 60 0000 C CNN +F 3 "" H 6350 4150 60 0000 C CNN + 1 6350 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U27 +U 1 1 6848340C +P 7950 4150 +F 0 "U27" H 7950 4150 60 0000 C CNN +F 1 "d_dff" H 7950 4300 60 0000 C CNN +F 2 "" H 7950 4150 60 0000 C CNN +F 3 "" H 7950 4150 60 0000 C CNN + 1 7950 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68483465 +P 1600 5000 +F 0 "U2" H 1600 4900 60 0000 C CNN +F 1 "d_inverter" H 1600 5150 60 0000 C CNN +F 2 "" H 1650 4950 60 0000 C CNN +F 3 "" H 1650 4950 60 0000 C CNN + 1 1600 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 684834F0 +P 2300 5000 +F 0 "U3" H 2300 4900 60 0000 C CNN +F 1 "d_inverter" H 2300 5150 60 0000 C CNN +F 2 "" H 2350 4950 60 0000 C CNN +F 3 "" H 2350 4950 60 0000 C CNN + 1 2300 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 684835E3 +P 3550 6900 +F 0 "U9" H 3550 6800 60 0000 C CNN +F 1 "d_inverter" H 3550 7050 60 0000 C CNN +F 2 "" H 3600 6850 60 0000 C CNN +F 3 "" H 3600 6850 60 0000 C CNN + 1 3550 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 6848362E +P 4250 6900 +F 0 "U14" H 4250 6800 60 0000 C CNN +F 1 "d_inverter" H 4250 7050 60 0000 C CNN +F 2 "" H 4300 6850 60 0000 C CNN +F 3 "" H 4300 6850 60 0000 C CNN + 1 4250 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 6848368A +P 4200 5800 +F 0 "U13" H 4200 5800 60 0000 C CNN +F 1 "d_and" H 4250 5900 60 0000 C CNN +F 2 "" H 4200 5800 60 0000 C CNN +F 3 "" H 4200 5800 60 0000 C CNN + 1 4200 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U18 +U 1 1 6848371F +P 5100 5750 +F 0 "U18" H 5100 5750 60 0000 C CNN +F 1 "d_nor" H 5150 5850 60 0000 C CNN +F 2 "" H 5100 5750 60 0000 C CNN +F 3 "" H 5100 5750 60 0000 C CNN + 1 5100 5750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 68483777 +P 2600 2050 +F 0 "U5" H 2600 2050 60 0000 C CNN +F 1 "d_nand" H 2650 2150 60 0000 C CNN +F 2 "" H 2600 2050 60 0000 C CNN +F 3 "" H 2600 2050 60 0000 C CNN + 1 2600 2050 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U8 +U 1 1 684837BE +P 3350 2050 +F 0 "U8" H 3350 2050 60 0000 C CNN +F 1 "d_nand" H 3400 2150 60 0000 C CNN +F 2 "" H 3350 2050 60 0000 C CNN +F 3 "" H 3350 2050 60 0000 C CNN + 1 3350 2050 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U11 +U 1 1 68483807 +P 4050 2050 +F 0 "U11" H 4050 2050 60 0000 C CNN +F 1 "d_nand" H 4100 2150 60 0000 C CNN +F 2 "" H 4050 2050 60 0000 C CNN +F 3 "" H 4050 2050 60 0000 C CNN + 1 4050 2050 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U16 +U 1 1 6848386E +P 4800 2050 +F 0 "U16" H 4800 2050 60 0000 C CNN +F 1 "d_nand" H 4850 2150 60 0000 C CNN +F 2 "" H 4800 2050 60 0000 C CNN +F 3 "" H 4800 2050 60 0000 C CNN + 1 4800 2050 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U21 +U 1 1 684838C3 +P 5500 2050 +F 0 "U21" H 5500 2050 60 0000 C CNN +F 1 "d_nand" H 5550 2150 60 0000 C CNN +F 2 "" H 5500 2050 60 0000 C CNN +F 3 "" H 5500 2050 60 0000 C CNN + 1 5500 2050 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U24 +U 1 1 6848391E +P 6400 2050 +F 0 "U24" H 6400 2050 60 0000 C CNN +F 1 "d_nand" H 6450 2150 60 0000 C CNN +F 2 "" H 6400 2050 60 0000 C CNN +F 3 "" H 6400 2050 60 0000 C CNN + 1 6400 2050 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U26 +U 1 1 68483993 +P 7200 2050 +F 0 "U26" H 7200 2050 60 0000 C CNN +F 1 "d_nand" H 7250 2150 60 0000 C CNN +F 2 "" H 7200 2050 60 0000 C CNN +F 3 "" H 7200 2050 60 0000 C CNN + 1 7200 2050 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U29 +U 1 1 684839E8 +P 8150 2050 +F 0 "U29" H 8150 2050 60 0000 C CNN +F 1 "d_nand" H 8200 2150 60 0000 C CNN +F 2 "" H 8150 2050 60 0000 C CNN +F 3 "" H 8150 2050 60 0000 C CNN + 1 8150 2050 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68483B29 +P 2550 1300 +F 0 "U4" H 2550 1200 60 0000 C CNN +F 1 "d_inverter" H 2550 1450 60 0000 C CNN +F 2 "" H 2600 1250 60 0000 C CNN +F 3 "" H 2600 1250 60 0000 C CNN + 1 2550 1300 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68483BAA +P 3300 1300 +F 0 "U6" H 3300 1200 60 0000 C CNN +F 1 "d_inverter" H 3300 1450 60 0000 C CNN +F 2 "" H 3350 1250 60 0000 C CNN +F 3 "" H 3350 1250 60 0000 C CNN + 1 3300 1300 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U10 +U 1 1 68483C2B +P 4000 1300 +F 0 "U10" H 4000 1200 60 0000 C CNN +F 1 "d_inverter" H 4000 1450 60 0000 C CNN +F 2 "" H 4050 1250 60 0000 C CNN +F 3 "" H 4050 1250 60 0000 C CNN + 1 4000 1300 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U15 +U 1 1 68483C8A +P 4750 1300 +F 0 "U15" H 4750 1200 60 0000 C CNN +F 1 "d_inverter" H 4750 1450 60 0000 C CNN +F 2 "" H 4800 1250 60 0000 C CNN +F 3 "" H 4800 1250 60 0000 C CNN + 1 4750 1300 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U19 +U 1 1 68483CE9 +P 5450 1300 +F 0 "U19" H 5450 1200 60 0000 C CNN +F 1 "d_inverter" H 5450 1450 60 0000 C CNN +F 2 "" H 5500 1250 60 0000 C CNN +F 3 "" H 5500 1250 60 0000 C CNN + 1 5450 1300 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U22 +U 1 1 68483D50 +P 6350 1300 +F 0 "U22" H 6350 1200 60 0000 C CNN +F 1 "d_inverter" H 6350 1450 60 0000 C CNN +F 2 "" H 6400 1250 60 0000 C CNN +F 3 "" H 6400 1250 60 0000 C CNN + 1 6350 1300 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U25 +U 1 1 68483DDF +P 7150 1300 +F 0 "U25" H 7150 1200 60 0000 C CNN +F 1 "d_inverter" H 7150 1450 60 0000 C CNN +F 2 "" H 7200 1250 60 0000 C CNN +F 3 "" H 7200 1250 60 0000 C CNN + 1 7150 1300 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U28 +U 1 1 68483E68 +P 8100 1300 +F 0 "U28" H 8100 1200 60 0000 C CNN +F 1 "d_inverter" H 8100 1450 60 0000 C CNN +F 2 "" H 8150 1250 60 0000 C CNN +F 3 "" H 8150 1250 60 0000 C CNN + 1 8100 1300 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U30 +U 1 1 68483ED5 +P 9450 1200 +F 0 "U30" H 9450 1100 60 0000 C CNN +F 1 "d_inverter" H 9450 1350 60 0000 C CNN +F 2 "" H 9500 1150 60 0000 C CNN +F 3 "" H 9500 1150 60 0000 C CNN + 1 9450 1200 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U31 +U 1 1 68483F50 +P 9450 1950 +F 0 "U31" H 9450 1850 60 0000 C CNN +F 1 "d_inverter" H 9450 2100 60 0000 C CNN +F 2 "" H 9500 1900 60 0000 C CNN +F 3 "" H 9500 1900 60 0000 C CNN + 1 9450 1950 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U32 +U 1 1 68483FC1 +P 9450 2650 +F 0 "U32" H 9450 2550 60 0000 C CNN +F 1 "d_inverter" H 9450 2800 60 0000 C CNN +F 2 "" H 9500 2600 60 0000 C CNN +F 3 "" H 9500 2600 60 0000 C CNN + 1 9450 2650 + 0 -1 -1 0 +$EndComp +$Comp +L d_nor U20 +U 1 1 6848433F +P 5450 6650 +F 0 "U20" H 5450 6650 60 0000 C CNN +F 1 "d_nor" H 5500 6750 60 0000 C CNN +F 2 "" H 5450 6650 60 0000 C CNN +F 3 "" H 5450 6650 60 0000 C CNN + 1 5450 6650 + 1 0 0 -1 +$EndComp +NoConn ~ 3300 3500 +NoConn ~ 4800 3500 +NoConn ~ 6350 3500 +NoConn ~ 7950 3500 +Wire Wire Line + 1900 5000 2000 5000 +Wire Wire Line + 2600 5000 7950 5000 +Wire Wire Line + 3300 5000 3300 4750 +Wire Wire Line + 4800 5000 4800 4750 +Connection ~ 3300 5000 +Wire Wire Line + 6350 5000 6350 4750 +Connection ~ 4800 5000 +Wire Wire Line + 7950 5000 7950 4750 +Connection ~ 6350 5000 +Wire Wire Line + 4350 6400 5000 6400 +Wire Wire Line + 5000 6400 5000 6550 +Wire Wire Line + 5000 6650 5000 6900 +Wire Wire Line + 5000 6900 4550 6900 +Wire Wire Line + 3950 6900 3850 6900 +Wire Wire Line + 9450 1650 9450 1500 +Wire Wire Line + 9450 2350 9450 2250 +Wire Wire Line + 9450 2950 9450 3800 +Wire Wire Line + 9450 3800 8500 3800 +Wire Wire Line + 6900 3800 7400 3800 +Wire Wire Line + 4250 3800 3850 3800 +Wire Wire Line + 5800 3800 5650 3800 +Wire Wire Line + 5650 3800 5650 5700 +Wire Wire Line + 5650 5700 5550 5700 +Wire Wire Line + 3850 3200 3850 5250 +Wire Wire Line + 3850 5250 3500 5250 +Wire Wire Line + 3500 5250 3500 5800 +Wire Wire Line + 3500 5800 3750 5800 +Wire Wire Line + 2750 4450 2750 5150 +Wire Wire Line + 2750 5150 7400 5150 +Wire Wire Line + 4250 5150 4250 4450 +Wire Wire Line + 5800 5150 5800 4450 +Connection ~ 4250 5150 +Wire Wire Line + 7400 5150 7400 4450 +Connection ~ 5800 5150 +Wire Wire Line + 5900 6600 5900 5150 +Connection ~ 5900 5150 +Wire Wire Line + 2750 3800 2500 3800 +Wire Wire Line + 2500 3800 2500 2500 +Wire Wire Line + 8150 2500 8150 3100 +Wire Wire Line + 8150 3100 9450 3100 +Connection ~ 9450 3100 +Wire Wire Line + 2600 2500 2600 3200 +Wire Wire Line + 2600 3200 6300 3200 +Wire Wire Line + 6300 3200 6300 2500 +Connection ~ 3850 3200 +Connection ~ 3850 4450 +Wire Wire Line + 3250 2500 3250 3300 +Wire Wire Line + 3250 3300 5400 3300 +Wire Wire Line + 5400 3300 5400 2500 +Wire Wire Line + 4050 3800 4050 3300 +Connection ~ 4050 3300 +Connection ~ 4050 3800 +Wire Wire Line + 2500 2650 4800 2650 +Wire Wire Line + 4800 2500 4800 2950 +Connection ~ 2500 2650 +Wire Wire Line + 4800 2950 9050 2950 +Wire Wire Line + 9050 2950 9050 4450 +Wire Wire Line + 9050 4450 8500 4450 +Connection ~ 4800 2650 +Wire Wire Line + 4050 2500 4050 3100 +Wire Wire Line + 4050 2950 3950 2950 +Wire Wire Line + 3950 2950 3950 5450 +Wire Wire Line + 3950 5450 3750 5450 +Wire Wire Line + 3750 5450 3750 5700 +Wire Wire Line + 5350 4450 5350 5450 +Wire Wire Line + 5350 5450 4650 5450 +Wire Wire Line + 4650 5450 4650 5650 +Wire Wire Line + 3350 2500 3350 2850 +Wire Wire Line + 3350 2850 7100 2850 +Wire Wire Line + 7100 2850 7100 2500 +Wire Wire Line + 5350 4450 5500 4450 +Wire Wire Line + 5500 4450 5500 2850 +Connection ~ 5500 2850 +Wire Wire Line + 3950 2500 3950 2750 +Wire Wire Line + 3950 2750 6400 2750 +Wire Wire Line + 6400 2750 6400 2500 +Wire Wire Line + 5350 3800 5350 2750 +Connection ~ 5350 2750 +Wire Wire Line + 4700 2500 4700 3050 +Wire Wire Line + 4700 3050 7200 3050 +Wire Wire Line + 7200 2500 7200 3800 +Connection ~ 7200 3800 +Connection ~ 7200 3050 +Wire Wire Line + 4050 3100 8050 3100 +Wire Wire Line + 8050 3100 8050 2500 +Connection ~ 4050 2950 +Wire Wire Line + 6900 4450 6900 3100 +Connection ~ 6900 3100 +Wire Wire Line + 5500 2500 5500 2550 +Wire Wire Line + 5500 2550 8150 2550 +Connection ~ 8150 2550 +$Comp +L PORT U1 +U 1 1 684881B5 +P 3300 750 +F 0 "U1" H 3350 850 30 0000 C CNN +F 1 "PORT" H 3300 750 30 0000 C CNN +F 2 "" H 3300 750 60 0000 C CNN +F 3 "" H 3300 750 60 0000 C CNN + 1 3300 750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 684882DE +P 2550 750 +F 0 "U1" H 2600 850 30 0000 C CNN +F 1 "PORT" H 2550 750 30 0000 C CNN +F 2 "" H 2550 750 60 0000 C CNN +F 3 "" H 2550 750 60 0000 C CNN + 2 2550 750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 6848834F +P 4000 750 +F 0 "U1" H 4050 850 30 0000 C CNN +F 1 "PORT" H 4000 750 30 0000 C CNN +F 2 "" H 4000 750 60 0000 C CNN +F 3 "" H 4000 750 60 0000 C CNN + 3 4000 750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 684883C0 +P 6350 750 +F 0 "U1" H 6400 850 30 0000 C CNN +F 1 "PORT" H 6350 750 30 0000 C CNN +F 2 "" H 6350 750 60 0000 C CNN +F 3 "" H 6350 750 60 0000 C CNN + 4 6350 750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 6848844F +P 7150 750 +F 0 "U1" H 7200 850 30 0000 C CNN +F 1 "PORT" H 7150 750 30 0000 C CNN +F 2 "" H 7150 750 60 0000 C CNN +F 3 "" H 7150 750 60 0000 C CNN + 5 7150 750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 684884D8 +P 1100 900 +F 0 "U1" H 1150 1000 30 0000 C CNN +F 1 "PORT" H 1100 900 30 0000 C CNN +F 2 "" H 1100 900 60 0000 C CNN +F 3 "" H 1100 900 60 0000 C CNN + 6 1100 900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68488553 +P 4750 750 +F 0 "U1" H 4800 850 30 0000 C CNN +F 1 "PORT" H 4750 750 30 0000 C CNN +F 2 "" H 4750 750 60 0000 C CNN +F 3 "" H 4750 750 60 0000 C CNN + 7 4750 750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 684885EA +P 1100 1250 +F 0 "U1" H 1150 1350 30 0000 C CNN +F 1 "PORT" H 1100 1250 30 0000 C CNN +F 2 "" H 1100 1250 60 0000 C CNN +F 3 "" H 1100 1250 60 0000 C CNN + 8 1100 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68488671 +P 1100 1550 +F 0 "U1" H 1150 1650 30 0000 C CNN +F 1 "PORT" H 1100 1550 30 0000 C CNN +F 2 "" H 1100 1550 60 0000 C CNN +F 3 "" H 1100 1550 60 0000 C CNN + 9 1100 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68488710 +P 8100 750 +F 0 "U1" H 8150 850 30 0000 C CNN +F 1 "PORT" H 8100 750 30 0000 C CNN +F 2 "" H 8100 750 60 0000 C CNN +F 3 "" H 8100 750 60 0000 C CNN + 10 8100 750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 68488821 +P 5450 750 +F 0 "U1" H 5500 850 30 0000 C CNN +F 1 "PORT" H 5450 750 30 0000 C CNN +F 2 "" H 5450 750 60 0000 C CNN +F 3 "" H 5450 750 60 0000 C CNN + 11 5450 750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 68488904 +P 9450 650 +F 0 "U1" H 9500 750 30 0000 C CNN +F 1 "PORT" H 9450 650 30 0000 C CNN +F 2 "" H 9450 650 60 0000 C CNN +F 3 "" H 9450 650 60 0000 C CNN + 12 9450 650 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 684889EF +P 3000 6900 +F 0 "U1" H 3050 7000 30 0000 C CNN +F 1 "PORT" H 3000 6900 30 0000 C CNN +F 2 "" H 3000 6900 60 0000 C CNN +F 3 "" H 3000 6900 60 0000 C CNN + 13 3000 6900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 68488A94 +P 3500 6400 +F 0 "U1" H 3550 6500 30 0000 C CNN +F 1 "PORT" H 3500 6400 30 0000 C CNN +F 2 "" H 3500 6400 60 0000 C CNN +F 3 "" H 3500 6400 60 0000 C CNN + 14 3500 6400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 68488BD6 +P 1100 1850 +F 0 "U1" H 1150 1950 30 0000 C CNN +F 1 "PORT" H 1100 1850 30 0000 C CNN +F 2 "" H 1100 1850 60 0000 C CNN +F 3 "" H 1100 1850 60 0000 C CNN + 16 1100 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 68488CE5 +P 1050 5000 +F 0 "U1" H 1100 5100 30 0000 C CNN +F 1 "PORT" H 1050 5000 30 0000 C CNN +F 2 "" H 1050 5000 60 0000 C CNN +F 3 "" H 1050 5000 60 0000 C CNN + 15 1050 5000 + 1 0 0 -1 +$EndComp +NoConn ~ 1350 900 +NoConn ~ 1350 1250 +NoConn ~ 1350 1550 +NoConn ~ 1350 1850 +$Comp +L d_inverter U12 +U 1 1 6848CA5F +P 4050 6400 +F 0 "U12" H 4050 6300 60 0000 C CNN +F 1 "d_inverter" H 4050 6550 60 0000 C CNN +F 2 "" H 4100 6350 60 0000 C CNN +F 3 "" H 4100 6350 60 0000 C CNN + 1 4050 6400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4022B/SC_CD4022B.sub b/library/SubcircuitLibrary/CD4022B/SC_CD4022B.sub new file mode 100644 index 000000000..3e924847d --- /dev/null +++ b/library/SubcircuitLibrary/CD4022B/SC_CD4022B.sub @@ -0,0 +1,130 @@ +* Subcircuit SC_CD4022B +.subckt SC_CD4022B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? net-_u1-pad7_ ? ? net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_cd4022b\sc_cd4022b.cir +* u7 net-_u16-pad2_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u17-pad1_ net-_u13-pad2_ d_dff +* u17 net-_u17-pad1_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u11-pad1_ net-_u17-pad6_ d_dff +* u23 net-_u18-pad3_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u16-pad1_ net-_u11-pad2_ d_dff +* u27 net-_u16-pad1_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u21-pad2_ net-_u16-pad2_ d_dff +* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter +* u3 net-_u2-pad2_ net-_u17-pad4_ d_inverter +* u9 net-_u1-pad13_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u13 net-_u11-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u18 net-_u17-pad6_ net-_u13-pad3_ net-_u18-pad3_ d_nor +* u5 net-_u16-pad2_ net-_u13-pad2_ net-_u4-pad1_ d_nand +* u8 net-_u17-pad1_ net-_u17-pad6_ net-_u6-pad1_ d_nand +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad1_ d_nand +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u15-pad1_ d_nand +* u21 net-_u17-pad1_ net-_u21-pad2_ net-_u19-pad1_ d_nand +* u24 net-_u13-pad2_ net-_u11-pad1_ net-_u22-pad1_ d_nand +* u26 net-_u17-pad6_ net-_u16-pad1_ net-_u25-pad1_ d_nand +* u29 net-_u11-pad2_ net-_u21-pad2_ net-_u28-pad1_ d_nand +* u4 net-_u4-pad1_ net-_u1-pad2_ d_inverter +* u6 net-_u6-pad1_ net-_u1-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad3_ d_inverter +* u15 net-_u15-pad1_ net-_u1-pad7_ d_inverter +* u19 net-_u19-pad1_ net-_u1-pad11_ d_inverter +* u22 net-_u22-pad1_ net-_u1-pad4_ d_inverter +* u25 net-_u25-pad1_ net-_u1-pad5_ d_inverter +* u28 net-_u28-pad1_ net-_u1-pad10_ d_inverter +* u30 net-_u30-pad1_ net-_u1-pad12_ d_inverter +* u31 net-_u31-pad1_ net-_u30-pad1_ d_inverter +* u32 net-_u21-pad2_ net-_u31-pad1_ d_inverter +* u20 net-_u12-pad2_ net-_u14-pad2_ net-_u17-pad2_ d_nor +* u12 net-_u1-pad14_ net-_u12-pad2_ d_inverter +a1 net-_u16-pad2_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u17-pad1_ net-_u13-pad2_ u7 +a2 net-_u17-pad1_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u11-pad1_ net-_u17-pad6_ u17 +a3 net-_u18-pad3_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u16-pad1_ net-_u11-pad2_ u23 +a4 net-_u16-pad1_ net-_u17-pad2_ ? net-_u17-pad4_ net-_u21-pad2_ net-_u16-pad2_ u27 +a5 net-_u1-pad15_ net-_u2-pad2_ u2 +a6 net-_u2-pad2_ net-_u17-pad4_ u3 +a7 net-_u1-pad13_ net-_u14-pad1_ u9 +a8 net-_u14-pad1_ net-_u14-pad2_ u14 +a9 [net-_u11-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a10 [net-_u17-pad6_ net-_u13-pad3_ ] net-_u18-pad3_ u18 +a11 [net-_u16-pad2_ net-_u13-pad2_ ] net-_u4-pad1_ u5 +a12 [net-_u17-pad1_ net-_u17-pad6_ ] net-_u6-pad1_ u8 +a13 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad1_ u11 +a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u15-pad1_ u16 +a15 [net-_u17-pad1_ net-_u21-pad2_ ] net-_u19-pad1_ u21 +a16 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u22-pad1_ u24 +a17 [net-_u17-pad6_ net-_u16-pad1_ ] net-_u25-pad1_ u26 +a18 [net-_u11-pad2_ net-_u21-pad2_ ] net-_u28-pad1_ u29 +a19 net-_u4-pad1_ net-_u1-pad2_ u4 +a20 net-_u6-pad1_ net-_u1-pad1_ u6 +a21 net-_u10-pad1_ net-_u1-pad3_ u10 +a22 net-_u15-pad1_ net-_u1-pad7_ u15 +a23 net-_u19-pad1_ net-_u1-pad11_ u19 +a24 net-_u22-pad1_ net-_u1-pad4_ u22 +a25 net-_u25-pad1_ net-_u1-pad5_ u25 +a26 net-_u28-pad1_ net-_u1-pad10_ u28 +a27 net-_u30-pad1_ net-_u1-pad12_ u30 +a28 net-_u31-pad1_ net-_u30-pad1_ u31 +a29 net-_u21-pad2_ net-_u31-pad1_ u32 +a30 [net-_u12-pad2_ net-_u14-pad2_ ] net-_u17-pad2_ u20 +a31 net-_u1-pad14_ net-_u12-pad2_ u12 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u17 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u23 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u27 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_CD4022B \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4022B/SC_CD4022B_Previous_Values.xml b/library/SubcircuitLibrary/CD4022B/SC_CD4022B_Previous_Values.xml new file mode 100644 index 000000000..d98f87951 --- /dev/null +++ b/library/SubcircuitLibrary/CD4022B/SC_CD4022B_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsmsd_dffd_dffd_dffd_dffd_inverterd_inverterd_inverterd_inverterd_andd_nord_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_nord_inverter \ No newline at end of file From 49164adaf93d4f3e966f26974609bd66c5e97326 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:51:24 +0530 Subject: [PATCH 11/33] Quadruple D-Type Flip-Flop With Clear --- library/SubcircuitLibrary/SN74F175/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/SN74F175/analysis diff --git a/library/SubcircuitLibrary/SN74F175/analysis b/library/SubcircuitLibrary/SN74F175/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/SN74F175/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 7b34feef981255182d8c7cfb4e72aaac4aecccee Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:52:29 +0530 Subject: [PATCH 12/33] Quadruple D-Type Flip-Flop With Clear --- .../SN74F175/SC_SN74F175-cache.lib | 90 +++++ .../SN74F175/SC_SN74F175.cir | 17 + .../SN74F175/SC_SN74F175.cir.out | 36 ++ .../SN74F175/SC_SN74F175.pro | 73 ++++ .../SN74F175/SC_SN74F175.sch | 333 ++++++++++++++++++ .../SN74F175/SC_SN74F175.sub | 30 ++ .../SN74F175/SC_SN74F175_Previous_Values.xml | 1 + 7 files changed, 580 insertions(+) create mode 100644 library/SubcircuitLibrary/SN74F175/SC_SN74F175-cache.lib create mode 100644 library/SubcircuitLibrary/SN74F175/SC_SN74F175.cir create mode 100644 library/SubcircuitLibrary/SN74F175/SC_SN74F175.cir.out create mode 100644 library/SubcircuitLibrary/SN74F175/SC_SN74F175.pro create mode 100644 library/SubcircuitLibrary/SN74F175/SC_SN74F175.sch create mode 100644 library/SubcircuitLibrary/SN74F175/SC_SN74F175.sub create mode 100644 library/SubcircuitLibrary/SN74F175/SC_SN74F175_Previous_Values.xml diff --git a/library/SubcircuitLibrary/SN74F175/SC_SN74F175-cache.lib b/library/SubcircuitLibrary/SN74F175/SC_SN74F175-cache.lib new file mode 100644 index 000000000..1f98a2e03 --- /dev/null +++ b/library/SubcircuitLibrary/SN74F175/SC_SN74F175-cache.lib @@ -0,0 +1,90 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74F175/SC_SN74F175.cir b/library/SubcircuitLibrary/SN74F175/SC_SN74F175.cir new file mode 100644 index 000000000..2d0126f8e --- /dev/null +++ b/library/SubcircuitLibrary/SN74F175/SC_SN74F175.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_SN74F175\SC_SN74F175.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 16:46:53 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U1-Pad4_ Net-_U3-Pad2_ ? Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_dff +U5 Net-_U1-Pad5_ Net-_U3-Pad2_ ? Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U1-Pad6_ d_dff +U6 Net-_U1-Pad12_ Net-_U3-Pad2_ ? Net-_U2-Pad2_ Net-_U1-Pad10_ Net-_U1-Pad11_ d_dff +U7 Net-_U1-Pad13_ Net-_U3-Pad2_ ? Net-_U2-Pad2_ Net-_U1-Pad15_ Net-_U1-Pad14_ d_dff +U3 Net-_U1-Pad9_ Net-_U3-Pad2_ d_buffer +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74F175/SC_SN74F175.cir.out b/library/SubcircuitLibrary/SN74F175/SC_SN74F175.cir.out new file mode 100644 index 000000000..a1961e851 --- /dev/null +++ b/library/SubcircuitLibrary/SN74F175/SC_SN74F175.cir.out @@ -0,0 +1,36 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn74f175\sc_sn74f175.cir + +* u4 net-_u1-pad4_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad3_ d_dff +* u5 net-_u1-pad5_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad7_ net-_u1-pad6_ d_dff +* u6 net-_u1-pad12_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad10_ net-_u1-pad11_ d_dff +* u7 net-_u1-pad13_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad15_ net-_u1-pad14_ d_dff +* u3 net-_u1-pad9_ net-_u3-pad2_ d_buffer +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 net-_u1-pad4_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad3_ u4 +a2 net-_u1-pad5_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad7_ net-_u1-pad6_ u5 +a3 net-_u1-pad12_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad10_ net-_u1-pad11_ u6 +a4 net-_u1-pad13_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad15_ net-_u1-pad14_ u7 +a5 net-_u1-pad9_ net-_u3-pad2_ u3 +a6 net-_u1-pad1_ net-_u2-pad2_ u2 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74F175/SC_SN74F175.pro b/library/SubcircuitLibrary/SN74F175/SC_SN74F175.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74F175/SC_SN74F175.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74F175/SC_SN74F175.sch b/library/SubcircuitLibrary/SN74F175/SC_SN74F175.sch new file mode 100644 index 000000000..4cb4822d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74F175/SC_SN74F175.sch @@ -0,0 +1,333 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_SN74F175-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U4 +U 1 1 684AEE3D +P 5350 1500 +F 0 "U4" H 5350 1500 60 0000 C CNN +F 1 "d_dff" H 5350 1650 60 0000 C CNN +F 2 "" H 5350 1500 60 0000 C CNN +F 3 "" H 5350 1500 60 0000 C CNN + 1 5350 1500 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U5 +U 1 1 684AEE6E +P 5350 3250 +F 0 "U5" H 5350 3250 60 0000 C CNN +F 1 "d_dff" H 5350 3400 60 0000 C CNN +F 2 "" H 5350 3250 60 0000 C CNN +F 3 "" H 5350 3250 60 0000 C CNN + 1 5350 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U6 +U 1 1 684AEEAF +P 5350 4900 +F 0 "U6" H 5350 4900 60 0000 C CNN +F 1 "d_dff" H 5350 5050 60 0000 C CNN +F 2 "" H 5350 4900 60 0000 C CNN +F 3 "" H 5350 4900 60 0000 C CNN + 1 5350 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U7 +U 1 1 684AEEFA +P 5350 6450 +F 0 "U7" H 5350 6450 60 0000 C CNN +F 1 "d_dff" H 5350 6600 60 0000 C CNN +F 2 "" H 5350 6450 60 0000 C CNN +F 3 "" H 5350 6450 60 0000 C CNN + 1 5350 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U3 +U 1 1 684AF0FB +P 2750 1800 +F 0 "U3" H 2750 1750 60 0000 C CNN +F 1 "d_buffer" H 2750 1850 60 0000 C CNN +F 2 "" H 2750 1800 60 0000 C CNN +F 3 "" H 2750 1800 60 0000 C CNN + 1 2750 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 684AF204 +P 2550 2400 +F 0 "U2" H 2550 2300 60 0000 C CNN +F 1 "d_inverter" H 2550 2550 60 0000 C CNN +F 2 "" H 2600 2350 60 0000 C CNN +F 3 "" H 2600 2350 60 0000 C CNN + 1 2550 2400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 1800 4800 1800 +Wire Wire Line + 3900 1800 3900 6750 +Wire Wire Line + 3900 3550 4800 3550 +Connection ~ 3900 1800 +Wire Wire Line + 3900 5200 4800 5200 +Connection ~ 3900 3550 +Wire Wire Line + 3900 6750 4800 6750 +Connection ~ 3900 5200 +Wire Wire Line + 2850 2400 5350 2400 +Wire Wire Line + 5350 2400 5350 2100 +Wire Wire Line + 5350 3850 3350 3850 +Wire Wire Line + 3350 2400 3350 7050 +Connection ~ 3350 2400 +Wire Wire Line + 3350 5500 5350 5500 +Connection ~ 3350 3850 +Wire Wire Line + 3350 7050 5350 7050 +Connection ~ 3350 5500 +NoConn ~ 5350 850 +NoConn ~ 5350 2600 +NoConn ~ 5350 4250 +NoConn ~ 5350 5800 +$Comp +L PORT U1 +U 1 1 684AF899 +P 2000 2400 +F 0 "U1" H 2050 2500 30 0000 C CNN +F 1 "PORT" H 2000 2400 30 0000 C CNN +F 2 "" H 2000 2400 60 0000 C CNN +F 3 "" H 2000 2400 60 0000 C CNN + 1 2000 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 684AF90A +P 6150 1150 +F 0 "U1" H 6200 1250 30 0000 C CNN +F 1 "PORT" H 6150 1150 30 0000 C CNN +F 2 "" H 6150 1150 60 0000 C CNN +F 3 "" H 6150 1150 60 0000 C CNN + 2 6150 1150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 684AF971 +P 6150 1800 +F 0 "U1" H 6200 1900 30 0000 C CNN +F 1 "PORT" H 6150 1800 30 0000 C CNN +F 2 "" H 6150 1800 60 0000 C CNN +F 3 "" H 6150 1800 60 0000 C CNN + 3 6150 1800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 684AF9CA +P 4550 1150 +F 0 "U1" H 4600 1250 30 0000 C CNN +F 1 "PORT" H 4550 1150 30 0000 C CNN +F 2 "" H 4550 1150 60 0000 C CNN +F 3 "" H 4550 1150 60 0000 C CNN + 4 4550 1150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 684AFA3D +P 4550 2900 +F 0 "U1" H 4600 3000 30 0000 C CNN +F 1 "PORT" H 4550 2900 30 0000 C CNN +F 2 "" H 4550 2900 60 0000 C CNN +F 3 "" H 4550 2900 60 0000 C CNN + 5 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 684AFAA2 +P 6150 3550 +F 0 "U1" H 6200 3650 30 0000 C CNN +F 1 "PORT" H 6150 3550 30 0000 C CNN +F 2 "" H 6150 3550 60 0000 C CNN +F 3 "" H 6150 3550 60 0000 C CNN + 6 6150 3550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 684AFB0F +P 6150 2900 +F 0 "U1" H 6200 3000 30 0000 C CNN +F 1 "PORT" H 6150 2900 30 0000 C CNN +F 2 "" H 6150 2900 60 0000 C CNN +F 3 "" H 6150 2900 60 0000 C CNN + 7 6150 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 684AFB74 +P 2000 900 +F 0 "U1" H 2050 1000 30 0000 C CNN +F 1 "PORT" H 2000 900 30 0000 C CNN +F 2 "" H 2000 900 60 0000 C CNN +F 3 "" H 2000 900 60 0000 C CNN + 8 2000 900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 684AFF81 +P 2000 1800 +F 0 "U1" H 2050 1900 30 0000 C CNN +F 1 "PORT" H 2000 1800 30 0000 C CNN +F 2 "" H 2000 1800 60 0000 C CNN +F 3 "" H 2000 1800 60 0000 C CNN + 9 2000 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 684AFFF2 +P 6150 4550 +F 0 "U1" H 6200 4650 30 0000 C CNN +F 1 "PORT" H 6150 4550 30 0000 C CNN +F 2 "" H 6150 4550 60 0000 C CNN +F 3 "" H 6150 4550 60 0000 C CNN + 10 6150 4550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 684B0079 +P 6150 5200 +F 0 "U1" H 6200 5300 30 0000 C CNN +F 1 "PORT" H 6150 5200 30 0000 C CNN +F 2 "" H 6150 5200 60 0000 C CNN +F 3 "" H 6150 5200 60 0000 C CNN + 11 6150 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 684B00E4 +P 4550 4550 +F 0 "U1" H 4600 4650 30 0000 C CNN +F 1 "PORT" H 4550 4550 30 0000 C CNN +F 2 "" H 4550 4550 60 0000 C CNN +F 3 "" H 4550 4550 60 0000 C CNN + 12 4550 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 684B016D +P 4550 6100 +F 0 "U1" H 4600 6200 30 0000 C CNN +F 1 "PORT" H 4550 6100 30 0000 C CNN +F 2 "" H 4550 6100 60 0000 C CNN +F 3 "" H 4550 6100 60 0000 C CNN + 13 4550 6100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 684B01EA +P 6150 6750 +F 0 "U1" H 6200 6850 30 0000 C CNN +F 1 "PORT" H 6150 6750 30 0000 C CNN +F 2 "" H 6150 6750 60 0000 C CNN +F 3 "" H 6150 6750 60 0000 C CNN + 14 6150 6750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 684B028B +P 6150 6100 +F 0 "U1" H 6200 6200 30 0000 C CNN +F 1 "PORT" H 6150 6100 30 0000 C CNN +F 2 "" H 6150 6100 60 0000 C CNN +F 3 "" H 6150 6100 60 0000 C CNN + 15 6150 6100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 684B030D +P 2000 1150 +F 0 "U1" H 2050 1250 30 0000 C CNN +F 1 "PORT" H 2000 1150 30 0000 C CNN +F 2 "" H 2000 1150 60 0000 C CNN +F 3 "" H 2000 1150 60 0000 C CNN + 16 2000 1150 + 1 0 0 -1 +$EndComp +NoConn ~ 2250 900 +NoConn ~ 2250 1150 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74F175/SC_SN74F175.sub b/library/SubcircuitLibrary/SN74F175/SC_SN74F175.sub new file mode 100644 index 000000000..e15ab5364 --- /dev/null +++ b/library/SubcircuitLibrary/SN74F175/SC_SN74F175.sub @@ -0,0 +1,30 @@ +* Subcircuit SC_SN74F175 +.subckt SC_SN74F175 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn74f175\sc_sn74f175.cir +* u4 net-_u1-pad4_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad3_ d_dff +* u5 net-_u1-pad5_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad7_ net-_u1-pad6_ d_dff +* u6 net-_u1-pad12_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad10_ net-_u1-pad11_ d_dff +* u7 net-_u1-pad13_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad15_ net-_u1-pad14_ d_dff +* u3 net-_u1-pad9_ net-_u3-pad2_ d_buffer +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +a1 net-_u1-pad4_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad3_ u4 +a2 net-_u1-pad5_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad7_ net-_u1-pad6_ u5 +a3 net-_u1-pad12_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad10_ net-_u1-pad11_ u6 +a4 net-_u1-pad13_ net-_u3-pad2_ ? net-_u2-pad2_ net-_u1-pad15_ net-_u1-pad14_ u7 +a5 net-_u1-pad9_ net-_u3-pad2_ u3 +a6 net-_u1-pad1_ net-_u2-pad2_ u2 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_SN74F175 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74F175/SC_SN74F175_Previous_Values.xml b/library/SubcircuitLibrary/SN74F175/SC_SN74F175_Previous_Values.xml new file mode 100644 index 000000000..b2ec89422 --- /dev/null +++ b/library/SubcircuitLibrary/SN74F175/SC_SN74F175_Previous_Values.xml @@ -0,0 +1 @@ +d_dffd_dffd_dffd_dffd_bufferd_inverterd_bufferd_bufferd_bufferd_bufferd_inverterd_inverterd_inverterd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file From b70e91f01db47bab9778b596f74ceccb569bcc80 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:54:16 +0530 Subject: [PATCH 13/33] 4-By-4 Register Files With 3-State Outputs --- library/SubcircuitLibrary/SN74LS670/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/SN74LS670/analysis diff --git a/library/SubcircuitLibrary/SN74LS670/analysis b/library/SubcircuitLibrary/SN74LS670/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS670/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 6beaa9cf14eb9de1aac4749451766fc0d35828b4 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:56:46 +0530 Subject: [PATCH 14/33] 4-By-4 Register Files With 3-State Outputs --- .../SN74LS670/SC_SN74LS670-cache.lib | 151 ++ .../SN74LS670/SC_SN74LS670.cir | 86 + .../SN74LS670/SC_SN74LS670.cir.out | 254 +++ .../SN74LS670/SC_SN74LS670.pro | 73 + .../SN74LS670/SC_SN74LS670.sch | 1660 +++++++++++++++++ .../SN74LS670/SC_SN74LS670.sub | 248 +++ .../SC_SN74LS670_Previous_Values.xml | 1 + 7 files changed, 2473 insertions(+) create mode 100644 library/SubcircuitLibrary/SN74LS670/SC_SN74LS670-cache.lib create mode 100644 library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.cir create mode 100644 library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.cir.out create mode 100644 library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.pro create mode 100644 library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.sch create mode 100644 library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.sub create mode 100644 library/SubcircuitLibrary/SN74LS670/SC_SN74LS670_Previous_Values.xml diff --git a/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670-cache.lib b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670-cache.lib new file mode 100644 index 000000000..a904d0454 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670-cache.lib @@ -0,0 +1,151 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dlatch +# +DEF d_dlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dlatch" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X EN 2 -550 -300 200 R 50 50 1 1 I +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.cir b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.cir new file mode 100644 index 000000000..f326f47cd --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.cir @@ -0,0 +1,86 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_SN74LS670\SC_SN74LS670.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/13/25 13:57:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U18 Net-_U18-Pad1_ Net-_U12-Pad3_ ? ? Net-_U18-Pad5_ ? d_dlatch +U26 Net-_U18-Pad1_ Net-_U22-Pad3_ ? ? Net-_U26-Pad5_ ? d_dlatch +U34 Net-_U18-Pad1_ Net-_U30-Pad3_ ? ? Net-_U34-Pad5_ ? d_dlatch +U42 Net-_U18-Pad1_ Net-_U38-Pad3_ ? ? Net-_U42-Pad5_ ? d_dlatch +U12 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad3_ d_and +U22 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U22-Pad3_ d_and +U30 Net-_U28-Pad1_ Net-_U10-Pad2_ Net-_U30-Pad3_ d_and +U38 Net-_U28-Pad1_ Net-_U14-Pad2_ Net-_U38-Pad3_ d_and +U6 Net-_U1-Pad15_ Net-_U18-Pad1_ d_inverter +X19 Net-_X11-Pad4_ Net-_X12-Pad4_ Net-_X19-Pad3_ Net-_X19-Pad4_ Net-_U51-Pad1_ 4_OR +U51 Net-_U51-Pad1_ Net-_U51-Pad2_ d_inverter +U55 Net-_U51-Pad2_ Net-_U48-Pad2_ Net-_U1-Pad10_ d_and +U19 Net-_U19-Pad1_ Net-_U13-Pad3_ ? ? Net-_U19-Pad5_ ? d_dlatch +U27 Net-_U19-Pad1_ Net-_U23-Pad3_ ? ? Net-_U27-Pad5_ ? d_dlatch +U35 Net-_U19-Pad1_ Net-_U31-Pad3_ ? ? Net-_U35-Pad5_ ? d_dlatch +U43 Net-_U19-Pad1_ Net-_U39-Pad3_ ? ? Net-_U43-Pad5_ ? d_dlatch +U13 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U13-Pad3_ d_and +U23 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U23-Pad3_ d_and +U31 Net-_U28-Pad1_ Net-_U10-Pad2_ Net-_U31-Pad3_ d_and +U39 Net-_U28-Pad1_ Net-_U14-Pad2_ Net-_U39-Pad3_ d_and +U4 Net-_U1-Pad1_ Net-_U19-Pad1_ d_inverter +X20 Net-_X15-Pad4_ Net-_X16-Pad4_ Net-_X13-Pad4_ Net-_X14-Pad4_ Net-_U52-Pad1_ 4_OR +U52 Net-_U52-Pad1_ Net-_U52-Pad2_ d_inverter +U56 Net-_U52-Pad2_ Net-_U48-Pad2_ Net-_U1-Pad9_ d_and +U17 Net-_U17-Pad1_ Net-_U11-Pad3_ ? ? Net-_U17-Pad5_ ? d_dlatch +U25 Net-_U17-Pad1_ Net-_U21-Pad3_ ? ? Net-_U25-Pad5_ ? d_dlatch +U33 Net-_U17-Pad1_ Net-_U29-Pad3_ ? ? Net-_U33-Pad5_ ? d_dlatch +U41 Net-_U17-Pad1_ Net-_U37-Pad3_ ? ? Net-_U41-Pad5_ ? d_dlatch +U11 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_and +U21 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U21-Pad3_ d_and +U29 Net-_U28-Pad1_ Net-_U10-Pad2_ Net-_U29-Pad3_ d_and +U37 Net-_U28-Pad1_ Net-_U14-Pad2_ Net-_U37-Pad3_ d_and +U3 Net-_U1-Pad2_ Net-_U17-Pad1_ d_inverter +X18 Net-_X18-Pad1_ Net-_X10-Pad4_ Net-_X18-Pad3_ Net-_X18-Pad4_ Net-_U50-Pad1_ 4_OR +U50 Net-_U50-Pad1_ Net-_U50-Pad2_ d_inverter +U54 Net-_U50-Pad2_ Net-_U48-Pad2_ Net-_U1-Pad7_ d_and +U16 Net-_U16-Pad1_ Net-_U10-Pad3_ ? ? Net-_U16-Pad5_ ? d_dlatch +U24 Net-_U16-Pad1_ Net-_U20-Pad3_ ? ? Net-_U24-Pad5_ ? d_dlatch +U32 Net-_U16-Pad1_ Net-_U28-Pad3_ ? ? Net-_U32-Pad5_ ? d_dlatch +U40 Net-_U16-Pad1_ Net-_U36-Pad3_ ? ? Net-_U40-Pad5_ ? d_dlatch +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U20 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U20-Pad3_ d_and +U28 Net-_U28-Pad1_ Net-_U10-Pad2_ Net-_U28-Pad3_ d_and +U36 Net-_U28-Pad1_ Net-_U14-Pad2_ Net-_U36-Pad3_ d_and +U2 Net-_U1-Pad3_ Net-_U16-Pad1_ d_inverter +X17 Net-_X17-Pad1_ Net-_X17-Pad2_ Net-_X1-Pad4_ Net-_X17-Pad4_ Net-_U49-Pad1_ 4_OR +U49 Net-_U49-Pad1_ Net-_U49-Pad2_ d_inverter +U53 Net-_U49-Pad2_ Net-_U48-Pad2_ Net-_U1-Pad6_ d_and +U5 Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U28-Pad1_ d_nor +U8 Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad1_ d_and +U7 Net-_U1-Pad12_ Net-_U7-Pad2_ d_inverter +U9 Net-_U1-Pad13_ Net-_U5-Pad2_ d_inverter +U14 Net-_U10-Pad2_ Net-_U14-Pad2_ d_inverter +U15 Net-_U1-Pad14_ Net-_U10-Pad2_ d_inverter +U46 Net-_U46-Pad1_ Net-_U46-Pad2_ Net-_U46-Pad3_ d_nor +U47 Net-_U46-Pad1_ Net-_U1-Pad5_ Net-_U46-Pad2_ d_nor +U48 Net-_U46-Pad1_ Net-_U48-Pad2_ d_inverter +U44 Net-_U44-Pad1_ Net-_U44-Pad2_ d_inverter +U45 Net-_U1-Pad4_ Net-_U44-Pad1_ d_inverter +X6 Net-_U24-Pad5_ Net-_U44-Pad1_ Net-_U46-Pad3_ Net-_X17-Pad2_ 3_and +X1 Net-_U32-Pad5_ Net-_U44-Pad2_ Net-_U46-Pad2_ Net-_X1-Pad4_ 3_and +X2 Net-_U40-Pad5_ Net-_U44-Pad2_ Net-_U46-Pad3_ Net-_X17-Pad4_ 3_and +X5 Net-_U16-Pad5_ Net-_U44-Pad1_ Net-_U46-Pad2_ Net-_X17-Pad1_ 3_and +X9 Net-_U17-Pad5_ Net-_U44-Pad1_ Net-_U46-Pad2_ Net-_X18-Pad1_ 3_and +X10 Net-_U25-Pad5_ Net-_U44-Pad1_ Net-_U46-Pad3_ Net-_X10-Pad4_ 3_and +X3 Net-_U33-Pad5_ Net-_U44-Pad2_ Net-_U46-Pad2_ Net-_X18-Pad3_ 3_and +X4 Net-_U41-Pad5_ Net-_U44-Pad2_ Net-_U46-Pad3_ Net-_X18-Pad4_ 3_and +X15 Net-_U19-Pad5_ Net-_U44-Pad1_ Net-_U46-Pad2_ Net-_X15-Pad4_ 3_and +X16 Net-_U27-Pad5_ Net-_U44-Pad1_ Net-_U46-Pad3_ Net-_X16-Pad4_ 3_and +X13 Net-_U35-Pad5_ Net-_U44-Pad2_ Net-_U46-Pad2_ Net-_X13-Pad4_ 3_and +X14 Net-_U43-Pad5_ Net-_U44-Pad2_ Net-_U46-Pad3_ Net-_X14-Pad4_ 3_and +X11 Net-_U18-Pad5_ Net-_U44-Pad1_ Net-_U46-Pad2_ Net-_X11-Pad4_ 3_and +X12 Net-_U26-Pad5_ Net-_U44-Pad1_ Net-_U46-Pad3_ Net-_X12-Pad4_ 3_and +X7 Net-_U34-Pad5_ Net-_U44-Pad2_ Net-_U46-Pad2_ Net-_X19-Pad3_ 3_and +X8 Net-_U42-Pad5_ Net-_U44-Pad2_ Net-_U46-Pad3_ Net-_X19-Pad4_ 3_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ ? Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.cir.out b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.cir.out new file mode 100644 index 000000000..9b226e276 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.cir.out @@ -0,0 +1,254 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn74ls670\sc_sn74ls670.cir + +.include 3_and.sub +.include 4_OR.sub +* u18 net-_u18-pad1_ net-_u12-pad3_ ? ? net-_u18-pad5_ ? d_dlatch +* u26 net-_u18-pad1_ net-_u22-pad3_ ? ? net-_u26-pad5_ ? d_dlatch +* u34 net-_u18-pad1_ net-_u30-pad3_ ? ? net-_u34-pad5_ ? d_dlatch +* u42 net-_u18-pad1_ net-_u38-pad3_ ? ? net-_u42-pad5_ ? d_dlatch +* u12 net-_u10-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u22 net-_u10-pad1_ net-_u14-pad2_ net-_u22-pad3_ d_and +* u30 net-_u28-pad1_ net-_u10-pad2_ net-_u30-pad3_ d_and +* u38 net-_u28-pad1_ net-_u14-pad2_ net-_u38-pad3_ d_and +* u6 net-_u1-pad15_ net-_u18-pad1_ d_inverter +x19 net-_x11-pad4_ net-_x12-pad4_ net-_x19-pad3_ net-_x19-pad4_ net-_u51-pad1_ 4_OR +* u51 net-_u51-pad1_ net-_u51-pad2_ d_inverter +* u55 net-_u51-pad2_ net-_u48-pad2_ net-_u1-pad10_ d_and +* u19 net-_u19-pad1_ net-_u13-pad3_ ? ? net-_u19-pad5_ ? d_dlatch +* u27 net-_u19-pad1_ net-_u23-pad3_ ? ? net-_u27-pad5_ ? d_dlatch +* u35 net-_u19-pad1_ net-_u31-pad3_ ? ? net-_u35-pad5_ ? d_dlatch +* u43 net-_u19-pad1_ net-_u39-pad3_ ? ? net-_u43-pad5_ ? d_dlatch +* u13 net-_u10-pad1_ net-_u10-pad2_ net-_u13-pad3_ d_and +* u23 net-_u10-pad1_ net-_u14-pad2_ net-_u23-pad3_ d_and +* u31 net-_u28-pad1_ net-_u10-pad2_ net-_u31-pad3_ d_and +* u39 net-_u28-pad1_ net-_u14-pad2_ net-_u39-pad3_ d_and +* u4 net-_u1-pad1_ net-_u19-pad1_ d_inverter +x20 net-_x15-pad4_ net-_x16-pad4_ net-_x13-pad4_ net-_x14-pad4_ net-_u52-pad1_ 4_OR +* u52 net-_u52-pad1_ net-_u52-pad2_ d_inverter +* u56 net-_u52-pad2_ net-_u48-pad2_ net-_u1-pad9_ d_and +* u17 net-_u17-pad1_ net-_u11-pad3_ ? ? net-_u17-pad5_ ? d_dlatch +* u25 net-_u17-pad1_ net-_u21-pad3_ ? ? net-_u25-pad5_ ? d_dlatch +* u33 net-_u17-pad1_ net-_u29-pad3_ ? ? net-_u33-pad5_ ? d_dlatch +* u41 net-_u17-pad1_ net-_u37-pad3_ ? ? net-_u41-pad5_ ? d_dlatch +* u11 net-_u10-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u21 net-_u10-pad1_ net-_u14-pad2_ net-_u21-pad3_ d_and +* u29 net-_u28-pad1_ net-_u10-pad2_ net-_u29-pad3_ d_and +* u37 net-_u28-pad1_ net-_u14-pad2_ net-_u37-pad3_ d_and +* u3 net-_u1-pad2_ net-_u17-pad1_ d_inverter +x18 net-_x18-pad1_ net-_x10-pad4_ net-_x18-pad3_ net-_x18-pad4_ net-_u50-pad1_ 4_OR +* u50 net-_u50-pad1_ net-_u50-pad2_ d_inverter +* u54 net-_u50-pad2_ net-_u48-pad2_ net-_u1-pad7_ d_and +* u16 net-_u16-pad1_ net-_u10-pad3_ ? ? net-_u16-pad5_ ? d_dlatch +* u24 net-_u16-pad1_ net-_u20-pad3_ ? ? net-_u24-pad5_ ? d_dlatch +* u32 net-_u16-pad1_ net-_u28-pad3_ ? ? net-_u32-pad5_ ? d_dlatch +* u40 net-_u16-pad1_ net-_u36-pad3_ ? ? net-_u40-pad5_ ? d_dlatch +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u20 net-_u10-pad1_ net-_u14-pad2_ net-_u20-pad3_ d_and +* u28 net-_u28-pad1_ net-_u10-pad2_ net-_u28-pad3_ d_and +* u36 net-_u28-pad1_ net-_u14-pad2_ net-_u36-pad3_ d_and +* u2 net-_u1-pad3_ net-_u16-pad1_ d_inverter +x17 net-_x17-pad1_ net-_x17-pad2_ net-_x1-pad4_ net-_x17-pad4_ net-_u49-pad1_ 4_OR +* u49 net-_u49-pad1_ net-_u49-pad2_ d_inverter +* u53 net-_u49-pad2_ net-_u48-pad2_ net-_u1-pad6_ d_and +* u5 net-_u1-pad12_ net-_u5-pad2_ net-_u28-pad1_ d_nor +* u8 net-_u7-pad2_ net-_u5-pad2_ net-_u10-pad1_ d_and +* u7 net-_u1-pad12_ net-_u7-pad2_ d_inverter +* u9 net-_u1-pad13_ net-_u5-pad2_ d_inverter +* u14 net-_u10-pad2_ net-_u14-pad2_ d_inverter +* u15 net-_u1-pad14_ net-_u10-pad2_ d_inverter +* u46 net-_u46-pad1_ net-_u46-pad2_ net-_u46-pad3_ d_nor +* u47 net-_u46-pad1_ net-_u1-pad5_ net-_u46-pad2_ d_nor +* u48 net-_u46-pad1_ net-_u48-pad2_ d_inverter +* u44 net-_u44-pad1_ net-_u44-pad2_ d_inverter +* u45 net-_u1-pad4_ net-_u44-pad1_ d_inverter +x6 net-_u24-pad5_ net-_u44-pad1_ net-_u46-pad3_ net-_x17-pad2_ 3_and +x1 net-_u32-pad5_ net-_u44-pad2_ net-_u46-pad2_ net-_x1-pad4_ 3_and +x2 net-_u40-pad5_ net-_u44-pad2_ net-_u46-pad3_ net-_x17-pad4_ 3_and +x5 net-_u16-pad5_ net-_u44-pad1_ net-_u46-pad2_ net-_x17-pad1_ 3_and +x9 net-_u17-pad5_ net-_u44-pad1_ net-_u46-pad2_ net-_x18-pad1_ 3_and +x10 net-_u25-pad5_ net-_u44-pad1_ net-_u46-pad3_ net-_x10-pad4_ 3_and +x3 net-_u33-pad5_ net-_u44-pad2_ net-_u46-pad2_ net-_x18-pad3_ 3_and +x4 net-_u41-pad5_ net-_u44-pad2_ net-_u46-pad3_ net-_x18-pad4_ 3_and +x15 net-_u19-pad5_ net-_u44-pad1_ net-_u46-pad2_ net-_x15-pad4_ 3_and +x16 net-_u27-pad5_ net-_u44-pad1_ net-_u46-pad3_ net-_x16-pad4_ 3_and +x13 net-_u35-pad5_ net-_u44-pad2_ net-_u46-pad2_ net-_x13-pad4_ 3_and +x14 net-_u43-pad5_ net-_u44-pad2_ net-_u46-pad3_ net-_x14-pad4_ 3_and +x11 net-_u18-pad5_ net-_u44-pad1_ net-_u46-pad2_ net-_x11-pad4_ 3_and +x12 net-_u26-pad5_ net-_u44-pad1_ net-_u46-pad3_ net-_x12-pad4_ 3_and +x7 net-_u34-pad5_ net-_u44-pad2_ net-_u46-pad2_ net-_x19-pad3_ 3_and +x8 net-_u42-pad5_ net-_u44-pad2_ net-_u46-pad3_ net-_x19-pad4_ 3_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ ? net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 net-_u18-pad1_ net-_u12-pad3_ ? ? net-_u18-pad5_ ? u18 +a2 net-_u18-pad1_ net-_u22-pad3_ ? ? net-_u26-pad5_ ? u26 +a3 net-_u18-pad1_ net-_u30-pad3_ ? ? net-_u34-pad5_ ? u34 +a4 net-_u18-pad1_ net-_u38-pad3_ ? ? net-_u42-pad5_ ? u42 +a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u10-pad1_ net-_u14-pad2_ ] net-_u22-pad3_ u22 +a7 [net-_u28-pad1_ net-_u10-pad2_ ] net-_u30-pad3_ u30 +a8 [net-_u28-pad1_ net-_u14-pad2_ ] net-_u38-pad3_ u38 +a9 net-_u1-pad15_ net-_u18-pad1_ u6 +a10 net-_u51-pad1_ net-_u51-pad2_ u51 +a11 [net-_u51-pad2_ net-_u48-pad2_ ] net-_u1-pad10_ u55 +a12 net-_u19-pad1_ net-_u13-pad3_ ? ? net-_u19-pad5_ ? u19 +a13 net-_u19-pad1_ net-_u23-pad3_ ? ? net-_u27-pad5_ ? u27 +a14 net-_u19-pad1_ net-_u31-pad3_ ? ? net-_u35-pad5_ ? u35 +a15 net-_u19-pad1_ net-_u39-pad3_ ? ? net-_u43-pad5_ ? u43 +a16 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u13-pad3_ u13 +a17 [net-_u10-pad1_ net-_u14-pad2_ ] net-_u23-pad3_ u23 +a18 [net-_u28-pad1_ net-_u10-pad2_ ] net-_u31-pad3_ u31 +a19 [net-_u28-pad1_ net-_u14-pad2_ ] net-_u39-pad3_ u39 +a20 net-_u1-pad1_ net-_u19-pad1_ u4 +a21 net-_u52-pad1_ net-_u52-pad2_ u52 +a22 [net-_u52-pad2_ net-_u48-pad2_ ] net-_u1-pad9_ u56 +a23 net-_u17-pad1_ net-_u11-pad3_ ? ? net-_u17-pad5_ ? u17 +a24 net-_u17-pad1_ net-_u21-pad3_ ? ? net-_u25-pad5_ ? u25 +a25 net-_u17-pad1_ net-_u29-pad3_ ? ? net-_u33-pad5_ ? u33 +a26 net-_u17-pad1_ net-_u37-pad3_ ? ? net-_u41-pad5_ ? u41 +a27 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a28 [net-_u10-pad1_ net-_u14-pad2_ ] net-_u21-pad3_ u21 +a29 [net-_u28-pad1_ net-_u10-pad2_ ] net-_u29-pad3_ u29 +a30 [net-_u28-pad1_ net-_u14-pad2_ ] net-_u37-pad3_ u37 +a31 net-_u1-pad2_ net-_u17-pad1_ u3 +a32 net-_u50-pad1_ net-_u50-pad2_ u50 +a33 [net-_u50-pad2_ net-_u48-pad2_ ] net-_u1-pad7_ u54 +a34 net-_u16-pad1_ net-_u10-pad3_ ? ? net-_u16-pad5_ ? u16 +a35 net-_u16-pad1_ net-_u20-pad3_ ? ? net-_u24-pad5_ ? u24 +a36 net-_u16-pad1_ net-_u28-pad3_ ? ? net-_u32-pad5_ ? u32 +a37 net-_u16-pad1_ net-_u36-pad3_ ? ? net-_u40-pad5_ ? u40 +a38 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a39 [net-_u10-pad1_ net-_u14-pad2_ ] net-_u20-pad3_ u20 +a40 [net-_u28-pad1_ net-_u10-pad2_ ] net-_u28-pad3_ u28 +a41 [net-_u28-pad1_ net-_u14-pad2_ ] net-_u36-pad3_ u36 +a42 net-_u1-pad3_ net-_u16-pad1_ u2 +a43 net-_u49-pad1_ net-_u49-pad2_ u49 +a44 [net-_u49-pad2_ net-_u48-pad2_ ] net-_u1-pad6_ u53 +a45 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u28-pad1_ u5 +a46 [net-_u7-pad2_ net-_u5-pad2_ ] net-_u10-pad1_ u8 +a47 net-_u1-pad12_ net-_u7-pad2_ u7 +a48 net-_u1-pad13_ net-_u5-pad2_ u9 +a49 net-_u10-pad2_ net-_u14-pad2_ u14 +a50 net-_u1-pad14_ net-_u10-pad2_ u15 +a51 [net-_u46-pad1_ net-_u46-pad2_ ] net-_u46-pad3_ u46 +a52 [net-_u46-pad1_ net-_u1-pad5_ ] net-_u46-pad2_ u47 +a53 net-_u46-pad1_ net-_u48-pad2_ u48 +a54 net-_u44-pad1_ net-_u44-pad2_ u44 +a55 net-_u1-pad4_ net-_u44-pad1_ u45 +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u18 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u26 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u34 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u42 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u19 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u27 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u35 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u43 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u17 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u25 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u33 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u41 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u16 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u24 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u32 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u40 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.pro b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.sch b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.sch new file mode 100644 index 000000000..39ddabee0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.sch @@ -0,0 +1,1660 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_SN74LS670-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dlatch U? +U 1 1 684B171A +P 4650 3250 +F 0 "U?" H 4650 3250 60 0000 C CNN +F 1 "d_dlatch" H 4650 3400 60 0000 C CNN +F 2 "" H 4650 3250 60 0000 C CNN +F 3 "" H 4650 3250 60 0000 C CNN + 1 4650 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B17AF +P 6850 3250 +F 0 "U?" H 6850 3250 60 0000 C CNN +F 1 "d_dlatch" H 6850 3400 60 0000 C CNN +F 2 "" H 6850 3250 60 0000 C CNN +F 3 "" H 6850 3250 60 0000 C CNN + 1 6850 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B17F8 +P 9050 3250 +F 0 "U?" H 9050 3250 60 0000 C CNN +F 1 "d_dlatch" H 9050 3400 60 0000 C CNN +F 2 "" H 9050 3250 60 0000 C CNN +F 3 "" H 9050 3250 60 0000 C CNN + 1 9050 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B183B +P 11300 3250 +F 0 "U?" H 11300 3250 60 0000 C CNN +F 1 "d_dlatch" H 11300 3400 60 0000 C CNN +F 2 "" H 11300 3250 60 0000 C CNN +F 3 "" H 11300 3250 60 0000 C CNN + 1 11300 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B18BC +P 3650 3600 +F 0 "U?" H 3650 3600 60 0000 C CNN +F 1 "d_and" H 3700 3700 60 0000 C CNN +F 2 "" H 3650 3600 60 0000 C CNN +F 3 "" H 3650 3600 60 0000 C CNN + 1 3650 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B192E +P 5850 3600 +F 0 "U?" H 5850 3600 60 0000 C CNN +F 1 "d_and" H 5900 3700 60 0000 C CNN +F 2 "" H 5850 3600 60 0000 C CNN +F 3 "" H 5850 3600 60 0000 C CNN + 1 5850 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B198B +P 8050 3600 +F 0 "U?" H 8050 3600 60 0000 C CNN +F 1 "d_and" H 8100 3700 60 0000 C CNN +F 2 "" H 8050 3600 60 0000 C CNN +F 3 "" H 8050 3600 60 0000 C CNN + 1 8050 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B1A02 +P 10300 3600 +F 0 "U?" H 10300 3600 60 0000 C CNN +F 1 "d_and" H 10350 3700 60 0000 C CNN +F 2 "" H 10300 3600 60 0000 C CNN +F 3 "" H 10300 3600 60 0000 C CNN + 1 10300 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 684B1ABF +P 2750 2550 +F 0 "U?" H 2750 2450 60 0000 C CNN +F 1 "d_inverter" H 2750 2700 60 0000 C CNN +F 2 "" H 2800 2500 60 0000 C CNN +F 3 "" H 2800 2500 60 0000 C CNN + 1 2750 2550 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X? +U 1 1 684B1CE3 +P 15200 3300 +F 0 "X?" H 15350 3200 60 0000 C CNN +F 1 "4_OR" H 15350 3400 60 0000 C CNN +F 2 "" H 15200 3300 60 0000 C CNN +F 3 "" H 15200 3300 60 0000 C CNN + 1 15200 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 684B1D62 +P 16300 3300 +F 0 "U?" H 16300 3200 60 0000 C CNN +F 1 "d_inverter" H 16300 3450 60 0000 C CNN +F 2 "" H 16350 3250 60 0000 C CNN +F 3 "" H 16350 3250 60 0000 C CNN + 1 16300 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B2488 +P 17050 3400 +F 0 "U?" H 17050 3400 60 0000 C CNN +F 1 "d_and" H 17100 3500 60 0000 C CNN +F 2 "" H 17050 3400 60 0000 C CNN +F 3 "" H 17050 3400 60 0000 C CNN + 1 17050 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B2663 +P 4750 6000 +F 0 "U?" H 4750 6000 60 0000 C CNN +F 1 "d_dlatch" H 4750 6150 60 0000 C CNN +F 2 "" H 4750 6000 60 0000 C CNN +F 3 "" H 4750 6000 60 0000 C CNN + 1 4750 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B2669 +P 6950 6000 +F 0 "U?" H 6950 6000 60 0000 C CNN +F 1 "d_dlatch" H 6950 6150 60 0000 C CNN +F 2 "" H 6950 6000 60 0000 C CNN +F 3 "" H 6950 6000 60 0000 C CNN + 1 6950 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B266F +P 9150 6000 +F 0 "U?" H 9150 6000 60 0000 C CNN +F 1 "d_dlatch" H 9150 6150 60 0000 C CNN +F 2 "" H 9150 6000 60 0000 C CNN +F 3 "" H 9150 6000 60 0000 C CNN + 1 9150 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B2675 +P 11400 6000 +F 0 "U?" H 11400 6000 60 0000 C CNN +F 1 "d_dlatch" H 11400 6150 60 0000 C CNN +F 2 "" H 11400 6000 60 0000 C CNN +F 3 "" H 11400 6000 60 0000 C CNN + 1 11400 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B267B +P 3750 6350 +F 0 "U?" H 3750 6350 60 0000 C CNN +F 1 "d_and" H 3800 6450 60 0000 C CNN +F 2 "" H 3750 6350 60 0000 C CNN +F 3 "" H 3750 6350 60 0000 C CNN + 1 3750 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B2681 +P 5950 6350 +F 0 "U?" H 5950 6350 60 0000 C CNN +F 1 "d_and" H 6000 6450 60 0000 C CNN +F 2 "" H 5950 6350 60 0000 C CNN +F 3 "" H 5950 6350 60 0000 C CNN + 1 5950 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B2687 +P 8150 6350 +F 0 "U?" H 8150 6350 60 0000 C CNN +F 1 "d_and" H 8200 6450 60 0000 C CNN +F 2 "" H 8150 6350 60 0000 C CNN +F 3 "" H 8150 6350 60 0000 C CNN + 1 8150 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B268D +P 10400 6350 +F 0 "U?" H 10400 6350 60 0000 C CNN +F 1 "d_and" H 10450 6450 60 0000 C CNN +F 2 "" H 10400 6350 60 0000 C CNN +F 3 "" H 10400 6350 60 0000 C CNN + 1 10400 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 684B2693 +P 2050 5300 +F 0 "U?" H 2050 5200 60 0000 C CNN +F 1 "d_inverter" H 2050 5450 60 0000 C CNN +F 2 "" H 2100 5250 60 0000 C CNN +F 3 "" H 2100 5250 60 0000 C CNN + 1 2050 5300 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X? +U 1 1 684B26B1 +P 15300 6050 +F 0 "X?" H 15450 5950 60 0000 C CNN +F 1 "4_OR" H 15450 6150 60 0000 C CNN +F 2 "" H 15300 6050 60 0000 C CNN +F 3 "" H 15300 6050 60 0000 C CNN + 1 15300 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 684B26B7 +P 16400 6050 +F 0 "U?" H 16400 5950 60 0000 C CNN +F 1 "d_inverter" H 16400 6200 60 0000 C CNN +F 2 "" H 16450 6000 60 0000 C CNN +F 3 "" H 16450 6000 60 0000 C CNN + 1 16400 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B26D0 +P 17150 6150 +F 0 "U?" H 17150 6150 60 0000 C CNN +F 1 "d_and" H 17200 6250 60 0000 C CNN +F 2 "" H 17150 6150 60 0000 C CNN +F 3 "" H 17150 6150 60 0000 C CNN + 1 17150 6150 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B4B96 +P 4600 8850 +F 0 "U?" H 4600 8850 60 0000 C CNN +F 1 "d_dlatch" H 4600 9000 60 0000 C CNN +F 2 "" H 4600 8850 60 0000 C CNN +F 3 "" H 4600 8850 60 0000 C CNN + 1 4600 8850 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B4B9C +P 6800 8850 +F 0 "U?" H 6800 8850 60 0000 C CNN +F 1 "d_dlatch" H 6800 9000 60 0000 C CNN +F 2 "" H 6800 8850 60 0000 C CNN +F 3 "" H 6800 8850 60 0000 C CNN + 1 6800 8850 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B4BA2 +P 9000 8850 +F 0 "U?" H 9000 8850 60 0000 C CNN +F 1 "d_dlatch" H 9000 9000 60 0000 C CNN +F 2 "" H 9000 8850 60 0000 C CNN +F 3 "" H 9000 8850 60 0000 C CNN + 1 9000 8850 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B4BA8 +P 11250 8850 +F 0 "U?" H 11250 8850 60 0000 C CNN +F 1 "d_dlatch" H 11250 9000 60 0000 C CNN +F 2 "" H 11250 8850 60 0000 C CNN +F 3 "" H 11250 8850 60 0000 C CNN + 1 11250 8850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B4BAE +P 3600 9200 +F 0 "U?" H 3600 9200 60 0000 C CNN +F 1 "d_and" H 3650 9300 60 0000 C CNN +F 2 "" H 3600 9200 60 0000 C CNN +F 3 "" H 3600 9200 60 0000 C CNN + 1 3600 9200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B4BB4 +P 5800 9200 +F 0 "U?" H 5800 9200 60 0000 C CNN +F 1 "d_and" H 5850 9300 60 0000 C CNN +F 2 "" H 5800 9200 60 0000 C CNN +F 3 "" H 5800 9200 60 0000 C CNN + 1 5800 9200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B4BBA +P 8000 9200 +F 0 "U?" H 8000 9200 60 0000 C CNN +F 1 "d_and" H 8050 9300 60 0000 C CNN +F 2 "" H 8000 9200 60 0000 C CNN +F 3 "" H 8000 9200 60 0000 C CNN + 1 8000 9200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B4BC0 +P 10250 9200 +F 0 "U?" H 10250 9200 60 0000 C CNN +F 1 "d_and" H 10300 9300 60 0000 C CNN +F 2 "" H 10250 9200 60 0000 C CNN +F 3 "" H 10250 9200 60 0000 C CNN + 1 10250 9200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 684B4BC6 +P 2000 8150 +F 0 "U?" H 2000 8050 60 0000 C CNN +F 1 "d_inverter" H 2000 8300 60 0000 C CNN +F 2 "" H 2050 8100 60 0000 C CNN +F 3 "" H 2050 8100 60 0000 C CNN + 1 2000 8150 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X? +U 1 1 684B4BE4 +P 15150 8900 +F 0 "X?" H 15300 8800 60 0000 C CNN +F 1 "4_OR" H 15300 9000 60 0000 C CNN +F 2 "" H 15150 8900 60 0000 C CNN +F 3 "" H 15150 8900 60 0000 C CNN + 1 15150 8900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 684B4BEA +P 16250 8900 +F 0 "U?" H 16250 8800 60 0000 C CNN +F 1 "d_inverter" H 16250 9050 60 0000 C CNN +F 2 "" H 16300 8850 60 0000 C CNN +F 3 "" H 16300 8850 60 0000 C CNN + 1 16250 8900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B4C03 +P 17000 9000 +F 0 "U?" H 17000 9000 60 0000 C CNN +F 1 "d_and" H 17050 9100 60 0000 C CNN +F 2 "" H 17000 9000 60 0000 C CNN +F 3 "" H 17000 9000 60 0000 C CNN + 1 17000 9000 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B6649 +P 4550 11350 +F 0 "U?" H 4550 11350 60 0000 C CNN +F 1 "d_dlatch" H 4550 11500 60 0000 C CNN +F 2 "" H 4550 11350 60 0000 C CNN +F 3 "" H 4550 11350 60 0000 C CNN + 1 4550 11350 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B664F +P 6750 11350 +F 0 "U?" H 6750 11350 60 0000 C CNN +F 1 "d_dlatch" H 6750 11500 60 0000 C CNN +F 2 "" H 6750 11350 60 0000 C CNN +F 3 "" H 6750 11350 60 0000 C CNN + 1 6750 11350 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B6655 +P 8950 11350 +F 0 "U?" H 8950 11350 60 0000 C CNN +F 1 "d_dlatch" H 8950 11500 60 0000 C CNN +F 2 "" H 8950 11350 60 0000 C CNN +F 3 "" H 8950 11350 60 0000 C CNN + 1 8950 11350 + 1 0 0 -1 +$EndComp +$Comp +L d_dlatch U? +U 1 1 684B665B +P 11200 11350 +F 0 "U?" H 11200 11350 60 0000 C CNN +F 1 "d_dlatch" H 11200 11500 60 0000 C CNN +F 2 "" H 11200 11350 60 0000 C CNN +F 3 "" H 11200 11350 60 0000 C CNN + 1 11200 11350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B6661 +P 3550 11700 +F 0 "U?" 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H 1950 10550 60 0000 C CNN +F 1 "d_inverter" H 1950 10800 60 0000 C CNN +F 2 "" H 2000 10600 60 0000 C CNN +F 3 "" H 2000 10600 60 0000 C CNN + 1 1950 10650 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X? +U 1 1 684B6697 +P 15100 11400 +F 0 "X?" H 15250 11300 60 0000 C CNN +F 1 "4_OR" H 15250 11500 60 0000 C CNN +F 2 "" H 15100 11400 60 0000 C CNN +F 3 "" H 15100 11400 60 0000 C CNN + 1 15100 11400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U? +U 1 1 684B669D +P 16200 11400 +F 0 "U?" H 16200 11300 60 0000 C CNN +F 1 "d_inverter" H 16200 11550 60 0000 C CNN +F 2 "" H 16250 11350 60 0000 C CNN +F 3 "" H 16250 11350 60 0000 C CNN + 1 16200 11400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 684B66B6 +P 16950 11500 +F 0 "U?" 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Wire Line + 13250 7200 13350 7200 +Connection ~ 13250 5950 +Wire Wire Line + 13350 6600 13150 6600 +Wire Wire Line + 13150 5250 13150 7600 +Wire Wire Line + 13150 7600 13300 7600 +Wire Wire Line + 13350 4900 13350 5250 +Connection ~ 13150 6600 +Connection ~ 13350 5250 +Wire Wire Line + 13250 8750 13300 8750 +Connection ~ 13250 7200 +Connection ~ 13250 8750 +Connection ~ 13250 10000 +Wire Wire Line + 13250 12000 12550 12000 +Wire Wire Line + 12550 12000 12550 13050 +Connection ~ 13250 11250 +Wire Wire Line + 13200 12500 12550 12500 +Connection ~ 12550 12500 +$Comp +L PORT U1 +U 1 1 68504AC0 +P 1500 5300 +F 0 "U1" H 1550 5400 30 0000 C CNN +F 1 "PORT" H 1500 5300 30 0000 C CNN +F 2 "" H 1500 5300 60 0000 C CNN +F 3 "" H 1500 5300 60 0000 C CNN + 1 1500 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68504CA1 +P 1450 8150 +F 0 "U1" H 1500 8250 30 0000 C CNN +F 1 "PORT" H 1450 8150 30 0000 C CNN +F 2 "" H 1450 8150 60 0000 C CNN +F 3 "" H 1450 8150 60 0000 C CNN + 2 1450 8150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68504D9E +P 1400 10650 +F 0 "U1" H 1450 10750 30 0000 C CNN +F 1 "PORT" H 1400 10650 30 0000 C CNN +F 2 "" H 1400 10650 60 0000 C CNN +F 3 "" H 1400 10650 60 0000 C CNN + 3 1400 10650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68504EE5 +P 11700 14250 +F 0 "U1" H 11750 14350 30 0000 C CNN +F 1 "PORT" H 11700 14250 30 0000 C CNN +F 2 "" H 11700 14250 60 0000 C CNN +F 3 "" H 11700 14250 60 0000 C CNN + 4 11700 14250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 685050CC +P 13450 14150 +F 0 "U1" H 13500 14250 30 0000 C CNN +F 1 "PORT" H 13450 14150 30 0000 C CNN +F 2 "" H 13450 14150 60 0000 C CNN +F 3 "" H 13450 14150 60 0000 C CNN + 5 13450 14150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 685051C9 +P 17650 11450 +F 0 "U1" H 17700 11550 30 0000 C CNN +F 1 "PORT" H 17650 11450 30 0000 C CNN +F 2 "" H 17650 11450 60 0000 C CNN +F 3 "" H 17650 11450 60 0000 C CNN + 6 17650 11450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 68505361 +P 17700 8950 +F 0 "U1" H 17750 9050 30 0000 C CNN +F 1 "PORT" H 17700 8950 30 0000 C CNN +F 2 "" H 17700 8950 60 0000 C CNN +F 3 "" H 17700 8950 60 0000 C CNN + 7 17700 8950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 68505450 +P 1450 4400 +F 0 "U1" H 1500 4500 30 0000 C CNN +F 1 "PORT" H 1450 4400 30 0000 C CNN +F 2 "" H 1450 4400 60 0000 C CNN +F 3 "" H 1450 4400 60 0000 C CNN + 8 1450 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 68505714 +P 17850 6100 +F 0 "U1" H 17900 6200 30 0000 C CNN +F 1 "PORT" H 17850 6100 30 0000 C CNN +F 2 "" H 17850 6100 60 0000 C CNN +F 3 "" H 17850 6100 60 0000 C CNN + 9 17850 6100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 68505917 +P 17750 3350 +F 0 "U1" H 17800 3450 30 0000 C CNN +F 1 "PORT" H 17750 3350 30 0000 C CNN +F 2 "" H 17750 3350 60 0000 C CNN +F 3 "" H 17750 3350 60 0000 C CNN + 10 17750 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 68505A34 +P 12850 14500 +F 0 "U1" H 12900 14600 30 0000 C CNN +F 1 "PORT" H 12850 14500 30 0000 C CNN +F 2 "" H 12850 14500 60 0000 C CNN +F 3 "" H 12850 14500 60 0000 C CNN + 11 12850 14500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 68505C61 +P 2250 14350 +F 0 "U1" H 2300 14450 30 0000 C CNN +F 1 "PORT" H 2250 14350 30 0000 C CNN +F 2 "" H 2250 14350 60 0000 C CNN +F 3 "" H 2250 14350 60 0000 C CNN + 12 2250 14350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 68505E34 +P 3300 14350 +F 0 "U1" H 3350 14450 30 0000 C CNN +F 1 "PORT" H 3300 14350 30 0000 C CNN +F 2 "" H 3300 14350 60 0000 C CNN +F 3 "" H 3300 14350 60 0000 C CNN + 13 3300 14350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 68505F0B +P 3900 14200 +F 0 "U1" H 3950 14300 30 0000 C CNN +F 1 "PORT" H 3900 14200 30 0000 C CNN +F 2 "" H 3900 14200 60 0000 C CNN +F 3 "" H 3900 14200 60 0000 C CNN + 14 3900 14200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 68505FF2 +P 2200 2550 +F 0 "U1" H 2250 2650 30 0000 C CNN +F 1 "PORT" H 2200 2550 30 0000 C CNN +F 2 "" H 2200 2550 60 0000 C CNN +F 3 "" H 2200 2550 60 0000 C CNN + 15 2200 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 6850624B +P 1450 4050 +F 0 "U1" H 1500 4150 30 0000 C CNN +F 1 "PORT" H 1450 4050 30 0000 C CNN +F 2 "" H 1450 4050 60 0000 C CNN +F 3 "" H 1450 4050 60 0000 C CNN + 16 1450 4050 + 1 0 0 -1 +$EndComp +NoConn ~ 1700 4050 +NoConn ~ 1700 4400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.sub b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.sub new file mode 100644 index 000000000..9932d7d84 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670.sub @@ -0,0 +1,248 @@ +* Subcircuit SC_SN74LS670 +.subckt SC_SN74LS670 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ ? net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn74ls670\sc_sn74ls670.cir +.include 3_and.sub +.include 4_OR.sub +* u18 net-_u18-pad1_ net-_u12-pad3_ ? ? net-_u18-pad5_ ? d_dlatch +* u26 net-_u18-pad1_ net-_u22-pad3_ ? ? net-_u26-pad5_ ? d_dlatch +* u34 net-_u18-pad1_ net-_u30-pad3_ ? ? net-_u34-pad5_ ? d_dlatch +* u42 net-_u18-pad1_ net-_u38-pad3_ ? ? net-_u42-pad5_ ? d_dlatch +* u12 net-_u10-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u22 net-_u10-pad1_ net-_u14-pad2_ net-_u22-pad3_ d_and +* u30 net-_u28-pad1_ net-_u10-pad2_ net-_u30-pad3_ d_and +* u38 net-_u28-pad1_ net-_u14-pad2_ net-_u38-pad3_ d_and +* u6 net-_u1-pad15_ net-_u18-pad1_ d_inverter +x19 net-_x11-pad4_ net-_x12-pad4_ net-_x19-pad3_ net-_x19-pad4_ net-_u51-pad1_ 4_OR +* u51 net-_u51-pad1_ net-_u51-pad2_ d_inverter +* u55 net-_u51-pad2_ net-_u48-pad2_ net-_u1-pad10_ d_and +* u19 net-_u19-pad1_ net-_u13-pad3_ ? ? net-_u19-pad5_ ? d_dlatch +* u27 net-_u19-pad1_ net-_u23-pad3_ ? ? net-_u27-pad5_ ? d_dlatch +* u35 net-_u19-pad1_ net-_u31-pad3_ ? ? net-_u35-pad5_ ? d_dlatch +* u43 net-_u19-pad1_ net-_u39-pad3_ ? ? net-_u43-pad5_ ? d_dlatch +* u13 net-_u10-pad1_ net-_u10-pad2_ net-_u13-pad3_ d_and +* u23 net-_u10-pad1_ net-_u14-pad2_ net-_u23-pad3_ d_and +* u31 net-_u28-pad1_ net-_u10-pad2_ net-_u31-pad3_ d_and +* u39 net-_u28-pad1_ net-_u14-pad2_ net-_u39-pad3_ d_and +* u4 net-_u1-pad1_ net-_u19-pad1_ d_inverter +x20 net-_x15-pad4_ net-_x16-pad4_ net-_x13-pad4_ net-_x14-pad4_ net-_u52-pad1_ 4_OR +* u52 net-_u52-pad1_ net-_u52-pad2_ d_inverter +* u56 net-_u52-pad2_ net-_u48-pad2_ net-_u1-pad9_ d_and +* u17 net-_u17-pad1_ net-_u11-pad3_ ? ? net-_u17-pad5_ ? d_dlatch +* u25 net-_u17-pad1_ net-_u21-pad3_ ? ? net-_u25-pad5_ ? d_dlatch +* u33 net-_u17-pad1_ net-_u29-pad3_ ? ? net-_u33-pad5_ ? d_dlatch +* u41 net-_u17-pad1_ net-_u37-pad3_ ? ? net-_u41-pad5_ ? d_dlatch +* u11 net-_u10-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u21 net-_u10-pad1_ net-_u14-pad2_ net-_u21-pad3_ d_and +* u29 net-_u28-pad1_ net-_u10-pad2_ net-_u29-pad3_ d_and +* u37 net-_u28-pad1_ net-_u14-pad2_ net-_u37-pad3_ d_and +* u3 net-_u1-pad2_ net-_u17-pad1_ d_inverter +x18 net-_x18-pad1_ net-_x10-pad4_ net-_x18-pad3_ net-_x18-pad4_ net-_u50-pad1_ 4_OR +* u50 net-_u50-pad1_ net-_u50-pad2_ d_inverter +* u54 net-_u50-pad2_ net-_u48-pad2_ net-_u1-pad7_ d_and +* u16 net-_u16-pad1_ net-_u10-pad3_ ? ? net-_u16-pad5_ ? d_dlatch +* u24 net-_u16-pad1_ net-_u20-pad3_ ? ? net-_u24-pad5_ ? d_dlatch +* u32 net-_u16-pad1_ net-_u28-pad3_ ? ? net-_u32-pad5_ ? d_dlatch +* u40 net-_u16-pad1_ net-_u36-pad3_ ? ? net-_u40-pad5_ ? d_dlatch +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u20 net-_u10-pad1_ net-_u14-pad2_ net-_u20-pad3_ d_and +* u28 net-_u28-pad1_ net-_u10-pad2_ net-_u28-pad3_ d_and +* u36 net-_u28-pad1_ net-_u14-pad2_ net-_u36-pad3_ d_and +* u2 net-_u1-pad3_ net-_u16-pad1_ d_inverter +x17 net-_x17-pad1_ net-_x17-pad2_ net-_x1-pad4_ net-_x17-pad4_ net-_u49-pad1_ 4_OR +* u49 net-_u49-pad1_ net-_u49-pad2_ d_inverter +* u53 net-_u49-pad2_ net-_u48-pad2_ net-_u1-pad6_ d_and +* u5 net-_u1-pad12_ net-_u5-pad2_ net-_u28-pad1_ d_nor +* u8 net-_u7-pad2_ net-_u5-pad2_ net-_u10-pad1_ d_and +* u7 net-_u1-pad12_ net-_u7-pad2_ d_inverter +* u9 net-_u1-pad13_ net-_u5-pad2_ d_inverter +* u14 net-_u10-pad2_ net-_u14-pad2_ d_inverter +* u15 net-_u1-pad14_ net-_u10-pad2_ d_inverter +* u46 net-_u46-pad1_ net-_u46-pad2_ net-_u46-pad3_ d_nor +* u47 net-_u46-pad1_ net-_u1-pad5_ net-_u46-pad2_ d_nor +* u48 net-_u46-pad1_ net-_u48-pad2_ d_inverter +* u44 net-_u44-pad1_ net-_u44-pad2_ d_inverter +* u45 net-_u1-pad4_ net-_u44-pad1_ d_inverter +x6 net-_u24-pad5_ net-_u44-pad1_ net-_u46-pad3_ net-_x17-pad2_ 3_and +x1 net-_u32-pad5_ net-_u44-pad2_ net-_u46-pad2_ net-_x1-pad4_ 3_and +x2 net-_u40-pad5_ net-_u44-pad2_ net-_u46-pad3_ net-_x17-pad4_ 3_and +x5 net-_u16-pad5_ net-_u44-pad1_ net-_u46-pad2_ net-_x17-pad1_ 3_and +x9 net-_u17-pad5_ net-_u44-pad1_ net-_u46-pad2_ net-_x18-pad1_ 3_and +x10 net-_u25-pad5_ net-_u44-pad1_ net-_u46-pad3_ net-_x10-pad4_ 3_and +x3 net-_u33-pad5_ net-_u44-pad2_ net-_u46-pad2_ net-_x18-pad3_ 3_and +x4 net-_u41-pad5_ net-_u44-pad2_ net-_u46-pad3_ net-_x18-pad4_ 3_and +x15 net-_u19-pad5_ net-_u44-pad1_ net-_u46-pad2_ net-_x15-pad4_ 3_and +x16 net-_u27-pad5_ net-_u44-pad1_ net-_u46-pad3_ net-_x16-pad4_ 3_and +x13 net-_u35-pad5_ net-_u44-pad2_ net-_u46-pad2_ net-_x13-pad4_ 3_and +x14 net-_u43-pad5_ net-_u44-pad2_ net-_u46-pad3_ net-_x14-pad4_ 3_and +x11 net-_u18-pad5_ net-_u44-pad1_ net-_u46-pad2_ net-_x11-pad4_ 3_and +x12 net-_u26-pad5_ net-_u44-pad1_ net-_u46-pad3_ net-_x12-pad4_ 3_and +x7 net-_u34-pad5_ net-_u44-pad2_ net-_u46-pad2_ net-_x19-pad3_ 3_and +x8 net-_u42-pad5_ net-_u44-pad2_ net-_u46-pad3_ net-_x19-pad4_ 3_and +a1 net-_u18-pad1_ net-_u12-pad3_ ? ? net-_u18-pad5_ ? u18 +a2 net-_u18-pad1_ net-_u22-pad3_ ? ? net-_u26-pad5_ ? u26 +a3 net-_u18-pad1_ net-_u30-pad3_ ? ? net-_u34-pad5_ ? u34 +a4 net-_u18-pad1_ net-_u38-pad3_ ? ? net-_u42-pad5_ ? u42 +a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u10-pad1_ net-_u14-pad2_ ] net-_u22-pad3_ u22 +a7 [net-_u28-pad1_ net-_u10-pad2_ ] net-_u30-pad3_ u30 +a8 [net-_u28-pad1_ net-_u14-pad2_ ] net-_u38-pad3_ u38 +a9 net-_u1-pad15_ net-_u18-pad1_ u6 +a10 net-_u51-pad1_ net-_u51-pad2_ u51 +a11 [net-_u51-pad2_ net-_u48-pad2_ ] net-_u1-pad10_ u55 +a12 net-_u19-pad1_ net-_u13-pad3_ ? ? net-_u19-pad5_ ? u19 +a13 net-_u19-pad1_ net-_u23-pad3_ ? ? net-_u27-pad5_ ? u27 +a14 net-_u19-pad1_ net-_u31-pad3_ ? ? net-_u35-pad5_ ? u35 +a15 net-_u19-pad1_ net-_u39-pad3_ ? ? net-_u43-pad5_ ? u43 +a16 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u13-pad3_ u13 +a17 [net-_u10-pad1_ net-_u14-pad2_ ] net-_u23-pad3_ u23 +a18 [net-_u28-pad1_ net-_u10-pad2_ ] net-_u31-pad3_ u31 +a19 [net-_u28-pad1_ net-_u14-pad2_ ] net-_u39-pad3_ u39 +a20 net-_u1-pad1_ net-_u19-pad1_ u4 +a21 net-_u52-pad1_ net-_u52-pad2_ u52 +a22 [net-_u52-pad2_ net-_u48-pad2_ ] net-_u1-pad9_ u56 +a23 net-_u17-pad1_ net-_u11-pad3_ ? ? net-_u17-pad5_ ? u17 +a24 net-_u17-pad1_ net-_u21-pad3_ ? ? net-_u25-pad5_ ? u25 +a25 net-_u17-pad1_ net-_u29-pad3_ ? ? net-_u33-pad5_ ? u33 +a26 net-_u17-pad1_ net-_u37-pad3_ ? ? net-_u41-pad5_ ? u41 +a27 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a28 [net-_u10-pad1_ net-_u14-pad2_ ] net-_u21-pad3_ u21 +a29 [net-_u28-pad1_ net-_u10-pad2_ ] net-_u29-pad3_ u29 +a30 [net-_u28-pad1_ net-_u14-pad2_ ] net-_u37-pad3_ u37 +a31 net-_u1-pad2_ net-_u17-pad1_ u3 +a32 net-_u50-pad1_ net-_u50-pad2_ u50 +a33 [net-_u50-pad2_ net-_u48-pad2_ ] net-_u1-pad7_ u54 +a34 net-_u16-pad1_ net-_u10-pad3_ ? ? net-_u16-pad5_ ? u16 +a35 net-_u16-pad1_ net-_u20-pad3_ ? ? net-_u24-pad5_ ? u24 +a36 net-_u16-pad1_ net-_u28-pad3_ ? ? net-_u32-pad5_ ? u32 +a37 net-_u16-pad1_ net-_u36-pad3_ ? ? net-_u40-pad5_ ? u40 +a38 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a39 [net-_u10-pad1_ net-_u14-pad2_ ] net-_u20-pad3_ u20 +a40 [net-_u28-pad1_ net-_u10-pad2_ ] net-_u28-pad3_ u28 +a41 [net-_u28-pad1_ net-_u14-pad2_ ] net-_u36-pad3_ u36 +a42 net-_u1-pad3_ net-_u16-pad1_ u2 +a43 net-_u49-pad1_ net-_u49-pad2_ u49 +a44 [net-_u49-pad2_ net-_u48-pad2_ ] net-_u1-pad6_ u53 +a45 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u28-pad1_ u5 +a46 [net-_u7-pad2_ net-_u5-pad2_ ] net-_u10-pad1_ u8 +a47 net-_u1-pad12_ net-_u7-pad2_ u7 +a48 net-_u1-pad13_ net-_u5-pad2_ u9 +a49 net-_u10-pad2_ net-_u14-pad2_ u14 +a50 net-_u1-pad14_ net-_u10-pad2_ u15 +a51 [net-_u46-pad1_ net-_u46-pad2_ ] net-_u46-pad3_ u46 +a52 [net-_u46-pad1_ net-_u1-pad5_ ] net-_u46-pad2_ u47 +a53 net-_u46-pad1_ net-_u48-pad2_ u48 +a54 net-_u44-pad1_ net-_u44-pad2_ u44 +a55 net-_u1-pad4_ net-_u44-pad1_ u45 +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u18 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u26 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u34 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u42 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u19 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u27 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u35 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u43 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u17 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u25 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u33 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u41 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u16 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u24 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u32 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, NgSpice Name: d_dlatch +.model u40 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_SN74LS670 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670_Previous_Values.xml new file mode 100644 index 000000000..d97a8e58a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS670/SC_SN74LS670_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsmsd_dlatchd_dlatchd_dlatchd_dlatchd_andd_andd_andd_andd_inverterd_inverterd_andd_dlatchd_dlatchd_dlatchd_dlatchd_andd_andd_andd_andd_inverterd_inverterd_andd_dlatchd_dlatchd_dlatchd_dlatchd_andd_andd_andd_andd_inverterd_inverterd_andd_dlatchd_dlatchd_dlatchd_dlatchd_andd_andd_andd_andd_inverterd_inverterd_andd_nord_andd_inverterd_inverterd_inverterd_inverterd_nord_nord_inverterd_inverterd_inverterC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_and \ No newline at end of file From 105a5cbb97dd2b0a9ca3508a53be988ebae2a508 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 16:58:53 +0530 Subject: [PATCH 15/33] 1- of-16 Decoder/Demultiplexer --- library/SubcircuitLibrary/SL74HC154/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/SL74HC154/analysis diff --git a/library/SubcircuitLibrary/SL74HC154/analysis b/library/SubcircuitLibrary/SL74HC154/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/SL74HC154/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 1254be924e6fd019eaece1293af31ed42ba91ef6 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:00:18 +0530 Subject: [PATCH 16/33] 1- of-16 Decoder/Demultiplexer --- .../SL74HC154/SC_SL74HC154-cache.lib | 97 ++ .../SL74HC154/SC_SL74HC154.cir | 53 + .../SL74HC154/SC_SL74HC154.cir.out | 133 ++ .../SL74HC154/SC_SL74HC154.pro | 73 ++ .../SL74HC154/SC_SL74HC154.sch | 1101 +++++++++++++++++ .../SL74HC154/SC_SL74HC154.sub | 127 ++ .../SC_SL74HC154_Previous_Values.xml | 1 + 7 files changed, 1585 insertions(+) create mode 100644 library/SubcircuitLibrary/SL74HC154/SC_SL74HC154-cache.lib create mode 100644 library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.cir create mode 100644 library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.cir.out create mode 100644 library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.pro create mode 100644 library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.sch create mode 100644 library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.sub create mode 100644 library/SubcircuitLibrary/SL74HC154/SC_SL74HC154_Previous_Values.xml diff --git a/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154-cache.lib b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154-cache.lib new file mode 100644 index 000000000..d7d01fc05 --- /dev/null +++ b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.cir b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.cir new file mode 100644 index 000000000..dbd89c488 --- /dev/null +++ b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.cir @@ -0,0 +1,53 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_SL74HC154\SC_SL74HC154.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/15/25 17:03:24 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U10 Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U10-Pad3_ d_nor +U9 Net-_U1-Pad19_ Net-_U1-Pad18_ Net-_U9-Pad3_ d_nor +X1 Net-_U11-Pad1_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad3_ Net-_U12-Pad1_ 5_and +X2 Net-_U11-Pad2_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad3_ Net-_U13-Pad1_ 5_and +X3 Net-_U11-Pad1_ Net-_U6-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad3_ Net-_U14-Pad1_ 5_and +X4 Net-_U11-Pad2_ Net-_U6-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad3_ Net-_U15-Pad1_ 5_and +X5 Net-_U11-Pad1_ Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad3_ Net-_U16-Pad1_ 5_and +X6 Net-_U11-Pad2_ Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad3_ Net-_U17-Pad1_ 5_and +X7 Net-_U11-Pad1_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad3_ Net-_U18-Pad1_ 5_and +X8 Net-_U11-Pad2_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad3_ Net-_U19-Pad1_ 5_and +X9 Net-_U11-Pad1_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U8-Pad2_ Net-_U10-Pad3_ Net-_U20-Pad1_ 5_and +X10 Net-_U11-Pad2_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U8-Pad2_ Net-_U9-Pad3_ Net-_U21-Pad1_ 5_and +X11 Net-_U11-Pad1_ Net-_U6-Pad2_ Net-_U4-Pad2_ Net-_U8-Pad2_ Net-_U9-Pad3_ Net-_U22-Pad1_ 5_and +X12 Net-_U11-Pad2_ Net-_U6-Pad2_ Net-_U4-Pad2_ Net-_U8-Pad2_ Net-_U9-Pad3_ Net-_U23-Pad1_ 5_and +X13 Net-_U11-Pad1_ Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U9-Pad3_ Net-_U24-Pad1_ 5_and +X14 Net-_U11-Pad2_ Net-_U2-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U9-Pad3_ Net-_U25-Pad1_ 5_and +X15 Net-_U11-Pad1_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U9-Pad3_ Net-_U26-Pad1_ 5_and +X16 Net-_U11-Pad2_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U9-Pad3_ Net-_U27-Pad1_ 5_and +U12 Net-_U12-Pad1_ Net-_U1-Pad1_ d_inverter +U13 Net-_U13-Pad1_ Net-_U1-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U1-Pad3_ d_inverter +U15 Net-_U15-Pad1_ Net-_U1-Pad4_ d_inverter +U16 Net-_U16-Pad1_ Net-_U1-Pad5_ d_inverter +U17 Net-_U17-Pad1_ Net-_U1-Pad6_ d_inverter +U18 Net-_U18-Pad1_ Net-_U1-Pad7_ d_inverter +U19 Net-_U19-Pad1_ Net-_U1-Pad8_ d_inverter +U20 Net-_U20-Pad1_ Net-_U1-Pad9_ d_inverter +U21 Net-_U21-Pad1_ Net-_U1-Pad10_ d_inverter +U22 Net-_U22-Pad1_ Net-_U1-Pad11_ d_inverter +U23 Net-_U23-Pad1_ Net-_U1-Pad13_ d_inverter +U24 Net-_U24-Pad1_ Net-_U1-Pad14_ d_inverter +U25 Net-_U25-Pad1_ Net-_U1-Pad15_ d_inverter +U26 Net-_U26-Pad1_ Net-_U1-Pad16_ d_inverter +U27 Net-_U27-Pad1_ Net-_U1-Pad17_ d_inverter +U3 Net-_U1-Pad23_ Net-_U11-Pad1_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U2 Net-_U1-Pad22_ Net-_U2-Pad2_ d_inverter +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ d_inverter +U4 Net-_U1-Pad21_ Net-_U4-Pad2_ d_inverter +U7 Net-_U4-Pad2_ Net-_U7-Pad2_ d_inverter +U5 Net-_U1-Pad20_ Net-_U5-Pad2_ d_inverter +U8 Net-_U5-Pad2_ Net-_U8-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ ? Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.cir.out b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.cir.out new file mode 100644 index 000000000..ee05c8671 --- /dev/null +++ b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.cir.out @@ -0,0 +1,133 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_sl74hc154\sc_sl74hc154.cir + +.include 5_and.sub +* u10 net-_u1-pad18_ net-_u1-pad19_ net-_u10-pad3_ d_nor +* u9 net-_u1-pad19_ net-_u1-pad18_ net-_u9-pad3_ d_nor +x1 net-_u11-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u12-pad1_ 5_and +x2 net-_u11-pad2_ net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u13-pad1_ 5_and +x3 net-_u11-pad1_ net-_u6-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u14-pad1_ 5_and +x4 net-_u11-pad2_ net-_u6-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u15-pad1_ 5_and +x5 net-_u11-pad1_ net-_u2-pad2_ net-_u7-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u16-pad1_ 5_and +x6 net-_u11-pad2_ net-_u2-pad2_ net-_u7-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u17-pad1_ 5_and +x7 net-_u11-pad1_ net-_u6-pad2_ net-_u7-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u18-pad1_ 5_and +x8 net-_u11-pad2_ net-_u6-pad2_ net-_u7-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u19-pad1_ 5_and +x9 net-_u11-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u10-pad3_ net-_u20-pad1_ 5_and +x10 net-_u11-pad2_ net-_u2-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u21-pad1_ 5_and +x11 net-_u11-pad1_ net-_u6-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u22-pad1_ 5_and +x12 net-_u11-pad2_ net-_u6-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u23-pad1_ 5_and +x13 net-_u11-pad1_ net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u24-pad1_ 5_and +x14 net-_u11-pad2_ net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u25-pad1_ 5_and +x15 net-_u11-pad1_ net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u26-pad1_ 5_and +x16 net-_u11-pad2_ net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u27-pad1_ 5_and +* u12 net-_u12-pad1_ net-_u1-pad1_ d_inverter +* u13 net-_u13-pad1_ net-_u1-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u1-pad3_ d_inverter +* u15 net-_u15-pad1_ net-_u1-pad4_ d_inverter +* u16 net-_u16-pad1_ net-_u1-pad5_ d_inverter +* u17 net-_u17-pad1_ net-_u1-pad6_ d_inverter +* u18 net-_u18-pad1_ net-_u1-pad7_ d_inverter +* u19 net-_u19-pad1_ net-_u1-pad8_ d_inverter +* u20 net-_u20-pad1_ net-_u1-pad9_ d_inverter +* u21 net-_u21-pad1_ net-_u1-pad10_ d_inverter +* u22 net-_u22-pad1_ net-_u1-pad11_ d_inverter +* u23 net-_u23-pad1_ net-_u1-pad13_ d_inverter +* u24 net-_u24-pad1_ net-_u1-pad14_ d_inverter +* u25 net-_u25-pad1_ net-_u1-pad15_ d_inverter +* u26 net-_u26-pad1_ net-_u1-pad16_ d_inverter +* u27 net-_u27-pad1_ net-_u1-pad17_ d_inverter +* u3 net-_u1-pad23_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u2 net-_u1-pad22_ net-_u2-pad2_ d_inverter +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u4 net-_u1-pad21_ net-_u4-pad2_ d_inverter +* u7 net-_u4-pad2_ net-_u7-pad2_ d_inverter +* u5 net-_u1-pad20_ net-_u5-pad2_ d_inverter +* u8 net-_u5-pad2_ net-_u8-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? port +a1 [net-_u1-pad18_ net-_u1-pad19_ ] net-_u10-pad3_ u10 +a2 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u9-pad3_ u9 +a3 net-_u12-pad1_ net-_u1-pad1_ u12 +a4 net-_u13-pad1_ net-_u1-pad2_ u13 +a5 net-_u14-pad1_ net-_u1-pad3_ u14 +a6 net-_u15-pad1_ net-_u1-pad4_ u15 +a7 net-_u16-pad1_ net-_u1-pad5_ u16 +a8 net-_u17-pad1_ net-_u1-pad6_ u17 +a9 net-_u18-pad1_ net-_u1-pad7_ u18 +a10 net-_u19-pad1_ net-_u1-pad8_ u19 +a11 net-_u20-pad1_ net-_u1-pad9_ u20 +a12 net-_u21-pad1_ net-_u1-pad10_ u21 +a13 net-_u22-pad1_ net-_u1-pad11_ u22 +a14 net-_u23-pad1_ net-_u1-pad13_ u23 +a15 net-_u24-pad1_ net-_u1-pad14_ u24 +a16 net-_u25-pad1_ net-_u1-pad15_ u25 +a17 net-_u26-pad1_ net-_u1-pad16_ u26 +a18 net-_u27-pad1_ net-_u1-pad17_ u27 +a19 net-_u1-pad23_ net-_u11-pad1_ u3 +a20 net-_u11-pad1_ net-_u11-pad2_ u11 +a21 net-_u1-pad22_ net-_u2-pad2_ u2 +a22 net-_u2-pad2_ net-_u6-pad2_ u6 +a23 net-_u1-pad21_ net-_u4-pad2_ u4 +a24 net-_u4-pad2_ net-_u7-pad2_ u7 +a25 net-_u1-pad20_ net-_u5-pad2_ u5 +a26 net-_u5-pad2_ net-_u8-pad2_ u8 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.pro b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.sch b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.sch new file mode 100644 index 000000000..139c2d1ce --- /dev/null +++ b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.sch @@ -0,0 +1,1101 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_SL74HC154-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nor U10 +U 1 1 684D2CB5 +P 2600 1600 +F 0 "U10" H 2600 1600 60 0000 C CNN +F 1 "d_nor" H 2650 1700 60 0000 C CNN +F 2 "" H 2600 1600 60 0000 C CNN +F 3 "" H 2600 1600 60 0000 C CNN + 1 2600 1600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U9 +U 1 1 684D2CF0 +P 2550 2050 +F 0 "U9" H 2550 2050 60 0000 C CNN +F 1 "d_nor" H 2600 2150 60 0000 C CNN +F 2 "" H 2550 2050 60 0000 C CNN +F 3 "" H 2550 2050 60 0000 C CNN + 1 2550 2050 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X1 +U 1 1 684D2D21 +P 5000 50 +F 0 "X1" H 5050 -50 60 0000 C CNN +F 1 "5_and" H 5100 200 60 0000 C CNN +F 2 "" H 5000 50 60 0000 C CNN +F 3 "" H 5000 50 60 0000 C CNN + 1 5000 50 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X2 +U 1 1 684D2EBF +P 5000 700 +F 0 "X2" H 5050 600 60 0000 C CNN +F 1 "5_and" H 5100 850 60 0000 C CNN +F 2 "" H 5000 700 60 0000 C CNN +F 3 "" H 5000 700 60 0000 C CNN + 1 5000 700 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X3 +U 1 1 684D2F1E +P 5000 1350 +F 0 "X3" H 5050 1250 60 0000 C CNN +F 1 "5_and" H 5100 1500 60 0000 C CNN +F 2 "" H 5000 1350 60 0000 C CNN +F 3 "" H 5000 1350 60 0000 C CNN + 1 5000 1350 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X4 +U 1 1 684D2F63 +P 5000 2000 +F 0 "X4" H 5050 1900 60 0000 C CNN +F 1 "5_and" H 5100 2150 60 0000 C CNN +F 2 "" H 5000 2000 60 0000 C CNN +F 3 "" H 5000 2000 60 0000 C CNN + 1 5000 2000 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X5 +U 1 1 684D2FAE +P 5000 2650 +F 0 "X5" H 5050 2550 60 0000 C CNN +F 1 "5_and" H 5100 2800 60 0000 C CNN +F 2 "" H 5000 2650 60 0000 C CNN +F 3 "" H 5000 2650 60 0000 C CNN + 1 5000 2650 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X6 +U 1 1 684D2FF8 +P 5000 3250 +F 0 "X6" H 5050 3150 60 0000 C CNN +F 1 "5_and" H 5100 3400 60 0000 C CNN +F 2 "" H 5000 3250 60 0000 C CNN +F 3 "" H 5000 3250 60 0000 C CNN + 1 5000 3250 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X7 +U 1 1 684D3043 +P 5000 3900 +F 0 "X7" H 5050 3800 60 0000 C CNN +F 1 "5_and" H 5100 4050 60 0000 C CNN +F 2 "" H 5000 3900 60 0000 C CNN +F 3 "" H 5000 3900 60 0000 C CNN + 1 5000 3900 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X8 +U 1 1 684D36DB +P 5000 4550 +F 0 "X8" H 5050 4450 60 0000 C CNN +F 1 "5_and" H 5100 4700 60 0000 C CNN +F 2 "" H 5000 4550 60 0000 C CNN +F 3 "" H 5000 4550 60 0000 C CNN + 1 5000 4550 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X9 +U 1 1 684EA006 +P 5000 5150 +F 0 "X9" H 5050 5050 60 0000 C CNN +F 1 "5_and" H 5100 5300 60 0000 C CNN +F 2 "" H 5000 5150 60 0000 C CNN +F 3 "" H 5000 5150 60 0000 C CNN + 1 5000 5150 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X10 +U 1 1 684EA07D +P 5000 5850 +F 0 "X10" H 5050 5750 60 0000 C CNN +F 1 "5_and" H 5100 6000 60 0000 C CNN +F 2 "" H 5000 5850 60 0000 C CNN +F 3 "" H 5000 5850 60 0000 C CNN + 1 5000 5850 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X11 +U 1 1 684EA0DA +P 5000 6550 +F 0 "X11" H 5050 6450 60 0000 C CNN +F 1 "5_and" H 5100 6700 60 0000 C CNN +F 2 "" H 5000 6550 60 0000 C CNN +F 3 "" H 5000 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+F 3 "" H 6400 10100 60 0000 C CNN + 17 6400 10100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 18 1 68507BA7 +P 1400 1500 +F 0 "U1" H 1450 1600 30 0000 C CNN +F 1 "PORT" H 1400 1500 30 0000 C CNN +F 2 "" H 1400 1500 60 0000 C CNN +F 3 "" H 1400 1500 60 0000 C CNN + 18 1400 1500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 19 1 68507C60 +P 1600 1600 +F 0 "U1" H 1650 1700 30 0000 C CNN +F 1 "PORT" H 1600 1600 30 0000 C CNN +F 2 "" H 1600 1600 60 0000 C CNN +F 3 "" H 1600 1600 60 0000 C CNN + 19 1600 1600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 21 1 685099C8 +P 1150 5150 +F 0 "U1" H 1200 5250 30 0000 C CNN +F 1 "PORT" H 1150 5150 30 0000 C CNN +F 2 "" H 1150 5150 60 0000 C CNN +F 3 "" H 1150 5150 60 0000 C CNN + 21 1150 5150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 22 1 68509A93 +P 1050 4100 +F 0 "U1" H 1100 4200 30 0000 C CNN +F 1 "PORT" H 1050 4100 30 0000 C CNN +F 2 "" H 1050 4100 60 0000 C CNN +F 3 "" H 1050 4100 60 0000 C CNN + 22 1050 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 23 1 68509B5E +P 1100 3250 +F 0 "U1" H 1150 3350 30 0000 C CNN +F 1 "PORT" H 1100 3250 30 0000 C CNN +F 2 "" H 1100 3250 60 0000 C CNN +F 3 "" H 1100 3250 60 0000 C CNN + 23 1100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 24 1 68509D37 +P 7550 4700 +F 0 "U1" H 7600 4800 30 0000 C CNN +F 1 "PORT" H 7550 4700 30 0000 C CNN +F 2 "" H 7550 4700 60 0000 C CNN +F 3 "" H 7550 4700 60 0000 C CNN + 24 7550 4700 + 1 0 0 -1 +$EndComp +NoConn ~ 7800 4400 +NoConn ~ 7800 4700 +$Comp +L PORT U1 +U 20 1 684EC5C6 +P 1150 6200 +F 0 "U1" H 1200 6300 30 0000 C CNN +F 1 "PORT" H 1150 6200 30 0000 C CNN +F 2 "" H 1150 6200 60 0000 C CNN +F 3 "" H 1150 6200 60 0000 C CNN + 20 1150 6200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.sub b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.sub new file mode 100644 index 000000000..011046fd1 --- /dev/null +++ b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154.sub @@ -0,0 +1,127 @@ +* Subcircuit SC_SL74HC154 +.subckt SC_SL74HC154 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_sl74hc154\sc_sl74hc154.cir +.include 5_and.sub +* u10 net-_u1-pad18_ net-_u1-pad19_ net-_u10-pad3_ d_nor +* u9 net-_u1-pad19_ net-_u1-pad18_ net-_u9-pad3_ d_nor +x1 net-_u11-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u12-pad1_ 5_and +x2 net-_u11-pad2_ net-_u2-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u13-pad1_ 5_and +x3 net-_u11-pad1_ net-_u6-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u14-pad1_ 5_and +x4 net-_u11-pad2_ net-_u6-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u15-pad1_ 5_and +x5 net-_u11-pad1_ net-_u2-pad2_ net-_u7-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u16-pad1_ 5_and +x6 net-_u11-pad2_ net-_u2-pad2_ net-_u7-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u17-pad1_ 5_and +x7 net-_u11-pad1_ net-_u6-pad2_ net-_u7-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u18-pad1_ 5_and +x8 net-_u11-pad2_ net-_u6-pad2_ net-_u7-pad2_ net-_u5-pad2_ net-_u10-pad3_ net-_u19-pad1_ 5_and +x9 net-_u11-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u10-pad3_ net-_u20-pad1_ 5_and +x10 net-_u11-pad2_ net-_u2-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u21-pad1_ 5_and +x11 net-_u11-pad1_ net-_u6-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u22-pad1_ 5_and +x12 net-_u11-pad2_ net-_u6-pad2_ net-_u4-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u23-pad1_ 5_and +x13 net-_u11-pad1_ net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u24-pad1_ 5_and +x14 net-_u11-pad2_ net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u25-pad1_ 5_and +x15 net-_u11-pad1_ net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u26-pad1_ 5_and +x16 net-_u11-pad2_ net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u9-pad3_ net-_u27-pad1_ 5_and +* u12 net-_u12-pad1_ net-_u1-pad1_ d_inverter +* u13 net-_u13-pad1_ net-_u1-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u1-pad3_ d_inverter +* u15 net-_u15-pad1_ net-_u1-pad4_ d_inverter +* u16 net-_u16-pad1_ net-_u1-pad5_ d_inverter +* u17 net-_u17-pad1_ net-_u1-pad6_ d_inverter +* u18 net-_u18-pad1_ net-_u1-pad7_ d_inverter +* u19 net-_u19-pad1_ net-_u1-pad8_ d_inverter +* u20 net-_u20-pad1_ net-_u1-pad9_ d_inverter +* u21 net-_u21-pad1_ net-_u1-pad10_ d_inverter +* u22 net-_u22-pad1_ net-_u1-pad11_ d_inverter +* u23 net-_u23-pad1_ net-_u1-pad13_ d_inverter +* u24 net-_u24-pad1_ net-_u1-pad14_ d_inverter +* u25 net-_u25-pad1_ net-_u1-pad15_ d_inverter +* u26 net-_u26-pad1_ net-_u1-pad16_ d_inverter +* u27 net-_u27-pad1_ net-_u1-pad17_ d_inverter +* u3 net-_u1-pad23_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u2 net-_u1-pad22_ net-_u2-pad2_ d_inverter +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u4 net-_u1-pad21_ net-_u4-pad2_ d_inverter +* u7 net-_u4-pad2_ net-_u7-pad2_ d_inverter +* u5 net-_u1-pad20_ net-_u5-pad2_ d_inverter +* u8 net-_u5-pad2_ net-_u8-pad2_ d_inverter +a1 [net-_u1-pad18_ net-_u1-pad19_ ] net-_u10-pad3_ u10 +a2 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u9-pad3_ u9 +a3 net-_u12-pad1_ net-_u1-pad1_ u12 +a4 net-_u13-pad1_ net-_u1-pad2_ u13 +a5 net-_u14-pad1_ net-_u1-pad3_ u14 +a6 net-_u15-pad1_ net-_u1-pad4_ u15 +a7 net-_u16-pad1_ net-_u1-pad5_ u16 +a8 net-_u17-pad1_ net-_u1-pad6_ u17 +a9 net-_u18-pad1_ net-_u1-pad7_ u18 +a10 net-_u19-pad1_ net-_u1-pad8_ u19 +a11 net-_u20-pad1_ net-_u1-pad9_ u20 +a12 net-_u21-pad1_ net-_u1-pad10_ u21 +a13 net-_u22-pad1_ net-_u1-pad11_ u22 +a14 net-_u23-pad1_ net-_u1-pad13_ u23 +a15 net-_u24-pad1_ net-_u1-pad14_ u24 +a16 net-_u25-pad1_ net-_u1-pad15_ u25 +a17 net-_u26-pad1_ net-_u1-pad16_ u26 +a18 net-_u27-pad1_ net-_u1-pad17_ u27 +a19 net-_u1-pad23_ net-_u11-pad1_ u3 +a20 net-_u11-pad1_ net-_u11-pad2_ u11 +a21 net-_u1-pad22_ net-_u2-pad2_ u2 +a22 net-_u2-pad2_ net-_u6-pad2_ u6 +a23 net-_u1-pad21_ net-_u4-pad2_ u4 +a24 net-_u4-pad2_ net-_u7-pad2_ u7 +a25 net-_u1-pad20_ net-_u5-pad2_ u5 +a26 net-_u5-pad2_ net-_u8-pad2_ u8 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_SL74HC154 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154_Previous_Values.xml b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154_Previous_Values.xml new file mode 100644 index 000000000..f5862e297 --- /dev/null +++ b/library/SubcircuitLibrary/SL74HC154/SC_SL74HC154_Previous_Values.xml @@ -0,0 +1 @@ +d_nord_nord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_nord_inverterd_inverterC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file From 3e44af8234225b8601ead80360ccbade032f50c1 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:01:47 +0530 Subject: [PATCH 17/33] Octal Buffer/Line Driver With 3-State Outputs --- library/SubcircuitLibrary/74ACT11240/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/74ACT11240/analysis diff --git a/library/SubcircuitLibrary/74ACT11240/analysis b/library/SubcircuitLibrary/74ACT11240/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11240/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 35ef839df66f1a69ef2f8d8af84b3afb4bec3ec1 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:02:45 +0530 Subject: [PATCH 18/33] Octal Buffer/Line Driver With 3-State Outputs --- .../74ACT11240/SC_74ACT11240-cache.lib | 73 +++ .../74ACT11240/SC_74ACT11240.cir | 29 + .../74ACT11240/SC_74ACT11240.cir.out | 84 +++ .../74ACT11240/SC_74ACT11240.pro | 73 +++ .../74ACT11240/SC_74ACT11240.sch | 555 ++++++++++++++++++ .../74ACT11240/SC_74ACT11240.sub | 78 +++ .../SC_74ACT11240_Previous_Values.xml | 1 + 7 files changed, 893 insertions(+) create mode 100644 library/SubcircuitLibrary/74ACT11240/SC_74ACT11240-cache.lib create mode 100644 library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.cir create mode 100644 library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.cir.out create mode 100644 library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.pro create mode 100644 library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.sch create mode 100644 library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.sub create mode 100644 library/SubcircuitLibrary/74ACT11240/SC_74ACT11240_Previous_Values.xml diff --git a/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240-cache.lib b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240-cache.lib new file mode 100644 index 000000000..f8261399d --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240-cache.lib @@ -0,0 +1,73 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.cir b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.cir new file mode 100644 index 000000000..359e72bac --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.cir @@ -0,0 +1,29 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_74ACT11240\SC_74ACT11240.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 21:34:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad24_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad23_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_tristate +U4 Net-_U1-Pad22_ Net-_U2-Pad2_ Net-_U4-Pad3_ d_tristate +U5 Net-_U1-Pad21_ Net-_U2-Pad2_ Net-_U5-Pad3_ d_tristate +U6 Net-_U1-Pad20_ Net-_U2-Pad2_ Net-_U10-Pad1_ d_tristate +U11 Net-_U1-Pad13_ Net-_U11-Pad2_ d_inverter +U12 Net-_U1-Pad17_ Net-_U11-Pad2_ Net-_U12-Pad3_ d_tristate +U13 Net-_U1-Pad16_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_tristate +U14 Net-_U1-Pad15_ Net-_U11-Pad2_ Net-_U14-Pad3_ d_tristate +U15 Net-_U1-Pad14_ Net-_U11-Pad2_ Net-_U15-Pad3_ d_tristate +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ ? ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ ? ? Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad24_ PORT +U7 Net-_U3-Pad3_ Net-_U1-Pad1_ d_inverter +U8 Net-_U4-Pad3_ Net-_U1-Pad2_ d_inverter +U9 Net-_U5-Pad3_ Net-_U1-Pad3_ d_inverter +U10 Net-_U10-Pad1_ Net-_U1-Pad4_ d_inverter +U16 Net-_U12-Pad3_ Net-_U1-Pad9_ d_inverter +U17 Net-_U13-Pad3_ Net-_U1-Pad10_ d_inverter +U18 Net-_U14-Pad3_ Net-_U1-Pad11_ d_inverter +U19 Net-_U15-Pad3_ Net-_U1-Pad12_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.cir.out b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.cir.out new file mode 100644 index 000000000..d8951e9f5 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.cir.out @@ -0,0 +1,84 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_74act11240\sc_74act11240.cir + +* u2 net-_u1-pad24_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad23_ net-_u2-pad2_ net-_u3-pad3_ d_tristate +* u4 net-_u1-pad22_ net-_u2-pad2_ net-_u4-pad3_ d_tristate +* u5 net-_u1-pad21_ net-_u2-pad2_ net-_u5-pad3_ d_tristate +* u6 net-_u1-pad20_ net-_u2-pad2_ net-_u10-pad1_ d_tristate +* u11 net-_u1-pad13_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad17_ net-_u11-pad2_ net-_u12-pad3_ d_tristate +* u13 net-_u1-pad16_ net-_u11-pad2_ net-_u13-pad3_ d_tristate +* u14 net-_u1-pad15_ net-_u11-pad2_ net-_u14-pad3_ d_tristate +* u15 net-_u1-pad14_ net-_u11-pad2_ net-_u15-pad3_ d_tristate +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ ? ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ ? ? net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ port +* u7 net-_u3-pad3_ net-_u1-pad1_ d_inverter +* u8 net-_u4-pad3_ net-_u1-pad2_ d_inverter +* u9 net-_u5-pad3_ net-_u1-pad3_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ d_inverter +* u16 net-_u12-pad3_ net-_u1-pad9_ d_inverter +* u17 net-_u13-pad3_ net-_u1-pad10_ d_inverter +* u18 net-_u14-pad3_ net-_u1-pad11_ d_inverter +* u19 net-_u15-pad3_ net-_u1-pad12_ d_inverter +a1 net-_u1-pad24_ net-_u2-pad2_ u2 +a2 net-_u1-pad23_ net-_u2-pad2_ net-_u3-pad3_ u3 +a3 net-_u1-pad22_ net-_u2-pad2_ net-_u4-pad3_ u4 +a4 net-_u1-pad21_ net-_u2-pad2_ net-_u5-pad3_ u5 +a5 net-_u1-pad20_ net-_u2-pad2_ net-_u10-pad1_ u6 +a6 net-_u1-pad13_ net-_u11-pad2_ u11 +a7 net-_u1-pad17_ net-_u11-pad2_ net-_u12-pad3_ u12 +a8 net-_u1-pad16_ net-_u11-pad2_ net-_u13-pad3_ u13 +a9 net-_u1-pad15_ net-_u11-pad2_ net-_u14-pad3_ u14 +a10 net-_u1-pad14_ net-_u11-pad2_ net-_u15-pad3_ u15 +a11 net-_u3-pad3_ net-_u1-pad1_ u7 +a12 net-_u4-pad3_ net-_u1-pad2_ u8 +a13 net-_u5-pad3_ net-_u1-pad3_ u9 +a14 net-_u10-pad1_ net-_u1-pad4_ u10 +a15 net-_u12-pad3_ net-_u1-pad9_ u16 +a16 net-_u13-pad3_ net-_u1-pad10_ u17 +a17 net-_u14-pad3_ net-_u1-pad11_ u18 +a18 net-_u15-pad3_ net-_u1-pad12_ u19 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u3 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.pro b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.sch b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.sch new file mode 100644 index 000000000..878d21002 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.sch @@ -0,0 +1,555 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_74ACT11240-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 68500D79 +P 3100 1450 +F 0 "U2" H 3100 1350 60 0000 C CNN +F 1 "d_inverter" H 3100 1600 60 0000 C CNN +F 2 "" H 3150 1400 60 0000 C CNN +F 3 "" H 3150 1400 60 0000 C CNN + 1 3100 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U3 +U 1 1 68500DD3 +P 3150 2050 +F 0 "U3" H 2900 2300 60 0000 C CNN +F 1 "d_tristate" H 2950 2500 60 0000 C CNN +F 2 "" H 3050 2400 60 0000 C CNN +F 3 "" H 3050 2400 60 0000 C CNN + 1 3150 2050 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U4 +U 1 1 68500E57 +P 3150 2950 +F 0 "U4" H 2900 3200 60 0000 C CNN +F 1 "d_tristate" H 2950 3400 60 0000 C CNN +F 2 "" H 3050 3300 60 0000 C CNN +F 3 "" H 3050 3300 60 0000 C CNN + 1 3150 2950 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U5 +U 1 1 68500E86 +P 3200 3900 +F 0 "U5" H 2950 4150 60 0000 C CNN +F 1 "d_tristate" H 3000 4350 60 0000 C CNN +F 2 "" H 3100 4250 60 0000 C CNN +F 3 "" H 3100 4250 60 0000 C CNN + 1 3200 3900 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U6 +U 1 1 68500EAD +P 3200 4850 +F 0 "U6" H 2950 5100 60 0000 C CNN +F 1 "d_tristate" H 3000 5300 60 0000 C CNN +F 2 "" H 3100 5200 60 0000 C CNN +F 3 "" H 3100 5200 60 0000 C CNN + 1 3200 4850 + 1 0 0 1 +$EndComp +Wire Wire Line + 3400 1450 3850 1450 +Wire Wire Line + 3850 1450 3850 4900 +Wire Wire Line + 3850 2100 3100 2100 +Wire Wire Line + 3850 3000 3100 3000 +Connection ~ 3850 2100 +Wire Wire Line + 3850 3950 3150 3950 +Connection ~ 3850 3000 +Wire Wire Line + 3850 4900 3150 4900 +Connection ~ 3850 3950 +$Comp +L d_inverter U11 +U 1 1 68501264 +P 6100 1450 +F 0 "U11" H 6100 1350 60 0000 C CNN +F 1 "d_inverter" H 6100 1600 60 0000 C CNN +F 2 "" H 6150 1400 60 0000 C CNN +F 3 "" H 6150 1400 60 0000 C CNN + 1 6100 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U12 +U 1 1 6850126A +P 6150 2050 +F 0 "U12" H 5900 2300 60 0000 C CNN +F 1 "d_tristate" H 5950 2500 60 0000 C CNN +F 2 "" H 6050 2400 60 0000 C CNN +F 3 "" H 6050 2400 60 0000 C CNN + 1 6150 2050 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U13 +U 1 1 68501270 +P 6150 2950 +F 0 "U13" H 5900 3200 60 0000 C CNN +F 1 "d_tristate" H 5950 3400 60 0000 C CNN +F 2 "" H 6050 3300 60 0000 C CNN +F 3 "" H 6050 3300 60 0000 C CNN + 1 6150 2950 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U14 +U 1 1 68501276 +P 6200 3900 +F 0 "U14" H 5950 4150 60 0000 C CNN +F 1 "d_tristate" H 6000 4350 60 0000 C CNN +F 2 "" H 6100 4250 60 0000 C CNN +F 3 "" H 6100 4250 60 0000 C CNN + 1 6200 3900 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U15 +U 1 1 6850127C +P 6200 4850 +F 0 "U15" H 5950 5100 60 0000 C CNN +F 1 "d_tristate" H 6000 5300 60 0000 C CNN +F 2 "" H 6100 5200 60 0000 C CNN +F 3 "" H 6100 5200 60 0000 C CNN + 1 6200 4850 + 1 0 0 1 +$EndComp +Wire Wire Line + 6400 1450 6850 1450 +Wire Wire Line + 6850 1450 6850 4900 +Wire Wire Line + 6850 2100 6100 2100 +Wire Wire Line + 6850 3000 6100 3000 +Connection ~ 6850 2100 +Wire Wire Line + 6850 3950 6150 3950 +Connection ~ 6850 3000 +Wire Wire Line + 6850 4900 6150 4900 +Connection ~ 6850 3950 +$Comp +L PORT U1 +U 1 1 68501297 +P 4550 2400 +F 0 "U1" H 4600 2500 30 0000 C CNN +F 1 "PORT" H 4550 2400 30 0000 C CNN +F 2 "" H 4550 2400 60 0000 C CNN +F 3 "" H 4550 2400 60 0000 C CNN + 1 4550 2400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 68501302 +P 4550 3300 +F 0 "U1" H 4600 3400 30 0000 C CNN +F 1 "PORT" H 4550 3300 30 0000 C CNN +F 2 "" H 4550 3300 60 0000 C CNN +F 3 "" H 4550 3300 60 0000 C CNN + 2 4550 3300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 68501349 +P 4600 4250 +F 0 "U1" H 4650 4350 30 0000 C CNN +F 1 "PORT" H 4600 4250 30 0000 C CNN +F 2 "" H 4600 4250 60 0000 C CNN +F 3 "" H 4600 4250 60 0000 C CNN + 3 4600 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 685013AA +P 4600 5200 +F 0 "U1" H 4650 5300 30 0000 C CNN +F 1 "PORT" H 4600 5200 30 0000 C CNN +F 2 "" H 4600 5200 60 0000 C CNN +F 3 "" H 4600 5200 60 0000 C CNN + 4 4600 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 6850140D +P 1450 2500 +F 0 "U1" H 1500 2600 30 0000 C CNN +F 1 "PORT" H 1450 2500 30 0000 C CNN +F 2 "" H 1450 2500 60 0000 C CNN +F 3 "" H 1450 2500 60 0000 C CNN + 5 1450 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68501476 +P 1450 2900 +F 0 "U1" H 1500 3000 30 0000 C CNN +F 1 "PORT" H 1450 2900 30 0000 C CNN +F 2 "" H 1450 2900 60 0000 C CNN +F 3 "" H 1450 2900 60 0000 C CNN + 6 1450 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 685014B9 +P 1450 3350 +F 0 "U1" H 1500 3450 30 0000 C CNN +F 1 "PORT" H 1450 3350 30 0000 C CNN +F 2 "" H 1450 3350 60 0000 C CNN +F 3 "" H 1450 3350 60 0000 C CNN + 7 1450 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685014FE +P 1450 3800 +F 0 "U1" H 1500 3900 30 0000 C CNN +F 1 "PORT" H 1450 3800 30 0000 C CNN +F 2 "" H 1450 3800 60 0000 C CNN +F 3 "" H 1450 3800 60 0000 C CNN + 8 1450 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6850154F +P 7550 2400 +F 0 "U1" H 7600 2500 30 0000 C CNN +F 1 "PORT" H 7550 2400 30 0000 C CNN +F 2 "" H 7550 2400 60 0000 C CNN +F 3 "" H 7550 2400 60 0000 C CNN + 9 7550 2400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 685015D8 +P 7550 3300 +F 0 "U1" H 7600 3400 30 0000 C CNN +F 1 "PORT" H 7550 3300 30 0000 C CNN +F 2 "" H 7550 3300 60 0000 C CNN +F 3 "" H 7550 3300 60 0000 C CNN + 10 7550 3300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6850165D +P 7600 4250 +F 0 "U1" H 7650 4350 30 0000 C CNN +F 1 "PORT" H 7600 4250 30 0000 C CNN +F 2 "" H 7600 4250 60 0000 C CNN +F 3 "" H 7600 4250 60 0000 C CNN + 11 7600 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 685016DE +P 7600 5200 +F 0 "U1" H 7650 5300 30 0000 C CNN +F 1 "PORT" H 7600 5200 30 0000 C CNN +F 2 "" H 7600 5200 60 0000 C CNN +F 3 "" H 7600 5200 60 0000 C CNN + 12 7600 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 68501755 +P 5550 1450 +F 0 "U1" H 5600 1550 30 0000 C CNN +F 1 "PORT" H 5550 1450 30 0000 C CNN +F 2 "" H 5550 1450 60 0000 C CNN +F 3 "" H 5550 1450 60 0000 C CNN + 13 5550 1450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 685017DC +P 5350 5200 +F 0 "U1" H 5400 5300 30 0000 C CNN +F 1 "PORT" H 5350 5200 30 0000 C CNN +F 2 "" H 5350 5200 60 0000 C CNN +F 3 "" H 5350 5200 60 0000 C CNN + 14 5350 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 68501897 +P 5350 4250 +F 0 "U1" H 5400 4350 30 0000 C CNN +F 1 "PORT" H 5350 4250 30 0000 C CNN +F 2 "" H 5350 4250 60 0000 C CNN +F 3 "" H 5350 4250 60 0000 C CNN + 15 5350 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 6850190C +P 5300 3300 +F 0 "U1" H 5350 3400 30 0000 C CNN +F 1 "PORT" H 5300 3300 30 0000 C CNN +F 2 "" H 5300 3300 60 0000 C CNN +F 3 "" H 5300 3300 60 0000 C CNN + 16 5300 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 17 1 6850197D +P 5300 2400 +F 0 "U1" H 5350 2500 30 0000 C CNN +F 1 "PORT" H 5300 2400 30 0000 C CNN +F 2 "" H 5300 2400 60 0000 C CNN +F 3 "" H 5300 2400 60 0000 C CNN + 17 5300 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 18 1 685019E8 +P 1450 4250 +F 0 "U1" H 1500 4350 30 0000 C CNN +F 1 "PORT" H 1450 4250 30 0000 C CNN +F 2 "" H 1450 4250 60 0000 C CNN +F 3 "" H 1450 4250 60 0000 C CNN + 18 1450 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 19 1 68501A6D +P 1450 4650 +F 0 "U1" H 1500 4750 30 0000 C CNN +F 1 "PORT" H 1450 4650 30 0000 C CNN +F 2 "" H 1450 4650 60 0000 C CNN +F 3 "" H 1450 4650 60 0000 C CNN + 19 1450 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 20 1 68501ADC +P 2350 5200 +F 0 "U1" H 2400 5300 30 0000 C CNN +F 1 "PORT" H 2350 5200 30 0000 C CNN +F 2 "" H 2350 5200 60 0000 C CNN +F 3 "" H 2350 5200 60 0000 C CNN + 20 2350 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 21 1 68501B89 +P 2350 4250 +F 0 "U1" H 2400 4350 30 0000 C CNN +F 1 "PORT" H 2350 4250 30 0000 C CNN +F 2 "" H 2350 4250 60 0000 C CNN +F 3 "" H 2350 4250 60 0000 C CNN + 21 2350 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 22 1 68501C1E +P 2300 3300 +F 0 "U1" H 2350 3400 30 0000 C CNN +F 1 "PORT" H 2300 3300 30 0000 C CNN +F 2 "" H 2300 3300 60 0000 C CNN +F 3 "" H 2300 3300 60 0000 C CNN + 22 2300 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 23 1 68501CA1 +P 2300 2400 +F 0 "U1" H 2350 2500 30 0000 C CNN +F 1 "PORT" H 2300 2400 30 0000 C CNN +F 2 "" H 2300 2400 60 0000 C CNN +F 3 "" H 2300 2400 60 0000 C CNN + 23 2300 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 24 1 68501D3C +P 2550 1450 +F 0 "U1" H 2600 1550 30 0000 C CNN +F 1 "PORT" H 2550 1450 30 0000 C CNN +F 2 "" H 2550 1450 60 0000 C CNN +F 3 "" H 2550 1450 60 0000 C CNN + 24 2550 1450 + 1 0 0 -1 +$EndComp +NoConn ~ 1700 2500 +NoConn ~ 1700 2900 +NoConn ~ 1700 3350 +NoConn ~ 1700 3800 +NoConn ~ 1700 4250 +NoConn ~ 1700 4650 +$Comp +L d_inverter U7 +U 1 1 6850190E +P 4000 2400 +F 0 "U7" H 4000 2300 60 0000 C CNN +F 1 "d_inverter" H 4000 2550 60 0000 C CNN +F 2 "" H 4050 2350 60 0000 C CNN +F 3 "" H 4050 2350 60 0000 C CNN + 1 4000 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 68501995 +P 4000 3300 +F 0 "U8" H 4000 3200 60 0000 C CNN +F 1 "d_inverter" H 4000 3450 60 0000 C CNN +F 2 "" H 4050 3250 60 0000 C CNN +F 3 "" H 4050 3250 60 0000 C CNN + 1 4000 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 68501A4E +P 4050 4250 +F 0 "U9" H 4050 4150 60 0000 C CNN +F 1 "d_inverter" H 4050 4400 60 0000 C CNN +F 2 "" H 4100 4200 60 0000 C CNN +F 3 "" H 4100 4200 60 0000 C CNN + 1 4050 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 68501B0A +P 4050 5200 +F 0 "U10" H 4050 5100 60 0000 C CNN +F 1 "d_inverter" H 4050 5350 60 0000 C CNN +F 2 "" H 4100 5150 60 0000 C CNN +F 3 "" H 4100 5150 60 0000 C CNN + 1 4050 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6850200D +P 7000 2400 +F 0 "U16" H 7000 2300 60 0000 C CNN +F 1 "d_inverter" H 7000 2550 60 0000 C CNN +F 2 "" H 7050 2350 60 0000 C CNN +F 3 "" H 7050 2350 60 0000 C CNN + 1 7000 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 6850208A +P 7000 3300 +F 0 "U17" H 7000 3200 60 0000 C CNN +F 1 "d_inverter" H 7000 3450 60 0000 C CNN +F 2 "" H 7050 3250 60 0000 C CNN +F 3 "" H 7050 3250 60 0000 C CNN + 1 7000 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 685021DF +P 7050 4250 +F 0 "U18" H 7050 4150 60 0000 C CNN +F 1 "d_inverter" H 7050 4400 60 0000 C CNN +F 2 "" H 7100 4200 60 0000 C CNN +F 3 "" H 7100 4200 60 0000 C CNN + 1 7050 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 685022BD +P 7050 5200 +F 0 "U19" H 7050 5100 60 0000 C CNN +F 1 "d_inverter" H 7050 5350 60 0000 C CNN +F 2 "" H 7100 5150 60 0000 C CNN +F 3 "" H 7100 5150 60 0000 C CNN + 1 7050 5200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.sub b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.sub new file mode 100644 index 000000000..c89a34de8 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.sub @@ -0,0 +1,78 @@ +* Subcircuit SC_74ACT11240 +.subckt SC_74ACT11240 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ ? ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ ? ? net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ +* c:\fossee2\esim\library\subcircuitlibrary\sc_74act11240\sc_74act11240.cir +* u2 net-_u1-pad24_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad23_ net-_u2-pad2_ net-_u3-pad3_ d_tristate +* u4 net-_u1-pad22_ net-_u2-pad2_ net-_u4-pad3_ d_tristate +* u5 net-_u1-pad21_ net-_u2-pad2_ net-_u5-pad3_ d_tristate +* u6 net-_u1-pad20_ net-_u2-pad2_ net-_u10-pad1_ d_tristate +* u11 net-_u1-pad13_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad17_ net-_u11-pad2_ net-_u12-pad3_ d_tristate +* u13 net-_u1-pad16_ net-_u11-pad2_ net-_u13-pad3_ d_tristate +* u14 net-_u1-pad15_ net-_u11-pad2_ net-_u14-pad3_ d_tristate +* u15 net-_u1-pad14_ net-_u11-pad2_ net-_u15-pad3_ d_tristate +* u7 net-_u3-pad3_ net-_u1-pad1_ d_inverter +* u8 net-_u4-pad3_ net-_u1-pad2_ d_inverter +* u9 net-_u5-pad3_ net-_u1-pad3_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ d_inverter +* u16 net-_u12-pad3_ net-_u1-pad9_ d_inverter +* u17 net-_u13-pad3_ net-_u1-pad10_ d_inverter +* u18 net-_u14-pad3_ net-_u1-pad11_ d_inverter +* u19 net-_u15-pad3_ net-_u1-pad12_ d_inverter +a1 net-_u1-pad24_ net-_u2-pad2_ u2 +a2 net-_u1-pad23_ net-_u2-pad2_ net-_u3-pad3_ u3 +a3 net-_u1-pad22_ net-_u2-pad2_ net-_u4-pad3_ u4 +a4 net-_u1-pad21_ net-_u2-pad2_ net-_u5-pad3_ u5 +a5 net-_u1-pad20_ net-_u2-pad2_ net-_u10-pad1_ u6 +a6 net-_u1-pad13_ net-_u11-pad2_ u11 +a7 net-_u1-pad17_ net-_u11-pad2_ net-_u12-pad3_ u12 +a8 net-_u1-pad16_ net-_u11-pad2_ net-_u13-pad3_ u13 +a9 net-_u1-pad15_ net-_u11-pad2_ net-_u14-pad3_ u14 +a10 net-_u1-pad14_ net-_u11-pad2_ net-_u15-pad3_ u15 +a11 net-_u3-pad3_ net-_u1-pad1_ u7 +a12 net-_u4-pad3_ net-_u1-pad2_ u8 +a13 net-_u5-pad3_ net-_u1-pad3_ u9 +a14 net-_u10-pad1_ net-_u1-pad4_ u10 +a15 net-_u12-pad3_ net-_u1-pad9_ u16 +a16 net-_u13-pad3_ net-_u1-pad10_ u17 +a17 net-_u14-pad3_ net-_u1-pad11_ u18 +a18 net-_u15-pad3_ net-_u1-pad12_ u19 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u3 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_74ACT11240 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240_Previous_Values.xml b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240_Previous_Values.xml new file mode 100644 index 000000000..c7dbfafb7 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11240/SC_74ACT11240_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_tristated_tristated_tristated_tristated_inverterd_tristated_tristated_tristated_tristated_inverterd_tristated_tristated_tristated_tristated_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file From 218d857910be8b40efba802b2be726d902f0015f Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:04:19 +0530 Subject: [PATCH 19/33] And-Or-Invert Gates --- library/SubcircuitLibrary/SN74LS51/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/SN74LS51/analysis diff --git a/library/SubcircuitLibrary/SN74LS51/analysis b/library/SubcircuitLibrary/SN74LS51/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS51/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 69dfb463f72d1e18b5d7202a702e92cfd8778517 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:05:30 +0530 Subject: [PATCH 20/33] And-Or-Invert Gates --- .../SN74LS51/SC_SN74LS51-cache.lib | 98 ++++++ .../SN74LS51/SC_SN74LS51.cir | 17 + .../SN74LS51/SC_SN74LS51.cir.out | 31 ++ .../SN74LS51/SC_SN74LS51.pro | 73 +++++ .../SN74LS51/SC_SN74LS51.sch | 299 ++++++++++++++++++ .../SN74LS51/SC_SN74LS51.sub | 25 ++ .../SN74LS51/SC_SN74LS51_Previous_Values.xml | 1 + 7 files changed, 544 insertions(+) create mode 100644 library/SubcircuitLibrary/SN74LS51/SC_SN74LS51-cache.lib create mode 100644 library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.cir create mode 100644 library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.cir.out create mode 100644 library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.pro create mode 100644 library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.sch create mode 100644 library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.sub create mode 100644 library/SubcircuitLibrary/SN74LS51/SC_SN74LS51_Previous_Values.xml diff --git a/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51-cache.lib b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51-cache.lib new file mode 100644 index 000000000..480bed840 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.cir b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.cir new file mode 100644 index 000000000..60fc8fd7c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_SN74LS51\SC_SN74LS51.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 12:25:05 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and +X2 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U4-Pad2_ 3_and +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and +U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U1-Pad8_ d_nor +U5 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.cir.out b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.cir.out new file mode 100644 index 000000000..a92e18a3b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.cir.out @@ -0,0 +1,31 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn74ls51\sc_sn74ls51.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and +x2 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u4-pad2_ 3_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u1-pad8_ d_nor +* u5 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad6_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a3 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u1-pad8_ u4 +a4 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad6_ u5 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.pro b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.sch b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.sch new file mode 100644 index 000000000..fdd93fe0c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.sch @@ -0,0 +1,299 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_SN74LS51-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 68510C76 +P 4200 1700 +F 0 "X1" H 4300 1650 60 0000 C CNN +F 1 "3_and" H 4350 1850 60 0000 C CNN +F 2 "" H 4200 1700 60 0000 C CNN +F 3 "" H 4200 1700 60 0000 C CNN + 1 4200 1700 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 68510CD2 +P 4200 2350 +F 0 "X2" H 4300 2300 60 0000 C CNN +F 1 "3_and" H 4350 2500 60 0000 C CNN +F 2 "" H 4200 2350 60 0000 C CNN +F 3 "" H 4200 2350 60 0000 C CNN + 1 4200 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 68510D2F +P 4300 3300 +F 0 "U2" H 4300 3300 60 0000 C CNN +F 1 "d_and" H 4350 3400 60 0000 C CNN +F 2 "" H 4300 3300 60 0000 C CNN +F 3 "" H 4300 3300 60 0000 C CNN + 1 4300 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 68510D82 +P 4300 3900 +F 0 "U3" H 4300 3900 60 0000 C CNN +F 1 "d_and" H 4350 4000 60 0000 C CNN +F 2 "" H 4300 3900 60 0000 C CNN +F 3 "" H 4300 3900 60 0000 C CNN + 1 4300 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U4 +U 1 1 68510DC9 +P 5500 2000 +F 0 "U4" H 5500 2000 60 0000 C CNN +F 1 "d_nor" H 5550 2100 60 0000 C CNN +F 2 "" H 5500 2000 60 0000 C CNN +F 3 "" H 5500 2000 60 0000 C CNN + 1 5500 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U5 +U 1 1 68510E0E +P 5550 3550 +F 0 "U5" H 5550 3550 60 0000 C CNN +F 1 "d_nor" H 5600 3650 60 0000 C CNN +F 2 "" H 5550 3550 60 0000 C CNN +F 3 "" H 5550 3550 60 0000 C CNN + 1 5550 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 1650 5050 1650 +Wire Wire Line + 5050 1650 5050 1900 +Wire Wire Line + 5050 2000 5050 2300 +Wire Wire Line + 5050 2300 4700 2300 +Wire Wire Line + 4750 3250 5100 3250 +Wire Wire Line + 5100 3250 5100 3450 +Wire Wire Line + 5100 3550 5100 3850 +Wire Wire Line + 5100 3850 4750 3850 +$Comp +L PORT U1 +U 1 1 685111CB +P 3600 1550 +F 0 "U1" H 3650 1650 30 0000 C CNN +F 1 "PORT" H 3600 1550 30 0000 C CNN +F 2 "" H 3600 1550 60 0000 C CNN +F 3 "" H 3600 1550 60 0000 C CNN + 1 3600 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6851121C +P 3600 3200 +F 0 "U1" H 3650 3300 30 0000 C CNN +F 1 "PORT" H 3600 3200 30 0000 C CNN +F 2 "" H 3600 3200 60 0000 C CNN +F 3 "" H 3600 3200 60 0000 C CNN + 2 3600 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6851126B +P 3850 3550 +F 0 "U1" H 3900 3650 30 0000 C CNN +F 1 "PORT" H 3850 3550 30 0000 C CNN +F 2 "" H 3850 3550 60 0000 C CNN +F 3 "" H 3850 3550 60 0000 C CNN + 3 3850 3550 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 685112C0 +P 3600 3800 +F 0 "U1" H 3650 3900 30 0000 C CNN +F 1 "PORT" H 3600 3800 30 0000 C CNN +F 2 "" H 3600 3800 60 0000 C CNN +F 3 "" H 3600 3800 60 0000 C CNN + 4 3600 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 685112EB +P 3850 4150 +F 0 "U1" H 3900 4250 30 0000 C CNN +F 1 "PORT" H 3850 4150 30 0000 C CNN +F 2 "" H 3850 4150 60 0000 C CNN +F 3 "" H 3850 4150 60 0000 C CNN + 5 3850 4150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 68511342 +P 6250 3500 +F 0 "U1" H 6300 3600 30 0000 C CNN +F 1 "PORT" H 6250 3500 30 0000 C CNN +F 2 "" H 6250 3500 60 0000 C CNN +F 3 "" H 6250 3500 60 0000 C CNN + 6 6250 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 685117F5 +P 3700 4800 +F 0 "U1" H 3750 4900 30 0000 C CNN +F 1 "PORT" H 3700 4800 30 0000 C CNN +F 2 "" H 3700 4800 60 0000 C CNN +F 3 "" H 3700 4800 60 0000 C CNN + 7 3700 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6851187E +P 6200 1950 +F 0 "U1" H 6250 2050 30 0000 C CNN +F 1 "PORT" H 6200 1950 30 0000 C CNN +F 2 "" H 6200 1950 60 0000 C CNN +F 3 "" H 6200 1950 60 0000 C CNN + 8 6200 1950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 685118FB +P 3600 2200 +F 0 "U1" H 3650 2300 30 0000 C CNN +F 1 "PORT" H 3600 2200 30 0000 C CNN +F 2 "" H 3600 2200 60 0000 C CNN +F 3 "" H 3600 2200 60 0000 C CNN + 9 3600 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68511978 +P 3300 2300 +F 0 "U1" H 3350 2400 30 0000 C CNN +F 1 "PORT" H 3300 2300 30 0000 C CNN +F 2 "" H 3300 2300 60 0000 C CNN +F 3 "" H 3300 2300 60 0000 C CNN + 10 3300 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 685119E7 +P 3850 2650 +F 0 "U1" H 3900 2750 30 0000 C CNN +F 1 "PORT" H 3850 2650 30 0000 C CNN +F 2 "" H 3850 2650 60 0000 C CNN +F 3 "" H 3850 2650 60 0000 C CNN + 11 3850 2650 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 68511A46 +P 3250 1650 +F 0 "U1" H 3300 1750 30 0000 C CNN +F 1 "PORT" H 3250 1650 30 0000 C CNN +F 2 "" H 3250 1650 60 0000 C CNN +F 3 "" H 3250 1650 60 0000 C CNN + 12 3250 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 68511AD3 +P 3850 2000 +F 0 "U1" H 3900 2100 30 0000 C CNN +F 1 "PORT" H 3850 2000 30 0000 C CNN +F 2 "" H 3850 2000 60 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 13 3850 2000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 68511B54 +P 3700 5100 +F 0 "U1" H 3750 5200 30 0000 C CNN +F 1 "PORT" H 3700 5100 30 0000 C CNN +F 2 "" H 3700 5100 60 0000 C CNN +F 3 "" H 3700 5100 60 0000 C CNN + 14 3700 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 1650 3850 1650 +Wire Wire Line + 3550 2300 3850 2300 +NoConn ~ 3950 4800 +NoConn ~ 3950 5100 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.sub b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.sub new file mode 100644 index 000000000..6eee4b67a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51.sub @@ -0,0 +1,25 @@ +* Subcircuit SC_SN74LS51 +.subckt SC_SN74LS51 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn74ls51\sc_sn74ls51.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and +x2 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u4-pad2_ 3_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u1-pad8_ d_nor +* u5 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad6_ d_nor +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a3 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u1-pad8_ u4 +a4 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad6_ u5 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_SN74LS51 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51_Previous_Values.xml new file mode 100644 index 000000000..5d366745c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS51/SC_SN74LS51_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsmsd_andd_andd_nord_norC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_and \ No newline at end of file From 62c256e8e74369b767273ca0e02a1f8715ed8a80 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:07:06 +0530 Subject: [PATCH 21/33] Octal Bus Transceiver With 3 State Outputs (Non Inverted) --- library/SubcircuitLibrary/M74HCT245/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/M74HCT245/analysis diff --git a/library/SubcircuitLibrary/M74HCT245/analysis b/library/SubcircuitLibrary/M74HCT245/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/M74HCT245/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 659238ff53f53e2f3e6e531509c35a148d318ce7 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:08:28 +0530 Subject: [PATCH 22/33] Octal Bus Transceiver With 3 State Outputs Non-Inverted --- .../M74HCT245/SC_M74HCT245-cache.lib | 109 +++ .../M74HCT245/SC_M74HCT245.cir | 30 + .../M74HCT245/SC_M74HCT245.cir.out | 88 +++ .../M74HCT245/SC_M74HCT245.pro | 73 ++ .../M74HCT245/SC_M74HCT245.sch | 644 ++++++++++++++++++ .../M74HCT245/SC_M74HCT245.sub | 82 +++ .../SC_M74HCT245_Previous_Values.xml | 1 + 7 files changed, 1027 insertions(+) create mode 100644 library/SubcircuitLibrary/M74HCT245/SC_M74HCT245-cache.lib create mode 100644 library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.cir create mode 100644 library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.cir.out create mode 100644 library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.pro create mode 100644 library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.sch create mode 100644 library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.sub create mode 100644 library/SubcircuitLibrary/M74HCT245/SC_M74HCT245_Previous_Values.xml diff --git a/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245-cache.lib b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245-cache.lib new file mode 100644 index 000000000..30075cc81 --- /dev/null +++ b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.cir b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.cir new file mode 100644 index 000000000..8402788e6 --- /dev/null +++ b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.cir @@ -0,0 +1,30 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_M74HCT245\SC_M74HCT245.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/18/25 17:39:10 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U1-Pad4_ Net-_U10-Pad2_ Net-_U1-Pad16_ d_tristate +U8 Net-_U15-Pad3_ Net-_U10-Pad2_ Net-_U1-Pad15_ d_tristate +U9 Net-_U1-Pad6_ Net-_U10-Pad2_ Net-_U1-Pad14_ d_tristate +U5 Net-_U1-Pad7_ Net-_U10-Pad2_ Net-_U1-Pad13_ d_tristate +U6 Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U1-Pad12_ d_tristate +U7 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U1-Pad11_ d_tristate +U3 Net-_U1-Pad3_ Net-_U10-Pad2_ Net-_U1-Pad17_ d_tristate +U10 Net-_U1-Pad2_ Net-_U10-Pad2_ Net-_U1-Pad18_ d_tristate +U16 Net-_U1-Pad16_ Net-_U12-Pad3_ Net-_U1-Pad4_ d_tristate +U15 Net-_U1-Pad15_ Net-_U12-Pad3_ Net-_U15-Pad3_ d_tristate +U17 Net-_U1-Pad14_ Net-_U12-Pad3_ Net-_U1-Pad6_ d_tristate +U18 Net-_U1-Pad13_ Net-_U12-Pad3_ Net-_U1-Pad7_ d_tristate +U19 Net-_U1-Pad12_ Net-_U12-Pad3_ Net-_U1-Pad8_ d_tristate +U20 Net-_U1-Pad11_ Net-_U12-Pad3_ Net-_U1-Pad9_ d_tristate +U14 Net-_U1-Pad17_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_tristate +U13 Net-_U1-Pad18_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_tristate +U2 Net-_U1-Pad19_ Net-_U11-Pad2_ d_inverter +U11 Net-_U1-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad2_ d_and +U12 Net-_U1-Pad19_ Net-_U1-Pad1_ Net-_U12-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ ? Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ ? Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.cir.out b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.cir.out new file mode 100644 index 000000000..dd78fa43e --- /dev/null +++ b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.cir.out @@ -0,0 +1,88 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_m74hct245\sc_m74hct245.cir + +* u4 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad16_ d_tristate +* u8 net-_u15-pad3_ net-_u10-pad2_ net-_u1-pad15_ d_tristate +* u9 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad14_ d_tristate +* u5 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad13_ d_tristate +* u6 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad12_ d_tristate +* u7 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad11_ d_tristate +* u3 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad17_ d_tristate +* u10 net-_u1-pad2_ net-_u10-pad2_ net-_u1-pad18_ d_tristate +* u16 net-_u1-pad16_ net-_u12-pad3_ net-_u1-pad4_ d_tristate +* u15 net-_u1-pad15_ net-_u12-pad3_ net-_u15-pad3_ d_tristate +* u17 net-_u1-pad14_ net-_u12-pad3_ net-_u1-pad6_ d_tristate +* u18 net-_u1-pad13_ net-_u12-pad3_ net-_u1-pad7_ d_tristate +* u19 net-_u1-pad12_ net-_u12-pad3_ net-_u1-pad8_ d_tristate +* u20 net-_u1-pad11_ net-_u12-pad3_ net-_u1-pad9_ d_tristate +* u14 net-_u1-pad17_ net-_u12-pad3_ net-_u1-pad3_ d_tristate +* u13 net-_u1-pad18_ net-_u12-pad3_ net-_u1-pad2_ d_tristate +* u2 net-_u1-pad19_ net-_u11-pad2_ d_inverter +* u11 net-_u1-pad1_ net-_u11-pad2_ net-_u10-pad2_ d_and +* u12 net-_u1-pad19_ net-_u1-pad1_ net-_u12-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? port +a1 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad16_ u4 +a2 net-_u15-pad3_ net-_u10-pad2_ net-_u1-pad15_ u8 +a3 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad14_ u9 +a4 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad13_ u5 +a5 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad12_ u6 +a6 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad11_ u7 +a7 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad17_ u3 +a8 net-_u1-pad2_ net-_u10-pad2_ net-_u1-pad18_ u10 +a9 net-_u1-pad16_ net-_u12-pad3_ net-_u1-pad4_ u16 +a10 net-_u1-pad15_ net-_u12-pad3_ net-_u15-pad3_ u15 +a11 net-_u1-pad14_ net-_u12-pad3_ net-_u1-pad6_ u17 +a12 net-_u1-pad13_ net-_u12-pad3_ net-_u1-pad7_ u18 +a13 net-_u1-pad12_ net-_u12-pad3_ net-_u1-pad8_ u19 +a14 net-_u1-pad11_ net-_u12-pad3_ net-_u1-pad9_ u20 +a15 net-_u1-pad17_ net-_u12-pad3_ net-_u1-pad3_ u14 +a16 net-_u1-pad18_ net-_u12-pad3_ net-_u1-pad2_ u13 +a17 net-_u1-pad19_ net-_u11-pad2_ u2 +a18 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u10-pad2_ u11 +a19 [net-_u1-pad19_ net-_u1-pad1_ ] net-_u12-pad3_ u12 +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u7 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u3 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u16 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.pro b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.sch b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.sch new file mode 100644 index 000000000..9df904e9b --- /dev/null +++ b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.sch @@ -0,0 +1,644 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_tristate U4 +U 1 1 6852A300 +P 2450 2900 +F 0 "U4" H 2200 3150 60 0000 C CNN +F 1 "d_tristate" H 2250 3350 60 0000 C CNN +F 2 "" H 2350 3250 60 0000 C CNN +F 3 "" H 2350 3250 60 0000 C CNN + 1 2450 2900 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U8 +U 1 1 6852A361 +P 2500 3700 +F 0 "U8" H 2250 3950 60 0000 C CNN +F 1 "d_tristate" H 2300 4150 60 0000 C CNN +F 2 "" H 2400 4050 60 0000 C CNN +F 3 "" H 2400 4050 60 0000 C CNN + 1 2500 3700 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U9 +U 1 1 6852A3E5 +P 2500 4600 +F 0 "U9" H 2250 4850 60 0000 C CNN +F 1 "d_tristate" H 2300 5050 60 0000 C CNN +F 2 "" H 2400 4950 60 0000 C CNN +F 3 "" H 2400 4950 60 0000 C CNN + 1 2500 4600 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U5 +U 1 1 6852A411 +P 2450 5350 +F 0 "U5" H 2200 5600 60 0000 C CNN +F 1 "d_tristate" H 2250 5800 60 0000 C CNN +F 2 "" H 2350 5700 60 0000 C CNN +F 3 "" H 2350 5700 60 0000 C CNN + 1 2450 5350 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U6 +U 1 1 6852A444 +P 2450 6100 +F 0 "U6" H 2200 6350 60 0000 C CNN +F 1 "d_tristate" H 2250 6550 60 0000 C CNN +F 2 "" H 2350 6450 60 0000 C CNN +F 3 "" H 2350 6450 60 0000 C CNN + 1 2450 6100 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U7 +U 1 1 6852A47C +P 2450 6850 +F 0 "U7" H 2200 7100 60 0000 C CNN +F 1 "d_tristate" H 2250 7300 60 0000 C CNN +F 2 "" H 2350 7200 60 0000 C CNN +F 3 "" H 2350 7200 60 0000 C CNN + 1 2450 6850 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U3 +U 1 1 6852A529 +P 2450 2050 +F 0 "U3" H 2200 2300 60 0000 C CNN +F 1 "d_tristate" H 2250 2500 60 0000 C CNN +F 2 "" H 2350 2400 60 0000 C CNN +F 3 "" H 2350 2400 60 0000 C CNN + 1 2450 2050 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U10 +U 1 1 6852A573 +P 2550 1200 +F 0 "U10" H 2300 1450 60 0000 C CNN +F 1 "d_tristate" H 2350 1650 60 0000 C CNN +F 2 "" H 2450 1550 60 0000 C CNN +F 3 "" H 2450 1550 60 0000 C CNN + 1 2550 1200 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U16 +U 1 1 6852A79A +P 4600 3150 +F 0 "U16" H 4350 3400 60 0000 C CNN +F 1 "d_tristate" H 4400 3600 60 0000 C CNN +F 2 "" H 4500 3500 60 0000 C CNN +F 3 "" H 4500 3500 60 0000 C CNN + 1 4600 3150 + -1 0 0 1 +$EndComp +$Comp +L d_tristate U15 +U 1 1 6852A7A1 +P 4550 3950 +F 0 "U15" H 4300 4200 60 0000 C CNN +F 1 "d_tristate" H 4350 4400 60 0000 C CNN +F 2 "" H 4450 4300 60 0000 C CNN +F 3 "" H 4450 4300 60 0000 C CNN + 1 4550 3950 + -1 0 0 1 +$EndComp +$Comp +L d_tristate U17 +U 1 1 6852A7A8 +P 4650 4750 +F 0 "U17" H 4400 5000 60 0000 C CNN +F 1 "d_tristate" H 4450 5200 60 0000 C CNN +F 2 "" H 4550 5100 60 0000 C CNN +F 3 "" H 4550 5100 60 0000 C CNN + 1 4650 4750 + -1 0 0 1 +$EndComp +$Comp +L d_tristate U18 +U 1 1 6852A7AF +P 4700 5500 +F 0 "U18" H 4450 5750 60 0000 C CNN +F 1 "d_tristate" H 4500 5950 60 0000 C CNN +F 2 "" H 4600 5850 60 0000 C CNN +F 3 "" H 4600 5850 60 0000 C CNN + 1 4700 5500 + -1 0 0 1 +$EndComp +$Comp +L d_tristate U19 +U 1 1 6852A7B6 +P 4750 6350 +F 0 "U19" H 4500 6600 60 0000 C CNN +F 1 "d_tristate" H 4550 6800 60 0000 C CNN +F 2 "" H 4650 6700 60 0000 C CNN +F 3 "" H 4650 6700 60 0000 C CNN + 1 4750 6350 + -1 0 0 1 +$EndComp +$Comp +L d_tristate U20 +U 1 1 6852A7BD +P 4750 7100 +F 0 "U20" H 4500 7350 60 0000 C CNN +F 1 "d_tristate" H 4550 7550 60 0000 C CNN +F 2 "" H 4650 7450 60 0000 C CNN +F 3 "" H 4650 7450 60 0000 C CNN + 1 4750 7100 + -1 0 0 1 +$EndComp +$Comp +L d_tristate U14 +U 1 1 6852A7C4 +P 4400 2300 +F 0 "U14" H 4150 2550 60 0000 C CNN +F 1 "d_tristate" H 4200 2750 60 0000 C CNN +F 2 "" H 4300 2650 60 0000 C CNN +F 3 "" H 4300 2650 60 0000 C CNN + 1 4400 2300 + -1 0 0 1 +$EndComp +$Comp +L d_tristate U13 +U 1 1 6852A7CB +P 4400 1400 +F 0 "U13" H 4150 1650 60 0000 C CNN +F 1 "d_tristate" H 4200 1850 60 0000 C CNN +F 2 "" H 4300 1750 60 0000 C CNN +F 3 "" H 4300 1750 60 0000 C CNN + 1 4400 1400 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6852AB06 +P 1850 950 +F 0 "U2" H 1850 850 60 0000 C CNN +F 1 "d_inverter" H 1850 1100 60 0000 C CNN +F 2 "" H 1900 900 60 0000 C CNN +F 3 "" H 1900 900 60 0000 C CNN + 1 1850 950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 6852AB5F +P 2600 950 +F 0 "U11" H 2600 950 60 0000 C CNN +F 1 "d_and" H 2650 1050 60 0000 C CNN +F 2 "" H 2600 950 60 0000 C CNN +F 3 "" H 2600 950 60 0000 C CNN + 1 2600 950 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U12 +U 1 1 6852AC00 +P 4400 850 +F 0 "U12" H 4400 850 60 0000 C CNN +F 1 "d_nor" H 4450 950 60 0000 C CNN +F 2 "" H 4400 850 60 0000 C CNN +F 3 "" H 4400 850 60 0000 C CNN + 1 4400 850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4850 850 4850 600 +Wire Wire Line + 4850 600 2150 600 +Wire Wire Line + 2150 600 2150 850 +Wire Wire Line + 3050 900 3050 1250 +Wire Wire Line + 2500 1250 3450 1250 +Wire Wire Line + 3450 1250 3450 6900 +Wire Wire Line + 3450 2100 2400 2100 +Connection ~ 3050 1250 +Wire Wire Line + 3450 2950 2400 2950 +Connection ~ 3450 2100 +Wire Wire Line + 3450 3750 2450 3750 +Connection ~ 3450 2950 +Wire Wire Line + 3450 4650 2450 4650 +Connection ~ 3450 3750 +Wire Wire Line + 3450 5400 2400 5400 +Connection ~ 3450 4650 +Wire Wire Line + 3450 6150 2400 6150 +Connection ~ 3450 5400 +Wire Wire Line + 3450 6900 2400 6900 +Connection ~ 3450 6150 +Wire Wire Line + 3950 900 3600 900 +Wire Wire Line + 3600 900 3600 7150 +Wire Wire Line + 3600 1450 4450 1450 +Wire Wire Line + 3600 2350 4450 2350 +Connection ~ 3600 1450 +Wire Wire Line + 3600 3200 4650 3200 +Connection ~ 3600 2350 +Wire Wire Line + 3600 4000 4600 4000 +Connection ~ 3600 3200 +Wire Wire Line + 3600 4800 4700 4800 +Connection ~ 3600 4000 +Wire Wire Line + 3600 5550 4750 5550 +Connection ~ 3600 4800 +Wire Wire Line + 3600 6400 4800 6400 +Connection ~ 3600 5550 +Wire Wire Line + 3600 7150 4800 7150 +Connection ~ 3600 6400 +Wire Wire Line + 4850 950 4850 1150 +Wire Wire Line + 4850 1150 1550 1150 +Wire Wire Line + 1550 1150 1550 950 +Wire Wire Line + 3100 1550 3100 1400 +Wire Wire Line + 3100 1400 5000 1400 +Wire Wire Line + 5000 1400 5000 1750 +Wire Wire Line + 1950 1550 1950 1850 +Wire Wire Line + 1950 1850 3850 1850 +Wire Wire Line + 3850 1850 3850 1750 +Wire Wire Line + 3000 2400 3150 2400 +Wire Wire Line + 3150 2400 3150 2250 +Wire Wire Line + 3150 2250 5000 2250 +Wire Wire Line + 5000 2250 5000 2650 +Wire Wire Line + 1850 2400 1850 2650 +Wire Wire Line + 1850 2650 3850 2650 +Wire Wire Line + 1850 3250 1850 3500 +Wire Wire Line + 1850 3500 4050 3500 +Wire Wire Line + 3000 3250 5200 3250 +Wire Wire Line + 5200 3250 5200 3500 +Wire Wire Line + 3050 4050 5150 4050 +Wire Wire Line + 5150 4050 5150 4300 +Wire Wire Line + 1900 4050 1900 4300 +Wire Wire Line + 1900 4300 4000 4300 +Wire Wire Line + 3050 4950 3050 4550 +Wire Wire Line + 3050 4550 5250 4550 +Wire Wire Line + 5250 4550 5250 5100 +Wire Wire Line + 1900 4950 1900 5250 +Wire Wire Line + 1900 5250 4100 5250 +Wire Wire Line + 4100 5250 4100 5100 +Wire Wire Line + 3000 5700 3000 5700 +Wire Wire Line + 3000 5700 3000 5300 +Wire Wire Line + 3000 5300 5300 5300 +Wire Wire Line + 5300 5300 5300 5850 +Wire Wire Line + 3000 6450 3000 6350 +Wire Wire Line + 3000 6350 5350 6350 +Wire Wire Line + 5350 6350 5350 6700 +Wire Wire Line + 3000 7200 3200 7200 +Wire Wire Line + 3200 7200 3200 7050 +Wire Wire Line + 3200 7050 5350 7050 +Wire Wire Line + 5350 7050 5350 7450 +Wire Wire Line + 4150 5850 4150 6000 +Wire Wire Line + 4150 6000 1850 6000 +Wire Wire Line + 1850 6000 1850 5700 +Wire Wire Line + 1850 6450 1850 6700 +Wire Wire Line + 1850 6700 4200 6700 +Wire Wire Line + 1850 7200 1850 7450 +Wire Wire Line + 1850 7450 4200 7450 +$Comp +L PORT U1 +U 1 1 6852D8EF +P 1400 700 +F 0 "U1" H 1450 800 30 0000 C CNN +F 1 "PORT" H 1400 700 30 0000 C CNN +F 2 "" H 1400 700 60 0000 C CNN +F 3 "" H 1400 700 60 0000 C CNN + 1 1400 700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6852D978 +P 1700 1550 +F 0 "U1" H 1750 1650 30 0000 C CNN +F 1 "PORT" H 1700 1550 30 0000 C CNN +F 2 "" H 1700 1550 60 0000 C CNN +F 3 "" H 1700 1550 60 0000 C CNN + 2 1700 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6852D9D9 +P 1600 2400 +F 0 "U1" H 1650 2500 30 0000 C CNN +F 1 "PORT" H 1600 2400 30 0000 C CNN +F 2 "" H 1600 2400 60 0000 C CNN +F 3 "" H 1600 2400 60 0000 C CNN + 3 1600 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6852E050 +P 1600 3250 +F 0 "U1" H 1650 3350 30 0000 C CNN +F 1 "PORT" H 1600 3250 30 0000 C CNN +F 2 "" H 1600 3250 60 0000 C CNN +F 3 "" H 1600 3250 60 0000 C CNN + 4 1600 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6852E0A1 +P 1700 4050 +F 0 "U1" H 1750 4150 30 0000 C CNN +F 1 "PORT" H 1700 4050 30 0000 C CNN +F 2 "" H 1700 4050 60 0000 C CNN +F 3 "" H 1700 4050 60 0000 C CNN + 5 1700 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6852E0F6 +P 1650 4950 +F 0 "U1" H 1700 5050 30 0000 C CNN +F 1 "PORT" H 1650 4950 30 0000 C CNN +F 2 "" H 1650 4950 60 0000 C CNN +F 3 "" H 1650 4950 60 0000 C CNN + 6 1650 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6852E882 +P 1600 5700 +F 0 "U1" H 1650 5800 30 0000 C CNN +F 1 "PORT" H 1600 5700 30 0000 C CNN +F 2 "" H 1600 5700 60 0000 C CNN +F 3 "" H 1600 5700 60 0000 C CNN + 7 1600 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6852E8DD +P 1600 6450 +F 0 "U1" H 1650 6550 30 0000 C CNN +F 1 "PORT" H 1600 6450 30 0000 C CNN +F 2 "" H 1600 6450 60 0000 C CNN +F 3 "" H 1600 6450 60 0000 C CNN + 8 1600 6450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6852E952 +P 1600 7200 +F 0 "U1" H 1650 7300 30 0000 C CNN +F 1 "PORT" H 1600 7200 30 0000 C CNN +F 2 "" H 1600 7200 60 0000 C CNN +F 3 "" H 1600 7200 60 0000 C CNN + 9 1600 7200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6852E9B1 +P 900 7500 +F 0 "U1" H 950 7600 30 0000 C CNN +F 1 "PORT" H 900 7500 30 0000 C CNN +F 2 "" H 900 7500 60 0000 C CNN +F 3 "" H 900 7500 60 0000 C CNN + 10 900 7500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6852F9A4 +P 5600 7450 +F 0 "U1" H 5650 7550 30 0000 C CNN +F 1 "PORT" H 5600 7450 30 0000 C CNN +F 2 "" H 5600 7450 60 0000 C CNN +F 3 "" H 5600 7450 60 0000 C CNN + 11 5600 7450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6852FA1D +P 5600 6700 +F 0 "U1" H 5650 6800 30 0000 C CNN +F 1 "PORT" H 5600 6700 30 0000 C CNN +F 2 "" H 5600 6700 60 0000 C CNN +F 3 "" H 5600 6700 60 0000 C CNN + 12 5600 6700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6852FA94 +P 5550 5850 +F 0 "U1" H 5600 5950 30 0000 C CNN +F 1 "PORT" H 5550 5850 30 0000 C CNN +F 2 "" H 5550 5850 60 0000 C CNN +F 3 "" H 5550 5850 60 0000 C CNN + 13 5550 5850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 6852FAFF +P 5500 5100 +F 0 "U1" H 5550 5200 30 0000 C CNN +F 1 "PORT" H 5500 5100 30 0000 C CNN +F 2 "" H 5500 5100 60 0000 C CNN +F 3 "" H 5500 5100 60 0000 C CNN + 14 5500 5100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 6852FB76 +P 5400 4300 +F 0 "U1" H 5450 4400 30 0000 C CNN +F 1 "PORT" H 5400 4300 30 0000 C CNN +F 2 "" H 5400 4300 60 0000 C CNN +F 3 "" H 5400 4300 60 0000 C CNN + 15 5400 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 6852FBFB +P 5450 3500 +F 0 "U1" H 5500 3600 30 0000 C CNN +F 1 "PORT" H 5450 3500 30 0000 C CNN +F 2 "" H 5450 3500 60 0000 C CNN +F 3 "" H 5450 3500 60 0000 C CNN + 16 5450 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 17 1 6853094E +P 5250 2650 +F 0 "U1" H 5300 2750 30 0000 C CNN +F 1 "PORT" H 5250 2650 30 0000 C CNN +F 2 "" H 5250 2650 60 0000 C CNN +F 3 "" H 5250 2650 60 0000 C CNN + 17 5250 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 18 1 685309C3 +P 5250 1750 +F 0 "U1" H 5300 1850 30 0000 C CNN +F 1 "PORT" H 5250 1750 30 0000 C CNN +F 2 "" H 5250 1750 60 0000 C CNN +F 3 "" H 5250 1750 60 0000 C CNN + 18 5250 1750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 19 1 68530A40 +P 5100 1150 +F 0 "U1" H 5150 1250 30 0000 C CNN +F 1 "PORT" H 5100 1150 30 0000 C CNN +F 2 "" H 5100 1150 60 0000 C CNN +F 3 "" H 5100 1150 60 0000 C CNN + 19 5100 1150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 20 1 68530ACD +P 900 7150 +F 0 "U1" H 950 7250 30 0000 C CNN +F 1 "PORT" H 900 7150 30 0000 C CNN +F 2 "" H 900 7150 60 0000 C CNN +F 3 "" H 900 7150 60 0000 C CNN + 20 900 7150 + 1 0 0 -1 +$EndComp +NoConn ~ 1150 7150 +NoConn ~ 1150 7500 +Wire Wire Line + 1650 700 2150 700 +Connection ~ 2150 700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.sub b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.sub new file mode 100644 index 000000000..6a6634a84 --- /dev/null +++ b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245.sub @@ -0,0 +1,82 @@ +* Subcircuit SC_M74HCT245 +.subckt SC_M74HCT245 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_m74hct245\sc_m74hct245.cir +* u4 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad16_ d_tristate +* u8 net-_u15-pad3_ net-_u10-pad2_ net-_u1-pad15_ d_tristate +* u9 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad14_ d_tristate +* u5 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad13_ d_tristate +* u6 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad12_ d_tristate +* u7 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad11_ d_tristate +* u3 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad17_ d_tristate +* u10 net-_u1-pad2_ net-_u10-pad2_ net-_u1-pad18_ d_tristate +* u16 net-_u1-pad16_ net-_u12-pad3_ net-_u1-pad4_ d_tristate +* u15 net-_u1-pad15_ net-_u12-pad3_ net-_u15-pad3_ d_tristate +* u17 net-_u1-pad14_ net-_u12-pad3_ net-_u1-pad6_ d_tristate +* u18 net-_u1-pad13_ net-_u12-pad3_ net-_u1-pad7_ d_tristate +* u19 net-_u1-pad12_ net-_u12-pad3_ net-_u1-pad8_ d_tristate +* u20 net-_u1-pad11_ net-_u12-pad3_ net-_u1-pad9_ d_tristate +* u14 net-_u1-pad17_ net-_u12-pad3_ net-_u1-pad3_ d_tristate +* u13 net-_u1-pad18_ net-_u12-pad3_ net-_u1-pad2_ d_tristate +* u2 net-_u1-pad19_ net-_u11-pad2_ d_inverter +* u11 net-_u1-pad1_ net-_u11-pad2_ net-_u10-pad2_ d_and +* u12 net-_u1-pad19_ net-_u1-pad1_ net-_u12-pad3_ d_nor +a1 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad16_ u4 +a2 net-_u15-pad3_ net-_u10-pad2_ net-_u1-pad15_ u8 +a3 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad14_ u9 +a4 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad13_ u5 +a5 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad12_ u6 +a6 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad11_ u7 +a7 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad17_ u3 +a8 net-_u1-pad2_ net-_u10-pad2_ net-_u1-pad18_ u10 +a9 net-_u1-pad16_ net-_u12-pad3_ net-_u1-pad4_ u16 +a10 net-_u1-pad15_ net-_u12-pad3_ net-_u15-pad3_ u15 +a11 net-_u1-pad14_ net-_u12-pad3_ net-_u1-pad6_ u17 +a12 net-_u1-pad13_ net-_u12-pad3_ net-_u1-pad7_ u18 +a13 net-_u1-pad12_ net-_u12-pad3_ net-_u1-pad8_ u19 +a14 net-_u1-pad11_ net-_u12-pad3_ net-_u1-pad9_ u20 +a15 net-_u1-pad17_ net-_u12-pad3_ net-_u1-pad3_ u14 +a16 net-_u1-pad18_ net-_u12-pad3_ net-_u1-pad2_ u13 +a17 net-_u1-pad19_ net-_u11-pad2_ u2 +a18 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u10-pad2_ u11 +a19 [net-_u1-pad19_ net-_u1-pad1_ ] net-_u12-pad3_ u12 +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u7 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u3 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u16 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_M74HCT245 \ No newline at end of file diff --git a/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245_Previous_Values.xml b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245_Previous_Values.xml new file mode 100644 index 000000000..5d8cc2b76 --- /dev/null +++ b/library/SubcircuitLibrary/M74HCT245/SC_M74HCT245_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsmsd_tristated_tristated_tristated_tristated_tristated_tristated_tristated_tristated_tristated_tristated_tristated_tristated_tristated_tristated_tristated_tristated_inverterd_andd_nor \ No newline at end of file From 6115fad50dd9272eac1e821fa4a402136850fbcf Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:10:03 +0530 Subject: [PATCH 23/33] 8-bit Magnitude/Identity Comparator --- library/SubcircuitLibrary/SN74LS684/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/SN74LS684/analysis diff --git a/library/SubcircuitLibrary/SN74LS684/analysis b/library/SubcircuitLibrary/SN74LS684/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS684/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 7cd658b1b93aa31b92862411503e626810047f66 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:11:17 +0530 Subject: [PATCH 24/33] 8-bit Magnitude/Identity Comparator --- .../SN74LS684/SC_SN74LS684-cache.lib | 209 +++ .../SN74LS684/SC_SN74LS684.cir | 65 + .../SN74LS684/SC_SN74LS684.cir.out | 190 +++ .../SN74LS684/SC_SN74LS684.pro | 73 + .../SN74LS684/SC_SN74LS684.sch | 1228 +++++++++++++++++ .../SN74LS684/SC_SN74LS684.sub | 184 +++ .../SC_SN74LS684_Previous_Values.xml | 1 + 7 files changed, 1950 insertions(+) create mode 100644 library/SubcircuitLibrary/SN74LS684/SC_SN74LS684-cache.lib create mode 100644 library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.cir create mode 100644 library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.cir.out create mode 100644 library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.pro create mode 100644 library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.sch create mode 100644 library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.sub create mode 100644 library/SubcircuitLibrary/SN74LS684/SC_SN74LS684_Previous_Values.xml diff --git a/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684-cache.lib b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684-cache.lib new file mode 100644 index 000000000..2742291d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684-cache.lib @@ -0,0 +1,209 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xnor +# +DEF d_xnor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xnor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 43 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.cir b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.cir new file mode 100644 index 000000000..fa3a4c129 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.cir @@ -0,0 +1,65 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_SN74LS684\SC_SN74LS684.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/21/25 20:23:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U10 Net-_U1-Pad17_ Net-_U10-Pad2_ d_inverter +U12 Net-_U1-Pad15_ Net-_U12-Pad2_ d_inverter +U13 Net-_U1-Pad16_ Net-_U13-Pad2_ d_inverter +U15 Net-_U1-Pad14_ Net-_U15-Pad2_ d_inverter +U16 Net-_U1-Pad11_ Net-_U16-Pad2_ d_inverter +U17 Net-_U1-Pad12_ Net-_U17-Pad2_ d_inverter +U6 Net-_U1-Pad8_ Net-_U22-Pad1_ d_inverter +U7 Net-_U1-Pad9_ Net-_U22-Pad2_ d_inverter +U8 Net-_U1-Pad6_ Net-_U24-Pad1_ d_inverter +U9 Net-_U1-Pad7_ Net-_U24-Pad2_ d_inverter +U4 Net-_U1-Pad4_ Net-_U25-Pad1_ d_inverter +U5 Net-_U1-Pad5_ Net-_U25-Pad2_ d_inverter +U11 Net-_U1-Pad18_ Net-_U11-Pad2_ d_inverter +U14 Net-_U1-Pad13_ Net-_U14-Pad2_ d_inverter +U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad3_ Net-_U23-Pad2_ d_inverter +U18 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U18-Pad3_ d_xnor +U19 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U19-Pad3_ d_xnor +U20 Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U20-Pad3_ d_xnor +U21 Net-_U16-Pad2_ Net-_U17-Pad2_ Net-_U21-Pad3_ d_xnor +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_xnor +U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_xnor +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_xnor +U23 Net-_U2-Pad2_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_xnor +X12 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U40-Pad1_ 5_and +X11 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U23-Pad3_ Net-_U40-Pad2_ 3_and +X9 Net-_U25-Pad3_ Net-_U24-Pad3_ Net-_U22-Pad3_ Net-_U21-Pad3_ Net-_U20-Pad3_ Net-_U37-Pad1_ 5_and +X8 Net-_U24-Pad3_ Net-_U22-Pad3_ Net-_U21-Pad3_ Net-_U20-Pad3_ Net-_U19-Pad3_ Net-_U39-Pad1_ 5_and +X5 Net-_U18-Pad3_ Net-_U25-Pad1_ Net-_U32-Pad2_ Net-_U39-Pad2_ 3_and +U39 Net-_U39-Pad1_ Net-_U39-Pad2_ Net-_U39-Pad3_ d_and +X7 Net-_U22-Pad3_ Net-_U21-Pad3_ Net-_U20-Pad3_ Net-_U19-Pad3_ Net-_U18-Pad3_ Net-_U36-Pad1_ 5_and +U35 Net-_U24-Pad1_ Net-_U30-Pad2_ Net-_U35-Pad3_ d_and +U36 Net-_U36-Pad1_ Net-_U35-Pad3_ Net-_U36-Pad3_ d_and +X1 Net-_U21-Pad3_ Net-_U20-Pad3_ Net-_U19-Pad3_ Net-_U38-Pad1_ 3_and +X3 Net-_U18-Pad3_ Net-_U22-Pad1_ Net-_U31-Pad2_ Net-_U38-Pad2_ 3_and +U38 Net-_U38-Pad1_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_and +X6 Net-_U20-Pad3_ Net-_U19-Pad3_ Net-_U18-Pad3_ Net-_U16-Pad2_ Net-_U26-Pad2_ Net-_X14-Pad1_ 5_and +X4 Net-_U19-Pad3_ Net-_U18-Pad3_ Net-_U14-Pad2_ Net-_U27-Pad2_ Net-_X14-Pad2_ 4_and +X2 Net-_U18-Pad3_ Net-_U12-Pad2_ Net-_U28-Pad2_ Net-_X14-Pad3_ 3_and +U34 Net-_U10-Pad2_ Net-_U29-Pad2_ Net-_U34-Pad3_ d_and +X10 Net-_U19-Pad3_ Net-_U18-Pad3_ Net-_U2-Pad2_ Net-_U33-Pad2_ Net-_U37-Pad2_ 4_and +U37 Net-_U37-Pad1_ Net-_U37-Pad2_ Net-_U37-Pad3_ d_and +U33 Net-_U23-Pad2_ Net-_U33-Pad2_ d_inverter +U32 Net-_U25-Pad2_ Net-_U32-Pad2_ d_inverter +U30 Net-_U24-Pad2_ Net-_U30-Pad2_ d_inverter +U31 Net-_U22-Pad2_ Net-_U31-Pad2_ d_inverter +U26 Net-_U17-Pad2_ Net-_U26-Pad2_ d_inverter +U27 Net-_U15-Pad2_ Net-_U27-Pad2_ d_inverter +U28 Net-_U13-Pad2_ Net-_U28-Pad2_ d_inverter +U29 Net-_U11-Pad2_ Net-_U29-Pad2_ d_inverter +U40 Net-_U40-Pad1_ Net-_U40-Pad2_ Net-_U1-Pad19_ d_nand +X13 Net-_U37-Pad3_ Net-_U39-Pad3_ Net-_U36-Pad3_ Net-_U38-Pad3_ Net-_U41-Pad1_ 4_OR +X14 Net-_X14-Pad1_ Net-_X14-Pad2_ Net-_X14-Pad3_ Net-_U34-Pad3_ Net-_U41-Pad2_ 4_OR +U41 Net-_U41-Pad1_ Net-_U41-Pad2_ Net-_U1-Pad1_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ ? Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.cir.out b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.cir.out new file mode 100644 index 000000000..aca2ab26b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.cir.out @@ -0,0 +1,190 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn74ls684\sc_sn74ls684.cir + +.include 5_and.sub +.include 3_and.sub +.include 4_OR.sub +.include 4_and.sub +* u10 net-_u1-pad17_ net-_u10-pad2_ d_inverter +* u12 net-_u1-pad15_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad16_ net-_u13-pad2_ d_inverter +* u15 net-_u1-pad14_ net-_u15-pad2_ d_inverter +* u16 net-_u1-pad11_ net-_u16-pad2_ d_inverter +* u17 net-_u1-pad12_ net-_u17-pad2_ d_inverter +* u6 net-_u1-pad8_ net-_u22-pad1_ d_inverter +* u7 net-_u1-pad9_ net-_u22-pad2_ d_inverter +* u8 net-_u1-pad6_ net-_u24-pad1_ d_inverter +* u9 net-_u1-pad7_ net-_u24-pad2_ d_inverter +* u4 net-_u1-pad4_ net-_u25-pad1_ d_inverter +* u5 net-_u1-pad5_ net-_u25-pad2_ d_inverter +* u11 net-_u1-pad18_ net-_u11-pad2_ d_inverter +* u14 net-_u1-pad13_ net-_u14-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad3_ net-_u23-pad2_ d_inverter +* u18 net-_u10-pad2_ net-_u11-pad2_ net-_u18-pad3_ d_xnor +* u19 net-_u12-pad2_ net-_u13-pad2_ net-_u19-pad3_ d_xnor +* u20 net-_u14-pad2_ net-_u15-pad2_ net-_u20-pad3_ d_xnor +* u21 net-_u16-pad2_ net-_u17-pad2_ net-_u21-pad3_ d_xnor +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_xnor +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_xnor +* u25 net-_u25-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_xnor +* u23 net-_u2-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_xnor +x12 net-_u18-pad3_ net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ net-_u22-pad3_ net-_u40-pad1_ 5_and +x11 net-_u24-pad3_ net-_u25-pad3_ net-_u23-pad3_ net-_u40-pad2_ 3_and +x9 net-_u25-pad3_ net-_u24-pad3_ net-_u22-pad3_ net-_u21-pad3_ net-_u20-pad3_ net-_u37-pad1_ 5_and +x8 net-_u24-pad3_ net-_u22-pad3_ net-_u21-pad3_ net-_u20-pad3_ net-_u19-pad3_ net-_u39-pad1_ 5_and +x5 net-_u18-pad3_ net-_u25-pad1_ net-_u32-pad2_ net-_u39-pad2_ 3_and +* u39 net-_u39-pad1_ net-_u39-pad2_ net-_u39-pad3_ d_and +x7 net-_u22-pad3_ net-_u21-pad3_ net-_u20-pad3_ net-_u19-pad3_ net-_u18-pad3_ net-_u36-pad1_ 5_and +* u35 net-_u24-pad1_ net-_u30-pad2_ net-_u35-pad3_ d_and +* u36 net-_u36-pad1_ net-_u35-pad3_ net-_u36-pad3_ d_and +x1 net-_u21-pad3_ net-_u20-pad3_ net-_u19-pad3_ net-_u38-pad1_ 3_and +x3 net-_u18-pad3_ net-_u22-pad1_ net-_u31-pad2_ net-_u38-pad2_ 3_and +* u38 net-_u38-pad1_ net-_u38-pad2_ net-_u38-pad3_ d_and +x6 net-_u20-pad3_ net-_u19-pad3_ net-_u18-pad3_ net-_u16-pad2_ net-_u26-pad2_ net-_x14-pad1_ 5_and +x4 net-_u19-pad3_ net-_u18-pad3_ net-_u14-pad2_ net-_u27-pad2_ net-_x14-pad2_ 4_and +x2 net-_u18-pad3_ net-_u12-pad2_ net-_u28-pad2_ net-_x14-pad3_ 3_and +* u34 net-_u10-pad2_ net-_u29-pad2_ net-_u34-pad3_ d_and +x10 net-_u19-pad3_ net-_u18-pad3_ net-_u2-pad2_ net-_u33-pad2_ net-_u37-pad2_ 4_and +* u37 net-_u37-pad1_ net-_u37-pad2_ net-_u37-pad3_ d_and +* u33 net-_u23-pad2_ net-_u33-pad2_ d_inverter +* u32 net-_u25-pad2_ net-_u32-pad2_ d_inverter +* u30 net-_u24-pad2_ net-_u30-pad2_ d_inverter +* u31 net-_u22-pad2_ net-_u31-pad2_ d_inverter +* u26 net-_u17-pad2_ net-_u26-pad2_ d_inverter +* u27 net-_u15-pad2_ net-_u27-pad2_ d_inverter +* u28 net-_u13-pad2_ net-_u28-pad2_ d_inverter +* u29 net-_u11-pad2_ net-_u29-pad2_ d_inverter +* u40 net-_u40-pad1_ net-_u40-pad2_ net-_u1-pad19_ d_nand +x13 net-_u37-pad3_ net-_u39-pad3_ net-_u36-pad3_ net-_u38-pad3_ net-_u41-pad1_ 4_OR +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x14-pad3_ net-_u34-pad3_ net-_u41-pad2_ 4_OR +* u41 net-_u41-pad1_ net-_u41-pad2_ net-_u1-pad1_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? port +a1 net-_u1-pad17_ net-_u10-pad2_ u10 +a2 net-_u1-pad15_ net-_u12-pad2_ u12 +a3 net-_u1-pad16_ net-_u13-pad2_ u13 +a4 net-_u1-pad14_ net-_u15-pad2_ u15 +a5 net-_u1-pad11_ net-_u16-pad2_ u16 +a6 net-_u1-pad12_ net-_u17-pad2_ u17 +a7 net-_u1-pad8_ net-_u22-pad1_ u6 +a8 net-_u1-pad9_ net-_u22-pad2_ u7 +a9 net-_u1-pad6_ net-_u24-pad1_ u8 +a10 net-_u1-pad7_ net-_u24-pad2_ u9 +a11 net-_u1-pad4_ net-_u25-pad1_ u4 +a12 net-_u1-pad5_ net-_u25-pad2_ u5 +a13 net-_u1-pad18_ net-_u11-pad2_ u11 +a14 net-_u1-pad13_ net-_u14-pad2_ u14 +a15 net-_u1-pad2_ net-_u2-pad2_ u2 +a16 net-_u1-pad3_ net-_u23-pad2_ u3 +a17 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u19-pad3_ u19 +a19 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u20-pad3_ u20 +a20 [net-_u16-pad2_ net-_u17-pad2_ ] net-_u21-pad3_ u21 +a21 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a22 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 +a23 [net-_u25-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u25 +a24 [net-_u2-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a25 [net-_u39-pad1_ net-_u39-pad2_ ] net-_u39-pad3_ u39 +a26 [net-_u24-pad1_ net-_u30-pad2_ ] net-_u35-pad3_ u35 +a27 [net-_u36-pad1_ net-_u35-pad3_ ] net-_u36-pad3_ u36 +a28 [net-_u38-pad1_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a29 [net-_u10-pad2_ net-_u29-pad2_ ] net-_u34-pad3_ u34 +a30 [net-_u37-pad1_ net-_u37-pad2_ ] net-_u37-pad3_ u37 +a31 net-_u23-pad2_ net-_u33-pad2_ u33 +a32 net-_u25-pad2_ net-_u32-pad2_ u32 +a33 net-_u24-pad2_ net-_u30-pad2_ u30 +a34 net-_u22-pad2_ net-_u31-pad2_ u31 +a35 net-_u17-pad2_ net-_u26-pad2_ u26 +a36 net-_u15-pad2_ net-_u27-pad2_ u27 +a37 net-_u13-pad2_ net-_u28-pad2_ u28 +a38 net-_u11-pad2_ net-_u29-pad2_ u29 +a39 [net-_u40-pad1_ net-_u40-pad2_ ] net-_u1-pad19_ u40 +a40 [net-_u41-pad1_ net-_u41-pad2_ ] net-_u1-pad1_ u41 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u20 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u21 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u22 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u24 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u23 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u41 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.pro b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.sch b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.sch new file mode 100644 index 000000000..eae9edc8f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.sch @@ -0,0 +1,1228 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr User 15748 15748 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U10 +U 1 1 68564704 +P 2100 750 +F 0 "U10" H 2100 650 60 0000 C CNN +F 1 "d_inverter" H 2100 900 60 0000 C CNN +F 2 "" H 2150 700 60 0000 C CNN +F 3 "" H 2150 700 60 0000 C CNN + 1 2100 750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 68564786 +P 2100 1500 +F 0 "U12" H 2100 1400 60 0000 C CNN +F 1 "d_inverter" H 2100 1650 60 0000 C CNN +F 2 "" H 2150 1450 60 0000 C CNN +F 3 "" H 2150 1450 60 0000 C CNN + 1 2100 1500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 685647B7 +P 2100 1850 +F 0 "U13" H 2100 1750 60 0000 C CNN +F 1 "d_inverter" H 2100 2000 60 0000 C CNN +F 2 "" H 2150 1800 60 0000 C CNN +F 3 "" H 2150 1800 60 0000 C CNN + 1 2100 1850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 685647F6 +P 2100 2500 +F 0 "U15" H 2100 2400 60 0000 C CNN +F 1 "d_inverter" H 2100 2650 60 0000 C CNN +F 2 "" H 2150 2450 60 0000 C CNN +F 3 "" H 2150 2450 60 0000 C CNN + 1 2100 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6856483B +P 2100 2800 +F 0 "U16" H 2100 2700 60 0000 C CNN +F 1 "d_inverter" H 2100 2950 60 0000 C CNN +F 2 "" H 2150 2750 60 0000 C CNN +F 3 "" H 2150 2750 60 0000 C CNN + 1 2100 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 6856498A +P 2100 3150 +F 0 "U17" H 2100 3050 60 0000 C CNN +F 1 "d_inverter" H 2100 3300 60 0000 C CNN +F 2 "" H 2150 3100 60 0000 C CNN +F 3 "" H 2150 3100 60 0000 C CNN + 1 2100 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 685649D3 +P 2050 3500 +F 0 "U6" H 2050 3400 60 0000 C CNN +F 1 "d_inverter" H 2050 3650 60 0000 C CNN +F 2 "" H 2100 3450 60 0000 C CNN +F 3 "" H 2100 3450 60 0000 C CNN + 1 2050 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68564A0C +P 2050 3750 +F 0 "U7" H 2050 3650 60 0000 C CNN +F 1 "d_inverter" H 2050 3900 60 0000 C CNN +F 2 "" H 2100 3700 60 0000 C CNN +F 3 "" H 2100 3700 60 0000 C CNN + 1 2050 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 68564B91 +P 2050 4100 +F 0 "U8" H 2050 4000 60 0000 C CNN +F 1 "d_inverter" H 2050 4250 60 0000 C CNN +F 2 "" H 2100 4050 60 0000 C CNN +F 3 "" H 2100 4050 60 0000 C CNN + 1 2050 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 68564BE2 +P 2050 4450 +F 0 "U9" H 2050 4350 60 0000 C CNN +F 1 "d_inverter" H 2050 4600 60 0000 C CNN +F 2 "" H 2100 4400 60 0000 C CNN +F 3 "" H 2100 4400 60 0000 C CNN + 1 2050 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68564C29 +P 2000 4800 +F 0 "U4" H 2000 4700 60 0000 C CNN +F 1 "d_inverter" H 2000 4950 60 0000 C CNN +F 2 "" H 2050 4750 60 0000 C CNN +F 3 "" H 2050 4750 60 0000 C CNN + 1 2000 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 68564C7A +P 2000 5100 +F 0 "U5" H 2000 5000 60 0000 C CNN +F 1 "d_inverter" H 2000 5250 60 0000 C CNN +F 2 "" H 2050 5050 60 0000 C CNN +F 3 "" H 2050 5050 60 0000 C CNN + 1 2000 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 68564CE5 +P 2100 1100 +F 0 "U11" H 2100 1000 60 0000 C CNN +F 1 "d_inverter" H 2100 1250 60 0000 C CNN +F 2 "" H 2150 1050 60 0000 C CNN +F 3 "" H 2150 1050 60 0000 C CNN + 1 2100 1100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 68564D47 +P 2100 2200 +F 0 "U14" H 2100 2100 60 0000 C CNN +F 1 "d_inverter" H 2100 2350 60 0000 C CNN +F 2 "" H 2150 2150 60 0000 C CNN +F 3 "" H 2150 2150 60 0000 C CNN + 1 2100 2200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68564F4A +P 1950 5500 +F 0 "U2" H 1950 5400 60 0000 C CNN +F 1 "d_inverter" H 1950 5650 60 0000 C CNN +F 2 "" H 2000 5450 60 0000 C CNN +F 3 "" H 2000 5450 60 0000 C CNN + 1 1950 5500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 68564F9F +P 1950 5800 +F 0 "U3" H 1950 5700 60 0000 C CNN +F 1 "d_inverter" H 1950 5950 60 0000 C CNN +F 2 "" H 2000 5750 60 0000 C CNN +F 3 "" H 2000 5750 60 0000 C CNN + 1 1950 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U18 +U 1 1 68564FF6 +P 5300 850 +F 0 "U18" H 5300 850 60 0000 C CNN +F 1 "d_xnor" H 5350 950 47 0000 C CNN +F 2 "" H 5300 850 60 0000 C CNN +F 3 "" H 5300 850 60 0000 C CNN + 1 5300 850 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U19 +U 1 1 68565063 +P 5300 1600 +F 0 "U19" H 5300 1600 60 0000 C CNN +F 1 "d_xnor" H 5350 1700 47 0000 C CNN +F 2 "" H 5300 1600 60 0000 C CNN +F 3 "" H 5300 1600 60 0000 C CNN + 1 5300 1600 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U20 +U 1 1 685650F6 +P 5350 2300 +F 0 "U20" H 5350 2300 60 0000 C CNN +F 1 "d_xnor" H 5400 2400 47 0000 C CNN +F 2 "" H 5350 2300 60 0000 C CNN +F 3 "" H 5350 2300 60 0000 C CNN + 1 5350 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U21 +U 1 1 68565139 +P 5350 2900 +F 0 "U21" H 5350 2900 60 0000 C CNN +F 1 "d_xnor" H 5400 3000 47 0000 C CNN +F 2 "" H 5350 2900 60 0000 C CNN +F 3 "" H 5350 2900 60 0000 C CNN + 1 5350 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U22 +U 1 1 685651B0 +P 5350 3600 +F 0 "U22" H 5350 3600 60 0000 C CNN +F 1 "d_xnor" H 5400 3700 47 0000 C CNN +F 2 "" H 5350 3600 60 0000 C CNN +F 3 "" H 5350 3600 60 0000 C CNN + 1 5350 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U24 +U 1 1 6856520B +P 5450 4200 +F 0 "U24" H 5450 4200 60 0000 C CNN +F 1 "d_xnor" H 5500 4300 47 0000 C CNN +F 2 "" H 5450 4200 60 0000 C CNN +F 3 "" H 5450 4200 60 0000 C CNN + 1 5450 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U25 +U 1 1 68565266 +P 5450 4900 +F 0 "U25" H 5450 4900 60 0000 C CNN +F 1 "d_xnor" H 5500 5000 47 0000 C CNN +F 2 "" H 5450 4900 60 0000 C CNN +F 3 "" H 5450 4900 60 0000 C CNN + 1 5450 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U23 +U 1 1 685652CF +P 5400 5600 +F 0 "U23" H 5400 5600 60 0000 C CNN +F 1 "d_xnor" H 5450 5700 47 0000 C CNN +F 2 "" H 5400 5600 60 0000 C CNN +F 3 "" H 5400 5600 60 0000 C CNN + 1 5400 5600 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X12 +U 1 1 68566290 +P 8700 2200 +F 0 "X12" H 8750 2100 60 0000 C CNN +F 1 "5_and" H 8800 2350 60 0000 C CNN +F 2 "" H 8700 2200 60 0000 C CNN +F 3 "" H 8700 2200 60 0000 C CNN + 1 8700 2200 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X11 +U 1 1 685662F5 +P 8650 4550 +F 0 "X11" H 8750 4500 60 0000 C CNN +F 1 "3_and" H 8800 4700 60 0000 C CNN +F 2 "" H 8650 4550 60 0000 C CNN +F 3 "" H 8650 4550 60 0000 C CNN + 1 8650 4550 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X9 +U 1 1 685676C0 +P 8100 6100 +F 0 "X9" H 8150 6000 60 0000 C CNN +F 1 "5_and" H 8200 6250 60 0000 C CNN +F 2 "" H 8100 6100 60 0000 C CNN +F 3 "" H 8100 6100 60 0000 C CNN + 1 8100 6100 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X8 +U 1 1 68567CCA +P 8050 7900 +F 0 "X8" H 8100 7800 60 0000 C CNN +F 1 "5_and" H 8150 8050 60 0000 C CNN +F 2 "" H 8050 7900 60 0000 C CNN +F 3 "" H 8050 7900 60 0000 C CNN + 1 8050 7900 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 68567D3B +P 7950 8600 +F 0 "X5" H 8050 8550 60 0000 C CNN +F 1 "3_and" H 8100 8750 60 0000 C CNN +F 2 "" H 7950 8600 60 0000 C CNN +F 3 "" H 7950 8600 60 0000 C CNN + 1 7950 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U39 +U 1 1 68567DB0 +P 9450 8300 +F 0 "U39" H 9450 8300 60 0000 C CNN +F 1 "d_and" H 9500 8400 60 0000 C CNN +F 2 "" H 9450 8300 60 0000 C CNN +F 3 "" H 9450 8300 60 0000 C CNN + 1 9450 8300 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X7 +U 1 1 68567E1D +P 8000 9400 +F 0 "X7" H 8050 9300 60 0000 C CNN +F 1 "5_and" H 8100 9550 60 0000 C CNN +F 2 "" H 8000 9400 60 0000 C CNN +F 3 "" H 8000 9400 60 0000 C CNN + 1 8000 9400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U35 +U 1 1 68567E8E +P 8000 10000 +F 0 "U35" H 8000 10000 60 0000 C CNN +F 1 "d_and" H 8050 10100 60 0000 C CNN +F 2 "" H 8000 10000 60 0000 C CNN +F 3 "" H 8000 10000 60 0000 C CNN + 1 8000 10000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U36 +U 1 1 68567F15 +P 9350 9650 +F 0 "U36" H 9350 9650 60 0000 C CNN +F 1 "d_and" H 9400 9750 60 0000 C CNN +F 2 "" H 9350 9650 60 0000 C CNN +F 3 "" H 9350 9650 60 0000 C CNN + 1 9350 9650 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 68567FFE +P 7850 10850 +F 0 "X1" H 7950 10800 60 0000 C CNN +F 1 "3_and" H 8000 11000 60 0000 C CNN +F 2 "" H 7850 10850 60 0000 C CNN +F 3 "" H 7850 10850 60 0000 C CNN + 1 7850 10850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 6856808B +P 7900 11400 +F 0 "X3" H 8000 11350 60 0000 C CNN +F 1 "3_and" H 8050 11550 60 0000 C CNN +F 2 "" H 7900 11400 60 0000 C CNN +F 3 "" H 7900 11400 60 0000 C CNN + 1 7900 11400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U38 +U 1 1 68568146 +P 9400 11050 +F 0 "U38" H 9400 11050 60 0000 C CNN +F 1 "d_and" H 9450 11150 60 0000 C CNN +F 2 "" H 9400 11050 60 0000 C CNN +F 3 "" H 9400 11050 60 0000 C CNN + 1 9400 11050 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X6 +U 1 1 685681D1 +P 7950 12150 +F 0 "X6" H 8000 12050 60 0000 C CNN +F 1 "5_and" H 8050 12300 60 0000 C CNN +F 2 "" H 7950 12150 60 0000 C CNN +F 3 "" H 7950 12150 60 0000 C CNN + 1 7950 12150 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 68568262 +P 7900 13050 +F 0 "X4" H 7950 13000 60 0000 C CNN +F 1 "4_and" H 8000 13150 60 0000 C CNN +F 2 "" H 7900 13050 60 0000 C CNN +F 3 "" H 7900 13050 60 0000 C CNN + 1 7900 13050 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 685682F3 +P 7850 13750 +F 0 "X2" H 7950 13700 60 0000 C CNN +F 1 "3_and" H 8000 13900 60 0000 C CNN +F 2 "" H 7850 13750 60 0000 C CNN +F 3 "" H 7850 13750 60 0000 C CNN + 1 7850 13750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U34 +U 1 1 68568380 +P 7950 14350 +F 0 "U34" H 7950 14350 60 0000 C CNN +F 1 "d_and" H 8000 14450 60 0000 C CNN +F 2 "" H 7950 14350 60 0000 C CNN +F 3 "" H 7950 14350 60 0000 C CNN + 1 7950 14350 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X10 +U 1 1 68568793 +P 8100 6800 +F 0 "X10" H 8150 6750 60 0000 C CNN +F 1 "4_and" H 8200 6900 60 0000 C CNN +F 2 "" H 8100 6800 60 0000 C CNN +F 3 "" H 8100 6800 60 0000 C CNN + 1 8100 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U37 +U 1 1 68568879 +P 9400 6550 +F 0 "U37" H 9400 6550 60 0000 C CNN +F 1 "d_and" H 9450 6650 60 0000 C CNN +F 2 "" H 9400 6550 60 0000 C CNN +F 3 "" H 9400 6550 60 0000 C CNN + 1 9400 6550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U33 +U 1 1 6856AFBD +P 7400 6950 +F 0 "U33" H 7400 6850 60 0000 C CNN +F 1 "d_inverter" H 7400 7100 60 0000 C CNN +F 2 "" H 7450 6900 60 0000 C CNN +F 3 "" H 7450 6900 60 0000 C CNN + 1 7400 6950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2400 750 4850 750 +Wire Wire Line + 4850 850 2400 850 +Wire Wire Line + 2400 850 2400 1100 +Wire Wire Line + 2400 1500 4850 1500 +Wire Wire Line + 2400 1850 4850 1850 +Wire Wire Line + 4850 1850 4850 1600 +Wire Wire Line + 2400 2200 4900 2200 +Wire Wire Line + 2400 2500 4900 2500 +Wire Wire Line + 4900 2500 4900 2300 +Wire Wire Line + 2400 2800 4900 2800 +Wire Wire Line + 4900 2900 4900 3150 +Wire Wire Line + 4900 3150 2400 3150 +Wire Wire Line + 2350 3500 4900 3500 +Wire Wire Line + 2350 3750 4900 3750 +Wire Wire Line + 4900 3750 4900 3600 +Wire Wire Line + 2350 4100 5000 4100 +Wire Wire Line + 2350 4450 5000 4450 +Wire Wire Line + 5000 4450 5000 4200 +Wire Wire Line + 2300 4800 5000 4800 +Wire Wire Line + 2300 5100 5000 5100 +Wire Wire Line + 5000 5100 5000 4900 +Wire Wire Line + 2250 5500 4950 5500 +Wire Wire Line + 2250 5800 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7900 9000 7900 +Wire Wire Line + 9000 7900 9000 8200 +Wire Wire Line + 9000 8300 9000 8550 +Wire Wire Line + 9000 8550 8450 8550 +Wire Wire Line + 6950 7700 7600 7700 +Connection ~ 6950 6000 +Wire Wire Line + 6750 7800 7600 7800 +Connection ~ 6750 6100 +Wire Wire Line + 6550 7900 7600 7900 +Connection ~ 6550 6200 +Wire Wire Line + 6400 8000 7600 8000 +Connection ~ 6400 6300 +Wire Wire Line + 6300 8100 7600 8100 +Connection ~ 6300 6650 +Wire Wire Line + 6100 8450 7600 8450 +Connection ~ 6100 6750 +Wire Wire Line + 7600 8550 4550 8550 +Wire Wire Line + 4550 8550 4550 4800 +Connection ~ 4550 4800 +$Comp +L d_inverter U32 +U 1 1 6856D132 +P 7300 8650 +F 0 "U32" H 7300 8550 60 0000 C CNN +F 1 "d_inverter" H 7300 8800 60 0000 C CNN +F 2 "" H 7350 8600 60 0000 C CNN +F 3 "" H 7350 8600 60 0000 C CNN + 1 7300 8650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 6856D82D +P 7250 10000 +F 0 "U30" H 7250 9900 60 0000 C CNN +F 1 "d_inverter" H 7250 10150 60 0000 C CNN +F 2 "" H 7300 9950 60 0000 C CNN +F 3 "" H 7300 9950 60 0000 C CNN + 1 7250 10000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U31 +U 1 1 6856D8B8 +P 7250 11450 +F 0 "U31" H 7250 11350 60 0000 C CNN +F 1 "d_inverter" H 7250 11600 60 0000 C CNN +F 2 "" H 7300 11400 60 0000 C CNN +F 3 "" H 7300 11400 60 0000 C CNN + 1 7250 11450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U26 +U 1 1 6856D981 +P 7200 12350 +F 0 "U26" H 7200 12250 60 0000 C CNN +F 1 "d_inverter" H 7200 12500 60 0000 C CNN +F 2 "" H 7250 12300 60 0000 C CNN +F 3 "" H 7250 12300 60 0000 C CNN + 1 7200 12350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 6856DA0E +P 7200 13200 +F 0 "U27" H 7200 13100 60 0000 C CNN +F 1 "d_inverter" H 7200 13350 60 0000 C CNN +F 2 "" H 7250 13150 60 0000 C CNN +F 3 "" H 7250 13150 60 0000 C CNN + 1 7200 13200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U28 +U 1 1 6856DAA3 +P 7200 13800 +F 0 "U28" H 7200 13700 60 0000 C CNN +F 1 "d_inverter" H 7200 13950 60 0000 C CNN +F 2 "" H 7250 13750 60 0000 C CNN +F 3 "" H 7250 13750 60 0000 C CNN + 1 7200 13800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 6856DB6D +P 7200 14350 +F 0 "U29" H 7200 14250 60 0000 C CNN +F 1 "d_inverter" H 7200 14500 60 0000 C CNN +F 2 "" H 7250 14300 60 0000 C CNN +F 3 "" H 7250 14300 60 0000 C CNN + 1 7200 14350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7000 8650 4450 8650 +Wire Wire Line + 4450 8650 4450 5100 +Connection ~ 4450 5100 +Wire Wire Line + 6750 9200 7550 9200 +Connection ~ 6750 7800 +Wire Wire Line + 6550 9300 7550 9300 +Connection ~ 6550 7900 +Wire Wire Line + 6400 9400 7550 9400 +Connection ~ 6400 8000 +Wire Wire Line + 6300 9500 7550 9500 +Connection ~ 6300 8100 +Wire Wire Line + 6100 9600 7550 9600 +Connection ~ 6100 8450 +Wire Wire Line + 7550 9900 4300 9900 +Wire Wire Line + 4300 9900 4300 4100 +Connection ~ 4300 4100 +Wire Wire Line + 4200 4450 4200 10000 +Wire Wire Line + 4200 10000 6950 10000 +Connection ~ 4200 4450 +Wire Wire Line + 8550 9400 8900 9400 +Wire Wire Line + 8900 9400 8900 9550 +Wire Wire Line + 8900 9650 8900 9950 +Wire Wire Line + 8900 9950 8450 9950 +Wire Wire Line + 6550 10700 7500 10700 +Connection ~ 6550 9300 +Wire Wire Line + 6400 10800 7500 10800 +Connection ~ 6400 9400 +Wire Wire Line + 6300 10900 7500 10900 +Connection ~ 6300 9500 +Wire Wire Line + 6100 11250 7550 11250 +Connection ~ 6100 9600 +Wire Wire Line + 4000 3500 4000 11350 +Wire Wire Line + 4000 11350 7550 11350 +Connection ~ 4000 3500 +Wire Wire Line + 6950 11450 3900 11450 +Wire Wire Line + 3900 11450 3900 3750 +Connection ~ 3900 3750 +Wire Wire Line + 8350 10800 8950 10800 +Wire Wire Line + 8950 10800 8950 10950 +Wire Wire Line + 8950 11050 8950 11350 +Wire Wire Line + 8950 11350 8400 11350 +Wire Wire Line + 6400 11950 7500 11950 +Connection ~ 6400 10800 +Wire Wire Line + 6300 12050 7500 12050 +Connection ~ 6300 10900 +Wire Wire Line + 6100 12150 7500 12150 +Connection ~ 6100 11250 +Wire Wire Line + 7500 12250 3800 12250 +Wire Wire Line + 3800 12250 3800 2800 +Connection ~ 3800 2800 +Wire Wire Line + 3700 3150 3700 12350 +Wire Wire Line + 3700 12350 6900 12350 +Connection ~ 3700 3150 +Wire Wire Line + 6300 12900 7500 12900 +Connection ~ 6300 12050 +Wire Wire Line + 6100 13000 7500 13000 +Connection ~ 6100 12150 +Wire Wire Line + 7500 13100 3600 13100 +Wire Wire Line + 3600 13100 3600 2200 +Connection ~ 3600 2200 +Wire Wire Line + 3500 2500 3500 13200 +Wire Wire Line + 3500 13200 6900 13200 +Connection ~ 3500 2500 +Wire Wire Line + 6100 13600 7500 13600 +Connection ~ 6100 13000 +Wire Wire Line + 7500 13700 3400 13700 +Wire Wire Line + 3400 13700 3400 1500 +Connection ~ 3400 1500 +Wire Wire Line + 3250 1850 3250 13800 +Wire Wire Line + 3250 13800 6900 13800 +Connection ~ 3250 1850 +Wire Wire Line + 7500 14250 3100 14250 +Wire Wire Line + 3100 14250 3100 750 +Connection ~ 3100 750 +Wire Wire Line + 3000 850 3000 14350 +Wire Wire Line + 3000 14350 6900 14350 +Connection ~ 3000 850 +$Comp +L d_nand U40 +U 1 1 68575AD3 +P 10500 3550 +F 0 "U40" H 10500 3550 60 0000 C CNN +F 1 "d_nand" H 10550 3650 60 0000 C CNN +F 2 "" H 10500 3550 60 0000 C CNN +F 3 "" H 10500 3550 60 0000 C CNN + 1 10500 3550 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X13 +U 1 1 6857638A +P 11600 9300 +F 0 "X13" H 11750 9200 60 0000 C CNN +F 1 "4_OR" H 11750 9400 60 0000 C CNN +F 2 "" H 11600 9300 60 0000 C CNN +F 3 "" H 11600 9300 60 0000 C CNN + 1 11600 9300 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X14 +U 1 1 68576423 +P 11700 12700 +F 0 "X14" H 11850 12600 60 0000 C CNN +F 1 "4_OR" H 11850 12800 60 0000 C CNN +F 2 "" H 11700 12700 60 0000 C CNN +F 3 "" H 11700 12700 60 0000 C CNN + 1 11700 12700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U41 +U 1 1 685765CA +P 13400 11200 +F 0 "U41" H 13400 11200 60 0000 C CNN +F 1 "d_nor" H 13450 11300 60 0000 C CNN +F 2 "" H 13400 11200 60 0000 C CNN +F 3 "" H 13400 11200 60 0000 C CNN + 1 13400 11200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9850 6500 11000 6500 +Wire Wire Line + 11000 6500 11000 9150 +Wire Wire Line + 11000 9150 11250 9150 +Wire Wire Line + 9900 8250 10800 8250 +Wire Wire Line + 10800 8250 10800 9250 +Wire Wire Line + 10800 9250 11250 9250 +Wire Wire Line + 9800 9600 10850 9600 +Wire Wire Line + 10850 9600 10850 9350 +Wire Wire Line + 10850 9350 11250 9350 +Wire Wire Line + 10900 9450 11250 9450 +Wire Wire Line + 10900 9450 10900 11000 +Wire Wire Line + 10900 11000 9850 11000 +Wire Wire Line + 8500 12150 11350 12150 +Wire Wire Line + 11350 12150 11350 12550 +Wire Wire Line + 8400 13050 8450 13050 +Wire Wire Line + 8450 13050 8450 12650 +Wire Wire Line + 8450 12650 11350 12650 +Wire Wire Line + 8400 14300 11350 14300 +Wire Wire Line + 11350 14300 11350 12850 +Wire Wire Line + 11350 12750 8950 12750 +Wire Wire Line + 8950 12750 8950 13700 +Wire Wire Line + 8950 13700 8350 13700 +Wire Wire Line + 12150 9300 12950 9300 +Wire Wire Line + 12950 9300 12950 11100 +Wire Wire Line + 12950 11200 12950 12700 +Wire Wire Line + 12950 12700 12250 12700 +$Comp +L PORT U1 +U 1 1 68578A87 +P 14100 11150 +F 0 "U1" H 14150 11250 30 0000 C CNN +F 1 "PORT" H 14100 11150 30 0000 C CNN +F 2 "" H 14100 11150 60 0000 C CNN +F 3 "" H 14100 11150 60 0000 C CNN + 1 14100 11150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 6857A97F +P 1400 5500 +F 0 "U1" H 1450 5600 30 0000 C CNN +F 1 "PORT" H 1400 5500 30 0000 C CNN +F 2 "" H 1400 5500 60 0000 C CNN +F 3 "" H 1400 5500 60 0000 C CNN + 2 1400 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6857AA26 +P 1400 5800 +F 0 "U1" H 1450 5900 30 0000 C CNN +F 1 "PORT" H 1400 5800 30 0000 C CNN +F 2 "" H 1400 5800 60 0000 C CNN +F 3 "" H 1400 5800 60 0000 C CNN + 3 1400 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6857AB08 +P 1450 4800 +F 0 "U1" H 1500 4900 30 0000 C CNN +F 1 "PORT" H 1450 4800 30 0000 C CNN +F 2 "" H 1450 4800 60 0000 C CNN +F 3 "" H 1450 4800 60 0000 C CNN + 4 1450 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6857ABB7 +P 1450 5100 +F 0 "U1" H 1500 5200 30 0000 C CNN +F 1 "PORT" H 1450 5100 30 0000 C CNN +F 2 "" H 1450 5100 60 0000 C CNN +F 3 "" H 1450 5100 60 0000 C CNN + 5 1450 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6857B319 +P 1500 4100 +F 0 "U1" H 1550 4200 30 0000 C CNN +F 1 "PORT" H 1500 4100 30 0000 C CNN +F 2 "" H 1500 4100 60 0000 C CNN +F 3 "" H 1500 4100 60 0000 C CNN + 6 1500 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6857B3DA +P 1500 4450 +F 0 "U1" H 1550 4550 30 0000 C CNN +F 1 "PORT" H 1500 4450 30 0000 C CNN +F 2 "" H 1500 4450 60 0000 C CNN +F 3 "" H 1500 4450 60 0000 C CNN + 7 1500 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6857B485 +P 1500 3500 +F 0 "U1" H 1550 3600 30 0000 C CNN +F 1 "PORT" H 1500 3500 30 0000 C CNN +F 2 "" H 1500 3500 60 0000 C CNN +F 3 "" H 1500 3500 60 0000 C CNN + 8 1500 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6857B53E +P 1500 3750 +F 0 "U1" H 1550 3850 30 0000 C CNN +F 1 "PORT" H 1500 3750 30 0000 C CNN +F 2 "" H 1500 3750 60 0000 C CNN +F 3 "" H 1500 3750 60 0000 C CNN + 9 1500 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6857B5E9 +P 1400 6400 +F 0 "U1" H 1450 6500 30 0000 C CNN +F 1 "PORT" H 1400 6400 30 0000 C CNN +F 2 "" H 1400 6400 60 0000 C CNN +F 3 "" H 1400 6400 60 0000 C CNN + 10 1400 6400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6857B6B8 +P 1550 2800 +F 0 "U1" H 1600 2900 30 0000 C CNN +F 1 "PORT" H 1550 2800 30 0000 C CNN +F 2 "" H 1550 2800 60 0000 C CNN +F 3 "" H 1550 2800 60 0000 C CNN + 11 1550 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6857B7CE +P 1550 3150 +F 0 "U1" H 1600 3250 30 0000 C CNN +F 1 "PORT" H 1550 3150 30 0000 C CNN +F 2 "" H 1550 3150 60 0000 C CNN +F 3 "" H 1550 3150 60 0000 C CNN + 12 1550 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6857B87F +P 1550 2200 +F 0 "U1" H 1600 2300 30 0000 C CNN +F 1 "PORT" H 1550 2200 30 0000 C CNN +F 2 "" H 1550 2200 60 0000 C CNN +F 3 "" H 1550 2200 60 0000 C CNN + 13 1550 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 6857B936 +P 1550 2500 +F 0 "U1" H 1600 2600 30 0000 C CNN +F 1 "PORT" H 1550 2500 30 0000 C CNN +F 2 "" H 1550 2500 60 0000 C CNN +F 3 "" H 1550 2500 60 0000 C CNN + 14 1550 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 6857B9FD +P 1550 1500 +F 0 "U1" H 1600 1600 30 0000 C CNN +F 1 "PORT" H 1550 1500 30 0000 C CNN +F 2 "" H 1550 1500 60 0000 C CNN +F 3 "" H 1550 1500 60 0000 C CNN + 15 1550 1500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 6857BAA8 +P 1550 1850 +F 0 "U1" H 1600 1950 30 0000 C CNN +F 1 "PORT" H 1550 1850 30 0000 C CNN +F 2 "" H 1550 1850 60 0000 C CNN +F 3 "" H 1550 1850 60 0000 C CNN + 16 1550 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 17 1 6857BB57 +P 1550 750 +F 0 "U1" H 1600 850 30 0000 C CNN +F 1 "PORT" H 1550 750 30 0000 C CNN +F 2 "" H 1550 750 60 0000 C CNN +F 3 "" H 1550 750 60 0000 C CNN + 17 1550 750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 18 1 6857BC14 +P 1550 1100 +F 0 "U1" H 1600 1200 30 0000 C CNN +F 1 "PORT" H 1550 1100 30 0000 C CNN +F 2 "" H 1550 1100 60 0000 C CNN +F 3 "" H 1550 1100 60 0000 C CNN + 18 1550 1100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 19 1 6857BD13 +P 11200 3500 +F 0 "U1" H 11250 3600 30 0000 C CNN +F 1 "PORT" H 11200 3500 30 0000 C CNN +F 2 "" H 11200 3500 60 0000 C CNN +F 3 "" H 11200 3500 60 0000 C CNN + 19 11200 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 20 1 6857BE21 +P 1400 6750 +F 0 "U1" H 1450 6850 30 0000 C CNN +F 1 "PORT" H 1400 6750 30 0000 C CNN +F 2 "" H 1400 6750 60 0000 C CNN +F 3 "" H 1400 6750 60 0000 C CNN + 20 1400 6750 + 1 0 0 -1 +$EndComp +NoConn ~ 1650 6400 +NoConn ~ 1650 6750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.sub b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.sub new file mode 100644 index 000000000..02c534b2c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684.sub @@ -0,0 +1,184 @@ +* Subcircuit SC_SN74LS684 +.subckt SC_SN74LS684 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn74ls684\sc_sn74ls684.cir +.include 5_and.sub +.include 3_and.sub +.include 4_OR.sub +.include 4_and.sub +* u10 net-_u1-pad17_ net-_u10-pad2_ d_inverter +* u12 net-_u1-pad15_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad16_ net-_u13-pad2_ d_inverter +* u15 net-_u1-pad14_ net-_u15-pad2_ d_inverter +* u16 net-_u1-pad11_ net-_u16-pad2_ d_inverter +* u17 net-_u1-pad12_ net-_u17-pad2_ d_inverter +* u6 net-_u1-pad8_ net-_u22-pad1_ d_inverter +* u7 net-_u1-pad9_ net-_u22-pad2_ d_inverter +* u8 net-_u1-pad6_ net-_u24-pad1_ d_inverter +* u9 net-_u1-pad7_ net-_u24-pad2_ d_inverter +* u4 net-_u1-pad4_ net-_u25-pad1_ d_inverter +* u5 net-_u1-pad5_ net-_u25-pad2_ d_inverter +* u11 net-_u1-pad18_ net-_u11-pad2_ d_inverter +* u14 net-_u1-pad13_ net-_u14-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad3_ net-_u23-pad2_ d_inverter +* u18 net-_u10-pad2_ net-_u11-pad2_ net-_u18-pad3_ d_xnor +* u19 net-_u12-pad2_ net-_u13-pad2_ net-_u19-pad3_ d_xnor +* u20 net-_u14-pad2_ net-_u15-pad2_ net-_u20-pad3_ d_xnor +* u21 net-_u16-pad2_ net-_u17-pad2_ net-_u21-pad3_ d_xnor +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_xnor +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_xnor +* u25 net-_u25-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_xnor +* u23 net-_u2-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_xnor +x12 net-_u18-pad3_ net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ net-_u22-pad3_ net-_u40-pad1_ 5_and +x11 net-_u24-pad3_ net-_u25-pad3_ net-_u23-pad3_ net-_u40-pad2_ 3_and +x9 net-_u25-pad3_ net-_u24-pad3_ net-_u22-pad3_ net-_u21-pad3_ net-_u20-pad3_ net-_u37-pad1_ 5_and +x8 net-_u24-pad3_ net-_u22-pad3_ net-_u21-pad3_ net-_u20-pad3_ net-_u19-pad3_ net-_u39-pad1_ 5_and +x5 net-_u18-pad3_ net-_u25-pad1_ net-_u32-pad2_ net-_u39-pad2_ 3_and +* u39 net-_u39-pad1_ net-_u39-pad2_ net-_u39-pad3_ d_and +x7 net-_u22-pad3_ net-_u21-pad3_ net-_u20-pad3_ net-_u19-pad3_ net-_u18-pad3_ net-_u36-pad1_ 5_and +* u35 net-_u24-pad1_ net-_u30-pad2_ net-_u35-pad3_ d_and +* u36 net-_u36-pad1_ net-_u35-pad3_ net-_u36-pad3_ d_and +x1 net-_u21-pad3_ net-_u20-pad3_ net-_u19-pad3_ net-_u38-pad1_ 3_and +x3 net-_u18-pad3_ net-_u22-pad1_ net-_u31-pad2_ net-_u38-pad2_ 3_and +* u38 net-_u38-pad1_ net-_u38-pad2_ net-_u38-pad3_ d_and +x6 net-_u20-pad3_ net-_u19-pad3_ net-_u18-pad3_ net-_u16-pad2_ net-_u26-pad2_ net-_x14-pad1_ 5_and +x4 net-_u19-pad3_ net-_u18-pad3_ net-_u14-pad2_ net-_u27-pad2_ net-_x14-pad2_ 4_and +x2 net-_u18-pad3_ net-_u12-pad2_ net-_u28-pad2_ net-_x14-pad3_ 3_and +* u34 net-_u10-pad2_ net-_u29-pad2_ net-_u34-pad3_ d_and +x10 net-_u19-pad3_ net-_u18-pad3_ net-_u2-pad2_ net-_u33-pad2_ net-_u37-pad2_ 4_and +* u37 net-_u37-pad1_ net-_u37-pad2_ net-_u37-pad3_ d_and +* u33 net-_u23-pad2_ net-_u33-pad2_ d_inverter +* u32 net-_u25-pad2_ net-_u32-pad2_ d_inverter +* u30 net-_u24-pad2_ net-_u30-pad2_ d_inverter +* u31 net-_u22-pad2_ net-_u31-pad2_ d_inverter +* u26 net-_u17-pad2_ net-_u26-pad2_ d_inverter +* u27 net-_u15-pad2_ net-_u27-pad2_ d_inverter +* u28 net-_u13-pad2_ net-_u28-pad2_ d_inverter +* u29 net-_u11-pad2_ net-_u29-pad2_ d_inverter +* u40 net-_u40-pad1_ net-_u40-pad2_ net-_u1-pad19_ d_nand +x13 net-_u37-pad3_ net-_u39-pad3_ net-_u36-pad3_ net-_u38-pad3_ net-_u41-pad1_ 4_OR +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x14-pad3_ net-_u34-pad3_ net-_u41-pad2_ 4_OR +* u41 net-_u41-pad1_ net-_u41-pad2_ net-_u1-pad1_ d_nor +a1 net-_u1-pad17_ net-_u10-pad2_ u10 +a2 net-_u1-pad15_ net-_u12-pad2_ u12 +a3 net-_u1-pad16_ net-_u13-pad2_ u13 +a4 net-_u1-pad14_ net-_u15-pad2_ u15 +a5 net-_u1-pad11_ net-_u16-pad2_ u16 +a6 net-_u1-pad12_ net-_u17-pad2_ u17 +a7 net-_u1-pad8_ net-_u22-pad1_ u6 +a8 net-_u1-pad9_ net-_u22-pad2_ u7 +a9 net-_u1-pad6_ net-_u24-pad1_ u8 +a10 net-_u1-pad7_ net-_u24-pad2_ u9 +a11 net-_u1-pad4_ net-_u25-pad1_ u4 +a12 net-_u1-pad5_ net-_u25-pad2_ u5 +a13 net-_u1-pad18_ net-_u11-pad2_ u11 +a14 net-_u1-pad13_ net-_u14-pad2_ u14 +a15 net-_u1-pad2_ net-_u2-pad2_ u2 +a16 net-_u1-pad3_ net-_u23-pad2_ u3 +a17 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u19-pad3_ u19 +a19 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u20-pad3_ u20 +a20 [net-_u16-pad2_ net-_u17-pad2_ ] net-_u21-pad3_ u21 +a21 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a22 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 +a23 [net-_u25-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u25 +a24 [net-_u2-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a25 [net-_u39-pad1_ net-_u39-pad2_ ] net-_u39-pad3_ u39 +a26 [net-_u24-pad1_ net-_u30-pad2_ ] net-_u35-pad3_ u35 +a27 [net-_u36-pad1_ net-_u35-pad3_ ] net-_u36-pad3_ u36 +a28 [net-_u38-pad1_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a29 [net-_u10-pad2_ net-_u29-pad2_ ] net-_u34-pad3_ u34 +a30 [net-_u37-pad1_ net-_u37-pad2_ ] net-_u37-pad3_ u37 +a31 net-_u23-pad2_ net-_u33-pad2_ u33 +a32 net-_u25-pad2_ net-_u32-pad2_ u32 +a33 net-_u24-pad2_ net-_u30-pad2_ u30 +a34 net-_u22-pad2_ net-_u31-pad2_ u31 +a35 net-_u17-pad2_ net-_u26-pad2_ u26 +a36 net-_u15-pad2_ net-_u27-pad2_ u27 +a37 net-_u13-pad2_ net-_u28-pad2_ u28 +a38 net-_u11-pad2_ net-_u29-pad2_ u29 +a39 [net-_u40-pad1_ net-_u40-pad2_ ] net-_u1-pad19_ u40 +a40 [net-_u41-pad1_ net-_u41-pad2_ ] net-_u1-pad1_ u41 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u20 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u21 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u22 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u24 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u23 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u41 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_SN74LS684 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684_Previous_Values.xml new file mode 100644 index 000000000..5bd81f8b4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS684/SC_SN74LS684_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_xnord_xnord_xnord_xnord_xnord_xnord_xnord_xnord_andd_andd_andd_andd_andd_andd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_nandd_norC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file From 4e4221592034df3c4094af3865d39d14a55e1464 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:14:04 +0530 Subject: [PATCH 25/33] 4-Bit Arithmetic Logic Unit --- library/SubcircuitLibrary/74F382/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/74F382/analysis diff --git a/library/SubcircuitLibrary/74F382/analysis b/library/SubcircuitLibrary/74F382/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/74F382/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From d1566768d40397614d14dc2b05cc51a1a0673578 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:15:04 +0530 Subject: [PATCH 26/33] 4-Bit Arithmetic Logic Unit --- .../74F382/SC_74F382-cache.lib | 209 ++ .../SubcircuitLibrary/74F382/SC_74F382.cir | 111 + .../74F382/SC_74F382.cir.out | 254 ++ .../SubcircuitLibrary/74F382/SC_74F382.pro | 73 + .../SubcircuitLibrary/74F382/SC_74F382.sch | 2450 +++++++++++++++++ .../SubcircuitLibrary/74F382/SC_74F382.sub | 248 ++ .../74F382/SC_74F382_Previous_Values.xml | 1 + 7 files changed, 3346 insertions(+) create mode 100644 library/SubcircuitLibrary/74F382/SC_74F382-cache.lib create mode 100644 library/SubcircuitLibrary/74F382/SC_74F382.cir create mode 100644 library/SubcircuitLibrary/74F382/SC_74F382.cir.out create mode 100644 library/SubcircuitLibrary/74F382/SC_74F382.pro create mode 100644 library/SubcircuitLibrary/74F382/SC_74F382.sch create mode 100644 library/SubcircuitLibrary/74F382/SC_74F382.sub create mode 100644 library/SubcircuitLibrary/74F382/SC_74F382_Previous_Values.xml diff --git a/library/SubcircuitLibrary/74F382/SC_74F382-cache.lib b/library/SubcircuitLibrary/74F382/SC_74F382-cache.lib new file mode 100644 index 000000000..46dc6b515 --- /dev/null +++ b/library/SubcircuitLibrary/74F382/SC_74F382-cache.lib @@ -0,0 +1,209 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74F382/SC_74F382.cir b/library/SubcircuitLibrary/74F382/SC_74F382.cir new file mode 100644 index 000000000..a178f98bd --- /dev/null +++ b/library/SubcircuitLibrary/74F382/SC_74F382.cir @@ -0,0 +1,111 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_74F382\SC_74F382.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/29/25 14:38:39 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U9-Pad2_ Net-_U5-Pad2_ Net-_U19-Pad3_ Net-_U17-Pad3_ Net-_X1-Pad5_ 4_and +X7 Net-_U16-Pad3_ Net-_U19-Pad3_ Net-_U21-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad3_ Net-_X31-Pad2_ 5_and +X2 Net-_U17-Pad3_ Net-_U21-Pad2_ Net-_U1-Pad4_ Net-_U9-Pad2_ Net-_X2-Pad5_ 4_and +X8 Net-_U9-Pad2_ Net-_U5-Pad2_ Net-_U16-Pad3_ Net-_U21-Pad2_ Net-_U23-Pad3_ Net-_X30-Pad1_ 5_and +X3 Net-_U17-Pad3_ Net-_U19-Pad3_ Net-_U5-Pad2_ Net-_U1-Pad3_ Net-_X3-Pad5_ 4_and +X4 Net-_U17-Pad3_ Net-_U19-Pad3_ Net-_U1-Pad4_ Net-_U9-Pad2_ Net-_X30-Pad3_ 4_and +X5 Net-_U16-Pad3_ Net-_U21-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_X30-Pad4_ 4_and +X31 Net-_X1-Pad5_ Net-_X31-Pad2_ Net-_X2-Pad5_ ? Net-_U25-Pad1_ 4_OR +X30 Net-_X30-Pad1_ Net-_X3-Pad5_ Net-_X30-Pad3_ Net-_X30-Pad4_ Net-_U24-Pad1_ 4_OR +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ d_inverter +U24 Net-_U24-Pad1_ Net-_U24-Pad2_ d_inverter +X9 Net-_U11-Pad2_ Net-_U7-Pad2_ Net-_U19-Pad3_ Net-_U17-Pad3_ Net-_X33-Pad1_ 4_and +X14 Net-_U16-Pad3_ Net-_U19-Pad3_ Net-_U21-Pad2_ Net-_U7-Pad2_ Net-_U1-Pad1_ Net-_X14-Pad6_ 5_and +X10 Net-_U17-Pad3_ Net-_U21-Pad2_ Net-_U1-Pad2_ Net-_U11-Pad2_ Net-_X10-Pad5_ 4_and +X15 Net-_U11-Pad2_ Net-_U7-Pad2_ Net-_U16-Pad3_ Net-_U21-Pad2_ Net-_U23-Pad3_ Net-_X15-Pad6_ 5_and +X11 Net-_U17-Pad3_ Net-_U19-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad1_ Net-_X11-Pad5_ 4_and +X12 Net-_U17-Pad3_ Net-_U19-Pad3_ Net-_U1-Pad2_ Net-_U11-Pad2_ Net-_X12-Pad5_ 4_and +X13 Net-_U16-Pad3_ Net-_U21-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_X13-Pad5_ 4_and +X33 Net-_X33-Pad1_ Net-_X14-Pad6_ Net-_X10-Pad5_ ? Net-_U27-Pad1_ 4_OR +X32 Net-_X15-Pad6_ Net-_X11-Pad5_ Net-_X12-Pad5_ Net-_X13-Pad5_ Net-_U26-Pad1_ 4_OR +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter +U26 Net-_U26-Pad1_ Net-_U26-Pad2_ d_inverter +U18 Net-_U16-Pad1_ Net-_U10-Pad1_ Net-_U18-Pad3_ d_and +U22 Net-_U16-Pad1_ Net-_U15-Pad2_ Net-_U22-Pad3_ d_and +U20 Net-_U10-Pad1_ Net-_U15-Pad2_ Net-_U20-Pad3_ d_and +U19 Net-_U16-Pad1_ Net-_U10-Pad2_ Net-_U19-Pad3_ d_nand +U16 Net-_U16-Pad1_ Net-_U10-Pad1_ Net-_U16-Pad3_ d_nand +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U33 Net-_U1-Pad15_ Net-_U32-Pad3_ Net-_U33-Pad3_ d_nand +U40 Net-_U33-Pad3_ Net-_U24-Pad2_ Net-_U1-Pad8_ d_xor +U9 Net-_U1-Pad3_ Net-_U9-Pad2_ d_inverter +U7 Net-_U1-Pad2_ Net-_U7-Pad2_ d_inverter +U11 Net-_U1-Pad1_ Net-_U11-Pad2_ d_inverter +X41 Net-_U1-Pad15_ Net-_U25-Pad2_ Net-_U32-Pad3_ Net-_U35-Pad1_ 3_and +X42 Net-_U25-Pad2_ Net-_U24-Pad2_ Net-_U32-Pad3_ Net-_U35-Pad2_ 3_and +U35 Net-_U35-Pad1_ Net-_U35-Pad2_ Net-_U35-Pad3_ d_nor +U39 Net-_U35-Pad3_ Net-_U26-Pad2_ Net-_U1-Pad9_ d_xor +X39 Net-_U1-Pad15_ Net-_U25-Pad2_ Net-_U27-Pad2_ Net-_U32-Pad3_ Net-_X39-Pad5_ 4_and +X40 Net-_U25-Pad2_ Net-_U27-Pad2_ Net-_U24-Pad2_ Net-_U32-Pad3_ Net-_X40-Pad5_ 4_and +X38 Net-_U27-Pad2_ Net-_U26-Pad2_ Net-_U32-Pad3_ Net-_X38-Pad4_ 3_and +X52 Net-_X39-Pad5_ Net-_X40-Pad5_ Net-_X38-Pad4_ ? Net-_U38-Pad1_ 4_OR +U38 Net-_U38-Pad1_ Net-_U38-Pad2_ d_inverter +U45 Net-_U38-Pad2_ Net-_U28-Pad2_ Net-_U1-Pad11_ d_xor +X16 Net-_U13-Pad2_ Net-_U6-Pad2_ Net-_U19-Pad3_ Net-_U17-Pad3_ Net-_X16-Pad5_ 4_and +X21 Net-_U16-Pad3_ Net-_U19-Pad3_ Net-_U21-Pad2_ Net-_U6-Pad2_ Net-_U1-Pad19_ Net-_X21-Pad6_ 5_and +X17 Net-_U17-Pad3_ Net-_U21-Pad2_ Net-_U1-Pad18_ Net-_U13-Pad2_ Net-_X17-Pad5_ 4_and +X22 Net-_U13-Pad2_ Net-_U6-Pad2_ Net-_U16-Pad3_ Net-_U21-Pad2_ Net-_U23-Pad3_ Net-_X22-Pad6_ 5_and +X18 Net-_U17-Pad3_ Net-_U19-Pad3_ Net-_U6-Pad2_ Net-_U1-Pad19_ Net-_X18-Pad5_ 4_and +X19 Net-_U17-Pad3_ Net-_U19-Pad3_ Net-_U1-Pad18_ Net-_U13-Pad2_ Net-_X19-Pad5_ 4_and +X20 Net-_U16-Pad3_ Net-_U21-Pad2_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_X20-Pad5_ 4_and +X35 Net-_X16-Pad5_ Net-_X21-Pad6_ Net-_X17-Pad5_ ? Net-_U29-Pad1_ 4_OR +X34 Net-_X22-Pad6_ Net-_X18-Pad5_ Net-_X19-Pad5_ Net-_X20-Pad5_ Net-_U28-Pad1_ 4_OR +U29 Net-_U29-Pad1_ Net-_U29-Pad2_ d_inverter +U28 Net-_U28-Pad1_ Net-_U28-Pad2_ d_inverter +X23 Net-_U14-Pad2_ Net-_U12-Pad2_ Net-_U19-Pad3_ Net-_U17-Pad3_ Net-_X23-Pad5_ 4_and +X28 Net-_U16-Pad3_ Net-_U19-Pad3_ Net-_U21-Pad2_ Net-_U12-Pad2_ Net-_U1-Pad17_ Net-_X28-Pad6_ 5_and +X24 Net-_U17-Pad3_ Net-_U21-Pad2_ Net-_U1-Pad16_ Net-_U14-Pad2_ Net-_X24-Pad5_ 4_and +X29 Net-_U14-Pad2_ Net-_U12-Pad2_ Net-_U16-Pad3_ Net-_U21-Pad2_ Net-_U23-Pad3_ Net-_X29-Pad6_ 5_and +X25 Net-_U17-Pad3_ Net-_U19-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad17_ Net-_X25-Pad5_ 4_and +X26 Net-_U17-Pad3_ Net-_U19-Pad3_ Net-_U1-Pad16_ Net-_U14-Pad2_ Net-_X26-Pad5_ 4_and +X27 Net-_U16-Pad3_ Net-_U21-Pad2_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_X27-Pad5_ 4_and +X37 Net-_X23-Pad5_ Net-_X28-Pad6_ Net-_X24-Pad5_ ? Net-_U31-Pad1_ 4_OR +X36 Net-_X29-Pad6_ Net-_X25-Pad5_ Net-_X26-Pad5_ Net-_X27-Pad5_ Net-_U30-Pad1_ 4_OR +U31 Net-_U31-Pad1_ Net-_U31-Pad2_ d_inverter +U30 Net-_U30-Pad1_ Net-_U30-Pad2_ d_inverter +U6 Net-_U1-Pad18_ Net-_U6-Pad2_ d_inverter +U13 Net-_U1-Pad19_ Net-_U13-Pad2_ d_inverter +U12 Net-_U1-Pad16_ Net-_U12-Pad2_ d_inverter +U14 Net-_U1-Pad17_ Net-_U14-Pad2_ d_inverter +U2 Net-_U1-Pad5_ Net-_U16-Pad1_ d_inverter +U8 Net-_U16-Pad1_ Net-_U8-Pad2_ d_inverter +U3 Net-_U1-Pad6_ Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U4 Net-_U1-Pad7_ Net-_U15-Pad1_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U32 Net-_U18-Pad3_ Net-_U15-Pad2_ Net-_U32-Pad3_ d_xor +U17 Net-_U10-Pad1_ Net-_U15-Pad1_ Net-_U17-Pad3_ d_nand +X6 Net-_U8-Pad2_ Net-_U10-Pad2_ Net-_U15-Pad1_ Net-_U21-Pad1_ 3_and +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ d_inverter +U23 Net-_U22-Pad3_ Net-_U20-Pad3_ Net-_U23-Pad3_ d_nor +X47 Net-_U1-Pad15_ Net-_U25-Pad2_ Net-_U27-Pad2_ Net-_U29-Pad2_ Net-_U32-Pad3_ Net-_X47-Pad6_ 5_and +X48 Net-_U25-Pad2_ Net-_U27-Pad2_ Net-_U29-Pad2_ Net-_U24-Pad2_ Net-_U32-Pad3_ Net-_X48-Pad6_ 5_and +X44 Net-_U27-Pad2_ Net-_U29-Pad2_ Net-_U26-Pad2_ Net-_U32-Pad3_ Net-_X44-Pad5_ 4_and +X43 Net-_U29-Pad2_ Net-_U28-Pad2_ Net-_U32-Pad3_ Net-_X43-Pad4_ 3_and +X54 Net-_X47-Pad6_ Net-_X48-Pad6_ Net-_X44-Pad5_ Net-_X43-Pad4_ Net-_U43-Pad1_ 4_OR +U43 Net-_U43-Pad1_ Net-_U43-Pad2_ d_inverter +U46 Net-_U43-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad12_ d_xor +U47 Net-_U43-Pad2_ Net-_U42-Pad3_ Net-_U1-Pad13_ d_xor +X45 Net-_U25-Pad2_ Net-_U27-Pad2_ Net-_U29-Pad2_ Net-_U31-Pad2_ Net-_U37-Pad1_ 4_and +U37 Net-_U37-Pad1_ ? d_inverter +X49 Net-_U25-Pad2_ Net-_U27-Pad2_ Net-_U29-Pad2_ Net-_U31-Pad2_ Net-_U24-Pad2_ Net-_X49-Pad6_ 5_and +X50 Net-_U27-Pad2_ Net-_U29-Pad2_ Net-_U31-Pad2_ Net-_U26-Pad2_ Net-_X50-Pad5_ 4_and +X46 Net-_U29-Pad2_ Net-_U31-Pad2_ Net-_U28-Pad2_ Net-_X46-Pad4_ 3_and +U34 Net-_U31-Pad2_ Net-_U30-Pad2_ Net-_U34-Pad3_ d_and +U36 Net-_U36-Pad1_ Net-_U36-Pad2_ d_inverter +U44 Net-_U41-Pad2_ Net-_U36-Pad2_ Net-_U1-Pad14_ d_nand +U42 Net-_U41-Pad2_ Net-_U36-Pad2_ Net-_U42-Pad3_ d_and +X53 Net-_X49-Pad6_ Net-_X50-Pad5_ Net-_X46-Pad4_ Net-_U34-Pad3_ Net-_U41-Pad1_ 4_OR +U41 Net-_U41-Pad1_ Net-_U41-Pad2_ d_inverter +X51 Net-_U1-Pad15_ Net-_U25-Pad2_ Net-_U27-Pad2_ Net-_U29-Pad2_ Net-_U31-Pad2_ Net-_U36-Pad1_ 5_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ ? Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/74F382/SC_74F382.cir.out b/library/SubcircuitLibrary/74F382/SC_74F382.cir.out new file mode 100644 index 000000000..a4a82c031 --- /dev/null +++ b/library/SubcircuitLibrary/74F382/SC_74F382.cir.out @@ -0,0 +1,254 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_74f382\sc_74f382.cir + +.include 4_and.sub +.include 4_OR.sub +.include 5_and.sub +.include 3_and.sub +x1 net-_u9-pad2_ net-_u5-pad2_ net-_u19-pad3_ net-_u17-pad3_ net-_x1-pad5_ 4_and +x7 net-_u16-pad3_ net-_u19-pad3_ net-_u21-pad2_ net-_u5-pad2_ net-_u1-pad3_ net-_x31-pad2_ 5_and +x2 net-_u17-pad3_ net-_u21-pad2_ net-_u1-pad4_ net-_u9-pad2_ net-_x2-pad5_ 4_and +x8 net-_u9-pad2_ net-_u5-pad2_ net-_u16-pad3_ net-_u21-pad2_ net-_u23-pad3_ net-_x30-pad1_ 5_and +x3 net-_u17-pad3_ net-_u19-pad3_ net-_u5-pad2_ net-_u1-pad3_ net-_x3-pad5_ 4_and +x4 net-_u17-pad3_ net-_u19-pad3_ net-_u1-pad4_ net-_u9-pad2_ net-_x30-pad3_ 4_and +x5 net-_u16-pad3_ net-_u21-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_x30-pad4_ 4_and +x31 net-_x1-pad5_ net-_x31-pad2_ net-_x2-pad5_ ? net-_u25-pad1_ 4_OR +x30 net-_x30-pad1_ net-_x3-pad5_ net-_x30-pad3_ net-_x30-pad4_ net-_u24-pad1_ 4_OR +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u24-pad2_ d_inverter +x9 net-_u11-pad2_ net-_u7-pad2_ net-_u19-pad3_ net-_u17-pad3_ net-_x33-pad1_ 4_and +x14 net-_u16-pad3_ net-_u19-pad3_ net-_u21-pad2_ net-_u7-pad2_ net-_u1-pad1_ net-_x14-pad6_ 5_and +x10 net-_u17-pad3_ net-_u21-pad2_ net-_u1-pad2_ net-_u11-pad2_ net-_x10-pad5_ 4_and +x15 net-_u11-pad2_ net-_u7-pad2_ net-_u16-pad3_ net-_u21-pad2_ net-_u23-pad3_ net-_x15-pad6_ 5_and +x11 net-_u17-pad3_ net-_u19-pad3_ net-_u7-pad2_ net-_u1-pad1_ net-_x11-pad5_ 4_and +x12 net-_u17-pad3_ net-_u19-pad3_ net-_u1-pad2_ net-_u11-pad2_ net-_x12-pad5_ 4_and +x13 net-_u16-pad3_ net-_u21-pad2_ net-_u1-pad2_ net-_u1-pad1_ net-_x13-pad5_ 4_and +x33 net-_x33-pad1_ net-_x14-pad6_ net-_x10-pad5_ ? net-_u27-pad1_ 4_OR +x32 net-_x15-pad6_ net-_x11-pad5_ net-_x12-pad5_ net-_x13-pad5_ net-_u26-pad1_ 4_OR +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u18 net-_u16-pad1_ net-_u10-pad1_ net-_u18-pad3_ d_and +* u22 net-_u16-pad1_ net-_u15-pad2_ net-_u22-pad3_ d_and +* u20 net-_u10-pad1_ net-_u15-pad2_ net-_u20-pad3_ d_and +* u19 net-_u16-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_nand +* u16 net-_u16-pad1_ net-_u10-pad1_ net-_u16-pad3_ d_nand +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u33 net-_u1-pad15_ net-_u32-pad3_ net-_u33-pad3_ d_nand +* u40 net-_u33-pad3_ net-_u24-pad2_ net-_u1-pad8_ d_xor +* u9 net-_u1-pad3_ net-_u9-pad2_ d_inverter +* u7 net-_u1-pad2_ net-_u7-pad2_ d_inverter +* u11 net-_u1-pad1_ net-_u11-pad2_ d_inverter +x41 net-_u1-pad15_ net-_u25-pad2_ net-_u32-pad3_ net-_u35-pad1_ 3_and +x42 net-_u25-pad2_ net-_u24-pad2_ net-_u32-pad3_ net-_u35-pad2_ 3_and +* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u35-pad3_ d_nor +* u39 net-_u35-pad3_ net-_u26-pad2_ net-_u1-pad9_ d_xor +x39 net-_u1-pad15_ net-_u25-pad2_ net-_u27-pad2_ net-_u32-pad3_ net-_x39-pad5_ 4_and +x40 net-_u25-pad2_ net-_u27-pad2_ net-_u24-pad2_ net-_u32-pad3_ net-_x40-pad5_ 4_and +x38 net-_u27-pad2_ net-_u26-pad2_ net-_u32-pad3_ net-_x38-pad4_ 3_and +x52 net-_x39-pad5_ net-_x40-pad5_ net-_x38-pad4_ ? net-_u38-pad1_ 4_OR +* u38 net-_u38-pad1_ net-_u38-pad2_ d_inverter +* u45 net-_u38-pad2_ net-_u28-pad2_ net-_u1-pad11_ d_xor +x16 net-_u13-pad2_ net-_u6-pad2_ net-_u19-pad3_ net-_u17-pad3_ net-_x16-pad5_ 4_and +x21 net-_u16-pad3_ net-_u19-pad3_ net-_u21-pad2_ net-_u6-pad2_ net-_u1-pad19_ net-_x21-pad6_ 5_and +x17 net-_u17-pad3_ net-_u21-pad2_ net-_u1-pad18_ net-_u13-pad2_ net-_x17-pad5_ 4_and +x22 net-_u13-pad2_ net-_u6-pad2_ net-_u16-pad3_ net-_u21-pad2_ net-_u23-pad3_ net-_x22-pad6_ 5_and +x18 net-_u17-pad3_ net-_u19-pad3_ net-_u6-pad2_ net-_u1-pad19_ net-_x18-pad5_ 4_and +x19 net-_u17-pad3_ net-_u19-pad3_ net-_u1-pad18_ net-_u13-pad2_ net-_x19-pad5_ 4_and +x20 net-_u16-pad3_ net-_u21-pad2_ net-_u1-pad18_ net-_u1-pad19_ net-_x20-pad5_ 4_and +x35 net-_x16-pad5_ net-_x21-pad6_ net-_x17-pad5_ ? net-_u29-pad1_ 4_OR +x34 net-_x22-pad6_ net-_x18-pad5_ net-_x19-pad5_ net-_x20-pad5_ net-_u28-pad1_ 4_OR +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter +x23 net-_u14-pad2_ net-_u12-pad2_ net-_u19-pad3_ net-_u17-pad3_ net-_x23-pad5_ 4_and +x28 net-_u16-pad3_ net-_u19-pad3_ net-_u21-pad2_ net-_u12-pad2_ net-_u1-pad17_ net-_x28-pad6_ 5_and +x24 net-_u17-pad3_ net-_u21-pad2_ net-_u1-pad16_ net-_u14-pad2_ net-_x24-pad5_ 4_and +x29 net-_u14-pad2_ net-_u12-pad2_ net-_u16-pad3_ net-_u21-pad2_ net-_u23-pad3_ net-_x29-pad6_ 5_and +x25 net-_u17-pad3_ net-_u19-pad3_ net-_u12-pad2_ net-_u1-pad17_ net-_x25-pad5_ 4_and +x26 net-_u17-pad3_ net-_u19-pad3_ net-_u1-pad16_ net-_u14-pad2_ net-_x26-pad5_ 4_and +x27 net-_u16-pad3_ net-_u21-pad2_ net-_u1-pad16_ net-_u1-pad17_ net-_x27-pad5_ 4_and +x37 net-_x23-pad5_ net-_x28-pad6_ net-_x24-pad5_ ? net-_u31-pad1_ 4_OR +x36 net-_x29-pad6_ net-_x25-pad5_ net-_x26-pad5_ net-_x27-pad5_ net-_u30-pad1_ 4_OR +* u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u6 net-_u1-pad18_ net-_u6-pad2_ d_inverter +* u13 net-_u1-pad19_ net-_u13-pad2_ d_inverter +* u12 net-_u1-pad16_ net-_u12-pad2_ d_inverter +* u14 net-_u1-pad17_ net-_u14-pad2_ d_inverter +* u2 net-_u1-pad5_ net-_u16-pad1_ d_inverter +* u8 net-_u16-pad1_ net-_u8-pad2_ d_inverter +* u3 net-_u1-pad6_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad7_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u32 net-_u18-pad3_ net-_u15-pad2_ net-_u32-pad3_ d_xor +* u17 net-_u10-pad1_ net-_u15-pad1_ net-_u17-pad3_ d_nand +x6 net-_u8-pad2_ net-_u10-pad2_ net-_u15-pad1_ net-_u21-pad1_ 3_and +* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter +* u23 net-_u22-pad3_ net-_u20-pad3_ net-_u23-pad3_ d_nor +x47 net-_u1-pad15_ net-_u25-pad2_ net-_u27-pad2_ net-_u29-pad2_ net-_u32-pad3_ net-_x47-pad6_ 5_and +x48 net-_u25-pad2_ net-_u27-pad2_ net-_u29-pad2_ net-_u24-pad2_ net-_u32-pad3_ net-_x48-pad6_ 5_and +x44 net-_u27-pad2_ net-_u29-pad2_ net-_u26-pad2_ net-_u32-pad3_ net-_x44-pad5_ 4_and +x43 net-_u29-pad2_ net-_u28-pad2_ net-_u32-pad3_ net-_x43-pad4_ 3_and +x54 net-_x47-pad6_ net-_x48-pad6_ net-_x44-pad5_ net-_x43-pad4_ net-_u43-pad1_ 4_OR +* u43 net-_u43-pad1_ net-_u43-pad2_ d_inverter +* u46 net-_u43-pad2_ net-_u30-pad2_ net-_u1-pad12_ d_xor +* u47 net-_u43-pad2_ net-_u42-pad3_ net-_u1-pad13_ d_xor +x45 net-_u25-pad2_ net-_u27-pad2_ net-_u29-pad2_ net-_u31-pad2_ net-_u37-pad1_ 4_and +* u37 net-_u37-pad1_ ? d_inverter +x49 net-_u25-pad2_ net-_u27-pad2_ net-_u29-pad2_ net-_u31-pad2_ net-_u24-pad2_ net-_x49-pad6_ 5_and +x50 net-_u27-pad2_ net-_u29-pad2_ net-_u31-pad2_ net-_u26-pad2_ net-_x50-pad5_ 4_and +x46 net-_u29-pad2_ net-_u31-pad2_ net-_u28-pad2_ net-_x46-pad4_ 3_and +* u34 net-_u31-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_and +* u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter +* u44 net-_u41-pad2_ net-_u36-pad2_ net-_u1-pad14_ d_nand +* u42 net-_u41-pad2_ net-_u36-pad2_ net-_u42-pad3_ d_and +x53 net-_x49-pad6_ net-_x50-pad5_ net-_x46-pad4_ net-_u34-pad3_ net-_u41-pad1_ 4_OR +* u41 net-_u41-pad1_ net-_u41-pad2_ d_inverter +x51 net-_u1-pad15_ net-_u25-pad2_ net-_u27-pad2_ net-_u29-pad2_ net-_u31-pad2_ net-_u36-pad1_ 5_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? port +a1 net-_u25-pad1_ net-_u25-pad2_ u25 +a2 net-_u24-pad1_ net-_u24-pad2_ u24 +a3 net-_u27-pad1_ net-_u27-pad2_ u27 +a4 net-_u26-pad1_ net-_u26-pad2_ u26 +a5 [net-_u16-pad1_ net-_u10-pad1_ ] net-_u18-pad3_ u18 +a6 [net-_u16-pad1_ net-_u15-pad2_ ] net-_u22-pad3_ u22 +a7 [net-_u10-pad1_ net-_u15-pad2_ ] net-_u20-pad3_ u20 +a8 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19 +a9 [net-_u16-pad1_ net-_u10-pad1_ ] net-_u16-pad3_ u16 +a10 net-_u1-pad4_ net-_u5-pad2_ u5 +a11 [net-_u1-pad15_ net-_u32-pad3_ ] net-_u33-pad3_ u33 +a12 [net-_u33-pad3_ net-_u24-pad2_ ] net-_u1-pad8_ u40 +a13 net-_u1-pad3_ net-_u9-pad2_ u9 +a14 net-_u1-pad2_ net-_u7-pad2_ u7 +a15 net-_u1-pad1_ net-_u11-pad2_ u11 +a16 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u35-pad3_ u35 +a17 [net-_u35-pad3_ net-_u26-pad2_ ] net-_u1-pad9_ u39 +a18 net-_u38-pad1_ net-_u38-pad2_ u38 +a19 [net-_u38-pad2_ net-_u28-pad2_ ] net-_u1-pad11_ u45 +a20 net-_u29-pad1_ net-_u29-pad2_ u29 +a21 net-_u28-pad1_ net-_u28-pad2_ u28 +a22 net-_u31-pad1_ net-_u31-pad2_ u31 +a23 net-_u30-pad1_ net-_u30-pad2_ u30 +a24 net-_u1-pad18_ net-_u6-pad2_ u6 +a25 net-_u1-pad19_ net-_u13-pad2_ u13 +a26 net-_u1-pad16_ net-_u12-pad2_ u12 +a27 net-_u1-pad17_ net-_u14-pad2_ u14 +a28 net-_u1-pad5_ net-_u16-pad1_ u2 +a29 net-_u16-pad1_ net-_u8-pad2_ u8 +a30 net-_u1-pad6_ net-_u10-pad1_ u3 +a31 net-_u10-pad1_ net-_u10-pad2_ u10 +a32 net-_u1-pad7_ net-_u15-pad1_ u4 +a33 net-_u15-pad1_ net-_u15-pad2_ u15 +a34 [net-_u18-pad3_ net-_u15-pad2_ ] net-_u32-pad3_ u32 +a35 [net-_u10-pad1_ net-_u15-pad1_ ] net-_u17-pad3_ u17 +a36 net-_u21-pad1_ net-_u21-pad2_ u21 +a37 [net-_u22-pad3_ net-_u20-pad3_ ] net-_u23-pad3_ u23 +a38 net-_u43-pad1_ net-_u43-pad2_ u43 +a39 [net-_u43-pad2_ net-_u30-pad2_ ] net-_u1-pad12_ u46 +a40 [net-_u43-pad2_ net-_u42-pad3_ ] net-_u1-pad13_ u47 +a41 net-_u37-pad1_ ? u37 +a42 [net-_u31-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34 +a43 net-_u36-pad1_ net-_u36-pad2_ u36 +a44 [net-_u41-pad2_ net-_u36-pad2_ ] net-_u1-pad14_ u44 +a45 [net-_u41-pad2_ net-_u36-pad2_ ] net-_u42-pad3_ u42 +a46 net-_u41-pad1_ net-_u41-pad2_ u41 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u40 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u39 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u45 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u32 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u46 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u47 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u44 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74F382/SC_74F382.pro b/library/SubcircuitLibrary/74F382/SC_74F382.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74F382/SC_74F382.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74F382/SC_74F382.sch b/library/SubcircuitLibrary/74F382/SC_74F382.sch new file mode 100644 index 000000000..3cfea7c34 --- /dev/null +++ b/library/SubcircuitLibrary/74F382/SC_74F382.sch @@ -0,0 +1,2450 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_74F382-cache +EELAYER 25 0 +EELAYER END +$Descr D 22000 34000 portrait +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4_and X1 +U 1 1 685E4FCF +P 7800 4350 +F 0 "X1" H 7850 4300 60 0000 C CNN +F 1 "4_and" H 7900 4450 60 0000 C CNN +F 2 "" H 7800 4350 60 0000 C CNN +F 3 "" H 7800 4350 60 0000 C CNN + 1 7800 4350 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X7 +U 1 1 685E502E +P 7850 5000 +F 0 "X7" H 7900 4900 60 0000 C CNN +F 1 "5_and" H 7950 5150 60 0000 C CNN +F 2 "" H 7850 5000 60 0000 C CNN +F 3 "" H 7850 5000 60 0000 C CNN + 1 7850 5000 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 685E5075 +P 7800 5750 +F 0 "X2" H 7850 5700 60 0000 C CNN +F 1 "4_and" H 7900 5850 60 0000 C CNN +F 2 "" H 7800 5750 60 0000 C CNN +F 3 "" H 7800 5750 60 0000 C CNN + 1 7800 5750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X8 +U 1 1 685E50C8 +P 7850 6450 +F 0 "X8" H 7900 6350 60 0000 C CNN +F 1 "5_and" H 7950 6600 60 0000 C CNN +F 2 "" H 7850 6450 60 0000 C CNN +F 3 "" H 7850 6450 60 0000 C CNN + 1 7850 6450 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 685E5113 +P 7800 7200 +F 0 "X3" H 7850 7150 60 0000 C CNN +F 1 "4_and" H 7900 7300 60 0000 C CNN +F 2 "" H 7800 7200 60 0000 C CNN +F 3 "" H 7800 7200 60 0000 C CNN + 1 7800 7200 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 685E518E +P 7800 7850 +F 0 "X4" H 7850 7800 60 0000 C CNN +F 1 "4_and" H 7900 7950 60 0000 C CNN +F 2 "" H 7800 7850 60 0000 C CNN +F 3 "" H 7800 7850 60 0000 C CNN + 1 7800 7850 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 685E51EB +P 7800 8450 +F 0 "X5" H 7850 8400 60 0000 C CNN +F 1 "4_and" H 7900 8550 60 0000 C CNN +F 2 "" H 7800 8450 60 0000 C CNN +F 3 "" H 7800 8450 60 0000 C CNN + 1 7800 8450 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X31 +U 1 1 685E5236 +P 10100 5250 +F 0 "X31" H 10250 5150 60 0000 C CNN +F 1 "4_OR" H 10250 5350 60 0000 C CNN +F 2 "" H 10100 5250 60 0000 C CNN +F 3 "" H 10100 5250 60 0000 C CNN + 1 10100 5250 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X30 +U 1 1 685E52C5 +P 10050 7350 +F 0 "X30" H 10200 7250 60 0000 C CNN +F 1 "4_OR" H 10200 7450 60 0000 C CNN +F 2 "" H 10050 7350 60 0000 C CNN +F 3 "" H 10050 7350 60 0000 C CNN + 1 10050 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 685E5328 +P 10950 5250 +F 0 "U25" H 10950 5150 60 0000 C CNN +F 1 "d_inverter" H 10950 5400 60 0000 C CNN +F 2 "" H 11000 5200 60 0000 C CNN +F 3 "" H 11000 5200 60 0000 C CNN + 1 10950 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 685E539F +P 10900 7350 +F 0 "U24" H 10900 7250 60 0000 C CNN +F 1 "d_inverter" H 10900 7500 60 0000 C CNN +F 2 "" H 10950 7300 60 0000 C CNN +F 3 "" H 10950 7300 60 0000 C CNN + 1 10900 7350 + 1 0 0 -1 +$EndComp +NoConn ~ 9750 5400 +$Comp +L 4_and X9 +U 1 1 685E57A1 +P 7850 9000 +F 0 "X9" H 7900 8950 60 0000 C CNN +F 1 "4_and" H 7950 9100 60 0000 C CNN +F 2 "" H 7850 9000 60 0000 C CNN +F 3 "" H 7850 9000 60 0000 C CNN + 1 7850 9000 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X14 +U 1 1 685E57A8 +P 7900 9650 +F 0 "X14" H 7950 9550 60 0000 C CNN +F 1 "5_and" H 8000 9800 60 0000 C CNN +F 2 "" H 7900 9650 60 0000 C CNN +F 3 "" H 7900 9650 60 0000 C CNN + 1 7900 9650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X10 +U 1 1 685E57AF +P 7850 10400 +F 0 "X10" H 7900 10350 60 0000 C CNN +F 1 "4_and" H 7950 10500 60 0000 C CNN +F 2 "" H 7850 10400 60 0000 C CNN +F 3 "" H 7850 10400 60 0000 C CNN + 1 7850 10400 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X15 +U 1 1 685E57B6 +P 7900 11100 +F 0 "X15" H 7950 11000 60 0000 C CNN +F 1 "5_and" H 8000 11250 60 0000 C CNN +F 2 "" H 7900 11100 60 0000 C CNN +F 3 "" H 7900 11100 60 0000 C CNN + 1 7900 11100 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X11 +U 1 1 685E57BD +P 7850 11850 +F 0 "X11" H 7900 11800 60 0000 C CNN +F 1 "4_and" H 7950 11950 60 0000 C CNN +F 2 "" H 7850 11850 60 0000 C CNN +F 3 "" H 7850 11850 60 0000 C CNN + 1 7850 11850 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X12 +U 1 1 685E57C4 +P 7850 12500 +F 0 "X12" H 7900 12450 60 0000 C CNN +F 1 "4_and" H 7950 12600 60 0000 C CNN +F 2 "" H 7850 12500 60 0000 C CNN +F 3 "" H 7850 12500 60 0000 C CNN + 1 7850 12500 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X13 +U 1 1 685E57CB +P 7850 13100 +F 0 "X13" H 7900 13050 60 0000 C CNN +F 1 "4_and" H 7950 13200 60 0000 C CNN +F 2 "" H 7850 13100 60 0000 C CNN +F 3 "" H 7850 13100 60 0000 C CNN + 1 7850 13100 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X33 +U 1 1 685E57D2 +P 10150 9900 +F 0 "X33" H 10300 9800 60 0000 C CNN +F 1 "4_OR" H 10300 10000 60 0000 C CNN +F 2 "" H 10150 9900 60 0000 C CNN +F 3 "" H 10150 9900 60 0000 C CNN + 1 10150 9900 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X32 +U 1 1 685E57D9 +P 10100 12000 +F 0 "X32" H 10250 11900 60 0000 C CNN +F 1 "4_OR" H 10250 12100 60 0000 C CNN +F 2 "" H 10100 12000 60 0000 C CNN +F 3 "" H 10100 12000 60 0000 C CNN + 1 10100 12000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 685E57E0 +P 11000 9900 +F 0 "U27" H 11000 9800 60 0000 C CNN +F 1 "d_inverter" H 11000 10050 60 0000 C CNN +F 2 "" H 11050 9850 60 0000 C CNN +F 3 "" H 11050 9850 60 0000 C CNN + 1 11000 9900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U26 +U 1 1 685E57E7 +P 10950 12000 +F 0 "U26" H 10950 11900 60 0000 C CNN +F 1 "d_inverter" H 10950 12150 60 0000 C CNN +F 2 "" H 11000 11950 60 0000 C CNN +F 3 "" H 11000 11950 60 0000 C CNN + 1 10950 12000 + 1 0 0 -1 +$EndComp +NoConn ~ 9800 10050 +$Comp +L d_and U18 +U 1 1 685FAF75 +P 7850 23900 +F 0 "U18" H 7850 23900 60 0000 C CNN +F 1 "d_and" H 7900 24000 60 0000 C CNN +F 2 "" H 7850 23900 60 0000 C CNN +F 3 "" H 7850 23900 60 0000 C CNN + 1 7850 23900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 685FB01C +P 9250 24200 +F 0 "U22" H 9250 24200 60 0000 C CNN +F 1 "d_and" H 9300 24300 60 0000 C CNN +F 2 "" H 9250 24200 60 0000 C CNN +F 3 "" H 9250 24200 60 0000 C CNN + 1 9250 24200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 685FB0D3 +P 7900 26150 +F 0 "U20" H 7900 26150 60 0000 C CNN +F 1 "d_and" H 7950 26250 60 0000 C CNN +F 2 "" H 7900 26150 60 0000 C CNN +F 3 "" H 7900 26150 60 0000 C CNN + 1 7900 26150 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U19 +U 1 1 685FB17E +P 7900 24650 +F 0 "U19" H 7900 24650 60 0000 C CNN +F 1 "d_nand" H 7950 24750 60 0000 C CNN +F 2 "" H 7900 24650 60 0000 C CNN +F 3 "" H 7900 24650 60 0000 C CNN + 1 7900 24650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U16 +U 1 1 685FB21D +P 6200 24500 +F 0 "U16" H 6200 24500 60 0000 C CNN +F 1 "d_nand" H 6250 24600 60 0000 C CNN +F 2 "" H 6200 24500 60 0000 C CNN +F 3 "" H 6200 24500 60 0000 C CNN + 1 6200 24500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 685FDE04 +P 4250 4300 +F 0 "U5" H 4250 4200 60 0000 C CNN +F 1 "d_inverter" H 4250 4450 60 0000 C CNN +F 2 "" H 4300 4250 60 0000 C CNN +F 3 "" H 4300 4250 60 0000 C CNN + 1 4250 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U33 +U 1 1 685FFA77 +P 14650 5300 +F 0 "U33" H 14650 5300 60 0000 C CNN +F 1 "d_nand" H 14700 5400 60 0000 C CNN +F 2 "" H 14650 5300 60 0000 C CNN +F 3 "" H 14650 5300 60 0000 C CNN + 1 14650 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U40 +U 1 1 685FFB7E +P 16700 5600 +F 0 "U40" H 16700 5600 60 0000 C CNN +F 1 "d_xor" H 16750 5700 47 0000 C CNN +F 2 "" H 16700 5600 60 0000 C CNN +F 3 "" H 16700 5600 60 0000 C CNN + 1 16700 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6860364C +P 4500 7100 +F 0 "U9" H 4500 7000 60 0000 C CNN +F 1 "d_inverter" H 4500 7250 60 0000 C CNN +F 2 "" H 4550 7050 60 0000 C CNN +F 3 "" H 4550 7050 60 0000 C CNN + 1 4500 7100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68604A47 +P 4450 9550 +F 0 "U7" H 4450 9450 60 0000 C CNN +F 1 "d_inverter" H 4450 9700 60 0000 C CNN +F 2 "" H 4500 9500 60 0000 C CNN +F 3 "" H 4500 9500 60 0000 C CNN + 1 4450 9550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 68604B78 +P 4550 11950 +F 0 "U11" H 4550 11850 60 0000 C CNN +F 1 "d_inverter" H 4550 12100 60 0000 C CNN +F 2 "" H 4600 11900 60 0000 C CNN +F 3 "" H 4600 11900 60 0000 C CNN + 1 4550 11950 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X41 +U 1 1 68606FD1 +P 13600 10450 +F 0 "X41" H 13700 10400 60 0000 C CNN +F 1 "3_and" H 13750 10600 60 0000 C CNN +F 2 "" H 13600 10450 60 0000 C CNN +F 3 "" H 13600 10450 60 0000 C CNN + 1 13600 10450 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X42 +U 1 1 68607072 +P 13600 11150 +F 0 "X42" H 13700 11100 60 0000 C CNN +F 1 "3_and" H 13750 11300 60 0000 C CNN +F 2 "" H 13600 11150 60 0000 C CNN +F 3 "" H 13600 11150 60 0000 C CNN + 1 13600 11150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U35 +U 1 1 6860711D +P 14850 10700 +F 0 "U35" H 14850 10700 60 0000 C CNN +F 1 "d_nor" H 14900 10800 60 0000 C CNN +F 2 "" H 14850 10700 60 0000 C CNN +F 3 "" H 14850 10700 60 0000 C CNN + 1 14850 10700 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U39 +U 1 1 686071D2 +P 16550 11350 +F 0 "U39" H 16550 11350 60 0000 C CNN +F 1 "d_xor" H 16600 11450 47 0000 C CNN +F 2 "" H 16550 11350 60 0000 C CNN +F 3 "" H 16550 11350 60 0000 C CNN + 1 16550 11350 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X39 +U 1 1 6861FA6F +P 13250 15550 +F 0 "X39" H 13300 15500 60 0000 C CNN +F 1 "4_and" H 13350 15650 60 0000 C CNN +F 2 "" H 13250 15550 60 0000 C CNN +F 3 "" H 13250 15550 60 0000 C CNN + 1 13250 15550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X40 +U 1 1 6861FB40 +P 13250 16250 +F 0 "X40" H 13300 16200 60 0000 C CNN +F 1 "4_and" H 13350 16350 60 0000 C CNN +F 2 "" H 13250 16250 60 0000 C CNN +F 3 "" H 13250 16250 60 0000 C CNN + 1 13250 16250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X38 +U 1 1 6861FBF1 +P 13200 16950 +F 0 "X38" H 13300 16900 60 0000 C CNN +F 1 "3_and" H 13350 17100 60 0000 C CNN +F 2 "" H 13200 16950 60 0000 C CNN +F 3 "" H 13200 16950 60 0000 C CNN + 1 13200 16950 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X52 +U 1 1 6861FCAA +P 15100 16250 +F 0 "X52" H 15250 16150 60 0000 C CNN +F 1 "4_OR" H 15250 16350 60 0000 C CNN +F 2 "" H 15100 16250 60 0000 C CNN +F 3 "" H 15100 16250 60 0000 C CNN + 1 15100 16250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U38 +U 1 1 6861FD49 +P 15950 16250 +F 0 "U38" H 15950 16150 60 0000 C CNN +F 1 "d_inverter" H 15950 16400 60 0000 C CNN +F 2 "" H 16000 16200 60 0000 C CNN +F 3 "" H 16000 16200 60 0000 C CNN + 1 15950 16250 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U45 +U 1 1 68620B3E +P 17800 17250 +F 0 "U45" H 17800 17250 60 0000 C CNN +F 1 "d_xor" H 17850 17350 47 0000 C CNN +F 2 "" H 17800 17250 60 0000 C CNN +F 3 "" H 17800 17250 60 0000 C CNN + 1 17800 17250 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X16 +U 1 1 6862BEF9 +P 7900 14100 +F 0 "X16" H 7950 14050 60 0000 C CNN +F 1 "4_and" H 8000 14200 60 0000 C CNN +F 2 "" H 7900 14100 60 0000 C CNN +F 3 "" H 7900 14100 60 0000 C CNN + 1 7900 14100 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X21 +U 1 1 6862BF00 +P 7950 14750 +F 0 "X21" H 8000 14650 60 0000 C CNN +F 1 "5_and" H 8050 14900 60 0000 C CNN +F 2 "" H 7950 14750 60 0000 C CNN +F 3 "" H 7950 14750 60 0000 C CNN + 1 7950 14750 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X17 +U 1 1 6862BF07 +P 7900 15500 +F 0 "X17" H 7950 15450 60 0000 C CNN +F 1 "4_and" H 8000 15600 60 0000 C CNN +F 2 "" H 7900 15500 60 0000 C CNN +F 3 "" H 7900 15500 60 0000 C CNN + 1 7900 15500 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X22 +U 1 1 6862BF0E +P 7950 16200 +F 0 "X22" H 8000 16100 60 0000 C CNN +F 1 "5_and" H 8050 16350 60 0000 C CNN +F 2 "" H 7950 16200 60 0000 C CNN +F 3 "" H 7950 16200 60 0000 C CNN + 1 7950 16200 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X18 +U 1 1 6862BF15 +P 7900 16950 +F 0 "X18" H 7950 16900 60 0000 C CNN +F 1 "4_and" H 8000 17050 60 0000 C CNN +F 2 "" H 7900 16950 60 0000 C CNN +F 3 "" H 7900 16950 60 0000 C CNN + 1 7900 16950 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X19 +U 1 1 6862BF1C +P 7900 17600 +F 0 "X19" H 7950 17550 60 0000 C CNN +F 1 "4_and" H 8000 17700 60 0000 C CNN +F 2 "" H 7900 17600 60 0000 C CNN +F 3 "" H 7900 17600 60 0000 C CNN + 1 7900 17600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X20 +U 1 1 6862BF23 +P 7900 18200 +F 0 "X20" H 7950 18150 60 0000 C CNN +F 1 "4_and" H 8000 18300 60 0000 C CNN +F 2 "" H 7900 18200 60 0000 C CNN +F 3 "" H 7900 18200 60 0000 C CNN + 1 7900 18200 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X35 +U 1 1 6862BF2A +P 10200 15000 +F 0 "X35" H 10350 14900 60 0000 C CNN +F 1 "4_OR" H 10350 15100 60 0000 C CNN +F 2 "" H 10200 15000 60 0000 C CNN +F 3 "" H 10200 15000 60 0000 C CNN + 1 10200 15000 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X34 +U 1 1 6862BF31 +P 10150 17100 +F 0 "X34" H 10300 17000 60 0000 C CNN +F 1 "4_OR" H 10300 17200 60 0000 C CNN +F 2 "" H 10150 17100 60 0000 C CNN +F 3 "" H 10150 17100 60 0000 C CNN + 1 10150 17100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 6862BF38 +P 11050 15000 +F 0 "U29" H 11050 14900 60 0000 C CNN +F 1 "d_inverter" H 11050 15150 60 0000 C CNN +F 2 "" H 11100 14950 60 0000 C CNN +F 3 "" H 11100 14950 60 0000 C CNN + 1 11050 15000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U28 +U 1 1 6862BF3F +P 11000 17100 +F 0 "U28" H 11000 17000 60 0000 C CNN +F 1 "d_inverter" H 11000 17250 60 0000 C CNN +F 2 "" H 11050 17050 60 0000 C CNN +F 3 "" H 11050 17050 60 0000 C CNN + 1 11000 17100 + 1 0 0 -1 +$EndComp +NoConn ~ 9850 15150 +$Comp +L 4_and X23 +U 1 1 6862BF47 +P 7950 18750 +F 0 "X23" H 8000 18700 60 0000 C CNN +F 1 "4_and" H 8050 18850 60 0000 C CNN +F 2 "" H 7950 18750 60 0000 C CNN +F 3 "" H 7950 18750 60 0000 C CNN + 1 7950 18750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X28 +U 1 1 6862BF4E +P 8000 19400 +F 0 "X28" H 8050 19300 60 0000 C CNN +F 1 "5_and" H 8100 19550 60 0000 C CNN +F 2 "" H 8000 19400 60 0000 C CNN +F 3 "" H 8000 19400 60 0000 C CNN + 1 8000 19400 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X24 +U 1 1 6862BF55 +P 7950 20150 +F 0 "X24" H 8000 20100 60 0000 C CNN +F 1 "4_and" H 8050 20250 60 0000 C CNN +F 2 "" H 7950 20150 60 0000 C CNN +F 3 "" H 7950 20150 60 0000 C CNN + 1 7950 20150 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X29 +U 1 1 6862BF5C +P 8000 20850 +F 0 "X29" H 8050 20750 60 0000 C CNN +F 1 "5_and" H 8100 21000 60 0000 C CNN +F 2 "" H 8000 20850 60 0000 C CNN +F 3 "" H 8000 20850 60 0000 C CNN + 1 8000 20850 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X25 +U 1 1 6862BF63 +P 7950 21600 +F 0 "X25" H 8000 21550 60 0000 C CNN +F 1 "4_and" H 8050 21700 60 0000 C CNN +F 2 "" H 7950 21600 60 0000 C CNN +F 3 "" H 7950 21600 60 0000 C CNN + 1 7950 21600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X26 +U 1 1 6862BF6A +P 7950 22250 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"" H 3700 17400 60 0000 C CNN +F 3 "" H 3700 17400 60 0000 C CNN + 19 3700 17400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 686246A4 +P 4000 18950 +F 0 "U1" H 4050 19050 30 0000 C CNN +F 1 "PORT" H 4000 18950 30 0000 C CNN +F 2 "" H 4000 18950 60 0000 C CNN +F 3 "" H 4000 18950 60 0000 C CNN + 16 4000 18950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 686296E1 +P 18500 17200 +F 0 "U1" H 18550 17300 30 0000 C CNN +F 1 "PORT" H 18500 17200 30 0000 C CNN +F 2 "" H 18500 17200 60 0000 C CNN +F 3 "" H 18500 17200 60 0000 C CNN + 11 18500 17200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6862A8FF +P 20150 21850 +F 0 "U1" H 20200 21950 30 0000 C CNN +F 1 "PORT" H 20150 21850 30 0000 C CNN +F 2 "" H 20150 21850 60 0000 C CNN +F 3 "" H 20150 21850 60 0000 C CNN + 12 20150 21850 + -1 0 0 1 +$EndComp +Wire Wire Line + 3950 17400 6050 17400 +Wire Wire Line + 4300 17400 4300 16850 +Connection ~ 6050 17400 +Connection ~ 4300 17400 +$Comp +L PORT U1 +U 17 1 6863092E +P 3950 23000 +F 0 "U1" H 4000 23100 30 0000 C CNN +F 1 "PORT" H 3950 23000 30 0000 C CNN +F 2 "" H 3950 23000 60 0000 C CNN +F 3 "" H 3950 23000 60 0000 C CNN + 17 3950 23000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6863361E +P 3050 24100 +F 0 "U1" H 3100 24200 30 0000 C CNN +F 1 "PORT" H 3050 24100 30 0000 C CNN +F 2 "" H 3050 24100 60 0000 C CNN +F 3 "" H 3050 24100 60 0000 C CNN + 5 3050 24100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6863375D +P 3100 25300 +F 0 "U1" H 3150 25400 30 0000 C CNN +F 1 "PORT" H 3100 25300 30 0000 C CNN +F 2 "" H 3100 25300 60 0000 C CNN +F 3 "" H 3100 25300 60 0000 C CNN + 6 3100 25300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68633870 +P 3100 26700 +F 0 "U1" H 3150 26800 30 0000 C CNN +F 1 "PORT" H 3100 26700 30 0000 C CNN +F 2 "" H 3100 26700 60 0000 C CNN +F 3 "" H 3100 26700 60 0000 C CNN + 7 3100 26700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68633995 +P 3150 28050 +F 0 "U1" H 3200 28150 30 0000 C CNN +F 1 "PORT" H 3150 28050 30 0000 C CNN +F 2 "" H 3150 28050 60 0000 C CNN +F 3 "" H 3150 28050 60 0000 C CNN + 10 3150 28050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 20 1 68633AE6 +P 3100 28400 +F 0 "U1" H 3150 28500 30 0000 C CNN +F 1 "PORT" H 3100 28400 30 0000 C CNN +F 2 "" H 3100 28400 60 0000 C CNN +F 3 "" H 3100 28400 60 0000 C CNN + 20 3100 28400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 68633C87 +P 20350 25750 +F 0 "U1" H 20400 25850 30 0000 C CNN +F 1 "PORT" H 20350 25750 30 0000 C CNN +F 2 "" H 20350 25750 60 0000 C CNN +F 3 "" H 20350 25750 60 0000 C CNN + 13 20350 25750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 68633DB2 +P 18050 27900 +F 0 "U1" H 18100 28000 30 0000 C CNN +F 1 "PORT" H 18050 27900 30 0000 C CNN +F 2 "" H 18050 27900 60 0000 C CNN +F 3 "" H 18050 27900 60 0000 C CNN + 14 18050 27900 + -1 0 0 1 +$EndComp +NoConn ~ 16200 24000 +NoConn ~ 3400 28050 +NoConn ~ 3350 28400 +NoConn ~ 14750 16400 +Wire Wire Line + 10050 26100 8350 26100 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74F382/SC_74F382.sub b/library/SubcircuitLibrary/74F382/SC_74F382.sub new file mode 100644 index 000000000..52e913444 --- /dev/null +++ b/library/SubcircuitLibrary/74F382/SC_74F382.sub @@ -0,0 +1,248 @@ +* Subcircuit SC_74F382 +.subckt SC_74F382 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_74f382\sc_74f382.cir +.include 4_and.sub +.include 4_OR.sub +.include 5_and.sub +.include 3_and.sub +x1 net-_u9-pad2_ net-_u5-pad2_ net-_u19-pad3_ net-_u17-pad3_ net-_x1-pad5_ 4_and +x7 net-_u16-pad3_ net-_u19-pad3_ net-_u21-pad2_ net-_u5-pad2_ net-_u1-pad3_ net-_x31-pad2_ 5_and +x2 net-_u17-pad3_ net-_u21-pad2_ net-_u1-pad4_ net-_u9-pad2_ net-_x2-pad5_ 4_and +x8 net-_u9-pad2_ net-_u5-pad2_ net-_u16-pad3_ net-_u21-pad2_ net-_u23-pad3_ net-_x30-pad1_ 5_and +x3 net-_u17-pad3_ net-_u19-pad3_ net-_u5-pad2_ net-_u1-pad3_ net-_x3-pad5_ 4_and +x4 net-_u17-pad3_ net-_u19-pad3_ net-_u1-pad4_ net-_u9-pad2_ net-_x30-pad3_ 4_and +x5 net-_u16-pad3_ net-_u21-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_x30-pad4_ 4_and +x31 net-_x1-pad5_ net-_x31-pad2_ net-_x2-pad5_ ? net-_u25-pad1_ 4_OR +x30 net-_x30-pad1_ net-_x3-pad5_ net-_x30-pad3_ net-_x30-pad4_ net-_u24-pad1_ 4_OR +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u24-pad2_ d_inverter +x9 net-_u11-pad2_ net-_u7-pad2_ net-_u19-pad3_ net-_u17-pad3_ net-_x33-pad1_ 4_and +x14 net-_u16-pad3_ net-_u19-pad3_ net-_u21-pad2_ net-_u7-pad2_ net-_u1-pad1_ net-_x14-pad6_ 5_and +x10 net-_u17-pad3_ net-_u21-pad2_ net-_u1-pad2_ net-_u11-pad2_ net-_x10-pad5_ 4_and +x15 net-_u11-pad2_ net-_u7-pad2_ net-_u16-pad3_ net-_u21-pad2_ net-_u23-pad3_ net-_x15-pad6_ 5_and +x11 net-_u17-pad3_ net-_u19-pad3_ net-_u7-pad2_ net-_u1-pad1_ net-_x11-pad5_ 4_and +x12 net-_u17-pad3_ net-_u19-pad3_ net-_u1-pad2_ net-_u11-pad2_ net-_x12-pad5_ 4_and +x13 net-_u16-pad3_ net-_u21-pad2_ net-_u1-pad2_ net-_u1-pad1_ net-_x13-pad5_ 4_and +x33 net-_x33-pad1_ net-_x14-pad6_ net-_x10-pad5_ ? net-_u27-pad1_ 4_OR +x32 net-_x15-pad6_ net-_x11-pad5_ net-_x12-pad5_ net-_x13-pad5_ net-_u26-pad1_ 4_OR +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u18 net-_u16-pad1_ net-_u10-pad1_ net-_u18-pad3_ d_and +* u22 net-_u16-pad1_ net-_u15-pad2_ net-_u22-pad3_ d_and +* u20 net-_u10-pad1_ net-_u15-pad2_ net-_u20-pad3_ d_and +* u19 net-_u16-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_nand +* u16 net-_u16-pad1_ net-_u10-pad1_ net-_u16-pad3_ d_nand +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u33 net-_u1-pad15_ net-_u32-pad3_ net-_u33-pad3_ d_nand +* u40 net-_u33-pad3_ net-_u24-pad2_ net-_u1-pad8_ d_xor +* u9 net-_u1-pad3_ net-_u9-pad2_ d_inverter +* u7 net-_u1-pad2_ net-_u7-pad2_ d_inverter +* u11 net-_u1-pad1_ net-_u11-pad2_ d_inverter +x41 net-_u1-pad15_ net-_u25-pad2_ net-_u32-pad3_ net-_u35-pad1_ 3_and +x42 net-_u25-pad2_ net-_u24-pad2_ net-_u32-pad3_ net-_u35-pad2_ 3_and +* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u35-pad3_ d_nor +* u39 net-_u35-pad3_ net-_u26-pad2_ net-_u1-pad9_ d_xor +x39 net-_u1-pad15_ net-_u25-pad2_ net-_u27-pad2_ net-_u32-pad3_ net-_x39-pad5_ 4_and +x40 net-_u25-pad2_ net-_u27-pad2_ net-_u24-pad2_ net-_u32-pad3_ net-_x40-pad5_ 4_and +x38 net-_u27-pad2_ net-_u26-pad2_ net-_u32-pad3_ net-_x38-pad4_ 3_and +x52 net-_x39-pad5_ net-_x40-pad5_ net-_x38-pad4_ ? net-_u38-pad1_ 4_OR +* u38 net-_u38-pad1_ net-_u38-pad2_ d_inverter +* u45 net-_u38-pad2_ net-_u28-pad2_ net-_u1-pad11_ d_xor +x16 net-_u13-pad2_ net-_u6-pad2_ net-_u19-pad3_ net-_u17-pad3_ net-_x16-pad5_ 4_and +x21 net-_u16-pad3_ net-_u19-pad3_ net-_u21-pad2_ net-_u6-pad2_ net-_u1-pad19_ net-_x21-pad6_ 5_and +x17 net-_u17-pad3_ net-_u21-pad2_ net-_u1-pad18_ net-_u13-pad2_ net-_x17-pad5_ 4_and +x22 net-_u13-pad2_ net-_u6-pad2_ net-_u16-pad3_ net-_u21-pad2_ net-_u23-pad3_ net-_x22-pad6_ 5_and +x18 net-_u17-pad3_ net-_u19-pad3_ net-_u6-pad2_ net-_u1-pad19_ net-_x18-pad5_ 4_and +x19 net-_u17-pad3_ net-_u19-pad3_ net-_u1-pad18_ net-_u13-pad2_ net-_x19-pad5_ 4_and +x20 net-_u16-pad3_ net-_u21-pad2_ net-_u1-pad18_ net-_u1-pad19_ net-_x20-pad5_ 4_and +x35 net-_x16-pad5_ net-_x21-pad6_ net-_x17-pad5_ ? net-_u29-pad1_ 4_OR +x34 net-_x22-pad6_ net-_x18-pad5_ net-_x19-pad5_ net-_x20-pad5_ net-_u28-pad1_ 4_OR +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter +x23 net-_u14-pad2_ net-_u12-pad2_ net-_u19-pad3_ net-_u17-pad3_ net-_x23-pad5_ 4_and +x28 net-_u16-pad3_ net-_u19-pad3_ net-_u21-pad2_ net-_u12-pad2_ net-_u1-pad17_ net-_x28-pad6_ 5_and +x24 net-_u17-pad3_ net-_u21-pad2_ net-_u1-pad16_ net-_u14-pad2_ net-_x24-pad5_ 4_and +x29 net-_u14-pad2_ net-_u12-pad2_ net-_u16-pad3_ net-_u21-pad2_ net-_u23-pad3_ net-_x29-pad6_ 5_and +x25 net-_u17-pad3_ net-_u19-pad3_ net-_u12-pad2_ net-_u1-pad17_ net-_x25-pad5_ 4_and +x26 net-_u17-pad3_ net-_u19-pad3_ net-_u1-pad16_ net-_u14-pad2_ net-_x26-pad5_ 4_and +x27 net-_u16-pad3_ net-_u21-pad2_ net-_u1-pad16_ net-_u1-pad17_ net-_x27-pad5_ 4_and +x37 net-_x23-pad5_ net-_x28-pad6_ net-_x24-pad5_ ? net-_u31-pad1_ 4_OR +x36 net-_x29-pad6_ net-_x25-pad5_ net-_x26-pad5_ net-_x27-pad5_ net-_u30-pad1_ 4_OR +* u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u6 net-_u1-pad18_ net-_u6-pad2_ d_inverter +* u13 net-_u1-pad19_ net-_u13-pad2_ d_inverter +* u12 net-_u1-pad16_ net-_u12-pad2_ d_inverter +* u14 net-_u1-pad17_ net-_u14-pad2_ d_inverter +* u2 net-_u1-pad5_ net-_u16-pad1_ d_inverter +* u8 net-_u16-pad1_ net-_u8-pad2_ d_inverter +* u3 net-_u1-pad6_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad7_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u32 net-_u18-pad3_ net-_u15-pad2_ net-_u32-pad3_ d_xor +* u17 net-_u10-pad1_ net-_u15-pad1_ net-_u17-pad3_ d_nand +x6 net-_u8-pad2_ net-_u10-pad2_ net-_u15-pad1_ net-_u21-pad1_ 3_and +* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter +* u23 net-_u22-pad3_ net-_u20-pad3_ net-_u23-pad3_ d_nor +x47 net-_u1-pad15_ net-_u25-pad2_ net-_u27-pad2_ net-_u29-pad2_ net-_u32-pad3_ net-_x47-pad6_ 5_and +x48 net-_u25-pad2_ net-_u27-pad2_ net-_u29-pad2_ net-_u24-pad2_ net-_u32-pad3_ net-_x48-pad6_ 5_and +x44 net-_u27-pad2_ net-_u29-pad2_ net-_u26-pad2_ net-_u32-pad3_ net-_x44-pad5_ 4_and +x43 net-_u29-pad2_ net-_u28-pad2_ net-_u32-pad3_ net-_x43-pad4_ 3_and +x54 net-_x47-pad6_ net-_x48-pad6_ net-_x44-pad5_ net-_x43-pad4_ net-_u43-pad1_ 4_OR +* u43 net-_u43-pad1_ net-_u43-pad2_ d_inverter +* u46 net-_u43-pad2_ net-_u30-pad2_ net-_u1-pad12_ d_xor +* u47 net-_u43-pad2_ net-_u42-pad3_ net-_u1-pad13_ d_xor +x45 net-_u25-pad2_ net-_u27-pad2_ net-_u29-pad2_ net-_u31-pad2_ net-_u37-pad1_ 4_and +* u37 net-_u37-pad1_ ? d_inverter +x49 net-_u25-pad2_ net-_u27-pad2_ net-_u29-pad2_ net-_u31-pad2_ net-_u24-pad2_ net-_x49-pad6_ 5_and +x50 net-_u27-pad2_ net-_u29-pad2_ net-_u31-pad2_ net-_u26-pad2_ net-_x50-pad5_ 4_and +x46 net-_u29-pad2_ net-_u31-pad2_ net-_u28-pad2_ net-_x46-pad4_ 3_and +* u34 net-_u31-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_and +* u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter +* u44 net-_u41-pad2_ net-_u36-pad2_ net-_u1-pad14_ d_nand +* u42 net-_u41-pad2_ net-_u36-pad2_ net-_u42-pad3_ d_and +x53 net-_x49-pad6_ net-_x50-pad5_ net-_x46-pad4_ net-_u34-pad3_ net-_u41-pad1_ 4_OR +* u41 net-_u41-pad1_ net-_u41-pad2_ d_inverter +x51 net-_u1-pad15_ net-_u25-pad2_ net-_u27-pad2_ net-_u29-pad2_ net-_u31-pad2_ net-_u36-pad1_ 5_and +a1 net-_u25-pad1_ net-_u25-pad2_ u25 +a2 net-_u24-pad1_ net-_u24-pad2_ u24 +a3 net-_u27-pad1_ net-_u27-pad2_ u27 +a4 net-_u26-pad1_ net-_u26-pad2_ u26 +a5 [net-_u16-pad1_ net-_u10-pad1_ ] net-_u18-pad3_ u18 +a6 [net-_u16-pad1_ net-_u15-pad2_ ] net-_u22-pad3_ u22 +a7 [net-_u10-pad1_ net-_u15-pad2_ ] net-_u20-pad3_ u20 +a8 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19 +a9 [net-_u16-pad1_ net-_u10-pad1_ ] net-_u16-pad3_ u16 +a10 net-_u1-pad4_ net-_u5-pad2_ u5 +a11 [net-_u1-pad15_ net-_u32-pad3_ ] net-_u33-pad3_ u33 +a12 [net-_u33-pad3_ net-_u24-pad2_ ] net-_u1-pad8_ u40 +a13 net-_u1-pad3_ net-_u9-pad2_ u9 +a14 net-_u1-pad2_ net-_u7-pad2_ u7 +a15 net-_u1-pad1_ net-_u11-pad2_ u11 +a16 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u35-pad3_ u35 +a17 [net-_u35-pad3_ net-_u26-pad2_ ] net-_u1-pad9_ u39 +a18 net-_u38-pad1_ net-_u38-pad2_ u38 +a19 [net-_u38-pad2_ net-_u28-pad2_ ] net-_u1-pad11_ u45 +a20 net-_u29-pad1_ net-_u29-pad2_ u29 +a21 net-_u28-pad1_ net-_u28-pad2_ u28 +a22 net-_u31-pad1_ net-_u31-pad2_ u31 +a23 net-_u30-pad1_ net-_u30-pad2_ u30 +a24 net-_u1-pad18_ net-_u6-pad2_ u6 +a25 net-_u1-pad19_ net-_u13-pad2_ u13 +a26 net-_u1-pad16_ net-_u12-pad2_ u12 +a27 net-_u1-pad17_ net-_u14-pad2_ u14 +a28 net-_u1-pad5_ net-_u16-pad1_ u2 +a29 net-_u16-pad1_ net-_u8-pad2_ u8 +a30 net-_u1-pad6_ net-_u10-pad1_ u3 +a31 net-_u10-pad1_ net-_u10-pad2_ u10 +a32 net-_u1-pad7_ net-_u15-pad1_ u4 +a33 net-_u15-pad1_ net-_u15-pad2_ u15 +a34 [net-_u18-pad3_ net-_u15-pad2_ ] net-_u32-pad3_ u32 +a35 [net-_u10-pad1_ net-_u15-pad1_ ] net-_u17-pad3_ u17 +a36 net-_u21-pad1_ net-_u21-pad2_ u21 +a37 [net-_u22-pad3_ net-_u20-pad3_ ] net-_u23-pad3_ u23 +a38 net-_u43-pad1_ net-_u43-pad2_ u43 +a39 [net-_u43-pad2_ net-_u30-pad2_ ] net-_u1-pad12_ u46 +a40 [net-_u43-pad2_ net-_u42-pad3_ ] net-_u1-pad13_ u47 +a41 net-_u37-pad1_ ? u37 +a42 [net-_u31-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34 +a43 net-_u36-pad1_ net-_u36-pad2_ u36 +a44 [net-_u41-pad2_ net-_u36-pad2_ ] net-_u1-pad14_ u44 +a45 [net-_u41-pad2_ net-_u36-pad2_ ] net-_u42-pad3_ u42 +a46 net-_u41-pad1_ net-_u41-pad2_ u41 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u40 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u39 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u45 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u32 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u46 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u47 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u44 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_74F382 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74F382/SC_74F382_Previous_Values.xml b/library/SubcircuitLibrary/74F382/SC_74F382_Previous_Values.xml new file mode 100644 index 000000000..9be449c49 --- /dev/null +++ b/library/SubcircuitLibrary/74F382/SC_74F382_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsmsd_inverterd_inverterd_inverterd_inverterd_andd_andd_andd_nandd_nandd_inverterd_nandd_xord_inverterd_inverterd_inverterd_nord_xord_inverterd_xord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_xord_nandd_inverterd_nord_inverterd_xord_xord_inverterd_andd_inverterd_nandd_andd_inverterC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE2\eSim\library\SubcircuitLibrary\5_and \ No newline at end of file From d8f5077c258e3a84aa724c6946c7a5bcf1c16c3b Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:18:45 +0530 Subject: [PATCH 27/33] Dual J-K Negative Edge-Triggered Flip-Flop --- library/SubcircuitLibrary/74LXC112/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/74LXC112/analysis diff --git a/library/SubcircuitLibrary/74LXC112/analysis b/library/SubcircuitLibrary/74LXC112/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/74LXC112/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 45fa95f7f1a108aebc368853a17b5fcade8583f7 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sat, 5 Jul 2025 17:20:02 +0530 Subject: [PATCH 28/33] Dual J-K Negative Edge-Triggered Flip-Flop --- .../74LXC112/SC_74LCX112-cache.lib | 114 +++ .../74LXC112/SC_74LCX112.cir | 31 + .../74LXC112/SC_74LCX112.cir.out | 58 ++ .../74LXC112/SC_74LCX112.pro | 73 ++ .../74LXC112/SC_74LCX112.sch | 683 ++++++++++++++++++ .../74LXC112/SC_74LCX112.sub | 52 ++ .../74LXC112/SC_74LCX112_Previous_Values.xml | 1 + 7 files changed, 1012 insertions(+) create mode 100644 library/SubcircuitLibrary/74LXC112/SC_74LCX112-cache.lib create mode 100644 library/SubcircuitLibrary/74LXC112/SC_74LCX112.cir create mode 100644 library/SubcircuitLibrary/74LXC112/SC_74LCX112.cir.out create mode 100644 library/SubcircuitLibrary/74LXC112/SC_74LCX112.pro create mode 100644 library/SubcircuitLibrary/74LXC112/SC_74LCX112.sch create mode 100644 library/SubcircuitLibrary/74LXC112/SC_74LCX112.sub create mode 100644 library/SubcircuitLibrary/74LXC112/SC_74LCX112_Previous_Values.xml diff --git a/library/SubcircuitLibrary/74LXC112/SC_74LCX112-cache.lib b/library/SubcircuitLibrary/74LXC112/SC_74LCX112-cache.lib new file mode 100644 index 000000000..0d16aefcc --- /dev/null +++ b/library/SubcircuitLibrary/74LXC112/SC_74LCX112-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74LXC112/SC_74LCX112.cir b/library/SubcircuitLibrary/74LXC112/SC_74LCX112.cir new file mode 100644 index 000000000..76b1fd87f --- /dev/null +++ b/library/SubcircuitLibrary/74LXC112/SC_74LCX112.cir @@ -0,0 +1,31 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_74LCX112\SC_74LCX112.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/03/25 19:07:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X7 Net-_U1-Pad5_ Net-_U1-Pad15_ Net-_U6-Pad2_ Net-_U8-Pad1_ 3_and +X8 Net-_U1-Pad5_ Net-_U1-Pad15_ Net-_U1-Pad1_ Net-_U8-Pad2_ 3_and +X3 Net-_U4-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_U2-Pad2_ 3_and +X4 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_U2-Pad1_ 3_and +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U1-Pad6_ d_nor +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad5_ d_nor +X1 Net-_U1-Pad6_ Net-_U1-Pad15_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U4-Pad1_ 4_and +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ d_inverter +X9 Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U6-Pad1_ 4_and +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +X10 Net-_U1-Pad9_ Net-_U1-Pad14_ Net-_U7-Pad2_ Net-_U9-Pad1_ 3_and +X11 Net-_U1-Pad9_ Net-_U1-Pad14_ Net-_U1-Pad13_ Net-_U9-Pad2_ 3_and +X5 Net-_U5-Pad2_ Net-_U1-Pad10_ Net-_U1-Pad7_ Net-_U3-Pad2_ 3_and +X6 Net-_U1-Pad13_ Net-_U1-Pad10_ Net-_U1-Pad7_ Net-_U3-Pad1_ 3_and +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U1-Pad7_ d_nor +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U1-Pad9_ d_nor +X2 Net-_U1-Pad7_ Net-_U1-Pad14_ Net-_U1-Pad11_ Net-_U1-Pad13_ Net-_U5-Pad1_ 4_and +U5 Net-_U5-Pad1_ Net-_U5-Pad2_ d_inverter +X12 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U7-Pad1_ 4_and +U7 Net-_U7-Pad1_ Net-_U7-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/74LXC112/SC_74LCX112.cir.out b/library/SubcircuitLibrary/74LXC112/SC_74LCX112.cir.out new file mode 100644 index 000000000..38f9ae9c7 --- /dev/null +++ b/library/SubcircuitLibrary/74LXC112/SC_74LCX112.cir.out @@ -0,0 +1,58 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_74lcx112\sc_74lcx112.cir + +.include 4_and.sub +.include 3_and.sub +x7 net-_u1-pad5_ net-_u1-pad15_ net-_u6-pad2_ net-_u8-pad1_ 3_and +x8 net-_u1-pad5_ net-_u1-pad15_ net-_u1-pad1_ net-_u8-pad2_ 3_and +x3 net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u2-pad2_ 3_and +x4 net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad6_ net-_u2-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u1-pad6_ d_nor +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad5_ d_nor +x1 net-_u1-pad6_ net-_u1-pad15_ net-_u1-pad3_ net-_u1-pad1_ net-_u4-pad1_ 4_and +* u4 net-_u4-pad1_ net-_u4-pad2_ d_inverter +x9 net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad2_ net-_u1-pad1_ net-_u6-pad1_ 4_and +* u6 net-_u6-pad1_ net-_u6-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +x10 net-_u1-pad9_ net-_u1-pad14_ net-_u7-pad2_ net-_u9-pad1_ 3_and +x11 net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad13_ net-_u9-pad2_ 3_and +x5 net-_u5-pad2_ net-_u1-pad10_ net-_u1-pad7_ net-_u3-pad2_ 3_and +x6 net-_u1-pad13_ net-_u1-pad10_ net-_u1-pad7_ net-_u3-pad1_ 3_and +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u1-pad7_ d_nor +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u1-pad9_ d_nor +x2 net-_u1-pad7_ net-_u1-pad14_ net-_u1-pad11_ net-_u1-pad13_ net-_u5-pad1_ 4_and +* u5 net-_u5-pad1_ net-_u5-pad2_ d_inverter +x12 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad12_ net-_u1-pad13_ net-_u7-pad1_ 4_and +* u7 net-_u7-pad1_ net-_u7-pad2_ d_inverter +a1 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u1-pad6_ u8 +a2 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad5_ u2 +a3 net-_u4-pad1_ net-_u4-pad2_ u4 +a4 net-_u6-pad1_ net-_u6-pad2_ u6 +a5 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u1-pad7_ u9 +a6 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u1-pad9_ u3 +a7 net-_u5-pad1_ net-_u5-pad2_ u5 +a8 net-_u7-pad1_ net-_u7-pad2_ u7 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74LXC112/SC_74LCX112.pro b/library/SubcircuitLibrary/74LXC112/SC_74LCX112.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74LXC112/SC_74LCX112.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74LXC112/SC_74LCX112.sch b/library/SubcircuitLibrary/74LXC112/SC_74LCX112.sch new file mode 100644 index 000000000..0201ebec4 --- /dev/null +++ b/library/SubcircuitLibrary/74LXC112/SC_74LCX112.sch @@ -0,0 +1,683 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_74LCX112-cache +EELAYER 25 0 +EELAYER END +$Descr A3 11693 16535 portrait +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X7 +U 1 1 68652B34 +P 6900 3500 +F 0 "X7" H 7000 3450 60 0000 C CNN +F 1 "3_and" H 7050 3650 60 0000 C CNN +F 2 "" H 6900 3500 60 0000 C CNN +F 3 "" H 6900 3500 60 0000 C CNN + 1 6900 3500 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X8 +U 1 1 68652B68 +P 6900 4500 +F 0 "X8" H 7000 4450 60 0000 C CNN +F 1 "3_and" H 7050 4650 60 0000 C CNN +F 2 "" H 6900 4500 60 0000 C CNN +F 3 "" H 6900 4500 60 0000 C CNN + 1 6900 4500 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 68652BB7 +P 3800 3450 +F 0 "X3" H 3900 3400 60 0000 C CNN +F 1 "3_and" H 3950 3600 60 0000 C CNN +F 2 "" H 3800 3450 60 0000 C CNN +F 3 "" H 3800 3450 60 0000 C CNN + 1 3800 3450 + -1 0 0 1 +$EndComp +$Comp +L 3_and X4 +U 1 1 68652BEA +P 3800 4400 +F 0 "X4" H 3900 4350 60 0000 C CNN +F 1 "3_and" H 3950 4550 60 0000 C CNN +F 2 "" H 3800 4400 60 0000 C CNN +F 3 "" H 3800 4400 60 0000 C CNN + 1 3800 4400 + -1 0 0 1 +$EndComp +$Comp +L d_nor U8 +U 1 1 68652C25 +P 8450 3950 +F 0 "U8" H 8450 3950 60 0000 C CNN +F 1 "d_nor" H 8500 4050 60 0000 C CNN +F 2 "" H 8450 3950 60 0000 C CNN +F 3 "" H 8450 3950 60 0000 C CNN + 1 8450 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U2 +U 1 1 68652C6C +P 2250 4000 +F 0 "U2" H 2250 4000 60 0000 C CNN +F 1 "d_nor" H 2300 4100 60 0000 C CNN +F 2 "" H 2250 4000 60 0000 C CNN +F 3 "" H 2250 4000 60 0000 C CNN + 1 2250 4000 + -1 0 0 1 +$EndComp +$Comp +L 4_and X1 +U 1 1 68652CB5 +P 3250 6600 +F 0 "X1" H 3300 6550 60 0000 C CNN +F 1 "4_and" H 3350 6700 60 0000 C CNN +F 2 "" H 3250 6600 60 0000 C CNN +F 3 "" H 3250 6600 60 0000 C CNN + 1 3250 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68652D04 +P 4050 6600 +F 0 "U4" H 4050 6500 60 0000 C CNN +F 1 "d_inverter" H 4050 6750 60 0000 C CNN +F 2 "" H 4100 6550 60 0000 C CNN +F 3 "" H 4100 6550 60 0000 C CNN + 1 4050 6600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X9 +U 1 1 68652E15 +P 7250 6550 +F 0 "X9" H 7300 6500 60 0000 C CNN +F 1 "4_and" H 7350 6650 60 0000 C CNN +F 2 "" H 7250 6550 60 0000 C CNN +F 3 "" H 7250 6550 60 0000 C CNN + 1 7250 6550 + -1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68652E1C +P 6450 6550 +F 0 "U6" H 6450 6450 60 0000 C CNN +F 1 "d_inverter" H 6450 6700 60 0000 C CNN +F 2 "" H 6500 6500 60 0000 C CNN +F 3 "" H 6500 6500 60 0000 C CNN + 1 6450 6550 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3300 3500 2700 3500 +Wire Wire Line + 2700 3500 2700 4000 +Wire Wire Line + 2700 4100 2700 4450 +Wire Wire Line + 2700 4450 3300 4450 +Wire Wire Line + 7400 3450 8000 3450 +Wire Wire Line + 8000 3450 8000 3850 +Wire Wire Line + 8000 3950 8000 4450 +Wire Wire Line + 8000 4450 7400 4450 +Wire Wire Line + 4150 3600 4450 3600 +Wire Wire Line + 4450 3600 4450 6600 +Wire Wire Line + 4450 6600 4350 6600 +Wire Wire Line + 6550 3550 5950 3550 +Wire Wire Line + 5950 3550 5950 6550 +Wire Wire Line + 5950 6550 6150 6550 +Wire Wire Line + 1800 2800 1800 5700 +Wire Wire Line + 1800 2800 6550 2800 +Wire Wire Line + 6550 2800 6550 3350 +Wire Wire Line + 4150 3400 5600 3400 +Wire Wire Line + 5600 3400 5600 2600 +Wire Wire Line + 5600 2600 9150 2600 +Wire Wire Line + 9150 2600 9150 5050 +Wire Wire Line + 8900 3900 9500 3900 +Wire Wire Line + 7650 6700 7800 6700 +Wire Wire Line + 7800 6700 7800 7200 +Wire Wire Line + 7800 7200 2150 7200 +Wire Wire Line + 2450 7200 2450 5350 +Wire Wire Line + 2450 6750 2850 6750 +Wire Wire Line + 4150 3500 4700 3500 +Wire Wire Line + 4700 3500 4700 5200 +Wire Wire Line + 4700 4450 4150 4450 +Wire Wire Line + 4700 5200 7900 5200 +Wire Wire Line + 7900 5200 7900 6500 +Wire Wire Line + 7650 6500 8550 6500 +Connection ~ 4700 4450 +Wire Wire Line + 2100 6550 2850 6550 +Wire Wire Line + 2200 6550 2200 4900 +Wire Wire Line + 2200 4900 6250 4900 +Wire Wire Line + 6250 4900 6250 3450 +Wire Wire Line + 6250 4450 6550 4450 +Wire Wire Line + 6250 3450 6550 3450 +Connection ~ 6250 4450 +Wire Wire Line + 6550 4350 6100 4350 +Wire Wire Line + 6100 4350 6100 2800 +Connection ~ 6100 2800 +Wire Wire Line + 4150 4350 4600 4350 +Wire Wire Line + 4600 4350 4600 3400 +Connection ~ 4600 3400 +Wire Wire Line + 2450 5350 4150 5350 +Wire Wire Line + 4150 5350 4150 4550 +Connection ~ 2450 6750 +Wire Wire Line + 4150 4550 6550 4550 +Wire Wire Line + 7650 6400 7750 6400 +Wire Wire Line + 7750 6400 7750 5700 +Wire Wire Line + 7750 5700 1800 5700 +Connection ~ 1800 4050 +Wire Wire Line + 9150 5050 2850 5050 +Wire Wire Line + 2850 5050 2850 6450 +Connection ~ 9150 3900 +$Comp +L PORT U1 +U 1 1 68668216 +P 1900 7200 +F 0 "U1" H 1950 7300 30 0000 C CNN +F 1 "PORT" H 1900 7200 30 0000 C CNN +F 2 "" H 1900 7200 60 0000 C CNN +F 3 "" H 1900 7200 60 0000 C CNN + 1 1900 7200 + 1 0 0 -1 +$EndComp +Connection ~ 2450 7200 +$Comp +L PORT U1 +U 2 1 68668309 +P 7900 6600 +F 0 "U1" H 7950 6700 30 0000 C CNN +F 1 "PORT" H 7900 6600 30 0000 C CNN +F 2 "" H 7900 6600 60 0000 C CNN +F 3 "" H 7900 6600 60 0000 C CNN + 2 7900 6600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 68668374 +P 2600 6650 +F 0 "U1" H 2650 6750 30 0000 C CNN +F 1 "PORT" H 2600 6650 30 0000 C CNN +F 2 "" H 2600 6650 60 0000 C CNN +F 3 "" H 2600 6650 60 0000 C CNN + 3 2600 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 686683C3 +P 8800 6500 +F 0 "U1" H 8850 6600 30 0000 C CNN +F 1 "PORT" H 8800 6500 30 0000 C CNN +F 2 "" H 8800 6500 60 0000 C CNN +F 3 "" H 8800 6500 60 0000 C CNN + 4 8800 6500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 686684CC +P 1150 4050 +F 0 "U1" H 1200 4150 30 0000 C CNN +F 1 "PORT" H 1150 4050 30 0000 C CNN +F 2 "" H 1150 4050 60 0000 C CNN +F 3 "" H 1150 4050 60 0000 C CNN + 5 1150 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68668533 +P 9750 3900 +F 0 "U1" H 9800 4000 30 0000 C CNN +F 1 "PORT" H 9750 3900 30 0000 C CNN +F 2 "" H 9750 3900 60 0000 C CNN +F 3 "" H 9750 3900 60 0000 C CNN + 6 9750 3900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 686685D6 +P 850 850 +F 0 "U1" H 900 950 30 0000 C CNN +F 1 "PORT" H 850 850 30 0000 C CNN +F 2 "" H 850 850 60 0000 C CNN +F 3 "" H 850 850 60 0000 C CNN + 8 850 850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 6866863B +P 850 1250 +F 0 "U1" H 900 1350 30 0000 C CNN +F 1 "PORT" H 850 1250 30 0000 C CNN +F 2 "" H 850 1250 60 0000 C CNN +F 3 "" H 850 1250 60 0000 C CNN + 16 850 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 68668686 +P 1850 6550 +F 0 "U1" H 1900 6650 30 0000 C CNN +F 1 "PORT" H 1850 6550 30 0000 C CNN +F 2 "" H 1850 6550 60 0000 C CNN +F 3 "" H 1850 6550 60 0000 C CNN + 15 1850 6550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 4050 1800 4050 +Connection ~ 7900 6500 +Connection ~ 2200 6550 +NoConn ~ 1100 850 +NoConn ~ 1100 1250 +$Comp +L 3_and X10 +U 1 1 68669009 +P 7250 9250 +F 0 "X10" H 7350 9200 60 0000 C CNN +F 1 "3_and" H 7400 9400 60 0000 C CNN +F 2 "" H 7250 9250 60 0000 C CNN +F 3 "" H 7250 9250 60 0000 C CNN + 1 7250 9250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X11 +U 1 1 68669010 +P 7250 10250 +F 0 "X11" H 7350 10200 60 0000 C CNN +F 1 "3_and" H 7400 10400 60 0000 C CNN +F 2 "" H 7250 10250 60 0000 C CNN +F 3 "" H 7250 10250 60 0000 C CNN + 1 7250 10250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 68669017 +P 4150 9200 +F 0 "X5" H 4250 9150 60 0000 C CNN +F 1 "3_and" H 4300 9350 60 0000 C CNN +F 2 "" H 4150 9200 60 0000 C CNN +F 3 "" H 4150 9200 60 0000 C CNN + 1 4150 9200 + -1 0 0 1 +$EndComp +$Comp +L 3_and X6 +U 1 1 6866901E +P 4150 10150 +F 0 "X6" H 4250 10100 60 0000 C CNN +F 1 "3_and" H 4300 10300 60 0000 C CNN +F 2 "" H 4150 10150 60 0000 C CNN +F 3 "" H 4150 10150 60 0000 C CNN + 1 4150 10150 + -1 0 0 1 +$EndComp +$Comp +L d_nor U9 +U 1 1 68669025 +P 8800 9700 +F 0 "U9" H 8800 9700 60 0000 C CNN +F 1 "d_nor" H 8850 9800 60 0000 C CNN +F 2 "" H 8800 9700 60 0000 C CNN +F 3 "" H 8800 9700 60 0000 C CNN + 1 8800 9700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U3 +U 1 1 6866902C +P 2600 9750 +F 0 "U3" H 2600 9750 60 0000 C CNN +F 1 "d_nor" H 2650 9850 60 0000 C CNN +F 2 "" H 2600 9750 60 0000 C CNN +F 3 "" H 2600 9750 60 0000 C CNN + 1 2600 9750 + -1 0 0 1 +$EndComp +$Comp +L 4_and X2 +U 1 1 68669033 +P 3600 12350 +F 0 "X2" H 3650 12300 60 0000 C CNN +F 1 "4_and" H 3700 12450 60 0000 C CNN +F 2 "" H 3600 12350 60 0000 C CNN +F 3 "" H 3600 12350 60 0000 C CNN + 1 3600 12350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6866903A +P 4400 12350 +F 0 "U5" H 4400 12250 60 0000 C CNN +F 1 "d_inverter" H 4400 12500 60 0000 C CNN +F 2 "" H 4450 12300 60 0000 C CNN +F 3 "" H 4450 12300 60 0000 C CNN + 1 4400 12350 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X12 +U 1 1 68669041 +P 7600 12300 +F 0 "X12" H 7650 12250 60 0000 C CNN +F 1 "4_and" H 7700 12400 60 0000 C CNN +F 2 "" H 7600 12300 60 0000 C CNN +F 3 "" H 7600 12300 60 0000 C CNN + 1 7600 12300 + -1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68669048 +P 6800 12300 +F 0 "U7" H 6800 12200 60 0000 C CNN +F 1 "d_inverter" H 6800 12450 60 0000 C CNN +F 2 "" H 6850 12250 60 0000 C CNN +F 3 "" H 6850 12250 60 0000 C CNN + 1 6800 12300 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3650 9250 3050 9250 +Wire Wire Line + 3050 9250 3050 9750 +Wire Wire Line + 3050 9850 3050 10200 +Wire Wire Line + 3050 10200 3650 10200 +Wire Wire Line + 7750 9200 8350 9200 +Wire Wire Line + 8350 9200 8350 9600 +Wire Wire Line + 8350 9700 8350 10200 +Wire Wire Line + 8350 10200 7750 10200 +Wire Wire Line + 4500 9350 4800 9350 +Wire Wire Line + 4800 9350 4800 12350 +Wire Wire Line + 4800 12350 4700 12350 +Wire Wire Line + 6900 9300 6300 9300 +Wire Wire Line + 6300 9300 6300 12300 +Wire Wire Line + 6300 12300 6500 12300 +Wire Wire Line + 2150 8550 2150 11450 +Wire Wire Line + 2150 8550 6900 8550 +Wire Wire Line + 6900 8550 6900 9100 +Wire Wire Line + 4500 9150 5950 9150 +Wire Wire Line + 5950 9150 5950 8350 +Wire Wire Line + 5950 8350 9500 8350 +Wire Wire Line + 9500 8350 9500 10800 +Wire Wire Line + 9250 9650 9850 9650 +Wire Wire Line + 8000 12450 8150 12450 +Wire Wire Line + 8150 12450 8150 12950 +Wire Wire Line + 8150 12950 2500 12950 +Wire Wire Line + 2800 12950 2800 11100 +Wire Wire Line + 2800 12500 3200 12500 +Wire Wire Line + 4500 9250 5050 9250 +Wire Wire Line + 5050 9250 5050 10950 +Wire Wire Line + 5050 10200 4500 10200 +Wire Wire Line + 5050 10950 8250 10950 +Wire Wire Line + 8250 10950 8250 12250 +Wire Wire Line + 8000 12250 8900 12250 +Connection ~ 5050 10200 +Wire Wire Line + 2450 12300 3200 12300 +Wire Wire Line + 2550 12300 2550 10650 +Wire Wire Line + 2550 10650 6600 10650 +Wire Wire Line + 6600 10650 6600 9200 +Wire Wire Line + 6600 10200 6900 10200 +Wire Wire Line + 6600 9200 6900 9200 +Connection ~ 6600 10200 +Wire Wire Line + 6900 10100 6450 10100 +Wire Wire Line + 6450 10100 6450 8550 +Connection ~ 6450 8550 +Wire Wire Line + 4500 10100 4950 10100 +Wire Wire Line + 4950 10100 4950 9150 +Connection ~ 4950 9150 +Wire Wire Line + 2800 11100 4500 11100 +Wire Wire Line + 4500 11100 4500 10300 +Connection ~ 2800 12500 +Wire Wire Line + 4500 10300 6900 10300 +Wire Wire Line + 8000 12150 8100 12150 +Wire Wire Line + 8100 12150 8100 11450 +Wire Wire Line + 8100 11450 2150 11450 +Connection ~ 2150 9800 +Wire Wire Line + 9500 10800 3200 10800 +Wire Wire Line + 3200 10800 3200 12200 +Connection ~ 9500 9650 +Connection ~ 2800 12950 +Wire Wire Line + 1750 9800 2150 9800 +Connection ~ 8250 12250 +Connection ~ 2550 12300 +$Comp +L PORT U1 +U 11 1 68669098 +P 2950 12400 +F 0 "U1" H 3000 12500 30 0000 C CNN +F 1 "PORT" H 2950 12400 30 0000 C CNN +F 2 "" H 2950 12400 60 0000 C CNN +F 3 "" H 2950 12400 60 0000 C CNN + 11 2950 12400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 686690A6 +P 1500 9800 +F 0 "U1" H 1550 9900 30 0000 C CNN +F 1 "PORT" H 1500 9800 30 0000 C CNN +F 2 "" H 1500 9800 60 0000 C CNN +F 3 "" H 1500 9800 60 0000 C CNN + 9 1500 9800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 686690B4 +P 2200 12300 +F 0 "U1" H 2250 12400 30 0000 C CNN +F 1 "PORT" H 2200 12300 30 0000 C CNN +F 2 "" H 2200 12300 60 0000 C CNN +F 3 "" H 2200 12300 60 0000 C CNN + 14 2200 12300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 68669091 +P 8250 12350 +F 0 "U1" H 8300 12450 30 0000 C CNN +F 1 "PORT" H 8250 12350 30 0000 C CNN +F 2 "" H 8250 12350 60 0000 C CNN +F 3 "" H 8250 12350 60 0000 C CNN + 12 8250 12350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6866909F +P 9150 12250 +F 0 "U1" H 9200 12350 30 0000 C CNN +F 1 "PORT" H 9150 12250 30 0000 C CNN +F 2 "" H 9150 12250 60 0000 C CNN +F 3 "" H 9150 12250 60 0000 C CNN + 10 9150 12250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 686690AD +P 10100 9650 +F 0 "U1" H 10150 9750 30 0000 C CNN +F 1 "PORT" H 10100 9650 30 0000 C CNN +F 2 "" H 10100 9650 60 0000 C CNN +F 3 "" H 10100 9650 60 0000 C CNN + 7 10100 9650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6866EE96 +P 2250 12950 +F 0 "U1" H 2300 13050 30 0000 C CNN +F 1 "PORT" H 2250 12950 30 0000 C CNN +F 2 "" H 2250 12950 60 0000 C CNN +F 3 "" H 2250 12950 60 0000 C CNN + 13 2250 12950 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74LXC112/SC_74LCX112.sub b/library/SubcircuitLibrary/74LXC112/SC_74LCX112.sub new file mode 100644 index 000000000..219d099d7 --- /dev/null +++ b/library/SubcircuitLibrary/74LXC112/SC_74LCX112.sub @@ -0,0 +1,52 @@ +* Subcircuit SC_74LCX112 +.subckt SC_74LCX112 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_74lcx112\sc_74lcx112.cir +.include 4_and.sub +.include 3_and.sub +x7 net-_u1-pad5_ net-_u1-pad15_ net-_u6-pad2_ net-_u8-pad1_ 3_and +x8 net-_u1-pad5_ net-_u1-pad15_ net-_u1-pad1_ net-_u8-pad2_ 3_and +x3 net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u2-pad2_ 3_and +x4 net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad6_ net-_u2-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u1-pad6_ d_nor +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad5_ d_nor +x1 net-_u1-pad6_ net-_u1-pad15_ net-_u1-pad3_ net-_u1-pad1_ net-_u4-pad1_ 4_and +* u4 net-_u4-pad1_ net-_u4-pad2_ d_inverter +x9 net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad2_ net-_u1-pad1_ net-_u6-pad1_ 4_and +* u6 net-_u6-pad1_ net-_u6-pad2_ d_inverter +x10 net-_u1-pad9_ net-_u1-pad14_ net-_u7-pad2_ net-_u9-pad1_ 3_and +x11 net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad13_ net-_u9-pad2_ 3_and +x5 net-_u5-pad2_ net-_u1-pad10_ net-_u1-pad7_ net-_u3-pad2_ 3_and +x6 net-_u1-pad13_ net-_u1-pad10_ net-_u1-pad7_ net-_u3-pad1_ 3_and +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u1-pad7_ d_nor +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u1-pad9_ d_nor +x2 net-_u1-pad7_ net-_u1-pad14_ net-_u1-pad11_ net-_u1-pad13_ net-_u5-pad1_ 4_and +* u5 net-_u5-pad1_ net-_u5-pad2_ d_inverter +x12 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad12_ net-_u1-pad13_ net-_u7-pad1_ 4_and +* u7 net-_u7-pad1_ net-_u7-pad2_ d_inverter +a1 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u1-pad6_ u8 +a2 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad5_ u2 +a3 net-_u4-pad1_ net-_u4-pad2_ u4 +a4 net-_u6-pad1_ net-_u6-pad2_ u6 +a5 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u1-pad7_ u9 +a6 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u1-pad9_ u3 +a7 net-_u5-pad1_ net-_u5-pad2_ u5 +a8 net-_u7-pad1_ net-_u7-pad2_ u7 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_74LCX112 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74LXC112/SC_74LCX112_Previous_Values.xml b/library/SubcircuitLibrary/74LXC112/SC_74LCX112_Previous_Values.xml new file mode 100644 index 000000000..a23595f24 --- /dev/null +++ b/library/SubcircuitLibrary/74LXC112/SC_74LCX112_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsmsd_nord_nord_inverterd_inverterd_nord_nord_inverterd_inverterC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_and \ No newline at end of file From 01febea0cd7a689602b88d9423b9136934073619 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sun, 6 Jul 2025 13:38:58 +0530 Subject: [PATCH 29/33] AND-OR-INVERT GATES --- library/SubcircuitLibrary/SN7451/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/SN7451/analysis diff --git a/library/SubcircuitLibrary/SN7451/analysis b/library/SubcircuitLibrary/SN7451/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/SN7451/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From ebace892fddfa688f32b1f4f3720eb60bde7fd13 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Sun, 6 Jul 2025 13:39:54 +0530 Subject: [PATCH 30/33] AND-OR-INVERT GATES --- .../SN7451/SC_SN7451-cache.lib | 80 +++++ .../SubcircuitLibrary/SN7451/SC_SN7451.cir | 17 + .../SN7451/SC_SN7451.cir.out | 36 +++ .../SubcircuitLibrary/SN7451/SC_SN7451.pro | 73 +++++ .../SubcircuitLibrary/SN7451/SC_SN7451.sch | 296 ++++++++++++++++++ .../SubcircuitLibrary/SN7451/SC_SN7451.sub | 30 ++ .../SN7451/SC_SN7451_Previous_Values.xml | 1 + 7 files changed, 533 insertions(+) create mode 100644 library/SubcircuitLibrary/SN7451/SC_SN7451-cache.lib create mode 100644 library/SubcircuitLibrary/SN7451/SC_SN7451.cir create mode 100644 library/SubcircuitLibrary/SN7451/SC_SN7451.cir.out create mode 100644 library/SubcircuitLibrary/SN7451/SC_SN7451.pro create mode 100644 library/SubcircuitLibrary/SN7451/SC_SN7451.sch create mode 100644 library/SubcircuitLibrary/SN7451/SC_SN7451.sub create mode 100644 library/SubcircuitLibrary/SN7451/SC_SN7451_Previous_Values.xml diff --git a/library/SubcircuitLibrary/SN7451/SC_SN7451-cache.lib b/library/SubcircuitLibrary/SN7451/SC_SN7451-cache.lib new file mode 100644 index 000000000..881d6e449 --- /dev/null +++ b/library/SubcircuitLibrary/SN7451/SC_SN7451-cache.lib @@ -0,0 +1,80 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7451/SC_SN7451.cir b/library/SubcircuitLibrary/SN7451/SC_SN7451.cir new file mode 100644 index 000000000..33fd17af1 --- /dev/null +++ b/library/SubcircuitLibrary/SN7451/SC_SN7451.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_SN7451\SC_SN7451.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/06/25 13:15:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad13_ Net-_U2-Pad3_ d_and +U3 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U3-Pad3_ d_and +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad8_ d_nor +U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and +U5 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U5-Pad3_ d_and +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad6_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ ? ? Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN7451/SC_SN7451.cir.out b/library/SubcircuitLibrary/SN7451/SC_SN7451.cir.out new file mode 100644 index 000000000..3683fba4c --- /dev/null +++ b/library/SubcircuitLibrary/SN7451/SC_SN7451.cir.out @@ -0,0 +1,36 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn7451\sc_sn7451.cir + +* u2 net-_u1-pad1_ net-_u1-pad13_ net-_u2-pad3_ d_and +* u3 net-_u1-pad9_ net-_u1-pad10_ net-_u3-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad8_ d_nor +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad6_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ ? ? net-_u1-pad13_ ? port +a1 [net-_u1-pad1_ net-_u1-pad13_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad8_ u6 +a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a5 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad6_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7451/SC_SN7451.pro b/library/SubcircuitLibrary/SN7451/SC_SN7451.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN7451/SC_SN7451.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7451/SC_SN7451.sch b/library/SubcircuitLibrary/SN7451/SC_SN7451.sch new file mode 100644 index 000000000..3bccad0b7 --- /dev/null +++ b/library/SubcircuitLibrary/SN7451/SC_SN7451.sch @@ -0,0 +1,296 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 686920C2 +P 4750 2150 +F 0 "U2" H 4750 2150 60 0000 C CNN +F 1 "d_and" H 4800 2250 60 0000 C CNN +F 2 "" H 4750 2150 60 0000 C CNN +F 3 "" H 4750 2150 60 0000 C CNN + 1 4750 2150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 686920F7 +P 4750 2750 +F 0 "U3" H 4750 2750 60 0000 C CNN +F 1 "d_and" H 4800 2850 60 0000 C CNN +F 2 "" H 4750 2750 60 0000 C CNN +F 3 "" H 4750 2750 60 0000 C CNN + 1 4750 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 68692138 +P 6050 2400 +F 0 "U6" H 6050 2400 60 0000 C CNN +F 1 "d_nor" H 6100 2500 60 0000 C CNN +F 2 "" H 6050 2400 60 0000 C CNN +F 3 "" H 6050 2400 60 0000 C CNN + 1 6050 2400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 2100 5600 2100 +Wire Wire Line + 5600 2100 5600 2300 +Wire Wire Line + 5600 2400 5600 2700 +Wire Wire Line + 5600 2700 5200 2700 +$Comp +L d_and U4 +U 1 1 6869221E +P 4750 3400 +F 0 "U4" H 4750 3400 60 0000 C CNN +F 1 "d_and" H 4800 3500 60 0000 C CNN +F 2 "" H 4750 3400 60 0000 C CNN +F 3 "" H 4750 3400 60 0000 C CNN + 1 4750 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 68692225 +P 4750 4000 +F 0 "U5" H 4750 4000 60 0000 C CNN +F 1 "d_and" H 4800 4100 60 0000 C CNN +F 2 "" H 4750 4000 60 0000 C CNN +F 3 "" H 4750 4000 60 0000 C CNN + 1 4750 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 6869222C +P 6050 3650 +F 0 "U7" H 6050 3650 60 0000 C CNN +F 1 "d_nor" H 6100 3750 60 0000 C CNN +F 2 "" H 6050 3650 60 0000 C CNN +F 3 "" H 6050 3650 60 0000 C CNN + 1 6050 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 3350 5600 3350 +Wire Wire Line + 5600 3350 5600 3550 +Wire Wire Line + 5600 3650 5600 3950 +Wire Wire Line + 5600 3950 5200 3950 +$Comp +L PORT U1 +U 1 1 68692266 +P 4050 2050 +F 0 "U1" H 4100 2150 30 0000 C CNN +F 1 "PORT" H 4050 2050 30 0000 C CNN +F 2 "" H 4050 2050 60 0000 C CNN +F 3 "" H 4050 2050 60 0000 C CNN + 1 4050 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 686922BC +P 4050 3300 +F 0 "U1" H 4100 3400 30 0000 C CNN +F 1 "PORT" H 4050 3300 30 0000 C CNN +F 2 "" H 4050 3300 60 0000 C CNN +F 3 "" H 4050 3300 60 0000 C CNN + 2 4050 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68692305 +P 4300 3650 +F 0 "U1" H 4350 3750 30 0000 C CNN +F 1 "PORT" H 4300 3650 30 0000 C CNN +F 2 "" H 4300 3650 60 0000 C CNN +F 3 "" H 4300 3650 60 0000 C CNN + 3 4300 3650 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 686923C9 +P 4050 3900 +F 0 "U1" H 4100 4000 30 0000 C CNN +F 1 "PORT" H 4050 3900 30 0000 C CNN +F 2 "" H 4050 3900 60 0000 C CNN +F 3 "" H 4050 3900 60 0000 C CNN + 4 4050 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68692422 +P 4300 4250 +F 0 "U1" H 4350 4350 30 0000 C CNN +F 1 "PORT" H 4300 4250 30 0000 C CNN +F 2 "" H 4300 4250 60 0000 C CNN +F 3 "" H 4300 4250 60 0000 C CNN + 5 4300 4250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 68692465 +P 6750 3600 +F 0 "U1" H 6800 3700 30 0000 C CNN +F 1 "PORT" H 6750 3600 30 0000 C CNN +F 2 "" H 6750 3600 60 0000 C CNN +F 3 "" H 6750 3600 60 0000 C CNN + 6 6750 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 686924C6 +P 4100 4950 +F 0 "U1" H 4150 5050 30 0000 C CNN +F 1 "PORT" H 4100 4950 30 0000 C CNN +F 2 "" H 4100 4950 60 0000 C CNN +F 3 "" H 4100 4950 60 0000 C CNN + 7 4100 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6869250D +P 6750 2350 +F 0 "U1" H 6800 2450 30 0000 C CNN +F 1 "PORT" H 6750 2350 30 0000 C CNN +F 2 "" H 6750 2350 60 0000 C CNN +F 3 "" H 6750 2350 60 0000 C CNN + 8 6750 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 686925D0 +P 4050 2650 +F 0 "U1" H 4100 2750 30 0000 C CNN +F 1 "PORT" H 4050 2650 30 0000 C CNN +F 2 "" H 4050 2650 60 0000 C CNN +F 3 "" H 4050 2650 60 0000 C CNN + 9 4050 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68692623 +P 4300 3000 +F 0 "U1" H 4350 3100 30 0000 C CNN +F 1 "PORT" H 4300 3000 30 0000 C CNN +F 2 "" H 4300 3000 60 0000 C CNN +F 3 "" H 4300 3000 60 0000 C CNN + 10 4300 3000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 68692696 +P 4100 5250 +F 0 "U1" H 4150 5350 30 0000 C CNN +F 1 "PORT" H 4100 5250 30 0000 C CNN +F 2 "" H 4100 5250 60 0000 C CNN +F 3 "" H 4100 5250 60 0000 C CNN + 11 4100 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 686926EF +P 4100 5500 +F 0 "U1" H 4150 5600 30 0000 C CNN +F 1 "PORT" H 4100 5500 30 0000 C CNN +F 2 "" H 4100 5500 60 0000 C CNN +F 3 "" H 4100 5500 60 0000 C CNN + 12 4100 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 68692744 +P 4300 2400 +F 0 "U1" H 4350 2500 30 0000 C CNN +F 1 "PORT" H 4300 2400 30 0000 C CNN +F 2 "" H 4300 2400 60 0000 C CNN +F 3 "" H 4300 2400 60 0000 C CNN + 13 4300 2400 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 686927B9 +P 4100 5800 +F 0 "U1" H 4150 5900 30 0000 C CNN +F 1 "PORT" H 4100 5800 30 0000 C CNN +F 2 "" H 4100 5800 60 0000 C CNN +F 3 "" H 4100 5800 60 0000 C CNN + 14 4100 5800 + 1 0 0 -1 +$EndComp +NoConn ~ 4350 4950 +NoConn ~ 4350 5250 +NoConn ~ 4350 5500 +NoConn ~ 4350 5800 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7451/SC_SN7451.sub b/library/SubcircuitLibrary/SN7451/SC_SN7451.sub new file mode 100644 index 000000000..69d0b2ea4 --- /dev/null +++ b/library/SubcircuitLibrary/SN7451/SC_SN7451.sub @@ -0,0 +1,30 @@ +* Subcircuit SC_SN7451 +.subckt SC_SN7451 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ ? ? net-_u1-pad13_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn7451\sc_sn7451.cir +* u2 net-_u1-pad1_ net-_u1-pad13_ net-_u2-pad3_ d_and +* u3 net-_u1-pad9_ net-_u1-pad10_ net-_u3-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad8_ d_nor +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad6_ d_nor +a1 [net-_u1-pad1_ net-_u1-pad13_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad8_ u6 +a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a5 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad6_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_SN7451 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7451/SC_SN7451_Previous_Values.xml b/library/SubcircuitLibrary/SN7451/SC_SN7451_Previous_Values.xml new file mode 100644 index 000000000..0f984700e --- /dev/null +++ b/library/SubcircuitLibrary/SN7451/SC_SN7451_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsmsd_andd_andd_nord_andd_andd_nor \ No newline at end of file From 474a67e20d611525975778aefea724c2fa2e0972 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:23:56 +0530 Subject: [PATCH 31/33] 4-BIT PARALLEL-ACCESS SHIFT REGISTERS --- library/SubcircuitLibrary/SN7495A/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/SN7495A/analysis diff --git a/library/SubcircuitLibrary/SN7495A/analysis b/library/SubcircuitLibrary/SN7495A/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From ea9ddeb7c63985d91cd36d4383e8375488c04367 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:26:43 +0530 Subject: [PATCH 32/33] 4-BIT PARALLEL-ACCESS SHIFT REGISTERS --- .../SN7495A/SC_SN7495A-cache.lib | 131 ++++ .../SubcircuitLibrary/SN7495A/SC_SN7495A.cir | 37 + .../SN7495A/SC_SN7495A.cir.out | 105 +++ .../SubcircuitLibrary/SN7495A/SC_SN7495A.pro | 73 ++ .../SubcircuitLibrary/SN7495A/SC_SN7495A.sch | 691 ++++++++++++++++++ .../SubcircuitLibrary/SN7495A/SC_SN7495A.sub | 99 +++ .../SN7495A/SC_SN7495A_Previous_Values.xml | 1 + .../SN7495A/srff_custom-cache.lib | 75 ++ .../SubcircuitLibrary/SN7495A/srff_custom.cir | 16 + .../SN7495A/srff_custom.cir.out | 32 + .../SubcircuitLibrary/SN7495A/srff_custom.pro | 73 ++ .../SubcircuitLibrary/SN7495A/srff_custom.sch | 198 +++++ .../SubcircuitLibrary/SN7495A/srff_custom.sub | 26 + .../SN7495A/srff_custom_Previous_Values.xml | 1 + 14 files changed, 1558 insertions(+) create mode 100644 library/SubcircuitLibrary/SN7495A/SC_SN7495A-cache.lib create mode 100644 library/SubcircuitLibrary/SN7495A/SC_SN7495A.cir create mode 100644 library/SubcircuitLibrary/SN7495A/SC_SN7495A.cir.out create mode 100644 library/SubcircuitLibrary/SN7495A/SC_SN7495A.pro create mode 100644 library/SubcircuitLibrary/SN7495A/SC_SN7495A.sch create mode 100644 library/SubcircuitLibrary/SN7495A/SC_SN7495A.sub create mode 100644 library/SubcircuitLibrary/SN7495A/SC_SN7495A_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SN7495A/srff_custom-cache.lib create mode 100644 library/SubcircuitLibrary/SN7495A/srff_custom.cir create mode 100644 library/SubcircuitLibrary/SN7495A/srff_custom.cir.out create mode 100644 library/SubcircuitLibrary/SN7495A/srff_custom.pro create mode 100644 library/SubcircuitLibrary/SN7495A/srff_custom.sch create mode 100644 library/SubcircuitLibrary/SN7495A/srff_custom.sub create mode 100644 library/SubcircuitLibrary/SN7495A/srff_custom_Previous_Values.xml diff --git a/library/SubcircuitLibrary/SN7495A/SC_SN7495A-cache.lib b/library/SubcircuitLibrary/SN7495A/SC_SN7495A-cache.lib new file mode 100644 index 000000000..45689bfb5 --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/SC_SN7495A-cache.lib @@ -0,0 +1,131 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# SRFF_CUSTOM +# +DEF SRFF_CUSTOM X 0 40 Y Y 1 F N +F0 "X" 400 550 60 H V C CNN +F1 "SRFF_CUSTOM" -100 550 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C -400 0 50 0 1 0 N +S -400 500 450 -500 0 1 0 N +X S 1 -600 350 200 R 50 50 1 1 I +X R 2 -600 -300 200 R 50 50 1 1 I +X CLK 3 -600 0 200 R 50 50 1 1 I +X Q 4 650 350 200 L 50 50 1 1 I +X Q_bar 5 650 -300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7495A/SC_SN7495A.cir b/library/SubcircuitLibrary/SN7495A/SC_SN7495A.cir new file mode 100644 index 000000000..84a3e7a97 --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/SC_SN7495A.cir @@ -0,0 +1,37 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_SN7495A\SC_SN7495A.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/29/25 17:30:29 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U12-Pad1_ Net-_U1-Pad1_ Net-_U8-Pad3_ d_and +U11 Net-_U1-Pad2_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U2 Net-_U12-Pad1_ Net-_U1-Pad9_ Net-_U2-Pad3_ d_and +U3 Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U3-Pad3_ d_and +U9 Net-_U11-Pad3_ Net-_U8-Pad3_ Net-_U10-Pad1_ d_nor +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U1-Pad13_ Net-_U12-Pad3_ d_and +U15 Net-_U1-Pad3_ Net-_U11-Pad2_ Net-_U13-Pad1_ d_and +U13 Net-_U13-Pad1_ Net-_U12-Pad3_ Net-_U13-Pad3_ d_nor +U14 Net-_U13-Pad3_ Net-_U14-Pad2_ d_inverter +U16 Net-_U12-Pad1_ Net-_U1-Pad12_ Net-_U16-Pad3_ d_and +U19 Net-_U1-Pad4_ Net-_U11-Pad2_ Net-_U17-Pad1_ d_and +U17 Net-_U17-Pad1_ Net-_U16-Pad3_ Net-_U17-Pad3_ d_nor +U18 Net-_U17-Pad3_ Net-_U18-Pad2_ d_inverter +U20 Net-_U12-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad3_ d_and +U23 Net-_U1-Pad5_ Net-_U11-Pad2_ Net-_U21-Pad1_ d_and +U21 Net-_U21-Pad1_ Net-_U20-Pad3_ Net-_U21-Pad3_ d_nor +U22 Net-_U21-Pad3_ Net-_U22-Pad2_ d_inverter +U5 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_or +U7 Net-_U5-Pad3_ Net-_U7-Pad2_ d_inverter +U4 Net-_U1-Pad6_ Net-_U12-Pad1_ d_inverter +U6 Net-_U12-Pad1_ Net-_U11-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X1 Net-_U10-Pad2_ Net-_U10-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad13_ ? SRFF_CUSTOM +X2 Net-_U14-Pad2_ Net-_U13-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad12_ ? SRFF_CUSTOM +X3 Net-_U18-Pad2_ Net-_U17-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad11_ ? SRFF_CUSTOM +X4 Net-_U22-Pad2_ Net-_U21-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad10_ ? SRFF_CUSTOM + +.end diff --git a/library/SubcircuitLibrary/SN7495A/SC_SN7495A.cir.out b/library/SubcircuitLibrary/SN7495A/SC_SN7495A.cir.out new file mode 100644 index 000000000..2784c7bd7 --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/SC_SN7495A.cir.out @@ -0,0 +1,105 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn7495a\sc_sn7495a.cir + +.include srff_custom.sub +* u8 net-_u12-pad1_ net-_u1-pad1_ net-_u8-pad3_ d_and +* u11 net-_u1-pad2_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u2 net-_u12-pad1_ net-_u1-pad9_ net-_u2-pad3_ d_and +* u3 net-_u1-pad6_ net-_u1-pad8_ net-_u3-pad3_ d_and +* u9 net-_u11-pad3_ net-_u8-pad3_ net-_u10-pad1_ d_nor +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u1-pad13_ net-_u12-pad3_ d_and +* u15 net-_u1-pad3_ net-_u11-pad2_ net-_u13-pad1_ d_and +* u13 net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ d_nor +* u14 net-_u13-pad3_ net-_u14-pad2_ d_inverter +* u16 net-_u12-pad1_ net-_u1-pad12_ net-_u16-pad3_ d_and +* u19 net-_u1-pad4_ net-_u11-pad2_ net-_u17-pad1_ d_and +* u17 net-_u17-pad1_ net-_u16-pad3_ net-_u17-pad3_ d_nor +* u18 net-_u17-pad3_ net-_u18-pad2_ d_inverter +* u20 net-_u12-pad1_ net-_u1-pad11_ net-_u20-pad3_ d_and +* u23 net-_u1-pad5_ net-_u11-pad2_ net-_u21-pad1_ d_and +* u21 net-_u21-pad1_ net-_u20-pad3_ net-_u21-pad3_ d_nor +* u22 net-_u21-pad3_ net-_u22-pad2_ d_inverter +* u5 net-_u2-pad3_ net-_u3-pad3_ net-_u5-pad3_ d_or +* u7 net-_u5-pad3_ net-_u7-pad2_ d_inverter +* u4 net-_u1-pad6_ net-_u12-pad1_ d_inverter +* u6 net-_u12-pad1_ net-_u11-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x1 net-_u10-pad2_ net-_u10-pad1_ net-_u7-pad2_ net-_u1-pad13_ ? srff_custom +x2 net-_u14-pad2_ net-_u13-pad3_ net-_u7-pad2_ net-_u1-pad12_ ? srff_custom +x3 net-_u18-pad2_ net-_u17-pad3_ net-_u7-pad2_ net-_u1-pad11_ ? srff_custom +x4 net-_u22-pad2_ net-_u21-pad3_ net-_u7-pad2_ net-_u1-pad10_ ? srff_custom +a1 [net-_u12-pad1_ net-_u1-pad1_ ] net-_u8-pad3_ u8 +a2 [net-_u1-pad2_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a3 [net-_u12-pad1_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a4 [net-_u1-pad6_ net-_u1-pad8_ ] net-_u3-pad3_ u3 +a5 [net-_u11-pad3_ net-_u8-pad3_ ] net-_u10-pad1_ u9 +a6 net-_u10-pad1_ net-_u10-pad2_ u10 +a7 [net-_u12-pad1_ net-_u1-pad13_ ] net-_u12-pad3_ u12 +a8 [net-_u1-pad3_ net-_u11-pad2_ ] net-_u13-pad1_ u15 +a9 [net-_u13-pad1_ net-_u12-pad3_ ] net-_u13-pad3_ u13 +a10 net-_u13-pad3_ net-_u14-pad2_ u14 +a11 [net-_u12-pad1_ net-_u1-pad12_ ] net-_u16-pad3_ u16 +a12 [net-_u1-pad4_ net-_u11-pad2_ ] net-_u17-pad1_ u19 +a13 [net-_u17-pad1_ net-_u16-pad3_ ] net-_u17-pad3_ u17 +a14 net-_u17-pad3_ net-_u18-pad2_ u18 +a15 [net-_u12-pad1_ net-_u1-pad11_ ] net-_u20-pad3_ u20 +a16 [net-_u1-pad5_ net-_u11-pad2_ ] net-_u21-pad1_ u23 +a17 [net-_u21-pad1_ net-_u20-pad3_ ] net-_u21-pad3_ u21 +a18 net-_u21-pad3_ net-_u22-pad2_ u22 +a19 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a20 net-_u5-pad3_ net-_u7-pad2_ u7 +a21 net-_u1-pad6_ net-_u12-pad1_ u4 +a22 net-_u12-pad1_ net-_u11-pad2_ u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7495A/SC_SN7495A.pro b/library/SubcircuitLibrary/SN7495A/SC_SN7495A.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/SC_SN7495A.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7495A/SC_SN7495A.sch b/library/SubcircuitLibrary/SN7495A/SC_SN7495A.sch new file mode 100644 index 000000000..1c60587e6 --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/SC_SN7495A.sch @@ -0,0 +1,691 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_SN7495A-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U8 +U 1 1 685CF2B1 +P 3950 3650 +F 0 "U8" H 3950 3650 60 0000 C CNN +F 1 "d_and" H 4000 3750 60 0000 C CNN +F 2 "" H 3950 3650 60 0000 C CNN +F 3 "" H 3950 3650 60 0000 C CNN + 1 3950 3650 + 0 1 1 0 +$EndComp +$Comp +L d_and U11 +U 1 1 685CF320 +P 4950 3650 +F 0 "U11" H 4950 3650 60 0000 C CNN +F 1 "d_and" H 5000 3750 60 0000 C CNN +F 2 "" H 4950 3650 60 0000 C CNN +F 3 "" H 4950 3650 60 0000 C CNN + 1 4950 3650 + 0 1 1 0 +$EndComp +$Comp +L d_and U2 +U 1 1 685CF359 +P 1750 6100 +F 0 "U2" H 1750 6100 60 0000 C CNN +F 1 "d_and" H 1800 6200 60 0000 C CNN +F 2 "" H 1750 6100 60 0000 C CNN +F 3 "" H 1750 6100 60 0000 C CNN + 1 1750 6100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 685CF3AC +P 1750 6700 +F 0 "U3" H 1750 6700 60 0000 C CNN +F 1 "d_and" H 1800 6800 60 0000 C CNN +F 2 "" H 1750 6700 60 0000 C CNN +F 3 "" H 1750 6700 60 0000 C CNN + 1 1750 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U9 +U 1 1 685CF411 +P 4400 4650 +F 0 "U9" H 4400 4650 60 0000 C CNN +F 1 "d_nor" H 4450 4750 60 0000 C CNN +F 2 "" H 4400 4650 60 0000 C CNN +F 3 "" H 4400 4650 60 0000 C CNN + 1 4400 4650 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U10 +U 1 1 685CF969 +P 4450 5650 +F 0 "U10" H 4450 5550 60 0000 C CNN +F 1 "d_inverter" H 4450 5800 60 0000 C CNN +F 2 "" H 4500 5600 60 0000 C CNN +F 3 "" H 4500 5600 60 0000 C CNN + 1 4450 5650 + 0 1 1 0 +$EndComp +$Comp +L d_and U12 +U 1 1 685CFAB0 +P 6850 3650 +F 0 "U12" H 6850 3650 60 0000 C CNN +F 1 "d_and" H 6900 3750 60 0000 C CNN +F 2 "" H 6850 3650 60 0000 C CNN +F 3 "" H 6850 3650 60 0000 C CNN + 1 6850 3650 + 0 1 1 0 +$EndComp +$Comp +L d_and U15 +U 1 1 685CFAB6 +P 7850 3650 +F 0 "U15" H 7850 3650 60 0000 C CNN +F 1 "d_and" H 7900 3750 60 0000 C CNN +F 2 "" H 7850 3650 60 0000 C CNN +F 3 "" H 7850 3650 60 0000 C CNN + 1 7850 3650 + 0 1 1 0 +$EndComp +$Comp +L d_nor U13 +U 1 1 685CFABC +P 7300 4650 +F 0 "U13" H 7300 4650 60 0000 C CNN +F 1 "d_nor" H 7350 4750 60 0000 C CNN +F 2 "" H 7300 4650 60 0000 C CNN +F 3 "" H 7300 4650 60 0000 C CNN + 1 7300 4650 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U14 +U 1 1 685CFAC6 +P 7350 5600 +F 0 "U14" H 7350 5500 60 0000 C CNN +F 1 "d_inverter" H 7350 5750 60 0000 C CNN +F 2 "" H 7400 5550 60 0000 C CNN +F 3 "" H 7400 5550 60 0000 C CNN + 1 7350 5600 + 0 1 1 0 +$EndComp +$Comp +L d_and U16 +U 1 1 685CFB6C +P 10050 3700 +F 0 "U16" H 10050 3700 60 0000 C CNN +F 1 "d_and" H 10100 3800 60 0000 C CNN +F 2 "" H 10050 3700 60 0000 C CNN +F 3 "" H 10050 3700 60 0000 C CNN + 1 10050 3700 + 0 1 1 0 +$EndComp +$Comp +L d_and U19 +U 1 1 685CFB72 +P 11050 3700 +F 0 "U19" H 11050 3700 60 0000 C CNN +F 1 "d_and" H 11100 3800 60 0000 C CNN +F 2 "" H 11050 3700 60 0000 C CNN +F 3 "" H 11050 3700 60 0000 C CNN + 1 11050 3700 + 0 1 1 0 +$EndComp +$Comp +L d_nor U17 +U 1 1 685CFB78 +P 10500 4700 +F 0 "U17" H 10500 4700 60 0000 C CNN +F 1 "d_nor" H 10550 4800 60 0000 C CNN +F 2 "" H 10500 4700 60 0000 C CNN +F 3 "" H 10500 4700 60 0000 C CNN + 1 10500 4700 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U18 +U 1 1 685CFB82 +P 10550 5650 +F 0 "U18" H 10550 5550 60 0000 C CNN +F 1 "d_inverter" H 10550 5800 60 0000 C CNN +F 2 "" H 10600 5600 60 0000 C CNN +F 3 "" H 10600 5600 60 0000 C CNN + 1 10550 5650 + 0 1 1 0 +$EndComp +$Comp +L d_and U20 +U 1 1 685CFC28 +P 13000 3650 +F 0 "U20" H 13000 3650 60 0000 C CNN +F 1 "d_and" H 13050 3750 60 0000 C CNN +F 2 "" H 13000 3650 60 0000 C CNN +F 3 "" H 13000 3650 60 0000 C CNN + 1 13000 3650 + 0 1 1 0 +$EndComp +$Comp +L d_and U23 +U 1 1 685CFC2E +P 14000 3650 +F 0 "U23" H 14000 3650 60 0000 C CNN +F 1 "d_and" H 14050 3750 60 0000 C CNN +F 2 "" H 14000 3650 60 0000 C CNN +F 3 "" H 14000 3650 60 0000 C CNN + 1 14000 3650 + 0 1 1 0 +$EndComp +$Comp +L d_nor U21 +U 1 1 685CFC34 +P 13450 4650 +F 0 "U21" H 13450 4650 60 0000 C CNN +F 1 "d_nor" H 13500 4750 60 0000 C CNN +F 2 "" H 13450 4650 60 0000 C CNN +F 3 "" H 13450 4650 60 0000 C CNN + 1 13450 4650 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U22 +U 1 1 685CFC3E +P 13500 5550 +F 0 "U22" H 13500 5450 60 0000 C CNN +F 1 "d_inverter" H 13500 5700 60 0000 C CNN +F 2 "" H 13550 5500 60 0000 C CNN +F 3 "" H 13550 5500 60 0000 C CNN + 1 13500 5550 + 0 1 1 0 +$EndComp +$Comp +L d_or U5 +U 1 1 685CFD94 +P 2700 6400 +F 0 "U5" H 2700 6400 60 0000 C CNN +F 1 "d_or" H 2700 6500 60 0000 C CNN +F 2 "" H 2700 6400 60 0000 C CNN +F 3 "" H 2700 6400 60 0000 C CNN + 1 2700 6400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 685D006C +P 3450 6350 +F 0 "U7" H 3450 6250 60 0000 C CNN +F 1 "d_inverter" H 3450 6500 60 0000 C CNN +F 2 "" H 3500 6300 60 0000 C CNN +F 3 "" H 3500 6300 60 0000 C CNN + 1 3450 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 685D00DD +P 2100 2850 +F 0 "U4" H 2100 2750 60 0000 C CNN +F 1 "d_inverter" H 2100 3000 60 0000 C CNN +F 2 "" H 2150 2800 60 0000 C CNN +F 3 "" H 2150 2800 60 0000 C CNN + 1 2100 2850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 685D0181 +P 3150 2850 +F 0 "U6" H 3150 2750 60 0000 C CNN +F 1 "d_inverter" H 3150 3000 60 0000 C CNN +F 2 "" H 3200 2800 60 0000 C CNN +F 3 "" H 3200 2800 60 0000 C CNN + 1 3150 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4000 4100 4400 4100 +Wire Wire Line + 4400 4100 4400 4200 +Wire Wire Line + 4500 4200 4500 4100 +Wire Wire Line + 4500 4100 5000 4100 +Wire Wire Line + 6900 4100 7300 4100 +Wire Wire Line + 7300 4100 7300 4200 +Wire Wire Line + 7400 4200 7400 4100 +Wire Wire Line + 7400 4100 7900 4100 +Wire Wire Line + 10100 4150 10500 4150 +Wire Wire Line + 10500 4150 10500 4250 +Wire Wire Line + 10600 4250 10600 4150 +Wire Wire Line + 10600 4150 11100 4150 +Wire Wire Line + 13050 4100 13450 4100 +Wire Wire Line + 13450 4100 13450 4200 +Wire Wire Line + 13550 4200 13550 4100 +Wire Wire Line + 13550 4100 14050 4100 +Wire Wire Line + 2250 6300 2250 6050 +Wire Wire Line + 2250 6050 2200 6050 +Wire Wire Line + 2250 6400 2250 6650 +Wire Wire Line + 2250 6650 2200 6650 +Wire Wire Line + 3750 6350 5050 6350 +Wire Wire Line + 4250 6350 4250 7450 +Wire Wire Line + 4250 7450 13550 7450 +Wire Wire Line + 7750 7450 7750 6300 +Wire Wire Line + 7750 6300 8100 6300 +Connection ~ 4250 6350 +Wire Wire Line + 10900 7450 10900 6350 +Wire Wire Line + 10900 6350 11300 6350 +Connection ~ 7750 7450 +Wire Wire Line + 13550 7450 13550 6250 +Wire Wire Line + 13550 6250 14050 6250 +Connection ~ 10900 7450 +Wire Wire Line + 1300 6600 1050 6600 +Wire Wire Line + 1050 6600 1050 2850 +Wire Wire Line + 1050 2850 1800 2850 +Wire Wire Line + 2400 2850 2850 2850 +Wire Wire Line + 1300 6000 1300 4150 +Wire Wire Line + 1300 4150 2650 4150 +Wire Wire Line + 2650 4150 2650 2850 +Connection ~ 2650 2850 +Wire Wire Line + 4450 5100 4450 5350 +Wire Wire Line + 4450 5950 5050 5950 +Wire Wire Line + 4450 5250 3850 5250 +Wire Wire Line + 3850 5250 3850 6800 +Wire Wire Line + 3850 6800 5050 6800 +Connection ~ 4450 5250 +Wire Wire Line + 7350 5100 7350 5300 +Wire Wire Line + 7350 5900 8100 5900 +Wire Wire Line + 7350 5250 7050 5250 +Wire Wire Line + 7050 5250 7050 6750 +Wire Wire Line + 7050 6750 8100 6750 +Connection ~ 7350 5250 +Wire Wire Line + 10550 5150 10550 5350 +Wire Wire Line + 10550 5950 11300 5950 +Wire Wire Line + 13500 5850 14050 5850 +Wire Wire Line + 13500 5250 13500 5100 +Wire Wire Line + 10550 5250 10250 5250 +Wire Wire Line + 10250 5250 10250 6800 +Wire Wire Line + 10250 6800 11300 6800 +Connection ~ 10550 5250 +Wire Wire Line + 13500 5200 13100 5200 +Wire Wire Line + 13100 5200 13100 6700 +Wire Wire Line + 13100 6700 14050 6700 +Connection ~ 13500 5200 +Wire Wire Line + 3450 2850 14000 2850 +Wire Wire Line + 4950 2850 4950 3200 +Wire Wire Line + 7850 2850 7850 3200 +Connection ~ 4950 2850 +Wire Wire Line + 11050 2850 11050 3250 +Connection ~ 7850 2850 +Wire Wire Line + 14000 2850 14000 3200 +Connection ~ 11050 2850 +Wire Wire Line + 2650 3000 13100 3000 +Wire Wire Line + 4050 3000 4050 3200 +Connection ~ 2650 3000 +Wire Wire Line + 6950 3000 6950 3200 +Connection ~ 4050 3000 +Wire Wire Line + 10150 3000 10150 3250 +Connection ~ 6950 3000 +Wire Wire Line + 13100 3000 13100 3200 +Connection ~ 10150 3000 +Wire Wire Line + 6450 3200 6450 6050 +Wire Wire Line + 6450 3200 6850 3200 +Wire Wire Line + 9550 3250 9550 5950 +Wire Wire Line + 9550 3250 10050 3250 +Wire Wire Line + 12650 3200 12650 6000 +Wire Wire Line + 12650 3200 13000 3200 +$Comp +L PORT U1 +U 1 1 685D6BAF +P 3700 3200 +F 0 "U1" H 3750 3300 30 0000 C CNN +F 1 "PORT" H 3700 3200 30 0000 C CNN +F 2 "" H 3700 3200 60 0000 C CNN +F 3 "" H 3700 3200 60 0000 C CNN + 1 3700 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685D718D +P 5300 3200 +F 0 "U1" H 5350 3300 30 0000 C CNN +F 1 "PORT" H 5300 3200 30 0000 C CNN +F 2 "" H 5300 3200 60 0000 C CNN +F 3 "" H 5300 3200 60 0000 C CNN + 2 5300 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 685D7232 +P 8200 3200 +F 0 "U1" H 8250 3300 30 0000 C CNN +F 1 "PORT" H 8200 3200 30 0000 C CNN +F 2 "" H 8200 3200 60 0000 C CNN +F 3 "" H 8200 3200 60 0000 C CNN + 3 8200 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 685D72A3 +P 11400 3250 +F 0 "U1" H 11450 3350 30 0000 C CNN +F 1 "PORT" H 11400 3250 30 0000 C CNN +F 2 "" H 11400 3250 60 0000 C CNN +F 3 "" H 11400 3250 60 0000 C CNN + 4 11400 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 685D7554 +P 14350 3200 +F 0 "U1" H 14400 3300 30 0000 C CNN +F 1 "PORT" H 14350 3200 30 0000 C CNN +F 2 "" H 14350 3200 60 0000 C CNN +F 3 "" H 14350 3200 60 0000 C CNN + 5 14350 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 685D7943 +P 800 2850 +F 0 "U1" H 850 2950 30 0000 C CNN +F 1 "PORT" H 800 2850 30 0000 C CNN +F 2 "" H 800 2850 60 0000 C CNN +F 3 "" H 800 2850 60 0000 C CNN + 6 800 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 685D79E2 +P 800 2600 +F 0 "U1" H 850 2700 30 0000 C CNN +F 1 "PORT" H 800 2600 30 0000 C CNN +F 2 "" H 800 2600 60 0000 C CNN +F 3 "" H 800 2600 60 0000 C CNN + 7 800 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685D7A7D +P 1050 6700 +F 0 "U1" H 1100 6800 30 0000 C CNN +F 1 "PORT" H 1050 6700 30 0000 C CNN +F 2 "" H 1050 6700 60 0000 C CNN +F 3 "" H 1050 6700 60 0000 C CNN + 8 1050 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 685D7B26 +P 1050 6100 +F 0 "U1" H 1100 6200 30 0000 C CNN +F 1 "PORT" H 1050 6100 30 0000 C CNN +F 2 "" H 1050 6100 60 0000 C CNN +F 3 "" H 1050 6100 60 0000 C CNN + 9 1050 6100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685D7BA3 +P 15650 5850 +F 0 "U1" H 15700 5950 30 0000 C CNN +F 1 "PORT" H 15650 5850 30 0000 C CNN +F 2 "" H 15650 5850 60 0000 C CNN +F 3 "" H 15650 5850 60 0000 C CNN + 10 15650 5850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 685D7CEC +P 12900 5950 +F 0 "U1" H 12950 6050 30 0000 C CNN +F 1 "PORT" H 12900 5950 30 0000 C CNN +F 2 "" H 12900 5950 60 0000 C CNN +F 3 "" H 12900 5950 60 0000 C CNN + 11 12900 5950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 685D7D8D +P 9800 5900 +F 0 "U1" H 9850 6000 30 0000 C CNN +F 1 "PORT" H 9800 5900 30 0000 C CNN +F 2 "" H 9800 5900 60 0000 C CNN +F 3 "" H 9800 5900 60 0000 C CNN + 12 9800 5900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 685D82AC +P 6700 5950 +F 0 "U1" H 6750 6050 30 0000 C CNN +F 1 "PORT" H 6700 5950 30 0000 C CNN +F 2 "" H 6700 5950 60 0000 C CNN +F 3 "" H 6700 5950 60 0000 C CNN + 13 6700 5950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 685D8B54 +P 800 2350 +F 0 "U1" H 850 2450 30 0000 C CNN +F 1 "PORT" H 800 2350 30 0000 C CNN +F 2 "" H 800 2350 60 0000 C CNN +F 3 "" H 800 2350 60 0000 C CNN + 14 800 2350 + 1 0 0 -1 +$EndComp +NoConn ~ 1050 2350 +NoConn ~ 1050 2600 +$Comp +L SRFF_CUSTOM X1 +U 1 1 685EC8A5 +P 5650 6400 +F 0 "X1" H 6050 6950 60 0000 C CNN +F 1 "SRFF_CUSTOM" H 5550 6950 60 0000 C CNN +F 2 "" H 5650 6400 60 0001 C CNN +F 3 "" H 5650 6400 60 0001 C CNN + 1 5650 6400 + 1 0 0 -1 +$EndComp +$Comp +L SRFF_CUSTOM X2 +U 1 1 685EC93E +P 8700 6300 +F 0 "X2" H 9100 6850 60 0000 C CNN +F 1 "SRFF_CUSTOM" H 8600 6850 60 0000 C CNN +F 2 "" H 8700 6300 60 0001 C CNN +F 3 "" H 8700 6300 60 0001 C CNN + 1 8700 6300 + 1 0 0 -1 +$EndComp +$Comp +L SRFF_CUSTOM X3 +U 1 1 685EC9E9 +P 11900 6350 +F 0 "X3" H 12300 6900 60 0000 C CNN +F 1 "SRFF_CUSTOM" H 11800 6900 60 0000 C CNN +F 2 "" H 11900 6350 60 0001 C CNN +F 3 "" H 11900 6350 60 0001 C CNN + 1 11900 6350 + 1 0 0 -1 +$EndComp +$Comp +L SRFF_CUSTOM X4 +U 1 1 685ECA8E +P 14650 6200 +F 0 "X4" H 15050 6750 60 0000 C CNN +F 1 "SRFF_CUSTOM" H 14550 6750 60 0000 C CNN +F 2 "" H 14650 6200 60 0001 C CNN +F 3 "" H 14650 6200 60 0001 C CNN + 1 14650 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 5950 5050 6050 +Wire Wire Line + 5050 6350 5050 6400 +Wire Wire Line + 5050 6800 5050 6700 +Wire Wire Line + 8100 5900 8100 5950 +Wire Wire Line + 8100 6750 8100 6600 +Wire Wire Line + 11300 5950 11300 6000 +Wire Wire Line + 11300 6800 11300 6650 +Wire Wire Line + 14050 6250 14050 6200 +Wire Wire Line + 14050 6700 14050 6500 +Wire Wire Line + 15300 5850 15400 5850 +NoConn ~ 15300 6500 +NoConn ~ 12550 6650 +NoConn ~ 9350 6600 +NoConn ~ 6300 6700 +Wire Wire Line + 6450 6050 6300 6050 +Connection ~ 6450 5950 +Wire Wire Line + 9550 5950 9350 5950 +Connection ~ 9550 5900 +Wire Wire Line + 12650 6000 12550 6000 +Connection ~ 12650 5950 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7495A/SC_SN7495A.sub b/library/SubcircuitLibrary/SN7495A/SC_SN7495A.sub new file mode 100644 index 000000000..1eb55c63d --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/SC_SN7495A.sub @@ -0,0 +1,99 @@ +* Subcircuit SC_SN7495A +.subckt SC_SN7495A net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn7495a\sc_sn7495a.cir +.include srff_custom.sub +* u8 net-_u12-pad1_ net-_u1-pad1_ net-_u8-pad3_ d_and +* u11 net-_u1-pad2_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u2 net-_u12-pad1_ net-_u1-pad9_ net-_u2-pad3_ d_and +* u3 net-_u1-pad6_ net-_u1-pad8_ net-_u3-pad3_ d_and +* u9 net-_u11-pad3_ net-_u8-pad3_ net-_u10-pad1_ d_nor +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u1-pad13_ net-_u12-pad3_ d_and +* u15 net-_u1-pad3_ net-_u11-pad2_ net-_u13-pad1_ d_and +* u13 net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ d_nor +* u14 net-_u13-pad3_ net-_u14-pad2_ d_inverter +* u16 net-_u12-pad1_ net-_u1-pad12_ net-_u16-pad3_ d_and +* u19 net-_u1-pad4_ net-_u11-pad2_ net-_u17-pad1_ d_and +* u17 net-_u17-pad1_ net-_u16-pad3_ net-_u17-pad3_ d_nor +* u18 net-_u17-pad3_ net-_u18-pad2_ d_inverter +* u20 net-_u12-pad1_ net-_u1-pad11_ net-_u20-pad3_ d_and +* u23 net-_u1-pad5_ net-_u11-pad2_ net-_u21-pad1_ d_and +* u21 net-_u21-pad1_ net-_u20-pad3_ net-_u21-pad3_ d_nor +* u22 net-_u21-pad3_ net-_u22-pad2_ d_inverter +* u5 net-_u2-pad3_ net-_u3-pad3_ net-_u5-pad3_ d_or +* u7 net-_u5-pad3_ net-_u7-pad2_ d_inverter +* u4 net-_u1-pad6_ net-_u12-pad1_ d_inverter +* u6 net-_u12-pad1_ net-_u11-pad2_ d_inverter +x1 net-_u10-pad2_ net-_u10-pad1_ net-_u7-pad2_ net-_u1-pad13_ ? srff_custom +x2 net-_u14-pad2_ net-_u13-pad3_ net-_u7-pad2_ net-_u1-pad12_ ? srff_custom +x3 net-_u18-pad2_ net-_u17-pad3_ net-_u7-pad2_ net-_u1-pad11_ ? srff_custom +x4 net-_u22-pad2_ net-_u21-pad3_ net-_u7-pad2_ net-_u1-pad10_ ? srff_custom +a1 [net-_u12-pad1_ net-_u1-pad1_ ] net-_u8-pad3_ u8 +a2 [net-_u1-pad2_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a3 [net-_u12-pad1_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a4 [net-_u1-pad6_ net-_u1-pad8_ ] net-_u3-pad3_ u3 +a5 [net-_u11-pad3_ net-_u8-pad3_ ] net-_u10-pad1_ u9 +a6 net-_u10-pad1_ net-_u10-pad2_ u10 +a7 [net-_u12-pad1_ net-_u1-pad13_ ] net-_u12-pad3_ u12 +a8 [net-_u1-pad3_ net-_u11-pad2_ ] net-_u13-pad1_ u15 +a9 [net-_u13-pad1_ net-_u12-pad3_ ] net-_u13-pad3_ u13 +a10 net-_u13-pad3_ net-_u14-pad2_ u14 +a11 [net-_u12-pad1_ net-_u1-pad12_ ] net-_u16-pad3_ u16 +a12 [net-_u1-pad4_ net-_u11-pad2_ ] net-_u17-pad1_ u19 +a13 [net-_u17-pad1_ net-_u16-pad3_ ] net-_u17-pad3_ u17 +a14 net-_u17-pad3_ net-_u18-pad2_ u18 +a15 [net-_u12-pad1_ net-_u1-pad11_ ] net-_u20-pad3_ u20 +a16 [net-_u1-pad5_ net-_u11-pad2_ ] net-_u21-pad1_ u23 +a17 [net-_u21-pad1_ net-_u20-pad3_ ] net-_u21-pad3_ u21 +a18 net-_u21-pad3_ net-_u22-pad2_ u22 +a19 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a20 net-_u5-pad3_ net-_u7-pad2_ u7 +a21 net-_u1-pad6_ net-_u12-pad1_ u4 +a22 net-_u12-pad1_ net-_u11-pad2_ u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SC_SN7495A \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7495A/SC_SN7495A_Previous_Values.xml b/library/SubcircuitLibrary/SN7495A/SC_SN7495A_Previous_Values.xml new file mode 100644 index 000000000..ed24e0040 --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/SC_SN7495A_Previous_Values.xml @@ -0,0 +1 @@ +d_srffd_srffd_srffd_srffd_andd_andd_andd_andd_nord_inverterd_andd_andd_nord_inverterd_andd_andd_nord_inverterd_andd_andd_nord_inverterd_ord_inverterd_inverterd_inverterd_andd_andd_nord_inverterd_andd_nord_inverterd_andd_nord_inverterC:\FOSSEE2\eSim\library\SubcircuitLibrary\srff_customC:\FOSSEE2\eSim\library\SubcircuitLibrary\srff_customC:\FOSSEE2\eSim\library\SubcircuitLibrary\srff_customC:\FOSSEE2\eSim\library\SubcircuitLibrary\srff_customtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7495A/srff_custom-cache.lib b/library/SubcircuitLibrary/SN7495A/srff_custom-cache.lib new file mode 100644 index 000000000..246dd8ccb --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/srff_custom-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7495A/srff_custom.cir b/library/SubcircuitLibrary/SN7495A/srff_custom.cir new file mode 100644 index 000000000..b28954af0 --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/srff_custom.cir @@ -0,0 +1,16 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\srff_custom\srff_custom.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/27/25 22:00:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_nand +U4 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U4-Pad3_ d_nand +U5 Net-_U3-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad4_ d_nand +U6 Net-_U1-Pad4_ Net-_U4-Pad3_ Net-_U1-Pad5_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT +U2 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/SN7495A/srff_custom.cir.out b/library/SubcircuitLibrary/SN7495A/srff_custom.cir.out new file mode 100644 index 000000000..8c64c1109 --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/srff_custom.cir.out @@ -0,0 +1,32 @@ +* c:\fossee2\esim\library\subcircuitlibrary\srff_custom\srff_custom.cir + +* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad4_ d_nand +* u6 net-_u1-pad4_ net-_u4-pad3_ net-_u1-pad5_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad4_ u5 +a4 [net-_u1-pad4_ net-_u4-pad3_ ] net-_u1-pad5_ u6 +a5 net-_u1-pad3_ net-_u2-pad2_ u2 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7495A/srff_custom.pro b/library/SubcircuitLibrary/SN7495A/srff_custom.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/srff_custom.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7495A/srff_custom.sch b/library/SubcircuitLibrary/SN7495A/srff_custom.sch new file mode 100644 index 000000000..cee6789d8 --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/srff_custom.sch @@ -0,0 +1,198 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U3 +U 1 1 685EBFD6 +P 3900 2450 +F 0 "U3" H 3900 2450 60 0000 C CNN +F 1 "d_nand" H 3950 2550 60 0000 C CNN +F 2 "" H 3900 2450 60 0000 C CNN +F 3 "" H 3900 2450 60 0000 C CNN + 1 3900 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 685EC025 +P 3900 3450 +F 0 "U4" H 3900 3450 60 0000 C CNN +F 1 "d_nand" H 3950 3550 60 0000 C CNN +F 2 "" H 3900 3450 60 0000 C CNN +F 3 "" H 3900 3450 60 0000 C CNN + 1 3900 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 685EC070 +P 5950 2500 +F 0 "U5" H 5950 2500 60 0000 C CNN +F 1 "d_nand" H 6000 2600 60 0000 C CNN +F 2 "" H 5950 2500 60 0000 C CNN +F 3 "" H 5950 2500 60 0000 C CNN + 1 5950 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U6 +U 1 1 685EC0ED +P 5950 3400 +F 0 "U6" H 5950 3400 60 0000 C CNN +F 1 "d_nand" H 6000 3500 60 0000 C CNN +F 2 "" H 5950 3400 60 0000 C CNN +F 3 "" H 5950 3400 60 0000 C CNN + 1 5950 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 2400 5500 2400 +Wire Wire Line + 3450 2450 3250 2450 +Wire Wire Line + 3250 2450 3250 3350 +Wire Wire Line + 3250 3350 3450 3350 +Wire Wire Line + 4350 3400 5500 3400 +Wire Wire Line + 6400 2450 6400 2900 +Wire Wire Line + 6400 2900 5500 2900 +Wire Wire Line + 5500 2900 5500 3300 +Wire Wire Line + 5500 2500 5500 2800 +Wire Wire Line + 5500 2800 6500 2800 +Wire Wire Line + 6500 2800 6500 3350 +Wire Wire Line + 6400 3350 6650 3350 +$Comp +L PORT U1 +U 1 1 685EC1AC +P 3200 2350 +F 0 "U1" H 3250 2450 30 0000 C CNN +F 1 "PORT" H 3200 2350 30 0000 C CNN +F 2 "" H 3200 2350 60 0000 C CNN +F 3 "" H 3200 2350 60 0000 C CNN + 1 3200 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685EC215 +P 3200 3450 +F 0 "U1" H 3250 3550 30 0000 C CNN +F 1 "PORT" H 3200 3450 30 0000 C CNN +F 2 "" H 3200 3450 60 0000 C CNN +F 3 "" H 3200 3450 60 0000 C CNN + 2 3200 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 685EC266 +P 2000 2850 +F 0 "U1" H 2050 2950 30 0000 C CNN +F 1 "PORT" H 2000 2850 30 0000 C CNN +F 2 "" H 2000 2850 60 0000 C CNN +F 3 "" H 2000 2850 60 0000 C CNN + 3 2000 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685EC2D2 +P 6900 2450 +F 0 "U1" H 6950 2550 30 0000 C CNN +F 1 "PORT" H 6900 2450 30 0000 C CNN +F 2 "" H 6900 2450 60 0000 C CNN +F 3 "" H 6900 2450 60 0000 C CNN + 4 6900 2450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 685EC34B +P 6900 3350 +F 0 "U1" H 6950 3450 30 0000 C CNN +F 1 "PORT" H 6900 3350 30 0000 C CNN +F 2 "" H 6900 3350 60 0000 C CNN +F 3 "" H 6900 3350 60 0000 C CNN + 5 6900 3350 + -1 0 0 1 +$EndComp +Wire Wire Line + 6400 2450 6650 2450 +Connection ~ 6500 3350 +Wire Wire Line + 3000 2850 3250 2850 +Connection ~ 3250 2850 +$Comp +L d_inverter U2 +U 1 1 685EC8BB +P 2700 2850 +F 0 "U2" H 2700 2750 60 0000 C CNN +F 1 "d_inverter" H 2700 3000 60 0000 C CNN +F 2 "" H 2750 2800 60 0000 C CNN +F 3 "" H 2750 2800 60 0000 C CNN + 1 2700 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2250 2850 2400 2850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7495A/srff_custom.sub b/library/SubcircuitLibrary/SN7495A/srff_custom.sub new file mode 100644 index 000000000..665cd2dcb --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/srff_custom.sub @@ -0,0 +1,26 @@ +* Subcircuit srff_custom +.subckt srff_custom net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\fossee2\esim\library\subcircuitlibrary\srff_custom\srff_custom.cir +* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand +* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand +* u5 net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad4_ d_nand +* u6 net-_u1-pad4_ net-_u4-pad3_ net-_u1-pad5_ d_nand +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3 +a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4 +a3 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad4_ u5 +a4 [net-_u1-pad4_ net-_u4-pad3_ ] net-_u1-pad5_ u6 +a5 net-_u1-pad3_ net-_u2-pad2_ u2 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends srff_custom \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7495A/srff_custom_Previous_Values.xml b/library/SubcircuitLibrary/SN7495A/srff_custom_Previous_Values.xml new file mode 100644 index 000000000..bdb5d78b6 --- /dev/null +++ b/library/SubcircuitLibrary/SN7495A/srff_custom_Previous_Values.xml @@ -0,0 +1 @@ +d_nandd_nandd_nandd_nandd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file From efcd1efa78f0e320755a9c8bc3f46dec9118f0de Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:49:37 +0530 Subject: [PATCH 33/33] Contains IC symbols --- library/SubcircuitLibrary/eSim_Subckt.lib | 2672 ++++++++++++--------- 1 file changed, 1486 insertions(+), 1186 deletions(-) diff --git a/library/SubcircuitLibrary/eSim_Subckt.lib b/library/SubcircuitLibrary/eSim_Subckt.lib index 56cddf041..d3f839be7 100644 --- a/library/SubcircuitLibrary/eSim_Subckt.lib +++ b/library/SubcircuitLibrary/eSim_Subckt.lib @@ -1,1186 +1,1486 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 10bitDAC -# -DEF 10bitDAC X 0 40 Y Y 1 F N -F0 "X" 0 50 60 H V C CNN -F1 "10bitDAC" -50 -50 60 H V C CNN -F2 "" 0 50 60 H I C CNN -F3 "" 0 50 60 H I C CNN -DRAW -S -500 500 400 -600 0 1 0 N -X D0 1 -700 -500 200 R 50 50 1 1 I -X D1 2 -700 -400 200 R 50 50 1 1 I -X D2 3 -700 -300 200 R 50 50 1 1 I -X D3 4 -700 -200 200 R 50 50 1 1 I -X D4 5 -700 -100 200 R 50 50 1 1 I -X D5 6 -700 0 200 R 50 50 1 1 I -X D6 7 -700 100 200 R 50 50 1 1 I -X D7 8 -700 200 200 R 50 50 1 1 I -X D8 9 -700 300 200 R 50 50 1 1 I -X D9 10 -700 400 200 R 50 50 1 1 I -X AnalogOut 11 600 350 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 2BITMUL -# -DEF 2BITMUL X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "2BITMUL" 0 0 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -300 400 300 -400 0 1 0 N -X A0 1 -500 300 200 R 50 50 1 1 I -X A1 2 -500 150 200 R 50 50 1 1 I -X B0 3 -500 -50 200 R 50 50 1 1 I -X B1 4 -500 -250 200 R 50 50 1 1 I -X M0 5 500 250 200 L 50 50 1 1 O -X M1 6 500 100 200 L 50 50 1 1 O -X M2 7 500 -50 200 L 50 50 1 1 O -X M3 8 500 -250 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 100 -50 60 H V C CNN -F1 "3_and" 150 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 -P 2 0 1 0 -150 200 200 200 N -P 3 0 1 0 -150 200 -150 -100 200 -100 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X out 4 500 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 4_OR -# -DEF 4_OR X 0 40 Y Y 1 F N -F0 "X" 150 -100 60 H V C CNN -F1 "4_OR" 150 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 -A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 -A -30 -99 393 627 146 0 1 0 N 150 250 350 0 -P 2 0 1 0 -200 -250 150 -250 N -P 2 0 1 0 -200 250 150 250 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X in4 4 -350 -150 200 R 50 50 1 1 I -X out 5 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 4_and -# -DEF 4_and X 0 40 Y Y 1 F N -F0 "X" 50 -50 60 H V C CNN -F1 "4_and" 100 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 -P 2 0 1 0 -200 200 150 200 N -P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N -X in1 1 -400 150 200 R 50 50 1 1 I -X in2 2 -400 50 200 R 50 50 1 1 I -X in3 3 -400 -50 200 R 50 50 1 1 I -X in4 4 -400 -150 200 R 50 50 1 1 I -X out 5 500 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 556 -# -DEF 556 X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "556" 0 0 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 400 250 -550 0 1 0 N -X dis1 1 -500 150 200 R 50 50 1 1 I -X thr1 2 -500 -150 200 R 50 50 1 1 I -X cv1 3 -150 -750 200 U 50 50 1 1 I -X rst1 4 -200 600 200 D 50 50 1 1 I -X out1 5 -500 0 200 R 50 50 1 1 O -X trig1 6 -500 -300 200 R 50 50 1 1 I -X gnd 7 0 -750 200 U 50 50 1 1 I -X trig2 8 450 -300 200 L 50 50 1 1 I -X out2 9 450 0 200 L 50 50 1 1 O -X rst2 10 100 600 200 D 50 50 1 1 I -X cv2 11 150 -750 200 U 50 50 1 1 I -X thr2 12 450 -150 200 L 50 50 1 1 I -X dis2 13 450 150 200 L 50 50 1 1 I -X vcc 14 -50 600 200 D 50 50 1 1 I -ENDDRAW -ENDDEF -# -# 5_and -# -DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 50 -100 60 H V C CNN -F1 "5_and" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 -P 2 0 1 0 -250 250 150 250 N -P 3 0 1 0 -250 250 -250 -250 150 -250 N -X in1 1 -450 200 200 R 50 50 1 1 I -X in2 2 -450 100 200 R 50 50 1 1 I -X in3 3 -450 0 200 R 50 50 1 1 I -X in4 4 -450 -100 200 R 50 50 1 1 I -X in5 5 -450 -200 200 R 50 50 1 1 I -X out 6 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 74HC194 -# -DEF 74HC194 X 0 40 Y Y 1 F N -F0 "X" 50 300 60 H V C CNN -F1 "74HC194" 50 550 60 H V C CNN -F2 "" 50 300 60 H I C CNN -F3 "" 50 300 60 H I C CNN -DRAW -A 0 1350 100 -1799 -1 0 1 0 N -100 1350 100 1350 -S -400 1350 450 -750 0 1 0 N -X MR_bar 1 -600 1200 200 R 50 50 1 1 I -X DSR 2 -600 950 200 R 50 50 1 1 I -X D0 3 -600 700 200 R 50 50 1 1 I -X D1 4 -600 450 200 R 50 50 1 1 I -X D2 5 -600 200 200 R 50 50 1 1 I -X D3 6 -600 -50 200 R 50 50 1 1 I -X DSL 7 -600 -300 200 R 50 50 1 1 I -X GND 8 -600 -550 200 R 50 50 1 1 I -X S0 9 650 -550 200 L 50 50 1 1 I -X S1 10 650 -300 200 L 50 50 1 1 I -X CP 11 650 -50 200 L 50 50 1 1 I -X Q3 12 650 200 200 L 50 50 1 1 O -X Q2 13 650 450 200 L 50 50 1 1 O -X Q1 14 650 700 200 L 50 50 1 1 O -X Q0 15 650 950 200 L 50 50 1 1 O -X VCC 16 650 1200 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# AN1186 -# -DEF AN1186 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "AN1186" -50 400 60 H V C CNN -F2 "" -50 400 60 H I C CNN -F3 "" -50 400 60 H I C CNN -DRAW -S -350 350 250 -350 0 1 0 N -X Clk 1 -550 300 200 R 50 50 1 1 I -X rst 2 -550 200 200 R 50 50 1 1 I -X data_in 3 -550 100 200 R 50 50 1 1 I -X q0 4 -550 0 200 R 50 50 1 1 O -X q1 5 -550 -100 200 R 50 50 1 1 O -X q2 6 -550 -200 200 R 50 50 1 1 O -X Gnd 7 -550 -300 200 R 50 50 1 1 I -X q3 8 450 -300 200 L 50 50 1 1 O -X q4 9 450 -200 200 L 50 50 1 1 O -X q5 10 450 -100 200 L 50 50 1 1 O -X q6 11 450 0 200 L 50 50 1 1 O -X q7 12 450 100 200 L 50 50 1 1 O -X NC 13 450 200 200 L 50 50 1 1 I -X Vcc 14 450 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# AN1186_CRC -# -DEF AN1186_CRC U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "AN1186_CRC" -50 400 60 H V C CNN -F2 "" -50 400 60 H I C CNN -F3 "" -50 400 60 H I C CNN -DRAW -S -350 350 250 -350 0 1 0 N -X Clk 1 -550 300 200 R 50 50 1 1 I -X rst 2 -550 200 200 R 50 50 1 1 I -X data_in 3 -550 100 200 R 50 50 1 1 I -X q0 4 -550 0 200 R 50 50 1 1 O -X q1 5 -550 -100 200 R 50 50 1 1 O -X q2 6 -550 -200 200 R 50 50 1 1 O -X Gnd 7 -550 -300 200 R 50 50 1 1 I -X q3 8 450 -300 200 L 50 50 1 1 O -X q4 9 450 -200 200 L 50 50 1 1 O -X q5 10 450 -100 200 L 50 50 1 1 O -X q6 11 450 0 200 L 50 50 1 1 O -X q7 12 450 100 200 L 50 50 1 1 O -X NC 13 450 200 200 L 50 50 1 1 I -X Vcc 14 450 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# AN1186_CRC_Gen -# -DEF AN1186_CRC_Gen X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "AN1186_CRC_Gen" 0 400 60 H V C CNN -F2 "" 0 -100 60 H I C CNN -F3 "" 0 -100 60 H I C CNN -DRAW -S -300 350 250 -400 0 1 0 N -X Clk 1 -500 250 200 R 50 50 1 1 I -X Rst 2 -500 150 200 R 50 50 1 1 I -X Data_in 3 -500 50 200 R 50 50 1 1 I -X q0 4 -500 -50 200 R 50 50 1 1 O -X q1 5 -500 -150 200 R 50 50 1 1 O -X q2 6 -500 -250 200 R 50 50 1 1 O -X Gnd 7 -500 -350 200 R 50 50 1 1 I -X q3 8 450 -350 200 L 50 50 1 1 O -X q4 9 450 -250 200 L 50 50 1 1 O -X q5 10 450 -150 200 L 50 50 1 1 O -X q6 11 450 -50 200 L 50 50 1 1 O -X q7 12 450 50 200 L 50 50 1 1 O -X NC 13 450 150 200 L 50 50 1 1 I -X Vcc 14 450 250 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# Bidirectional_switch -# -DEF Bidirectional_switch X 0 40 Y Y 1 F N -F0 "X" -150 -200 60 H V C CNN -F1 "Bidirectional_switch" 50 0 60 H V C CNN -F2 "" 50 0 60 H I C CNN -F3 "" 50 0 60 H I C CNN -DRAW -P 2 0 1 0 150 -250 500 -250 N -P 3 0 1 0 -400 -250 -100 -250 150 -100 N -X ~ 1 -550 -250 200 R 50 50 1 1 B -X ~ 2 700 -250 200 L 50 50 1 1 B -X ~ 3 -100 -450 200 U 50 50 1 1 B -ENDDRAW -ENDDEF -# -# CBTL02043A -# -DEF CBTL02043A X 0 40 Y Y 1 F N -F0 "X" 1550 750 60 H V C CNN -F1 "CBTL02043A" 1550 850 60 H V C CNN -F2 "" 1550 850 60 H I C CNN -F3 "" 1550 850 60 H I C CNN -DRAW -S 1200 800 1850 -250 0 1 0 N -X Vdd 1 1000 700 200 R 50 50 1 1 I -X XSD 2 1000 600 200 R 50 50 1 1 I -X A0_P 3 1000 500 200 R 50 50 1 1 B -X A0_N 4 1000 400 200 R 50 50 1 1 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E 6 -650 50 200 R 50 50 1 1 I -X Kb 7 -650 -100 200 R 50 50 1 1 I -X VSS 8 -650 -250 200 R 50 50 1 1 I -X Kc 9 600 -250 200 L 50 50 1 1 I -X Ka 10 600 -100 200 L 50 50 1 1 I -X D 11 600 50 200 L 50 50 1 1 I -X C 12 600 200 200 L 50 50 1 1 I -X B 13 600 350 200 L 50 50 1 1 I -X A 14 600 500 200 L 50 50 1 1 I -X Expand 15 600 650 200 L 50 50 1 1 I -X VDD 16 600 800 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# CMOS_NAND -# -DEF CMOS_NAND X 0 40 Y Y 1 F N -F0 "X" -100 -150 60 H V C CNN -F1 "CMOS_NAND" 0 -50 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 -C 550 0 50 0 1 0 N -P 2 0 1 0 -350 300 300 300 N -P 3 0 1 0 -350 300 -350 -400 300 -400 N -X in1 1 -550 250 200 R 50 50 1 1 I -X in2 2 -550 -300 200 R 50 50 1 1 I -X out 3 800 0 279 L 79 79 1 1 I -ENDDRAW -ENDDEF -# -# Clock_pulse_generator -# -DEF Clock_pulse_generator X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "Clock_pulse_generator" 0 -100 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -550 200 600 -300 0 1 0 N -X Vdd 1 -750 100 200 R 50 50 1 1 I -X R 2 -750 -50 200 R 50 50 1 1 I -X C 3 -750 -200 200 R 50 50 1 1 I -X Clkout 4 800 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# DFF -# -DEF DFF X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "DFF" 0 100 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -550 750 550 -500 0 1 0 N -X D 1 -750 550 200 R 50 50 1 1 I -X CLK 2 -750 -250 200 R 50 50 1 1 I -X SET 3 0 950 200 D 50 50 1 1 I -X RESET 4 0 -700 200 U 50 50 1 1 I -X Q 5 750 550 200 L 50 50 1 1 O -X Q_bar 6 750 -250 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC-LM3900 -# -DEF IC-LM3900 X 0 40 Y Y 1 F N -F0 "X" 0 -300 60 H V C CNN -F1 "IC-LM3900" 0 -200 60 H V C CNN -F2 "" 0 -200 60 H I C CNN -F3 "" 0 -200 60 H I C CNN -DRAW -A -1200 -100 150 -899 899 0 0 0 N -1200 -250 -1200 50 -T 0 -550 -500 60 0 0 0 + Normal 0 C C -T 0 -550 50 60 0 0 0 + Normal 0 C C -T 0 750 -300 60 0 0 0 + Normal 0 C C -T 0 750 250 60 0 0 0 + Normal 0 C C -T 0 -550 -250 60 0 0 0 - Normal 0 C C -T 0 -550 300 60 0 0 0 - Normal 0 C C -T 0 750 -500 60 0 0 0 - Normal 0 C C -T 0 750 50 60 0 0 0 - Normal 0 C C -T 0 650 -400 60 0 0 0 1 Normal 0 C C -T 0 -450 -400 60 0 0 0 2 Normal 0 C C -T 0 650 150 60 0 0 0 3 Normal 0 C C -T 0 -450 150 60 0 0 0 4 Normal 0 C C -S -1200 750 1150 -1050 0 0 0 N -P 3 0 0 0 -600 -550 -650 -550 -650 -800 N -P 3 0 0 0 -200 -400 50 -400 50 -800 N -P 3 0 0 0 400 -400 350 -400 350 -800 N -P 3 0 0 0 800 0 950 0 950 500 N -P 5 0 0 0 -600 -250 -800 -250 -800 -700 -300 -700 -300 -800 N -P 5 0 0 0 -600 0 -800 0 -800 400 -300 400 -300 500 N -P 5 0 0 0 -600 300 -700 300 -700 450 50 450 50 500 N -P 5 0 0 0 -200 150 150 150 150 450 350 450 350 500 N -P 5 0 0 0 400 150 250 150 250 400 650 400 650 500 N -P 5 0 0 0 800 -550 900 -550 900 -750 650 -750 650 -800 N -P 5 0 0 0 800 -250 950 -250 950 -650 -950 -650 -950 -800 N -P 6 0 0 0 800 300 1000 300 1000 -100 -1000 -100 -1000 500 -650 500 N -C -600 -400 71 0 1 0 N -C -600 150 71 0 1 0 N -C 800 -400 71 0 1 0 N -C 800 150 71 0 1 0 N -P 4 0 1 0 -650 -350 -600 -450 -550 -350 -650 -350 N -P 4 0 1 0 -650 200 -600 100 -550 200 -650 200 N -P 4 0 1 0 -600 -200 -600 -600 -200 -400 -600 -200 N -P 4 0 1 0 -600 350 -600 -50 -200 150 -600 350 N -P 4 0 1 0 800 -600 800 -200 400 -400 800 -600 N -P 4 0 1 0 800 -50 800 350 400 150 800 -50 N -P 4 0 1 0 850 -450 800 -350 750 -450 850 -450 N -P 4 0 1 0 850 100 800 200 750 100 850 100 N -X IN1+ 1 -950 -1250 200 U 50 50 1 1 I -X IN2+ 2 -650 -1250 200 U 50 50 1 1 I -X IN2- 3 -300 -1250 200 U 50 50 1 1 I -X OUT2 4 50 -1250 200 U 50 50 1 1 O -X OUT1 5 350 -1250 200 U 50 50 1 1 O -X IN1- 6 650 -1250 200 U 50 50 1 1 I -X GND 7 950 -1250 200 U 50 50 1 1 I -X IN3- 8 950 950 200 D 50 50 1 1 I -X OUT3 9 650 950 200 D 50 50 1 1 O -X OUT4 10 350 950 200 D 50 50 1 1 O -X IN4- 11 50 950 200 D 50 50 1 1 I -X IN4+ 12 -300 950 200 D 50 50 1 1 I -X IN3+ 13 -650 950 200 D 50 50 1 1 I -X VCC 14 -950 950 200 D 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4002 -# -DEF IC_4002 X 0 40 Y Y 1 F N -F0 "X" 0 150 60 H V C CNN -F1 "IC_4002" 0 0 60 H V C CNN -F2 "" 50 -150 60 H V C CNN -F3 "" 50 -150 60 H V C CNN -DRAW -S -250 350 250 -400 0 1 0 N -X 1Y 1 -450 250 200 R 50 50 1 1 O -X 1A 2 -450 150 200 R 50 50 1 1 I -X 1B 3 -450 50 200 R 50 50 1 1 I -X 1C 4 -450 -50 200 R 50 50 1 1 I -X 1D 5 -450 -150 200 R 50 50 1 1 I -X NC 6 -450 -250 200 R 50 50 1 1 I -X GND 7 -450 -350 200 R 50 50 1 1 I -X NC 8 450 -350 200 L 50 50 1 1 I -X 2A 9 450 -250 200 L 50 50 1 1 I -X 2B 10 450 -150 200 L 50 50 1 1 I -X 2C 11 450 -50 200 L 50 50 1 1 I -X 2D 12 450 50 200 L 50 50 1 1 I -X 2Y 13 450 150 200 L 50 50 1 1 O -X VCC 14 450 250 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4012 -# -DEF IC_4012 X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "IC_4012" 0 200 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 400 350 -400 0 1 0 N -X Q1 1 -500 300 200 R 50 50 1 1 O -X A1 2 -500 200 200 R 50 50 1 1 I -X B1 3 -500 100 200 R 50 50 1 1 I -X C1 4 -500 0 200 R 50 50 1 1 I -X D1 5 -500 -100 200 R 50 50 1 1 I -X NC 6 -500 -200 200 R 50 50 1 1 N -X VSS 7 -500 -300 200 R 50 50 1 1 I -X NC 8 550 -300 200 L 50 50 1 1 N -X A2 9 550 -200 200 L 50 50 1 1 I -X B2 10 550 -100 200 L 50 50 1 1 I -X C2 11 550 0 200 L 50 50 1 1 I -X D2 12 550 100 200 L 50 50 1 1 I -X Q2 13 550 200 200 L 50 50 1 1 O -X VDD 14 550 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4017 -# -DEF IC_4017 X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "IC_4017" 0 0 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -350 850 400 -850 0 1 0 N -X 1 1 600 650 200 L 50 50 1 1 O -X 2 2 600 500 200 L 50 50 1 1 O -X 3 3 600 350 200 L 50 50 1 1 O -X 4 4 600 200 200 L 50 50 1 1 O -X 5 5 600 50 200 L 50 50 1 1 O -X 6 6 600 -100 200 L 50 50 1 1 O -X 7 7 600 -250 200 L 50 50 1 1 O -X 8 8 600 -400 200 L 50 50 1 1 O -X 9 9 600 -600 200 L 50 50 1 1 O -X 10 10 600 -750 200 L 50 50 1 1 O -X RST 11 -550 -400 200 R 50 50 1 1 I -X CLK 12 -550 350 200 R 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4023 -# -DEF IC_4023 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "IC_4023" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 450 300 -450 0 1 0 N -X A1 1 -500 300 200 R 50 50 1 1 I -X B1 2 -500 200 200 R 50 50 1 1 I -X A2 3 -500 100 200 R 50 50 1 1 I -X B2 4 -500 0 200 R 50 50 1 1 I -X C2 5 -500 -100 200 R 50 50 1 1 I -X Q2 6 -500 -200 200 R 50 50 1 1 O -X Vss 7 -500 -300 200 R 50 50 1 1 I -X C1 8 500 -300 200 L 50 50 1 1 I -X Q1 9 500 -200 200 L 50 50 1 1 O -X Q3 10 500 -100 200 L 50 50 1 1 O -X C3 11 500 0 200 L 50 50 1 1 I -X B3 12 500 100 200 L 50 50 1 1 I -X A3 13 500 200 200 L 50 50 1 1 I -X Vdd 14 500 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4028 -# -DEF IC_4028 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "IC_4028" 0 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 450 300 -450 0 1 0 N -X Q4 1 -500 350 200 R 50 50 1 1 O -X Q2 2 -500 250 200 R 50 50 1 1 O -X Q0 3 -500 150 200 R 50 50 1 1 O -X Q7 4 -500 50 200 R 50 50 1 1 O -X Q9 5 -500 -50 200 R 50 50 1 1 O -X Q5 6 -500 -150 200 R 50 50 1 1 O -X Q6 7 -500 -250 200 R 50 50 1 1 O -X Vss 8 -500 -350 200 R 50 50 1 1 I -X Q8 9 500 -350 200 L 50 50 1 1 O -X A0 10 500 -250 200 L 50 50 1 1 I -X A3 11 500 -150 200 L 50 50 1 1 I -X A2 12 500 -50 200 L 50 50 1 1 I -X A1 13 500 50 200 L 50 50 1 1 I -X Q1 14 500 150 200 L 50 50 1 1 O -X Q3 15 500 250 200 L 50 50 1 1 O -X Vdd 16 500 350 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC_4073 -# -DEF IC_4073 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "IC_4073" 0 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 400 300 -400 0 1 0 N -X A1 1 -500 300 200 R 50 50 1 1 I -X B1 2 -500 200 200 R 50 50 1 1 I -X A2 3 -500 100 200 R 50 50 1 1 I -X B2 4 -500 0 200 R 50 50 1 1 I -X C2 5 -500 -100 200 R 50 50 1 1 I -X Q2 6 -500 -200 200 R 50 50 1 1 O -X Vss 7 -500 -300 200 R 50 50 1 1 I -X C1 8 500 -300 200 L 50 50 1 1 I -X Q1 9 500 -200 200 L 50 50 1 1 O -X Q3 10 500 -100 200 L 50 50 1 1 O -X A3 11 500 0 200 L 50 50 1 1 I -X B3 12 500 100 200 L 50 50 1 1 I -X C3 13 500 200 200 L 50 50 1 1 I -X Vdd 14 500 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_74153 -# -DEF IC_74153 X 0 40 Y Y 1 F N -F0 "X" 100 50 60 H V C CNN -F1 "IC_74153" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -T 0 100 -200 60 0 0 0 4:1 Normal 0 C C -T 0 100 -100 60 0 0 0 DUAL Normal 0 C C -T 0 100 -300 60 0 0 0 MUX Normal 0 C C -S -200 500 350 -550 0 1 0 N -X a0 1 -400 350 200 R 50 50 1 1 I -X a1 2 -400 250 200 R 50 50 1 1 I -X a2 3 -400 150 200 R 50 50 1 1 I -X a3 4 -400 50 200 R 50 50 1 1 I -X EA 5 0 700 200 D 50 50 1 1 I I -X b0 6 -400 -150 200 R 50 50 1 1 I -X b1 7 -400 -250 200 R 50 50 1 1 I -X b2 8 -400 -350 200 R 50 50 1 1 I -X b3 9 -400 -450 200 R 50 50 1 1 I -X EB 10 200 700 200 D 50 50 1 1 I I -X s1 11 50 -750 200 U 50 50 1 1 I -X s0 12 150 -750 200 U 50 50 1 1 I -X ya 13 550 250 200 L 50 50 1 1 O -X yb 14 550 -300 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC_74154 -# -DEF IC_74154 X 0 40 Y Y 1 F N -F0 "X" 0 -200 60 H V C CNN -F1 "IC_74154" 50 -50 60 H V C CNN -F2 "" 0 50 60 H V C CNN -F3 "" 0 50 60 H V C CNN -DRAW -T 0 0 400 60 0 0 0 4:16~ Normal 0 C C -T 0 0 250 60 0 0 0 decoder Normal 0 C C -S -350 700 400 -700 0 0 0 N -X ~Y0 1 -550 550 200 R 50 50 1 1 O I -X ~Y1 2 -550 450 200 R 50 50 1 1 O I -X ~Y2 3 -550 350 200 R 50 50 1 1 O I -X ~Y3 4 -550 250 200 R 50 50 1 1 O I -X ~Y4 5 -550 150 200 R 50 50 1 1 O I -X ~Y5 6 -550 50 200 R 50 50 1 1 O I -X ~Y6 7 -550 -50 200 R 50 50 1 1 O I -X ~Y7 8 -550 -150 200 R 50 50 1 1 O I -X ~Y8 9 -550 -250 200 R 50 50 1 1 O I -X ~Y9 10 -550 -350 200 R 50 50 1 1 O I -X A3 20 600 150 200 L 50 50 1 1 I -X ~Y10 11 -550 -450 200 R 50 50 1 1 O I -X A2 21 600 250 200 L 50 50 1 1 I -X GND 12 -550 -550 200 R 50 50 1 1 I -X A1 22 600 350 200 L 50 50 1 1 I -X ~Y11 13 600 -550 200 L 50 50 1 1 O I -X A0 23 600 450 200 L 50 50 1 1 I -X ~Y12 14 600 -450 200 L 50 50 1 1 O I -X Vcc 24 600 550 200 L 50 50 1 1 I -X ~Y13 15 600 -350 200 L 50 50 1 1 O I -X ~Y14 16 600 -250 200 L 50 50 1 1 O I -X ~Y15 17 600 -150 200 L 50 50 1 1 O I -X ~E0 18 600 -50 200 L 50 50 1 1 I I -X ~E1 19 600 50 200 L 50 50 1 1 I I -ENDDRAW -ENDDEF -# -# IC_74157 -# -DEF IC_74157 X 0 40 Y Y 1 F N -F0 "X" 50 -50 60 H V C CNN -F1 "IC_74157" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -T 0 50 -300 60 0 0 0 2:1 Normal 0 C C -T 0 50 -400 60 0 0 0 MUX Normal 0 C C -T 0 50 -200 60 0 0 0 QUAD Normal 0 C C -S -350 550 400 -650 0 1 0 N -X a0 1 -550 450 200 R 50 50 1 1 I -X a1 2 -550 300 200 R 50 50 1 1 I -X b0 3 -550 200 200 R 50 50 1 1 I -X b1 4 -550 100 200 R 50 50 1 1 I -X c0 5 -550 0 200 R 50 50 1 1 I -X c1 6 -550 -100 200 R 50 50 1 1 I -X d0 7 -550 -200 200 R 50 50 1 1 I -X d1 8 -550 -300 200 R 50 50 1 1 I -X EN 9 -550 -550 200 R 50 50 1 1 I I -X S 10 -550 -450 200 R 50 50 1 1 I -X Yd 11 600 0 200 L 50 50 1 1 O -X Ya 12 600 300 200 L 50 50 1 1 O -X Yb 13 600 200 200 L 50 50 1 1 O -X Yc 14 600 100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC_7485 -# -DEF IC_7485 X 0 40 Y Y 1 F N -F0 "X" -50 -100 60 H V C CNN -F1 "IC_7485" -50 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C -S -350 450 400 -400 0 1 0 N -X AB(in) 3 600 -300 200 L 50 50 1 1 I -X A3 4 -550 100 200 R 50 50 1 1 I -X B3 5 -550 -350 200 R 50 50 1 1 I -X A2 6 -550 200 200 R 50 50 1 1 I -X B2 7 -550 -250 200 R 50 50 1 1 I -X A1 8 -550 300 200 R 50 50 1 1 I -X B1 9 -550 -150 200 R 50 50 1 1 I -X A0 10 -550 400 200 R 50 50 1 1 I -X B0 11 -550 -50 200 R 50 50 1 1 I -X A>B(out) 12 600 350 200 L 50 50 1 1 O -X A=B(out) 13 600 250 200 L 50 50 1 1 O -X AB(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A