diff --git a/drivers/gpu/drm/panel/panel-sharp-y030xx067a.c b/drivers/gpu/drm/panel/panel-sharp-y030xx067a.c
index b636183302d79f..4577431af1a4c9 100644
--- a/drivers/gpu/drm/panel/panel-sharp-y030xx067a.c
+++ b/drivers/gpu/drm/panel/panel-sharp-y030xx067a.c
@@ -5,6 +5,7 @@
  * Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
  */
 
+#include <linux/bitfield.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/gpio/consumer.h>
@@ -18,7 +19,96 @@
 #include <drm/drm_modes.h>
 #include <drm/drm_panel.h>
 
-#include <video/mipi_display.h>
+#define REG00_VBRT_CTRL(val)		(val)
+
+#define REG01_COM_DC(val)		(val)
+
+#define REG02_DA_CONTRAST(val)		(val)
+#define REG02_VESA_SEL(val)		((val) << 5)
+#define REG02_COMDC_SW			BIT(7)
+
+#define REG03_VPOSITION(val)		(val)
+#define REG03_BSMOUNT			BIT(5)
+#define REG03_COMTST			BIT(6)
+#define REG03_HPOSITION1		BIT(7)
+
+#define REG04_HPOSITION1(val)		(val)
+
+#define REG05_CLIP			BIT(0)
+#define REG05_NVM_VREFRESH		BIT(1)
+#define REG05_SLFR			BIT(2)
+#define REG05_SLBRCHARGE(val)		((val) << 3)
+#define REG05_PRECHARGE_LEVEL(val)	((val) << 6)
+
+#define REG06_TEST5			BIT(0)
+#define REG06_SLDWN			BIT(1)
+#define REG06_SLRGT			BIT(2)
+#define REG06_TEST2			BIT(3)
+#define REG06_XPSAVE			BIT(4)
+#define REG06_GAMMA_SEL(val)		((val) << 5)
+#define REG06_NT			BIT(7)
+
+#define REG07_TEST1			BIT(0)
+#define REG07_HDVD_POL			BIT(1)
+#define REG07_CK_POL			BIT(2)
+#define REG07_TEST3			BIT(3)
+#define REG07_TEST4			BIT(4)
+#define REG07_480_LINEMASK		BIT(5)
+#define REG07_AMPTST(val)		((val) << 6)
+
+#define REG08_SLHRC(val)		(val)
+#define REG08_CLOCK_DIV(val)		((val) << 2)
+#define REG08_PANEL(val)		((val) << 5)
+
+#define REG09_SUB_BRIGHT_R(val)		(val)
+#define REG09_NW_NB			BIT(6)
+#define REG09_IPCON			BIT(7)
+
+#define REG0A_SUB_BRIGHT_B(val)		(val)
+#define REG0A_PAIR			BIT(6)
+#define REG0A_DE_SEL			BIT(7)
+
+#define REG0B_MBK_POSITION(val)		(val)
+#define REG0B_HD_FREERUN		BIT(4)
+#define REG0B_VD_FREERUN		BIT(5)
+#define REG0B_YUV2BIN(val)		((val) << 6)
+
+#define REG0C_CONTRAST_R(val)		(val)
+#define REG0C_DOUBLEREAD		BIT(7)
+
+#define REG0D_CONTRAST_G(val)		(val)
+#define REG0D_RGB_YUV			BIT(7)
+
+#define REG0E_CONTRAST_B(val)		(val)
+#define REG0E_PIXELCOLORWIRE		BIT(7)
+
+#define REG0F_ASPECT			BIT(0)
+#define REG0F_OVERSCAN(val)		((val) << 1)
+#define REG0F_FRAMEWIDTH(val)		((val) << 3)
+
+#define REG10_BRIGHT(val)		(val)
+
+#define REG11_SIG_GAIN(val)		(val)
+#define REG11_SIGC_CNTL			BIT(6)
+#define REG11_SIGC_POL			BIT(7)
+
+#define REG12_COLOR(val)		(val)
+#define REG12_PWCKSEL(val)		((val) << 6)
+
+#define REG13_4096LEVEL_CNTL(val)	(val)
+#define REG13_SL4096(val)		((val) << 4)
+#define REG13_LIMITER_CONTROL		BIT(7)
+
+#define REG14_PANEL_TEST(val)		(val)
+
+#define REG15_NVM_LINK0			BIT(0)
+#define REG15_NVM_LINK1			BIT(1)
+#define REG15_NVM_LINK2			BIT(2)
+#define REG15_NVM_LINK3			BIT(3)
+#define REG15_NVM_LINK4			BIT(4)
+#define REG15_NVM_LINK5			BIT(5)
+#define REG15_NVM_LINK6			BIT(6)
+#define REG15_NVM_LINK7			BIT(7)
 
 struct y030xx067a_info {
 	const struct drm_display_mode *display_modes;
@@ -44,18 +134,19 @@ static inline struct y030xx067a *to_y030xx067a(struct drm_panel *panel)
 }
 
 static const struct reg_sequence y030xx067a_init_sequence[] = {
-	{ 0x02, 0x7f, },
-	{ 0x03, 0x0a, },
-	{ 0x04, 0x80, },
-	{ 0x06, 0x90, },
-	{ 0x08, 0x28, },
-	{ 0x09, 0x20, },
-	{ 0x0a, 0x20, },
-	{ 0x0c, 0x10, },
-	{ 0x0d, 0x10, },
-	{ 0x0e, 0x90, },
-	{ 0x10, 0x7f, },
-	{ 0x11, 0x3f, },
+	{ 0x00, REG00_VBRT_CTRL(0x7f) },	
+	{ 0x02, REG02_DA_CONTRAST(0x1f) },
+	{ 0x03, REG03_VPOSITION(0x0a) },
+	{ 0x04, REG04_HPOSITION1(0xd1) },
+	{ 0x06, REG06_XPSAVE | REG06_NT },
+	{ 0x08, REG08_PANEL(0x1) | REG08_CLOCK_DIV(0x2) },
+	{ 0x09, REG09_SUB_BRIGHT_R(0x20) },
+	{ 0x0a, REG0A_SUB_BRIGHT_B(0x20) },
+	{ 0x0c, REG0C_CONTRAST_R(0x10) },
+	{ 0x0d, REG0D_CONTRAST_G(0x10) },
+	{ 0x0e, REG0E_CONTRAST_B(0x10) | REG0E_PIXELCOLORWIRE },
+	{ 0x10, REG10_BRIGHT(0x80) },
+	{ 0x11, REG11_SIG_GAIN(0x3f) },
 };
 
 static int y030xx067a_prepare(struct drm_panel *panel)
@@ -123,7 +214,7 @@ static int y030xx067a_get_modes(struct drm_panel *panel,
 		drm_mode_probed_add(connector, mode);
 	}
 
-	connector->display_info.bpc = 6;
+	connector->display_info.bpc = 8;
 	connector->display_info.width_mm = panel_info->width_mm;
 	connector->display_info.height_mm = panel_info->height_mm;
 
@@ -212,14 +303,14 @@ static const struct drm_display_mode y030xx067a_modes[] = {
 	{
 		.clock = 54000,
 		.hdisplay = 320,
-		.hsync_start = 320 + 128,
-		.hsync_end = 320 + 128 + 28,
-		.htotal = 320 + 128 + 28 + 25,
+		.hsync_start = 320 + 90,
+		.hsync_end = 320 + 90 + 37,
+		.htotal = 320 + 90 + 37 + 33,
 		.vdisplay = 480,
-		.vsync_start = 480 + 36,
-		.vsync_end = 480 + 36 + 1,
-		.vtotal = 480 + 36 + 1 + 16,
-		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+		.vsync_start = 480 + 109,
+		.vsync_end = 480 + 109 + 20,
+		.vtotal = 480 + 109 + 20 + 16,
+		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 	},
 };
 
@@ -228,8 +319,8 @@ static const struct y030xx067a_info y030xx067a_info = {
 	.num_modes = ARRAY_SIZE(y030xx067a_modes),
 	.width_mm = 69,
 	.height_mm = 51,
-	.bus_format = MEDIA_BUS_FMT_RGB565_2X8_LE,
-	.bus_flags = 0,
+	.bus_format = MEDIA_BUS_FMT_RGB888_3X8,
+	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | DRM_BUS_FLAG_DE_LOW,
 };
 
 static const struct of_device_id y030xx067a_of_match[] = {