From f9db48dbf17221eda4e84585aaae4376ec76ce52 Mon Sep 17 00:00:00 2001 From: Ian Seyler Date: Sun, 23 Feb 2025 15:30:11 -0500 Subject: [PATCH 1/3] Remove interrupts via PIC --- src/init/pic.asm | 81 ------------------------------------------------ src/init/smp.asm | 8 ----- src/pure64.asm | 29 ++++++++++++----- 3 files changed, 22 insertions(+), 96 deletions(-) delete mode 100644 src/init/pic.asm diff --git a/src/init/pic.asm b/src/init/pic.asm deleted file mode 100644 index 243a63b..0000000 --- a/src/init/pic.asm +++ /dev/null @@ -1,81 +0,0 @@ -; ============================================================================= -; Pure64 -- a 64-bit OS/software loader written in Assembly for x86-64 systems -; Copyright (C) 2008-2025 Return Infinity -- see LICENSE.TXT -; -; INIT PIC -; ============================================================================= - - -init_pic: - ; Initialize and remap PIC IRQ's - ; ICW1 - mov al, 0x11; ; Initialize PIC 1, init (bit 4) and ICW4 (bit 0) - out 0x20, al - mov al, 0x11; ; Initialize PIC 2, init (bit 4) and ICW4 (bit 0) - out 0xA0, al - ; ICW2 - mov al, 0x20 ; IRQ 0-7: interrupts 20h-27h - out 0x21, al - mov al, 0x28 ; IRQ 8-15: interrupts 28h-2Fh - out 0xA1, al - ; ICW3 - mov al, 4 - out 0x21, al - mov al, 2 - out 0xA1, al - ; ICW4 - mov al, 1 - out 0x21, al - mov al, 1 - out 0xA1, al - - ; Set up RTC -rtc_poll: - mov al, 0x0A ; Status Register A - out 0x70, al ; Select the address - in al, 0x71 ; Read the data - test al, 0x80 ; Is there an update in process? - jne rtc_poll ; If so then keep polling - mov al, 0x0A ; Status Register A - out 0x70, al ; Select the address - mov al, 00100110b ; UIP (0), RTC@32.768KHz (010), Rate@1024Hz (0110) - out 0x71, al ; Write the data - mov al, 0x0B ; Status Register B - out 0x70, al ; Select the address - in al, 0x71 ; Read the current settings - push rax ; Save the current Register B settings - mov al, 0x0B ; Status Register B - out 0x70, al ; Select the address - pop rax ; Restore the Register B settings to AL - bts ax, 6 ; Set Periodic Interrupt Enable (bit 6) - out 0x71, al ; Write the new settings - - ; Enable specific interrupt - in al, 0x21 - mov al, 11111011b ; Enable Cascade (HPET Timer 0) - out 0x21, al - - sti ; Enable interrupts - - ; Acknowledge the RTC - mov al, 0x0C ; Status Register C - out 0x70, al ; Select the address - in al, 0x71 ; Read the value to clear any existing interrupt value - - ; Enable PIT - ; Base rate is 1193182 Hz - mov al, 0x36 ; Channel 0 (7:6), Access Mode lo/hi (5:4), Mode 3 (3:1), Binary (0) - out 0x43, al - mov al, 0x3C ; 60 - out 0x40, al ; Set low byte of PIT reload value - mov al, 0x00 - out 0x40, al ; Set high byte of PIT reload value - ; New rate is 19866 Hz (1193182 / 60) - ; 0.050286633812733 milliseconds (ms) - ; 50.28663381273300814 microseconds (us) - - ret - - -; ============================================================================= -; EOF diff --git a/src/init/smp.asm b/src/init/smp.asm index 8e3abf1..47f626a 100644 --- a/src/init/smp.asm +++ b/src/init/smp.asm @@ -109,14 +109,6 @@ noMP: div rcx mov [p_cpu_speed], ax - cli ; Disable Interrupts - - ; Disable PIT - mov al, 0x30 ; Channel 0 (7:6), Access Mode lo/hi (5:4), Mode 0 (3:1), Binary (0) - out 0x43, al - mov al, 0x00 - out 0x40, al - ret diff --git a/src/pure64.asm b/src/pure64.asm index 30d285f..8cd18d2 100644 --- a/src/pure64.asm +++ b/src/pure64.asm @@ -208,6 +208,28 @@ start64: out 0x21, al out 0xA1, al + ; Initialize and remap PIC IRQ's + ; ICW1 + mov al, 0x11; ; Initialize PIC 1, init (bit 4) and ICW4 (bit 0) + out 0x20, al + mov al, 0x11; ; Initialize PIC 2, init (bit 4) and ICW4 (bit 0) + out 0xA0, al + ; ICW2 + mov al, 0x20 ; IRQ 0-7: interrupts 20h-27h + out 0x21, al + mov al, 0x28 ; IRQ 8-15: interrupts 28h-2Fh + out 0xA1, al + ; ICW3 + mov al, 4 + out 0x21, al + mov al, 2 + out 0xA1, al + ; ICW4 + mov al, 1 + out 0x21, al + mov al, 1 + out 0xA1, al + ; Disable NMIs in al, 0x70 or al, 0x80 @@ -723,12 +745,6 @@ pde_end: mov ebx, 4 call debug_block - mov rsi, msg_pic - call debug_msg - call init_pic ; Configure the PIC(s), activate interrupts - mov rsi, msg_ok - call debug_msg - mov rsi, msg_smp call debug_msg call init_smp ; Init of SMP, deactivate interrupts @@ -883,7 +899,6 @@ clear_regs: %include "init/acpi.asm" %include "init/cpu.asm" -%include "init/pic.asm" %include "init/serial.asm" %include "init/hpet.asm" %include "init/smp.asm" From a0f1824468c149bc173647dd66b7e676fe100c61 Mon Sep 17 00:00:00 2001 From: Ian Seyler Date: Sun, 23 Feb 2025 15:35:51 -0500 Subject: [PATCH 2/3] Cleanup --- src/init/smp_ap.asm | 33 ++++++++++++--------------------- src/sysvar.asm | 1 - 2 files changed, 12 insertions(+), 22 deletions(-) diff --git a/src/init/smp_ap.asm b/src/init/smp_ap.asm index 4d57e02..ef5b414 100644 --- a/src/init/smp_ap.asm +++ b/src/init/smp_ap.asm @@ -10,7 +10,7 @@ BITS 16 init_smp_ap: -; Enable the A20 gate + ; Enable the A20 gate set_A20_ap: in al, 0x64 test al, 0x02 @@ -24,10 +24,10 @@ check_A20_ap: mov al, 0xDF out 0x60, al -; At this point we are done with real mode and BIOS interrupts. Jump to 32-bit mode. - lgdt [cs:GDTR32] ; load GDT register + ; At this point we are done with real mode and BIOS interrupts. Jump to 32-bit mode. + lgdt [cs:GDTR32] ; Load GDT register - mov eax, cr0 ; switch to 32-bit protected mode + mov eax, cr0 ; Switch to 32-bit protected mode or al, 1 mov cr0, eax @@ -41,7 +41,7 @@ align 16 BITS 32 startap32: - mov eax, 16 ; load 4 GB data descriptor + mov eax, 16 ; Load 4 GB data descriptor mov ds, ax ; to all data segment registers mov es, ax mov fs, ax @@ -56,30 +56,30 @@ startap32: xor ebp, ebp mov esp, 0x7000 ; Set a known free location for the temporary stack (shared by all APs) -; Load the GDT + ; Load the GDT lgdt [GDTR64] -; Enable extended properties + ; Enable extended properties mov eax, cr4 or eax, 0x0000000B0 ; PGE (Bit 7), PAE (Bit 5), and PSE (Bit 4) mov cr4, eax -; Point cr3 at PML4 + ; Point cr3 at PML4 mov eax, 0x00002008 ; Write-thru (Bit 3) mov cr3, eax -; Enable long mode and SYSCALL/SYSRET + ; Enable long mode and SYSCALL/SYSRET mov ecx, 0xC0000080 ; EFER MSR number rdmsr ; Read EFER or eax, 0x00000101 ; LME (Bit 8) wrmsr ; Write EFER -; Enable paging to activate long mode + ; Enable paging to activate long mode mov eax, cr0 or eax, 0x80000000 ; PG (Bit 31) mov cr0, eax -; Make the jump directly from 16-bit real mode to 64-bit long mode + ; Make the jump directly from 16-bit real mode to 64-bit long mode jmp SYS64_CODE_SEL:startap64 align 16 @@ -124,22 +124,13 @@ startap64: mov rsp, rax ; Pure64 leaves 0x50000-0x9FFFF free so we use that lgdt [GDTR64] ; Load the GDT - lidt [IDTR64] ; load IDT register - -; Enable Local APIC on AP -; mov rsi, [p_LocalAPICAddress] -; add rsi, 0x00f0 ; Offset to Spurious Interrupt Register -; mov rdi, rsi -; lodsd -; or eax, 0000000100000000b -; stosd + lidt [IDTR64] ; Load the IDT call init_cpu ; Setup CPU sti ; Activate interrupts for SMP jmp ap_sleep - align 16 ap_sleep: diff --git a/src/sysvar.asm b/src/sysvar.asm index 8cb3c1f..9800342 100644 --- a/src/sysvar.asm +++ b/src/sysvar.asm @@ -17,7 +17,6 @@ msg_bios: db 'bios', 0 msg_uefi: db 'uefi', 0 msg_acpi: db 13, 10, 'acpi ', 0 msg_bsp: db 13, 10, 'bsp ', 0 -msg_pic: db 13, 10, 'pic ', 0 msg_smp: db 13, 10, 'smp ', 0 msg_kernel: db 13, 10, 'kernel start', 13, 10, 0 From 37fcc9bee6c5d753534d68bc938522592ff60c56 Mon Sep 17 00:00:00 2001 From: Ian Seyler Date: Sun, 23 Feb 2025 15:37:46 -0500 Subject: [PATCH 3/3] Cleanup --- src/init/cpu.asm | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/init/cpu.asm b/src/init/cpu.asm index f194de4..433fdda 100644 --- a/src/init/cpu.asm +++ b/src/init/cpu.asm @@ -8,16 +8,16 @@ init_cpu: -; Disable Cache + ; Disable Cache mov rax, cr0 btr rax, 29 ; Clear No Write Thru (Bit 29) bts rax, 30 ; Set Cache Disable (Bit 30) mov cr0, rax -; Flush Cache + ; Flush Cache wbinvd -; Flush TLB + ; Flush TLB mov rax, cr3 mov cr3, rax @@ -108,35 +108,35 @@ init_cpu: ; bts eax, 11 ; Set MTRR Enable (Bit 11), Only enables Variable Range MTRR's ; wrmsr -; Flush TLB + ; Flush TLB mov rax, cr3 mov cr3, rax -; Flush Cache + ; Flush Cache wbinvd -; Enable Cache + ; Enable Cache mov rax, cr0 btr rax, 29 ; Clear No Write Thru (Bit 29) btr rax, 30 ; Clear CD (Bit 30) mov cr0, rax -; Enable Floating Point + ; Enable Floating Point mov rax, cr0 bts rax, 1 ; Set Monitor co-processor (Bit 1) btr rax, 2 ; Clear Emulation (Bit 2) mov cr0, rax -; Enable SSE + ; Enable SSE mov rax, cr4 bts rax, 9 ; Set Operating System Support for FXSAVE and FXSTOR instructions (Bit 9) bts rax, 10 ; Set Operating System Support for Unmasked SIMD Floating-Point Exceptions (Bit 10) mov cr4, rax -; Enable Math Co-processor + ; Enable Math Co-processor finit -; Enable AVX-1 and AVX-2 + ; Enable AVX-1 and AVX-2 mov eax, 1 ; CPUID Feature information 1 cpuid ; Sets info in ECX and EDX bt ecx, 28 ; AVX-1 is supported if bit 28 is set in ECX @@ -154,7 +154,7 @@ avx_supported: xsetbv ; Save XCR0 register avx_not_supported: -; Enable AVX-512 + ; Enable AVX-512 mov eax, 7 ; CPUID Feature information 7 xor ecx, ecx ; Extended Features 0 cpuid ; Sets info in EBX, ECX, and EDX