From 8e8ab0cd7e60a1122be01c572f72e625f5d4a2a1 Mon Sep 17 00:00:00 2001 From: Adeel Mujahid <3840695+am11@users.noreply.github.com> Date: Tue, 21 Mar 2023 02:03:59 +0200 Subject: [PATCH 01/20] Remove calling convention modifiers from cpuid sig (#83672) > /runtime/src/coreclr/vm/cgensys.h:107:26: error: stdcall calling convention is not supported on builtin function [-Werror,-Wignored-attributes] --- src/coreclr/vm/cgensys.h | 8 ++++---- src/coreclr/vm/i386/cgenx86.cpp | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/coreclr/vm/cgensys.h b/src/coreclr/vm/cgensys.h index 760827ccfb8b4e..75f266be916023 100644 --- a/src/coreclr/vm/cgensys.h +++ b/src/coreclr/vm/cgensys.h @@ -97,11 +97,11 @@ inline void GetSpecificCpuInfo(CORINFO_CPU * cpuInfo) // MSVC directly defines intrinsics for __cpuid and __cpuidex matching the below signatures // We define matching signatures for use on Unix platforms. -extern "C" void __stdcall __cpuid(int cpuInfo[4], int function_id); -extern "C" void __stdcall __cpuidex(int cpuInfo[4], int function_id, int subFunction_id); +extern "C" void __cpuid(int cpuInfo[4], int function_id); +extern "C" void __cpuidex(int cpuInfo[4], int function_id, int subFunction_id); #endif // TARGET_UNIX -extern "C" DWORD __stdcall xmmYmmStateSupport(); -extern "C" DWORD __stdcall avx512StateSupport(); +extern "C" DWORD xmmYmmStateSupport(); +extern "C" DWORD avx512StateSupport(); #endif inline bool TargetHasAVXSupport() diff --git a/src/coreclr/vm/i386/cgenx86.cpp b/src/coreclr/vm/i386/cgenx86.cpp index 4e958a44b30d51..020593b8735361 100644 --- a/src/coreclr/vm/i386/cgenx86.cpp +++ b/src/coreclr/vm/i386/cgenx86.cpp @@ -1084,7 +1084,7 @@ void ResumeAtJit(PCONTEXT pContext, LPVOID oldESP) #ifndef TARGET_UNIX #pragma warning(push) #pragma warning(disable: 4035) -extern "C" DWORD __stdcall xmmYmmStateSupport() +extern "C" DWORD xmmYmmStateSupport() { // No CONTRACT STATIC_CONTRACT_NOTHROW; @@ -1108,7 +1108,7 @@ extern "C" DWORD __stdcall xmmYmmStateSupport() #pragma warning(push) #pragma warning(disable: 4035) -extern "C" DWORD __stdcall avx512StateSupport() +extern "C" DWORD avx512StateSupport() { // No CONTRACT STATIC_CONTRACT_NOTHROW; @@ -1159,7 +1159,7 @@ void __cpuidex(int cpuInfo[4], int function_id, int subFunction_id) } #endif -extern "C" DWORD __stdcall xmmYmmStateSupport() +extern "C" DWORD xmmYmmStateSupport() { DWORD eax; __asm(" xgetbv\n" \ @@ -1171,7 +1171,7 @@ extern "C" DWORD __stdcall xmmYmmStateSupport() return ((eax & 0x06) == 0x06) ? 1 : 0; } -extern "C" DWORD __stdcall avx512StateSupport() +extern "C" DWORD avx512StateSupport() { DWORD eax; __asm(" xgetbv\n" \ From 0b03ca623899c29cc8ad12ca36b3087c2a35d812 Mon Sep 17 00:00:00 2001 From: Charles Stoner <10732005+cston@users.noreply.github.com> Date: Mon, 20 Mar 2023 17:08:42 -0700 Subject: [PATCH 02/20] SyntaxValueProvider: avoid performance issue with syntax list containing many items (#83483) --- ...alueProvider_ForAttributeWithSimpleName.cs | 11 +++++- .../LoggerMessageGeneratorParserTests.cs | 34 +++++++++++++++++++ 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/src/libraries/Common/src/Roslyn/SyntaxValueProvider_ForAttributeWithSimpleName.cs b/src/libraries/Common/src/Roslyn/SyntaxValueProvider_ForAttributeWithSimpleName.cs index 53c718404b30d5..f26f63b6b2d2de 100644 --- a/src/libraries/Common/src/Roslyn/SyntaxValueProvider_ForAttributeWithSimpleName.cs +++ b/src/libraries/Common/src/Roslyn/SyntaxValueProvider_ForAttributeWithSimpleName.cs @@ -334,7 +334,16 @@ void processMember( // For any other node, just keep recursing deeper to see if we can find an attribute. Note: we cannot // terminate the search anywhere as attributes may be found on things like local functions, and that // means having to dive deep into statements and expressions. - foreach (var child in node.ChildNodesAndTokens().Reverse()) + var childNodesAndTokens = node.ChildNodesAndTokens(); + + // Avoid performance issue in ChildSyntaxList when iterating the child list in reverse + // (see https://github.com/dotnet/roslyn/issues/66475) by iterating forward first to + // ensure child nodes are realized. + foreach (var childNode in childNodesAndTokens) + { + } + + foreach (var child in childNodesAndTokens.Reverse()) { if (child.IsNode) nodeStack.Append(child.AsNode()!); diff --git a/src/libraries/Microsoft.Extensions.Logging.Abstractions/tests/Microsoft.Extensions.Logging.Generators.Tests/LoggerMessageGeneratorParserTests.cs b/src/libraries/Microsoft.Extensions.Logging.Abstractions/tests/Microsoft.Extensions.Logging.Generators.Tests/LoggerMessageGeneratorParserTests.cs index 9d80c884bf2fab..462111ad00c372 100644 --- a/src/libraries/Microsoft.Extensions.Logging.Abstractions/tests/Microsoft.Extensions.Logging.Generators.Tests/LoggerMessageGeneratorParserTests.cs +++ b/src/libraries/Microsoft.Extensions.Logging.Abstractions/tests/Microsoft.Extensions.Logging.Generators.Tests/LoggerMessageGeneratorParserTests.cs @@ -877,6 +877,40 @@ partial class C Assert.Empty(diagnostics); } + [Fact] + public static void SyntaxListWithManyItems() + { + const int nItems = 200000; + var builder = new System.Text.StringBuilder(); + builder.AppendLine( + """ + using Microsoft.Extensions.Logging; + class Program + { + [LoggerMessage(EventId = 1, Level = LogLevel.Debug, Message = "M1")] + static partial void M1(ILogger logger) + { + """); + builder.AppendLine(" int[] values = new[] { "); + for (int i = 0; i < nItems; i++) + { + builder.Append("0, "); + } + builder.AppendLine("};"); + builder.AppendLine("}"); + builder.AppendLine("}"); + + string source = builder.ToString(); + Compilation compilation = CompilationHelper.CreateCompilation(source); + LoggerMessageGenerator generator = new LoggerMessageGenerator(); + + (ImmutableArray diagnostics, _) = + RoslynTestUtils.RunGenerator(compilation, generator); + + Assert.Single(diagnostics); + Assert.Equal(DiagnosticDescriptors.LoggingMethodHasBody.Id, diagnostics[0].Id); + } + private static async Task> RunGenerator( string code, bool wrap = true, From 0c9568a409467a0cfdad3224a46087f815d5e1ca Mon Sep 17 00:00:00 2001 From: Egor Bogatov Date: Tue, 21 Mar 2023 01:49:42 +0100 Subject: [PATCH 03/20] Improve RA for LowerBlockStore (#83627) --- src/coreclr/jit/lowerxarch.cpp | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/src/coreclr/jit/lowerxarch.cpp b/src/coreclr/jit/lowerxarch.cpp index 44592e4e1f24ac..56fd1c30c1a653 100644 --- a/src/coreclr/jit/lowerxarch.cpp +++ b/src/coreclr/jit/lowerxarch.cpp @@ -348,15 +348,27 @@ void Lowering::LowerBlockStore(GenTreeBlk* blkNode) { const bool canUse16BytesSimdMov = !blkNode->IsOnHeapAndContainsReferences(); #ifdef TARGET_AMD64 - const bool willUseOnlySimdMov = canUse16BytesSimdMov && (size % XMM_REGSIZE_BYTES == 0); + + bool willUseOnlySimdMov = size % XMM_REGSIZE_BYTES == 0; + if (!willUseOnlySimdMov) + { + // If we have a remainder we still might only use SIMD to process it (via overlapping) + // unless it's more efficient to do that via scalar op (for sizes 1,2,4 and 8) + const unsigned remainder = size % XMM_REGSIZE_BYTES; + if (!isPow2(remainder) || (remainder > REGSIZE_BYTES)) + { + willUseOnlySimdMov = true; + } + } #else const bool willUseOnlySimdMov = (size % 8 == 0); #endif - if (willUseOnlySimdMov) + if (willUseOnlySimdMov && canUse16BytesSimdMov) { src->SetContained(); } - else if (size > comp->getUnrollThreshold(Compiler::UnrollKind::Memset, /*canUseSimd*/ false)) + else if (size > comp->getUnrollThreshold(Compiler::UnrollKind::Memset, + /*canUseSimd*/ canUse16BytesSimdMov)) { // It turns out we can't use SIMD so the default threshold is too big goto TOO_BIG_TO_UNROLL; From beab6cd5a22cf6e2bd0c36d9443b1283872815c1 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Mon, 20 Mar 2023 19:08:44 -0700 Subject: [PATCH 04/20] Use BitOperations::PopCount() in genCountBits() (#83661) --- src/coreclr/jit/codegenarmarch.cpp | 2 +- src/coreclr/jit/compiler.hpp | 19 ++++++++++--------- src/coreclr/jit/emit.cpp | 4 ++-- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/coreclr/jit/codegenarmarch.cpp b/src/coreclr/jit/codegenarmarch.cpp index e73477ef980522..8d3628038fc785 100644 --- a/src/coreclr/jit/codegenarmarch.cpp +++ b/src/coreclr/jit/codegenarmarch.cpp @@ -4185,7 +4185,7 @@ void CodeGen::genCreateAndStoreGCInfo(unsigned codeSize, // -all callee-preserved registers in case of varargs // -saved bool for synchronized methods - int preservedAreaSize = (2 + genCountBits(RBM_ENC_CALLEE_SAVED)) * REGSIZE_BYTES; + int preservedAreaSize = (2 + genCountBits((uint64_t)RBM_ENC_CALLEE_SAVED)) * REGSIZE_BYTES; if (compiler->info.compIsVarArgs) { diff --git a/src/coreclr/jit/compiler.hpp b/src/coreclr/jit/compiler.hpp index 4da90e95523c9c..1783eddb1bca31 100644 --- a/src/coreclr/jit/compiler.hpp +++ b/src/coreclr/jit/compiler.hpp @@ -255,18 +255,19 @@ inline regMaskTP genFindLowestReg(regMaskTP value) * A rather simple routine that counts the number of bits in a given number. */ -template -inline unsigned genCountBits(T bits) +inline unsigned genCountBits(uint64_t bits) { - unsigned cnt = 0; + return BitOperations::PopCount(bits); +} - while (bits) - { - cnt++; - bits -= genFindLowestBit(bits); - } +/***************************************************************************** + * + * A rather simple routine that counts the number of bits in a given number. + */ - return cnt; +inline unsigned genCountBits(uint32_t bits) +{ + return BitOperations::PopCount(bits); } /***************************************************************************** diff --git a/src/coreclr/jit/emit.cpp b/src/coreclr/jit/emit.cpp index 9a47ef14442b7f..70460fdbb77111 100644 --- a/src/coreclr/jit/emit.cpp +++ b/src/coreclr/jit/emit.cpp @@ -1741,10 +1741,10 @@ void emitter::emitCheckIGList() } // An IG can have at most one of the prolog and epilog flags set. - assert(genCountBits(currIG->igFlags & (IGF_FUNCLET_PROLOG | IGF_FUNCLET_EPILOG | IGF_EPILOG)) <= 1); + assert(genCountBits((unsigned)currIG->igFlags & (IGF_FUNCLET_PROLOG | IGF_FUNCLET_EPILOG | IGF_EPILOG)) <= 1); // An IG can't have both IGF_HAS_ALIGN and IGF_REMOVED_ALIGN. - assert(genCountBits(currIG->igFlags & (IGF_HAS_ALIGN | IGF_REMOVED_ALIGN)) <= 1); + assert(genCountBits((unsigned)currIG->igFlags & (IGF_HAS_ALIGN | IGF_REMOVED_ALIGN)) <= 1); if (currIG->igFlags & IGF_EXTEND) { From 12e9711813ccdca852a59af0c91c633d1fd031b0 Mon Sep 17 00:00:00 2001 From: Tanner Gooding Date: Mon, 20 Mar 2023 19:16:57 -0700 Subject: [PATCH 05/20] Cleanup some HWIntrinsic logic to ensure the right gtType and simdSize are being set (#83516) * Cleanup some HWIntrinsic logic to ensure the right gtType and simdSize are being set * Apply formatting patch * Add a missing GetLower call * Fix an assert for lowering TYP_SIMD12 where its handled as TYP_SIMD16 * Ensure GetLower is used in Dot for TYP_SIMD32 * Apply formatting patch * Insert after, not before, for the _GetLower to avoid a codegen regression * Put the _GetLower in the right place to avoid the codegen regression * Don't change the simd size of TYP_SIMD8/12 DotProduct unnecessarily --- src/coreclr/jit/gentree.cpp | 59 ++++++------ src/coreclr/jit/hwintrinsicarm64.cpp | 8 +- src/coreclr/jit/hwintrinsicxarch.cpp | 2 +- src/coreclr/jit/lower.h | 2 +- src/coreclr/jit/lowerxarch.cpp | 128 ++++++++++++--------------- 5 files changed, 89 insertions(+), 110 deletions(-) diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index f811a72061f9a8..7f9f38da566b92 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -19544,7 +19544,8 @@ GenTree* Compiler::gtNewSimdBinOpNode(genTreeOps op, assert(varTypeIsArithmetic(simdBaseType)); assert(op1 != nullptr); - assert(op1->TypeIs(type, simdBaseType, genActualType(simdBaseType))); + assert(op1->TypeIs(type, simdBaseType, genActualType(simdBaseType)) || + (op1->TypeIs(TYP_SIMD12) && type == TYP_SIMD16)); assert(op2 != nullptr); @@ -19554,7 +19555,8 @@ GenTree* Compiler::gtNewSimdBinOpNode(genTreeOps op, } else { - assert(op2->TypeIs(type, simdBaseType, genActualType(simdBaseType))); + assert(op2->TypeIs(type, simdBaseType, genActualType(simdBaseType)) || + (op2->TypeIs(TYP_SIMD12) && type == TYP_SIMD16)); } NamedIntrinsic intrinsic = NI_Illegal; @@ -22425,11 +22427,9 @@ GenTree* Compiler::gtNewSimdNarrowNode(var_types type, GenTree* vecCon2 = gtCloneExpr(vecCon1); - tmp1 = gtNewSimdHWIntrinsicNode(type, op1, vecCon1, NI_SSE2_And, simdBaseJitType, simdSize, - isSimdAsHWIntrinsic); - tmp2 = gtNewSimdHWIntrinsicNode(type, op2, vecCon2, NI_SSE2_And, simdBaseJitType, simdSize, - isSimdAsHWIntrinsic); - tmp3 = gtNewSimdHWIntrinsicNode(type, tmp1, tmp2, NI_SSE2_PackUnsignedSaturate, CORINFO_TYPE_UBYTE, + tmp1 = gtNewSimdBinOpNode(GT_AND, type, op1, vecCon1, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); + tmp2 = gtNewSimdBinOpNode(GT_AND, type, op2, vecCon2, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); + tmp3 = gtNewSimdHWIntrinsicNode(type, tmp1, tmp2, NI_AVX2_PackUnsignedSaturate, CORINFO_TYPE_UBYTE, simdSize, isSimdAsHWIntrinsic); CorInfoType permuteBaseJitType = (simdBaseType == TYP_BYTE) ? CORINFO_TYPE_LONG : CORINFO_TYPE_ULONG; @@ -22468,11 +22468,9 @@ GenTree* Compiler::gtNewSimdNarrowNode(var_types type, GenTree* vecCon2 = gtCloneExpr(vecCon1); - tmp1 = gtNewSimdHWIntrinsicNode(type, op1, vecCon1, NI_SSE2_And, simdBaseJitType, simdSize, - isSimdAsHWIntrinsic); - tmp2 = gtNewSimdHWIntrinsicNode(type, op2, vecCon2, NI_SSE2_And, simdBaseJitType, simdSize, - isSimdAsHWIntrinsic); - tmp3 = gtNewSimdHWIntrinsicNode(type, tmp1, tmp2, NI_SSE41_PackUnsignedSaturate, CORINFO_TYPE_USHORT, + tmp1 = gtNewSimdBinOpNode(GT_AND, type, op1, vecCon1, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); + tmp2 = gtNewSimdBinOpNode(GT_AND, type, op2, vecCon2, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); + tmp3 = gtNewSimdHWIntrinsicNode(type, tmp1, tmp2, NI_AVX2_PackUnsignedSaturate, CORINFO_TYPE_USHORT, simdSize, isSimdAsHWIntrinsic); CorInfoType permuteBaseJitType = (simdBaseType == TYP_BYTE) ? CORINFO_TYPE_LONG : CORINFO_TYPE_ULONG; @@ -22576,10 +22574,8 @@ GenTree* Compiler::gtNewSimdNarrowNode(var_types type, GenTree* vecCon2 = gtCloneExpr(vecCon1); - tmp1 = gtNewSimdHWIntrinsicNode(type, op1, vecCon1, NI_SSE2_And, simdBaseJitType, simdSize, - isSimdAsHWIntrinsic); - tmp2 = gtNewSimdHWIntrinsicNode(type, op2, vecCon2, NI_SSE2_And, simdBaseJitType, simdSize, - isSimdAsHWIntrinsic); + tmp1 = gtNewSimdBinOpNode(GT_AND, type, op1, vecCon1, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); + tmp2 = gtNewSimdBinOpNode(GT_AND, type, op2, vecCon2, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); return gtNewSimdHWIntrinsicNode(type, tmp1, tmp2, NI_SSE2_PackUnsignedSaturate, CORINFO_TYPE_UBYTE, simdSize, isSimdAsHWIntrinsic); @@ -22618,10 +22614,10 @@ GenTree* Compiler::gtNewSimdNarrowNode(var_types type, GenTree* vecCon2 = gtCloneExpr(vecCon1); - tmp1 = gtNewSimdHWIntrinsicNode(type, op1, vecCon1, NI_SSE2_And, simdBaseJitType, simdSize, - isSimdAsHWIntrinsic); - tmp2 = gtNewSimdHWIntrinsicNode(type, op2, vecCon2, NI_SSE2_And, simdBaseJitType, simdSize, - isSimdAsHWIntrinsic); + tmp1 = + gtNewSimdBinOpNode(GT_AND, type, op1, vecCon1, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); + tmp2 = + gtNewSimdBinOpNode(GT_AND, type, op2, vecCon2, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); return gtNewSimdHWIntrinsicNode(type, tmp1, tmp2, NI_SSE41_PackUnsignedSaturate, CORINFO_TYPE_USHORT, simdSize, isSimdAsHWIntrinsic); @@ -22928,8 +22924,8 @@ GenTree* Compiler::gtNewSimdShuffleNode(var_types type, simdBaseJitType = varTypeIsUnsigned(simdBaseType) ? CORINFO_TYPE_UBYTE : CORINFO_TYPE_BYTE; GenTree* op1Dup = fgMakeMultiUse(&op1, clsHnd); - GenTree* op1Lower = gtNewSimdHWIntrinsicNode(type, op1, NI_Vector256_GetLower, simdBaseJitType, simdSize, - isSimdAsHWIntrinsic); + GenTree* op1Lower = gtNewSimdHWIntrinsicNode(TYP_SIMD16, op1, NI_Vector256_GetLower, simdBaseJitType, + simdSize, isSimdAsHWIntrinsic); op2 = gtNewVconNode(TYP_SIMD16); op2->AsVecCon()->gtSimd16Val = vecCns.v128[0]; @@ -22937,7 +22933,7 @@ GenTree* Compiler::gtNewSimdShuffleNode(var_types type, op1Lower = gtNewSimdHWIntrinsicNode(TYP_SIMD16, op1Lower, op2, NI_SSSE3_Shuffle, simdBaseJitType, 16, isSimdAsHWIntrinsic); - GenTree* op1Upper = gtNewSimdHWIntrinsicNode(type, op1Dup, gtNewIconNode(1), NI_AVX_ExtractVector128, + GenTree* op1Upper = gtNewSimdHWIntrinsicNode(TYP_SIMD16, op1Dup, gtNewIconNode(1), NI_AVX_ExtractVector128, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); op2 = gtNewVconNode(TYP_SIMD16); @@ -23346,12 +23342,12 @@ GenTree* Compiler::gtNewSimdSumNode( op1 = gtNewSimdHWIntrinsicNode(TYP_SIMD16, op1, gtNewIconNode(0x01, TYP_INT), NI_AVX_ExtractVector128, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); - tmp = gtNewSimdHWIntrinsicNode(simdType, tmp, NI_Vector256_GetLower, simdBaseJitType, simdSize, + tmp = gtNewSimdHWIntrinsicNode(TYP_SIMD16, tmp, NI_Vector256_GetLower, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); op1 = gtNewSimdHWIntrinsicNode(TYP_SIMD16, op1, tmp, intrinsic, simdBaseJitType, 16, isSimdAsHWIntrinsic); } - return gtNewSimdHWIntrinsicNode(type, op1, NI_Vector128_ToScalar, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); + return gtNewSimdHWIntrinsicNode(type, op1, NI_Vector128_ToScalar, simdBaseJitType, 16, isSimdAsHWIntrinsic); #elif defined(TARGET_ARM64) switch (simdBaseType) { @@ -23544,8 +23540,8 @@ GenTree* Compiler::gtNewSimdWidenLowerNode( assert(compIsaSupportedDebugOnly(InstructionSet_AVX)); assert(!varTypeIsIntegral(simdBaseType) || compIsaSupportedDebugOnly(InstructionSet_AVX2)); - tmp1 = - gtNewSimdHWIntrinsicNode(type, op1, NI_Vector256_GetLower, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); + tmp1 = gtNewSimdHWIntrinsicNode(TYP_SIMD16, op1, NI_Vector256_GetLower, simdBaseJitType, simdSize, + isSimdAsHWIntrinsic); switch (simdBaseType) { @@ -23673,7 +23669,8 @@ GenTree* Compiler::gtNewSimdWidenLowerNode( if (simdSize == 8) { - tmp1 = gtNewSimdHWIntrinsicNode(type, tmp1, NI_Vector128_GetLower, simdBaseJitType, 16, isSimdAsHWIntrinsic); + tmp1 = + gtNewSimdHWIntrinsicNode(TYP_SIMD8, tmp1, NI_Vector128_GetLower, simdBaseJitType, 16, isSimdAsHWIntrinsic); } return tmp1; @@ -23706,8 +23703,8 @@ GenTree* Compiler::gtNewSimdWidenUpperNode( assert(compIsaSupportedDebugOnly(InstructionSet_AVX)); assert(!varTypeIsIntegral(simdBaseType) || compIsaSupportedDebugOnly(InstructionSet_AVX2)); - tmp1 = gtNewSimdHWIntrinsicNode(type, op1, gtNewIconNode(1), NI_AVX_ExtractVector128, simdBaseJitType, simdSize, - isSimdAsHWIntrinsic); + tmp1 = gtNewSimdHWIntrinsicNode(TYP_SIMD16, op1, gtNewIconNode(1), NI_AVX_ExtractVector128, simdBaseJitType, + simdSize, isSimdAsHWIntrinsic); switch (simdBaseType) { @@ -23860,7 +23857,7 @@ GenTree* Compiler::gtNewSimdWidenUpperNode( zero = gtNewZeroConNode(TYP_SIMD16); tmp1 = gtNewSimdHWIntrinsicNode(TYP_SIMD16, tmp1, zero, gtNewIconNode(index), NI_AdvSimd_ExtractVector128, simdBaseJitType, 16, isSimdAsHWIntrinsic); - return gtNewSimdHWIntrinsicNode(type, tmp1, NI_Vector128_GetLower, simdBaseJitType, simdSize, + return gtNewSimdHWIntrinsicNode(TYP_SIMD8, tmp1, NI_Vector128_GetLower, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); } #else diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index 57f3498ad4010a..01f7a4420df1b8 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -424,7 +424,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, assert(retType == TYP_SIMD8); op1 = impSIMDPopStack(TYP_SIMD16); - retNode = gtNewSimdHWIntrinsicNode(retType, op1, NI_Vector128_GetLower, simdBaseJitType, simdSize); + retNode = gtNewSimdHWIntrinsicNode(TYP_SIMD8, op1, NI_Vector128_GetLower, simdBaseJitType, simdSize); break; } @@ -1056,7 +1056,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, if (varTypeIsByte(simdBaseType) && (simdSize == 16)) { - CORINFO_CLASS_HANDLE simdClsHnd = gtGetStructHandleForSimdOrHW(simdType, simdBaseJitType); + CORINFO_CLASS_HANDLE simdClsHnd = gtGetStructHandleForSimdOrHW(TYP_SIMD16, simdBaseJitType); op1 = impCloneExpr(op1, &op2, simdClsHnd, CHECK_SPILL_ALL, nullptr DEBUGARG("Clone op1 for vector extractmostsignificantbits")); @@ -1069,10 +1069,10 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, /* isSimdAsHWIntrinsic */ false); op1 = gtNewCastNode(TYP_INT, op1, /* isUnsigned */ true, TYP_INT); - GenTree* zero = gtNewZeroConNode(simdType); + GenTree* zero = gtNewZeroConNode(TYP_SIMD16); ssize_t index = 8 / genTypeSize(simdBaseType); - op2 = gtNewSimdHWIntrinsicNode(simdType, op2, zero, gtNewIconNode(index), NI_AdvSimd_ExtractVector128, + op2 = gtNewSimdHWIntrinsicNode(TYP_SIMD16, op2, zero, gtNewIconNode(index), NI_AdvSimd_ExtractVector128, simdBaseJitType, simdSize, /* isSimdAsHWIntrinsic */ false); op2 = gtNewSimdHWIntrinsicNode(TYP_SIMD8, op2, NI_Vector128_GetLower, simdBaseJitType, simdSize, /* isSimdAsHWIntrinsic */ false); diff --git a/src/coreclr/jit/hwintrinsicxarch.cpp b/src/coreclr/jit/hwintrinsicxarch.cpp index 977bb1b320a871..e9412330705900 100644 --- a/src/coreclr/jit/hwintrinsicxarch.cpp +++ b/src/coreclr/jit/hwintrinsicxarch.cpp @@ -1382,7 +1382,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, simdVal.u64[3] = 0x8080808080808080; shuffleIntrinsic = NI_AVX2_Shuffle; - moveMaskIntrinsic = NI_AVX2_MoveMask; + moveMaskIntrinsic = NI_SSE2_MoveMask; } else if (compOpportunisticallyDependsOn(InstructionSet_SSSE3)) { diff --git a/src/coreclr/jit/lower.h b/src/coreclr/jit/lower.h index 2a7eb25ca9c7d9..db5aa9dc2119b5 100644 --- a/src/coreclr/jit/lower.h +++ b/src/coreclr/jit/lower.h @@ -349,13 +349,13 @@ class Lowering final : public Phase GenTree* LowerHWIntrinsic(GenTreeHWIntrinsic* node); void LowerHWIntrinsicCC(GenTreeHWIntrinsic* node, NamedIntrinsic newIntrinsicId, GenCondition condition); GenTree* LowerHWIntrinsicCmpOp(GenTreeHWIntrinsic* node, genTreeOps cmpOp); - void LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* node); GenTree* LowerHWIntrinsicCreate(GenTreeHWIntrinsic* node); GenTree* LowerHWIntrinsicDot(GenTreeHWIntrinsic* node); #if defined(TARGET_XARCH) void LowerFusedMultiplyAdd(GenTreeHWIntrinsic* node); void LowerHWIntrinsicToScalar(GenTreeHWIntrinsic* node); void LowerHWIntrinsicGetElement(GenTreeHWIntrinsic* node); + GenTree* LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* node); GenTree* LowerHWIntrinsicWithElement(GenTreeHWIntrinsic* node); GenTree* TryLowerAndOpToResetLowestSetBit(GenTreeOp* andNode); GenTree* TryLowerAndOpToExtractLowestSetBit(GenTreeOp* andNode); diff --git a/src/coreclr/jit/lowerxarch.cpp b/src/coreclr/jit/lowerxarch.cpp index 56fd1c30c1a653..f7b087b9db07bf 100644 --- a/src/coreclr/jit/lowerxarch.cpp +++ b/src/coreclr/jit/lowerxarch.cpp @@ -1049,8 +1049,7 @@ GenTree* Lowering::LowerHWIntrinsic(GenTreeHWIntrinsic* node) case NI_Vector128_ConditionalSelect: case NI_Vector256_ConditionalSelect: { - LowerHWIntrinsicCndSel(node); - break; + return LowerHWIntrinsicCndSel(node); } case NI_Vector128_Create: @@ -1787,7 +1786,7 @@ GenTree* Lowering::LowerHWIntrinsicCmpOp(GenTreeHWIntrinsic* node, genTreeOps cm // Arguments: // node - The hardware intrinsic node. // -void Lowering::LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* node) +GenTree* Lowering::LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* node) { var_types simdType = node->gtType; CorInfoType simdBaseJitType = node->GetSimdBaseJitType(); @@ -1844,7 +1843,7 @@ void Lowering::LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* node) { // result = BlendVariable op3 (right) op2 (left) op1 (mask) node->ResetHWIntrinsicId(blendVariableId, comp, op3, op2, op1); - return; + return LowerNode(node); } } @@ -1860,6 +1859,7 @@ void Lowering::LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* node) GenTree* tmp1; GenTree* tmp2; GenTree* tmp3; + GenTree* tmp4; LIR::Use op1Use(BlockRange(), &node->Op(1), node); ReplaceWithLclVar(op1Use); @@ -1882,42 +1882,24 @@ void Lowering::LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* node) BlockRange().InsertAfter(op3, tmp3); LowerNode(tmp3); - // determine which Or intrinsic to use, depending on target architecture - NamedIntrinsic orIntrinsic = NI_Illegal; - - if (simdSize == 32) - { - assert(comp->compIsaSupportedDebugOnly(InstructionSet_AVX)); + // ... + // tmp4 = tmp2 | tmp3 + // ... + tmp4 = comp->gtNewSimdBinOpNode(GT_OR, simdType, tmp2, tmp3, simdBaseJitType, simdSize, isSimdAsHWIntrinsic); + BlockRange().InsertBefore(node, tmp4); - if (varTypeIsFloating(simdBaseType)) - { - orIntrinsic = NI_AVX_Or; - } - else if (comp->compOpportunisticallyDependsOn(InstructionSet_AVX2)) - { - orIntrinsic = NI_AVX2_Or; - } - else - { - // Since this is a bitwise operation, we can still support it by lying - // about the type and doing the operation using a supported instruction - orIntrinsic = NI_AVX_Or; - simdBaseJitType = CORINFO_TYPE_FLOAT; - } - } - else if (simdBaseType == TYP_FLOAT) + LIR::Use use; + if (BlockRange().TryGetUse(node, &use)) { - orIntrinsic = NI_SSE_Or; + use.ReplaceWith(tmp4); } else { - orIntrinsic = NI_SSE2_Or; + tmp4->SetUnusedValue(); } - // ... - // result = tmp2 | tmp3 - node->ResetHWIntrinsicId(orIntrinsic, tmp2, tmp3); - node->SetSimdBaseJitType(simdBaseJitType); + BlockRange().Remove(node); + return LowerNode(tmp4); } //---------------------------------------------------------------------------------------------- @@ -1998,6 +1980,9 @@ GenTree* Lowering::LowerHWIntrinsicCreate(GenTreeHWIntrinsic* node) { if (isCreateScalar) { + node->gtType = TYP_SIMD16; + node->SetSimdSize(16); + switch (simdBaseType) { case TYP_BYTE: @@ -3284,6 +3269,7 @@ void Lowering::LowerHWIntrinsicGetElement(GenTreeHWIntrinsic* node) unreached(); } + node->SetSimdSize(16); node->ResetHWIntrinsicId(resIntrinsic, op1); } else @@ -3328,11 +3314,10 @@ void Lowering::LowerHWIntrinsicGetElement(GenTreeHWIntrinsic* node) unreached(); } + node->SetSimdSize(16); node->ResetHWIntrinsicId(resIntrinsic, op1, op2); } - node->SetSimdSize(16); - if (node->GetHWIntrinsicId() != intrinsicId) { LowerNode(node); @@ -3738,9 +3723,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) GenTree* tmp2 = nullptr; GenTree* tmp3 = nullptr; - NamedIntrinsic multiply = NI_Illegal; NamedIntrinsic horizontalAdd = NI_Illegal; - NamedIntrinsic add = NI_Illegal; NamedIntrinsic shuffle = NI_Illegal; if (simdSize == 32) @@ -3753,10 +3736,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) case TYP_UINT: { assert(comp->compIsaSupportedDebugOnly(InstructionSet_AVX2)); - - multiply = NI_AVX2_MultiplyLow; horizontalAdd = NI_AVX2_HorizontalAdd; - add = NI_AVX2_Add; break; } @@ -3769,11 +3749,13 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) // /--* op1 simd16 // +--* op2 simd16 // +--* idx int - // tmp1 = * HWINTRINSIC simd16 T DotProduct - // /--* tmp1 simd16 - // * STORE_LCL_VAR simd16 - // tmp1 = LCL_VAR simd16 - // tmp2 = LCL_VAR simd16 + // tmp1 = * HWINTRINSIC simd32 T DotProduct + // /--* tmp1 simd32 + // * STORE_LCL_VAR simd32 + // tmp1 = LCL_VAR simd32 + // /--* tmp1 simd32 + // tmp1 = * HWINTRINSIC simd16 T GetLower + // tmp2 = LCL_VAR simd32 // idx = CNS_INT int 0x01 // /--* tmp2 simd16 // +--* idx int @@ -3814,8 +3796,13 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) BlockRange().InsertAfter(idx, tmp2); LowerNode(tmp2); - tmp3 = comp->gtNewSimdHWIntrinsicNode(TYP_SIMD16, tmp1, tmp2, NI_SSE_Add, simdBaseJitType, 16); - BlockRange().InsertAfter(tmp2, tmp3); + tmp1 = + comp->gtNewSimdHWIntrinsicNode(TYP_SIMD16, tmp1, NI_Vector256_GetLower, simdBaseJitType, simdSize); + BlockRange().InsertAfter(tmp2, tmp1); + LowerNode(tmp1); + + tmp3 = comp->gtNewSimdBinOpNode(GT_ADD, TYP_SIMD16, tmp2, tmp1, simdBaseJitType, 16, false); + BlockRange().InsertAfter(tmp1, tmp3); LowerNode(tmp3); node->SetSimdSize(16); @@ -3828,10 +3815,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) case TYP_DOUBLE: { assert(comp->compIsaSupportedDebugOnly(InstructionSet_AVX)); - - multiply = NI_AVX_Multiply; horizontalAdd = NI_AVX_HorizontalAdd; - add = NI_AVX_Add; break; } @@ -3850,9 +3834,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) case TYP_SHORT: case TYP_USHORT: { - multiply = NI_SSE2_MultiplyLow; horizontalAdd = NI_SSSE3_HorizontalAdd; - add = NI_SSE2_Add; if (!comp->compOpportunisticallyDependsOn(InstructionSet_SSSE3)) { @@ -3864,11 +3846,8 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) case TYP_INT: case TYP_UINT: { - multiply = NI_SSE41_MultiplyLow; - horizontalAdd = NI_SSSE3_HorizontalAdd; - add = NI_SSE2_Add; - assert(comp->compIsaSupportedDebugOnly(InstructionSet_SSE41)); + horizontalAdd = NI_SSSE3_HorizontalAdd; break; } @@ -3927,9 +3906,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) return LowerNode(node); } - multiply = NI_SSE_Multiply; horizontalAdd = NI_SSE3_HorizontalAdd; - add = NI_SSE_Add; if (!comp->compOpportunisticallyDependsOn(InstructionSet_SSE3)) { @@ -3981,9 +3958,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) return LowerNode(node); } - multiply = NI_SSE2_Multiply; horizontalAdd = NI_SSE3_HorizontalAdd; - add = NI_SSE2_Add; if (!comp->compOpportunisticallyDependsOn(InstructionSet_SSE3)) { @@ -4046,10 +4021,9 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) GenTreeVecCon* vecCon1 = comp->gtNewVconNode(simdType); memcpy(&vecCon1->gtSimdVal, &simd16Val, sizeof(simd16_t)); - BlockRange().InsertAfter(op1, vecCon1); - op1 = comp->gtNewSimdHWIntrinsicNode(simdType, op1, vecCon1, NI_SSE_And, simdBaseJitType, simdSize); + op1 = comp->gtNewSimdBinOpNode(GT_AND, simdType, op1, vecCon1, simdBaseJitType, simdSize, false); BlockRange().InsertAfter(vecCon1, op1); LowerNode(vecCon1); @@ -4075,10 +4049,9 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) GenTreeVecCon* vecCon2 = comp->gtNewVconNode(simdType); memcpy(&vecCon2->gtSimdVal, &simd16Val, sizeof(simd16_t)); - BlockRange().InsertAfter(op2, vecCon2); - op2 = comp->gtNewSimdHWIntrinsicNode(simdType, op2, vecCon2, NI_SSE_And, simdBaseJitType, simdSize); + op2 = comp->gtNewSimdBinOpNode(GT_AND, simdType, op2, vecCon2, simdBaseJitType, simdSize, false); BlockRange().InsertAfter(vecCon2, op2); LowerNode(vecCon2); @@ -4096,7 +4069,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) // var tmp1 = Isa.Multiply(op1, op2); // ... - tmp1 = comp->gtNewSimdHWIntrinsicNode(simdType, op1, op2, multiply, simdBaseJitType, simdSize); + tmp1 = comp->gtNewSimdBinOpNode(GT_MUL, simdType, op1, op2, simdBaseJitType, simdSize, false); BlockRange().InsertBefore(node, tmp1); LowerNode(tmp1); @@ -4301,7 +4274,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) // tmp1 = Isa.Add(tmp1, tmp2); // ... - tmp1 = comp->gtNewSimdHWIntrinsicNode(simdType, tmp1, tmp2, add, simdBaseJitType, simdSize); + tmp1 = comp->gtNewSimdBinOpNode(GT_ADD, simdType, tmp1, tmp2, simdBaseJitType, simdSize, false); } BlockRange().InsertAfter(tmp2, tmp1); @@ -4312,12 +4285,14 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) { // We will be constructing the following parts: // ... - // /--* tmp1 simd16 - // * STORE_LCL_VAR simd16 - // tmp1 = LCL_VAR simd16 - // tmp2 = LCL_VAR simd16 + // /--* tmp1 simd32 + // * STORE_LCL_VAR simd32 + // tmp1 = LCL_VAR simd32 + // /--* tmp1 simd32 + // tmp1 = * HWINTRINSIC simd16 T GetLower + // tmp2 = LCL_VAR simd32 // idx = CNS_INT int 0x01 - // /--* tmp2 simd16 + // /--* tmp2 simd32 // +--* idx int // tmp2 = * HWINTRINSIC simd16 T ExtractVector128 // /--* tmp1 simd16 @@ -4329,9 +4304,11 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) // ... // var tmp2 = tmp1; // tmp2 = Avx.ExtractVector128(tmp2, 0x01); - // var tmp1 = Isa.Add(tmp1, tmp2); + // var tmp1 = Isa.Add(tmp1.GetLower(), tmp2); // ... + assert(simdBaseType != TYP_FLOAT); + node->Op(1) = tmp1; LIR::Use tmp1Use(BlockRange(), &node->Op(1), node); ReplaceWithLclVar(tmp1Use); @@ -4348,11 +4325,16 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node) BlockRange().InsertAfter(idx, tmp2); LowerNode(tmp2); - tmp1 = comp->gtNewSimdHWIntrinsicNode(TYP_SIMD16, tmp1, tmp2, add, simdBaseJitType, 16); + tmp1 = comp->gtNewSimdHWIntrinsicNode(TYP_SIMD16, tmp1, NI_Vector256_GetLower, simdBaseJitType, simdSize); BlockRange().InsertAfter(tmp2, tmp1); LowerNode(tmp1); + tmp3 = comp->gtNewSimdBinOpNode(GT_ADD, TYP_SIMD16, tmp2, tmp1, simdBaseJitType, 16, false); + BlockRange().InsertAfter(tmp1, tmp3); + LowerNode(tmp3); + node->SetSimdSize(16); + tmp1 = tmp3; } if (varTypeIsSIMD(node->gtType)) From 7b651743dc951384f6c3d8455c88518022c7c3b9 Mon Sep 17 00:00:00 2001 From: Marc Brooks Date: Mon, 20 Mar 2023 22:33:39 -0500 Subject: [PATCH 06/20] Correct doc comment for IMultiplyOperators returns (#83693) Replaced _divided-by_ with _multiplied-by_ in both IMultiplyOperators.cs and NFloat.cs. Fixes https://github.com/dotnet/runtime/issues/80521 --- .../src/System/Numerics/IMultiplyOperators.cs | 4 ++-- .../src/System/Runtime/InteropServices/NFloat.cs | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/libraries/System.Private.CoreLib/src/System/Numerics/IMultiplyOperators.cs b/src/libraries/System.Private.CoreLib/src/System/Numerics/IMultiplyOperators.cs index e93e3d466823c2..ac78fe9f446479 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Numerics/IMultiplyOperators.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Numerics/IMultiplyOperators.cs @@ -13,13 +13,13 @@ public interface IMultiplyOperators /// Multiplies two values together to compute their product. /// The value which multiplies. /// The value which multiplies . - /// The product of divided-by . + /// The product of multiplied-by . static abstract TResult operator *(TSelf left, TOther right); /// Multiplies two values together to compute their product. /// The value which multiplies. /// The value which multiplies . - /// The product of divided-by . + /// The product of multiplied-by . /// The product of multiplied-by is not representable by . static virtual TResult operator checked *(TSelf left, TOther right) => left * right; } diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/InteropServices/NFloat.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/InteropServices/NFloat.cs index 6d6ebd900e61dd..fa60aa987cbbf1 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/InteropServices/NFloat.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/InteropServices/NFloat.cs @@ -164,7 +164,7 @@ public double Value /// Multiplies two values together to compute their product. /// The value which multiplies. /// The value which multiplies . - /// The product of divided-by . + /// The product of multiplied-by . [NonVersionable] public static NFloat operator *(NFloat left, NFloat right) => new NFloat(left._value * right._value); From 17f576f070059760d0253d9e653918b40c6b7457 Mon Sep 17 00:00:00 2001 From: dotnet bot Date: Tue, 21 Mar 2023 00:53:26 -0700 Subject: [PATCH 07/20] Localized file check-in by OneLocBuild Task: Build definition ID 679: Build ID 2140030 (#83703) --- .../gen/Resources/xlf/Strings.cs.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.de.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.es.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.fr.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.it.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.ja.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.ko.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.pl.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.pt-BR.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.ru.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.tr.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.zh-Hans.xlf | 8 ++++---- .../gen/Resources/xlf/Strings.zh-Hant.xlf | 8 ++++---- 13 files changed, 52 insertions(+), 52 deletions(-) diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.cs.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.cs.xlf index a455d29fb3119d..f51196cf6cf40e 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.cs.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.cs.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + Vlastnost „{0}“ u typu „{1}“ se nepodporuje. Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + Nevygenerovala se logika vazby pro vlastnost typu. Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + Typ „{0}“ se nepodporuje: {1}. Did not generate binding logic for a type. - Did not generate binding logic for a type. + Nevygenerovala se logika vazby pro typ. diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.de.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.de.xlf index 83f3e0c9d3dc23..b615aed3283c4c 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.de.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.de.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + Die Eigenschaft „{0}“ für den Typ „{1}“ wird nicht unterstützt. Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + Für eine Eigenschaft eines Typs wurde keine Bindungslogik generiert. Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + Der Typ „{0}“ wird nicht unterstützt: {1}. Did not generate binding logic for a type. - Did not generate binding logic for a type. + Für einen Typ wurde keine Bindungslogik generiert. diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.es.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.es.xlf index 65e1a98fc2cb1e..69637f9600d4c6 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.es.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.es.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + La propiedad '{0}' en el tipo '{1}' no se admite. Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + No se generó la lógica de enlace para una propiedad en un tipo. Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + El tipo '{0}' no se admite: {1}. Did not generate binding logic for a type. - Did not generate binding logic for a type. + No se generó la lógica de enlace para un tipo. diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.fr.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.fr.xlf index 8b28eb2e7e0dc3..4b8d40565d4ad1 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.fr.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.fr.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + La propriété '{0}' sur le type '{1}' n’est pas prise en charge. Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + La logique de liaison n’a pas été généré pour une propriété sur un type. Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + Le type '{0}' n’est pas pris en charge : {1}. Did not generate binding logic for a type. - Did not generate binding logic for a type. + La logique de liaison n’a pas été générée pour un type. diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.it.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.it.xlf index ea90ac50d329c4..dff7aa401318fc 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.it.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.it.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + La proprietà '{0}' nel tipo '{1}' non è supportata. Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + Non è stata generata la logica di binding per una proprietà in un tipo. Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + Il tipo '{0}' non è supportato: {1}. Did not generate binding logic for a type. - Did not generate binding logic for a type. + Non è stata generata la logica di binding per un tipo. diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ja.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ja.xlf index 7b109d9c36227d..2a1ac3baa49695 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ja.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ja.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + 型 '{1}' のプロパティ '{0}' はサポートされていません。 Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + 型のプロパティのバインディング ロジックを生成しませんでした。 Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + 型 '{0}' はサポートされていません: {1}。 Did not generate binding logic for a type. - Did not generate binding logic for a type. + 型のバインディング ロジックを生成しませんでした。 diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ko.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ko.xlf index 769679e7946d8a..60054f8a58b9a0 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ko.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ko.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + '{1}' 형식의 속성 '{0}'은(는) 지원되지 않습니다. Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + 형식의 속성에 대한 바인딩 논리를 생성하지 않았습니다. Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + '{0}' 형식은 지원되지 않습니다. {1}. Did not generate binding logic for a type. - Did not generate binding logic for a type. + 형식에 대한 바인딩 논리를 생성하지 않았습니다. diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.pl.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.pl.xlf index 03783e569ef457..a624827ae01820 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.pl.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.pl.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + Właściwość „{0}” w typie „{1}” nie jest obsługiwana. Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + Nie wygenerowano logiki powiązania dla właściwości w typie. Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + Typ „{0}” nie jest obsługiwany: {1}. Did not generate binding logic for a type. - Did not generate binding logic for a type. + Nie wygenerowano logiki powiązania dla typu. diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.pt-BR.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.pt-BR.xlf index 606db804a431b2..cd4990cbd6890c 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.pt-BR.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.pt-BR.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + Não há suporte para a propriedade '{0}' no tipo '{1}'. Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + Não foi gerada lógica de associação para uma propriedade em um tipo. Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + Não há suporte para o tipo '{0}': {1}. Did not generate binding logic for a type. - Did not generate binding logic for a type. + Não foi gerada lógica de associação para um tipo. diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ru.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ru.xlf index 478a310db9d60c..b102972922ae04 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ru.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.ru.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + Свойство "{0}" типа "{1}" не поддерживается. Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + Не создана логика привязки для свойства типа. Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + Тип "{0}" не поддерживается: {1}. Did not generate binding logic for a type. - Did not generate binding logic for a type. + Не создана логика привязки для типа. diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.tr.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.tr.xlf index c645685a521827..5de2a119312dc1 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.tr.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.tr.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + '{1}' türündeki '{0}' özelliği desteklenmiyor. Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + Türdeki bir özellik için bağlama mantığı oluşturulmadı. Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + '{0}' türü desteklenmiyor: {1}. Did not generate binding logic for a type. - Did not generate binding logic for a type. + Bir tür için bağlama mantığı oluşturulmadı. diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.zh-Hans.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.zh-Hans.xlf index 4125bda3d69328..d5d3c89bf32dcf 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.zh-Hans.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.zh-Hans.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + 类型“{1}”中的属性“{0}”不受支持。 Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + 没有为类型中的属性生成绑定逻辑。 Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + 类型“{0}”不受支持:{1}。 Did not generate binding logic for a type. - Did not generate binding logic for a type. + 没有为类型生成绑定逻辑。 diff --git a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.zh-Hant.xlf b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.zh-Hant.xlf index e78a617f37d58f..6e8b7bc7559d53 100644 --- a/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.zh-Hant.xlf +++ b/src/libraries/Microsoft.Extensions.Configuration.Binder/gen/Resources/xlf/Strings.zh-Hant.xlf @@ -4,22 +4,22 @@ Property '{0}' on type '{1}' is not supported. - Property '{0}' on type '{1}' is not supported. + 不支援類型 '{1}' 的屬性 '{0}'。 Did not generate binding logic for a property on a type. - Did not generate binding logic for a property on a type. + 未在類型上產生屬性的繫結邏輯。 Type '{0}' is not supported: {1}. - Type '{0}' is not supported: {1}. + 不支援類型 '{0}': {1}。 Did not generate binding logic for a type. - Did not generate binding logic for a type. + 未產生類型的繫結邏輯。 From 8c5cf110b4d2fa0b98cad4b60e4abba5a6562c58 Mon Sep 17 00:00:00 2001 From: Jan Dupej <109523496+jandupej@users.noreply.github.com> Date: Tue, 21 Mar 2023 10:37:45 +0100 Subject: [PATCH 08/20] [mono][jit] Adding compare all/any intrinsics. (#83515) * xxAny, xAll comparisons in progress. * xxAny, xxAll comparisons, part 2. * [mono][jit] Adding compare all/any operations. Fixed umov,smov macros. * Removed superfluous changes. * Restored newline at the end of HelloWorld. * Fixed unmatched brace. * Indentation. * Normalized boolean values to 0/1. SIMD_EXTR_ constants have friendlier names. Equality/Inequality are now also intrinsics. * Fixed element type for comparisons. * Temporarily disabled intrinsics. Will be permanenty reenabled once all are implemented. --- src/mono/mono/arch/arm64/arm64-codegen.h | 61 +++++-------- src/mono/mono/mini/cpu-arm64.mdesc | 1 + src/mono/mono/mini/mini-arm64.c | 24 +++++ src/mono/mono/mini/mini-ops.h | 5 ++ src/mono/mono/mini/mini.h | 5 ++ src/mono/mono/mini/simd-intrinsics.c | 110 +++++++++++++++-------- 6 files changed, 129 insertions(+), 77 deletions(-) diff --git a/src/mono/mono/arch/arm64/arm64-codegen.h b/src/mono/mono/arch/arm64/arm64-codegen.h index a6ea6c3faa3504..b348d274e60251 100644 --- a/src/mono/mono/arch/arm64/arm64-codegen.h +++ b/src/mono/mono/arch/arm64/arm64-codegen.h @@ -1139,19 +1139,16 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_dup_g_4s(p, rd, rn) arm_neon_cpy_opcode ((p), VREG_FULL, 0b0, 0b00100, 0b0001, (rd), (rn)) #define arm_neon_dup_g_2d(p, rd, rn) arm_neon_cpy_opcode ((p), VREG_FULL, 0b0, 0b00100, 0b0001, (rd), (rn)) -// the opcode is smov, but we define variants smovs and smovd by whether they fill a 32 or 64-bit reg. -#define arm_neon_smovs_b(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b00001 | ((index) << 1), 0b0101, (rd), (rn)) -#define arm_neon_smovs_h(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b00010 | ((index) << 2), 0b0101, (rd), (rn)) -#define arm_neon_smovd_b(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b00001 | ((index) << 1), 0b0101, (rd), (rn)) -#define arm_neon_smovd_h(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b00010 | ((index) << 2), 0b0101, (rd), (rn)) -#define arm_neon_smovd_s(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b00100 | ((index) << 3), 0b0101, (rd), (rn)) - -// the opcode is umov, but we define variants smovs and smovd by whether they fill a 32 or 64-bit reg. -#define arm_neon_umovs_b(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b00001 | ((index) << 1), 0b0111, (rd), (rn)) -#define arm_neon_umovs_h(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b00010 | ((index) << 2), 0b0111, (rd), (rn)) -#define arm_neon_umovd_b(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b00001 | ((index) << 1), 0b0111, (rd), (rn)) -#define arm_neon_umovd_h(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b00010 | ((index) << 2), 0b0111, (rd), (rn)) -#define arm_neon_umovd_s(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b00100 | ((index) << 3), 0b0111, (rd), (rn)) +#define arm_neon_smov_b(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00001 | ((index) << 1), 0b0101, (rd), (rn)) +#define arm_neon_smov_h(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00010 | ((index) << 2), 0b0101, (rd), (rn)) +#define arm_neon_smov_s(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00100 | ((index) << 3), 0b0101, (rd), (rn)) +#define arm_neon_smov_d(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b0, 0b01000 | ((index) << 4), 0b0101, (rd), (rn)) + +#define arm_neon_umov_b(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00001 | ((index) << 1), 0b0111, (rd), (rn)) +#define arm_neon_umov_h(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00010 | ((index) << 2), 0b0111, (rd), (rn)) +#define arm_neon_umov_s(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00100 | ((index) << 3), 0b0111, (rd), (rn)) +#define arm_neon_umov_d(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b0, 0b01000 | ((index) << 4), 0b0111, (rd), (rn)) + /* NEON :: 3-register same FP16 */ // TODO @@ -1576,6 +1573,9 @@ arm_encode_arith_imm (int imm, guint32 *shift) /* NEON :: across lanes */ #define arm_neon_xln_opcode(p, q, u, size, opcode, rd, rn) arm_neon_opcode_2reg ((p), (q), 0b00001110001100000000100000000000 | (u) << 29 | (size) << 22 | (opcode) << 12, (rd), (rn)) +#define arm_neon_umaxv(p, width, type, rd, rn) arm_neon_xln_opcode ((p), (width), 0b1, (type), 0b01010, (rd), (rn)) +#define arm_neon_uminv(p, width, type, rd, rn) arm_neon_xln_opcode ((p), (width), 0b1, (type), 0b11010, (rd), (rn)) + // contrary to most other opcodes, the suffix is the type of source #define arm_neon_saddlv_8b(p, rd, rn) arm_neon_xln_opcode ((p), VREG_LOW, 0b0, SIZE_1, 0b00011, (rd), (rn)) #define arm_neon_saddlv_16b(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b0, SIZE_1, 0b00011, (rd), (rn)) @@ -1609,18 +1609,6 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_uaddlv_8h(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, SIZE_2, 0b00011, (rd), (rn)) #define arm_neon_uaddlv_4s(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, SIZE_4, 0b00011, (rd), (rn)) -#define arm_neon_umaxv_8b(p, rd, rn) arm_neon_xln_opcode ((p), VREG_LOW, 0b1, SIZE_1, 0b01010, (rd), (rn)) -#define arm_neon_umaxv_16b(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, SIZE_1, 0b01010, (rd), (rn)) -#define arm_neon_umaxv_4h(p, rd, rn) arm_neon_xln_opcode ((p), VREG_LOW, 0b1, SIZE_2, 0b01010, (rd), (rn)) -#define arm_neon_umaxv_8h(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, SIZE_2, 0b01010, (rd), (rn)) -#define arm_neon_umaxv_4s(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, SIZE_4, 0b01010, (rd), (rn)) - -#define arm_neon_uminv_8b(p, rd, rn) arm_neon_xln_opcode ((p), VREG_LOW, 0b1, SIZE_1, 0b11010, (rd), (rn)) -#define arm_neon_uminv_16b(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, SIZE_1, 0b11010, (rd), (rn)) -#define arm_neon_uminv_4h(p, rd, rn) arm_neon_xln_opcode ((p), VREG_LOW, 0b1, SIZE_2, 0b11010, (rd), (rn)) -#define arm_neon_uminv_8h(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, SIZE_2, 0b11010, (rd), (rn)) -#define arm_neon_uminv_4s(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, SIZE_4, 0b11010, (rd), (rn)) - #define arm_neon_fmaxnmv_4s(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, SIZE_1, 0b01100, (rd), (rn)) #define arm_neon_fmaxv_4s(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, SIZE_1, 0b01111, (rd), (rn)) #define arm_neon_fminnmv_4s(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b1, 0b10 | SIZE_1, 0b01100, (rd), (rn)) @@ -2313,6 +2301,15 @@ arm_encode_arith_imm (int imm, guint32 *shift) arm_neon_shimm_opcode ((p), (q), (u), (__temp_emit0 >> 3) & 0b1111, __temp_emit0 & 0b111, (opcode), (rd), (rn)) \ } while (0) +#define arm_neon_shimm_shl_immh_immb(size, shift) (((shift) + (8 << (size))) & 0b01111111) +#define arm_neon_shimm_shl_opcode(p, q, u, size, opcode, rd, rn, shift) do { \ + int32_t ___temp_emit0 = arm_neon_shimm_shl_immh_immb ((size), (shift)); \ + arm_neon_shimm_opcode ((p), (q), (u), (__temp_emit0 >> 3) & 0b1111, __temp_emit0 & 0b111, (opcode), (rd), (rn)) \ +} while (0) + +#define arm_neon_sli(p, width, type, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), (width), 0b1, (type), 0b01010, (rd), (rn), (shift)) +#define arm_neon_shrn(p, type, rd, rn, shift) arm_neon_shimm_shr_opcode ((p), VREG_LOW, 0b0, (type), 0b10000, (rd), (rn), (shift)) + #define arm_neon_sshr_8b(p, rd, rn, shift) arm_neon_shimm_shr_opcode ((p), VREG_LOW, 0b0, SIZE_1, 0b00000, (rd), (rn), (shift)) #define arm_neon_sshr_16b(p, rd, rn, shift) arm_neon_shimm_shr_opcode ((p), VREG_FULL, 0b0, SIZE_1, 0b00000, (rd), (rn), (shift)) #define arm_neon_sshr_4h(p, rd, rn, shift) arm_neon_shimm_shr_opcode ((p), VREG_LOW, 0b0, SIZE_2, 0b00000, (rd), (rn), (shift)) @@ -2345,12 +2342,6 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_srsra_4s(p, rd, rn, shift) arm_neon_shimm_shr_opcode ((p), VREG_FULL, 0b0, SIZE_4, 0b00110, (rd), (rn), (shift)) #define arm_neon_srsra_2d(p, rd, rn, shift) arm_neon_shimm_shr_opcode ((p), VREG_FULL, 0b0, SIZE_8, 0b00110, (rd), (rn), (shift)) -#define arm_neon_shimm_shl_immh_immb(size, shift) (((shift) + (8 << (size))) & 0b01111111) -#define arm_neon_shimm_shl_opcode(p, q, u, size, opcode, rd, rn, shift) do { \ - int32_t ___temp_emit0 = arm_neon_shimm_shl_immh_immb ((size), (shift)); \ - arm_neon_shimm_opcode ((p), (q), (u), (__temp_emit0 >> 3) & 0b1111, __temp_emit0 & 0b111, (opcode), (rd), (rn)) \ -} while (0) - #define arm_neon_shl_8b(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_LOW, 0b0, SIZE_1, 0b01010, (rd), (rn), (shift)) #define arm_neon_shl_16b(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_FULL, 0b0, SIZE_1, 0b01010, (rd), (rn), (shift)) #define arm_neon_shl_4h(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_LOW, 0b0, SIZE_2, 0b01010, (rd), (rn), (shift)) @@ -2454,14 +2445,6 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_sri_4s(p, rd, rn, shift) arm_neon_shimm_shr_opcode ((p), VREG_FULL, 0b1, SIZE_4, 0b01000, (rd), (rn), (shift)) #define arm_neon_sri_2d(p, rd, rn, shift) arm_neon_shimm_shr_opcode ((p), VREG_FULL, 0b1, SIZE_8, 0b01000, (rd), (rn), (shift)) -#define arm_neon_sli_8b(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_LOW, 0b1, SIZE_1, 0b01010, (rd), (rn), (shift)) -#define arm_neon_sli_16b(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_FULL, 0b1, SIZE_1, 0b01010, (rd), (rn), (shift)) -#define arm_neon_sli_4h(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_LOW, 0b1, SIZE_2, 0b01010, (rd), (rn), (shift)) -#define arm_neon_sli_8h(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_FULL, 0b1, SIZE_2, 0b01010, (rd), (rn), (shift)) -#define arm_neon_sli_2s(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_LOW, 0b1, SIZE_4, 0b01010, (rd), (rn), (shift)) -#define arm_neon_sli_4s(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_FULL, 0b1, SIZE_4, 0b01010, (rd), (rn), (shift)) -#define arm_neon_sli_2d(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_FULL, 0b1, SIZE_8, 0b01010, (rd), (rn), (shift)) - #define arm_neon_sqshlu_8b(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_LOW, 0b1, SIZE_1, 0b01100, (rd), (rn), (shift)) #define arm_neon_sqshlu_16b(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_FULL, 0b1, SIZE_1, 0b01100, (rd), (rn), (shift)) #define arm_neon_sqshlu_4h(p, rd, rn, shift) arm_neon_shimm_shl_opcode ((p), VREG_LOW, 0b1, SIZE_2, 0b01100, (rd), (rn), (shift)) diff --git a/src/mono/mono/mini/cpu-arm64.mdesc b/src/mono/mono/mini/cpu-arm64.mdesc index a084543ebb5b2e..b6f8f23a64c257 100644 --- a/src/mono/mono/mini/cpu-arm64.mdesc +++ b/src/mono/mono/mini/cpu-arm64.mdesc @@ -503,6 +503,7 @@ xcompare: dest:x src1:x src2:x len:4 xcompare_fp: dest:x src1:x src2:x len:4 negate: dest:x src1:x len:4 ones_complement: dest:x src1:x len:4 +xextract: dest:i src1:x len:12 xbinop_forceint: dest:x src1:x src2:x len:4 xcast: dest:x src1:x len:4 clob:1 diff --git a/src/mono/mono/mini/mini-arm64.c b/src/mono/mono/mini/mini-arm64.c index d54b3137a0f77f..57b140565ff6b1 100644 --- a/src/mono/mono/mini/mini-arm64.c +++ b/src/mono/mono/mini/mini-arm64.c @@ -3396,6 +3396,27 @@ emit_move_return_value (MonoCompile *cfg, guint8 * code, MonoInst *ins) return code; } +static guint8* +emit_xextract (guint8* code, int width, int mode, int dreg, int sreg1) +{ + switch (mode) { + case SIMD_EXTR_IS_ANY_SET: + arm_neon_umaxv (code, width, TYPE_I8, FP_TEMP_REG, sreg1); + arm_neon_umov_b (code, dreg, FP_TEMP_REG, 0); + arm_lsrw(code, dreg, dreg, 7); // dreg contains 0xff for TRUE or 0x0 for FALSE, normalize to 0x1/0x0 + break; + case SIMD_EXTR_ARE_ALL_SET: + arm_neon_uminv (code, width, TYPE_I8, FP_TEMP_REG, sreg1); + arm_neon_umov_b (code, dreg, FP_TEMP_REG, 0); + arm_lsrw(code, dreg, dreg, 7); + break; + default: + g_assert_not_reached (); + } + + return code; +} + /* * emit_branch_island: * @@ -3822,6 +3843,9 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb) case OP_XZERO: arm_neon_eor_16b (code, dreg, dreg, dreg); break; + case OP_XEXTRACT: + code = emit_xextract (code, VREG_FULL, ins->inst_c0, dreg, sreg1); + break; /* ALU */ case OP_IADD: diff --git a/src/mono/mono/mini/mini-ops.h b/src/mono/mono/mini/mini-ops.h index 020e446a4bf785..1303bfebf9ff8d 100644 --- a/src/mono/mono/mini/mini-ops.h +++ b/src/mono/mono/mini/mini-ops.h @@ -1479,6 +1479,10 @@ MINI_OP(OP_XCOMPARE_SCALAR, "xcompare_scalar", XREG, XREG, XREG) MINI_OP(OP_XCOMPARE_FP, "xcompare_fp", XREG, XREG, XREG) MINI_OP(OP_XCOMPARE_FP_SCALAR, "xcompare_fp_scalar", XREG, XREG, XREG) +/* Extract from XREG into IREG. + * inst_c0 - specific instruction, one of SIMD_EXTR_... */ +MINI_OP(OP_XEXTRACT, "xextract", IREG, XREG, NONE) + /* * Generic SIMD operations, the rest of the JIT doesn't care about the exact operation. */ @@ -1486,6 +1490,7 @@ MINI_OP(OP_XBINOP, "xbinop", XREG, XREG, XREG) MINI_OP(OP_XBINOP_FORCEINT, "xbinop_forceint", XREG, XREG, XREG) MINI_OP(OP_XBINOP_SCALAR, "xbinop_scalar", XREG, XREG, XREG) MINI_OP(OP_XBINOP_BYSCALAR, "xbinop_byscalar", XREG, XREG, XREG) + /* inst_c0 contains an INTRINS_ enum, inst_c1 might contain additional data */ MINI_OP(OP_XOP, "xop", NONE, NONE, NONE) MINI_OP(OP_XOP_X_I, "xop_x_i", XREG, IREG, NONE) diff --git a/src/mono/mono/mini/mini.h b/src/mono/mono/mini/mini.h index 41a6a3b6d8e54f..943242eadb4940 100644 --- a/src/mono/mono/mini/mini.h +++ b/src/mono/mono/mini/mini.h @@ -2933,6 +2933,11 @@ enum { SIMD_PREFETCH_MODE_2, }; +enum { + SIMD_EXTR_IS_ANY_SET, + SIMD_EXTR_ARE_ALL_SET +}; + int mini_primitive_type_size (MonoTypeEnum type); MonoTypeEnum mini_get_simd_type_info (MonoClass *klass, guint32 *nelems); diff --git a/src/mono/mono/mini/simd-intrinsics.c b/src/mono/mono/mini/simd-intrinsics.c index 73121fc4a3668a..747e6b237b4b84 100644 --- a/src/mono/mono/mini/simd-intrinsics.c +++ b/src/mono/mono/mini/simd-intrinsics.c @@ -509,11 +509,18 @@ static MonoInst* emit_xequal (MonoCompile *cfg, MonoClass *klass, MonoInst *arg1, MonoInst *arg2) { #ifdef TARGET_ARM64 - int size = mono_class_value_size (klass, NULL); - if (size == 16) + if (!COMPILE_LLVM (cfg)) { + MonoTypeEnum elemt = get_underlying_type (m_class_get_this_arg (arg1->klass)); + MonoInst* cmp = emit_xcompare (cfg, arg1->klass, elemt, arg1, arg2); + MonoInst* ret = emit_simd_ins (cfg, mono_defaults.boolean_class, OP_XEXTRACT, cmp->dreg, -1); + ret->inst_c0 = SIMD_EXTR_ARE_ALL_SET; + ret->inst_c1 = mono_class_value_size (klass, NULL); + return ret; + } else if (mono_class_value_size (klass, NULL) == 16) { return emit_simd_ins (cfg, klass, OP_XEQUAL_ARM64_V128_FAST, arg1->dreg, arg2->dreg); - else + } else { return emit_simd_ins (cfg, klass, OP_XEQUAL, arg1->dreg, arg2->dreg); + } #else MonoInst *ins = emit_simd_ins (cfg, klass, OP_XEQUAL, arg1->dreg, arg2->dreg); if (!COMPILE_LLVM (cfg)) @@ -1201,9 +1208,9 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi return NULL; } - if (!strcmp (m_class_get_name (cfg->method->klass), "Vector256")) - return NULL; // TODO: Fix Vector256.WithUpper/WithLower - + if (!strcmp (m_class_get_name (cfg->method->klass), "Vector256") || !strcmp (m_class_get_name (cfg->method->klass), "Vector512")) + return NULL; + // FIXME: This limitation could be removed once everything here are supported by mini JIT on arm64 #ifdef TARGET_ARM64 if (!COMPILE_LLVM (cfg)) { @@ -1216,6 +1223,16 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi case SN_LessThanOrEqual: case SN_Negate: case SN_OnesComplement: + case SN_EqualsAny: + case SN_GreaterThanAny: + case SN_GreaterThanOrEqualAny: + case SN_LessThanAny: + case SN_LessThanOrEqualAny: + case SN_EqualsAll: + case SN_GreaterThanAll: + case SN_GreaterThanOrEqualAll: + case SN_LessThanAll: + case SN_LessThanOrEqualAll: case SN_Subtract: case SN_BitwiseAnd: case SN_BitwiseOr: @@ -1488,18 +1505,27 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi if (!is_element_type_primitive (fsig->params [0])) return NULL; MonoClass *arg_class = mono_class_from_mono_type_internal (fsig->params [0]); - switch (id) { - case SN_Equals: - return emit_xcompare (cfg, klass, arg0_type, args [0], args [1]); - case SN_EqualsAll: - return emit_xequal (cfg, arg_class, args [0], args [1]); - case SN_EqualsAny: { - MonoInst *cmp_eq = emit_xcompare (cfg, arg_class, arg0_type, args [0], args [1]); - MonoInst *zero = emit_xzero (cfg, arg_class); - return emit_not_xequal (cfg, arg_class, cmp_eq, zero); + if (id == SN_Equals) + return emit_xcompare (cfg, klass, arg0_type, args [0], args [1]); + + if (COMPILE_LLVM (cfg)) { + switch (id) { + case SN_EqualsAll: + return emit_xequal (cfg, arg_class, args [0], args [1]); + case SN_EqualsAny: { + MonoInst *cmp_eq = emit_xcompare (cfg, arg_class, arg0_type, args [0], args [1]); + MonoInst *zero = emit_xzero (cfg, arg_class); + return emit_not_xequal (cfg, arg_class, cmp_eq, zero); + } } - default: g_assert_not_reached (); + } else { + MonoInst* cmp = emit_xcompare (cfg, arg_class, arg0_type, args [0], args [1]); + MonoInst* ret = emit_simd_ins (cfg, mono_defaults.boolean_class, OP_XEXTRACT, cmp->dreg, -1); + ret->inst_c0 = (id == SN_EqualsAll) ? SIMD_EXTR_ARE_ALL_SET : SIMD_EXTR_IS_ANY_SET; + ret->inst_c1 = mono_class_value_size (klass, NULL); + return ret; } + g_assert_not_reached (); } case SN_ExtractMostSignificantBits: { if (!is_element_type_primitive (fsig->params [0]) || type_enum_is_float (arg0_type)) @@ -1567,34 +1593,40 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi fsig->ret->type == MONO_TYPE_BOOLEAN && mono_metadata_type_equal (fsig->params [0], fsig->params [1])); - MonoInst *cmp = emit_xcompare_for_intrinsic (cfg, klass, id, arg0_type, args [0], args [1]); - MonoClass *arg_class = mono_class_from_mono_type_internal (fsig->params [0]); - + gboolean is_all = FALSE; switch (id) { case SN_GreaterThanAll: case SN_GreaterThanOrEqualAll: case SN_LessThanAll: - case SN_LessThanOrEqualAll: { - // for floating point numbers all ones is NaN and so - // they must be treated differently than integer types - if (type_enum_is_float (arg0_type)) { + case SN_LessThanOrEqualAll: + is_all = TRUE; + break; + } + + MonoClass *arg_class = mono_class_from_mono_type_internal (fsig->params [0]); + if (COMPILE_LLVM (cfg)) { + MonoInst *cmp = emit_xcompare_for_intrinsic (cfg, klass, id, arg0_type, args [0], args [1]); + if (is_all) { + // for floating point numbers all ones is NaN and so + // they must be treated differently than integer types + if (type_enum_is_float (arg0_type)) { + MonoInst *zero = emit_xzero (cfg, arg_class); + MonoInst *inverted_cmp = emit_xcompare (cfg, klass, arg0_type, cmp, zero); + return emit_xequal (cfg, arg_class, inverted_cmp, zero); + } + + MonoInst *ones = emit_xones (cfg, arg_class); + return emit_xequal (cfg, arg_class, cmp, ones); + } else { MonoInst *zero = emit_xzero (cfg, arg_class); - MonoInst *inverted_cmp = emit_xcompare (cfg, klass, arg0_type, cmp, zero); - return emit_xequal (cfg, arg_class, inverted_cmp, zero); + return emit_not_xequal (cfg, arg_class, cmp, zero); } - - MonoInst *ones = emit_xones (cfg, arg_class); - return emit_xequal (cfg, arg_class, cmp, ones); - } - case SN_GreaterThanAny: - case SN_GreaterThanOrEqualAny: - case SN_LessThanAny: - case SN_LessThanOrEqualAny: { - MonoInst *zero = emit_xzero (cfg, arg_class); - return emit_not_xequal (cfg, arg_class, cmp, zero); - } - default: - g_assert_not_reached (); + } else { + MonoInst* cmp = emit_xcompare_for_intrinsic (cfg, arg_class, id, arg0_type, args [0], args [1]); + MonoInst* ret = emit_simd_ins (cfg, mono_defaults.boolean_class, OP_XEXTRACT, cmp->dreg, -1); + ret->inst_c0 = is_all ? SIMD_EXTR_ARE_ALL_SET : SIMD_EXTR_IS_ANY_SET; + ret->inst_c1 = mono_class_value_size (klass, NULL); + return ret; } } case SN_Narrow: { @@ -1908,6 +1940,8 @@ emit_vector64_vector128_t (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSign case SN_op_BitwiseAnd: case SN_op_BitwiseOr: case SN_op_ExclusiveOr: + case SN_op_Equality: + case SN_op_Inequality: break; default: return NULL; From c1acb35ce2b90f241ccdf3ead79544516c673e5f Mon Sep 17 00:00:00 2001 From: SwapnilGaikwad Date: Tue, 21 Mar 2023 12:39:01 +0000 Subject: [PATCH 09/20] Replace a load with cheaper mov instruction when possible (#83458) --- src/coreclr/jit/emitarm64.cpp | 84 +++++++++++++++++++++++++++++++++-- src/coreclr/jit/emitarm64.h | 11 +++++ 2 files changed, 91 insertions(+), 4 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index ce39079d467ae1..cc865da38e7484 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -16183,7 +16183,7 @@ bool emitter::IsRedundantLdStr( // ins - The instruction code // reg1Attr - The emit attribute for register 1 // reg1 - Register 1 -// reg2 - Encoded register 2 +// reg2 - Register 2 // imm - Immediate offset, prior to scaling by operand size // size - Operand size // fmt - Instruction format @@ -16194,9 +16194,6 @@ bool emitter::IsRedundantLdStr( bool emitter::ReplaceLdrStrWithPairInstr( instruction ins, emitAttr reg1Attr, regNumber reg1, regNumber reg2, ssize_t imm, emitAttr size, insFormat fmt) { - // Register 2 needs conversion to unencoded value. - reg2 = encodingZRtoSP(reg2); - RegisterOrder optimizationOrder = IsOptimizableLdrStrWithPair(ins, reg1, reg2, imm, size, fmt); if (optimizationOrder != eRO_none) @@ -16367,4 +16364,83 @@ emitter::RegisterOrder emitter::IsOptimizableLdrStrWithPair( return optimisationOrder; } +//----------------------------------------------------------------------------------- +// IsOptimizableLdrToMov: Check if it is possible to optimize a second "ldr" +// instruction into a cheaper "mov" instruction. +// +// Examples: ldr w1, [x20, #0x10] +// ldr w2, [x20, #0x10] => mov w1, w2 +// +// Arguments: +// ins - The instruction code +// reg1 - Register 1 number +// reg2 - Register 2 number +// imm - Immediate offset, prior to scaling by operand size +// size - Operand size +// fmt - Instruction format +// +// Return Value: +// true - Optimization of the second instruction is possible +// +bool emitter::IsOptimizableLdrToMov( + instruction ins, regNumber reg1, regNumber reg2, ssize_t imm, emitAttr size, insFormat fmt) +{ + if (ins != INS_ldr) + { + // This instruction is not an "ldr" instruction. + return false; + } + + if (ins != emitLastIns->idIns()) + { + // Not successive "ldr" instructions. + return false; + } + + regNumber prevReg1 = emitLastIns->idReg1(); + regNumber prevReg2 = emitLastIns->idReg2(); + insFormat lastInsFmt = emitLastIns->idInsFmt(); + emitAttr prevSize = emitLastIns->idOpSize(); + ssize_t prevImm = emitGetInsSC(emitLastIns); + + if ((reg2 != prevReg2) || !isGeneralRegisterOrSP(reg2)) + { + // The "register 2" should be same as previous instruction and + // should either be a general register or stack pointer. + return false; + } + + if (prevImm != imm) + { + // Then we are loading from a different immediate offset. + return false; + } + + if (!isGeneralRegister(reg1) || !isGeneralRegister(prevReg1)) + { + // Either register 1 or previous register 1 is not a general register + // or the zero register, so we cannot optimise. + return false; + } + + if (lastInsFmt != fmt) + { + // The formats of the two instructions differ. + return false; + } + + if (prevReg1 == prevReg2) + { + // Then the previous load overwrote the register that we are indexing against. + return false; + } + + if (prevSize != size) + { + // Operand sizes differ. + return false; + } + + return true; +} #endif // defined(TARGET_ARM64) diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index d82f7dd833a1fa..7c8fac3e772c35 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -130,6 +130,7 @@ RegisterOrder IsOptimizableLdrStrWithPair( instruction ins, regNumber reg1, regNumber reg2, ssize_t imm, emitAttr size, insFormat fmt); bool ReplaceLdrStrWithPairInstr( instruction ins, emitAttr reg1Attr, regNumber reg1, regNumber reg2, ssize_t imm, emitAttr size, insFormat fmt); +bool IsOptimizableLdrToMov(instruction ins, regNumber reg1, regNumber reg2, ssize_t imm, emitAttr size, insFormat fmt); // Try to optimize a Ldr or Str with an alternative instruction. inline bool OptimizeLdrStr(instruction ins, @@ -156,6 +157,9 @@ inline bool OptimizeLdrStr(instruction ins, return true; } + // Register 2 needs conversion to unencoded value for following optimisation checks. + reg2 = encodingZRtoSP(reg2); + // If the previous instruction was a matching load/store, then try to replace it instead of emitting. // Don't do this if either instruction had a local variable. if ((emitLastIns->idIns() == ins) && !localVar && !emitLastIns->idIsLclVar() && @@ -164,6 +168,13 @@ inline bool OptimizeLdrStr(instruction ins, return true; } + // If we have a second LDR instruction from the same source, then try to replace it with a MOV. + if (IsOptimizableLdrToMov(ins, reg1, reg2, imm, size, fmt)) + { + emitIns_Mov(INS_mov, reg1Attr, reg1, emitLastIns->idReg1(), true); + return true; + } + return false; } From 5896cbc81a82b78b22bbab9c5abb694b0a2e2db0 Mon Sep 17 00:00:00 2001 From: Steve Pfister Date: Tue, 21 Mar 2023 10:14:30 -0400 Subject: [PATCH 10/20] [tvOS] Bump to new OSX 13 AppleTV queue (#83272) --- eng/pipelines/libraries/helix-queues-setup.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/eng/pipelines/libraries/helix-queues-setup.yml b/eng/pipelines/libraries/helix-queues-setup.yml index 0a0461ef35a348..41e1eb4207fbe9 100644 --- a/eng/pipelines/libraries/helix-queues-setup.yml +++ b/eng/pipelines/libraries/helix-queues-setup.yml @@ -125,11 +125,11 @@ jobs: # tvOS devices - ${{ if in(parameters.platform, 'tvos_arm64') }}: - # split traffic for runtime-extra-platforms (which mostly runs on rolling builds) + # if necessary, you can split traffic between queues this way for PR's and rolling builds - ${{ if ne(parameters.jobParameters.isExtraPlatforms, true) }}: - - OSX.1015.Amd64.AppleTV.Open + - OSX.13.Amd64.AppleTV.Open - ${{ if eq(parameters.jobParameters.isExtraPlatforms, true) }}: - - OSX.1100.Amd64.AppleTV.Open + - OSX.13.Amd64.AppleTV.Open # windows x64 - ${{ if eq(parameters.platform, 'windows_x64') }}: From bb3dc9c34a60721130fc7e6c6545b3e7d2fd34c7 Mon Sep 17 00:00:00 2001 From: Jan Dupej <109523496+jandupej@users.noreply.github.com> Date: Tue, 21 Mar 2023 15:49:00 +0100 Subject: [PATCH 11/20] [mono][jit] Add vector horizontal sums and ToScalar on arm64. (#83675) * SN_Sum operation on arm64. Fixed dup. Replaced addv, addp, faddp with their generalized variants. Added OP_EXTRACTx opcodes to arm64 codegen. Added horizontal sums. * Fixed smov macro. Added SN_ToScalar. Fixed code style. * Fixed vector sums of nint/nuint. * Temporarily disable intrinsics, until all are implemented. --- src/mono/mono/arch/arm64/arm64-codegen.h | 38 ++++------------ src/mono/mono/arch/arm64/codegen-test.c | 5 ++ src/mono/mono/mini/cpu-arm64.mdesc | 7 +++ src/mono/mono/mini/mini-arm64.c | 58 ++++++++++++++++++++++++ src/mono/mono/mini/simd-arm64.h | 3 ++ src/mono/mono/mini/simd-intrinsics.c | 20 ++++++-- 6 files changed, 97 insertions(+), 34 deletions(-) diff --git a/src/mono/mono/arch/arm64/arm64-codegen.h b/src/mono/mono/arch/arm64/arm64-codegen.h index b348d274e60251..2f4eb469b32e72 100644 --- a/src/mono/mono/arch/arm64/arm64-codegen.h +++ b/src/mono/mono/arch/arm64/arm64-codegen.h @@ -1122,15 +1122,12 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_ins_g(p, type, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b0, (((index) << 1) | 0b1) << (type), 0b0011, (rd), (rn)) #define arm_neon_ins_e(p, type, rd, rn, indexd, indexs) arm_neon_cpy_opcode ((p), 0b1, 0b1, (((indexd) << 1) | 0b1) << (type), (indexs) << (type), (rd), (rn)) -// Specific opcodes: -#define arm_neon_dup_e_8b(p, rd, rn, index) arm_neon_cpy_opcode ((p), VREG_LOW, 0b0, 0b00001 | ((index) << 1), 0b0000, (rd), (rn)) -#define arm_neon_dup_e_16b(p, rd, rn, index) arm_neon_cpy_opcode ((p), VREG_FULL, 0b0, 0b00001 | ((index) << 1), 0b0000, (rd), (rn)) -#define arm_neon_dup_e_4h(p, rd, rn, index) arm_neon_cpy_opcode ((p), VREG_LOW, 0b0, 0b00010 | ((index) << 2), 0b0000, (rd), (rn)) -#define arm_neon_dup_e_8h(p, rd, rn, index) arm_neon_cpy_opcode ((p), VREG_FULL, 0b0, 0b00010 | ((index) << 2), 0b0000, (rd), (rn)) -#define arm_neon_dup_e_2s(p, rd, rn, index) arm_neon_cpy_opcode ((p), VREG_LOW, 0b0, 0b00100 | ((index) << 3), 0b0000, (rd), (rn)) -#define arm_neon_dup_e_4s(p, rd, rn, index) arm_neon_cpy_opcode ((p), VREG_FULL, 0b0, 0b00100 | ((index) << 3), 0b0000, (rd), (rn)) -#define arm_neon_dup_e_2d(p, rd, rn, index) arm_neon_cpy_opcode ((p), VREG_FULL, 0b0, 0b00100 | ((index) << 4), 0b0000, (rd), (rn)) +#define arm_neon_smov(p, type, rd, rn, index) arm_neon_cpy_opcode ((p), (type == TYPE_I32) ? 0b1 : 0b0, 0b0, (0b00001 << (type)) | ((index) << ((type) + 1)), 0b0101, (rd), (rn)) +#define arm_neon_umov(p, type, rd, rn, index) arm_neon_cpy_opcode ((p), (type == TYPE_I64) ? 0b1 : 0b0, 0b0, (0b00001 << (type)) | ((index) << ((type) + 1)), 0b0111, (rd), (rn)) +#define arm_neon_dup_e(p, width, type, rd, rn, index) arm_neon_cpy_opcode ((p), (width), 0b0, (0b00001 << (type)) | ((index) << ((type)+1)), 0b0000, (rd), (rn)) +#define arm_neon_fdup_e(p, width, type, rd, rn, index) arm_neon_dup_e ((p), (width), (type) + TYPE_I32, (rd), (rn), (index)) +// Specific opcodes: #define arm_neon_dup_g_8b(p, rd, rn) arm_neon_cpy_opcode ((p), VREG_LOW, 0b0, 0b00001, 0b0001, (rd), (rn)) #define arm_neon_dup_g_16b(p, rd, rn) arm_neon_cpy_opcode ((p), VREG_FULL, 0b0, 0b00001, 0b0001, (rd), (rn)) #define arm_neon_dup_g_4h(p, rd, rn) arm_neon_cpy_opcode ((p), VREG_LOW, 0b0, 0b00010, 0b0001, (rd), (rn)) @@ -1141,15 +1138,13 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_smov_b(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00001 | ((index) << 1), 0b0101, (rd), (rn)) #define arm_neon_smov_h(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00010 | ((index) << 2), 0b0101, (rd), (rn)) -#define arm_neon_smov_s(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00100 | ((index) << 3), 0b0101, (rd), (rn)) -#define arm_neon_smov_d(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b0, 0b01000 | ((index) << 4), 0b0101, (rd), (rn)) +#define arm_neon_smov_s(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b0, 0b00100 | ((index) << 3), 0b0101, (rd), (rn)) #define arm_neon_umov_b(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00001 | ((index) << 1), 0b0111, (rd), (rn)) #define arm_neon_umov_h(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00010 | ((index) << 2), 0b0111, (rd), (rn)) #define arm_neon_umov_s(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b0, 0b0, 0b00100 | ((index) << 3), 0b0111, (rd), (rn)) #define arm_neon_umov_d(p, rd, rn, index) arm_neon_cpy_opcode ((p), 0b1, 0b0, 0b01000 | ((index) << 4), 0b0111, (rd), (rn)) - /* NEON :: 3-register same FP16 */ // TODO @@ -1572,6 +1567,7 @@ arm_encode_arith_imm (int imm, guint32 *shift) /* NEON :: across lanes */ #define arm_neon_xln_opcode(p, q, u, size, opcode, rd, rn) arm_neon_opcode_2reg ((p), (q), 0b00001110001100000000100000000000 | (u) << 29 | (size) << 22 | (opcode) << 12, (rd), (rn)) +#define arm_neon_addv(p, width, type, rd, rn) arm_neon_xln_opcode ((p), (width), 0b0, (type), 0b11011, (rd), (rn)) #define arm_neon_umaxv(p, width, type, rd, rn) arm_neon_xln_opcode ((p), (width), 0b1, (type), 0b01010, (rd), (rn)) #define arm_neon_uminv(p, width, type, rd, rn) arm_neon_xln_opcode ((p), (width), 0b1, (type), 0b11010, (rd), (rn)) @@ -1595,12 +1591,6 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_sminv_8h(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b0, SIZE_2, 0b11010, (rd), (rn)) #define arm_neon_sminv_4s(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b0, SIZE_4, 0b11010, (rd), (rn)) -#define arm_neon_addv_8b(p, rd, rn) arm_neon_xln_opcode ((p), VREG_LOW, 0b0, SIZE_1, 0b11011, (rd), (rn)) -#define arm_neon_addv_16b(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b0, SIZE_1, 0b11011, (rd), (rn)) -#define arm_neon_addv_4h(p, rd, rn) arm_neon_xln_opcode ((p), VREG_LOW, 0b0, SIZE_2, 0b11011, (rd), (rn)) -#define arm_neon_addv_8h(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b0, SIZE_2, 0b11011, (rd), (rn)) -#define arm_neon_addv_4s(p, rd, rn) arm_neon_xln_opcode ((p), VREG_FULL, 0b0, SIZE_4, 0b11011, (rd), (rn)) - // some fp16 opcodes here: fmaxnmv, fmaxv, fminnmv, fminv #define arm_neon_uaddlv_8b(p, rd, rn) arm_neon_xln_opcode ((p), VREG_LOW, 0b1, SIZE_1, 0b00011, (rd), (rn)) @@ -1809,6 +1799,7 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_cmeq(p, width, type, rd, rn, rm) arm_neon_3svec_opcode ((p), (width), 0b1, (type), 0b10001, (rd), (rn), (rm)) #define arm_neon_cmhi(p, width, type, rd, rn, rm) arm_neon_3svec_opcode ((p), (width), 0b1, (type), 0b00110, (rd), (rn), (rm)) #define arm_neon_cmhs(p, width, type, rd, rn, rm) arm_neon_3svec_opcode ((p), (width), 0b1, (type), 0b00111, (rd), (rn), (rm)) +#define arm_neon_addp(p, width, type, rd, rn, rm) arm_neon_3svec_opcode ((p), (width), 0b0, (type), 0b10111, (rd), (rn), (rm)) // Generalized macros for float ops: // width - determines if full register or its lower half is used one of {VREG_LOW, VREG_FULL} @@ -1822,6 +1813,7 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_fcmeq(p, width, type, rd, rn, rm) arm_neon_3svec_opcode ((p), (width), 0b0, (type), 0b11100, (rd), (rn), (rm)) #define arm_neon_fcmge(p, width, type, rd, rn, rm) arm_neon_3svec_opcode ((p), (width), 0b1, (type), 0b11100, (rd), (rn), (rm)) #define arm_neon_fcmgt(p, width, type, rd, rn, rm) arm_neon_3svec_opcode ((p), (width), 0b1, 0b10 | (type), 0b11100, (rd), (rn), (rm)) +#define arm_neon_faddp(p, width, type, rd, rn, rm) arm_neon_3svec_opcode ((p), (width), 0b1, (type), 0b11010, (rd), (rn), (rm)) // Generalized macros for bitwise ops: // width - determines if full register or its lower half is used one of {VREG_LOW, VREG_FULL} @@ -1991,14 +1983,6 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_sqdmulh_2s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_LOW, 0b0, SIZE_4, 0b10110, (rd), (rn), (rm)) #define arm_neon_sqdmulh_4s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b0, SIZE_4, 0b10110, (rd), (rn), (rm)) -#define arm_neon_addp_8b(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_LOW, 0b0, SIZE_1, 0b10111, (rd), (rn), (rm)) -#define arm_neon_addp_16b(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b0, SIZE_1, 0b10111, (rd), (rn), (rm)) -#define arm_neon_addp_4h(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_LOW, 0b0, SIZE_2, 0b10111, (rd), (rn), (rm)) -#define arm_neon_addp_8h(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b0, SIZE_2, 0b10111, (rd), (rn), (rm)) -#define arm_neon_addp_2s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_LOW, 0b0, SIZE_4, 0b10111, (rd), (rn), (rm)) -#define arm_neon_addp_4s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b0, SIZE_4, 0b10111, (rd), (rn), (rm)) -#define arm_neon_addp_2d(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b0, SIZE_8, 0b10111, (rd), (rn), (rm)) - #define arm_neon_fmaxnm_2s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_LOW, 0b0, SIZE_1, 0b11000, (rd), (rn), (rm)) #define arm_neon_fmaxnm_4s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b0, SIZE_1, 0b11000, (rd), (rn), (rm)) #define arm_neon_fmaxnm_2d(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b0, SIZE_2, 0b11000, (rd), (rn), (rm)) @@ -2234,10 +2218,6 @@ arm_encode_arith_imm (int imm, guint32 *shift) #define arm_neon_fmaxnmp_4s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b1, SIZE_1, 0b11000, (rd), (rn), (rm)) #define arm_neon_fmaxnmp_2d(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b1, SIZE_2, 0b11000, (rd), (rn), (rm)) -#define arm_neon_faddp_2s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_LOW, 0b1, SIZE_1, 0b11010, (rd), (rn), (rm)) -#define arm_neon_faddp_4s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b1, SIZE_1, 0b11010, (rd), (rn), (rm)) -#define arm_neon_faddp_2d(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b1, SIZE_2, 0b11010, (rd), (rn), (rm)) - #define arm_neon_fmul_2s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_LOW, 0b1, SIZE_1, 0b11011, (rd), (rn), (rm)) #define arm_neon_fmul_4s(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b1, SIZE_1, 0b11011, (rd), (rn), (rm)) #define arm_neon_fmul_2d(p, rd, rn, rm) arm_neon_3svec_opcode ((p), VREG_FULL, 0b1, SIZE_2, 0b11011, (rd), (rn), (rm)) diff --git a/src/mono/mono/arch/arm64/codegen-test.c b/src/mono/mono/arch/arm64/codegen-test.c index b89adf007f2eea..b50a6432cf252a 100644 --- a/src/mono/mono/arch/arm64/codegen-test.c +++ b/src/mono/mono/arch/arm64/codegen-test.c @@ -477,6 +477,11 @@ main (int argc, char *argv []) arm_neon_ins_e (code, TYPE_I8, ARMREG_R0, ARMREG_R1, 1, 5); // insert v1.b[5] into v0.b[1] arm_neon_ins_e (code, TYPE_I32, ARMREG_R0, ARMREG_R1, 1, 2); // insert v1.s[2] into v0.s[1] + // pairwise and horizontal adds + arm_neon_addv (code, VREG_FULL, TYPE_I8, ARMREG_R0, ARMREG_R1); + arm_neon_addp (code, VREG_FULL, TYPE_I8, ARMREG_R0, ARMREG_R1, ARMREG_R2); + arm_neon_faddp (code, VREG_FULL, TYPE_F32, ARMREG_R0, ARMREG_R1, ARMREG_R2); + for (i = 0; i < code - buf; ++i) printf (".byte %d\n", buf [i]); printf ("\n"); diff --git a/src/mono/mono/mini/cpu-arm64.mdesc b/src/mono/mono/mini/cpu-arm64.mdesc index b6f8f23a64c257..39716de51ccfb3 100644 --- a/src/mono/mono/mini/cpu-arm64.mdesc +++ b/src/mono/mono/mini/cpu-arm64.mdesc @@ -506,6 +506,13 @@ ones_complement: dest:x src1:x len:4 xextract: dest:i src1:x len:12 xbinop_forceint: dest:x src1:x src2:x len:4 xcast: dest:x src1:x len:4 clob:1 +extract_i1: dest:i src1:x len:4 +extract_i2: dest:i src1:x len:4 +extract_i4: dest:i src1:x len:4 +extract_i8: dest:i src1:x len:4 +extract_r4: dest:f src1:x len:4 +extract_r8: dest:f src1:x len:4 +arm64_xaddv: dest:x src1:x len:8 generic_class_init: src1:a len:44 clob:c gc_safe_point: src1:i len:12 clob:c diff --git a/src/mono/mono/mini/mini-arm64.c b/src/mono/mono/mini/mini-arm64.c index 57b140565ff6b1..55c26e0e4f35eb 100644 --- a/src/mono/mono/mini/mini-arm64.c +++ b/src/mono/mono/mini/mini-arm64.c @@ -27,6 +27,7 @@ #include #include #include +#include "llvm-intrinsics-types.h" #include "interp/interp.h" @@ -35,6 +36,7 @@ #define PARENTHESIZE(...) (__VA_ARGS__) #define EXPAND_FUN(m, ...) EXPAND(m PARENTHESIZE(__VA_ARGS__)) #define OPFMT_WDSS _w, dreg, sreg1, sreg2 +#define OPFMT_WTDS _w, _t, dreg, sreg1 #define OPFMT_WTDSS _w, _t, dreg, sreg1, sreg2 #define OPFMT_WTDSS_REV _w, _t, dreg, sreg2, sreg1 #define _UNDEF(...) g_assert_not_reached () @@ -3466,6 +3468,12 @@ is_type_float_macro (MonoTypeEnum type) return (type == MONO_TYPE_R4 || type == MONO_TYPE_R8); } +static gboolean +is_type_unsigned_macro (MonoTypeEnum type) +{ + return (type == MONO_TYPE_U1 || type == MONO_TYPE_U2 || type == MONO_TYPE_U4 || type == MONO_TYPE_U8); +} + static int get_vector_size_macro (MonoInst *ins) { @@ -3736,6 +3744,56 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb) case OP_XCAST: break; + case OP_EXTRACT_I1: + case OP_EXTRACT_I2: + case OP_EXTRACT_I4: + case OP_EXTRACT_I8: { + const int t = get_type_size_macro (ins->inst_c1); + // smov is not defined for i64 + if (is_type_unsigned_macro (ins->inst_c1) || t == TYPE_I64) { + arm_neon_umov (code, t, ins->dreg, ins->sreg1, ins->inst_c0); + } else { + arm_neon_smov (code, t, ins->dreg, ins->sreg1, ins->inst_c0); + } + break; + } + case OP_EXTRACT_R4: + case OP_EXTRACT_R8: + if (ins->dreg != ins->sreg1 || ins->inst_c0 != 0) { + const int t = get_type_size_macro (ins->inst_c1); + // Technically, this broadcasts element #inst_c0 to all dest XREG elements; whereas it should + // set the FREG to the said element. Since FREG and XREG pool is the same on arm64 and the rest + // of the F/XREG is ignored in FREG mode, this operation remains valid. + arm_neon_fdup_e (code, VREG_FULL, t, ins->dreg, ins->sreg1, ins->inst_c0); + } + break; + case OP_ARM64_XADDV: { + switch (ins->inst_c0) { + case INTRINS_AARCH64_ADV_SIMD_FADDV: + if (ins->inst_c1 == MONO_TYPE_R8) { + arm_neon_faddp (code, VREG_FULL, TYPE_F64, ins->dreg, ins->sreg1, ins->sreg1); + } else if (ins->inst_c1 == MONO_TYPE_R4) { + arm_neon_faddp (code, VREG_FULL, TYPE_F32, ins->dreg, ins->sreg1, ins->sreg1); + arm_neon_faddp (code, VREG_FULL, TYPE_F32, ins->dreg, ins->dreg, ins->dreg); + } else { + g_assert_not_reached (); + } + break; + + case INTRINS_AARCH64_ADV_SIMD_UADDV: + case INTRINS_AARCH64_ADV_SIMD_SADDV: + if (get_type_size_macro (ins->inst_c1) == TYPE_I64) + arm_neon_addp (code, VREG_FULL, TYPE_I64, ins->dreg, ins->sreg1, ins->sreg1); + else + g_assert_not_reached (); // remaining int types are handled through the codegen table + break; + + default: + g_assert_not_reached (); + } + break; + } + /* BRANCH */ case OP_BR: mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_B); diff --git a/src/mono/mono/mini/simd-arm64.h b/src/mono/mono/mini/simd-arm64.h index 4af1a21892d4c7..21836b05103b12 100644 --- a/src/mono/mono/mini/simd-arm64.h +++ b/src/mono/mono/mini/simd-arm64.h @@ -62,3 +62,6 @@ SIMD_OP (128, OP_XBINOP, OP_FMIN, WTDSS, _UNDEF, SIMD_OP (128, OP_XBINOP_FORCEINT, XBINOP_FORCEINT_AND, WDSS, arm_neon_and, arm_neon_and, arm_neon_and, arm_neon_and, arm_neon_and, arm_neon_and) SIMD_OP (128, OP_XBINOP_FORCEINT, XBINOP_FORCEINT_OR, WDSS, arm_neon_orr, arm_neon_orr, arm_neon_orr, arm_neon_orr, arm_neon_orr, arm_neon_orr) SIMD_OP (128, OP_XBINOP_FORCEINT, XBINOP_FORCEINT_XOR, WDSS, arm_neon_eor, arm_neon_eor, arm_neon_eor, arm_neon_eor, arm_neon_eor, arm_neon_eor) +SIMD_OP (128, OP_ARM64_XADDV, INTRINS_AARCH64_ADV_SIMD_UADDV, WTDS, arm_neon_addv, arm_neon_addv, arm_neon_addv, _SKIP, _UNDEF, _UNDEF) +SIMD_OP (128, OP_ARM64_XADDV, INTRINS_AARCH64_ADV_SIMD_SADDV, WTDS, arm_neon_addv, arm_neon_addv, arm_neon_addv, _SKIP, _UNDEF, _UNDEF) +SIMD_OP (128, OP_ARM64_XADDV, INTRINS_AARCH64_ADV_SIMD_FADDV, WTDS, _UNDEF, _UNDEF, _UNDEF, _UNDEF, _SKIP, _SKIP) \ No newline at end of file diff --git a/src/mono/mono/mini/simd-intrinsics.c b/src/mono/mono/mini/simd-intrinsics.c index 747e6b237b4b84..168fff859c935c 100644 --- a/src/mono/mono/mini/simd-intrinsics.c +++ b/src/mono/mono/mini/simd-intrinsics.c @@ -620,15 +620,23 @@ emit_sum_vector (MonoCompile *cfg, MonoType *vector_type, MonoTypeEnum element_t return ins; } - MonoInst *ins = emit_simd_ins (cfg, vector_class, OP_ARM64_XADDV, arg->dreg, -1); - + MonoInst *sum = emit_simd_ins (cfg, vector_class, OP_ARM64_XADDV, arg->dreg, -1); if (type_enum_is_float (element_type)) { - ins->inst_c0 = INTRINS_AARCH64_ADV_SIMD_FADDV; + sum->inst_c0 = INTRINS_AARCH64_ADV_SIMD_FADDV; + sum->inst_c1 = element_type; } else { - ins->inst_c0 = type_enum_is_unsigned (element_type) ? INTRINS_AARCH64_ADV_SIMD_UADDV : INTRINS_AARCH64_ADV_SIMD_SADDV; + sum->inst_c0 = type_enum_is_unsigned (element_type) ? INTRINS_AARCH64_ADV_SIMD_UADDV : INTRINS_AARCH64_ADV_SIMD_SADDV; + sum->inst_c1 = element_type; } - return ins; + if (COMPILE_LLVM (cfg)) { + return sum; + } else { + MonoInst *ins = emit_simd_ins (cfg, vector_class, type_to_extract_op (element_type), sum->dreg, -1); + ins->inst_c0 = 0; + ins->inst_c1 = element_type; + return ins; + } } #endif #ifdef TARGET_WASM @@ -1250,6 +1258,8 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi case SN_AsUInt64: case SN_Max: case SN_Min: + case SN_Sum: + case SN_ToScalar: break; default: return NULL; From 93dda3be9ce619a0ca58f46ef78f21266aaf42a2 Mon Sep 17 00:00:00 2001 From: Ilona Tomkowicz <32700855+ilonatommy@users.noreply.github.com> Date: Tue, 21 Mar 2023 15:53:21 +0100 Subject: [PATCH 12/20] [browser] Fix encoding problem when publishing with AOT (#83510) * Fix. * Regex approach is not necessary. * Fix encoding on Windows. * Fixed build error. * Reverted unnecessary changes. Blocked relink with unicode. * Revet + nit. * Applied @kg's review. --- .../Wasm.Build.Tests/BuildPublishTests.cs | 53 +++++++++++-------- .../wasm/Wasm.Build.Tests/BuildTestBase.cs | 20 +++---- .../NativeRebuildTestsBase.cs | 8 --- src/tasks/AotCompilerTask/MonoAOTCompiler.cs | 33 +++++++++++- 4 files changed, 72 insertions(+), 42 deletions(-) diff --git a/src/mono/wasm/Wasm.Build.Tests/BuildPublishTests.cs b/src/mono/wasm/Wasm.Build.Tests/BuildPublishTests.cs index dd05980878209e..c56308cc97fd9f 100644 --- a/src/mono/wasm/Wasm.Build.Tests/BuildPublishTests.cs +++ b/src/mono/wasm/Wasm.Build.Tests/BuildPublishTests.cs @@ -25,7 +25,7 @@ public BuildPublishTests(ITestOutputHelper output, SharedBuildPerTestClassFixtur [BuildAndRun(host: RunHost.Chrome, aot: false, config: "Debug")] public void BuildThenPublishNoAOT(BuildArgs buildArgs, RunHost host, string id) { - string projectName = $"build_publish_{buildArgs.Config}{s_unicodeChar}"; + string projectName = GetTestProjectPath(prefix: "build_publish", config: buildArgs.Config); buildArgs = buildArgs with { ProjectName = projectName }; buildArgs = ExpandBuildArgs(buildArgs); @@ -73,7 +73,7 @@ void Run() => RunAndTestWasmApp( [BuildAndRun(host: RunHost.Chrome, aot: true, config: "Debug")] public void BuildThenPublishWithAOT(BuildArgs buildArgs, RunHost host, string id) { - string projectName = $"build_publish_{buildArgs.Config}"; + string projectName = GetTestProjectPath(prefix: "build_publish", config: buildArgs.Config); buildArgs = buildArgs with { ProjectName = projectName }; buildArgs = ExpandBuildArgs(buildArgs, extraProperties: "<_WasmDevel>true"); @@ -108,23 +108,25 @@ public void BuildThenPublishWithAOT(BuildArgs buildArgs, RunHost host, string id _testOutput.WriteLine($"{Environment.NewLine}Publishing with no changes ..{Environment.NewLine}"); + // FIXME: relinking for paths with unicode does not work: + // [ActiveIssue("https://github.com/dotnet/runtime/issues/83497")] // relink by default for Release+publish - (_, output) = BuildProject(buildArgs, - id: id, - new BuildProjectOptions( - DotnetWasmFromRuntimePack: false, - CreateProject: false, - Publish: true, - UseCache: false, - Label: "first_publish")); - - var publishStat = StatFiles(pathsDict.Select(kvp => kvp.Value.fullPath)); - Assert.True(publishStat["pinvoke.o"].Exists); - Assert.True(publishStat[$"{mainDll}.bc"].Exists); - CheckOutputForNativeBuild(expectAOT: true, expectRelinking: false, buildArgs, output); - CompareStat(firstBuildStat, publishStat, pathsDict.Values); - - Run(expectAOT: true); + // (_, output) = BuildProject(buildArgs, + // id: id, + // new BuildProjectOptions( + // DotnetWasmFromRuntimePack: false, + // CreateProject: false, + // Publish: true, + // UseCache: false, + // Label: "first_publish")); + + // var publishStat = StatFiles(pathsDict.Select(kvp => kvp.Value.fullPath)); + // Assert.True(publishStat["pinvoke.o"].Exists); + // Assert.True(publishStat[$"{mainDll}.bc"].Exists); + // CheckOutputForNativeBuild(expectAOT: true, expectRelinking: false, buildArgs, output); + // CompareStat(firstBuildStat, publishStat, pathsDict.Values); + + // Run(expectAOT: true); // second build (_, output) = BuildProject(buildArgs, @@ -142,7 +144,9 @@ public void BuildThenPublishWithAOT(BuildArgs buildArgs, RunHost host, string id // no native files changed pathsDict.UpdateTo(unchanged: true); - CompareStat(publishStat, secondBuildStat, pathsDict.Values); + // FIXME: elinking for paths with unicode does not work: + // [ActiveIssue("https://github.com/dotnet/runtime/issues/83497")] + // CompareStat(publishStat, secondBuildStat, pathsDict.Values); void Run(bool expectAOT) => RunAndTestWasmApp( buildArgs with { AOT = expectAOT }, @@ -152,11 +156,14 @@ void Run(bool expectAOT) => RunAndTestWasmApp( void CheckOutputForNativeBuild(bool expectAOT, bool expectRelinking, BuildArgs buildArgs, string buildOutput) { - AssertSubstring($"{buildArgs.ProjectName}.dll -> {buildArgs.ProjectName}.dll.bc", buildOutput, expectAOT); - AssertSubstring($"{buildArgs.ProjectName}.dll.bc -> {buildArgs.ProjectName}.dll.o", buildOutput, expectAOT); + AssertSubstring($"{buildArgs.ProjectName}.dll -> {buildArgs.ProjectName}.dll.bc", buildOutput, contains: expectAOT); + AssertSubstring($"{buildArgs.ProjectName}.dll.bc -> {buildArgs.ProjectName}.dll.o", buildOutput, contains: expectAOT); - AssertSubstring("pinvoke.c -> pinvoke.o", buildOutput, expectRelinking || expectAOT); + AssertSubstring("pinvoke.c -> pinvoke.o", buildOutput, contains: expectRelinking || expectAOT); } - + + + // appending UTF-8 char makes sure project build&publish under all types of paths is supported + string GetTestProjectPath(string prefix, string config) => $"{prefix}_{config}_{s_unicodeChar}"; } } diff --git a/src/mono/wasm/Wasm.Build.Tests/BuildTestBase.cs b/src/mono/wasm/Wasm.Build.Tests/BuildTestBase.cs index 19ddf2943d6d25..6dc3e5e525468d 100644 --- a/src/mono/wasm/Wasm.Build.Tests/BuildTestBase.cs +++ b/src/mono/wasm/Wasm.Build.Tests/BuildTestBase.cs @@ -195,16 +195,8 @@ protected string RunAndTestWasmApp(BuildArgs buildArgs, useWasmConsoleOutput: useWasmConsoleOutput ); - if (buildArgs.AOT) - { - Assert.Contains("AOT: image 'System.Private.CoreLib' found.", output); - Assert.Contains($"AOT: image '{buildArgs.ProjectName}' found.", output); - } - else - { - Assert.DoesNotContain("AOT: image 'System.Private.CoreLib' found.", output); - Assert.DoesNotContain($"AOT: image '{buildArgs.ProjectName}' found.", output); - } + AssertSubstring("AOT: image 'System.Private.CoreLib' found.", output, contains: buildArgs.AOT); + AssertSubstring($"AOT: image '{buildArgs.ProjectName}' found.", output, contains: buildArgs.AOT); if (test != null) test(output); @@ -1204,6 +1196,14 @@ public static int Main() RunHost.NodeJS => new NodeJSHostRunner(), _ => new BrowserHostRunner(), }; + + protected void AssertSubstring(string substring, string full, bool contains) + { + if (contains) + Assert.Contains(substring, full); + else + Assert.DoesNotContain(substring, full); + } } public record BuildArgs(string ProjectName, diff --git a/src/mono/wasm/Wasm.Build.Tests/NativeRebuildTests/NativeRebuildTestsBase.cs b/src/mono/wasm/Wasm.Build.Tests/NativeRebuildTests/NativeRebuildTestsBase.cs index c9b4e2bc666020..aac389bde66bc2 100644 --- a/src/mono/wasm/Wasm.Build.Tests/NativeRebuildTests/NativeRebuildTestsBase.cs +++ b/src/mono/wasm/Wasm.Build.Tests/NativeRebuildTests/NativeRebuildTestsBase.cs @@ -186,13 +186,5 @@ internal void CompareStat(IDictionary oldStat, IDictionary _symbolNameFixups = new(); + private bool ProcessAndValidateArguments() { if (!File.Exists(CompilerBinaryPath)) @@ -1025,7 +1027,7 @@ private bool GenerateAotModulesTable(IEnumerable assemblies, string[] if (!TryGetAssemblyName(asmPath, out string? assemblyName)) return false; - string symbolName = assemblyName.Replace ('.', '_').Replace ('-', '_').Replace(' ', '_'); + string symbolName = FixupSymbolName(assemblyName); symbols.Add($"mono_aot_module_{symbolName}_info"); } @@ -1160,6 +1162,35 @@ private static List ConvertAssembliesDictToOrderedList(ConcurrentDict return outItems; } + private string FixupSymbolName(string name) + { + if (_symbolNameFixups.TryGetValue(name, out string? fixedName)) + return fixedName; + + UTF8Encoding utf8 = new(); + byte[] bytes = utf8.GetBytes(name); + StringBuilder sb = new(); + + foreach (byte b in bytes) + { + if ((b >= (byte)'0' && b <= (byte)'9') || + (b >= (byte)'a' && b <= (byte)'z') || + (b >= (byte)'A' && b <= (byte)'Z') || + (b == (byte)'_')) + { + sb.Append((char)b); + } + else + { + sb.Append('_'); + } + } + + fixedName = sb.ToString(); + _symbolNameFixups[name] = fixedName; + return fixedName; + } + internal sealed class PrecompileArguments { public PrecompileArguments(string ResponseFilePath, IDictionary EnvironmentVariables, string WorkingDir, ITaskItem AOTAssembly, IList ProxyFiles) From edb161ab06ddc69d27aee2c0e990a60221ebbe92 Mon Sep 17 00:00:00 2001 From: Milos Kotlar Date: Tue, 21 Mar 2023 16:50:34 +0100 Subject: [PATCH 13/20] [mono][aot] Load AOT module of a container assembly using assembly name (#83711) * Load AOT module of a container assembly using assembly name * Use mono_image_init to init the image * Implement mono_loader_lock on load_container_amodule * Avoid recursive invocation by setting container_assm_name to NULL --- src/mono/mono/mini/aot-runtime.c | 55 +++++++++++++++++++------------- 1 file changed, 33 insertions(+), 22 deletions(-) diff --git a/src/mono/mono/mini/aot-runtime.c b/src/mono/mono/mini/aot-runtime.c index d60b926835006a..46e0aff893914f 100644 --- a/src/mono/mono/mini/aot-runtime.c +++ b/src/mono/mono/mini/aot-runtime.c @@ -2433,35 +2433,46 @@ mono_aot_init (void) /* * load_container_amodule: * - * Load the container assembly and its AOT image. + * Load AOT module of a container assembly */ static void load_container_amodule (MonoAssemblyLoadContext *alc) { - ERROR_DECL (error); - + // If container_amodule loaded, don't lock the runtime if (!container_assm_name || container_amodule) return; - char *local_ref = container_assm_name; - container_assm_name = NULL; - MonoImageOpenStatus status = MONO_IMAGE_OK; - MonoAssemblyOpenRequest req; - gchar *dll = g_strdup_printf ( "%s.dll", local_ref); - /* - * Don't fire managed assembly load events whose execution - * might require this module to be already loaded. - */ - mono_assembly_request_prepare_open (&req, alc); - req.request.no_managed_load_event = TRUE; - MonoAssembly *assm = mono_assembly_request_open (dll, &req, &status); - if (!assm) { - gchar *exe = g_strdup_printf ("%s.exe", local_ref); - assm = mono_assembly_request_open (exe, &req, &status); - } - g_assert (assm); - load_aot_module (alc, assm, NULL, error); - container_amodule = assm->image->aot_module; + mono_loader_lock (); + // There might be several threads that passed the first check + // Adding another check to ensure single load of a container assembly due to race condition + if (!container_amodule) { + ERROR_DECL (error); + + // This method is recursively invoked within the same thread during AOT module loads + // It avoids recursive invocation by setting container_assm_name to NULL + char *local_ref = container_assm_name; + container_assm_name = NULL; + + // Create a fake MonoAssembly/MonoImage to retrieve its AOT module. + // Container MonoAssembly/MonoImage shouldn't be used during the runtime. + MonoAssembly *assm = g_new0 (MonoAssembly, 1); + assm->image = g_new0 (MonoImage, 1); + assm->image->dynamic = 0; + assm->image->alc = alc; + assm->aname.name = local_ref; + + mono_image_init (assm->image); + MonoAotFileInfo* info = (MonoAotFileInfo *)g_hash_table_lookup (static_aot_modules, assm->aname.name); + assm->image->guid = (char*)info->assembly_guid; + mono_assembly_addref (assm); + + load_aot_module(alc, assm, NULL, error); + mono_memory_barrier (); + g_assert (assm->image->aot_module); + container_amodule = assm->image->aot_module; + } + + mono_loader_unlock (); } static gboolean From 92f8abcd2f23fb64bb8a1c74346578c308ff6aab Mon Sep 17 00:00:00 2001 From: Bill Holmes Date: Wed, 22 Mar 2023 13:20:02 -0400 Subject: [PATCH 14/20] Revert "Formatting license files to match Unity legal standardization (#45)" This reverts commit 8c08cd3e4e357aff66e6222322c5a70165a1273b. --- Directory.Build.props | 4 +- LICENSE.md => LICENSE.TXT | 0 Microsoft Patent Promise.TXT => PATENTS.TXT | 6 +- ...arty Notices.md => THIRD-PARTY-NOTICES.TXT | 557 +++++------------- .../pkg/sfx/installers/dotnet-host.proj | 4 +- unity/CITools/BuildDriver/Program.cs | 2 +- 6 files changed, 145 insertions(+), 428 deletions(-) rename LICENSE.md => LICENSE.TXT (100%) rename Microsoft Patent Promise.TXT => PATENTS.TXT (92%) rename Third Party Notices.md => THIRD-PARTY-NOTICES.TXT (85%) diff --git a/Directory.Build.props b/Directory.Build.props index d9829f1d0981cc..60a661e66ca444 100644 --- a/Directory.Build.props +++ b/Directory.Build.props @@ -274,11 +274,11 @@ microsoft,dotnetframework true $([MSBuild]::NormalizePath('$(LibrariesProjectRoot)', 'Microsoft.NETCore.Platforms', 'src', 'runtime.json')) - $(MSBuildThisFileDirectory)LICENSE.md + $(MSBuildThisFileDirectory)LICENSE.TXT MIT false $(CopyrightNetFoundation) - $(MSBuildThisFileDirectory)Third Party Notices.md + $(MSBuildThisFileDirectory)THIRD-PARTY-NOTICES.TXT https://go.microsoft.com/fwlink/?LinkID=799421 $(MSBuildProjectName.Contains('Private')) diff --git a/LICENSE.md b/LICENSE.TXT similarity index 100% rename from LICENSE.md rename to LICENSE.TXT diff --git a/Microsoft Patent Promise.TXT b/PATENTS.TXT similarity index 92% rename from Microsoft Patent Promise.TXT rename to PATENTS.TXT index b28f0255d9669c..695305bf6abbb9 100644 --- a/Microsoft Patent Promise.TXT +++ b/PATENTS.TXT @@ -1,8 +1,4 @@ -This patent promise is contained in the PATENTS.TXT file of https://github.com/dotnet/runtime and is included here for your reference: - ----- - -Microsoft Patent Promise for .NET Libraries and Runtime Components +Microsoft Patent Promise for .NET Libraries and Runtime Components Microsoft Corporation and its affiliates ("Microsoft") promise not to assert any .NET Patents against you for making, using, selling, offering for sale, diff --git a/Third Party Notices.md b/THIRD-PARTY-NOTICES.TXT similarity index 85% rename from Third Party Notices.md rename to THIRD-PARTY-NOTICES.TXT index 84bfb1b787fd4b..f2a43f5250e830 100644 --- a/Third Party Notices.md +++ b/THIRD-PARTY-NOTICES.TXT @@ -1,65 +1,37 @@ -This package contains third-party software components governed by the license(s) indicated below: ---------- +.NET Runtime uses third-party libraries or other resources that may be +distributed under licenses different than the .NET Runtime software. -Component Name: ASP.NET +In the event that we accidentally failed to list a required notice, please +bring it to our attention. Post an issue or email us: -License Type: Apache License, Version 2.0. + dotnet@microsoft.com -Copyright © .NET Foundation. All rights reserved. +The attached notices are provided for information only. -``` -The MIT License (MIT) - -Copyright (c) .NET Foundation and Contributors - -All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. -``` ---------- +License notice for ASP.NET +------------------------------- -Component Name: Slicing-by-8 +Copyright (c) .NET Foundation. All rights reserved. +Licensed under the Apache License, Version 2.0. -License Type: BSD +Available at +https://github.com/dotnet/aspnetcore/blob/main/LICENSE.txt -Copyright © 2004-2006 Intel Corporation - All Rights Reserved +License notice for Slicing-by-8 +------------------------------- http://sourceforge.net/projects/slicing-by-8/ -``` -Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. +Copyright (c) 2004-2006 Intel Corporation - All Rights Reserved -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` ---------- -Component Name: Unicode data +This software program is licensed subject to the BSD License, available at +http://www.opensource.org/licenses/bsd-license.html. -License Type: Unicode -Copyright © 1991-2020 Unicode, Inc. All rights reserved. +License notice for Unicode data +------------------------------- -``` https://www.unicode.org/license.html Copyright © 1991-2022 Unicode, Inc. All rights reserved. @@ -93,19 +65,13 @@ Except as contained in this notice, the name of a copyright holder shall not be used in advertising or otherwise to promote the sale, use or other dealings in these Data Files or Software without prior written authorization of the copyright holder. -``` ---------- - -Component Name: Zlib -License Type: Zlib - -Copyright © 1995-2017 Jean-loup Gailly and Mark Adler +License notice for Zlib +----------------------- https://github.com/madler/zlib https://zlib.net/zlib_license.html -``` /* zlib.h -- interface of the 'zlib' general purpose compression library version 1.2.12, March 27th, 2022 @@ -131,19 +97,16 @@ https://zlib.net/zlib_license.html jloup@gzip.org madler@alumni.caltech.edu */ -``` ---------- - -Component Name: Mono -License Type: MIT - -Copyright © .NET Foundation Contributors +License notice for Mono +------------------------------- http://www.mono-project.com/docs/about-mono/ +Copyright (c) .NET Foundation Contributors + MIT License -``` + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the Software), to deal in the Software without restriction, including without limitation the rights @@ -161,31 +124,20 @@ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -License notice for Mono -``` ---------- - -Component Name: International Organization for Standardization -License Type: [Provide license type, i.e. "MIT", "Apache 2.0"] +License notice for International Organization for Standardization +----------------------------------------------------------------- -Copyright © 1986 International Organization for Standardization - -``` Portions (C) International Organization for Standardization 1986: Permission to copy in any form is granted for use with conforming SGML systems and applications as defined in ISO 8879, provided this notice is included in all copies. -``` ---------- - -Component Name: Intel -License Type: Intel +License notice for Intel +------------------------ -Copyright © 2004-2006 Intel Corporation - All Rights Reserved +"Copyright (c) 2004-2006 Intel Corporation - All Rights Reserved -``` Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -206,20 +158,12 @@ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` ---------- -Component Name: Xamarin and Novell - -License Type: Xamarin and Novell - -Copyright © 2015 Xamarin, Inc -Copyright © 2011 Novell, Inc +License notice for Xamarin and Novell +------------------------------------- -http://www.xamarin.com -http://www.novell.com +Copyright (c) 2015 Xamarin, Inc (http://www.xamarin.com) -``` Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights @@ -237,8 +181,9 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` -``` + +Copyright (c) 2011 Novell, Inc (http://www.novell.com) + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights @@ -257,13 +202,9 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- - -Component Name: W3C +Third party notice for W3C +-------------------------- -License Type: W3C -``` "W3C SOFTWARE AND DOCUMENT NOTICE AND LICENSE Status: This license takes effect 13 May, 2015. This work is being provided by the copyright holders under the following license. @@ -277,16 +218,12 @@ Disclaimers THIS WORK IS PROVIDED "AS IS," AND COPYRIGHT HOLDERS MAKE NO REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO, WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE OR THAT THE USE OF THE SOFTWARE OR DOCUMENT WILL NOT INFRINGE ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS. COPYRIGHT HOLDERS WILL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF ANY USE OF THE SOFTWARE OR DOCUMENT. The name and trademarks of copyright holders may NOT be used in advertising or publicity pertaining to the work without specific, written prior permission. Title to copyright in this work will at all times remain with copyright holders." -``` ---------- - -Component Name: Bit Twiddling Hacks -License Type: ?????? +License notice for Bit Twiddling Hacks +-------------------------------------- -Copyright © 1997-2005 Sean Eron Anderson (aggregate collection) +Bit Twiddling Hacks -``` By Sean Eron Anderson seander@cs.stanford.edu @@ -296,18 +233,10 @@ descriptions are © 1997-2005 Sean Eron Anderson. The code and descriptions are distributed in the hope that they will be useful, but WITHOUT ANY WARRANTY and without even the implied warranty of merchantability or fitness for a particular purpose. -``` ---------- - -Component Name: Brotli - -License Type: Brotli -Copyright © 2009, 2010, 2013-2016 by the Brotli Authors. -Copyright © 2011, Google Inc. -Copyright © 2015 The Chromium Authors. All rights reserved. +License notice for Brotli +-------------------------------------- -``` Copyright (c) 2009, 2010, 2013-2016 by the Brotli Authors. Permission is hereby granted, free of charge, to any person obtaining a copy @@ -327,8 +256,7 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` -``` + compress_fragment.c: Copyright (c) 2011, Google Inc. All rights reserved. @@ -358,8 +286,7 @@ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` -``` + decode_fuzzer.c: Copyright (c) 2015 The Chromium Authors. All rights reserved. @@ -388,18 +315,16 @@ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE." -``` ---------- -Component Name: Json.NET +License notice for Json.NET +------------------------------- -License Type: MIT +https://github.com/JamesNK/Newtonsoft.Json/blob/master/LICENSE.md -Copyright © 2007 James Newton-King +The MIT License (MIT) -https://github.com/JamesNK/Newtonsoft.Json/blob/master/LICENSE.md +Copyright (c) 2007 James Newton-King -``` Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to @@ -416,20 +341,16 @@ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- - -Component Name: vectorized base64 encoding / decoding -License Type: Unkown +License notice for vectorized base64 encoding / decoding +-------------------------------------------------------- -Copyright © 2005-2007, Nick Galbreath -Copyright © 2013-2017, Alfred Klomp -Copyright © 2015-2017, Wojciech Mula -Copyright © 2016-2017, Matthieu Darbois +Copyright (c) 2005-2007, Nick Galbreath +Copyright (c) 2013-2017, Alfred Klomp +Copyright (c) 2015-2017, Wojciech Mula +Copyright (c) 2016-2017, Matthieu Darbois All rights reserved. -``` Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -452,16 +373,10 @@ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` ---------- - -Component Name: RFC 3492 - -License Type: The Internet Society -Copyright © 2003 The Internet Society +License notice for RFC 3492 +--------------------------- -``` The punycode implementation is based on the sample code in RFC 3492 Copyright (C) The Internet Society (2003). All Rights Reserved. @@ -489,18 +404,10 @@ TASK FORCE DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTY THAT THE USE OF THE INFORMATION HEREIN WILL NOT INFRINGE ANY RIGHTS OR ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. -``` ---------- -Component Name: Algorithm from Internet Draft document "UUIDs and GUIDs" +License notice for Algorithm from Internet Draft document "UUIDs and GUIDs" +--------------------------------------------------------------------------- -License Type: Multiple - -Copyright © 1990- 1993, 1996 Open Software Foundation, Inc. -Copyright © 1989 by Hewlett-Packard Company, Palo Alto, Ca. & Digital Equipment Corporation, Maynard, Mass. -Copyright © 1997 The Internet Society. All Rights Reserved. - -``` Copyright (c) 1990- 1993, 1996 Open Software Foundation, Inc. Copyright (c) 1989 by Hewlett-Packard Company, Palo Alto, Ca. & Digital Equipment Corporation, Maynard, Mass. @@ -516,8 +423,7 @@ specific, written prior permission. Neither Open Software Foundation, Inc., Hewlett-Packard Company, Microsoft, nor Digital Equipment Corporation makes any representations about the suitability of this software for any purpose. -``` -``` + Copyright(C) The Internet Society 1997. All Rights Reserved. This document and translations of it may be copied and furnished to others, @@ -541,18 +447,15 @@ DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTY THAT THE USE OF THE INFORMATION HEREIN WILL NOT INFRINGE ANY RIGHTS OR ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. -``` ---------- - -Component Name: Algorithm from RFC 4122 - A Universally Unique IDentifier (UUID) URN Namespace -License Type: Multiple +License notice for Algorithm from RFC 4122 - +A Universally Unique IDentifier (UUID) URN Namespace +---------------------------------------------------- -Copyright © 1990- 1993, 1996 Open Software Foundation, Inc. -Copyright © 1989 by Hewlett-Packard Company, Palo Alto, Ca. & Digital Equipment Corporation, Maynard, Mass. -Copyright © 1998 Microsoft. - -``` +Copyright (c) 1990- 1993, 1996 Open Software Foundation, Inc. +Copyright (c) 1989 by Hewlett-Packard Company, Palo Alto, Ca. & +Digital Equipment Corporation, Maynard, Mass. +Copyright (c) 1998 Microsoft. To anyone who acknowledges that this file is provided "AS IS" without any express or implied warranty: permission to use, copy, modify, and distribute this file for any purpose is hereby @@ -565,16 +468,10 @@ without specific, written prior permission. Neither Open Software Foundation, Inc., Hewlett-Packard Company, Microsoft, nor Digital Equipment Corporation makes any representations about the suitability of this software for any purpose." -``` ---------- - -Component Name: The LLVM Compiler Infrastructure -License Type: Apache 2.0 License with LLVM exceptions +License notice for The LLVM Compiler Infrastructure +--------------------------------------------------- -https://llvm.org/docs/DeveloperPolicy.html#new-llvm-project-license-framework - -``` Developed by: LLVM Team @@ -609,39 +506,23 @@ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE. -``` ---------- - -Component Name: Bob Jenkins -License Type: Unknown +License notice for Bob Jenkins +------------------------------ -Copyright © 1996 Bob Jenkins - -``` By Bob Jenkins, 1996. bob_jenkins@burtleburtle.net. You may use this code any way you wish, private, educational, or commercial. It's free. -``` ---------- - -Component Name: Greg Parker -License Type: Unkown +License notice for Greg Parker +------------------------------ -Copyright © 2000 Greg Parker - -``` Greg Parker gparker@cs.stanford.edu December 2000 This code is in the public domain and may be copied or modified without permission. -``` ---------- - -Component Name: libunwind based code -License Type: MIT +License notice for libunwind based code +---------------------------------------- -``` Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including @@ -660,16 +541,10 @@ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- - -Component Name: Printing Floating-Point Numbers (Dragon4) -License Type: Unknown +License notice for Printing Floating-Point Numbers (Dragon4) +------------------------------------------------------------ -Copyright © 2014 Ryan Juckett - -``` /****************************************************************************** Copyright (c) 2014 Ryan Juckett http://www.ryanjuckett.com/ @@ -693,16 +568,10 @@ Copyright © 2014 Ryan Juckett 3. This notice may not be removed or altered from any source distribution. ******************************************************************************/ -``` ---------- - -Component Name: Printing Floating-point Numbers (Grisu3) -License Type: [Provide license type, i.e. "MIT", "Apache 2.0"] +License notice for Printing Floating-point Numbers (Grisu3) +----------------------------------------------------------- -Copyright © 2012 the V8 project authors. - -``` Copyright 2012 the V8 project authors. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are @@ -729,17 +598,14 @@ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` - ---------- - -Component Name: xxHash Library -License Type: BSD 2-Clause +License notice for xxHash +------------------------- -Copyright © 2012-2014, Yann Collet All rights reserved. +xxHash Library +Copyright (c) 2012-2014, Yann Collet +All rights reserved. -``` Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -760,19 +626,15 @@ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` ---------- - -Component Name: Berkeley SoftFloat Release 3e -License Type: Unknown - -Copyright © 2018 John R. Hauser +License notice for Berkeley SoftFloat Release 3e +------------------------------------------------ https://github.com/ucb-bar/berkeley-softfloat-3 https://github.com/ucb-bar/berkeley-softfloat-3/blob/master/COPYING.txt -``` +License for Berkeley SoftFloat Release 3e + John R. Hauser 2018 January 20 @@ -806,16 +668,10 @@ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` ---------- - -Component Name: xoshiro RNGs -License Type: Public Domain +License notice for xoshiro RNGs +-------------------------------- -http://creativecommons.org/publicdomain/zero/1.0/ - -``` Written in 2018 by David Blackman and Sebastiano Vigna (vigna@acm.org) To the extent possible under law, the author has dedicated all copyright @@ -823,20 +679,13 @@ and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty. See . -``` - ---------- -Component Name: fastmod +License for fastmod (https://github.com/lemire/fastmod) and ibm-fpgen (https://github.com/nigeltao/parse-number-fxx-test-data) +-------------------------------------- -License Type: Apache 2.0 + Copyright 2018 Daniel Lemire -Copyright © 2018 Daniel Lemire - -https://github.com/lemire/fastmod - -``` -Licensed under the Apache License, Version 2.0 (the "License"); + Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at @@ -847,18 +696,10 @@ Licensed under the Apache License, Version 2.0 (the "License"); WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -``` ---------- - -Component Name: sse4-strstr - -License Type: BSD 2-Clause -Copyright © 2008-2016, Wojciech Muła +License for sse4-strstr (https://github.com/WojciechMula/sse4-strstr) +-------------------------------------- -https://github.com/WojciechMula/sse4-strstr - -``` Copyright (c) 2008-2016, Wojciech Muła All rights reserved. @@ -884,39 +725,16 @@ https://github.com/WojciechMula/sse4-strstr LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` ---------- - -Component Name: ibm-fpgen - -License Type: Apache 2.0 - -Copyright © 2018 Daniel Lemire - -https://github.com/nigeltao/parse-number-fxx-test-data - -``` -Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -``` ---------- +License notice for The C++ REST SDK +----------------------------------- -Component Name: The C++ REST SDK +C++ REST SDK -License Type: MIT +The MIT License (MIT) -Copyright © Microsoft Corporation +Copyright (c) Microsoft Corporation -``` All rights reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of @@ -936,17 +754,16 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- +License notice for MessagePack-CSharp +------------------------------------- -Component Name: MessagePack-CSharp +MessagePack for C# -License Type: MIT +MIT License -Copyright © 2017 Yoshifumi Kawai +Copyright (c) 2017 Yoshifumi Kawai -``` Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights @@ -964,18 +781,12 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- -Component Name: lz4net - -License Type: BSD 2-Clause "Simplified" License - -Copyright © 2013-2017, Milosz Krajewski +License notice for lz4net +------------------------------------- -https://github.com/MiloszKrajewski/lz4net +lz4net -``` Copyright (c) 2013-2017, Milosz Krajewski All rights reserved. @@ -987,16 +798,10 @@ Redistributions of source code must retain the above copyright notice, this list Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` ---------- - -Component Name: Nerdbank.Streams - -License Type: MIT -Copyright © Andrew Arnott +License notice for Nerdbank.Streams +----------------------------------- -``` The MIT License (MIT) Copyright (c) Andrew Arnott @@ -1018,16 +823,10 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- -Component Name: RapidJSON +License notice for RapidJSON +---------------------------- -License Type: MIT - -Copyright © 2015 THL A29 Limited, a Tencent company, and Milo Yip. All rights reserved. - -``` Tencent is pleased to support the open source community by making RapidJSON available. Copyright (C) 2015 THL A29 Limited, a Tencent company, and Milo Yip. All rights reserved. @@ -1041,18 +840,12 @@ Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -``` ---------- - -Component Name: DirectX Math Library - -License Type: MIT -Copyright © 2011-2020 Microsoft Corp +License notice for DirectX Math Library +--------------------------------------- https://github.com/microsoft/DirectXMath/blob/master/LICENSE -``` The MIT License (MIT) Copyright (c) 2011-2020 Microsoft Corp @@ -1073,16 +866,10 @@ PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIG HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- +License notice for ldap4net +--------------------------- -Component Name: ldap4net - -License Type: MIT - -Copyright © 2018 Alexander Chermyanin -``` The MIT License (MIT) Copyright (c) 2018 Alexander Chermyanin @@ -1092,16 +879,10 @@ Permission is hereby granted, free of charge, to any person obtaining a copy of The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` - ---------- -Component Name: vectorized sorting code +License notice for vectorized sorting code +------------------------------------------ -License Type: MIT - -Copyright © 2020 Dan Shechter -``` MIT License Copyright (c) 2020 Dan Shechter @@ -1123,16 +904,10 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- - -Component Name: musl -License Type: MIT +License notice for musl +----------------------- -Copyright © 2005-2020 Rich Felker, et al. - -``` musl as a whole is licensed under the following standard MIT license: Copyright © 2005-2020 Rich Felker, et al. @@ -1155,29 +930,21 @@ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- -Component Name: "Faster Unsigned Division by Constants" -License Type: Public Domain +License notice for "Faster Unsigned Division by Constants" +------------------------------ -``` Reference implementations of computing and using the "magic number" approach to dividing by constants, including codegen instructions. The unsigned division incorporates the "round down" optimization per ridiculous_fish. This is free and unencumbered software. Any copyright is dedicated to the Public Domain. -``` ---------- -Component Name: mimalloc -License Type: MIT +License notice for mimalloc +----------------------------------- -Copyright © 2019 Microsoft Corporation, Daan Leijen - -``` MIT License Copyright (c) 2019 Microsoft Corporation, Daan Leijen @@ -1199,17 +966,9 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- - -ComponentName: License for remote stack unwind - -License Type: Apache License, Version 2.0. - -Copyright © 2019 LLVM Project -``` License for remote stack unwind (https://github.com/llvm/llvm-project/blob/main/lldb/source/Symbol/CompactUnwindInfo.cpp) +-------------------------------------- Copyright 2019 LLVM Project @@ -1225,15 +984,9 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -``` ---------- -Component Name: Apple header files - -License Type: Unknown - -Copyright © 1980, 1986, 1993 The Regents of the University of California. All rights reserved. +License notice for Apple header files +------------------------------------- -``` Copyright (c) 1980, 1986, 1993 The Regents of the University of California. All rights reserved. @@ -1264,14 +1017,10 @@ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` ---------- -Component Name: JavaScript queues - -License Type: Creative Commons +License notice for JavaScript queues +------------------------------------- -``` CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE LEGAL SERVICES. DISTRIBUTION OF THIS DOCUMENT DOES NOT CREATE AN ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES REGARDING THE USE OF THIS DOCUMENT OR THE INFORMATION OR WORKS PROVIDED HEREUNDER, AND DISCLAIMS LIABILITY FOR DAMAGES RESULTING FROM THE USE OF THIS DOCUMENT OR THE INFORMATION OR WORKS PROVIDED HEREUNDER. Statement of Purpose @@ -1295,6 +1044,7 @@ b. Affirmer offers the Work as-is and makes no representations or warranties of c. Affirmer disclaims responsibility for clearing rights of other persons that may apply to the Work or any use thereof, including without limitation any person's Copyright and Related Rights in the Work. Further, Affirmer disclaims responsibility for obtaining any necessary consents, permissions or other rights required for any use of the Work. d. Affirmer understands and acknowledges that Creative Commons is not a party to this document and has no duty or obligation with respect to this CC0 or use of the Work. + License notice for FastFloat algorithm ------------------------------------- MIT License @@ -1314,14 +1064,10 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -``` ---------- - -Component Name: MsQuic -License Type: MIT +License notice for MsQuic +-------------------------------------- -``` Copyright (c) Microsoft Corporation. Licensed under the MIT License. @@ -1353,16 +1099,7 @@ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -``` ---------- -Component Name: code from The Practice of Programming - -License Type: Unknown - -Copyright © 1999 Lucent Technologies - -``` License notice for code from The Practice of Programming ------------------------------- @@ -1372,29 +1109,14 @@ Excerpted from 'The Practice of Programming by Brian W. Kernighan and Rob Pike You may use this code for any purpose, as long as you leave the copyright notice and book citation attached. -``` ---------- - -Component Name: Euclidean Affine Functions and Applications to Calendar Algorithms - -License Type: Unknown -Copyright © 1999 Lucent Technologies - -``` -Copyright © 1999 Lucent Technologies +Notice for Euclidean Affine Functions and Applications to Calendar +Algorithms +------------------------------- Aspects of Date/Time processing based on algorithm described in "Euclidean Affine Functions and Applications to Calendar Algorithms", Cassio Neri and Lorenz Schneider. https://arxiv.org/pdf/2102.06959.pdf -``` ---------- - -Component Name:amd/aocl-libm-ose - -License Type: Unknown -Copyright © 2008-2020 Advanced Micro Devices, Inc. All rights reserved. -``` License notice for amd/aocl-libm-ose ------------------------------- @@ -1420,5 +1142,4 @@ BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DA OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. -``` \ No newline at end of file +POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/src/installer/pkg/sfx/installers/dotnet-host.proj b/src/installer/pkg/sfx/installers/dotnet-host.proj index 5595e81156c4c1..edf3f5bf753fe5 100644 --- a/src/installer/pkg/sfx/installers/dotnet-host.proj +++ b/src/installer/pkg/sfx/installers/dotnet-host.proj @@ -51,9 +51,9 @@ - - Date: Wed, 22 Mar 2023 13:34:22 -0400 Subject: [PATCH 15/20] Update to net8.0 in the Unity files --- unity/CITools/BuildDriver/BuildDriver.csproj | 2 +- .../UnityEmbedHost.Tests.csproj | 2 +- unity/coreclr-test/coreclr-test.csproj | 2 +- unity/embed_api_tests/main.cpp | 28 +++++++++---------- unity/forwarder-test/forwarder-test.csproj | 2 +- .../unity-embed-host/unity-embed-host.csproj | 2 +- 6 files changed, 19 insertions(+), 19 deletions(-) diff --git a/unity/CITools/BuildDriver/BuildDriver.csproj b/unity/CITools/BuildDriver/BuildDriver.csproj index 21e8152652dfa7..a22420ca392ca7 100644 --- a/unity/CITools/BuildDriver/BuildDriver.csproj +++ b/unity/CITools/BuildDriver/BuildDriver.csproj @@ -2,7 +2,7 @@ Exe - net7.0 + net8.0 enable enable preview diff --git a/unity/UnityEmbedHost.Tests/UnityEmbedHost.Tests.csproj b/unity/UnityEmbedHost.Tests/UnityEmbedHost.Tests.csproj index 86d091fbf1eccc..22c2e9eb1670f7 100644 --- a/unity/UnityEmbedHost.Tests/UnityEmbedHost.Tests.csproj +++ b/unity/UnityEmbedHost.Tests/UnityEmbedHost.Tests.csproj @@ -1,7 +1,7 @@ - net7.0 + net8.0 enable enable true diff --git a/unity/coreclr-test/coreclr-test.csproj b/unity/coreclr-test/coreclr-test.csproj index e3e48389a19a11..aa2b31f710cbae 100644 --- a/unity/coreclr-test/coreclr-test.csproj +++ b/unity/coreclr-test/coreclr-test.csproj @@ -3,7 +3,7 @@ library true - net7.0 + net8.0 false 0 diff --git a/unity/embed_api_tests/main.cpp b/unity/embed_api_tests/main.cpp index 6cb39d3335fad6..eea6e4dd6a0aba 100644 --- a/unity/embed_api_tests/main.cpp +++ b/unity/embed_api_tests/main.cpp @@ -568,9 +568,9 @@ TEST(type_forwarder_lookup_results_in_identical_class) { MonoClass *directLookup = GetClassHelper(kTestDLLNameSpace, kTestClassName); #if defined(_DEBUG) - std::string testDllPath = abs_path_from_file("../forwarder-test/bin/Debug/net7.0/forwarder-test.dll"); + std::string testDllPath = abs_path_from_file("../forwarder-test/bin/Debug/net8.0/forwarder-test.dll"); #else - std::string testDllPath = abs_path_from_file("../forwarder-test/bin/Release/net7.0/forwarder-test.dll"); + std::string testDllPath = abs_path_from_file("../forwarder-test/bin/Release/net8.0/forwarder-test.dll"); #endif MonoAssembly *forwarderAssembly = mono_domain_assembly_open (g_domain, testDllPath.c_str()); GET_AND_CHECK(forwarderImage, mono_assembly_get_image(forwarderAssembly)); @@ -2414,9 +2414,9 @@ void SetupMono(Mode mode) { g_Mode = mode; #if defined(_DEBUG) - std::string testDllPath = abs_path_from_file("../coreclr-test/bin/Debug/net7.0/coreclr-test.dll"); + std::string testDllPath = abs_path_from_file("../coreclr-test/bin/Debug/net8.0/coreclr-test.dll"); #else - std::string testDllPath = abs_path_from_file("../coreclr-test/bin/Release/net7.0/coreclr-test.dll"); + std::string testDllPath = abs_path_from_file("../coreclr-test/bin/Release/net8.0/coreclr-test.dll"); #endif std::string monoLibFolder; @@ -2426,44 +2426,44 @@ void SetupMono(Mode mode) #if defined(__APPLE__) #if defined(_DEBUG) #ifdef __aarch64__ - monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-arm64/Debug/runtimes/osx-arm64/lib/net7.0"); + monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-arm64/Debug/runtimes/osx-arm64/lib/net8.0"); g_monoDllPath = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-arm64/Debug/runtimes/osx-arm64/native/libcoreclr.dylib"); #else - monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-x64/Debug/runtimes/osx-x64/lib/net7.0"); + monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-x64/Debug/runtimes/osx-x64/lib/net8.0"); g_monoDllPath = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-x64/Debug/runtimes/osx-x64/native/libcoreclr.dylib"); #endif // __aarch64__ #else #ifdef __aarch64__ - monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-arm64/Release/runtimes/osx-arm64/lib/net7.0"); + monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-arm64/Release/runtimes/osx-arm64/lib/net8.0"); g_monoDllPath = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-arm64/Release/runtimes/osx-arm64/native/libcoreclr.dylib"); #else - monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-x64/Release/runtimes/osx-x64/lib/net7.0"); + monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-x64/Release/runtimes/osx-x64/lib/net8.0"); g_monoDllPath = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.osx-x64/Release/runtimes/osx-x64/native/libcoreclr.dylib"); #endif // __aarch64__ #endif #elif defined(__linux__) #if defined(_DEBUG) - monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.linux-x64/Debug/runtimes/linux-x64/lib/net7.0"); + monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.linux-x64/Debug/runtimes/linux-x64/lib/net8.0"); g_monoDllPath = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.linux-x64/Debug/runtimes/linux-x64/native/libcoreclr.so"); #else - monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.linux-x64/Release/runtimes/linux-x64/lib/net7.0"); + monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.linux-x64/Release/runtimes/linux-x64/lib/net8.0"); g_monoDllPath = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.linux-x64/Release/runtimes/linux-x64/native/libcoreclr.so"); #endif #elif defined(WIN32) #if defined(_DEBUG) #ifdef _M_AMD64 - monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x64/Debug/runtimes/win-x64/lib/net7.0"); + monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x64/Debug/runtimes/win-x64/lib/net8.0"); g_monoDllPath = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x64/Debug/runtimes/win-x64/native/coreclr.dll"); #else - monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x86/Debug/runtimes/win-x86/lib/net7.0"); + monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x86/Debug/runtimes/win-x86/lib/net8.0"); g_monoDllPath = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x86/Debug/runtimes/win-x86/native/coreclr.dll"); #endif #else #ifdef _M_AMD64 - monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x64/Release/runtimes/win-x64/lib/net7.0"); + monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x64/Release/runtimes/win-x64/lib/net8.0"); g_monoDllPath = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x64/Release/runtimes/win-x64/native/coreclr.dll"); #else - monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x86/Release/runtimes/win-x86/lib/net7.0"); + monoLibFolder = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x86/Release/runtimes/win-x86/lib/net8.0"); g_monoDllPath = abs_path_from_file("../../artifacts/bin/microsoft.netcore.app.runtime.win-x86/Release/runtimes/win-x86/native/coreclr.dll"); #endif #endif diff --git a/unity/forwarder-test/forwarder-test.csproj b/unity/forwarder-test/forwarder-test.csproj index 0f2e61ff740706..59e36058e35a31 100644 --- a/unity/forwarder-test/forwarder-test.csproj +++ b/unity/forwarder-test/forwarder-test.csproj @@ -3,7 +3,7 @@ library true - net7.0 + net8.0 false diff --git a/unity/unity-embed-host/unity-embed-host.csproj b/unity/unity-embed-host/unity-embed-host.csproj index ec5a4b9d7bdf16..f85dc152eff2b3 100644 --- a/unity/unity-embed-host/unity-embed-host.csproj +++ b/unity/unity-embed-host/unity-embed-host.csproj @@ -3,7 +3,7 @@ library true - net7.0 + net8.0 false true $(IntermediateOutputPath) From 759a329be83ddf7c3135189f5fe82409c6954fe9 Mon Sep 17 00:00:00 2001 From: Bill Holmes Date: Thu, 23 Mar 2023 12:40:33 -0400 Subject: [PATCH 16/20] Fixing Unity tests for Linux Casing on the platform name changed --- unity/CITools/BuildDriver/CoreCLR.cs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/unity/CITools/BuildDriver/CoreCLR.cs b/unity/CITools/BuildDriver/CoreCLR.cs index dfc70f53c118b0..503304d5cecc1d 100644 --- a/unity/CITools/BuildDriver/CoreCLR.cs +++ b/unity/CITools/BuildDriver/CoreCLR.cs @@ -68,7 +68,7 @@ private static void TestUnityPal(GlobalConfig gConfig) psi.Arguments = "clr.paltests"; Utils.RunProcess(psi, gConfig); - string osString = RuntimeInformation.IsOSPlatform(OSPlatform.OSX) ? "OSX" : "Linux"; + string osString = RuntimeInformation.IsOSPlatform(OSPlatform.OSX) ? "OSX" : "linux"; NPath paltests = Paths.Artifacts.Combine("bin", "coreclr", $"{osString}.{gConfig.Architecture}.Debug", "paltests"); psi.FileName = paltests.Combine("runpaltests.sh"); psi.Arguments = paltests; From c729824c7b16c46117ea81f3112a9ef5b33dea69 Mon Sep 17 00:00:00 2001 From: Bill Holmes Date: Wed, 22 Mar 2023 13:38:06 -0400 Subject: [PATCH 17/20] Get Frozen Segment working with the Unity NULL GC --- unity/unitygc/unitygc.cpp | 55 ++++++++++++++++++++++++++++++++++----- 1 file changed, 49 insertions(+), 6 deletions(-) diff --git a/unity/unitygc/unitygc.cpp b/unity/unitygc/unitygc.cpp index d8708bd7e77b5c..1a016c8dc60e8a 100644 --- a/unity/unitygc/unitygc.cpp +++ b/unity/unitygc/unitygc.cpp @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include "gcenv.base.h" @@ -36,6 +38,15 @@ static const char* sUnityGC = "UnityGC"; #define UNITYGC_EXPORT #endif +class heap_segment +{ +public: + uint8_t* allocated; + uint8_t* committed; + uint8_t* reserved; + uint8_t* mem; +}; + class GCHeap : public IGCHeap { public: @@ -365,7 +376,10 @@ class GCHeap : public IGCHeap // Returns true if this pointer points into a GC heap, false otherwise. virtual bool IsHeapPointer(void* object, bool small_heap_only = false) { - return m_pGlobalHeapStart <= object && object <= m_pGlobalHeapCurrent; + bool ret = m_pGlobalHeapStart <= object && object <= m_pGlobalHeapCurrent; + if (!ret) + return IsInFrozenSegment((Object*)object); + return ret; } // Return the generation that has been condemned by the current GC. @@ -674,26 +688,55 @@ class GCHeap : public IGCHeap =========================================================================== */ + std::vector m_segment_infos; + // Registers a frozen segment with the GC. virtual segment_handle RegisterFrozenSegment(segment_info *pseginfo) { - assert(0); - return NULL; - } + heap_segment * seg = (heap_segment*)malloc(sizeof(heap_segment)); + if (!seg) + { + return NULL; + } + + uint8_t* base_mem = (uint8_t*)pseginfo->pvMem; + seg->mem = base_mem + pseginfo->ibFirstObject; + seg->allocated = base_mem + pseginfo->ibAllocated; + seg->committed = base_mem + pseginfo->ibCommit; + seg->reserved = base_mem + pseginfo->ibReserved; + + m_segment_infos.push_back(seg); + return reinterpret_cast< segment_handle >(seg); + } // Unregisters a frozen segment. virtual void UnregisterFrozenSegment(segment_handle seg) { - assert(0); + heap_segment* sInfo = reinterpret_cast< heap_segment* >(seg); + auto foundItem = std::find(m_segment_infos.begin(), m_segment_infos.end(), sInfo); + assert(foundItem == m_segment_infos.end()); + m_segment_infos.erase(foundItem); + free(sInfo); } // Indicates whether an object is in a frozen segment. virtual bool IsInFrozenSegment(Object *object) { - assert(0); + for (auto item = m_segment_infos.begin(), __end = m_segment_infos.end(); item != __end; ++item) + { + if((*item)->mem <= ((uint8_t*)object) && (*item)->reserved >= ((uint8_t*)object)) + return true; + } return false; } + virtual void UpdateFrozenSegment(segment_handle seg, uint8_t* allocated, uint8_t* committed) + { + heap_segment* sInfo = reinterpret_cast< heap_segment* >(seg); + sInfo->committed = committed; + sInfo->allocated = allocated; + } + /* =========================================================================== Routines for informing the GC about which events are enabled. From 5522dd8d606a7f40e1908e24d68eb95eb4e0d4a1 Mon Sep 17 00:00:00 2001 From: Bill Holmes Date: Wed, 22 Mar 2023 15:05:16 -0400 Subject: [PATCH 18/20] Unity GC write barrier patch This is a temporary patch to allow our NULL GC to work with upstream changes. Check the upper bounds in JIT_WriteBarrier_PreGrow64 and JIT_WriteBarrier_WriteWatch_PreGrow64. We must remove this when we return to default coreclr gc. --- src/coreclr/clrdefinitions.cmake | 1 + .../vm/amd64/JitHelpers_FastWriteBarriers.asm | 23 +++++++++++ .../vm/amd64/jithelpers_fastwritebarriers.S | 35 +++++++++++++++++ src/coreclr/vm/amd64/jitinterfaceamd64.cpp | 38 +++++++++++++++++++ 4 files changed, 97 insertions(+) diff --git a/src/coreclr/clrdefinitions.cmake b/src/coreclr/clrdefinitions.cmake index e86061f14f3e2f..18a2676319d3d8 100644 --- a/src/coreclr/clrdefinitions.cmake +++ b/src/coreclr/clrdefinitions.cmake @@ -118,6 +118,7 @@ if(FEATURE_UNITY_EMBEDDING_INTERFACE) add_definitions(-DFEATURE_UNITY_ASSEMBLY_MEMORY_PATH) add_definitions(-DFEATURE_UNITY_MODULE_NUM_TYPEDEFS) add_definitions(-DFEATURE_UNITY_EXPLICIT_LAYOUT_INHERITANCE) + add_definitions(-DFEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH) endif() if(FEATURE_GDBJIT) add_definitions(-DFEATURE_GDBJIT) diff --git a/src/coreclr/vm/amd64/JitHelpers_FastWriteBarriers.asm b/src/coreclr/vm/amd64/JitHelpers_FastWriteBarriers.asm index 68ab221278442b..5b3a84c05896ff 100644 --- a/src/coreclr/vm/amd64/JitHelpers_FastWriteBarriers.asm +++ b/src/coreclr/vm/amd64/JitHelpers_FastWriteBarriers.asm @@ -56,6 +56,17 @@ PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_Lower nop ; padding for alignment of constant +ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + +PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_Upper + mov r8, 0F0F0F0F0F0F0F0F0h + + cmp rdx, r8 + jae Exit + + nop ; padding for alignment of constant +endif + PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_CardTable mov rax, 0F0F0F0F0F0F0F0F0h @@ -384,6 +395,18 @@ PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Lower ; Touch the card table entry, if not already dirty. shr rcx, 0Bh NOP_2_BYTE ; padding for alignment of constant + +ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + +PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Upper + mov r8, 0F0F0F0F0F0F0F0F0h + + cmp rdx, r8 + jae Exit + + nop ; padding for alignment of constant +endif + PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_CardTable mov rax, 0F0F0F0F0F0F0F0F0h cmp byte ptr [rcx + rax], 0FFh diff --git a/src/coreclr/vm/amd64/jithelpers_fastwritebarriers.S b/src/coreclr/vm/amd64/jithelpers_fastwritebarriers.S index f987751bdcb358..15978a7fb82039 100644 --- a/src/coreclr/vm/amd64/jithelpers_fastwritebarriers.S +++ b/src/coreclr/vm/amd64/jithelpers_fastwritebarriers.S @@ -32,6 +32,23 @@ PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_Lower nop // padding for alignment of constant +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + +PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_Upper + movabs r8, 0xF0F0F0F0F0F0F0F0 + + cmp rsi, r8 + +#ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES + .byte 0x73, 0x4b +#else + .byte 0x73, 0x2b +#endif + // jae Exit_PreGrow64 + + nop // padding for alignment of constant +#endif + PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_CardTable movabs rax, 0xF0F0F0F0F0F0F0F0 @@ -415,6 +432,24 @@ PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Lower // Touch the card table entry, if not already dirty. shr rdi, 0x0B NOP_2_BYTE // padding for alignment of constant + +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + +PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Upper + movabs r10, 0xF0F0F0F0F0F0F0F0 + + cmp rsi, r10 + +#ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES + .byte 0x73, 0x3b +#else + .byte 0x73, 0x2b +#endif + // jae Exit_WriteWatch_PreGrow64 + + nop // padding for alignment of constant +#endif + PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_CardTable movabs rax, 0xF0F0F0F0F0F0F0F0 cmp byte ptr [rdi + rax], 0xFF diff --git a/src/coreclr/vm/amd64/jitinterfaceamd64.cpp b/src/coreclr/vm/amd64/jitinterfaceamd64.cpp index 08d5e9493f6c22..1e2efafb42701c 100644 --- a/src/coreclr/vm/amd64/jitinterfaceamd64.cpp +++ b/src/coreclr/vm/amd64/jitinterfaceamd64.cpp @@ -26,6 +26,9 @@ EXTERN_C void JIT_WriteBarrier_End(); EXTERN_C void JIT_WriteBarrier_PreGrow64(Object **dst, Object *ref); EXTERN_C void JIT_WriteBarrier_PreGrow64_Patch_Label_Lower(); +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH +EXTERN_C void JIT_WriteBarrier_PreGrow64_Patch_Label_Upper(); +#endif EXTERN_C void JIT_WriteBarrier_PreGrow64_Patch_Label_CardTable(); #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES EXTERN_C void JIT_WriteBarrier_PreGrow64_Patch_Label_CardBundleTable(); @@ -79,6 +82,9 @@ EXTERN_C void JIT_WriteBarrier_Bit_Region64_End(); EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64(Object **dst, Object *ref); EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_WriteWatchTable(); EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Lower(); +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH +EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Upper(); +#endif EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_CardTable(); #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_CardBundleTable(); @@ -172,9 +178,15 @@ void WriteBarrierManager::Validate() #endif pLowerBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_Lower, 2); +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + pUpperBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_Upper, 2); +#endif pCardTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_CardTable, 2); _ASSERTE_ALL_BUILDS((reinterpret_cast(pLowerBoundImmediate) & 0x7) == 0); +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + _ASSERTE_ALL_BUILDS((reinterpret_cast(pUpperBoundImmediate) & 0x7) == 0); +#endif _ASSERTE_ALL_BUILDS((reinterpret_cast(pCardTableImmediate) & 0x7) == 0); #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES @@ -239,10 +251,16 @@ void WriteBarrierManager::Validate() pWriteWatchTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_WriteWatchTable, 2); pLowerBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_Lower, 2); +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + pUpperBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_Upper, 2); +#endif pCardTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_CardTable, 2); _ASSERTE_ALL_BUILDS((reinterpret_cast(pWriteWatchTableImmediate) & 0x7) == 0); _ASSERTE_ALL_BUILDS((reinterpret_cast(pLowerBoundImmediate) & 0x7) == 0); +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + _ASSERTE_ALL_BUILDS((reinterpret_cast(pUpperBoundImmediate) & 0x7) == 0); +#endif _ASSERTE_ALL_BUILDS((reinterpret_cast(pCardTableImmediate) & 0x7) == 0); #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES @@ -433,11 +451,17 @@ int WriteBarrierManager::ChangeWriteBarrierTo(WriteBarrierType newWriteBarrier, case WRITE_BARRIER_PREGROW64: { m_pLowerBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_Lower, 2); +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + m_pUpperBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_Upper, 2); +#endif m_pCardTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_CardTable, 2); // Make sure that we will be bashing the right places (immediates should be hardcoded to 0x0f0f0f0f0f0f0f0f0). _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pLowerBoundImmediate); _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pCardTableImmediate); +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pUpperBoundImmediate); +#endif #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES m_pCardBundleTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_CardBundleTable, 2); @@ -529,11 +553,17 @@ int WriteBarrierManager::ChangeWriteBarrierTo(WriteBarrierType newWriteBarrier, { m_pWriteWatchTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_WriteWatchTable, 2); m_pLowerBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_Lower, 2); +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + m_pUpperBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_Upper, 2); +#endif m_pCardTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_CardTable, 2); // Make sure that we will be bashing the right places (immediates should be hardcoded to 0x0f0f0f0f0f0f0f0f0). _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pWriteWatchTableImmediate); _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pLowerBoundImmediate); +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pUpperBoundImmediate); +#endif _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pCardTableImmediate); #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES @@ -788,6 +818,12 @@ int WriteBarrierManager::UpdateEphemeralBounds(bool isRuntimeSuspended) case WRITE_BARRIER_WRITE_WATCH_BYTE_REGIONS64: case WRITE_BARRIER_WRITE_WATCH_BIT_REGIONS64: #endif // FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP +#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH + case WRITE_BARRIER_PREGROW64: +#ifdef FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP + case WRITE_BARRIER_WRITE_WATCH_PREGROW64: +#endif // FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP +#endif // FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH { // Change immediate if different from new g_ephermeral_high. if (*(UINT64*)m_pUpperBoundImmediate != (size_t)g_ephemeral_high) @@ -797,11 +833,13 @@ int WriteBarrierManager::UpdateEphemeralBounds(bool isRuntimeSuspended) stompWBCompleteActions |= SWB_ICACHE_FLUSH; } } +#ifndef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH FALLTHROUGH; case WRITE_BARRIER_PREGROW64: #ifdef FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP case WRITE_BARRIER_WRITE_WATCH_PREGROW64: #endif // FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP +#endif // FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH { // Change immediate if different from new g_ephermeral_low. if (*(UINT64*)m_pLowerBoundImmediate != (size_t)g_ephemeral_low) From 4828b6f45a4e712c24e9d6780a477f8364b8106a Mon Sep 17 00:00:00 2001 From: Bill Holmes Date: Fri, 24 Mar 2023 12:00:35 -0400 Subject: [PATCH 19/20] Revert "Unity GC write barrier patch" This reverts commit 5522dd8d606a7f40e1908e24d68eb95eb4e0d4a1. --- src/coreclr/clrdefinitions.cmake | 1 - .../vm/amd64/JitHelpers_FastWriteBarriers.asm | 23 ----------- .../vm/amd64/jithelpers_fastwritebarriers.S | 35 ----------------- src/coreclr/vm/amd64/jitinterfaceamd64.cpp | 38 ------------------- 4 files changed, 97 deletions(-) diff --git a/src/coreclr/clrdefinitions.cmake b/src/coreclr/clrdefinitions.cmake index 18a2676319d3d8..e86061f14f3e2f 100644 --- a/src/coreclr/clrdefinitions.cmake +++ b/src/coreclr/clrdefinitions.cmake @@ -118,7 +118,6 @@ if(FEATURE_UNITY_EMBEDDING_INTERFACE) add_definitions(-DFEATURE_UNITY_ASSEMBLY_MEMORY_PATH) add_definitions(-DFEATURE_UNITY_MODULE_NUM_TYPEDEFS) add_definitions(-DFEATURE_UNITY_EXPLICIT_LAYOUT_INHERITANCE) - add_definitions(-DFEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH) endif() if(FEATURE_GDBJIT) add_definitions(-DFEATURE_GDBJIT) diff --git a/src/coreclr/vm/amd64/JitHelpers_FastWriteBarriers.asm b/src/coreclr/vm/amd64/JitHelpers_FastWriteBarriers.asm index 5b3a84c05896ff..68ab221278442b 100644 --- a/src/coreclr/vm/amd64/JitHelpers_FastWriteBarriers.asm +++ b/src/coreclr/vm/amd64/JitHelpers_FastWriteBarriers.asm @@ -56,17 +56,6 @@ PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_Lower nop ; padding for alignment of constant -ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - -PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_Upper - mov r8, 0F0F0F0F0F0F0F0F0h - - cmp rdx, r8 - jae Exit - - nop ; padding for alignment of constant -endif - PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_CardTable mov rax, 0F0F0F0F0F0F0F0F0h @@ -395,18 +384,6 @@ PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Lower ; Touch the card table entry, if not already dirty. shr rcx, 0Bh NOP_2_BYTE ; padding for alignment of constant - -ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - -PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Upper - mov r8, 0F0F0F0F0F0F0F0F0h - - cmp rdx, r8 - jae Exit - - nop ; padding for alignment of constant -endif - PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_CardTable mov rax, 0F0F0F0F0F0F0F0F0h cmp byte ptr [rcx + rax], 0FFh diff --git a/src/coreclr/vm/amd64/jithelpers_fastwritebarriers.S b/src/coreclr/vm/amd64/jithelpers_fastwritebarriers.S index 15978a7fb82039..f987751bdcb358 100644 --- a/src/coreclr/vm/amd64/jithelpers_fastwritebarriers.S +++ b/src/coreclr/vm/amd64/jithelpers_fastwritebarriers.S @@ -32,23 +32,6 @@ PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_Lower nop // padding for alignment of constant -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - -PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_Upper - movabs r8, 0xF0F0F0F0F0F0F0F0 - - cmp rsi, r8 - -#ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES - .byte 0x73, 0x4b -#else - .byte 0x73, 0x2b -#endif - // jae Exit_PreGrow64 - - nop // padding for alignment of constant -#endif - PATCH_LABEL JIT_WriteBarrier_PreGrow64_Patch_Label_CardTable movabs rax, 0xF0F0F0F0F0F0F0F0 @@ -432,24 +415,6 @@ PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Lower // Touch the card table entry, if not already dirty. shr rdi, 0x0B NOP_2_BYTE // padding for alignment of constant - -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - -PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Upper - movabs r10, 0xF0F0F0F0F0F0F0F0 - - cmp rsi, r10 - -#ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES - .byte 0x73, 0x3b -#else - .byte 0x73, 0x2b -#endif - // jae Exit_WriteWatch_PreGrow64 - - nop // padding for alignment of constant -#endif - PATCH_LABEL JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_CardTable movabs rax, 0xF0F0F0F0F0F0F0F0 cmp byte ptr [rdi + rax], 0xFF diff --git a/src/coreclr/vm/amd64/jitinterfaceamd64.cpp b/src/coreclr/vm/amd64/jitinterfaceamd64.cpp index 1e2efafb42701c..08d5e9493f6c22 100644 --- a/src/coreclr/vm/amd64/jitinterfaceamd64.cpp +++ b/src/coreclr/vm/amd64/jitinterfaceamd64.cpp @@ -26,9 +26,6 @@ EXTERN_C void JIT_WriteBarrier_End(); EXTERN_C void JIT_WriteBarrier_PreGrow64(Object **dst, Object *ref); EXTERN_C void JIT_WriteBarrier_PreGrow64_Patch_Label_Lower(); -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH -EXTERN_C void JIT_WriteBarrier_PreGrow64_Patch_Label_Upper(); -#endif EXTERN_C void JIT_WriteBarrier_PreGrow64_Patch_Label_CardTable(); #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES EXTERN_C void JIT_WriteBarrier_PreGrow64_Patch_Label_CardBundleTable(); @@ -82,9 +79,6 @@ EXTERN_C void JIT_WriteBarrier_Bit_Region64_End(); EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64(Object **dst, Object *ref); EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_WriteWatchTable(); EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Lower(); -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH -EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_Upper(); -#endif EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_CardTable(); #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES EXTERN_C void JIT_WriteBarrier_WriteWatch_PreGrow64_Patch_Label_CardBundleTable(); @@ -178,15 +172,9 @@ void WriteBarrierManager::Validate() #endif pLowerBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_Lower, 2); -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - pUpperBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_Upper, 2); -#endif pCardTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_CardTable, 2); _ASSERTE_ALL_BUILDS((reinterpret_cast(pLowerBoundImmediate) & 0x7) == 0); -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - _ASSERTE_ALL_BUILDS((reinterpret_cast(pUpperBoundImmediate) & 0x7) == 0); -#endif _ASSERTE_ALL_BUILDS((reinterpret_cast(pCardTableImmediate) & 0x7) == 0); #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES @@ -251,16 +239,10 @@ void WriteBarrierManager::Validate() pWriteWatchTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_WriteWatchTable, 2); pLowerBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_Lower, 2); -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - pUpperBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_Upper, 2); -#endif pCardTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_CardTable, 2); _ASSERTE_ALL_BUILDS((reinterpret_cast(pWriteWatchTableImmediate) & 0x7) == 0); _ASSERTE_ALL_BUILDS((reinterpret_cast(pLowerBoundImmediate) & 0x7) == 0); -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - _ASSERTE_ALL_BUILDS((reinterpret_cast(pUpperBoundImmediate) & 0x7) == 0); -#endif _ASSERTE_ALL_BUILDS((reinterpret_cast(pCardTableImmediate) & 0x7) == 0); #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES @@ -451,17 +433,11 @@ int WriteBarrierManager::ChangeWriteBarrierTo(WriteBarrierType newWriteBarrier, case WRITE_BARRIER_PREGROW64: { m_pLowerBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_Lower, 2); -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - m_pUpperBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_Upper, 2); -#endif m_pCardTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_CardTable, 2); // Make sure that we will be bashing the right places (immediates should be hardcoded to 0x0f0f0f0f0f0f0f0f0). _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pLowerBoundImmediate); _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pCardTableImmediate); -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pUpperBoundImmediate); -#endif #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES m_pCardBundleTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_PreGrow64, Patch_Label_CardBundleTable, 2); @@ -553,17 +529,11 @@ int WriteBarrierManager::ChangeWriteBarrierTo(WriteBarrierType newWriteBarrier, { m_pWriteWatchTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_WriteWatchTable, 2); m_pLowerBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_Lower, 2); -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - m_pUpperBoundImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_Upper, 2); -#endif m_pCardTableImmediate = CALC_PATCH_LOCATION(JIT_WriteBarrier_WriteWatch_PreGrow64, Patch_Label_CardTable, 2); // Make sure that we will be bashing the right places (immediates should be hardcoded to 0x0f0f0f0f0f0f0f0f0). _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pWriteWatchTableImmediate); _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pLowerBoundImmediate); -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pUpperBoundImmediate); -#endif _ASSERTE_ALL_BUILDS(0xf0f0f0f0f0f0f0f0 == *(UINT64*)m_pCardTableImmediate); #ifdef FEATURE_MANUALLY_MANAGED_CARD_BUNDLES @@ -818,12 +788,6 @@ int WriteBarrierManager::UpdateEphemeralBounds(bool isRuntimeSuspended) case WRITE_BARRIER_WRITE_WATCH_BYTE_REGIONS64: case WRITE_BARRIER_WRITE_WATCH_BIT_REGIONS64: #endif // FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP -#ifdef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH - case WRITE_BARRIER_PREGROW64: -#ifdef FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP - case WRITE_BARRIER_WRITE_WATCH_PREGROW64: -#endif // FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP -#endif // FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH { // Change immediate if different from new g_ephermeral_high. if (*(UINT64*)m_pUpperBoundImmediate != (size_t)g_ephemeral_high) @@ -833,13 +797,11 @@ int WriteBarrierManager::UpdateEphemeralBounds(bool isRuntimeSuspended) stompWBCompleteActions |= SWB_ICACHE_FLUSH; } } -#ifndef FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH FALLTHROUGH; case WRITE_BARRIER_PREGROW64: #ifdef FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP case WRITE_BARRIER_WRITE_WATCH_PREGROW64: #endif // FEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP -#endif // FEATURE_UNITY_NULLGC_WRITEBARRIER_PATCH { // Change immediate if different from new g_ephermeral_low. if (*(UINT64*)m_pLowerBoundImmediate != (size_t)g_ephemeral_low) From 2516f54c6cf595e1a7f898eeb74f191e8bf038d1 Mon Sep 17 00:00:00 2001 From: Bill Holmes Date: Fri, 24 Mar 2023 11:58:05 -0400 Subject: [PATCH 20/20] Force write barrier code to use the upper bounds With the null gc, we always want to have the upper bounds check This ensures that the tiny bounds we setup will always miss. Remove this when we remove the null GC. --- src/coreclr/clrdefinitions.cmake | 1 + src/coreclr/vm/amd64/jitinterfaceamd64.cpp | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/coreclr/clrdefinitions.cmake b/src/coreclr/clrdefinitions.cmake index e86061f14f3e2f..44dc363685830c 100644 --- a/src/coreclr/clrdefinitions.cmake +++ b/src/coreclr/clrdefinitions.cmake @@ -118,6 +118,7 @@ if(FEATURE_UNITY_EMBEDDING_INTERFACE) add_definitions(-DFEATURE_UNITY_ASSEMBLY_MEMORY_PATH) add_definitions(-DFEATURE_UNITY_MODULE_NUM_TYPEDEFS) add_definitions(-DFEATURE_UNITY_EXPLICIT_LAYOUT_INHERITANCE) + add_definitions(-DFEATURE_UNITY_REQUIRE_WRITEBARRIERPOSTGROW_ALWAYS) endif() if(FEATURE_GDBJIT) add_definitions(-DFEATURE_GDBJIT) diff --git a/src/coreclr/vm/amd64/jitinterfaceamd64.cpp b/src/coreclr/vm/amd64/jitinterfaceamd64.cpp index 08d5e9493f6c22..4262e3b140979d 100644 --- a/src/coreclr/vm/amd64/jitinterfaceamd64.cpp +++ b/src/coreclr/vm/amd64/jitinterfaceamd64.cpp @@ -835,6 +835,13 @@ int WriteBarrierManager::UpdateWriteWatchAndCardTableLocations(bool isRuntimeSus // If we are told that we require an upper bounds check (GC did some heap reshuffling), // we need to switch to the WriteBarrier_PostGrow function for good. +#ifdef FEATURE_UNITY_REQUIRE_WRITEBARRIERPOSTGROW_ALWAYS + // REMOVE THIS when we remove null gc! + // With the null gc, we always want to have the upper bounds check + // This ensures that the tiny bounds we setup will always miss + bReqUpperBoundsCheck = true; +#endif + WriteBarrierType newType; if (NeedDifferentWriteBarrier(bReqUpperBoundsCheck, g_region_use_bitwise_write_barrier, &newType)) {