From b6e87175333e7d46108dba6d4595a11b36e8e3e4 Mon Sep 17 00:00:00 2001 From: Finn Wilkinson Date: Thu, 26 Oct 2023 09:22:33 +0100 Subject: [PATCH 1/8] Added fix to CMakeLists.txt file --- CMakeLists.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index ccbc9074a0..b7401e11f4 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -128,6 +128,12 @@ option(SIMENG_OPTIMIZE "Enable Extra Compiler Optimizatoins" OFF) option(SIMENG_ENABLE_SST "Compile SimEng SST Wrapper" OFF) option(SIMENG_ENABLE_SST_TESTS "Enable testing for SST" OFF) +# Set CXX flag for Apple Mac so that `binary_function` and `unary_function` types that are used in SST can be recognised. +# They were deprecated in C++11 and removed in C++17, and Apple Clang v15 no longer supports these types without the following flag +if(APPLE) + add_compile_options(-D_LIBCPP_ENABLE_CXX17_REMOVED_UNARY_BINARY_FUNCTION) +endif() + if (SIMENG_OPTIMIZE) # Turn on link time optimization for all targets. set(CMAKE_INTERPROCEDURAL_OPTIMIZATION ON) From a5eaa5e6f0e6483b1929acf3f2f009e3e8bb8fae Mon Sep 17 00:00:00 2001 From: Finn Wilkinson Date: Mon, 30 Oct 2023 11:56:47 +0000 Subject: [PATCH 2/8] Changed add_compile_option to add_compile_defenitions. --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b7401e11f4..0378af46ba 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -131,7 +131,7 @@ option(SIMENG_ENABLE_SST_TESTS "Enable testing for SST" OFF) # Set CXX flag for Apple Mac so that `binary_function` and `unary_function` types that are used in SST can be recognised. # They were deprecated in C++11 and removed in C++17, and Apple Clang v15 no longer supports these types without the following flag if(APPLE) - add_compile_options(-D_LIBCPP_ENABLE_CXX17_REMOVED_UNARY_BINARY_FUNCTION) + add_compile_definitions(_LIBCPP_ENABLE_CXX17_REMOVED_UNARY_BINARY_FUNCTION) endif() if (SIMENG_OPTIMIZE) From 306bb57231eb429e512add4925296268ad0d8aa9 Mon Sep 17 00:00:00 2001 From: Finn Wilkinson Date: Tue, 31 Oct 2023 15:42:12 +0000 Subject: [PATCH 3/8] Updated CMakeLists.txt comment. --- CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 0378af46ba..4f3e614d05 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -130,6 +130,7 @@ option(SIMENG_ENABLE_SST_TESTS "Enable testing for SST" OFF) # Set CXX flag for Apple Mac so that `binary_function` and `unary_function` types that are used in SST can be recognised. # They were deprecated in C++11 and removed in C++17, and Apple Clang v15 no longer supports these types without the following flag +# TODO: Remove one SST integration has updated to SST version 13 or later - the use of unary and binary functions are removed in later versions. if(APPLE) add_compile_definitions(_LIBCPP_ENABLE_CXX17_REMOVED_UNARY_BINARY_FUNCTION) endif() From e6e805655e6cda21ce0a2325cce873e969d80442 Mon Sep 17 00:00:00 2001 From: Finn Wilkinson Date: Wed, 1 Nov 2023 10:04:24 +0000 Subject: [PATCH 4/8] Fixed typo. --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4f3e614d05..99a35bc718 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -130,7 +130,7 @@ option(SIMENG_ENABLE_SST_TESTS "Enable testing for SST" OFF) # Set CXX flag for Apple Mac so that `binary_function` and `unary_function` types that are used in SST can be recognised. # They were deprecated in C++11 and removed in C++17, and Apple Clang v15 no longer supports these types without the following flag -# TODO: Remove one SST integration has updated to SST version 13 or later - the use of unary and binary functions are removed in later versions. +# TODO: Remove once SST integration has updated to SST version 13 or later - the use of unary and binary functions are removed in later versions. if(APPLE) add_compile_definitions(_LIBCPP_ENABLE_CXX17_REMOVED_UNARY_BINARY_FUNCTION) endif() From ae67ad3c44ed66ad9579575bd2712a8dd6abc300 Mon Sep 17 00:00:00 2001 From: Finn Wilkinson Date: Fri, 27 Oct 2023 16:17:34 +0100 Subject: [PATCH 5/8] Added new getSourceOperands() function to get the RegisterValue vector for an instruction's source operands. --- src/include/simeng/Instruction.hh | 4 ++++ src/include/simeng/arch/aarch64/Instruction.hh | 4 ++++ src/include/simeng/arch/riscv/Instruction.hh | 4 ++++ src/lib/arch/aarch64/Instruction.cc | 5 +++++ src/lib/arch/riscv/Instruction.cc | 5 +++++ test/unit/MockInstruction.hh | 1 + 6 files changed, 23 insertions(+) diff --git a/src/include/simeng/Instruction.hh b/src/include/simeng/Instruction.hh index ac9f4be53c..ea4e923229 100644 --- a/src/include/simeng/Instruction.hh +++ b/src/include/simeng/Instruction.hh @@ -26,6 +26,10 @@ class Instruction { /** Retrieve the source registers this instruction reads. */ virtual const span getOperandRegisters() const = 0; + /** Retrieve the data contained in the source registers this instruction + * reads.*/ + virtual const span getSourceOperands() const = 0; + /** Retrieve the destination registers this instruction will write to. * A register value of -1 signifies a Zero Register read, and should not be * renamed. */ diff --git a/src/include/simeng/arch/aarch64/Instruction.hh b/src/include/simeng/arch/aarch64/Instruction.hh index e833617b12..69f9dc8f18 100644 --- a/src/include/simeng/arch/aarch64/Instruction.hh +++ b/src/include/simeng/arch/aarch64/Instruction.hh @@ -279,6 +279,10 @@ class Instruction : public simeng::Instruction { /** Retrieve the source registers this instruction reads. */ const span getOperandRegisters() const override; + /** Retrieve the data contained in the source registers this instruction + * reads.*/ + const span getSourceOperands() const override; + /** Retrieve the destination registers this instruction will write to. * A register value of -1 signifies a Zero Register read, and should not be * renamed. */ diff --git a/src/include/simeng/arch/riscv/Instruction.hh b/src/include/simeng/arch/riscv/Instruction.hh index a0eaecf69a..92900bd405 100644 --- a/src/include/simeng/arch/riscv/Instruction.hh +++ b/src/include/simeng/arch/riscv/Instruction.hh @@ -76,6 +76,10 @@ class Instruction : public simeng::Instruction { /** Retrieve the source registers this instruction reads. */ const span getOperandRegisters() const override; + /** Retrieve the data contained in the source registers this instruction + * reads.*/ + const span getSourceOperands() const override; + /** Retrieve the destination registers this instruction will write to. * A register value of -1 signifies a Zero Register read, and should not be * renamed. */ diff --git a/src/lib/arch/aarch64/Instruction.cc b/src/lib/arch/aarch64/Instruction.cc index dff88a81d8..502d2ad12d 100644 --- a/src/lib/arch/aarch64/Instruction.cc +++ b/src/lib/arch/aarch64/Instruction.cc @@ -36,6 +36,11 @@ InstructionException Instruction::getException() const { return exception_; } const span Instruction::getOperandRegisters() const { return {const_cast(sourceRegisters.data()), sourceRegisterCount}; } + +const span Instruction::getSourceOperands() const { + return {const_cast(operands.data()), operands.size()}; +} + const span Instruction::getDestinationRegisters() const { return {const_cast(destinationRegisters.data()), destinationRegisterCount}; diff --git a/src/lib/arch/riscv/Instruction.cc b/src/lib/arch/riscv/Instruction.cc index 81fd9a35a1..b9e39edc2d 100644 --- a/src/lib/arch/riscv/Instruction.cc +++ b/src/lib/arch/riscv/Instruction.cc @@ -41,6 +41,11 @@ InstructionException Instruction::getException() const { return exception_; } const span Instruction::getOperandRegisters() const { return {const_cast(sourceRegisters.data()), sourceRegisterCount}; } + +const span Instruction::getSourceOperands() const { + return {const_cast(operands.data()), operands.size()}; +} + const span Instruction::getDestinationRegisters() const { return {const_cast(destinationRegisters.data()), destinationRegisterCount}; diff --git a/test/unit/MockInstruction.hh b/test/unit/MockInstruction.hh index c35c687e58..b923dc0edf 100644 --- a/test/unit/MockInstruction.hh +++ b/test/unit/MockInstruction.hh @@ -10,6 +10,7 @@ class MockInstruction : public Instruction { public: MOCK_CONST_METHOD0(getException, InstructionException()); MOCK_CONST_METHOD0(getOperandRegisters, const span()); + MOCK_CONST_METHOD0(getSourceOperands, const span()); MOCK_CONST_METHOD0(getDestinationRegisters, const span()); MOCK_METHOD2(renameSource, void(uint16_t i, Register renamed)); MOCK_METHOD2(renameDestination, void(uint16_t i, Register renamed)); From 084814248f58dd596bb6dadc96ae5e92462015bb Mon Sep 17 00:00:00 2001 From: Finn Wilkinson Date: Mon, 30 Oct 2023 11:51:45 +0000 Subject: [PATCH 6/8] Ammended SVCR functionality so that MSR reg updates are accounted for properly and so that changes to SM or ZA bits are checked before zeroing out SVE / SME registers. --- src/lib/arch/aarch64/Architecture.cc | 1 + src/lib/arch/aarch64/ExceptionHandler.cc | 81 +++++++----- src/lib/arch/aarch64/Instruction_execute.cc | 9 +- test/regression/aarch64/Exception.cc | 131 ++++++++++++++++++++ 4 files changed, 190 insertions(+), 32 deletions(-) diff --git a/src/lib/arch/aarch64/Architecture.cc b/src/lib/arch/aarch64/Architecture.cc index 4da1fae90e..ab6359c0cd 100644 --- a/src/lib/arch/aarch64/Architecture.cc +++ b/src/lib/arch/aarch64/Architecture.cc @@ -34,6 +34,7 @@ Architecture::Architecture(kernel::Linux& kernel, YAML::Node config) systemRegisterMap_[ARM64_SYSREG_MIDR_EL1] = systemRegisterMap_.size(); systemRegisterMap_[ARM64_SYSREG_CNTVCT_EL0] = systemRegisterMap_.size(); systemRegisterMap_[ARM64_SYSREG_PMCCNTR_EL0] = systemRegisterMap_.size(); + systemRegisterMap_[ARM64_SYSREG_SVCR] = systemRegisterMap_.size(); // Get Virtual Counter Timer and Processor Cycle Counter system registers. VCTreg_ = { diff --git a/src/lib/arch/aarch64/ExceptionHandler.cc b/src/lib/arch/aarch64/ExceptionHandler.cc index 88f796f495..5accdc2bde 100644 --- a/src/lib/arch/aarch64/ExceptionHandler.cc +++ b/src/lib/arch/aarch64/ExceptionHandler.cc @@ -654,52 +654,71 @@ bool ExceptionHandler::init() { instruction_.getArchitecture().getRegisterFileStructures(); // Retrieve metadata from architecture auto metadata = instruction_.getMetadata(); + // Get Architecture + const Architecture& arch = instruction_.getArchitecture(); - // Update SVCR value - const uint64_t svcrBits = static_cast(metadata.operands[0].svcr); - const uint8_t imm = metadata.operands[1].imm; - const uint64_t currSVCR = instruction_.getArchitecture().getSVCRval(); uint64_t newSVCR = 0; + const uint64_t currSVCR = instruction_.getArchitecture().getSVCRval(); - if (imm == 0) { - // Zero out relevant bits dictated by svcrBits - const uint64_t mask = 0xFFFFFFFFFFFFFFFF ^ svcrBits; - newSVCR = currSVCR & mask; - } else if (imm == 1) { - // Enable relevant bits, dictated by svcrBits - const uint64_t mask = 0xFFFFFFFFFFFFFFFF & svcrBits; - newSVCR = currSVCR | mask; + // Check if exception was called by AArch64_MSR (msr systemreg, xt) or + // AArch64_MSRpstatesvcrImm1 (msr svcr, #imm) + if (metadata.opcode == Opcode::AArch64_MSR) { + newSVCR = instruction_.getSourceOperands()[0].get(); + } else if (metadata.opcode == Opcode::AArch64_MSRpstatesvcrImm1) { + const uint64_t svcrBits = + static_cast(metadata.operands[0].svcr); + const uint64_t imm = metadata.operands[1].imm; + assert((imm == 0 || imm == 1) && + "[SimEng:ExceptionHandler] SVCR Instruction invalid - Imm value " + "can only be 0 or 1"); + // Zero out SM & ZA bits as appropriate + newSVCR = currSVCR & ~(svcrBits); + // Update only relevant bits of SVCR + newSVCR = newSVCR | (svcrBits * imm); } else { - // Invalid instruction - assert("SVCR Instruction invalid - Imm value can only be 0 or 1"); + std::cerr << "[SimEng::ExceptionHandler] SVCR system register exception " + "triggered by incorrect instruction. Opcode " + << metadata.opcode << std::endl; + exit(1); } - instruction_.getArchitecture().setSVCRval(newSVCR); + arch.setSVCRval(newSVCR); // Initialise vectors for all registers & values std::vector regs; std::vector regValues; - // Add Vector/Predicate registers + 0 values (zeroed out on Streaming Mode - // context switch) - if (exception != InstructionException::ZAregisterStatusUpdate) { - for (uint16_t i = 0; i < regFileStruct[RegisterType::VECTOR].quantity; - i++) { - regs.push_back({RegisterType::VECTOR, i}); - regValues.push_back(RegisterValue(0, 256)); - if (i < regFileStruct[RegisterType::PREDICATE].quantity) { - regs.push_back({RegisterType::PREDICATE, i}); - regValues.push_back(RegisterValue(0, 32)); + // If SVCR.ZA has changed state then zero out ZA register, else don't + if (exception != InstructionException::StreamingModeUpdate) { + if ((newSVCR & ARM64_SVCR_SVCRZA) != (currSVCR & ARM64_SVCR_SVCRZA)) { + for (uint16_t i = 0; i < regFileStruct[RegisterType::MATRIX].quantity; + i++) { + regs.push_back({RegisterType::MATRIX, i}); + regValues.push_back(RegisterValue(0, 256)); } } } - // Zero out ZA register (zeroed out on ZA-reg context switch) - if (exception != InstructionException::StreamingModeUpdate) { - for (uint16_t i = 0; i < regFileStruct[RegisterType::MATRIX].quantity; - i++) { - regs.push_back({RegisterType::MATRIX, i}); - regValues.push_back(RegisterValue(0, 256)); + // If SVCR.SM has changed state then zero out SVE, NEON, Predicate + // registers, else don't + if (exception != InstructionException::ZAregisterStatusUpdate) { + if ((newSVCR & ARM64_SVCR_SVCRSM) != (currSVCR & ARM64_SVCR_SVCRSM)) { + for (uint16_t i = 0; i < regFileStruct[RegisterType::VECTOR].quantity; + i++) { + regs.push_back({RegisterType::VECTOR, i}); + regValues.push_back(RegisterValue(0, 256)); + if (i < regFileStruct[RegisterType::PREDICATE].quantity) { + regs.push_back({RegisterType::PREDICATE, i}); + regValues.push_back(RegisterValue(0, 32)); + } + } } } + + // Update SVCR system register in regFile + regs.push_back( + {RegisterType::SYSTEM, + static_cast(arch.getSystemRegisterTag(ARM64_SYSREG_SVCR))}); + regValues.push_back(RegisterValue(newSVCR, 8)); + ProcessStateChange stateChange = {ChangeType::REPLACEMENT, regs, regValues}; return concludeSyscall(stateChange); } diff --git a/src/lib/arch/aarch64/Instruction_execute.cc b/src/lib/arch/aarch64/Instruction_execute.cc index 390ce2f240..3bca6609b0 100644 --- a/src/lib/arch/aarch64/Instruction_execute.cc +++ b/src/lib/arch/aarch64/Instruction_execute.cc @@ -3812,7 +3812,14 @@ void Instruction::execute() { break; } case Opcode::AArch64_MSR: { // msr (systemreg|Sop0_op1_Cn_Cm_op2), xt - results[0] = operands[0]; + // Handle case where SVCR is being updated as this invokes additional + // functionality + if (metadata.operands[0].reg == + static_cast(ARM64_SYSREG_SVCR)) { + return SMZAupdated(); + } else { + results[0] = operands[0]; + } break; } case Opcode::AArch64_MSUBWrrr: { // msub wd, wn, wm, wa diff --git a/test/regression/aarch64/Exception.cc b/test/regression/aarch64/Exception.cc index 8bac46bdd1..e7500e90ee 100644 --- a/test/regression/aarch64/Exception.cc +++ b/test/regression/aarch64/Exception.cc @@ -51,6 +51,49 @@ TEST_P(Exception, SME_context_modes) { EXPECT_EQ(stdout_.substr(0, sizeof(err2) - 1), err2); } +// Ensure that calling smstart/smstop such that the values in SVCR.SMZA do not +// change doesn't cause a flush of the associated register files +TEST_P(Exception, Null_Smstart_smstop_calls) { + RUN_AARCH64(R"( + smstart + dup z0.d, #3 + smstart + )"); + CHECK_NEON(0, uint64_t, fillNeon({3}, SVL / 8)); + + RUN_AARCH64(R"( + smstart + dup z0.d, #4 + smstart sm + )"); + CHECK_NEON(0, uint64_t, fillNeon({4}, SVL / 8)); + + RUN_AARCH64(R"( + smstart + dup z0.d, #5 + smstart za + )"); + CHECK_NEON(0, uint64_t, fillNeon({5}, SVL / 8)); + + RUN_AARCH64(R"( + dup z0.d, #6 + smstop + )"); + CHECK_NEON(0, uint64_t, fillNeon({6}, VL / 8)); + + RUN_AARCH64(R"( + dup z0.d, #7 + smstop sm + )"); + CHECK_NEON(0, uint64_t, fillNeon({7}, VL / 8)); + + RUN_AARCH64(R"( + dup z0.d, #8 + smstop za + )"); + CHECK_NEON(0, uint64_t, fillNeon({8}, VL / 8)); +} + TEST_P(Exception, svcr) { // Check that smstart and smstop correctly change value of SVCR system // register, verified by the correctly performed behaviour @@ -76,6 +119,13 @@ TEST_P(Exception, svcr) { )"); CHECK_NEON(0, uint64_t, fillNeon({0}, VL / 8)); + RUN_AARCH64(R"( + # Ensure z regs get enabled when SM enabled + smstart sm + dup z0.d, #3 + )"); + CHECK_NEON(0, uint64_t, fillNeon({3}, SVL / 8)); + RUN_AARCH64(R"( # Ensure z regs get zeroed out when SM disabled smstart @@ -84,6 +134,14 @@ TEST_P(Exception, svcr) { )"); CHECK_NEON(0, uint64_t, fillNeon({0}, VL / 8)); + RUN_AARCH64(R"( + # Ensure z regs do not get zeroed out when ZA is disabled + smstart + dup z0.d, #3 + smstop za + )"); + CHECK_NEON(0, uint64_t, fillNeon({3}, SVL / 8)); + RUN_AARCH64(R"( # Ensure za reg gets zeroed out when ZA enabled smstart @@ -98,6 +156,79 @@ TEST_P(Exception, svcr) { for (int i = 0; i < (SVL / 8); i++) { CHECK_MAT_ROW(ARM64_REG_ZA, i, uint32_t, fillNeon({0}, SVL / 8)); } + + // Check that changes to SVCR using msr svcr, xn work correctly + RUN_AARCH64(R"( + mov x4, #3 + mov x5, #0 + # Ensure vector length changes from SVE's to SME's + cntb x0 + msr svcr, x4 + cntb x1 + msr svcr, x5 + cntb x2 + )"); + EXPECT_EQ(getGeneralRegister(0), VL / 8); + EXPECT_EQ(getGeneralRegister(1), SVL / 8); + EXPECT_EQ(getGeneralRegister(2), VL / 8); + EXPECT_EQ(getGeneralRegister(0), getGeneralRegister(2)); + EXPECT_GT(getGeneralRegister(1), getGeneralRegister(0)); + EXPECT_GT(SVL, VL); + + RUN_AARCH64(R"( + mov x4, #3 + # Ensure z regs get zeroed out when SM enabled + dup z0.d, #3 + msr svcr, x4 + )"); + CHECK_NEON(0, uint64_t, fillNeon({0}, VL / 8)); + + RUN_AARCH64(R"( + mov x4, #1 + # Ensure z regs get enabled when SM enabled + msr svcr, x4 + dup z0.d, #3 + )"); + CHECK_NEON(0, uint64_t, fillNeon({3}, SVL / 8)); + + RUN_AARCH64(R"( + mov x4, #3 + mov x5, #0 + # Ensure z regs get zeroed out when SM disabled + msr svcr, x4 + dup z0.d, #3 + msr svcr, x5 + )"); + CHECK_NEON(0, uint64_t, fillNeon({0}, VL / 8)); + + RUN_AARCH64(R"( + # enable SM and ZA + mov x4, #3 + # just disable ZA + mov x5, #1 + # Ensure z regs do not get zeroed out when ZA is disabled + msr svcr, x4 + dup z0.d, #3 + msr svcr, x5 + )"); + CHECK_NEON(0, uint64_t, fillNeon({3}, SVL / 8)); + + RUN_AARCH64(R"( + mov x4, #3 + mov x5, #0 + # Ensure za reg gets zeroed out when ZA enabled + msr svcr, x4 + dup z0.s, #2 + dup z1.s, #3 + ptrue p0.s + ptrue p1.s + fmopa za0.s, p0/m, p1/m, z0.s, z1.s + msr svcr, x5 + msr svcr, x4 + )"); + for (int i = 0; i < (SVL / 8); i++) { + CHECK_MAT_ROW(ARM64_REG_ZA, i, uint32_t, fillNeon({0}, SVL / 8)); + } } #endif From 8c888e9eaf8f1f4fcf7ef5837de6de964f11252e Mon Sep 17 00:00:00 2001 From: Finn Wilkinson Date: Mon, 30 Oct 2023 16:16:32 +0000 Subject: [PATCH 7/8] Corrected metadata for multi-struct NEON stores with postIndex offset. --- src/lib/arch/aarch64/InstructionMetadata.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/lib/arch/aarch64/InstructionMetadata.cc b/src/lib/arch/aarch64/InstructionMetadata.cc index 0fdab7e770..16e4cbb3ba 100644 --- a/src/lib/arch/aarch64/InstructionMetadata.cc +++ b/src/lib/arch/aarch64/InstructionMetadata.cc @@ -1406,6 +1406,12 @@ InstructionMetadata::InstructionMetadata(const cs_insn& insn) operands[3].access = CS_AC_READ; operands[4].access = CS_AC_READ | CS_AC_WRITE; operands[5].access = CS_AC_READ; + // determine correct type for operand 5 + if (operandStr.find("#") != std::string::npos) { + operands[5].type = ARM64_OP_IMM; + } else { + operands[5].type = ARM64_OP_REG; + } break; case Opcode::AArch64_ST1Twov16b: [[fallthrough]]; @@ -1426,6 +1432,12 @@ InstructionMetadata::InstructionMetadata(const cs_insn& insn) operands[1].access = CS_AC_READ; operands[2].access = CS_AC_READ | CS_AC_WRITE; operands[3].access = CS_AC_READ; + // determine correct type for operand 3 + if (operandStr.find("#") != std::string::npos) { + operands[3].type = ARM64_OP_IMM; + } else { + operands[3].type = ARM64_OP_REG; + } break; case Opcode::AArch64_ST2Twov4s_POST: // ST2 post incorrectly flags read and write From bf6318751e1c2fc95fbc1df56a57eab7de46b851 Mon Sep 17 00:00:00 2001 From: Finn Wilkinson Date: Tue, 31 Oct 2023 15:34:29 +0000 Subject: [PATCH 8/8] Ensured use of arch variable. --- src/lib/arch/aarch64/ExceptionHandler.cc | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/lib/arch/aarch64/ExceptionHandler.cc b/src/lib/arch/aarch64/ExceptionHandler.cc index 5accdc2bde..c34da19f42 100644 --- a/src/lib/arch/aarch64/ExceptionHandler.cc +++ b/src/lib/arch/aarch64/ExceptionHandler.cc @@ -649,16 +649,15 @@ bool ExceptionHandler::init() { } else if (exception == InstructionException::StreamingModeUpdate || exception == InstructionException::ZAregisterStatusUpdate || exception == InstructionException::SMZAUpdate) { + // Get Architecture + const Architecture& arch = instruction_.getArchitecture(); // Retrieve register file structure from architecture - auto regFileStruct = - instruction_.getArchitecture().getRegisterFileStructures(); + auto regFileStruct = arch.getRegisterFileStructures(); // Retrieve metadata from architecture auto metadata = instruction_.getMetadata(); - // Get Architecture - const Architecture& arch = instruction_.getArchitecture(); uint64_t newSVCR = 0; - const uint64_t currSVCR = instruction_.getArchitecture().getSVCRval(); + const uint64_t currSVCR = arch.getSVCRval(); // Check if exception was called by AArch64_MSR (msr systemreg, xt) or // AArch64_MSRpstatesvcrImm1 (msr svcr, #imm)