From b072e2db163b1ce89e2fd632f0b2403c365ce67f Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Tue, 16 Jan 2024 19:05:05 +0000 Subject: [PATCH 01/12] Fixed config file issue regarding vector length --- src/lib/config/ModelConfig.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index 3d7b28c977..6c77ce7841 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -886,6 +886,18 @@ void ModelConfig::postValidation() { // Record any unlinked port names for (const auto& prt : portnames) invalid_ << "\t- " << prt << " has no associated reservation station\n"; + + // Check for valid LSQ-L1-Interface Load and Store Bandwidth + if (configTree_["Core"]["Vector-Length"].as() / 8 > \ + configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { + invalid_ << "\t- Vector-Length (bits) must be greater than \ + Load-Bandwidth (bytes)\n"; + } + else if (configTree_["Core"]["Vector-Length"].as() / 8 > \ + configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as()) { + invalid_ << "\t- Vector-Length (bits) must be greater than \ + Store-Bandwidth (bytes)\n"; + } } ryml::Tree ModelConfig::getConfig() { return configTree_; } From 3e628c919b17b08bdaff88649f07ac4acb7ac143 Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Thu, 18 Jan 2024 17:40:34 +0000 Subject: [PATCH 02/12] Fixed Fetch-Block-Size memory leak --- src/include/simeng/arch/Architecture.hh | 2 +- src/include/simeng/arch/aarch64/Architecture.hh | 2 +- src/include/simeng/arch/riscv/Architecture.hh | 2 +- src/include/simeng/pipeline/FetchUnit.hh | 2 +- src/lib/arch/aarch64/Architecture.cc | 2 +- src/lib/arch/riscv/Architecture.cc | 2 +- src/lib/models/emulation/Core.cc | 2 +- src/lib/pipeline/FetchUnit.cc | 3 +-- test/unit/MockArchitecture.hh | 2 +- 9 files changed, 9 insertions(+), 10 deletions(-) diff --git a/src/include/simeng/arch/Architecture.hh b/src/include/simeng/arch/Architecture.hh index 9a2d4c69bc..f7f163815c 100644 --- a/src/include/simeng/arch/Architecture.hh +++ b/src/include/simeng/arch/Architecture.hh @@ -65,7 +65,7 @@ class Architecture { * Writes into the supplied macro-op vector, and returns the number of bytes * consumed to produce it; a value of 0 indicates too few bytes were present * for a valid decoding. */ - virtual uint8_t predecode(const void* ptr, uint8_t bytesAvailable, + virtual uint8_t predecode(const void* ptr, uint16_t bytesAvailable, uint64_t instructionAddress, MacroOp& output) const = 0; diff --git a/src/include/simeng/arch/aarch64/Architecture.hh b/src/include/simeng/arch/aarch64/Architecture.hh index 1204b1f915..181124eb56 100644 --- a/src/include/simeng/arch/aarch64/Architecture.hh +++ b/src/include/simeng/arch/aarch64/Architecture.hh @@ -24,7 +24,7 @@ class Architecture : public arch::Architecture { /** Pre-decode instruction memory into a macro-op of `Instruction` * instances. Returns the number of bytes consumed to produce it (always 4), * and writes into the supplied macro-op vector. */ - uint8_t predecode(const void* ptr, uint8_t bytesAvailable, + uint8_t predecode(const void* ptr, uint16_t bytesAvailable, uint64_t instructionAddress, MacroOp& output) const override; diff --git a/src/include/simeng/arch/riscv/Architecture.hh b/src/include/simeng/arch/riscv/Architecture.hh index 5d5d17c185..16489fc643 100644 --- a/src/include/simeng/arch/riscv/Architecture.hh +++ b/src/include/simeng/arch/riscv/Architecture.hh @@ -23,7 +23,7 @@ class Architecture : public arch::Architecture { /** Pre-decode instruction memory into a macro-op of `Instruction` * instances. Returns the number of bytes consumed to produce it (always 4), * and writes into the supplied macro-op vector. */ - uint8_t predecode(const void* ptr, uint8_t bytesAvailable, + uint8_t predecode(const void* ptr, uint16_t bytesAvailable, uint64_t instructionAddress, MacroOp& output) const override; diff --git a/src/include/simeng/pipeline/FetchUnit.hh b/src/include/simeng/pipeline/FetchUnit.hh index c09f830654..aac4e47f62 100644 --- a/src/include/simeng/pipeline/FetchUnit.hh +++ b/src/include/simeng/pipeline/FetchUnit.hh @@ -115,7 +115,7 @@ class FetchUnit { uint8_t* fetchBuffer_; /** The amount of data currently in the fetch buffer. */ - uint8_t bufferedBytes_ = 0; + uint16_t bufferedBytes_ = 0; }; } // namespace pipeline diff --git a/src/lib/arch/aarch64/Architecture.cc b/src/lib/arch/aarch64/Architecture.cc index 5fa77159b4..b72d6654b5 100644 --- a/src/lib/arch/aarch64/Architecture.cc +++ b/src/lib/arch/aarch64/Architecture.cc @@ -144,7 +144,7 @@ Architecture::~Architecture() { SVCRval_ = 0; } -uint8_t Architecture::predecode(const void* ptr, uint8_t bytesAvailable, +uint8_t Architecture::predecode(const void* ptr, uint16_t bytesAvailable, uint64_t instructionAddress, MacroOp& output) const { // Check that instruction address is 4-byte aligned as required by Armv9.2-a diff --git a/src/lib/arch/riscv/Architecture.cc b/src/lib/arch/riscv/Architecture.cc index 8765e3dee8..16f4134616 100644 --- a/src/lib/arch/riscv/Architecture.cc +++ b/src/lib/arch/riscv/Architecture.cc @@ -144,7 +144,7 @@ Architecture::~Architecture() { groupExecutionInfo_.clear(); } -uint8_t Architecture::predecode(const void* ptr, uint8_t bytesAvailable, +uint8_t Architecture::predecode(const void* ptr, uint16_t bytesAvailable, uint64_t instructionAddress, MacroOp& output) const { // Check that instruction address is 4-byte aligned as required by RISC-V diff --git a/src/lib/models/emulation/Core.cc b/src/lib/models/emulation/Core.cc index a37b8e038a..e6ce1e4d6d 100644 --- a/src/lib/models/emulation/Core.cc +++ b/src/lib/models/emulation/Core.cc @@ -8,7 +8,7 @@ namespace emulation { // TODO: Expose as config option /** The number of bytes fetched each cycle. */ -const uint8_t FETCH_SIZE = 4; +const uint16_t FETCH_SIZE = 4; const unsigned int clockFrequency = 2.5 * 1e9; Core::Core(MemoryInterface& instructionMemory, MemoryInterface& dataMemory, diff --git a/src/lib/pipeline/FetchUnit.cc b/src/lib/pipeline/FetchUnit.cc index fc0bbedc12..2da1ada097 100644 --- a/src/lib/pipeline/FetchUnit.cc +++ b/src/lib/pipeline/FetchUnit.cc @@ -41,7 +41,6 @@ void FetchUnit::tick() { auto bytesRead = isa_.predecode(&(loopBuffer_.front().encoding), loopBuffer_.front().instructionSize, loopBuffer_.front().address, macroOp); - assert(bytesRead != 0 && "predecode failure for loop buffer entry"); // Set prediction to recorded value during loop buffer filling @@ -58,7 +57,7 @@ void FetchUnit::tick() { // Pointer to the instruction data to decode from const uint8_t* buffer; - uint8_t bufferOffset; + uint16_t bufferOffset; // Check if more instruction data is required if (bufferedBytes_ < isa_.getMaxInstructionSize()) { diff --git a/test/unit/MockArchitecture.hh b/test/unit/MockArchitecture.hh index 0df643ee9e..7795571f2f 100644 --- a/test/unit/MockArchitecture.hh +++ b/test/unit/MockArchitecture.hh @@ -9,7 +9,7 @@ namespace simeng { class MockArchitecture : public arch::Architecture { public: MOCK_CONST_METHOD4(predecode, - uint8_t(const void* ptr, uint8_t bytesAvailable, + uint8_t(const void* ptr, uint16_t bytesAvailable, uint64_t instructionAddress, MacroOp& output)); MOCK_CONST_METHOD1(canRename, bool(Register reg)); MOCK_CONST_METHOD1(getSystemRegisterTag, int32_t(uint16_t reg)); From 092e87d70cc57c5b3085c6f43c73148decf6a241 Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Thu, 18 Jan 2024 18:24:42 +0000 Subject: [PATCH 03/12] Clang formatted ModelConfig.cc --- src/lib/config/ModelConfig.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index 6c77ce7841..855bff031a 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -888,15 +888,15 @@ void ModelConfig::postValidation() { invalid_ << "\t- " << prt << " has no associated reservation station\n"; // Check for valid LSQ-L1-Interface Load and Store Bandwidth - if (configTree_["Core"]["Vector-Length"].as() / 8 > \ - configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { - invalid_ << "\t- Vector-Length (bits) must be greater than \ - Load-Bandwidth (bytes)\n"; - } - else if (configTree_["Core"]["Vector-Length"].as() / 8 > \ - configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as()) { - invalid_ << "\t- Vector-Length (bits) must be greater than \ - Store-Bandwidth (bytes)\n"; + if (configTree_["Core"]["Vector-Length"].as() / 8 > + configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { + invalid_ << "\t- Vector-Length (bits) must be greater than Load-Bandwidth " + "(bytes)\n"; + } else if (configTree_["Core"]["Vector-Length"].as() / 8 > + configTree_["LSQ-L1-Interface"]["Store-Bandwidth"] + .as()) { + invalid_ << "\t- Vector-Length (bits) must be greater than Store-Bandwidth " + "(bytes)\n"; } } From bf85b15fecf1d5273984a86a63d2c08c923000c6 Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Fri, 19 Jan 2024 14:16:50 +0000 Subject: [PATCH 04/12] Added more informative comments. Separated load and store check --- src/lib/config/ModelConfig.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index 855bff031a..397515a874 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -887,14 +887,15 @@ void ModelConfig::postValidation() { for (const auto& prt : portnames) invalid_ << "\t- " << prt << " has no associated reservation station\n"; - // Check for valid LSQ-L1-Interface Load and Store Bandwidth + // Ensure LSQ-L1-Interface Load/Store Bandwidth is large enough for vector + // unit if (configTree_["Core"]["Vector-Length"].as() / 8 > configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { invalid_ << "\t- Vector-Length (bits) must be greater than Load-Bandwidth " "(bytes)\n"; - } else if (configTree_["Core"]["Vector-Length"].as() / 8 > - configTree_["LSQ-L1-Interface"]["Store-Bandwidth"] - .as()) { + } + if (configTree_["Core"]["Vector-Length"].as() / 8 > + configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as()) { invalid_ << "\t- Vector-Length (bits) must be greater than Store-Bandwidth " "(bytes)\n"; } From f1115e9093059acbbc2e2cf6ca103921c6ff8c13 Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Mon, 22 Jan 2024 15:55:53 +0000 Subject: [PATCH 05/12] Added test for SVL and made descriptions more informative --- src/lib/config/ModelConfig.cc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index 397515a874..526d8476f3 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -887,8 +887,8 @@ void ModelConfig::postValidation() { for (const auto& prt : portnames) invalid_ << "\t- " << prt << " has no associated reservation station\n"; - // Ensure LSQ-L1-Interface Load/Store Bandwidth is large enough for vector - // unit + // Ensure LSQ-L1-Interface Load/Store Bandwidth is large enough to accomodate + // a full vector load of the specified Vector-Length parameter if (configTree_["Core"]["Vector-Length"].as() / 8 > configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { invalid_ << "\t- Vector-Length (bits) must be greater than Load-Bandwidth " @@ -899,6 +899,22 @@ void ModelConfig::postValidation() { invalid_ << "\t- Vector-Length (bits) must be greater than Store-Bandwidth " "(bytes)\n"; } + + // Ensure LSQ-L1-Interface Load/Store Bandwidth is also large enough to + // accomodate a full vector load of the specified Streaming-Vector-Length + // parameter when streaming mode is enabled + if (configTree_["Core"]["Streaming-Vector-Length"].as() / 8 > + configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { + invalid_ << "\t- Streaming-Vector-Length (bits) must be greater than " + "Load-Bandwidth " + "(bytes)\n"; + } + if (configTree_["Core"]["Streaming-Vector-Length"].as() / 8 > + configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as()) { + invalid_ << "\t- Streaming-Vector-Length (bits) must be greater than " + "Store-Bandwidth " + "(bytes)\n"; + } } ryml::Tree ModelConfig::getConfig() { return configTree_; } From 2494b3997dbff0fa20ca07e694d4d626f5ea43af Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Wed, 24 Jan 2024 17:21:10 +0000 Subject: [PATCH 06/12] Fixed bug where 2048 was missed as a valid value for Fetch-Block-Size --- src/lib/config/ModelConfig.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index 526d8476f3..5765cf896e 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -318,7 +318,7 @@ void ModelConfig::setExpectations(bool isDefault) { expectations_["Fetch"].addChild( ExpectationNode::createExpectation(32, "Fetch-Block-Size")); expectations_["Fetch"]["Fetch-Block-Size"].setValueSet(std::vector{ - 4, 8, 16, 32, 64, 128, 256, 512, 1024, 4096, 8192, 16384, 32768}); + 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768}); expectations_["Fetch"].addChild( ExpectationNode::createExpectation(32, "Loop-Buffer-Size")); From c62c7f7a7629a37712f79095816df0b0de3531bc Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Tue, 6 Feb 2024 17:33:27 +0000 Subject: [PATCH 07/12] Added aarch64 if statement around bandwidth checks, and fixed error messages being wrong way around --- src/lib/config/ModelConfig.cc | 53 +++++++++++++++++------------------ 1 file changed, 26 insertions(+), 27 deletions(-) diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index 42ab3b0ef9..eb6c1f9374 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -927,33 +927,32 @@ void ModelConfig::postValidation() { "supported. Interface-Type used is " << l1iType << "\n"; - // Ensure LSQ-L1-Interface Load/Store Bandwidth is large enough to accomodate - // a full vector load of the specified Vector-Length parameter - if (configTree_["Core"]["Vector-Length"].as() / 8 > - configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { - invalid_ << "\t- Vector-Length (bits) must be greater than Load-Bandwidth " - "(bytes)\n"; - } - if (configTree_["Core"]["Vector-Length"].as() / 8 > - configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as()) { - invalid_ << "\t- Vector-Length (bits) must be greater than Store-Bandwidth " - "(bytes)\n"; - } - - // Ensure LSQ-L1-Interface Load/Store Bandwidth is also large enough to - // accomodate a full vector load of the specified Streaming-Vector-Length - // parameter when streaming mode is enabled - if (configTree_["Core"]["Streaming-Vector-Length"].as() / 8 > - configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { - invalid_ << "\t- Streaming-Vector-Length (bits) must be greater than " - "Load-Bandwidth " - "(bytes)\n"; - } - if (configTree_["Core"]["Streaming-Vector-Length"].as() / 8 > - configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as()) { - invalid_ << "\t- Streaming-Vector-Length (bits) must be greater than " - "Store-Bandwidth " - "(bytes)\n"; + if (isa_ == ISA::AArch64) { + // Ensure LSQ-L1-Interface Load/Store Bandwidth is large enough to accomodate + // a full vector load of the specified Vector-Length parameter + if (configTree_["Core"]["Vector-Length"].as() / 8 > + configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { + invalid_ << "\t- Load-Bandwidth (bytes) must be greater than Vector-Length (bits). " + "The current Load-Bandwidth is set to " << configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as() << " bytes, when it must be at least " << configTree_["Core"]["Vector-Length"].as() / 8 << "\n"; + } + if (configTree_["Core"]["Vector-Length"].as() / 8 > + configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as()) { + invalid_ << "\t- Store-Bandwidth (bytes) must be greater than Vector-Length (bits). " + "The current Store-Bandwidth is set to " << configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as() << " bytes, when it must be at least " << configTree_["Core"]["Vector-Length"].as() / 8 << "\n"; + } + // Ensure LSQ-L1-Interface Load/Store Bandwidth is also large enough to + // accomodate a full vector load of the specified Streaming-Vector-Length + // parameter when streaming mode is enabled + if (configTree_["Core"]["Streaming-Vector-Length"].as() / 8 > + configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { + invalid_ << "\t- Load-Bandwidth (bytes) must be greater than Streaming-Vector-Length (bits). " + "The current Load-Bandwidth is set to " << configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as() << " bytes, when it must be at least " << configTree_["Core"]["Streaming-Vector-Length"].as() / 8 << "\n"; + } + if (configTree_["Core"]["Streaming-Vector-Length"].as() / 8 > + configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as()) { + invalid_ << "\t- Store-Bandwidth (bytes) must be greater than Streaming-Vector-Length (bits). " + "The current Store-Bandwidth is set to " << configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as() << " bytes, when it must be at least " << configTree_["Core"]["Streaming-Vector-Length"].as() / 8 << "\n"; + } } } From 620e53306c51a40c53a7bb877c1e1edd83523860 Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Tue, 6 Feb 2024 17:35:32 +0000 Subject: [PATCH 08/12] Clang tidy --- src/lib/config/ModelConfig.cc | 42 ++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index eb6c1f9374..48368f1516 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -928,30 +928,52 @@ void ModelConfig::postValidation() { << l1iType << "\n"; if (isa_ == ISA::AArch64) { - // Ensure LSQ-L1-Interface Load/Store Bandwidth is large enough to accomodate - // a full vector load of the specified Vector-Length parameter + // Ensure LSQ-L1-Interface Load/Store Bandwidth is large enough to + // accomodate a full vector load of the specified Vector-Length parameter if (configTree_["Core"]["Vector-Length"].as() / 8 > configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { - invalid_ << "\t- Load-Bandwidth (bytes) must be greater than Vector-Length (bits). " - "The current Load-Bandwidth is set to " << configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as() << " bytes, when it must be at least " << configTree_["Core"]["Vector-Length"].as() / 8 << "\n"; + invalid_ + << "\t- Load-Bandwidth (bytes) must be greater than Vector-Length " + "(bits). " + "The current Load-Bandwidth is set to " + << configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as() + << " bytes, when it must be at least " + << configTree_["Core"]["Vector-Length"].as() / 8 << "\n"; } if (configTree_["Core"]["Vector-Length"].as() / 8 > configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as()) { - invalid_ << "\t- Store-Bandwidth (bytes) must be greater than Vector-Length (bits). " - "The current Store-Bandwidth is set to " << configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as() << " bytes, when it must be at least " << configTree_["Core"]["Vector-Length"].as() / 8 << "\n"; + invalid_ + << "\t- Store-Bandwidth (bytes) must be greater than Vector-Length " + "(bits). " + "The current Store-Bandwidth is set to " + << configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as() + << " bytes, when it must be at least " + << configTree_["Core"]["Vector-Length"].as() / 8 << "\n"; } // Ensure LSQ-L1-Interface Load/Store Bandwidth is also large enough to // accomodate a full vector load of the specified Streaming-Vector-Length // parameter when streaming mode is enabled if (configTree_["Core"]["Streaming-Vector-Length"].as() / 8 > configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as()) { - invalid_ << "\t- Load-Bandwidth (bytes) must be greater than Streaming-Vector-Length (bits). " - "The current Load-Bandwidth is set to " << configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as() << " bytes, when it must be at least " << configTree_["Core"]["Streaming-Vector-Length"].as() / 8 << "\n"; + invalid_ + << "\t- Load-Bandwidth (bytes) must be greater than " + "Streaming-Vector-Length (bits). " + "The current Load-Bandwidth is set to " + << configTree_["LSQ-L1-Interface"]["Load-Bandwidth"].as() + << " bytes, when it must be at least " + << configTree_["Core"]["Streaming-Vector-Length"].as() / 8 + << "\n"; } if (configTree_["Core"]["Streaming-Vector-Length"].as() / 8 > configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as()) { - invalid_ << "\t- Store-Bandwidth (bytes) must be greater than Streaming-Vector-Length (bits). " - "The current Store-Bandwidth is set to " << configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as() << " bytes, when it must be at least " << configTree_["Core"]["Streaming-Vector-Length"].as() / 8 << "\n"; + invalid_ + << "\t- Store-Bandwidth (bytes) must be greater than " + "Streaming-Vector-Length (bits). " + "The current Store-Bandwidth is set to " + << configTree_["LSQ-L1-Interface"]["Store-Bandwidth"].as() + << " bytes, when it must be at least " + << configTree_["Core"]["Streaming-Vector-Length"].as() / 8 + << "\n"; } } } From 230a61b48092c1a80f78a70790c9faef8aa27d81 Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Tue, 6 Feb 2024 18:57:54 +0000 Subject: [PATCH 09/12] Fixed gtests breaking due to using invalid load/store bandwidths --- test/regression/aarch64/Exception.cc | 9 ++++++--- test/unit/aarch64/ArchitectureTest.cc | 4 ++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/test/regression/aarch64/Exception.cc b/test/regression/aarch64/Exception.cc index 9b27ec4aae..5f8aedccb5 100644 --- a/test/regression/aarch64/Exception.cc +++ b/test/regression/aarch64/Exception.cc @@ -237,13 +237,16 @@ INSTANTIATE_TEST_SUITE_P( ::testing::Values( std::make_tuple( EMULATION, - "{Core: {Vector-Length: 512, Streaming-Vector-Length: 1024}}"), + "{Core: {Vector-Length: 512, Streaming-Vector-Length: 1024}, " + "LSQ-L1-Interface: {Load-Bandwidth: 256, Store-Bandwidth: 256}}"), std::make_tuple( INORDER, - "{Core: {Vector-Length: 512, Streaming-Vector-Length: 1024}}"), + "{Core: {Vector-Length: 512, Streaming-Vector-Length: 1024}, " + "LSQ-L1-Interface: {Load-Bandwidth: 256, Store-Bandwidth: 256}}"), std::make_tuple( OUTOFORDER, - "{Core: {Vector-Length: 512, Streaming-Vector-Length: 1024}}")), + "{Core: {Vector-Length: 512, Streaming-Vector-Length: 1024}, " + "LSQ-L1-Interface: {Load-Bandwidth: 256, Store-Bandwidth: 256}}")), paramToString); } // namespace diff --git a/test/unit/aarch64/ArchitectureTest.cc b/test/unit/aarch64/ArchitectureTest.cc index 63b2805ce3..29238dd4dc 100644 --- a/test/unit/aarch64/ArchitectureTest.cc +++ b/test/unit/aarch64/ArchitectureTest.cc @@ -32,6 +32,10 @@ class AArch64ArchitectureTest : public testing::Test { Vector-Length: 512, Streaming-Vector-Length: 128 }, + LSQ-L1-Interface: { + Load-Bandwidth: 64, + Store-Bandwidth: 64 + }, Ports: { '0': {Portname: Port 0, Instruction-Group-Support: [FP, SVE]}, '1': {Portname: Port 1, Instruction-Group-Support: [PREDICATE]}, From 4f829314403b835fa6e192c34ce18c9142d6a5fb Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Wed, 7 Feb 2024 18:22:56 +0000 Subject: [PATCH 10/12] Updated value bounds to reflect minimum load/store bandwidths --- src/lib/config/ModelConfig.cc | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index 48368f1516..8abe6a2fba 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -485,13 +485,29 @@ void ModelConfig::setExpectations(bool isDefault) { expectations_["LSQ-L1-Interface"].addChild( ExpectationNode::createExpectation(32, "Load-Bandwidth")); - expectations_["LSQ-L1-Interface"]["Load-Bandwidth"].setValueBounds( - 1, UINT16_MAX); + // AArch64 requires a vector length of at least 128, requiring a minimum of 16 + // byte load bandwidths + // For RV64, the the minimum required load bandwidth is 8 bytes + if (isa_ == ISA::AArch64) { + expectations_["LSQ-L1-Interface"]["Load-Bandwidth"] + .setValueBounds(16, UINT16_MAX); + } else if (isa_ == ISA::RV64) { + expectations_["LSQ-L1-Interface"]["Load-Bandwidth"] + .setValueBounds(8, UINT16_MAX); + } expectations_["LSQ-L1-Interface"].addChild( ExpectationNode::createExpectation(32, "Store-Bandwidth")); - expectations_["LSQ-L1-Interface"]["Store-Bandwidth"].setValueBounds( - 1, UINT16_MAX); + // AArch64 requires a vector length of at least 128, requiring a minimum of 16 + // byte store bandwidths + // For RV64, the the minimum required store bandwidth is 8 bytes + if (isa_ == ISA::AArch64) { + expectations_["LSQ-L1-Interface"]["Store-Bandwidth"] + .setValueBounds(16, UINT16_MAX); + } else if (isa_ == ISA::RV64) { + expectations_["LSQ-L1-Interface"]["Store-Bandwidth"] + .setValueBounds(8, UINT16_MAX); + } expectations_["LSQ-L1-Interface"].addChild( ExpectationNode::createExpectation( From 655067cbf9cf581f4ec3f1da23745bf4324192cd Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Thu, 8 Feb 2024 14:24:17 +0000 Subject: [PATCH 11/12] Increased min register count temporarily. Merged isa check for load/store bandwidths --- src/lib/config/ModelConfig.cc | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index 8abe6a2fba..94242bb4aa 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -349,14 +349,16 @@ void ModelConfig::setExpectations(bool isDefault) { expectations_["Register-Set"].addChild( ExpectationNode::createExpectation(32, "GeneralPurpose-Count")); + // TODO: Reduce to 32 once renaming issue has been sorted expectations_["Register-Set"]["GeneralPurpose-Count"] - .setValueBounds(32, UINT16_MAX); + .setValueBounds(38, UINT16_MAX); expectations_["Register-Set"].addChild( ExpectationNode::createExpectation( 32, "FloatingPoint/SVE-Count")); + // TODO: Reduce to 32 once renaming issue has been sorted expectations_["Register-Set"]["FloatingPoint/SVE-Count"] - .setValueBounds(32, UINT16_MAX); + .setValueBounds(38, UINT16_MAX); expectations_["Register-Set"].addChild( ExpectationNode::createExpectation(17, "Predicate-Count", @@ -377,14 +379,16 @@ void ModelConfig::setExpectations(bool isDefault) { expectations_["Register-Set"].addChild( ExpectationNode::createExpectation(32, "GeneralPurpose-Count")); + // TODO: Reduce to 32 once renaming issue has been sorted expectations_["Register-Set"]["GeneralPurpose-Count"] - .setValueBounds(32, UINT16_MAX); + .setValueBounds(38, UINT16_MAX); expectations_["Register-Set"].addChild( ExpectationNode::createExpectation(32, "FloatingPoint-Count")); + // TODO: Reduce to 32 once renaming issue has been sorted expectations_["Register-Set"]["FloatingPoint-Count"] - .setValueBounds(32, UINT16_MAX); + .setValueBounds(38, UINT16_MAX); } // Pipeline-Widths @@ -485,28 +489,23 @@ void ModelConfig::setExpectations(bool isDefault) { expectations_["LSQ-L1-Interface"].addChild( ExpectationNode::createExpectation(32, "Load-Bandwidth")); - // AArch64 requires a vector length of at least 128, requiring a minimum of 16 - // byte load bandwidths - // For RV64, the the minimum required load bandwidth is 8 bytes - if (isa_ == ISA::AArch64) { - expectations_["LSQ-L1-Interface"]["Load-Bandwidth"] - .setValueBounds(16, UINT16_MAX); - } else if (isa_ == ISA::RV64) { - expectations_["LSQ-L1-Interface"]["Load-Bandwidth"] - .setValueBounds(8, UINT16_MAX); - } expectations_["LSQ-L1-Interface"].addChild( ExpectationNode::createExpectation(32, "Store-Bandwidth")); + // AArch64 requires a vector length of at least 128, requiring a minimum of 16 - // byte store bandwidths - // For RV64, the the minimum required store bandwidth is 8 bytes + // byte load/store bandwidths + // For RV64, the the minimum required load/store bandwidth is 8 bytes if (isa_ == ISA::AArch64) { + expectations_["LSQ-L1-Interface"]["Load-Bandwidth"] + .setValueBounds(16, UINT16_MAX); expectations_["LSQ-L1-Interface"]["Store-Bandwidth"] .setValueBounds(16, UINT16_MAX); } else if (isa_ == ISA::RV64) { expectations_["LSQ-L1-Interface"]["Store-Bandwidth"] .setValueBounds(8, UINT16_MAX); + expectations_["LSQ-L1-Interface"]["Load-Bandwidth"] + .setValueBounds(8, UINT16_MAX); } expectations_["LSQ-L1-Interface"].addChild( From 0066c08f788beca16b797235ad325cf27339a8a6 Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Thu, 8 Feb 2024 15:23:04 +0000 Subject: [PATCH 12/12] Fixed mistake with forgetting to also update createExpectation --- src/lib/config/ModelConfig.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/lib/config/ModelConfig.cc b/src/lib/config/ModelConfig.cc index 94242bb4aa..e94cc52895 100644 --- a/src/lib/config/ModelConfig.cc +++ b/src/lib/config/ModelConfig.cc @@ -346,17 +346,17 @@ void ModelConfig::setExpectations(bool isDefault) { // Register-Set expectations_.addChild(ExpectationNode::createExpectation("Register-Set")); if (isa_ == ISA::AArch64) { + // TODO: Reduce to 32 once renaming issue has been sorted expectations_["Register-Set"].addChild( - ExpectationNode::createExpectation(32, + ExpectationNode::createExpectation(38, "GeneralPurpose-Count")); - // TODO: Reduce to 32 once renaming issue has been sorted expectations_["Register-Set"]["GeneralPurpose-Count"] .setValueBounds(38, UINT16_MAX); + // TODO: Reduce to 32 once renaming issue has been sorted expectations_["Register-Set"].addChild( ExpectationNode::createExpectation( - 32, "FloatingPoint/SVE-Count")); - // TODO: Reduce to 32 once renaming issue has been sorted + 38, "FloatingPoint/SVE-Count")); expectations_["Register-Set"]["FloatingPoint/SVE-Count"] .setValueBounds(38, UINT16_MAX);