From a05cd0a227b9269c99037b0e627ff0eef829d804 Mon Sep 17 00:00:00 2001 From: jj16791 Date: Tue, 20 Feb 2024 18:59:30 +0000 Subject: [PATCH 01/11] Initial update to docs/text files for 0.9.6 release --- CMakeLists.txt | 2 +- CONTRIBUTORS.txt | 2 ++ RELEASE-NOTES.txt | 8 ++++---- docs/sphinx/index.rst | 6 ++++-- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 9bd70577f3..88c0789dc5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -50,7 +50,7 @@ FetchContent_Declare( ) cmake_policy(SET CMP0048 NEW) -project(SimEng VERSION 0.9.4 LANGUAGES C CXX) +project(SimEng VERSION 0.9.6 LANGUAGES C CXX) # If no build type was defined, default to Release if(NOT CMAKE_BUILD_TYPE) diff --git a/CONTRIBUTORS.txt b/CONTRIBUTORS.txt index a2485e96e1..dc05816c2e 100644 --- a/CONTRIBUTORS.txt +++ b/CONTRIBUTORS.txt @@ -12,6 +12,8 @@ Current development team: Finn Wilkinson Rahat Muneeb Daniel Weaver + Alex Cockrean + Joseph Moore Additional Contributors: Ainsley Rutterford diff --git a/RELEASE-NOTES.txt b/RELEASE-NOTES.txt index f55e29d1fc..2a8a1c68e0 100644 --- a/RELEASE-NOTES.txt +++ b/RELEASE-NOTES.txt @@ -1,4 +1,4 @@ -Welcome to the 0.9.5 open source release of the Simulation Engine! SimEng is a fast, easy to use and modify, cycle-level simulator for CPUs. Its initial focus is on simulating single Arm cores in server CPUs, and so the instruction set architecture (ISA) target is initially Arm9.2-a+SVE+SME. RISC-V has also seen some inital support, starting with rv64ima. Later versions of the Arm ISA, additional RISC-V ISA extensions and other ISAs, will be supported in future releases. +Welcome to the 0.9.6 open source release of the Simulation Engine! SimEng is a fast, easy to use and modify, cycle-level simulator for CPUs. Its initial focus is on simulating single Arm cores in server CPUs, and so the instruction set architecture (ISA) target is initially Arm9.2-a+SVE+SME. RISC-V has also seen some inital support, starting with rv64ima. Later versions of the Arm ISA, additional RISC-V ISA extensions and other ISAs, will be supported in future releases. This SimEng release should be considered beta software - you are the first users outside of the core developers, so there *will* be lots of bugs and missing features. The good news is that the code has been designed to be simple to understand and modify, so if you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll get to it as soon as we can. @@ -6,7 +6,7 @@ You can find all the user and developer documentation on the SimEng webpage: https://uob-hpc.github.io/SimEng/index.html -SimEng should be fast, much faster than other cycle-level CPU simulators. The fastest hardware we’ve run it on is an M1-Ultra Mac Studio, where we’ve measured SimEng running at up to ~1 MIPS for the Out of Order (OoO) core in our ThunderX2 and A64fx models. SVE (vector) codes are more complex to simulate and tend to be slower - on the same hardware we saw simulated SVE codes running at around 0.6 MIPS. +SimEng should be fast, much faster than other cycle-level CPU simulators. The fastest hardware we’ve run it on is an M1-Ultra Mac Studio, where we’ve measured SimEng running at up to ~1.2 MIPS for the Out of Order (OoO) core in our ThunderX2 and A64fx models. SVE (vector) and SME (matrix) codes are more complex to simulate and tend to be slower - on the same hardware we saw simulated SVE codes running at around 0.9 MIPS and SME codes at around 0.8 MIPS. Things that should work in this release include: * Static AArch64, with SVE/SME, binaries compiled with either GCC 7.3 or later, or Arm Clang 20/LLVM 9 or later @@ -25,7 +25,7 @@ Current limitations (to be addressed in a future release): * We don't currently support running MPI programs (we’ve had a statically linked OpenMPI single rank program run correctly, but this was painful to build) * We only support a subset of Linux's system calls, and these run under emulation. The subset of 43 calls is enough to run all the codes we've tried so far * Only partial support for micro-oping, mainly for Load and Store operations -* Only partial support for the ISA - we’ve focused on implementing the instructions we’ve seen generated by the compiler for all the test cases we’ve considered, about 1000 different AArch64 instructions (~15% of the entire ISA) and about 150 different RISC-V instructions so far (~33% of the RISC-V ISA supported by Capstone). You’re likely to come across “instruction not implemented” errors, just let us know when you see these +* Only partial support for the ISA - we’ve focused on implementing the instructions we’ve seen generated by the compiler for all the test cases we’ve considered, about 1000 different AArch64 instructions (~16% of the entire ISA) and about 210 different RISC-V instructions so far (~46% of the RISC-V ISA supported by Capstone). You’re likely to come across “instruction not implemented” errors, just let us know when you see these * Single core, single thread only for now * Internally, SimEng currently only supports a very simple memory model, assuming all load/stores will hit the L1 cache. However, we have a tested integration with the SST framework (http://sst-simulator.org) allowing for a full memory model to be simulated. @@ -33,7 +33,7 @@ Supported OSs (we’ve tested these, SimEng may also work on other platforms): * CentOS 7 * Ubuntu * Cray’s CLE 7, which is based on SLES 15 -* macOS Big Sur/Monterey +* macOS Monterey/Ventura/Sonoma Compilers supported for building SimEng itself: * GCC 7 or later diff --git a/docs/sphinx/index.rst b/docs/sphinx/index.rst index 9eee5198ec..dca6969b24 100644 --- a/docs/sphinx/index.rst +++ b/docs/sphinx/index.rst @@ -44,7 +44,7 @@ SimEng is a framework for building modern, cycle-accurate processor simulators. - Accurate, aiming for simulated cycle times being within 5-10% of real hardware - Open source, with a permissive license to enable collaboration across academia and industry -SimEng places an emphasis on performance and ease of use, whilst maintaining a clean, modern, simple and well-documented code base. For example, the current out-of-order (OoO) model is implemented in around 10,000 lines of simple C++, with another 17,000 and 3,000 lines or so implementing the specifics of the AArch64 and RISC-V ISAs respectively, and around 27,000 lines of code in the accompanying test suite. SimEng should be simple to read and understand, making it ideal to modify to your requirements and include it in your projects. +SimEng places an emphasis on performance and ease of use, whilst maintaining a clean, modern, simple and well-documented code base. For example, the current out-of-order (OoO) model is implemented in around 11,000 lines of simple C++, with another 18,000 and 5,000 lines or so implementing the specifics of the AArch64 and RISC-V ISAs respectively, and around 41,000 lines of code in the accompanying test suite. SimEng should be simple to read and understand, making it ideal to modify to your requirements and include it in your projects. Features @@ -70,7 +70,9 @@ SimEng was first presented by `Professor Simon McIntosh-Smith `_ - ModSim 2023 - :download:`Leveraging Arm's Scalable Matrix Extension to Accelerate Matrix Multiplication Kernels ` +- PMBS 2022 - `An Initial Evaluation of Arm's Scalable Matrix Extension `_ - ModSim 2022 - :download:`A design space exploration for optimal vector unit composition ` - :download:`Modelling Advanced Arm-based CPUs with SimEng ` @@ -78,7 +80,7 @@ Additionally, other works concerning SimEng and its use can be found below: Release ------- -This is SimEng's seventh release, and should be considered beta level software (version 0.9.5). We expect you to find issues, primarily in unimplemented instructions or unimplemented system calls. Please let us know when you hit these, either by submitting a pull request (PR), or by filing an issue on the Github repo. You can find the all the code and associated test suites for SimEng in the `GitHub repository `_. The file `RELEASE_NOTES.txt `_, found in the root of the project, explains the status of the project and includes other relevant information from the SimEng development team. +This is SimEng's seventh release, and should be considered beta level software (version 0.9.6). We expect you to find issues, primarily in unimplemented instructions or unimplemented system calls. Please let us know when you hit these, either by submitting a pull request (PR), or by filing an issue on the Github repo. You can find the all the code and associated test suites for SimEng in the `GitHub repository `_. The file `RELEASE_NOTES.txt `_, found in the root of the project, explains the status of the project and includes other relevant information from the SimEng development team. SimEng is released under the same license as LLVM, the permissive `Apache 2.0 `_ license. We are passionate about enabling experimentation with computer architectures, and want users and developers in academic and industry to have complete freedom to use SimEng anyway they wish, including using it in commercial settings. From eb39159e023c2e57030810e0a33feefebd6dd296 Mon Sep 17 00:00:00 2001 From: jj16791 Date: Tue, 20 Feb 2024 19:25:00 +0000 Subject: [PATCH 02/11] Updated riscv extension string --- RELEASE-NOTES.txt | 4 ++-- docs/sphinx/index.rst | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/RELEASE-NOTES.txt b/RELEASE-NOTES.txt index 2a8a1c68e0..347c32e436 100644 --- a/RELEASE-NOTES.txt +++ b/RELEASE-NOTES.txt @@ -1,4 +1,4 @@ -Welcome to the 0.9.6 open source release of the Simulation Engine! SimEng is a fast, easy to use and modify, cycle-level simulator for CPUs. Its initial focus is on simulating single Arm cores in server CPUs, and so the instruction set architecture (ISA) target is initially Arm9.2-a+SVE+SME. RISC-V has also seen some inital support, starting with rv64ima. Later versions of the Arm ISA, additional RISC-V ISA extensions and other ISAs, will be supported in future releases. +Welcome to the 0.9.6 open source release of the Simulation Engine! SimEng is a fast, easy to use and modify, cycle-level simulator for CPUs. Its initial focus is on simulating single Arm cores in server CPUs, and so the instruction set architecture (ISA) target is initially Arm9.2-a+SVE+SME. RISC-V has also seen some inital support, starting with rv64imafd. Later versions of the Arm ISA, additional RISC-V ISA extensions and other ISAs, will be supported in future releases. This SimEng release should be considered beta software - you are the first users outside of the core developers, so there *will* be lots of bugs and missing features. The good news is that the code has been designed to be simple to understand and modify, so if you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll get to it as soon as we can. @@ -10,7 +10,7 @@ SimEng should be fast, much faster than other cycle-level CPU simulators. The fa Things that should work in this release include: * Static AArch64, with SVE/SME, binaries compiled with either GCC 7.3 or later, or Arm Clang 20/LLVM 9 or later -* Static RISC-V binaries targetting rv64ima and compiled with GCC 12.2.0 +* Static RISC-V binaries targetting rv64imafd and compiled with GCC 12.2.0 * Single thread OpenMP programs * Binaries compiled from Fortran or C programs diff --git a/docs/sphinx/index.rst b/docs/sphinx/index.rst index dca6969b24..74a6e39936 100644 --- a/docs/sphinx/index.rst +++ b/docs/sphinx/index.rst @@ -50,7 +50,7 @@ SimEng places an emphasis on performance and ease of use, whilst maintaining a c Features -------- -Currently, SimEng targets the Armv9.2-a ISA with support for the SVE, SVE2, and SME extensions as well as RISC-V rv64ima. SimEng has the ability to model up to out-of-order, superscalar, single-core processors, and to emulate a subset of Linux system-calls. It supports statically compiled C and Fortran binaries that run on real hardware, with additional support for single-threaded OpenMP binaries too. Internally, SimEng currently models memory as an infinite L1 cache, i.e. it assumes that all loads and stores hit the L1 cache. However, we have a tested integration with the `Structural Simulation Toolkit `_ (SST) allowing for a full memory model to be simulated; more information can be found in the :doc:`SST Integration section `. +Currently, SimEng targets the Armv9.2-a ISA with support for the SVE, SVE2, and SME extensions as well as RISC-V rv64imafd. SimEng has the ability to model up to out-of-order, superscalar, single-core processors, and to emulate a subset of Linux system-calls. It supports statically compiled C and Fortran binaries that run on real hardware, with additional support for single-threaded OpenMP binaries too. Internally, SimEng currently models memory as an infinite L1 cache, i.e. it assumes that all loads and stores hit the L1 cache. However, we have a tested integration with the `Structural Simulation Toolkit `_ (SST) allowing for a full memory model to be simulated; more information can be found in the :doc:`SST Integration section `. The main component provided by the simulator is a discrete processor core model, shown in diagrammatic form below. This model accepts a clock signal and supports a memory access interface. A single YAML format configuration file can be passed to the simulation to specify models of existing microarchitectures, such as Marvell's ThunderX2 or Fujitsu's A64fx, or to model hypothetical core designs. From 2cdddcdd357fad16a2b76b4a4cd0ee4c7481653f Mon Sep 17 00:00:00 2001 From: jj16791 Date: Tue, 20 Feb 2024 19:35:30 +0000 Subject: [PATCH 03/11] Updated overview of riscv extension support in the release notes --- RELEASE-NOTES.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/RELEASE-NOTES.txt b/RELEASE-NOTES.txt index 347c32e436..8d480f9326 100644 --- a/RELEASE-NOTES.txt +++ b/RELEASE-NOTES.txt @@ -1,4 +1,4 @@ -Welcome to the 0.9.6 open source release of the Simulation Engine! SimEng is a fast, easy to use and modify, cycle-level simulator for CPUs. Its initial focus is on simulating single Arm cores in server CPUs, and so the instruction set architecture (ISA) target is initially Arm9.2-a+SVE+SME. RISC-V has also seen some inital support, starting with rv64imafd. Later versions of the Arm ISA, additional RISC-V ISA extensions and other ISAs, will be supported in future releases. +Welcome to the 0.9.6 open source release of the Simulation Engine! SimEng is a fast, easy to use and modify, cycle-level simulator for CPUs. Its initial focus is on simulating single Arm cores in server CPUs, and so the instruction set architecture (ISA) target is initially Arm9.2-a+SVE+SME. There is also RISC-V support currently covering the rv64imafd set of extensions. Later versions of the Arm ISA, additional RISC-V ISA extensions and other ISAs, will be supported in future releases. This SimEng release should be considered beta software - you are the first users outside of the core developers, so there *will* be lots of bugs and missing features. The good news is that the code has been designed to be simple to understand and modify, so if you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll get to it as soon as we can. From 6cf41a1f698d65186f9aac0f4ba403a5e293f224 Mon Sep 17 00:00:00 2001 From: jj16791 Date: Wed, 21 Feb 2024 09:06:40 +0000 Subject: [PATCH 04/11] Updated RISCV string --- RELEASE-NOTES.txt | 2 +- docs/sphinx/index.rst | 4 ++-- src/lib/arch/riscv/Instruction_execute.cc | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/RELEASE-NOTES.txt b/RELEASE-NOTES.txt index 8d480f9326..ed7b7cbf3d 100644 --- a/RELEASE-NOTES.txt +++ b/RELEASE-NOTES.txt @@ -1,4 +1,4 @@ -Welcome to the 0.9.6 open source release of the Simulation Engine! SimEng is a fast, easy to use and modify, cycle-level simulator for CPUs. Its initial focus is on simulating single Arm cores in server CPUs, and so the instruction set architecture (ISA) target is initially Arm9.2-a+SVE+SME. There is also RISC-V support currently covering the rv64imafd set of extensions. Later versions of the Arm ISA, additional RISC-V ISA extensions and other ISAs, will be supported in future releases. +Welcome to the 0.9.6 open source release of the Simulation Engine! SimEng is a fast, easy to use and modify, cycle-level simulator for CPUs. Its initial focus is on simulating single Arm cores in server CPUs, and so the instruction set architecture (ISA) target is initially Arm9.2-a+SVE+SME. There is also RISC-V support currently covering the rv64imafdc set of extensions. Later versions of the Arm ISA, additional RISC-V ISA extensions and other ISAs, will be supported in future releases. This SimEng release should be considered beta software - you are the first users outside of the core developers, so there *will* be lots of bugs and missing features. The good news is that the code has been designed to be simple to understand and modify, so if you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll get to it as soon as we can. diff --git a/docs/sphinx/index.rst b/docs/sphinx/index.rst index 74a6e39936..41bd9ffa40 100644 --- a/docs/sphinx/index.rst +++ b/docs/sphinx/index.rst @@ -50,7 +50,7 @@ SimEng places an emphasis on performance and ease of use, whilst maintaining a c Features -------- -Currently, SimEng targets the Armv9.2-a ISA with support for the SVE, SVE2, and SME extensions as well as RISC-V rv64imafd. SimEng has the ability to model up to out-of-order, superscalar, single-core processors, and to emulate a subset of Linux system-calls. It supports statically compiled C and Fortran binaries that run on real hardware, with additional support for single-threaded OpenMP binaries too. Internally, SimEng currently models memory as an infinite L1 cache, i.e. it assumes that all loads and stores hit the L1 cache. However, we have a tested integration with the `Structural Simulation Toolkit `_ (SST) allowing for a full memory model to be simulated; more information can be found in the :doc:`SST Integration section `. +Currently, SimEng targets the Armv9.2-a ISA with support for the SVE, SVE2, and SME extensions as well as RISC-V rv64imafdc. SimEng has the ability to model up to out-of-order, superscalar, single-core processors, and to emulate a subset of Linux system-calls. It supports statically compiled C and Fortran binaries that run on real hardware, with additional support for single-threaded OpenMP binaries too. Internally, SimEng currently models memory as an infinite L1 cache, i.e. it assumes that all loads and stores hit the L1 cache. However, we have a tested integration with the `Structural Simulation Toolkit `_ (SST) allowing for a full memory model to be simulated; more information can be found in the :doc:`SST Integration section `. The main component provided by the simulator is a discrete processor core model, shown in diagrammatic form below. This model accepts a clock signal and supports a memory access interface. A single YAML format configuration file can be passed to the simulation to specify models of existing microarchitectures, such as Marvell's ThunderX2 or Fujitsu's A64fx, or to model hypothetical core designs. @@ -80,7 +80,7 @@ Additionally, other works concerning SimEng and its use can be found below: Release ------- -This is SimEng's seventh release, and should be considered beta level software (version 0.9.6). We expect you to find issues, primarily in unimplemented instructions or unimplemented system calls. Please let us know when you hit these, either by submitting a pull request (PR), or by filing an issue on the Github repo. You can find the all the code and associated test suites for SimEng in the `GitHub repository `_. The file `RELEASE_NOTES.txt `_, found in the root of the project, explains the status of the project and includes other relevant information from the SimEng development team. +This is SimEng's eighth release, and should be considered beta level software (version 0.9.6). We expect you to find issues, primarily in unimplemented instructions or unimplemented system calls. Please let us know when you hit these, either by submitting a pull request (PR), or by filing an issue on the Github repo. You can find the all the code and associated test suites for SimEng in the `GitHub repository `_. The file `RELEASE_NOTES.txt `_, found in the root of the project, explains the status of the project and includes other relevant information from the SimEng development team. SimEng is released under the same license as LLVM, the permissive `Apache 2.0 `_ license. We are passionate about enabling experimentation with computer architectures, and want users and developers in academic and industry to have complete freedom to use SimEng anyway they wish, including using it in commercial settings. diff --git a/src/lib/arch/riscv/Instruction_execute.cc b/src/lib/arch/riscv/Instruction_execute.cc index 2b7e7255e2..9910183316 100644 --- a/src/lib/arch/riscv/Instruction_execute.cc +++ b/src/lib/arch/riscv/Instruction_execute.cc @@ -177,7 +177,7 @@ void Instruction::execute() { "Attempted to execute an instruction before all source operands were " "provided"); - // Implementation of rv64iamfdc according to the v. 20191213 unprivileged spec + // Implementation of rv64imafdc according to the v. 20191213 unprivileged spec executed_ = true; switch (metadata_.opcode) { From bdda151590b81bdf9808b6cb1ee0b5a927f88c40 Mon Sep 17 00:00:00 2001 From: jj16791 Date: Wed, 21 Feb 2024 09:06:59 +0000 Subject: [PATCH 05/11] Fixed config integration test --- test/integration/ConfigTest.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/integration/ConfigTest.cc b/test/integration/ConfigTest.cc index 5e0772a26f..12c295d2d4 100644 --- a/test/integration/ConfigTest.cc +++ b/test/integration/ConfigTest.cc @@ -95,7 +95,7 @@ TEST(ConfigTest, Default) { emittedConfig = ryml::emitrs_yaml(simeng::config::SimInfo::getConfig()); expectedValues = - "Core:\n ISA: rv64\n 'Simulation-Mode': emulation\n " + "Core:\n ISA: rv64\n Compressed: 0\n 'Simulation-Mode': emulation\n " "'Clock-Frequency-GHz': 1\n 'Timer-Frequency-MHz': 100\n " "'Micro-Operations': 0\nFetch:\n 'Fetch-Block-Size': 32\n " "'Loop-Buffer-Size': 32\n 'Loop-Detection-Threshold': " From 3c0459cb5cf3ac6386f41eaf8334f247ac0b7622 Mon Sep 17 00:00:00 2001 From: jj16791 Date: Wed, 21 Feb 2024 11:23:18 +0000 Subject: [PATCH 06/11] Fixed incorrect MIPS figures --- RELEASE-NOTES.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/RELEASE-NOTES.txt b/RELEASE-NOTES.txt index ed7b7cbf3d..fdecc5c30b 100644 --- a/RELEASE-NOTES.txt +++ b/RELEASE-NOTES.txt @@ -6,11 +6,11 @@ You can find all the user and developer documentation on the SimEng webpage: https://uob-hpc.github.io/SimEng/index.html -SimEng should be fast, much faster than other cycle-level CPU simulators. The fastest hardware we’ve run it on is an M1-Ultra Mac Studio, where we’ve measured SimEng running at up to ~1.2 MIPS for the Out of Order (OoO) core in our ThunderX2 and A64fx models. SVE (vector) and SME (matrix) codes are more complex to simulate and tend to be slower - on the same hardware we saw simulated SVE codes running at around 0.9 MIPS and SME codes at around 0.8 MIPS. +SimEng should be fast, much faster than other cycle-level CPU simulators. The fastest hardware we’ve run it on is an M1-Ultra Mac Studio, where we’ve measured SimEng running at up to 1.4 MIPS for the Out of Order (OoO) core in our ThunderX2 and A64fx models. SVE (vector) and SME (matrix) codes are more complex to simulate and tend to be slower - on the same hardware we saw simulated SVE codes running at around 1.1 MIPS and SME codes at around 0.9 MIPS. Things that should work in this release include: * Static AArch64, with SVE/SME, binaries compiled with either GCC 7.3 or later, or Arm Clang 20/LLVM 9 or later -* Static RISC-V binaries targetting rv64imafd and compiled with GCC 12.2.0 +* Static RISC-V binaries targetting rv64imafdc and compiled with GCC 12.2.0 * Single thread OpenMP programs * Binaries compiled from Fortran or C programs From 56661d35498242eaf97ca9a16696a779e1212bb8 Mon Sep 17 00:00:00 2001 From: jj16791 Date: Wed, 21 Feb 2024 14:00:06 +0000 Subject: [PATCH 07/11] Comment fixes --- docs/sphinx/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/sphinx/index.rst b/docs/sphinx/index.rst index 41bd9ffa40..ac7026f9a9 100644 --- a/docs/sphinx/index.rst +++ b/docs/sphinx/index.rst @@ -70,7 +70,7 @@ SimEng was first presented by `Professor Simon McIntosh-Smith `_ +- Second International workshop on RISC-V for HPC at SC2023 - `An Empirical Comparison of the RISC-V and AArch64 Instruction Sets `_ - ModSim 2023 - :download:`Leveraging Arm's Scalable Matrix Extension to Accelerate Matrix Multiplication Kernels ` - PMBS 2022 - `An Initial Evaluation of Arm's Scalable Matrix Extension `_ - ModSim 2022 - :download:`A design space exploration for optimal vector unit composition ` @@ -80,7 +80,7 @@ Additionally, other works concerning SimEng and its use can be found below: Release ------- -This is SimEng's eighth release, and should be considered beta level software (version 0.9.6). We expect you to find issues, primarily in unimplemented instructions or unimplemented system calls. Please let us know when you hit these, either by submitting a pull request (PR), or by filing an issue on the Github repo. You can find the all the code and associated test suites for SimEng in the `GitHub repository `_. The file `RELEASE_NOTES.txt `_, found in the root of the project, explains the status of the project and includes other relevant information from the SimEng development team. +This is SimEng's eighth release, and should be considered beta level software (version 0.9.6). We expect you to find issues, primarily in unimplemented instructions or unimplemented system calls. Please let us know when you hit these, either by submitting a pull request (PR), or by filing an issue on the Github repo. You can find all the code and associated test suites for SimEng in the `GitHub repository `_. The file `RELEASE_NOTES.txt `_, found in the root of the project, explains the status of the project and includes other relevant information from the SimEng development team. SimEng is released under the same license as LLVM, the permissive `Apache 2.0 `_ license. We are passionate about enabling experimentation with computer architectures, and want users and developers in academic and industry to have complete freedom to use SimEng anyway they wish, including using it in commercial settings. From 76510e1ed4c8da92d2e74590d85e70208906b95f Mon Sep 17 00:00:00 2001 From: jj16791 Date: Wed, 21 Feb 2024 16:09:50 +0000 Subject: [PATCH 08/11] Updated sphinx version to be compatible with more modern themes --- docs/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/requirements.txt b/docs/requirements.txt index 176c63857f..a1b07749b6 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,4 +1,4 @@ -Sphinx==1.6.7 +Sphinx==5.0.0 sphinx-rtd-theme==0.5.2 mistune==0.8.4 m2r2==0.3.1 From d52b43188dae48cb2deae016cbded085df2e8f84 Mon Sep 17 00:00:00 2001 From: jj16791 Date: Wed, 21 Feb 2024 16:14:22 +0000 Subject: [PATCH 09/11] Changed circleCI config to run docs builder on dev as well --- .circleci/config.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index fb75f0311f..c50f328582 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -49,4 +49,6 @@ workflows: - docs-build filters: branches: - only: main \ No newline at end of file + only: + - main + - dev \ No newline at end of file From 3b082239f347b6d264eae041ebdc5b3ae01e6b30 Mon Sep 17 00:00:00 2001 From: jj16791 Date: Wed, 21 Feb 2024 16:17:47 +0000 Subject: [PATCH 10/11] Reverted circleCI change --- .circleci/config.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index c50f328582..27cca27cd1 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -50,5 +50,4 @@ workflows: filters: branches: only: - - main - - dev \ No newline at end of file + - main \ No newline at end of file From 35d60148cd357c58f11c4416c4abc168cdce2eb9 Mon Sep 17 00:00:00 2001 From: jj16791 Date: Wed, 21 Feb 2024 16:19:26 +0000 Subject: [PATCH 11/11] Updated jinja2 python package to resolve vulnerability --- docs/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/requirements.txt b/docs/requirements.txt index a1b07749b6..58104ce890 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -2,4 +2,4 @@ Sphinx==5.0.0 sphinx-rtd-theme==0.5.2 mistune==0.8.4 m2r2==0.3.1 -Jinja2==3.0.3 \ No newline at end of file +Jinja2==3.1.3 \ No newline at end of file