From d9da9f2813b9ea2b4b7df3711e9e2248f0d2f12b Mon Sep 17 00:00:00 2001 From: JosephMoore25 Date: Wed, 1 May 2024 12:47:54 +0100 Subject: [PATCH] Corrected RV shift word instructions --- src/lib/arch/riscv/Instruction_execute.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/lib/arch/riscv/Instruction_execute.cc b/src/lib/arch/riscv/Instruction_execute.cc index 9910183316..cacce63561 100644 --- a/src/lib/arch/riscv/Instruction_execute.cc +++ b/src/lib/arch/riscv/Instruction_execute.cc @@ -243,14 +243,14 @@ void Instruction::execute() { case Opcode::RISCV_SLLW: { // SLLW rd,rs1,rs2 const int32_t rs1 = sourceValues_[0].get(); const int32_t rs2 = - sourceValues_[1].get() & 63; // Only use lowest 6 bits + sourceValues_[1].get() & 31; // Only use lowest 5 bits int64_t out = signExtendW(static_cast(rs1 << rs2)); results_[0] = RegisterValue(out, 8); break; } case Opcode::RISCV_SLLIW: { // SLLIW rd,rs1,shamt const int32_t rs1 = sourceValues_[0].get(); - const int32_t shamt = sourceImm_ & 63; // Only use lowest 6 bits + const int32_t shamt = sourceImm_ & 31; // Only use lowest 5 bits uint64_t out = signExtendW(static_cast(rs1 << shamt)); results_[0] = RegisterValue(out, 8); break; @@ -273,14 +273,14 @@ void Instruction::execute() { case Opcode::RISCV_SRLW: { // SRLW rd,rs1,rs2 const uint32_t rs1 = sourceValues_[0].get(); const uint32_t rs2 = - sourceValues_[1].get() & 63; // Only use lowest 6 bits + sourceValues_[1].get() & 31; // Only use lowest 5 bits uint64_t out = signExtendW(static_cast(rs1 >> rs2)); results_[0] = RegisterValue(out, 8); break; } case Opcode::RISCV_SRLIW: { // SRLIW rd,rs1,shamt const uint32_t rs1 = sourceValues_[0].get(); - const uint32_t shamt = sourceImm_ & 63; // Only use lowest 6 bits + const uint32_t shamt = sourceImm_ & 31; // Only use lowest 5 bits uint64_t out = signExtendW(static_cast(rs1 >> shamt)); results_[0] = RegisterValue(out, 8); break; @@ -303,14 +303,14 @@ void Instruction::execute() { case Opcode::RISCV_SRAW: { // SRAW rd,rs1,rs2 const int32_t rs1 = sourceValues_[0].get(); const int32_t rs2 = - sourceValues_[1].get() & 63; // Only use lowest 6 bits + sourceValues_[1].get() & 31; // Only use lowest 5 bits int64_t out = static_cast(rs1 >> rs2); results_[0] = RegisterValue(out, 8); break; } case Opcode::RISCV_SRAIW: { // SRAIW rd,rs1,shamt const int32_t rs1 = sourceValues_[0].get(); - const int32_t shamt = sourceImm_ & 63; // Only use lowest 6 bits + const int32_t shamt = sourceImm_ & 31; // Only use lowest 5 bits int64_t out = static_cast(rs1 >> shamt); results_[0] = RegisterValue(out, 8); break;