From ae73a0038d3bdc13689230c6c83872fa3a37ab02 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Tue, 6 Oct 2020 17:49:08 +0900 Subject: [PATCH 01/19] arch: cxd56xx: Introduce cxd56_cpuindex.h Signed-off-by: Masayuki Ishikawa --- arch/arm/src/cxd56xx/cxd56_cpuindex.c | 7 +------ arch/arm/src/cxd56xx/cxd56_cpuindex.h | 30 +++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 6 deletions(-) create mode 100644 arch/arm/src/cxd56xx/cxd56_cpuindex.h diff --git a/arch/arm/src/cxd56xx/cxd56_cpuindex.c b/arch/arm/src/cxd56xx/cxd56_cpuindex.c index f850af0e8e480..1d9fa85323996 100644 --- a/arch/arm/src/cxd56xx/cxd56_cpuindex.c +++ b/arch/arm/src/cxd56xx/cxd56_cpuindex.c @@ -42,15 +42,10 @@ #include #include "arm_arch.h" +#include "cxd56_cpuindex.h" #ifdef CONFIG_SMP -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define CXD56_ADSP_PID 0x0e002040 /* APP_DSP Processor ID */ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/arm/src/cxd56xx/cxd56_cpuindex.h b/arch/arm/src/cxd56xx/cxd56_cpuindex.h new file mode 100644 index 0000000000000..651759c3969b1 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_cpuindex.h @@ -0,0 +1,30 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_cpuindex.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CPUINDEX_H +#define __ARCH_ARM_SRC_CXD56XX_CXD56_CPUINDEX_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CXD56_ADSP_PID 0x0e002040 /* APP_DSP Processor ID */ + +#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CPUINDEX_H */ From 4cde35342e81d220f7a70057af8d7ec9e0fb7efa Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Tue, 6 Oct 2020 18:10:58 +0900 Subject: [PATCH 02/19] arch: cxd56xx: Add interrupt stack for SMP Summary: - This commit adds interrupt stack for SMP Impact: - Affects SMP only Testing: - Tested with spresense:wifi_smp with CONFIG_ARCH_INTERRUPTSTACK=2048 Signed-off-by: Masayuki Ishikawa --- arch/arm/src/cxd56xx/chip.h | 64 ++++++++++++++++++++++++++++++++ arch/arm/src/cxd56xx/cxd56_irq.c | 57 ++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+) diff --git a/arch/arm/src/cxd56xx/chip.h b/arch/arm/src/cxd56xx/chip.h index 33240c5b08aa4..c25c9bdf65a2c 100644 --- a/arch/arm/src/cxd56xx/chip.h +++ b/arch/arm/src/cxd56xx/chip.h @@ -42,6 +42,10 @@ #include +#ifndef __ASSEMBLY__ +# include +#endif + /* Include the chip capabilities file */ #include @@ -50,4 +54,64 @@ #include "hardware/cxd5602_memorymap.h" +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +# include "cxd56_cpuindex.h" +#endif + +/**************************************************************************** + * Macro Definitions + ****************************************************************************/ + +#ifdef __ASSEMBLY__ + +/**************************************************************************** + * Name: setintstack + * + * Description: + * Set the current stack pointer to the "top" the correct interrupt stack + * for the current CPU. + * + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 + .macro setintstack, tmp1, tmp2 +#if CONFIG_SMP_NCPUS > 1 + ldr \tmp1, =CXD56_ADSP_PID + ldr \tmp1, [\tmp1, 0] + sub \tmp1, 2 /* tmp1 = getreg32(CXD56_ADSP_PID) - 2 */ + ldr \tmp2, =g_cpu_intstack_top + ldr sp, [\tmp2, \tmp1, lsl #2] /* sp = g_cpu_intstack_top[tmp1] */ +#endif + .endm +#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */ + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +uintptr_t arm_intstack_base(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_H */ diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c index 8a562f659bae4..805e5d59fd3f9 100644 --- a/arch/arm/src/cxd56xx/cxd56_irq.c +++ b/arch/arm/src/cxd56xx/cxd56_irq.c @@ -72,6 +72,13 @@ #define INTC_EN(n) (CXD56_INTC_BASE + 0x10 + (((n) >> 5) << 2)) +/* Interrupt stack definitions for SMP */ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +# define INTSTACK_SIZE CONFIG_ARCH_INTERRUPTSTACK +# define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE) +#endif + /**************************************************************************** * Public Data ****************************************************************************/ @@ -97,6 +104,36 @@ static volatile int8_t g_cpu_for_irq[CXD56_IRQ_NIRQS]; extern void up_send_irqreq(int idx, int irq, int cpu); #endif +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +/* In the SMP configuration, we will need custom interrupt stacks. + * These definitions provide the aligned stack allocations. + */ + +static uint64_t g_intstack_alloc[INTSTACK_ALLOC >> 3]; + +/* These definitions provide the "top" of the push-down stacks. */ + +const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] = +{ + (uint32_t)g_intstack_alloc + INTSTACK_SIZE, +#if CONFIG_SMP_NCPUS > 1 + (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE), +#if CONFIG_SMP_NCPUS > 2 + (uint32_t)g_intstack_alloc + (3 * INTSTACK_SIZE), +#if CONFIG_SMP_NCPUS > 3 + (uint32_t)g_intstack_alloc + (4 * INTSTACK_SIZE), +#if CONFIG_SMP_NCPUS > 4 + (uint32_t)g_intstack_alloc + (5 * INTSTACK_SIZE), +#if CONFIG_SMP_NCPUS > 5 + (uint32_t)g_intstack_alloc + (6 * INTSTACK_SIZE), +#endif /* CONFIG_SMP_NCPUS > 5 */ +#endif /* CONFIG_SMP_NCPUS > 4 */ +#endif /* CONFIG_SMP_NCPUS > 3 */ +#endif /* CONFIG_SMP_NCPUS > 2 */ +#endif /* CONFIG_SMP_NCPUS > 1 */ +}; +#endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 */ + /* This is the address of the exception vector table (determined by the * linker script). */ @@ -604,3 +641,23 @@ int up_prioritize_irq(int irq, int priority) return OK; } #endif + +/**************************************************************************** + * Name: arm_intstack_base + * + * Description: + * Return a pointer to the "base" the correct interrupt stack allocation + * for the current CPU. + * + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +uintptr_t arm_intstack_base(void) +{ + uintptr_t base = (uintptr_t)g_intstack_alloc; + uint32_t cpu = up_cpu_index(); + base += cpu * INTSTACK_SIZE; + + return base; +} +#endif From 36f5ce65afb99a340b13b257b14c6f304ac94d50 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 19 Oct 2020 13:04:54 +0900 Subject: [PATCH 03/19] arch: imx6: Fix style warnings in chip.h Signed-off-by: Masayuki Ishikawa --- arch/arm/src/imx6/chip.h | 54 +++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 29 deletions(-) diff --git a/arch/arm/src/imx6/chip.h b/arch/arm/src/imx6/chip.h index b22e877cdd205..54a31a38fadb6 100644 --- a/arch/arm/src/imx6/chip.h +++ b/arch/arm/src/imx6/chip.h @@ -72,8 +72,8 @@ #ifdef __ASSEMBLY__ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .globl g_irqstack_top - .globl g_fiqstack_top + .globl g_irqstack_top + .globl g_fiqstack_top #endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */ #endif /* __ASSEMBLY__ */ @@ -84,7 +84,7 @@ #ifdef __ASSEMBLY__ -/*************************************************************************** +/**************************************************************************** * Name: cpuindex * * Description: @@ -93,30 +93,30 @@ ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .macro cpuindex, index - mrc p15, 0, \index, c0, c0, 5 /* Read the MPIDR */ - and \index, \index, #3 /* Bits 0-1=CPU ID */ - .endm + .macro cpuindex, index + mrc p15, 0, \index, c0, c0, 5 /* Read the MPIDR */ + and \index, \index, #3 /* Bits 0-1=CPU ID */ + .endm #endif -/*************************************************************************** +/**************************************************************************** * Name: setirqstack * * Description: * Set the current stack pointer to the -"top" of the IRQ interrupt * stack for the current CPU. * - ***************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .macro setirqstack, tmp1, tmp2 - mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */ - and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */ - ldr \tmp2, =g_irqstack_top /* tmp2=Array of IRQ stack pointers */ - lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */ - add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */ - ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */ - .endm + .macro setirqstack, tmp1, tmp2 + mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */ + and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */ + ldr \tmp2, =g_irqstack_top /* tmp2=Array of IRQ stack pointers */ + lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */ + add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */ + ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */ + .endm #endif /**************************************************************************** @@ -129,14 +129,14 @@ ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .macro setfiqstack, tmp1, tmp2 - mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */ - and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */ - ldr \tmp2, =g_fiqstack_top /* tmp2=Array of FIQ stack pointers */ - lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */ - add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */ - ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */ - .endm + .macro setfiqstack, tmp1, tmp2 + mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */ + and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */ + ldr \tmp2, =g_fiqstack_top /* tmp2=Array of FIQ stack pointers */ + lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */ + add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */ + ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */ + .endm #endif #endif /* __ASSEMBLY__ */ @@ -188,8 +188,4 @@ static inline uintptr_t arm_intstack_top(void) #endif /* !__ASSEMBLY__ */ -/**************************************************************************** - * Public Functions - ****************************************************************************/ - #endif /* __ARCH_ARM_SRC_IMX6_CHIP_H */ From fc3e7fefa0db500399ef4e7ac3db0daa0eea240a Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 19 Oct 2020 21:48:47 +0900 Subject: [PATCH 04/19] arch: arm: Fix interrupt stack handlings for SMP Summary: - Modify arm_intstack_base() to return "top" of the IRQ stack for the current CPU - This change fixes IRQ stack dump information for ARM SMP - Add arm_intstack_alloc() to return "bottom" of the IRQ stack for the current CPU - Also, these functions are now implemented in xxx_irq.c (imx/cxd56/lc823450) - up_color_intstack() and up_check_intstack() now call arm_intstack_alloc() - These semantics are now consistent with non-SMP case - up_color_intstack() now initializes whole IRQ stack region for SMP - Adjust IRQ stack top address for each CPU (e.g. -8) - Fix setintstack to handle in case of NCPUS=1 (cxd56, lc823450) - Adjust INTSTACK_SIZE to 8 bytes alignment (cxd56, lc823450) - Refactor setintstack for lc823450 - Remove old IRQ stack coloring code from up_irqinitialize() (lc823450) - Introduce g_cpu_intstack_top for lc823450 - Refactor header files Impact: - Affects imx6/cxd56xx/lc823450 SMP with interrupt stack enabled Testing: - Tested with sabre-6quad:smp (with QEMU, NCPUS=1 and 4) - Tested with spresense:wifi_smp (NCPUS=1 and 2) - Tested with lc823450-xgevk:rndis (NCPUS=1 and 2) Signed-off-by: Masayuki Ishikawa --- arch/arm/src/common/arm_checkstack.c | 2 +- arch/arm/src/common/arm_initialize.c | 6 +- arch/arm/src/cxd56xx/chip.h | 31 +--------- arch/arm/src/cxd56xx/cxd56_irq.c | 37 +++++++----- arch/arm/src/cxd56xx/cxd56_irq.h | 15 +++-- arch/arm/src/imx6/chip.h | 64 --------------------- arch/arm/src/imx6/imx_irq.c | 40 +++++++++++-- arch/arm/src/imx6/imx_irq.h | 20 ++----- arch/arm/src/lc823450/chip.h | 85 ++-------------------------- arch/arm/src/lc823450/lc823450_irq.c | 56 ++++++++++++------ arch/arm/src/lc823450/lc823450_irq.h | 21 ++----- 11 files changed, 130 insertions(+), 247 deletions(-) diff --git a/arch/arm/src/common/arm_checkstack.c b/arch/arm/src/common/arm_checkstack.c index c3e51ba8e011e..efd736e3d209c 100644 --- a/arch/arm/src/common/arm_checkstack.c +++ b/arch/arm/src/common/arm_checkstack.c @@ -245,7 +245,7 @@ ssize_t up_check_stack_remain(void) size_t up_check_intstack(void) { #ifdef CONFIG_SMP - return do_stackcheck((FAR void *)arm_intstack_base(), + return do_stackcheck((FAR void *)arm_intstack_alloc(), INT32_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)); #else return do_stackcheck((FAR void *)&g_intstackalloc, diff --git a/arch/arm/src/common/arm_initialize.c b/arch/arm/src/common/arm_initialize.c index e73e3e9281300..291ff5c23e37a 100644 --- a/arch/arm/src/common/arm_initialize.c +++ b/arch/arm/src/common/arm_initialize.c @@ -62,13 +62,17 @@ static inline void up_color_intstack(void) { #ifdef CONFIG_SMP - uint32_t *ptr = (uint32_t *)arm_intstack_base(); + uint32_t *ptr = (uint32_t *)arm_intstack_alloc(); #else uint32_t *ptr = (uint32_t *)&g_intstackalloc; #endif ssize_t size; +#ifdef CONFIG_SMP + for (size = ((CONFIG_ARCH_INTERRUPTSTACK & ~3) * CONFIG_SMP_NCPUS); +#else for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); +#endif size > 0; size -= sizeof(uint32_t)) { diff --git a/arch/arm/src/cxd56xx/chip.h b/arch/arm/src/cxd56xx/chip.h index c25c9bdf65a2c..d952f0448f320 100644 --- a/arch/arm/src/cxd56xx/chip.h +++ b/arch/arm/src/cxd56xx/chip.h @@ -56,6 +56,7 @@ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 # include "cxd56_cpuindex.h" +# include "cxd56_irq.h" #endif /**************************************************************************** @@ -75,43 +76,13 @@ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 .macro setintstack, tmp1, tmp2 -#if CONFIG_SMP_NCPUS > 1 ldr \tmp1, =CXD56_ADSP_PID ldr \tmp1, [\tmp1, 0] sub \tmp1, 2 /* tmp1 = getreg32(CXD56_ADSP_PID) - 2 */ ldr \tmp2, =g_cpu_intstack_top ldr sp, [\tmp2, \tmp1, lsl #2] /* sp = g_cpu_intstack_top[tmp1] */ -#endif .endm #endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */ #endif /* __ASSEMBLY__ */ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_base(void); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_H */ diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c index 805e5d59fd3f9..f113dcef06f9e 100644 --- a/arch/arm/src/cxd56xx/cxd56_irq.c +++ b/arch/arm/src/cxd56xx/cxd56_irq.c @@ -72,10 +72,7 @@ #define INTC_EN(n) (CXD56_INTC_BASE + 0x10 + (((n) >> 5) << 2)) -/* Interrupt stack definitions for SMP */ - #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -# define INTSTACK_SIZE CONFIG_ARCH_INTERRUPTSTACK # define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE) #endif @@ -115,17 +112,17 @@ static uint64_t g_intstack_alloc[INTSTACK_ALLOC >> 3]; const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] = { - (uint32_t)g_intstack_alloc + INTSTACK_SIZE, + (uint32_t)g_intstack_alloc + INTSTACK_SIZE - 8, #if CONFIG_SMP_NCPUS > 1 - (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE), + (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE) - 8, #if CONFIG_SMP_NCPUS > 2 - (uint32_t)g_intstack_alloc + (3 * INTSTACK_SIZE), + (uint32_t)g_intstack_alloc + (3 * INTSTACK_SIZE) - 8, #if CONFIG_SMP_NCPUS > 3 - (uint32_t)g_intstack_alloc + (4 * INTSTACK_SIZE), + (uint32_t)g_intstack_alloc + (4 * INTSTACK_SIZE) - 8, #if CONFIG_SMP_NCPUS > 4 - (uint32_t)g_intstack_alloc + (5 * INTSTACK_SIZE), + (uint32_t)g_intstack_alloc + (5 * INTSTACK_SIZE) - 8, #if CONFIG_SMP_NCPUS > 5 - (uint32_t)g_intstack_alloc + (6 * INTSTACK_SIZE), + (uint32_t)g_intstack_alloc + (6 * INTSTACK_SIZE) - 8, #endif /* CONFIG_SMP_NCPUS > 5 */ #endif /* CONFIG_SMP_NCPUS > 4 */ #endif /* CONFIG_SMP_NCPUS > 3 */ @@ -647,17 +644,29 @@ int up_prioritize_irq(int irq, int priority) * * Description: * Return a pointer to the "base" the correct interrupt stack allocation - * for the current CPU. + * for the current CPU. NOTE: Here, the base means "top" of the stack * ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 uintptr_t arm_intstack_base(void) { - uintptr_t base = (uintptr_t)g_intstack_alloc; - uint32_t cpu = up_cpu_index(); - base += cpu * INTSTACK_SIZE; + return g_cpu_intstack_top[up_cpu_index()]; +} +#endif - return base; +/**************************************************************************** + * Name: arm_intstack_alloc + * + * Description: + * Return a pointer to the "alloc" the correct interrupt stack allocation + * for the current CPU. + * + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +uintptr_t arm_intstack_alloc(void) +{ + return g_cpu_intstack_top[up_cpu_index()] - (INTSTACK_SIZE - 8); } #endif diff --git a/arch/arm/src/cxd56xx/cxd56_irq.h b/arch/arm/src/cxd56xx/cxd56_irq.h index 09241d050d230..22077e8b3ca3f 100644 --- a/arch/arm/src/cxd56xx/cxd56_irq.h +++ b/arch/arm/src/cxd56xx/cxd56_irq.h @@ -48,6 +48,12 @@ * Pre-processor Definitions ****************************************************************************/ +/* The size of one interrupt stack. This is the configured value aligned + * the 8-bytes as required by the ARM EABI. + */ + +#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~7) + /**************************************************************************** * Public Types ****************************************************************************/ @@ -67,14 +73,15 @@ extern "C" #define EXTERN extern #endif -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions Prototypes ****************************************************************************/ +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +EXTERN uintptr_t arm_intstack_base(void); +EXTERN uintptr_t arm_intstack_alloc(void); +#endif + #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/imx6/chip.h b/arch/arm/src/imx6/chip.h index 54a31a38fadb6..c994f8c784be9 100644 --- a/arch/arm/src/imx6/chip.h +++ b/arch/arm/src/imx6/chip.h @@ -61,23 +61,6 @@ #define CHIP_MPCORE_VBASE IMX_ARMMP_VSECTION -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __ASSEMBLY__ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .globl g_irqstack_top - .globl g_fiqstack_top -#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */ - -#endif /* __ASSEMBLY__ */ - /**************************************************************************** * Macro Definitions ****************************************************************************/ @@ -141,51 +124,4 @@ #endif /* __ASSEMBLY__ */ -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Name: arm_intstack_base - * - * Description: - * Return a pointer to the "base" the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -static inline uintptr_t arm_intstack_base(void) -{ - uintptr_t base = (uintptr_t)g_irqstack_alloc; -#if CONFIG_SMP_NCPUS > 1 - uint32_t cpu = up_cpu_index(); - - base += cpu * INTSTACK_SIZE; -#endif - - return base; -} -#endif - -/**************************************************************************** - * Name: arm_intstack_top - * - * Description: - * Return a pointer to the "top" the correct interrupt stack for the - * current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -static inline uintptr_t arm_intstack_top(void) -{ - return arm_intstack_base() + INTSTACK_SIZE; -} -#endif - -#endif /* !__ASSEMBLY__ */ - #endif /* __ARCH_ARM_SRC_IMX6_CHIP_H */ diff --git a/arch/arm/src/imx6/imx_irq.c b/arch/arm/src/imx6/imx_irq.c index 89a62ff99d295..1f7738f9a042d 100644 --- a/arch/arm/src/imx6/imx_irq.c +++ b/arch/arm/src/imx6/imx_irq.c @@ -88,15 +88,15 @@ uint64_t g_fiqstack_alloc[INTSTACK_ALLOC >> 3]; uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS] = { - (uintptr_t)g_irqstack_alloc + INTSTACK_SIZE, + (uintptr_t)g_irqstack_alloc + INTSTACK_SIZE - 8, #if CONFIG_SMP_NCPUS > 1 - (uintptr_t)g_irqstack_alloc + 2 * INTSTACK_SIZE, + (uintptr_t)g_irqstack_alloc + (2 * INTSTACK_SIZE) - 8, #endif #if CONFIG_SMP_NCPUS > 2 - (uintptr_t)g_irqstack_alloc + 3 * INTSTACK_SIZE, + (uintptr_t)g_irqstack_alloc + (3 * INTSTACK_SIZE) - 8, #endif #if CONFIG_SMP_NCPUS > 3 - (uintptr_t)g_irqstack_alloc + 4 * INTSTACK_SIZE + (uintptr_t)g_irqstack_alloc + (4 * INTSTACK_SIZE) - 8 #endif }; @@ -186,3 +186,35 @@ void up_irqinitialize(void) up_irq_enable(); #endif } + +/**************************************************************************** + * Name: arm_intstack_base + * + * Description: + * Return a pointer to the "base" the correct interrupt stack allocation + * for the current CPU. NOTE: Here, the base means "top" of the stack + * + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +uintptr_t arm_intstack_base(void) +{ + return g_irqstack_top[up_cpu_index()]; +} +#endif + +/**************************************************************************** + * Name: arm_intstack_alloc + * + * Description: + * Return a pointer to the "alloc" the correct interrupt stack allocation + * for the current CPU. + * + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +uintptr_t arm_intstack_alloc(void) +{ + return g_irqstack_top[up_cpu_index()] - (INTSTACK_SIZE - 8); +} +#endif diff --git a/arch/arm/src/imx6/imx_irq.h b/arch/arm/src/imx6/imx_irq.h index 4751ced0fdfa7..fec7845b074cb 100644 --- a/arch/arm/src/imx6/imx_irq.h +++ b/arch/arm/src/imx6/imx_irq.h @@ -67,25 +67,15 @@ extern "C" #define EXTERN extern #endif -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -/* In the SMP configuration, we will need custom IRQ and FIQ stacks. - * These definitions provide the aligned stack allocations. - */ - -EXTERN uint64_t g_irqstack_alloc[]; -EXTERN uint64_t g_fiqstack_alloc[]; - -/* These are arrays that point to the top of each interrupt stack */ - -EXTERN uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS]; -EXTERN uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS]; - -#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */ - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +EXTERN uintptr_t arm_intstack_base(void); +EXTERN uintptr_t arm_intstack_alloc(void); +#endif + #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/lc823450/chip.h b/arch/arm/src/lc823450/chip.h index af32ff05d0daa..61a8ddcce0453 100644 --- a/arch/arm/src/lc823450/chip.h +++ b/arch/arm/src/lc823450/chip.h @@ -55,18 +55,6 @@ * Public Types ****************************************************************************/ -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __ASSEMBLY__ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .globl g_instack_alloc -#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */ - -#endif /* __ASSEMBLY__ */ - /**************************************************************************** * Macro Definitions ****************************************************************************/ @@ -84,77 +72,12 @@ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 .macro setintstack, tmp1, tmp2 -#if CONFIG_SMP_NCPUS > 1 - ldr \tmp1, =CORE_COREID - ldr \tmp1, [\tmp1, 0] /* \tmp = getreg32(coreid_reg) */ - and \tmp1, \tmp1, 1 /* \tmp = COREID */ - cmp \tmp1, #0 - bne 1f - ldr \tmp1, =g_cpu0_instack_base - ldr sp, [\tmp1, 0] /* sp = getreg32(g_cpu0_instack_base) */ - b 2f -1: - ldr \tmp1, =g_cpu1_instack_base - ldr sp, [\tmp1, 0] /* sp = getreg32(g_cpu1_instack_base) */ -2: -#else - ldr \tmp1, =g_cpu0_instack_base - ldr sp, [\tmp1, 0] /* sp = getreg32(g_cpu0_instack_base) */ -#endif + ldr \tmp1, =CORE_COREID + ldr \tmp1, [\tmp1, 0] /* tmp1 = getreg32(CORE_COREID) */ + ldr \tmp2, =g_cpu_intstack_top + ldr sp, [\tmp2, \tmp1, lsl #2] /* sp = g_cpu_intstack_top[tmp1] */ .endm #endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */ #endif /* __ASSEMBLY__ */ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: arm_intstack_base - * - * Description: - * Set the current stack pointer to the "base" the correct interrupt stack - * allocation for the current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -static inline uintptr_t arm_intstack_base(void) -{ - uintptr_t base = (uintptr_t)g_instack_alloc; -#if CONFIG_SMP_NCPUS > 1 - uint32_t coreid = getreg32(CORE_COREID); - - if ((coreid & CORE_COREID_ID) != 0) - { - base += INTSTACK_SIZE; - } -#endif - - return base; -} -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#if defined(__cplusplus) -} -#endif -#undef EXTERN - -#endif /* !__ASSEMBLY__ */ - #endif /* _ARCH_ARM_SRC_LC823450_CHIP_H */ diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c index ed59700a2dece..4e0beaa0715b1 100644 --- a/arch/arm/src/lc823450/lc823450_irq.c +++ b/arch/arm/src/lc823450/lc823450_irq.c @@ -89,17 +89,17 @@ volatile uint32_t *g_current_regs[1]; * These definitions provide the aligned stack allocations. */ -uint64_t g_instack_alloc[INTSTACK_ALLOC >> 3]; +uint64_t g_intstack_alloc[INTSTACK_ALLOC >> 3]; /* These definitions provide the "top" of the push-down stacks. */ -const uint32_t g_cpu0_instack_base = - (uint32_t)g_instack_alloc + INTSTACK_SIZE; - +const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] = +{ + (uint32_t)g_intstack_alloc + INTSTACK_SIZE - 8, #if CONFIG_SMP_NCPUS > 1 -const uint32_t g_cpu1_instack_base = - (uint32_t)g_instack_alloc + 2 * INTSTACK_SIZE; -#endif + (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE) - 8, +#endif /* CONFIG_SMP_NCPUS > 1 */ +}; #endif /**************************************************************************** @@ -470,16 +470,6 @@ void up_irqinitialize(void) putreg32(0xffffffff, NVIC_IRQ0_31_CLEAR); putreg32(0xffffffff, NVIC_IRQ32_63_CLEAR); - /* Colorize the interrupt stack for debug purposes */ - -#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 - { - size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); - arm_stack_color((FAR void *)((uintptr_t)&g_intstackbase - - intstack_size), intstack_size); - } -#endif - /* The standard location for the vector table is at the beginning of FLASH * at address 0x0800:0000. If we are using the STMicro DFU bootloader, * then the vector table will be offset to a different location in FLASH @@ -869,3 +859,35 @@ int lc823450_irq_register(int irq, struct lc823450_irq_ops *ops) return OK; } #endif /* CONFIG_LC823450_VIRQ */ + +/**************************************************************************** + * Name: arm_intstack_base + * + * Description: + * Return a pointer to the "base" the correct interrupt stack allocation + * for the current CPU. NOTE: Here, the base means "top" of the stack + * + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +uintptr_t arm_intstack_base(void) +{ + return g_cpu_intstack_top[up_cpu_index()]; +} +#endif + +/**************************************************************************** + * Name: arm_intstack_alloc + * + * Description: + * Return a pointer to the "alloc" the correct interrupt stack allocation + * for the current CPU. + * + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +uintptr_t arm_intstack_alloc(void) +{ + return g_cpu_intstack_top[up_cpu_index()] - (INTSTACK_SIZE - 8); +} +#endif diff --git a/arch/arm/src/lc823450/lc823450_irq.h b/arch/arm/src/lc823450/lc823450_irq.h index caea743c19d38..89d965146a04b 100644 --- a/arch/arm/src/lc823450/lc823450_irq.h +++ b/arch/arm/src/lc823450/lc823450_irq.h @@ -67,26 +67,15 @@ extern "C" #define EXTERN extern #endif -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -/* In the SMP configuration, we will need two custom interrupt stacks. - * These definitions provide the aligned stack allocations. - */ - -EXTERN uint64_t g_instack_alloc[]; - -/* These definitions provide the "top" of the push-down stacks. */ - -EXTERN const uint32_t g_cpu0_instack_base; -#if CONFIG_SMP_NCPUS > 1 -EXTERN const uint32_t g_cpu1_instack_base; -#endif - -#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */ - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +EXTERN uintptr_t arm_intstack_base(void); +EXTERN uintptr_t arm_intstack_alloc(void); +#endif + #undef EXTERN #if defined(__cplusplus) } From 78cefc647b748fdcdf737c72d5bac2370ce7ad3b Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Tue, 20 Oct 2020 11:47:16 +0900 Subject: [PATCH 05/19] boards: lc823450-xgevk: Update rndis/defconfig Summary: - Add CONFIG_ARCH_STACKDUMP=y - Add CONFIG_STACK_COLORATION=y - Remove CONFIG_NSH_DISABLE_MB=y - Remove CONFIG_NSH_DISABLE_MH=y Impact: - Affects lc823450-xgevk:rndis only Testing: - Tested with smp, ostest. Signed-off-by: Masayuki Ishikawa --- boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig b/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig index 724723b31084b..f7695b3072ec0 100644 --- a/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig +++ b/boards/arm/lc823450/lc823450-xgevk/configs/rndis/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_LC823450_XGEVK=y CONFIG_ARCH_CHIP="lc823450" CONFIG_ARCH_CHIP_LC823450=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STDARG_H=y CONFIG_AUDIO=y CONFIG_AUDIO_BUFFER_NUMBYTES=1024 @@ -116,8 +117,6 @@ CONFIG_NSH_DISABLE_DIRNAME=y CONFIG_NSH_DISABLE_EXEC=y CONFIG_NSH_DISABLE_GET=y CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_MB=y -CONFIG_NSH_DISABLE_MH=y CONFIG_NSH_DISABLE_MKFIFO=y CONFIG_NSH_DISABLE_MKRD=y CONFIG_NSH_DISABLE_PUT=y @@ -167,6 +166,7 @@ CONFIG_SMP=y CONFIG_SMP_NCPUS=2 CONFIG_SPI=y CONFIG_SPINLOCK_IRQ=y +CONFIG_STACK_COLORATION=y CONFIG_START_DAY=3 CONFIG_START_MONTH=10 CONFIG_START_YEAR=2013 From 81880a6552f8d18c3bb86b6991ec1e78269391f6 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Tue, 20 Oct 2020 11:52:31 +0900 Subject: [PATCH 06/19] boards: sabre-6quad: Update smp/defconfig Summary: - Remove CONFIG_HOST_WINDOWS=y - Add CONFIG_READLINE_CMD_HISTORY=y - Add CONFIG_STACK_COLORATION=y Impact: - Affects sabre-6quad:smp only Testing: - Tested with smp, ostest with QEMU Signed-off-by: Masayuki Ishikawa --- boards/arm/imx6/sabre-6quad/configs/smp/defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/boards/arm/imx6/sabre-6quad/configs/smp/defconfig b/boards/arm/imx6/sabre-6quad/configs/smp/defconfig index a308f022ebfa9..1177c272fcce1 100644 --- a/boards/arm/imx6/sabre-6quad/configs/smp/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/smp/defconfig @@ -28,7 +28,6 @@ CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y CONFIG_IMX6_UART1=y CONFIG_IMX_DDR_SIZE=1073741824 CONFIG_INTELHEX_BINARY=y @@ -45,12 +44,14 @@ CONFIG_RAM_SIZE=1073741824 CONFIG_RAM_START=0x10000000 CONFIG_RAM_VSTART=0x10000000 CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORKPRIORITY=192 CONFIG_SCHED_INSTRUMENTATION=y CONFIG_SMP=y CONFIG_SPINLOCK_IRQ=y +CONFIG_STACK_COLORATION=y CONFIG_START_MONTH=3 CONFIG_START_YEAR=2016 CONFIG_SYMTAB_ORDEREDBYNAME=y From 7cb3593fcee985bef65698f469f837726b8e75bf Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 22 Oct 2020 09:43:43 +0900 Subject: [PATCH 07/19] arch: armv7-a: Fix style warnings in smp.h Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/smp.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/armv7-a/smp.h b/arch/arm/src/armv7-a/smp.h index 7f3e37539b61f..a94170c7646e1 100644 --- a/arch/arm/src/armv7-a/smp.h +++ b/arch/arm/src/armv7-a/smp.h @@ -122,9 +122,9 @@ void __cpu3_start(void); * * Description: * Continues the C-level initialization started by the assembly language - * __cpu[n]_start function. At a minimum, this function needs to initialize - * interrupt handling and, perhaps, wait on WFI for arm_cpu_start() to - * issue an SGI. + * __cpu[n]_start function. At a minimum, this function needs to + * initialize interrupt handling and, perhaps, wait on WFI for + * arm_cpu_start() to issue an SGI. * * This function must be provided by the each ARMv7-A MCU and implement * MCU-specific initialization logic. From 76637611829734886e95a3e5707ef08b5f4b7397 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Fri, 23 Oct 2020 14:18:43 +0900 Subject: [PATCH 08/19] arch: armv7-a: Fix style warnings in arm_cpuidlestack.c Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/arm_cpuidlestack.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/src/armv7-a/arm_cpuidlestack.c b/arch/arm/src/armv7-a/arm_cpuidlestack.c index d389622d63ca3..7059e806eb997 100644 --- a/arch/arm/src/armv7-a/arm_cpuidlestack.c +++ b/arch/arm/src/armv7-a/arm_cpuidlestack.c @@ -133,7 +133,6 @@ int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size) /* Get the top of the stack */ - stack_alloc = (uintptr_t)g_cpu_stackalloc[cpu]; DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc)); top_of_stack = stack_alloc + SMP_STACK_TOP; From 56cccf5ea209cbb26086f097c1e7daf7e6f6fa6b Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 22 Oct 2020 09:46:07 +0900 Subject: [PATCH 09/19] arch: armv7-a: Fix CPUx IDLE stack top for SMP Summary: - This commit fixes CPUx IDLE stack top for SMP - Also removes SMP_STACK_TOP from smp.h Impact: - Affects armv7-a SMP only Testing: - Tested with sabre-6quad:smp (QEMU) Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/arm_cpuidlestack.c | 2 +- arch/arm/src/armv7-a/smp.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpuidlestack.c b/arch/arm/src/armv7-a/arm_cpuidlestack.c index 7059e806eb997..1acdeae7177ca 100644 --- a/arch/arm/src/armv7-a/arm_cpuidlestack.c +++ b/arch/arm/src/armv7-a/arm_cpuidlestack.c @@ -135,7 +135,7 @@ int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size) stack_alloc = (uintptr_t)g_cpu_stackalloc[cpu]; DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc)); - top_of_stack = stack_alloc + SMP_STACK_TOP; + top_of_stack = stack_alloc + SMP_STACK_SIZE; tcb->adj_stack_size = SMP_STACK_SIZE; tcb->stack_alloc_ptr = (FAR uint32_t *)stack_alloc; diff --git a/arch/arm/src/armv7-a/smp.h b/arch/arm/src/armv7-a/smp.h index a94170c7646e1..e168ce680556d 100644 --- a/arch/arm/src/armv7-a/smp.h +++ b/arch/arm/src/armv7-a/smp.h @@ -58,7 +58,6 @@ #define SMP_STACK_MASK 7 #define SMP_STACK_SIZE ((CONFIG_SMP_IDLETHREAD_STACKSIZE + 7) & ~7) #define SMP_STACK_WORDS (SMP_STACK_SIZE >> 2) -#define SMP_STACK_TOP (SMP_STACK_SIZE - 8) /**************************************************************************** * Public Data From 481dfc6e6258cb3483b86e6e9a534f172d5c170b Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 22 Oct 2020 12:49:25 +0900 Subject: [PATCH 10/19] boards: sabre-6quad: Update nsh/defconfig Summary: - Add CONFIG_DEBUG_FULLOPT=y - Add CONFIG_DEBUG_SYMBOLS=y - Remove CONFIG_HOST_WINDOWS=y - Add CONFIG_READLINE_CMD_HISTORY=y - Add CONFIG_STACK_COLORATION=y Impact: - Affects sabre-6quad:nsh only Testing: - Tested with QEMU Signed-off-by: Masayuki Ishikawa --- boards/arm/imx6/sabre-6quad/configs/nsh/defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig b/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig index c42ae64c05b59..30aa9a25a8b34 100644 --- a/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig @@ -20,11 +20,12 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=99369 CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_ZERO=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y CONFIG_IMX6_UART1=y CONFIG_IMX_DDR_SIZE=1073741824 CONFIG_INTELHEX_BINARY=y @@ -42,10 +43,12 @@ CONFIG_RAM_SIZE=1073741824 CONFIG_RAM_START=0x10000000 CONFIG_RAM_VSTART=0x10000000 CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORKPRIORITY=192 CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y CONFIG_START_MONTH=3 CONFIG_START_YEAR=2016 CONFIG_SYMTAB_ORDEREDBYNAME=y From 07e6a6a29de8a8e6c183afc7589b253cca905bba Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 22 Oct 2020 10:06:05 +0900 Subject: [PATCH 11/19] armv7-a, imx6: Refactor interrupt stack related code Summary: - Remove -4/-8 offset coding in imx_irq.c and arm_vectors.S - Instead, add SP adjustment after calling setirqstack/setfiqstack - Fix off-by-one irq/fiq stack allocation in 8-byte aligned arch - Fix comments on the user stack pointer in arm_vectors.S - Also, fix up_dumpstate() to extract the user stack pointer - NOTE: stack pointer alignment is 8-byte Impact: - Affects armv7-a with interrupt stack enabled Testing: - Tested with sabre-6quad:smp with QEMU - Tested with sabre-6quad:nsh with QEMU Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/arm_assert.c | 25 +++++++++++-------------- arch/arm/src/armv7-a/arm_vectors.S | 10 +++++----- arch/arm/src/imx6/imx_irq.c | 10 +++++----- 3 files changed, 21 insertions(+), 24 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c index 07a2decbf7f97..f04eaa001243e 100644 --- a/arch/arm/src/armv7-a/arm_assert.c +++ b/arch/arm/src/armv7-a/arm_assert.c @@ -265,24 +265,10 @@ static void up_dumpstate(void) if (sp > istackbase - istacksize && sp < istackbase) { - uint32_t *stackbase; - /* Yes.. dump the interrupt stack */ _alert("Interrupt Stack\n", sp); up_stackdump(sp, istackbase); - - /* Extract the user stack pointer which should lie - * at the base of the interrupt stack. - */ - -#ifdef CONFIG_SMP - stackbase = (uint32_t *)arm_intstack_base(); -#else - stackbase = (uint32_t *)&g_intstackbase; -#endif - sp = *stackbase; - _alert("User sp: %08x\n", sp); } else if (CURRENT_REGS) { @@ -291,6 +277,17 @@ static void up_dumpstate(void) } #endif + /* Extract the user stack pointer if we are in an interrupt handler. + * If we are not in an interrupt handler. Then sp is the user stack + * pointer (and the above range check should have failed). + */ + + if (CURRENT_REGS) + { + sp = CURRENT_REGS[REG_R13]; + _alert("User sp: %08x\n", sp); + } + /* Dump the user stack if the stack pointer lies within the allocated user * stack memory. */ diff --git a/arch/arm/src/armv7-a/arm_vectors.S b/arch/arm/src/armv7-a/arm_vectors.S index 6df8755c4c946..e0559048164dc 100644 --- a/arch/arm/src/armv7-a/arm_vectors.S +++ b/arch/arm/src/armv7-a/arm_vectors.S @@ -261,7 +261,7 @@ arm_vectorirq: /* Call arm_decodeirq() on the interrupt stack */ setirqstack r1, r3 /* SP = IRQ stack top */ - str r0, [sp] /* Save the user stack pointer */ + str r0, [sp, #-4]! /* Save the xcp address at SP-4 then update SP */ mov r4, sp /* Save the SP in a preserved register */ bic sp, sp, #7 /* Force 8-byte alignment */ bl arm_decodeirq /* Call the handler */ @@ -1004,7 +1004,7 @@ arm_vectorfiq: #if CONFIG_ARCH_INTERRUPTSTACK > 7 setfiqstack r1, r4 /* SP = FIQ stack top */ - str r0, [sp] /* Save the user stack pointer */ + str r0, [sp, #-4]! /* Save the xcp address at SP-4 then update SP */ mov r4, sp /* Save the SP in a preserved register */ bic sp, sp, #7 /* Force 8-byte alignment */ bl arm_decodefiq /* Call the handler */ @@ -1072,7 +1072,7 @@ arm_vectorfiq: #if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 .bss - .align 4 + .balign 8 .globl g_intstackalloc .type g_intstackalloc, object @@ -1080,7 +1080,7 @@ arm_vectorfiq: .type g_intstackbase, object g_intstackalloc: - .skip ((CONFIG_ARCH_INTERRUPTSTACK & ~7) - 4) + .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7) g_intstackbase: .skip 4 .size g_intstackbase, 4 @@ -1096,7 +1096,7 @@ g_intstackbase: .type g_fiqstackbase, object g_fiqstackalloc: - .skip ((CONFIG_ARCH_INTERRUPTSTACK & ~7) - 4) + .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7) g_fiqstackbase: .skip 4 .size g_fiqstackbase, 4 diff --git a/arch/arm/src/imx6/imx_irq.c b/arch/arm/src/imx6/imx_irq.c index 1f7738f9a042d..7d3b76033e576 100644 --- a/arch/arm/src/imx6/imx_irq.c +++ b/arch/arm/src/imx6/imx_irq.c @@ -88,15 +88,15 @@ uint64_t g_fiqstack_alloc[INTSTACK_ALLOC >> 3]; uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS] = { - (uintptr_t)g_irqstack_alloc + INTSTACK_SIZE - 8, + (uintptr_t)g_irqstack_alloc + INTSTACK_SIZE, #if CONFIG_SMP_NCPUS > 1 - (uintptr_t)g_irqstack_alloc + (2 * INTSTACK_SIZE) - 8, + (uintptr_t)g_irqstack_alloc + (2 * INTSTACK_SIZE), #endif #if CONFIG_SMP_NCPUS > 2 - (uintptr_t)g_irqstack_alloc + (3 * INTSTACK_SIZE) - 8, + (uintptr_t)g_irqstack_alloc + (3 * INTSTACK_SIZE), #endif #if CONFIG_SMP_NCPUS > 3 - (uintptr_t)g_irqstack_alloc + (4 * INTSTACK_SIZE) - 8 + (uintptr_t)g_irqstack_alloc + (4 * INTSTACK_SIZE) #endif }; @@ -215,6 +215,6 @@ uintptr_t arm_intstack_base(void) #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 uintptr_t arm_intstack_alloc(void) { - return g_irqstack_top[up_cpu_index()] - (INTSTACK_SIZE - 8); + return g_irqstack_top[up_cpu_index()] - INTSTACK_SIZE; } #endif From 887b6e7965e4144d46c4e78bf9787dda1869fb50 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 22 Oct 2020 11:57:14 +0900 Subject: [PATCH 12/19] arm, c5471: Refactor interrupt stack related code Summary: - Apply the same logic for armv7-a - NOTE: stack pointer alignment is 4-byte Impact: - Affects arm (arm7/9) and c5471 with interrupt stack enabled Testing: - Built with c5471evm.nsh (CONFIG_ARCH_INTERRUPTSTACK=2048) - Built with ea3131:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048) - Not tested but should work Signed-off-by: Masayuki Ishikawa --- arch/arm/src/arm/arm_assert.c | 21 +++++++++++++-------- arch/arm/src/arm/arm_vectors.S | 6 +++--- arch/arm/src/c5471/c5471_vectors.S | 6 +++--- 3 files changed, 19 insertions(+), 14 deletions(-) diff --git a/arch/arm/src/arm/arm_assert.c b/arch/arm/src/arm/arm_assert.c index e4f445bb8069e..4957af560b9eb 100644 --- a/arch/arm/src/arm/arm_assert.c +++ b/arch/arm/src/arm/arm_assert.c @@ -210,18 +210,12 @@ static void up_dumpstate(void) * stack? */ - if (sp <= istackbase && sp > istackbase - istacksize) + if (sp < istackbase && sp > istackbase - istacksize) { /* Yes.. dump the interrupt stack */ + _alert("Interrupt Stack\n", sp); up_stackdump(sp, istackbase); - - /* Extract the user stack pointer which should lie - * at the base of the interrupt stack. - */ - - sp = g_intstackbase; - _alert("sp: %08x\n", sp); } else if (CURRENT_REGS) { @@ -229,6 +223,17 @@ static void up_dumpstate(void) up_stackdump(istackbase - istacksize, istackbase); } + /* Extract the user stack pointer if we are in an interrupt handler. + * If we are not in an interrupt handler. Then sp is the user stack + * pointer (and the above range check should have failed). + */ + + if (CURRENT_REGS) + { + sp = CURRENT_REGS[REG_R13]; + _alert("User sp: %08x\n", sp); + } + /* Show user stack info */ _alert("User stack:\n"); diff --git a/arch/arm/src/arm/arm_vectors.S b/arch/arm/src/arm/arm_vectors.S index c03f091edad5e..9606131192af4 100644 --- a/arch/arm/src/arm/arm_vectors.S +++ b/arch/arm/src/arm/arm_vectors.S @@ -132,7 +132,7 @@ arm_vectorirq: #if CONFIG_ARCH_INTERRUPTSTACK > 3 ldr sp, .Lirqstackbase /* SP = interrupt stack base */ - str r0, [sp] /* Save the user stack pointer */ + str r0, [sp, #-4]! /* Save the xcp address at SP-4 then update SP */ bl arm_decodeirq /* Call the handler */ ldr sp, [sp] /* Restore the user stack pointer */ #else @@ -432,13 +432,13 @@ arm_vectorfiq: #if CONFIG_ARCH_INTERRUPTSTACK > 3 .bss - .align 4 + .balign 4 .globl g_intstackalloc .type g_intstackalloc, object .globl g_intstackbase .type g_intstackbase, object g_intstackalloc: - .skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4) + .skip (CONFIG_ARCH_INTERRUPTSTACK & ~3) g_intstackbase: .skip 4 .size g_intstackbase, 4 diff --git a/arch/arm/src/c5471/c5471_vectors.S b/arch/arm/src/c5471/c5471_vectors.S index 95f4357a771a7..813e0534edc4a 100644 --- a/arch/arm/src/c5471/c5471_vectors.S +++ b/arch/arm/src/c5471/c5471_vectors.S @@ -162,7 +162,7 @@ arm_vectorirq: #if CONFIG_ARCH_INTERRUPTSTACK > 3 ldr sp, .Lirqstackbase /* SP = interrupt stack base */ - str r1, [sp] /* Save the user stack pointer */ + str r1, [sp, #-4]! /* Save the xcp address at SP-4 then update SP */ bl arm_doirq /* Call the handler */ ldr sp, [sp] /* Restore the user stack pointer */ #else @@ -471,13 +471,13 @@ arm_vectoraddrexcptn: #if CONFIG_ARCH_INTERRUPTSTACK > 3 .bss - .align 4 + .balign 4 .global g_intstackalloc .global g_intstackbase .type g_intstackalloc, object .type g_intstackbase, object g_intstackalloc: - .skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4) + .skip (CONFIG_ARCH_INTERRUPTSTACK & ~3) g_intstackbase: .skip 4 .size g_intstackbase, 4 From a72873a76a32bc2b916c626431180104b968e4f9 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 22 Oct 2020 11:13:38 +0900 Subject: [PATCH 13/19] arch: armv7-r: Refactor interrupt stack related code Summary: - Apply the same logic for armv7-a - NOTE: stack pointer alignment is 8-byte Impact: - Affects armv7-r with interrupt stack enabled Testing: - Not tested but should work Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-r/arm_assert.c | 26 +++++++++++++++----------- arch/arm/src/armv7-r/arm_vectors.S | 22 +++++++++++----------- 2 files changed, 26 insertions(+), 22 deletions(-) diff --git a/arch/arm/src/armv7-r/arm_assert.c b/arch/arm/src/armv7-r/arm_assert.c index c91e2ca1d33bc..ed516c750bee1 100644 --- a/arch/arm/src/armv7-r/arm_assert.c +++ b/arch/arm/src/armv7-r/arm_assert.c @@ -195,7 +195,7 @@ static void up_dumpstate(void) uint32_t sp = arm_getsp(); uint32_t ustackbase; uint32_t ustacksize; -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 7 uint32_t istackbase; uint32_t istacksize; #endif @@ -214,11 +214,11 @@ static void up_dumpstate(void) _alert("Current sp: %08x\n", sp); -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 7 /* Get the limits on the interrupt stack memory */ istackbase = (uint32_t)&g_intstackbase; - istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~7); /* Show interrupt stack info */ @@ -253,7 +253,7 @@ static void up_dumpstate(void) } #endif -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 7 /* Does the current stack pointer lie within the interrupt stack? */ if (sp > istackbase - istacksize && sp < istackbase) @@ -262,13 +262,6 @@ static void up_dumpstate(void) _alert("Interrupt Stack\n", sp); up_stackdump(sp, istackbase); - - /* Extract the user stack pointer which should lie - * at the base of the interrupt stack. - */ - - sp = g_intstackbase; - _alert("User sp: %08x\n", sp); } else if (CURRENT_REGS) { @@ -277,6 +270,17 @@ static void up_dumpstate(void) } #endif + /* Extract the user stack pointer if we are in an interrupt handler. + * If we are not in an interrupt handler. Then sp is the user stack + * pointer (and the above range check should have failed). + */ + + if (CURRENT_REGS) + { + sp = CURRENT_REGS[REG_R13]; + _alert("User sp: %08x\n", sp); + } + /* Dump the user stack if the stack pointer lies within the allocated user * stack memory. */ diff --git a/arch/arm/src/armv7-r/arm_vectors.S b/arch/arm/src/armv7-r/arm_vectors.S index bea7c927bcebf..f3064ad219987 100644 --- a/arch/arm/src/armv7-r/arm_vectors.S +++ b/arch/arm/src/armv7-r/arm_vectors.S @@ -179,9 +179,9 @@ arm_vectorirq: mov fp, #0 /* Init frame pointer */ mov r0, sp /* Get r0=xcp */ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 7 ldr sp, .Lirqstackbase /* SP = interrupt stack base */ - str r0, [sp] /* Save the user stack pointer */ + str r0, [sp, #-4]! /* Save the xcp address at SP-4 then update SP */ mov r4, sp /* Save the SP in a preserved register */ bic sp, sp, #7 /* Force 8-byte alignment */ bl arm_decodeirq /* Call the handler */ @@ -232,7 +232,7 @@ arm_vectorirq: .Lirqtmp: .word g_irqtmp -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 7 .Lirqstackbase: .word g_intstackbase #endif @@ -890,9 +890,9 @@ arm_vectorfiq: mov fp, #0 /* Init frame pointer */ mov r0, sp /* Get r0=xcp */ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 7 ldr sp, .Lfiqstackbase /* SP = interrupt stack base */ - str r0, [sp] /* Save the user stack pointer */ + str r0, [sp, #-4]! /* Save the xcp address at SP-4 then update SP */ mov r4, sp /* Save the SP in a preserved register */ bic sp, sp, #7 /* Force 8-byte alignment */ bl arm_decodefiq /* Call the handler */ @@ -943,7 +943,7 @@ arm_vectorfiq: .Lfiqtmp: .word g_fiqtmp -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 7 .Lfiqstackbase: .word g_intstackbase #endif @@ -957,9 +957,9 @@ arm_vectorfiq: * Name: g_intstackalloc/g_intstackbase ************************************************************************************/ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#if CONFIG_ARCH_INTERRUPTSTACK > 7 .bss - .align 4 + .balign 8 .globl g_intstackalloc .type g_intstackalloc, object @@ -967,11 +967,11 @@ arm_vectorfiq: .type g_intstackbase, object g_intstackalloc: - .skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4) + .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7) g_intstackbase: .skip 4 .size g_intstackbase, 4 - .size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3) + .size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~7) -#endif /* CONFIG_ARCH_INTERRUPTSTACK > 3 */ +#endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 */ .end From 617e765030ebd955ad816f2f42764935a37a7da5 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 22 Oct 2020 14:50:50 +0900 Subject: [PATCH 14/19] boards: stm32f4discovery: Update wifi/defconfig Summary: - Add CONFIG_ARCH_INTERRUPTSTACK=2048 - Add CONFIG_ARMV7M_LAZYFPU=y - Add CONFIG_TESTING_OSTEST_FPUSIZE=132 Impact: - Affects stm32f4discovery:wifi only Testing: - Tested with ostest, uSD card, Wi-Fi Signed-off-by: Masayuki Ishikawa --- boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig index 54912f275dc5f..9f48660c75bb2 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig @@ -5,7 +5,6 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # -# CONFIG_ARCH_FPU is not set # CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_HAVE_WRITEPROTECT is not set # CONFIG_NSH_ARGCAT is not set @@ -19,7 +18,9 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LAZYFPU=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y @@ -101,6 +102,7 @@ CONFIG_SYSTEM_NSH_SYMTAB_ARRAYNAME="g_symtab" CONFIG_SYSTEM_NSH_SYMTAB_COUNTNAME="g_nsymbols" CONFIG_SYSTEM_NTPC=y CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_FPUSIZE=132 CONFIG_USART2_RXBUFSIZE=128 CONFIG_USART2_SERIAL_CONSOLE=y CONFIG_USART2_TXBUFSIZE=128 From aef92e370cdbc7d9c1d000fdd1930e53df14a5f5 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 22 Oct 2020 14:06:31 +0900 Subject: [PATCH 15/19] armv7-m, cxd56xx, lc823450: Refactor interrupt stack related code Summary: - Remove +4/-8 offset coding - Also, fix alignments for g_intstackalloc - NOTE: stack pointer alignment is 8-byte Impact: - Affects armv7-m with interrupt stack enabled Testing: - Tested with spresense:wifi_smp - Tested with lc823450:smp - Tested with stm32f4discovery:wifi Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-m/arm_assert.c | 2 +- arch/arm/src/armv7-m/gnu/arm_exception.S | 6 +++--- arch/arm/src/armv7-m/gnu/arm_lazyexception.S | 6 +++--- arch/arm/src/cxd56xx/cxd56_irq.c | 14 +++++++------- arch/arm/src/lc823450/lc823450_irq.c | 6 +++--- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/src/armv7-m/arm_assert.c b/arch/arm/src/armv7-m/arm_assert.c index 382297f202bdb..c1a29cdd60b2e 100644 --- a/arch/arm/src/armv7-m/arm_assert.c +++ b/arch/arm/src/armv7-m/arm_assert.c @@ -244,7 +244,7 @@ static void up_dumpstate(void) * stack? */ - if (sp <= istackbase && sp > istackbase - istacksize) + if (sp < istackbase && sp > istackbase - istacksize) { /* Yes.. dump the interrupt stack */ diff --git a/arch/arm/src/armv7-m/gnu/arm_exception.S b/arch/arm/src/armv7-m/gnu/arm_exception.S index b9580eeec5732..34e5031264c39 100644 --- a/arch/arm/src/armv7-m/gnu/arm_exception.S +++ b/arch/arm/src/armv7-m/gnu/arm_exception.S @@ -67,7 +67,7 @@ * no privileged task has run. */ -# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4 +# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8 # error Interrupt stack must be used with high priority interrupts in kernel mode # endif @@ -197,7 +197,7 @@ exception_common: * here prohibits nested interrupts without some additional logic! */ - setintstack r2, r3 + setintstack r2, r3 /* SP = IRQ stack top */ #else /* Otherwise, we will re-use the interrupted thread's stack. That may @@ -321,7 +321,7 @@ exception_common: .bss .global g_intstackalloc .global g_intstackbase - .align 8 + .balign 8 g_intstackalloc: .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7) g_intstackbase: diff --git a/arch/arm/src/armv7-m/gnu/arm_lazyexception.S b/arch/arm/src/armv7-m/gnu/arm_lazyexception.S index 57ee25096ff8b..9d15f901eeb1a 100644 --- a/arch/arm/src/armv7-m/gnu/arm_lazyexception.S +++ b/arch/arm/src/armv7-m/gnu/arm_lazyexception.S @@ -50,7 +50,7 @@ * nested interrupt, the interrupt stack if no privileged task has run. */ -# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4 +# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8 # error Interrupt stack must be used with high priority interrupts in kernel mode # endif @@ -192,7 +192,7 @@ exception_common: * here prohibits nested interrupts without some additional logic! */ - setintstack r2, r3 + setintstack r2, r3 /* SP = IRQ stack top */ #else /* Otherwise, we will re-use the interrupted thread's stack. That may @@ -340,7 +340,7 @@ exception_common: .bss .global g_intstackalloc .global g_intstackbase - .align 8 + .balign 8 g_intstackalloc: .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7) g_intstackbase: diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c index f113dcef06f9e..d59872e61576e 100644 --- a/arch/arm/src/cxd56xx/cxd56_irq.c +++ b/arch/arm/src/cxd56xx/cxd56_irq.c @@ -112,17 +112,17 @@ static uint64_t g_intstack_alloc[INTSTACK_ALLOC >> 3]; const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] = { - (uint32_t)g_intstack_alloc + INTSTACK_SIZE - 8, + (uint32_t)g_intstack_alloc + INTSTACK_SIZE, #if CONFIG_SMP_NCPUS > 1 - (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE) - 8, + (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE), #if CONFIG_SMP_NCPUS > 2 - (uint32_t)g_intstack_alloc + (3 * INTSTACK_SIZE) - 8, + (uint32_t)g_intstack_alloc + (3 * INTSTACK_SIZE), #if CONFIG_SMP_NCPUS > 3 - (uint32_t)g_intstack_alloc + (4 * INTSTACK_SIZE) - 8, + (uint32_t)g_intstack_alloc + (4 * INTSTACK_SIZE), #if CONFIG_SMP_NCPUS > 4 - (uint32_t)g_intstack_alloc + (5 * INTSTACK_SIZE) - 8, + (uint32_t)g_intstack_alloc + (5 * INTSTACK_SIZE), #if CONFIG_SMP_NCPUS > 5 - (uint32_t)g_intstack_alloc + (6 * INTSTACK_SIZE) - 8, + (uint32_t)g_intstack_alloc + (6 * INTSTACK_SIZE), #endif /* CONFIG_SMP_NCPUS > 5 */ #endif /* CONFIG_SMP_NCPUS > 4 */ #endif /* CONFIG_SMP_NCPUS > 3 */ @@ -667,6 +667,6 @@ uintptr_t arm_intstack_base(void) #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 uintptr_t arm_intstack_alloc(void) { - return g_cpu_intstack_top[up_cpu_index()] - (INTSTACK_SIZE - 8); + return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE; } #endif diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c index 4e0beaa0715b1..4583ae95f5e80 100644 --- a/arch/arm/src/lc823450/lc823450_irq.c +++ b/arch/arm/src/lc823450/lc823450_irq.c @@ -95,9 +95,9 @@ uint64_t g_intstack_alloc[INTSTACK_ALLOC >> 3]; const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] = { - (uint32_t)g_intstack_alloc + INTSTACK_SIZE - 8, + (uint32_t)g_intstack_alloc + INTSTACK_SIZE, #if CONFIG_SMP_NCPUS > 1 - (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE) - 8, + (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE), #endif /* CONFIG_SMP_NCPUS > 1 */ }; #endif @@ -888,6 +888,6 @@ uintptr_t arm_intstack_base(void) #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 uintptr_t arm_intstack_alloc(void) { - return g_cpu_intstack_top[up_cpu_index()] - (INTSTACK_SIZE - 8); + return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE; } #endif From f9653cc3ceb73c239a7d4cb69cb552b8148ee6db Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 22 Oct 2020 15:20:39 +0900 Subject: [PATCH 16/19] arch: armv8-m: Refactor interrupt stack related code Summary: - Apply the same logic for armv7-m - NOTE: stack pointer alignment is 8-byte Impact: - Affects armv8-m with interrupt stack enabled Testing: - Not tested but should work Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv8-m/arm_assert.c | 2 +- arch/arm/src/armv8-m/arm_exception.S | 4 ++-- arch/arm/src/armv8-m/arm_lazyexception.S | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/armv8-m/arm_assert.c b/arch/arm/src/armv8-m/arm_assert.c index ac0b9b7215113..bc6cb3a1d9356 100644 --- a/arch/arm/src/armv8-m/arm_assert.c +++ b/arch/arm/src/armv8-m/arm_assert.c @@ -244,7 +244,7 @@ static void up_dumpstate(void) * stack? */ - if (sp <= istackbase && sp > istackbase - istacksize) + if (sp < istackbase && sp > istackbase - istacksize) { /* Yes.. dump the interrupt stack */ diff --git a/arch/arm/src/armv8-m/arm_exception.S b/arch/arm/src/armv8-m/arm_exception.S index c7dc5af6e097e..9a3c434e0a92d 100644 --- a/arch/arm/src/armv8-m/arm_exception.S +++ b/arch/arm/src/armv8-m/arm_exception.S @@ -67,7 +67,7 @@ * no privileged task has run. */ -# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4 +# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8 # error Interrupt stack must be used with high priority interrupts in kernel mode # endif @@ -355,7 +355,7 @@ exception_common: .bss .global g_intstackalloc .global g_intstackbase - .align 8 + .balign 8 g_intstackalloc: .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7) g_intstackbase: diff --git a/arch/arm/src/armv8-m/arm_lazyexception.S b/arch/arm/src/armv8-m/arm_lazyexception.S index ade51c1adbac1..fe89b3206331e 100644 --- a/arch/arm/src/armv8-m/arm_lazyexception.S +++ b/arch/arm/src/armv8-m/arm_lazyexception.S @@ -50,7 +50,7 @@ * nested interrupt, the interrupt stack if no privileged task has run. */ -# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4 +# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8 # error Interrupt stack must be used with high priority interrupts in kernel mode # endif @@ -373,7 +373,7 @@ exception_common: .bss .global g_intstackalloc .global g_intstackbase - .align 8 + .balign 8 g_intstackalloc: .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7) g_intstackbase: From 69f1ba0404df86ac92b18efb4db5a3916f739af5 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Thu, 22 Oct 2020 15:46:31 +0900 Subject: [PATCH 17/19] arch: armv6-m: Refactor interrupt stack related code Summary: - Apply the same logic for armv7-m - NOTE: stack pointer alignment is 4-byte Impact: - Affects armv6-m with interrupt stack enabled Testing: - Built with freedom-kl25z:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048) - Not tested but should work Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv6-m/arm_assert.c | 2 +- arch/arm/src/armv6-m/arm_exception.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/armv6-m/arm_assert.c b/arch/arm/src/armv6-m/arm_assert.c index 382a039a3943d..11c97ba1e72c4 100644 --- a/arch/arm/src/armv6-m/arm_assert.c +++ b/arch/arm/src/armv6-m/arm_assert.c @@ -247,7 +247,7 @@ static void up_dumpstate(void) * stack? */ - if (sp <= istackbase && sp > istackbase - istacksize) + if (sp < istackbase && sp > istackbase - istacksize) { /* Yes.. dump the interrupt stack */ diff --git a/arch/arm/src/armv6-m/arm_exception.S b/arch/arm/src/armv6-m/arm_exception.S index c70c57a2eb969..ecc6c04df29ea 100644 --- a/arch/arm/src/armv6-m/arm_exception.S +++ b/arch/arm/src/armv6-m/arm_exception.S @@ -270,7 +270,7 @@ exception_common: .bss .global g_intstackalloc .global g_intstackbase - .align 4 + .balign 4 g_intstackalloc: .skip (CONFIG_ARCH_INTERRUPTSTACK & ~3) g_intstackbase: From 36d14371275c1cc283f575163cb39033565cce55 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Fri, 23 Oct 2020 14:35:41 +0900 Subject: [PATCH 18/19] arm: armv7-a: Fix kernel stack dump in arm_assert.c Summary: - This commit fixes kernel stack dump information Impact: - Affects armv7-a with kernel build Testing: - Built with sama5d4-ek:knsh - Not tested Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/arm_assert.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c index f04eaa001243e..015aa83578267 100644 --- a/arch/arm/src/armv7-a/arm_assert.c +++ b/arch/arm/src/armv7-a/arm_assert.c @@ -252,7 +252,7 @@ static void up_dumpstate(void) if (rtcb->xcp.kstack) { kstackbase = (uint32_t)rtcb->xcp.kstack + - CONFIG_ARCH_KERNEL_STACKSIZE - 4; + CONFIG_ARCH_KERNEL_STACKSIZE; _alert("Kernel stack:\n"); _alert(" base: %08x\n", kstackbase); From 659890731fad45e8a3e1cbfafd43d332183c4ff1 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 2 Nov 2020 17:06:21 +0900 Subject: [PATCH 19/19] sched: irq: Fix enter_critical_section() in an irq handler for SMP Summary: - I found a deadlock during Wi-Fi audio streaming test plus stress test - The testing environment was spresense:wifi_smp (NCPUS=4) - The deadlock happened because two CPUs called up_cpu_pause() almost simultaneously - This situation should not happen, because up_cpu_pause() is called in a critical section - Actually, the latter call was from nxsem_post() in an IRQ handler - And when enter_critical_section() was called, irq_waitlock() detected a deadlock - Then it called up_cpu_paused() to break the deadlock - However, this resulted in setting g_cpu_irqset on the CPU - Even though another CPU had held a g_cpu_irqlock - This situation violates the critical section and should be avoided - To avoid the situation, if a CPU sets g_cpu_irqset after calling up_cpu_paused() - The CPU must release g_cpu_irqlock first - Then retry irq_waitlock() to acquire g_cpu_irqlock Impact: - Affect SMP Testing: - Tested with spresense:wifi_smp (NCPUS=2 and 4) - Tested with spresense:smp - Tested with sim:smp - Tested with sabre-6quad:smp (QEMU) - Tested with maix-bit:smp (QEMU) - Tested with esp32-core:smp (QEMU) - Tested with lc823450-xgevk:rndis Signed-off-by: Masayuki Ishikawa --- sched/irq/irq_csection.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 6993641fd2726..9eeb4b4c4aa0b 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -265,6 +265,7 @@ irqstate_t enter_critical_section(void) * no longer blocked by the critical section). */ +try_again_in_irq: if (!irq_waitlock(cpu)) { /* We are in a deadlock condition due to a pending @@ -273,6 +274,24 @@ irqstate_t enter_critical_section(void) */ DEBUGVERIFY(up_cpu_paused(cpu)); + + /* NOTE: As the result of up_cpu_paused(cpu), this CPU + * might set g_cpu_irqset in nxsched_resume_scheduler() + * However, another CPU might hold g_cpu_irqlock. + * To avoid this situation, releae g_cpu_irqlock first. + */ + + if ((g_cpu_irqset & (1 << cpu)) != 0) + { + spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, + &g_cpu_irqlock); + } + + /* NOTE: Here, this CPU does not hold g_cpu_irqlock, + * so call irq_waitlock(cpu) to acquire g_cpu_irqlock. + */ + + goto try_again_in_irq; } }