From a07c614fb6e52946b34983ea402d3da0391e762d Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 16 Nov 2020 13:31:36 +0900 Subject: [PATCH 01/10] arch: armv7-a: Fix style warnings in arm_l2cc_pl310.c Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/arm_l2cc_pl310.c | 37 +++++++++++++++++---------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c index 3726cc881e2ae..1239556d8bfb9 100644 --- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-a/chip/arm-l2cc_pl310.c * * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. @@ -36,7 +36,7 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Included Files @@ -59,7 +59,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration ***********************************************************/ + +/* Configuration ************************************************************/ + /* Number of ways depends on ARM configuration */ #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) @@ -315,18 +317,19 @@ void arm_l2ccinitialize(void) /* Make sure that this is a PL310 cache, version r3p2. * - * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which is - * r3p2, but the chip that I have actually* reports 0x410000C9 which is some - * later revision. + * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which + * is r3p2, but the chip that I have actually* reports 0x410000C9 which + * is some later revision. */ - //DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2); + /* DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == + * L2CC_IDR_REV_R3P2); + */ /* Make sure that actual cache configuration agrees with the configured * cache configuration. */ - #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0); #elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY) @@ -336,17 +339,23 @@ void arm_l2ccinitialize(void) #endif #if defined(CONFIG_ARMV7A_WAYSIZE_16KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_16KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_16KB); #elif defined(CONFIG_ARMV7A_WAYSIZE_32KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_32KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_32KB); #elif defined(CONFIG_ARMV7A_WAYSIZE_64KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_64KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_64KB); #elif defined(CONFIG_ARMV7A_WAYSIZE_128KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_128KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_128KB); #elif defined(CONFIG_ARMV7A_WAYSIZE_256KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_256KB); #elif defined(CONFIG_ARMV7A_WAYSIZE_512KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_512KB); #else # error No way size selected #endif From 327414ceed1fc6b16d1233d35b6172e30dadf0ee Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 16 Nov 2020 13:49:15 +0900 Subject: [PATCH 02/10] arch: armv7-a: Fix style warnings in l2cc_pl310.h Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/l2cc_pl310.h | 256 +++++++++++++++--------------- 1 file changed, 129 insertions(+), 127 deletions(-) diff --git a/arch/arm/src/armv7-a/l2cc_pl310.h b/arch/arm/src/armv7-a/l2cc_pl310.h index 16d8f723cb4b9..b42c864099bce 100644 --- a/arch/arm/src/armv7-a/l2cc_pl310.h +++ b/arch/arm/src/armv7-a/l2cc_pl310.h @@ -57,6 +57,7 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ + /* General Definitions **************************************************************/ #define PL310_CACHE_LINE_SIZE 32 @@ -110,7 +111,7 @@ #define L2CC_DLKR_OFFSET(n) (0x0900 + ((n) << 3)) /* Data Lockdown Register */ #define L2CC_ILKR_OFFSET(n) (0x0904 + ((n) << 3)) /* Instruction Lockdown Register */ - /* 0x0940-0x0f4c Reserved */ + /* 0x0940-0x0f4c Reserved */ #ifdef CONFIG_PL310_LOCKDOWN_BY_LINE # define L2CC_LKLN_OFFSET 0x0950 /* Lock Line Enable Register */ # define L2CC_UNLKW_OFFSET 0x0954 /* Unlock Way Register */ @@ -170,23 +171,23 @@ /* Cache ID Register (32-bit ID) */ #define L2CC_IDR_REV_MASK 0x0000003f -# define L2CC_IDR_REV_R0P0 0x00000000 -# define L2CC_IDR_REV_R1P0 0x00000002 -# define L2CC_IDR_REV_R2P0 0x00000004 -# define L2CC_IDR_REV_R3P0 0x00000005 -# define L2CC_IDR_REV_R3P1 0x00000006 -# define L2CC_IDR_REV_R3P2 0x00000008 +#define L2CC_IDR_REV_R0P0 0x00000000 +#define L2CC_IDR_REV_R1P0 0x00000002 +#define L2CC_IDR_REV_R2P0 0x00000004 +#define L2CC_IDR_REV_R3P0 0x00000005 +#define L2CC_IDR_REV_R3P1 0x00000006 +#define L2CC_IDR_REV_R3P2 0x00000008 /* Cache Type Register */ #define L2CC_TYPR_IL2ASS (1 << 6) /* Bit 6: Instruction L2 Cache Associativity */ #define L2CC_TYPR_IL2WSIZE_SHIFT (8) /* Bits 8-10: Instruction L2 Cache Way Size */ #define L2CC_TYPR_IL2WSIZE_MASK (7 << L2CC_TYPR_IL2WSIZE_SHIFT) -# define L2CC_TYPR_IL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT) +#define L2CC_TYPR_IL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT) #define L2CC_TYPR_DL2ASS (1 << 18) /* Bit 18: Data L2 Cache Associativity */ #define L2CC_TYPR_DL2WSIZE_SHIFT (20) /* Bits 20-22: Data L2 Cache Way Size */ #define L2CC_TYPR_DL2WSIZE_MASK (7 << L2CC_TYPR_DL2WSIZE_SHIFT) -# define L2CC_TYPR_DL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT) +#define L2CC_TYPR_DL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT) /* Control Register */ @@ -202,21 +203,22 @@ #define L2CC_ACR_ASS (1 << 16) /* Bit 16: Associativity */ #define L2CC_ACR_WAYSIZE_SHIFT (17) /* Bits 17-19: Way Size */ #define L2CC_ACR_WAYSIZE_MASK (7 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_16KB (1 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_32KB (2 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_64KB (3 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_128KB (4 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_256KB (5 << L2CC_ACR_WAYSIZE_SHIFT) -# define L2CC_ACR_WAYSIZE_512KB (6 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_16KB (1 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_32KB (2 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_64KB (3 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_128KB (4 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_256KB (5 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_512KB (6 << L2CC_ACR_WAYSIZE_SHIFT) #define L2CC_ACR_EMBEN (1 << 20) /* Bit 20: Event Monitor Bus Enable */ #define L2CC_ACR_PEN (1 << 21) /* Bit 21: Parity Enable */ #define L2CC_ACR_SAOEN (1 << 22) /* Bit 22: Shared Attribute Override Enable */ #define L2CC_ACR_FWA_SHIFT (23) /* Bits 23-24: Force Write Allocate */ #define L2CC_ACR_FWA_MASK (3 << L2CC_ACR_FWA_SHIFT) -# define L2CC_ACR_FWA_AWCACHE (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */ -# define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */ -# define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */ -# define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */ +#define L2CC_ACR_FWA_AWCACHE (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */ +#define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */ +#define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */ +#define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */ + #define L2CC_ACR_CRPOL (1 << 25) /* Bit 25: Cache Replacement Policy */ #define L2CC_ACR_NSLEN (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */ #define L2CC_ACR_NSIAC (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */ @@ -230,25 +232,25 @@ #define L2CC_TRCR_TSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */ #define L2CC_TRCR_TSETLAT_MASK (7 << L2CC_TRCR_TSETLAT_SHIFT) -# define L2CC_TRCR_TSETLAT(n) ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT) +#define L2CC_TRCR_TSETLAT(n) ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT) #define L2CC_TRCR_TRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */ #define L2CC_TRCR_TRDLAT_MASK (7 << L2CC_TRCR_TRDLAT_SHIFT) -# define L2CC_TRCR_TRDLAT(n) ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT) +#define L2CC_TRCR_TRDLAT(n) ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT) #define L2CC_TRCR_TWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */ #define L2CC_TRCR_TWRLAT_MASK (7 << L2CC_TRCR_TWRLAT_SHIFT) -# define L2CC_TRCR_TWRLAT(n) ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT) +#define L2CC_TRCR_TWRLAT(n) ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT) /* Data RAM Control Register */ #define L2CC_DRCR_DSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */ #define L2CC_DRCR_DSETLAT_MASK (7 << L2CC_DRCR_DSETLAT_SHIFT) -# define L2CC_DRCR_DSETLAT(n) ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT) +#define L2CC_DRCR_DSETLAT(n) ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT) #define L2CC_DRCR_DRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */ #define L2CC_DRCR_DRDLAT_MASK (7 << L2CC_DRCR_DRDLAT_SHIFT) -# define L2CC_DRCR_DRDLAT(n) ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT) +#define L2CC_DRCR_DRDLAT(n) ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT) #define L2CC_DRCR_DWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */ #define L2CC_DRCR_DWRLAT_MASK (7 << L2CC_DRCR_DWRLAT_SHIFT) -# define L2CC_DRCR_DWRLAT(n) ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT) +#define L2CC_DRCR_DWRLAT(n) ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT) /* Event Counter Control Register */ @@ -258,60 +260,60 @@ /* Event Counter 1 Configuration Register */ - -#define L2CC_ECFGR1_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ -#define L2CC_ECFGR1_EIGEN_MASK (3 << L2CC_ECFGR1_EIGEN_SHIFT) -# define L2CC_ECFGR1_EIGEN_INTDIS (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */ -# define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */ -# define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */ -# define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */ -#define L2CC_ECFGR1_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ -#define L2CC_ECFGR1_ESRC_MASK (15 << L2CC_ECFGR1_ESRC_SHIFT) -# define L2CC_ECFGR1_ESRC_CNTDIS (0 << L2CC_ECFGR1_ESRC_SHIFT) /* Counter Disabled */ -# define L2CC_ECFGR1_ESRC_CO (1 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is CO */ -# define L2CC_ECFGR1_ESRC_DRHIT (2 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRHIT */ -# define L2CC_ECFGR1_ESRC_DRREQ (3 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRREQ */ -# define L2CC_ECFGR1_ESRC_DWHIT (4 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWHIT */ -# define L2CC_ECFGR1_ESRC_DWREQ (5 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWREQ */ -# define L2CC_ECFGR1_ESRC_DWTREQ (6 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWTREQ */ -# define L2CC_ECFGR1_ESRC_IRHIT (7 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRHIT */ -# define L2CC_ECFGR1_ESRC_IRREQ (8 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRREQ */ -# define L2CC_ECFGR1_ESRC_WA (9 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is WA */ -# define L2CC_ECFGR1_ESRC_IPFALLOC (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */ -# define L2CC_ECFGR1_ESRC_EPFHIT (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */ -# define L2CC_ECFGR1_ESRC_EPFALLOC (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */ -# define L2CC_ECFGR1_ESRC_SRRCVD (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */ -# define L2CC_ECFGR1_ESRC_SRCONF (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */ -# define L2CC_ECFGR1_ESRC_EPFRCVD (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */ +#define L2CC_ECFGR1_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ +#define L2CC_ECFGR1_EIGEN_MASK (3 << L2CC_ECFGR1_EIGEN_SHIFT) +#define L2CC_ECFGR1_EIGEN_INTDIS (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */ +#define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */ +#define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */ +#define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */ +#define L2CC_ECFGR1_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ +#define L2CC_ECFGR1_ESRC_MASK (15 << L2CC_ECFGR1_ESRC_SHIFT) +#define L2CC_ECFGR1_ESRC_CNTDIS (0 << L2CC_ECFGR1_ESRC_SHIFT) /* Counter Disabled */ +#define L2CC_ECFGR1_ESRC_CO (1 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is CO */ +#define L2CC_ECFGR1_ESRC_DRHIT (2 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRHIT */ +#define L2CC_ECFGR1_ESRC_DRREQ (3 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRREQ */ +#define L2CC_ECFGR1_ESRC_DWHIT (4 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWHIT */ +#define L2CC_ECFGR1_ESRC_DWREQ (5 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWREQ */ +#define L2CC_ECFGR1_ESRC_DWTREQ (6 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWTREQ */ +#define L2CC_ECFGR1_ESRC_IRHIT (7 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRHIT */ +#define L2CC_ECFGR1_ESRC_IRREQ (8 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRREQ */ +#define L2CC_ECFGR1_ESRC_WA (9 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is WA */ +#define L2CC_ECFGR1_ESRC_IPFALLOC (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */ +#define L2CC_ECFGR1_ESRC_EPFHIT (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */ +#define L2CC_ECFGR1_ESRC_EPFALLOC (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */ +#define L2CC_ECFGR1_ESRC_SRRCVD (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */ +#define L2CC_ECFGR1_ESRC_SRCONF (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */ +#define L2CC_ECFGR1_ESRC_EPFRCVD (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */ /* Event Counter 0 Configuration Register */ -#define L2CC_ECFGR0_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ -#define L2CC_ECFGR0_EIGEN_MASK (3 << L2CC_ECFGR0_EIGEN_SHIFT) -# define L2CC_ECFGR0_EIGEN_INTDIS (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */ -# define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */ -# define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */ -# define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */ -#define L2CC_ECFGR0_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ -#define L2CC_ECFGR0_ESRC_MASK (15 << L2CC_ECFGR0_ESRC_SHIFT) -# define L2CC_ECFGR0_ESRC_CNTDIS (0 << L2CC_ECFGR0_ESRC_SHIFT) /* Counter Disabled */ -# define L2CC_ECFGR0_ESRC_CO (1 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is CO */ -# define L2CC_ECFGR0_ESRC_DRHIT (2 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRHIT */ -# define L2CC_ECFGR0_ESRC_DRREQ (3 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRREQ */ -# define L2CC_ECFGR0_ESRC_DWHIT (4 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWHIT */ -# define L2CC_ECFGR0_ESRC_DWREQ (5 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWREQ */ -# define L2CC_ECFGR0_ESRC_DWTREQ (6 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWTREQ */ -# define L2CC_ECFGR0_ESRC_IRHIT (7 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRHIT */ -# define L2CC_ECFGR0_ESRC_IRREQ (8 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRREQ */ -# define L2CC_ECFGR0_ESRC_WA (9 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is WA */ -# define L2CC_ECFGR0_ESRC_IPFALLOC (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */ -# define L2CC_ECFGR0_ESRC_EPFHIT (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */ -# define L2CC_ECFGR0_ESRC_EPFALLOC (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */ -# define L2CC_ECFGR0_ESRC_SRRCVD (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */ -# define L2CC_ECFGR0_ESRC_SRCONF (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */ -# define L2CC_ECFGR0_ESRC_EPFRCVD (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */ +#define L2CC_ECFGR0_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ +#define L2CC_ECFGR0_EIGEN_MASK (3 << L2CC_ECFGR0_EIGEN_SHIFT) +#define L2CC_ECFGR0_EIGEN_INTDIS (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */ +#define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */ +#define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */ +#define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */ +#define L2CC_ECFGR0_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ +#define L2CC_ECFGR0_ESRC_MASK (15 << L2CC_ECFGR0_ESRC_SHIFT) +#define L2CC_ECFGR0_ESRC_CNTDIS (0 << L2CC_ECFGR0_ESRC_SHIFT) /* Counter Disabled */ +#define L2CC_ECFGR0_ESRC_CO (1 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is CO */ +#define L2CC_ECFGR0_ESRC_DRHIT (2 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRHIT */ +#define L2CC_ECFGR0_ESRC_DRREQ (3 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRREQ */ +#define L2CC_ECFGR0_ESRC_DWHIT (4 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWHIT */ +#define L2CC_ECFGR0_ESRC_DWREQ (5 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWREQ */ +#define L2CC_ECFGR0_ESRC_DWTREQ (6 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWTREQ */ +#define L2CC_ECFGR0_ESRC_IRHIT (7 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRHIT */ +#define L2CC_ECFGR0_ESRC_IRREQ (8 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRREQ */ +#define L2CC_ECFGR0_ESRC_WA (9 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is WA */ +#define L2CC_ECFGR0_ESRC_IPFALLOC (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */ +#define L2CC_ECFGR0_ESRC_EPFHIT (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */ +#define L2CC_ECFGR0_ESRC_EPFALLOC (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */ +#define L2CC_ECFGR0_ESRC_SRRCVD (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */ +#define L2CC_ECFGR0_ESRC_SRCONF (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */ +#define L2CC_ECFGR0_ESRC_EPFRCVD (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */ /* Event Counter 1 Value Register (32-bit value) */ + /* Event Counter 0 Value Register (32-bit value) */ /* Interrupt Mask Register, Masked Interrupt Status Register, Raw Interrupt Status @@ -337,110 +339,110 @@ #define L2CC_IPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ #define L2CC_IPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ #define L2CC_IPALR_IDX_MASK (0x1ff << L2CC_IPALR_IDX_SHIFT) -# define L2CC_IPALR_IDX(n) ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT) +#define L2CC_IPALR_IDX(n) ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT) #define L2CC_IPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */ #define L2CC_IPALR_TAG_MASK (0x3ffff << L2CC_IPALR_TAG_SHIFT) -# define L2CC_IPALR_TAG(n) ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT) +#define L2CC_IPALR_TAG(n) ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT) /* Invalidate Way Register */ #define L2CC_IWR_WAY(n) (1 << (n)) /* Bist 0-7: Invalidate Way Number n, n=0..7 */ -# define L2CC_IWR_WAY0 (1 << 0) /* Bit 0: Invalidate Way Number 0 */ -# define L2CC_IWR_WAY1 (1 << 1) /* Bit 1: Invalidate Way Number 1 */ -# define L2CC_IWR_WAY2 (1 << 2) /* Bit 2: Invalidate Way Number 2 */ -# define L2CC_IWR_WAY3 (1 << 3) /* Bit 3: Invalidate Way Number 3 */ -# define L2CC_IWR_WAY4 (1 << 4) /* Bit 4: Invalidate Way Number 4 */ -# define L2CC_IWR_WAY5 (1 << 5) /* Bit 5: Invalidate Way Number 5 */ -# define L2CC_IWR_WAY6 (1 << 6) /* Bit 6: Invalidate Way Number 6 */ -# define L2CC_IWR_WAY7 (1 << 7) /* Bit 7: Invalidate Way Number 7 */ +#define L2CC_IWR_WAY0 (1 << 0) /* Bit 0: Invalidate Way Number 0 */ +#define L2CC_IWR_WAY1 (1 << 1) /* Bit 1: Invalidate Way Number 1 */ +#define L2CC_IWR_WAY2 (1 << 2) /* Bit 2: Invalidate Way Number 2 */ +#define L2CC_IWR_WAY3 (1 << 3) /* Bit 3: Invalidate Way Number 3 */ +#define L2CC_IWR_WAY4 (1 << 4) /* Bit 4: Invalidate Way Number 4 */ +#define L2CC_IWR_WAY5 (1 << 5) /* Bit 5: Invalidate Way Number 5 */ +#define L2CC_IWR_WAY6 (1 << 6) /* Bit 6: Invalidate Way Number 6 */ +#define L2CC_IWR_WAY7 (1 << 7) /* Bit 7: Invalidate Way Number 7 */ /* Clean Physical Address Line Register */ #define L2CC_CPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ #define L2CC_CPALR_IDX_SHIFT (5) /* Bits 5-13: Index number */ #define L2CC_CPALR_IDX_MASK (0x1ff << L2CC_CPALR_IDX_SHIFT) -# define L2CC_CPALR_IDX(n) ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT) +#define L2CC_CPALR_IDX(n) ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT) #define L2CC_CPALR_TAG_SHIFT (14) /* Bits 14-31: Tag number */ #define L2CC_CPALR_TAG_MASK (0x3ffff << L2CC_CPALR_TAG_SHIFT) -# define L2CC_CPALR_TAG(n) ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT) +#define L2CC_CPALR_TAG(n) ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT) /* Clean Index Register */ #define L2CC_CIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ #define L2CC_CIR_IDX_SHIFT (5) /* Bits 5-13: Index number */ #define L2CC_CIR_IDX_MASK (0x1ff << L2CC_CIR_IDX_SHIFT) -# define L2CC_CIR_IDX(n) ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT) +#define L2CC_CIR_IDX(n) ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT) #define L2CC_CIR_WAY_SHIFT (28) /* Bits 28-30: Way number */ #define L2CC_CIR_WAY_MASK (7 << L2CC_CIR_WAY_SHIFT) -# define L2CC_CIR_WAY(n) ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT) +#define L2CC_CIR_WAY(n) ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT) /* Clean Way Register */ #define L2CC_CWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Way Number n, n=0..7 */ -# define L2CC_CWR_WAY0 (1 << 0) /* Bit 0: Clean Way Number 0 */ -# define L2CC_CWR_WAY1 (1 << 1) /* Bit 1: Clean Way Number 1 */ -# define L2CC_CWR_WAY2 (1 << 2) /* Bit 2: Clean Way Number 2 */ -# define L2CC_CWR_WAY3 (1 << 3) /* Bit 3: Clean Way Number 3 */ -# define L2CC_CWR_WAY4 (1 << 4) /* Bit 4: Clean Way Number 4 */ -# define L2CC_CWR_WAY5 (1 << 5) /* Bit 5: Clean Way Number 5 */ -# define L2CC_CWR_WAY6 (1 << 6) /* Bit 6: Clean Way Number 6 */ -# define L2CC_CWR_WAY7 (1 << 7) /* Bit 7: Clean Way Number 7 */ +#define L2CC_CWR_WAY0 (1 << 0) /* Bit 0: Clean Way Number 0 */ +#define L2CC_CWR_WAY1 (1 << 1) /* Bit 1: Clean Way Number 1 */ +#define L2CC_CWR_WAY2 (1 << 2) /* Bit 2: Clean Way Number 2 */ +#define L2CC_CWR_WAY3 (1 << 3) /* Bit 3: Clean Way Number 3 */ +#define L2CC_CWR_WAY4 (1 << 4) /* Bit 4: Clean Way Number 4 */ +#define L2CC_CWR_WAY5 (1 << 5) /* Bit 5: Clean Way Number 5 */ +#define L2CC_CWR_WAY6 (1 << 6) /* Bit 6: Clean Way Number 6 */ +#define L2CC_CWR_WAY7 (1 << 7) /* Bit 7: Clean Way Number 7 */ /* Clean Invalidate Physical Address Line Register */ #define L2CC_CIPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ #define L2CC_CIPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ #define L2CC_CIPALR_IDX_MASK (0x1ff << L2CC_CIPALR_IDX_SHIFT) -# define L2CC_CIPALR_IDX(n) ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT) +#define L2CC_CIPALR_IDX(n) ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT) #define L2CC_CIPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */ #define L2CC_CIPALR_TAG_MASK (0x3ffff << L2CC_CIPALR_TAG_SHIFT) -# define L2CC_CIPALR_TAG(n) ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT) +#define L2CC_CIPALR_TAG(n) ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT) /* Clean Invalidate Index Register */ #define L2CC_CIIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ #define L2CC_CIIR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ #define L2CC_CIIR_IDX_MASK (0x1ff << L2CC_CIIR_IDX_SHIFT) -# define L2CC_CIIR_IDX(n) ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT) +#define L2CC_CIIR_IDX(n) ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT) #define L2CC_CIIR_WAY_SHIFT (28) /* Bits 28-30: Way Number */ #define L2CC_CIIR_WAY_MASK (7 << L2CC_CIIR_WAY_SHIFT) -# define L2CC_CIIR_WAY(n) ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT) +#define L2CC_CIIR_WAY(n) ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT) /* Clean Invalidate Way Register */ #define L2CC_CIWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Invalidate Way Number n, n=1..7 */ -# define L2CC_CIWR_WAY0 (1 << 0) /* Bit 0: Clean Invalidate Way Number 0 */ -# define L2CC_CIWR_WAY1 (1 << 1) /* Bit 1: Clean Invalidate Way Number 1 */ -# define L2CC_CIWR_WAY2 (1 << 2) /* Bit 2: Clean Invalidate Way Number 2 */ -# define L2CC_CIWR_WAY3 (1 << 3) /* Bit 3: Clean Invalidate Way Number 3 */ -# define L2CC_CIWR_WAY4 (1 << 4) /* Bit 4: Clean Invalidate Way Number 4 */ -# define L2CC_CIWR_WAY5 (1 << 5) /* Bit 5: Clean Invalidate Way Number 5 */ -# define L2CC_CIWR_WAY6 (1 << 6) /* Bit 6: Clean Invalidate Way Number 6 */ -# define L2CC_CIWR_WAY7 (1 << 7) /* Bit 7: Clean Invalidate Way Number 7 */ +#define L2CC_CIWR_WAY0 (1 << 0) /* Bit 0: Clean Invalidate Way Number 0 */ +#define L2CC_CIWR_WAY1 (1 << 1) /* Bit 1: Clean Invalidate Way Number 1 */ +#define L2CC_CIWR_WAY2 (1 << 2) /* Bit 2: Clean Invalidate Way Number 2 */ +#define L2CC_CIWR_WAY3 (1 << 3) /* Bit 3: Clean Invalidate Way Number 3 */ +#define L2CC_CIWR_WAY4 (1 << 4) /* Bit 4: Clean Invalidate Way Number 4 */ +#define L2CC_CIWR_WAY5 (1 << 5) /* Bit 5: Clean Invalidate Way Number 5 */ +#define L2CC_CIWR_WAY6 (1 << 6) /* Bit 6: Clean Invalidate Way Number 6 */ +#define L2CC_CIWR_WAY7 (1 << 7) /* Bit 7: Clean Invalidate Way Number 7 */ /* Data Lockdown Register */ #define L2CC_DLKR_DLK(n) (1 << (n)) /* Bits 0-7: Data Lockdown in Way Number n, n=0..7 */ -# define L2CC_DLKR_DLK0 (1 << 0) /* Bit 0: Data Lockdown in Way Number 0 */ -# define L2CC_DLKR_DLK1 (1 << 1) /* Bit 1: Data Lockdown in Way Number 1 */ -# define L2CC_DLKR_DLK2 (1 << 2) /* Bit 2: Data Lockdown in Way Number 2 */ -# define L2CC_DLKR_DLK3 (1 << 3) /* Bit 3: Data Lockdown in Way Number 3 */ -# define L2CC_DLKR_DLK4 (1 << 4) /* Bit 4: Data Lockdown in Way Number 4 */ -# define L2CC_DLKR_DLK5 (1 << 5) /* Bit 5: Data Lockdown in Way Number 5 */ -# define L2CC_DLKR_DLK6 (1 << 6) /* Bit 6: Data Lockdown in Way Number 6 */ -# define L2CC_DLKR_DLK7 (1 << 7) /* Bit 7: Data Lockdown in Way Number 7 */ +#define L2CC_DLKR_DLK0 (1 << 0) /* Bit 0: Data Lockdown in Way Number 0 */ +#define L2CC_DLKR_DLK1 (1 << 1) /* Bit 1: Data Lockdown in Way Number 1 */ +#define L2CC_DLKR_DLK2 (1 << 2) /* Bit 2: Data Lockdown in Way Number 2 */ +#define L2CC_DLKR_DLK3 (1 << 3) /* Bit 3: Data Lockdown in Way Number 3 */ +#define L2CC_DLKR_DLK4 (1 << 4) /* Bit 4: Data Lockdown in Way Number 4 */ +#define L2CC_DLKR_DLK5 (1 << 5) /* Bit 5: Data Lockdown in Way Number 5 */ +#define L2CC_DLKR_DLK6 (1 << 6) /* Bit 6: Data Lockdown in Way Number 6 */ +#define L2CC_DLKR_DLK7 (1 << 7) /* Bit 7: Data Lockdown in Way Number 7 */ /* Instruction Lockdown Register */ #define L2CC_ILKR_ILK(n) (1 << (n)) /* Bits 0-7: Instruction Lockdown in Way Number n, n=0..7 */ -# define L2CC_ILKR_ILK0 (1 << 0) /* Bit 0: Instruction Lockdown in Way Number 0 */ -# define L2CC_ILKR_ILK1 (1 << 1) /* Bit 1: Instruction Lockdown in Way Number 1 */ -# define L2CC_ILKR_ILK2 (1 << 2) /* Bit 2: Instruction Lockdown in Way Number 2 */ -# define L2CC_ILKR_ILK3 (1 << 3) /* Bit 3: Instruction Lockdown in Way Number 3 */ -# define L2CC_ILKR_ILK4 (1 << 4) /* Bit 4: Instruction Lockdown in Way Number 4 */ -# define L2CC_ILKR_ILK5 (1 << 5) /* Bit 5: Instruction Lockdown in Way Number 5 */ -# define L2CC_ILKR_ILK6 (1 << 6) /* Bit 6: Instruction Lockdown in Way Number 6 */ -# define L2CC_ILKR_ILK7 (1 << 7) /* Bit 7: Instruction Lockdown in Way Number 7 */ +#define L2CC_ILKR_ILK0 (1 << 0) /* Bit 0: Instruction Lockdown in Way Number 0 */ +#define L2CC_ILKR_ILK1 (1 << 1) /* Bit 1: Instruction Lockdown in Way Number 1 */ +#define L2CC_ILKR_ILK2 (1 << 2) /* Bit 2: Instruction Lockdown in Way Number 2 */ +#define L2CC_ILKR_ILK3 (1 << 3) /* Bit 3: Instruction Lockdown in Way Number 3 */ +#define L2CC_ILKR_ILK4 (1 << 4) /* Bit 4: Instruction Lockdown in Way Number 4 */ +#define L2CC_ILKR_ILK5 (1 << 5) /* Bit 5: Instruction Lockdown in Way Number 5 */ +#define L2CC_ILKR_ILK6 (1 << 6) /* Bit 6: Instruction Lockdown in Way Number 6 */ +#define L2CC_ILKR_ILK7 (1 << 7) /* Bit 7: Instruction Lockdown in Way Number 7 */ /* Lock Line Enable Register */ @@ -453,8 +455,8 @@ #ifdef CONFIG_PL310_LOCKDOWN_BY_LINE # define L2CC_UNLKW_WAY_SHIFT (0) /* Bits 0-15: Unlock line for corresponding way */ # define L2CC_UNLKW_WAY_MASK (0xffff << L2CC_UNLKW_WAY_SHIFT) -# define L2CC_UNLKW_WAY_SET(n) ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT) -# define L2CC_UNLKW_WAY_BIT(n) ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT) +# define L2CC_UNLKW_WAY_SET(n) ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT) +# define L2CC_UNLKW_WAY_BIT(n) ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT) #endif /* Address filter start */ @@ -480,7 +482,7 @@ #define L2CC_PCR_SHIFT (0) /* Bits 0-4: Prefetch Offset */ #define L2CC_PCR_MASK (31 << L2CC_PCR_SHIFT) -# define L2CC_PCR_PREFETCH(n) ((uint32_t)(n) << L2CC_PCR_SHIFT) +#define L2CC_PCR_PREFETCH(n) ((uint32_t)(n) << L2CC_PCR_SHIFT) #define L2CC_PCR_NSIDEN (1 << 21) /* Bit 21: Not Same ID on Exclusive Sequence Enable */ #define L2CC_PCR_IDLEN (1 << 23) /* Bit 23: INCR Double Linefill Enable */ #define L2CC_PCR_PDEN (1 << 24) /* Bit 24: Prefetch Drop Enable */ From 902068629c39ac749e2afafc1b45061e77efaafb Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 16 Nov 2020 13:52:19 +0900 Subject: [PATCH 03/10] arch: armv7-a: Fix compile errors in arm_l2cc_pl310.c Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/arm_l2cc_pl310.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c index 1239556d8bfb9..9fa82f80f12b5 100644 --- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c @@ -67,7 +67,7 @@ #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) # define PL310_NWAYS 8 # define PL310_WAY_MASK 0x000000ff -#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) +#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY) # define PL310_NWAYS 16 # define PL310_WAY_MASK 0x0000ffff #else From 79ef13fd56de6c68eba8994c9b65a6152854876b Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 16 Nov 2020 13:53:49 +0900 Subject: [PATCH 04/10] arch: armv7-a: Fix comile errors in l2cc_pl310.h Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/l2cc_pl310.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-a/l2cc_pl310.h b/arch/arm/src/armv7-a/l2cc_pl310.h index b42c864099bce..1c283c93230eb 100644 --- a/arch/arm/src/armv7-a/l2cc_pl310.h +++ b/arch/arm/src/armv7-a/l2cc_pl310.h @@ -52,7 +52,7 @@ * header file as L2CC_VBASE. */ -#include "chip/chip.h" +#include "chip.h" /************************************************************************************ * Pre-processor Definitions From 8a53e36fe96461cbb1ae9e17a27c1c949da11801 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 16 Nov 2020 13:57:11 +0900 Subject: [PATCH 05/10] arch: imx6: Fix compile errors in chip.h Signed-off-by: Masayuki Ishikawa > --- arch/arm/src/imx6/chip.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/src/imx6/chip.h b/arch/arm/src/imx6/chip.h index c994f8c784be9..705fbe6d5ef22 100644 --- a/arch/arm/src/imx6/chip.h +++ b/arch/arm/src/imx6/chip.h @@ -61,6 +61,12 @@ #define CHIP_MPCORE_VBASE IMX_ARMMP_VSECTION +/* arch/arm/src/armv7-a/l2cc_pl310.h includes this file and expects it + * to provide the address of the L2CC-PL310 implementation. + */ + +#define L2CC_VBASE IMX_PL310_VBASE + /**************************************************************************** * Macro Definitions ****************************************************************************/ From 7e3238e4d361ea77ca63610dc9ac89271209c60f Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 16 Nov 2020 13:58:57 +0900 Subject: [PATCH 06/10] arch: imx6: Add arm_l2cc_pl310.c to Make.defs Signed-off-by: Masayuki Ishikawa --- arch/arm/src/imx6/Make.defs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index e07033fcdfabf..eb84c44ef171b 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -117,6 +117,10 @@ endif CMN_CSRCS += arm_cache.c +ifeq ($(CONFIG_ARCH_L2CACHE),y) +CMN_CSRCS += arm_l2cc_pl310.c +endif + ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += arm_savefpu.S arm_restorefpu.S CMN_CSRCS += arm_copyarmstate.c From 16f85352dbb0978e826e63bc044c2d07720560dd Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 16 Nov 2020 14:01:06 +0900 Subject: [PATCH 07/10] arch: armv7-a: Fix arm_l2cc_pl310.c with DEBUGASSERT() Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/arm_l2cc_pl310.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c index 9fa82f80f12b5..d387bc8aa8e81 100644 --- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c @@ -333,7 +333,7 @@ void arm_l2ccinitialize(void) #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0); #elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 1); + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS); #else # error No associativity selected #endif From 911d952185b818baf427564bbe0f4051aad1ff89 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 16 Nov 2020 15:04:51 +0900 Subject: [PATCH 08/10] boards: sabre-6quad: Enable L2CC for nsh/defconfig Summary: - This commit adds L2CC to nsh/defconfig - Also adds EXAMPLES_HELLO, TESTING_GETPRIME and TESTING_OSTEST Impact: - sabre-6quad:nsh only Testing: - Tested with both QEMU and dev board Signed-off-by: Masayuki Ishikawa --- boards/arm/imx6/sabre-6quad/configs/nsh/defconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig b/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig index 30aa9a25a8b34..b804cde2f7a13 100644 --- a/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/nsh/defconfig @@ -17,12 +17,18 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_LOWVECTORS=y CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7A_ASSOCIATIVITY_16WAY=y +CONFIG_ARMV7A_L2CC_PL310=y +CONFIG_ARMV7A_WAYSIZE_64KB=y CONFIG_BOARD_LOOPSPERMSEC=99369 CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y @@ -35,6 +41,8 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y +CONFIG_PL310_LOCKDOWN_BY_LINE=y +CONFIG_PL310_LOCKDOWN_BY_MASTER=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAMLOG=y CONFIG_RAMLOG_BUFSIZE=16384 @@ -53,5 +61,7 @@ CONFIG_START_MONTH=3 CONFIG_START_YEAR=2016 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y CONFIG_UART1_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" From 8f0f0f00024edaa0c1795b286ba6bff27854151a Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 16 Nov 2020 15:08:25 +0900 Subject: [PATCH 09/10] boards: sabre-6quad: Enable L2CC for smp/defconfig Summary: - This commit adds L2CC to smp/defconfig - Also adds CLOCK_MONOTONIC Impact: - sabre-6quad:smp only Testing: - Tested with both QEMU and dev board Signed-off-by: Masayuki Ishikawa --- boards/arm/imx6/sabre-6quad/configs/smp/defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/boards/arm/imx6/sabre-6quad/configs/smp/defconfig b/boards/arm/imx6/sabre-6quad/configs/smp/defconfig index 1177c272fcce1..5f2ee1a10de23 100644 --- a/boards/arm/imx6/sabre-6quad/configs/smp/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/smp/defconfig @@ -17,14 +17,19 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_LOWVECTORS=y CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7A_ASSOCIATIVITY_16WAY=y +CONFIG_ARMV7A_L2CC_PL310=y +CONFIG_ARMV7A_WAYSIZE_64KB=y CONFIG_BOARD_LOOPSPERMSEC=99369 CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_ZERO=y CONFIG_DRIVER_NOTE=y CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y @@ -36,6 +41,8 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y +CONFIG_PL310_LOCKDOWN_BY_LINE=y +CONFIG_PL310_LOCKDOWN_BY_MASTER=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAMLOG=y CONFIG_RAMLOG_BUFSIZE=16384 From adffd517d8846a3e083d328ccf6e4c1376c7862a Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 16 Nov 2020 15:17:18 +0900 Subject: [PATCH 10/10] arch: armv7-a: Remove unnecessary d-cache operation in arm_cpustart.c Summary: - Remove unnecessary d-cache operation to make boot fast Impact: - armv7-a SMP only Testing: - Tested with sabre-6quad:smp (QEMU and dev board) Signed-off-by: Masayuki Ishikawa --- arch/arm/src/armv7-a/arm_cpustart.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c index ca883d56de9f5..de6b037bf5629 100644 --- a/arch/arm/src/armv7-a/arm_cpustart.c +++ b/arch/arm/src/armv7-a/arm_cpustart.c @@ -171,10 +171,6 @@ int up_cpu_start(int cpu) sched_note_cpu_start(this_task(), cpu); #endif - /* Make the content of CPU0 L1 cache has been written to coherent L2 */ - - cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1); - /* Execute SGI1 */ return arm_cpu_sgi(GIC_IRQ_SGI1, (1 << cpu));