From 2a72d9d9bc6b2f51d8c2da15c72244853c44b037 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 6 Mar 2020 17:52:50 -0600 Subject: [PATCH] arch/z80/src/ez80/ez80_spi.c: Correct oversight in previous commit Commit 797e45d6bfc467743a3ff350858d2169cad5126e attempted to reduce the frequency of SPI reconfiguration by keeping track of the current frequency and mode settings and changing these settings only when the new settings differ from the old settings. However, the original commit neglected to save the new frequency setting and, hence, was not effective in what it was trying to do: Every time the SPI setfrequency() method was called, it still looked like a new frequency and the frequency was still reconfigured, even though it hadn't really changed. --- arch/z80/src/ez80/ez80_spi.c | 11 ++++++----- boards/z80/ez80/z20x/src/z20x.h | 4 ---- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/arch/z80/src/ez80/ez80_spi.c b/arch/z80/src/ez80/ez80_spi.c index fdb9ba039d81f..f46b4a5a06854 100644 --- a/arch/z80/src/ez80/ez80_spi.c +++ b/arch/z80/src/ez80/ez80_spi.c @@ -236,7 +236,8 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, outp(EZ80_SPI_BRG_L, brg & 0xff); outp(EZ80_SPI_BRG_H, (brg >> 8) & 0xff); - g_spi_actual = ((EZ80_SYS_CLK_FREQ + 1) / 2 + brg - 1) / brg; + g_spi_frequency = frequency; + g_spi_actual = ((EZ80_SYS_CLK_FREQ + 1) / 2 + brg - 1) / brg; finfo("BRG=%lu Actual=%lu\n", (unsigned long)brg, (unsigned long)g_spi_actual); @@ -580,10 +581,10 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, * prior to calling this function. Specifically: GPIOs should have * been configured for output, and all chip selects disabled. * - * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However, - * If multiple devices on on the bus, then multiple chip selects will be - * required. Therefore, all GPIO chip management is deferred to board- - * specific logic. + * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. + * However, if multiple devices on on the bus, then multiple chip + * selects will be required. Therefore, all GPIO chip management is + * deferred to board-specific logic. * * Input Parameters: * Port number (for hardware that has multiple SPI interfaces) diff --git a/boards/z80/ez80/z20x/src/z20x.h b/boards/z80/ez80/z20x/src/z20x.h index 64bc9cea08674..38c71c3412317 100644 --- a/boards/z80/ez80/z20x/src/z20x.h +++ b/boards/z80/ez80/z20x/src/z20x.h @@ -86,10 +86,6 @@ * Chip select 3 is not used */ -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /* RAM Memory map * * 040000 Beginning of RAM