diff --git a/src/tir/usmp/transform/assign_pool_info.cc b/src/tir/usmp/transform/assign_pool_info.cc
index 009083373690..e75610ea0551 100644
--- a/src/tir/usmp/transform/assign_pool_info.cc
+++ b/src/tir/usmp/transform/assign_pool_info.cc
@@ -49,7 +49,8 @@ class PoolInfoAssigner : public StmtExprMutator {
     Array<usmp::PoolInfo> pool_infos =
         module->GetAttr<Array<usmp::PoolInfo>>(tvm::attr::kPoolInfoIRModuleAttr)
             .value_or({usmp::PoolInfo(
-                "global_workspace", {{target_host.value(), PoolInfo::kTargetPoolReadWriteAccess}},
+                "global_workspace",
+                {{target_host.value(), String(PoolInfo::kTargetPoolReadWriteAccess)}},
                 PoolInfo::kUnrestrictedPoolSizeHint, PoolInfo::kUnknownClockFrequency,
                 PoolInfo::kUnknownReadBandwidth, PoolInfo::kUnknownWriteBandwidth, 0, 0,
                 {{target_host.value(), 1}}, Bool(true))});
diff --git a/tests/python/unittest/test_meta_schedule_mutator_mutate_tile_size.py b/tests/python/unittest/test_meta_schedule_mutator_mutate_tile_size.py
index 9e75497b6cc2..4a3b1f8e943a 100644
--- a/tests/python/unittest/test_meta_schedule_mutator_mutate_tile_size.py
+++ b/tests/python/unittest/test_meta_schedule_mutator_mutate_tile_size.py
@@ -79,7 +79,7 @@ def test_mutate_tile_size_matmul():
     )
     results = {}
     sch = _sch(decisions=[[4, 32, 4, 1]])
-    for _ in range(100):
+    for _ in range(1000):
         trace = mutator.apply(sch.trace)
         assert trace.insts[4].kind.name == "SamplePerfectTile"
         decision = trace.decisions[trace.insts[4]]