From 0813fe0a15e66bdd429ac18d8c87c4b59f6f6ffd Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Sat, 23 Nov 2019 16:18:02 +0800 Subject: [PATCH 01/24] Update task_python_vta.sh --- tests/scripts/task_python_vta.sh | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/tests/scripts/task_python_vta.sh b/tests/scripts/task_python_vta.sh index 397efa139770..4b3f0e1cf6c5 100755 --- a/tests/scripts/task_python_vta.sh +++ b/tests/scripts/task_python_vta.sh @@ -35,19 +35,19 @@ python3 -m pytest -v vta/tests/python/unittest echo "Running integration test in fsim..." python3 -m pytest -v vta/tests/python/integration -# # Build VTA chisel design and verilator simulator -# (make -C vta/hardware/chisel/) +# Build VTA chisel design and verilator simulator +make -C vta/hardware/chisel/ -# # Set default VTA config to use TSIM cycle accurate sim -# cp vta/config/tsim_sample.json vta/config/vta_config.json +# Set default VTA config to use TSIM cycle accurate sim +cp vta/config/tsim_sample.json vta/config/vta_config.json -# # Run unit tests in cycle accurate simulator -# echo "Running unittest in tsim..." -# python3 -m pytest -v vta/tests/python/unittest +# Run unit tests in cycle accurate simulator +echo "Running unittest in tsim..." +python3 -m pytest -v vta/tests/python/unittest -# # Run unit tests in cycle accurate simulator -# echo "Running integration test in tsim..." -# python3 -m pytest -v vta/tests/python/integration +# Run unit tests in cycle accurate simulator +echo "Running integration test in tsim..." +python3 -m pytest -v vta/tests/python/integration -# # Reset default fsim simulation -# cp vta/config/fsim_sample.json vta/config/vta_config.json +# Reset default fsim simulation +cp vta/config/fsim_sample.json vta/config/vta_config.json From c59ead432fc52767efcd3e6eb28cd8249f7ac507 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Tue, 7 Jan 2020 16:27:41 +0800 Subject: [PATCH 02/24] install sbt=1.1.1 with apt-get --- docker/install/ubuntu_install_chisel.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/docker/install/ubuntu_install_chisel.sh b/docker/install/ubuntu_install_chisel.sh index 6a0dafc8ed41..072ce67916ff 100755 --- a/docker/install/ubuntu_install_chisel.sh +++ b/docker/install/ubuntu_install_chisel.sh @@ -28,4 +28,6 @@ apt-get install apt-transport-https echo "deb https://dl.bintray.com/sbt/debian /" | tee -a /etc/apt/sources.list.d/sbt.list apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823 apt-get update -apt-get install -y verilator sbt +# Note: The settings in vta/hardware/chisel/project/build.properties +# file determines required sbt version. +apt-get install -y verilator sbt=1.1.1 From 33fa60cffcee98f388a87aabeb2e42df501ccb0d Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Tue, 7 Jan 2020 17:05:17 +0800 Subject: [PATCH 03/24] update verilator_opt --- vta/hardware/chisel/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vta/hardware/chisel/Makefile b/vta/hardware/chisel/Makefile index 743f6c6f2f80..a98c52c77078 100644 --- a/vta/hardware/chisel/Makefile +++ b/vta/hardware/chisel/Makefile @@ -94,7 +94,7 @@ else endif ifneq ($(USE_THREADS), 0) - verilator_opt += -threads $(USE_THREADS) + verilator_opt += --threads $(USE_THREADS) cxx_flags += -DVL_THREADED cxx_objs += $(verilator_build_dir)/verilated_threads.o endif From d8b9dfde8e51af2feadf99e0ad2c87abc2a37874 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Tue, 7 Jan 2020 18:10:40 +0800 Subject: [PATCH 04/24] install verilator with major version 4.0 --- docker/install/ubuntu_install_chisel.sh | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/docker/install/ubuntu_install_chisel.sh b/docker/install/ubuntu_install_chisel.sh index 072ce67916ff..c78439b32c6a 100755 --- a/docker/install/ubuntu_install_chisel.sh +++ b/docker/install/ubuntu_install_chisel.sh @@ -30,4 +30,12 @@ apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2 apt-get update # Note: The settings in vta/hardware/chisel/project/build.properties # file determines required sbt version. -apt-get install -y verilator sbt=1.1.1 +apt-get install -y sbt=1.1.1 + +# Install the Verilator with major version 4.0 +wget https://www.veripool.org/ftp/verilator-4.010.tgz +tar xf verilator-4.010.tgz +cd verilator-4.010/ +./configure +make -j4 +make install From 8f63c39b20358cf5adc63101f6247f772a501630 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Wed, 8 Jan 2020 09:50:38 +0800 Subject: [PATCH 05/24] disable multi-threading for now --- tests/scripts/task_python_vta.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/scripts/task_python_vta.sh b/tests/scripts/task_python_vta.sh index 9b994be4ebca..bcce31b5bc42 100755 --- a/tests/scripts/task_python_vta.sh +++ b/tests/scripts/task_python_vta.sh @@ -38,7 +38,7 @@ echo "Running integration test in fsim..." python3 -m pytest -v vta/tests/python/integration # Build VTA chisel design and verilator simulator -make -C vta/hardware/chisel/ +make -C vta/hardware/chisel/ USE_THREADS=0 lib # Set default VTA config to use TSIM cycle accurate sim cp vta/config/tsim_sample.json vta/config/vta_config.json From a1d558c09ec67f19bc7d8f3e49c308ce446cf5c9 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Fri, 10 Jan 2020 16:43:57 +0800 Subject: [PATCH 06/24] bug fix for correcting uop fetch address in LoadUop module --- docker/install/ubuntu_install_chisel.sh | 12 +----------- .../chisel/src/main/scala/core/LoadUop.scala | 2 +- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/docker/install/ubuntu_install_chisel.sh b/docker/install/ubuntu_install_chisel.sh index c78439b32c6a..6a0dafc8ed41 100755 --- a/docker/install/ubuntu_install_chisel.sh +++ b/docker/install/ubuntu_install_chisel.sh @@ -28,14 +28,4 @@ apt-get install apt-transport-https echo "deb https://dl.bintray.com/sbt/debian /" | tee -a /etc/apt/sources.list.d/sbt.list apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823 apt-get update -# Note: The settings in vta/hardware/chisel/project/build.properties -# file determines required sbt version. -apt-get install -y sbt=1.1.1 - -# Install the Verilator with major version 4.0 -wget https://www.veripool.org/ftp/verilator-4.010.tgz -tar xf verilator-4.010.tgz -cd verilator-4.010/ -./configure -make -j4 -make install +apt-get install -y verilator sbt diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala index 3432ec641733..c1be6c872318 100644 --- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala +++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala @@ -133,7 +133,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { raddr := io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes))) }.otherwise { raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil( - uopBytes)))) - uopBytes.U + uopBytes)))) + uopBytes.U } }.elsewhen(state === sReadData && xcnt === xlen && xrem =/= 0.U) { raddr := raddr + xmax_bytes From b2848056eb562cc539c8dfbdc69c3df4df378039 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Fri, 10 Jan 2020 17:16:08 +0800 Subject: [PATCH 07/24] bug fix for correcting uop fetch address in LoadUop module --- vta/hardware/chisel/src/main/scala/core/LoadUop.scala | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala index c1be6c872318..a84179111ac8 100644 --- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala +++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala @@ -132,8 +132,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { when(offsetIsEven) { raddr := io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes))) }.otherwise { - raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil( - uopBytes)))) + uopBytes.U + raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes)))) + uopBytes.U } }.elsewhen(state === sReadData && xcnt === xlen && xrem =/= 0.U) { raddr := raddr + xmax_bytes From 85292ce87740347a874aa12e2767b39768604fd7 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Fri, 10 Jan 2020 17:36:37 +0800 Subject: [PATCH 08/24] adjustment to read from dram_offset --- vta/hardware/chisel/src/main/scala/core/LoadUop.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala index a84179111ac8..735b2b78feb5 100644 --- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala +++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala @@ -129,7 +129,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { // read-from-dram val maskOffset = VecInit(Seq.fill(M_DRAM_OFFSET_BITS)(true.B)).asUInt when(state === sIdle) { - when(offsetIsEven) { + when((dec.dram_offset % 2.U) === 0.U) { raddr := io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes))) }.otherwise { raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes)))) + uopBytes.U From fe24e25a0d6904ee047c322e94921f1a0c24b7d1 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Mon, 13 Jan 2020 09:55:16 +0800 Subject: [PATCH 09/24] enable USE_THREADS with verilator 4.x --- tests/scripts/task_python_vta.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/scripts/task_python_vta.sh b/tests/scripts/task_python_vta.sh index bcce31b5bc42..446e8c93d842 100755 --- a/tests/scripts/task_python_vta.sh +++ b/tests/scripts/task_python_vta.sh @@ -38,7 +38,7 @@ echo "Running integration test in fsim..." python3 -m pytest -v vta/tests/python/integration # Build VTA chisel design and verilator simulator -make -C vta/hardware/chisel/ USE_THREADS=0 lib +make -C vta/hardware/chisel/ USE_THREADS=4 lib # Set default VTA config to use TSIM cycle accurate sim cp vta/config/tsim_sample.json vta/config/vta_config.json From 6f5c6ddfb9ba1f0d6d029fee9c46769bea3c8461 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Mon, 13 Jan 2020 10:33:58 +0800 Subject: [PATCH 10/24] DEBUG: try avoid core dump with verilator 4.x --- tests/scripts/task_python_vta.sh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tests/scripts/task_python_vta.sh b/tests/scripts/task_python_vta.sh index 446e8c93d842..52dd641cbd22 100755 --- a/tests/scripts/task_python_vta.sh +++ b/tests/scripts/task_python_vta.sh @@ -29,6 +29,9 @@ rm -rf ~/.tvm # Rebuild cython make cython3 +# Reset default fsim simulation +cp vta/config/fsim_sample.json vta/config/vta_config.json + # Run unit tests in functional/fast simulator echo "Running unittest in fsim..." python3 -m pytest -v vta/tests/python/unittest @@ -38,7 +41,8 @@ echo "Running integration test in fsim..." python3 -m pytest -v vta/tests/python/integration # Build VTA chisel design and verilator simulator -make -C vta/hardware/chisel/ USE_THREADS=4 lib +make -C vta/hardware/chisel cleanall +make -C vta/hardware/chisel USE_THREADS=0 lib # Set default VTA config to use TSIM cycle accurate sim cp vta/config/tsim_sample.json vta/config/vta_config.json From e9e22e469b41e6ccd4ed27c7d94ea5280fd34b8d Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Wed, 15 Jan 2020 15:29:53 +0800 Subject: [PATCH 11/24] bug fix in LoadUop module --- vta/hardware/chisel/src/main/scala/core/LoadUop.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala index 735b2b78feb5..90c309bc31ab 100644 --- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala +++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala @@ -77,7 +77,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { val xcnt = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len)) val xlen = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len)) val xrem = Reg(chiselTypeOf(dec.xsize)) - val xsize = (dec.xsize >> log2Ceil(numUop)) + dec.xsize(0) + (dec.sram_offset % 2.U) - 1.U + val xsize = (dec.xsize >> log2Ceil(numUop)) + dec.xsize(0) - 1.U val xmax = (1 << mp.lenBits).U val xmax_bytes = ((1 << mp.lenBits) * mp.dataBits / 8).U From 0000e27707649c48a9ab893467a6cb77a5be195a Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Wed, 15 Jan 2020 18:33:37 +0800 Subject: [PATCH 12/24] log mega cycles in tsim --- vta/hardware/dpi/tsim_device.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/vta/hardware/dpi/tsim_device.cc b/vta/hardware/dpi/tsim_device.cc index 1dae2738c984..d197fbd4385e 100644 --- a/vta/hardware/dpi/tsim_device.cc +++ b/vta/hardware/dpi/tsim_device.cc @@ -141,6 +141,8 @@ int VTADPISim() { tfp->dump(static_cast(trace_count * 2 + 1)); #endif trace_count++; + if ((trace_count % 1000000) == 1) + fprintf(stderr, "[traced %dM cycles]\n", trace_count / 1000000); while (top->sim_wait) { top->clock = 0; std::this_thread::sleep_for(std::chrono::milliseconds(100)); From 713e9c93e89295a6e0a4f31364540dc6ea316945 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 16 Jan 2020 10:26:37 +0800 Subject: [PATCH 13/24] download cat.png to avoid fetching in each run --- vta/tutorials/frontend/deploy_vision_on_vta.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/vta/tutorials/frontend/deploy_vision_on_vta.py b/vta/tutorials/frontend/deploy_vision_on_vta.py index 47773bda5ec7..154eb85ed9a5 100644 --- a/vta/tutorials/frontend/deploy_vision_on_vta.py +++ b/vta/tutorials/frontend/deploy_vision_on_vta.py @@ -225,10 +225,11 @@ # Download test image image_url = 'https://homes.cs.washington.edu/~moreau/media/vta/cat.jpg' -response = requests.get(image_url) +image_fn = 'cat.png' +download.download(image_url, image_fn) # Prepare test image for inference -image = Image.open(BytesIO(response.content)).resize((224, 224)) +image = Image.open(image_fn).resize((224, 224)) plt.imshow(image) plt.show() image = np.array(image) - np.array([123., 117., 104.]) From 0fda8c2bece62ca2d87e3f5974154b29c6e5b23e Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 16 Jan 2020 13:13:07 +0800 Subject: [PATCH 14/24] bug fix in LoadUop module --- vta/hardware/chisel/src/main/scala/core/LoadUop.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala index 90c309bc31ab..4798fc6edafb 100644 --- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala +++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala @@ -132,7 +132,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { when((dec.dram_offset % 2.U) === 0.U) { raddr := io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes))) }.otherwise { - raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes)))) + uopBytes.U + raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes)))) - uopBytes.U } }.elsewhen(state === sReadData && xcnt === xlen && xrem =/= 0.U) { raddr := raddr + xmax_bytes From aea604604130675c8ba2fc9a41678aa943027c37 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 16 Jan 2020 15:44:52 +0800 Subject: [PATCH 15/24] solve dram_even/sram_even issue --- .../chisel/src/main/scala/core/LoadUop.scala | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala index 4798fc6edafb..095990fc61b3 100644 --- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala +++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala @@ -81,7 +81,8 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { val xmax = (1 << mp.lenBits).U val xmax_bytes = ((1 << mp.lenBits) * mp.dataBits / 8).U - val offsetIsEven = (dec.sram_offset % 2.U) === 0.U + val dram_even = (dec.dram_offset % 2.U) === 0.U + val sram_even = (dec.sram_offset % 2.U) === 0.U val sizeIsEven = (dec.xsize % 2.U) === 0.U val sIdle :: sReadCmd :: sReadData :: Nil = Enum(3) @@ -129,7 +130,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { // read-from-dram val maskOffset = VecInit(Seq.fill(M_DRAM_OFFSET_BITS)(true.B)).asUInt when(state === sIdle) { - when((dec.dram_offset % 2.U) === 0.U) { + when(dram_even) { raddr := io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes))) }.otherwise { raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes)))) - uopBytes.U @@ -161,7 +162,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { val mem = SyncReadMem(uopDepth, chiselTypeOf(wdata)) val wmask = Reg(Vec(numUop, Bool())) - when(offsetIsEven) { + when(sram_even) { when(sizeIsEven) { wmask := "b_11".U.asTypeOf(wmask) }.elsewhen(io.vme_rd.cmd.fire()) { @@ -179,10 +180,13 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { } } }.otherwise { - when(io.vme_rd.cmd.fire()) { + when(sizeIsEven) { + // TODO (liangfu): write the other word + wmask := "b_01".U.asTypeOf(wmask) + }.elsewhen(io.vme_rd.cmd.fire()) { wmask := "b_10".U.asTypeOf(wmask) }.elsewhen(io.vme_rd.data.fire()) { - when(sizeIsEven && (xcnt === xlen - 1.U) && (xrem === 0.U)) { + when((xcnt === xlen - 1.U) && (xrem === 0.U)) { wmask := "b_01".U.asTypeOf(wmask) }.otherwise { wmask := "b_11".U.asTypeOf(wmask) @@ -191,6 +195,12 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { } wdata := io.vme_rd.data.bits.asTypeOf(wdata) + when(dram_even === false.B && sram_even) { + wdata(0) := io.vme_rd.data.bits.asTypeOf(wdata)(1) + }.elsewhen(sram_even === false.B && dram_even) { + wdata(1) := io.vme_rd.data.bits.asTypeOf(wdata)(0) + } + when(io.vme_rd.data.fire()) { mem.write(waddr, wdata, wmask) } From 0317a6d412ebf3c84946640198c37feb9a21f1b1 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 16 Jan 2020 16:49:01 +0800 Subject: [PATCH 16/24] bug fix --- vta/hardware/chisel/src/main/scala/core/LoadUop.scala | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala index 095990fc61b3..1f7a61dc15b1 100644 --- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala +++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala @@ -180,13 +180,10 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { } } }.otherwise { - when(sizeIsEven) { - // TODO (liangfu): write the other word - wmask := "b_01".U.asTypeOf(wmask) - }.elsewhen(io.vme_rd.cmd.fire()) { + when(io.vme_rd.cmd.fire()) { wmask := "b_10".U.asTypeOf(wmask) }.elsewhen(io.vme_rd.data.fire()) { - when((xcnt === xlen - 1.U) && (xrem === 0.U)) { + when(sizeIsEven && (xcnt === xlen - 1.U) && (xrem === 0.U)) { wmask := "b_01".U.asTypeOf(wmask) }.otherwise { wmask := "b_11".U.asTypeOf(wmask) From de109fef98924dba0aa8e589e04f2f89c4bfeefe Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 16 Jan 2020 17:17:21 +0800 Subject: [PATCH 17/24] introduce scalalint in ci --- Makefile | 7 +++++-- tests/scripts/task_lint.sh | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index d34fbe4c9d88..566cdf071d3b 100644 --- a/Makefile +++ b/Makefile @@ -17,7 +17,7 @@ ROOTDIR = $(CURDIR) -.PHONY: clean all test doc pylint cpplint lint\ +.PHONY: clean all test doc pylint cpplint scalalint lint\ cython cython2 cython3 web runtime vta ifndef DMLC_CORE_PATH @@ -80,7 +80,10 @@ pylint: jnilint: python3 3rdparty/dmlc-core/scripts/lint.py tvm4j-jni cpp jvm/native/src -lint: cpplint pylint jnilint +scalalint: + cd vta/hardware/chisel && make lint && cd ../../.. + +lint: cpplint pylint jnilint scalalint doc: doxygen docs/Doxyfile diff --git a/tests/scripts/task_lint.sh b/tests/scripts/task_lint.sh index 544ef7224770..33f3165f9e7b 100755 --- a/tests/scripts/task_lint.sh +++ b/tests/scripts/task_lint.sh @@ -50,6 +50,8 @@ echo "Check codestyle of python code..." make pylint echo "Check codestyle of jni code..." make jnilint +echo "Check codestyle of scala code..." +make scalalint echo "Check documentations of c++ code..." make doc 2>/tmp/$$.log.txt From 05f798c148d0284aca5ffbeb8867082789bbf291 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 16 Jan 2020 17:19:41 +0800 Subject: [PATCH 18/24] speedup tsim in ci --- Makefile | 2 +- tests/scripts/task_python_vta.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 566cdf071d3b..ad24baaa1485 100644 --- a/Makefile +++ b/Makefile @@ -81,7 +81,7 @@ jnilint: python3 3rdparty/dmlc-core/scripts/lint.py tvm4j-jni cpp jvm/native/src scalalint: - cd vta/hardware/chisel && make lint && cd ../../.. + make -C vta/hardware/chisel lint lint: cpplint pylint jnilint scalalint diff --git a/tests/scripts/task_python_vta.sh b/tests/scripts/task_python_vta.sh index 52dd641cbd22..20c4e6c3f6b6 100755 --- a/tests/scripts/task_python_vta.sh +++ b/tests/scripts/task_python_vta.sh @@ -42,7 +42,7 @@ python3 -m pytest -v vta/tests/python/integration # Build VTA chisel design and verilator simulator make -C vta/hardware/chisel cleanall -make -C vta/hardware/chisel USE_THREADS=0 lib +make -C vta/hardware/chisel lib # Set default VTA config to use TSIM cycle accurate sim cp vta/config/tsim_sample.json vta/config/vta_config.json From ca0aa2cba4ad04fbf67d8c13afb6ca752864cc3f Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 16 Jan 2020 17:31:38 +0800 Subject: [PATCH 19/24] bug fix --- vta/hardware/chisel/src/main/scala/core/LoadUop.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala index 1f7a61dc15b1..c7d0f4439858 100644 --- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala +++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala @@ -77,7 +77,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { val xcnt = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len)) val xlen = Reg(chiselTypeOf(io.vme_rd.cmd.bits.len)) val xrem = Reg(chiselTypeOf(dec.xsize)) - val xsize = (dec.xsize >> log2Ceil(numUop)) + dec.xsize(0) - 1.U + val xsize = (dec.xsize >> log2Ceil(numUop)) + dec.xsize(0) + (dec.sram_offset % 2.U) - 1.U val xmax = (1 << mp.lenBits).U val xmax_bytes = ((1 << mp.lenBits) * mp.dataBits / 8).U From 8b1b12fd40ad6cfd7a070441b78ef826f168222a Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 16 Jan 2020 17:44:17 +0800 Subject: [PATCH 20/24] lint scala code before building --- tests/scripts/task_lint.sh | 2 -- tests/scripts/task_python_vta.sh | 5 +++++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/tests/scripts/task_lint.sh b/tests/scripts/task_lint.sh index 33f3165f9e7b..544ef7224770 100755 --- a/tests/scripts/task_lint.sh +++ b/tests/scripts/task_lint.sh @@ -50,8 +50,6 @@ echo "Check codestyle of python code..." make pylint echo "Check codestyle of jni code..." make jnilint -echo "Check codestyle of scala code..." -make scalalint echo "Check documentations of c++ code..." make doc 2>/tmp/$$.log.txt diff --git a/tests/scripts/task_python_vta.sh b/tests/scripts/task_python_vta.sh index 20c4e6c3f6b6..a7d079320e35 100755 --- a/tests/scripts/task_python_vta.sh +++ b/tests/scripts/task_python_vta.sh @@ -40,7 +40,12 @@ python3 -m pytest -v vta/tests/python/unittest echo "Running integration test in fsim..." python3 -m pytest -v vta/tests/python/integration +# Check style of scala code +echo "Check style of scala code..." +make -C vta/hardware/chisel lint + # Build VTA chisel design and verilator simulator +echo "Building VTA chisel design..." make -C vta/hardware/chisel cleanall make -C vta/hardware/chisel lib From 444fd2f3f4e6267953324851259f9ad56653e007 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 16 Jan 2020 18:36:27 +0800 Subject: [PATCH 21/24] disable multi-threading --- tests/scripts/task_python_vta.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/scripts/task_python_vta.sh b/tests/scripts/task_python_vta.sh index a7d079320e35..10c16113a1f5 100755 --- a/tests/scripts/task_python_vta.sh +++ b/tests/scripts/task_python_vta.sh @@ -47,7 +47,7 @@ make -C vta/hardware/chisel lint # Build VTA chisel design and verilator simulator echo "Building VTA chisel design..." make -C vta/hardware/chisel cleanall -make -C vta/hardware/chisel lib +make -C vta/hardware/chisel USE_THREADS=0 lib # Set default VTA config to use TSIM cycle accurate sim cp vta/config/tsim_sample.json vta/config/vta_config.json From 0ec9d8109ac6ec436f54d815f6a6a1c97f28c477 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Fri, 17 Jan 2020 10:05:54 +0800 Subject: [PATCH 22/24] split fsim/tsim script --- tests/scripts/task_python_vta_fsim.sh | 41 +++++++++++++++++++ ..._python_vta.sh => task_python_vta_tsim.sh} | 15 +------ 2 files changed, 43 insertions(+), 13 deletions(-) create mode 100755 tests/scripts/task_python_vta_fsim.sh rename tests/scripts/{task_python_vta.sh => task_python_vta_tsim.sh} (82%) diff --git a/tests/scripts/task_python_vta_fsim.sh b/tests/scripts/task_python_vta_fsim.sh new file mode 100755 index 000000000000..a6bfb1c24d01 --- /dev/null +++ b/tests/scripts/task_python_vta_fsim.sh @@ -0,0 +1,41 @@ +#!/bin/bash +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. + +set -e +set -u + +export PYTHONPATH=python:vta/python:topi/python + +# cleanup pycache +find . -type f -path "*.pyc" | xargs rm -f + +rm -rf ~/.tvm + +# Rebuild cython +make cython3 + +# Reset default fsim simulation +cp vta/config/fsim_sample.json vta/config/vta_config.json + +# Run unit tests in functional/fast simulator +echo "Running unittest in fsim..." +python3 -m pytest -v vta/tests/python/unittest + +# Run unit tests in functional/fast simulator +echo "Running integration test in fsim..." +python3 -m pytest -v vta/tests/python/integration diff --git a/tests/scripts/task_python_vta.sh b/tests/scripts/task_python_vta_tsim.sh similarity index 82% rename from tests/scripts/task_python_vta.sh rename to tests/scripts/task_python_vta_tsim.sh index 10c16113a1f5..eba62e537a85 100755 --- a/tests/scripts/task_python_vta.sh +++ b/tests/scripts/task_python_vta_tsim.sh @@ -29,16 +29,8 @@ rm -rf ~/.tvm # Rebuild cython make cython3 -# Reset default fsim simulation -cp vta/config/fsim_sample.json vta/config/vta_config.json - -# Run unit tests in functional/fast simulator -echo "Running unittest in fsim..." -python3 -m pytest -v vta/tests/python/unittest - -# Run unit tests in functional/fast simulator -echo "Running integration test in fsim..." -python3 -m pytest -v vta/tests/python/integration +# Set default VTA config to use TSIM cycle accurate sim +cp vta/config/tsim_sample.json vta/config/vta_config.json # Check style of scala code echo "Check style of scala code..." @@ -49,9 +41,6 @@ echo "Building VTA chisel design..." make -C vta/hardware/chisel cleanall make -C vta/hardware/chisel USE_THREADS=0 lib -# Set default VTA config to use TSIM cycle accurate sim -cp vta/config/tsim_sample.json vta/config/vta_config.json - # Run unit tests in cycle accurate simulator echo "Running unittest in tsim..." python3 -m pytest -v vta/tests/python/unittest From 28be2287323217703237ec7be18373b217ff945c Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Fri, 17 Jan 2020 10:42:19 +0800 Subject: [PATCH 23/24] update Jenkins settings --- Jenkinsfile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index f974fdcb0246..6b92f969142c 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -217,7 +217,8 @@ stage('Build') { timeout(time: max_time, unit: 'MINUTES') { sh "${docker_run} ${ci_cpu} ./tests/scripts/task_python_unittest.sh" sh "${docker_run} ${ci_cpu} ./tests/scripts/task_python_integration.sh" - sh "${docker_run} ${ci_cpu} ./tests/scripts/task_python_vta.sh" + sh "${docker_run} ${ci_cpu} ./tests/scripts/task_python_vta_fsim.sh" + sh "${docker_run} ${ci_cpu} ./tests/scripts/task_python_vta_tsim.sh" sh "${docker_run} ${ci_cpu} ./tests/scripts/task_golang.sh" } } @@ -269,7 +270,7 @@ stage('Unit Test') { timeout(time: max_time, unit: 'MINUTES') { sh "${docker_run} ${ci_i386} ./tests/scripts/task_python_unittest.sh" sh "${docker_run} ${ci_i386} ./tests/scripts/task_python_integration.sh" - sh "${docker_run} ${ci_i386} ./tests/scripts/task_python_vta.sh" + sh "${docker_run} ${ci_i386} ./tests/scripts/task_python_vta_fsim.sh" } } } From 1d858835ef411bc7c936495b539db5f26080fc0d Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Fri, 17 Jan 2020 19:44:49 +0800 Subject: [PATCH 24/24] duplicate task_python_vta_fsim.sh as task_python_vta.sh for now --- tests/scripts/task_python_vta.sh | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100755 tests/scripts/task_python_vta.sh diff --git a/tests/scripts/task_python_vta.sh b/tests/scripts/task_python_vta.sh new file mode 100755 index 000000000000..a6bfb1c24d01 --- /dev/null +++ b/tests/scripts/task_python_vta.sh @@ -0,0 +1,41 @@ +#!/bin/bash +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. + +set -e +set -u + +export PYTHONPATH=python:vta/python:topi/python + +# cleanup pycache +find . -type f -path "*.pyc" | xargs rm -f + +rm -rf ~/.tvm + +# Rebuild cython +make cython3 + +# Reset default fsim simulation +cp vta/config/fsim_sample.json vta/config/vta_config.json + +# Run unit tests in functional/fast simulator +echo "Running unittest in fsim..." +python3 -m pytest -v vta/tests/python/unittest + +# Run unit tests in functional/fast simulator +echo "Running integration test in fsim..." +python3 -m pytest -v vta/tests/python/integration