From e390eb7ef70b2c419cf2c0cde6fd91c863957bae Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Mon, 23 Dec 2019 18:55:53 +0800 Subject: [PATCH 1/2] [VTA][Chisel] End-to-end Inference with Chisel VTA --- vta/hardware/chisel/src/main/scala/core/TensorAlu.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala index b438641d2938..428c5d3cadbe 100644 --- a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala +++ b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala @@ -230,7 +230,7 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module { tensorImm.data.valid := state === sReadTensorB tensorImm.data.bits.foreach { b => b.foreach { c => - c := dec.alu_imm + c := Mux(dec.alu_imm(C_ALU_IMM_BITS - 1), Cat(-1.S((aluBits - C_ALU_IMM_BITS).W), dec.alu_imm), dec.alu_imm) } } From 439cbb1df41b0e6b7218ee5ca27da0c5c77507c1 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Mon, 23 Dec 2019 19:01:23 +0800 Subject: [PATCH 2/2] Update TensorAlu.scala --- vta/hardware/chisel/src/main/scala/core/TensorAlu.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala index 428c5d3cadbe..6f1a804d8726 100644 --- a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala +++ b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala @@ -230,7 +230,8 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module { tensorImm.data.valid := state === sReadTensorB tensorImm.data.bits.foreach { b => b.foreach { c => - c := Mux(dec.alu_imm(C_ALU_IMM_BITS - 1), Cat(-1.S((aluBits - C_ALU_IMM_BITS).W), dec.alu_imm), dec.alu_imm) + c := Mux(dec.alu_imm(C_ALU_IMM_BITS - 1), + Cat(-1.S((aluBits - C_ALU_IMM_BITS).W), dec.alu_imm), dec.alu_imm) } }