From 0d31cdd16da964f3a20f53d766b9b3a68106f15e Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Tue, 23 Jun 2020 05:49:52 +0000 Subject: [PATCH 1/4] [BACKPORT-0.6][VTA][Chisel] End-to-end Inference with Chisel VTA (#4574) --- vta/hardware/chisel/src/main/scala/core/TensorAlu.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala index b438641d2938..6f1a804d8726 100644 --- a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala +++ b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala @@ -230,7 +230,8 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module { tensorImm.data.valid := state === sReadTensorB tensorImm.data.bits.foreach { b => b.foreach { c => - c := dec.alu_imm + c := Mux(dec.alu_imm(C_ALU_IMM_BITS - 1), + Cat(-1.S((aluBits - C_ALU_IMM_BITS).W), dec.alu_imm), dec.alu_imm) } } From ac418811abad5ddafde742a5b979468f2b618022 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Tue, 23 Jun 2020 05:51:26 +0000 Subject: [PATCH 2/4] [BACKPORT-0.6][VTA] Added declare of aluBits for TensorAlu (#4624) Co-authored-by: Kevin Yuan --- vta/hardware/chisel/src/main/scala/core/TensorAlu.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala index 6f1a804d8726..21e57f2dab94 100644 --- a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala +++ b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala @@ -108,6 +108,7 @@ class AluVector(implicit p: Parameters) extends Module { * acc-scratchpad. */ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module { + val aluBits = p(CoreKey).accBits val io = IO(new Bundle { val start = Input(Bool()) val done = Output(Bool()) From 4615bccebc0d3b14f5b4bf3bf774408fcfaae0d1 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 25 Jun 2020 01:33:44 +0000 Subject: [PATCH 3/4] retrigger ci --- vta/hardware/chisel/src/main/scala/core/TensorAlu.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala index 21e57f2dab94..24d5d6bcc62f 100644 --- a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala +++ b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala @@ -7,7 +7,7 @@ * "License"); you may not use this file except in compliance * with the License. You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, * software distributed under the License is distributed on an From 252cef546d947cdd98c992610a7c044bd0d1d424 Mon Sep 17 00:00:00 2001 From: Liangfu Chen Date: Thu, 25 Jun 2020 01:34:34 +0000 Subject: [PATCH 4/4] retrigger ci --- vta/hardware/chisel/src/main/scala/core/TensorAlu.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala index 24d5d6bcc62f..21e57f2dab94 100644 --- a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala +++ b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala @@ -7,7 +7,7 @@ * "License"); you may not use this file except in compliance * with the License. You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, * software distributed under the License is distributed on an