diff --git a/cranelift/codegen/src/isa/riscv64/inst/args.rs b/cranelift/codegen/src/isa/riscv64/inst/args.rs
index 08791062ad26..e7d698cb15db 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/args.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/args.rs
@@ -35,6 +35,9 @@ pub enum AMode {
     /// clobber pushes. See the diagram in the documentation for
     /// [crate::isa::riscv64::abi](the ABI module) for more details.
     NominalSPOffset(i64, Type),
+
+    /// Emits a relocation that resolves to the appropriate location
+    Label(MachLabel),
 }
 
 impl AMode {
@@ -42,48 +45,42 @@ impl AMode {
         AMode::RegOffset(reg, imm, ty)
     }
 
-    pub(crate) fn get_base_register(&self) -> Reg {
+    pub(crate) fn get_base_register(&self) -> Option<Reg> {
         match self {
-            &AMode::RegOffset(reg, ..) => reg,
-            &AMode::SPOffset(..) => stack_reg(),
-            &AMode::FPOffset(..) => fp_reg(),
-            &AMode::NominalSPOffset(..) => stack_reg(),
+            &AMode::RegOffset(reg, ..) => Some(reg),
+            &AMode::SPOffset(..) => Some(stack_reg()),
+            &AMode::FPOffset(..) => Some(fp_reg()),
+            &AMode::NominalSPOffset(..) => Some(stack_reg()),
+            &AMode::Label(_) => None,
         }
     }
 
-    pub(crate) fn get_offset_with_state(&self, state: &EmitState) -> i64 {
+    pub(crate) fn get_offset_with_state(&self, state: &EmitState) -> Option<i64> {
         match self {
-            &AMode::NominalSPOffset(offset, _) => offset + state.virtual_sp_offset,
+            &AMode::NominalSPOffset(offset, _) => Some(offset + state.virtual_sp_offset),
             _ => self.get_offset(),
         }
     }
 
-    fn get_offset(&self) -> i64 {
+    pub(crate) fn get_offset(&self) -> Option<i64> {
         match self {
-            &AMode::RegOffset(_, offset, ..) => offset,
-            &AMode::SPOffset(offset, _) => offset,
-            &AMode::FPOffset(offset, _) => offset,
-            &AMode::NominalSPOffset(offset, _) => offset,
+            &AMode::RegOffset(_, offset, ..) => Some(offset),
+            &AMode::SPOffset(offset, _) => Some(offset),
+            &AMode::FPOffset(offset, _) => Some(offset),
+            &AMode::NominalSPOffset(offset, _) => Some(offset),
+            &AMode::Label(_) => None,
         }
     }
 
     pub(crate) fn to_string_with_alloc(&self, allocs: &mut AllocationConsumer<'_>) -> String {
-        let reg = self.get_base_register();
-        let next = allocs.next(reg);
-        let offset = self.get_offset();
         match self {
+            &AMode::Label(l) => format!(".L{}", l.as_u32()),
             &AMode::NominalSPOffset(..) => format!("{}", self),
-            _ => format!("{}({})", offset, reg_name(next),),
-        }
-    }
-
-    pub(crate) fn to_addr(&self, allocs: &mut AllocationConsumer<'_>) -> String {
-        let reg = self.get_base_register();
-        let next = allocs.next(reg);
-        let offset = self.get_offset();
-        match self {
-            &AMode::NominalSPOffset(..) => format!("nsp{:+}", offset),
-            _ => format!("{}{:+}", reg_name(next), offset),
+            _ => {
+                let reg = self.get_base_register().unwrap();
+                let next = allocs.next(reg);
+                format!("{}({})", self.get_offset().unwrap(), reg_name(next),)
+            }
         }
     }
 }
@@ -103,6 +100,9 @@ impl Display for AMode {
             &AMode::FPOffset(offset, ..) => {
                 write!(f, "{}(fp)", offset)
             }
+            &AMode::Label(label) => {
+                write!(f, ".L{}", label.as_u32())
+            }
         }
     }
 }
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
index 36bdc2aa7018..217858d7d68c 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -25,75 +25,6 @@ impl EmitInfo {
     }
 }
 
-/// load constant by put the constant in the code stream.
-/// calculate the pc and using load instruction.
-#[derive(Clone, Copy)]
-pub(crate) enum LoadConstant {
-    U32(u32),
-    U64(u64),
-}
-
-impl LoadConstant {
-    fn to_le_bytes(self) -> Vec<u8> {
-        match self {
-            LoadConstant::U32(x) => Vec::from_iter(x.to_le_bytes().into_iter()),
-            LoadConstant::U64(x) => Vec::from_iter(x.to_le_bytes().into_iter()),
-        }
-    }
-    fn load_op(self) -> LoadOP {
-        match self {
-            LoadConstant::U32(_) => LoadOP::Lwu,
-            LoadConstant::U64(_) => LoadOP::Ld,
-        }
-    }
-    fn load_ty(self) -> Type {
-        match self {
-            LoadConstant::U32(_) => R32,
-            LoadConstant::U64(_) => R64,
-        }
-    }
-
-    pub(crate) fn load_constant<F: FnMut(Type) -> Writable<Reg>>(
-        self,
-        rd: Writable<Reg>,
-        alloc_tmp: &mut F,
-    ) -> SmallInstVec<Inst> {
-        let mut insts = SmallInstVec::new();
-        // get current pc.
-        let pc = alloc_tmp(I64);
-        insts.push(Inst::Auipc {
-            rd: pc,
-            imm: Imm20 { bits: 0 },
-        });
-        // load
-        insts.push(Inst::Load {
-            rd,
-            op: self.load_op(),
-            flags: MemFlags::new(),
-            from: AMode::RegOffset(pc.to_reg(), 12, self.load_ty()),
-        });
-        let data = self.to_le_bytes();
-        // jump over.
-        insts.push(Inst::Jal {
-            dest: BranchTarget::ResolvedOffset(Inst::INSTRUCTION_SIZE + data.len() as i32),
-        });
-        insts.push(Inst::RawData { data });
-        insts
-    }
-
-    // load and perform an extra add.
-    pub(crate) fn load_constant_and_add(self, rd: Writable<Reg>, rs: Reg) -> SmallInstVec<Inst> {
-        let mut insts = self.load_constant(rd, &mut |_| rd);
-        insts.push(Inst::AluRRR {
-            alu_op: AluOPRRR::Add,
-            rd,
-            rs1: rd.to_reg(),
-            rs2: rs,
-        });
-        insts
-    }
-}
-
 pub(crate) fn reg_to_gpr_num(m: Reg) -> u32 {
     u32::try_from(m.to_real_reg().unwrap().hw_enc() & 31).unwrap()
 }
@@ -480,17 +411,35 @@ impl MachInstEmit for Inst {
             }
             &Inst::LoadConst32 { rd, imm } => {
                 let rd = allocs.next_writable(rd);
-                LoadConstant::U32(imm)
-                    .load_constant(rd, &mut |_| rd)
-                    .into_iter()
-                    .for_each(|inst| inst.emit(&[], sink, emit_info, state));
+                let label_data = sink.get_label();
+                let data = imm.to_le_bytes();
+
+                // Emit the constant into the pool
+                sink.defer_constant(label_data, 4, &data[..], u32::MAX);
+
+                let inst = Inst::Load {
+                    rd,
+                    op: LoadOP::Lw,
+                    flags: MemFlags::trusted(),
+                    from: AMode::Label(label_data),
+                };
+                inst.emit(&[], sink, emit_info, state);
             }
             &Inst::LoadConst64 { rd, imm } => {
                 let rd = allocs.next_writable(rd);
-                LoadConstant::U64(imm)
-                    .load_constant(rd, &mut |_| rd)
-                    .into_iter()
-                    .for_each(|inst| inst.emit(&[], sink, emit_info, state));
+                let label_data = sink.get_label();
+                let data = imm.to_le_bytes();
+
+                // Emit the constant into the pool
+                sink.defer_constant(label_data, 8, &data[..], u32::MAX);
+
+                let inst = Inst::Load {
+                    rd,
+                    op: LoadOP::Ld,
+                    flags: MemFlags::trusted(),
+                    from: AMode::Label(label_data),
+                };
+                inst.emit(&[], sink, emit_info, state);
             }
             &Inst::FpuRR {
                 frm,
@@ -603,80 +552,118 @@ impl MachInstEmit for Inst {
                 from,
                 flags,
             } => {
-                let x;
-                let base = from.get_base_register();
-                let base = allocs.next(base);
                 let rd = allocs.next_writable(rd);
-                let offset = from.get_offset_with_state(state);
-                if let Some(imm12) = Imm12::maybe_from_u64(offset as u64) {
-                    let srcloc = state.cur_srcloc();
-                    if !srcloc.is_default() && !flags.notrap() {
-                        // Register the offset at which the actual load instruction starts.
-                        sink.add_trap(TrapCode::HeapOutOfBounds);
+
+                match from {
+                    AMode::Label(target) => {
+                        // Get the current PC.
+                        sink.use_label_at_offset(sink.cur_offset(), target, LabelUse::PCRelHi20);
+                        let inst = Inst::Auipc {
+                            rd,
+                            imm: Imm20::from_bits(0),
+                        };
+                        inst.emit(&[], sink, emit_info, state);
+
+                        // Emit the actual load with a zero offset.
+                        // This later gets patched up
+                        sink.use_label_at_offset(sink.cur_offset(), target, LabelUse::PCRelLo12I);
+                        let inst = Inst::Load {
+                            rd,
+                            op,
+                            flags,
+                            from: AMode::RegOffset(rd.to_reg(), 0, I64),
+                        };
+                        inst.emit(&[], sink, emit_info, state);
                     }
-                    x = op.op_code()
-                        | reg_to_gpr_num(rd.to_reg()) << 7
-                        | op.funct3() << 12
-                        | reg_to_gpr_num(base) << 15
-                        | (imm12.as_u32()) << 20;
-                    sink.put4(x);
-                } else {
-                    let tmp = writable_spilltmp_reg();
-                    let mut insts =
-                        LoadConstant::U64(offset as u64).load_constant_and_add(tmp, base);
-                    let srcloc = state.cur_srcloc();
-                    if !srcloc.is_default() && !flags.notrap() {
-                        // Register the offset at which the actual load instruction starts.
-                        sink.add_trap(TrapCode::HeapOutOfBounds);
+                    from => {
+                        let base = allocs.next(from.get_base_register().unwrap());
+                        let offset = from.get_offset_with_state(state).unwrap();
+                        if let Some(imm12) = Imm12::maybe_from_u64(offset as u64) {
+                            let srcloc = state.cur_srcloc();
+                            if !srcloc.is_default() && !flags.notrap() {
+                                // Register the offset at which the actual load instruction starts.
+                                sink.add_trap(TrapCode::HeapOutOfBounds);
+                            }
+                            let inst = op.op_code()
+                                | reg_to_gpr_num(rd.to_reg()) << 7
+                                | op.funct3() << 12
+                                | reg_to_gpr_num(base) << 15
+                                | (imm12.as_u32()) << 20;
+                            sink.put4(inst);
+                        } else {
+                            let tmp = writable_spilltmp_reg();
+                            let mut insts = Inst::load_constant_and_add_u64(
+                                tmp,
+                                base,
+                                offset as u64,
+                                &mut |_| tmp,
+                            );
+                            let srcloc = state.cur_srcloc();
+                            if !srcloc.is_default() && !flags.notrap() {
+                                // Register the offset at which the actual load instruction starts.
+                                sink.add_trap(TrapCode::HeapOutOfBounds);
+                            }
+                            insts.push(Inst::Load {
+                                op,
+                                from: AMode::RegOffset(tmp.to_reg(), 0, I64),
+                                rd,
+                                flags,
+                            });
+                            insts
+                                .into_iter()
+                                .for_each(|inst| inst.emit(&[], sink, emit_info, state));
+                        }
                     }
-                    insts.push(Inst::Load {
-                        op,
-                        from: AMode::RegOffset(tmp.to_reg(), 0, I64),
-                        rd,
-                        flags,
-                    });
-                    insts
-                        .into_iter()
-                        .for_each(|inst| inst.emit(&[], sink, emit_info, state));
-                }
+                };
             }
             &Inst::Store { op, src, flags, to } => {
-                let base = allocs.next(to.get_base_register());
                 let src = allocs.next(src);
-                let offset = to.get_offset_with_state(state);
-                let x;
-                if let Some(imm12) = Imm12::maybe_from_u64(offset as u64) {
-                    let srcloc = state.cur_srcloc();
-                    if !srcloc.is_default() && !flags.notrap() {
-                        // Register the offset at which the actual load instruction starts.
-                        sink.add_trap(TrapCode::HeapOutOfBounds);
+
+                match to {
+                    AMode::Label(_target) => {
+                        unimplemented!("Store with label target is unimplemented!")
                     }
-                    x = op.op_code()
-                        | (imm12.as_u32() & 0x1f) << 7
-                        | op.funct3() << 12
-                        | reg_to_gpr_num(base) << 15
-                        | reg_to_gpr_num(src) << 20
-                        | (imm12.as_u32() >> 5) << 25;
-                    sink.put4(x);
-                } else {
-                    let tmp = writable_spilltmp_reg();
-                    let mut insts =
-                        LoadConstant::U64(offset as u64).load_constant_and_add(tmp, base);
-                    let srcloc = state.cur_srcloc();
-                    if !srcloc.is_default() && !flags.notrap() {
-                        // Register the offset at which the actual load instruction starts.
-                        sink.add_trap(TrapCode::HeapOutOfBounds);
+                    to => {
+                        let base = allocs.next(to.get_base_register().unwrap());
+                        let offset = to.get_offset_with_state(state).unwrap();
+                        if let Some(imm12) = Imm12::maybe_from_u64(offset as u64) {
+                            let srcloc = state.cur_srcloc();
+                            if !srcloc.is_default() && !flags.notrap() {
+                                // Register the offset at which the actual load instruction starts.
+                                sink.add_trap(TrapCode::HeapOutOfBounds);
+                            }
+                            let inst = op.op_code()
+                                | (imm12.as_u32() & 0x1f) << 7
+                                | op.funct3() << 12
+                                | reg_to_gpr_num(base) << 15
+                                | reg_to_gpr_num(src) << 20
+                                | (imm12.as_u32() >> 5) << 25;
+                            sink.put4(inst);
+                        } else {
+                            let tmp = writable_spilltmp_reg();
+                            let mut insts = Inst::load_constant_and_add_u64(
+                                tmp,
+                                base,
+                                offset as u64,
+                                &mut |_| tmp,
+                            );
+                            let srcloc = state.cur_srcloc();
+                            if !srcloc.is_default() && !flags.notrap() {
+                                // Register the offset at which the actual load instruction starts.
+                                sink.add_trap(TrapCode::HeapOutOfBounds);
+                            }
+                            insts.push(Inst::Store {
+                                op,
+                                to: AMode::RegOffset(tmp.to_reg(), 0, I64),
+                                flags,
+                                src,
+                            });
+                            insts
+                                .into_iter()
+                                .for_each(|inst| inst.emit(&[], sink, emit_info, state));
+                        }
                     }
-                    insts.push(Inst::Store {
-                        op,
-                        to: AMode::RegOffset(tmp.to_reg(), 0, I64),
-                        flags,
-                        src,
-                    });
-                    insts
-                        .into_iter()
-                        .for_each(|inst| inst.emit(&[], sink, emit_info, state));
-                }
+                };
             }
 
             &Inst::ReferenceCheck { rd, op, x } => {
@@ -1160,23 +1147,35 @@ impl MachInstEmit for Inst {
             }
 
             &Inst::LoadAddr { rd, mem } => {
-                let base = mem.get_base_register();
-                let base = allocs.next(base);
                 let rd = allocs.next_writable(rd);
-                let offset = mem.get_offset_with_state(state);
-                if let Some(offset) = Imm12::maybe_from_u64(offset as u64) {
-                    Inst::AluRRImm12 {
-                        alu_op: AluOPRRI::Addi,
-                        rd,
-                        rs: base,
-                        imm12: offset,
+
+                match mem {
+                    AMode::Label(_target) => {
+                        unimplemented!("LoadAddr with label target is unimplemented!")
+                    }
+                    mem => {
+                        let base = allocs.next(mem.get_base_register().unwrap());
+                        let offset = mem.get_offset_with_state(state).unwrap();
+                        if let Some(offset) = Imm12::maybe_from_u64(offset as u64) {
+                            Inst::AluRRImm12 {
+                                alu_op: AluOPRRI::Addi,
+                                rd,
+                                rs: base,
+                                imm12: offset,
+                            }
+                            .emit(&[], sink, emit_info, state);
+                        } else {
+                            let insts = Inst::load_constant_and_add_u64(
+                                rd,
+                                base,
+                                offset as u64,
+                                &mut |_| rd,
+                            );
+                            insts
+                                .into_iter()
+                                .for_each(|i| i.emit(&[], sink, emit_info, state));
+                        }
                     }
-                    .emit(&[], sink, emit_info, state);
-                } else {
-                    let insts = LoadConstant::U64(offset as u64).load_constant_and_add(rd, base);
-                    insts
-                        .into_iter()
-                        .for_each(|i| i.emit(&[], sink, emit_info, state));
                 }
             }
 
diff --git a/cranelift/codegen/src/isa/riscv64/inst/imms.rs b/cranelift/codegen/src/isa/riscv64/inst/imms.rs
index bee1971636c8..57da1b22473f 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/imms.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/imms.rs
@@ -75,6 +75,11 @@ pub struct Imm20 {
 }
 
 impl Imm20 {
+    #[inline]
+    pub fn zero() -> Self {
+        Self::from_bits(0)
+    }
+
     #[inline]
     pub fn from_bits(bits: i32) -> Self {
         Self {
diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
index 64f2e5a5d604..630d27eade6b 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@@ -252,6 +252,22 @@ impl Inst {
         insts.unwrap_or_else(|| smallvec![Inst::LoadConst64 { rd, imm: value }])
     }
 
+    pub fn load_constant_and_add_u64<F: FnMut(Type) -> Writable<Reg>>(
+        rd: Writable<Reg>,
+        add: Reg,
+        value: u64,
+        alloc_tmp: &mut F,
+    ) -> SmallInstVec<Inst> {
+        let mut insts = Inst::load_constant_u64(rd, value, alloc_tmp);
+        insts.push(Inst::AluRRR {
+            alu_op: AluOPRRR::Add,
+            rd,
+            rs1: rd.to_reg(),
+            rs2: add,
+        });
+        insts
+    }
+
     pub(crate) fn construct_auipc_and_jalr(
         link: Option<Writable<Reg>>,
         tmp: Writable<Reg>,
@@ -361,12 +377,16 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             collector.reg_def(rd);
         }
         &Inst::Load { rd, from, .. } => {
-            collector.reg_use(from.get_base_register());
             collector.reg_def(rd);
+            if let Some(reg) = from.get_base_register() {
+                collector.reg_use(reg);
+            }
         }
         &Inst::Store { to, src, .. } => {
-            collector.reg_use(to.get_base_register());
             collector.reg_use(src);
+            if let Some(reg) = to.get_base_register() {
+                collector.reg_use(reg);
+            }
         }
 
         &Inst::Args { ref args } => {
@@ -416,8 +436,10 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             collector.reg_def(rd);
         }
         &Inst::LoadAddr { rd, mem } => {
-            collector.reg_use(mem.get_base_register());
             collector.reg_early_def(rd);
+            if let Some(reg) = mem.get_base_register() {
+                collector.reg_use(reg);
+            }
         }
 
         &Inst::VirtualSPOffsetAdj { .. } => {}
@@ -1201,26 +1223,12 @@ impl Inst {
                 format!("{} {},{}", "lui", format_reg(rd.to_reg(), allocs), imm.bits)
             }
             &Inst::LoadConst32 { rd, imm } => {
-                use std::fmt::Write;
-
                 let rd = format_reg(rd.to_reg(), allocs);
-                let mut buf = String::new();
-                write!(&mut buf, "auipc {},0; ", rd).unwrap();
-                write!(&mut buf, "ld {},12({}); ", rd, rd).unwrap();
-                write!(&mut buf, "j {}; ", Inst::INSTRUCTION_SIZE + 4).unwrap();
-                write!(&mut buf, ".4byte 0x{:x}", imm).unwrap();
-                buf
+                format!("li {rd},0x{imm:x}")
             }
             &Inst::LoadConst64 { rd, imm } => {
-                use std::fmt::Write;
-
                 let rd = format_reg(rd.to_reg(), allocs);
-                let mut buf = String::new();
-                write!(&mut buf, "auipc {},0; ", rd).unwrap();
-                write!(&mut buf, "ld {},12({}); ", rd, rd).unwrap();
-                write!(&mut buf, "j {}; ", Inst::INSTRUCTION_SIZE + 8).unwrap();
-                write!(&mut buf, ".8byte 0x{:x}", imm).unwrap();
-                buf
+                format!("li {rd},0x{imm:x}")
             }
             &Inst::AluRRR {
                 alu_op,
@@ -1351,8 +1359,8 @@ impl Inst {
                 from,
                 flags: _flags,
             } => {
-                let base = from.to_string_with_alloc(allocs);
                 let rd = format_reg(rd.to_reg(), allocs);
+                let base = from.to_string_with_alloc(allocs);
                 format!("{} {},{}", op.op_name(), rd, base,)
             }
             &Inst::Store {
@@ -1361,8 +1369,8 @@ impl Inst {
                 op,
                 flags: _flags,
             } => {
-                let base = to.to_string_with_alloc(allocs);
                 let src = format_reg(src, allocs);
+                let base = to.to_string_with_alloc(allocs);
                 format!("{} {},{}", op.op_name(), src, base,)
             }
             &Inst::Args { ref args } => {
@@ -1477,8 +1485,8 @@ impl Inst {
                 format!("load_sym {},{}{:+}", rd, name.display(None), offset)
             }
             &MInst::LoadAddr { ref rd, ref mem } => {
-                let rs = mem.to_addr(allocs);
                 let rd = format_reg(rd.to_reg(), allocs);
+                let rs = mem.to_string_with_alloc(allocs);
                 format!("load_addr {},{}", rd, rs)
             }
             &MInst::VirtualSPOffsetAdj { amount } => {
@@ -1553,6 +1561,20 @@ pub enum LabelUse {
     /// is added to the current pc to give the target address. The
     /// conditional branch range is ±4 KiB.
     B12,
+
+    /// Equivalent to the `R_RISCV_PCREL_HI20` relocation, Allows setting
+    /// the immediate field of an `auipc` instruction.
+    ///
+    /// Since we currently don't support offsets in labels, this relocation has
+    /// an implicit offset of 4.
+    PCRelHi20,
+
+    /// Equivalent to the `R_RISCV_PCREL_LO12_I` relocation, Allows setting
+    /// the immediate field of I Type instructions such as `addi` or `lw`.
+    ///
+    /// Since we currently don't support offsets in labels, this relocation has
+    /// an implicit offset of 4.
+    PCRelLo12I,
 }
 
 impl MachInstLabelUse for LabelUse {
@@ -1564,7 +1586,9 @@ impl MachInstLabelUse for LabelUse {
     fn max_pos_range(self) -> CodeOffset {
         match self {
             LabelUse::Jal20 => ((1 << 19) - 1) * 2,
-            LabelUse::PCRel32 => Inst::imm_max() as CodeOffset,
+            LabelUse::PCRelLo12I | LabelUse::PCRelHi20 | LabelUse::PCRel32 => {
+                Inst::imm_max() as CodeOffset
+            }
             LabelUse::B12 => ((1 << 11) - 1) * 2,
         }
     }
@@ -1580,9 +1604,8 @@ impl MachInstLabelUse for LabelUse {
     /// Size of window into code needed to do the patch.
     fn patch_size(self) -> CodeOffset {
         match self {
-            LabelUse::Jal20 => 4,
+            LabelUse::Jal20 | LabelUse::B12 | LabelUse::PCRelHi20 | LabelUse::PCRelLo12I => 4,
             LabelUse::PCRel32 => 8,
-            LabelUse::B12 => 4,
         }
     }
 
@@ -1607,8 +1630,7 @@ impl MachInstLabelUse for LabelUse {
     /// Is a veneer supported for this label reference type?
     fn supports_veneer(self) -> bool {
         match self {
-            Self::B12 => true,
-            Self::Jal20 => true,
+            Self::Jal20 | Self::B12 => true,
             _ => false,
         }
     }
@@ -1616,8 +1638,7 @@ impl MachInstLabelUse for LabelUse {
     /// How large is the veneer, if supported?
     fn veneer_size(self) -> CodeOffset {
         match self {
-            Self::B12 => 8,
-            Self::Jal20 => 8,
+            Self::Jal20 | Self::B12 => 8,
             _ => unreachable!(),
         }
     }
@@ -1701,6 +1722,19 @@ impl LabelUse {
                     | ((offset >> 12 & 0b1) << 31);
                 buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn | v));
             }
+
+            LabelUse::PCRelHi20 => {
+                let offset = offset as u32 + 4;
+                let hi20 = offset & 0xFFFFF000;
+                let insn = (insn & 0xFFF) | hi20;
+                buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn));
+            }
+
+            LabelUse::PCRelLo12I => {
+                let offset = (offset as u32 + 4) & 0xFFF;
+                let insn = (insn & 0xFFFFF) | (offset << 20);
+                buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn));
+            }
         }
     }
 }
diff --git a/cranelift/filetests/filetests/isa/riscv64/constants.clif b/cranelift/filetests/filetests/isa/riscv64/constants.clif
index 43190c6c7e76..e5c410541099 100644
--- a/cranelift/filetests/filetests/isa/riscv64/constants.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/constants.clif
@@ -50,7 +50,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
+;   li a0,0xffff0000
 ;   ret
 
 function %f() -> i64 {
@@ -60,7 +60,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff00000000
+;   li a0,0xffff00000000
 ;   ret
 
 function %f() -> i64 {
@@ -70,7 +70,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff000000000000
+;   li a0,0xffff000000000000
 ;   ret
 
 function %f() -> i64 {
@@ -100,7 +100,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffffffff0000ffff
+;   li a0,0xffffffff0000ffff
 ;   ret
 
 function %f() -> i64 {
@@ -110,7 +110,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000ffffffff
+;   li a0,0xffff0000ffffffff
 ;   ret
 
 function %f() -> i64 {
@@ -120,7 +120,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffffffffffff
+;   li a0,0xffffffffffff
 ;   ret
 
 function %f() -> i64 {
@@ -130,7 +130,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xf34bf0a31212003a
+;   li a0,0xf34bf0a31212003a
 ;   ret
 
 function %f() -> i64 {
@@ -140,7 +140,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0x12e900001ef40000
+;   li a0,0x12e900001ef40000
 ;   ret
 
 function %f() -> i64 {
@@ -150,7 +150,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0x12e9ffff1ef4ffff
+;   li a0,0x12e9ffff1ef4ffff
 ;   ret
 
 function %f() -> i32 {
@@ -170,7 +170,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xfffffff7
+;   li a0,0xfffffff7
 ;   ret
 
 function %f() -> i64 {
@@ -180,7 +180,7 @@ block0:
 }
 
 ; block0:
-;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xfffffff7
+;   li a0,0xfffffff7
 ;   ret
 
 function %f() -> i64 {
@@ -200,7 +200,7 @@ block0:
 }
 
 ; block0:
-;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0x3ff0000000000000
+;   li t1,0x3ff0000000000000
 ;   fmv.d.x fa0,t1
 ;   ret
 
@@ -222,7 +222,7 @@ block0:
 }
 
 ; block0:
-;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0x4049000000000000
+;   li t1,0x4049000000000000
 ;   fmv.d.x fa0,t1
 ;   ret
 
@@ -266,7 +266,7 @@ block0:
 }
 
 ; block0:
-;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xc030000000000000
+;   li t1,0xc030000000000000
 ;   fmv.d.x fa0,t1
 ;   ret
 
@@ -277,7 +277,7 @@ block0:
 }
 
 ; block0:
-;   auipc t1,0; ld t1,12(t1); j 8; .4byte 0xc1800000
+;   li t1,0xc1800000
 ;   fmv.w.x fa0,t1
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/reftypes.clif b/cranelift/filetests/filetests/isa/riscv64/reftypes.clif
index 56cf5b83d627..f2b9e35f66f5 100644
--- a/cranelift/filetests/filetests/isa/riscv64/reftypes.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/reftypes.clif
@@ -73,7 +73,7 @@ block3(v7: r64, v8: r64):
 ;   mv s7,a2
 ;   load_sym a1,%f+0
 ;   callind a1
-;   load_addr a1,nsp+0
+;   load_addr a1,0(nominal_sp)
 ;   ld t4,8(nominal_sp)
 ;   sd t4,0(a1)
 ;   andi a1,a0,255
@@ -91,7 +91,7 @@ block3(v7: r64, v8: r64):
 ;   ld a1,16(nominal_sp)
 ;   j label5
 ; block5:
-;   load_addr a2,nsp+0
+;   load_addr a2,0(nominal_sp)
 ;   ld a2,0(a2)
 ;   mv a3,s7
 ;   sd a2,0(a3)
diff --git a/cranelift/filetests/filetests/isa/riscv64/stack.clif b/cranelift/filetests/filetests/isa/riscv64/stack.clif
index d70250ceb409..97fb86a73f88 100644
--- a/cranelift/filetests/filetests/isa/riscv64/stack.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/stack.clif
@@ -17,7 +17,7 @@ block0:
 ;   mv fp,sp
 ;   add sp,-16
 ; block0:
-;   load_addr a0,nsp+0
+;   load_addr a0,0(nominal_sp)
 ;   add sp,+16
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
@@ -42,7 +42,7 @@ block0:
 ;   call %Probestack
 ;   add sp,-100016
 ; block0:
-;   load_addr a0,nsp+0
+;   load_addr a0,0(nominal_sp)
 ;   add sp,+100016
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
@@ -63,7 +63,7 @@ block0:
 ;   mv fp,sp
 ;   add sp,-16
 ; block0:
-;   load_addr t1,nsp+0
+;   load_addr t1,0(nominal_sp)
 ;   ld a0,0(t1)
 ;   add sp,+16
 ;   ld ra,8(sp)
@@ -89,7 +89,7 @@ block0:
 ;   call %Probestack
 ;   add sp,-100016
 ; block0:
-;   load_addr t1,nsp+0
+;   load_addr t1,0(nominal_sp)
 ;   ld a0,0(t1)
 ;   add sp,+100016
 ;   ld ra,8(sp)
@@ -111,7 +111,7 @@ block0(v0: i64):
 ;   mv fp,sp
 ;   add sp,-16
 ; block0:
-;   load_addr t2,nsp+0
+;   load_addr t2,0(nominal_sp)
 ;   sd a0,0(t2)
 ;   add sp,+16
 ;   ld ra,8(sp)
@@ -137,7 +137,7 @@ block0(v0: i64):
 ;   call %Probestack
 ;   add sp,-100016
 ; block0:
-;   load_addr t2,nsp+0
+;   load_addr t2,0(nominal_sp)
 ;   sd a0,0(t2)
 ;   add sp,+100016
 ;   ld ra,8(sp)
@@ -493,7 +493,7 @@ block0(v0: i128):
 ;   add sp,-16
 ; block0:
 ;   mv a2,a0
-;   load_addr a0,nsp+0
+;   load_addr a0,0(nominal_sp)
 ;   sd a2,0(a0)
 ;   sd a1,8(a0)
 ;   add sp,+16
@@ -518,7 +518,7 @@ block0(v0: i128):
 ;   add sp,-32
 ; block0:
 ;   mv a2,a0
-;   load_addr a0,nsp+32
+;   load_addr a0,32(nominal_sp)
 ;   sd a2,0(a0)
 ;   sd a1,8(a0)
 ;   add sp,+32
@@ -546,7 +546,7 @@ block0(v0: i128):
 ;   add sp,-100016
 ; block0:
 ;   mv a2,a0
-;   load_addr a0,nsp+0
+;   load_addr a0,0(nominal_sp)
 ;   sd a2,0(a0)
 ;   sd a1,8(a0)
 ;   add sp,+100016
@@ -569,7 +569,7 @@ block0:
 ;   mv fp,sp
 ;   add sp,-16
 ; block0:
-;   load_addr t2,nsp+0
+;   load_addr t2,0(nominal_sp)
 ;   ld a0,0(t2)
 ;   ld a1,8(t2)
 ;   add sp,+16
@@ -593,7 +593,7 @@ block0:
 ;   mv fp,sp
 ;   add sp,-32
 ; block0:
-;   load_addr t2,nsp+32
+;   load_addr t2,32(nominal_sp)
 ;   ld a0,0(t2)
 ;   ld a1,8(t2)
 ;   add sp,+32
@@ -620,7 +620,7 @@ block0:
 ;   call %Probestack
 ;   add sp,-100016
 ; block0:
-;   load_addr t2,nsp+0
+;   load_addr t2,0(nominal_sp)
 ;   ld a0,0(t2)
 ;   ld a1,8(t2)
 ;   add sp,+100016
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
index 8125a69d1293..f869c6d8acb3 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0004
+;;   li t3,0xffff0004
 ;;   add t1,t0,t3
 ;;   ult t2,t1,t0##ty=i64
 ;;   trap_if t2,heap_oob
@@ -52,7 +52,7 @@
 ;; block1:
 ;;   ld t2,0(a2)
 ;;   add t2,t2,t0
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0000
+;;   li t1,0xffff0000
 ;;   add a0,t2,t1
 ;;   sw a1,0(a0)
 ;;   j label2
@@ -64,7 +64,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0004
+;;   li t3,0xffff0004
 ;;   add t1,t0,t3
 ;;   ult t2,t1,t0##ty=i64
 ;;   trap_if t2,heap_oob
@@ -74,11 +74,11 @@
 ;; block1:
 ;;   ld t2,0(a1)
 ;;   add t2,t2,t0
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0000
+;;   li t1,0xffff0000
 ;;   add a0,t2,t1
 ;;   lw a0,0(a0)
 ;;   j label2
 ;; block2:
 ;;   ret
 ;; block3:
-;;   udf##trap_code=heap_oob
\ No newline at end of file
+;;   udf##trap_code=heap_oob
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 11170dc238a1..5710dc3ca10a 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0001
+;;   li t3,0xffff0001
 ;;   add t1,t0,t3
 ;;   ult t2,t1,t0##ty=i64
 ;;   trap_if t2,heap_oob
@@ -52,7 +52,7 @@
 ;; block1:
 ;;   ld t2,0(a2)
 ;;   add t2,t2,t0
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0000
+;;   li t1,0xffff0000
 ;;   add a0,t2,t1
 ;;   sb a1,0(a0)
 ;;   j label2
@@ -64,7 +64,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0001
+;;   li t3,0xffff0001
 ;;   add t1,t0,t3
 ;;   ult t2,t1,t0##ty=i64
 ;;   trap_if t2,heap_oob
@@ -74,11 +74,11 @@
 ;; block1:
 ;;   ld t2,0(a1)
 ;;   add t2,t2,t0
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0000
+;;   li t1,0xffff0000
 ;;   add a0,t2,t1
 ;;   lbu a0,0(a0)
 ;;   j label2
 ;; block2:
 ;;   ret
 ;; block3:
-;;   udf##trap_code=heap_oob
\ No newline at end of file
+;;   udf##trap_code=heap_oob
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 98afb5b82fef..01bb495d26b5 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -42,14 +42,14 @@
 ;; function u0:0:
 ;; block0:
 ;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0004
+;;   li t0,0xffff0004
 ;;   add t2,a0,t0
 ;;   ult a3,t2,a0##ty=i64
 ;;   trap_if a3,heap_oob
 ;;   ld a3,8(a2)
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   li a2,0xffff0000
 ;;   add a2,a0,a2
 ;;   ugt t2,t2,a3##ty=i64
 ;;   li a3,0
@@ -62,14 +62,14 @@
 ;; function u0:1:
 ;; block0:
 ;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0004
+;;   li t0,0xffff0004
 ;;   add t2,a0,t0
 ;;   ult a2,t2,a0##ty=i64
 ;;   trap_if a2,heap_oob
 ;;   ld a2,8(a1)
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
+;;   li a1,0xffff0000
 ;;   add a1,a0,a1
 ;;   ugt t2,t2,a2##ty=i64
 ;;   li a2,0
@@ -77,4 +77,4 @@
 ;;   lw a0,0(a0)
 ;;   j label1
 ;; block1:
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 8088426a5fd5..b83d6647aa19 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -42,14 +42,14 @@
 ;; function u0:0:
 ;; block0:
 ;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0001
+;;   li t0,0xffff0001
 ;;   add t2,a0,t0
 ;;   ult a3,t2,a0##ty=i64
 ;;   trap_if a3,heap_oob
 ;;   ld a3,8(a2)
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   li a2,0xffff0000
 ;;   add a2,a0,a2
 ;;   ugt t2,t2,a3##ty=i64
 ;;   li a3,0
@@ -62,14 +62,14 @@
 ;; function u0:1:
 ;; block0:
 ;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0001
+;;   li t0,0xffff0001
 ;;   add t2,a0,t0
 ;;   ult a2,t2,a0##ty=i64
 ;;   trap_if a2,heap_oob
 ;;   ld a2,8(a1)
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
+;;   li a1,0xffff0000
 ;;   add a1,a0,a1
 ;;   ugt t2,t2,a2##ty=i64
 ;;   li a2,0
@@ -77,4 +77,4 @@
 ;;   lbu a0,0(a0)
 ;;   j label1
 ;; block1:
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
index e59f6b26e490..0054a6086a96 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0004
+;;   li t3,0xffff0004
 ;;   add t1,t0,t3
 ;;   ult t2,t1,t0##ty=i64
 ;;   trap_if t2,heap_oob
@@ -52,7 +52,7 @@
 ;; block1:
 ;;   ld t2,0(a2)
 ;;   add t2,t2,t0
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0000
+;;   li t1,0xffff0000
 ;;   add a0,t2,t1
 ;;   sw a1,0(a0)
 ;;   j label2
@@ -64,7 +64,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0004
+;;   li t3,0xffff0004
 ;;   add t1,t0,t3
 ;;   ult t2,t1,t0##ty=i64
 ;;   trap_if t2,heap_oob
@@ -74,11 +74,11 @@
 ;; block1:
 ;;   ld t2,0(a1)
 ;;   add t2,t2,t0
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0000
+;;   li t1,0xffff0000
 ;;   add a0,t2,t1
 ;;   lw a0,0(a0)
 ;;   j label2
 ;; block2:
 ;;   ret
 ;; block3:
-;;   udf##trap_code=heap_oob
\ No newline at end of file
+;;   udf##trap_code=heap_oob
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index e50a94341122..ab9b52052b50 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0001
+;;   li t3,0xffff0001
 ;;   add t1,t0,t3
 ;;   ult t2,t1,t0##ty=i64
 ;;   trap_if t2,heap_oob
@@ -52,7 +52,7 @@
 ;; block1:
 ;;   ld t2,0(a2)
 ;;   add t2,t2,t0
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0000
+;;   li t1,0xffff0000
 ;;   add a0,t2,t1
 ;;   sb a1,0(a0)
 ;;   j label2
@@ -64,7 +64,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   uext.w t0,a0
-;;   auipc t3,0; ld t3,12(t3); j 12; .8byte 0xffff0001
+;;   li t3,0xffff0001
 ;;   add t1,t0,t3
 ;;   ult t2,t1,t0##ty=i64
 ;;   trap_if t2,heap_oob
@@ -74,11 +74,11 @@
 ;; block1:
 ;;   ld t2,0(a1)
 ;;   add t2,t2,t0
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0000
+;;   li t1,0xffff0000
 ;;   add a0,t2,t1
 ;;   lbu a0,0(a0)
 ;;   j label2
 ;; block2:
 ;;   ret
 ;; block3:
-;;   udf##trap_code=heap_oob
\ No newline at end of file
+;;   udf##trap_code=heap_oob
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index f613be130b97..41e3add6994b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -42,14 +42,14 @@
 ;; function u0:0:
 ;; block0:
 ;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0004
+;;   li t0,0xffff0004
 ;;   add t2,a0,t0
 ;;   ult a3,t2,a0##ty=i64
 ;;   trap_if a3,heap_oob
 ;;   ld a3,8(a2)
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   li a2,0xffff0000
 ;;   add a2,a0,a2
 ;;   ugt t2,t2,a3##ty=i64
 ;;   li a3,0
@@ -62,14 +62,14 @@
 ;; function u0:1:
 ;; block0:
 ;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0004
+;;   li t0,0xffff0004
 ;;   add t2,a0,t0
 ;;   ult a2,t2,a0##ty=i64
 ;;   trap_if a2,heap_oob
 ;;   ld a2,8(a1)
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
+;;   li a1,0xffff0000
 ;;   add a1,a0,a1
 ;;   ugt t2,t2,a2##ty=i64
 ;;   li a2,0
@@ -77,4 +77,4 @@
 ;;   lw a0,0(a0)
 ;;   j label1
 ;; block1:
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index b34c53839bbb..3ba745a9b660 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -42,14 +42,14 @@
 ;; function u0:0:
 ;; block0:
 ;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0001
+;;   li t0,0xffff0001
 ;;   add t2,a0,t0
 ;;   ult a3,t2,a0##ty=i64
 ;;   trap_if a3,heap_oob
 ;;   ld a3,8(a2)
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   li a2,0xffff0000
 ;;   add a2,a0,a2
 ;;   ugt t2,t2,a3##ty=i64
 ;;   li a3,0
@@ -62,14 +62,14 @@
 ;; function u0:1:
 ;; block0:
 ;;   uext.w a0,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0001
+;;   li t0,0xffff0001
 ;;   add t2,a0,t0
 ;;   ult a2,t2,a0##ty=i64
 ;;   trap_if a2,heap_oob
 ;;   ld a2,8(a1)
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
+;;   li a1,0xffff0000
 ;;   add a1,a0,a1
 ;;   ugt t2,t2,a2##ty=i64
 ;;   li a2,0
@@ -77,4 +77,4 @@
 ;;   lbu a0,0(a0)
 ;;   j label1
 ;; block1:
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
index d7629a47119b..a28503406283 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -41,7 +41,7 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0004
+;;   li a7,0xffff0004
 ;;   add t4,a0,a7
 ;;   ult t1,t4,a0##ty=i64
 ;;   trap_if t1,heap_oob
@@ -51,7 +51,7 @@
 ;; block1:
 ;;   ld t1,0(a2)
 ;;   add t1,t1,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   li t0,0xffff0000
 ;;   add t2,t1,t0
 ;;   sw a1,0(t2)
 ;;   j label2
@@ -62,7 +62,7 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0004
+;;   li a7,0xffff0004
 ;;   add t4,a0,a7
 ;;   ult t1,t4,a0##ty=i64
 ;;   trap_if t1,heap_oob
@@ -72,11 +72,11 @@
 ;; block1:
 ;;   ld t1,0(a1)
 ;;   add t1,t1,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   li t0,0xffff0000
 ;;   add t2,t1,t0
 ;;   lw a0,0(t2)
 ;;   j label2
 ;; block2:
 ;;   ret
 ;; block3:
-;;   udf##trap_code=heap_oob
\ No newline at end of file
+;;   udf##trap_code=heap_oob
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index e73189853dc8..964de49097e9 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -41,7 +41,7 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0001
+;;   li a7,0xffff0001
 ;;   add t4,a0,a7
 ;;   ult t1,t4,a0##ty=i64
 ;;   trap_if t1,heap_oob
@@ -51,7 +51,7 @@
 ;; block1:
 ;;   ld t1,0(a2)
 ;;   add t1,t1,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   li t0,0xffff0000
 ;;   add t2,t1,t0
 ;;   sb a1,0(t2)
 ;;   j label2
@@ -62,7 +62,7 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0001
+;;   li a7,0xffff0001
 ;;   add t4,a0,a7
 ;;   ult t1,t4,a0##ty=i64
 ;;   trap_if t1,heap_oob
@@ -72,11 +72,11 @@
 ;; block1:
 ;;   ld t1,0(a1)
 ;;   add t1,t1,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   li t0,0xffff0000
 ;;   add t2,t1,t0
 ;;   lbu a0,0(t2)
 ;;   j label2
 ;; block2:
 ;;   ret
 ;; block3:
-;;   udf##trap_code=heap_oob
\ No newline at end of file
+;;   udf##trap_code=heap_oob
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index bf692814dba6..c2b4899ec3d7 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -41,14 +41,14 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
+;;   li t4,0xffff0004
 ;;   add t1,a0,t4
 ;;   ult a3,t1,a0##ty=i64
 ;;   trap_if a3,heap_oob
 ;;   ld t2,8(a2)
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   li a2,0xffff0000
 ;;   add a0,a0,a2
 ;;   ugt t1,t1,t2##ty=i64
 ;;   li a2,0
@@ -60,14 +60,14 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
+;;   li t4,0xffff0004
 ;;   add t1,a0,t4
 ;;   ult a2,t1,a0##ty=i64
 ;;   trap_if a2,heap_oob
 ;;   ld t2,8(a1)
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
+;;   li a1,0xffff0000
 ;;   add a0,a0,a1
 ;;   ugt t1,t1,t2##ty=i64
 ;;   li a1,0
@@ -75,4 +75,4 @@
 ;;   lw a0,0(t2)
 ;;   j label1
 ;; block1:
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index c0de90c2709f..c7dc5772558f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,14 +41,14 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
+;;   li t4,0xffff0001
 ;;   add t1,a0,t4
 ;;   ult a3,t1,a0##ty=i64
 ;;   trap_if a3,heap_oob
 ;;   ld t2,8(a2)
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   li a2,0xffff0000
 ;;   add a0,a0,a2
 ;;   ugt t1,t1,t2##ty=i64
 ;;   li a2,0
@@ -60,14 +60,14 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
+;;   li t4,0xffff0001
 ;;   add t1,a0,t4
 ;;   ult a2,t1,a0##ty=i64
 ;;   trap_if a2,heap_oob
 ;;   ld t2,8(a1)
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
+;;   li a1,0xffff0000
 ;;   add a0,a0,a1
 ;;   ugt t1,t1,t2##ty=i64
 ;;   li a1,0
@@ -75,4 +75,4 @@
 ;;   lbu a0,0(t2)
 ;;   j label1
 ;; block1:
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
index c509b188a0c5..e917a790a43a 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -41,7 +41,7 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0004
+;;   li a7,0xffff0004
 ;;   add t4,a0,a7
 ;;   ult t1,t4,a0##ty=i64
 ;;   trap_if t1,heap_oob
@@ -51,7 +51,7 @@
 ;; block1:
 ;;   ld t1,0(a2)
 ;;   add t1,t1,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   li t0,0xffff0000
 ;;   add t2,t1,t0
 ;;   sw a1,0(t2)
 ;;   j label2
@@ -62,7 +62,7 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0004
+;;   li a7,0xffff0004
 ;;   add t4,a0,a7
 ;;   ult t1,t4,a0##ty=i64
 ;;   trap_if t1,heap_oob
@@ -72,11 +72,11 @@
 ;; block1:
 ;;   ld t1,0(a1)
 ;;   add t1,t1,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   li t0,0xffff0000
 ;;   add t2,t1,t0
 ;;   lw a0,0(t2)
 ;;   j label2
 ;; block2:
 ;;   ret
 ;; block3:
-;;   udf##trap_code=heap_oob
\ No newline at end of file
+;;   udf##trap_code=heap_oob
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 05eb78d444eb..65e05a4bd048 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -41,7 +41,7 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0001
+;;   li a7,0xffff0001
 ;;   add t4,a0,a7
 ;;   ult t1,t4,a0##ty=i64
 ;;   trap_if t1,heap_oob
@@ -51,7 +51,7 @@
 ;; block1:
 ;;   ld t1,0(a2)
 ;;   add t1,t1,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   li t0,0xffff0000
 ;;   add t2,t1,t0
 ;;   sb a1,0(t2)
 ;;   j label2
@@ -62,7 +62,7 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0001
+;;   li a7,0xffff0001
 ;;   add t4,a0,a7
 ;;   ult t1,t4,a0##ty=i64
 ;;   trap_if t1,heap_oob
@@ -72,11 +72,11 @@
 ;; block1:
 ;;   ld t1,0(a1)
 ;;   add t1,t1,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
+;;   li t0,0xffff0000
 ;;   add t2,t1,t0
 ;;   lbu a0,0(t2)
 ;;   j label2
 ;; block2:
 ;;   ret
 ;; block3:
-;;   udf##trap_code=heap_oob
\ No newline at end of file
+;;   udf##trap_code=heap_oob
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index e5762ae96de8..ba796cc19f51 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -41,14 +41,14 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
+;;   li t4,0xffff0004
 ;;   add t1,a0,t4
 ;;   ult a3,t1,a0##ty=i64
 ;;   trap_if a3,heap_oob
 ;;   ld t2,8(a2)
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   li a2,0xffff0000
 ;;   add a0,a0,a2
 ;;   ugt t1,t1,t2##ty=i64
 ;;   li a2,0
@@ -60,14 +60,14 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
+;;   li t4,0xffff0004
 ;;   add t1,a0,t4
 ;;   ult a2,t1,a0##ty=i64
 ;;   trap_if a2,heap_oob
 ;;   ld t2,8(a1)
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
+;;   li a1,0xffff0000
 ;;   add a0,a0,a1
 ;;   ugt t1,t1,t2##ty=i64
 ;;   li a1,0
@@ -75,4 +75,4 @@
 ;;   lw a0,0(t2)
 ;;   j label1
 ;; block1:
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index a4b0f0c6a3c2..0c504c205166 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,14 +41,14 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
+;;   li t4,0xffff0001
 ;;   add t1,a0,t4
 ;;   ult a3,t1,a0##ty=i64
 ;;   trap_if a3,heap_oob
 ;;   ld t2,8(a2)
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
+;;   li a2,0xffff0000
 ;;   add a0,a0,a2
 ;;   ugt t1,t1,t2##ty=i64
 ;;   li a2,0
@@ -60,14 +60,14 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
+;;   li t4,0xffff0001
 ;;   add t1,a0,t4
 ;;   ult a2,t1,a0##ty=i64
 ;;   trap_if a2,heap_oob
 ;;   ld t2,8(a1)
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
+;;   li a1,0xffff0000
 ;;   add a0,a0,a1
 ;;   ugt t1,t1,t2##ty=i64
 ;;   li a1,0
@@ -75,4 +75,4 @@
 ;;   lbu a0,0(t2)
 ;;   j label1
 ;; block1:
-;;   ret
\ No newline at end of file
+;;   ret
diff --git a/cranelift/filetests/filetests/runtests/issue-5569.clif b/cranelift/filetests/filetests/runtests/issue-5569.clif
new file mode 100644
index 000000000000..067066ed7d70
--- /dev/null
+++ b/cranelift/filetests/filetests/runtests/issue-5569.clif
@@ -0,0 +1,404 @@
+test interpret
+test run
+set use_egraphs=true
+set enable_llvm_abi_extensions=true
+target aarch64
+target s390x
+target x86_64
+target riscv64
+
+;; See https://github.com/bytecodealliance/wasmtime/issues/5569
+;; This issue essentially boils down to a veneer being emitted right
+;; in the middle of a load constant sequence that used hard coded
+;; offsets between instructions.
+
+function %a(i16, f64, i32, i64, i16, i128, f32) -> i16 {
+    ss0 = explicit_slot 24
+
+block0(v0: i16, v1: f64, v2: i32, v3: i64, v4: i16, v5: i128, v6: f32):
+    v8 = iconst.i8 0
+    v9 = iconst.i16 0
+    v10 = iconst.i32 0
+    v11 = iconst.i64 0
+    v12 = uextend.i128 v11  ; v11 = 0
+    stack_store v12, ss0
+    stack_store v11, ss0+16  ; v11 = 0
+    v55 = iconst.i32 0
+    v56 = iconst.i32 1
+    v57 = icmp eq v2, v55  ; v55 = 0
+    v58 = ishl_imm v56, 31  ; v56 = 1
+    v59 = isub v55, v56  ; v55 = 0, v56 = 1
+    v60 = icmp eq v2, v58
+    v61 = icmp eq v2, v59
+    v62 = band v60, v61
+    v63 = bor v57, v62
+    v64 = select v63, v56, v2  ; v56 = 1
+    v13 = sdiv v2, v64
+    v65 = iconst.i32 0
+    v66 = iconst.i32 1
+    v67 = icmp eq v13, v65  ; v65 = 0
+    v68 = ishl_imm v66, 31  ; v66 = 1
+    v69 = isub v65, v66  ; v65 = 0, v66 = 1
+    v70 = icmp eq v13, v68
+    v71 = icmp eq v13, v69
+    v72 = band v70, v71
+    v73 = bor v67, v72
+    v74 = select v73, v66, v13  ; v66 = 1
+    v14 = sdiv v13, v74
+    v75 = iconst.i32 0
+    v76 = iconst.i32 1
+    v77 = icmp eq v14, v75  ; v75 = 0
+    v78 = ishl_imm v76, 31  ; v76 = 1
+    v79 = isub v75, v76  ; v75 = 0, v76 = 1
+    v80 = icmp eq v14, v78
+    v81 = icmp eq v14, v79
+    v82 = band v80, v81
+    v83 = bor v77, v82
+    v84 = select v83, v76, v14  ; v76 = 1
+    v15 = sdiv v14, v84
+    v85 = iconst.i64 0
+    v86 = iconst.i64 1
+    v87 = icmp eq v3, v85  ; v85 = 0
+    v88 = ishl_imm v86, 63  ; v86 = 1
+    v89 = isub v85, v86  ; v85 = 0, v86 = 1
+    v90 = icmp eq v3, v88
+    v91 = icmp eq v3, v89
+    v92 = band v90, v91
+    v93 = bor v87, v92
+    v94 = select v93, v86, v3  ; v86 = 1
+    v16 = sdiv v3, v94
+    v95 = iconst.i32 0
+    v96 = iconst.i32 1
+    v97 = icmp eq v15, v95  ; v95 = 0
+    v98 = ishl_imm v96, 31  ; v96 = 1
+    v99 = isub v95, v96  ; v95 = 0, v96 = 1
+    v100 = icmp eq v15, v98
+    v101 = icmp eq v15, v99
+    v102 = band v100, v101
+    v103 = bor v97, v102
+    v104 = select v103, v96, v15  ; v96 = 1
+    v17 = sdiv v15, v104
+    v18 = fmax_pseudo v6, v6
+    v105 = iconst.i32 0
+    v106 = iconst.i32 1
+    v107 = icmp eq v17, v105  ; v105 = 0
+    v108 = ishl_imm v106, 31  ; v106 = 1
+    v109 = isub v105, v106  ; v105 = 0, v106 = 1
+    v110 = icmp eq v17, v108
+    v111 = icmp eq v17, v109
+    v112 = band v110, v111
+    v113 = bor v107, v112
+    v114 = select v113, v106, v17  ; v106 = 1
+    v19 = sdiv v17, v114
+    v115 = iconst.i32 0
+    v116 = iconst.i32 1
+    v117 = icmp eq v19, v115  ; v115 = 0
+    v118 = ishl_imm v116, 31  ; v116 = 1
+    v119 = isub v115, v116  ; v115 = 0, v116 = 1
+    v120 = icmp eq v19, v118
+    v121 = icmp eq v19, v119
+    v122 = band v120, v121
+    v123 = bor v117, v122
+    v124 = select v123, v116, v19  ; v116 = 1
+    v20 = sdiv v19, v124
+    v125 = iconst.i32 0
+    v126 = iconst.i32 1
+    v127 = icmp eq v20, v125  ; v125 = 0
+    v128 = ishl_imm v126, 31  ; v126 = 1
+    v129 = isub v125, v126  ; v125 = 0, v126 = 1
+    v130 = icmp eq v20, v128
+    v131 = icmp eq v20, v129
+    v132 = band v130, v131
+    v133 = bor v127, v132
+    v134 = select v133, v126, v20  ; v126 = 1
+    v21 = sdiv v20, v134
+    stack_store v16, ss0+4
+    v135 = iconst.i32 0
+    v136 = iconst.i32 1
+    v137 = icmp eq v21, v135  ; v135 = 0
+    v138 = ishl_imm v136, 31  ; v136 = 1
+    v139 = isub v135, v136  ; v135 = 0, v136 = 1
+    v140 = icmp eq v21, v138
+    v141 = icmp eq v21, v139
+    v142 = band v140, v141
+    v143 = bor v137, v142
+    v144 = select v143, v136, v21  ; v136 = 1
+    v22 = sdiv v21, v144
+    v145 = iconst.i32 0
+    v146 = iconst.i32 1
+    v147 = icmp eq v22, v145  ; v145 = 0
+    v148 = ishl_imm v146, 31  ; v146 = 1
+    v149 = isub v145, v146  ; v145 = 0, v146 = 1
+    v150 = icmp eq v22, v148
+    v151 = icmp eq v22, v149
+    v152 = band v150, v151
+    v153 = bor v147, v152
+    v154 = select v153, v146, v22  ; v146 = 1
+    v23 = sdiv v22, v154
+    v155 = iconst.i32 0
+    v156 = iconst.i32 1
+    v157 = icmp eq v23, v155  ; v155 = 0
+    v158 = ishl_imm v156, 31  ; v156 = 1
+    v159 = isub v155, v156  ; v155 = 0, v156 = 1
+    v160 = icmp eq v23, v158
+    v161 = icmp eq v23, v159
+    v162 = band v160, v161
+    v163 = bor v157, v162
+    v164 = select v163, v156, v23  ; v156 = 1
+    v24 = sdiv v23, v164
+    v165 = iconst.i32 0
+    v166 = iconst.i32 1
+    v167 = icmp eq v24, v165  ; v165 = 0
+    v168 = ishl_imm v166, 31  ; v166 = 1
+    v169 = isub v165, v166  ; v165 = 0, v166 = 1
+    v170 = icmp eq v24, v168
+    v171 = icmp eq v24, v169
+    v172 = band v170, v171
+    v173 = bor v167, v172
+    v174 = select v173, v166, v24  ; v166 = 1
+    v25 = sdiv v24, v174
+    v175 = iconst.i32 0
+    v176 = iconst.i32 1
+    v177 = icmp eq v25, v175  ; v175 = 0
+    v178 = ishl_imm v176, 31  ; v176 = 1
+    v179 = isub v175, v176  ; v175 = 0, v176 = 1
+    v180 = icmp eq v25, v178
+    v181 = icmp eq v25, v179
+    v182 = band v180, v181
+    v183 = bor v177, v182
+    v184 = select v183, v176, v25  ; v176 = 1
+    v26 = sdiv v25, v184
+    v185 = iconst.i32 0
+    v186 = iconst.i32 1
+    v187 = icmp eq v26, v185  ; v185 = 0
+    v188 = ishl_imm v186, 31  ; v186 = 1
+    v189 = isub v185, v186  ; v185 = 0, v186 = 1
+    v190 = icmp eq v26, v188
+    v191 = icmp eq v26, v189
+    v192 = band v190, v191
+    v193 = bor v187, v192
+    v194 = select v193, v186, v26  ; v186 = 1
+    v27 = sdiv v26, v194
+    v195 = iconst.i32 0
+    v196 = iconst.i32 1
+    v197 = icmp eq v27, v195  ; v195 = 0
+    v198 = ishl_imm v196, 31  ; v196 = 1
+    v199 = isub v195, v196  ; v195 = 0, v196 = 1
+    v200 = icmp eq v27, v198
+    v201 = icmp eq v27, v199
+    v202 = band v200, v201
+    v203 = bor v197, v202
+    v204 = select v203, v196, v27  ; v196 = 1
+    v28 = sdiv v27, v204
+    v205 = iconst.i32 0
+    v206 = iconst.i32 1
+    v207 = icmp eq v28, v205  ; v205 = 0
+    v208 = ishl_imm v206, 31  ; v206 = 1
+    v209 = isub v205, v206  ; v205 = 0, v206 = 1
+    v210 = icmp eq v28, v208
+    v211 = icmp eq v28, v209
+    v212 = band v210, v211
+    v213 = bor v207, v212
+    v214 = select v213, v206, v28  ; v206 = 1
+    v29 = sdiv v28, v214
+    v52 = nearest v1
+    v53 = fcmp ne v52, v52
+    v54 = f64const +NaN
+    v30 = select v53, v54, v52  ; v54 = +NaN
+    v215 = iconst.i32 0
+    v216 = iconst.i32 1
+    v217 = icmp eq v29, v215  ; v215 = 0
+    v218 = ishl_imm v216, 31  ; v216 = 1
+    v219 = isub v215, v216  ; v215 = 0, v216 = 1
+    v220 = icmp eq v29, v218
+    v221 = icmp eq v29, v219
+    v222 = band v220, v221
+    v223 = bor v217, v222
+    v224 = select v223, v216, v29  ; v216 = 1
+    v31 = sdiv v29, v224
+    v225 = iconst.i32 0
+    v226 = iconst.i32 1
+    v227 = icmp eq v31, v225  ; v225 = 0
+    v228 = ishl_imm v226, 31  ; v226 = 1
+    v229 = isub v225, v226  ; v225 = 0, v226 = 1
+    v230 = icmp eq v31, v228
+    v231 = icmp eq v31, v229
+    v232 = band v230, v231
+    v233 = bor v227, v232
+    v234 = select v233, v226, v31  ; v226 = 1
+    v32 = sdiv v31, v234
+    v235 = iconst.i32 0
+    v236 = iconst.i32 1
+    v237 = icmp eq v32, v235  ; v235 = 0
+    v238 = ishl_imm v236, 31  ; v236 = 1
+    v239 = isub v235, v236  ; v235 = 0, v236 = 1
+    v240 = icmp eq v32, v238
+    v241 = icmp eq v32, v239
+    v242 = band v240, v241
+    v243 = bor v237, v242
+    v244 = select v243, v236, v32  ; v236 = 1
+    v33 = sdiv v32, v244
+    v245 = iconst.i32 0
+    v246 = iconst.i32 1
+    v247 = icmp eq v33, v245  ; v245 = 0
+    v248 = ishl_imm v246, 31  ; v246 = 1
+    v249 = isub v245, v246  ; v245 = 0, v246 = 1
+    v250 = icmp eq v33, v248
+    v251 = icmp eq v33, v249
+    v252 = band v250, v251
+    v253 = bor v247, v252
+    v254 = select v253, v246, v33  ; v246 = 1
+    v34 = sdiv v33, v254
+    v35 = fmax_pseudo v18, v18
+    v255 = iconst.i32 0
+    v256 = iconst.i32 1
+    v257 = icmp eq v34, v255  ; v255 = 0
+    v258 = ishl_imm v256, 31  ; v256 = 1
+    v259 = isub v255, v256  ; v255 = 0, v256 = 1
+    v260 = icmp eq v34, v258
+    v261 = icmp eq v34, v259
+    v262 = band v260, v261
+    v263 = bor v257, v262
+    v264 = select v263, v256, v34  ; v256 = 1
+    v36 = sdiv v34, v264
+    v265 = iconst.i32 0
+    v266 = iconst.i32 1
+    v267 = icmp eq v36, v265  ; v265 = 0
+    v268 = ishl_imm v266, 31  ; v266 = 1
+    v269 = isub v265, v266  ; v265 = 0, v266 = 1
+    v270 = icmp eq v36, v268
+    v271 = icmp eq v36, v269
+    v272 = band v270, v271
+    v273 = bor v267, v272
+    v274 = select v273, v266, v36  ; v266 = 1
+    v37 = sdiv v36, v274
+    v275 = iconst.i32 0
+    v276 = iconst.i32 1
+    v277 = icmp eq v37, v275  ; v275 = 0
+    v278 = ishl_imm v276, 31  ; v276 = 1
+    v279 = isub v275, v276  ; v275 = 0, v276 = 1
+    v280 = icmp eq v37, v278
+    v281 = icmp eq v37, v279
+    v282 = band v280, v281
+    v283 = bor v277, v282
+    v284 = select v283, v276, v37  ; v276 = 1
+    v38 = sdiv v37, v284
+    stack_store v16, ss0+4
+    v285 = iconst.i32 0
+    v286 = iconst.i32 1
+    v287 = icmp eq v38, v285  ; v285 = 0
+    v288 = ishl_imm v286, 31  ; v286 = 1
+    v289 = isub v285, v286  ; v285 = 0, v286 = 1
+    v290 = icmp eq v38, v288
+    v291 = icmp eq v38, v289
+    v292 = band v290, v291
+    v293 = bor v287, v292
+    v294 = select v293, v286, v38  ; v286 = 1
+    v39 = sdiv v38, v294
+    v295 = iconst.i32 0
+    v296 = iconst.i32 1
+    v297 = icmp eq v39, v295  ; v295 = 0
+    v298 = ishl_imm v296, 31  ; v296 = 1
+    v299 = isub v295, v296  ; v295 = 0, v296 = 1
+    v300 = icmp eq v39, v298
+    v301 = icmp eq v39, v299
+    v302 = band v300, v301
+    v303 = bor v297, v302
+    v304 = select v303, v296, v39  ; v296 = 1
+    v40 = sdiv v39, v304
+    v41 = rotr v16, v16
+    v305 = iconst.i32 0
+    v306 = iconst.i32 1
+    v307 = icmp eq v40, v305  ; v305 = 0
+    v308 = ishl_imm v306, 31  ; v306 = 1
+    v309 = isub v305, v306  ; v305 = 0, v306 = 1
+    v310 = icmp eq v40, v308
+    v311 = icmp eq v40, v309
+    v312 = band v310, v311
+    v313 = bor v307, v312
+    v314 = select v313, v306, v40  ; v306 = 1
+    v42 = sdiv v40, v314
+    v315 = iconst.i32 0
+    v316 = iconst.i32 1
+    v317 = icmp eq v42, v315  ; v315 = 0
+    v318 = ishl_imm v316, 31  ; v316 = 1
+    v319 = isub v315, v316  ; v315 = 0, v316 = 1
+    v320 = icmp eq v42, v318
+    v321 = icmp eq v42, v319
+    v322 = band v320, v321
+    v323 = bor v317, v322
+    v324 = select v323, v316, v42  ; v316 = 1
+    v43 = sdiv v42, v324
+    v325 = iconst.i32 0
+    v326 = iconst.i32 1
+    v327 = icmp eq v43, v325  ; v325 = 0
+    v328 = ishl_imm v326, 31  ; v326 = 1
+    v329 = isub v325, v326  ; v325 = 0, v326 = 1
+    v330 = icmp eq v43, v328
+    v331 = icmp eq v43, v329
+    v332 = band v330, v331
+    v333 = bor v327, v332
+    v334 = select v333, v326, v43  ; v326 = 1
+    v44 = sdiv v43, v334
+    v335 = iconst.i32 0
+    v336 = iconst.i32 1
+    v337 = icmp eq v44, v335  ; v335 = 0
+    v338 = ishl_imm v336, 31  ; v336 = 1
+    v339 = isub v335, v336  ; v335 = 0, v336 = 1
+    v340 = icmp eq v44, v338
+    v341 = icmp eq v44, v339
+    v342 = band v340, v341
+    v343 = bor v337, v342
+    v344 = select v343, v336, v44  ; v336 = 1
+    v45 = sdiv v44, v344
+    v345 = iconst.i32 0
+    v346 = iconst.i32 1
+    v347 = icmp eq v45, v345  ; v345 = 0
+    v348 = ishl_imm v346, 31  ; v346 = 1
+    v349 = isub v345, v346  ; v345 = 0, v346 = 1
+    v350 = icmp eq v45, v348
+    v351 = icmp eq v45, v349
+    v352 = band v350, v351
+    v353 = bor v347, v352
+    v354 = select v353, v346, v45  ; v346 = 1
+    v46 = sdiv v45, v354
+    v355 = iconst.i32 0
+    v356 = iconst.i32 1
+    v357 = icmp eq v46, v355  ; v355 = 0
+    v358 = ishl_imm v356, 31  ; v356 = 1
+    v359 = isub v355, v356  ; v355 = 0, v356 = 1
+    v360 = icmp eq v46, v358
+    v361 = icmp eq v46, v359
+    v362 = band v360, v361
+    v363 = bor v357, v362
+    v364 = select v363, v356, v46  ; v356 = 1
+    v47 = sdiv v46, v364
+    v48 = bxor v5, v5
+    v365 = iconst.i32 0
+    v366 = iconst.i32 1
+    v367 = icmp eq v47, v365  ; v365 = 0
+    v368 = ishl_imm v366, 31  ; v366 = 1
+    v369 = isub v365, v366  ; v365 = 0, v366 = 1
+    v370 = icmp eq v47, v368
+    v371 = icmp eq v47, v369
+    v372 = band v370, v371
+    v373 = bor v367, v372
+    v374 = select v373, v366, v47  ; v366 = 1
+    v49 = sdiv v47, v374
+    v375 = iconst.i32 0
+    v376 = iconst.i32 1
+    v377 = icmp eq v49, v375  ; v375 = 0
+    v378 = ishl_imm v376, 31  ; v376 = 1
+    v379 = isub v375, v376  ; v375 = 0, v376 = 1
+    v380 = icmp eq v49, v378
+    v381 = icmp eq v49, v379
+    v382 = band v380, v381
+    v383 = bor v377, v382
+    v384 = select v383, v376, v49  ; v376 = 1
+    v50 = sdiv v49, v384
+    v51 = stack_addr.i64 ss0+4
+    store v30, v51+6
+    return v0
+}
+
+; run: %a(8, 0.0, 0, 0, 0, 0, 0.0) == 8