diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
index 2501d02aca02..cc0c04f747c4 100644
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -234,13 +234,6 @@
       (rs OptionReg)
       (imm OptionUimm5)
       (csr CsrAddress))
-    ;; an integer compare.
-    (Icmp
-      (cc IntCC)
-      (rd WritableReg)
-      (a ValueRegs)
-      (b ValueRegs)
-      (ty Type))
     ;; select a reg base on condition.
     ;; very useful because in lowering stage we can not have condition branch.
     (SelectReg
@@ -755,6 +748,7 @@
     (writable_reg_to_reg rd)))
 
 
+
 ;;;; Instruction Helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; RV32I Base Integer Instruction Set
@@ -861,12 +855,36 @@
 (rule (rv_andi rs1 imm)
   (alu_rr_imm12 (AluOPRRI.Andi) rs1 imm))
 
+;; Helper for emitting the `slt` ("Set Less Than") instruction.
+;; rd ← rs1 < rs2
+(decl rv_slt (Reg Reg) Reg)
+(rule (rv_slt rs1 rs2)
+  (alu_rrr (AluOPRRR.Slt) rs1 rs2))
+
+;; Helper for emitting the `sltz` instruction.
+;; This instruction is a mnemonic for `slt rd, rs, zero`.
+(decl rv_sltz (Reg) Reg)
+(rule (rv_sltz rs1)
+  (rv_slt rs1 (zero_reg)))
+
+;; Helper for emitting the `sgtz` instruction.
+;; This instruction is a mnemonic for `slt rd, zero, rs`.
+(decl rv_sgtz (Reg) Reg)
+(rule (rv_sgtz rs1)
+  (rv_slt (zero_reg) rs1))
+  
+;; Helper for emiting the `slti` ("Set Less Than Immediate") instruction.
+;; rd ← rs1 < imm
+(decl rv_slti (Reg Imm12) Reg)
+(rule (rv_slti rs1 imm)
+  (alu_rr_imm12 (AluOPRRI.Slti) rs1 imm))
+
 ;; Helper for emitting the `sltu` ("Set Less Than Unsigned") instruction.
 ;; rd ← rs1 < rs2
 (decl rv_sltu (Reg Reg) Reg)
 (rule (rv_sltu rs1 rs2)
   (alu_rrr (AluOPRRR.SltU) rs1 rs2))
-
+  
 ;; Helper for emitting the `snez` instruction.
 ;; This instruction is a mnemonic for `sltu rd, zero, rs`.
 (decl rv_snez (Reg) Reg)
@@ -1311,6 +1329,11 @@
 (decl imm12_from_u64 (Imm12) u64)
 (extern extractor imm12_from_u64 imm12_from_u64)
 
+;; Extracts an imm12 from an i64. The i64 must be in a range that can be
+;; represented as an imm12. The value is sign-extended acording to the type
+;; provided.
+(decl pure partial imm12_sextend_i64 (Type i64) Imm12)
+(extern constructor imm12_sextend_i64 imm12_sextend_i64)
 
 
 ;; Float Helpers
@@ -2262,13 +2285,183 @@
     (move_x_to_f tmp2 ty)))
 
 
-;;; lower icmp
-(decl lower_icmp (IntCC ValueRegs ValueRegs Type) Reg)
-(rule 1 (lower_icmp cc x y ty)
-  (if (signed_cond_code cc))
-  (gen_icmp cc (ext_int_if_need $true x ty) (ext_int_if_need $true y ty) ty))
-(rule (lower_icmp cc x y ty)
-  (gen_icmp cc (ext_int_if_need $false x ty) (ext_int_if_need $false y ty) ty))
+
+
+;; For Equal and NotEqual it doesen't matter the type of extension that we 
+;; perform, as long as we are consistent on both sides. So try to pick the
+;; ExtendOp's that have a dedicated instruction in the Base ISA.
+;;
+;; The special cases here are:
+;; - i8 -> any: we should prefer ExtendOp.Zero
+;; - i32 -> i64: we should prefer ExtendOp.Signed
+;;
+;; We only handle the signed case here since the unsigned case is the default
+;; for `intcc_to_extend_op`. The other cases lower into a two instruction
+;; sequence.
+(decl icmp_intcc_extend (IntCC Type) ExtendOp)
+(rule 1 (icmp_intcc_extend (IntCC.Equal) $I32) (ExtendOp.Signed))
+(rule 1 (icmp_intcc_extend (IntCC.NotEqual) $I32) (ExtendOp.Signed))
+(rule (icmp_intcc_extend cc _) (intcc_to_extend_op cc))
+
+
+;; Generates an icmp sequence for the given type.
+(decl gen_icmp (IntCC ValueRegs ValueRegs Type) Reg)
+
+;; On I128's we don't need any extension.
+(rule 1 (gen_icmp cc x y $I128)
+  (gen_icmp_inner cc x y $I128))
+
+;; Otherwise emit the extension sequence before the comparision.
+(rule (gen_icmp cc x y (fits_in_64 ty))
+  (let ((extend_op ExtendOp (icmp_intcc_extend cc ty))
+        (x_ext Reg (extend x extend_op ty $I64))
+        (y_ext Reg (extend y extend_op ty $I64)))
+      (gen_icmp_inner cc x_ext y_ext ty)))
+
+
+
+;; This emits just the comparision instructions and assumes that
+;; the arguments are already extended.
+;;
+;; We only have actual lowerings for Equal/NotEqual/SignedLessThan/UnsignedLessThan.
+;; Everything else just recurses into one of those cases.
+(decl gen_icmp_inner (IntCC ValueRegs ValueRegs Type) Reg)
+
+;; We only implement LessThan, for GreaterThan we just reverse the arguments
+(rule 4 (gen_icmp_inner cc x y ty)
+  (if (intcc_greater_than cc))
+  (gen_icmp_inner (intcc_reverse cc) y x ty))
+
+;; For these rules, we can just use the normal rules and then invert the result.
+;; i.e. `x <= y` is the same as `!(x > y)`.
+(rule 3 (gen_icmp_inner cc x y ty)
+  (if-let (IntCC.UnsignedLessThanOrEqual) (intcc_unsigned cc))
+  (let ((res Reg (gen_icmp_inner (intcc_inverse cc) x y ty)))
+    (rv_xori res (imm12_const 1))))
+
+
+;; For `*LessThan` we have a dedicated instruction `slt`/`sltu`.
+(rule (gen_icmp_inner (IntCC.SignedLessThan) x y (fits_in_64 ty))
+  (rv_slt x y))
+(rule (gen_icmp_inner (IntCC.UnsignedLessThan) x y (fits_in_64 ty))
+  (rv_sltu x y))
+
+
+;; Compare the top halves of the two values. If they are equal, then
+;; we can just check the bottom halves. Otherwise we only need to check
+;; the top halves.
+;;
+;; In both signed and unsigned variants the bottom half is always compared
+;; as unsigned. Since we know that the top halves are equal both signs
+;; are the same. If the number is positive, this is fairly straight forward
+;; and if the number is negative in the signed case we can still use
+;; an unsigned comparision due to the way two's complement works.
+;;
+;; As an example:  0xFFFE < 0xFFFF Here both are negative numbers, but when 
+;; considering only at the bottom byte, 0xFE is smaller than 0xFF when viewed
+;; as unsigned. This also holds true when viewing both of these numbers as
+;; signed (-2 < -1), so we can use the unsigned comparison for the bottom half.
+;;
+;; Emit the following sequence:
+;;     slt{,u}   t1, x_hi, y_hi
+;;     sltu      t2, x_lo, y_lo
+;;     beq       x_hi, y_hi, .top_is_equal
+;;     mov       rd, t1
+;;     j         .end
+;; .top_is_equal:
+;;     mov       rd, t2
+;; .end:
+(rule 2 (gen_icmp_inner cc x y $I128)
+  (if-let (IntCC.UnsignedLessThan) (intcc_unsigned cc))
+  (let ((x_lo Reg (value_regs_get x 0))
+        (x_hi Reg (value_regs_get x 1))
+        (y_lo Reg (value_regs_get y 0))
+        (y_hi Reg (value_regs_get y 1))
+        ;; Generate compares for both halves.
+        ;; The bottom compare depends on the IntCC.
+        (top_cmp Reg (gen_icmp_inner cc x_hi y_hi $I64))
+        (bottom_cmp Reg (rv_slt x_lo y_lo)))
+    ;; If the high parts are equal, the result only depends on the bottom
+    (gen_select_reg (IntCC.Equal) x_hi y_hi bottom_cmp top_cmp)))
+
+
+;; Compare both registers using xor, and set the result using the dedicated
+;; `seqz`/`snez` instructions.
+(rule (gen_icmp_inner (IntCC.Equal) x y (fits_in_64 ty))
+  (rv_seqz (rv_xor x y)))
+(rule (gen_icmp_inner (IntCC.NotEqual) x y (fits_in_64 ty))
+  (rv_snez (rv_xor x y)))
+
+;; In the I128 case we just `xor` everything and check if its zero at the end.
+(rule 1 (gen_icmp_inner (IntCC.Equal) x y $I128)
+  (let ((top_eq Reg (rv_xor (value_regs_get x 0) (value_regs_get y 0)))
+        (bottom_eq Reg (rv_xor (value_regs_get x 1) (value_regs_get y 1)))
+        (res Reg (rv_or top_eq bottom_eq)))
+    (rv_seqz res)))
+(rule 1 (gen_icmp_inner (IntCC.NotEqual) x y $I128)
+  (let ((top_eq Reg (rv_xor (value_regs_get x 0) (value_regs_get y 0)))
+        (bottom_eq Reg (rv_xor (value_regs_get x 1) (value_regs_get y 1)))
+        (res Reg (rv_or top_eq bottom_eq)))
+    (rv_snez res)))
+
+
+
+
+;; For some icmp's we can optimize the instruction sequence if the RHS is a constant.
+;;
+;; TODO: Currently we only have rules for <=64bit types. We can add more rules for I128's
+(decl gen_icmp_imm (IntCC ValueRegs i64 Type) Reg)
+
+;; This rule isn't totally necessary since we can just use `slti 0`, but
+;; it's the official mnemonic for this operation and gives a slightly nicer
+;; disassembly output.
+(rule 5 (gen_icmp_imm (IntCC.SignedLessThan) x 0 (fits_in_64 ty))
+  (rv_sltz (sext x ty $I64)))
+
+;; `sgtz` is preferable since our equivalent immediate lowering has to do `slt+xori`.
+(rule 5 (gen_icmp_imm (IntCC.SignedGreaterThan) x 0 (fits_in_64 ty))
+  (rv_sgtz (sext x ty $I64)))
+
+;; For these IntCC's we need to both add 1 to the immediate and invert the result.
+;; i.e. `x > imm` is the same as `!(x < imm + 1)`.
+(rule 4 (gen_icmp_imm cc x imm ty)
+  (if-let (IntCC.UnsignedGreaterThan) (intcc_unsigned cc))
+  (let ((res Reg (gen_icmp_imm (intcc_reverse cc) x (i64_add imm 1) ty)))
+    (rv_xori res (imm12_const 1))))
+  
+;; We directly support the inverse of these condition codes. So lower the inverse
+;; and then invert the result using `xor`.
+;; i.e. `x >= imm` is the same as `!(x < imm)`.
+(rule 3 (gen_icmp_imm cc x imm ty)
+  (if-let (IntCC.UnsignedGreaterThanOrEqual) (intcc_unsigned cc))
+  (let ((res Reg (gen_icmp_imm (intcc_inverse cc) x imm ty)))
+    (rv_xori res (imm12_const 1))))
+
+;; Here we can add 1 to the immediate and use the reverse condition code.
+;; i.e. `x <= imm` is the same as `x < imm + 1`.
+(rule 2 (gen_icmp_imm cc x imm ty)
+  (if-let (IntCC.UnsignedLessThanOrEqual) (intcc_unsigned cc))
+  (gen_icmp_imm (intcc_without_equal cc) x (i64_add imm 1) ty))
+
+;; We have dedicated instructions for these two cases. (`slti`/`sltiu`)
+(rule 1 (gen_icmp_imm (IntCC.SignedLessThan) x n (fits_in_64 ty))
+  (if-let imm (imm12_sextend_i64 ty n))
+  (rv_slti (sext x ty $I64) imm))
+(rule 1 (gen_icmp_imm (IntCC.UnsignedLessThan) x n (fits_in_64 ty)) 
+  (if-let imm (imm12_sextend_i64 ty n))
+  (rv_sltiu (zext x ty $I64) imm))
+
+;; In the fallback case we load the immediate and then compare.
+(rule (gen_icmp_imm cc x n (fits_in_64 ty))
+  (let ((extend_op ExtendOp (icmp_intcc_extend cc ty))
+        (x_ext Reg (extend x extend_op ty $I64))
+        ;; TODO: Ideally we shouldn't need the sign extend instruction
+        ;; here. We should be able to do it at compile time. But our
+        ;; constant loading infrastructure isn't great yet.
+        (i Reg (imm $I64 (i64_as_u64 n)))
+        (y_ext Reg (extend i extend_op ty $I64)))
+    (gen_icmp cc x_ext y_ext $I64)))
+
 
 
 (decl i128_sub (ValueRegs ValueRegs) ValueRegs)
@@ -2492,8 +2685,8 @@
     ((r_const_neg_1 Reg (load_imm12 -1))
       (r_const_min Reg (rv_slli (load_imm12 1) (imm12_const 63)))
       (tmp_rs1 Reg (shift_int_to_most_significant rs1 ty))
-      (t1 Reg (gen_icmp (IntCC.Equal) r_const_neg_1 rs2 ty))
-      (t2 Reg (gen_icmp (IntCC.Equal) r_const_min tmp_rs1 ty))
+      (t1 Reg (gen_icmp (IntCC.Equal) r_const_neg_1 rs2 $I64))
+      (t2 Reg (gen_icmp (IntCC.Equal) r_const_min tmp_rs1 $I64))
       (test Reg (rv_and t1 t2)))
     (gen_trapif test (TrapCode.IntegerOverflow))))
 
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
index eb90867ae243..d83c5c5bb33f 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -1160,38 +1160,6 @@ impl MachInstEmit for Inst {
             &Inst::EBreak => {
                 sink.put4(0x00100073);
             }
-            &Inst::Icmp {
-                cc,
-                rd,
-                ref a,
-                ref b,
-                ty,
-            } => {
-                let a = alloc_value_regs(a, &mut allocs);
-                let b = alloc_value_regs(b, &mut allocs);
-                let rd = allocs.next_writable(rd);
-                let label_true = sink.get_label();
-                let label_false = sink.get_label();
-                Inst::lower_br_icmp(
-                    cc,
-                    a,
-                    b,
-                    BranchTarget::Label(label_true),
-                    BranchTarget::Label(label_false),
-                    ty,
-                )
-                .into_iter()
-                .for_each(|i| i.emit(&[], sink, emit_info, state));
-
-                sink.bind_label(label_true, &mut state.ctrl_plane);
-                Inst::load_imm12(rd, Imm12::TRUE).emit(&[], sink, emit_info, state);
-                Inst::Jal {
-                    dest: BranchTarget::offset(Inst::INSTRUCTION_SIZE * 2),
-                }
-                .emit(&[], sink, emit_info, state);
-                sink.bind_label(label_false, &mut state.ctrl_plane);
-                Inst::load_imm12(rd, Imm12::FALSE).emit(&[], sink, emit_info, state);
-            }
             &Inst::AtomicCas {
                 offset,
                 t0,
diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
index ea61641da3bb..9cb6eff3f1fd 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@@ -503,12 +503,6 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             collector.reg_def(rd);
         }
 
-        &Inst::Icmp { rd, a, b, .. } => {
-            collector.reg_uses(a.regs());
-            collector.reg_uses(b.regs());
-            collector.reg_def(rd);
-        }
-
         &Inst::SelectReg {
             rd,
             rs1,
@@ -1104,12 +1098,6 @@ impl Inst {
                     ty, dst, e, v, addr, t0, offset,
                 )
             }
-            &Inst::Icmp { cc, rd, a, b, ty } => {
-                let a = format_regs(a.regs(), allocs);
-                let b = format_regs(b.regs(), allocs);
-                let rd = format_reg(rd.to_reg(), allocs);
-                format!("{} {},{},{}##ty={}", cc.to_static_str(), rd, a, b, ty)
-            }
             &Inst::IntSelect {
                 op,
                 ref dst,
@@ -1187,6 +1175,15 @@ impl Inst {
                 let rs2_s = format_reg(rs2, allocs);
                 let rd_s = format_reg(rd.to_reg(), allocs);
                 match alu_op {
+                    AluOPRRR::Slt if rs2 == zero_reg() => {
+                        format!("sltz {},{}", rd_s, rs1_s)
+                    }
+                    AluOPRRR::Slt if rs1 == zero_reg() => {
+                        format!("sgtz {},{}", rd_s, rs2_s)
+                    }
+                    AluOPRRR::SltU if rs1 == zero_reg() => {
+                        format!("snez {},{}", rd_s, rs2_s)
+                    }
                     AluOPRRR::Adduw if rs2 == zero_reg() => {
                         format!("zext.w {},{}", rd_s, rs1_s)
                     }
diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle
index 6559b75bc81b..2164d8350c75 100644
--- a/cranelift/codegen/src/isa/riscv64/lower.isle
+++ b/cranelift/codegen/src/isa/riscv64/lower.isle
@@ -833,18 +833,18 @@
   (lower (store flags x @ (value_type $I128 ) p @ (value_type (ty_addr64 _)) offset))
   (gen_store_128 p offset flags x))
 
-(decl gen_icmp (IntCC ValueRegs ValueRegs Type) Reg)
-(rule
-  (gen_icmp cc x y ty)
-  (let
-    ((result WritableReg (temp_writable_reg $I64))
-      (_ Unit (emit (MInst.Icmp cc result x y ty))))
-    result))
-
 ;;;;;  Rules for `icmp`;;;;;;;;;
-(rule
-  (lower (icmp cc x @ (value_type ty) y))
-  (lower_icmp cc x y ty))
+(rule (lower (icmp cc x @ (value_type ty) y))
+  (gen_icmp cc x y ty))
+
+;; We have some optimizations that we can do when one of the sides is
+;; a constant.
+(rule 1 (lower (icmp cc x @ (value_type (fits_in_64 ty)) (u64_from_iconst y)))
+  (gen_icmp_imm cc x (i64_sextend_imm64 ty (imm64 y)) ty))
+
+;; If the const is on the LHS, move it to the right and flip the IntCC.
+(rule 2 (lower (icmp cc (u64_from_iconst x) y @ (value_type (fits_in_64 ty))))
+  (gen_icmp_imm (intcc_reverse cc) y (i64_sextend_imm64 ty (imm64 x)) ty))
 
 ;;;;;  Rules for `fcmp`;;;;;;;;;
 (rule
diff --git a/cranelift/codegen/src/isa/riscv64/lower/isle.rs b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
index 5a3195ee2164..95ff0947e5d7 100644
--- a/cranelift/codegen/src/isa/riscv64/lower/isle.rs
+++ b/cranelift/codegen/src/isa/riscv64/lower/isle.rs
@@ -102,7 +102,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
         targets: &VecMachLabel,
         ty: Type,
     ) -> Unit {
-        let test = generated_code::constructor_lower_icmp(self, cc, a, b, ty);
+        let test = generated_code::constructor_gen_icmp(self, cc, a, b, ty);
         self.emit(&MInst::CondBr {
             taken: BranchTarget::Label(targets[0]),
             not_taken: BranchTarget::Label(targets[1]),
@@ -159,9 +159,11 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
         }
         tmp.map(|r| r.to_reg())
     }
+
     fn imm12_and(&mut self, imm: Imm12, x: i32) -> Imm12 {
         Imm12::from_bits(imm.as_i16() & (x as i16))
     }
+
     fn alloc_vec_writable(&mut self, ty: Type) -> VecWritableReg {
         if ty.is_int() || ty == R32 || ty == R64 {
             if ty.bits() <= 64 {
@@ -195,6 +197,14 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12> {
         Imm12::maybe_from_u64(arg0)
     }
+
+    #[inline]
+    fn imm12_sextend_i64(&mut self, ty: Type, imm: i64) -> Option<Imm12> {
+        let shift_count = 64 - ty.bits();
+        let value = (imm << (shift_count)) >> (shift_count);
+        Imm12::maybe_from_u64(value as u64)
+    }
+
     #[inline]
     fn writable_zero_reg(&mut self) -> WritableReg {
         writable_zero_reg()
@@ -211,6 +221,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
     fn imm_from_bits(&mut self, val: u64) -> Imm12 {
         Imm12::maybe_from_u64(val).unwrap()
     }
+
     #[inline]
     fn imm_from_neg_bits(&mut self, val: i64) -> Imm12 {
         Imm12::maybe_from_u64(val as u64).unwrap()
diff --git a/cranelift/codegen/src/isle_prelude.rs b/cranelift/codegen/src/isle_prelude.rs
index d64973ce5b42..7640b58d9006 100644
--- a/cranelift/codegen/src/isle_prelude.rs
+++ b/cranelift/codegen/src/isle_prelude.rs
@@ -48,6 +48,11 @@ macro_rules! isle_common_prelude_methods {
             x.wrapping_neg()
         }
 
+        #[inline]
+        fn i64_add(&mut self, x: i64, y: i64) -> i64 {
+            x.wrapping_add(y)
+        }
+
         #[inline]
         fn u64_add(&mut self, x: u64, y: u64) -> u64 {
             x.wrapping_add(y)
@@ -726,6 +731,11 @@ macro_rules! isle_common_prelude_methods {
             x.unsigned()
         }
 
+        #[inline]
+        fn intcc_without_equal(&mut self, cc: &IntCC) -> IntCC {
+            cc.without_equal()
+        }
+
         #[inline]
         fn signed_cond_code(&mut self, cc: &condcodes::IntCC) -> Option<condcodes::IntCC> {
             match cc {
diff --git a/cranelift/codegen/src/prelude.isle b/cranelift/codegen/src/prelude.isle
index ad703ed8fe87..94b7bb8492d7 100644
--- a/cranelift/codegen/src/prelude.isle
+++ b/cranelift/codegen/src/prelude.isle
@@ -97,6 +97,9 @@
 (decl pure i64_neg (i64) i64)
 (extern constructor i64_neg i64_neg)
 
+(decl pure i64_add (i64 i64) i64)
+(extern constructor i64_add i64_add)
+
 (decl u128_as_u64 (u64) u128)
 (extern extractor u128_as_u64 u128_as_u64)
 
@@ -507,10 +510,23 @@
 (decl pure intcc_unsigned (IntCC) IntCC)
 (extern constructor intcc_unsigned intcc_unsigned)
 
+;; This is a direct import of `IntCC::without_equal`.
+;; Get the corresponding IntCC with the equal component removed.
+;; For conditions without an equal component, this is a no-op.
+(decl pure intcc_without_equal (IntCC) IntCC)
+(extern constructor intcc_without_equal intcc_without_equal)
+
 ;; Pure constructor that only matches signed integer cond codes.
 (decl pure partial signed_cond_code (IntCC) IntCC)
 (extern constructor signed_cond_code signed_cond_code)
 
+;; A constructor that maches any *GreaterThan or *GreaterThanOrEqual IntCC
+(decl pure partial intcc_greater_than (IntCC) Unit)
+(rule (intcc_greater_than (IntCC.SignedGreaterThan)) (unit))
+(rule (intcc_greater_than (IntCC.UnsignedGreaterThan)) (unit))
+(rule (intcc_greater_than (IntCC.SignedGreaterThanOrEqual)) (unit))
+(rule (intcc_greater_than (IntCC.UnsignedGreaterThanOrEqual)) (unit))
+
 ;;;; Helpers for Working with TrapCode ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (decl pure trap_code_division_by_zero () TrapCode)
diff --git a/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif b/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif
index 4952bc7196ec..28437bf8bb41 100644
--- a/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/arithmetic.clif
@@ -93,10 +93,12 @@ block0(v0: i64, v1: i64):
 ;   li a2,-1
 ;   li a3,1
 ;   slli a4,a3,63
-;   eq a6,a2,a1##ty=i64
-;   eq t3,a4,a0##ty=i64
-;   and t0,a6,t3
-;   trap_if t0,int_ovf
+;   xor a6,a2,a1
+;   seqz t3,a6
+;   xor t0,a4,a0
+;   seqz t2,t0
+;   and a2,t3,t2
+;   trap_if a2,int_ovf
 ;   trap_ifc int_divz##(zero eq a1)
 ;   div a0,a0,a1
 ;   ret
@@ -106,16 +108,12 @@ block0(v0: i64, v1: i64):
 ;   addi a2, zero, -1
 ;   addi a3, zero, 1
 ;   slli a4, a3, 0x3f
-;   bne a2, a1, 0xc
-;   addi a6, zero, 1
-;   j 8
-;   mv a6, zero
-;   bne a4, a0, 0xc
-;   addi t3, zero, 1
-;   j 8
-;   mv t3, zero
-;   and t0, a6, t3
-;   beqz t0, 8
+;   xor a6, a2, a1
+;   seqz t3, a6
+;   xor t0, a4, a0
+;   seqz t2, t0
+;   and a2, t3, t2
+;   beqz a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   bne zero, a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
@@ -131,38 +129,36 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li a6,2
+;   li t3,2
 ;   li a1,-1
 ;   li a2,1
 ;   slli a4,a2,63
-;   eq a7,a1,a6##ty=i64
-;   eq t3,a4,a0##ty=i64
-;   and t0,a7,t3
-;   trap_if t0,int_ovf
-;   trap_ifc int_divz##(zero eq a6)
-;   div a0,a0,a6
+;   xor a6,a1,t3
+;   seqz t4,a6
+;   xor t0,a4,a0
+;   seqz t2,t0
+;   and a1,t4,t2
+;   trap_if a1,int_ovf
+;   trap_ifc int_divz##(zero eq t3)
+;   div a0,a0,t3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a6, zero, 2
+;   addi t3, zero, 2
 ;   addi a1, zero, -1
 ;   addi a2, zero, 1
 ;   slli a4, a2, 0x3f
-;   bne a1, a6, 0xc
-;   addi a7, zero, 1
-;   j 8
-;   mv a7, zero
-;   bne a4, a0, 0xc
-;   addi t3, zero, 1
-;   j 8
-;   mv t3, zero
-;   and t0, a7, t3
-;   beqz t0, 8
+;   xor a6, a1, t3
+;   seqz t4, a6
+;   xor t0, a4, a0
+;   seqz t2, t0
+;   and a1, t4, t2
+;   beqz a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
-;   bne zero, a6, 8
+;   bne zero, t3, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   div a0, a0, a6
+;   div a0, a0, t3
 ;   ret
 
 function %f8(i64, i64) -> i64 {
@@ -258,10 +254,12 @@ block0(v0: i32, v1: i32):
 ;   li a6,1
 ;   slli t3,a6,63
 ;   slli t0,a0,32
-;   eq t2,a4,a2##ty=i32
-;   eq a1,t3,t0##ty=i32
-;   and a3,t2,a1
-;   trap_if a3,int_ovf
+;   xor t2,a4,a2
+;   seqz a1,t2
+;   xor a3,t3,t0
+;   seqz a5,a3
+;   and a7,a1,a5
+;   trap_if a7,int_ovf
 ;   trap_ifc int_divz##(zero eq a2)
 ;   divw a0,a0,a2
 ;   ret
@@ -274,16 +272,12 @@ block0(v0: i32, v1: i32):
 ;   addi a6, zero, 1
 ;   slli t3, a6, 0x3f
 ;   slli t0, a0, 0x20
-;   bne a4, a2, 0xc
-;   addi t2, zero, 1
-;   j 8
-;   mv t2, zero
-;   bne t3, t0, 0xc
-;   addi a1, zero, 1
-;   j 8
-;   mv a1, zero
-;   and a3, t2, a1
-;   beqz a3, 8
+;   xor t2, a4, a2
+;   seqz a1, t2
+;   xor a3, t3, t0
+;   seqz a5, a3
+;   and a7, a1, a5
+;   beqz a7, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   bne zero, a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
@@ -299,40 +293,38 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   li t4,2
+;   li t1,2
 ;   sext.w a0,a0
-;   sext.w a2,t4
+;   sext.w a2,t1
 ;   li a4,-1
 ;   li a6,1
 ;   slli t3,a6,63
 ;   slli t0,a0,32
-;   eq t2,a4,a2##ty=i32
-;   eq a1,t3,t0##ty=i32
-;   and a3,t2,a1
-;   trap_if a3,int_ovf
+;   xor t2,a4,a2
+;   seqz a1,t2
+;   xor a3,t3,t0
+;   seqz a5,a3
+;   and a7,a1,a5
+;   trap_if a7,int_ovf
 ;   trap_ifc int_divz##(zero eq a2)
 ;   divw a0,a0,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t4, zero, 2
+;   addi t1, zero, 2
 ;   sext.w a0, a0
-;   sext.w a2, t4
+;   sext.w a2, t1
 ;   addi a4, zero, -1
 ;   addi a6, zero, 1
 ;   slli t3, a6, 0x3f
 ;   slli t0, a0, 0x20
-;   bne a4, a2, 0xc
-;   addi t2, zero, 1
-;   j 8
-;   mv t2, zero
-;   bne t3, t0, 0xc
-;   addi a1, zero, 1
-;   j 8
-;   mv a1, zero
-;   and a3, t2, a1
-;   beqz a3, 8
+;   xor t2, a4, a2
+;   seqz a1, t2
+;   xor a3, t3, t0
+;   seqz a5, a3
+;   and a7, a1, a5
+;   beqz a7, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
 ;   bne zero, a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
@@ -848,37 +840,35 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li a6,-1
+;   li t3,-1
 ;   li a1,-1
 ;   li a2,1
 ;   slli a4,a2,63
-;   eq a7,a1,a6##ty=i64
-;   eq t3,a4,a0##ty=i64
-;   and t0,a7,t3
-;   trap_if t0,int_ovf
-;   trap_ifc int_divz##(zero eq a6)
-;   div a0,a0,a6
+;   xor a6,a1,t3
+;   seqz t4,a6
+;   xor t0,a4,a0
+;   seqz t2,t0
+;   and a1,t4,t2
+;   trap_if a1,int_ovf
+;   trap_ifc int_divz##(zero eq t3)
+;   div a0,a0,t3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a6, zero, -1
+;   addi t3, zero, -1
 ;   addi a1, zero, -1
 ;   addi a2, zero, 1
 ;   slli a4, a2, 0x3f
-;   bne a1, a6, 0xc
-;   addi a7, zero, 1
-;   j 8
-;   mv a7, zero
-;   bne a4, a0, 0xc
-;   addi t3, zero, 1
-;   j 8
-;   mv t3, zero
-;   and t0, a7, t3
-;   beqz t0, 8
+;   xor a6, a1, t3
+;   seqz t4, a6
+;   xor t0, a4, a0
+;   seqz t2, t0
+;   and a1, t4, t2
+;   beqz a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
-;   bne zero, a6, 8
+;   bne zero, t3, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   div a0, a0, a6
+;   div a0, a0, t3
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/condbr.clif b/cranelift/filetests/filetests/isa/riscv64/condbr.clif
index 617afdfe005b..10f88e8b972b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/condbr.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/condbr.clif
@@ -10,15 +10,14 @@ block0(v0: i64, v1: i64):
 
 ; VCode:
 ; block0:
-;   eq a0,a0,a1##ty=i64
+;   xor a0,a0,a1
+;   seqz a0,a0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a0, a1, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   xor a0, a0, a1
+;   seqz a0, a0
 ;   ret
 
 function %icmp_eq_i128(i128, i128) -> i8 {
@@ -29,16 +28,18 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   eq a0,[a0,a1],[a2,a3]##ty=i128
+;   xor a2,a0,a2
+;   xor a4,a1,a3
+;   or a6,a2,a4
+;   seqz a0,a6
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a1, a3, 0x10
-;   bne a0, a2, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   xor a2, a0, a2
+;   xor a4, a1, a3
+;   or a6, a2, a4
+;   seqz a0, a6
 ;   ret
 
 function %icmp_ne_i128(i128, i128) -> i8 {
@@ -49,16 +50,18 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   ne a0,[a0,a1],[a2,a3]##ty=i128
+;   xor a2,a0,a2
+;   xor a4,a1,a3
+;   or a6,a2,a4
+;   snez a0,a6
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a1, a3, 8
-;   beq a0, a2, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   xor a2, a0, a2
+;   xor a4, a1, a3
+;   or a6, a2, a4
+;   snez a0, a6
 ;   ret
 
 function %icmp_slt_i128(i128, i128) -> i8 {
@@ -69,17 +72,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   slt a0,[a0,a1],[a2,a3]##ty=i128
+;   mv a6,a2
+;   slt a2,a1,a3
+;   slt a4,a0,a6
+;   select_reg a0,a4,a2##condition=(a1 eq a3)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a0, zero, 1
+;   ori a6, a2, 0
+;   slt a2, a1, a3
+;   slt a4, a0, a6
+;   beq a1, a3, 0xc
+;   ori a0, a2, 0
 ;   j 8
-;   mv a0, zero
+;   ori a0, a4, 0
 ;   ret
 
 function %icmp_ult_i128(i128, i128) -> i8 {
@@ -90,17 +97,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   ult a0,[a0,a1],[a2,a3]##ty=i128
+;   mv a6,a2
+;   sltu a2,a1,a3
+;   slt a4,a0,a6
+;   select_reg a0,a4,a2##condition=(a1 eq a3)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a0, zero, 1
+;   ori a6, a2, 0
+;   sltu a2, a1, a3
+;   slt a4, a0, a6
+;   beq a1, a3, 0xc
+;   ori a0, a2, 0
 ;   j 8
-;   mv a0, zero
+;   ori a0, a4, 0
 ;   ret
 
 function %icmp_sle_i128(i128, i128) -> i8 {
@@ -111,17 +122,23 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   sle a0,[a0,a1],[a2,a3]##ty=i128
+;   mv a7,a2
+;   slt a2,a3,a1
+;   slt a4,a7,a0
+;   select_reg a6,a4,a2##condition=(a3 eq a1)
+;   xori a0,a6,1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bltu a2, a0, 0xc
-;   addi a0, zero, 1
+;   ori a7, a2, 0
+;   slt a2, a3, a1
+;   slt a4, a7, a0
+;   beq a3, a1, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a0, zero
+;   ori a6, a4, 0
+;   xori a0, a6, 1
 ;   ret
 
 function %icmp_ule_i128(i128, i128) -> i8 {
@@ -132,17 +149,23 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   ule a0,[a0,a1],[a2,a3]##ty=i128
+;   mv a7,a2
+;   sltu a2,a3,a1
+;   slt a4,a7,a0
+;   select_reg a6,a4,a2##condition=(a3 eq a1)
+;   xori a0,a6,1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bltu a2, a0, 0xc
-;   addi a0, zero, 1
+;   ori a7, a2, 0
+;   sltu a2, a3, a1
+;   slt a4, a7, a0
+;   beq a3, a1, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a0, zero
+;   ori a6, a4, 0
+;   xori a0, a6, 1
 ;   ret
 
 function %icmp_sgt_i128(i128, i128) -> i8 {
@@ -153,17 +176,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   sgt a0,[a0,a1],[a2,a3]##ty=i128
+;   mv a6,a2
+;   slt a2,a3,a1
+;   slt a4,a6,a0
+;   select_reg a0,a4,a2##condition=(a3 eq a1)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a0, zero, 1
+;   ori a6, a2, 0
+;   slt a2, a3, a1
+;   slt a4, a6, a0
+;   beq a3, a1, 0xc
+;   ori a0, a2, 0
 ;   j 8
-;   mv a0, zero
+;   ori a0, a4, 0
 ;   ret
 
 function %icmp_ugt_i128(i128, i128) -> i8 {
@@ -174,17 +201,21 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   ugt a0,[a0,a1],[a2,a3]##ty=i128
+;   mv a6,a2
+;   sltu a2,a3,a1
+;   slt a4,a6,a0
+;   select_reg a0,a4,a2##condition=(a3 eq a1)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a0, zero, 1
+;   ori a6, a2, 0
+;   sltu a2, a3, a1
+;   slt a4, a6, a0
+;   beq a3, a1, 0xc
+;   ori a0, a2, 0
 ;   j 8
-;   mv a0, zero
+;   ori a0, a4, 0
 ;   ret
 
 function %icmp_sge_i128(i128, i128) -> i8 {
@@ -195,17 +226,23 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   sge a0,[a0,a1],[a2,a3]##ty=i128
+;   mv a7,a2
+;   slt a2,a1,a3
+;   slt a4,a0,a7
+;   select_reg a6,a4,a2##condition=(a1 eq a3)
+;   xori a0,a6,1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bltu a0, a2, 0xc
-;   addi a0, zero, 1
+;   ori a7, a2, 0
+;   slt a2, a1, a3
+;   slt a4, a0, a7
+;   beq a1, a3, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a0, zero
+;   ori a6, a4, 0
+;   xori a0, a6, 1
 ;   ret
 
 function %icmp_uge_i128(i128, i128) -> i8 {
@@ -216,17 +253,23 @@ block0(v0: i128, v1: i128):
 
 ; VCode:
 ; block0:
-;   uge a0,[a0,a1],[a2,a3]##ty=i128
+;   mv a7,a2
+;   sltu a2,a1,a3
+;   slt a4,a0,a7
+;   select_reg a6,a4,a2##condition=(a1 eq a3)
+;   xori a0,a6,1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bltu a0, a2, 0xc
-;   addi a0, zero, 1
+;   ori a7, a2, 0
+;   sltu a2, a1, a3
+;   slt a4, a0, a7
+;   beq a1, a3, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a0, zero
+;   ori a6, a4, 0
+;   xori a0, a6, 1
 ;   ret
 
 function %f(i64, i64) -> i64 {
@@ -245,8 +288,9 @@ block2:
 
 ; VCode:
 ; block0:
-;   eq a2,a0,a1##ty=i64
-;   bne a2,zero,taken(label2),not_taken(label1)
+;   xor a2,a0,a1
+;   seqz a4,a2
+;   bne a4,zero,taken(label2),not_taken(label1)
 ; block1:
 ;   li a0,2
 ;   ret
@@ -256,15 +300,13 @@ block2:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a0, a1, 0xc
-;   addi a2, zero, 1
-;   j 8
-;   mv a2, zero
-;   bnez a2, 0xc
-; block1: ; offset 0x14
+;   xor a2, a0, a1
+;   seqz a4, a2
+;   bnez a4, 0xc
+; block1: ; offset 0xc
 ;   addi a0, zero, 2
 ;   ret
-; block2: ; offset 0x1c
+; block2: ; offset 0x14
 ;   addi a0, zero, 1
 ;   ret
 
@@ -280,8 +322,9 @@ block1:
 
 ; VCode:
 ; block0:
-;   eq a1,a0,a1##ty=i64
-;   bne a1,zero,taken(label1),not_taken(label2)
+;   xor a1,a0,a1
+;   seqz a3,a1
+;   bne a3,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -292,11 +335,9 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a0, a1, 0xc
-;   addi a1, zero, 1
-;   j 8
-;   mv a1, zero
-; block1: ; offset 0x10
+;   xor a1, a0, a1
+;   seqz a3, a1
+; block1: ; offset 0x8
 ;   addi a0, zero, 1
 ;   ret
 
@@ -311,8 +352,11 @@ block1:
 
 ; VCode:
 ; block0:
-;   ne a0,[a0,a1],[zerozero]##ty=i128
-;   bne a0,zero,taken(label1),not_taken(label2)
+;   xor a0,a0,zero
+;   xor a2,a1,zero
+;   or a4,a0,a2
+;   snez a6,a4
+;   bne a6,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -322,12 +366,11 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bnez a1, 8
-;   beqz a0, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-; block1: ; offset 0x14
+;   xor a0, a0, zero
+;   xor a2, a1, zero
+;   or a4, a0, a2
+;   snez a6, a4
+; block1: ; offset 0x10
 ;   ret
 
 function %i128_bricmp_eq(i128, i128) {
@@ -341,8 +384,11 @@ block1:
 
 ; VCode:
 ; block0:
-;   eq a2,[a0,a1],[a2,a3]##ty=i128
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   xor a2,a0,a2
+;   xor a4,a1,a3
+;   or a6,a2,a4
+;   seqz t3,a6
+;   bne t3,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -352,12 +398,11 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a1, a3, 0x10
-;   bne a0, a2, 0xc
-;   addi a2, zero, 1
-;   j 8
-;   mv a2, zero
-; block1: ; offset 0x14
+;   xor a2, a0, a2
+;   xor a4, a1, a3
+;   or a6, a2, a4
+;   seqz t3, a6
+; block1: ; offset 0x10
 ;   ret
 
 function %i128_bricmp_ne(i128, i128) {
@@ -371,8 +416,11 @@ block1:
 
 ; VCode:
 ; block0:
-;   ne a2,[a0,a1],[a2,a3]##ty=i128
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   xor a2,a0,a2
+;   xor a4,a1,a3
+;   or a6,a2,a4
+;   snez t3,a6
+;   bne t3,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -382,12 +430,11 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bne a1, a3, 8
-;   beq a0, a2, 0xc
-;   addi a2, zero, 1
-;   j 8
-;   mv a2, zero
-; block1: ; offset 0x14
+;   xor a2, a0, a2
+;   xor a4, a1, a3
+;   or a6, a2, a4
+;   snez t3, a6
+; block1: ; offset 0x10
 ;   ret
 
 function %i128_bricmp_slt(i128, i128) {
@@ -401,8 +448,11 @@ block1:
 
 ; VCode:
 ; block0:
-;   slt a2,[a0,a1],[a2,a3]##ty=i128
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   mv a6,a2
+;   slt a2,a1,a3
+;   slt a4,a0,a6
+;   select_reg a6,a4,a2##condition=(a1 eq a3)
+;   bne a6,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -412,13 +462,14 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a2, zero, 1
+;   ori a6, a2, 0
+;   slt a2, a1, a3
+;   slt a4, a0, a6
+;   beq a1, a3, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a2, zero
-; block1: ; offset 0x18
+;   ori a6, a4, 0
+; block1: ; offset 0x1c
 ;   ret
 
 function %i128_bricmp_ult(i128, i128) {
@@ -432,8 +483,11 @@ block1:
 
 ; VCode:
 ; block0:
-;   ult a2,[a0,a1],[a2,a3]##ty=i128
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   mv a6,a2
+;   sltu a2,a1,a3
+;   slt a4,a0,a6
+;   select_reg a6,a4,a2##condition=(a1 eq a3)
+;   bne a6,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -443,13 +497,14 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a0, a2, 0xc
-;   addi a2, zero, 1
+;   ori a6, a2, 0
+;   sltu a2, a1, a3
+;   slt a4, a0, a6
+;   beq a1, a3, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a2, zero
-; block1: ; offset 0x18
+;   ori a6, a4, 0
+; block1: ; offset 0x1c
 ;   ret
 
 function %i128_bricmp_sle(i128, i128) {
@@ -463,8 +518,12 @@ block1:
 
 ; VCode:
 ; block0:
-;   sle a2,[a0,a1],[a2,a3]##ty=i128
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   mv a7,a2
+;   slt a2,a3,a1
+;   slt a4,a7,a0
+;   select_reg a6,a4,a2##condition=(a3 eq a1)
+;   xori t3,a6,1
+;   bne t3,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -474,13 +533,15 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bltu a2, a0, 0xc
-;   addi a2, zero, 1
+;   ori a7, a2, 0
+;   slt a2, a3, a1
+;   slt a4, a7, a0
+;   beq a3, a1, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a2, zero
-; block1: ; offset 0x18
+;   ori a6, a4, 0
+;   xori t3, a6, 1
+; block1: ; offset 0x20
 ;   ret
 
 function %i128_bricmp_ule(i128, i128) {
@@ -494,8 +555,12 @@ block1:
 
 ; VCode:
 ; block0:
-;   ule a2,[a0,a1],[a2,a3]##ty=i128
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   mv a7,a2
+;   sltu a2,a3,a1
+;   slt a4,a7,a0
+;   select_reg a6,a4,a2##condition=(a3 eq a1)
+;   xori t3,a6,1
+;   bne t3,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -505,13 +570,15 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a1, a3, 0xc
-;   bne a1, a3, 0x10
-;   bltu a2, a0, 0xc
-;   addi a2, zero, 1
+;   ori a7, a2, 0
+;   sltu a2, a3, a1
+;   slt a4, a7, a0
+;   beq a3, a1, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a2, zero
-; block1: ; offset 0x18
+;   ori a6, a4, 0
+;   xori t3, a6, 1
+; block1: ; offset 0x20
 ;   ret
 
 function %i128_bricmp_sgt(i128, i128) {
@@ -525,8 +592,11 @@ block1:
 
 ; VCode:
 ; block0:
-;   sgt a2,[a0,a1],[a2,a3]##ty=i128
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   mv a6,a2
+;   slt a2,a3,a1
+;   slt a4,a6,a0
+;   select_reg a6,a4,a2##condition=(a3 eq a1)
+;   bne a6,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -536,13 +606,14 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a2, zero, 1
+;   ori a6, a2, 0
+;   slt a2, a3, a1
+;   slt a4, a6, a0
+;   beq a3, a1, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a2, zero
-; block1: ; offset 0x18
+;   ori a6, a4, 0
+; block1: ; offset 0x1c
 ;   ret
 
 function %i128_bricmp_ugt(i128, i128) {
@@ -556,8 +627,11 @@ block1:
 
 ; VCode:
 ; block0:
-;   ugt a2,[a0,a1],[a2,a3]##ty=i128
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   mv a6,a2
+;   sltu a2,a3,a1
+;   slt a4,a6,a0
+;   select_reg a6,a4,a2##condition=(a3 eq a1)
+;   bne a6,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -567,13 +641,14 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bgeu a2, a0, 0xc
-;   addi a2, zero, 1
+;   ori a6, a2, 0
+;   sltu a2, a3, a1
+;   slt a4, a6, a0
+;   beq a3, a1, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a2, zero
-; block1: ; offset 0x18
+;   ori a6, a4, 0
+; block1: ; offset 0x1c
 ;   ret
 
 function %i128_bricmp_sge(i128, i128) {
@@ -587,8 +662,12 @@ block1:
 
 ; VCode:
 ; block0:
-;   sge a2,[a0,a1],[a2,a3]##ty=i128
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   mv a7,a2
+;   slt a2,a1,a3
+;   slt a4,a0,a7
+;   select_reg a6,a4,a2##condition=(a1 eq a3)
+;   xori t3,a6,1
+;   bne t3,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -598,13 +677,15 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   blt a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bltu a0, a2, 0xc
-;   addi a2, zero, 1
+;   ori a7, a2, 0
+;   slt a2, a1, a3
+;   slt a4, a0, a7
+;   beq a1, a3, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a2, zero
-; block1: ; offset 0x18
+;   ori a6, a4, 0
+;   xori t3, a6, 1
+; block1: ; offset 0x20
 ;   ret
 
 function %i128_bricmp_uge(i128, i128) {
@@ -618,8 +699,12 @@ block1:
 
 ; VCode:
 ; block0:
-;   uge a2,[a0,a1],[a2,a3]##ty=i128
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   mv a7,a2
+;   sltu a2,a1,a3
+;   slt a4,a0,a7
+;   select_reg a6,a4,a2##condition=(a1 eq a3)
+;   xori t3,a6,1
+;   bne t3,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -629,13 +714,15 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   bltu a3, a1, 0xc
-;   bne a1, a3, 0x10
-;   bltu a0, a2, 0xc
-;   addi a2, zero, 1
+;   ori a7, a2, 0
+;   sltu a2, a1, a3
+;   slt a4, a0, a7
+;   beq a1, a3, 0xc
+;   ori a6, a2, 0
 ;   j 8
-;   mv a2, zero
-; block1: ; offset 0x18
+;   ori a6, a4, 0
+;   xori t3, a6, 1
+; block1: ; offset 0x20
 ;   ret
 
 function %i8_brif(i8){
diff --git a/cranelift/filetests/filetests/isa/riscv64/condops.clif b/cranelift/filetests/filetests/isa/riscv64/condops.clif
index 2ac8dd6af5ca..cb2e8f2fb0a7 100644
--- a/cranelift/filetests/filetests/isa/riscv64/condops.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/condops.clif
@@ -38,21 +38,20 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   li a2,42
-;   andi a0,a0,255
-;   andi a2,a2,255
-;   eq a0,a0,a2##ty=i8
+;   andi t2,a0,255
+;   li a1,42
+;   andi a3,a1,255
+;   xor a5,t2,a3
+;   seqz a0,a5
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a2, zero, 0x2a
-;   andi a0, a0, 0xff
-;   andi a2, a2, 0xff
-;   bne a0, a2, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   andi t2, a0, 0xff
+;   addi a1, zero, 0x2a
+;   andi a3, a1, 0xff
+;   xor a5, t2, a3
+;   seqz a0, a5
 ;   ret
 
 function %h(i8, i8, i8) -> i8 {
diff --git a/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif b/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif
index 54573373b0bf..0f6907cd4c95 100644
--- a/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif
@@ -11,7 +11,7 @@ block0(v0: i128):
 ; VCode:
 ; block0:
 ;   or a0,a0,a1
-;   sltu a2,zero,a0
+;   snez a2,a0
 ;   sub a1,zero,a2
 ;   mv a0,a1
 ;   ret
@@ -33,7 +33,7 @@ block0(v0: i128):
 ; VCode:
 ; block0:
 ;   or a0,a0,a1
-;   sltu a2,zero,a0
+;   snez a2,a0
 ;   sub a0,zero,a2
 ;   ret
 ; 
@@ -53,7 +53,7 @@ block0(v0: i128):
 ; VCode:
 ; block0:
 ;   or a0,a0,a1
-;   sltu a2,zero,a0
+;   snez a2,a0
 ;   sub a0,zero,a2
 ;   ret
 ; 
@@ -73,7 +73,7 @@ block0(v0: i128):
 ; VCode:
 ; block0:
 ;   or a0,a0,a1
-;   sltu a2,zero,a0
+;   snez a2,a0
 ;   sub a0,zero,a2
 ;   ret
 ; 
@@ -93,7 +93,7 @@ block0(v0: i128):
 ; VCode:
 ; block0:
 ;   or a0,a0,a1
-;   sltu a2,zero,a0
+;   snez a2,a0
 ;   sub a0,zero,a2
 ;   ret
 ; 
@@ -112,7 +112,7 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   sltu t2,zero,a0
+;   snez t2,a0
 ;   sub a1,zero,t2
 ;   mv a0,a1
 ;   ret
@@ -134,7 +134,7 @@ block0(v0: i32):
 ; block0:
 ;   slli t2,a0,32
 ;   srli a1,t2,32
-;   sltu a3,zero,a1
+;   snez a3,a1
 ;   sub a1,zero,a3
 ;   mv a0,a1
 ;   ret
@@ -158,7 +158,7 @@ block0(v0: i16):
 ; block0:
 ;   slli t2,a0,48
 ;   srli a1,t2,48
-;   sltu a3,zero,a1
+;   snez a3,a1
 ;   sub a1,zero,a3
 ;   mv a0,a1
 ;   ret
@@ -181,7 +181,7 @@ block0(v0: i8):
 ; VCode:
 ; block0:
 ;   andi t2,a0,255
-;   sltu a1,zero,t2
+;   snez a1,t2
 ;   sub a1,zero,a1
 ;   mv a0,a1
 ;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/icmp-i128.clif b/cranelift/filetests/filetests/isa/riscv64/icmp-i128.clif
new file mode 100644
index 000000000000..7769deb2ef8b
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/riscv64/icmp-i128.clif
@@ -0,0 +1,255 @@
+test compile precise-output
+target riscv64
+
+function %icmp_eq_i128(i128, i128) -> i8 {
+block0(v0: i128, v1: i128):
+  v2 = icmp.i128 eq v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   xor a2,a0,a2
+;   xor a4,a1,a3
+;   or a6,a2,a4
+;   seqz a0,a6
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xor a2, a0, a2
+;   xor a4, a1, a3
+;   or a6, a2, a4
+;   seqz a0, a6
+;   ret
+
+function %icmp_ne_i128(i128, i128) -> i8 {
+block0(v0: i128, v1: i128):
+  v2 = icmp.i128 ne v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   xor a2,a0,a2
+;   xor a4,a1,a3
+;   or a6,a2,a4
+;   snez a0,a6
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xor a2, a0, a2
+;   xor a4, a1, a3
+;   or a6, a2, a4
+;   snez a0, a6
+;   ret
+
+function %icmp_slt_i128(i128, i128) -> i8 {
+block0(v0: i128, v1: i128):
+  v2 = icmp.i128 slt v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   mv a6,a2
+;   slt a2,a1,a3
+;   slt a4,a0,a6
+;   select_reg a0,a4,a2##condition=(a1 eq a3)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a6, a2, 0
+;   slt a2, a1, a3
+;   slt a4, a0, a6
+;   beq a1, a3, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, a4, 0
+;   ret
+
+function %icmp_sgt_i128(i128, i128) -> i8 {
+block0(v0: i128, v1: i128):
+  v2 = icmp.i128 sgt v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   mv a6,a2
+;   slt a2,a3,a1
+;   slt a4,a6,a0
+;   select_reg a0,a4,a2##condition=(a3 eq a1)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a6, a2, 0
+;   slt a2, a3, a1
+;   slt a4, a6, a0
+;   beq a3, a1, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, a4, 0
+;   ret
+
+function %icmp_sle_i128(i128, i128) -> i8 {
+block0(v0: i128, v1: i128):
+  v2 = icmp.i128 sle v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   mv a7,a2
+;   slt a2,a3,a1
+;   slt a4,a7,a0
+;   select_reg a6,a4,a2##condition=(a3 eq a1)
+;   xori a0,a6,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a7, a2, 0
+;   slt a2, a3, a1
+;   slt a4, a7, a0
+;   beq a3, a1, 0xc
+;   ori a6, a2, 0
+;   j 8
+;   ori a6, a4, 0
+;   xori a0, a6, 1
+;   ret
+
+function %icmp_sge_i128(i128, i128) -> i8 {
+block0(v0: i128, v1: i128):
+  v2 = icmp.i128 sge v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   mv a7,a2
+;   slt a2,a1,a3
+;   slt a4,a0,a7
+;   select_reg a6,a4,a2##condition=(a1 eq a3)
+;   xori a0,a6,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a7, a2, 0
+;   slt a2, a1, a3
+;   slt a4, a0, a7
+;   beq a1, a3, 0xc
+;   ori a6, a2, 0
+;   j 8
+;   ori a6, a4, 0
+;   xori a0, a6, 1
+;   ret
+
+function %icmp_ult_i128(i128, i128) -> i8 {
+block0(v0: i128, v1: i128):
+  v2 = icmp.i128 ult v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   mv a6,a2
+;   sltu a2,a1,a3
+;   slt a4,a0,a6
+;   select_reg a0,a4,a2##condition=(a1 eq a3)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a6, a2, 0
+;   sltu a2, a1, a3
+;   slt a4, a0, a6
+;   beq a1, a3, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, a4, 0
+;   ret
+
+function %icmp_ugt_i128(i128, i128) -> i8 {
+block0(v0: i128, v1: i128):
+  v2 = icmp.i128 ugt v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   mv a6,a2
+;   sltu a2,a3,a1
+;   slt a4,a6,a0
+;   select_reg a0,a4,a2##condition=(a3 eq a1)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a6, a2, 0
+;   sltu a2, a3, a1
+;   slt a4, a6, a0
+;   beq a3, a1, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, a4, 0
+;   ret
+
+function %icmp_ule_i128(i128, i128) -> i8 {
+block0(v0: i128, v1: i128):
+  v2 = icmp.i128 ule v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   mv a7,a2
+;   sltu a2,a3,a1
+;   slt a4,a7,a0
+;   select_reg a6,a4,a2##condition=(a3 eq a1)
+;   xori a0,a6,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a7, a2, 0
+;   sltu a2, a3, a1
+;   slt a4, a7, a0
+;   beq a3, a1, 0xc
+;   ori a6, a2, 0
+;   j 8
+;   ori a6, a4, 0
+;   xori a0, a6, 1
+;   ret
+
+function %icmp_uge_i128(i128, i128) -> i8 {
+block0(v0: i128, v1: i128):
+  v2 = icmp.i128 uge v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   mv a7,a2
+;   sltu a2,a1,a3
+;   slt a4,a0,a7
+;   select_reg a6,a4,a2##condition=(a1 eq a3)
+;   xori a0,a6,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   ori a7, a2, 0
+;   sltu a2, a1, a3
+;   slt a4, a0, a7
+;   beq a1, a3, 0xc
+;   ori a6, a2, 0
+;   j 8
+;   ori a6, a4, 0
+;   xori a0, a6, 1
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/riscv64/icmp-imm-i128.clif b/cranelift/filetests/filetests/isa/riscv64/icmp-imm-i128.clif
new file mode 100644
index 000000000000..aad97d55cbff
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/riscv64/icmp-imm-i128.clif
@@ -0,0 +1,299 @@
+test compile precise-output
+target riscv64
+
+function %icmp_eq_i128_imm(i128) -> i8 {
+block0(v0: i128):
+  v1 = iconst.i64 42
+  v2 = uextend.i128 v1
+  v3 = icmp.i128 eq v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   li a5,42
+;   li a6,0
+;   xor a2,a0,a5
+;   xor a4,a1,a6
+;   or a6,a2,a4
+;   seqz a0,a6
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a5, zero, 0x2a
+;   mv a6, zero
+;   xor a2, a0, a5
+;   xor a4, a1, a6
+;   or a6, a2, a4
+;   seqz a0, a6
+;   ret
+
+function %icmp_ne_i128_imm(i128) -> i8 {
+block0(v0: i128):
+  v1 = iconst.i64 42
+  v2 = uextend.i128 v1
+  v3 = icmp.i128 ne v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   li a5,42
+;   li a6,0
+;   xor a2,a0,a5
+;   xor a4,a1,a6
+;   or a6,a2,a4
+;   snez a0,a6
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a5, zero, 0x2a
+;   mv a6, zero
+;   xor a2, a0, a5
+;   xor a4, a1, a6
+;   or a6, a2, a4
+;   snez a0, a6
+;   ret
+
+function %icmp_slt_i128_imm(i128) -> i8 {
+block0(v0: i128):
+  v1 = iconst.i64 42
+  v2 = uextend.i128 v1
+  v3 = icmp.i128 slt v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   li a4,42
+;   li a5,0
+;   slt a2,a1,a5
+;   slt a4,a0,a4
+;   select_reg a0,a4,a2##condition=(a1 eq a5)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a4, zero, 0x2a
+;   mv a5, zero
+;   slt a2, a1, a5
+;   slt a4, a0, a4
+;   beq a1, a5, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, a4, 0
+;   ret
+
+function %icmp_sgt_i128_imm(i128) -> i8 {
+block0(v0: i128):
+  v1 = iconst.i64 42
+  v2 = uextend.i128 v1
+  v3 = icmp.i128 sgt v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   li a4,42
+;   li a5,0
+;   slt a2,a5,a1
+;   slt a4,a4,a0
+;   select_reg a0,a4,a2##condition=(a5 eq a1)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a4, zero, 0x2a
+;   mv a5, zero
+;   slt a2, a5, a1
+;   slt a4, a4, a0
+;   beq a5, a1, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, a4, 0
+;   ret
+
+function %icmp_sle_i128_imm(i128) -> i8 {
+block0(v0: i128):
+  v1 = iconst.i64 42
+  v2 = uextend.i128 v1
+  v3 = icmp.i128 sle v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   li a5,42
+;   li a6,0
+;   slt a2,a6,a1
+;   slt a4,a5,a0
+;   select_reg a6,a4,a2##condition=(a6 eq a1)
+;   xori a0,a6,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a5, zero, 0x2a
+;   mv a6, zero
+;   slt a2, a6, a1
+;   slt a4, a5, a0
+;   beq a6, a1, 0xc
+;   ori a6, a2, 0
+;   j 8
+;   ori a6, a4, 0
+;   xori a0, a6, 1
+;   ret
+
+function %icmp_sge_i128_imm(i128) -> i8 {
+block0(v0: i128):
+  v1 = iconst.i64 42
+  v2 = uextend.i128 v1
+  v3 = icmp.i128 sge v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   li a5,42
+;   li a6,0
+;   slt a2,a1,a6
+;   slt a4,a0,a5
+;   select_reg a6,a4,a2##condition=(a1 eq a6)
+;   xori a0,a6,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a5, zero, 0x2a
+;   mv a6, zero
+;   slt a2, a1, a6
+;   slt a4, a0, a5
+;   beq a1, a6, 0xc
+;   ori a6, a2, 0
+;   j 8
+;   ori a6, a4, 0
+;   xori a0, a6, 1
+;   ret
+
+function %icmp_ult_i128_imm(i128) -> i8 {
+block0(v0: i128):
+  v1 = iconst.i64 42
+  v2 = uextend.i128 v1
+  v3 = icmp.i128 ult v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   li a4,42
+;   li a5,0
+;   sltu a2,a1,a5
+;   slt a4,a0,a4
+;   select_reg a0,a4,a2##condition=(a1 eq a5)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a4, zero, 0x2a
+;   mv a5, zero
+;   sltu a2, a1, a5
+;   slt a4, a0, a4
+;   beq a1, a5, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, a4, 0
+;   ret
+
+function %icmp_ugt_i128_imm(i128) -> i8 {
+block0(v0: i128):
+  v1 = iconst.i64 42
+  v2 = uextend.i128 v1
+  v3 = icmp.i128 ugt v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   li a4,42
+;   li a5,0
+;   sltu a2,a5,a1
+;   slt a4,a4,a0
+;   select_reg a0,a4,a2##condition=(a5 eq a1)
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a4, zero, 0x2a
+;   mv a5, zero
+;   sltu a2, a5, a1
+;   slt a4, a4, a0
+;   beq a5, a1, 0xc
+;   ori a0, a2, 0
+;   j 8
+;   ori a0, a4, 0
+;   ret
+
+function %icmp_ule_i128_imm(i128) -> i8 {
+block0(v0: i128):
+  v1 = iconst.i64 42
+  v2 = uextend.i128 v1
+  v3 = icmp.i128 ule v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   li a5,42
+;   li a6,0
+;   sltu a2,a6,a1
+;   slt a4,a5,a0
+;   select_reg a6,a4,a2##condition=(a6 eq a1)
+;   xori a0,a6,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a5, zero, 0x2a
+;   mv a6, zero
+;   sltu a2, a6, a1
+;   slt a4, a5, a0
+;   beq a6, a1, 0xc
+;   ori a6, a2, 0
+;   j 8
+;   ori a6, a4, 0
+;   xori a0, a6, 1
+;   ret
+
+function %icmp_uge_i128_imm(i128) -> i8 {
+block0(v0: i128):
+  v1 = iconst.i64 42
+  v2 = uextend.i128 v1
+  v3 = icmp.i128 uge v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   li a5,42
+;   li a6,0
+;   sltu a2,a1,a6
+;   slt a4,a0,a5
+;   select_reg a6,a4,a2##condition=(a1 eq a6)
+;   xori a0,a6,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a5, zero, 0x2a
+;   mv a6, zero
+;   sltu a2, a1, a6
+;   slt a4, a0, a5
+;   beq a1, a6, 0xc
+;   ori a6, a2, 0
+;   j 8
+;   ori a6, a4, 0
+;   xori a0, a6, 1
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/riscv64/icmp-imm.clif b/cranelift/filetests/filetests/isa/riscv64/icmp-imm.clif
new file mode 100644
index 000000000000..0fcd7911dc8f
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/riscv64/icmp-imm.clif
@@ -0,0 +1,1043 @@
+test compile precise-output
+target riscv64
+
+
+function %icmp_eq_i8_imm(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 42
+    v2 = icmp eq v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi t2,a0,255
+;   li a1,42
+;   andi a3,a1,255
+;   xor a5,t2,a3
+;   seqz a0,a5
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi t2, a0, 0xff
+;   addi a1, zero, 0x2a
+;   andi a3, a1, 0xff
+;   xor a5, t2, a3
+;   seqz a0, a5
+;   ret
+
+function %icmp_eq_i16_imm(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 42
+    v2 = icmp eq v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srli a1,t2,48
+;   li a3,42
+;   slli a5,a3,48
+;   srli a7,a5,48
+;   xor t4,a1,a7
+;   seqz a0,t4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srli a1, t2, 0x30
+;   addi a3, zero, 0x2a
+;   slli a5, a3, 0x30
+;   srli a7, a5, 0x30
+;   xor t4, a1, a7
+;   seqz a0, t4
+;   ret
+
+function %icmp_eq_i32_imm(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 42
+    v2 = icmp eq v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w t2,a0
+;   li a1,42
+;   sext.w a3,a1
+;   xor a5,t2,a3
+;   seqz a0,a5
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w t2, a0
+;   addi a1, zero, 0x2a
+;   sext.w a3, a1
+;   xor a5, t2, a3
+;   seqz a0, a5
+;   ret
+
+function %icmp_eq_i64_imm(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp eq v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   li t2,42
+;   xor a1,a0,t2
+;   seqz a0,a1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 0x2a
+;   xor a1, a0, t2
+;   seqz a0, a1
+;   ret
+
+function %icmp_ne_i8_imm(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 42
+    v2 = icmp ne v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi t2,a0,255
+;   li a1,42
+;   andi a3,a1,255
+;   xor a5,t2,a3
+;   snez a0,a5
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi t2, a0, 0xff
+;   addi a1, zero, 0x2a
+;   andi a3, a1, 0xff
+;   xor a5, t2, a3
+;   snez a0, a5
+;   ret
+
+function %icmp_ne_i16_imm(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 42
+    v2 = icmp ne v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srli a1,t2,48
+;   li a3,42
+;   slli a5,a3,48
+;   srli a7,a5,48
+;   xor t4,a1,a7
+;   snez a0,t4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srli a1, t2, 0x30
+;   addi a3, zero, 0x2a
+;   slli a5, a3, 0x30
+;   srli a7, a5, 0x30
+;   xor t4, a1, a7
+;   snez a0, t4
+;   ret
+
+function %icmp_ne_i32_imm(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 42
+    v2 = icmp ne v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w t2,a0
+;   li a1,42
+;   sext.w a3,a1
+;   xor a5,t2,a3
+;   snez a0,a5
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w t2, a0
+;   addi a1, zero, 0x2a
+;   sext.w a3, a1
+;   xor a5, t2, a3
+;   snez a0, a5
+;   ret
+
+function %icmp_ne_i64_imm(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp ne v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   li t2,42
+;   xor a1,a0,t2
+;   snez a0,a1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t2, zero, 0x2a
+;   xor a1, a0, t2
+;   snez a0, a1
+;   ret
+
+function %icmp_sge_i8_imm(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 42
+    v2 = icmp sge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,56
+;   srai a1,t2,56
+;   slti a3,a1,42
+;   xori a0,a3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai a1, t2, 0x38
+;   slti a3, a1, 0x2a
+;   xori a0, a3, 1
+;   ret
+
+function %icmp_sge_i16_imm(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 42
+    v2 = icmp sge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srai a1,t2,48
+;   slti a3,a1,42
+;   xori a0,a3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai a1, t2, 0x30
+;   slti a3, a1, 0x2a
+;   xori a0, a3, 1
+;   ret
+
+function %icmp_sge_i32_imm(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 42
+    v2 = icmp sge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w t2,a0
+;   slti a1,t2,42
+;   xori a0,a1,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w t2, a0
+;   slti a1, t2, 0x2a
+;   xori a0, a1, 1
+;   ret
+
+function %icmp_sge_i64_imm(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp sge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slti t2,a0,42
+;   xori a0,t2,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slti t2, a0, 0x2a
+;   xori a0, t2, 1
+;   ret
+
+function %icmp_sgt_i8_imm(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 42
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,56
+;   srai a1,t2,56
+;   slti a3,a1,43
+;   xori a0,a3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai a1, t2, 0x38
+;   slti a3, a1, 0x2b
+;   xori a0, a3, 1
+;   ret
+
+function %icmp_sgt_i16_imm(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 42
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srai a1,t2,48
+;   slti a3,a1,43
+;   xori a0,a3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai a1, t2, 0x30
+;   slti a3, a1, 0x2b
+;   xori a0, a3, 1
+;   ret
+
+function %icmp_sgt_i32_imm(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 42
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w t2,a0
+;   slti a1,t2,43
+;   xori a0,a1,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w t2, a0
+;   slti a1, t2, 0x2b
+;   xori a0, a1, 1
+;   ret
+
+function %icmp_sgt_i64_imm(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slti t2,a0,43
+;   xori a0,t2,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slti t2, a0, 0x2b
+;   xori a0, t2, 1
+;   ret
+
+function %icmp_sle_i8_imm(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 42
+    v2 = icmp sle v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,56
+;   srai a1,t2,56
+;   slti a0,a1,43
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai a1, t2, 0x38
+;   slti a0, a1, 0x2b
+;   ret
+
+function %icmp_sle_i16_imm(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 42
+    v2 = icmp sle v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srai a1,t2,48
+;   slti a0,a1,43
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai a1, t2, 0x30
+;   slti a0, a1, 0x2b
+;   ret
+
+function %icmp_sle_i32_imm(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 42
+    v2 = icmp sle v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w t2,a0
+;   slti a0,t2,43
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w t2, a0
+;   slti a0, t2, 0x2b
+;   ret
+
+function %icmp_sle_i64_imm(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp sle v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slti a0,a0,43
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slti a0, a0, 0x2b
+;   ret
+
+function %icmp_slt_i8_imm(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 42
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,56
+;   srai a1,t2,56
+;   slti a0,a1,42
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai a1, t2, 0x38
+;   slti a0, a1, 0x2a
+;   ret
+
+function %icmp_slt_i16_imm(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 42
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srai a1,t2,48
+;   slti a0,a1,42
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai a1, t2, 0x30
+;   slti a0, a1, 0x2a
+;   ret
+
+function %icmp_slt_i32_imm(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 42
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w t2,a0
+;   slti a0,t2,42
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w t2, a0
+;   slti a0, t2, 0x2a
+;   ret
+
+function %icmp_slt_i64_imm(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slti a0,a0,42
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slti a0, a0, 0x2a
+;   ret
+
+function %icmp_uge_i8_imm(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 42
+    v2 = icmp uge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi t2,a0,255
+;   sltiu a1,t2,42
+;   xori a0,a1,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi t2, a0, 0xff
+;   sltiu a1, t2, 0x2a
+;   xori a0, a1, 1
+;   ret
+
+function %icmp_uge_i16_imm(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 42
+    v2 = icmp uge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srli a1,t2,48
+;   sltiu a3,a1,42
+;   xori a0,a3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srli a1, t2, 0x30
+;   sltiu a3, a1, 0x2a
+;   xori a0, a3, 1
+;   ret
+
+function %icmp_uge_i32_imm(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 42
+    v2 = icmp uge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,32
+;   srli a1,t2,32
+;   sltiu a3,a1,42
+;   xori a0,a3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srli a1, t2, 0x20
+;   sltiu a3, a1, 0x2a
+;   xori a0, a3, 1
+;   ret
+
+function %icmp_uge_i64_imm(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp uge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltiu t2,a0,42
+;   xori a0,t2,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sltiu t2, a0, 0x2a
+;   xori a0, t2, 1
+;   ret
+
+function %icmp_ugt_i8_imm(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 42
+    v2 = icmp ugt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi t2,a0,255
+;   sltiu a1,t2,43
+;   xori a0,a1,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi t2, a0, 0xff
+;   sltiu a1, t2, 0x2b
+;   xori a0, a1, 1
+;   ret
+
+function %icmp_ugt_i16_imm(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 42
+    v2 = icmp ugt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srli a1,t2,48
+;   sltiu a3,a1,43
+;   xori a0,a3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srli a1, t2, 0x30
+;   sltiu a3, a1, 0x2b
+;   xori a0, a3, 1
+;   ret
+
+function %icmp_ugt_i32_imm(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 42
+    v2 = icmp ugt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,32
+;   srli a1,t2,32
+;   sltiu a3,a1,43
+;   xori a0,a3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srli a1, t2, 0x20
+;   sltiu a3, a1, 0x2b
+;   xori a0, a3, 1
+;   ret
+
+function %icmp_ugt_i64_imm(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp ugt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltiu t2,a0,43
+;   xori a0,t2,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sltiu t2, a0, 0x2b
+;   xori a0, t2, 1
+;   ret
+
+function %icmp_ule_i8_imm(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 42
+    v2 = icmp ule v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi t2,a0,255
+;   sltiu a0,t2,43
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi t2, a0, 0xff
+;   sltiu a0, t2, 0x2b
+;   ret
+
+function %icmp_ule_i16_imm(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 42
+    v2 = icmp ule v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srli a1,t2,48
+;   sltiu a0,a1,43
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srli a1, t2, 0x30
+;   sltiu a0, a1, 0x2b
+;   ret
+
+function %icmp_ule_i32_imm(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 42
+    v2 = icmp ule v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,32
+;   srli a1,t2,32
+;   sltiu a0,a1,43
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srli a1, t2, 0x20
+;   sltiu a0, a1, 0x2b
+;   ret
+
+function %icmp_ule_i64_imm(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp ule v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltiu a0,a0,43
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sltiu a0, a0, 0x2b
+;   ret
+
+function %icmp_ult_i8_imm(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 42
+    v2 = icmp ult v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi t2,a0,255
+;   sltiu a0,t2,42
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi t2, a0, 0xff
+;   sltiu a0, t2, 0x2a
+;   ret
+
+function %icmp_ult_i16_imm(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 42
+    v2 = icmp ult v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srli a1,t2,48
+;   sltiu a0,a1,42
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srli a1, t2, 0x30
+;   sltiu a0, a1, 0x2a
+;   ret
+
+function %icmp_ult_i32_imm(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 42
+    v2 = icmp ult v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,32
+;   srli a1,t2,32
+;   sltiu a0,a1,42
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x20
+;   srli a1, t2, 0x20
+;   sltiu a0, a1, 0x2a
+;   ret
+
+function %icmp_ult_i64_imm(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp ult v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltiu a0,a0,42
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sltiu a0, a0, 0x2a
+;   ret
+
+function %icmp_slt_i8_imm_0(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 0
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,56
+;   srai a1,t2,56
+;   sltz a0,a1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai a1, t2, 0x38
+;   sltz a0, a1
+;   ret
+
+function %icmp_slt_i16_imm_0(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 0
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srai a1,t2,48
+;   sltz a0,a1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai a1, t2, 0x30
+;   sltz a0, a1
+;   ret
+
+function %icmp_slt_i32_imm_0(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 0
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w t2,a0
+;   sltz a0,t2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w t2, a0
+;   sltz a0, t2
+;   ret
+
+function %icmp_slt_i64_imm_0(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 0
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltz a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sltz a0, a0
+;   ret
+
+
+
+function %icmp_sgt_i8_imm_0(i8) -> i8 {
+block0(v0: i8):
+    v1 = iconst.i8 0
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,56
+;   srai a1,t2,56
+;   sgtz a0,a1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x38
+;   srai a1, t2, 0x38
+;   sgtz a0, a1
+;   ret
+
+function %icmp_sgt_i16_imm_0(i16) -> i8 {
+block0(v0: i16):
+    v1 = iconst.i16 0
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli t2,a0,48
+;   srai a1,t2,48
+;   sgtz a0,a1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli t2, a0, 0x30
+;   srai a1, t2, 0x30
+;   sgtz a0, a1
+;   ret
+
+function %icmp_sgt_i32_imm_0(i32) -> i8 {
+block0(v0: i32):
+    v1 = iconst.i32 0
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w t2,a0
+;   sgtz a0,t2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w t2, a0
+;   sgtz a0, t2
+;   ret
+
+function %icmp_sgt_i64_imm_0(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 0
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sgtz a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sgtz a0, a0
+;   ret
+
+
+
+
+
+;;; Special cases
+
+;; This tests that we still optimize when the const is the lhs
+function %icmp_slt_i64_imm_lhs(i64) -> i8 {
+block0(v0: i64):
+    v1 = iconst.i64 42
+    v2 = icmp slt v1, v0
+    return v2
+}
+
+; VCode:
+; block0:
+;   slti t2,a0,43
+;   xori a0,t2,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slti t2, a0, 0x2b
+;   xori a0, t2, 1
+;   ret
\ No newline at end of file
diff --git a/cranelift/filetests/filetests/isa/riscv64/icmp.clif b/cranelift/filetests/filetests/isa/riscv64/icmp.clif
new file mode 100644
index 000000000000..153b1151844d
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/riscv64/icmp.clif
@@ -0,0 +1,884 @@
+test compile precise-output
+target riscv64
+
+
+function %icmp_eq_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+    v2 = icmp eq v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   andi a2,a1,255
+;   xor a4,a0,a2
+;   seqz a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   andi a2, a1, 0xff
+;   xor a4, a0, a2
+;   seqz a0, a4
+;   ret
+
+function %icmp_eq_i16(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+    v2 = icmp eq v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,48
+;   srli a2,a0,48
+;   slli a4,a1,48
+;   srli a6,a4,48
+;   xor t3,a2,a6
+;   seqz a0,t3
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a2, a0, 0x30
+;   slli a4, a1, 0x30
+;   srli a6, a4, 0x30
+;   xor t3, a2, a6
+;   seqz a0, t3
+;   ret
+
+function %icmp_eq_i32(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+    v2 = icmp eq v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w a0,a0
+;   sext.w a2,a1
+;   xor a4,a0,a2
+;   seqz a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w a0, a0
+;   sext.w a2, a1
+;   xor a4, a0, a2
+;   seqz a0, a4
+;   ret
+
+function %icmp_eq_i64(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = icmp eq v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   xor a0,a0,a1
+;   seqz a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xor a0, a0, a1
+;   seqz a0, a0
+;   ret
+
+function %icmp_ne_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+    v2 = icmp ne v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   andi a2,a1,255
+;   xor a4,a0,a2
+;   snez a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   andi a2, a1, 0xff
+;   xor a4, a0, a2
+;   snez a0, a4
+;   ret
+
+function %icmp_ne_i16(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+    v2 = icmp ne v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,48
+;   srli a2,a0,48
+;   slli a4,a1,48
+;   srli a6,a4,48
+;   xor t3,a2,a6
+;   snez a0,t3
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a2, a0, 0x30
+;   slli a4, a1, 0x30
+;   srli a6, a4, 0x30
+;   xor t3, a2, a6
+;   snez a0, t3
+;   ret
+
+function %icmp_ne_i32(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+    v2 = icmp ne v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w a0,a0
+;   sext.w a2,a1
+;   xor a4,a0,a2
+;   snez a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w a0, a0
+;   sext.w a2, a1
+;   xor a4, a0, a2
+;   snez a0, a4
+;   ret
+
+function %icmp_ne_i64(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = icmp ne v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   xor a0,a0,a1
+;   snez a0,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   xor a0, a0, a1
+;   snez a0, a0
+;   ret
+
+function %icmp_sge_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+    v2 = icmp sge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,56
+;   srai a2,a0,56
+;   slli a4,a1,56
+;   srai a6,a4,56
+;   slt t3,a2,a6
+;   xori a0,t3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a2, a0, 0x38
+;   slli a4, a1, 0x38
+;   srai a6, a4, 0x38
+;   slt t3, a2, a6
+;   xori a0, t3, 1
+;   ret
+
+function %icmp_sge_i16(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+    v2 = icmp sge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,48
+;   srai a2,a0,48
+;   slli a4,a1,48
+;   srai a6,a4,48
+;   slt t3,a2,a6
+;   xori a0,t3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srai a2, a0, 0x30
+;   slli a4, a1, 0x30
+;   srai a6, a4, 0x30
+;   slt t3, a2, a6
+;   xori a0, t3, 1
+;   ret
+
+function %icmp_sge_i32(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+    v2 = icmp sge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w a0,a0
+;   sext.w a2,a1
+;   slt a4,a0,a2
+;   xori a0,a4,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w a0, a0
+;   sext.w a2, a1
+;   slt a4, a0, a2
+;   xori a0, a4, 1
+;   ret
+
+function %icmp_sge_i64(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = icmp sge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slt a0,a0,a1
+;   xori a0,a0,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slt a0, a0, a1
+;   xori a0, a0, 1
+;   ret
+
+function %icmp_sgt_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,56
+;   srai a2,a0,56
+;   slli a4,a1,56
+;   srai a6,a4,56
+;   slt a0,a6,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a2, a0, 0x38
+;   slli a4, a1, 0x38
+;   srai a6, a4, 0x38
+;   slt a0, a6, a2
+;   ret
+
+function %icmp_sgt_i16(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,48
+;   srai a2,a0,48
+;   slli a4,a1,48
+;   srai a6,a4,48
+;   slt a0,a6,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srai a2, a0, 0x30
+;   slli a4, a1, 0x30
+;   srai a6, a4, 0x30
+;   slt a0, a6, a2
+;   ret
+
+function %icmp_sgt_i32(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w a0,a0
+;   sext.w a2,a1
+;   slt a0,a2,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w a0, a0
+;   sext.w a2, a1
+;   slt a0, a2, a0
+;   ret
+
+function %icmp_sgt_i64(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = icmp sgt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slt a0,a1,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slt a0, a1, a0
+;   ret
+
+function %icmp_sle_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+    v2 = icmp sle v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,56
+;   srai a2,a0,56
+;   slli a4,a1,56
+;   srai a6,a4,56
+;   slt t3,a6,a2
+;   xori a0,t3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a2, a0, 0x38
+;   slli a4, a1, 0x38
+;   srai a6, a4, 0x38
+;   slt t3, a6, a2
+;   xori a0, t3, 1
+;   ret
+
+function %icmp_sle_i16(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+    v2 = icmp sle v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,48
+;   srai a2,a0,48
+;   slli a4,a1,48
+;   srai a6,a4,48
+;   slt t3,a6,a2
+;   xori a0,t3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srai a2, a0, 0x30
+;   slli a4, a1, 0x30
+;   srai a6, a4, 0x30
+;   slt t3, a6, a2
+;   xori a0, t3, 1
+;   ret
+
+function %icmp_sle_i32(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+    v2 = icmp sle v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w a0,a0
+;   sext.w a2,a1
+;   slt a4,a2,a0
+;   xori a0,a4,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w a0, a0
+;   sext.w a2, a1
+;   slt a4, a2, a0
+;   xori a0, a4, 1
+;   ret
+
+function %icmp_sle_i64(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = icmp sle v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slt a0,a1,a0
+;   xori a0,a0,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slt a0, a1, a0
+;   xori a0, a0, 1
+;   ret
+
+function %icmp_slt_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,56
+;   srai a2,a0,56
+;   slli a4,a1,56
+;   srai a6,a4,56
+;   slt a0,a2,a6
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x38
+;   srai a2, a0, 0x38
+;   slli a4, a1, 0x38
+;   srai a6, a4, 0x38
+;   slt a0, a2, a6
+;   ret
+
+function %icmp_slt_i16(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,48
+;   srai a2,a0,48
+;   slli a4,a1,48
+;   srai a6,a4,48
+;   slt a0,a2,a6
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srai a2, a0, 0x30
+;   slli a4, a1, 0x30
+;   srai a6, a4, 0x30
+;   slt a0, a2, a6
+;   ret
+
+function %icmp_slt_i32(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sext.w a0,a0
+;   sext.w a2,a1
+;   slt a0,a0,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sext.w a0, a0
+;   sext.w a2, a1
+;   slt a0, a0, a2
+;   ret
+
+function %icmp_slt_i64(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = icmp slt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slt a0,a0,a1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slt a0, a0, a1
+;   ret
+
+function %icmp_uge_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+    v2 = icmp uge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   andi a2,a1,255
+;   sltu a4,a0,a2
+;   xori a0,a4,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   andi a2, a1, 0xff
+;   sltu a4, a0, a2
+;   xori a0, a4, 1
+;   ret
+
+function %icmp_uge_i16(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+    v2 = icmp uge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,48
+;   srli a2,a0,48
+;   slli a4,a1,48
+;   srli a6,a4,48
+;   sltu t3,a2,a6
+;   xori a0,t3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a2, a0, 0x30
+;   slli a4, a1, 0x30
+;   srli a6, a4, 0x30
+;   sltu t3, a2, a6
+;   xori a0, t3, 1
+;   ret
+
+function %icmp_uge_i32(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+    v2 = icmp uge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,32
+;   srli a2,a0,32
+;   slli a4,a1,32
+;   srli a6,a4,32
+;   sltu t3,a2,a6
+;   xori a0,t3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srli a2, a0, 0x20
+;   slli a4, a1, 0x20
+;   srli a6, a4, 0x20
+;   sltu t3, a2, a6
+;   xori a0, t3, 1
+;   ret
+
+function %icmp_uge_i64(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = icmp uge v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltu a0,a0,a1
+;   xori a0,a0,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sltu a0, a0, a1
+;   xori a0, a0, 1
+;   ret
+
+function %icmp_ugt_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+    v2 = icmp ugt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   andi a2,a1,255
+;   sltu a0,a2,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   andi a2, a1, 0xff
+;   sltu a0, a2, a0
+;   ret
+
+function %icmp_ugt_i16(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+    v2 = icmp ugt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,48
+;   srli a2,a0,48
+;   slli a4,a1,48
+;   srli a6,a4,48
+;   sltu a0,a6,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a2, a0, 0x30
+;   slli a4, a1, 0x30
+;   srli a6, a4, 0x30
+;   sltu a0, a6, a2
+;   ret
+
+function %icmp_ugt_i32(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+    v2 = icmp ugt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,32
+;   srli a2,a0,32
+;   slli a4,a1,32
+;   srli a6,a4,32
+;   sltu a0,a6,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srli a2, a0, 0x20
+;   slli a4, a1, 0x20
+;   srli a6, a4, 0x20
+;   sltu a0, a6, a2
+;   ret
+
+function %icmp_ugt_i64(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = icmp ugt v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltu a0,a1,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sltu a0, a1, a0
+;   ret
+
+function %icmp_ule_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+    v2 = icmp ule v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   andi a2,a1,255
+;   sltu a4,a2,a0
+;   xori a0,a4,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   andi a2, a1, 0xff
+;   sltu a4, a2, a0
+;   xori a0, a4, 1
+;   ret
+
+function %icmp_ule_i16(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+    v2 = icmp ule v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,48
+;   srli a2,a0,48
+;   slli a4,a1,48
+;   srli a6,a4,48
+;   sltu t3,a6,a2
+;   xori a0,t3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a2, a0, 0x30
+;   slli a4, a1, 0x30
+;   srli a6, a4, 0x30
+;   sltu t3, a6, a2
+;   xori a0, t3, 1
+;   ret
+
+function %icmp_ule_i32(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+    v2 = icmp ule v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,32
+;   srli a2,a0,32
+;   slli a4,a1,32
+;   srli a6,a4,32
+;   sltu t3,a6,a2
+;   xori a0,t3,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srli a2, a0, 0x20
+;   slli a4, a1, 0x20
+;   srli a6, a4, 0x20
+;   sltu t3, a6, a2
+;   xori a0, t3, 1
+;   ret
+
+function %icmp_ule_i64(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = icmp ule v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltu a0,a1,a0
+;   xori a0,a0,1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sltu a0, a1, a0
+;   xori a0, a0, 1
+;   ret
+
+function %icmp_ult_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+    v2 = icmp ult v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   andi a0,a0,255
+;   andi a2,a1,255
+;   sltu a0,a0,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   andi a0, a0, 0xff
+;   andi a2, a1, 0xff
+;   sltu a0, a0, a2
+;   ret
+
+function %icmp_ult_i16(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+    v2 = icmp ult v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,48
+;   srli a2,a0,48
+;   slli a4,a1,48
+;   srli a6,a4,48
+;   sltu a0,a2,a6
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x30
+;   srli a2, a0, 0x30
+;   slli a4, a1, 0x30
+;   srli a6, a4, 0x30
+;   sltu a0, a2, a6
+;   ret
+
+function %icmp_ult_i32(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+    v2 = icmp ult v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   slli a0,a0,32
+;   srli a2,a0,32
+;   slli a4,a1,32
+;   srli a6,a4,32
+;   sltu a0,a2,a6
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   slli a0, a0, 0x20
+;   srli a2, a0, 0x20
+;   slli a4, a1, 0x20
+;   srli a6, a4, 0x20
+;   sltu a0, a2, a6
+;   ret
+
+function %icmp_ult_i64(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+    v2 = icmp ult v0, v1
+    return v2
+}
+
+; VCode:
+; block0:
+;   sltu a0,a0,a1
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   sltu a0, a0, a1
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif b/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
index 4b259c88f1c2..b54ff889087b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif
@@ -12,26 +12,29 @@ block0:
 
 ; VCode:
 ; block0:
-;   lui a3,14
-;   addi a3,a3,3532
-;   slli t2,a3,48
+;   lui a6,14
+;   addi a6,a6,3532
+;   slli t2,a6,48
 ;   srli a1,t2,48
-;   slli a3,a3,48
-;   srli a5,a3,48
-;   ne a0,a1,a5##ty=i16
+;   lui a4,1048574
+;   addi a4,a4,3532
+;   slli a7,a4,48
+;   srli t4,a7,48
+;   xor t1,a1,t4
+;   snez a0,t1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lui a3, 0xe
-;   addi a3, a3, -0x234
-;   slli t2, a3, 0x30
+;   lui a6, 0xe
+;   addi a6, a6, -0x234
+;   slli t2, a6, 0x30
 ;   srli a1, t2, 0x30
-;   slli a3, a3, 0x30
-;   srli a5, a3, 0x30
-;   beq a1, a5, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
+;   lui a4, 0xffffe
+;   addi a4, a4, -0x234
+;   slli a7, a4, 0x30
+;   srli t4, a7, 0x30
+;   xor t1, a1, t4
+;   snez a0, t1
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif b/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
index cceaedf594bf..5f72945a3dce 100644
--- a/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
@@ -12,35 +12,34 @@ block0(v0: i8, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   li t1,42
-;   andi t4,a0,255
-;   andi t1,t1,255
-;   eq a0,t4,t1##ty=i8
-;   andi a5,a0,255
-;   sltu a7,zero,a5
-;   sub t4,zero,a7
-;   and t1,a1,t4
-;   not a0,t4
-;   and a2,a2,a0
-;   or a0,t1,a2
+;   andi t3,a0,255
+;   li t0,42
+;   andi t2,t0,255
+;   xor a3,t3,t2
+;   seqz a3,a3
+;   andi a6,a3,255
+;   snez t3,a6
+;   sub t0,zero,t3
+;   and t2,a1,t0
+;   not a1,t0
+;   and a3,a2,a1
+;   or a0,t2,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t1, zero, 0x2a
-;   andi t4, a0, 0xff
-;   andi t1, t1, 0xff
-;   bne t4, t1, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   andi a5, a0, 0xff
-;   snez a7, a5
-;   neg t4, a7
-;   and t1, a1, t4
-;   not a0, t4
-;   and a2, a2, a0
-;   or a0, t1, a2
+;   andi t3, a0, 0xff
+;   addi t0, zero, 0x2a
+;   andi t2, t0, 0xff
+;   xor a3, t3, t2
+;   seqz a3, a3
+;   andi a6, a3, 0xff
+;   snez t3, a6
+;   neg t0, t3
+;   and t2, a1, t0
+;   not a1, t0
+;   and a3, a2, a1
+;   or a0, t2, a3
 ;   ret
 
 function %f(i8, i16, i16) -> i16 {
@@ -53,35 +52,34 @@ block0(v0: i8, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   li t1,42
-;   andi t4,a0,255
-;   andi t1,t1,255
-;   eq a0,t4,t1##ty=i8
-;   andi a5,a0,255
-;   sltu a7,zero,a5
-;   sub t4,zero,a7
-;   and t1,a1,t4
-;   not a0,t4
-;   and a2,a2,a0
-;   or a0,t1,a2
+;   andi t3,a0,255
+;   li t0,42
+;   andi t2,t0,255
+;   xor a3,t3,t2
+;   seqz a3,a3
+;   andi a6,a3,255
+;   snez t3,a6
+;   sub t0,zero,t3
+;   and t2,a1,t0
+;   not a1,t0
+;   and a3,a2,a1
+;   or a0,t2,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t1, zero, 0x2a
-;   andi t4, a0, 0xff
-;   andi t1, t1, 0xff
-;   bne t4, t1, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   andi a5, a0, 0xff
-;   snez a7, a5
-;   neg t4, a7
-;   and t1, a1, t4
-;   not a0, t4
-;   and a2, a2, a0
-;   or a0, t1, a2
+;   andi t3, a0, 0xff
+;   addi t0, zero, 0x2a
+;   andi t2, t0, 0xff
+;   xor a3, t3, t2
+;   seqz a3, a3
+;   andi a6, a3, 0xff
+;   snez t3, a6
+;   neg t0, t3
+;   and t2, a1, t0
+;   not a1, t0
+;   and a3, a2, a1
+;   or a0, t2, a3
 ;   ret
 
 function %f(i8, i32, i32) -> i32 {
@@ -94,35 +92,34 @@ block0(v0: i8, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   li t1,42
-;   andi t4,a0,255
-;   andi t1,t1,255
-;   eq a0,t4,t1##ty=i8
-;   andi a5,a0,255
-;   sltu a7,zero,a5
-;   sub t4,zero,a7
-;   and t1,a1,t4
-;   not a0,t4
-;   and a2,a2,a0
-;   or a0,t1,a2
+;   andi t3,a0,255
+;   li t0,42
+;   andi t2,t0,255
+;   xor a3,t3,t2
+;   seqz a3,a3
+;   andi a6,a3,255
+;   snez t3,a6
+;   sub t0,zero,t3
+;   and t2,a1,t0
+;   not a1,t0
+;   and a3,a2,a1
+;   or a0,t2,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t1, zero, 0x2a
-;   andi t4, a0, 0xff
-;   andi t1, t1, 0xff
-;   bne t4, t1, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   andi a5, a0, 0xff
-;   snez a7, a5
-;   neg t4, a7
-;   and t1, a1, t4
-;   not a0, t4
-;   and a2, a2, a0
-;   or a0, t1, a2
+;   andi t3, a0, 0xff
+;   addi t0, zero, 0x2a
+;   andi t2, t0, 0xff
+;   xor a3, t3, t2
+;   seqz a3, a3
+;   andi a6, a3, 0xff
+;   snez t3, a6
+;   neg t0, t3
+;   and t2, a1, t0
+;   not a1, t0
+;   and a3, a2, a1
+;   or a0, t2, a3
 ;   ret
 
 function %f(i8, i64, i64) -> i64 {
@@ -135,35 +132,34 @@ block0(v0: i8, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   li t1,42
-;   andi t4,a0,255
-;   andi t1,t1,255
-;   eq a0,t4,t1##ty=i8
-;   andi a5,a0,255
-;   sltu a7,zero,a5
-;   sub t4,zero,a7
-;   and t1,a1,t4
-;   not a0,t4
-;   and a2,a2,a0
-;   or a0,t1,a2
+;   andi t3,a0,255
+;   li t0,42
+;   andi t2,t0,255
+;   xor a3,t3,t2
+;   seqz a3,a3
+;   andi a6,a3,255
+;   snez t3,a6
+;   sub t0,zero,t3
+;   and t2,a1,t0
+;   not a1,t0
+;   and a3,a2,a1
+;   or a0,t2,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t1, zero, 0x2a
-;   andi t4, a0, 0xff
-;   andi t1, t1, 0xff
-;   bne t4, t1, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   andi a5, a0, 0xff
-;   snez a7, a5
-;   neg t4, a7
-;   and t1, a1, t4
-;   not a0, t4
-;   and a2, a2, a0
-;   or a0, t1, a2
+;   andi t3, a0, 0xff
+;   addi t0, zero, 0x2a
+;   andi t2, t0, 0xff
+;   xor a3, t3, t2
+;   seqz a3, a3
+;   andi a6, a3, 0xff
+;   snez t3, a6
+;   neg t0, t3
+;   and t2, a1, t0
+;   not a1, t0
+;   and a3, a2, a1
+;   or a0, t2, a3
 ;   ret
 
 function %f(i8, i128, i128) -> i128 {
@@ -176,43 +172,42 @@ block0(v0: i8, v1: i128, v2: i128):
 
 ; VCode:
 ; block0:
-;   li a5,42
-;   andi a6,a0,255
-;   andi a5,a5,255
-;   eq a6,a6,a5##ty=i8
-;   andi a7,a6,255
-;   sltu t4,zero,a7
-;   sub t1,zero,t4
-;   and a0,a1,t1
-;   and a2,a2,t1
-;   not a5,t1
-;   not a6,t1
-;   and t3,a3,a5
-;   and t0,a4,a6
-;   or a0,a0,t3
-;   or a1,a2,t0
+;   andi a5,a0,255
+;   li a6,42
+;   andi a6,a6,255
+;   xor a7,a5,a6
+;   seqz t4,a7
+;   andi t3,t4,255
+;   snez t0,t3
+;   sub t2,zero,t0
+;   and a1,a1,t2
+;   and a5,a2,t2
+;   not a6,t2
+;   not a7,t2
+;   and t4,a3,a6
+;   and t1,a4,a7
+;   or a0,a1,t4
+;   or a1,a5,t1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a5, zero, 0x2a
-;   andi a6, a0, 0xff
-;   andi a5, a5, 0xff
-;   bne a6, a5, 0xc
-;   addi a6, zero, 1
-;   j 8
-;   mv a6, zero
-;   andi a7, a6, 0xff
-;   snez t4, a7
-;   neg t1, t4
-;   and a0, a1, t1
-;   and a2, a2, t1
-;   not a5, t1
-;   not a6, t1
-;   and t3, a3, a5
-;   and t0, a4, a6
-;   or a0, a0, t3
-;   or a1, a2, t0
+;   andi a5, a0, 0xff
+;   addi a6, zero, 0x2a
+;   andi a6, a6, 0xff
+;   xor a7, a5, a6
+;   seqz t4, a7
+;   andi t3, t4, 0xff
+;   snez t0, t3
+;   neg t2, t0
+;   and a1, a1, t2
+;   and a5, a2, t2
+;   not a6, t2
+;   not a7, t2
+;   and t4, a3, a6
+;   and t1, a4, a7
+;   or a0, a1, t4
+;   or a1, a5, t1
 ;   ret
 
 function %f(i16, i8, i8) -> i8 {
@@ -225,39 +220,38 @@ block0(v0: i16, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli t4,a0,48
-;   srli t1,t4,48
-;   slli a0,a3,48
-;   srli a3,a0,48
-;   eq a4,t1,a3##ty=i16
-;   andi a7,a4,255
-;   sltu t4,zero,a7
-;   sub t1,zero,t4
-;   and a0,a1,t1
-;   not a3,t1
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   slli t3,a0,48
+;   srli t0,t3,48
+;   li t2,42
+;   slli a3,t2,48
+;   srli a3,a3,48
+;   xor a5,t0,a3
+;   seqz a7,a5
+;   andi t3,a7,255
+;   snez t0,t3
+;   sub t2,zero,t0
+;   and a1,a1,t2
+;   not a3,t2
+;   and a5,a2,a3
+;   or a0,a1,a5
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli t4, a0, 0x30
-;   srli t1, t4, 0x30
-;   slli a0, a3, 0x30
-;   srli a3, a0, 0x30
-;   bne t1, a3, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   andi a7, a4, 0xff
-;   snez t4, a7
-;   neg t1, t4
-;   and a0, a1, t1
-;   not a3, t1
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   slli t3, a0, 0x30
+;   srli t0, t3, 0x30
+;   addi t2, zero, 0x2a
+;   slli a3, t2, 0x30
+;   srli a3, a3, 0x30
+;   xor a5, t0, a3
+;   seqz a7, a5
+;   andi t3, a7, 0xff
+;   snez t0, t3
+;   neg t2, t0
+;   and a1, a1, t2
+;   not a3, t2
+;   and a5, a2, a3
+;   or a0, a1, a5
 ;   ret
 
 function %f(i16, i16, i16) -> i16 {
@@ -270,39 +264,38 @@ block0(v0: i16, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli t4,a0,48
-;   srli t1,t4,48
-;   slli a0,a3,48
-;   srli a3,a0,48
-;   eq a4,t1,a3##ty=i16
-;   andi a7,a4,255
-;   sltu t4,zero,a7
-;   sub t1,zero,t4
-;   and a0,a1,t1
-;   not a3,t1
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   slli t3,a0,48
+;   srli t0,t3,48
+;   li t2,42
+;   slli a3,t2,48
+;   srli a3,a3,48
+;   xor a5,t0,a3
+;   seqz a7,a5
+;   andi t3,a7,255
+;   snez t0,t3
+;   sub t2,zero,t0
+;   and a1,a1,t2
+;   not a3,t2
+;   and a5,a2,a3
+;   or a0,a1,a5
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli t4, a0, 0x30
-;   srli t1, t4, 0x30
-;   slli a0, a3, 0x30
-;   srli a3, a0, 0x30
-;   bne t1, a3, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   andi a7, a4, 0xff
-;   snez t4, a7
-;   neg t1, t4
-;   and a0, a1, t1
-;   not a3, t1
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   slli t3, a0, 0x30
+;   srli t0, t3, 0x30
+;   addi t2, zero, 0x2a
+;   slli a3, t2, 0x30
+;   srli a3, a3, 0x30
+;   xor a5, t0, a3
+;   seqz a7, a5
+;   andi t3, a7, 0xff
+;   snez t0, t3
+;   neg t2, t0
+;   and a1, a1, t2
+;   not a3, t2
+;   and a5, a2, a3
+;   or a0, a1, a5
 ;   ret
 
 function %f(i16, i32, i32) -> i32 {
@@ -315,39 +308,38 @@ block0(v0: i16, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli t4,a0,48
-;   srli t1,t4,48
-;   slli a0,a3,48
-;   srli a3,a0,48
-;   eq a4,t1,a3##ty=i16
-;   andi a7,a4,255
-;   sltu t4,zero,a7
-;   sub t1,zero,t4
-;   and a0,a1,t1
-;   not a3,t1
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   slli t3,a0,48
+;   srli t0,t3,48
+;   li t2,42
+;   slli a3,t2,48
+;   srli a3,a3,48
+;   xor a5,t0,a3
+;   seqz a7,a5
+;   andi t3,a7,255
+;   snez t0,t3
+;   sub t2,zero,t0
+;   and a1,a1,t2
+;   not a3,t2
+;   and a5,a2,a3
+;   or a0,a1,a5
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli t4, a0, 0x30
-;   srli t1, t4, 0x30
-;   slli a0, a3, 0x30
-;   srli a3, a0, 0x30
-;   bne t1, a3, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   andi a7, a4, 0xff
-;   snez t4, a7
-;   neg t1, t4
-;   and a0, a1, t1
-;   not a3, t1
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   slli t3, a0, 0x30
+;   srli t0, t3, 0x30
+;   addi t2, zero, 0x2a
+;   slli a3, t2, 0x30
+;   srli a3, a3, 0x30
+;   xor a5, t0, a3
+;   seqz a7, a5
+;   andi t3, a7, 0xff
+;   snez t0, t3
+;   neg t2, t0
+;   and a1, a1, t2
+;   not a3, t2
+;   and a5, a2, a3
+;   or a0, a1, a5
 ;   ret
 
 function %f(i16, i64, i64) -> i64 {
@@ -360,39 +352,38 @@ block0(v0: i16, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli t4,a0,48
-;   srli t1,t4,48
-;   slli a0,a3,48
-;   srli a3,a0,48
-;   eq a4,t1,a3##ty=i16
-;   andi a7,a4,255
-;   sltu t4,zero,a7
-;   sub t1,zero,t4
-;   and a0,a1,t1
-;   not a3,t1
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   slli t3,a0,48
+;   srli t0,t3,48
+;   li t2,42
+;   slli a3,t2,48
+;   srli a3,a3,48
+;   xor a5,t0,a3
+;   seqz a7,a5
+;   andi t3,a7,255
+;   snez t0,t3
+;   sub t2,zero,t0
+;   and a1,a1,t2
+;   not a3,t2
+;   and a5,a2,a3
+;   or a0,a1,a5
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli t4, a0, 0x30
-;   srli t1, t4, 0x30
-;   slli a0, a3, 0x30
-;   srli a3, a0, 0x30
-;   bne t1, a3, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   andi a7, a4, 0xff
-;   snez t4, a7
-;   neg t1, t4
-;   and a0, a1, t1
-;   not a3, t1
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   slli t3, a0, 0x30
+;   srli t0, t3, 0x30
+;   addi t2, zero, 0x2a
+;   slli a3, t2, 0x30
+;   srli a3, a3, 0x30
+;   xor a5, t0, a3
+;   seqz a7, a5
+;   andi t3, a7, 0xff
+;   snez t0, t3
+;   neg t2, t0
+;   and a1, a1, t2
+;   not a3, t2
+;   and a5, a2, a3
+;   or a0, a1, a5
 ;   ret
 
 function %f(i16, i128, i128) -> i128 {
@@ -405,47 +396,46 @@ block0(v0: i16, v1: i128, v2: i128):
 
 ; VCode:
 ; block0:
-;   li a6,42
 ;   slli a5,a0,48
 ;   srli a5,a5,48
-;   slli a6,a6,48
-;   srli t3,a6,48
-;   eq t0,a5,t3##ty=i16
-;   andi t4,t0,255
-;   sltu t1,zero,t4
-;   sub a0,zero,t1
-;   and a6,a1,a0
-;   and a5,a2,a0
-;   not a7,a0
-;   not t3,a0
-;   and t0,a3,a7
-;   and t2,a4,t3
-;   or a0,a6,t0
-;   or a1,a5,t2
+;   li a6,42
+;   slli a7,a6,48
+;   srli t4,a7,48
+;   xor t1,a5,t4
+;   seqz a0,t1
+;   andi t0,a0,255
+;   snez t2,t0
+;   sub a7,zero,t2
+;   and a6,a1,a7
+;   and a5,a2,a7
+;   not t3,a7
+;   not t4,a7
+;   and t1,a3,t3
+;   and a1,a4,t4
+;   or a0,a6,t1
+;   or a1,a5,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a6, zero, 0x2a
 ;   slli a5, a0, 0x30
 ;   srli a5, a5, 0x30
-;   slli a6, a6, 0x30
-;   srli t3, a6, 0x30
-;   bne a5, t3, 0xc
-;   addi t0, zero, 1
-;   j 8
-;   mv t0, zero
-;   andi t4, t0, 0xff
-;   snez t1, t4
-;   neg a0, t1
-;   and a6, a1, a0
-;   and a5, a2, a0
-;   not a7, a0
-;   not t3, a0
-;   and t0, a3, a7
-;   and t2, a4, t3
-;   or a0, a6, t0
-;   or a1, a5, t2
+;   addi a6, zero, 0x2a
+;   slli a7, a6, 0x30
+;   srli t4, a7, 0x30
+;   xor t1, a5, t4
+;   seqz a0, t1
+;   andi t0, a0, 0xff
+;   snez t2, t0
+;   neg a7, t2
+;   and a6, a1, a7
+;   and a5, a2, a7
+;   not t3, a7
+;   not t4, a7
+;   and t1, a3, t3
+;   and a1, a4, t4
+;   or a0, a6, t1
+;   or a1, a5, a1
 ;   ret
 
 function %f(i32, i8, i8) -> i8 {
@@ -458,39 +448,34 @@ block0(v0: i32, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli t4,a0,32
-;   srli t1,t4,32
-;   slli a0,a3,32
-;   srli a3,a0,32
-;   eq a4,t1,a3##ty=i32
-;   andi a7,a4,255
-;   sltu t4,zero,a7
-;   sub t1,zero,t4
-;   and a0,a1,t1
-;   not a3,t1
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   sext.w t3,a0
+;   li t0,42
+;   sext.w t2,t0
+;   xor a3,t3,t2
+;   seqz a3,a3
+;   andi a6,a3,255
+;   snez t3,a6
+;   sub t0,zero,t3
+;   and t2,a1,t0
+;   not a1,t0
+;   and a3,a2,a1
+;   or a0,t2,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli t4, a0, 0x20
-;   srli t1, t4, 0x20
-;   slli a0, a3, 0x20
-;   srli a3, a0, 0x20
-;   bne t1, a3, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   andi a7, a4, 0xff
-;   snez t4, a7
-;   neg t1, t4
-;   and a0, a1, t1
-;   not a3, t1
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   sext.w t3, a0
+;   addi t0, zero, 0x2a
+;   sext.w t2, t0
+;   xor a3, t3, t2
+;   seqz a3, a3
+;   andi a6, a3, 0xff
+;   snez t3, a6
+;   neg t0, t3
+;   and t2, a1, t0
+;   not a1, t0
+;   and a3, a2, a1
+;   or a0, t2, a3
 ;   ret
 
 function %f(i32, i16, i16) -> i16 {
@@ -503,39 +488,34 @@ block0(v0: i32, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli t4,a0,32
-;   srli t1,t4,32
-;   slli a0,a3,32
-;   srli a3,a0,32
-;   eq a4,t1,a3##ty=i32
-;   andi a7,a4,255
-;   sltu t4,zero,a7
-;   sub t1,zero,t4
-;   and a0,a1,t1
-;   not a3,t1
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   sext.w t3,a0
+;   li t0,42
+;   sext.w t2,t0
+;   xor a3,t3,t2
+;   seqz a3,a3
+;   andi a6,a3,255
+;   snez t3,a6
+;   sub t0,zero,t3
+;   and t2,a1,t0
+;   not a1,t0
+;   and a3,a2,a1
+;   or a0,t2,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli t4, a0, 0x20
-;   srli t1, t4, 0x20
-;   slli a0, a3, 0x20
-;   srli a3, a0, 0x20
-;   bne t1, a3, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   andi a7, a4, 0xff
-;   snez t4, a7
-;   neg t1, t4
-;   and a0, a1, t1
-;   not a3, t1
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   sext.w t3, a0
+;   addi t0, zero, 0x2a
+;   sext.w t2, t0
+;   xor a3, t3, t2
+;   seqz a3, a3
+;   andi a6, a3, 0xff
+;   snez t3, a6
+;   neg t0, t3
+;   and t2, a1, t0
+;   not a1, t0
+;   and a3, a2, a1
+;   or a0, t2, a3
 ;   ret
 
 function %f(i32, i32, i32) -> i32 {
@@ -548,39 +528,34 @@ block0(v0: i32, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli t4,a0,32
-;   srli t1,t4,32
-;   slli a0,a3,32
-;   srli a3,a0,32
-;   eq a4,t1,a3##ty=i32
-;   andi a7,a4,255
-;   sltu t4,zero,a7
-;   sub t1,zero,t4
-;   and a0,a1,t1
-;   not a3,t1
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   sext.w t3,a0
+;   li t0,42
+;   sext.w t2,t0
+;   xor a3,t3,t2
+;   seqz a3,a3
+;   andi a6,a3,255
+;   snez t3,a6
+;   sub t0,zero,t3
+;   and t2,a1,t0
+;   not a1,t0
+;   and a3,a2,a1
+;   or a0,t2,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli t4, a0, 0x20
-;   srli t1, t4, 0x20
-;   slli a0, a3, 0x20
-;   srli a3, a0, 0x20
-;   bne t1, a3, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   andi a7, a4, 0xff
-;   snez t4, a7
-;   neg t1, t4
-;   and a0, a1, t1
-;   not a3, t1
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   sext.w t3, a0
+;   addi t0, zero, 0x2a
+;   sext.w t2, t0
+;   xor a3, t3, t2
+;   seqz a3, a3
+;   andi a6, a3, 0xff
+;   snez t3, a6
+;   neg t0, t3
+;   and t2, a1, t0
+;   not a1, t0
+;   and a3, a2, a1
+;   or a0, t2, a3
 ;   ret
 
 function %f(i32, i64, i64) -> i64 {
@@ -593,39 +568,34 @@ block0(v0: i32, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   li a3,42
-;   slli t4,a0,32
-;   srli t1,t4,32
-;   slli a0,a3,32
-;   srli a3,a0,32
-;   eq a4,t1,a3##ty=i32
-;   andi a7,a4,255
-;   sltu t4,zero,a7
-;   sub t1,zero,t4
-;   and a0,a1,t1
-;   not a3,t1
-;   and a4,a2,a3
-;   or a0,a0,a4
+;   sext.w t3,a0
+;   li t0,42
+;   sext.w t2,t0
+;   xor a3,t3,t2
+;   seqz a3,a3
+;   andi a6,a3,255
+;   snez t3,a6
+;   sub t0,zero,t3
+;   and t2,a1,t0
+;   not a1,t0
+;   and a3,a2,a1
+;   or a0,t2,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a3, zero, 0x2a
-;   slli t4, a0, 0x20
-;   srli t1, t4, 0x20
-;   slli a0, a3, 0x20
-;   srli a3, a0, 0x20
-;   bne t1, a3, 0xc
-;   addi a4, zero, 1
-;   j 8
-;   mv a4, zero
-;   andi a7, a4, 0xff
-;   snez t4, a7
-;   neg t1, t4
-;   and a0, a1, t1
-;   not a3, t1
-;   and a4, a2, a3
-;   or a0, a0, a4
+;   sext.w t3, a0
+;   addi t0, zero, 0x2a
+;   sext.w t2, t0
+;   xor a3, t3, t2
+;   seqz a3, a3
+;   andi a6, a3, 0xff
+;   snez t3, a6
+;   neg t0, t3
+;   and t2, a1, t0
+;   not a1, t0
+;   and a3, a2, a1
+;   or a0, t2, a3
 ;   ret
 
 function %f(i32, i128, i128) -> i128 {
@@ -638,47 +608,42 @@ block0(v0: i32, v1: i128, v2: i128):
 
 ; VCode:
 ; block0:
+;   sext.w a5,a0
 ;   li a6,42
-;   slli a5,a0,32
-;   srli a5,a5,32
-;   slli a6,a6,32
-;   srli t3,a6,32
-;   eq t0,a5,t3##ty=i32
-;   andi t4,t0,255
-;   sltu t1,zero,t4
-;   sub a0,zero,t1
-;   and a6,a1,a0
-;   and a5,a2,a0
-;   not a7,a0
-;   not t3,a0
-;   and t0,a3,a7
-;   and t2,a4,t3
-;   or a0,a6,t0
-;   or a1,a5,t2
+;   sext.w a6,a6
+;   xor a7,a5,a6
+;   seqz t4,a7
+;   andi t3,t4,255
+;   snez t0,t3
+;   sub t2,zero,t0
+;   and a1,a1,t2
+;   and a5,a2,t2
+;   not a6,t2
+;   not a7,t2
+;   and t4,a3,a6
+;   and t1,a4,a7
+;   or a0,a1,t4
+;   or a1,a5,t1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
+;   sext.w a5, a0
 ;   addi a6, zero, 0x2a
-;   slli a5, a0, 0x20
-;   srli a5, a5, 0x20
-;   slli a6, a6, 0x20
-;   srli t3, a6, 0x20
-;   bne a5, t3, 0xc
-;   addi t0, zero, 1
-;   j 8
-;   mv t0, zero
-;   andi t4, t0, 0xff
-;   snez t1, t4
-;   neg a0, t1
-;   and a6, a1, a0
-;   and a5, a2, a0
-;   not a7, a0
-;   not t3, a0
-;   and t0, a3, a7
-;   and t2, a4, t3
-;   or a0, a6, t0
-;   or a1, a5, t2
+;   sext.w a6, a6
+;   xor a7, a5, a6
+;   seqz t4, a7
+;   andi t3, t4, 0xff
+;   snez t0, t3
+;   neg t2, t0
+;   and a1, a1, t2
+;   and a5, a2, t2
+;   not a6, t2
+;   not a7, t2
+;   and t4, a3, a6
+;   and t1, a4, a7
+;   or a0, a1, t4
+;   or a1, a5, t1
 ;   ret
 
 function %f(i64, i8, i8) -> i8 {
@@ -691,31 +656,30 @@ block0(v0: i64, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   li t4,42
-;   eq t4,a0,t4##ty=i64
-;   andi a3,t4,255
-;   sltu a5,zero,a3
-;   sub a7,zero,a5
-;   and t4,a1,a7
-;   not t1,a7
-;   and a0,a2,t1
-;   or a0,t4,a0
+;   li t3,42
+;   xor t0,a0,t3
+;   seqz t2,t0
+;   andi a4,t2,255
+;   snez a6,a4
+;   sub t3,zero,a6
+;   and t0,a1,t3
+;   not t2,t3
+;   and a1,a2,t2
+;   or a0,t0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t4, zero, 0x2a
-;   bne a0, t4, 0xc
-;   addi t4, zero, 1
-;   j 8
-;   mv t4, zero
-;   andi a3, t4, 0xff
-;   snez a5, a3
-;   neg a7, a5
-;   and t4, a1, a7
-;   not t1, a7
-;   and a0, a2, t1
-;   or a0, t4, a0
+;   addi t3, zero, 0x2a
+;   xor t0, a0, t3
+;   seqz t2, t0
+;   andi a4, t2, 0xff
+;   snez a6, a4
+;   neg t3, a6
+;   and t0, a1, t3
+;   not t2, t3
+;   and a1, a2, t2
+;   or a0, t0, a1
 ;   ret
 
 function %f(i64, i16, i16) -> i16 {
@@ -728,31 +692,30 @@ block0(v0: i64, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   li t4,42
-;   eq t4,a0,t4##ty=i64
-;   andi a3,t4,255
-;   sltu a5,zero,a3
-;   sub a7,zero,a5
-;   and t4,a1,a7
-;   not t1,a7
-;   and a0,a2,t1
-;   or a0,t4,a0
+;   li t3,42
+;   xor t0,a0,t3
+;   seqz t2,t0
+;   andi a4,t2,255
+;   snez a6,a4
+;   sub t3,zero,a6
+;   and t0,a1,t3
+;   not t2,t3
+;   and a1,a2,t2
+;   or a0,t0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t4, zero, 0x2a
-;   bne a0, t4, 0xc
-;   addi t4, zero, 1
-;   j 8
-;   mv t4, zero
-;   andi a3, t4, 0xff
-;   snez a5, a3
-;   neg a7, a5
-;   and t4, a1, a7
-;   not t1, a7
-;   and a0, a2, t1
-;   or a0, t4, a0
+;   addi t3, zero, 0x2a
+;   xor t0, a0, t3
+;   seqz t2, t0
+;   andi a4, t2, 0xff
+;   snez a6, a4
+;   neg t3, a6
+;   and t0, a1, t3
+;   not t2, t3
+;   and a1, a2, t2
+;   or a0, t0, a1
 ;   ret
 
 function %f(i64, i32, i32) -> i32 {
@@ -765,31 +728,30 @@ block0(v0: i64, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   li t4,42
-;   eq t4,a0,t4##ty=i64
-;   andi a3,t4,255
-;   sltu a5,zero,a3
-;   sub a7,zero,a5
-;   and t4,a1,a7
-;   not t1,a7
-;   and a0,a2,t1
-;   or a0,t4,a0
+;   li t3,42
+;   xor t0,a0,t3
+;   seqz t2,t0
+;   andi a4,t2,255
+;   snez a6,a4
+;   sub t3,zero,a6
+;   and t0,a1,t3
+;   not t2,t3
+;   and a1,a2,t2
+;   or a0,t0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t4, zero, 0x2a
-;   bne a0, t4, 0xc
-;   addi t4, zero, 1
-;   j 8
-;   mv t4, zero
-;   andi a3, t4, 0xff
-;   snez a5, a3
-;   neg a7, a5
-;   and t4, a1, a7
-;   not t1, a7
-;   and a0, a2, t1
-;   or a0, t4, a0
+;   addi t3, zero, 0x2a
+;   xor t0, a0, t3
+;   seqz t2, t0
+;   andi a4, t2, 0xff
+;   snez a6, a4
+;   neg t3, a6
+;   and t0, a1, t3
+;   not t2, t3
+;   and a1, a2, t2
+;   or a0, t0, a1
 ;   ret
 
 function %f(i64, i64, i64) -> i64 {
@@ -802,31 +764,30 @@ block0(v0: i64, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   li t4,42
-;   eq t4,a0,t4##ty=i64
-;   andi a3,t4,255
-;   sltu a5,zero,a3
-;   sub a7,zero,a5
-;   and t4,a1,a7
-;   not t1,a7
-;   and a0,a2,t1
-;   or a0,t4,a0
+;   li t3,42
+;   xor t0,a0,t3
+;   seqz t2,t0
+;   andi a4,t2,255
+;   snez a6,a4
+;   sub t3,zero,a6
+;   and t0,a1,t3
+;   not t2,t3
+;   and a1,a2,t2
+;   or a0,t0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t4, zero, 0x2a
-;   bne a0, t4, 0xc
-;   addi t4, zero, 1
-;   j 8
-;   mv t4, zero
-;   andi a3, t4, 0xff
-;   snez a5, a3
-;   neg a7, a5
-;   and t4, a1, a7
-;   not t1, a7
-;   and a0, a2, t1
-;   or a0, t4, a0
+;   addi t3, zero, 0x2a
+;   xor t0, a0, t3
+;   seqz t2, t0
+;   andi a4, t2, 0xff
+;   snez a6, a4
+;   neg t3, a6
+;   and t0, a1, t3
+;   not t2, t3
+;   and a1, a2, t2
+;   or a0, t0, a1
 ;   ret
 
 function %f(i64, i128, i128) -> i128 {
@@ -840,38 +801,37 @@ block0(v0: i64, v1: i128, v2: i128):
 ; VCode:
 ; block0:
 ;   li a5,42
-;   eq a5,a0,a5##ty=i64
-;   andi a5,a5,255
-;   sltu a7,zero,a5
-;   sub t4,zero,a7
-;   and t1,a1,t4
-;   and a1,a2,t4
-;   not a2,t4
-;   not a5,t4
-;   and a6,a3,a2
-;   and t3,a4,a5
-;   or a0,t1,a6
-;   or a1,a1,t3
+;   xor a5,a0,a5
+;   seqz a5,a5
+;   andi a6,a5,255
+;   snez t3,a6
+;   sub t0,zero,t3
+;   and t2,a1,t0
+;   and a1,a2,t0
+;   not a6,t0
+;   not a5,t0
+;   and a7,a3,a6
+;   and t4,a4,a5
+;   or a0,t2,a7
+;   or a1,a1,t4
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a5, zero, 0x2a
-;   bne a0, a5, 0xc
-;   addi a5, zero, 1
-;   j 8
-;   mv a5, zero
-;   andi a5, a5, 0xff
-;   snez a7, a5
-;   neg t4, a7
-;   and t1, a1, t4
-;   and a1, a2, t4
-;   not a2, t4
-;   not a5, t4
-;   and a6, a3, a2
-;   and t3, a4, a5
-;   or a0, t1, a6
-;   or a1, a1, t3
+;   xor a5, a0, a5
+;   seqz a5, a5
+;   andi a6, a5, 0xff
+;   snez t3, a6
+;   neg t0, t3
+;   and t2, a1, t0
+;   and a1, a2, t0
+;   not a6, t0
+;   not a5, t0
+;   and a7, a3, a6
+;   and t4, a4, a5
+;   or a0, t2, a7
+;   or a1, a1, t4
 ;   ret
 
 function %f(i128, i8, i8) -> i8 {
@@ -885,34 +845,36 @@ block0(v0: i128, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   li t1,42
-;   li t2,0
-;   eq t1,[a0,a1],[t1,t2]##ty=i128
-;   andi a5,t1,255
-;   sltu a7,zero,a5
-;   sub t4,zero,a7
-;   and t1,a2,t4
-;   not a0,t4
-;   and a2,a3,a0
-;   or a0,t1,a2
+;   li a4,42
+;   li a5,0
+;   xor t1,a0,a4
+;   xor a0,a1,a5
+;   or a4,t1,a0
+;   seqz a4,a4
+;   andi t3,a4,255
+;   snez t0,t3
+;   sub t2,zero,t0
+;   and a1,a2,t2
+;   not a4,t2
+;   and a5,a3,a4
+;   or a0,a1,a5
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t1, zero, 0x2a
-;   mv t2, zero
-;   bne a1, t2, 0x10
-;   bne a0, t1, 0xc
-;   addi t1, zero, 1
-;   j 8
-;   mv t1, zero
-;   andi a5, t1, 0xff
-;   snez a7, a5
-;   neg t4, a7
-;   and t1, a2, t4
-;   not a0, t4
-;   and a2, a3, a0
-;   or a0, t1, a2
+;   addi a4, zero, 0x2a
+;   mv a5, zero
+;   xor t1, a0, a4
+;   xor a0, a1, a5
+;   or a4, t1, a0
+;   seqz a4, a4
+;   andi t3, a4, 0xff
+;   snez t0, t3
+;   neg t2, t0
+;   and a1, a2, t2
+;   not a4, t2
+;   and a5, a3, a4
+;   or a0, a1, a5
 ;   ret
 
 function %f(i128, i16, i16) -> i16 {
@@ -926,34 +888,36 @@ block0(v0: i128, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   li t1,42
-;   li t2,0
-;   eq t1,[a0,a1],[t1,t2]##ty=i128
-;   andi a5,t1,255
-;   sltu a7,zero,a5
-;   sub t4,zero,a7
-;   and t1,a2,t4
-;   not a0,t4
-;   and a2,a3,a0
-;   or a0,t1,a2
+;   li a4,42
+;   li a5,0
+;   xor t1,a0,a4
+;   xor a0,a1,a5
+;   or a4,t1,a0
+;   seqz a4,a4
+;   andi t3,a4,255
+;   snez t0,t3
+;   sub t2,zero,t0
+;   and a1,a2,t2
+;   not a4,t2
+;   and a5,a3,a4
+;   or a0,a1,a5
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t1, zero, 0x2a
-;   mv t2, zero
-;   bne a1, t2, 0x10
-;   bne a0, t1, 0xc
-;   addi t1, zero, 1
-;   j 8
-;   mv t1, zero
-;   andi a5, t1, 0xff
-;   snez a7, a5
-;   neg t4, a7
-;   and t1, a2, t4
-;   not a0, t4
-;   and a2, a3, a0
-;   or a0, t1, a2
+;   addi a4, zero, 0x2a
+;   mv a5, zero
+;   xor t1, a0, a4
+;   xor a0, a1, a5
+;   or a4, t1, a0
+;   seqz a4, a4
+;   andi t3, a4, 0xff
+;   snez t0, t3
+;   neg t2, t0
+;   and a1, a2, t2
+;   not a4, t2
+;   and a5, a3, a4
+;   or a0, a1, a5
 ;   ret
 
 function %f(i128, i32, i32) -> i32 {
@@ -967,34 +931,36 @@ block0(v0: i128, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   li t1,42
-;   li t2,0
-;   eq t1,[a0,a1],[t1,t2]##ty=i128
-;   andi a5,t1,255
-;   sltu a7,zero,a5
-;   sub t4,zero,a7
-;   and t1,a2,t4
-;   not a0,t4
-;   and a2,a3,a0
-;   or a0,t1,a2
+;   li a4,42
+;   li a5,0
+;   xor t1,a0,a4
+;   xor a0,a1,a5
+;   or a4,t1,a0
+;   seqz a4,a4
+;   andi t3,a4,255
+;   snez t0,t3
+;   sub t2,zero,t0
+;   and a1,a2,t2
+;   not a4,t2
+;   and a5,a3,a4
+;   or a0,a1,a5
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t1, zero, 0x2a
-;   mv t2, zero
-;   bne a1, t2, 0x10
-;   bne a0, t1, 0xc
-;   addi t1, zero, 1
-;   j 8
-;   mv t1, zero
-;   andi a5, t1, 0xff
-;   snez a7, a5
-;   neg t4, a7
-;   and t1, a2, t4
-;   not a0, t4
-;   and a2, a3, a0
-;   or a0, t1, a2
+;   addi a4, zero, 0x2a
+;   mv a5, zero
+;   xor t1, a0, a4
+;   xor a0, a1, a5
+;   or a4, t1, a0
+;   seqz a4, a4
+;   andi t3, a4, 0xff
+;   snez t0, t3
+;   neg t2, t0
+;   and a1, a2, t2
+;   not a4, t2
+;   and a5, a3, a4
+;   or a0, a1, a5
 ;   ret
 
 function %f(i128, i64, i64) -> i64 {
@@ -1008,34 +974,36 @@ block0(v0: i128, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   li t1,42
-;   li t2,0
-;   eq t1,[a0,a1],[t1,t2]##ty=i128
-;   andi a5,t1,255
-;   sltu a7,zero,a5
-;   sub t4,zero,a7
-;   and t1,a2,t4
-;   not a0,t4
-;   and a2,a3,a0
-;   or a0,t1,a2
+;   li a4,42
+;   li a5,0
+;   xor t1,a0,a4
+;   xor a0,a1,a5
+;   or a4,t1,a0
+;   seqz a4,a4
+;   andi t3,a4,255
+;   snez t0,t3
+;   sub t2,zero,t0
+;   and a1,a2,t2
+;   not a4,t2
+;   and a5,a3,a4
+;   or a0,a1,a5
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t1, zero, 0x2a
-;   mv t2, zero
-;   bne a1, t2, 0x10
-;   bne a0, t1, 0xc
-;   addi t1, zero, 1
-;   j 8
-;   mv t1, zero
-;   andi a5, t1, 0xff
-;   snez a7, a5
-;   neg t4, a7
-;   and t1, a2, t4
-;   not a0, t4
-;   and a2, a3, a0
-;   or a0, t1, a2
+;   addi a4, zero, 0x2a
+;   mv a5, zero
+;   xor t1, a0, a4
+;   xor a0, a1, a5
+;   or a4, t1, a0
+;   seqz a4, a4
+;   andi t3, a4, 0xff
+;   snez t0, t3
+;   neg t2, t0
+;   and a1, a2, t2
+;   not a4, t2
+;   and a5, a3, a4
+;   or a0, a1, a5
 ;   ret
 
 function %f(i128, i128, i128) -> i128 {
@@ -1049,41 +1017,43 @@ block0(v0: i128, v1: i128, v2: i128):
 
 ; VCode:
 ; block0:
-;   li a6,42
-;   li a7,0
-;   eq a6,[a0,a1],[a6,a7]##ty=i128
-;   andi a7,a6,255
-;   sltu t4,zero,a7
-;   sub t1,zero,t4
-;   and a0,a2,t1
-;   and a2,a3,t1
-;   not a7,t1
-;   not a6,t1
-;   and t3,a4,a7
-;   and t0,a5,a6
-;   or a0,a0,t3
-;   or a1,a2,t0
+;   li a7,42
+;   li t3,0
+;   xor a6,a0,a7
+;   xor a7,a1,t3
+;   or t3,a6,a7
+;   seqz t0,t3
+;   andi t0,t0,255
+;   snez t2,t0
+;   sub a1,zero,t2
+;   and a7,a2,a1
+;   and a6,a3,a1
+;   not t3,a1
+;   not t4,a1
+;   and t1,a4,t3
+;   and a1,a5,t4
+;   or a0,a7,t1
+;   or a1,a6,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a6, zero, 0x2a
-;   mv a7, zero
-;   bne a1, a7, 0x10
-;   bne a0, a6, 0xc
-;   addi a6, zero, 1
-;   j 8
-;   mv a6, zero
-;   andi a7, a6, 0xff
-;   snez t4, a7
-;   neg t1, t4
-;   and a0, a2, t1
-;   and a2, a3, t1
-;   not a7, t1
-;   not a6, t1
-;   and t3, a4, a7
-;   and t0, a5, a6
-;   or a0, a0, t3
-;   or a1, a2, t0
+;   addi a7, zero, 0x2a
+;   mv t3, zero
+;   xor a6, a0, a7
+;   xor a7, a1, t3
+;   or t3, a6, a7
+;   seqz t0, t3
+;   andi t0, t0, 0xff
+;   snez t2, t0
+;   neg a1, t2
+;   and a7, a2, a1
+;   and a6, a3, a1
+;   not t3, a1
+;   not t4, a1
+;   and t1, a4, t3
+;   and a1, a5, t4
+;   or a0, a7, t1
+;   or a1, a6, a1
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/traps.clif b/cranelift/filetests/filetests/isa/riscv64/traps.clif
index bdd6ede18a5f..141be31659bc 100644
--- a/cranelift/filetests/filetests/isa/riscv64/traps.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/traps.clif
@@ -26,8 +26,9 @@ block0(v0: i64):
 ; VCode:
 ; block0:
 ;   li a1,42
-;   eq a0,a0,a1##ty=i64
-;   bne a0,zero,taken(label2),not_taken(label1)
+;   xor a0,a0,a1
+;   seqz a2,a0
+;   bne a2,zero,taken(label2),not_taken(label1)
 ; block1:
 ;   ret
 ; block2:
@@ -36,14 +37,12 @@ block0(v0: i64):
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a1, zero, 0x2a
-;   bne a0, a1, 0xc
-;   addi a0, zero, 1
-;   j 8
-;   mv a0, zero
-;   bnez a0, 8
-; block1: ; offset 0x18
+;   xor a0, a0, a1
+;   seqz a2, a0
+;   bnez a2, 8
+; block1: ; offset 0x10
 ;   ret
-; block2: ; offset 0x1c
+; block2: ; offset 0x14
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
 
 function %h() {
diff --git a/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif b/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif
index d1ba180c4628..7c2505418ee1 100644
--- a/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif
@@ -106,7 +106,7 @@ block0(v0: i64):
 ;   mv a4,a0
 ;   li a1,127
 ;   add a0,a4,a1
-;   ult a2,a0,a4##ty=i64
+;   sltu a2,a0,a4
 ;   trap_if a2,user0
 ;   ret
 ; 
@@ -115,10 +115,7 @@ block0(v0: i64):
 ;   ori a4, a0, 0
 ;   addi a1, zero, 0x7f
 ;   add a0, a4, a1
-;   bgeu a0, a4, 0xc
-;   addi a2, zero, 1
-;   j 8
-;   mv a2, zero
+;   sltu a2, a0, a4
 ;   beqz a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
 ;   ret
@@ -134,7 +131,7 @@ block0(v0: i64):
 ; block0:
 ;   li a1,127
 ;   add a0,a1,a0
-;   ult a2,a0,a1##ty=i64
+;   sltu a2,a0,a1
 ;   trap_if a2,user0
 ;   ret
 ; 
@@ -142,10 +139,7 @@ block0(v0: i64):
 ; block0: ; offset 0x0
 ;   addi a1, zero, 0x7f
 ;   add a0, a1, a0
-;   bgeu a0, a1, 0xc
-;   addi a2, zero, 1
-;   j 8
-;   mv a2, zero
+;   sltu a2, a0, a1
 ;   beqz a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
 ;   ret
@@ -160,7 +154,7 @@ block0(v0: i64, v1: i64):
 ; block0:
 ;   add a1,a0,a1
 ;   mv a3,a1
-;   ult a2,a3,a0##ty=i64
+;   sltu a2,a3,a0
 ;   mv a0,a3
 ;   trap_if a2,user0
 ;   ret
@@ -169,10 +163,7 @@ block0(v0: i64, v1: i64):
 ; block0: ; offset 0x0
 ;   add a1, a0, a1
 ;   ori a3, a1, 0
-;   bgeu a3, a0, 0xc
-;   addi a2, zero, 1
-;   j 8
-;   mv a2, zero
+;   sltu a2, a3, a0
 ;   ori a0, a3, 0
 ;   beqz a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat
index f99f5defcb4d..c09e6251e304 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat
@@ -45,7 +45,7 @@
 ;;   srli t3,a6,32
 ;;   ld a7,8(a2)
 ;;   addi a7,a7,-4
-;;   ugt a7,t3,a7##ty=i64
+;;   sltu a7,a7,t3
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t4,0(a2)
@@ -63,7 +63,7 @@
 ;;   srli t3,a6,32
 ;;   ld a7,8(a1)
 ;;   addi a7,a7,-4
-;;   ugt a7,t3,a7##ty=i64
+;;   sltu a7,a7,t3
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t4,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
index 74495be63ed0..3435f6f04efb 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
@@ -47,7 +47,7 @@
 ;;   lui a0,1048575
 ;;   addi a0,a0,4092
 ;;   add t1,t1,a0
-;;   ugt t1,t2,t1##ty=i64
+;;   sltu t1,t1,t2
 ;;   bne t1,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a0,0(a2)
@@ -69,7 +69,7 @@
 ;;   lui a0,1048575
 ;;   addi a0,a0,4092
 ;;   add t1,t1,a0
-;;   ugt t1,t2,t1##ty=i64
+;;   sltu t1,t1,t2
 ;;   bne t1,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a0,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
index 820e72762fd6..bbaa06eed11c 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -45,10 +45,10 @@
 ;;   srli t2,t0,32
 ;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0004
 ;;   add t0,t2,t1
-;;   ult a0,t0,t2##ty=i64
+;;   sltu a0,t0,t2
 ;;   trap_if a0,heap_oob
 ;;   ld a0,8(a2)
-;;   ugt a0,t0,a0##ty=i64
+;;   sltu a0,a0,t0
 ;;   bne a0,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a0,0(a2)
@@ -68,10 +68,10 @@
 ;;   srli t2,t0,32
 ;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0004
 ;;   add t0,t2,t1
-;;   ult a0,t0,t2##ty=i64
+;;   sltu a0,t0,t2
 ;;   trap_if a0,heap_oob
 ;;   ld a0,8(a1)
-;;   ugt a0,t0,a0##ty=i64
+;;   sltu a0,a0,t0
 ;;   bne a0,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a0,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index 8171df33fee2..f9e41c513763 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -41,15 +41,16 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a7,a5,32
-;;   ld a6,8(a2)
-;;   uge a6,a7,a6##ty=i64
-;;   bne a6,zero,taken(label3),not_taken(label1)
+;;   slli a6,a0,32
+;;   srli t3,a6,32
+;;   ld a7,8(a2)
+;;   sltu a6,t3,a7
+;;   xori t4,a6,1
+;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
-;;   ld t3,0(a2)
-;;   add a7,t3,a7
-;;   sb a1,0(a7)
+;;   ld t4,0(a2)
+;;   add t3,t4,t3
+;;   sb a1,0(t3)
 ;;   j label2
 ;; block2:
 ;;   ret
@@ -58,15 +59,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a7,a5,32
-;;   ld a6,8(a1)
-;;   uge a6,a7,a6##ty=i64
-;;   bne a6,zero,taken(label3),not_taken(label1)
+;;   slli a6,a0,32
+;;   srli t3,a6,32
+;;   ld a7,8(a1)
+;;   sltu a6,t3,a7
+;;   xori t4,a6,1
+;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
-;;   ld t3,0(a1)
-;;   add a7,t3,a7
-;;   lbu a0,0(a7)
+;;   ld t4,0(a1)
+;;   add t3,t4,t3
+;;   lbu a0,0(t3)
 ;;   j label2
 ;; block2:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 3cd1a6b88803..721c9e7e2b39 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -47,7 +47,7 @@
 ;;   lui a0,1048575
 ;;   addi a0,a0,4095
 ;;   add t1,t1,a0
-;;   ugt t1,t2,t1##ty=i64
+;;   sltu t1,t1,t2
 ;;   bne t1,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a0,0(a2)
@@ -69,7 +69,7 @@
 ;;   lui a0,1048575
 ;;   addi a0,a0,4095
 ;;   add t1,t1,a0
-;;   ugt t1,t2,t1##ty=i64
+;;   sltu t1,t1,t2
 ;;   bne t1,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a0,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 3318a9b1d6a1..5791f3857f43 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -45,10 +45,10 @@
 ;;   srli t2,t0,32
 ;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0001
 ;;   add t0,t2,t1
-;;   ult a0,t0,t2##ty=i64
+;;   sltu a0,t0,t2
 ;;   trap_if a0,heap_oob
 ;;   ld a0,8(a2)
-;;   ugt a0,t0,a0##ty=i64
+;;   sltu a0,a0,t0
 ;;   bne a0,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a0,0(a2)
@@ -68,10 +68,10 @@
 ;;   srli t2,t0,32
 ;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0001
 ;;   add t0,t2,t1
-;;   ult a0,t0,t2##ty=i64
+;;   sltu a0,t0,t2
 ;;   trap_if a0,heap_oob
 ;;   ld a0,8(a1)
-;;   ugt a0,t0,a0##ty=i64
+;;   sltu a0,a0,t0
 ;;   bne a0,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a0,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
index 67f77c562caf..5c650b4896cd 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -45,12 +45,12 @@
 ;;   srli a3,a3,32
 ;;   ld a4,8(a2)
 ;;   addi a4,a4,-4
-;;   ugt a4,a3,a4##ty=i64
+;;   sltu a4,a4,a3
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   li a3,0
 ;;   andi t4,a4,255
-;;   sltu t1,zero,t4
+;;   snez t1,t4
 ;;   sub a0,zero,t1
 ;;   and a3,a3,a0
 ;;   not a4,a0
@@ -67,12 +67,12 @@
 ;;   srli a3,a2,32
 ;;   ld a2,8(a1)
 ;;   addi a2,a2,-4
-;;   ugt a4,a3,a2##ty=i64
+;;   sltu a4,a2,a3
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a3
 ;;   li a3,0
 ;;   andi t4,a4,255
-;;   sltu t1,zero,t4
+;;   snez t1,t4
 ;;   sub a0,zero,t1
 ;;   and a3,a3,a0
 ;;   not a4,a0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index cb9f3b4a1435..bc0d63ddb5af 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -47,14 +47,14 @@
 ;;   lui t3,1048575
 ;;   addi t3,t3,4092
 ;;   add a6,a6,t3
-;;   ugt t3,a7,a6##ty=i64
+;;   sltu t3,a6,a7
 ;;   ld a6,0(a2)
 ;;   add a6,a6,a7
 ;;   lui a7,1
 ;;   add a6,a6,a7
 ;;   li a7,0
 ;;   andi a0,t3,255
-;;   sltu a2,zero,a0
+;;   snez a2,a0
 ;;   sub a4,zero,a2
 ;;   and a7,a7,a4
 ;;   not t3,a4
@@ -73,14 +73,14 @@
 ;;   lui t3,1048575
 ;;   addi t3,t3,4092
 ;;   add a6,a6,t3
-;;   ugt t3,a7,a6##ty=i64
+;;   sltu t3,a6,a7
 ;;   ld a6,0(a1)
 ;;   add a6,a6,a7
 ;;   lui a7,1
 ;;   add a6,a6,a7
 ;;   li a7,0
 ;;   andi a0,t3,255
-;;   sltu a2,zero,a0
+;;   snez a2,a0
 ;;   sub a4,zero,a2
 ;;   and a7,a7,a4
 ;;   not t3,a4
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index bb494a2e0f56..4136c77517f2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -45,17 +45,17 @@
 ;;   srli a7,a5,32
 ;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0004
 ;;   add a5,a7,a6
-;;   ult t3,a5,a7##ty=i64
+;;   sltu t3,a5,a7
 ;;   trap_if t3,heap_oob
 ;;   ld t3,8(a2)
-;;   ugt t3,a5,t3##ty=i64
+;;   sltu t3,t3,a5
 ;;   ld t4,0(a2)
 ;;   add a7,t4,a7
 ;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
 ;;   add a7,a7,t4
 ;;   li t4,0
 ;;   andi a2,t3,255
-;;   sltu a3,zero,a2
+;;   snez a3,a2
 ;;   sub a5,zero,a3
 ;;   and t3,t4,a5
 ;;   not t4,a5
@@ -72,17 +72,17 @@
 ;;   srli a7,a5,32
 ;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0004
 ;;   add a5,a7,a6
-;;   ult t3,a5,a7##ty=i64
+;;   sltu t3,a5,a7
 ;;   trap_if t3,heap_oob
 ;;   ld t3,8(a1)
-;;   ugt t3,a5,t3##ty=i64
+;;   sltu t3,t3,a5
 ;;   ld t4,0(a1)
 ;;   add a7,t4,a7
 ;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
 ;;   add a7,a7,t4
 ;;   li t4,0
 ;;   andi a1,t3,255
-;;   sltu a3,zero,a1
+;;   snez a3,a1
 ;;   sub a5,zero,a3
 ;;   and t3,t4,a5
 ;;   not t4,a5
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index b9d0fdcb5c99..4f667e0da4cc 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,42 +41,44 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a0,a0,32
-;;   srli a3,a0,32
+;;   slli a3,a0,32
+;;   srli a3,a3,32
 ;;   ld a4,8(a2)
-;;   uge a4,a3,a4##ty=i64
+;;   sltu a4,a3,a4
+;;   xori a4,a4,1
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   li a3,0
-;;   andi t3,a4,255
-;;   sltu t0,zero,t3
-;;   sub t2,zero,t0
-;;   and a3,a3,t2
-;;   not a4,t2
-;;   and a5,a2,a4
-;;   or a7,a3,a5
-;;   sb a1,0(a7)
+;;   andi t4,a4,255
+;;   snez t1,t4
+;;   sub a0,zero,t1
+;;   and a3,a3,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   sb a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a0,a0,32
-;;   srli a2,a0,32
-;;   ld a3,8(a1)
-;;   uge a3,a2,a3##ty=i64
-;;   ld a1,0(a1)
-;;   add a1,a1,a2
-;;   li a2,0
-;;   andi t3,a3,255
-;;   sltu t0,zero,t3
-;;   sub t2,zero,t0
-;;   and a2,a2,t2
-;;   not a3,t2
-;;   and a5,a1,a3
-;;   or a7,a2,a5
-;;   lbu a0,0(a7)
+;;   slli a2,a0,32
+;;   srli a3,a2,32
+;;   ld a2,8(a1)
+;;   sltu a2,a3,a2
+;;   xori a4,a2,1
+;;   ld a2,0(a1)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   snez t1,t4
+;;   sub a0,zero,t1
+;;   and a3,a3,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   lbu a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index fcbfb69265b1..103ba9a8a9da 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -47,14 +47,14 @@
 ;;   lui t3,1048575
 ;;   addi t3,t3,4095
 ;;   add a6,a6,t3
-;;   ugt t3,a7,a6##ty=i64
+;;   sltu t3,a6,a7
 ;;   ld a6,0(a2)
 ;;   add a6,a6,a7
 ;;   lui a7,1
 ;;   add a6,a6,a7
 ;;   li a7,0
 ;;   andi a0,t3,255
-;;   sltu a2,zero,a0
+;;   snez a2,a0
 ;;   sub a4,zero,a2
 ;;   and a7,a7,a4
 ;;   not t3,a4
@@ -73,14 +73,14 @@
 ;;   lui t3,1048575
 ;;   addi t3,t3,4095
 ;;   add a6,a6,t3
-;;   ugt t3,a7,a6##ty=i64
+;;   sltu t3,a6,a7
 ;;   ld a6,0(a1)
 ;;   add a6,a6,a7
 ;;   lui a7,1
 ;;   add a6,a6,a7
 ;;   li a7,0
 ;;   andi a0,t3,255
-;;   sltu a2,zero,a0
+;;   snez a2,a0
 ;;   sub a4,zero,a2
 ;;   and a7,a7,a4
 ;;   not t3,a4
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 5aa80eeb8d2b..5b83cedef614 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -45,17 +45,17 @@
 ;;   srli a7,a5,32
 ;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0001
 ;;   add a5,a7,a6
-;;   ult t3,a5,a7##ty=i64
+;;   sltu t3,a5,a7
 ;;   trap_if t3,heap_oob
 ;;   ld t3,8(a2)
-;;   ugt t3,a5,t3##ty=i64
+;;   sltu t3,t3,a5
 ;;   ld t4,0(a2)
 ;;   add a7,t4,a7
 ;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
 ;;   add a7,a7,t4
 ;;   li t4,0
 ;;   andi a2,t3,255
-;;   sltu a3,zero,a2
+;;   snez a3,a2
 ;;   sub a5,zero,a3
 ;;   and t3,t4,a5
 ;;   not t4,a5
@@ -72,17 +72,17 @@
 ;;   srli a7,a5,32
 ;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0001
 ;;   add a5,a7,a6
-;;   ult t3,a5,a7##ty=i64
+;;   sltu t3,a5,a7
 ;;   trap_if t3,heap_oob
 ;;   ld t3,8(a1)
-;;   ugt t3,a5,t3##ty=i64
+;;   sltu t3,t3,a5
 ;;   ld t4,0(a1)
 ;;   add a7,t4,a7
 ;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
 ;;   add a7,a7,t4
 ;;   li t4,0
 ;;   andi a1,t3,255
-;;   sltu a3,zero,a1
+;;   snez a3,a1
 ;;   sub a5,zero,a3
 ;;   and t3,t4,a5
 ;;   not t4,a5
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
index 40dd0f89b3af..48e259b20f49 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
@@ -44,7 +44,7 @@
 ;;   slli a5,a0,32
 ;;   srli a7,a5,32
 ;;   ld a6,8(a2)
-;;   ugt a6,a7,a6##ty=i64
+;;   sltu a6,a6,a7
 ;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t3,0(a2)
@@ -61,7 +61,7 @@
 ;;   slli a5,a0,32
 ;;   srli a7,a5,32
 ;;   ld a6,8(a1)
-;;   ugt a6,a7,a6##ty=i64
+;;   sltu a6,a6,a7
 ;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t3,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
index d4ccae50837b..e22bc98234c2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
@@ -44,7 +44,7 @@
 ;;   slli a7,a0,32
 ;;   srli t4,a7,32
 ;;   ld t3,8(a2)
-;;   ugt t3,t4,t3##ty=i64
+;;   sltu t3,t3,t4
 ;;   bne t3,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a2)
@@ -63,7 +63,7 @@
 ;;   slli a7,a0,32
 ;;   srli t4,a7,32
 ;;   ld t3,8(a1)
-;;   ugt t3,t4,t3##ty=i64
+;;   sltu t3,t3,t4
 ;;   bne t3,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
index 39dda859af1e..60fbb9411974 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -44,7 +44,7 @@
 ;;   slli a7,a0,32
 ;;   srli t4,a7,32
 ;;   ld t3,8(a2)
-;;   ugt t3,t4,t3##ty=i64
+;;   sltu t3,t3,t4
 ;;   bne t3,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a2)
@@ -63,7 +63,7 @@
 ;;   slli a7,a0,32
 ;;   srli t4,a7,32
 ;;   ld t3,8(a1)
-;;   ugt t3,t4,t3##ty=i64
+;;   sltu t3,t3,t4
 ;;   bne t3,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 7adb564ac195..a06fd232c0be 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -41,15 +41,16 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a7,a5,32
-;;   ld a6,8(a2)
-;;   uge a6,a7,a6##ty=i64
-;;   bne a6,zero,taken(label3),not_taken(label1)
+;;   slli a6,a0,32
+;;   srli t3,a6,32
+;;   ld a7,8(a2)
+;;   sltu a6,t3,a7
+;;   xori t4,a6,1
+;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
-;;   ld t3,0(a2)
-;;   add a7,t3,a7
-;;   sb a1,0(a7)
+;;   ld t4,0(a2)
+;;   add t3,t4,t3
+;;   sb a1,0(t3)
 ;;   j label2
 ;; block2:
 ;;   ret
@@ -58,15 +59,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a5,a0,32
-;;   srli a7,a5,32
-;;   ld a6,8(a1)
-;;   uge a6,a7,a6##ty=i64
-;;   bne a6,zero,taken(label3),not_taken(label1)
+;;   slli a6,a0,32
+;;   srli t3,a6,32
+;;   ld a7,8(a1)
+;;   sltu a6,t3,a7
+;;   xori t4,a6,1
+;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
-;;   ld t3,0(a1)
-;;   add a7,t3,a7
-;;   lbu a0,0(a7)
+;;   ld t4,0(a1)
+;;   add t3,t4,t3
+;;   lbu a0,0(t3)
 ;;   j label2
 ;; block2:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 28c20d7931f2..731842ef8a27 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -44,7 +44,7 @@
 ;;   slli a7,a0,32
 ;;   srli t4,a7,32
 ;;   ld t3,8(a2)
-;;   ugt t3,t4,t3##ty=i64
+;;   sltu t3,t3,t4
 ;;   bne t3,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a2)
@@ -63,7 +63,7 @@
 ;;   slli a7,a0,32
 ;;   srli t4,a7,32
 ;;   ld t3,8(a1)
-;;   ugt t3,t4,t3##ty=i64
+;;   sltu t3,t3,t4
 ;;   bne t3,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 6caf11f388fd..bde2939f6b5f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -44,7 +44,7 @@
 ;;   slli a7,a0,32
 ;;   srli t4,a7,32
 ;;   ld t3,8(a2)
-;;   ugt t3,t4,t3##ty=i64
+;;   sltu t3,t3,t4
 ;;   bne t3,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a2)
@@ -63,7 +63,7 @@
 ;;   slli a7,a0,32
 ;;   srli t4,a7,32
 ;;   ld t3,8(a1)
-;;   ugt t3,t4,t3##ty=i64
+;;   sltu t3,t3,t4
 ;;   bne t3,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index 23fc37420d0e..5079f97ad597 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -44,12 +44,12 @@
 ;;   slli a0,a0,32
 ;;   srli a3,a0,32
 ;;   ld a4,8(a2)
-;;   ugt a4,a3,a4##ty=i64
+;;   sltu a4,a4,a3
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   li a3,0
 ;;   andi t3,a4,255
-;;   sltu t0,zero,t3
+;;   snez t0,t3
 ;;   sub t2,zero,t0
 ;;   and a3,a3,t2
 ;;   not a4,t2
@@ -65,12 +65,12 @@
 ;;   slli a0,a0,32
 ;;   srli a2,a0,32
 ;;   ld a3,8(a1)
-;;   ugt a3,a2,a3##ty=i64
+;;   sltu a3,a3,a2
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a2
 ;;   li a2,0
 ;;   andi t3,a3,255
-;;   sltu t0,zero,t3
+;;   snez t0,t3
 ;;   sub t2,zero,t0
 ;;   and a2,a2,t2
 ;;   not a3,t2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 6f51038a81d4..2674af946883 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -44,14 +44,14 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   ld a3,8(a2)
-;;   ugt a4,a5,a3##ty=i64
+;;   sltu a4,a3,a5
 ;;   ld a3,0(a2)
 ;;   add a3,a3,a5
 ;;   lui a5,1
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
-;;   sltu t2,zero,t0
+;;   snez t2,t0
 ;;   sub a2,zero,t2
 ;;   and a4,a5,a2
 ;;   not a5,a2
@@ -67,14 +67,14 @@
 ;;   slli a2,a0,32
 ;;   srli a5,a2,32
 ;;   ld a3,8(a1)
-;;   ugt a4,a5,a3##ty=i64
+;;   sltu a4,a3,a5
 ;;   ld a3,0(a1)
 ;;   add a3,a3,a5
 ;;   lui a5,1
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
-;;   sltu t2,zero,t0
+;;   snez t2,t0
 ;;   sub a1,zero,t2
 ;;   and a4,a5,a1
 ;;   not a5,a1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 08fbad1904ca..bf46beb585a9 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -44,14 +44,14 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   ld a3,8(a2)
-;;   ugt a4,a5,a3##ty=i64
+;;   sltu a4,a3,a5
 ;;   ld a3,0(a2)
 ;;   add a3,a3,a5
 ;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
-;;   sltu t2,zero,t0
+;;   snez t2,t0
 ;;   sub a2,zero,t2
 ;;   and a4,a5,a2
 ;;   not a5,a2
@@ -67,14 +67,14 @@
 ;;   slli a2,a0,32
 ;;   srli a5,a2,32
 ;;   ld a3,8(a1)
-;;   ugt a4,a5,a3##ty=i64
+;;   sltu a4,a3,a5
 ;;   ld a3,0(a1)
 ;;   add a3,a3,a5
 ;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
-;;   sltu t2,zero,t0
+;;   snez t2,t0
 ;;   sub a1,zero,t2
 ;;   and a4,a5,a1
 ;;   not a5,a1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 8ab4f482fd8f..fff2f1b92152 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,42 +41,44 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a0,a0,32
-;;   srli a3,a0,32
+;;   slli a3,a0,32
+;;   srli a3,a3,32
 ;;   ld a4,8(a2)
-;;   uge a4,a3,a4##ty=i64
+;;   sltu a4,a3,a4
+;;   xori a4,a4,1
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   li a3,0
-;;   andi t3,a4,255
-;;   sltu t0,zero,t3
-;;   sub t2,zero,t0
-;;   and a3,a3,t2
-;;   not a4,t2
-;;   and a5,a2,a4
-;;   or a7,a3,a5
-;;   sb a1,0(a7)
+;;   andi t4,a4,255
+;;   snez t1,t4
+;;   sub a0,zero,t1
+;;   and a3,a3,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   sb a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a0,a0,32
-;;   srli a2,a0,32
-;;   ld a3,8(a1)
-;;   uge a3,a2,a3##ty=i64
-;;   ld a1,0(a1)
-;;   add a1,a1,a2
-;;   li a2,0
-;;   andi t3,a3,255
-;;   sltu t0,zero,t3
-;;   sub t2,zero,t0
-;;   and a2,a2,t2
-;;   not a3,t2
-;;   and a5,a1,a3
-;;   or a7,a2,a5
-;;   lbu a0,0(a7)
+;;   slli a2,a0,32
+;;   srli a3,a2,32
+;;   ld a2,8(a1)
+;;   sltu a2,a3,a2
+;;   xori a4,a2,1
+;;   ld a2,0(a1)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   snez t1,t4
+;;   sub a0,zero,t1
+;;   and a3,a3,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   lbu a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 3be511d027e9..874c1adef9a3 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -44,14 +44,14 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   ld a3,8(a2)
-;;   ugt a4,a5,a3##ty=i64
+;;   sltu a4,a3,a5
 ;;   ld a3,0(a2)
 ;;   add a3,a3,a5
 ;;   lui a5,1
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
-;;   sltu t2,zero,t0
+;;   snez t2,t0
 ;;   sub a2,zero,t2
 ;;   and a4,a5,a2
 ;;   not a5,a2
@@ -67,14 +67,14 @@
 ;;   slli a2,a0,32
 ;;   srli a5,a2,32
 ;;   ld a3,8(a1)
-;;   ugt a4,a5,a3##ty=i64
+;;   sltu a4,a3,a5
 ;;   ld a3,0(a1)
 ;;   add a3,a3,a5
 ;;   lui a5,1
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
-;;   sltu t2,zero,t0
+;;   snez t2,t0
 ;;   sub a1,zero,t2
 ;;   and a4,a5,a1
 ;;   not a5,a1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index c5fac9a92678..5fe1d5d008bb 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -44,14 +44,14 @@
 ;;   slli a3,a0,32
 ;;   srli a5,a3,32
 ;;   ld a3,8(a2)
-;;   ugt a4,a5,a3##ty=i64
+;;   sltu a4,a3,a5
 ;;   ld a3,0(a2)
 ;;   add a3,a3,a5
 ;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
-;;   sltu t2,zero,t0
+;;   snez t2,t0
 ;;   sub a2,zero,t2
 ;;   and a4,a5,a2
 ;;   not a5,a2
@@ -67,14 +67,14 @@
 ;;   slli a2,a0,32
 ;;   srli a5,a2,32
 ;;   ld a3,8(a1)
-;;   ugt a4,a5,a3##ty=i64
+;;   sltu a4,a3,a5
 ;;   ld a3,0(a1)
 ;;   add a3,a3,a5
 ;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
 ;;   add a3,a3,a5
 ;;   li a5,0
 ;;   andi t0,a4,255
-;;   sltu t2,zero,t0
+;;   snez t2,t0
 ;;   sub a1,zero,t2
 ;;   and a4,a5,a1
 ;;   not a5,a1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0_offset.wat
index b0a8d8f710b0..0f642b9e73a2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0_offset.wat
@@ -43,7 +43,7 @@
 ;; block0:
 ;;   ld a5,8(a2)
 ;;   addi a5,a5,-4
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   bne a5,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a6,0(a2)
@@ -59,7 +59,7 @@
 ;; block0:
 ;;   ld a5,8(a1)
 ;;   addi a5,a5,-4
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   bne a5,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a6,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
index 878602f6572c..012ab01febc2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
@@ -45,7 +45,7 @@
 ;;   lui t0,1048575
 ;;   addi t0,t0,4092
 ;;   add t4,t4,t0
-;;   ugt t4,a0,t4##ty=i64
+;;   sltu t4,t4,a0
 ;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a2)
@@ -65,7 +65,7 @@
 ;;   lui t0,1048575
 ;;   addi t0,t0,4092
 ;;   add t4,t4,t0
-;;   ugt t4,a0,t4##ty=i64
+;;   sltu t4,t4,a0
 ;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
index e4ad3ee89014..b899170fd919 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -43,10 +43,10 @@
 ;; block0:
 ;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
 ;;   add t3,a0,t4
-;;   ult t0,t3,a0##ty=i64
+;;   sltu t0,t3,a0
 ;;   trap_if t0,heap_oob
 ;;   ld t0,8(a2)
-;;   ugt t0,t3,t0##ty=i64
+;;   sltu t0,t0,t3
 ;;   bne t0,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t1,0(a2)
@@ -64,10 +64,10 @@
 ;; block0:
 ;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0004
 ;;   add t3,a0,t4
-;;   ult t0,t3,a0##ty=i64
+;;   sltu t0,t3,a0
 ;;   trap_if t0,heap_oob
 ;;   ld t0,8(a1)
-;;   ugt t0,t3,t0##ty=i64
+;;   sltu t0,t0,t3
 ;;   bne t0,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t1,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index ebd149ab903f..78424bdcde9d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -41,13 +41,14 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a4,8(a2)
-;;   uge a4,a0,a4##ty=i64
-;;   bne a4,zero,taken(label3),not_taken(label1)
+;;   ld a5,8(a2)
+;;   sltu a4,a0,a5
+;;   xori a6,a4,1
+;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
-;;   ld a5,0(a2)
-;;   add a5,a5,a0
-;;   sb a1,0(a5)
+;;   ld a6,0(a2)
+;;   add a6,a6,a0
+;;   sb a1,0(a6)
 ;;   j label2
 ;; block2:
 ;;   ret
@@ -56,13 +57,14 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a4,8(a1)
-;;   uge a4,a0,a4##ty=i64
-;;   bne a4,zero,taken(label3),not_taken(label1)
+;;   ld a5,8(a1)
+;;   sltu a4,a0,a5
+;;   xori a6,a4,1
+;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
-;;   ld a5,0(a1)
-;;   add a5,a5,a0
-;;   lbu a0,0(a5)
+;;   ld a6,0(a1)
+;;   add a6,a6,a0
+;;   lbu a0,0(a6)
 ;;   j label2
 ;; block2:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 111316126ff1..ad142338e71f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -45,7 +45,7 @@
 ;;   lui t0,1048575
 ;;   addi t0,t0,4095
 ;;   add t4,t4,t0
-;;   ugt t4,a0,t4##ty=i64
+;;   sltu t4,t4,a0
 ;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a2)
@@ -65,7 +65,7 @@
 ;;   lui t0,1048575
 ;;   addi t0,t0,4095
 ;;   add t4,t4,t0
-;;   ugt t4,a0,t4##ty=i64
+;;   sltu t4,t4,a0
 ;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t0,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 6bb92fd9cb46..bb98fe32cb0f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -43,10 +43,10 @@
 ;; block0:
 ;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
 ;;   add t3,a0,t4
-;;   ult t0,t3,a0##ty=i64
+;;   sltu t0,t3,a0
 ;;   trap_if t0,heap_oob
 ;;   ld t0,8(a2)
-;;   ugt t0,t3,t0##ty=i64
+;;   sltu t0,t0,t3
 ;;   bne t0,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t1,0(a2)
@@ -64,10 +64,10 @@
 ;; block0:
 ;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0001
 ;;   add t3,a0,t4
-;;   ult t0,t3,a0##ty=i64
+;;   sltu t0,t3,a0
 ;;   trap_if t0,heap_oob
 ;;   ld t0,8(a1)
-;;   ugt t0,t3,t0##ty=i64
+;;   sltu t0,t0,t3
 ;;   bne t0,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t1,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
index 95538dd91919..01e85d043123 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -43,12 +43,12 @@
 ;; block0:
 ;;   ld a3,8(a2)
 ;;   addi a3,a3,-4
-;;   ugt a4,a0,a3##ty=i64
+;;   sltu a4,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a0,a2,a0
 ;;   li a3,0
 ;;   andi a7,a4,255
-;;   sltu t4,zero,a7
+;;   snez t4,a7
 ;;   sub t1,zero,t4
 ;;   and a2,a3,t1
 ;;   not a3,t1
@@ -63,12 +63,12 @@
 ;; block0:
 ;;   ld a2,8(a1)
 ;;   addi a2,a2,-4
-;;   ugt a3,a0,a2##ty=i64
+;;   sltu a3,a2,a0
 ;;   ld a1,0(a1)
 ;;   add a0,a1,a0
 ;;   li a2,0
 ;;   andi a7,a3,255
-;;   sltu t4,zero,a7
+;;   snez t4,a7
 ;;   sub t1,zero,t4
 ;;   and a1,a2,t1
 ;;   not a2,t1
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 169c79927e88..14f09eb395d1 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -45,14 +45,14 @@
 ;;   lui a5,1048575
 ;;   addi a5,a5,4092
 ;;   add a4,a4,a5
-;;   ugt a5,a0,a4##ty=i64
+;;   sltu a5,a4,a0
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a0
 ;;   lui a6,1
 ;;   add a4,a4,a6
 ;;   li a6,0
 ;;   andi t1,a5,255
-;;   sltu a0,zero,t1
+;;   snez a0,t1
 ;;   sub a2,zero,a0
 ;;   and a5,a6,a2
 ;;   not a6,a2
@@ -69,14 +69,14 @@
 ;;   lui a5,1048575
 ;;   addi a5,a5,4092
 ;;   add a4,a4,a5
-;;   ugt a5,a0,a4##ty=i64
+;;   sltu a5,a4,a0
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a0
 ;;   lui a6,1
 ;;   add a4,a4,a6
 ;;   li a6,0
 ;;   andi t1,a5,255
-;;   sltu a0,zero,t1
+;;   snez a0,t1
 ;;   sub a2,zero,a0
 ;;   and a5,a6,a2
 ;;   not a6,a2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 711ee993b425..1245a9d4200a 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -43,17 +43,17 @@
 ;; block0:
 ;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0004
 ;;   add a3,a0,a4
-;;   ult a5,a3,a0##ty=i64
+;;   sltu a5,a3,a0
 ;;   trap_if a5,heap_oob
 ;;   ld a5,8(a2)
-;;   ugt a6,a3,a5##ty=i64
+;;   sltu a6,a5,a3
 ;;   ld a5,0(a2)
 ;;   add a5,a5,a0
 ;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
 ;;   add a5,a5,a7
 ;;   li a7,0
 ;;   andi t2,a6,255
-;;   sltu a2,zero,t2
+;;   snez a2,t2
 ;;   sub a3,zero,a2
 ;;   and a6,a7,a3
 ;;   not a7,a3
@@ -68,17 +68,17 @@
 ;; block0:
 ;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0004
 ;;   add a3,a0,a4
-;;   ult a5,a3,a0##ty=i64
+;;   sltu a5,a3,a0
 ;;   trap_if a5,heap_oob
 ;;   ld a5,8(a1)
-;;   ugt a6,a3,a5##ty=i64
+;;   sltu a6,a5,a3
 ;;   ld a5,0(a1)
 ;;   add a5,a5,a0
 ;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
 ;;   add a5,a5,a7
 ;;   li a7,0
 ;;   andi t2,a6,255
-;;   sltu a1,zero,t2
+;;   snez a1,t2
 ;;   sub a3,zero,a1
 ;;   and a6,a7,a3
 ;;   not a7,a3
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index c488b2fa0f75..a6e2f7e9bd87 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,38 +41,40 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld t2,8(a2)
-;;   uge a3,a0,t2##ty=i64
-;;   ld t2,0(a2)
-;;   add t2,t2,a0
-;;   li a2,0
-;;   andi a6,a3,255
-;;   sltu t3,zero,a6
-;;   sub t0,zero,t3
-;;   and a0,a2,t0
-;;   not a2,t0
-;;   and a3,t2,a2
-;;   or a5,a0,a3
-;;   sb a1,0(a5)
+;;   ld a3,8(a2)
+;;   sltu t2,a0,a3
+;;   xori a4,t2,1
+;;   ld a2,0(a2)
+;;   add a0,a2,a0
+;;   li a3,0
+;;   andi a7,a4,255
+;;   snez t4,a7
+;;   sub t1,zero,t4
+;;   and a2,a3,t1
+;;   not a3,t1
+;;   and a4,a0,a3
+;;   or a6,a2,a4
+;;   sb a1,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld t2,8(a1)
-;;   uge a2,a0,t2##ty=i64
-;;   ld t2,0(a1)
-;;   add t2,t2,a0
-;;   li a1,0
-;;   andi a6,a2,255
-;;   sltu t3,zero,a6
-;;   sub t0,zero,t3
-;;   and a0,a1,t0
-;;   not a1,t0
-;;   and a3,t2,a1
-;;   or a5,a0,a3
-;;   lbu a0,0(a5)
+;;   ld a2,8(a1)
+;;   sltu t2,a0,a2
+;;   xori a3,t2,1
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   li a2,0
+;;   andi a7,a3,255
+;;   snez t4,a7
+;;   sub t1,zero,t4
+;;   and a1,a2,t1
+;;   not a2,t1
+;;   and a4,a0,a2
+;;   or a6,a1,a4
+;;   lbu a0,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index dcd8657c46ba..4468295a0cba 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -45,14 +45,14 @@
 ;;   lui a5,1048575
 ;;   addi a5,a5,4095
 ;;   add a4,a4,a5
-;;   ugt a5,a0,a4##ty=i64
+;;   sltu a5,a4,a0
 ;;   ld a4,0(a2)
 ;;   add a4,a4,a0
 ;;   lui a6,1
 ;;   add a4,a4,a6
 ;;   li a6,0
 ;;   andi t1,a5,255
-;;   sltu a0,zero,t1
+;;   snez a0,t1
 ;;   sub a2,zero,a0
 ;;   and a5,a6,a2
 ;;   not a6,a2
@@ -69,14 +69,14 @@
 ;;   lui a5,1048575
 ;;   addi a5,a5,4095
 ;;   add a4,a4,a5
-;;   ugt a5,a0,a4##ty=i64
+;;   sltu a5,a4,a0
 ;;   ld a4,0(a1)
 ;;   add a4,a4,a0
 ;;   lui a6,1
 ;;   add a4,a4,a6
 ;;   li a6,0
 ;;   andi t1,a5,255
-;;   sltu a0,zero,t1
+;;   snez a0,t1
 ;;   sub a2,zero,a0
 ;;   and a5,a6,a2
 ;;   not a6,a2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 46030e9bcb2d..0762ccc59870 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -43,17 +43,17 @@
 ;; block0:
 ;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0001
 ;;   add a3,a0,a4
-;;   ult a5,a3,a0##ty=i64
+;;   sltu a5,a3,a0
 ;;   trap_if a5,heap_oob
 ;;   ld a5,8(a2)
-;;   ugt a6,a3,a5##ty=i64
+;;   sltu a6,a5,a3
 ;;   ld a5,0(a2)
 ;;   add a5,a5,a0
 ;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
 ;;   add a5,a5,a7
 ;;   li a7,0
 ;;   andi t2,a6,255
-;;   sltu a2,zero,t2
+;;   snez a2,t2
 ;;   sub a3,zero,a2
 ;;   and a6,a7,a3
 ;;   not a7,a3
@@ -68,17 +68,17 @@
 ;; block0:
 ;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0001
 ;;   add a3,a0,a4
-;;   ult a5,a3,a0##ty=i64
+;;   sltu a5,a3,a0
 ;;   trap_if a5,heap_oob
 ;;   ld a5,8(a1)
-;;   ugt a6,a3,a5##ty=i64
+;;   sltu a6,a5,a3
 ;;   ld a5,0(a1)
 ;;   add a5,a5,a0
 ;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
 ;;   add a5,a5,a7
 ;;   li a7,0
 ;;   andi t2,a6,255
-;;   sltu a1,zero,t2
+;;   snez a1,t2
 ;;   sub a3,zero,a1
 ;;   and a6,a7,a3
 ;;   not a7,a3
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
index a248ccc6f0d5..91ab6956eb21 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a4,8(a2)
-;;   ugt a4,a0,a4##ty=i64
+;;   sltu a4,a4,a0
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a5,0(a2)
@@ -57,7 +57,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a4,8(a1)
-;;   ugt a4,a0,a4##ty=i64
+;;   sltu a4,a4,a0
 ;;   bne a4,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a5,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
index 7fc16caef684..1dbeeb76f094 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a6,8(a2)
-;;   ugt a6,a0,a6##ty=i64
+;;   sltu a6,a6,a0
 ;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a7,0(a2)
@@ -59,7 +59,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a6,8(a1)
-;;   ugt a6,a0,a6##ty=i64
+;;   sltu a6,a6,a0
 ;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a7,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
index b76521a575eb..574bc5570e8d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0xffff0000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a6,8(a2)
-;;   ugt a6,a0,a6##ty=i64
+;;   sltu a6,a6,a0
 ;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a7,0(a2)
@@ -59,7 +59,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a6,8(a1)
-;;   ugt a6,a0,a6##ty=i64
+;;   sltu a6,a6,a0
 ;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a7,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 3f302ff333cc..f7f439c940d5 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -41,13 +41,14 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a4,8(a2)
-;;   uge a4,a0,a4##ty=i64
-;;   bne a4,zero,taken(label3),not_taken(label1)
+;;   ld a5,8(a2)
+;;   sltu a4,a0,a5
+;;   xori a6,a4,1
+;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
-;;   ld a5,0(a2)
-;;   add a5,a5,a0
-;;   sb a1,0(a5)
+;;   ld a6,0(a2)
+;;   add a6,a6,a0
+;;   sb a1,0(a6)
 ;;   j label2
 ;; block2:
 ;;   ret
@@ -56,13 +57,14 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a4,8(a1)
-;;   uge a4,a0,a4##ty=i64
-;;   bne a4,zero,taken(label3),not_taken(label1)
+;;   ld a5,8(a1)
+;;   sltu a4,a0,a5
+;;   xori a6,a4,1
+;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
-;;   ld a5,0(a1)
-;;   add a5,a5,a0
-;;   lbu a0,0(a5)
+;;   ld a6,0(a1)
+;;   add a6,a6,a0
+;;   lbu a0,0(a6)
 ;;   j label2
 ;; block2:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 41435f04a907..2145e6b4e6ce 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a6,8(a2)
-;;   ugt a6,a0,a6##ty=i64
+;;   sltu a6,a6,a0
 ;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a7,0(a2)
@@ -59,7 +59,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a6,8(a1)
-;;   ugt a6,a0,a6##ty=i64
+;;   sltu a6,a6,a0
 ;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a7,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
index 08213f990617..3faf5a0c659c 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0xffff0000_offset.wat
@@ -42,7 +42,7 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a6,8(a2)
-;;   ugt a6,a0,a6##ty=i64
+;;   sltu a6,a6,a0
 ;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a7,0(a2)
@@ -59,7 +59,7 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a6,8(a1)
-;;   ugt a6,a0,a6##ty=i64
+;;   sltu a6,a6,a0
 ;;   bne a6,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a7,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index 1bd978036ebe..865fb6ef932c 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -42,12 +42,12 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld t2,8(a2)
-;;   ugt a3,a0,t2##ty=i64
+;;   sltu a3,t2,a0
 ;;   ld t2,0(a2)
 ;;   add t2,t2,a0
 ;;   li a2,0
 ;;   andi a6,a3,255
-;;   sltu t3,zero,a6
+;;   snez t3,a6
 ;;   sub t0,zero,t3
 ;;   and a0,a2,t0
 ;;   not a2,t0
@@ -61,12 +61,12 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld t2,8(a1)
-;;   ugt a2,a0,t2##ty=i64
+;;   sltu a2,t2,a0
 ;;   ld t2,0(a1)
 ;;   add t2,t2,a0
 ;;   li a1,0
 ;;   andi a6,a2,255
-;;   sltu t3,zero,a6
+;;   snez t3,a6
 ;;   sub t0,zero,t3
 ;;   and a0,a1,t0
 ;;   not a1,t0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index ab8b1ebd3ea7..94056be2614d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -42,14 +42,14 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   lui a4,1
 ;;   add a2,a2,a4
 ;;   li a4,0
 ;;   andi t3,a3,255
-;;   sltu t0,zero,t3
+;;   snez t0,t3
 ;;   sub t2,zero,t0
 ;;   and a3,a4,t2
 ;;   not a4,t2
@@ -63,14 +63,14 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   ugt a2,a0,a2##ty=i64
+;;   sltu a2,a2,a0
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a0
 ;;   lui a3,1
 ;;   add a1,a1,a3
 ;;   li a3,0
 ;;   andi t3,a2,255
-;;   sltu t0,zero,t3
+;;   snez t0,t3
 ;;   sub t2,zero,t0
 ;;   and a2,a3,t2
 ;;   not a3,t2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index fb3ee241fa6b..c3ccf2b79acd 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -42,14 +42,14 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0000
 ;;   add a2,a2,a4
 ;;   li a4,0
 ;;   andi t3,a3,255
-;;   sltu t0,zero,t3
+;;   snez t0,t3
 ;;   sub t2,zero,t0
 ;;   and a3,a4,t2
 ;;   not a4,t2
@@ -63,14 +63,14 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   ugt a2,a0,a2##ty=i64
+;;   sltu a2,a2,a0
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a0
 ;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
 ;;   add a1,a1,a3
 ;;   li a3,0
 ;;   andi t3,a2,255
-;;   sltu t0,zero,t3
+;;   snez t0,t3
 ;;   sub t2,zero,t0
 ;;   and a2,a3,t2
 ;;   not a3,t2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 61bf3ae3942a..37a79c1c0556 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,38 +41,40 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld t2,8(a2)
-;;   uge a3,a0,t2##ty=i64
-;;   ld t2,0(a2)
-;;   add t2,t2,a0
-;;   li a2,0
-;;   andi a6,a3,255
-;;   sltu t3,zero,a6
-;;   sub t0,zero,t3
-;;   and a0,a2,t0
-;;   not a2,t0
-;;   and a3,t2,a2
-;;   or a5,a0,a3
-;;   sb a1,0(a5)
+;;   ld a3,8(a2)
+;;   sltu t2,a0,a3
+;;   xori a4,t2,1
+;;   ld a2,0(a2)
+;;   add a0,a2,a0
+;;   li a3,0
+;;   andi a7,a4,255
+;;   snez t4,a7
+;;   sub t1,zero,t4
+;;   and a2,a3,t1
+;;   not a3,t1
+;;   and a4,a0,a3
+;;   or a6,a2,a4
+;;   sb a1,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld t2,8(a1)
-;;   uge a2,a0,t2##ty=i64
-;;   ld t2,0(a1)
-;;   add t2,t2,a0
-;;   li a1,0
-;;   andi a6,a2,255
-;;   sltu t3,zero,a6
-;;   sub t0,zero,t3
-;;   and a0,a1,t0
-;;   not a1,t0
-;;   and a3,t2,a1
-;;   or a5,a0,a3
-;;   lbu a0,0(a5)
+;;   ld a2,8(a1)
+;;   sltu t2,a0,a2
+;;   xori a3,t2,1
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   li a2,0
+;;   andi a7,a3,255
+;;   snez t4,a7
+;;   sub t1,zero,t4
+;;   and a1,a2,t1
+;;   not a2,t1
+;;   and a4,a0,a2
+;;   or a6,a1,a4
+;;   lbu a0,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index c91ab3179c4e..bc08a4083dc3 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -42,14 +42,14 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   lui a4,1
 ;;   add a2,a2,a4
 ;;   li a4,0
 ;;   andi t3,a3,255
-;;   sltu t0,zero,t3
+;;   snez t0,t3
 ;;   sub t2,zero,t0
 ;;   and a3,a4,t2
 ;;   not a4,t2
@@ -63,14 +63,14 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   ugt a2,a0,a2##ty=i64
+;;   sltu a2,a2,a0
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a0
 ;;   lui a3,1
 ;;   add a1,a1,a3
 ;;   li a3,0
 ;;   andi t3,a2,255
-;;   sltu t0,zero,t3
+;;   snez t0,t3
 ;;   sub t2,zero,t0
 ;;   and a2,a3,t2
 ;;   not a3,t2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index ef2f55b8b21b..376077b07f22 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -42,14 +42,14 @@
 ;; function u0:0:
 ;; block0:
 ;;   ld a3,8(a2)
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a3,a0
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
 ;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0000
 ;;   add a2,a2,a4
 ;;   li a4,0
 ;;   andi t3,a3,255
-;;   sltu t0,zero,t3
+;;   snez t0,t3
 ;;   sub t2,zero,t0
 ;;   and a3,a4,t2
 ;;   not a4,t2
@@ -63,14 +63,14 @@
 ;; function u0:1:
 ;; block0:
 ;;   ld a2,8(a1)
-;;   ugt a2,a0,a2##ty=i64
+;;   sltu a2,a2,a0
 ;;   ld a1,0(a1)
 ;;   add a1,a1,a0
 ;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
 ;;   add a1,a1,a3
 ;;   li a3,0
 ;;   andi t3,a2,255
-;;   sltu t0,zero,t3
+;;   snez t0,t3
 ;;   sub t2,zero,t0
 ;;   and a2,a3,t2
 ;;   not a3,t2
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat
index f4a7174a6e9b..e1379ba2f1e6 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0_offset.wat
@@ -43,7 +43,7 @@
 ;;   srli t3,a6,32
 ;;   lui a7,65536
 ;;   addi a7,a7,4092
-;;   ugt a7,t3,a7##ty=i64
+;;   sltu a7,a7,t3
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t4,0(a2)
@@ -61,7 +61,7 @@
 ;;   srli t3,a6,32
 ;;   lui a7,65536
 ;;   addi a7,a7,4092
-;;   ugt a7,t3,a7##ty=i64
+;;   sltu a7,a7,t3
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t4,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
index af003621a851..a4e685204f48 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
@@ -43,7 +43,7 @@
 ;;   srli t0,t3,32
 ;;   lui t4,65535
 ;;   addi t4,t4,4092
-;;   ugt t4,t0,t4##ty=i64
+;;   sltu t4,t4,t0
 ;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t1,0(a2)
@@ -63,7 +63,7 @@
 ;;   srli t0,t3,32
 ;;   lui t4,65535
 ;;   addi t4,t4,4092
-;;   ugt t4,t0,t4##ty=i64
+;;   sltu t4,t4,t0
 ;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t1,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
index 6a6ccb51e9a2..2133f747d244 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -43,7 +43,7 @@
 ;;   srli t3,a6,32
 ;;   lui a7,65536
 ;;   addi a7,a7,4095
-;;   ugt a7,t3,a7##ty=i64
+;;   sltu a7,a7,t3
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t4,0(a2)
@@ -61,7 +61,7 @@
 ;;   srli t3,a6,32
 ;;   lui a7,65536
 ;;   addi a7,a7,4095
-;;   ugt a7,t3,a7##ty=i64
+;;   sltu a7,a7,t3
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t4,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 5a8fbbc128a4..fe07aa90376e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -43,7 +43,7 @@
 ;;   srli t0,t3,32
 ;;   lui t4,65535
 ;;   addi t4,t4,4095
-;;   ugt t4,t0,t4##ty=i64
+;;   sltu t4,t4,t0
 ;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t1,0(a2)
@@ -63,7 +63,7 @@
 ;;   srli t0,t3,32
 ;;   lui t4,65535
 ;;   addi t4,t4,4095
-;;   ugt t4,t0,t4##ty=i64
+;;   sltu t4,t4,t0
 ;;   bne t4,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t1,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
index b709b33b0bfc..d9f503c03170 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -40,21 +40,22 @@
 ;; function u0:0:
 ;; block0:
 ;;   slli a3,a0,32
-;;   srli a3,a3,32
-;;   lui a4,65536
-;;   addi a4,a4,4092
-;;   ugt a4,a3,a4##ty=i64
-;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   li a3,0
-;;   andi t4,a4,255
-;;   sltu t1,zero,t4
-;;   sub a0,zero,t1
-;;   and a3,a3,a0
-;;   not a4,a0
-;;   and a6,a2,a4
-;;   or t3,a3,a6
-;;   sw a1,0(t3)
+;;   srli a4,a3,32
+;;   lui a3,65536
+;;   addi a3,a3,4093
+;;   sltu a5,a4,a3
+;;   xori a6,a5,1
+;;   ld a3,0(a2)
+;;   add a3,a3,a4
+;;   li a4,0
+;;   andi t0,a6,255
+;;   snez t2,t0
+;;   sub a2,zero,t2
+;;   and a4,a4,a2
+;;   not a5,a2
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   sw a1,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
@@ -62,21 +63,22 @@
 ;; function u0:1:
 ;; block0:
 ;;   slli a2,a0,32
-;;   srli a3,a2,32
+;;   srli a4,a2,32
 ;;   lui a2,65536
-;;   addi a2,a2,4092
-;;   ugt a4,a3,a2##ty=i64
-;;   ld a2,0(a1)
-;;   add a2,a2,a3
-;;   li a3,0
-;;   andi t4,a4,255
-;;   sltu t1,zero,t4
-;;   sub a0,zero,t1
-;;   and a3,a3,a0
-;;   not a4,a0
-;;   and a6,a2,a4
-;;   or t3,a3,a6
-;;   lw a0,0(t3)
+;;   addi a2,a2,4093
+;;   sltu a5,a4,a2
+;;   xori a6,a5,1
+;;   ld a3,0(a1)
+;;   add a3,a3,a4
+;;   li a4,0
+;;   andi t0,a6,255
+;;   snez t2,t0
+;;   sub a1,zero,t2
+;;   and a4,a4,a1
+;;   not a5,a1
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   lw a0,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index a827bbe9882f..643152d0ea78 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -39,48 +39,50 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a6,a3,32
-;;   lui a4,65535
-;;   addi a4,a4,4092
-;;   ugt a5,a6,a4##ty=i64
-;;   ld a4,0(a2)
-;;   add a4,a4,a6
+;;   slli a4,a0,32
+;;   srli a6,a4,32
+;;   lui a3,65535
+;;   addi a3,a3,4093
+;;   sltu a7,a6,a3
+;;   xori t3,a7,1
+;;   ld a5,0(a2)
+;;   add a5,a5,a6
 ;;   lui a6,1
-;;   add a4,a4,a6
+;;   add a5,a5,a6
 ;;   li a6,0
-;;   andi t1,a5,255
-;;   sltu a0,zero,t1
-;;   sub a2,zero,a0
-;;   and a5,a6,a2
-;;   not a6,a2
-;;   and t3,a4,a6
-;;   or t0,a5,t3
-;;   sw a1,0(t0)
+;;   andi t2,t3,255
+;;   snez a2,t2
+;;   sub a3,zero,a2
+;;   and a6,a6,a3
+;;   not a7,a3
+;;   and t4,a5,a7
+;;   or t1,a6,t4
+;;   sw a1,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a3,a0,32
-;;   srli a6,a3,32
-;;   lui a4,65535
-;;   addi a4,a4,4092
-;;   ugt a5,a6,a4##ty=i64
-;;   ld a4,0(a1)
-;;   add a4,a4,a6
+;;   slli a4,a0,32
+;;   srli a6,a4,32
+;;   lui a3,65535
+;;   addi a3,a3,4093
+;;   sltu a7,a6,a3
+;;   xori t3,a7,1
+;;   ld a5,0(a1)
+;;   add a5,a5,a6
 ;;   lui a6,1
-;;   add a4,a4,a6
+;;   add a5,a5,a6
 ;;   li a6,0
-;;   andi t1,a5,255
-;;   sltu a0,zero,t1
-;;   sub a2,zero,a0
-;;   and a5,a6,a2
-;;   not a6,a2
-;;   and t3,a4,a6
-;;   or t0,a5,t3
-;;   lw a0,0(t0)
+;;   andi t2,t3,255
+;;   snez a1,t2
+;;   sub a3,zero,a1
+;;   and a6,a6,a3
+;;   not a7,a3
+;;   and t4,a5,a7
+;;   or t1,a6,t4
+;;   lw a0,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 78de2ddc8dcc..949014b6f6e6 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,14 +41,14 @@
 ;; block0:
 ;;   slli a3,a0,32
 ;;   srli a3,a3,32
-;;   lui a4,65536
-;;   addi a4,a4,4095
-;;   ugt a4,a3,a4##ty=i64
+;;   lui a0,65536
+;;   sltu a4,a3,a0
+;;   xori a4,a4,1
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a3
 ;;   li a3,0
 ;;   andi t4,a4,255
-;;   sltu t1,zero,t4
+;;   snez t1,t4
 ;;   sub a0,zero,t1
 ;;   and a3,a3,a0
 ;;   not a4,a0
@@ -63,14 +63,14 @@
 ;; block0:
 ;;   slli a2,a0,32
 ;;   srli a3,a2,32
-;;   lui a2,65536
-;;   addi a2,a2,4095
-;;   ugt a4,a3,a2##ty=i64
+;;   lui a0,65536
+;;   sltu a2,a3,a0
+;;   xori a4,a2,1
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a3
 ;;   li a3,0
 ;;   andi t4,a4,255
-;;   sltu t1,zero,t4
+;;   snez t1,t4
 ;;   sub a0,zero,t1
 ;;   and a3,a3,a0
 ;;   not a4,a0
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 83e1ce6e0d67..fab7c596d135 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -40,19 +40,19 @@
 ;; function u0:0:
 ;; block0:
 ;;   slli a3,a0,32
-;;   srli a6,a3,32
-;;   lui a4,65535
-;;   addi a4,a4,4095
-;;   ugt a5,a6,a4##ty=i64
+;;   srli a5,a3,32
+;;   lui a3,65535
+;;   sltu a4,a5,a3
+;;   xori a6,a4,1
 ;;   ld a4,0(a2)
-;;   add a4,a4,a6
-;;   lui a6,1
-;;   add a4,a4,a6
-;;   li a6,0
-;;   andi t1,a5,255
-;;   sltu a0,zero,t1
+;;   add a4,a4,a5
+;;   lui a5,1
+;;   add a4,a4,a5
+;;   li a5,0
+;;   andi t1,a6,255
+;;   snez a0,t1
 ;;   sub a2,zero,a0
-;;   and a5,a6,a2
+;;   and a5,a5,a2
 ;;   not a6,a2
 ;;   and t3,a4,a6
 ;;   or t0,a5,t3
@@ -64,19 +64,19 @@
 ;; function u0:1:
 ;; block0:
 ;;   slli a3,a0,32
-;;   srli a6,a3,32
-;;   lui a4,65535
-;;   addi a4,a4,4095
-;;   ugt a5,a6,a4##ty=i64
+;;   srli a5,a3,32
+;;   lui a2,65535
+;;   sltu a4,a5,a2
+;;   xori a6,a4,1
 ;;   ld a4,0(a1)
-;;   add a4,a4,a6
-;;   lui a6,1
-;;   add a4,a4,a6
-;;   li a6,0
-;;   andi t1,a5,255
-;;   sltu a0,zero,t1
+;;   add a4,a4,a5
+;;   lui a5,1
+;;   add a4,a4,a5
+;;   li a5,0
+;;   andi t1,a6,255
+;;   snez a0,t1
 ;;   sub a2,zero,a0
-;;   and a5,a6,a2
+;;   and a5,a5,a2
 ;;   not a6,a2
 ;;   and t3,a4,a6
 ;;   or t0,a5,t3
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0_offset.wat
index 48035981444f..d7da51ae80ed 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a5,65536
 ;;   addi a5,a5,4092
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   bne a5,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a6,0(a2)
@@ -57,7 +57,7 @@
 ;; block0:
 ;;   lui a5,65536
 ;;   addi a5,a5,4092
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   bne a5,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a6,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
index e5dc45b23db4..b03360481902 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a7,65535
 ;;   addi a7,a7,4092
-;;   ugt a7,a0,a7##ty=i64
+;;   sltu a7,a7,a0
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t3,0(a2)
@@ -59,7 +59,7 @@
 ;; block0:
 ;;   lui a7,65535
 ;;   addi a7,a7,4092
-;;   ugt a7,a0,a7##ty=i64
+;;   sltu a7,a7,a0
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t3,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
index 1c3e1fdfc4ce..0a350debcb85 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a5,65536
 ;;   addi a5,a5,4095
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   bne a5,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a6,0(a2)
@@ -57,7 +57,7 @@
 ;; block0:
 ;;   lui a5,65536
 ;;   addi a5,a5,4095
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   bne a5,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a6,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
index 320be4fbcd78..8111dddb0134 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a7,65535
 ;;   addi a7,a7,4095
-;;   ugt a7,a0,a7##ty=i64
+;;   sltu a7,a7,a0
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t3,0(a2)
@@ -59,7 +59,7 @@
 ;; block0:
 ;;   lui a7,65535
 ;;   addi a7,a7,4095
-;;   ugt a7,a0,a7##ty=i64
+;;   sltu a7,a7,a0
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t3,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
index e30e0a0a1213..d8c3758809b7 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -39,42 +39,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   mv a4,a2
-;;   lui a2,65536
-;;   addi a2,a2,4092
-;;   ugt a2,a0,a2##ty=i64
-;;   ld a3,0(a4)
-;;   add a0,a3,a0
+;;   lui t2,65536
+;;   addi t2,t2,4093
+;;   sltu a3,a0,t2
+;;   xori a4,a3,1
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
 ;;   li a3,0
-;;   andi a7,a2,255
-;;   sltu t4,zero,a7
-;;   sub t1,zero,t4
-;;   and a2,a3,t1
-;;   not a3,t1
-;;   and a4,a0,a3
-;;   or a6,a2,a4
-;;   sw a1,0(a6)
+;;   andi t3,a4,255
+;;   snez t0,t3
+;;   sub t2,zero,t0
+;;   and a3,a3,t2
+;;   not a4,t2
+;;   and a5,a2,a4
+;;   or a7,a3,a5
+;;   sw a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   mv a4,a1
-;;   lui a1,65536
-;;   addi a1,a1,4092
-;;   ugt a1,a0,a1##ty=i64
-;;   ld a2,0(a4)
-;;   add a0,a2,a0
+;;   lui t2,65536
+;;   addi t2,t2,4093
+;;   sltu a2,a0,t2
+;;   xori a4,a2,1
+;;   ld a1,0(a1)
+;;   add a1,a1,a0
 ;;   li a2,0
-;;   andi a7,a1,255
-;;   sltu t4,zero,a7
-;;   sub t1,zero,t4
-;;   and a1,a2,t1
-;;   not a2,t1
-;;   and a4,a0,a2
-;;   or a6,a1,a4
-;;   lw a0,0(a6)
+;;   andi t3,a4,255
+;;   snez t0,t3
+;;   sub t2,zero,t0
+;;   and a2,a2,t2
+;;   not a3,t2
+;;   and a5,a1,a3
+;;   or a7,a2,a5
+;;   lw a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 1c03fd957463..920c2c0a9d25 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -40,21 +40,22 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a3,a3,4092
-;;   ugt a3,a0,a3##ty=i64
-;;   ld a2,0(a2)
-;;   add a2,a2,a0
+;;   addi a3,a3,4093
+;;   sltu a4,a0,a3
+;;   xori a6,a4,1
+;;   ld a3,0(a2)
+;;   add a3,a3,a0
 ;;   lui a4,1
-;;   add a2,a2,a4
+;;   add a3,a3,a4
 ;;   li a4,0
-;;   andi t4,a3,255
-;;   sltu t1,zero,t4
-;;   sub a0,zero,t1
-;;   and a3,a4,a0
-;;   not a4,a0
-;;   and a6,a2,a4
-;;   or t3,a3,a6
-;;   sw a1,0(t3)
+;;   andi t0,a6,255
+;;   snez t2,t0
+;;   sub a2,zero,t2
+;;   and a4,a4,a2
+;;   not a5,a2
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   sw a1,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
@@ -62,21 +63,22 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a2,65535
-;;   addi a2,a2,4092
-;;   ugt a3,a0,a2##ty=i64
-;;   ld a2,0(a1)
-;;   add a2,a2,a0
+;;   addi a2,a2,4093
+;;   sltu a4,a0,a2
+;;   xori a6,a4,1
+;;   ld a3,0(a1)
+;;   add a3,a3,a0
 ;;   lui a4,1
-;;   add a2,a2,a4
+;;   add a3,a3,a4
 ;;   li a4,0
-;;   andi t4,a3,255
-;;   sltu t1,zero,t4
-;;   sub a0,zero,t1
-;;   and a3,a4,a0
-;;   not a4,a0
-;;   and a6,a2,a4
-;;   or t3,a3,a6
-;;   lw a0,0(t3)
+;;   andi t0,a6,255
+;;   snez t2,t0
+;;   sub a1,zero,t2
+;;   and a4,a4,a1
+;;   not a5,a1
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   lw a0,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index d755a4f65adc..42c3284b470d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -40,14 +40,14 @@
 ;; function u0:0:
 ;; block0:
 ;;   mv a4,a2
-;;   lui a2,65536
-;;   addi a2,a2,4095
-;;   ugt a2,a0,a2##ty=i64
+;;   lui t1,65536
+;;   sltu a2,a0,t1
+;;   xori a2,a2,1
 ;;   ld a3,0(a4)
 ;;   add a0,a3,a0
 ;;   li a3,0
 ;;   andi a7,a2,255
-;;   sltu t4,zero,a7
+;;   snez t4,a7
 ;;   sub t1,zero,t4
 ;;   and a2,a3,t1
 ;;   not a3,t1
@@ -60,17 +60,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   mv a4,a1
-;;   lui a1,65536
-;;   addi a1,a1,4095
-;;   ugt a1,a0,a1##ty=i64
-;;   ld a2,0(a4)
-;;   add a0,a2,a0
-;;   li a2,0
-;;   andi a7,a1,255
-;;   sltu t4,zero,a7
+;;   lui t1,65536
+;;   sltu a2,a0,t1
+;;   xori a2,a2,1
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   li a1,0
+;;   andi a7,a2,255
+;;   snez t4,a7
 ;;   sub t1,zero,t4
-;;   and a1,a2,t1
+;;   and a1,a1,t1
 ;;   not a2,t1
 ;;   and a4,a0,a2
 ;;   or a6,a1,a4
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 6f2b6a18a934..2059e88cfaef 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -40,17 +40,17 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a3,a3,4095
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a0,a3
+;;   xori a4,a3,1
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
-;;   lui a4,1
-;;   add a2,a2,a4
-;;   li a4,0
-;;   andi t4,a3,255
-;;   sltu t1,zero,t4
+;;   lui a3,1
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   snez t1,t4
 ;;   sub a0,zero,t1
-;;   and a3,a4,a0
+;;   and a3,a3,a0
 ;;   not a4,a0
 ;;   and a6,a2,a4
 ;;   or t3,a3,a6
@@ -62,17 +62,17 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a2,65535
-;;   addi a2,a2,4095
-;;   ugt a3,a0,a2##ty=i64
+;;   sltu a2,a0,a2
+;;   xori a4,a2,1
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a0
-;;   lui a4,1
-;;   add a2,a2,a4
-;;   li a4,0
-;;   andi t4,a3,255
-;;   sltu t1,zero,t4
+;;   lui a3,1
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   snez t1,t4
 ;;   sub a0,zero,t1
-;;   and a3,a4,a0
+;;   and a3,a3,a0
 ;;   not a4,a0
 ;;   and a6,a2,a4
 ;;   or t3,a3,a6
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
index c0f6b6f0d612..922c23171868 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a5,65536
 ;;   addi a5,a5,4092
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   bne a5,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a6,0(a2)
@@ -57,7 +57,7 @@
 ;; block0:
 ;;   lui a5,65536
 ;;   addi a5,a5,4092
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   bne a5,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a6,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
index b326b7a1c559..a465db8de36d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i32_access_0x1000_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a7,65535
 ;;   addi a7,a7,4092
-;;   ugt a7,a0,a7##ty=i64
+;;   sltu a7,a7,a0
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t3,0(a2)
@@ -59,7 +59,7 @@
 ;; block0:
 ;;   lui a7,65535
 ;;   addi a7,a7,4092
-;;   ugt a7,a0,a7##ty=i64
+;;   sltu a7,a7,a0
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t3,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
index 05fa839f476a..101262673508 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a5,65536
 ;;   addi a5,a5,4095
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   bne a5,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a6,0(a2)
@@ -57,7 +57,7 @@
 ;; block0:
 ;;   lui a5,65536
 ;;   addi a5,a5,4095
-;;   ugt a5,a0,a5##ty=i64
+;;   sltu a5,a5,a0
 ;;   bne a5,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld a6,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
index 239f0c75c873..ef8fb17f664d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_no_spectre_i8_access_0x1000_offset.wat
@@ -41,7 +41,7 @@
 ;; block0:
 ;;   lui a7,65535
 ;;   addi a7,a7,4095
-;;   ugt a7,a0,a7##ty=i64
+;;   sltu a7,a7,a0
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t3,0(a2)
@@ -59,7 +59,7 @@
 ;; block0:
 ;;   lui a7,65535
 ;;   addi a7,a7,4095
-;;   ugt a7,a0,a7##ty=i64
+;;   sltu a7,a7,a0
 ;;   bne a7,zero,taken(label3),not_taken(label1)
 ;; block1:
 ;;   ld t3,0(a1)
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index 6d358beffe7a..c8c7afa0f840 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -39,42 +39,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   mv a4,a2
-;;   lui a2,65536
-;;   addi a2,a2,4092
-;;   ugt a2,a0,a2##ty=i64
-;;   ld a3,0(a4)
-;;   add a0,a3,a0
+;;   lui t2,65536
+;;   addi t2,t2,4093
+;;   sltu a3,a0,t2
+;;   xori a4,a3,1
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
 ;;   li a3,0
-;;   andi a7,a2,255
-;;   sltu t4,zero,a7
-;;   sub t1,zero,t4
-;;   and a2,a3,t1
-;;   not a3,t1
-;;   and a4,a0,a3
-;;   or a6,a2,a4
-;;   sw a1,0(a6)
+;;   andi t3,a4,255
+;;   snez t0,t3
+;;   sub t2,zero,t0
+;;   and a3,a3,t2
+;;   not a4,t2
+;;   and a5,a2,a4
+;;   or a7,a3,a5
+;;   sw a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   mv a4,a1
-;;   lui a1,65536
-;;   addi a1,a1,4092
-;;   ugt a1,a0,a1##ty=i64
-;;   ld a2,0(a4)
-;;   add a0,a2,a0
+;;   lui t2,65536
+;;   addi t2,t2,4093
+;;   sltu a2,a0,t2
+;;   xori a4,a2,1
+;;   ld a1,0(a1)
+;;   add a1,a1,a0
 ;;   li a2,0
-;;   andi a7,a1,255
-;;   sltu t4,zero,a7
-;;   sub t1,zero,t4
-;;   and a1,a2,t1
-;;   not a2,t1
-;;   and a4,a0,a2
-;;   or a6,a1,a4
-;;   lw a0,0(a6)
+;;   andi t3,a4,255
+;;   snez t0,t3
+;;   sub t2,zero,t0
+;;   and a2,a2,t2
+;;   not a3,t2
+;;   and a5,a1,a3
+;;   or a7,a2,a5
+;;   lw a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index b40a4633afd5..a415eef81857 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -40,21 +40,22 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a3,a3,4092
-;;   ugt a3,a0,a3##ty=i64
-;;   ld a2,0(a2)
-;;   add a2,a2,a0
+;;   addi a3,a3,4093
+;;   sltu a4,a0,a3
+;;   xori a6,a4,1
+;;   ld a3,0(a2)
+;;   add a3,a3,a0
 ;;   lui a4,1
-;;   add a2,a2,a4
+;;   add a3,a3,a4
 ;;   li a4,0
-;;   andi t4,a3,255
-;;   sltu t1,zero,t4
-;;   sub a0,zero,t1
-;;   and a3,a4,a0
-;;   not a4,a0
-;;   and a6,a2,a4
-;;   or t3,a3,a6
-;;   sw a1,0(t3)
+;;   andi t0,a6,255
+;;   snez t2,t0
+;;   sub a2,zero,t2
+;;   and a4,a4,a2
+;;   not a5,a2
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   sw a1,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
@@ -62,21 +63,22 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a2,65535
-;;   addi a2,a2,4092
-;;   ugt a3,a0,a2##ty=i64
-;;   ld a2,0(a1)
-;;   add a2,a2,a0
+;;   addi a2,a2,4093
+;;   sltu a4,a0,a2
+;;   xori a6,a4,1
+;;   ld a3,0(a1)
+;;   add a3,a3,a0
 ;;   lui a4,1
-;;   add a2,a2,a4
+;;   add a3,a3,a4
 ;;   li a4,0
-;;   andi t4,a3,255
-;;   sltu t1,zero,t4
-;;   sub a0,zero,t1
-;;   and a3,a4,a0
-;;   not a4,a0
-;;   and a6,a2,a4
-;;   or t3,a3,a6
-;;   lw a0,0(t3)
+;;   andi t0,a6,255
+;;   snez t2,t0
+;;   sub a1,zero,t2
+;;   and a4,a4,a1
+;;   not a5,a1
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   lw a0,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index 4bbf4a4f3373..d16cfc27b4ca 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -40,14 +40,14 @@
 ;; function u0:0:
 ;; block0:
 ;;   mv a4,a2
-;;   lui a2,65536
-;;   addi a2,a2,4095
-;;   ugt a2,a0,a2##ty=i64
+;;   lui t1,65536
+;;   sltu a2,a0,t1
+;;   xori a2,a2,1
 ;;   ld a3,0(a4)
 ;;   add a0,a3,a0
 ;;   li a3,0
 ;;   andi a7,a2,255
-;;   sltu t4,zero,a7
+;;   snez t4,a7
 ;;   sub t1,zero,t4
 ;;   and a2,a3,t1
 ;;   not a3,t1
@@ -60,17 +60,16 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   mv a4,a1
-;;   lui a1,65536
-;;   addi a1,a1,4095
-;;   ugt a1,a0,a1##ty=i64
-;;   ld a2,0(a4)
-;;   add a0,a2,a0
-;;   li a2,0
-;;   andi a7,a1,255
-;;   sltu t4,zero,a7
+;;   lui t1,65536
+;;   sltu a2,a0,t1
+;;   xori a2,a2,1
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   li a1,0
+;;   andi a7,a2,255
+;;   snez t4,a7
 ;;   sub t1,zero,t4
-;;   and a1,a2,t1
+;;   and a1,a1,t1
 ;;   not a2,t1
 ;;   and a4,a0,a2
 ;;   or a6,a1,a4
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 7915fdfc5719..9e07678a52a2 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -40,17 +40,17 @@
 ;; function u0:0:
 ;; block0:
 ;;   lui a3,65535
-;;   addi a3,a3,4095
-;;   ugt a3,a0,a3##ty=i64
+;;   sltu a3,a0,a3
+;;   xori a4,a3,1
 ;;   ld a2,0(a2)
 ;;   add a2,a2,a0
-;;   lui a4,1
-;;   add a2,a2,a4
-;;   li a4,0
-;;   andi t4,a3,255
-;;   sltu t1,zero,t4
+;;   lui a3,1
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   snez t1,t4
 ;;   sub a0,zero,t1
-;;   and a3,a4,a0
+;;   and a3,a3,a0
 ;;   not a4,a0
 ;;   and a6,a2,a4
 ;;   or t3,a3,a6
@@ -62,17 +62,17 @@
 ;; function u0:1:
 ;; block0:
 ;;   lui a2,65535
-;;   addi a2,a2,4095
-;;   ugt a3,a0,a2##ty=i64
+;;   sltu a2,a0,a2
+;;   xori a4,a2,1
 ;;   ld a2,0(a1)
 ;;   add a2,a2,a0
-;;   lui a4,1
-;;   add a2,a2,a4
-;;   li a4,0
-;;   andi t4,a3,255
-;;   sltu t1,zero,t4
+;;   lui a3,1
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   snez t1,t4
 ;;   sub a0,zero,t1
-;;   and a3,a4,a0
+;;   and a3,a3,a0
 ;;   not a4,a0
 ;;   and a6,a2,a4
 ;;   or t3,a3,a6