diff --git a/arch/AArch64/AArch64GenInstrInfo.inc b/arch/AArch64/AArch64GenInstrInfo.inc index 65c9120059..8ce807b23a 100644 --- a/arch/AArch64/AArch64GenInstrInfo.inc +++ b/arch/AArch64/AArch64GenInstrInfo.inc @@ -4539,422 +4539,422 @@ enum { #define nullptr 0 -static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<insn_cache); if (i != 0) { diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h index 2e414daf8a..a8eda4f899 100644 --- a/arch/AArch64/AArch64Mapping.h +++ b/arch/AArch64/AArch64Mapping.h @@ -32,7 +32,7 @@ void arm64_op_addFP(MCInst *MI, float fp); void arm64_op_addImm(MCInst *MI, int64_t imm); -uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id); +const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id); void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, diff --git a/arch/ARM/ARMBaseInfo.h b/arch/ARM/ARMBaseInfo.h index 0f802b6c81..b7279569f6 100644 --- a/arch/ARM/ARMBaseInfo.h +++ b/arch/ARM/ARMBaseInfo.h @@ -443,30 +443,30 @@ enum TraceSyncBOpt { CSYNC = 0 }; -MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding); -MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12); +const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding); +const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12); // returns APSR with _ qualifier. // Note: ARMv7-M deprecates using MSR APSR without a _ qualifier -static inline MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) +static inline const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) { return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF)); } -static inline MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) +static inline const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) { return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF)); } // returns true if TestFeatures are all present in FeaturesRequired -static inline bool MClassSysReg_isInRequiredFeatures(MClassSysReg *TheReg, int TestFeatures) +static inline bool MClassSysReg_isInRequiredFeatures(const MClassSysReg *TheReg, int TestFeatures) { return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures); } // lookup system register using 12-bit SYSm value. // Note: the search is uniqued using M1 mask -static inline MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) +static inline const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) { return lookupMClassSysRegByM1Encoding12(SYSm); } diff --git a/arch/ARM/ARMGenInstrInfo.inc b/arch/ARM/ARMGenInstrInfo.inc index 7d22b5f0c0..82178f342b 100644 --- a/arch/ARM/ARMGenInstrInfo.inc +++ b/arch/ARM/ARMGenInstrInfo.inc @@ -2990,424 +2990,424 @@ enum { #define nullptr 0 -static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<csh->mode, ARM_FeatureMClass)) { - MClassSysReg *TheReg; + const MClassSysReg *TheReg; unsigned SYSm = (unsigned)MCOperand_getImm(Op) & 0xFFF; // 12-bit SYMm unsigned Opcode = MCInst_getOpcode(MI); @@ -1827,7 +1827,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - BankedReg *TheReg = lookupBankedRegByEncoding(Banked); + const BankedReg *TheReg = lookupBankedRegByEncoding(Banked); SStream_concat0(O, TheReg->Name); ARM_addSysReg(MI, TheReg->sysreg); diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index f9d20b40c1..a8d8698c05 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -345,7 +345,7 @@ void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) } #ifndef CAPSTONE_DIET -static const char *insn_name_maps[] = { +static const char * const insn_name_maps[] = { NULL, // ARM_INS_INVALID #include "ARMMappingInsnName.inc" }; @@ -475,7 +475,7 @@ typedef struct insn_op { uint8_t access[7]; } insn_op; -static insn_op insn_ops[] = { +static const insn_op insn_ops[] = { { // NULL item { 0 } @@ -485,7 +485,7 @@ static insn_op insn_ops[] = { }; // given internal insn id, return operand access info -uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id) +const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id) { int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h index 3e039c55ca..1f413d0ce7 100644 --- a/arch/ARM/ARMMapping.h +++ b/arch/ARM/ARMMapping.h @@ -23,7 +23,7 @@ bool ARM_rel_branch(cs_struct *h, unsigned int insn_id); bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id); -uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id); +const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id); void ARM_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, @@ -35,6 +35,6 @@ typedef struct BankedReg { uint16_t Encoding; } BankedReg; -BankedReg *lookupBankedRegByEncoding(uint8_t encoding); +const BankedReg *lookupBankedRegByEncoding(uint8_t encoding); #endif diff --git a/arch/BPF/BPFMapping.c b/arch/BPF/BPFMapping.c index 33fae2c624..e333a5f1d3 100644 --- a/arch/BPF/BPFMapping.c +++ b/arch/BPF/BPFMapping.c @@ -137,7 +137,7 @@ const char *BPF_reg_name(csh handle, unsigned int reg) if (EBPF_MODE(handle)) { if (reg < BPF_REG_R0 || reg > BPF_REG_R10) return NULL; - static const char* reg_names[11] = { + static const char reg_names[11][4] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" diff --git a/arch/EVM/EVMDisassembler.c b/arch/EVM/EVMDisassembler.c index 8f8c72d1b5..23512dbae1 100644 --- a/arch/EVM/EVMDisassembler.c +++ b/arch/EVM/EVMDisassembler.c @@ -8,7 +8,7 @@ #include "EVMDisassembler.h" #include "EVMMapping.h" -static short opcodes[256] = { +static const short opcodes[256] = { EVM_INS_STOP, EVM_INS_ADD, EVM_INS_MUL, diff --git a/arch/EVM/EVMMapping.c b/arch/EVM/EVMMapping.c index d6e94b5fe6..bbd8d41c3a 100644 --- a/arch/EVM/EVMMapping.c +++ b/arch/EVM/EVMMapping.c @@ -11,14 +11,14 @@ #include "EVMMapping.h" #ifndef CAPSTONE_DIET -static cs_evm insns[256] = { +static const cs_evm insns[256] = { #include "EVMMappingInsn.inc" }; #endif // look for @id in @insns, given its size in @max. // return -1 if not found -static int evm_insn_find(cs_evm *insns, unsigned int max, unsigned int id) +static int evm_insn_find(const cs_evm *insns, unsigned int max, unsigned int id) { if (id >= max) return -1; @@ -44,7 +44,7 @@ void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) } #ifndef CAPSTONE_DIET -static name_map insn_name_maps[256] = { +static const name_map insn_name_maps[256] = { { EVM_INS_STOP, "stop" }, { EVM_INS_ADD, "add" }, { EVM_INS_MUL, "mul" }, @@ -317,7 +317,7 @@ const char *EVM_insn_name(csh handle, unsigned int id) } #ifndef CAPSTONE_DIET -static name_map group_name_maps[] = { +static const name_map group_name_maps[] = { // generic groups { EVM_GRP_INVALID, NULL }, { EVM_GRP_JUMP, "jump" }, diff --git a/arch/M680X/M680XDisassembler.c b/arch/M680X/M680XDisassembler.c index f19bb103ff..0d7a8864f3 100644 --- a/arch/M680X/M680XDisassembler.c +++ b/arch/M680X/M680XDisassembler.c @@ -1399,11 +1399,11 @@ static void indexed09_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) } -m680x_reg g_idx12_to_reg_ids[4] = { +static const m680x_reg g_idx12_to_reg_ids[4] = { M680X_REG_X, M680X_REG_Y, M680X_REG_S, M680X_REG_PC, }; -m680x_reg g_or12_to_reg_ids[3] = { +static const m680x_reg g_or12_to_reg_ids[3] = { M680X_REG_A, M680X_REG_B, M680X_REG_D }; @@ -2130,7 +2130,7 @@ static const cpu_tables g_cpu_tables[] = { }, }; -static const char *s_cpu_type[] = { +static const char * const s_cpu_type[] = { "INVALID", "6301", "6309", "6800", "6801", "6805", "6808", "6809", "6811", "CPU12", "HCS08", }; diff --git a/arch/M680X/M680XInstPrinter.c b/arch/M680X/M680XInstPrinter.c index 2219931d58..83a9490982 100644 --- a/arch/M680X/M680XInstPrinter.c +++ b/arch/M680X/M680XInstPrinter.c @@ -87,7 +87,7 @@ static const char s_instruction_names[][6] = { "xgdx", "xgdy", }; -static name_map s_group_names[] = { +static const name_map s_group_names[] = { { M680X_GRP_INVALID, "" }, { M680X_GRP_JUMP, "jump" }, { M680X_GRP_CALL, "call" }, diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c index 42a3efdf69..4122e6b001 100644 --- a/arch/M68K/M68KDisassembler.c +++ b/arch/M68K/M68KDisassembler.c @@ -222,38 +222,38 @@ typedef struct { /* ================================= DATA ================================= */ /* ======================================================================== */ -static instruction_struct g_instruction_table[0x10000]; +static const instruction_struct g_instruction_table[0x10000]; /* used by ops like asr, ror, addq, etc */ -static uint32_t g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7}; +static const uint32_t g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7}; -static uint32_t g_5bit_data_table[32] = { +static const uint32_t g_5bit_data_table[32] = { 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 }; -static m68k_insn s_branch_lut[] = { +static const m68k_insn s_branch_lut[] = { M68K_INS_INVALID, M68K_INS_INVALID, M68K_INS_BHI, M68K_INS_BLS, M68K_INS_BCC, M68K_INS_BCS, M68K_INS_BNE, M68K_INS_BEQ, M68K_INS_BVC, M68K_INS_BVS, M68K_INS_BPL, M68K_INS_BMI, M68K_INS_BGE, M68K_INS_BLT, M68K_INS_BGT, M68K_INS_BLE, }; -static m68k_insn s_dbcc_lut[] = { +static const m68k_insn s_dbcc_lut[] = { M68K_INS_DBT, M68K_INS_DBF, M68K_INS_DBHI, M68K_INS_DBLS, M68K_INS_DBCC, M68K_INS_DBCS, M68K_INS_DBNE, M68K_INS_DBEQ, M68K_INS_DBVC, M68K_INS_DBVS, M68K_INS_DBPL, M68K_INS_DBMI, M68K_INS_DBGE, M68K_INS_DBLT, M68K_INS_DBGT, M68K_INS_DBLE, }; -static m68k_insn s_scc_lut[] = { +static const m68k_insn s_scc_lut[] = { M68K_INS_ST, M68K_INS_SF, M68K_INS_SHI, M68K_INS_SLS, M68K_INS_SCC, M68K_INS_SCS, M68K_INS_SNE, M68K_INS_SEQ, M68K_INS_SVC, M68K_INS_SVS, M68K_INS_SPL, M68K_INS_SMI, M68K_INS_SGE, M68K_INS_SLT, M68K_INS_SGT, M68K_INS_SLE, }; -static m68k_insn s_trap_lut[] = { +static const m68k_insn s_trap_lut[] = { M68K_INS_TRAPT, M68K_INS_TRAPF, M68K_INS_TRAPHI, M68K_INS_TRAPLS, M68K_INS_TRAPCC, M68K_INS_TRAPCS, M68K_INS_TRAPNE, M68K_INS_TRAPEQ, M68K_INS_TRAPVC, M68K_INS_TRAPVS, M68K_INS_TRAPPL, M68K_INS_TRAPMI, @@ -3379,7 +3379,7 @@ static void d68020_unpk_mm(m68k_info *info) static int instruction_is_valid(m68k_info *info, const unsigned int word_check) { const unsigned int instruction = info->ir; - instruction_struct *i = &g_instruction_table[instruction]; + const instruction_struct *i = &g_instruction_table[instruction]; if ( (i->word2_mask && ((word_check & i->word2_mask) != i->word2_match)) || (i->instruction == d68000_invalid) ) { diff --git a/arch/M68K/M68KInstPrinter.c b/arch/M68K/M68KInstPrinter.c index de467c324c..3f62690aec 100644 --- a/arch/M68K/M68KInstPrinter.c +++ b/arch/M68K/M68KInstPrinter.c @@ -28,9 +28,9 @@ #include "../../MCRegisterInfo.h" #ifndef CAPSTONE_DIET -static const char* s_spacing = " "; +static const char s_spacing[] = " "; -static const char* s_reg_names[] = { +static const char* const s_reg_names[] = { "invalid", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", @@ -43,7 +43,7 @@ static const char* s_reg_names[] = { "fpcr", "fpsr", "fpiar", }; -static const char* s_instruction_names[] = { +static const char* const s_instruction_names[] = { "invalid", "abcd", "add", "adda", "addi", "addq", "addx", "and", "andi", "asl", "asr", "bhs", "blo", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc", "bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble", "bra", "bsr", "bchg", "bclr", "bset", "btst", "bfchg", "bfclr", "bfexts", "bfextu", "bfffo", "bfins", @@ -367,7 +367,7 @@ const char* M68K_insn_name(csh handle, unsigned int id) } #ifndef CAPSTONE_DIET -static name_map group_name_maps[] = { +static const name_map group_name_maps[] = { { M68K_GRP_INVALID , NULL }, { M68K_GRP_JUMP, "jump" }, { M68K_GRP_RET , "ret" }, diff --git a/arch/M68K/M68KInstructionTable.inc b/arch/M68K/M68KInstructionTable.inc index 9af6f17af0..1d6dfca0cf 100644 --- a/arch/M68K/M68KInstructionTable.inc +++ b/arch/M68K/M68KInstructionTable.inc @@ -1,5 +1,5 @@ /* This table is auto-generated. DO NOT MANUALLY EDIT! Look in M68KInstructionTblGen.c for more info */ -static instruction_struct g_instruction_table[] = { +static const instruction_struct g_instruction_table[] = { { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, diff --git a/arch/MOS65XX/MOS65XXDisassembler.c b/arch/MOS65XX/MOS65XXDisassembler.c index 74297f10f3..1827ab0813 100644 --- a/arch/MOS65XX/MOS65XXDisassembler.c +++ b/arch/MOS65XX/MOS65XXDisassembler.c @@ -20,12 +20,12 @@ static const struct OpInfo OpInfoTable[]= { }; -static const char* RegNames[] = { +static const char* const RegNames[] = { "invalid", "A", "X", "Y", "P", "SP", "DP", "B", "K" }; #ifndef CAPSTONE_DIET -static const char* GroupNames[] = { +static const char* const GroupNames[] = { NULL, "jump", "call", diff --git a/arch/Mips/MipsGenDisassemblerTables.inc b/arch/Mips/MipsGenDisassemblerTables.inc index 5013293e09..e926f77884 100644 --- a/arch/Mips/MipsGenDisassemblerTables.inc +++ b/arch/Mips/MipsGenDisassemblerTables.inc @@ -24,7 +24,7 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ return (insn & fieldMask) >> startBit; \ } -static uint8_t DecoderTableCOP3_32[] = { +static const uint8_t DecoderTableCOP3_32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15 /* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51 @@ -42,7 +42,7 @@ static uint8_t DecoderTableCOP3_32[] = { 0 }; -static uint8_t DecoderTableMicroMips16[] = { +static const uint8_t DecoderTableMicroMips16[] = { /* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33 /* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... diff --git a/arch/Mips/MipsGenRegisterInfo.inc b/arch/Mips/MipsGenRegisterInfo.inc index 14319cd16f..4501a407fd 100644 --- a/arch/Mips/MipsGenRegisterInfo.inc +++ b/arch/Mips/MipsGenRegisterInfo.inc @@ -494,7 +494,7 @@ enum { #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC -static MCPhysReg MipsRegDiffLists[] = { +static const MCPhysReg MipsRegDiffLists[] = { /* 0 */ 0, 0, /* 2 */ 4, 1, 1, 1, 1, 0, /* 8 */ 364, 65286, 1, 1, 1, 0, @@ -587,14 +587,14 @@ static MCPhysReg MipsRegDiffLists[] = { /* 251 */ 65535, 0, }; -static uint16_t MipsSubRegIdxLists[] = { +static const uint16_t MipsSubRegIdxLists[] = { /* 0 */ 1, 0, /* 2 */ 3, 4, 5, 6, 7, 0, /* 8 */ 2, 9, 8, 0, /* 12 */ 9, 1, 8, 10, 11, 0, }; -static MCRegisterDesc MipsRegDesc[] = { // Descriptors +static const MCRegisterDesc MipsRegDesc[] = { // Descriptors { 6, 0, 0, 0, 0, 0 }, { 2007, 1, 82, 1, 4017, 0 }, { 2010, 1, 1, 1, 4017, 0 }, @@ -992,626 +992,626 @@ static MCRegisterDesc MipsRegDesc[] = { // Descriptors }; // OddSP Register Class... - static MCPhysReg OddSP[] = { + static const MCPhysReg OddSP[] = { Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, }; // OddSP Bit set. - static uint8_t OddSPBits[] = { + static const uint8_t OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, }; // CCR Register Class... - static MCPhysReg CCR[] = { + static const MCPhysReg CCR[] = { Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, }; // CCR Bit set. - static uint8_t CCRBits[] = { + static const uint8_t CCRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // COP2 Register Class... - static MCPhysReg COP2[] = { + static const MCPhysReg COP2[] = { Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, }; // COP2 Bit set. - static uint8_t COP2Bits[] = { + static const uint8_t COP2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01, }; // COP3 Register Class... - static MCPhysReg COP3[] = { + static const MCPhysReg COP3[] = { Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, }; // COP3 Bit set. - static uint8_t COP3Bits[] = { + static const uint8_t COP3Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f, }; // DSPR Register Class... - static MCPhysReg DSPR[] = { + static const MCPhysReg DSPR[] = { Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, }; // DSPR Bit set. - static uint8_t DSPRBits[] = { + static const uint8_t DSPRBits[] = { 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, }; // FGR32 Register Class... - static MCPhysReg FGR32[] = { + static const MCPhysReg FGR32[] = { Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, }; // FGR32 Bit set. - static uint8_t FGR32Bits[] = { + static const uint8_t FGR32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // FGRCC Register Class... - static MCPhysReg FGRCC[] = { + static const MCPhysReg FGRCC[] = { Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, }; // FGRCC Bit set. - static uint8_t FGRCCBits[] = { + static const uint8_t FGRCCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // FGRH32 Register Class... - static MCPhysReg FGRH32[] = { + static const MCPhysReg FGRH32[] = { Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31, }; // FGRH32 Bit set. - static uint8_t FGRH32Bits[] = { + static const uint8_t FGRH32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, }; // GPR32 Register Class... - static MCPhysReg GPR32[] = { + static const MCPhysReg GPR32[] = { Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, }; // GPR32 Bit set. - static uint8_t GPR32Bits[] = { + static const uint8_t GPR32Bits[] = { 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, }; // HWRegs Register Class... - static MCPhysReg HWRegs[] = { + static const MCPhysReg HWRegs[] = { Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, }; // HWRegs Bit set. - static uint8_t HWRegsBits[] = { + static const uint8_t HWRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // OddSP_with_sub_hi Register Class... - static MCPhysReg OddSP_with_sub_hi[] = { + static const MCPhysReg OddSP_with_sub_hi[] = { Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, }; // OddSP_with_sub_hi Bit set. - static uint8_t OddSP_with_sub_hiBits[] = { + static const uint8_t OddSP_with_sub_hiBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, }; // FGR32_and_OddSP Register Class... - static MCPhysReg FGR32_and_OddSP[] = { + static const MCPhysReg FGR32_and_OddSP[] = { Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, }; // FGR32_and_OddSP Bit set. - static uint8_t FGR32_and_OddSPBits[] = { + static const uint8_t FGR32_and_OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, }; // FGRH32_and_OddSP Register Class... - static MCPhysReg FGRH32_and_OddSP[] = { + static const MCPhysReg FGRH32_and_OddSP[] = { Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, }; // FGRH32_and_OddSP Bit set. - static uint8_t FGRH32_and_OddSPBits[] = { + static const uint8_t FGRH32_and_OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, }; // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... - static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { + static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, }; // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. - static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { + static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, }; // CPU16RegsPlusSP Register Class... - static MCPhysReg CPU16RegsPlusSP[] = { + static const MCPhysReg CPU16RegsPlusSP[] = { Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, }; // CPU16RegsPlusSP Bit set. - static uint8_t CPU16RegsPlusSPBits[] = { + static const uint8_t CPU16RegsPlusSPBits[] = { 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // CC Register Class... - static MCPhysReg CC[] = { + static const MCPhysReg CC[] = { Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7, }; // CC Bit set. - static uint8_t CCBits[] = { + static const uint8_t CCBits[] = { 0x00, 0x00, 0x00, 0x80, 0x7f, }; // CPU16Regs Register Class... - static MCPhysReg CPU16Regs[] = { + static const MCPhysReg CPU16Regs[] = { Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, }; // CPU16Regs Bit set. - static uint8_t CPU16RegsBits[] = { + static const uint8_t CPU16RegsBits[] = { 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // FCC Register Class... - static MCPhysReg FCC[] = { + static const MCPhysReg FCC[] = { Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, }; // FCC Bit set. - static uint8_t FCCBits[] = { + static const uint8_t FCCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, }; // GPRMM16 Register Class... - static MCPhysReg GPRMM16[] = { + static const MCPhysReg GPRMM16[] = { Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, }; // GPRMM16 Bit set. - static uint8_t GPRMM16Bits[] = { + static const uint8_t GPRMM16Bits[] = { 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // GPRMM16MoveP Register Class... - static MCPhysReg GPRMM16MoveP[] = { + static const MCPhysReg GPRMM16MoveP[] = { Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, }; // GPRMM16MoveP Bit set. - static uint8_t GPRMM16MovePBits[] = { + static const uint8_t GPRMM16MovePBits[] = { 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, }; // GPRMM16Zero Register Class... - static MCPhysReg GPRMM16Zero[] = { + static const MCPhysReg GPRMM16Zero[] = { Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, }; // GPRMM16Zero Bit set. - static uint8_t GPRMM16ZeroBits[] = { + static const uint8_t GPRMM16ZeroBits[] = { 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // MSACtrl Register Class... - static MCPhysReg MSACtrl[] = { + static const MCPhysReg MSACtrl[] = { Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, }; // MSACtrl Bit set. - static uint8_t MSACtrlBits[] = { + static const uint8_t MSACtrlBits[] = { 0x00, 0xfc, 0x03, }; // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... - static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { + static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, }; // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. - static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { + static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, }; // CPU16Regs_and_GPRMM16Zero Register Class... - static MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { + static const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, }; // CPU16Regs_and_GPRMM16Zero Bit set. - static uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { + static const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // CPU16Regs_and_GPRMM16MoveP Register Class... - static MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { + static const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { Mips_S1, Mips_V0, Mips_V1, Mips_S0, }; // CPU16Regs_and_GPRMM16MoveP Bit set. - static uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { + static const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // GPRMM16MoveP_and_GPRMM16Zero Register Class... - static MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { + static const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, }; // GPRMM16MoveP_and_GPRMM16Zero Bit set. - static uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { + static const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // HI32DSP Register Class... - static MCPhysReg HI32DSP[] = { + static const MCPhysReg HI32DSP[] = { Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, }; // HI32DSP Bit set. - static uint8_t HI32DSPBits[] = { + static const uint8_t HI32DSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, }; // LO32DSP Register Class... - static MCPhysReg LO32DSP[] = { + static const MCPhysReg LO32DSP[] = { Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, }; // LO32DSP Bit set. - static uint8_t LO32DSPBits[] = { + static const uint8_t LO32DSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, }; // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... - static MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { + static const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { Mips_S1, Mips_V0, Mips_V1, }; // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. - static uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { + static const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // CPURAReg Register Class... - static MCPhysReg CPURAReg[] = { + static const MCPhysReg CPURAReg[] = { Mips_RA, }; // CPURAReg Bit set. - static uint8_t CPURARegBits[] = { + static const uint8_t CPURARegBits[] = { 0x00, 0x00, 0x08, }; // CPUSPReg Register Class... - static MCPhysReg CPUSPReg[] = { + static const MCPhysReg CPUSPReg[] = { Mips_SP, }; // CPUSPReg Bit set. - static uint8_t CPUSPRegBits[] = { + static const uint8_t CPUSPRegBits[] = { 0x00, 0x00, 0x10, }; // DSPCC Register Class... - static MCPhysReg DSPCC[] = { + static const MCPhysReg DSPCC[] = { Mips_DSPCCond, }; // DSPCC Bit set. - static uint8_t DSPCCBits[] = { + static const uint8_t DSPCCBits[] = { 0x04, }; // HI32 Register Class... - static MCPhysReg HI32[] = { + static const MCPhysReg HI32[] = { Mips_HI0, }; // HI32 Bit set. - static uint8_t HI32Bits[] = { + static const uint8_t HI32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // LO32 Register Class... - static MCPhysReg LO32[] = { + static const MCPhysReg LO32[] = { Mips_LO0, }; // LO32 Bit set. - static uint8_t LO32Bits[] = { + static const uint8_t LO32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, }; // FGR64 Register Class... - static MCPhysReg FGR64[] = { + static const MCPhysReg FGR64[] = { Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, }; // FGR64 Bit set. - static uint8_t FGR64Bits[] = { + static const uint8_t FGR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // GPR64 Register Class... - static MCPhysReg GPR64[] = { + static const MCPhysReg GPR64[] = { Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, }; // GPR64 Bit set. - static uint8_t GPR64Bits[] = { + static const uint8_t GPR64Bits[] = { 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, }; // AFGR64 Register Class... - static MCPhysReg AFGR64[] = { + static const MCPhysReg AFGR64[] = { Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, }; // AFGR64 Bit set. - static uint8_t AFGR64Bits[] = { + static const uint8_t AFGR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, }; // FGR64_and_OddSP Register Class... - static MCPhysReg FGR64_and_OddSP[] = { + static const MCPhysReg FGR64_and_OddSP[] = { Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, }; // FGR64_and_OddSP Bit set. - static uint8_t FGR64_and_OddSPBits[] = { + static const uint8_t FGR64_and_OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, }; // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... - static MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { + static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, }; // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. - static uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { + static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // AFGR64_and_OddSP Register Class... - static MCPhysReg AFGR64_and_OddSP[] = { + static const MCPhysReg AFGR64_and_OddSP[] = { Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, }; // AFGR64_and_OddSP Bit set. - static uint8_t AFGR64_and_OddSPBits[] = { + static const uint8_t AFGR64_and_OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, }; // GPR64_with_sub_32_in_CPU16Regs Register Class... - static MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { + static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs Bit set. - static uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { + static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... - static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { + static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. - static uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { + static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16Zero Register Class... - static MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { + static const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16Zero Bit set. - static uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { + static const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... - static MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { + static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. - static uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { + static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // ACC64DSP Register Class... - static MCPhysReg ACC64DSP[] = { + static const MCPhysReg ACC64DSP[] = { Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, }; // ACC64DSP Bit set. - static uint8_t ACC64DSPBits[] = { + static const uint8_t ACC64DSPBits[] = { 0x00, 0x00, 0x00, 0x3c, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... - static MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { + static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. - static uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { + static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... - static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { + static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. - static uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { + static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... - static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { + static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { Mips_V0_64, Mips_V1_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. - static uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { + static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // OCTEON_MPL Register Class... - static MCPhysReg OCTEON_MPL[] = { + static const MCPhysReg OCTEON_MPL[] = { Mips_MPL0, Mips_MPL1, Mips_MPL2, }; // OCTEON_MPL Bit set. - static uint8_t OCTEON_MPLBits[] = { + static const uint8_t OCTEON_MPLBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, }; // OCTEON_P Register Class... - static MCPhysReg OCTEON_P[] = { + static const MCPhysReg OCTEON_P[] = { Mips_P0, Mips_P1, Mips_P2, }; // OCTEON_P Bit set. - static uint8_t OCTEON_PBits[] = { + static const uint8_t OCTEON_PBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, }; // ACC64 Register Class... - static MCPhysReg ACC64[] = { + static const MCPhysReg ACC64[] = { Mips_AC0, }; // ACC64 Bit set. - static uint8_t ACC64Bits[] = { + static const uint8_t ACC64Bits[] = { 0x00, 0x00, 0x00, 0x04, }; // GPR64_with_sub_32_in_CPURAReg Register Class... - static MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { + static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { Mips_RA_64, }; // GPR64_with_sub_32_in_CPURAReg Bit set. - static uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { + static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // GPR64_with_sub_32_in_CPUSPReg Register Class... - static MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { + static const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { Mips_SP_64, }; // GPR64_with_sub_32_in_CPUSPReg Bit set. - static uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { + static const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, }; // HI64 Register Class... - static MCPhysReg HI64[] = { + static const MCPhysReg HI64[] = { Mips_HI0_64, }; // HI64 Bit set. - static uint8_t HI64Bits[] = { + static const uint8_t HI64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, }; // LO64 Register Class... - static MCPhysReg LO64[] = { + static const MCPhysReg LO64[] = { Mips_LO0_64, }; // LO64 Bit set. - static uint8_t LO64Bits[] = { + static const uint8_t LO64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // MSA128B Register Class... - static MCPhysReg MSA128B[] = { + static const MCPhysReg MSA128B[] = { Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128B Bit set. - static uint8_t MSA128BBits[] = { + static const uint8_t MSA128BBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128D Register Class... - static MCPhysReg MSA128D[] = { + static const MCPhysReg MSA128D[] = { Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128D Bit set. - static uint8_t MSA128DBits[] = { + static const uint8_t MSA128DBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128H Register Class... - static MCPhysReg MSA128H[] = { + static const MCPhysReg MSA128H[] = { Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128H Bit set. - static uint8_t MSA128HBits[] = { + static const uint8_t MSA128HBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128W Register Class... - static MCPhysReg MSA128W[] = { + static const MCPhysReg MSA128W[] = { Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128W Bit set. - static uint8_t MSA128WBits[] = { + static const uint8_t MSA128WBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128B_with_sub_64_in_OddSP Register Class... - static MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { + static const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31, }; // MSA128B_with_sub_64_in_OddSP Bit set. - static uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { + static const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, }; // MSA128WEvens Register Class... - static MCPhysReg MSA128WEvens[] = { + static const MCPhysReg MSA128WEvens[] = { Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30, }; // MSA128WEvens Bit set. - static uint8_t MSA128WEvensBits[] = { + static const uint8_t MSA128WEvensBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, }; // ACC128 Register Class... - static MCPhysReg ACC128[] = { + static const MCPhysReg ACC128[] = { Mips_AC0_64, }; // ACC128 Bit set. - static uint8_t ACC128Bits[] = { + static const uint8_t ACC128Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, }; -static MCRegisterClass MipsMCRegisterClasses[] = { +static const MCRegisterClass MipsMCRegisterClasses[] = { { OddSP, OddSPBits, sizeof(OddSPBits) }, { CCR, CCRBits, sizeof(CCRBits) }, { COP2, COP2Bits, sizeof(COP2Bits) }, diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c index 9f5083602d..c8a159d80e 100644 --- a/arch/Mips/MipsMapping.c +++ b/arch/Mips/MipsMapping.c @@ -210,7 +210,7 @@ const char *Mips_reg_name(csh handle, unsigned int reg) #endif } -static insn_map insns[] = { +static const insn_map insns[] = { // dummy item { 0, 0, diff --git a/arch/PowerPC/PPCGenInstrInfo.inc b/arch/PowerPC/PPCGenInstrInfo.inc index 90e0157b21..47fdd93ab8 100644 --- a/arch/PowerPC/PPCGenInstrInfo.inc +++ b/arch/PowerPC/PPCGenInstrInfo.inc @@ -2178,313 +2178,313 @@ enum { #define nullptr 0 -static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static MCOperandInfo OperandInfo10[] = { { 0, 0|(1< #include "SystemZMCTargetDesc.h" #define GET_REGINFO_ENUM @@ -113,30 +114,80 @@ const unsigned SystemZMC_CR64Regs[16] = { SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15 }; +/* All register classes that have 0-15. */ +#define DEF_REG16(N) \ + [SystemZ_R ## N ## L] = N, \ + [SystemZ_R ## N ## H] = N, \ + [SystemZ_R ## N ## D] = N, \ + [SystemZ_F ## N ## S] = N, \ + [SystemZ_F ## N ## D] = N, \ + [SystemZ_V ## N] = N, \ + [SystemZ_A ## N] = N, \ + [SystemZ_C ## N] = N + +/* All register classes that (also) have 16-31. */ +#define DEF_REG32(N) \ + [SystemZ_F ## N ## S] = N, \ + [SystemZ_F ## N ## D] = N, \ + [SystemZ_V ## N] = N + +static const uint8_t Map[SystemZ_NUM_TARGET_REGS] = { + DEF_REG16(0), + DEF_REG16(1), + DEF_REG16(2), + DEF_REG16(3), + DEF_REG16(4), + DEF_REG16(5), + DEF_REG16(6), + DEF_REG16(8), + DEF_REG16(9), + DEF_REG16(10), + DEF_REG16(11), + DEF_REG16(12), + DEF_REG16(13), + DEF_REG16(14), + DEF_REG16(15), + + DEF_REG32(16), + DEF_REG32(17), + DEF_REG32(18), + DEF_REG32(19), + DEF_REG32(20), + DEF_REG32(21), + DEF_REG32(22), + DEF_REG32(23), + DEF_REG32(24), + DEF_REG32(25), + DEF_REG32(26), + DEF_REG32(27), + DEF_REG32(28), + DEF_REG32(29), + DEF_REG32(30), + DEF_REG32(31), + + /* The float Q registers are non-sequential. */ + [SystemZ_F0Q] = 0, + [SystemZ_F1Q] = 1, + [SystemZ_F4Q] = 4, + [SystemZ_F5Q] = 5, + [SystemZ_F8Q] = 8, + [SystemZ_F9Q] = 9, + [SystemZ_F12Q] = 12, + [SystemZ_F13Q] = 13, + + /* The integer Q registers are all even. */ + [SystemZ_R0Q] = 0, + [SystemZ_R2Q] = 2, + [SystemZ_R4Q] = 4, + [SystemZ_R6Q] = 6, + [SystemZ_R8Q] = 8, + [SystemZ_R10Q] = 10, + [SystemZ_R12Q] = 12, + [SystemZ_R14Q] = 14, +}; + unsigned SystemZMC_getFirstReg(unsigned Reg) { - static unsigned Map[SystemZ_NUM_TARGET_REGS]; - static int Initialized = 0; - unsigned I; - - if (!Initialized) { - Initialized = 1; - for (I = 0; I < 16; ++I) { - Map[SystemZMC_GR32Regs[I]] = I; - Map[SystemZMC_GRH32Regs[I]] = I; - Map[SystemZMC_GR64Regs[I]] = I; - Map[SystemZMC_GR128Regs[I]] = I; - Map[SystemZMC_FP32Regs[I]] = I; - Map[SystemZMC_FP64Regs[I]] = I; - Map[SystemZMC_FP128Regs[I]] = I; - Map[SystemZMC_VR32Regs[I]] = I; - Map[SystemZMC_VR64Regs[I]] = I; - Map[SystemZMC_VR128Regs[I]] = I; - Map[SystemZMC_AR32Regs[I]] = I; - Map[SystemZMC_CR64Regs[I]] = I; - } - } - // assert(Reg < SystemZ_NUM_TARGET_REGS); return Map[Reg]; } diff --git a/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc b/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc index 70dd72a747..a5242dae9d 100644 --- a/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc +++ b/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc @@ -295,7 +295,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { 0U }; - static char AsmStrs[] = { + static const char AsmStrs[] = { /* 0 */ 'n', 'o', 'p', 9, 9, 0, /* 6 */ 's', 'u', 'b', '2', 9, 0, /* 12 */ 's', 'a', 'd', 'd', '2', 9, 0, @@ -576,9 +576,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. -static char *getRegisterName(unsigned RegNo) { +static const char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET - static char AsmStrs[] = { + static const char AsmStrs[] = { /* 0 */ 'a', '1', '0', 0, /* 4 */ 'b', '1', '0', 0, /* 8 */ 'a', '2', '0', 0, diff --git a/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc b/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc index edee71a43a..415e6b76be 100644 --- a/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc +++ b/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc @@ -21,7 +21,7 @@ static InsnType fname(InsnType insn, unsigned startBit, \ return (insn & fieldMask) >> startBit; \ } -static uint8_t DecoderTable32[] = { +static const uint8_t DecoderTable32[] = { /* 0 */ MCD_OPC_ExtractField, 2, 5, // Inst{6-2} ... /* 3 */ MCD_OPC_FilterValue, 0, 199, 0, // Skip to: 206 /* 7 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... @@ -1268,12 +1268,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ -static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \ +static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ InsnType insn, uint64_t Address, \ MCRegisterInfo *MRI, \ int feature) { \ uint64_t Bits = getFeatureBits(feature); \ - uint8_t *Ptr = DecodeTable; \ + const uint8_t *Ptr = DecodeTable; \ uint32_t CurFieldValue = 0, ExpectedValue; \ DecodeStatus S = MCDisassembler_Success; \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ diff --git a/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc b/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc index f02f288b2a..c095762f39 100644 --- a/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc +++ b/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc @@ -126,15 +126,15 @@ enum { #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC -static MCPhysReg TMS320C64xRegDiffLists[] = { +static const MCPhysReg TMS320C64xRegDiffLists[] = { /* 0 */ 65535, 0, }; -static uint16_t TMS320C64xSubRegIdxLists[] = { +static const uint16_t TMS320C64xSubRegIdxLists[] = { /* 0 */ 0, }; -static MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors +static const MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors { 3, 0, 0, 0, 0 }, { 310, 1, 1, 0, 1 }, { 319, 1, 1, 0, 1 }, @@ -228,46 +228,46 @@ static MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors }; // GPRegs Register Class... -static MCPhysReg GPRegs[] = { +static const MCPhysReg GPRegs[] = { TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31, }; // GPRegs Bit set. -static uint8_t GPRegsBits[] = { +static const uint8_t GPRegsBits[] = { 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, }; // AFRegs Register Class... -static MCPhysReg AFRegs[] = { +static const MCPhysReg AFRegs[] = { TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, }; // AFRegs Bit set. -static uint8_t AFRegsBits[] = { +static const uint8_t AFRegsBits[] = { 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // BFRegs Register Class... -static MCPhysReg BFRegs[] = { +static const MCPhysReg BFRegs[] = { TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31, }; // BFRegs Bit set. -static uint8_t BFRegsBits[] = { +static const uint8_t BFRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // ControlRegs Register Class... -static MCPhysReg ControlRegs[] = { +static const MCPhysReg ControlRegs[] = { TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_DIER, TMS320C64x_DNUM, TMS320C64x_ECR, TMS320C64x_GFPGFR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, TMS320C64x_ICR, TMS320C64x_IER, TMS320C64x_IERR, TMS320C64x_ILC, TMS320C64x_IRP, TMS320C64x_ISR, TMS320C64x_ISTP, TMS320C64x_ITSR, TMS320C64x_NRP, TMS320C64x_NTSR, TMS320C64x_PCE1, TMS320C64x_REP, TMS320C64x_RILC, TMS320C64x_SSR, TMS320C64x_TSCH, TMS320C64x_TSCL, TMS320C64x_TSR, }; // ControlRegs Bit set. -static uint8_t ControlRegsBits[] = { +static const uint8_t ControlRegsBits[] = { 0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, }; -static MCRegisterClass TMS320C64xMCRegisterClasses[] = { +static const MCRegisterClass TMS320C64xMCRegisterClasses[] = { { GPRegs, GPRegsBits, TMS320C64x_GPRegsRegClassID }, { AFRegs, AFRegsBits, TMS320C64x_AFRegsRegClassID }, { BFRegs, BFRegsBits, TMS320C64x_BFRegsRegClassID }, diff --git a/arch/TMS320C64x/TMS320C64xInstPrinter.c b/arch/TMS320C64x/TMS320C64xInstPrinter.c index 49556c7833..46bdbe7c43 100644 --- a/arch/TMS320C64x/TMS320C64xInstPrinter.c +++ b/arch/TMS320C64x/TMS320C64xInstPrinter.c @@ -27,7 +27,7 @@ #include "capstone/tms320c64x.h" -static char *getRegisterName(unsigned RegNo); +static const char *getRegisterName(unsigned RegNo); static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O); static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O); diff --git a/arch/TMS320C64x/TMS320C64xMapping.c b/arch/TMS320C64x/TMS320C64xMapping.c index eb30614694..feb3aeab8a 100644 --- a/arch/TMS320C64x/TMS320C64xMapping.c +++ b/arch/TMS320C64x/TMS320C64xMapping.c @@ -13,7 +13,7 @@ #define GET_INSTRINFO_ENUM #include "TMS320C64xGenInstrInfo.inc" -static name_map reg_name_maps[] = { +static const name_map reg_name_maps[] = { { TMS320C64X_REG_INVALID, NULL }, { TMS320C64X_REG_AMR, "amr" }, @@ -131,7 +131,7 @@ tms320c64x_reg TMS320C64x_reg_id(char *name) return 0; } -static insn_map insns[] = { +static const insn_map insns[] = { { 0, 0, #ifndef CAPSTONE_DIET @@ -1719,7 +1719,7 @@ void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) #ifndef CAPSTONE_DIET //grep TMS320C64X_INS include/capstone/tms320c64x.h | awk '{print "{"$1 "\""tolower(substr($1, 16, length($1)-16))"\"""},"}' -static name_map insn_name_maps[] = { +static const name_map insn_name_maps[] = { {TMS320C64X_INS_INVALID, NULL}, {TMS320C64X_INS_ABS, "abs"}, {TMS320C64X_INS_ABS2, "abs2"}, @@ -1882,7 +1882,7 @@ const char *TMS320C64x_insn_name(csh handle, unsigned int id) } #ifndef CAPSTONE_DIET -static name_map group_name_maps[] = { +static const name_map group_name_maps[] = { { TMS320C64X_GRP_INVALID, NULL }, { TMS320C64X_GRP_FUNIT_D, "funit_d" }, { TMS320C64X_GRP_FUNIT_L, "funit_l" }, diff --git a/arch/WASM/WASMDisassembler.c b/arch/WASM/WASMDisassembler.c index 956f1a2b63..a05ee0c757 100644 --- a/arch/WASM/WASMDisassembler.c +++ b/arch/WASM/WASMDisassembler.c @@ -9,7 +9,7 @@ #include "WASMMapping.h" #include "../../cs_priv.h" -static short opcodes[256] = { +static const short opcodes[256] = { WASM_INS_UNREACHABLE, WASM_INS_NOP, WASM_INS_BLOCK, diff --git a/arch/WASM/WASMMapping.c b/arch/WASM/WASMMapping.c index 036634a593..88a6f513ba 100644 --- a/arch/WASM/WASMMapping.c +++ b/arch/WASM/WASMMapping.c @@ -17,7 +17,7 @@ void WASM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) } #ifndef CAPSTONE_DIET -static name_map insn_name_maps[256] = { +static const name_map insn_name_maps[256] = { { WASM_INS_UNREACHABLE, "unreachable" }, { WASM_INS_NOP, "nop" }, { WASM_INS_BLOCK, "block" }, @@ -290,7 +290,7 @@ const char *WASM_insn_name(csh handle, unsigned int id) } #ifndef CAPSTONE_DIET -static name_map group_name_maps[] = { +static const name_map group_name_maps[] = { // generic groups { WASM_GRP_INVALID, NULL }, // special groups @@ -303,7 +303,7 @@ static name_map group_name_maps[] = { #endif #ifndef CAPSTONE_DIET -static name_map kind_name_maps[] = { +static const name_map kind_name_maps[] = { { WASM_OP_INVALID, "Invalid" }, { WASM_OP_NONE, "None" }, { WASM_OP_INT7, "uint7" }, diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c index 8544a44f28..216efb2566 100644 --- a/arch/X86/X86ATTInstPrinter.c +++ b/arch/X86/X86ATTInstPrinter.c @@ -284,7 +284,7 @@ static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags) { uint8_t count, i; - uint8_t *arr = X86_get_op_access(h, id, eflags); + const uint8_t *arr = X86_get_op_access(h, id, eflags); if (!arr) { access[0] = 0; diff --git a/arch/X86/X86DisassemblerDecoder.c b/arch/X86/X86DisassemblerDecoder.c index 4c10358444..891afd99a1 100644 --- a/arch/X86/X86DisassemblerDecoder.c +++ b/arch/X86/X86DisassemblerDecoder.c @@ -160,7 +160,7 @@ static InstrUID decode(OpcodeType type, { const struct ModRMDecision *dec = NULL; unsigned int index; - static struct OpcodeDecision emptyDecision = { 0 }; + static const struct OpcodeDecision emptyDecision = { 0 }; switch (type) { default: break; // never reach diff --git a/arch/X86/X86GenRegisterInfo.inc b/arch/X86/X86GenRegisterInfo.inc index 0018adf42c..d2598b196d 100644 --- a/arch/X86/X86GenRegisterInfo.inc +++ b/arch/X86/X86GenRegisterInfo.inc @@ -487,7 +487,7 @@ static const uint16_t X86SubRegIdxLists[] = { /* 22 */ 8, 7, 0, }; -static MCRegisterDesc X86RegDesc[] = { +static const MCRegisterDesc X86RegDesc[] = { { 5, 0, 0, 0, 0, 0 }, { 873, 2, 184, 2, 4641, 0 }, { 1014, 2, 180, 2, 4641, 0 }, @@ -1457,7 +1457,7 @@ static MCRegisterDesc X86RegDesc[] = { }; -static MCRegisterClass X86MCRegisterClasses[] = { +static const MCRegisterClass X86MCRegisterClasses[] = { { GR8, GR8Bits, sizeof(GR8Bits) }, { GRH8, GRH8Bits, sizeof(GRH8Bits) }, { GR8_NOREX, GR8_NOREXBits, sizeof(GR8_NOREXBits) }, diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c index b028d7e9bb..5361172d29 100644 --- a/arch/X86/X86IntelInstPrinter.c +++ b/arch/X86/X86IntelInstPrinter.c @@ -428,7 +428,7 @@ static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64 { #ifndef CAPSTONE_DIET uint8_t i; - uint8_t *arr = X86_get_op_access(h, id, eflags); + const uint8_t *arr = X86_get_op_access(h, id, eflags); if (!arr) { access[0] = 0; diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c index 455c0100c4..ae005ba194 100644 --- a/arch/X86/X86Mapping.c +++ b/arch/X86/X86Mapping.c @@ -856,7 +856,7 @@ const char *X86_reg_name(csh handle, unsigned int reg) } #ifndef CAPSTONE_DIET -static const char *insn_name_maps[] = { +static const char * const insn_name_maps[] = { NULL, // X86_INS_INVALID #ifndef CAPSTONE_X86_REDUCE #include "X86MappingInsnName.inc" @@ -1216,7 +1216,7 @@ struct insn_reg2 { enum cs_ac_type access1, access2; }; -static struct insn_reg insn_regs_att[] = { +static const struct insn_reg insn_regs_att[] = { { X86_INSB, X86_REG_DX, CS_AC_READ }, { X86_INSL, X86_REG_DX, CS_AC_READ }, { X86_INSW, X86_REG_DX, CS_AC_READ }, @@ -1309,7 +1309,7 @@ static struct insn_reg insn_regs_att[] = { { X86_XCHG64ar, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, }; -static struct insn_reg insn_regs_att_extra[] = { +static const struct insn_reg insn_regs_att_extra[] = { // dummy entry, to avoid empty array { 0, 0 }, #ifndef CAPSTONE_X86_REDUCE @@ -1330,7 +1330,7 @@ static struct insn_reg insn_regs_att_extra[] = { #endif }; -static struct insn_reg insn_regs_intel[] = { +static const struct insn_reg insn_regs_intel[] = { { X86_ADC16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_ADC32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_ADC64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, @@ -1420,7 +1420,7 @@ static struct insn_reg insn_regs_intel[] = { { X86_XOR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, }; -static struct insn_reg insn_regs_intel_extra[] = { +static const struct insn_reg insn_regs_intel_extra[] = { // dummy entry, to avoid empty array { 0, 0, 0 }, #ifndef CAPSTONE_X86_REDUCE @@ -1446,7 +1446,7 @@ static struct insn_reg insn_regs_intel_extra[] = { #endif }; -static struct insn_reg2 insn_regs_intel2[] = { +static const struct insn_reg2 insn_regs_intel2[] = { { X86_IN16rr, X86_REG_AX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, { X86_IN32rr, X86_REG_EAX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, { X86_IN8rr, X86_REG_AL, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, @@ -1457,7 +1457,7 @@ static struct insn_reg2 insn_regs_intel2[] = { { X86_OUT8rr, X86_REG_DX, X86_REG_AL, CS_AC_READ, CS_AC_READ }, }; -static int binary_search1(struct insn_reg *insns, unsigned int max, unsigned int id) +static int binary_search1(const struct insn_reg *insns, unsigned int max, unsigned int id) { unsigned int first, last, mid; @@ -1486,7 +1486,7 @@ static int binary_search1(struct insn_reg *insns, unsigned int max, unsigned int return -1; } -static int binary_search2(struct insn_reg2 *insns, unsigned int max, unsigned int id) +static int binary_search2(const struct insn_reg2 *insns, unsigned int max, unsigned int id) { unsigned int first, last, mid; @@ -2042,7 +2042,7 @@ typedef struct insn_op { uint8_t access[6]; } insn_op; -static insn_op insn_ops[] = { +static const insn_op insn_ops[] = { #ifdef CAPSTONE_X86_REDUCE #include "X86MappingInsnOp_reduce.inc" #else @@ -2051,7 +2051,7 @@ static insn_op insn_ops[] = { }; // given internal insn id, return operand access info -uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags) +const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags) { unsigned int i = find_insn(id); if (i != -1) { @@ -2117,7 +2117,7 @@ void X86_reg_access(const cs_insn *insn, // map immediate size to instruction id // this array is sorted for binary searching -static struct size_id { +static const struct size_id { uint8_t enc_size; uint8_t size; uint16_t id; @@ -2165,7 +2165,7 @@ uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size) #include "X86GenRegisterInfo.inc" // map internal register id to public register id -static struct register_map { +static const struct register_map { unsigned short id; unsigned short pub_id; } reg_map [] = { diff --git a/arch/X86/X86Mapping.h b/arch/X86/X86Mapping.h index dbdb645b19..89bbfcd8c4 100644 --- a/arch/X86/X86Mapping.h +++ b/arch/X86/X86Mapping.h @@ -78,7 +78,7 @@ void op_addAvxSae(MCInst *MI); void op_addAvxRoundingMode(MCInst *MI, int v); // given internal insn id, return operand access info -uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags); +const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags); void X86_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, diff --git a/arch/XCore/XCoreGenRegisterInfo.inc b/arch/XCore/XCoreGenRegisterInfo.inc index 52c8af068e..0349badb56 100644 --- a/arch/XCore/XCoreGenRegisterInfo.inc +++ b/arch/XCore/XCoreGenRegisterInfo.inc @@ -62,7 +62,7 @@ static const uint16_t XCoreSubRegIdxLists[] = { /* 0 */ 0, }; -static MCRegisterDesc XCoreRegDesc[] = { // Descriptors +static const MCRegisterDesc XCoreRegDesc[] = { // Descriptors { 3, 0, 0, 0, 0, 0 }, { 38, 1, 1, 0, 1, 0 }, { 41, 1, 1, 0, 1, 0 }, @@ -102,7 +102,7 @@ static MCRegisterDesc XCoreRegDesc[] = { // Descriptors 0xe0, 0xff, 0x01, }; -static MCRegisterClass XCoreMCRegisterClasses[] = { +static const MCRegisterClass XCoreMCRegisterClasses[] = { { RRegs, RRegsBits, sizeof(RRegsBits) }, { GRRegs, GRRegsBits, sizeof(GRRegsBits) }, }; diff --git a/contrib/m68k_instruction_tbl_gen/M68KInstructionTblGen.c b/contrib/m68k_instruction_tbl_gen/M68KInstructionTblGen.c index 75f1b22081..54de4955e9 100644 --- a/contrib/m68k_instruction_tbl_gen/M68KInstructionTblGen.c +++ b/contrib/m68k_instruction_tbl_gen/M68KInstructionTblGen.c @@ -1,6 +1,7 @@ #include #include #include +#include /* This code is used to build the static lookup table used inside the M68KDisassembler.c code * To run this use the Makefile in the same directory @@ -422,7 +423,7 @@ static void build_opcode_table(void) qsort((void *)g_opcode_info, opcode_info_length, sizeof(g_opcode_info[0]), compare_nof_true_bits); printf("/* This table is auto-generated. DO NOT MANUALLY EDIT! Look in M68KInstructionTblGen.c for more info */\n"); - printf("static instruction_struct g_instruction_table[] = {\n"); + printf("static const instruction_struct g_instruction_table[] = {\n"); for(i=0;i<0x10000;i++) { const char *name = "d68000_invalid"; diff --git a/cs.c b/cs.c index 6c540bdfb7..e42764a604 100644 --- a/cs.c +++ b/cs.c @@ -69,7 +69,7 @@ #include "arch/MOS65XX/MOS65XXModule.h" #include "arch/BPF/BPFModule.h" -static struct { +static const struct { // constructor initialization cs_err (*arch_init)(cs_struct *); // support cs_option() @@ -234,7 +234,7 @@ static struct { }; // bitmask of enabled architectures -static uint32_t all_arch = 0 +static const uint32_t all_arch = 0 #ifdef CAPSTONE_HAS_ARM | (1 << CS_ARCH_ARM) #endif diff --git a/suite/synctools/instrinfo-arch.py b/suite/synctools/instrinfo-arch.py index aa4d6924ac..fed572eaa7 100755 --- a/suite/synctools/instrinfo-arch.py +++ b/suite/synctools/instrinfo-arch.py @@ -134,8 +134,7 @@ def get_first_insn(filename): line = line.rstrip() if 'static const MCOperandInfo ' in line: - line2 = line.replace('static const MCOperandInfo ', 'static MCOperandInfo ') - line2 = line2.replace('::', '_') + line2 = line.replace('::', '_') print(line2) elif 'Insts[] = {' in line: diff --git a/suite/synctools/registerinfo.py b/suite/synctools/registerinfo.py index e9d356c1b7..27e05d287a 100755 --- a/suite/synctools/registerinfo.py +++ b/suite/synctools/registerinfo.py @@ -215,7 +215,7 @@ if arch + 'RegDesc' in line: finding_struct = False - print("static MCRegisterDesc " + arch + "RegDesc[] = {") + print("static const MCRegisterDesc " + arch + "RegDesc[] = {") continue if finding_struct: @@ -266,11 +266,7 @@ if 'MCRegisterClass ' + arch + 'MCRegisterClasses[] = {' in line: finding_struct = False - if arch.upper() == 'ARM': - print("static MCRegisterClass " + arch + "MCRegisterClasses[] = {") - else: - print("static MCRegisterClass " + arch + "MCRegisterClasses[] = {") - #print("static MCRegisterClass2 " + arch + "MCRegisterClasses[] = {") + print("static const MCRegisterClass " + arch + "MCRegisterClasses[] = {") continue if finding_struct: @@ -285,10 +281,6 @@ # { GR8, GR8Bits, 130, 20, sizeof(GR8Bits), X86_GR8RegClassID, 1, 1, 1, 1 }, tmp = line.split(',') - if arch.upper() == 'ARM': - print(" %s, %s, %s }," %(tmp[0].strip(), tmp[1].strip(), tmp[4].strip())) - else: # AArch64 - print(" %s, %s, %s }," %(tmp[0].strip(), tmp[1].strip(), tmp[4].strip())) - #print(" %s, %s, %s, %s }," %(tmp[0].strip(), tmp[1].strip(), tmp[3].strip(), tmp[4].strip())) + print(" %s, %s, %s }," %(tmp[0].strip(), tmp[1].strip(), tmp[4].strip())) print("#endif // GET_REGINFO_MC_DESC") diff --git a/suite/synctools/systemregister.py b/suite/synctools/systemregister.py index 4146d81041..ed3e94352f 100755 --- a/suite/synctools/systemregister.py +++ b/suite/synctools/systemregister.py @@ -62,7 +62,7 @@ if 'MClassSysRegsList[]' in line: count += 1 - print('static MClassSysReg MClassSysRegsList[] = {') + print('static const MClassSysReg MClassSysRegsList[] = {') continue if count == 1: @@ -89,7 +89,7 @@ if 'BankedRegsList[]' in line: count += 1 - print('static BankedReg BankedRegsList[] = {') + print('static const BankedReg BankedRegsList[] = {') continue if count == 1: @@ -115,7 +115,7 @@ if 'lookupMClassSysRegByM2M3Encoding8' in line and '{' in line: count += 1 - print('MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)\n{') + print('const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)\n{') print(' unsigned int i;') continue @@ -151,7 +151,7 @@ if 'lookupMClassSysRegByM1Encoding12' in line and '{' in line: count += 1 - print('MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)\n{') + print('const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)\n{') print(' unsigned int i;') continue @@ -186,7 +186,7 @@ if 'lookupBankedRegByEncoding' in line and '{' in line: count += 1 - print('BankedReg *lookupBankedRegByEncoding(uint8_t encoding)\n{') + print('const BankedReg *lookupBankedRegByEncoding(uint8_t encoding)\n{') print(' unsigned int i;') continue