From 41c3f2f8258b7935da60e33b7229cd7832981606 Mon Sep 17 00:00:00 2001 From: Tom Kelly Date: Thu, 26 Sep 2019 08:53:37 +0100 Subject: [PATCH] Fix for x86_op record for ocaml bindings --- bindings/ocaml/ocaml.c | 18 ++++++++++-------- bindings/ocaml/test_x86.ml | 6 +++--- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/bindings/ocaml/ocaml.c b/bindings/ocaml/ocaml.c index ac95ad26aa..74cc731421 100644 --- a/bindings/ocaml/ocaml.c +++ b/bindings/ocaml/ocaml.c @@ -369,15 +369,15 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t for (i = 0; i < lcount; i++) { switch(insn[j-1].detail->x86.operands[i].type) { case X86_OP_REG: - tmp = caml_alloc(5, 1); + tmp = caml_alloc(1, 1); Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].reg)); break; case X86_OP_IMM: - tmp = caml_alloc(5, 2); + tmp = caml_alloc(1, 2); Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].imm)); break; case X86_OP_MEM: - tmp = caml_alloc(5, 3); + tmp = caml_alloc(1, 3); tmp2 = caml_alloc(5, 0); Store_field(tmp2, 0, Val_int(insn[j-1].detail->x86.operands[i].mem.segment)); Store_field(tmp2, 1, Val_int(insn[j-1].detail->x86.operands[i].mem.base)); @@ -388,14 +388,16 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t Store_field(tmp, 0, tmp2); break; default: + tmp = caml_alloc(1, 0); // X86_OP_INVALID break; } - Store_field(tmp, 1, Val_int(insn[j-1].detail->x86.operands[i].size)); - Store_field(tmp, 2, Val_int(insn[j-1].detail->x86.operands[i].access)); - Store_field(tmp, 3, Val_int(insn[j-1].detail->x86.operands[i].avx_bcast)); - Store_field(tmp, 4, Val_int(insn[j-1].detail->x86.operands[i].avx_zero_opmask)); - tmp2 = caml_alloc(1, 0); + + tmp2 = caml_alloc(5, 0); Store_field(tmp2, 0, tmp); + Store_field(tmp2, 1, Val_int(insn[j-1].detail->x86.operands[i].size)); + Store_field(tmp2, 2, Val_int(insn[j-1].detail->x86.operands[i].access)); + Store_field(tmp2, 3, Val_int(insn[j-1].detail->x86.operands[i].avx_bcast)); + Store_field(tmp2, 4, Val_int(insn[j-1].detail->x86.operands[i].avx_zero_opmask)); Store_field(array, i, tmp2); } } else // empty array diff --git a/bindings/ocaml/test_x86.ml b/bindings/ocaml/test_x86.ml index ce343e49ee..d35bf0f01b 100644 --- a/bindings/ocaml/test_x86.ml +++ b/bindings/ocaml/test_x86.ml @@ -30,9 +30,9 @@ let all_tests = [ let print_op handle i op = ( match op.value with | X86_OP_INVALID _ -> (); (* this would never happens *) - | X86_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); - | X86_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; - | X86_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; + | X86_OP_REG reg -> printf "\t\top[%d]: REG = %s [sz=%d]\n" i (cs_reg_name handle reg) op.size; + | X86_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x [sz=%d]\n" i imm op.size; + | X86_OP_MEM mem -> ( printf "\t\top[%d]: MEM [sz=%d]\n" i op.size; if mem.base != 0 then printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); if mem.index != 0 then