diff --git a/CMakeLists.txt b/CMakeLists.txt index 870fe0dd65..dd4f170e37 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -88,6 +88,7 @@ set(SOURCES_ENGINE cs.c MCInst.c MCInstrDesc.c + MCInstPrinter.c MCRegisterInfo.c SStream.c utils.c @@ -100,6 +101,7 @@ set(HEADERS_ENGINE MCFixedLenDisassembler.h MCInst.h MCInstrDesc.h + MCInstPrinter.h MCRegisterInfo.h SStream.h utils.h @@ -201,20 +203,13 @@ if (CAPSTONE_MIPS_SUPPORT) arch/Mips/MipsDisassembler.h arch/Mips/MipsGenAsmWriter.inc arch/Mips/MipsGenDisassemblerTables.inc - arch/Mips/MipsGenInstrInfo.inc - arch/Mips/MipsGenRegisterInfo.inc - arch/Mips/MipsGenSubtargetInfo.inc arch/Mips/MipsInstPrinter.h arch/Mips/MipsMapping.h - arch/Mips/MipsMappingInsn.inc ) set(HEADERS_MIPS arch/Mips/MipsDisassembler.h arch/Mips/MipsGenAsmWriter.inc arch/Mips/MipsGenDisassemblerTables.inc - arch/Mips/MipsGenInstrInfo.inc - arch/Mips/MipsGenRegisterInfo.inc - arch/Mips/MipsGenSubtargetInfo.inc arch/Mips/MipsInstPrinter.h arch/Mips/MipsMapping.h ) diff --git a/MCInstPrinter.c b/MCInstPrinter.c new file mode 100644 index 0000000000..b1d61c9ffd --- /dev/null +++ b/MCInstPrinter.c @@ -0,0 +1,114 @@ +// +// Created by Phosphorus15 on 2021/5/14. +// +#include "MCInstPrinter.h" +#include "MCInst.h" + +static bool MCInstPrinter_matchAliasCondition( + const MCInst *MI, unsigned *OpIdx, const PatternsForOpcode *OpToPatterns, + const AliasPattern *Patterns, const AliasPatternCond *Conds, + const AliasPatternCond *Cond, bool *OrPredicateResult) { + // FIXME so here's on problem we ought to detect feature bits here + if (Cond->Kind == AliasPatternCond_K_Feature || + Cond->Kind == AliasPatternCond_K_NegFeature) + return true; // STI->getFeatureBits().test(C.Value); + // For feature tests where just one feature is required in a list, set the + // predicate result bit to whether the expression will return true, and only + // return the real result at the end of list marker. + if (Cond->Kind == AliasPatternCond_K_OrFeature) { + // *OrPredicateResult |= STI->getFeatureBits().test(C.Value); + return true; + } + if (Cond->Kind == AliasPatternCond_K_OrNegFeature) { + // *OrPredicateResult |= !(STI->getFeatureBits().test(C.Value)); + return true; + } + if (Cond->Kind == AliasPatternCond_K_EndOrFeatures) { + bool Res = *OrPredicateResult; + *OrPredicateResult = false; + return Res; + } + + MCOperand *Opnd = MCInst_getOperand((MCInst *)MI, *OpIdx); + *OpIdx = *OpIdx + 1; + switch (Cond->Kind) { + case AliasPatternCond_K_Imm: + // Operand must be a specific immediate. + return MCOperand_isImm(Opnd) && MCOperand_getImm(Opnd) == Cond->Value; + case AliasPatternCond_K_Reg: + // Operand must be a specific register. + return MCOperand_isReg(Opnd) && MCOperand_getReg(Opnd) == Cond->Value; + case AliasPatternCond_K_TiedReg: + // Operand must match the register of another operand. + return MCOperand_isReg(Opnd) && + MCOperand_getReg(Opnd) == + MCOperand_getReg(MCInst_getOperand((MCInst *)MI, Cond->Value)); + case AliasPatternCond_K_RegClass: + // Operand must be a register in this class. Value is a register class id. + return MCOperand_isReg(Opnd) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, Cond->Value), + MCOperand_getReg(Opnd)); + case AliasPatternCond_K_Custom: + // Operand must match some custom criteria. + // TODO might affect something return M.ValidateMCOperand(Opnd, + // *STI, C.Value); + return false; + case AliasPatternCond_K_Ignore: + // Operand can be anything. + return true; + case AliasPatternCond_K_Feature: + case AliasPatternCond_K_NegFeature: + case AliasPatternCond_K_OrFeature: + case AliasPatternCond_K_OrNegFeature: + case AliasPatternCond_K_EndOrFeatures: + default: + return false; + // TODO: Impossible to reach + // llvm_unreachable("handled earlier"); + } +} + +const char *MCInstPrinter_matchAliasPatterns( + const MCInst *MI, const PatternsForOpcode *OpToPatterns, + const AliasPattern *Patterns, const AliasPatternCond *Conds, + const char *AsmStrings[], unsigned len) { + + // Binary search by opcode. Return false if there are no aliases for this + // opcode. + PatternsForOpcode *It = + Binary_Search(OpToPatterns, MCInst_getOpcode(MI), len); + if (It == NULL || It->Opcode != MCInst_getOpcode(MI)) + return NULL; + + // Try all patterns for this opcode. + uint32_t AsmStrOffset = ~0U; + + for (unsigned i = It->PatternStart; i < It->PatternStart + It->NumPatterns; + i++) { + const AliasPattern Pattern = Patterns[i]; + if (MCInst_getNumOperands(MI) != Pattern.NumOperands) + return NULL; + unsigned OpIdx = 0; + bool OrPredicateResult = false; + bool fallThrough = true; + for (unsigned j = Pattern.AliasCondStart; + j < Pattern.AliasCondStart + Pattern.NumConds; j++) { + fallThrough &= MCInstPrinter_matchAliasCondition( + MI, &OpIdx, OpToPatterns, Patterns, Conds, &Conds[j], + &OrPredicateResult); + if (!fallThrough) + break; + } + if (fallThrough) { + AsmStrOffset = Pattern.AsmStrOffset; + break; + } + } + + // If no alias matched, don't print an alias. + if (AsmStrOffset == ~0U) + return NULL; + + return (const char *)((*AsmStrings) + AsmStrOffset); +} diff --git a/MCInstPrinter.h b/MCInstPrinter.h new file mode 100644 index 0000000000..687121167b --- /dev/null +++ b/MCInstPrinter.h @@ -0,0 +1,67 @@ +// +// Created by Phosphorus15 on 2021/5/14. +// + +#ifndef CAPSTONE_MCINSTPRINTER_H +#define CAPSTONE_MCINSTPRINTER_H + +#include "MCInst.h" +#include "capstone/platform.h" +#include "stdlib.h" + +// TODO we'll need this later +const MCRegisterInfo *MRI; + +typedef enum CondKind { + AliasPatternCond_K_Feature, // Match only if a feature is enabled. + AliasPatternCond_K_NegFeature, // Match only if a feature is disabled. + AliasPatternCond_K_OrFeature, // Match only if one of a set of features is + // enabled. + AliasPatternCond_K_OrNegFeature, // Match only if one of a set of features is + // disabled. + AliasPatternCond_K_EndOrFeatures, // Note end of list of K_Or(Neg)?Features. + AliasPatternCond_K_Ignore, // Match any operand. + AliasPatternCond_K_Reg, // Match a specific register. + AliasPatternCond_K_TiedReg, // Match another already matched register. + AliasPatternCond_K_Imm, // Match a specific immediate. + AliasPatternCond_K_RegClass, // Match registers in a class. + AliasPatternCond_K_Custom, // Call custom matcher by index. +} CondKind; + +typedef struct PatternsForOpcode { + uint32_t Opcode; + uint16_t PatternStart; + uint16_t NumPatterns; +} PatternsForOpcode; + +typedef struct AliasPattern { + uint32_t AsmStrOffset; + uint32_t AliasCondStart; + uint8_t NumOperands; + uint8_t NumConds; +} AliasPattern; + +typedef struct AliasPatternCond { + CondKind Kind; + uint32_t Value; +} AliasPatternCond; + +static inline int cmp_less(const void *l, const void *r) { + return ((signed)((const PatternsForOpcode *)l)->Opcode) - + ((signed)((const PatternsForOpcode *)r)->Opcode); +} + +// Binary Search Implementation - let's use bsearch for now +static inline PatternsForOpcode *Binary_Search(const PatternsForOpcode *OpToPatterns, + const unsigned opcode, unsigned len) { + return bsearch((void *)&opcode, (void *)OpToPatterns, len, + sizeof(PatternsForOpcode), cmp_less); +} + + +const char *MCInstPrinter_matchAliasPatterns( + const MCInst *MI, const PatternsForOpcode *OpToPatterns, + const AliasPattern *Patterns, const AliasPatternCond *Conds, + const char *AsmStrings[], unsigned len); + +#endif // CAPSTONE_MCINSTPRINTER_H diff --git a/Makefile b/Makefile index 942dcca47d..dfd8cda24b 100644 --- a/Makefile +++ b/Makefile @@ -305,7 +305,7 @@ endif LIBOBJ = -LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o +LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/MCRegisterInfo.o LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF) LIBOBJ += $(OBJDIR)/MCInst.o diff --git a/MathExtras.h b/MathExtras.h index e9f18689ba..5bc79322eb 100644 --- a/MathExtras.h +++ b/MathExtras.h @@ -439,4 +439,34 @@ static inline unsigned int countLeadingZeros(int x) return count; } +/// \brief Count number of 0's from the least significant bit to the most +/// stopping at the first 1. +/// +/// Only unsigned integral types are allowed. +/// +/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are +/// valid arguments. +static inline unsigned int countTrailingZeros(int x) { + int i; + const unsigned bits = sizeof(x) * 8 - 1; + unsigned count = 0; + + if (x < 0) { + return 0; + } + + for (i = bits; --i;) { + if (x % 2 == 0) + count++; + else + break; + } + + // considering it is signed integer + if (count == bits - 1 && x > 0) + count++; + + return count; +} + #endif diff --git a/arch/Mips/CapstoneMipsModule.h b/arch/Mips/CapstoneMipsModule.h new file mode 100644 index 0000000000..a9cb260659 --- /dev/null +++ b/arch/Mips/CapstoneMipsModule.h @@ -0,0 +1,1919 @@ +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} + +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget1SImm16(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeJumpTarget(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget21MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget26MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeJumpTargetXMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMem(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMemEVA(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLoadByte15(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCacheOp(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCacheOpMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePrefeOpMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSyncI(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSyncI_MM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSynciR6(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMImm4(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMImm9(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMImm12(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMImm16(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFMemMMR2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeLi16Imm(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePOOL16BEncodedField(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst *Inst, unsigned Value, + uint64_t Address, + void *Decoder, unsigned, + unsigned, unsigned); + +static DecodeStatus DecodeUImmWithOffset(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder, + unsigned Bits, unsigned Offset) { + return DecodeUImmWithOffsetAndScale(Inst, Value, Address, Decoder, Bits, + Offset, 1); +} +static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst *Inst, unsigned Value, + uint64_t Address, + void *Decoder, unsigned); + +static DecodeStatus DecodeInsSize(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeINSVE_DF(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDAHIDATI(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDAHIDATI(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDINS(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeDEXT(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeCRC(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned RegPair, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMovePOperands(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +#include "MipsGenDisassemblerTables.inc" + +static DecodeStatus DecodeINSVE_DF(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder) { + DecodeStatus (*RegDecoder)(MCInst *, unsigned, uint64_t, void *); + + // The size of the n field depends on the element size + // The register class also depends on this. + unsigned tmp = fieldFromInstruction(insn, 17, 5); + unsigned NSize = 0; + RegDecoder = 0x0; + if ((tmp & 0x18) == 0x00) { // INSVE_B + NSize = 4; + RegDecoder = DecodeMSA128BRegisterClass; + } else if ((tmp & 0x1c) == 0x10) { // INSVE_H + NSize = 3; + RegDecoder = DecodeMSA128HRegisterClass; + } else if ((tmp & 0x1e) == 0x18) { // INSVE_W + NSize = 2; + RegDecoder = DecodeMSA128WRegisterClass; + } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D + NSize = 1; + RegDecoder = DecodeMSA128DRegisterClass; + } else + llvm_unreachable("Invalid encoding"); + + assert(NSize != 0 && RegDecoder != 0x0); + + // $wd + tmp = fieldFromInstruction(insn, 6, 5); + if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + // $wd_in + if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + // $n + tmp = fieldFromInstruction(insn, 16, NSize); + MCOperand_CreateImm0(MI, tmp); + // $ws + tmp = fieldFromInstruction(insn, 11, 5); + if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + // $n2 + MCOperand_CreateImm0(MI, 0); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + unsigned Rs = fieldFromInstruction(insn, 16, 5); + unsigned Imm = fieldFromInstruction(insn, 0, 16); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDAHIDATI(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder) { + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Imm = fieldFromInstruction(insn, 0, 16); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the ADDI instruction from the earlier + // ISA's instead). + // + // We have: + // 0b001000 sssss ttttt iiiiiiiiiiiiiiii + // BOVC if rs >= rt + // BEQZALC if rs == 0 && rt != 0 + // BEQC if rs < rt && rs != 0 + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, Mips_BOVC); + HasRs = true; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, Mips_BEQC); + HasRs = true; + } else + MCInst_setOpcode(MI, Mips_BEQZALC); + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, + void *Decoder) { + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = 0; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, Mips_BOVC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, Mips_BEQC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + } else { + MCInst_setOpcode(MI, Mips_BEQZALC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the ADDI instruction from the earlier + // ISA's instead). + // + // We have: + // 0b011000 sssss ttttt iiiiiiiiiiiiiiii + // BNVC if rs >= rt + // BNEZALC if rs == 0 && rt != 0 + // BNEC if rs < rt && rs != 0 + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, Mips_BNVC); + HasRs = true; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, Mips_BNEC); + HasRs = true; + } else + MCInst_setOpcode(MI, Mips_BNEZALC); + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, + void *Decoder) { + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = 0; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, Mips_BNVC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, Mips_BNEC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + } else { + MCInst_setOpcode(MI, Mips_BNEZALC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, + void *Decoder) { + // We have: + // 0b110101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BGTZC_MMR6 if rs == 0 && rt != 0 + // BLTZC_MMR6 if rs == rt && rt != 0 + // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 + + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BGTZC_MMR6); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BLTZC_MMR6); + else { + MCInst_setOpcode(MI, Mips_BLTC_MMR6); + HasRs = true; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, + void *Decoder) { + // We have: + // 0b111101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BLEZC_MMR6 if rs == 0 && rt != 0 + // BGEZC_MMR6 if rs == rt && rt != 0 + // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 + + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BLEZC_MMR6); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BGEZC_MMR6); + else { + HasRs = true; + MCInst_setOpcode(MI, Mips_BGEC_MMR6); + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BLEZL instruction from the earlier + // ISA's instead). + // + // We have: + // 0b010110 sssss ttttt iiiiiiiiiiiiiiii + // Invalid if rs == 0 + // BLEZC if rs == 0 && rt != 0 + // BGEZC if rs == rt && rt != 0 + // BGEC if rs != rt && rs != 0 && rt != 0 + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BLEZC); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BGEZC); + else { + HasRs = true; + MCInst_setOpcode(MI, Mips_BGEC); + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BGTZL instruction from the earlier + // ISA's instead). + // + // We have: + // 0b010111 sssss ttttt iiiiiiiiiiiiiiii + // Invalid if rs == 0 + // BGTZC if rs == 0 && rt != 0 + // BLTZC if rs == rt && rt != 0 + // BLTC if rs != rt && rs != 0 && rt != 0 + + bool HasRs = false; + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BGTZC); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BLTZC); + else { + MCInst_setOpcode(MI, Mips_BLTC); + HasRs = true; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BGTZ instruction from the earlier + // ISA's instead). + // + // We have: + // 0b000111 sssss ttttt iiiiiiiiiiiiiiii + // BGTZ if rt == 0 + // BGTZALC if rs == 0 && rt != 0 + // BLTZALC if rs != 0 && rs == rt + // BLTUC if rs != 0 && rs != rt + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + bool HasRt = false; + + if (Rt == 0) { + MCInst_setOpcode(MI, Mips_BGTZ); + HasRs = true; + } else if (Rs == 0) { + MCInst_setOpcode(MI, Mips_BGTZALC); + HasRt = true; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, Mips_BLTZALC); + HasRs = true; + } else { + MCInst_setOpcode(MI, Mips_BLTUC); + HasRs = true; + HasRt = true; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + if (HasRt) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BLEZL instruction from the earlier + // ISA's instead). + // + // We have: + // 0b000110 sssss ttttt iiiiiiiiiiiiiiii + // Invalid if rs == 0 + // BLEZALC if rs == 0 && rt != 0 + // BGEZALC if rs == rt && rt != 0 + // BGEUC if rs != rt && rs != 0 && rt != 0 + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BLEZALC); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BGEZALC); + else { + HasRs = true; + MCInst_setOpcode(MI, Mips_BGEUC); + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDEXT(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder) { + unsigned Msbd = fieldFromInstruction(Insn, 11, 5); + unsigned Lsb = fieldFromInstruction(Insn, 6, 5); + unsigned Size = 0; + unsigned Pos = 0; + + switch (MCInst_getOpcode(MI)) { + case Mips_DEXT: + Pos = Lsb; + Size = Msbd + 1; + break; + case Mips_DEXTM: + Pos = Lsb; + Size = Msbd + 1 + 32; + break; + case Mips_DEXTU: + Pos = Lsb + 32; + Size = Msbd + 1; + break; + default: + llvm_unreachable("Unknown DEXT instruction!"); + } + + MCInst_setOpcode(MI, Mips_DEXT); + + unsigned Rs = fieldFromInstruction(Insn, 21, 5); + unsigned Rt = fieldFromInstruction(Insn, 16, 5); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rt)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateImm0(MI, Pos); + MCOperand_CreateImm0(MI, Size); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDINS(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder) { + unsigned Msbd = fieldFromInstruction(Insn, 11, 5); + unsigned Lsb = fieldFromInstruction(Insn, 6, 5); + unsigned Size = 0; + unsigned Pos = 0; + + switch (MCInst_getOpcode(MI)) { + case Mips_DINS: + Pos = Lsb; + Size = Msbd + 1 - Pos; + break; + case Mips_DINSM: + Pos = Lsb; + Size = Msbd + 33 - Pos; + break; + case Mips_DINSU: + Pos = Lsb + 32; + // mbsd = pos + size - 33 + // mbsd - pos + 33 = size + Size = Msbd + 33 - Pos; + break; + default: + llvm_unreachable("Unknown DINS instruction!"); + } + + unsigned Rs = fieldFromInstruction(Insn, 21, 5); + unsigned Rt = fieldFromInstruction(Insn, 16, 5); + + MCInst_setOpcode(MI, Mips_DINS); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rt)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateImm0(MI, Pos); + MCOperand_CreateImm0(MI, Size); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCRC(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder) { + unsigned Rs = fieldFromInstruction(Insn, 21, 5); + unsigned Rt = fieldFromInstruction(Insn, 16, 5); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + return MCDisassembler_Fail; +} + +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_GPR64RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_GPRMM16RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_GPRMM16ZeroRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_GPRMM16MovePRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (Inst->csh->mode & CS_MODE_MIPS64) + return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); + + return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); +} +static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_FGR64RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_FGR32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_CCRRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_FCCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_FGRCCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMem(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SC || MCInst_getOpcode(Inst) == Mips_SCD) + MCOperand_CreateReg0(Inst, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMemEVA(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn >> 7, 9); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SCE) + MCOperand_CreateReg0(Inst, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeLoadByte15(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeCacheOp(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Hint = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeCacheOpMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0xfff, 12); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Hint = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} +static DecodeStatus DecodePrefeOpMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0x1ff, 9); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Hint = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn >> 7, 9); + unsigned Hint = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeSyncI(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeSyncI_MM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeSynciR6(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Immediate = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Immediate); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); + unsigned Reg = fieldFromInstruction(Insn, 6, 5); + unsigned Base = fieldFromInstruction(Insn, 11, 5); + + Reg = getReg(Inst->MRI, Mips_MSA128BRegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + + // The immediate field of an LD/ST instruction is scaled which means it must + // be multiplied (when decoding) by the size (in bytes) of the instructions' + // data format. + // .b - 1 byte + // .h - 2 bytes + // .w - 4 bytes + // .d - 8 bytes + switch (MCInst_getOpcode(Inst)) { + default: + assert(false && "Unexpected instruction"); + return MCDisassembler_Fail; + break; + case Mips_LD_B: + case Mips_ST_B: + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_LD_H: + case Mips_ST_H: + MCOperand_CreateImm0(Inst, Offset * 2); + break; + case Mips_LD_W: + case Mips_ST_W: + MCOperand_CreateImm0(Inst, Offset * 4); + break; + case Mips_LD_D: + case Mips_ST_D: + MCOperand_CreateImm0(Inst, Offset * 8); + break; + } + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMemMMImm4(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned Offset = Insn & 0xf; + unsigned Reg = fieldFromInstruction(Insn, 7, 3); + unsigned Base = fieldFromInstruction(Insn, 4, 3); + + switch (MCInst_getOpcode(Inst)) { + case Mips_LBU16_MM: + case Mips_LHU16_MM: + case Mips_LW16_MM: + if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + break; + case Mips_SB16_MM: + case Mips_SB16_MMR6: + case Mips_SH16_MM: + case Mips_SH16_MMR6: + case Mips_SW16_MM: + case Mips_SW16_MMR6: + if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + break; + } + + if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + switch (MCInst_getOpcode(Inst)) { + case Mips_LBU16_MM: + if (Offset == 0xf) + MCOperand_CreateImm0(Inst, -1); + else + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_SB16_MM: + case Mips_SB16_MMR6: + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_LHU16_MM: + case Mips_SH16_MM: + case Mips_SH16_MMR6: + MCOperand_CreateImm0(Inst, Offset << 1); + break; + case Mips_LW16_MM: + case Mips_SW16_MM: + case Mips_SW16_MMR6: + MCOperand_CreateImm0(Inst, Offset << 2); + break; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned Offset = Insn & 0x1F; + unsigned Reg = fieldFromInstruction(Insn, 5, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Mips_SP); + MCOperand_CreateImm0(Inst, Offset << 2); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned Offset = Insn & 0x7F; + unsigned Reg = fieldFromInstruction(Insn, 7, 3); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Mips_GP); + MCOperand_CreateImm0(Inst, Offset << 2); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + int Offset; + switch (MCInst_getOpcode(Inst)) { + case Mips_LWM16_MMR6: + case Mips_SWM16_MMR6: + Offset = fieldFromInstruction(Insn, 4, 4); + break; + default: + Offset = SignExtend32(Insn & 0xf, 4); + break; + } + + if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, Mips_SP); + MCOperand_CreateImm0(Inst, Offset << 2); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMemMMImm9(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0x1ff, 9); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SCE_MM || + MCInst_getOpcode(Inst) == Mips_SC_MMR6) + MCOperand_CreateReg0(Inst, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMemMMImm12(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0x0fff, 12); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + switch (MCInst_getOpcode(Inst)) { + case Mips_SWM32_MM: + case Mips_LWM32_MM: + if (DecodeRegListOperand(Inst, Insn, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_SC_MM: + MCOperand_CreateReg0(Inst, Reg); + 0x0; + default: + MCOperand_CreateReg0(Inst, Reg); + if (MCInst_getOpcode(Inst) == Mips_LWP_MM || + MCInst_getOpcode(Inst) == Mips_SWP_MM) + MCOperand_CreateReg0(Inst, Reg + 1); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + } + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMemMMImm16(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_FGR64RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMemMMR2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + // This function is the same as DecodeFMem but with the Reg and Base fields + // swapped according to microMIPS spec. + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_FGR64RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_COP2RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_COP3RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0x07ff, 11); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 11, 5); + + Reg = getReg(Inst->MRI, Mips_COP2RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0x07ff, 11); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Inst->MRI, Mips_COP2RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int64_t Offset = SignExtend64(Insn >> 7, 9) & 0x1ff; + unsigned Rt = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Rt = getReg(Inst->MRI, Mips_GPR32RegClassID, Rt); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SC_R6 || + MCInst_getOpcode(Inst) == Mips_SCD_R6) { + MCOperand_CreateReg0(Inst, Rt); + } + + MCOperand_CreateReg0(Inst, Rt); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + // Currently only hardware register 29 is supported. + if (RegNo != 29) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, Mips_HWR29); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 30 || RegNo % 2) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_AFGR64RegClassID, RegNo / 2); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo >= 4) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_ACC64DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo >= 4) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_HI32DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo >= 4) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_LO32DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_MSA128BRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_MSA128HRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_MSA128WRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_MSA128DRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_MSACtrlRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_COP0RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_COP2RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = (SignExtend32(Offset, 16) * 4) + 4; + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget1SImm16(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = (SignExtend32(Offset, 16) * 2); + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeJumpTarget(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; + MCOperand_CreateImm0(Inst, JumpOffset); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset, 21) * 4 + 4; + + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget21MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset, 21) * 4 + 4; + + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset, 26) * 4 + 4; + + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset << 1, 8); + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset << 1, 11); + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + // llvm has a plus 4 out here - which turns out to be inconsitent with our + // test suite + int32_t BranchOffset = SignExtend32(Offset, 16) * 2 /* + 4 */; + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget26MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset << 1, 27); + + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; + MCOperand_CreateImm0(Inst, JumpOffset); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeJumpTargetXMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; + MCOperand_CreateImm0(Inst, JumpOffset); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder) { + if (Value == 0) + MCOperand_CreateImm0(Inst, 1); + else if (Value == 0x7) + MCOperand_CreateImm0(Inst, -1); + else + MCOperand_CreateImm0(Inst, Value << 2); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLi16Imm(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder) { + if (Value == 0x7F) + MCOperand_CreateImm0(Inst, -1); + else + MCOperand_CreateImm0(Inst, Value); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOOL16BEncodedField(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, Value == 0x0 ? 8 : Value); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst *Inst, unsigned Value, + uint64_t Address, + void *Decoder, unsigned Bits, + unsigned Offset, + unsigned Scale) { + Value &= ((1 << Bits) - 1); + Value *= Scale; + MCOperand_CreateImm0(Inst, Value + Offset); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst *Inst, unsigned Value, + uint64_t Address, + void *Decoder, unsigned Bits) { + unsigned Offset = 0; // we don't have default values in C, so here it goes + unsigned ScaleBy = 1; + int32_t Imm = SignExtend32(Value, Bits) * ScaleBy; + MCOperand_CreateImm0(Inst, (int64_t)Imm + Offset); + return MCDisassembler_Success; +} +static DecodeStatus DecodeInsSize(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + // First we need to grab the pos(lsb) from MCInst. + // This function only handles the 32 bit variants of ins, as dins + // variants are handled differently. + int Pos = MCOperand_getImm(MCInst_getOperand(Inst, 2)); + int Size = (int)Insn - Pos + 1; + MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); + return MCDisassembler_Success; +} +static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); + return MCDisassembler_Success; +} +static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int32_t DecodedValue; + switch (Insn) { + case 0: + DecodedValue = 256; + break; + case 1: + DecodedValue = 257; + break; + case 510: + DecodedValue = -258; + break; + case 511: + DecodedValue = -257; + break; + default: + DecodedValue = SignExtend32(Insn, 9); + break; + } + MCOperand_CreateImm0(Inst, DecodedValue * 4); + return MCDisassembler_Success; +} +static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + // Insn must be >= 0, since it is unsigned that condition is always true. + assert(Insn < 16); + int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, + 16, 31, 32, 63, 64, 255, 32768, 65535}; + MCOperand_CreateImm0(Inst, DecodedValues[Insn]); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, + Mips_S5, Mips_S6, Mips_S7, Mips_FP}; + unsigned RegNum; + + unsigned RegLst = fieldFromInstruction(Insn, 21, 5); + + // Empty register lists are not allowed. + if (RegLst == 0) + return MCDisassembler_Fail; + + RegNum = RegLst & 0xf; + + // RegLst values 10-15, and 26-31 are reserved. + if (RegNum > 9) + return MCDisassembler_Fail; + + for (unsigned i = 0; i < RegNum; i++) + MCOperand_CreateReg0(Inst, Regs[i]); + + if (RegLst & 0x10) + MCOperand_CreateReg0(Inst, Mips_RA); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3}; + unsigned RegLst; + switch (MCInst_getOpcode(Inst)) { + default: + RegLst = fieldFromInstruction(Insn, 4, 2); + break; + case Mips_LWM16_MMR6: + case Mips_SWM16_MMR6: + RegLst = fieldFromInstruction(Insn, 8, 2); + break; + } + unsigned RegNum = RegLst & 0x3; + + for (unsigned i = 0; i <= RegNum; i++) + MCOperand_CreateReg0(Inst, Regs[i]); + + MCOperand_CreateReg0(Inst, Mips_RA); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMovePOperands(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned RegPair = fieldFromInstruction(Insn, 7, 3); + if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + unsigned RegRs; + if (Inst->csh->mode & CS_MODE_MIPS32R6) + RegRs = fieldFromInstruction(Insn, 0, 2) | + (fieldFromInstruction(Insn, 3, 1) << 2); + else + RegRs = fieldFromInstruction(Insn, 1, 3); + if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + unsigned RegRt = fieldFromInstruction(Insn, 4, 3); + if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned RegPair, + uint64_t Address, void *Decoder) { + switch (RegPair) { + default: + return MCDisassembler_Fail; + case 0: + MCOperand_CreateReg0(Inst, Mips_A1); + MCOperand_CreateReg0(Inst, Mips_A2); + break; + case 1: + MCOperand_CreateReg0(Inst, Mips_A1); + MCOperand_CreateReg0(Inst, Mips_A3); + break; + case 2: + MCOperand_CreateReg0(Inst, Mips_A2); + MCOperand_CreateReg0(Inst, Mips_A3); + break; + case 3: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_S5); + break; + case 4: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_S6); + break; + case 5: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_A1); + break; + case 6: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_A2); + break; + case 7: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_A3); + break; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, SignExtend32(Insn << 2, 25)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // We have: + // 0b000111 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BGTZALC_MMR6 if rs == 0 && rt != 0 + // BLTZALC_MMR6 if rs != 0 && rs == rt + // BLTUC_MMR6 if rs != 0 && rs != rt + + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + unsigned Imm = 0; + bool HasRs = false; + bool HasRt = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) { + MCInst_setOpcode(MI, Mips_BGTZALC_MMR6); + HasRt = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, Mips_BLTZALC_MMR6); + HasRs = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else { + MCInst_setOpcode(MI, Mips_BLTUC_MMR6); + HasRs = true; + HasRt = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + if (HasRt) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // We have: + // 0b000110 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BLEZALC_MMR6 if rs == 0 && rt != 0 + // BGEZALC_MMR6 if rs == rt && rt != 0 + // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 + + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + unsigned Imm = 0; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) { + MCInst_setOpcode(MI, Mips_BLEZALC_MMR6); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, Mips_BGEZALC_MMR6); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else { + HasRs = true; + MCInst_setOpcode(MI, Mips_BGEUC_MMR6); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c index 294082394a..94d58257f8 100644 --- a/arch/Mips/MipsDisassembler.c +++ b/arch/Mips/MipsDisassembler.c @@ -39,304 +39,53 @@ #include "../../MCRegisterInfo.h" #include "../../MCDisassembler.h" -// Forward declare these because the autogenerated code will reference them. -// Definitions are further down. -static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBranchTarget(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeJumpTarget(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBranchTarget21(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBranchTarget26(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); - -// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); - -// DecodeBranchTargetMM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -// DecodeJumpTargetMM - Decode microMIPS jump target, which is -// shifted left by 1 bit. -static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCacheOp(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCacheOpR6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCacheOpMM(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSyncI(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128Mem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMImm4(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMImm12(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMImm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeLiSimm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm4(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -// Decode the immediate field of an LSA instruction which -// is off by one. -static DecodeStatus DecodeLSAImm(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeInsSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeExtSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm9SP(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeANDI16Imm(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't -/// handle. -static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeRegListOperand(MCInst *Inst, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeRegListOperand16(MCInst *Inst, - uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMovePRegPair(MCInst *Inst, - uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); - #define GET_SUBTARGETINFO_ENUM -#include "MipsGenSubtargetInfo.inc" - -// Hacky: enable all features for disassembler -static uint64_t getFeatureBits(int mode) -{ - uint64_t Bits = (uint64_t)-1; // include every features at first - - // By default we do not support Mips1 - Bits &= ~Mips_FeatureMips1; - - // No MicroMips - Bits &= ~Mips_FeatureMicroMips; - - // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() - // some features are mutually execlusive - if (mode & CS_MODE_16) { - //Bits &= ~Mips_FeatureMips32r2; - //Bits &= ~Mips_FeatureMips32; - //Bits &= ~Mips_FeatureFPIdx; - //Bits &= ~Mips_FeatureBitCount; - //Bits &= ~Mips_FeatureSwap; - //Bits &= ~Mips_FeatureSEInReg; - //Bits &= ~Mips_FeatureMips64r2; - //Bits &= ~Mips_FeatureFP64Bit; - } else if (mode & CS_MODE_32) { - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureFP64Bit; - Bits &= ~Mips_FeatureMips64r2; - Bits &= ~Mips_FeatureMips32r6; - Bits &= ~Mips_FeatureMips64r6; - } else if (mode & CS_MODE_64) { - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureMips64r6; - Bits &= ~Mips_FeatureMips32r6; - } else if (mode & CS_MODE_MIPS32R6) { - Bits |= Mips_FeatureMips32r6; - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureFP64Bit; - Bits &= ~Mips_FeatureMips64r6; - Bits &= ~Mips_FeatureMips64r2; - } - - if (mode & CS_MODE_MICRO) { - Bits |= Mips_FeatureMicroMips; - Bits &= ~Mips_FeatureMips4_32r2; - Bits &= ~Mips_FeatureMips2; - } - - return Bits; -} - -#include "MipsGenDisassemblerTables.inc" +#define UNIT ((uint64_t)1) +static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo); +// static uint64_t getFeatureBits(int mode); +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require); #define GET_REGINFO_ENUM -#include "MipsGenRegisterInfo.inc" - #define GET_REGINFO_MC_DESC -#include "MipsGenRegisterInfo.inc" - #define GET_INSTRINFO_ENUM -#include "MipsGenInstrInfo.inc" +#define MIPS_GET_DISASSEMBLER +#include "CapstoneMipsModule.h" + +/// Extract 'not' into Require, Require being '0' or 'false' means returns true +/// when the feature is not available Also we're not using bits to represent +/// feature anymore (for obvious reason) +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require) { + // if(Feature == Mips_FeatureFP64Bit) return true; // enables all fp + // instructions (32/64) + switch (Feature) { + default: + return true; // For arbitrary checks we always declare it true - enables all + // checks + case Mips_FeatureMips1: // Disabled features + case Mips_FeatureMicroMips: + return getbool(Bits & CS_MODE_MICRO) == Require; + case Mips_FeatureMips4_32r2: + case Mips_FeatureMips2: + return getbool(Bits & CS_MODE_MICRO) != Require; // these two are disabled + case Mips_FeatureSoftFloat: // Soft float represents no instruction + return !Require; + case Mips_FeatureMips16: + return getbool(Bits & CS_MODE_16) == Require; + case Mips_FeatureMips32r6: + return getbool(Bits & CS_MODE_MIPS32R6) == Require; + case Mips_FeatureMips64r6: + return getbool(Bits & (CS_MODE_16 | CS_MODE_32 | CS_MODE_MIPS32R6 | + CS_MODE_64)) != Require; + case Mips_FeatureFP64Bit: + return true; // enable this feature if required + case Mips_FeatureMips64r2: + return getbool(Bits & CS_MODE_64) == Require; + } + return false; // unreachable +} + void Mips_init(MCRegisterInfo *MRI) { @@ -354,14 +103,10 @@ void Mips_init(MCRegisterInfo *MRI) // MipsRegEncodingTable); - MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394, - 0, 0, - MipsMCRegisterClasses, 62, - 0, 0, - MipsRegDiffLists, - 0, - MipsSubRegIdxLists, 12, - 0); + MCRegisterInfo_InitMCRegisterInfo( + MRI, MipsRegDesc, ARR_SIZE(MipsRegDesc), 0, 0, MipsMCRegisterClasses, + ARR_SIZE(MipsMCRegisterClasses), 0, 0, MipsRegDiffLists, 0, + MipsSubRegIdxLists, ARR_SIZE(MipsSubRegIdxLists), 0); } /// Read two bytes from the ArrayRef and return 16 bit halfword sorted @@ -412,6 +157,8 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr, uint32_t Insn; DecodeStatus Result; + instr->MRI = MRI; + if (instr->flat_insn->detail) { memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips)); } @@ -521,1274 +268,5 @@ static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) return rc->RegsBegin[RegNo]; } -static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *); - // The size of the n field depends on the element size - // The register class also depends on this. - uint32_t tmp = fieldFromInstruction(insn, 17, 5); - unsigned NSize = 0; - DecodeFN RegDecoder = NULL; - - if ((tmp & 0x18) == 0x00) { // INSVE_B - NSize = 4; - RegDecoder = DecodeMSA128BRegisterClass; - } else if ((tmp & 0x1c) == 0x10) { // INSVE_H - NSize = 3; - RegDecoder = DecodeMSA128HRegisterClass; - } else if ((tmp & 0x1e) == 0x18) { // INSVE_W - NSize = 2; - RegDecoder = DecodeMSA128WRegisterClass; - } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D - NSize = 1; - RegDecoder = DecodeMSA128DRegisterClass; - } //else llvm_unreachable("Invalid encoding"); - - //assert(NSize != 0 && RegDecoder != nullptr); - if (NSize == 0 || RegDecoder == NULL) - return MCDisassembler_Fail; - - // $wd - tmp = fieldFromInstruction(insn, 6, 5); - if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) - return MCDisassembler_Fail; - - // $wd_in - if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) - return MCDisassembler_Fail; - - // $n - tmp = fieldFromInstruction(insn, 16, NSize); - MCOperand_CreateImm0(MI, tmp); - - // $ws - tmp = fieldFromInstruction(insn, 11, 5); - if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) - return MCDisassembler_Fail; - - // $n2 - MCOperand_CreateImm0(MI, 0); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the ADDI instruction from the earlier - // ISA's instead). - // - // We have: - // 0b001000 sssss ttttt iiiiiiiiiiiiiiii - // BOVC if rs >= rt - // BEQZALC if rs == 0 && rt != 0 - // BEQC if rs < rt && rs != 0 - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - bool HasRs = false; - - if (Rs >= Rt) { - MCInst_setOpcode(MI, Mips_BOVC); - HasRs = true; - } else if (Rs != 0 && Rs < Rt) { - MCInst_setOpcode(MI, Mips_BEQC); - HasRs = true; - } else - MCInst_setOpcode(MI, Mips_BEQZALC); - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the ADDI instruction from the earlier - // ISA's instead). - // - // We have: - // 0b011000 sssss ttttt iiiiiiiiiiiiiiii - // BNVC if rs >= rt - // BNEZALC if rs == 0 && rt != 0 - // BNEC if rs < rt && rs != 0 - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - bool HasRs = false; - - if (Rs >= Rt) { - MCInst_setOpcode(MI, Mips_BNVC); - HasRs = true; - } else if (Rs != 0 && Rs < Rt) { - MCInst_setOpcode(MI, Mips_BNEC); - HasRs = true; - } else - MCInst_setOpcode(MI, Mips_BNEZALC); - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the BLEZL instruction from the earlier - // ISA's instead). - // - // We have: - // 0b010110 sssss ttttt iiiiiiiiiiiiiiii - // Invalid if rs == 0 - // BLEZC if rs == 0 && rt != 0 - // BGEZC if rs == rt && rt != 0 - // BGEC if rs != rt && rs != 0 && rt != 0 - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - bool HasRs = false; - - if (Rt == 0) - return MCDisassembler_Fail; - else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BLEZC); - else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BGEZC); - else { - HasRs = true; - MCInst_setOpcode(MI, Mips_BGEC); - } - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the BGTZL instruction from the earlier - // ISA's instead). - // - // We have: - // 0b010111 sssss ttttt iiiiiiiiiiiiiiii - // Invalid if rs == 0 - // BGTZC if rs == 0 && rt != 0 - // BLTZC if rs == rt && rt != 0 - // BLTC if rs != rt && rs != 0 && rt != 0 - - bool HasRs = false; - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - - if (Rt == 0) - return MCDisassembler_Fail; - else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BGTZC); - else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BLTZC); - else { - MCInst_setOpcode(MI, Mips_BLTC); - HasRs = true; - } - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the BGTZ instruction from the earlier - // ISA's instead). - // - // We have: - // 0b000111 sssss ttttt iiiiiiiiiiiiiiii - // BGTZ if rt == 0 - // BGTZALC if rs == 0 && rt != 0 - // BLTZALC if rs != 0 && rs == rt - // BLTUC if rs != 0 && rs != rt - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - bool HasRs = false; - bool HasRt = false; - - if (Rt == 0) { - MCInst_setOpcode(MI, Mips_BGTZ); - HasRs = true; - } else if (Rs == 0) { - MCInst_setOpcode(MI, Mips_BGTZALC); - HasRt = true; - } else if (Rs == Rt) { - MCInst_setOpcode(MI, Mips_BLTZALC); - HasRs = true; - } else { - MCInst_setOpcode(MI, Mips_BLTUC); - HasRs = true; - HasRt = true; - } - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - if (HasRt) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the BLEZL instruction from the earlier - // ISA's instead). - // - // We have: - // 0b000110 sssss ttttt iiiiiiiiiiiiiiii - // Invalid if rs == 0 - // BLEZALC if rs == 0 && rt != 0 - // BGEZALC if rs == rt && rt != 0 - // BGEUC if rs != rt && rs != 0 && rt != 0 - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - bool HasRs = false; - - if (Rt == 0) - return MCDisassembler_Fail; - else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BLEZALC); - else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BGEZALC); - else { - HasRs = true; - MCInst_setOpcode(MI, Mips_BGEUC); - } - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - return MCDisassembler_Fail; -} - -static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - // if (static_cast(Decoder)->isGP64()) - if (Inst->csh->mode & CS_MODE_MIPS64) - return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); - - return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - int opcode = MCInst_getOpcode(Inst); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - if (opcode == Mips_SC || opcode == Mips_SCD) { - MCOperand_CreateReg0(Inst, Reg); - } - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCacheOp(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Hint = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCacheOpMM(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xfff, 12); - unsigned Base = fieldFromInstruction(Insn, 16, 5); - unsigned Hint = fieldFromInstruction(Insn, 21, 5); - - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCacheOpR6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = fieldFromInstruction(Insn, 7, 9); - unsigned Hint = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSyncI(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); - unsigned Reg = fieldFromInstruction(Insn, 6, 5); - unsigned Base = fieldFromInstruction(Insn, 11, 5); - - Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - // MCOperand_CreateImm0(Inst, Offset); - - // The immediate field of an LD/ST instruction is scaled which means it must - // be multiplied (when decoding) by the size (in bytes) of the instructions' - // data format. - // .b - 1 byte - // .h - 2 bytes - // .w - 4 bytes - // .d - 8 bytes - switch(MCInst_getOpcode(Inst)) { - default: - //assert (0 && "Unexpected instruction"); - return MCDisassembler_Fail; - break; - case Mips_LD_B: - case Mips_ST_B: - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_LD_H: - case Mips_ST_H: - MCOperand_CreateImm0(Inst, Offset * 2); - break; - case Mips_LD_W: - case Mips_ST_W: - MCOperand_CreateImm0(Inst, Offset * 4); - break; - case Mips_LD_D: - case Mips_ST_D: - MCOperand_CreateImm0(Inst, Offset * 8); - break; - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMImm4(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Offset = Insn & 0xf; - unsigned Reg = fieldFromInstruction(Insn, 7, 3); - unsigned Base = fieldFromInstruction(Insn, 4, 3); - - switch (MCInst_getOpcode(Inst)) { - case Mips_LBU16_MM: - case Mips_LHU16_MM: - case Mips_LW16_MM: - if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - break; - case Mips_SB16_MM: - case Mips_SH16_MM: - case Mips_SW16_MM: - if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - break; - } - - if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - - switch (MCInst_getOpcode(Inst)) { - case Mips_LBU16_MM: - if (Offset == 0xf) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_SB16_MM: - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_LHU16_MM: - case Mips_SH16_MM: - MCOperand_CreateImm0(Inst, Offset << 1); - break; - case Mips_LW16_MM: - case Mips_SW16_MM: - MCOperand_CreateImm0(Inst, Offset << 2); - break; - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Offset = Insn & 0x1F; - unsigned Reg = fieldFromInstruction(Insn, 5, 5); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Mips_SP); - MCOperand_CreateImm0(Inst, Offset << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Offset = Insn & 0x7F; - unsigned Reg = fieldFromInstruction(Insn, 7, 3); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Mips_GP); - MCOperand_CreateImm0(Inst, Offset << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xf, 4); - - if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, Mips_SP); - MCOperand_CreateImm0(Inst, Offset * 4); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMImm12(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0x0fff, 12); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - switch (MCInst_getOpcode(Inst)) { - case Mips_SWM32_MM: - case Mips_LWM32_MM: - if (DecodeRegListOperand(Inst, Insn, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_SC_MM: - MCOperand_CreateReg0(Inst, Reg); - // fallthrough - default: - MCOperand_CreateReg0(Inst, Reg); - if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM) - MCOperand_CreateReg0(Inst, Reg + 1); - - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMImm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFMem2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFMem3(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0x07ff, 11); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 11, 5); - - Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9); - unsigned Rt = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - if (MCInst_getOpcode(Inst) == Mips_SC_R6 || - MCInst_getOpcode(Inst) == Mips_SCD_R6) { - MCOperand_CreateReg0(Inst, Rt); - } - - MCOperand_CreateReg0(Inst, Rt); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - // Currently only hardware register 29 is supported. - if (RegNo != 29) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, Mips_HWR29); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 30 || RegNo % 2) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo >= 4) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo >= 4) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo >= 4) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4; - MCOperand_CreateImm0(Inst, TargetAddress); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeJumpTarget(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF); - MCOperand_CreateImm0(Inst, TargetAddress); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget21(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 21) * 4; - - MCOperand_CreateImm0(Inst, BranchOffset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget26(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 26) * 4; - - MCOperand_CreateImm0(Inst, BranchOffset); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 7) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 10) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 16) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; - MCOperand_CreateImm0(Inst, JumpOffset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - if (Value == 0) - MCOperand_CreateImm0(Inst, 1); - else if (Value == 0x7) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Value << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, Value << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeLiSimm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - if (Value == 0x7F) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Value); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm4(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Value, 4)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeLSAImm(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - // We add one to the immediate field as it was encoded as 'imm - 1'. - MCOperand_CreateImm0(Inst, Insn + 1); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeInsSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - // First we need to grab the pos(lsb) from MCInst. - int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2)); - int Size = (int) Insn - Pos + 1; - MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeExtSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Size = (int)Insn + 1; - - MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - int32_t DecodedValue; - - switch (Insn) { - case 0: DecodedValue = 256; break; - case 1: DecodedValue = 257; break; - case 510: DecodedValue = -258; break; - case 511: DecodedValue = -257; break; - default: DecodedValue = SignExtend32(Insn, 9); break; - } - MCOperand_CreateImm0(Inst, DecodedValue * 4); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - // Insn must be >= 0, since it is unsigned that condition is always true. - // assert(Insn < 16); - int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, - 255, 32768, 65535}; - - if (Insn >= 16) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, DecodedValues[Insn]); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, Insn << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, - Mips_S6, Mips_FP}; - unsigned RegNum; - unsigned int i; - - unsigned RegLst = fieldFromInstruction(Insn, 21, 5); - // Empty register lists are not allowed. - if (RegLst == 0) - return MCDisassembler_Fail; - - RegNum = RegLst & 0xf; - for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++) - MCOperand_CreateReg0(Inst, Regs[i]); - - if (RegLst & 0x10) - MCOperand_CreateReg0(Inst, Mips_RA); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3}; - unsigned RegLst = fieldFromInstruction(Insn, 4, 2); - unsigned RegNum = RegLst & 0x3; - unsigned int i; - - for (i = 0; i <= RegNum; i++) - MCOperand_CreateReg0(Inst, Regs[i]); - - MCOperand_CreateReg0(Inst, Mips_RA); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned RegPair = fieldFromInstruction(Insn, 7, 3); - - switch (RegPair) { - default: - return MCDisassembler_Fail; - case 0: - MCOperand_CreateReg0(Inst, Mips_A1); - MCOperand_CreateReg0(Inst, Mips_A2); - break; - case 1: - MCOperand_CreateReg0(Inst, Mips_A1); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - case 2: - MCOperand_CreateReg0(Inst, Mips_A2); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - case 3: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_S5); - break; - case 4: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_S6); - break; - case 5: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A1); - break; - case 6: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A2); - break; - case 7: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4); - return MCDisassembler_Success; -} #endif diff --git a/arch/Mips/MipsGenAsmWriter.inc b/arch/Mips/MipsGenAsmWriter.inc index cd252131f9..a51b9f3c9a 100644 --- a/arch/Mips/MipsGenAsmWriter.inc +++ b/arch/Mips/MipsGenAsmWriter.inc @@ -11,4683 +11,13074 @@ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) -{ - static const uint32_t OpInfo[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 9396U, // DBG_VALUE - 0U, // REG_SEQUENCE - 0U, // COPY - 9389U, // BUNDLE - 9406U, // LIFETIME_START - 9376U, // LIFETIME_END - 0U, // STACKMAP - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 21660U, // ABSQ_S_PH - 18025U, // ABSQ_S_QB - 24850U, // ABSQ_S_W - 134237992U, // ADD - 18294U, // ADDIUPC - 18294U, // ADDIUPC_MM - 22527U, // ADDIUR1SP_MM - 134234410U, // ADDIUR2_MM - 8683851U, // ADDIUS5_MM - 546875U, // ADDIUSP_MM - 134239193U, // ADDQH_PH - 134239310U, // ADDQH_R_PH - 134242253U, // ADDQH_R_W - 134241856U, // ADDQH_W - 134239267U, // ADDQ_PH - 134239366U, // ADDQ_S_PH - 134242558U, // ADDQ_S_W - 134236055U, // ADDSC - 134234730U, // ADDS_A_B - 134236180U, // ADDS_A_D - 134238138U, // ADDS_A_H - 134241564U, // ADDS_A_W - 134235198U, // ADDS_S_B - 134237269U, // ADDS_S_D - 134238695U, // ADDS_S_H - 134242608U, // ADDS_S_W - 134235413U, // ADDS_U_B - 134237736U, // ADDS_U_D - 134238973U, // ADDS_U_H - 134243026U, // ADDS_U_W - 134234575U, // ADDU16_MM - 134235621U, // ADDUH_QB - 134235729U, // ADDUH_R_QB - 134239465U, // ADDU_PH - 134235834U, // ADDU_QB - 134239410U, // ADDU_S_PH - 134235775U, // ADDU_S_QB - 2281718627U, // ADDVI_B - 2281720348U, // ADDVI_D - 2281722002U, // ADDVI_H - 2281725637U, // ADDVI_W - 134235491U, // ADDV_B - 134237836U, // ADDV_D - 134239051U, // ADDV_H - 134243126U, // ADDV_W - 134236094U, // ADDWC - 134234712U, // ADD_A_B - 134236161U, // ADD_A_D - 134238120U, // ADD_A_H - 134241545U, // ADD_A_W - 134237992U, // ADD_MM - 134239685U, // ADDi - 134239685U, // ADDi_MM - 134241307U, // ADDiu - 134241307U, // ADDiu_MM - 134241261U, // ADDu - 134241261U, // ADDu_MM - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 134240158U, // ALIGN - 18286U, // ALUIPC - 134238014U, // AND - 835930U, // AND16_MM - 134238014U, // AND64 - 134234471U, // ANDI16_MM - 2281718486U, // ANDI_B - 134238014U, // AND_MM - 134241389U, // AND_V - 0U, // AND_V_D_PSEUDO - 0U, // AND_V_H_PSEUDO - 0U, // AND_V_W_PSEUDO - 134239691U, // ANDi - 134239691U, // ANDi64 - 134239691U, // ANDi_MM - 134238028U, // APPEND - 134235092U, // ASUB_S_B - 134237099U, // ASUB_S_D - 134238527U, // ASUB_S_H - 134242388U, // ASUB_S_W - 134235307U, // ASUB_U_B - 134237566U, // ASUB_U_D - 134238815U, // ASUB_U_H - 134242856U, // ASUB_U_W - 0U, // ATOMIC_CMP_SWAP_I16 - 0U, // ATOMIC_CMP_SWAP_I32 - 0U, // ATOMIC_CMP_SWAP_I64 - 0U, // ATOMIC_CMP_SWAP_I8 - 0U, // ATOMIC_LOAD_ADD_I16 - 0U, // ATOMIC_LOAD_ADD_I32 - 0U, // ATOMIC_LOAD_ADD_I64 - 0U, // ATOMIC_LOAD_ADD_I8 - 0U, // ATOMIC_LOAD_AND_I16 - 0U, // ATOMIC_LOAD_AND_I32 - 0U, // ATOMIC_LOAD_AND_I64 - 0U, // ATOMIC_LOAD_AND_I8 - 0U, // ATOMIC_LOAD_NAND_I16 - 0U, // ATOMIC_LOAD_NAND_I32 - 0U, // ATOMIC_LOAD_NAND_I64 - 0U, // ATOMIC_LOAD_NAND_I8 - 0U, // ATOMIC_LOAD_OR_I16 - 0U, // ATOMIC_LOAD_OR_I32 - 0U, // ATOMIC_LOAD_OR_I64 - 0U, // ATOMIC_LOAD_OR_I8 - 0U, // ATOMIC_LOAD_SUB_I16 - 0U, // ATOMIC_LOAD_SUB_I32 - 0U, // ATOMIC_LOAD_SUB_I64 - 0U, // ATOMIC_LOAD_SUB_I8 - 0U, // ATOMIC_LOAD_XOR_I16 - 0U, // ATOMIC_LOAD_XOR_I32 - 0U, // ATOMIC_LOAD_XOR_I64 - 0U, // ATOMIC_LOAD_XOR_I8 - 0U, // ATOMIC_SWAP_I16 - 0U, // ATOMIC_SWAP_I32 - 0U, // ATOMIC_SWAP_I64 - 0U, // ATOMIC_SWAP_I8 - 134239795U, // AUI - 18279U, // AUIPC - 134235178U, // AVER_S_B - 134237249U, // AVER_S_D - 134238665U, // AVER_S_H - 134242588U, // AVER_S_W - 134235393U, // AVER_U_B - 134237716U, // AVER_U_D - 134238953U, // AVER_U_H - 134243006U, // AVER_U_W - 134235120U, // AVE_S_B - 134237181U, // AVE_S_D - 134238597U, // AVE_S_H - 134242470U, // AVE_S_W - 134235335U, // AVE_U_B - 134237648U, // AVE_U_D - 134238885U, // AVE_U_H - 134242938U, // AVE_U_W - 23579U, // AddiuRxImmX16 - 1072155U, // AddiuRxPcImmX16 - 285236251U, // AddiuRxRxImm16 - 16800795U, // AddiuRxRxImmX16 - 25189403U, // AddiuRxRyOffMemX16 - 1336343U, // AddiuSpImm16 - 549911U, // AddiuSpImmX16 - 134241261U, // AdduRxRyRz16 - 16797502U, // AndRxRxRy16 - 0U, // B - 541013U, // B16_MM - 134241260U, // BADDu - 546393U, // BAL - 542494U, // BALC - 134240157U, // BALIGN - 0U, // BAL_BR - 167788585U, // BBIT0 - 167788717U, // BBIT032 - 167788710U, // BBIT1 - 167788726U, // BBIT132 - 542473U, // BC - 20351U, // BC0F - 22218U, // BC0FL - 23455U, // BC0T - 22347U, // BC0TL - 25733U, // BC1EQZ - 20357U, // BC1F - 22225U, // BC1FL - 20357U, // BC1F_MM - 25717U, // BC1NEZ - 23461U, // BC1T - 22354U, // BC1TL - 23461U, // BC1T_MM - 25741U, // BC2EQZ - 20363U, // BC2F - 22232U, // BC2FL - 25725U, // BC2NEZ - 23467U, // BC2T - 22361U, // BC2TL - 20369U, // BC3F - 22239U, // BC3FL - 23473U, // BC3T - 22368U, // BC3TL - 2281718555U, // BCLRI_B - 2281720292U, // BCLRI_D - 2281721946U, // BCLRI_H - 2281725581U, // BCLRI_W - 134235059U, // BCLR_B - 134237023U, // BCLR_D - 134238494U, // BCLR_H - 134242304U, // BCLR_W - 134240340U, // BEQ - 134240340U, // BEQ64 - 134236044U, // BEQC - 134240063U, // BEQL - 16882U, // BEQZ16_MM - 18246U, // BEQZALC - 18394U, // BEQZC - 18394U, // BEQZC_MM - 134240340U, // BEQ_MM - 134235917U, // BGEC - 134236068U, // BGEUC - 25500U, // BGEZ - 25500U, // BGEZ64 - 22115U, // BGEZAL - 18219U, // BGEZALC - 22311U, // BGEZALL - 23424U, // BGEZALS_MM - 22115U, // BGEZAL_MM - 18373U, // BGEZC - 22391U, // BGEZL - 25500U, // BGEZ_MM - 25560U, // BGTZ - 25560U, // BGTZ64 - 18255U, // BGTZALC - 18401U, // BGTZC - 22405U, // BGTZL - 25560U, // BGTZ_MM - 2298495744U, // BINSLI_B - 2298497481U, // BINSLI_D - 2298499135U, // BINSLI_H - 2298502770U, // BINSLI_W - 151012243U, // BINSL_B - 151014033U, // BINSL_D - 151015601U, // BINSL_H - 151019280U, // BINSL_W - 2298495805U, // BINSRI_B - 2298497526U, // BINSRI_D - 2298499180U, // BINSRI_H - 2298502815U, // BINSRI_W - 151012291U, // BINSR_B - 151014289U, // BINSR_D - 151015726U, // BINSR_H - 151019570U, // BINSR_W - 23733U, // BITREV - 22477U, // BITSWAP - 25506U, // BLEZ - 25506U, // BLEZ64 - 18228U, // BLEZALC - 18380U, // BLEZC - 22398U, // BLEZL - 25506U, // BLEZ_MM - 134236062U, // BLTC - 134236075U, // BLTUC - 25566U, // BLTZ - 25566U, // BLTZ64 - 22123U, // BLTZAL - 18264U, // BLTZALC - 22320U, // BLTZALL - 23433U, // BLTZALS_MM - 22123U, // BLTZAL_MM - 18408U, // BLTZC - 22412U, // BLTZL - 25566U, // BLTZ_MM - 2298495860U, // BMNZI_B - 151018662U, // BMNZ_V - 2298495852U, // BMZI_B - 151018648U, // BMZ_V - 134238058U, // BNE - 134238058U, // BNE64 - 134235923U, // BNEC - 2281718494U, // BNEGI_B - 2281720240U, // BNEGI_D - 2281721894U, // BNEGI_H - 2281725529U, // BNEGI_W - 134234814U, // BNEG_B - 134236568U, // BNEG_D - 134238222U, // BNEG_H - 134241776U, // BNEG_W - 134239940U, // BNEL - 16874U, // BNEZ16_MM - 18237U, // BNEZALC - 18387U, // BNEZC - 18387U, // BNEZC_MM - 134238058U, // BNE_MM - 134236082U, // BNVC - 17803U, // BNZ_B - 20233U, // BNZ_D - 21363U, // BNZ_H - 23711U, // BNZ_V - 25463U, // BNZ_W - 134236088U, // BOVC - 540871U, // BPOSGE32 - 0U, // BPOSGE32_PSEUDO - 22080U, // BREAK - 65909U, // BREAK16_MM - 22080U, // BREAK_MM - 2298495719U, // BSELI_B - 0U, // BSEL_D_PSEUDO - 0U, // BSEL_FD_PSEUDO - 0U, // BSEL_FW_PSEUDO - 0U, // BSEL_H_PSEUDO - 151018620U, // BSEL_V - 0U, // BSEL_W_PSEUDO - 2281718609U, // BSETI_B - 2281720330U, // BSETI_D - 2281721984U, // BSETI_H - 2281725619U, // BSETI_W - 134235275U, // BSET_B - 134237385U, // BSET_D - 134238783U, // BSET_H - 134242762U, // BSET_W - 17797U, // BZ_B - 20217U, // BZ_D - 21357U, // BZ_H - 23698U, // BZ_V - 25457U, // BZ_W - 541278U, // B_MM_Pseudo - 402678723U, // BeqzRxImm16 - 25539U, // BeqzRxImmX16 - 1327710U, // Bimm16 - 541278U, // BimmX16 - 402678696U, // BnezRxImm16 - 25512U, // BnezRxImmX16 - 9368U, // Break16 - 1598417U, // Bteqz16 - 536893428U, // BteqzT8CmpX16 - 536892936U, // BteqzT8CmpiX16 - 536894397U, // BteqzT8SltX16 - 536892966U, // BteqzT8SltiX16 - 536894505U, // BteqzT8SltiuX16 - 536894541U, // BteqzT8SltuX16 - 549841U, // BteqzX16 - 1598390U, // Btnez16 - 671111156U, // BtnezT8CmpX16 - 671110664U, // BtnezT8CmpiX16 - 671112125U, // BtnezT8SltX16 - 671110694U, // BtnezT8SltiX16 - 671112233U, // BtnezT8SltiuX16 - 671112269U, // BtnezT8SltuX16 - 549814U, // BtnezX16 - 0U, // BuildPairF64 - 0U, // BuildPairF64_64 - 85859U, // CACHE - 85859U, // CACHE_MM - 85859U, // CACHE_R6 - 19003U, // CEIL_L_D64 - 23031U, // CEIL_L_S - 20179U, // CEIL_W_D32 - 20179U, // CEIL_W_D64 - 20179U, // CEIL_W_MM - 23353U, // CEIL_W_S - 23353U, // CEIL_W_S_MM - 134234890U, // CEQI_B - 134236627U, // CEQI_D - 134238281U, // CEQI_H - 134241916U, // CEQI_W - 134235044U, // CEQ_B - 134236930U, // CEQ_D - 134238472U, // CEQ_H - 134242192U, // CEQ_W - 16444U, // CFC1 - 16444U, // CFC1_MM - 16968U, // CFCMSA - 134243407U, // CINS - 134243363U, // CINS32 - 19639U, // CLASS_D - 23205U, // CLASS_S - 134235129U, // CLEI_S_B - 134237190U, // CLEI_S_D - 134238606U, // CLEI_S_H - 134242479U, // CLEI_S_W - 2281718992U, // CLEI_U_B - 2281721305U, // CLEI_U_D - 2281722542U, // CLEI_U_H - 2281726595U, // CLEI_U_W - 134235111U, // CLE_S_B - 134237172U, // CLE_S_D - 134238588U, // CLE_S_H - 134242461U, // CLE_S_W - 134235326U, // CLE_U_B - 134237639U, // CLE_U_D - 134238876U, // CLE_U_H - 134242929U, // CLE_U_W - 22452U, // CLO - 22452U, // CLO_MM - 22452U, // CLO_R6 - 134235149U, // CLTI_S_B - 134237210U, // CLTI_S_D - 134238626U, // CLTI_S_H - 134242499U, // CLTI_S_W - 2281719012U, // CLTI_U_B - 2281721325U, // CLTI_U_D - 2281722562U, // CLTI_U_H - 2281726615U, // CLTI_U_W - 134235217U, // CLT_S_B - 134237288U, // CLT_S_D - 134238714U, // CLT_S_H - 134242627U, // CLT_S_W - 134235444U, // CLT_U_B - 134237767U, // CLT_U_D - 134239004U, // CLT_U_H - 134243057U, // CLT_U_W - 25534U, // CLZ - 25534U, // CLZ_MM - 25534U, // CLZ_R6 - 134235667U, // CMPGDU_EQ_QB - 134235572U, // CMPGDU_LE_QB - 134235786U, // CMPGDU_LT_QB - 134235681U, // CMPGU_EQ_QB - 134235586U, // CMPGU_LE_QB - 134235800U, // CMPGU_LT_QB - 17966U, // CMPU_EQ_QB - 17871U, // CMPU_LE_QB - 18085U, // CMPU_LT_QB - 134236919U, // CMP_EQ_D - 21548U, // CMP_EQ_PH - 134240864U, // CMP_EQ_S - 134236489U, // CMP_F_D - 134240675U, // CMP_F_S - 134236333U, // CMP_LE_D - 21444U, // CMP_LE_PH - 134240596U, // CMP_LE_S - 134237410U, // CMP_LT_D - 21717U, // CMP_LT_PH - 134240959U, // CMP_LT_S - 134236507U, // CMP_SAF_D - 134240685U, // CMP_SAF_S - 134236946U, // CMP_SEQ_D - 134240883U, // CMP_SEQ_S - 134236370U, // CMP_SLE_D - 134240625U, // CMP_SLE_S - 134237437U, // CMP_SLT_D - 134240978U, // CMP_SLT_S - 134236994U, // CMP_SUEQ_D - 134240914U, // CMP_SUEQ_S - 134236418U, // CMP_SULE_D - 134240656U, // CMP_SULE_S - 134237485U, // CMP_SULT_D - 134241009U, // CMP_SULT_S - 134236876U, // CMP_SUN_D - 134240837U, // CMP_SUN_S - 134236974U, // CMP_UEQ_D - 134240903U, // CMP_UEQ_S - 134236398U, // CMP_ULE_D - 134240645U, // CMP_ULE_S - 134237465U, // CMP_ULT_D - 134240998U, // CMP_ULT_S - 134236858U, // CMP_UN_D - 134240827U, // CMP_UN_S - 9454U, // CONSTPOOL_ENTRY - 0U, // COPY_FD_PSEUDO - 0U, // COPY_FW_PSEUDO - 2952807544U, // COPY_S_B - 2952809637U, // COPY_S_D - 2952811052U, // COPY_S_H - 2952814987U, // COPY_S_W - 2952807759U, // COPY_U_B - 2952810104U, // COPY_U_D - 2952811319U, // COPY_U_H - 2952815394U, // COPY_U_W - 1867863U, // CTC1 - 1867863U, // CTC1_MM - 16976U, // CTCMSA - 22833U, // CVT_D32_S - 23896U, // CVT_D32_W - 23896U, // CVT_D32_W_MM - 22087U, // CVT_D64_L - 22833U, // CVT_D64_S - 23896U, // CVT_D64_W - 22833U, // CVT_D_S_MM - 19024U, // CVT_L_D64 - 19024U, // CVT_L_D64_MM - 23052U, // CVT_L_S - 23052U, // CVT_L_S_MM - 19362U, // CVT_S_D32 - 19362U, // CVT_S_D32_MM - 19362U, // CVT_S_D64 - 22096U, // CVT_S_L - 24651U, // CVT_S_W - 24651U, // CVT_S_W_MM - 20200U, // CVT_W_D32 - 20200U, // CVT_W_D64 - 20200U, // CVT_W_MM - 23374U, // CVT_W_S - 23374U, // CVT_W_S_MM - 19183U, // C_EQ_D32 - 19183U, // C_EQ_D64 - 23128U, // C_EQ_S - 18754U, // C_F_D32 - 18754U, // C_F_D64 - 22940U, // C_F_S - 18597U, // C_LE_D32 - 18597U, // C_LE_D64 - 22860U, // C_LE_S - 19674U, // C_LT_D32 - 19674U, // C_LT_D64 - 23223U, // C_LT_S - 18588U, // C_NGE_D32 - 18588U, // C_NGE_D64 - 22851U, // C_NGE_S - 18623U, // C_NGLE_D32 - 18623U, // C_NGLE_D64 - 22878U, // C_NGLE_S - 19040U, // C_NGL_D32 - 19040U, // C_NGL_D64 - 23068U, // C_NGL_S - 19665U, // C_NGT_D32 - 19665U, // C_NGT_D64 - 23214U, // C_NGT_S - 18633U, // C_OLE_D32 - 18633U, // C_OLE_D64 - 22888U, // C_OLE_S - 19700U, // C_OLT_D32 - 19700U, // C_OLT_D64 - 23241U, // C_OLT_S - 19209U, // C_SEQ_D32 - 19209U, // C_SEQ_D64 - 23146U, // C_SEQ_S - 18824U, // C_SF_D32 - 18824U, // C_SF_D64 - 22986U, // C_SF_S - 19237U, // C_UEQ_D32 - 19237U, // C_UEQ_D64 - 23166U, // C_UEQ_S - 18661U, // C_ULE_D32 - 18661U, // C_ULE_D64 - 22908U, // C_ULE_S - 19728U, // C_ULT_D32 - 19728U, // C_ULT_D64 - 23261U, // C_ULT_S - 19122U, // C_UN_D32 - 19122U, // C_UN_D64 - 23091U, // C_UN_S - 22516U, // CmpRxRy16 - 939546120U, // CmpiRxImm16 - 22024U, // CmpiRxImmX16 - 549945U, // Constant32 - 134237991U, // DADD - 134239684U, // DADDi - 134241306U, // DADDiu - 134241267U, // DADDu - 8689123U, // DAHI - 134240165U, // DALIGN - 8689184U, // DATI - 134239794U, // DAUI - 22476U, // DBITSWAP - 22451U, // DCLO - 22451U, // DCLO_R6 - 25533U, // DCLZ - 25533U, // DCLZ_R6 - 134241469U, // DDIV - 134241377U, // DDIVU - 9480U, // DERET - 9480U, // DERET_MM - 134243425U, // DEXT - 134243400U, // DEXTM - 134243438U, // DEXTU - 546247U, // DI - 134243413U, // DINS - 134243393U, // DINSM - 134243431U, // DINSU - 134241470U, // DIV - 134241378U, // DIVU - 134235238U, // DIV_S_B - 134237331U, // DIV_S_D - 134238735U, // DIV_S_H - 134242670U, // DIV_S_W - 134235453U, // DIV_U_B - 134237798U, // DIV_U_D - 134239013U, // DIV_U_H - 134243088U, // DIV_U_W - 546247U, // DI_MM - 134234690U, // DLSA - 134234690U, // DLSA_R6 - 134234121U, // DMFC0 - 16450U, // DMFC1 - 134234372U, // DMFC2 - 134238036U, // DMOD - 134241281U, // DMODU - 134234128U, // DMTC0 - 1867869U, // DMTC1 - 134234379U, // DMTC2 - 134239671U, // DMUH - 134241299U, // DMUHU - 134240103U, // DMUL - 23495U, // DMULT - 23641U, // DMULTu - 134241343U, // DMULU - 134240103U, // DMUL_R6 - 134237239U, // DOTP_S_D - 134238655U, // DOTP_S_H - 134242538U, // DOTP_S_W - 134237706U, // DOTP_U_D - 134238943U, // DOTP_U_H - 134242996U, // DOTP_U_W - 151014368U, // DPADD_S_D - 151015784U, // DPADD_S_H - 151019657U, // DPADD_S_W - 151014835U, // DPADD_U_D - 151016072U, // DPADD_U_H - 151020125U, // DPADD_U_W - 134239524U, // DPAQX_SA_W_PH - 134239607U, // DPAQX_S_W_PH - 134241998U, // DPAQ_SA_L_W - 134239566U, // DPAQ_S_W_PH - 134239859U, // DPAU_H_QBL - 134240355U, // DPAU_H_QBR - 134239645U, // DPAX_W_PH - 134239514U, // DPA_W_PH - 22521U, // DPOP - 134239539U, // DPSQX_SA_W_PH - 134239621U, // DPSQX_S_W_PH - 134242011U, // DPSQ_SA_L_W - 134239594U, // DPSQ_S_W_PH - 151014335U, // DPSUB_S_D - 151015763U, // DPSUB_S_H - 151019624U, // DPSUB_S_W - 151014802U, // DPSUB_U_D - 151016051U, // DPSUB_U_H - 151020092U, // DPSUB_U_W - 134239871U, // DPSU_H_QBL - 134240367U, // DPSU_H_QBR - 134239656U, // DPSX_W_PH - 134239635U, // DPS_W_PH - 134240512U, // DROTR - 134234351U, // DROTR32 - 134241513U, // DROTRV - 21370U, // DSBH - 25610U, // DSDIV - 20275U, // DSHD - 134240057U, // DSLL - 134234321U, // DSLL32 - 1073764153U, // DSLL64_32 - 134241475U, // DSLLV - 134234684U, // DSRA - 134234303U, // DSRA32 - 134241454U, // DSRAV - 134240069U, // DSRL - 134234329U, // DSRL32 - 134241482U, // DSRLV - 134235901U, // DSUB - 134241246U, // DSUBu - 25596U, // DUDIV - 25611U, // DivRxRy16 - 25597U, // DivuRxRy16 - 9438U, // EHB - 9438U, // EHB_MM - 546259U, // EI - 546259U, // EI_MM - 9481U, // ERET - 9481U, // ERET_MM - 134243426U, // EXT - 134240324U, // EXTP - 134240221U, // EXTPDP - 134241497U, // EXTPDPV - 134241506U, // EXTPV - 134242731U, // EXTRV_RS_W - 134242285U, // EXTRV_R_W - 134238744U, // EXTRV_S_H - 134243168U, // EXTRV_W - 134242720U, // EXTR_RS_W - 134242264U, // EXTR_R_W - 134238675U, // EXTR_S_H - 134242363U, // EXTR_W - 134243419U, // EXTS - 134243371U, // EXTS32 - 134243426U, // EXT_MM - 0U, // ExtractElementF64 - 0U, // ExtractElementF64_64 - 0U, // FABS_D - 19631U, // FABS_D32 - 19631U, // FABS_D64 - 19631U, // FABS_MM - 23198U, // FABS_S - 23198U, // FABS_S_MM - 0U, // FABS_W - 134236265U, // FADD_D - 134236266U, // FADD_D32 - 134236266U, // FADD_D64 - 134236266U, // FADD_MM - 134240572U, // FADD_S - 134240572U, // FADD_S_MM - 134241633U, // FADD_W - 134236499U, // FCAF_D - 134241752U, // FCAF_W - 134236929U, // FCEQ_D - 134242191U, // FCEQ_W - 19638U, // FCLASS_D - 25015U, // FCLASS_W - 134236343U, // FCLE_D - 134241675U, // FCLE_W - 134237420U, // FCLT_D - 134242770U, // FCLT_W - 2204821U, // FCMP_D32 - 2204821U, // FCMP_D32_MM - 2204821U, // FCMP_D64 - 2466965U, // FCMP_S32 - 2466965U, // FCMP_S32_MM - 134236439U, // FCNE_D - 134241709U, // FCNE_W - 134237039U, // FCOR_D - 134242320U, // FCOR_W - 134236985U, // FCUEQ_D - 134242207U, // FCUEQ_W - 134236409U, // FCULE_D - 134241691U, // FCULE_W - 134237476U, // FCULT_D - 134242786U, // FCULT_W - 134236455U, // FCUNE_D - 134241725U, // FCUNE_W - 134236868U, // FCUN_D - 134242097U, // FCUN_W - 134237862U, // FDIV_D - 134237863U, // FDIV_D32 - 134237863U, // FDIV_D64 - 134237863U, // FDIV_MM - 134241045U, // FDIV_S - 134241045U, // FDIV_S_MM - 134243152U, // FDIV_W - 134238402U, // FEXDO_H - 134242113U, // FEXDO_W - 134236152U, // FEXP2_D - 0U, // FEXP2_D_1_PSEUDO - 134241536U, // FEXP2_W - 0U, // FEXP2_W_1_PSEUDO - 19064U, // FEXUPL_D - 24311U, // FEXUPL_W - 19327U, // FEXUPR_D - 24608U, // FEXUPR_W - 19569U, // FFINT_S_D - 24908U, // FFINT_S_W - 20048U, // FFINT_U_D - 25338U, // FFINT_U_W - 19074U, // FFQL_D - 24321U, // FFQL_W - 19337U, // FFQR_D - 24618U, // FFQR_W - 17277U, // FILL_B - 19049U, // FILL_D - 0U, // FILL_FD_PSEUDO - 0U, // FILL_FW_PSEUDO - 20635U, // FILL_H - 24296U, // FILL_W - 18415U, // FLOG2_D - 23799U, // FLOG2_W - 19013U, // FLOOR_L_D64 - 23041U, // FLOOR_L_S - 20189U, // FLOOR_W_D32 - 20189U, // FLOOR_W_D64 - 20189U, // FLOOR_W_MM - 23363U, // FLOOR_W_S - 23363U, // FLOOR_W_S_MM - 151013489U, // FMADD_D - 151018857U, // FMADD_W - 134236190U, // FMAX_A_D - 134241574U, // FMAX_A_W - 134237937U, // FMAX_D - 134243177U, // FMAX_W - 134236170U, // FMIN_A_D - 134241554U, // FMIN_A_W - 134236842U, // FMIN_D - 134242089U, // FMIN_W - 20150U, // FMOV_D32 - 20150U, // FMOV_D32_MM - 20150U, // FMOV_D64 - 23324U, // FMOV_S - 23324U, // FMOV_S_MM - 151013447U, // FMSUB_D - 151018815U, // FMSUB_W - 134236826U, // FMUL_D - 134236827U, // FMUL_D32 - 134236827U, // FMUL_D64 - 134236827U, // FMUL_MM - 134240805U, // FMUL_S - 134240805U, // FMUL_S_MM - 134242073U, // FMUL_W - 18841U, // FNEG_D32 - 18841U, // FNEG_D64 - 18841U, // FNEG_MM - 23002U, // FNEG_S - 23002U, // FNEG_S_MM - 19175U, // FRCP_D - 24394U, // FRCP_W - 19786U, // FRINT_D - 25084U, // FRINT_W - 19814U, // FRSQRT_D - 25112U, // FRSQRT_W - 134236518U, // FSAF_D - 134241760U, // FSAF_W - 134236957U, // FSEQ_D - 134242199U, // FSEQ_W - 134236381U, // FSLE_D - 134241683U, // FSLE_W - 134237448U, // FSLT_D - 134242778U, // FSLT_W - 134236447U, // FSNE_D - 134241717U, // FSNE_W - 134237047U, // FSOR_D - 134242328U, // FSOR_W - 19805U, // FSQRT_D - 19806U, // FSQRT_D32 - 19806U, // FSQRT_D64 - 19806U, // FSQRT_MM - 23301U, // FSQRT_S - 23301U, // FSQRT_S_MM - 25103U, // FSQRT_W - 134236223U, // FSUB_D - 134236224U, // FSUB_D32 - 134236224U, // FSUB_D64 - 134236224U, // FSUB_MM - 134240554U, // FSUB_S - 134240554U, // FSUB_S_MM - 134241591U, // FSUB_W - 134237006U, // FSUEQ_D - 134242216U, // FSUEQ_W - 134236430U, // FSULE_D - 134241700U, // FSULE_W - 134237497U, // FSULT_D - 134242795U, // FSULT_W - 134236464U, // FSUNE_D - 134241734U, // FSUNE_W - 134236887U, // FSUN_D - 134242105U, // FSUN_W - 19580U, // FTINT_S_D - 24919U, // FTINT_S_W - 20059U, // FTINT_U_D - 25349U, // FTINT_U_W - 134238479U, // FTQ_H - 134242225U, // FTQ_W - 19402U, // FTRUNC_S_D - 24691U, // FTRUNC_S_W - 19869U, // FTRUNC_U_D - 25159U, // FTRUNC_U_W - 1224758783U, // GotPrologue16 - 134237142U, // HADD_S_D - 134238558U, // HADD_S_H - 134242431U, // HADD_S_W - 134237609U, // HADD_U_D - 134238846U, // HADD_U_H - 134242899U, // HADD_U_W - 134237109U, // HSUB_S_D - 134238537U, // HSUB_S_H - 134242398U, // HSUB_S_W - 134237576U, // HSUB_U_D - 134238825U, // HSUB_U_H - 134242866U, // HSUB_U_W - 134235508U, // ILVEV_B - 134237853U, // ILVEV_D - 134239068U, // ILVEV_H - 134243143U, // ILVEV_W - 134235036U, // ILVL_B - 134236834U, // ILVL_D - 134238394U, // ILVL_H - 134242081U, // ILVL_W - 134234788U, // ILVOD_B - 134236307U, // ILVOD_D - 134238196U, // ILVOD_H - 134241666U, // ILVOD_W - 134235084U, // ILVR_B - 134237082U, // ILVR_D - 134238519U, // ILVR_H - 134242371U, // ILVR_W - 134243408U, // INS - 44582043U, // INSERT_B - 0U, // INSERT_B_VIDX_PSEUDO - 44584275U, // INSERT_D - 0U, // INSERT_D_VIDX_PSEUDO - 0U, // INSERT_FD_PSEUDO - 0U, // INSERT_FD_VIDX_PSEUDO - 0U, // INSERT_FW_PSEUDO - 0U, // INSERT_FW_VIDX_PSEUDO - 44585551U, // INSERT_H - 0U, // INSERT_H_VIDX_PSEUDO - 44589573U, // INSERT_W - 0U, // INSERT_W_VIDX_PSEUDO - 16801009U, // INSV - 52970157U, // INSVE_B - 52971833U, // INSVE_D - 52973565U, // INSVE_H - 52977103U, // INSVE_W - 134243408U, // INS_MM - 546365U, // J - 546398U, // JAL - 22768U, // JALR - 547056U, // JALR16_MM - 22768U, // JALR64 - 0U, // JALR64Pseudo - 0U, // JALRPseudo - 541104U, // JALRS16_MM - 23442U, // JALRS_MM - 17822U, // JALR_HB - 22768U, // JALR_MM - 547706U, // JALS_MM - 549771U, // JALX - 549771U, // JALX_MM - 546398U, // JAL_MM - 18212U, // JIALC - 18201U, // JIC - 547052U, // JR - 541091U, // JR16_MM - 547052U, // JR64 - 546873U, // JRADDIUSP - 542610U, // JRC16_MM - 542103U, // JR_HB - 542103U, // JR_HB_R6 - 547052U, // JR_MM - 546365U, // J_MM - 2905694U, // Jal16 - 3167838U, // JalB16 - 546398U, // JalOneReg - 22110U, // JalTwoReg - 9430U, // JrRa16 - 9421U, // JrcRa16 - 549872U, // JrcRx16 - 540673U, // JumpLinkReg16 - 58738087U, // LB - 58738087U, // LB64 - 58737088U, // LBU16_MM - 1358979985U, // LBUX - 58738087U, // LB_MM - 58743769U, // LBu - 58743769U, // LBu64 - 58743769U, // LBu_MM - 58740538U, // LD - 58736688U, // LDC1 - 58736688U, // LDC164 - 58736688U, // LDC1_MM - 58736888U, // LDC2 - 58736888U, // LDC2_R6 - 58736947U, // LDC3 - 17103U, // LDI_B - 18857U, // LDI_D - 20511U, // LDI_H - 24146U, // LDI_W - 58742458U, // LDL - 18273U, // LDPC - 58742954U, // LDR - 1358970992U, // LDXC1 - 1358970992U, // LDXC164 - 58737301U, // LD_B - 58738820U, // LD_D - 58740709U, // LD_H - 58744179U, // LD_W - 25189403U, // LEA_ADDiu - 25189402U, // LEA_ADDiu64 - 25189403U, // LEA_ADDiu_MM - 58741643U, // LH - 58741643U, // LH64 - 58737111U, // LHU16_MM - 1358979974U, // LHX - 58741643U, // LH_MM - 58743822U, // LHu - 58743822U, // LHu64 - 58743822U, // LHu_MM - 16751U, // LI16_MM - 58742563U, // LL - 58740537U, // LLD - 58740537U, // LLD_R6 - 58742563U, // LL_MM - 58742563U, // LL_R6 - 58736647U, // LOAD_ACC128 - 58736647U, // LOAD_ACC64 - 58736647U, // LOAD_ACC64DSP - 58742794U, // LOAD_CCOND_DSP - 0U, // LONG_BRANCH_ADDiu - 0U, // LONG_BRANCH_DADDiu - 0U, // LONG_BRANCH_LUi - 134234691U, // LSA - 134234691U, // LSA_R6 - 1358971006U, // LUXC1 - 1358971006U, // LUXC164 - 1358971006U, // LUXC1_MM - 33576504U, // LUi - 33576504U, // LUi64 - 33576504U, // LUi_MM - 58745726U, // LW - 58737118U, // LW16_MM - 58745726U, // LW64 - 58736740U, // LWC1 - 58736740U, // LWC1_MM - 58736914U, // LWC2 - 58736914U, // LWC2_R6 - 58736959U, // LWC3 - 58745726U, // LWGP_MM - 58742637U, // LWL - 58742637U, // LWL64 - 58742637U, // LWL_MM - 3522956U, // LWM16_MM - 3522785U, // LWM32_MM - 3528595U, // LWM_MM - 18310U, // LWPC - 137290U, // LWP_MM - 58743054U, // LWR - 58743054U, // LWR64 - 58743054U, // LWR_MM - 58745726U, // LWSP_MM - 18303U, // LWUPC - 58743912U, // LWU_MM - 1358979991U, // LWX - 1358971020U, // LWXC1 - 1358971020U, // LWXC1_MM - 1358977945U, // LWXS_MM - 58745726U, // LW_MM - 58743912U, // LWu - 58738087U, // LbRxRyOffMemX16 - 58743769U, // LbuRxRyOffMemX16 - 58741643U, // LhRxRyOffMemX16 - 58743822U, // LhuRxRyOffMemX16 - 939546111U, // LiRxImm16 - 22005U, // LiRxImmAlignX16 - 22015U, // LiRxImmX16 - 33571334U, // LoadAddr32Imm - 58737158U, // LoadAddr32Reg - 33576447U, // LoadImm32Reg - 22019U, // LoadImm64Reg - 3695486U, // LwConstant32 - 268460926U, // LwRxPcTcp16 - 25470U, // LwRxPcTcpX16 - 58745726U, // LwRxRyOffMemX16 - 1493197694U, // LwRxSpImmX16 - 20269U, // MADD - 151013751U, // MADDF_D - 151017921U, // MADDF_S - 151015667U, // MADDR_Q_H - 151019386U, // MADDR_Q_W - 23546U, // MADDU - 134241274U, // MADDU_DSP - 23546U, // MADDU_MM - 151012706U, // MADDV_B - 151015051U, // MADDV_D - 151016266U, // MADDV_H - 151020341U, // MADDV_W - 134236274U, // MADD_D32 - 134236274U, // MADD_D32_MM - 134236274U, // MADD_D64 - 134237997U, // MADD_DSP - 20269U, // MADD_MM - 151015637U, // MADD_Q_H - 151019356U, // MADD_Q_W - 134240571U, // MADD_S - 134240571U, // MADD_S_MM - 134239974U, // MAQ_SA_W_PHL - 134240436U, // MAQ_SA_W_PHR - 134240002U, // MAQ_S_W_PHL - 134240464U, // MAQ_S_W_PHR - 134236215U, // MAXA_D - 134240544U, // MAXA_S - 134235159U, // MAXI_S_B - 134237220U, // MAXI_S_D - 134238636U, // MAXI_S_H - 134242509U, // MAXI_S_W - 2281719022U, // MAXI_U_B - 2281721335U, // MAXI_U_D - 2281722572U, // MAXI_U_H - 2281726625U, // MAXI_U_W - 134234740U, // MAX_A_B - 134236191U, // MAX_A_D - 134238148U, // MAX_A_H - 134241575U, // MAX_A_W - 134237938U, // MAX_D - 134241111U, // MAX_S - 134235247U, // MAX_S_B - 134237340U, // MAX_S_D - 134238755U, // MAX_S_H - 134242690U, // MAX_S_W - 134235462U, // MAX_U_B - 134237807U, // MAX_U_D - 134239022U, // MAX_U_H - 134243097U, // MAX_U_W - 134234122U, // MFC0 - 16451U, // MFC1 - 16451U, // MFC1_MM - 134234373U, // MFC2 - 16457U, // MFHC1_D32 - 16457U, // MFHC1_D64 - 16457U, // MFHC1_MM - 546281U, // MFHI - 546281U, // MFHI16_MM - 546281U, // MFHI64 - 21993U, // MFHI_DSP - 546281U, // MFHI_MM - 546745U, // MFLO - 546745U, // MFLO16_MM - 546745U, // MFLO64 - 22457U, // MFLO_DSP - 546745U, // MFLO_MM - 134236200U, // MINA_D - 134240536U, // MINA_S - 134235139U, // MINI_S_B - 134237200U, // MINI_S_D - 134238616U, // MINI_S_H - 134242489U, // MINI_S_W - 2281719002U, // MINI_U_B - 2281721315U, // MINI_U_D - 2281722552U, // MINI_U_H - 2281726605U, // MINI_U_W - 134234721U, // MIN_A_B - 134236171U, // MIN_A_D - 134238129U, // MIN_A_H - 134241555U, // MIN_A_W - 134236843U, // MIN_D - 134240812U, // MIN_S - 134235169U, // MIN_S_B - 134237230U, // MIN_S_D - 134238646U, // MIN_S_H - 134242529U, // MIN_S_W - 134235384U, // MIN_U_B - 134237697U, // MIN_U_D - 134238934U, // MIN_U_H - 134242987U, // MIN_U_W - 0U, // MIPSeh_return32 - 0U, // MIPSeh_return64 - 134238037U, // MOD - 134235899U, // MODSUB - 134241282U, // MODU - 134235102U, // MOD_S_B - 134237163U, // MOD_S_D - 134238579U, // MOD_S_H - 134242452U, // MOD_S_W - 134235317U, // MOD_U_B - 134237630U, // MOD_U_D - 134238867U, // MOD_U_H - 134242920U, // MOD_U_W - 20345U, // MOVE16_MM - 67491813U, // MOVEP_MM - 23668U, // MOVE_V - 134236560U, // MOVF_D32 - 134236560U, // MOVF_D32_MM - 134236560U, // MOVF_D64 - 134238109U, // MOVF_I - 134238109U, // MOVF_I64 - 134238109U, // MOVF_I_MM - 134240722U, // MOVF_S - 134240722U, // MOVF_S_MM - 134236895U, // MOVN_I64_D64 - 134240173U, // MOVN_I64_I - 134240173U, // MOVN_I64_I64 - 134240848U, // MOVN_I64_S - 134236895U, // MOVN_I_D32 - 134236895U, // MOVN_I_D32_MM - 134236895U, // MOVN_I_D64 - 134240173U, // MOVN_I_I - 134240173U, // MOVN_I_I64 - 134240173U, // MOVN_I_MM - 134240848U, // MOVN_I_S - 134240848U, // MOVN_I_S_MM - 134237558U, // MOVT_D32 - 134237558U, // MOVT_D32_MM - 134237558U, // MOVT_D64 - 134241235U, // MOVT_I - 134241235U, // MOVT_I64 - 134241235U, // MOVT_I_MM - 134241037U, // MOVT_S - 134241037U, // MOVT_S_MM - 134237978U, // MOVZ_I64_D64 - 134243300U, // MOVZ_I64_I - 134243300U, // MOVZ_I64_I64 - 134241138U, // MOVZ_I64_S - 134237978U, // MOVZ_I_D32 - 134237978U, // MOVZ_I_D32_MM - 134237978U, // MOVZ_I_D64 - 134243300U, // MOVZ_I_I - 134243300U, // MOVZ_I_I64 - 134243300U, // MOVZ_I_MM - 134241138U, // MOVZ_I_S - 134241138U, // MOVZ_I_S_MM - 18179U, // MSUB - 151013742U, // MSUBF_D - 151017912U, // MSUBF_S - 151015656U, // MSUBR_Q_H - 151019375U, // MSUBR_Q_W - 23525U, // MSUBU - 134241253U, // MSUBU_DSP - 23525U, // MSUBU_MM - 151012697U, // MSUBV_B - 151015042U, // MSUBV_D - 151016257U, // MSUBV_H - 151020332U, // MSUBV_W - 134236232U, // MSUB_D32 - 134236232U, // MSUB_D32_MM - 134236232U, // MSUB_D64 - 134235907U, // MSUB_DSP - 18179U, // MSUB_MM - 151015627U, // MSUB_Q_H - 151019346U, // MSUB_Q_W - 134240553U, // MSUB_S - 134240553U, // MSUB_S_MM - 134234129U, // MTC0 - 1867870U, // MTC1 - 1867870U, // MTC1_MM - 134234380U, // MTC2 - 1884240U, // MTHC1_D32 - 1884240U, // MTHC1_D64 - 1884240U, // MTHC1_MM - 546287U, // MTHI - 546287U, // MTHI64 - 1873391U, // MTHI_DSP - 546287U, // MTHI_MM - 1873900U, // MTHLIP - 546758U, // MTLO - 546758U, // MTLO64 - 1873862U, // MTLO_DSP - 546758U, // MTLO_MM - 540701U, // MTM0 - 540826U, // MTM1 - 540958U, // MTM2 - 540707U, // MTP0 - 540832U, // MTP1 - 540964U, // MTP2 - 134239672U, // MUH - 134241300U, // MUHU - 134240104U, // MUL - 134240015U, // MULEQ_S_W_PHL - 134240477U, // MULEQ_S_W_PHR - 134239883U, // MULEU_S_PH_QBL - 134240379U, // MULEU_S_PH_QBR - 134239433U, // MULQ_RS_PH - 134242709U, // MULQ_RS_W - 134239377U, // MULQ_S_PH - 134242568U, // MULQ_S_W - 134238462U, // MULR_Q_H - 134242181U, // MULR_Q_W - 134239579U, // MULSAQ_S_W_PH - 134239554U, // MULSA_W_PH - 23496U, // MULT - 134241370U, // MULTU_DSP - 134241224U, // MULT_DSP - 23496U, // MULT_MM - 23642U, // MULTu - 23642U, // MULTu_MM - 134241337U, // MULU - 134235517U, // MULV_B - 134237870U, // MULV_D - 134239077U, // MULV_H - 134243160U, // MULV_W - 134240104U, // MUL_MM - 134239250U, // MUL_PH - 134238431U, // MUL_Q_H - 134242150U, // MUL_Q_W - 134240104U, // MUL_R6 - 134239345U, // MUL_S_PH - 546281U, // Mfhi16 - 546745U, // Mflo16 - 20345U, // Move32R16 - 20345U, // MoveR3216 - 23496U, // MultRxRy16 - 75799496U, // MultRxRyRz16 - 23642U, // MultuRxRy16 - 75799642U, // MultuRxRyRz16 - 17028U, // NLOC_B - 18521U, // NLOC_D - 20436U, // NLOC_H - 23880U, // NLOC_W - 17036U, // NLZC_B - 18529U, // NLZC_D - 20444U, // NLZC_H - 23888U, // NLZC_W - 134236282U, // NMADD_D32 - 134236282U, // NMADD_D32_MM - 134236282U, // NMADD_D64 - 134240570U, // NMADD_S - 134240570U, // NMADD_S_MM - 134236240U, // NMSUB_D32 - 134236240U, // NMSUB_D32_MM - 134236240U, // NMSUB_D64 - 134240552U, // NMSUB_S - 134240552U, // NMSUB_S_MM - 0U, // NOP - 134240502U, // NOR - 134240502U, // NOR64 - 2281718573U, // NORI_B - 134240502U, // NOR_MM - 134241412U, // NOR_V - 0U, // NOR_V_D_PSEUDO - 0U, // NOR_V_H_PSEUDO - 0U, // NOR_V_W_PSEUDO - 16825U, // NOT16_MM - 20387U, // NegRxRy16 - 23502U, // NotRxRy16 - 134240503U, // OR - 836010U, // OR16_MM - 134240503U, // OR64 - 2281718574U, // ORI_B - 134240503U, // OR_MM - 134241413U, // OR_V - 0U, // OR_V_D_PSEUDO - 0U, // OR_V_H_PSEUDO - 0U, // OR_V_W_PSEUDO - 134239771U, // ORi - 134239771U, // ORi64 - 134239771U, // ORi_MM - 16799991U, // OrRxRxRy16 - 134239239U, // PACKRL_PH - 9442U, // PAUSE - 9442U, // PAUSE_MM - 134235499U, // PCKEV_B - 134237844U, // PCKEV_D - 134239059U, // PCKEV_H - 134243134U, // PCKEV_W - 134234779U, // PCKOD_B - 134236298U, // PCKOD_D - 134238187U, // PCKOD_H - 134241657U, // PCKOD_W - 17555U, // PCNT_B - 19778U, // PCNT_D - 21063U, // PCNT_H - 25076U, // PCNT_W - 134239203U, // PICK_PH - 134235631U, // PICK_QB - 22522U, // POP - 22186U, // PRECEQU_PH_QBL - 16906U, // PRECEQU_PH_QBLA - 22682U, // PRECEQU_PH_QBR - 16939U, // PRECEQU_PH_QBRA - 22260U, // PRECEQ_W_PHL - 22722U, // PRECEQ_W_PHR - 22171U, // PRECEU_PH_QBL - 16890U, // PRECEU_PH_QBLA - 22667U, // PRECEU_PH_QBR - 16923U, // PRECEU_PH_QBRA - 134239155U, // PRECRQU_S_QB_PH - 134241800U, // PRECRQ_PH_W - 134239128U, // PRECRQ_QB_PH - 134241831U, // PRECRQ_RS_PH_W - 134239142U, // PRECR_QB_PH - 134241784U, // PRECR_SRA_PH_W - 134241813U, // PRECR_SRA_R_PH_W - 85911U, // PREF - 85911U, // PREF_MM - 85911U, // PREF_R6 - 134238019U, // PREPEND - 0U, // PseudoCMPU_EQ_QB - 0U, // PseudoCMPU_LE_QB - 0U, // PseudoCMPU_LT_QB - 0U, // PseudoCMP_EQ_PH - 0U, // PseudoCMP_LE_PH - 0U, // PseudoCMP_LT_PH - 16391U, // PseudoCVT_D32_W - 16391U, // PseudoCVT_D64_L - 16391U, // PseudoCVT_D64_W - 16391U, // PseudoCVT_S_L - 16391U, // PseudoCVT_S_W - 0U, // PseudoDMULT - 0U, // PseudoDMULTu - 0U, // PseudoDSDIV - 0U, // PseudoDUDIV - 0U, // PseudoIndirectBranch - 0U, // PseudoIndirectBranch64 - 0U, // PseudoMADD - 0U, // PseudoMADDU - 0U, // PseudoMFHI - 0U, // PseudoMFHI64 - 0U, // PseudoMFLO - 0U, // PseudoMFLO64 - 0U, // PseudoMSUB - 0U, // PseudoMSUBU - 0U, // PseudoMTLOHI - 0U, // PseudoMTLOHI64 - 0U, // PseudoMTLOHI_DSP - 0U, // PseudoMULT - 0U, // PseudoMULTu - 0U, // PseudoPICK_PH - 0U, // PseudoPICK_QB - 0U, // PseudoReturn - 0U, // PseudoReturn64 - 0U, // PseudoSDIV - 0U, // PseudoSELECTFP_F_D32 - 0U, // PseudoSELECTFP_F_D64 - 0U, // PseudoSELECTFP_F_I - 0U, // PseudoSELECTFP_F_I64 - 0U, // PseudoSELECTFP_F_S - 0U, // PseudoSELECTFP_T_D32 - 0U, // PseudoSELECTFP_T_D64 - 0U, // PseudoSELECTFP_T_I - 0U, // PseudoSELECTFP_T_I64 - 0U, // PseudoSELECTFP_T_S - 0U, // PseudoSELECT_D32 - 0U, // PseudoSELECT_D64 - 0U, // PseudoSELECT_I - 0U, // PseudoSELECT_I64 - 0U, // PseudoSELECT_S - 0U, // PseudoUDIV - 18155U, // RADDU_W_QB - 33577003U, // RDDSP - 22791U, // RDHWR - 22791U, // RDHWR64 - 22791U, // RDHWR_MM - 21766U, // REPLV_PH - 18135U, // REPLV_QB - 33575925U, // REPL_PH - 33572353U, // REPL_QB - 19787U, // RINT_D - 23293U, // RINT_S - 134240513U, // ROTR - 134241514U, // ROTRV - 134241514U, // ROTRV_MM - 134240513U, // ROTR_MM - 18992U, // ROUND_L_D64 - 23020U, // ROUND_L_S - 20168U, // ROUND_W_D32 - 20168U, // ROUND_W_D64 - 20168U, // ROUND_W_MM - 23342U, // ROUND_W_S - 23342U, // ROUND_W_S_MM - 0U, // Restore16 - 0U, // RestoreX16 - 0U, // RetRA - 0U, // RetRA16 - 134235208U, // SAT_S_B - 134237279U, // SAT_S_D - 2281722353U, // SAT_S_H - 134242618U, // SAT_S_W - 134235435U, // SAT_U_B - 134237758U, // SAT_U_D - 2281722643U, // SAT_U_H - 134243048U, // SAT_U_W - 58738423U, // SB - 58736980U, // SB16_MM - 58738423U, // SB64 - 58738423U, // SB_MM - 3966874U, // SC - 3968802U, // SCD - 3968802U, // SCD_R6 - 3966874U, // SC_MM - 3966874U, // SC_R6 - 58740570U, // SD - 546774U, // SDBBP - 65946U, // SDBBP16_MM - 546774U, // SDBBP_MM - 546774U, // SDBBP_R6 - 58736694U, // SDC1 - 58736694U, // SDC164 - 58736694U, // SDC1_MM - 58736894U, // SDC2 - 58736894U, // SDC2_R6 - 58736953U, // SDC3 - 25611U, // SDIV - 25611U, // SDIV_MM - 58742463U, // SDL - 58742959U, // SDR - 1358970999U, // SDXC1 - 1358970999U, // SDXC164 - 17810U, // SEB - 17810U, // SEB64 - 17810U, // SEB_MM - 21382U, // SEH - 21382U, // SEH64 - 21382U, // SEH_MM - 134243273U, // SELEQZ - 134243273U, // SELEQZ64 - 134237968U, // SELEQZ_D - 134241128U, // SELEQZ_S - 134243246U, // SELNEZ - 134243246U, // SELNEZ64 - 134237951U, // SELNEZ_D - 134241118U, // SELNEZ_S - 151013977U, // SEL_D - 151018005U, // SEL_S - 134240345U, // SEQ - 134239758U, // SEQi - 58742195U, // SH - 58736993U, // SH16_MM - 58742195U, // SH64 - 2281718455U, // SHF_B - 2281721863U, // SHF_H - 2281725417U, // SHF_W - 22463U, // SHILO - 23761U, // SHILOV - 134239484U, // SHLLV_PH - 134235853U, // SHLLV_QB - 134239421U, // SHLLV_S_PH - 134242679U, // SHLLV_S_W - 134239212U, // SHLL_PH - 134235640U, // SHLL_QB - 134239334U, // SHLL_S_PH - 134242519U, // SHLL_S_W - 134239474U, // SHRAV_PH - 134235843U, // SHRAV_QB - 134239322U, // SHRAV_R_PH - 134235741U, // SHRAV_R_QB - 134242274U, // SHRAV_R_W - 134239119U, // SHRA_PH - 134235563U, // SHRA_QB - 134239287U, // SHRA_R_PH - 134235706U, // SHRA_R_QB - 134242232U, // SHRA_R_W - 134239504U, // SHRLV_PH - 134235873U, // SHRLV_QB - 134239230U, // SHRL_PH - 134235658U, // SHRL_QB - 58742195U, // SH_MM - 2969584334U, // SLDI_B - 2969586088U, // SLDI_D - 2969587742U, // SLDI_H - 2969591377U, // SLDI_W - 822100628U, // SLD_B - 822102147U, // SLD_D - 822104036U, // SLD_H - 822107506U, // SLD_W - 134240058U, // SLL - 134234494U, // SLL16_MM - 1610635066U, // SLL64_32 - 1610635066U, // SLL64_64 - 2281718512U, // SLLI_B - 2281720249U, // SLLI_D - 2281721903U, // SLLI_H - 2281725538U, // SLLI_W - 134241476U, // SLLV - 134241476U, // SLLV_MM - 134235013U, // SLL_B - 134236785U, // SLL_D - 134238371U, // SLL_H - 134240058U, // SLL_MM - 134242032U, // SLL_W - 134241213U, // SLT - 134241213U, // SLT64 - 134241213U, // SLT_MM - 134239782U, // SLTi - 134239782U, // SLTi64 - 134239782U, // SLTi_MM - 134241321U, // SLTiu - 134241321U, // SLTiu64 - 134241321U, // SLTiu_MM - 134241357U, // SLTu - 134241357U, // SLTu64 - 134241357U, // SLTu_MM - 134238063U, // SNE - 134239703U, // SNEi - 0U, // SNZ_B_PSEUDO - 0U, // SNZ_D_PSEUDO - 0U, // SNZ_H_PSEUDO - 0U, // SNZ_V_PSEUDO - 0U, // SNZ_W_PSEUDO - 2952807239U, // SPLATI_B - 2952808960U, // SPLATI_D - 2952810614U, // SPLATI_H - 2952814249U, // SPLATI_W - 805323906U, // SPLAT_B - 805326016U, // SPLAT_D - 805327414U, // SPLAT_H - 805331393U, // SPLAT_W - 134234685U, // SRA - 2281718470U, // SRAI_B - 2281720224U, // SRAI_D - 2281721878U, // SRAI_H - 2281725513U, // SRAI_W - 134234898U, // SRARI_B - 134236635U, // SRARI_D - 2281721937U, // SRARI_H - 134241924U, // SRARI_W - 134235051U, // SRAR_B - 134237015U, // SRAR_D - 134238486U, // SRAR_H - 134242296U, // SRAR_W - 134241455U, // SRAV - 134241455U, // SRAV_MM - 134234749U, // SRA_B - 134236208U, // SRA_D - 134238157U, // SRA_H - 134234685U, // SRA_MM - 134241584U, // SRA_W - 134240070U, // SRL - 134234501U, // SRL16_MM - 2281718520U, // SRLI_B - 2281720257U, // SRLI_D - 2281721911U, // SRLI_H - 2281725546U, // SRLI_W - 134234916U, // SRLRI_B - 134236653U, // SRLRI_D - 2281721955U, // SRLRI_H - 134241942U, // SRLRI_W - 134235067U, // SRLR_B - 134237031U, // SRLR_D - 134238502U, // SRLR_H - 134242312U, // SRLR_W - 134241483U, // SRLV - 134241483U, // SRLV_MM - 134235020U, // SRL_B - 134236810U, // SRL_D - 134238378U, // SRL_H - 134240070U, // SRL_MM - 134242057U, // SRL_W - 9463U, // SSNOP - 9463U, // SSNOP_MM - 58736647U, // STORE_ACC128 - 58736647U, // STORE_ACC64 - 58736647U, // STORE_ACC64DSP - 58742810U, // STORE_CCOND_DSP - 58737829U, // ST_B - 58740080U, // ST_D - 58741337U, // ST_H - 58745378U, // ST_W - 134235902U, // SUB - 134239183U, // SUBQH_PH - 134239298U, // SUBQH_R_PH - 134242242U, // SUBQH_R_W - 134241847U, // SUBQH_W - 134239258U, // SUBQ_PH - 134239355U, // SUBQ_S_PH - 134242548U, // SUBQ_S_W - 134235423U, // SUBSUS_U_B - 134237746U, // SUBSUS_U_D - 134238983U, // SUBSUS_U_H - 134243036U, // SUBSUS_U_W - 134235226U, // SUBSUU_S_B - 134237319U, // SUBSUU_S_D - 134238723U, // SUBSUU_S_H - 134242658U, // SUBSUU_S_W - 134235188U, // SUBS_S_B - 134237259U, // SUBS_S_D - 134238685U, // SUBS_S_H - 134242598U, // SUBS_S_W - 134235403U, // SUBS_U_B - 134237726U, // SUBS_U_D - 134238963U, // SUBS_U_H - 134243016U, // SUBS_U_W - 134234567U, // SUBU16_MM - 134235611U, // SUBUH_QB - 134235717U, // SUBUH_R_QB - 134239456U, // SUBU_PH - 134235825U, // SUBU_QB - 134239399U, // SUBU_S_PH - 134235764U, // SUBU_S_QB - 2281718618U, // SUBVI_B - 2281720339U, // SUBVI_D - 2281721993U, // SUBVI_H - 2281725628U, // SUBVI_W - 134235482U, // SUBV_B - 134237827U, // SUBV_D - 134239042U, // SUBV_H - 134243117U, // SUBV_W - 134235902U, // SUB_MM - 134241247U, // SUBu - 134241247U, // SUBu_MM - 1358971013U, // SUXC1 - 1358971013U, // SUXC164 - 1358971013U, // SUXC1_MM - 58745730U, // SW - 58737124U, // SW16_MM - 58745730U, // SW64 - 58736746U, // SWC1 - 58736746U, // SWC1_MM - 58736920U, // SWC2 - 58736920U, // SWC2_R6 - 58736965U, // SWC3 - 58742642U, // SWL - 58742642U, // SWL64 - 58742642U, // SWL_MM - 3522963U, // SWM16_MM - 3522792U, // SWM32_MM - 3528600U, // SWM_MM - 137295U, // SWP_MM - 58743059U, // SWR - 58743059U, // SWR64 - 58743059U, // SWR_MM - 58745730U, // SWSP_MM - 1358971027U, // SWXC1 - 1358971027U, // SWXC1_MM - 58745730U, // SW_MM - 549939U, // SYNC - 153021U, // SYNCI - 549939U, // SYNC_MM - 546590U, // SYSCALL - 546590U, // SYSCALL_MM - 0U, // SZ_B_PSEUDO - 0U, // SZ_D_PSEUDO - 0U, // SZ_H_PSEUDO - 0U, // SZ_V_PSEUDO - 0U, // SZ_W_PSEUDO - 0U, // Save16 - 0U, // SaveX16 - 58738423U, // SbRxRyOffMemX16 - 549866U, // SebRx16 - 549878U, // SehRx16 - 4367299U, // SelBeqZ - 4367272U, // SelBneZ - 1828886516U, // SelTBteqZCmp - 1828886024U, // SelTBteqZCmpi - 1828887485U, // SelTBteqZSlt - 1828886054U, // SelTBteqZSlti - 1828887593U, // SelTBteqZSltiu - 1828887629U, // SelTBteqZSltu - 1963104244U, // SelTBtneZCmp - 1963103752U, // SelTBtneZCmpi - 1963105213U, // SelTBtneZSlt - 1963103782U, // SelTBtneZSlti - 1963105321U, // SelTBtneZSltiu - 1963105357U, // SelTBtneZSltu - 58742195U, // ShRxRyOffMemX16 - 134240058U, // SllX16 - 16800964U, // SllvRxRy16 - 92576701U, // SltCCRxRy16 - 23485U, // SltRxRy16 - 92575270U, // SltiCCRxImmX16 - 939546150U, // SltiRxImm16 - 22054U, // SltiRxImmX16 - 92576809U, // SltiuCCRxImmX16 - 939547689U, // SltiuRxImm16 - 23593U, // SltiuRxImmX16 - 92576845U, // SltuCCRxRy16 - 23629U, // SltuRxRy16 - 92576845U, // SltuRxRyRz16 - 134234685U, // SraX16 - 16800943U, // SravRxRy16 - 134240070U, // SrlX16 - 16800971U, // SrlvRxRy16 - 134241247U, // SubuRxRyRz16 - 58745730U, // SwRxRyOffMemX16 - 1493197698U, // SwRxSpImmX16 - 0U, // TAILCALL - 0U, // TAILCALL64_R - 0U, // TAILCALL_R - 134240350U, // TEQ - 33576468U, // TEQI - 33576468U, // TEQI_MM - 134240350U, // TEQ_MM - 134238046U, // TGE - 33576401U, // TGEI - 33578018U, // TGEIU - 33578018U, // TGEIU_MM - 33576401U, // TGEI_MM - 134241288U, // TGEU - 134241288U, // TGEU_MM - 134238046U, // TGE_MM - 9458U, // TLBP - 9458U, // TLBP_MM - 9469U, // TLBR - 9469U, // TLBR_MM - 9448U, // TLBWI - 9448U, // TLBWI_MM - 9474U, // TLBWR - 9474U, // TLBWR_MM - 134241218U, // TLT - 33576492U, // TLTI - 33578032U, // TLTIU_MM - 33576492U, // TLTI_MM - 134241363U, // TLTU - 134241363U, // TLTU_MM - 134241218U, // TLT_MM - 134238068U, // TNE - 33576413U, // TNEI - 33576413U, // TNEI_MM - 134238068U, // TNE_MM - 0U, // TRAP - 18981U, // TRUNC_L_D64 - 23009U, // TRUNC_L_S - 20157U, // TRUNC_W_D32 - 20157U, // TRUNC_W_D64 - 20157U, // TRUNC_W_MM - 23331U, // TRUNC_W_S - 23331U, // TRUNC_W_S_MM - 33578032U, // TTLTIU - 25597U, // UDIV - 25597U, // UDIV_MM - 134241335U, // V3MULU - 134234135U, // VMM0 - 134241350U, // VMULU - 151012022U, // VSHF_B - 151013760U, // VSHF_D - 151015430U, // VSHF_H - 151018984U, // VSHF_W - 9486U, // WAIT - 547767U, // WAIT_MM - 33577010U, // WRDSP - 21376U, // WSBH - 21376U, // WSBH_MM - 134240507U, // XOR - 836009U, // XOR16_MM - 134240507U, // XOR64 - 2281718581U, // XORI_B - 134240507U, // XOR_MM - 134241419U, // XOR_V - 0U, // XOR_V_D_PSEUDO - 0U, // XOR_V_H_PSEUDO - 0U, // XOR_V_W_PSEUDO - 134239770U, // XORi - 134239770U, // XORi64 - 134239770U, // XORi_MM - 16799995U, // XorRxRxRy16 - 0U - }; +static void printInstruction(MCInst *MI, SStream *O, + const MCRegisterInfo *MRI) { + static const uint32_t OpInfo[] = {0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 9396U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 9389U, // BUNDLE + 9406U, // LIFETIME_START + 9376U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 21660U, // ABSQ_S_PH + 18025U, // ABSQ_S_QB + 24850U, // ABSQ_S_W + 134237992U, // ADD + 18294U, // ADDIUPC + 18294U, // ADDIUPC_MM + 22527U, // ADDIUR1SP_MM + 134234410U, // ADDIUR2_MM + 8683851U, // ADDIUS5_MM + 546875U, // ADDIUSP_MM + 134239193U, // ADDQH_PH + 134239310U, // ADDQH_R_PH + 134242253U, // ADDQH_R_W + 134241856U, // ADDQH_W + 134239267U, // ADDQ_PH + 134239366U, // ADDQ_S_PH + 134242558U, // ADDQ_S_W + 134236055U, // ADDSC + 134234730U, // ADDS_A_B + 134236180U, // ADDS_A_D + 134238138U, // ADDS_A_H + 134241564U, // ADDS_A_W + 134235198U, // ADDS_S_B + 134237269U, // ADDS_S_D + 134238695U, // ADDS_S_H + 134242608U, // ADDS_S_W + 134235413U, // ADDS_U_B + 134237736U, // ADDS_U_D + 134238973U, // ADDS_U_H + 134243026U, // ADDS_U_W + 134234575U, // ADDU16_MM + 134235621U, // ADDUH_QB + 134235729U, // ADDUH_R_QB + 134239465U, // ADDU_PH + 134235834U, // ADDU_QB + 134239410U, // ADDU_S_PH + 134235775U, // ADDU_S_QB + 2281718627U, // ADDVI_B + 2281720348U, // ADDVI_D + 2281722002U, // ADDVI_H + 2281725637U, // ADDVI_W + 134235491U, // ADDV_B + 134237836U, // ADDV_D + 134239051U, // ADDV_H + 134243126U, // ADDV_W + 134236094U, // ADDWC + 134234712U, // ADD_A_B + 134236161U, // ADD_A_D + 134238120U, // ADD_A_H + 134241545U, // ADD_A_W + 134237992U, // ADD_MM + 134239685U, // ADDi + 134239685U, // ADDi_MM + 134241307U, // ADDiu + 134241307U, // ADDiu_MM + 134241261U, // ADDu + 134241261U, // ADDu_MM + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 134240158U, // ALIGN + 18286U, // ALUIPC + 134238014U, // AND + 835930U, // AND16_MM + 134238014U, // AND64 + 134234471U, // ANDI16_MM + 2281718486U, // ANDI_B + 134238014U, // AND_MM + 134241389U, // AND_V + 0U, // AND_V_D_PSEUDO + 0U, // AND_V_H_PSEUDO + 0U, // AND_V_W_PSEUDO + 134239691U, // ANDi + 134239691U, // ANDi64 + 134239691U, // ANDi_MM + 134238028U, // APPEND + 134235092U, // ASUB_S_B + 134237099U, // ASUB_S_D + 134238527U, // ASUB_S_H + 134242388U, // ASUB_S_W + 134235307U, // ASUB_U_B + 134237566U, // ASUB_U_D + 134238815U, // ASUB_U_H + 134242856U, // ASUB_U_W + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I8 + 134239795U, // AUI + 18279U, // AUIPC + 134235178U, // AVER_S_B + 134237249U, // AVER_S_D + 134238665U, // AVER_S_H + 134242588U, // AVER_S_W + 134235393U, // AVER_U_B + 134237716U, // AVER_U_D + 134238953U, // AVER_U_H + 134243006U, // AVER_U_W + 134235120U, // AVE_S_B + 134237181U, // AVE_S_D + 134238597U, // AVE_S_H + 134242470U, // AVE_S_W + 134235335U, // AVE_U_B + 134237648U, // AVE_U_D + 134238885U, // AVE_U_H + 134242938U, // AVE_U_W + 23579U, // AddiuRxImmX16 + 1072155U, // AddiuRxPcImmX16 + 285236251U, // AddiuRxRxImm16 + 16800795U, // AddiuRxRxImmX16 + 25189403U, // AddiuRxRyOffMemX16 + 1336343U, // AddiuSpImm16 + 549911U, // AddiuSpImmX16 + 134241261U, // AdduRxRyRz16 + 16797502U, // AndRxRxRy16 + 0U, // B + 541013U, // B16_MM + 134241260U, // BADDu + 546393U, // BAL + 542494U, // BALC + 134240157U, // BALIGN + 0U, // BAL_BR + 167788585U, // BBIT0 + 167788717U, // BBIT032 + 167788710U, // BBIT1 + 167788726U, // BBIT132 + 542473U, // BC + 20351U, // BC0F + 22218U, // BC0FL + 23455U, // BC0T + 22347U, // BC0TL + 25733U, // BC1EQZ + 20357U, // BC1F + 22225U, // BC1FL + 20357U, // BC1F_MM + 25717U, // BC1NEZ + 23461U, // BC1T + 22354U, // BC1TL + 23461U, // BC1T_MM + 25741U, // BC2EQZ + 20363U, // BC2F + 22232U, // BC2FL + 25725U, // BC2NEZ + 23467U, // BC2T + 22361U, // BC2TL + 20369U, // BC3F + 22239U, // BC3FL + 23473U, // BC3T + 22368U, // BC3TL + 2281718555U, // BCLRI_B + 2281720292U, // BCLRI_D + 2281721946U, // BCLRI_H + 2281725581U, // BCLRI_W + 134235059U, // BCLR_B + 134237023U, // BCLR_D + 134238494U, // BCLR_H + 134242304U, // BCLR_W + 134240340U, // BEQ + 134240340U, // BEQ64 + 134236044U, // BEQC + 134240063U, // BEQL + 16882U, // BEQZ16_MM + 18246U, // BEQZALC + 18394U, // BEQZC + 18394U, // BEQZC_MM + 134240340U, // BEQ_MM + 134235917U, // BGEC + 134236068U, // BGEUC + 25500U, // BGEZ + 25500U, // BGEZ64 + 22115U, // BGEZAL + 18219U, // BGEZALC + 22311U, // BGEZALL + 23424U, // BGEZALS_MM + 22115U, // BGEZAL_MM + 18373U, // BGEZC + 22391U, // BGEZL + 25500U, // BGEZ_MM + 25560U, // BGTZ + 25560U, // BGTZ64 + 18255U, // BGTZALC + 18401U, // BGTZC + 22405U, // BGTZL + 25560U, // BGTZ_MM + 2298495744U, // BINSLI_B + 2298497481U, // BINSLI_D + 2298499135U, // BINSLI_H + 2298502770U, // BINSLI_W + 151012243U, // BINSL_B + 151014033U, // BINSL_D + 151015601U, // BINSL_H + 151019280U, // BINSL_W + 2298495805U, // BINSRI_B + 2298497526U, // BINSRI_D + 2298499180U, // BINSRI_H + 2298502815U, // BINSRI_W + 151012291U, // BINSR_B + 151014289U, // BINSR_D + 151015726U, // BINSR_H + 151019570U, // BINSR_W + 23733U, // BITREV + 22477U, // BITSWAP + 25506U, // BLEZ + 25506U, // BLEZ64 + 18228U, // BLEZALC + 18380U, // BLEZC + 22398U, // BLEZL + 25506U, // BLEZ_MM + 134236062U, // BLTC + 134236075U, // BLTUC + 25566U, // BLTZ + 25566U, // BLTZ64 + 22123U, // BLTZAL + 18264U, // BLTZALC + 22320U, // BLTZALL + 23433U, // BLTZALS_MM + 22123U, // BLTZAL_MM + 18408U, // BLTZC + 22412U, // BLTZL + 25566U, // BLTZ_MM + 2298495860U, // BMNZI_B + 151018662U, // BMNZ_V + 2298495852U, // BMZI_B + 151018648U, // BMZ_V + 134238058U, // BNE + 134238058U, // BNE64 + 134235923U, // BNEC + 2281718494U, // BNEGI_B + 2281720240U, // BNEGI_D + 2281721894U, // BNEGI_H + 2281725529U, // BNEGI_W + 134234814U, // BNEG_B + 134236568U, // BNEG_D + 134238222U, // BNEG_H + 134241776U, // BNEG_W + 134239940U, // BNEL + 16874U, // BNEZ16_MM + 18237U, // BNEZALC + 18387U, // BNEZC + 18387U, // BNEZC_MM + 134238058U, // BNE_MM + 134236082U, // BNVC + 17803U, // BNZ_B + 20233U, // BNZ_D + 21363U, // BNZ_H + 23711U, // BNZ_V + 25463U, // BNZ_W + 134236088U, // BOVC + 540871U, // BPOSGE32 + 0U, // BPOSGE32_PSEUDO + 22080U, // BREAK + 65909U, // BREAK16_MM + 22080U, // BREAK_MM + 2298495719U, // BSELI_B + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 151018620U, // BSEL_V + 0U, // BSEL_W_PSEUDO + 2281718609U, // BSETI_B + 2281720330U, // BSETI_D + 2281721984U, // BSETI_H + 2281725619U, // BSETI_W + 134235275U, // BSET_B + 134237385U, // BSET_D + 134238783U, // BSET_H + 134242762U, // BSET_W + 17797U, // BZ_B + 20217U, // BZ_D + 21357U, // BZ_H + 23698U, // BZ_V + 25457U, // BZ_W + 541278U, // B_MM_Pseudo + 402678723U, // BeqzRxImm16 + 25539U, // BeqzRxImmX16 + 1327710U, // Bimm16 + 541278U, // BimmX16 + 402678696U, // BnezRxImm16 + 25512U, // BnezRxImmX16 + 9368U, // Break16 + 1598417U, // Bteqz16 + 536893428U, // BteqzT8CmpX16 + 536892936U, // BteqzT8CmpiX16 + 536894397U, // BteqzT8SltX16 + 536892966U, // BteqzT8SltiX16 + 536894505U, // BteqzT8SltiuX16 + 536894541U, // BteqzT8SltuX16 + 549841U, // BteqzX16 + 1598390U, // Btnez16 + 671111156U, // BtnezT8CmpX16 + 671110664U, // BtnezT8CmpiX16 + 671112125U, // BtnezT8SltX16 + 671110694U, // BtnezT8SltiX16 + 671112233U, // BtnezT8SltiuX16 + 671112269U, // BtnezT8SltuX16 + 549814U, // BtnezX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 85859U, // CACHE + 85859U, // CACHE_MM + 85859U, // CACHE_R6 + 19003U, // CEIL_L_D64 + 23031U, // CEIL_L_S + 20179U, // CEIL_W_D32 + 20179U, // CEIL_W_D64 + 20179U, // CEIL_W_MM + 23353U, // CEIL_W_S + 23353U, // CEIL_W_S_MM + 134234890U, // CEQI_B + 134236627U, // CEQI_D + 134238281U, // CEQI_H + 134241916U, // CEQI_W + 134235044U, // CEQ_B + 134236930U, // CEQ_D + 134238472U, // CEQ_H + 134242192U, // CEQ_W + 16444U, // CFC1 + 16444U, // CFC1_MM + 16968U, // CFCMSA + 134243407U, // CINS + 134243363U, // CINS32 + 19639U, // CLASS_D + 23205U, // CLASS_S + 134235129U, // CLEI_S_B + 134237190U, // CLEI_S_D + 134238606U, // CLEI_S_H + 134242479U, // CLEI_S_W + 2281718992U, // CLEI_U_B + 2281721305U, // CLEI_U_D + 2281722542U, // CLEI_U_H + 2281726595U, // CLEI_U_W + 134235111U, // CLE_S_B + 134237172U, // CLE_S_D + 134238588U, // CLE_S_H + 134242461U, // CLE_S_W + 134235326U, // CLE_U_B + 134237639U, // CLE_U_D + 134238876U, // CLE_U_H + 134242929U, // CLE_U_W + 22452U, // CLO + 22452U, // CLO_MM + 22452U, // CLO_R6 + 134235149U, // CLTI_S_B + 134237210U, // CLTI_S_D + 134238626U, // CLTI_S_H + 134242499U, // CLTI_S_W + 2281719012U, // CLTI_U_B + 2281721325U, // CLTI_U_D + 2281722562U, // CLTI_U_H + 2281726615U, // CLTI_U_W + 134235217U, // CLT_S_B + 134237288U, // CLT_S_D + 134238714U, // CLT_S_H + 134242627U, // CLT_S_W + 134235444U, // CLT_U_B + 134237767U, // CLT_U_D + 134239004U, // CLT_U_H + 134243057U, // CLT_U_W + 25534U, // CLZ + 25534U, // CLZ_MM + 25534U, // CLZ_R6 + 134235667U, // CMPGDU_EQ_QB + 134235572U, // CMPGDU_LE_QB + 134235786U, // CMPGDU_LT_QB + 134235681U, // CMPGU_EQ_QB + 134235586U, // CMPGU_LE_QB + 134235800U, // CMPGU_LT_QB + 17966U, // CMPU_EQ_QB + 17871U, // CMPU_LE_QB + 18085U, // CMPU_LT_QB + 134236919U, // CMP_EQ_D + 21548U, // CMP_EQ_PH + 134240864U, // CMP_EQ_S + 134236489U, // CMP_F_D + 134240675U, // CMP_F_S + 134236333U, // CMP_LE_D + 21444U, // CMP_LE_PH + 134240596U, // CMP_LE_S + 134237410U, // CMP_LT_D + 21717U, // CMP_LT_PH + 134240959U, // CMP_LT_S + 134236507U, // CMP_SAF_D + 134240685U, // CMP_SAF_S + 134236946U, // CMP_SEQ_D + 134240883U, // CMP_SEQ_S + 134236370U, // CMP_SLE_D + 134240625U, // CMP_SLE_S + 134237437U, // CMP_SLT_D + 134240978U, // CMP_SLT_S + 134236994U, // CMP_SUEQ_D + 134240914U, // CMP_SUEQ_S + 134236418U, // CMP_SULE_D + 134240656U, // CMP_SULE_S + 134237485U, // CMP_SULT_D + 134241009U, // CMP_SULT_S + 134236876U, // CMP_SUN_D + 134240837U, // CMP_SUN_S + 134236974U, // CMP_UEQ_D + 134240903U, // CMP_UEQ_S + 134236398U, // CMP_ULE_D + 134240645U, // CMP_ULE_S + 134237465U, // CMP_ULT_D + 134240998U, // CMP_ULT_S + 134236858U, // CMP_UN_D + 134240827U, // CMP_UN_S + 9454U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 2952807544U, // COPY_S_B + 2952809637U, // COPY_S_D + 2952811052U, // COPY_S_H + 2952814987U, // COPY_S_W + 2952807759U, // COPY_U_B + 2952810104U, // COPY_U_D + 2952811319U, // COPY_U_H + 2952815394U, // COPY_U_W + 1867863U, // CTC1 + 1867863U, // CTC1_MM + 16976U, // CTCMSA + 22833U, // CVT_D32_S + 23896U, // CVT_D32_W + 23896U, // CVT_D32_W_MM + 22087U, // CVT_D64_L + 22833U, // CVT_D64_S + 23896U, // CVT_D64_W + 22833U, // CVT_D_S_MM + 19024U, // CVT_L_D64 + 19024U, // CVT_L_D64_MM + 23052U, // CVT_L_S + 23052U, // CVT_L_S_MM + 19362U, // CVT_S_D32 + 19362U, // CVT_S_D32_MM + 19362U, // CVT_S_D64 + 22096U, // CVT_S_L + 24651U, // CVT_S_W + 24651U, // CVT_S_W_MM + 20200U, // CVT_W_D32 + 20200U, // CVT_W_D64 + 20200U, // CVT_W_MM + 23374U, // CVT_W_S + 23374U, // CVT_W_S_MM + 19183U, // C_EQ_D32 + 19183U, // C_EQ_D64 + 23128U, // C_EQ_S + 18754U, // C_F_D32 + 18754U, // C_F_D64 + 22940U, // C_F_S + 18597U, // C_LE_D32 + 18597U, // C_LE_D64 + 22860U, // C_LE_S + 19674U, // C_LT_D32 + 19674U, // C_LT_D64 + 23223U, // C_LT_S + 18588U, // C_NGE_D32 + 18588U, // C_NGE_D64 + 22851U, // C_NGE_S + 18623U, // C_NGLE_D32 + 18623U, // C_NGLE_D64 + 22878U, // C_NGLE_S + 19040U, // C_NGL_D32 + 19040U, // C_NGL_D64 + 23068U, // C_NGL_S + 19665U, // C_NGT_D32 + 19665U, // C_NGT_D64 + 23214U, // C_NGT_S + 18633U, // C_OLE_D32 + 18633U, // C_OLE_D64 + 22888U, // C_OLE_S + 19700U, // C_OLT_D32 + 19700U, // C_OLT_D64 + 23241U, // C_OLT_S + 19209U, // C_SEQ_D32 + 19209U, // C_SEQ_D64 + 23146U, // C_SEQ_S + 18824U, // C_SF_D32 + 18824U, // C_SF_D64 + 22986U, // C_SF_S + 19237U, // C_UEQ_D32 + 19237U, // C_UEQ_D64 + 23166U, // C_UEQ_S + 18661U, // C_ULE_D32 + 18661U, // C_ULE_D64 + 22908U, // C_ULE_S + 19728U, // C_ULT_D32 + 19728U, // C_ULT_D64 + 23261U, // C_ULT_S + 19122U, // C_UN_D32 + 19122U, // C_UN_D64 + 23091U, // C_UN_S + 22516U, // CmpRxRy16 + 939546120U, // CmpiRxImm16 + 22024U, // CmpiRxImmX16 + 549945U, // Constant32 + 134237991U, // DADD + 134239684U, // DADDi + 134241306U, // DADDiu + 134241267U, // DADDu + 8689123U, // DAHI + 134240165U, // DALIGN + 8689184U, // DATI + 134239794U, // DAUI + 22476U, // DBITSWAP + 22451U, // DCLO + 22451U, // DCLO_R6 + 25533U, // DCLZ + 25533U, // DCLZ_R6 + 134241469U, // DDIV + 134241377U, // DDIVU + 9480U, // DERET + 9480U, // DERET_MM + 134243425U, // DEXT + 134243400U, // DEXTM + 134243438U, // DEXTU + 546247U, // DI + 134243413U, // DINS + 134243393U, // DINSM + 134243431U, // DINSU + 134241470U, // DIV + 134241378U, // DIVU + 134235238U, // DIV_S_B + 134237331U, // DIV_S_D + 134238735U, // DIV_S_H + 134242670U, // DIV_S_W + 134235453U, // DIV_U_B + 134237798U, // DIV_U_D + 134239013U, // DIV_U_H + 134243088U, // DIV_U_W + 546247U, // DI_MM + 134234690U, // DLSA + 134234690U, // DLSA_R6 + 134234121U, // DMFC0 + 16450U, // DMFC1 + 134234372U, // DMFC2 + 134238036U, // DMOD + 134241281U, // DMODU + 134234128U, // DMTC0 + 1867869U, // DMTC1 + 134234379U, // DMTC2 + 134239671U, // DMUH + 134241299U, // DMUHU + 134240103U, // DMUL + 23495U, // DMULT + 23641U, // DMULTu + 134241343U, // DMULU + 134240103U, // DMUL_R6 + 134237239U, // DOTP_S_D + 134238655U, // DOTP_S_H + 134242538U, // DOTP_S_W + 134237706U, // DOTP_U_D + 134238943U, // DOTP_U_H + 134242996U, // DOTP_U_W + 151014368U, // DPADD_S_D + 151015784U, // DPADD_S_H + 151019657U, // DPADD_S_W + 151014835U, // DPADD_U_D + 151016072U, // DPADD_U_H + 151020125U, // DPADD_U_W + 134239524U, // DPAQX_SA_W_PH + 134239607U, // DPAQX_S_W_PH + 134241998U, // DPAQ_SA_L_W + 134239566U, // DPAQ_S_W_PH + 134239859U, // DPAU_H_QBL + 134240355U, // DPAU_H_QBR + 134239645U, // DPAX_W_PH + 134239514U, // DPA_W_PH + 22521U, // DPOP + 134239539U, // DPSQX_SA_W_PH + 134239621U, // DPSQX_S_W_PH + 134242011U, // DPSQ_SA_L_W + 134239594U, // DPSQ_S_W_PH + 151014335U, // DPSUB_S_D + 151015763U, // DPSUB_S_H + 151019624U, // DPSUB_S_W + 151014802U, // DPSUB_U_D + 151016051U, // DPSUB_U_H + 151020092U, // DPSUB_U_W + 134239871U, // DPSU_H_QBL + 134240367U, // DPSU_H_QBR + 134239656U, // DPSX_W_PH + 134239635U, // DPS_W_PH + 134240512U, // DROTR + 134234351U, // DROTR32 + 134241513U, // DROTRV + 21370U, // DSBH + 25610U, // DSDIV + 20275U, // DSHD + 134240057U, // DSLL + 134234321U, // DSLL32 + 1073764153U, // DSLL64_32 + 134241475U, // DSLLV + 134234684U, // DSRA + 134234303U, // DSRA32 + 134241454U, // DSRAV + 134240069U, // DSRL + 134234329U, // DSRL32 + 134241482U, // DSRLV + 134235901U, // DSUB + 134241246U, // DSUBu + 25596U, // DUDIV + 25611U, // DivRxRy16 + 25597U, // DivuRxRy16 + 9438U, // EHB + 9438U, // EHB_MM + 546259U, // EI + 546259U, // EI_MM + 9481U, // ERET + 9481U, // ERET_MM + 134243426U, // EXT + 134240324U, // EXTP + 134240221U, // EXTPDP + 134241497U, // EXTPDPV + 134241506U, // EXTPV + 134242731U, // EXTRV_RS_W + 134242285U, // EXTRV_R_W + 134238744U, // EXTRV_S_H + 134243168U, // EXTRV_W + 134242720U, // EXTR_RS_W + 134242264U, // EXTR_R_W + 134238675U, // EXTR_S_H + 134242363U, // EXTR_W + 134243419U, // EXTS + 134243371U, // EXTS32 + 134243426U, // EXT_MM + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 19631U, // FABS_D32 + 19631U, // FABS_D64 + 19631U, // FABS_MM + 23198U, // FABS_S + 23198U, // FABS_S_MM + 0U, // FABS_W + 134236265U, // FADD_D + 134236266U, // FADD_D32 + 134236266U, // FADD_D64 + 134236266U, // FADD_MM + 134240572U, // FADD_S + 134240572U, // FADD_S_MM + 134241633U, // FADD_W + 134236499U, // FCAF_D + 134241752U, // FCAF_W + 134236929U, // FCEQ_D + 134242191U, // FCEQ_W + 19638U, // FCLASS_D + 25015U, // FCLASS_W + 134236343U, // FCLE_D + 134241675U, // FCLE_W + 134237420U, // FCLT_D + 134242770U, // FCLT_W + 2204821U, // FCMP_D32 + 2204821U, // FCMP_D32_MM + 2204821U, // FCMP_D64 + 2466965U, // FCMP_S32 + 2466965U, // FCMP_S32_MM + 134236439U, // FCNE_D + 134241709U, // FCNE_W + 134237039U, // FCOR_D + 134242320U, // FCOR_W + 134236985U, // FCUEQ_D + 134242207U, // FCUEQ_W + 134236409U, // FCULE_D + 134241691U, // FCULE_W + 134237476U, // FCULT_D + 134242786U, // FCULT_W + 134236455U, // FCUNE_D + 134241725U, // FCUNE_W + 134236868U, // FCUN_D + 134242097U, // FCUN_W + 134237862U, // FDIV_D + 134237863U, // FDIV_D32 + 134237863U, // FDIV_D64 + 134237863U, // FDIV_MM + 134241045U, // FDIV_S + 134241045U, // FDIV_S_MM + 134243152U, // FDIV_W + 134238402U, // FEXDO_H + 134242113U, // FEXDO_W + 134236152U, // FEXP2_D + 0U, // FEXP2_D_1_PSEUDO + 134241536U, // FEXP2_W + 0U, // FEXP2_W_1_PSEUDO + 19064U, // FEXUPL_D + 24311U, // FEXUPL_W + 19327U, // FEXUPR_D + 24608U, // FEXUPR_W + 19569U, // FFINT_S_D + 24908U, // FFINT_S_W + 20048U, // FFINT_U_D + 25338U, // FFINT_U_W + 19074U, // FFQL_D + 24321U, // FFQL_W + 19337U, // FFQR_D + 24618U, // FFQR_W + 17277U, // FILL_B + 19049U, // FILL_D + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 20635U, // FILL_H + 24296U, // FILL_W + 18415U, // FLOG2_D + 23799U, // FLOG2_W + 19013U, // FLOOR_L_D64 + 23041U, // FLOOR_L_S + 20189U, // FLOOR_W_D32 + 20189U, // FLOOR_W_D64 + 20189U, // FLOOR_W_MM + 23363U, // FLOOR_W_S + 23363U, // FLOOR_W_S_MM + 151013489U, // FMADD_D + 151018857U, // FMADD_W + 134236190U, // FMAX_A_D + 134241574U, // FMAX_A_W + 134237937U, // FMAX_D + 134243177U, // FMAX_W + 134236170U, // FMIN_A_D + 134241554U, // FMIN_A_W + 134236842U, // FMIN_D + 134242089U, // FMIN_W + 20150U, // FMOV_D32 + 20150U, // FMOV_D32_MM + 20150U, // FMOV_D64 + 23324U, // FMOV_S + 23324U, // FMOV_S_MM + 151013447U, // FMSUB_D + 151018815U, // FMSUB_W + 134236826U, // FMUL_D + 134236827U, // FMUL_D32 + 134236827U, // FMUL_D64 + 134236827U, // FMUL_MM + 134240805U, // FMUL_S + 134240805U, // FMUL_S_MM + 134242073U, // FMUL_W + 18841U, // FNEG_D32 + 18841U, // FNEG_D64 + 18841U, // FNEG_MM + 23002U, // FNEG_S + 23002U, // FNEG_S_MM + 19175U, // FRCP_D + 24394U, // FRCP_W + 19786U, // FRINT_D + 25084U, // FRINT_W + 19814U, // FRSQRT_D + 25112U, // FRSQRT_W + 134236518U, // FSAF_D + 134241760U, // FSAF_W + 134236957U, // FSEQ_D + 134242199U, // FSEQ_W + 134236381U, // FSLE_D + 134241683U, // FSLE_W + 134237448U, // FSLT_D + 134242778U, // FSLT_W + 134236447U, // FSNE_D + 134241717U, // FSNE_W + 134237047U, // FSOR_D + 134242328U, // FSOR_W + 19805U, // FSQRT_D + 19806U, // FSQRT_D32 + 19806U, // FSQRT_D64 + 19806U, // FSQRT_MM + 23301U, // FSQRT_S + 23301U, // FSQRT_S_MM + 25103U, // FSQRT_W + 134236223U, // FSUB_D + 134236224U, // FSUB_D32 + 134236224U, // FSUB_D64 + 134236224U, // FSUB_MM + 134240554U, // FSUB_S + 134240554U, // FSUB_S_MM + 134241591U, // FSUB_W + 134237006U, // FSUEQ_D + 134242216U, // FSUEQ_W + 134236430U, // FSULE_D + 134241700U, // FSULE_W + 134237497U, // FSULT_D + 134242795U, // FSULT_W + 134236464U, // FSUNE_D + 134241734U, // FSUNE_W + 134236887U, // FSUN_D + 134242105U, // FSUN_W + 19580U, // FTINT_S_D + 24919U, // FTINT_S_W + 20059U, // FTINT_U_D + 25349U, // FTINT_U_W + 134238479U, // FTQ_H + 134242225U, // FTQ_W + 19402U, // FTRUNC_S_D + 24691U, // FTRUNC_S_W + 19869U, // FTRUNC_U_D + 25159U, // FTRUNC_U_W + 1224758783U, // GotPrologue16 + 134237142U, // HADD_S_D + 134238558U, // HADD_S_H + 134242431U, // HADD_S_W + 134237609U, // HADD_U_D + 134238846U, // HADD_U_H + 134242899U, // HADD_U_W + 134237109U, // HSUB_S_D + 134238537U, // HSUB_S_H + 134242398U, // HSUB_S_W + 134237576U, // HSUB_U_D + 134238825U, // HSUB_U_H + 134242866U, // HSUB_U_W + 134235508U, // ILVEV_B + 134237853U, // ILVEV_D + 134239068U, // ILVEV_H + 134243143U, // ILVEV_W + 134235036U, // ILVL_B + 134236834U, // ILVL_D + 134238394U, // ILVL_H + 134242081U, // ILVL_W + 134234788U, // ILVOD_B + 134236307U, // ILVOD_D + 134238196U, // ILVOD_H + 134241666U, // ILVOD_W + 134235084U, // ILVR_B + 134237082U, // ILVR_D + 134238519U, // ILVR_H + 134242371U, // ILVR_W + 134243408U, // INS + 44582043U, // INSERT_B + 0U, // INSERT_B_VIDX_PSEUDO + 44584275U, // INSERT_D + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 44585551U, // INSERT_H + 0U, // INSERT_H_VIDX_PSEUDO + 44589573U, // INSERT_W + 0U, // INSERT_W_VIDX_PSEUDO + 16801009U, // INSV + 52970157U, // INSVE_B + 52971833U, // INSVE_D + 52973565U, // INSVE_H + 52977103U, // INSVE_W + 134243408U, // INS_MM + 546365U, // J + 546398U, // JAL + 22768U, // JALR + 547056U, // JALR16_MM + 22768U, // JALR64 + 0U, // JALR64Pseudo + 0U, // JALRPseudo + 541104U, // JALRS16_MM + 23442U, // JALRS_MM + 17822U, // JALR_HB + 22768U, // JALR_MM + 547706U, // JALS_MM + 549771U, // JALX + 549771U, // JALX_MM + 546398U, // JAL_MM + 18212U, // JIALC + 18201U, // JIC + 547052U, // JR + 541091U, // JR16_MM + 547052U, // JR64 + 546873U, // JRADDIUSP + 542610U, // JRC16_MM + 542103U, // JR_HB + 542103U, // JR_HB_R6 + 547052U, // JR_MM + 546365U, // J_MM + 2905694U, // Jal16 + 3167838U, // JalB16 + 546398U, // JalOneReg + 22110U, // JalTwoReg + 9430U, // JrRa16 + 9421U, // JrcRa16 + 549872U, // JrcRx16 + 540673U, // JumpLinkReg16 + 58738087U, // LB + 58738087U, // LB64 + 58737088U, // LBU16_MM + 1358979985U, // LBUX + 58738087U, // LB_MM + 58743769U, // LBu + 58743769U, // LBu64 + 58743769U, // LBu_MM + 58740538U, // LD + 58736688U, // LDC1 + 58736688U, // LDC164 + 58736688U, // LDC1_MM + 58736888U, // LDC2 + 58736888U, // LDC2_R6 + 58736947U, // LDC3 + 17103U, // LDI_B + 18857U, // LDI_D + 20511U, // LDI_H + 24146U, // LDI_W + 58742458U, // LDL + 18273U, // LDPC + 58742954U, // LDR + 1358970992U, // LDXC1 + 1358970992U, // LDXC164 + 58737301U, // LD_B + 58738820U, // LD_D + 58740709U, // LD_H + 58744179U, // LD_W + 25189403U, // LEA_ADDiu + 25189402U, // LEA_ADDiu64 + 25189403U, // LEA_ADDiu_MM + 58741643U, // LH + 58741643U, // LH64 + 58737111U, // LHU16_MM + 1358979974U, // LHX + 58741643U, // LH_MM + 58743822U, // LHu + 58743822U, // LHu64 + 58743822U, // LHu_MM + 16751U, // LI16_MM + 58742563U, // LL + 58740537U, // LLD + 58740537U, // LLD_R6 + 58742563U, // LL_MM + 58742563U, // LL_R6 + 58736647U, // LOAD_ACC128 + 58736647U, // LOAD_ACC64 + 58736647U, // LOAD_ACC64DSP + 58742794U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_LUi + 134234691U, // LSA + 134234691U, // LSA_R6 + 1358971006U, // LUXC1 + 1358971006U, // LUXC164 + 1358971006U, // LUXC1_MM + 33576504U, // LUi + 33576504U, // LUi64 + 33576504U, // LUi_MM + 58745726U, // LW + 58737118U, // LW16_MM + 58745726U, // LW64 + 58736740U, // LWC1 + 58736740U, // LWC1_MM + 58736914U, // LWC2 + 58736914U, // LWC2_R6 + 58736959U, // LWC3 + 58745726U, // LWGP_MM + 58742637U, // LWL + 58742637U, // LWL64 + 58742637U, // LWL_MM + 3522956U, // LWM16_MM + 3522785U, // LWM32_MM + 3528595U, // LWM_MM + 18310U, // LWPC + 137290U, // LWP_MM + 58743054U, // LWR + 58743054U, // LWR64 + 58743054U, // LWR_MM + 58745726U, // LWSP_MM + 18303U, // LWUPC + 58743912U, // LWU_MM + 1358979991U, // LWX + 1358971020U, // LWXC1 + 1358971020U, // LWXC1_MM + 1358977945U, // LWXS_MM + 58745726U, // LW_MM + 58743912U, // LWu + 58738087U, // LbRxRyOffMemX16 + 58743769U, // LbuRxRyOffMemX16 + 58741643U, // LhRxRyOffMemX16 + 58743822U, // LhuRxRyOffMemX16 + 939546111U, // LiRxImm16 + 22005U, // LiRxImmAlignX16 + 22015U, // LiRxImmX16 + 33571334U, // LoadAddr32Imm + 58737158U, // LoadAddr32Reg + 33576447U, // LoadImm32Reg + 22019U, // LoadImm64Reg + 3695486U, // LwConstant32 + 268460926U, // LwRxPcTcp16 + 25470U, // LwRxPcTcpX16 + 58745726U, // LwRxRyOffMemX16 + 1493197694U, // LwRxSpImmX16 + 20269U, // MADD + 151013751U, // MADDF_D + 151017921U, // MADDF_S + 151015667U, // MADDR_Q_H + 151019386U, // MADDR_Q_W + 23546U, // MADDU + 134241274U, // MADDU_DSP + 23546U, // MADDU_MM + 151012706U, // MADDV_B + 151015051U, // MADDV_D + 151016266U, // MADDV_H + 151020341U, // MADDV_W + 134236274U, // MADD_D32 + 134236274U, // MADD_D32_MM + 134236274U, // MADD_D64 + 134237997U, // MADD_DSP + 20269U, // MADD_MM + 151015637U, // MADD_Q_H + 151019356U, // MADD_Q_W + 134240571U, // MADD_S + 134240571U, // MADD_S_MM + 134239974U, // MAQ_SA_W_PHL + 134240436U, // MAQ_SA_W_PHR + 134240002U, // MAQ_S_W_PHL + 134240464U, // MAQ_S_W_PHR + 134236215U, // MAXA_D + 134240544U, // MAXA_S + 134235159U, // MAXI_S_B + 134237220U, // MAXI_S_D + 134238636U, // MAXI_S_H + 134242509U, // MAXI_S_W + 2281719022U, // MAXI_U_B + 2281721335U, // MAXI_U_D + 2281722572U, // MAXI_U_H + 2281726625U, // MAXI_U_W + 134234740U, // MAX_A_B + 134236191U, // MAX_A_D + 134238148U, // MAX_A_H + 134241575U, // MAX_A_W + 134237938U, // MAX_D + 134241111U, // MAX_S + 134235247U, // MAX_S_B + 134237340U, // MAX_S_D + 134238755U, // MAX_S_H + 134242690U, // MAX_S_W + 134235462U, // MAX_U_B + 134237807U, // MAX_U_D + 134239022U, // MAX_U_H + 134243097U, // MAX_U_W + 134234122U, // MFC0 + 16451U, // MFC1 + 16451U, // MFC1_MM + 134234373U, // MFC2 + 16457U, // MFHC1_D32 + 16457U, // MFHC1_D64 + 16457U, // MFHC1_MM + 546281U, // MFHI + 546281U, // MFHI16_MM + 546281U, // MFHI64 + 21993U, // MFHI_DSP + 546281U, // MFHI_MM + 546745U, // MFLO + 546745U, // MFLO16_MM + 546745U, // MFLO64 + 22457U, // MFLO_DSP + 546745U, // MFLO_MM + 134236200U, // MINA_D + 134240536U, // MINA_S + 134235139U, // MINI_S_B + 134237200U, // MINI_S_D + 134238616U, // MINI_S_H + 134242489U, // MINI_S_W + 2281719002U, // MINI_U_B + 2281721315U, // MINI_U_D + 2281722552U, // MINI_U_H + 2281726605U, // MINI_U_W + 134234721U, // MIN_A_B + 134236171U, // MIN_A_D + 134238129U, // MIN_A_H + 134241555U, // MIN_A_W + 134236843U, // MIN_D + 134240812U, // MIN_S + 134235169U, // MIN_S_B + 134237230U, // MIN_S_D + 134238646U, // MIN_S_H + 134242529U, // MIN_S_W + 134235384U, // MIN_U_B + 134237697U, // MIN_U_D + 134238934U, // MIN_U_H + 134242987U, // MIN_U_W + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 134238037U, // MOD + 134235899U, // MODSUB + 134241282U, // MODU + 134235102U, // MOD_S_B + 134237163U, // MOD_S_D + 134238579U, // MOD_S_H + 134242452U, // MOD_S_W + 134235317U, // MOD_U_B + 134237630U, // MOD_U_D + 134238867U, // MOD_U_H + 134242920U, // MOD_U_W + 20345U, // MOVE16_MM + 67491813U, // MOVEP_MM + 23668U, // MOVE_V + 134236560U, // MOVF_D32 + 134236560U, // MOVF_D32_MM + 134236560U, // MOVF_D64 + 134238109U, // MOVF_I + 134238109U, // MOVF_I64 + 134238109U, // MOVF_I_MM + 134240722U, // MOVF_S + 134240722U, // MOVF_S_MM + 134236895U, // MOVN_I64_D64 + 134240173U, // MOVN_I64_I + 134240173U, // MOVN_I64_I64 + 134240848U, // MOVN_I64_S + 134236895U, // MOVN_I_D32 + 134236895U, // MOVN_I_D32_MM + 134236895U, // MOVN_I_D64 + 134240173U, // MOVN_I_I + 134240173U, // MOVN_I_I64 + 134240173U, // MOVN_I_MM + 134240848U, // MOVN_I_S + 134240848U, // MOVN_I_S_MM + 134237558U, // MOVT_D32 + 134237558U, // MOVT_D32_MM + 134237558U, // MOVT_D64 + 134241235U, // MOVT_I + 134241235U, // MOVT_I64 + 134241235U, // MOVT_I_MM + 134241037U, // MOVT_S + 134241037U, // MOVT_S_MM + 134237978U, // MOVZ_I64_D64 + 134243300U, // MOVZ_I64_I + 134243300U, // MOVZ_I64_I64 + 134241138U, // MOVZ_I64_S + 134237978U, // MOVZ_I_D32 + 134237978U, // MOVZ_I_D32_MM + 134237978U, // MOVZ_I_D64 + 134243300U, // MOVZ_I_I + 134243300U, // MOVZ_I_I64 + 134243300U, // MOVZ_I_MM + 134241138U, // MOVZ_I_S + 134241138U, // MOVZ_I_S_MM + 18179U, // MSUB + 151013742U, // MSUBF_D + 151017912U, // MSUBF_S + 151015656U, // MSUBR_Q_H + 151019375U, // MSUBR_Q_W + 23525U, // MSUBU + 134241253U, // MSUBU_DSP + 23525U, // MSUBU_MM + 151012697U, // MSUBV_B + 151015042U, // MSUBV_D + 151016257U, // MSUBV_H + 151020332U, // MSUBV_W + 134236232U, // MSUB_D32 + 134236232U, // MSUB_D32_MM + 134236232U, // MSUB_D64 + 134235907U, // MSUB_DSP + 18179U, // MSUB_MM + 151015627U, // MSUB_Q_H + 151019346U, // MSUB_Q_W + 134240553U, // MSUB_S + 134240553U, // MSUB_S_MM + 134234129U, // MTC0 + 1867870U, // MTC1 + 1867870U, // MTC1_MM + 134234380U, // MTC2 + 1884240U, // MTHC1_D32 + 1884240U, // MTHC1_D64 + 1884240U, // MTHC1_MM + 546287U, // MTHI + 546287U, // MTHI64 + 1873391U, // MTHI_DSP + 546287U, // MTHI_MM + 1873900U, // MTHLIP + 546758U, // MTLO + 546758U, // MTLO64 + 1873862U, // MTLO_DSP + 546758U, // MTLO_MM + 540701U, // MTM0 + 540826U, // MTM1 + 540958U, // MTM2 + 540707U, // MTP0 + 540832U, // MTP1 + 540964U, // MTP2 + 134239672U, // MUH + 134241300U, // MUHU + 134240104U, // MUL + 134240015U, // MULEQ_S_W_PHL + 134240477U, // MULEQ_S_W_PHR + 134239883U, // MULEU_S_PH_QBL + 134240379U, // MULEU_S_PH_QBR + 134239433U, // MULQ_RS_PH + 134242709U, // MULQ_RS_W + 134239377U, // MULQ_S_PH + 134242568U, // MULQ_S_W + 134238462U, // MULR_Q_H + 134242181U, // MULR_Q_W + 134239579U, // MULSAQ_S_W_PH + 134239554U, // MULSA_W_PH + 23496U, // MULT + 134241370U, // MULTU_DSP + 134241224U, // MULT_DSP + 23496U, // MULT_MM + 23642U, // MULTu + 23642U, // MULTu_MM + 134241337U, // MULU + 134235517U, // MULV_B + 134237870U, // MULV_D + 134239077U, // MULV_H + 134243160U, // MULV_W + 134240104U, // MUL_MM + 134239250U, // MUL_PH + 134238431U, // MUL_Q_H + 134242150U, // MUL_Q_W + 134240104U, // MUL_R6 + 134239345U, // MUL_S_PH + 546281U, // Mfhi16 + 546745U, // Mflo16 + 20345U, // Move32R16 + 20345U, // MoveR3216 + 23496U, // MultRxRy16 + 75799496U, // MultRxRyRz16 + 23642U, // MultuRxRy16 + 75799642U, // MultuRxRyRz16 + 17028U, // NLOC_B + 18521U, // NLOC_D + 20436U, // NLOC_H + 23880U, // NLOC_W + 17036U, // NLZC_B + 18529U, // NLZC_D + 20444U, // NLZC_H + 23888U, // NLZC_W + 134236282U, // NMADD_D32 + 134236282U, // NMADD_D32_MM + 134236282U, // NMADD_D64 + 134240570U, // NMADD_S + 134240570U, // NMADD_S_MM + 134236240U, // NMSUB_D32 + 134236240U, // NMSUB_D32_MM + 134236240U, // NMSUB_D64 + 134240552U, // NMSUB_S + 134240552U, // NMSUB_S_MM + 0U, // NOP + 134240502U, // NOR + 134240502U, // NOR64 + 2281718573U, // NORI_B + 134240502U, // NOR_MM + 134241412U, // NOR_V + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 16825U, // NOT16_MM + 20387U, // NegRxRy16 + 23502U, // NotRxRy16 + 134240503U, // OR + 836010U, // OR16_MM + 134240503U, // OR64 + 2281718574U, // ORI_B + 134240503U, // OR_MM + 134241413U, // OR_V + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 134239771U, // ORi + 134239771U, // ORi64 + 134239771U, // ORi_MM + 16799991U, // OrRxRxRy16 + 134239239U, // PACKRL_PH + 9442U, // PAUSE + 9442U, // PAUSE_MM + 134235499U, // PCKEV_B + 134237844U, // PCKEV_D + 134239059U, // PCKEV_H + 134243134U, // PCKEV_W + 134234779U, // PCKOD_B + 134236298U, // PCKOD_D + 134238187U, // PCKOD_H + 134241657U, // PCKOD_W + 17555U, // PCNT_B + 19778U, // PCNT_D + 21063U, // PCNT_H + 25076U, // PCNT_W + 134239203U, // PICK_PH + 134235631U, // PICK_QB + 22522U, // POP + 22186U, // PRECEQU_PH_QBL + 16906U, // PRECEQU_PH_QBLA + 22682U, // PRECEQU_PH_QBR + 16939U, // PRECEQU_PH_QBRA + 22260U, // PRECEQ_W_PHL + 22722U, // PRECEQ_W_PHR + 22171U, // PRECEU_PH_QBL + 16890U, // PRECEU_PH_QBLA + 22667U, // PRECEU_PH_QBR + 16923U, // PRECEU_PH_QBRA + 134239155U, // PRECRQU_S_QB_PH + 134241800U, // PRECRQ_PH_W + 134239128U, // PRECRQ_QB_PH + 134241831U, // PRECRQ_RS_PH_W + 134239142U, // PRECR_QB_PH + 134241784U, // PRECR_SRA_PH_W + 134241813U, // PRECR_SRA_R_PH_W + 85911U, // PREF + 85911U, // PREF_MM + 85911U, // PREF_R6 + 134238019U, // PREPEND + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 16391U, // PseudoCVT_D32_W + 16391U, // PseudoCVT_D64_L + 16391U, // PseudoCVT_D64_W + 16391U, // PseudoCVT_S_L + 16391U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMULT + 0U, // PseudoMULTu + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 0U, // PseudoUDIV + 18155U, // RADDU_W_QB + 33577003U, // RDDSP + 22791U, // RDHWR + 22791U, // RDHWR64 + 22791U, // RDHWR_MM + 21766U, // REPLV_PH + 18135U, // REPLV_QB + 33575925U, // REPL_PH + 33572353U, // REPL_QB + 19787U, // RINT_D + 23293U, // RINT_S + 134240513U, // ROTR + 134241514U, // ROTRV + 134241514U, // ROTRV_MM + 134240513U, // ROTR_MM + 18992U, // ROUND_L_D64 + 23020U, // ROUND_L_S + 20168U, // ROUND_W_D32 + 20168U, // ROUND_W_D64 + 20168U, // ROUND_W_MM + 23342U, // ROUND_W_S + 23342U, // ROUND_W_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 0U, // RetRA + 0U, // RetRA16 + 134235208U, // SAT_S_B + 134237279U, // SAT_S_D + 2281722353U, // SAT_S_H + 134242618U, // SAT_S_W + 134235435U, // SAT_U_B + 134237758U, // SAT_U_D + 2281722643U, // SAT_U_H + 134243048U, // SAT_U_W + 58738423U, // SB + 58736980U, // SB16_MM + 58738423U, // SB64 + 58738423U, // SB_MM + 3966874U, // SC + 3968802U, // SCD + 3968802U, // SCD_R6 + 3966874U, // SC_MM + 3966874U, // SC_R6 + 58740570U, // SD + 546774U, // SDBBP + 65946U, // SDBBP16_MM + 546774U, // SDBBP_MM + 546774U, // SDBBP_R6 + 58736694U, // SDC1 + 58736694U, // SDC164 + 58736694U, // SDC1_MM + 58736894U, // SDC2 + 58736894U, // SDC2_R6 + 58736953U, // SDC3 + 25611U, // SDIV + 25611U, // SDIV_MM + 58742463U, // SDL + 58742959U, // SDR + 1358970999U, // SDXC1 + 1358970999U, // SDXC164 + 17810U, // SEB + 17810U, // SEB64 + 17810U, // SEB_MM + 21382U, // SEH + 21382U, // SEH64 + 21382U, // SEH_MM + 134243273U, // SELEQZ + 134243273U, // SELEQZ64 + 134237968U, // SELEQZ_D + 134241128U, // SELEQZ_S + 134243246U, // SELNEZ + 134243246U, // SELNEZ64 + 134237951U, // SELNEZ_D + 134241118U, // SELNEZ_S + 151013977U, // SEL_D + 151018005U, // SEL_S + 134240345U, // SEQ + 134239758U, // SEQi + 58742195U, // SH + 58736993U, // SH16_MM + 58742195U, // SH64 + 2281718455U, // SHF_B + 2281721863U, // SHF_H + 2281725417U, // SHF_W + 22463U, // SHILO + 23761U, // SHILOV + 134239484U, // SHLLV_PH + 134235853U, // SHLLV_QB + 134239421U, // SHLLV_S_PH + 134242679U, // SHLLV_S_W + 134239212U, // SHLL_PH + 134235640U, // SHLL_QB + 134239334U, // SHLL_S_PH + 134242519U, // SHLL_S_W + 134239474U, // SHRAV_PH + 134235843U, // SHRAV_QB + 134239322U, // SHRAV_R_PH + 134235741U, // SHRAV_R_QB + 134242274U, // SHRAV_R_W + 134239119U, // SHRA_PH + 134235563U, // SHRA_QB + 134239287U, // SHRA_R_PH + 134235706U, // SHRA_R_QB + 134242232U, // SHRA_R_W + 134239504U, // SHRLV_PH + 134235873U, // SHRLV_QB + 134239230U, // SHRL_PH + 134235658U, // SHRL_QB + 58742195U, // SH_MM + 2969584334U, // SLDI_B + 2969586088U, // SLDI_D + 2969587742U, // SLDI_H + 2969591377U, // SLDI_W + 822100628U, // SLD_B + 822102147U, // SLD_D + 822104036U, // SLD_H + 822107506U, // SLD_W + 134240058U, // SLL + 134234494U, // SLL16_MM + 1610635066U, // SLL64_32 + 1610635066U, // SLL64_64 + 2281718512U, // SLLI_B + 2281720249U, // SLLI_D + 2281721903U, // SLLI_H + 2281725538U, // SLLI_W + 134241476U, // SLLV + 134241476U, // SLLV_MM + 134235013U, // SLL_B + 134236785U, // SLL_D + 134238371U, // SLL_H + 134240058U, // SLL_MM + 134242032U, // SLL_W + 134241213U, // SLT + 134241213U, // SLT64 + 134241213U, // SLT_MM + 134239782U, // SLTi + 134239782U, // SLTi64 + 134239782U, // SLTi_MM + 134241321U, // SLTiu + 134241321U, // SLTiu64 + 134241321U, // SLTiu_MM + 134241357U, // SLTu + 134241357U, // SLTu64 + 134241357U, // SLTu_MM + 134238063U, // SNE + 134239703U, // SNEi + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 2952807239U, // SPLATI_B + 2952808960U, // SPLATI_D + 2952810614U, // SPLATI_H + 2952814249U, // SPLATI_W + 805323906U, // SPLAT_B + 805326016U, // SPLAT_D + 805327414U, // SPLAT_H + 805331393U, // SPLAT_W + 134234685U, // SRA + 2281718470U, // SRAI_B + 2281720224U, // SRAI_D + 2281721878U, // SRAI_H + 2281725513U, // SRAI_W + 134234898U, // SRARI_B + 134236635U, // SRARI_D + 2281721937U, // SRARI_H + 134241924U, // SRARI_W + 134235051U, // SRAR_B + 134237015U, // SRAR_D + 134238486U, // SRAR_H + 134242296U, // SRAR_W + 134241455U, // SRAV + 134241455U, // SRAV_MM + 134234749U, // SRA_B + 134236208U, // SRA_D + 134238157U, // SRA_H + 134234685U, // SRA_MM + 134241584U, // SRA_W + 134240070U, // SRL + 134234501U, // SRL16_MM + 2281718520U, // SRLI_B + 2281720257U, // SRLI_D + 2281721911U, // SRLI_H + 2281725546U, // SRLI_W + 134234916U, // SRLRI_B + 134236653U, // SRLRI_D + 2281721955U, // SRLRI_H + 134241942U, // SRLRI_W + 134235067U, // SRLR_B + 134237031U, // SRLR_D + 134238502U, // SRLR_H + 134242312U, // SRLR_W + 134241483U, // SRLV + 134241483U, // SRLV_MM + 134235020U, // SRL_B + 134236810U, // SRL_D + 134238378U, // SRL_H + 134240070U, // SRL_MM + 134242057U, // SRL_W + 9463U, // SSNOP + 9463U, // SSNOP_MM + 58736647U, // STORE_ACC128 + 58736647U, // STORE_ACC64 + 58736647U, // STORE_ACC64DSP + 58742810U, // STORE_CCOND_DSP + 58737829U, // ST_B + 58740080U, // ST_D + 58741337U, // ST_H + 58745378U, // ST_W + 134235902U, // SUB + 134239183U, // SUBQH_PH + 134239298U, // SUBQH_R_PH + 134242242U, // SUBQH_R_W + 134241847U, // SUBQH_W + 134239258U, // SUBQ_PH + 134239355U, // SUBQ_S_PH + 134242548U, // SUBQ_S_W + 134235423U, // SUBSUS_U_B + 134237746U, // SUBSUS_U_D + 134238983U, // SUBSUS_U_H + 134243036U, // SUBSUS_U_W + 134235226U, // SUBSUU_S_B + 134237319U, // SUBSUU_S_D + 134238723U, // SUBSUU_S_H + 134242658U, // SUBSUU_S_W + 134235188U, // SUBS_S_B + 134237259U, // SUBS_S_D + 134238685U, // SUBS_S_H + 134242598U, // SUBS_S_W + 134235403U, // SUBS_U_B + 134237726U, // SUBS_U_D + 134238963U, // SUBS_U_H + 134243016U, // SUBS_U_W + 134234567U, // SUBU16_MM + 134235611U, // SUBUH_QB + 134235717U, // SUBUH_R_QB + 134239456U, // SUBU_PH + 134235825U, // SUBU_QB + 134239399U, // SUBU_S_PH + 134235764U, // SUBU_S_QB + 2281718618U, // SUBVI_B + 2281720339U, // SUBVI_D + 2281721993U, // SUBVI_H + 2281725628U, // SUBVI_W + 134235482U, // SUBV_B + 134237827U, // SUBV_D + 134239042U, // SUBV_H + 134243117U, // SUBV_W + 134235902U, // SUB_MM + 134241247U, // SUBu + 134241247U, // SUBu_MM + 1358971013U, // SUXC1 + 1358971013U, // SUXC164 + 1358971013U, // SUXC1_MM + 58745730U, // SW + 58737124U, // SW16_MM + 58745730U, // SW64 + 58736746U, // SWC1 + 58736746U, // SWC1_MM + 58736920U, // SWC2 + 58736920U, // SWC2_R6 + 58736965U, // SWC3 + 58742642U, // SWL + 58742642U, // SWL64 + 58742642U, // SWL_MM + 3522963U, // SWM16_MM + 3522792U, // SWM32_MM + 3528600U, // SWM_MM + 137295U, // SWP_MM + 58743059U, // SWR + 58743059U, // SWR64 + 58743059U, // SWR_MM + 58745730U, // SWSP_MM + 1358971027U, // SWXC1 + 1358971027U, // SWXC1_MM + 58745730U, // SW_MM + 549939U, // SYNC + 153021U, // SYNCI + 549939U, // SYNC_MM + 546590U, // SYSCALL + 546590U, // SYSCALL_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 0U, // Save16 + 0U, // SaveX16 + 58738423U, // SbRxRyOffMemX16 + 549866U, // SebRx16 + 549878U, // SehRx16 + 4367299U, // SelBeqZ + 4367272U, // SelBneZ + 1828886516U, // SelTBteqZCmp + 1828886024U, // SelTBteqZCmpi + 1828887485U, // SelTBteqZSlt + 1828886054U, // SelTBteqZSlti + 1828887593U, // SelTBteqZSltiu + 1828887629U, // SelTBteqZSltu + 1963104244U, // SelTBtneZCmp + 1963103752U, // SelTBtneZCmpi + 1963105213U, // SelTBtneZSlt + 1963103782U, // SelTBtneZSlti + 1963105321U, // SelTBtneZSltiu + 1963105357U, // SelTBtneZSltu + 58742195U, // ShRxRyOffMemX16 + 134240058U, // SllX16 + 16800964U, // SllvRxRy16 + 92576701U, // SltCCRxRy16 + 23485U, // SltRxRy16 + 92575270U, // SltiCCRxImmX16 + 939546150U, // SltiRxImm16 + 22054U, // SltiRxImmX16 + 92576809U, // SltiuCCRxImmX16 + 939547689U, // SltiuRxImm16 + 23593U, // SltiuRxImmX16 + 92576845U, // SltuCCRxRy16 + 23629U, // SltuRxRy16 + 92576845U, // SltuRxRyRz16 + 134234685U, // SraX16 + 16800943U, // SravRxRy16 + 134240070U, // SrlX16 + 16800971U, // SrlvRxRy16 + 134241247U, // SubuRxRyRz16 + 58745730U, // SwRxRyOffMemX16 + 1493197698U, // SwRxSpImmX16 + 0U, // TAILCALL + 0U, // TAILCALL64_R + 0U, // TAILCALL_R + 134240350U, // TEQ + 33576468U, // TEQI + 33576468U, // TEQI_MM + 134240350U, // TEQ_MM + 134238046U, // TGE + 33576401U, // TGEI + 33578018U, // TGEIU + 33578018U, // TGEIU_MM + 33576401U, // TGEI_MM + 134241288U, // TGEU + 134241288U, // TGEU_MM + 134238046U, // TGE_MM + 9458U, // TLBP + 9458U, // TLBP_MM + 9469U, // TLBR + 9469U, // TLBR_MM + 9448U, // TLBWI + 9448U, // TLBWI_MM + 9474U, // TLBWR + 9474U, // TLBWR_MM + 134241218U, // TLT + 33576492U, // TLTI + 33578032U, // TLTIU_MM + 33576492U, // TLTI_MM + 134241363U, // TLTU + 134241363U, // TLTU_MM + 134241218U, // TLT_MM + 134238068U, // TNE + 33576413U, // TNEI + 33576413U, // TNEI_MM + 134238068U, // TNE_MM + 0U, // TRAP + 18981U, // TRUNC_L_D64 + 23009U, // TRUNC_L_S + 20157U, // TRUNC_W_D32 + 20157U, // TRUNC_W_D64 + 20157U, // TRUNC_W_MM + 23331U, // TRUNC_W_S + 23331U, // TRUNC_W_S_MM + 33578032U, // TTLTIU + 25597U, // UDIV + 25597U, // UDIV_MM + 134241335U, // V3MULU + 134234135U, // VMM0 + 134241350U, // VMULU + 151012022U, // VSHF_B + 151013760U, // VSHF_D + 151015430U, // VSHF_H + 151018984U, // VSHF_W + 9486U, // WAIT + 547767U, // WAIT_MM + 33577010U, // WRDSP + 21376U, // WSBH + 21376U, // WSBH_MM + 134240507U, // XOR + 836009U, // XOR16_MM + 134240507U, // XOR64 + 2281718581U, // XORI_B + 134240507U, // XOR_MM + 134241419U, // XOR_V + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 134239770U, // XORi + 134239770U, // XORi64 + 134239770U, // XORi_MM + 16799995U, // XorRxRxRy16 + 0U}; - static const uint8_t OpInfo2[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 0U, // DBG_VALUE - 0U, // REG_SEQUENCE - 0U, // COPY - 0U, // BUNDLE - 0U, // LIFETIME_START - 0U, // LIFETIME_END - 0U, // STACKMAP - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 0U, // ABSQ_S_PH - 0U, // ABSQ_S_QB - 0U, // ABSQ_S_W - 0U, // ADD - 0U, // ADDIUPC - 0U, // ADDIUPC_MM - 0U, // ADDIUR1SP_MM - 0U, // ADDIUR2_MM - 0U, // ADDIUS5_MM - 0U, // ADDIUSP_MM - 0U, // ADDQH_PH - 0U, // ADDQH_R_PH - 0U, // ADDQH_R_W - 0U, // ADDQH_W - 0U, // ADDQ_PH - 0U, // ADDQ_S_PH - 0U, // ADDQ_S_W - 0U, // ADDSC - 0U, // ADDS_A_B - 0U, // ADDS_A_D - 0U, // ADDS_A_H - 0U, // ADDS_A_W - 0U, // ADDS_S_B - 0U, // ADDS_S_D - 0U, // ADDS_S_H - 0U, // ADDS_S_W - 0U, // ADDS_U_B - 0U, // ADDS_U_D - 0U, // ADDS_U_H - 0U, // ADDS_U_W - 0U, // ADDU16_MM - 0U, // ADDUH_QB - 0U, // ADDUH_R_QB - 0U, // ADDU_PH - 0U, // ADDU_QB - 0U, // ADDU_S_PH - 0U, // ADDU_S_QB - 0U, // ADDVI_B - 0U, // ADDVI_D - 0U, // ADDVI_H - 0U, // ADDVI_W - 0U, // ADDV_B - 0U, // ADDV_D - 0U, // ADDV_H - 0U, // ADDV_W - 0U, // ADDWC - 0U, // ADD_A_B - 0U, // ADD_A_D - 0U, // ADD_A_H - 0U, // ADD_A_W - 0U, // ADD_MM - 0U, // ADDi - 0U, // ADDi_MM - 0U, // ADDiu - 0U, // ADDiu_MM - 0U, // ADDu - 0U, // ADDu_MM - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 4U, // ALIGN - 0U, // ALUIPC - 0U, // AND - 0U, // AND16_MM - 0U, // AND64 - 0U, // ANDI16_MM - 0U, // ANDI_B - 0U, // AND_MM - 0U, // AND_V - 0U, // AND_V_D_PSEUDO - 0U, // AND_V_H_PSEUDO - 0U, // AND_V_W_PSEUDO - 1U, // ANDi - 1U, // ANDi64 - 1U, // ANDi_MM - 1U, // APPEND - 0U, // ASUB_S_B - 0U, // ASUB_S_D - 0U, // ASUB_S_H - 0U, // ASUB_S_W - 0U, // ASUB_U_B - 0U, // ASUB_U_D - 0U, // ASUB_U_H - 0U, // ASUB_U_W - 0U, // ATOMIC_CMP_SWAP_I16 - 0U, // ATOMIC_CMP_SWAP_I32 - 0U, // ATOMIC_CMP_SWAP_I64 - 0U, // ATOMIC_CMP_SWAP_I8 - 0U, // ATOMIC_LOAD_ADD_I16 - 0U, // ATOMIC_LOAD_ADD_I32 - 0U, // ATOMIC_LOAD_ADD_I64 - 0U, // ATOMIC_LOAD_ADD_I8 - 0U, // ATOMIC_LOAD_AND_I16 - 0U, // ATOMIC_LOAD_AND_I32 - 0U, // ATOMIC_LOAD_AND_I64 - 0U, // ATOMIC_LOAD_AND_I8 - 0U, // ATOMIC_LOAD_NAND_I16 - 0U, // ATOMIC_LOAD_NAND_I32 - 0U, // ATOMIC_LOAD_NAND_I64 - 0U, // ATOMIC_LOAD_NAND_I8 - 0U, // ATOMIC_LOAD_OR_I16 - 0U, // ATOMIC_LOAD_OR_I32 - 0U, // ATOMIC_LOAD_OR_I64 - 0U, // ATOMIC_LOAD_OR_I8 - 0U, // ATOMIC_LOAD_SUB_I16 - 0U, // ATOMIC_LOAD_SUB_I32 - 0U, // ATOMIC_LOAD_SUB_I64 - 0U, // ATOMIC_LOAD_SUB_I8 - 0U, // ATOMIC_LOAD_XOR_I16 - 0U, // ATOMIC_LOAD_XOR_I32 - 0U, // ATOMIC_LOAD_XOR_I64 - 0U, // ATOMIC_LOAD_XOR_I8 - 0U, // ATOMIC_SWAP_I16 - 0U, // ATOMIC_SWAP_I32 - 0U, // ATOMIC_SWAP_I64 - 0U, // ATOMIC_SWAP_I8 - 0U, // AUI - 0U, // AUIPC - 0U, // AVER_S_B - 0U, // AVER_S_D - 0U, // AVER_S_H - 0U, // AVER_S_W - 0U, // AVER_U_B - 0U, // AVER_U_D - 0U, // AVER_U_H - 0U, // AVER_U_W - 0U, // AVE_S_B - 0U, // AVE_S_D - 0U, // AVE_S_H - 0U, // AVE_S_W - 0U, // AVE_U_B - 0U, // AVE_U_D - 0U, // AVE_U_H - 0U, // AVE_U_W - 0U, // AddiuRxImmX16 - 0U, // AddiuRxPcImmX16 - 0U, // AddiuRxRxImm16 - 0U, // AddiuRxRxImmX16 - 0U, // AddiuRxRyOffMemX16 - 0U, // AddiuSpImm16 - 0U, // AddiuSpImmX16 - 0U, // AdduRxRyRz16 - 0U, // AndRxRxRy16 - 0U, // B - 0U, // B16_MM - 0U, // BADDu - 0U, // BAL - 0U, // BALC - 1U, // BALIGN - 0U, // BAL_BR - 0U, // BBIT0 - 0U, // BBIT032 - 0U, // BBIT1 - 0U, // BBIT132 - 0U, // BC - 0U, // BC0F - 0U, // BC0FL - 0U, // BC0T - 0U, // BC0TL - 0U, // BC1EQZ - 0U, // BC1F - 0U, // BC1FL - 0U, // BC1F_MM - 0U, // BC1NEZ - 0U, // BC1T - 0U, // BC1TL - 0U, // BC1T_MM - 0U, // BC2EQZ - 0U, // BC2F - 0U, // BC2FL - 0U, // BC2NEZ - 0U, // BC2T - 0U, // BC2TL - 0U, // BC3F - 0U, // BC3FL - 0U, // BC3T - 0U, // BC3TL - 0U, // BCLRI_B - 0U, // BCLRI_D - 0U, // BCLRI_H - 0U, // BCLRI_W - 0U, // BCLR_B - 0U, // BCLR_D - 0U, // BCLR_H - 0U, // BCLR_W - 0U, // BEQ - 0U, // BEQ64 - 0U, // BEQC - 0U, // BEQL - 0U, // BEQZ16_MM - 0U, // BEQZALC - 0U, // BEQZC - 0U, // BEQZC_MM - 0U, // BEQ_MM - 0U, // BGEC - 0U, // BGEUC - 0U, // BGEZ - 0U, // BGEZ64 - 0U, // BGEZAL - 0U, // BGEZALC - 0U, // BGEZALL - 0U, // BGEZALS_MM - 0U, // BGEZAL_MM - 0U, // BGEZC - 0U, // BGEZL - 0U, // BGEZ_MM - 0U, // BGTZ - 0U, // BGTZ64 - 0U, // BGTZALC - 0U, // BGTZC - 0U, // BGTZL - 0U, // BGTZ_MM - 1U, // BINSLI_B - 1U, // BINSLI_D - 1U, // BINSLI_H - 1U, // BINSLI_W - 2U, // BINSL_B - 2U, // BINSL_D - 2U, // BINSL_H - 2U, // BINSL_W - 1U, // BINSRI_B - 1U, // BINSRI_D - 1U, // BINSRI_H - 1U, // BINSRI_W - 2U, // BINSR_B - 2U, // BINSR_D - 2U, // BINSR_H - 2U, // BINSR_W - 0U, // BITREV - 0U, // BITSWAP - 0U, // BLEZ - 0U, // BLEZ64 - 0U, // BLEZALC - 0U, // BLEZC - 0U, // BLEZL - 0U, // BLEZ_MM - 0U, // BLTC - 0U, // BLTUC - 0U, // BLTZ - 0U, // BLTZ64 - 0U, // BLTZAL - 0U, // BLTZALC - 0U, // BLTZALL - 0U, // BLTZALS_MM - 0U, // BLTZAL_MM - 0U, // BLTZC - 0U, // BLTZL - 0U, // BLTZ_MM - 1U, // BMNZI_B - 2U, // BMNZ_V - 1U, // BMZI_B - 2U, // BMZ_V - 0U, // BNE - 0U, // BNE64 - 0U, // BNEC - 0U, // BNEGI_B - 0U, // BNEGI_D - 0U, // BNEGI_H - 0U, // BNEGI_W - 0U, // BNEG_B - 0U, // BNEG_D - 0U, // BNEG_H - 0U, // BNEG_W - 0U, // BNEL - 0U, // BNEZ16_MM - 0U, // BNEZALC - 0U, // BNEZC - 0U, // BNEZC_MM - 0U, // BNE_MM - 0U, // BNVC - 0U, // BNZ_B - 0U, // BNZ_D - 0U, // BNZ_H - 0U, // BNZ_V - 0U, // BNZ_W - 0U, // BOVC - 0U, // BPOSGE32 - 0U, // BPOSGE32_PSEUDO - 0U, // BREAK - 0U, // BREAK16_MM - 0U, // BREAK_MM - 1U, // BSELI_B - 0U, // BSEL_D_PSEUDO - 0U, // BSEL_FD_PSEUDO - 0U, // BSEL_FW_PSEUDO - 0U, // BSEL_H_PSEUDO - 2U, // BSEL_V - 0U, // BSEL_W_PSEUDO - 0U, // BSETI_B - 0U, // BSETI_D - 0U, // BSETI_H - 0U, // BSETI_W - 0U, // BSET_B - 0U, // BSET_D - 0U, // BSET_H - 0U, // BSET_W - 0U, // BZ_B - 0U, // BZ_D - 0U, // BZ_H - 0U, // BZ_V - 0U, // BZ_W - 0U, // B_MM_Pseudo - 0U, // BeqzRxImm16 - 0U, // BeqzRxImmX16 - 0U, // Bimm16 - 0U, // BimmX16 - 0U, // BnezRxImm16 - 0U, // BnezRxImmX16 - 0U, // Break16 - 0U, // Bteqz16 - 0U, // BteqzT8CmpX16 - 0U, // BteqzT8CmpiX16 - 0U, // BteqzT8SltX16 - 0U, // BteqzT8SltiX16 - 0U, // BteqzT8SltiuX16 - 0U, // BteqzT8SltuX16 - 0U, // BteqzX16 - 0U, // Btnez16 - 0U, // BtnezT8CmpX16 - 0U, // BtnezT8CmpiX16 - 0U, // BtnezT8SltX16 - 0U, // BtnezT8SltiX16 - 0U, // BtnezT8SltiuX16 - 0U, // BtnezT8SltuX16 - 0U, // BtnezX16 - 0U, // BuildPairF64 - 0U, // BuildPairF64_64 - 0U, // CACHE - 0U, // CACHE_MM - 0U, // CACHE_R6 - 0U, // CEIL_L_D64 - 0U, // CEIL_L_S - 0U, // CEIL_W_D32 - 0U, // CEIL_W_D64 - 0U, // CEIL_W_MM - 0U, // CEIL_W_S - 0U, // CEIL_W_S_MM - 0U, // CEQI_B - 0U, // CEQI_D - 0U, // CEQI_H - 0U, // CEQI_W - 0U, // CEQ_B - 0U, // CEQ_D - 0U, // CEQ_H - 0U, // CEQ_W - 0U, // CFC1 - 0U, // CFC1_MM - 0U, // CFCMSA - 5U, // CINS - 5U, // CINS32 - 0U, // CLASS_D - 0U, // CLASS_S - 0U, // CLEI_S_B - 0U, // CLEI_S_D - 0U, // CLEI_S_H - 0U, // CLEI_S_W - 0U, // CLEI_U_B - 0U, // CLEI_U_D - 0U, // CLEI_U_H - 0U, // CLEI_U_W - 0U, // CLE_S_B - 0U, // CLE_S_D - 0U, // CLE_S_H - 0U, // CLE_S_W - 0U, // CLE_U_B - 0U, // CLE_U_D - 0U, // CLE_U_H - 0U, // CLE_U_W - 0U, // CLO - 0U, // CLO_MM - 0U, // CLO_R6 - 0U, // CLTI_S_B - 0U, // CLTI_S_D - 0U, // CLTI_S_H - 0U, // CLTI_S_W - 0U, // CLTI_U_B - 0U, // CLTI_U_D - 0U, // CLTI_U_H - 0U, // CLTI_U_W - 0U, // CLT_S_B - 0U, // CLT_S_D - 0U, // CLT_S_H - 0U, // CLT_S_W - 0U, // CLT_U_B - 0U, // CLT_U_D - 0U, // CLT_U_H - 0U, // CLT_U_W - 0U, // CLZ - 0U, // CLZ_MM - 0U, // CLZ_R6 - 0U, // CMPGDU_EQ_QB - 0U, // CMPGDU_LE_QB - 0U, // CMPGDU_LT_QB - 0U, // CMPGU_EQ_QB - 0U, // CMPGU_LE_QB - 0U, // CMPGU_LT_QB - 0U, // CMPU_EQ_QB - 0U, // CMPU_LE_QB - 0U, // CMPU_LT_QB - 0U, // CMP_EQ_D - 0U, // CMP_EQ_PH - 0U, // CMP_EQ_S - 0U, // CMP_F_D - 0U, // CMP_F_S - 0U, // CMP_LE_D - 0U, // CMP_LE_PH - 0U, // CMP_LE_S - 0U, // CMP_LT_D - 0U, // CMP_LT_PH - 0U, // CMP_LT_S - 0U, // CMP_SAF_D - 0U, // CMP_SAF_S - 0U, // CMP_SEQ_D - 0U, // CMP_SEQ_S - 0U, // CMP_SLE_D - 0U, // CMP_SLE_S - 0U, // CMP_SLT_D - 0U, // CMP_SLT_S - 0U, // CMP_SUEQ_D - 0U, // CMP_SUEQ_S - 0U, // CMP_SULE_D - 0U, // CMP_SULE_S - 0U, // CMP_SULT_D - 0U, // CMP_SULT_S - 0U, // CMP_SUN_D - 0U, // CMP_SUN_S - 0U, // CMP_UEQ_D - 0U, // CMP_UEQ_S - 0U, // CMP_ULE_D - 0U, // CMP_ULE_S - 0U, // CMP_ULT_D - 0U, // CMP_ULT_S - 0U, // CMP_UN_D - 0U, // CMP_UN_S - 0U, // CONSTPOOL_ENTRY - 0U, // COPY_FD_PSEUDO - 0U, // COPY_FW_PSEUDO - 8U, // COPY_S_B - 8U, // COPY_S_D - 8U, // COPY_S_H - 8U, // COPY_S_W - 8U, // COPY_U_B - 8U, // COPY_U_D - 8U, // COPY_U_H - 8U, // COPY_U_W - 0U, // CTC1 - 0U, // CTC1_MM - 0U, // CTCMSA - 0U, // CVT_D32_S - 0U, // CVT_D32_W - 0U, // CVT_D32_W_MM - 0U, // CVT_D64_L - 0U, // CVT_D64_S - 0U, // CVT_D64_W - 0U, // CVT_D_S_MM - 0U, // CVT_L_D64 - 0U, // CVT_L_D64_MM - 0U, // CVT_L_S - 0U, // CVT_L_S_MM - 0U, // CVT_S_D32 - 0U, // CVT_S_D32_MM - 0U, // CVT_S_D64 - 0U, // CVT_S_L - 0U, // CVT_S_W - 0U, // CVT_S_W_MM - 0U, // CVT_W_D32 - 0U, // CVT_W_D64 - 0U, // CVT_W_MM - 0U, // CVT_W_S - 0U, // CVT_W_S_MM - 0U, // C_EQ_D32 - 0U, // C_EQ_D64 - 0U, // C_EQ_S - 0U, // C_F_D32 - 0U, // C_F_D64 - 0U, // C_F_S - 0U, // C_LE_D32 - 0U, // C_LE_D64 - 0U, // C_LE_S - 0U, // C_LT_D32 - 0U, // C_LT_D64 - 0U, // C_LT_S - 0U, // C_NGE_D32 - 0U, // C_NGE_D64 - 0U, // C_NGE_S - 0U, // C_NGLE_D32 - 0U, // C_NGLE_D64 - 0U, // C_NGLE_S - 0U, // C_NGL_D32 - 0U, // C_NGL_D64 - 0U, // C_NGL_S - 0U, // C_NGT_D32 - 0U, // C_NGT_D64 - 0U, // C_NGT_S - 0U, // C_OLE_D32 - 0U, // C_OLE_D64 - 0U, // C_OLE_S - 0U, // C_OLT_D32 - 0U, // C_OLT_D64 - 0U, // C_OLT_S - 0U, // C_SEQ_D32 - 0U, // C_SEQ_D64 - 0U, // C_SEQ_S - 0U, // C_SF_D32 - 0U, // C_SF_D64 - 0U, // C_SF_S - 0U, // C_UEQ_D32 - 0U, // C_UEQ_D64 - 0U, // C_UEQ_S - 0U, // C_ULE_D32 - 0U, // C_ULE_D64 - 0U, // C_ULE_S - 0U, // C_ULT_D32 - 0U, // C_ULT_D64 - 0U, // C_ULT_S - 0U, // C_UN_D32 - 0U, // C_UN_D64 - 0U, // C_UN_S - 0U, // CmpRxRy16 - 0U, // CmpiRxImm16 - 0U, // CmpiRxImmX16 - 0U, // Constant32 - 0U, // DADD - 0U, // DADDi - 0U, // DADDiu - 0U, // DADDu - 0U, // DAHI - 4U, // DALIGN - 0U, // DATI - 0U, // DAUI - 0U, // DBITSWAP - 0U, // DCLO - 0U, // DCLO_R6 - 0U, // DCLZ - 0U, // DCLZ_R6 - 0U, // DDIV - 0U, // DDIVU - 0U, // DERET - 0U, // DERET_MM - 21U, // DEXT - 21U, // DEXTM - 21U, // DEXTU - 0U, // DI - 21U, // DINS - 21U, // DINSM - 21U, // DINSU - 0U, // DIV - 0U, // DIVU - 0U, // DIV_S_B - 0U, // DIV_S_D - 0U, // DIV_S_H - 0U, // DIV_S_W - 0U, // DIV_U_B - 0U, // DIV_U_D - 0U, // DIV_U_H - 0U, // DIV_U_W - 0U, // DI_MM - 4U, // DLSA - 4U, // DLSA_R6 - 1U, // DMFC0 - 0U, // DMFC1 - 1U, // DMFC2 - 0U, // DMOD - 0U, // DMODU - 1U, // DMTC0 - 0U, // DMTC1 - 1U, // DMTC2 - 0U, // DMUH - 0U, // DMUHU - 0U, // DMUL - 0U, // DMULT - 0U, // DMULTu - 0U, // DMULU - 0U, // DMUL_R6 - 0U, // DOTP_S_D - 0U, // DOTP_S_H - 0U, // DOTP_S_W - 0U, // DOTP_U_D - 0U, // DOTP_U_H - 0U, // DOTP_U_W - 2U, // DPADD_S_D - 2U, // DPADD_S_H - 2U, // DPADD_S_W - 2U, // DPADD_U_D - 2U, // DPADD_U_H - 2U, // DPADD_U_W - 0U, // DPAQX_SA_W_PH - 0U, // DPAQX_S_W_PH - 0U, // DPAQ_SA_L_W - 0U, // DPAQ_S_W_PH - 0U, // DPAU_H_QBL - 0U, // DPAU_H_QBR - 0U, // DPAX_W_PH - 0U, // DPA_W_PH - 0U, // DPOP - 0U, // DPSQX_SA_W_PH - 0U, // DPSQX_S_W_PH - 0U, // DPSQ_SA_L_W - 0U, // DPSQ_S_W_PH - 2U, // DPSUB_S_D - 2U, // DPSUB_S_H - 2U, // DPSUB_S_W - 2U, // DPSUB_U_D - 2U, // DPSUB_U_H - 2U, // DPSUB_U_W - 0U, // DPSU_H_QBL - 0U, // DPSU_H_QBR - 0U, // DPSX_W_PH - 0U, // DPS_W_PH - 1U, // DROTR - 1U, // DROTR32 - 0U, // DROTRV - 0U, // DSBH - 0U, // DSDIV - 0U, // DSHD - 1U, // DSLL - 1U, // DSLL32 - 0U, // DSLL64_32 - 0U, // DSLLV - 1U, // DSRA - 1U, // DSRA32 - 0U, // DSRAV - 1U, // DSRL - 1U, // DSRL32 - 0U, // DSRLV - 0U, // DSUB - 0U, // DSUBu - 0U, // DUDIV - 0U, // DivRxRy16 - 0U, // DivuRxRy16 - 0U, // EHB - 0U, // EHB_MM - 0U, // EI - 0U, // EI_MM - 0U, // ERET - 0U, // ERET_MM - 21U, // EXT - 1U, // EXTP - 1U, // EXTPDP - 0U, // EXTPDPV - 0U, // EXTPV - 0U, // EXTRV_RS_W - 0U, // EXTRV_R_W - 0U, // EXTRV_S_H - 0U, // EXTRV_W - 1U, // EXTR_RS_W - 1U, // EXTR_R_W - 1U, // EXTR_S_H - 1U, // EXTR_W - 5U, // EXTS - 5U, // EXTS32 - 21U, // EXT_MM - 0U, // ExtractElementF64 - 0U, // ExtractElementF64_64 - 0U, // FABS_D - 0U, // FABS_D32 - 0U, // FABS_D64 - 0U, // FABS_MM - 0U, // FABS_S - 0U, // FABS_S_MM - 0U, // FABS_W - 0U, // FADD_D - 0U, // FADD_D32 - 0U, // FADD_D64 - 0U, // FADD_MM - 0U, // FADD_S - 0U, // FADD_S_MM - 0U, // FADD_W - 0U, // FCAF_D - 0U, // FCAF_W - 0U, // FCEQ_D - 0U, // FCEQ_W - 0U, // FCLASS_D - 0U, // FCLASS_W - 0U, // FCLE_D - 0U, // FCLE_W - 0U, // FCLT_D - 0U, // FCLT_W - 0U, // FCMP_D32 - 0U, // FCMP_D32_MM - 0U, // FCMP_D64 - 0U, // FCMP_S32 - 0U, // FCMP_S32_MM - 0U, // FCNE_D - 0U, // FCNE_W - 0U, // FCOR_D - 0U, // FCOR_W - 0U, // FCUEQ_D - 0U, // FCUEQ_W - 0U, // FCULE_D - 0U, // FCULE_W - 0U, // FCULT_D - 0U, // FCULT_W - 0U, // FCUNE_D - 0U, // FCUNE_W - 0U, // FCUN_D - 0U, // FCUN_W - 0U, // FDIV_D - 0U, // FDIV_D32 - 0U, // FDIV_D64 - 0U, // FDIV_MM - 0U, // FDIV_S - 0U, // FDIV_S_MM - 0U, // FDIV_W - 0U, // FEXDO_H - 0U, // FEXDO_W - 0U, // FEXP2_D - 0U, // FEXP2_D_1_PSEUDO - 0U, // FEXP2_W - 0U, // FEXP2_W_1_PSEUDO - 0U, // FEXUPL_D - 0U, // FEXUPL_W - 0U, // FEXUPR_D - 0U, // FEXUPR_W - 0U, // FFINT_S_D - 0U, // FFINT_S_W - 0U, // FFINT_U_D - 0U, // FFINT_U_W - 0U, // FFQL_D - 0U, // FFQL_W - 0U, // FFQR_D - 0U, // FFQR_W - 0U, // FILL_B - 0U, // FILL_D - 0U, // FILL_FD_PSEUDO - 0U, // FILL_FW_PSEUDO - 0U, // FILL_H - 0U, // FILL_W - 0U, // FLOG2_D - 0U, // FLOG2_W - 0U, // FLOOR_L_D64 - 0U, // FLOOR_L_S - 0U, // FLOOR_W_D32 - 0U, // FLOOR_W_D64 - 0U, // FLOOR_W_MM - 0U, // FLOOR_W_S - 0U, // FLOOR_W_S_MM - 2U, // FMADD_D - 2U, // FMADD_W - 0U, // FMAX_A_D - 0U, // FMAX_A_W - 0U, // FMAX_D - 0U, // FMAX_W - 0U, // FMIN_A_D - 0U, // FMIN_A_W - 0U, // FMIN_D - 0U, // FMIN_W - 0U, // FMOV_D32 - 0U, // FMOV_D32_MM - 0U, // FMOV_D64 - 0U, // FMOV_S - 0U, // FMOV_S_MM - 2U, // FMSUB_D - 2U, // FMSUB_W - 0U, // FMUL_D - 0U, // FMUL_D32 - 0U, // FMUL_D64 - 0U, // FMUL_MM - 0U, // FMUL_S - 0U, // FMUL_S_MM - 0U, // FMUL_W - 0U, // FNEG_D32 - 0U, // FNEG_D64 - 0U, // FNEG_MM - 0U, // FNEG_S - 0U, // FNEG_S_MM - 0U, // FRCP_D - 0U, // FRCP_W - 0U, // FRINT_D - 0U, // FRINT_W - 0U, // FRSQRT_D - 0U, // FRSQRT_W - 0U, // FSAF_D - 0U, // FSAF_W - 0U, // FSEQ_D - 0U, // FSEQ_W - 0U, // FSLE_D - 0U, // FSLE_W - 0U, // FSLT_D - 0U, // FSLT_W - 0U, // FSNE_D - 0U, // FSNE_W - 0U, // FSOR_D - 0U, // FSOR_W - 0U, // FSQRT_D - 0U, // FSQRT_D32 - 0U, // FSQRT_D64 - 0U, // FSQRT_MM - 0U, // FSQRT_S - 0U, // FSQRT_S_MM - 0U, // FSQRT_W - 0U, // FSUB_D - 0U, // FSUB_D32 - 0U, // FSUB_D64 - 0U, // FSUB_MM - 0U, // FSUB_S - 0U, // FSUB_S_MM - 0U, // FSUB_W - 0U, // FSUEQ_D - 0U, // FSUEQ_W - 0U, // FSULE_D - 0U, // FSULE_W - 0U, // FSULT_D - 0U, // FSULT_W - 0U, // FSUNE_D - 0U, // FSUNE_W - 0U, // FSUN_D - 0U, // FSUN_W - 0U, // FTINT_S_D - 0U, // FTINT_S_W - 0U, // FTINT_U_D - 0U, // FTINT_U_W - 0U, // FTQ_H - 0U, // FTQ_W - 0U, // FTRUNC_S_D - 0U, // FTRUNC_S_W - 0U, // FTRUNC_U_D - 0U, // FTRUNC_U_W - 0U, // GotPrologue16 - 0U, // HADD_S_D - 0U, // HADD_S_H - 0U, // HADD_S_W - 0U, // HADD_U_D - 0U, // HADD_U_H - 0U, // HADD_U_W - 0U, // HSUB_S_D - 0U, // HSUB_S_H - 0U, // HSUB_S_W - 0U, // HSUB_U_D - 0U, // HSUB_U_H - 0U, // HSUB_U_W - 0U, // ILVEV_B - 0U, // ILVEV_D - 0U, // ILVEV_H - 0U, // ILVEV_W - 0U, // ILVL_B - 0U, // ILVL_D - 0U, // ILVL_H - 0U, // ILVL_W - 0U, // ILVOD_B - 0U, // ILVOD_D - 0U, // ILVOD_H - 0U, // ILVOD_W - 0U, // ILVR_B - 0U, // ILVR_D - 0U, // ILVR_H - 0U, // ILVR_W - 21U, // INS - 0U, // INSERT_B - 0U, // INSERT_B_VIDX_PSEUDO - 0U, // INSERT_D - 0U, // INSERT_D_VIDX_PSEUDO - 0U, // INSERT_FD_PSEUDO - 0U, // INSERT_FD_VIDX_PSEUDO - 0U, // INSERT_FW_PSEUDO - 0U, // INSERT_FW_VIDX_PSEUDO - 0U, // INSERT_H - 0U, // INSERT_H_VIDX_PSEUDO - 0U, // INSERT_W - 0U, // INSERT_W_VIDX_PSEUDO - 0U, // INSV - 0U, // INSVE_B - 0U, // INSVE_D - 0U, // INSVE_H - 0U, // INSVE_W - 21U, // INS_MM - 0U, // J - 0U, // JAL - 0U, // JALR - 0U, // JALR16_MM - 0U, // JALR64 - 0U, // JALR64Pseudo - 0U, // JALRPseudo - 0U, // JALRS16_MM - 0U, // JALRS_MM - 0U, // JALR_HB - 0U, // JALR_MM - 0U, // JALS_MM - 0U, // JALX - 0U, // JALX_MM - 0U, // JAL_MM - 0U, // JIALC - 0U, // JIC - 0U, // JR - 0U, // JR16_MM - 0U, // JR64 - 0U, // JRADDIUSP - 0U, // JRC16_MM - 0U, // JR_HB - 0U, // JR_HB_R6 - 0U, // JR_MM - 0U, // J_MM - 0U, // Jal16 - 0U, // JalB16 - 0U, // JalOneReg - 0U, // JalTwoReg - 0U, // JrRa16 - 0U, // JrcRa16 - 0U, // JrcRx16 - 0U, // JumpLinkReg16 - 0U, // LB - 0U, // LB64 - 0U, // LBU16_MM - 0U, // LBUX - 0U, // LB_MM - 0U, // LBu - 0U, // LBu64 - 0U, // LBu_MM - 0U, // LD - 0U, // LDC1 - 0U, // LDC164 - 0U, // LDC1_MM - 0U, // LDC2 - 0U, // LDC2_R6 - 0U, // LDC3 - 0U, // LDI_B - 0U, // LDI_D - 0U, // LDI_H - 0U, // LDI_W - 0U, // LDL - 0U, // LDPC - 0U, // LDR - 0U, // LDXC1 - 0U, // LDXC164 - 0U, // LD_B - 0U, // LD_D - 0U, // LD_H - 0U, // LD_W - 0U, // LEA_ADDiu - 0U, // LEA_ADDiu64 - 0U, // LEA_ADDiu_MM - 0U, // LH - 0U, // LH64 - 0U, // LHU16_MM - 0U, // LHX - 0U, // LH_MM - 0U, // LHu - 0U, // LHu64 - 0U, // LHu_MM - 0U, // LI16_MM - 0U, // LL - 0U, // LLD - 0U, // LLD_R6 - 0U, // LL_MM - 0U, // LL_R6 - 0U, // LOAD_ACC128 - 0U, // LOAD_ACC64 - 0U, // LOAD_ACC64DSP - 0U, // LOAD_CCOND_DSP - 0U, // LONG_BRANCH_ADDiu - 0U, // LONG_BRANCH_DADDiu - 0U, // LONG_BRANCH_LUi - 4U, // LSA - 4U, // LSA_R6 - 0U, // LUXC1 - 0U, // LUXC164 - 0U, // LUXC1_MM - 0U, // LUi - 0U, // LUi64 - 0U, // LUi_MM - 0U, // LW - 0U, // LW16_MM - 0U, // LW64 - 0U, // LWC1 - 0U, // LWC1_MM - 0U, // LWC2 - 0U, // LWC2_R6 - 0U, // LWC3 - 0U, // LWGP_MM - 0U, // LWL - 0U, // LWL64 - 0U, // LWL_MM - 0U, // LWM16_MM - 0U, // LWM32_MM - 0U, // LWM_MM - 0U, // LWPC - 0U, // LWP_MM - 0U, // LWR - 0U, // LWR64 - 0U, // LWR_MM - 0U, // LWSP_MM - 0U, // LWUPC - 0U, // LWU_MM - 0U, // LWX - 0U, // LWXC1 - 0U, // LWXC1_MM - 0U, // LWXS_MM - 0U, // LW_MM - 0U, // LWu - 0U, // LbRxRyOffMemX16 - 0U, // LbuRxRyOffMemX16 - 0U, // LhRxRyOffMemX16 - 0U, // LhuRxRyOffMemX16 - 0U, // LiRxImm16 - 0U, // LiRxImmAlignX16 - 0U, // LiRxImmX16 - 0U, // LoadAddr32Imm - 0U, // LoadAddr32Reg - 0U, // LoadImm32Reg - 0U, // LoadImm64Reg - 0U, // LwConstant32 - 0U, // LwRxPcTcp16 - 0U, // LwRxPcTcpX16 - 0U, // LwRxRyOffMemX16 - 0U, // LwRxSpImmX16 - 0U, // MADD - 2U, // MADDF_D - 2U, // MADDF_S - 2U, // MADDR_Q_H - 2U, // MADDR_Q_W - 0U, // MADDU - 0U, // MADDU_DSP - 0U, // MADDU_MM - 2U, // MADDV_B - 2U, // MADDV_D - 2U, // MADDV_H - 2U, // MADDV_W - 20U, // MADD_D32 - 20U, // MADD_D32_MM - 20U, // MADD_D64 - 0U, // MADD_DSP - 0U, // MADD_MM - 2U, // MADD_Q_H - 2U, // MADD_Q_W - 20U, // MADD_S - 20U, // MADD_S_MM - 0U, // MAQ_SA_W_PHL - 0U, // MAQ_SA_W_PHR - 0U, // MAQ_S_W_PHL - 0U, // MAQ_S_W_PHR - 0U, // MAXA_D - 0U, // MAXA_S - 0U, // MAXI_S_B - 0U, // MAXI_S_D - 0U, // MAXI_S_H - 0U, // MAXI_S_W - 0U, // MAXI_U_B - 0U, // MAXI_U_D - 0U, // MAXI_U_H - 0U, // MAXI_U_W - 0U, // MAX_A_B - 0U, // MAX_A_D - 0U, // MAX_A_H - 0U, // MAX_A_W - 0U, // MAX_D - 0U, // MAX_S - 0U, // MAX_S_B - 0U, // MAX_S_D - 0U, // MAX_S_H - 0U, // MAX_S_W - 0U, // MAX_U_B - 0U, // MAX_U_D - 0U, // MAX_U_H - 0U, // MAX_U_W - 1U, // MFC0 - 0U, // MFC1 - 0U, // MFC1_MM - 1U, // MFC2 - 0U, // MFHC1_D32 - 0U, // MFHC1_D64 - 0U, // MFHC1_MM - 0U, // MFHI - 0U, // MFHI16_MM - 0U, // MFHI64 - 0U, // MFHI_DSP - 0U, // MFHI_MM - 0U, // MFLO - 0U, // MFLO16_MM - 0U, // MFLO64 - 0U, // MFLO_DSP - 0U, // MFLO_MM - 0U, // MINA_D - 0U, // MINA_S - 0U, // MINI_S_B - 0U, // MINI_S_D - 0U, // MINI_S_H - 0U, // MINI_S_W - 0U, // MINI_U_B - 0U, // MINI_U_D - 0U, // MINI_U_H - 0U, // MINI_U_W - 0U, // MIN_A_B - 0U, // MIN_A_D - 0U, // MIN_A_H - 0U, // MIN_A_W - 0U, // MIN_D - 0U, // MIN_S - 0U, // MIN_S_B - 0U, // MIN_S_D - 0U, // MIN_S_H - 0U, // MIN_S_W - 0U, // MIN_U_B - 0U, // MIN_U_D - 0U, // MIN_U_H - 0U, // MIN_U_W - 0U, // MIPSeh_return32 - 0U, // MIPSeh_return64 - 0U, // MOD - 0U, // MODSUB - 0U, // MODU - 0U, // MOD_S_B - 0U, // MOD_S_D - 0U, // MOD_S_H - 0U, // MOD_S_W - 0U, // MOD_U_B - 0U, // MOD_U_D - 0U, // MOD_U_H - 0U, // MOD_U_W - 0U, // MOVE16_MM - 0U, // MOVEP_MM - 0U, // MOVE_V - 0U, // MOVF_D32 - 0U, // MOVF_D32_MM - 0U, // MOVF_D64 - 0U, // MOVF_I - 0U, // MOVF_I64 - 0U, // MOVF_I_MM - 0U, // MOVF_S - 0U, // MOVF_S_MM - 0U, // MOVN_I64_D64 - 0U, // MOVN_I64_I - 0U, // MOVN_I64_I64 - 0U, // MOVN_I64_S - 0U, // MOVN_I_D32 - 0U, // MOVN_I_D32_MM - 0U, // MOVN_I_D64 - 0U, // MOVN_I_I - 0U, // MOVN_I_I64 - 0U, // MOVN_I_MM - 0U, // MOVN_I_S - 0U, // MOVN_I_S_MM - 0U, // MOVT_D32 - 0U, // MOVT_D32_MM - 0U, // MOVT_D64 - 0U, // MOVT_I - 0U, // MOVT_I64 - 0U, // MOVT_I_MM - 0U, // MOVT_S - 0U, // MOVT_S_MM - 0U, // MOVZ_I64_D64 - 0U, // MOVZ_I64_I - 0U, // MOVZ_I64_I64 - 0U, // MOVZ_I64_S - 0U, // MOVZ_I_D32 - 0U, // MOVZ_I_D32_MM - 0U, // MOVZ_I_D64 - 0U, // MOVZ_I_I - 0U, // MOVZ_I_I64 - 0U, // MOVZ_I_MM - 0U, // MOVZ_I_S - 0U, // MOVZ_I_S_MM - 0U, // MSUB - 2U, // MSUBF_D - 2U, // MSUBF_S - 2U, // MSUBR_Q_H - 2U, // MSUBR_Q_W - 0U, // MSUBU - 0U, // MSUBU_DSP - 0U, // MSUBU_MM - 2U, // MSUBV_B - 2U, // MSUBV_D - 2U, // MSUBV_H - 2U, // MSUBV_W - 20U, // MSUB_D32 - 20U, // MSUB_D32_MM - 20U, // MSUB_D64 - 0U, // MSUB_DSP - 0U, // MSUB_MM - 2U, // MSUB_Q_H - 2U, // MSUB_Q_W - 20U, // MSUB_S - 20U, // MSUB_S_MM - 1U, // MTC0 - 0U, // MTC1 - 0U, // MTC1_MM - 1U, // MTC2 - 0U, // MTHC1_D32 - 0U, // MTHC1_D64 - 0U, // MTHC1_MM - 0U, // MTHI - 0U, // MTHI64 - 0U, // MTHI_DSP - 0U, // MTHI_MM - 0U, // MTHLIP - 0U, // MTLO - 0U, // MTLO64 - 0U, // MTLO_DSP - 0U, // MTLO_MM - 0U, // MTM0 - 0U, // MTM1 - 0U, // MTM2 - 0U, // MTP0 - 0U, // MTP1 - 0U, // MTP2 - 0U, // MUH - 0U, // MUHU - 0U, // MUL - 0U, // MULEQ_S_W_PHL - 0U, // MULEQ_S_W_PHR - 0U, // MULEU_S_PH_QBL - 0U, // MULEU_S_PH_QBR - 0U, // MULQ_RS_PH - 0U, // MULQ_RS_W - 0U, // MULQ_S_PH - 0U, // MULQ_S_W - 0U, // MULR_Q_H - 0U, // MULR_Q_W - 0U, // MULSAQ_S_W_PH - 0U, // MULSA_W_PH - 0U, // MULT - 0U, // MULTU_DSP - 0U, // MULT_DSP - 0U, // MULT_MM - 0U, // MULTu - 0U, // MULTu_MM - 0U, // MULU - 0U, // MULV_B - 0U, // MULV_D - 0U, // MULV_H - 0U, // MULV_W - 0U, // MUL_MM - 0U, // MUL_PH - 0U, // MUL_Q_H - 0U, // MUL_Q_W - 0U, // MUL_R6 - 0U, // MUL_S_PH - 0U, // Mfhi16 - 0U, // Mflo16 - 0U, // Move32R16 - 0U, // MoveR3216 - 0U, // MultRxRy16 - 0U, // MultRxRyRz16 - 0U, // MultuRxRy16 - 0U, // MultuRxRyRz16 - 0U, // NLOC_B - 0U, // NLOC_D - 0U, // NLOC_H - 0U, // NLOC_W - 0U, // NLZC_B - 0U, // NLZC_D - 0U, // NLZC_H - 0U, // NLZC_W - 20U, // NMADD_D32 - 20U, // NMADD_D32_MM - 20U, // NMADD_D64 - 20U, // NMADD_S - 20U, // NMADD_S_MM - 20U, // NMSUB_D32 - 20U, // NMSUB_D32_MM - 20U, // NMSUB_D64 - 20U, // NMSUB_S - 20U, // NMSUB_S_MM - 0U, // NOP - 0U, // NOR - 0U, // NOR64 - 0U, // NORI_B - 0U, // NOR_MM - 0U, // NOR_V - 0U, // NOR_V_D_PSEUDO - 0U, // NOR_V_H_PSEUDO - 0U, // NOR_V_W_PSEUDO - 0U, // NOT16_MM - 0U, // NegRxRy16 - 0U, // NotRxRy16 - 0U, // OR - 0U, // OR16_MM - 0U, // OR64 - 0U, // ORI_B - 0U, // OR_MM - 0U, // OR_V - 0U, // OR_V_D_PSEUDO - 0U, // OR_V_H_PSEUDO - 0U, // OR_V_W_PSEUDO - 1U, // ORi - 1U, // ORi64 - 1U, // ORi_MM - 0U, // OrRxRxRy16 - 0U, // PACKRL_PH - 0U, // PAUSE - 0U, // PAUSE_MM - 0U, // PCKEV_B - 0U, // PCKEV_D - 0U, // PCKEV_H - 0U, // PCKEV_W - 0U, // PCKOD_B - 0U, // PCKOD_D - 0U, // PCKOD_H - 0U, // PCKOD_W - 0U, // PCNT_B - 0U, // PCNT_D - 0U, // PCNT_H - 0U, // PCNT_W - 0U, // PICK_PH - 0U, // PICK_QB - 0U, // POP - 0U, // PRECEQU_PH_QBL - 0U, // PRECEQU_PH_QBLA - 0U, // PRECEQU_PH_QBR - 0U, // PRECEQU_PH_QBRA - 0U, // PRECEQ_W_PHL - 0U, // PRECEQ_W_PHR - 0U, // PRECEU_PH_QBL - 0U, // PRECEU_PH_QBLA - 0U, // PRECEU_PH_QBR - 0U, // PRECEU_PH_QBRA - 0U, // PRECRQU_S_QB_PH - 0U, // PRECRQ_PH_W - 0U, // PRECRQ_QB_PH - 0U, // PRECRQ_RS_PH_W - 0U, // PRECR_QB_PH - 1U, // PRECR_SRA_PH_W - 1U, // PRECR_SRA_R_PH_W - 0U, // PREF - 0U, // PREF_MM - 0U, // PREF_R6 - 1U, // PREPEND - 0U, // PseudoCMPU_EQ_QB - 0U, // PseudoCMPU_LE_QB - 0U, // PseudoCMPU_LT_QB - 0U, // PseudoCMP_EQ_PH - 0U, // PseudoCMP_LE_PH - 0U, // PseudoCMP_LT_PH - 0U, // PseudoCVT_D32_W - 0U, // PseudoCVT_D64_L - 0U, // PseudoCVT_D64_W - 0U, // PseudoCVT_S_L - 0U, // PseudoCVT_S_W - 0U, // PseudoDMULT - 0U, // PseudoDMULTu - 0U, // PseudoDSDIV - 0U, // PseudoDUDIV - 0U, // PseudoIndirectBranch - 0U, // PseudoIndirectBranch64 - 0U, // PseudoMADD - 0U, // PseudoMADDU - 0U, // PseudoMFHI - 0U, // PseudoMFHI64 - 0U, // PseudoMFLO - 0U, // PseudoMFLO64 - 0U, // PseudoMSUB - 0U, // PseudoMSUBU - 0U, // PseudoMTLOHI - 0U, // PseudoMTLOHI64 - 0U, // PseudoMTLOHI_DSP - 0U, // PseudoMULT - 0U, // PseudoMULTu - 0U, // PseudoPICK_PH - 0U, // PseudoPICK_QB - 0U, // PseudoReturn - 0U, // PseudoReturn64 - 0U, // PseudoSDIV - 0U, // PseudoSELECTFP_F_D32 - 0U, // PseudoSELECTFP_F_D64 - 0U, // PseudoSELECTFP_F_I - 0U, // PseudoSELECTFP_F_I64 - 0U, // PseudoSELECTFP_F_S - 0U, // PseudoSELECTFP_T_D32 - 0U, // PseudoSELECTFP_T_D64 - 0U, // PseudoSELECTFP_T_I - 0U, // PseudoSELECTFP_T_I64 - 0U, // PseudoSELECTFP_T_S - 0U, // PseudoSELECT_D32 - 0U, // PseudoSELECT_D64 - 0U, // PseudoSELECT_I - 0U, // PseudoSELECT_I64 - 0U, // PseudoSELECT_S - 0U, // PseudoUDIV - 0U, // RADDU_W_QB - 0U, // RDDSP - 0U, // RDHWR - 0U, // RDHWR64 - 0U, // RDHWR_MM - 0U, // REPLV_PH - 0U, // REPLV_QB - 0U, // REPL_PH - 0U, // REPL_QB - 0U, // RINT_D - 0U, // RINT_S - 1U, // ROTR - 0U, // ROTRV - 0U, // ROTRV_MM - 1U, // ROTR_MM - 0U, // ROUND_L_D64 - 0U, // ROUND_L_S - 0U, // ROUND_W_D32 - 0U, // ROUND_W_D64 - 0U, // ROUND_W_MM - 0U, // ROUND_W_S - 0U, // ROUND_W_S_MM - 0U, // Restore16 - 0U, // RestoreX16 - 0U, // RetRA - 0U, // RetRA16 - 1U, // SAT_S_B - 1U, // SAT_S_D - 0U, // SAT_S_H - 1U, // SAT_S_W - 1U, // SAT_U_B - 1U, // SAT_U_D - 0U, // SAT_U_H - 1U, // SAT_U_W - 0U, // SB - 0U, // SB16_MM - 0U, // SB64 - 0U, // SB_MM - 0U, // SC - 0U, // SCD - 0U, // SCD_R6 - 0U, // SC_MM - 0U, // SC_R6 - 0U, // SD - 0U, // SDBBP - 0U, // SDBBP16_MM - 0U, // SDBBP_MM - 0U, // SDBBP_R6 - 0U, // SDC1 - 0U, // SDC164 - 0U, // SDC1_MM - 0U, // SDC2 - 0U, // SDC2_R6 - 0U, // SDC3 - 0U, // SDIV - 0U, // SDIV_MM - 0U, // SDL - 0U, // SDR - 0U, // SDXC1 - 0U, // SDXC164 - 0U, // SEB - 0U, // SEB64 - 0U, // SEB_MM - 0U, // SEH - 0U, // SEH64 - 0U, // SEH_MM - 0U, // SELEQZ - 0U, // SELEQZ64 - 0U, // SELEQZ_D - 0U, // SELEQZ_S - 0U, // SELNEZ - 0U, // SELNEZ64 - 0U, // SELNEZ_D - 0U, // SELNEZ_S - 2U, // SEL_D - 2U, // SEL_S - 0U, // SEQ - 0U, // SEQi - 0U, // SH - 0U, // SH16_MM - 0U, // SH64 - 0U, // SHF_B - 0U, // SHF_H - 0U, // SHF_W - 0U, // SHILO - 0U, // SHILOV - 0U, // SHLLV_PH - 0U, // SHLLV_QB - 0U, // SHLLV_S_PH - 0U, // SHLLV_S_W - 1U, // SHLL_PH - 1U, // SHLL_QB - 1U, // SHLL_S_PH - 1U, // SHLL_S_W - 0U, // SHRAV_PH - 0U, // SHRAV_QB - 0U, // SHRAV_R_PH - 0U, // SHRAV_R_QB - 0U, // SHRAV_R_W - 1U, // SHRA_PH - 1U, // SHRA_QB - 1U, // SHRA_R_PH - 1U, // SHRA_R_QB - 1U, // SHRA_R_W - 0U, // SHRLV_PH - 0U, // SHRLV_QB - 1U, // SHRL_PH - 1U, // SHRL_QB - 0U, // SH_MM - 9U, // SLDI_B - 9U, // SLDI_D - 9U, // SLDI_H - 9U, // SLDI_W - 10U, // SLD_B - 10U, // SLD_D - 10U, // SLD_H - 10U, // SLD_W - 1U, // SLL - 0U, // SLL16_MM - 0U, // SLL64_32 - 0U, // SLL64_64 - 0U, // SLLI_B - 0U, // SLLI_D - 0U, // SLLI_H - 0U, // SLLI_W - 0U, // SLLV - 0U, // SLLV_MM - 0U, // SLL_B - 0U, // SLL_D - 0U, // SLL_H - 1U, // SLL_MM - 0U, // SLL_W - 0U, // SLT - 0U, // SLT64 - 0U, // SLT_MM - 0U, // SLTi - 0U, // SLTi64 - 0U, // SLTi_MM - 0U, // SLTiu - 0U, // SLTiu64 - 0U, // SLTiu_MM - 0U, // SLTu - 0U, // SLTu64 - 0U, // SLTu_MM - 0U, // SNE - 0U, // SNEi - 0U, // SNZ_B_PSEUDO - 0U, // SNZ_D_PSEUDO - 0U, // SNZ_H_PSEUDO - 0U, // SNZ_V_PSEUDO - 0U, // SNZ_W_PSEUDO - 8U, // SPLATI_B - 8U, // SPLATI_D - 8U, // SPLATI_H - 8U, // SPLATI_W - 8U, // SPLAT_B - 8U, // SPLAT_D - 8U, // SPLAT_H - 8U, // SPLAT_W - 1U, // SRA - 0U, // SRAI_B - 0U, // SRAI_D - 0U, // SRAI_H - 0U, // SRAI_W - 1U, // SRARI_B - 1U, // SRARI_D - 0U, // SRARI_H - 1U, // SRARI_W - 0U, // SRAR_B - 0U, // SRAR_D - 0U, // SRAR_H - 0U, // SRAR_W - 0U, // SRAV - 0U, // SRAV_MM - 0U, // SRA_B - 0U, // SRA_D - 0U, // SRA_H - 1U, // SRA_MM - 0U, // SRA_W - 1U, // SRL - 0U, // SRL16_MM - 0U, // SRLI_B - 0U, // SRLI_D - 0U, // SRLI_H - 0U, // SRLI_W - 1U, // SRLRI_B - 1U, // SRLRI_D - 0U, // SRLRI_H - 1U, // SRLRI_W - 0U, // SRLR_B - 0U, // SRLR_D - 0U, // SRLR_H - 0U, // SRLR_W - 0U, // SRLV - 0U, // SRLV_MM - 0U, // SRL_B - 0U, // SRL_D - 0U, // SRL_H - 1U, // SRL_MM - 0U, // SRL_W - 0U, // SSNOP - 0U, // SSNOP_MM - 0U, // STORE_ACC128 - 0U, // STORE_ACC64 - 0U, // STORE_ACC64DSP - 0U, // STORE_CCOND_DSP - 0U, // ST_B - 0U, // ST_D - 0U, // ST_H - 0U, // ST_W - 0U, // SUB - 0U, // SUBQH_PH - 0U, // SUBQH_R_PH - 0U, // SUBQH_R_W - 0U, // SUBQH_W - 0U, // SUBQ_PH - 0U, // SUBQ_S_PH - 0U, // SUBQ_S_W - 0U, // SUBSUS_U_B - 0U, // SUBSUS_U_D - 0U, // SUBSUS_U_H - 0U, // SUBSUS_U_W - 0U, // SUBSUU_S_B - 0U, // SUBSUU_S_D - 0U, // SUBSUU_S_H - 0U, // SUBSUU_S_W - 0U, // SUBS_S_B - 0U, // SUBS_S_D - 0U, // SUBS_S_H - 0U, // SUBS_S_W - 0U, // SUBS_U_B - 0U, // SUBS_U_D - 0U, // SUBS_U_H - 0U, // SUBS_U_W - 0U, // SUBU16_MM - 0U, // SUBUH_QB - 0U, // SUBUH_R_QB - 0U, // SUBU_PH - 0U, // SUBU_QB - 0U, // SUBU_S_PH - 0U, // SUBU_S_QB - 0U, // SUBVI_B - 0U, // SUBVI_D - 0U, // SUBVI_H - 0U, // SUBVI_W - 0U, // SUBV_B - 0U, // SUBV_D - 0U, // SUBV_H - 0U, // SUBV_W - 0U, // SUB_MM - 0U, // SUBu - 0U, // SUBu_MM - 0U, // SUXC1 - 0U, // SUXC164 - 0U, // SUXC1_MM - 0U, // SW - 0U, // SW16_MM - 0U, // SW64 - 0U, // SWC1 - 0U, // SWC1_MM - 0U, // SWC2 - 0U, // SWC2_R6 - 0U, // SWC3 - 0U, // SWL - 0U, // SWL64 - 0U, // SWL_MM - 0U, // SWM16_MM - 0U, // SWM32_MM - 0U, // SWM_MM - 0U, // SWP_MM - 0U, // SWR - 0U, // SWR64 - 0U, // SWR_MM - 0U, // SWSP_MM - 0U, // SWXC1 - 0U, // SWXC1_MM - 0U, // SW_MM - 0U, // SYNC - 0U, // SYNCI - 0U, // SYNC_MM - 0U, // SYSCALL - 0U, // SYSCALL_MM - 0U, // SZ_B_PSEUDO - 0U, // SZ_D_PSEUDO - 0U, // SZ_H_PSEUDO - 0U, // SZ_V_PSEUDO - 0U, // SZ_W_PSEUDO - 0U, // Save16 - 0U, // SaveX16 - 0U, // SbRxRyOffMemX16 - 0U, // SebRx16 - 0U, // SehRx16 - 0U, // SelBeqZ - 0U, // SelBneZ - 0U, // SelTBteqZCmp - 0U, // SelTBteqZCmpi - 0U, // SelTBteqZSlt - 0U, // SelTBteqZSlti - 0U, // SelTBteqZSltiu - 0U, // SelTBteqZSltu - 0U, // SelTBtneZCmp - 0U, // SelTBtneZCmpi - 0U, // SelTBtneZSlt - 0U, // SelTBtneZSlti - 0U, // SelTBtneZSltiu - 0U, // SelTBtneZSltu - 0U, // ShRxRyOffMemX16 - 1U, // SllX16 - 0U, // SllvRxRy16 - 0U, // SltCCRxRy16 - 0U, // SltRxRy16 - 0U, // SltiCCRxImmX16 - 0U, // SltiRxImm16 - 0U, // SltiRxImmX16 - 0U, // SltiuCCRxImmX16 - 0U, // SltiuRxImm16 - 0U, // SltiuRxImmX16 - 0U, // SltuCCRxRy16 - 0U, // SltuRxRy16 - 0U, // SltuRxRyRz16 - 1U, // SraX16 - 0U, // SravRxRy16 - 1U, // SrlX16 - 0U, // SrlvRxRy16 - 0U, // SubuRxRyRz16 - 0U, // SwRxRyOffMemX16 - 0U, // SwRxSpImmX16 - 0U, // TAILCALL - 0U, // TAILCALL64_R - 0U, // TAILCALL_R - 1U, // TEQ - 0U, // TEQI - 0U, // TEQI_MM - 1U, // TEQ_MM - 1U, // TGE - 0U, // TGEI - 0U, // TGEIU - 0U, // TGEIU_MM - 0U, // TGEI_MM - 1U, // TGEU - 1U, // TGEU_MM - 1U, // TGE_MM - 0U, // TLBP - 0U, // TLBP_MM - 0U, // TLBR - 0U, // TLBR_MM - 0U, // TLBWI - 0U, // TLBWI_MM - 0U, // TLBWR - 0U, // TLBWR_MM - 1U, // TLT - 0U, // TLTI - 0U, // TLTIU_MM - 0U, // TLTI_MM - 1U, // TLTU - 1U, // TLTU_MM - 1U, // TLT_MM - 1U, // TNE - 0U, // TNEI - 0U, // TNEI_MM - 1U, // TNE_MM - 0U, // TRAP - 0U, // TRUNC_L_D64 - 0U, // TRUNC_L_S - 0U, // TRUNC_W_D32 - 0U, // TRUNC_W_D64 - 0U, // TRUNC_W_MM - 0U, // TRUNC_W_S - 0U, // TRUNC_W_S_MM - 0U, // TTLTIU - 0U, // UDIV - 0U, // UDIV_MM - 0U, // V3MULU - 0U, // VMM0 - 0U, // VMULU - 2U, // VSHF_B - 2U, // VSHF_D - 2U, // VSHF_H - 2U, // VSHF_W - 0U, // WAIT - 0U, // WAIT_MM - 0U, // WRDSP - 0U, // WSBH - 0U, // WSBH_MM - 0U, // XOR - 0U, // XOR16_MM - 0U, // XOR64 - 0U, // XORI_B - 0U, // XOR_MM - 0U, // XOR_V - 0U, // XOR_V_D_PSEUDO - 0U, // XOR_V_H_PSEUDO - 0U, // XOR_V_W_PSEUDO - 1U, // XORi - 1U, // XORi64 - 1U, // XORi_MM - 0U, // XorRxRxRy16 - 0U - }; + static const uint8_t OpInfo2[] = {0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 0U, // ABSQ_S_PH + 0U, // ABSQ_S_QB + 0U, // ABSQ_S_W + 0U, // ADD + 0U, // ADDIUPC + 0U, // ADDIUPC_MM + 0U, // ADDIUR1SP_MM + 0U, // ADDIUR2_MM + 0U, // ADDIUS5_MM + 0U, // ADDIUSP_MM + 0U, // ADDQH_PH + 0U, // ADDQH_R_PH + 0U, // ADDQH_R_W + 0U, // ADDQH_W + 0U, // ADDQ_PH + 0U, // ADDQ_S_PH + 0U, // ADDQ_S_W + 0U, // ADDSC + 0U, // ADDS_A_B + 0U, // ADDS_A_D + 0U, // ADDS_A_H + 0U, // ADDS_A_W + 0U, // ADDS_S_B + 0U, // ADDS_S_D + 0U, // ADDS_S_H + 0U, // ADDS_S_W + 0U, // ADDS_U_B + 0U, // ADDS_U_D + 0U, // ADDS_U_H + 0U, // ADDS_U_W + 0U, // ADDU16_MM + 0U, // ADDUH_QB + 0U, // ADDUH_R_QB + 0U, // ADDU_PH + 0U, // ADDU_QB + 0U, // ADDU_S_PH + 0U, // ADDU_S_QB + 0U, // ADDVI_B + 0U, // ADDVI_D + 0U, // ADDVI_H + 0U, // ADDVI_W + 0U, // ADDV_B + 0U, // ADDV_D + 0U, // ADDV_H + 0U, // ADDV_W + 0U, // ADDWC + 0U, // ADD_A_B + 0U, // ADD_A_D + 0U, // ADD_A_H + 0U, // ADD_A_W + 0U, // ADD_MM + 0U, // ADDi + 0U, // ADDi_MM + 0U, // ADDiu + 0U, // ADDiu_MM + 0U, // ADDu + 0U, // ADDu_MM + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 4U, // ALIGN + 0U, // ALUIPC + 0U, // AND + 0U, // AND16_MM + 0U, // AND64 + 0U, // ANDI16_MM + 0U, // ANDI_B + 0U, // AND_MM + 0U, // AND_V + 0U, // AND_V_D_PSEUDO + 0U, // AND_V_H_PSEUDO + 0U, // AND_V_W_PSEUDO + 1U, // ANDi + 1U, // ANDi64 + 1U, // ANDi_MM + 1U, // APPEND + 0U, // ASUB_S_B + 0U, // ASUB_S_D + 0U, // ASUB_S_H + 0U, // ASUB_S_W + 0U, // ASUB_U_B + 0U, // ASUB_U_D + 0U, // ASUB_U_H + 0U, // ASUB_U_W + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I8 + 0U, // AUI + 0U, // AUIPC + 0U, // AVER_S_B + 0U, // AVER_S_D + 0U, // AVER_S_H + 0U, // AVER_S_W + 0U, // AVER_U_B + 0U, // AVER_U_D + 0U, // AVER_U_H + 0U, // AVER_U_W + 0U, // AVE_S_B + 0U, // AVE_S_D + 0U, // AVE_S_H + 0U, // AVE_S_W + 0U, // AVE_U_B + 0U, // AVE_U_D + 0U, // AVE_U_H + 0U, // AVE_U_W + 0U, // AddiuRxImmX16 + 0U, // AddiuRxPcImmX16 + 0U, // AddiuRxRxImm16 + 0U, // AddiuRxRxImmX16 + 0U, // AddiuRxRyOffMemX16 + 0U, // AddiuSpImm16 + 0U, // AddiuSpImmX16 + 0U, // AdduRxRyRz16 + 0U, // AndRxRxRy16 + 0U, // B + 0U, // B16_MM + 0U, // BADDu + 0U, // BAL + 0U, // BALC + 1U, // BALIGN + 0U, // BAL_BR + 0U, // BBIT0 + 0U, // BBIT032 + 0U, // BBIT1 + 0U, // BBIT132 + 0U, // BC + 0U, // BC0F + 0U, // BC0FL + 0U, // BC0T + 0U, // BC0TL + 0U, // BC1EQZ + 0U, // BC1F + 0U, // BC1FL + 0U, // BC1F_MM + 0U, // BC1NEZ + 0U, // BC1T + 0U, // BC1TL + 0U, // BC1T_MM + 0U, // BC2EQZ + 0U, // BC2F + 0U, // BC2FL + 0U, // BC2NEZ + 0U, // BC2T + 0U, // BC2TL + 0U, // BC3F + 0U, // BC3FL + 0U, // BC3T + 0U, // BC3TL + 0U, // BCLRI_B + 0U, // BCLRI_D + 0U, // BCLRI_H + 0U, // BCLRI_W + 0U, // BCLR_B + 0U, // BCLR_D + 0U, // BCLR_H + 0U, // BCLR_W + 0U, // BEQ + 0U, // BEQ64 + 0U, // BEQC + 0U, // BEQL + 0U, // BEQZ16_MM + 0U, // BEQZALC + 0U, // BEQZC + 0U, // BEQZC_MM + 0U, // BEQ_MM + 0U, // BGEC + 0U, // BGEUC + 0U, // BGEZ + 0U, // BGEZ64 + 0U, // BGEZAL + 0U, // BGEZALC + 0U, // BGEZALL + 0U, // BGEZALS_MM + 0U, // BGEZAL_MM + 0U, // BGEZC + 0U, // BGEZL + 0U, // BGEZ_MM + 0U, // BGTZ + 0U, // BGTZ64 + 0U, // BGTZALC + 0U, // BGTZC + 0U, // BGTZL + 0U, // BGTZ_MM + 1U, // BINSLI_B + 1U, // BINSLI_D + 1U, // BINSLI_H + 1U, // BINSLI_W + 2U, // BINSL_B + 2U, // BINSL_D + 2U, // BINSL_H + 2U, // BINSL_W + 1U, // BINSRI_B + 1U, // BINSRI_D + 1U, // BINSRI_H + 1U, // BINSRI_W + 2U, // BINSR_B + 2U, // BINSR_D + 2U, // BINSR_H + 2U, // BINSR_W + 0U, // BITREV + 0U, // BITSWAP + 0U, // BLEZ + 0U, // BLEZ64 + 0U, // BLEZALC + 0U, // BLEZC + 0U, // BLEZL + 0U, // BLEZ_MM + 0U, // BLTC + 0U, // BLTUC + 0U, // BLTZ + 0U, // BLTZ64 + 0U, // BLTZAL + 0U, // BLTZALC + 0U, // BLTZALL + 0U, // BLTZALS_MM + 0U, // BLTZAL_MM + 0U, // BLTZC + 0U, // BLTZL + 0U, // BLTZ_MM + 1U, // BMNZI_B + 2U, // BMNZ_V + 1U, // BMZI_B + 2U, // BMZ_V + 0U, // BNE + 0U, // BNE64 + 0U, // BNEC + 0U, // BNEGI_B + 0U, // BNEGI_D + 0U, // BNEGI_H + 0U, // BNEGI_W + 0U, // BNEG_B + 0U, // BNEG_D + 0U, // BNEG_H + 0U, // BNEG_W + 0U, // BNEL + 0U, // BNEZ16_MM + 0U, // BNEZALC + 0U, // BNEZC + 0U, // BNEZC_MM + 0U, // BNE_MM + 0U, // BNVC + 0U, // BNZ_B + 0U, // BNZ_D + 0U, // BNZ_H + 0U, // BNZ_V + 0U, // BNZ_W + 0U, // BOVC + 0U, // BPOSGE32 + 0U, // BPOSGE32_PSEUDO + 0U, // BREAK + 0U, // BREAK16_MM + 0U, // BREAK_MM + 1U, // BSELI_B + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 2U, // BSEL_V + 0U, // BSEL_W_PSEUDO + 0U, // BSETI_B + 0U, // BSETI_D + 0U, // BSETI_H + 0U, // BSETI_W + 0U, // BSET_B + 0U, // BSET_D + 0U, // BSET_H + 0U, // BSET_W + 0U, // BZ_B + 0U, // BZ_D + 0U, // BZ_H + 0U, // BZ_V + 0U, // BZ_W + 0U, // B_MM_Pseudo + 0U, // BeqzRxImm16 + 0U, // BeqzRxImmX16 + 0U, // Bimm16 + 0U, // BimmX16 + 0U, // BnezRxImm16 + 0U, // BnezRxImmX16 + 0U, // Break16 + 0U, // Bteqz16 + 0U, // BteqzT8CmpX16 + 0U, // BteqzT8CmpiX16 + 0U, // BteqzT8SltX16 + 0U, // BteqzT8SltiX16 + 0U, // BteqzT8SltiuX16 + 0U, // BteqzT8SltuX16 + 0U, // BteqzX16 + 0U, // Btnez16 + 0U, // BtnezT8CmpX16 + 0U, // BtnezT8CmpiX16 + 0U, // BtnezT8SltX16 + 0U, // BtnezT8SltiX16 + 0U, // BtnezT8SltiuX16 + 0U, // BtnezT8SltuX16 + 0U, // BtnezX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 0U, // CACHE + 0U, // CACHE_MM + 0U, // CACHE_R6 + 0U, // CEIL_L_D64 + 0U, // CEIL_L_S + 0U, // CEIL_W_D32 + 0U, // CEIL_W_D64 + 0U, // CEIL_W_MM + 0U, // CEIL_W_S + 0U, // CEIL_W_S_MM + 0U, // CEQI_B + 0U, // CEQI_D + 0U, // CEQI_H + 0U, // CEQI_W + 0U, // CEQ_B + 0U, // CEQ_D + 0U, // CEQ_H + 0U, // CEQ_W + 0U, // CFC1 + 0U, // CFC1_MM + 0U, // CFCMSA + 5U, // CINS + 5U, // CINS32 + 0U, // CLASS_D + 0U, // CLASS_S + 0U, // CLEI_S_B + 0U, // CLEI_S_D + 0U, // CLEI_S_H + 0U, // CLEI_S_W + 0U, // CLEI_U_B + 0U, // CLEI_U_D + 0U, // CLEI_U_H + 0U, // CLEI_U_W + 0U, // CLE_S_B + 0U, // CLE_S_D + 0U, // CLE_S_H + 0U, // CLE_S_W + 0U, // CLE_U_B + 0U, // CLE_U_D + 0U, // CLE_U_H + 0U, // CLE_U_W + 0U, // CLO + 0U, // CLO_MM + 0U, // CLO_R6 + 0U, // CLTI_S_B + 0U, // CLTI_S_D + 0U, // CLTI_S_H + 0U, // CLTI_S_W + 0U, // CLTI_U_B + 0U, // CLTI_U_D + 0U, // CLTI_U_H + 0U, // CLTI_U_W + 0U, // CLT_S_B + 0U, // CLT_S_D + 0U, // CLT_S_H + 0U, // CLT_S_W + 0U, // CLT_U_B + 0U, // CLT_U_D + 0U, // CLT_U_H + 0U, // CLT_U_W + 0U, // CLZ + 0U, // CLZ_MM + 0U, // CLZ_R6 + 0U, // CMPGDU_EQ_QB + 0U, // CMPGDU_LE_QB + 0U, // CMPGDU_LT_QB + 0U, // CMPGU_EQ_QB + 0U, // CMPGU_LE_QB + 0U, // CMPGU_LT_QB + 0U, // CMPU_EQ_QB + 0U, // CMPU_LE_QB + 0U, // CMPU_LT_QB + 0U, // CMP_EQ_D + 0U, // CMP_EQ_PH + 0U, // CMP_EQ_S + 0U, // CMP_F_D + 0U, // CMP_F_S + 0U, // CMP_LE_D + 0U, // CMP_LE_PH + 0U, // CMP_LE_S + 0U, // CMP_LT_D + 0U, // CMP_LT_PH + 0U, // CMP_LT_S + 0U, // CMP_SAF_D + 0U, // CMP_SAF_S + 0U, // CMP_SEQ_D + 0U, // CMP_SEQ_S + 0U, // CMP_SLE_D + 0U, // CMP_SLE_S + 0U, // CMP_SLT_D + 0U, // CMP_SLT_S + 0U, // CMP_SUEQ_D + 0U, // CMP_SUEQ_S + 0U, // CMP_SULE_D + 0U, // CMP_SULE_S + 0U, // CMP_SULT_D + 0U, // CMP_SULT_S + 0U, // CMP_SUN_D + 0U, // CMP_SUN_S + 0U, // CMP_UEQ_D + 0U, // CMP_UEQ_S + 0U, // CMP_ULE_D + 0U, // CMP_ULE_S + 0U, // CMP_ULT_D + 0U, // CMP_ULT_S + 0U, // CMP_UN_D + 0U, // CMP_UN_S + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 8U, // COPY_S_B + 8U, // COPY_S_D + 8U, // COPY_S_H + 8U, // COPY_S_W + 8U, // COPY_U_B + 8U, // COPY_U_D + 8U, // COPY_U_H + 8U, // COPY_U_W + 0U, // CTC1 + 0U, // CTC1_MM + 0U, // CTCMSA + 0U, // CVT_D32_S + 0U, // CVT_D32_W + 0U, // CVT_D32_W_MM + 0U, // CVT_D64_L + 0U, // CVT_D64_S + 0U, // CVT_D64_W + 0U, // CVT_D_S_MM + 0U, // CVT_L_D64 + 0U, // CVT_L_D64_MM + 0U, // CVT_L_S + 0U, // CVT_L_S_MM + 0U, // CVT_S_D32 + 0U, // CVT_S_D32_MM + 0U, // CVT_S_D64 + 0U, // CVT_S_L + 0U, // CVT_S_W + 0U, // CVT_S_W_MM + 0U, // CVT_W_D32 + 0U, // CVT_W_D64 + 0U, // CVT_W_MM + 0U, // CVT_W_S + 0U, // CVT_W_S_MM + 0U, // C_EQ_D32 + 0U, // C_EQ_D64 + 0U, // C_EQ_S + 0U, // C_F_D32 + 0U, // C_F_D64 + 0U, // C_F_S + 0U, // C_LE_D32 + 0U, // C_LE_D64 + 0U, // C_LE_S + 0U, // C_LT_D32 + 0U, // C_LT_D64 + 0U, // C_LT_S + 0U, // C_NGE_D32 + 0U, // C_NGE_D64 + 0U, // C_NGE_S + 0U, // C_NGLE_D32 + 0U, // C_NGLE_D64 + 0U, // C_NGLE_S + 0U, // C_NGL_D32 + 0U, // C_NGL_D64 + 0U, // C_NGL_S + 0U, // C_NGT_D32 + 0U, // C_NGT_D64 + 0U, // C_NGT_S + 0U, // C_OLE_D32 + 0U, // C_OLE_D64 + 0U, // C_OLE_S + 0U, // C_OLT_D32 + 0U, // C_OLT_D64 + 0U, // C_OLT_S + 0U, // C_SEQ_D32 + 0U, // C_SEQ_D64 + 0U, // C_SEQ_S + 0U, // C_SF_D32 + 0U, // C_SF_D64 + 0U, // C_SF_S + 0U, // C_UEQ_D32 + 0U, // C_UEQ_D64 + 0U, // C_UEQ_S + 0U, // C_ULE_D32 + 0U, // C_ULE_D64 + 0U, // C_ULE_S + 0U, // C_ULT_D32 + 0U, // C_ULT_D64 + 0U, // C_ULT_S + 0U, // C_UN_D32 + 0U, // C_UN_D64 + 0U, // C_UN_S + 0U, // CmpRxRy16 + 0U, // CmpiRxImm16 + 0U, // CmpiRxImmX16 + 0U, // Constant32 + 0U, // DADD + 0U, // DADDi + 0U, // DADDiu + 0U, // DADDu + 0U, // DAHI + 4U, // DALIGN + 0U, // DATI + 0U, // DAUI + 0U, // DBITSWAP + 0U, // DCLO + 0U, // DCLO_R6 + 0U, // DCLZ + 0U, // DCLZ_R6 + 0U, // DDIV + 0U, // DDIVU + 0U, // DERET + 0U, // DERET_MM + 21U, // DEXT + 21U, // DEXTM + 21U, // DEXTU + 0U, // DI + 21U, // DINS + 21U, // DINSM + 21U, // DINSU + 0U, // DIV + 0U, // DIVU + 0U, // DIV_S_B + 0U, // DIV_S_D + 0U, // DIV_S_H + 0U, // DIV_S_W + 0U, // DIV_U_B + 0U, // DIV_U_D + 0U, // DIV_U_H + 0U, // DIV_U_W + 0U, // DI_MM + 4U, // DLSA + 4U, // DLSA_R6 + 1U, // DMFC0 + 0U, // DMFC1 + 1U, // DMFC2 + 0U, // DMOD + 0U, // DMODU + 1U, // DMTC0 + 0U, // DMTC1 + 1U, // DMTC2 + 0U, // DMUH + 0U, // DMUHU + 0U, // DMUL + 0U, // DMULT + 0U, // DMULTu + 0U, // DMULU + 0U, // DMUL_R6 + 0U, // DOTP_S_D + 0U, // DOTP_S_H + 0U, // DOTP_S_W + 0U, // DOTP_U_D + 0U, // DOTP_U_H + 0U, // DOTP_U_W + 2U, // DPADD_S_D + 2U, // DPADD_S_H + 2U, // DPADD_S_W + 2U, // DPADD_U_D + 2U, // DPADD_U_H + 2U, // DPADD_U_W + 0U, // DPAQX_SA_W_PH + 0U, // DPAQX_S_W_PH + 0U, // DPAQ_SA_L_W + 0U, // DPAQ_S_W_PH + 0U, // DPAU_H_QBL + 0U, // DPAU_H_QBR + 0U, // DPAX_W_PH + 0U, // DPA_W_PH + 0U, // DPOP + 0U, // DPSQX_SA_W_PH + 0U, // DPSQX_S_W_PH + 0U, // DPSQ_SA_L_W + 0U, // DPSQ_S_W_PH + 2U, // DPSUB_S_D + 2U, // DPSUB_S_H + 2U, // DPSUB_S_W + 2U, // DPSUB_U_D + 2U, // DPSUB_U_H + 2U, // DPSUB_U_W + 0U, // DPSU_H_QBL + 0U, // DPSU_H_QBR + 0U, // DPSX_W_PH + 0U, // DPS_W_PH + 1U, // DROTR + 1U, // DROTR32 + 0U, // DROTRV + 0U, // DSBH + 0U, // DSDIV + 0U, // DSHD + 1U, // DSLL + 1U, // DSLL32 + 0U, // DSLL64_32 + 0U, // DSLLV + 1U, // DSRA + 1U, // DSRA32 + 0U, // DSRAV + 1U, // DSRL + 1U, // DSRL32 + 0U, // DSRLV + 0U, // DSUB + 0U, // DSUBu + 0U, // DUDIV + 0U, // DivRxRy16 + 0U, // DivuRxRy16 + 0U, // EHB + 0U, // EHB_MM + 0U, // EI + 0U, // EI_MM + 0U, // ERET + 0U, // ERET_MM + 21U, // EXT + 1U, // EXTP + 1U, // EXTPDP + 0U, // EXTPDPV + 0U, // EXTPV + 0U, // EXTRV_RS_W + 0U, // EXTRV_R_W + 0U, // EXTRV_S_H + 0U, // EXTRV_W + 1U, // EXTR_RS_W + 1U, // EXTR_R_W + 1U, // EXTR_S_H + 1U, // EXTR_W + 5U, // EXTS + 5U, // EXTS32 + 21U, // EXT_MM + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 0U, // FABS_D32 + 0U, // FABS_D64 + 0U, // FABS_MM + 0U, // FABS_S + 0U, // FABS_S_MM + 0U, // FABS_W + 0U, // FADD_D + 0U, // FADD_D32 + 0U, // FADD_D64 + 0U, // FADD_MM + 0U, // FADD_S + 0U, // FADD_S_MM + 0U, // FADD_W + 0U, // FCAF_D + 0U, // FCAF_W + 0U, // FCEQ_D + 0U, // FCEQ_W + 0U, // FCLASS_D + 0U, // FCLASS_W + 0U, // FCLE_D + 0U, // FCLE_W + 0U, // FCLT_D + 0U, // FCLT_W + 0U, // FCMP_D32 + 0U, // FCMP_D32_MM + 0U, // FCMP_D64 + 0U, // FCMP_S32 + 0U, // FCMP_S32_MM + 0U, // FCNE_D + 0U, // FCNE_W + 0U, // FCOR_D + 0U, // FCOR_W + 0U, // FCUEQ_D + 0U, // FCUEQ_W + 0U, // FCULE_D + 0U, // FCULE_W + 0U, // FCULT_D + 0U, // FCULT_W + 0U, // FCUNE_D + 0U, // FCUNE_W + 0U, // FCUN_D + 0U, // FCUN_W + 0U, // FDIV_D + 0U, // FDIV_D32 + 0U, // FDIV_D64 + 0U, // FDIV_MM + 0U, // FDIV_S + 0U, // FDIV_S_MM + 0U, // FDIV_W + 0U, // FEXDO_H + 0U, // FEXDO_W + 0U, // FEXP2_D + 0U, // FEXP2_D_1_PSEUDO + 0U, // FEXP2_W + 0U, // FEXP2_W_1_PSEUDO + 0U, // FEXUPL_D + 0U, // FEXUPL_W + 0U, // FEXUPR_D + 0U, // FEXUPR_W + 0U, // FFINT_S_D + 0U, // FFINT_S_W + 0U, // FFINT_U_D + 0U, // FFINT_U_W + 0U, // FFQL_D + 0U, // FFQL_W + 0U, // FFQR_D + 0U, // FFQR_W + 0U, // FILL_B + 0U, // FILL_D + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 0U, // FILL_H + 0U, // FILL_W + 0U, // FLOG2_D + 0U, // FLOG2_W + 0U, // FLOOR_L_D64 + 0U, // FLOOR_L_S + 0U, // FLOOR_W_D32 + 0U, // FLOOR_W_D64 + 0U, // FLOOR_W_MM + 0U, // FLOOR_W_S + 0U, // FLOOR_W_S_MM + 2U, // FMADD_D + 2U, // FMADD_W + 0U, // FMAX_A_D + 0U, // FMAX_A_W + 0U, // FMAX_D + 0U, // FMAX_W + 0U, // FMIN_A_D + 0U, // FMIN_A_W + 0U, // FMIN_D + 0U, // FMIN_W + 0U, // FMOV_D32 + 0U, // FMOV_D32_MM + 0U, // FMOV_D64 + 0U, // FMOV_S + 0U, // FMOV_S_MM + 2U, // FMSUB_D + 2U, // FMSUB_W + 0U, // FMUL_D + 0U, // FMUL_D32 + 0U, // FMUL_D64 + 0U, // FMUL_MM + 0U, // FMUL_S + 0U, // FMUL_S_MM + 0U, // FMUL_W + 0U, // FNEG_D32 + 0U, // FNEG_D64 + 0U, // FNEG_MM + 0U, // FNEG_S + 0U, // FNEG_S_MM + 0U, // FRCP_D + 0U, // FRCP_W + 0U, // FRINT_D + 0U, // FRINT_W + 0U, // FRSQRT_D + 0U, // FRSQRT_W + 0U, // FSAF_D + 0U, // FSAF_W + 0U, // FSEQ_D + 0U, // FSEQ_W + 0U, // FSLE_D + 0U, // FSLE_W + 0U, // FSLT_D + 0U, // FSLT_W + 0U, // FSNE_D + 0U, // FSNE_W + 0U, // FSOR_D + 0U, // FSOR_W + 0U, // FSQRT_D + 0U, // FSQRT_D32 + 0U, // FSQRT_D64 + 0U, // FSQRT_MM + 0U, // FSQRT_S + 0U, // FSQRT_S_MM + 0U, // FSQRT_W + 0U, // FSUB_D + 0U, // FSUB_D32 + 0U, // FSUB_D64 + 0U, // FSUB_MM + 0U, // FSUB_S + 0U, // FSUB_S_MM + 0U, // FSUB_W + 0U, // FSUEQ_D + 0U, // FSUEQ_W + 0U, // FSULE_D + 0U, // FSULE_W + 0U, // FSULT_D + 0U, // FSULT_W + 0U, // FSUNE_D + 0U, // FSUNE_W + 0U, // FSUN_D + 0U, // FSUN_W + 0U, // FTINT_S_D + 0U, // FTINT_S_W + 0U, // FTINT_U_D + 0U, // FTINT_U_W + 0U, // FTQ_H + 0U, // FTQ_W + 0U, // FTRUNC_S_D + 0U, // FTRUNC_S_W + 0U, // FTRUNC_U_D + 0U, // FTRUNC_U_W + 0U, // GotPrologue16 + 0U, // HADD_S_D + 0U, // HADD_S_H + 0U, // HADD_S_W + 0U, // HADD_U_D + 0U, // HADD_U_H + 0U, // HADD_U_W + 0U, // HSUB_S_D + 0U, // HSUB_S_H + 0U, // HSUB_S_W + 0U, // HSUB_U_D + 0U, // HSUB_U_H + 0U, // HSUB_U_W + 0U, // ILVEV_B + 0U, // ILVEV_D + 0U, // ILVEV_H + 0U, // ILVEV_W + 0U, // ILVL_B + 0U, // ILVL_D + 0U, // ILVL_H + 0U, // ILVL_W + 0U, // ILVOD_B + 0U, // ILVOD_D + 0U, // ILVOD_H + 0U, // ILVOD_W + 0U, // ILVR_B + 0U, // ILVR_D + 0U, // ILVR_H + 0U, // ILVR_W + 21U, // INS + 0U, // INSERT_B + 0U, // INSERT_B_VIDX_PSEUDO + 0U, // INSERT_D + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 0U, // INSERT_H + 0U, // INSERT_H_VIDX_PSEUDO + 0U, // INSERT_W + 0U, // INSERT_W_VIDX_PSEUDO + 0U, // INSV + 0U, // INSVE_B + 0U, // INSVE_D + 0U, // INSVE_H + 0U, // INSVE_W + 21U, // INS_MM + 0U, // J + 0U, // JAL + 0U, // JALR + 0U, // JALR16_MM + 0U, // JALR64 + 0U, // JALR64Pseudo + 0U, // JALRPseudo + 0U, // JALRS16_MM + 0U, // JALRS_MM + 0U, // JALR_HB + 0U, // JALR_MM + 0U, // JALS_MM + 0U, // JALX + 0U, // JALX_MM + 0U, // JAL_MM + 0U, // JIALC + 0U, // JIC + 0U, // JR + 0U, // JR16_MM + 0U, // JR64 + 0U, // JRADDIUSP + 0U, // JRC16_MM + 0U, // JR_HB + 0U, // JR_HB_R6 + 0U, // JR_MM + 0U, // J_MM + 0U, // Jal16 + 0U, // JalB16 + 0U, // JalOneReg + 0U, // JalTwoReg + 0U, // JrRa16 + 0U, // JrcRa16 + 0U, // JrcRx16 + 0U, // JumpLinkReg16 + 0U, // LB + 0U, // LB64 + 0U, // LBU16_MM + 0U, // LBUX + 0U, // LB_MM + 0U, // LBu + 0U, // LBu64 + 0U, // LBu_MM + 0U, // LD + 0U, // LDC1 + 0U, // LDC164 + 0U, // LDC1_MM + 0U, // LDC2 + 0U, // LDC2_R6 + 0U, // LDC3 + 0U, // LDI_B + 0U, // LDI_D + 0U, // LDI_H + 0U, // LDI_W + 0U, // LDL + 0U, // LDPC + 0U, // LDR + 0U, // LDXC1 + 0U, // LDXC164 + 0U, // LD_B + 0U, // LD_D + 0U, // LD_H + 0U, // LD_W + 0U, // LEA_ADDiu + 0U, // LEA_ADDiu64 + 0U, // LEA_ADDiu_MM + 0U, // LH + 0U, // LH64 + 0U, // LHU16_MM + 0U, // LHX + 0U, // LH_MM + 0U, // LHu + 0U, // LHu64 + 0U, // LHu_MM + 0U, // LI16_MM + 0U, // LL + 0U, // LLD + 0U, // LLD_R6 + 0U, // LL_MM + 0U, // LL_R6 + 0U, // LOAD_ACC128 + 0U, // LOAD_ACC64 + 0U, // LOAD_ACC64DSP + 0U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_LUi + 4U, // LSA + 4U, // LSA_R6 + 0U, // LUXC1 + 0U, // LUXC164 + 0U, // LUXC1_MM + 0U, // LUi + 0U, // LUi64 + 0U, // LUi_MM + 0U, // LW + 0U, // LW16_MM + 0U, // LW64 + 0U, // LWC1 + 0U, // LWC1_MM + 0U, // LWC2 + 0U, // LWC2_R6 + 0U, // LWC3 + 0U, // LWGP_MM + 0U, // LWL + 0U, // LWL64 + 0U, // LWL_MM + 0U, // LWM16_MM + 0U, // LWM32_MM + 0U, // LWM_MM + 0U, // LWPC + 0U, // LWP_MM + 0U, // LWR + 0U, // LWR64 + 0U, // LWR_MM + 0U, // LWSP_MM + 0U, // LWUPC + 0U, // LWU_MM + 0U, // LWX + 0U, // LWXC1 + 0U, // LWXC1_MM + 0U, // LWXS_MM + 0U, // LW_MM + 0U, // LWu + 0U, // LbRxRyOffMemX16 + 0U, // LbuRxRyOffMemX16 + 0U, // LhRxRyOffMemX16 + 0U, // LhuRxRyOffMemX16 + 0U, // LiRxImm16 + 0U, // LiRxImmAlignX16 + 0U, // LiRxImmX16 + 0U, // LoadAddr32Imm + 0U, // LoadAddr32Reg + 0U, // LoadImm32Reg + 0U, // LoadImm64Reg + 0U, // LwConstant32 + 0U, // LwRxPcTcp16 + 0U, // LwRxPcTcpX16 + 0U, // LwRxRyOffMemX16 + 0U, // LwRxSpImmX16 + 0U, // MADD + 2U, // MADDF_D + 2U, // MADDF_S + 2U, // MADDR_Q_H + 2U, // MADDR_Q_W + 0U, // MADDU + 0U, // MADDU_DSP + 0U, // MADDU_MM + 2U, // MADDV_B + 2U, // MADDV_D + 2U, // MADDV_H + 2U, // MADDV_W + 20U, // MADD_D32 + 20U, // MADD_D32_MM + 20U, // MADD_D64 + 0U, // MADD_DSP + 0U, // MADD_MM + 2U, // MADD_Q_H + 2U, // MADD_Q_W + 20U, // MADD_S + 20U, // MADD_S_MM + 0U, // MAQ_SA_W_PHL + 0U, // MAQ_SA_W_PHR + 0U, // MAQ_S_W_PHL + 0U, // MAQ_S_W_PHR + 0U, // MAXA_D + 0U, // MAXA_S + 0U, // MAXI_S_B + 0U, // MAXI_S_D + 0U, // MAXI_S_H + 0U, // MAXI_S_W + 0U, // MAXI_U_B + 0U, // MAXI_U_D + 0U, // MAXI_U_H + 0U, // MAXI_U_W + 0U, // MAX_A_B + 0U, // MAX_A_D + 0U, // MAX_A_H + 0U, // MAX_A_W + 0U, // MAX_D + 0U, // MAX_S + 0U, // MAX_S_B + 0U, // MAX_S_D + 0U, // MAX_S_H + 0U, // MAX_S_W + 0U, // MAX_U_B + 0U, // MAX_U_D + 0U, // MAX_U_H + 0U, // MAX_U_W + 1U, // MFC0 + 0U, // MFC1 + 0U, // MFC1_MM + 1U, // MFC2 + 0U, // MFHC1_D32 + 0U, // MFHC1_D64 + 0U, // MFHC1_MM + 0U, // MFHI + 0U, // MFHI16_MM + 0U, // MFHI64 + 0U, // MFHI_DSP + 0U, // MFHI_MM + 0U, // MFLO + 0U, // MFLO16_MM + 0U, // MFLO64 + 0U, // MFLO_DSP + 0U, // MFLO_MM + 0U, // MINA_D + 0U, // MINA_S + 0U, // MINI_S_B + 0U, // MINI_S_D + 0U, // MINI_S_H + 0U, // MINI_S_W + 0U, // MINI_U_B + 0U, // MINI_U_D + 0U, // MINI_U_H + 0U, // MINI_U_W + 0U, // MIN_A_B + 0U, // MIN_A_D + 0U, // MIN_A_H + 0U, // MIN_A_W + 0U, // MIN_D + 0U, // MIN_S + 0U, // MIN_S_B + 0U, // MIN_S_D + 0U, // MIN_S_H + 0U, // MIN_S_W + 0U, // MIN_U_B + 0U, // MIN_U_D + 0U, // MIN_U_H + 0U, // MIN_U_W + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 0U, // MOD + 0U, // MODSUB + 0U, // MODU + 0U, // MOD_S_B + 0U, // MOD_S_D + 0U, // MOD_S_H + 0U, // MOD_S_W + 0U, // MOD_U_B + 0U, // MOD_U_D + 0U, // MOD_U_H + 0U, // MOD_U_W + 0U, // MOVE16_MM + 0U, // MOVEP_MM + 0U, // MOVE_V + 0U, // MOVF_D32 + 0U, // MOVF_D32_MM + 0U, // MOVF_D64 + 0U, // MOVF_I + 0U, // MOVF_I64 + 0U, // MOVF_I_MM + 0U, // MOVF_S + 0U, // MOVF_S_MM + 0U, // MOVN_I64_D64 + 0U, // MOVN_I64_I + 0U, // MOVN_I64_I64 + 0U, // MOVN_I64_S + 0U, // MOVN_I_D32 + 0U, // MOVN_I_D32_MM + 0U, // MOVN_I_D64 + 0U, // MOVN_I_I + 0U, // MOVN_I_I64 + 0U, // MOVN_I_MM + 0U, // MOVN_I_S + 0U, // MOVN_I_S_MM + 0U, // MOVT_D32 + 0U, // MOVT_D32_MM + 0U, // MOVT_D64 + 0U, // MOVT_I + 0U, // MOVT_I64 + 0U, // MOVT_I_MM + 0U, // MOVT_S + 0U, // MOVT_S_MM + 0U, // MOVZ_I64_D64 + 0U, // MOVZ_I64_I + 0U, // MOVZ_I64_I64 + 0U, // MOVZ_I64_S + 0U, // MOVZ_I_D32 + 0U, // MOVZ_I_D32_MM + 0U, // MOVZ_I_D64 + 0U, // MOVZ_I_I + 0U, // MOVZ_I_I64 + 0U, // MOVZ_I_MM + 0U, // MOVZ_I_S + 0U, // MOVZ_I_S_MM + 0U, // MSUB + 2U, // MSUBF_D + 2U, // MSUBF_S + 2U, // MSUBR_Q_H + 2U, // MSUBR_Q_W + 0U, // MSUBU + 0U, // MSUBU_DSP + 0U, // MSUBU_MM + 2U, // MSUBV_B + 2U, // MSUBV_D + 2U, // MSUBV_H + 2U, // MSUBV_W + 20U, // MSUB_D32 + 20U, // MSUB_D32_MM + 20U, // MSUB_D64 + 0U, // MSUB_DSP + 0U, // MSUB_MM + 2U, // MSUB_Q_H + 2U, // MSUB_Q_W + 20U, // MSUB_S + 20U, // MSUB_S_MM + 1U, // MTC0 + 0U, // MTC1 + 0U, // MTC1_MM + 1U, // MTC2 + 0U, // MTHC1_D32 + 0U, // MTHC1_D64 + 0U, // MTHC1_MM + 0U, // MTHI + 0U, // MTHI64 + 0U, // MTHI_DSP + 0U, // MTHI_MM + 0U, // MTHLIP + 0U, // MTLO + 0U, // MTLO64 + 0U, // MTLO_DSP + 0U, // MTLO_MM + 0U, // MTM0 + 0U, // MTM1 + 0U, // MTM2 + 0U, // MTP0 + 0U, // MTP1 + 0U, // MTP2 + 0U, // MUH + 0U, // MUHU + 0U, // MUL + 0U, // MULEQ_S_W_PHL + 0U, // MULEQ_S_W_PHR + 0U, // MULEU_S_PH_QBL + 0U, // MULEU_S_PH_QBR + 0U, // MULQ_RS_PH + 0U, // MULQ_RS_W + 0U, // MULQ_S_PH + 0U, // MULQ_S_W + 0U, // MULR_Q_H + 0U, // MULR_Q_W + 0U, // MULSAQ_S_W_PH + 0U, // MULSA_W_PH + 0U, // MULT + 0U, // MULTU_DSP + 0U, // MULT_DSP + 0U, // MULT_MM + 0U, // MULTu + 0U, // MULTu_MM + 0U, // MULU + 0U, // MULV_B + 0U, // MULV_D + 0U, // MULV_H + 0U, // MULV_W + 0U, // MUL_MM + 0U, // MUL_PH + 0U, // MUL_Q_H + 0U, // MUL_Q_W + 0U, // MUL_R6 + 0U, // MUL_S_PH + 0U, // Mfhi16 + 0U, // Mflo16 + 0U, // Move32R16 + 0U, // MoveR3216 + 0U, // MultRxRy16 + 0U, // MultRxRyRz16 + 0U, // MultuRxRy16 + 0U, // MultuRxRyRz16 + 0U, // NLOC_B + 0U, // NLOC_D + 0U, // NLOC_H + 0U, // NLOC_W + 0U, // NLZC_B + 0U, // NLZC_D + 0U, // NLZC_H + 0U, // NLZC_W + 20U, // NMADD_D32 + 20U, // NMADD_D32_MM + 20U, // NMADD_D64 + 20U, // NMADD_S + 20U, // NMADD_S_MM + 20U, // NMSUB_D32 + 20U, // NMSUB_D32_MM + 20U, // NMSUB_D64 + 20U, // NMSUB_S + 20U, // NMSUB_S_MM + 0U, // NOP + 0U, // NOR + 0U, // NOR64 + 0U, // NORI_B + 0U, // NOR_MM + 0U, // NOR_V + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 0U, // NOT16_MM + 0U, // NegRxRy16 + 0U, // NotRxRy16 + 0U, // OR + 0U, // OR16_MM + 0U, // OR64 + 0U, // ORI_B + 0U, // OR_MM + 0U, // OR_V + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 1U, // ORi + 1U, // ORi64 + 1U, // ORi_MM + 0U, // OrRxRxRy16 + 0U, // PACKRL_PH + 0U, // PAUSE + 0U, // PAUSE_MM + 0U, // PCKEV_B + 0U, // PCKEV_D + 0U, // PCKEV_H + 0U, // PCKEV_W + 0U, // PCKOD_B + 0U, // PCKOD_D + 0U, // PCKOD_H + 0U, // PCKOD_W + 0U, // PCNT_B + 0U, // PCNT_D + 0U, // PCNT_H + 0U, // PCNT_W + 0U, // PICK_PH + 0U, // PICK_QB + 0U, // POP + 0U, // PRECEQU_PH_QBL + 0U, // PRECEQU_PH_QBLA + 0U, // PRECEQU_PH_QBR + 0U, // PRECEQU_PH_QBRA + 0U, // PRECEQ_W_PHL + 0U, // PRECEQ_W_PHR + 0U, // PRECEU_PH_QBL + 0U, // PRECEU_PH_QBLA + 0U, // PRECEU_PH_QBR + 0U, // PRECEU_PH_QBRA + 0U, // PRECRQU_S_QB_PH + 0U, // PRECRQ_PH_W + 0U, // PRECRQ_QB_PH + 0U, // PRECRQ_RS_PH_W + 0U, // PRECR_QB_PH + 1U, // PRECR_SRA_PH_W + 1U, // PRECR_SRA_R_PH_W + 0U, // PREF + 0U, // PREF_MM + 0U, // PREF_R6 + 1U, // PREPEND + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 0U, // PseudoCVT_D32_W + 0U, // PseudoCVT_D64_L + 0U, // PseudoCVT_D64_W + 0U, // PseudoCVT_S_L + 0U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMULT + 0U, // PseudoMULTu + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 0U, // PseudoUDIV + 0U, // RADDU_W_QB + 0U, // RDDSP + 0U, // RDHWR + 0U, // RDHWR64 + 0U, // RDHWR_MM + 0U, // REPLV_PH + 0U, // REPLV_QB + 0U, // REPL_PH + 0U, // REPL_QB + 0U, // RINT_D + 0U, // RINT_S + 1U, // ROTR + 0U, // ROTRV + 0U, // ROTRV_MM + 1U, // ROTR_MM + 0U, // ROUND_L_D64 + 0U, // ROUND_L_S + 0U, // ROUND_W_D32 + 0U, // ROUND_W_D64 + 0U, // ROUND_W_MM + 0U, // ROUND_W_S + 0U, // ROUND_W_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 0U, // RetRA + 0U, // RetRA16 + 1U, // SAT_S_B + 1U, // SAT_S_D + 0U, // SAT_S_H + 1U, // SAT_S_W + 1U, // SAT_U_B + 1U, // SAT_U_D + 0U, // SAT_U_H + 1U, // SAT_U_W + 0U, // SB + 0U, // SB16_MM + 0U, // SB64 + 0U, // SB_MM + 0U, // SC + 0U, // SCD + 0U, // SCD_R6 + 0U, // SC_MM + 0U, // SC_R6 + 0U, // SD + 0U, // SDBBP + 0U, // SDBBP16_MM + 0U, // SDBBP_MM + 0U, // SDBBP_R6 + 0U, // SDC1 + 0U, // SDC164 + 0U, // SDC1_MM + 0U, // SDC2 + 0U, // SDC2_R6 + 0U, // SDC3 + 0U, // SDIV + 0U, // SDIV_MM + 0U, // SDL + 0U, // SDR + 0U, // SDXC1 + 0U, // SDXC164 + 0U, // SEB + 0U, // SEB64 + 0U, // SEB_MM + 0U, // SEH + 0U, // SEH64 + 0U, // SEH_MM + 0U, // SELEQZ + 0U, // SELEQZ64 + 0U, // SELEQZ_D + 0U, // SELEQZ_S + 0U, // SELNEZ + 0U, // SELNEZ64 + 0U, // SELNEZ_D + 0U, // SELNEZ_S + 2U, // SEL_D + 2U, // SEL_S + 0U, // SEQ + 0U, // SEQi + 0U, // SH + 0U, // SH16_MM + 0U, // SH64 + 0U, // SHF_B + 0U, // SHF_H + 0U, // SHF_W + 0U, // SHILO + 0U, // SHILOV + 0U, // SHLLV_PH + 0U, // SHLLV_QB + 0U, // SHLLV_S_PH + 0U, // SHLLV_S_W + 1U, // SHLL_PH + 1U, // SHLL_QB + 1U, // SHLL_S_PH + 1U, // SHLL_S_W + 0U, // SHRAV_PH + 0U, // SHRAV_QB + 0U, // SHRAV_R_PH + 0U, // SHRAV_R_QB + 0U, // SHRAV_R_W + 1U, // SHRA_PH + 1U, // SHRA_QB + 1U, // SHRA_R_PH + 1U, // SHRA_R_QB + 1U, // SHRA_R_W + 0U, // SHRLV_PH + 0U, // SHRLV_QB + 1U, // SHRL_PH + 1U, // SHRL_QB + 0U, // SH_MM + 9U, // SLDI_B + 9U, // SLDI_D + 9U, // SLDI_H + 9U, // SLDI_W + 10U, // SLD_B + 10U, // SLD_D + 10U, // SLD_H + 10U, // SLD_W + 1U, // SLL + 0U, // SLL16_MM + 0U, // SLL64_32 + 0U, // SLL64_64 + 0U, // SLLI_B + 0U, // SLLI_D + 0U, // SLLI_H + 0U, // SLLI_W + 0U, // SLLV + 0U, // SLLV_MM + 0U, // SLL_B + 0U, // SLL_D + 0U, // SLL_H + 1U, // SLL_MM + 0U, // SLL_W + 0U, // SLT + 0U, // SLT64 + 0U, // SLT_MM + 0U, // SLTi + 0U, // SLTi64 + 0U, // SLTi_MM + 0U, // SLTiu + 0U, // SLTiu64 + 0U, // SLTiu_MM + 0U, // SLTu + 0U, // SLTu64 + 0U, // SLTu_MM + 0U, // SNE + 0U, // SNEi + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 8U, // SPLATI_B + 8U, // SPLATI_D + 8U, // SPLATI_H + 8U, // SPLATI_W + 8U, // SPLAT_B + 8U, // SPLAT_D + 8U, // SPLAT_H + 8U, // SPLAT_W + 1U, // SRA + 0U, // SRAI_B + 0U, // SRAI_D + 0U, // SRAI_H + 0U, // SRAI_W + 1U, // SRARI_B + 1U, // SRARI_D + 0U, // SRARI_H + 1U, // SRARI_W + 0U, // SRAR_B + 0U, // SRAR_D + 0U, // SRAR_H + 0U, // SRAR_W + 0U, // SRAV + 0U, // SRAV_MM + 0U, // SRA_B + 0U, // SRA_D + 0U, // SRA_H + 1U, // SRA_MM + 0U, // SRA_W + 1U, // SRL + 0U, // SRL16_MM + 0U, // SRLI_B + 0U, // SRLI_D + 0U, // SRLI_H + 0U, // SRLI_W + 1U, // SRLRI_B + 1U, // SRLRI_D + 0U, // SRLRI_H + 1U, // SRLRI_W + 0U, // SRLR_B + 0U, // SRLR_D + 0U, // SRLR_H + 0U, // SRLR_W + 0U, // SRLV + 0U, // SRLV_MM + 0U, // SRL_B + 0U, // SRL_D + 0U, // SRL_H + 1U, // SRL_MM + 0U, // SRL_W + 0U, // SSNOP + 0U, // SSNOP_MM + 0U, // STORE_ACC128 + 0U, // STORE_ACC64 + 0U, // STORE_ACC64DSP + 0U, // STORE_CCOND_DSP + 0U, // ST_B + 0U, // ST_D + 0U, // ST_H + 0U, // ST_W + 0U, // SUB + 0U, // SUBQH_PH + 0U, // SUBQH_R_PH + 0U, // SUBQH_R_W + 0U, // SUBQH_W + 0U, // SUBQ_PH + 0U, // SUBQ_S_PH + 0U, // SUBQ_S_W + 0U, // SUBSUS_U_B + 0U, // SUBSUS_U_D + 0U, // SUBSUS_U_H + 0U, // SUBSUS_U_W + 0U, // SUBSUU_S_B + 0U, // SUBSUU_S_D + 0U, // SUBSUU_S_H + 0U, // SUBSUU_S_W + 0U, // SUBS_S_B + 0U, // SUBS_S_D + 0U, // SUBS_S_H + 0U, // SUBS_S_W + 0U, // SUBS_U_B + 0U, // SUBS_U_D + 0U, // SUBS_U_H + 0U, // SUBS_U_W + 0U, // SUBU16_MM + 0U, // SUBUH_QB + 0U, // SUBUH_R_QB + 0U, // SUBU_PH + 0U, // SUBU_QB + 0U, // SUBU_S_PH + 0U, // SUBU_S_QB + 0U, // SUBVI_B + 0U, // SUBVI_D + 0U, // SUBVI_H + 0U, // SUBVI_W + 0U, // SUBV_B + 0U, // SUBV_D + 0U, // SUBV_H + 0U, // SUBV_W + 0U, // SUB_MM + 0U, // SUBu + 0U, // SUBu_MM + 0U, // SUXC1 + 0U, // SUXC164 + 0U, // SUXC1_MM + 0U, // SW + 0U, // SW16_MM + 0U, // SW64 + 0U, // SWC1 + 0U, // SWC1_MM + 0U, // SWC2 + 0U, // SWC2_R6 + 0U, // SWC3 + 0U, // SWL + 0U, // SWL64 + 0U, // SWL_MM + 0U, // SWM16_MM + 0U, // SWM32_MM + 0U, // SWM_MM + 0U, // SWP_MM + 0U, // SWR + 0U, // SWR64 + 0U, // SWR_MM + 0U, // SWSP_MM + 0U, // SWXC1 + 0U, // SWXC1_MM + 0U, // SW_MM + 0U, // SYNC + 0U, // SYNCI + 0U, // SYNC_MM + 0U, // SYSCALL + 0U, // SYSCALL_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 0U, // Save16 + 0U, // SaveX16 + 0U, // SbRxRyOffMemX16 + 0U, // SebRx16 + 0U, // SehRx16 + 0U, // SelBeqZ + 0U, // SelBneZ + 0U, // SelTBteqZCmp + 0U, // SelTBteqZCmpi + 0U, // SelTBteqZSlt + 0U, // SelTBteqZSlti + 0U, // SelTBteqZSltiu + 0U, // SelTBteqZSltu + 0U, // SelTBtneZCmp + 0U, // SelTBtneZCmpi + 0U, // SelTBtneZSlt + 0U, // SelTBtneZSlti + 0U, // SelTBtneZSltiu + 0U, // SelTBtneZSltu + 0U, // ShRxRyOffMemX16 + 1U, // SllX16 + 0U, // SllvRxRy16 + 0U, // SltCCRxRy16 + 0U, // SltRxRy16 + 0U, // SltiCCRxImmX16 + 0U, // SltiRxImm16 + 0U, // SltiRxImmX16 + 0U, // SltiuCCRxImmX16 + 0U, // SltiuRxImm16 + 0U, // SltiuRxImmX16 + 0U, // SltuCCRxRy16 + 0U, // SltuRxRy16 + 0U, // SltuRxRyRz16 + 1U, // SraX16 + 0U, // SravRxRy16 + 1U, // SrlX16 + 0U, // SrlvRxRy16 + 0U, // SubuRxRyRz16 + 0U, // SwRxRyOffMemX16 + 0U, // SwRxSpImmX16 + 0U, // TAILCALL + 0U, // TAILCALL64_R + 0U, // TAILCALL_R + 1U, // TEQ + 0U, // TEQI + 0U, // TEQI_MM + 1U, // TEQ_MM + 1U, // TGE + 0U, // TGEI + 0U, // TGEIU + 0U, // TGEIU_MM + 0U, // TGEI_MM + 1U, // TGEU + 1U, // TGEU_MM + 1U, // TGE_MM + 0U, // TLBP + 0U, // TLBP_MM + 0U, // TLBR + 0U, // TLBR_MM + 0U, // TLBWI + 0U, // TLBWI_MM + 0U, // TLBWR + 0U, // TLBWR_MM + 1U, // TLT + 0U, // TLTI + 0U, // TLTIU_MM + 0U, // TLTI_MM + 1U, // TLTU + 1U, // TLTU_MM + 1U, // TLT_MM + 1U, // TNE + 0U, // TNEI + 0U, // TNEI_MM + 1U, // TNE_MM + 0U, // TRAP + 0U, // TRUNC_L_D64 + 0U, // TRUNC_L_S + 0U, // TRUNC_W_D32 + 0U, // TRUNC_W_D64 + 0U, // TRUNC_W_MM + 0U, // TRUNC_W_S + 0U, // TRUNC_W_S_MM + 0U, // TTLTIU + 0U, // UDIV + 0U, // UDIV_MM + 0U, // V3MULU + 0U, // VMM0 + 0U, // VMULU + 2U, // VSHF_B + 2U, // VSHF_D + 2U, // VSHF_H + 2U, // VSHF_W + 0U, // WAIT + 0U, // WAIT_MM + 0U, // WRDSP + 0U, // WSBH + 0U, // WSBH_MM + 0U, // XOR + 0U, // XOR16_MM + 0U, // XOR64 + 0U, // XORI_B + 0U, // XOR_MM + 0U, // XOR_V + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 1U, // XORi + 1U, // XORi64 + 1U, // XORi_MM + 0U, // XorRxRxRy16 + 0U}; #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0, - /* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0, - /* 15 */ 'd', 'm', 't', 'c', '0', 9, 0, - /* 22 */ 'v', 'm', 'm', '0', 9, 0, - /* 28 */ 'm', 't', 'm', '0', 9, 0, - /* 34 */ 'm', 't', 'p', '0', 9, 0, - /* 40 */ 'b', 'b', 'i', 't', '0', 9, 0, - /* 47 */ 'l', 'd', 'c', '1', 9, 0, - /* 53 */ 's', 'd', 'c', '1', 9, 0, - /* 59 */ 'c', 'f', 'c', '1', 9, 0, - /* 65 */ 'd', 'm', 'f', 'c', '1', 9, 0, - /* 72 */ 'm', 'f', 'h', 'c', '1', 9, 0, - /* 79 */ 'm', 't', 'h', 'c', '1', 9, 0, - /* 86 */ 'c', 't', 'c', '1', 9, 0, - /* 92 */ 'd', 'm', 't', 'c', '1', 9, 0, - /* 99 */ 'l', 'w', 'c', '1', 9, 0, - /* 105 */ 's', 'w', 'c', '1', 9, 0, - /* 111 */ 'l', 'd', 'x', 'c', '1', 9, 0, - /* 118 */ 's', 'd', 'x', 'c', '1', 9, 0, - /* 125 */ 'l', 'u', 'x', 'c', '1', 9, 0, - /* 132 */ 's', 'u', 'x', 'c', '1', 9, 0, - /* 139 */ 'l', 'w', 'x', 'c', '1', 9, 0, - /* 146 */ 's', 'w', 'x', 'c', '1', 9, 0, - /* 153 */ 'm', 't', 'm', '1', 9, 0, - /* 159 */ 'm', 't', 'p', '1', 9, 0, - /* 165 */ 'b', 'b', 'i', 't', '1', 9, 0, - /* 172 */ 'b', 'b', 'i', 't', '0', '3', '2', 9, 0, - /* 181 */ 'b', 'b', 'i', 't', '1', '3', '2', 9, 0, - /* 190 */ 'd', 's', 'r', 'a', '3', '2', 9, 0, - /* 198 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 9, 0, - /* 208 */ 'd', 's', 'l', 'l', '3', '2', 9, 0, - /* 216 */ 'd', 's', 'r', 'l', '3', '2', 9, 0, - /* 224 */ 'l', 'w', 'm', '3', '2', 9, 0, - /* 231 */ 's', 'w', 'm', '3', '2', 9, 0, - /* 238 */ 'd', 'r', 'o', 't', 'r', '3', '2', 9, 0, - /* 247 */ 'l', 'd', 'c', '2', 9, 0, - /* 253 */ 's', 'd', 'c', '2', 9, 0, - /* 259 */ 'd', 'm', 'f', 'c', '2', 9, 0, - /* 266 */ 'd', 'm', 't', 'c', '2', 9, 0, - /* 273 */ 'l', 'w', 'c', '2', 9, 0, - /* 279 */ 's', 'w', 'c', '2', 9, 0, - /* 285 */ 'm', 't', 'm', '2', 9, 0, - /* 291 */ 'm', 't', 'p', '2', 9, 0, - /* 297 */ 'a', 'd', 'd', 'i', 'u', 'r', '2', 9, 0, - /* 306 */ 'l', 'd', 'c', '3', 9, 0, - /* 312 */ 's', 'd', 'c', '3', 9, 0, - /* 318 */ 'l', 'w', 'c', '3', 9, 0, - /* 324 */ 's', 'w', 'c', '3', 9, 0, - /* 330 */ 'a', 'd', 'd', 'i', 'u', 's', '5', 9, 0, - /* 339 */ 's', 'b', '1', '6', 9, 0, - /* 345 */ 'a', 'n', 'd', '1', '6', 9, 0, - /* 352 */ 's', 'h', '1', '6', 9, 0, - /* 358 */ 'a', 'n', 'd', 'i', '1', '6', 9, 0, - /* 366 */ 'l', 'i', '1', '6', 9, 0, - /* 372 */ 'b', 'r', 'e', 'a', 'k', '1', '6', 9, 0, - /* 381 */ 's', 'l', 'l', '1', '6', 9, 0, - /* 388 */ 's', 'r', 'l', '1', '6', 9, 0, - /* 395 */ 'l', 'w', 'm', '1', '6', 9, 0, - /* 402 */ 's', 'w', 'm', '1', '6', 9, 0, - /* 409 */ 's', 'd', 'b', 'b', 'p', '1', '6', 9, 0, - /* 418 */ 'j', 'r', '1', '6', 9, 0, - /* 424 */ 'x', 'o', 'r', '1', '6', 9, 0, - /* 431 */ 'j', 'a', 'l', 'r', 's', '1', '6', 9, 0, - /* 440 */ 'n', 'o', 't', '1', '6', 9, 0, - /* 447 */ 'l', 'b', 'u', '1', '6', 9, 0, - /* 454 */ 's', 'u', 'b', 'u', '1', '6', 9, 0, - /* 462 */ 'a', 'd', 'd', 'u', '1', '6', 9, 0, - /* 470 */ 'l', 'h', 'u', '1', '6', 9, 0, - /* 477 */ 'l', 'w', '1', '6', 9, 0, - /* 483 */ 's', 'w', '1', '6', 9, 0, - /* 489 */ 'b', 'n', 'e', 'z', '1', '6', 9, 0, - /* 497 */ 'b', 'e', 'q', 'z', '1', '6', 9, 0, - /* 505 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, - /* 521 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, - /* 538 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, - /* 554 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, - /* 571 */ 'd', 's', 'r', 'a', 9, 0, - /* 577 */ 'd', 'l', 's', 'a', 9, 0, - /* 583 */ 'c', 'f', 'c', 'm', 's', 'a', 9, 0, - /* 591 */ 'c', 't', 'c', 'm', 's', 'a', 9, 0, - /* 599 */ 'a', 'd', 'd', '_', 'a', '.', 'b', 9, 0, - /* 608 */ 'm', 'i', 'n', '_', 'a', '.', 'b', 9, 0, - /* 617 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'b', 9, 0, - /* 627 */ 'm', 'a', 'x', '_', 'a', '.', 'b', 9, 0, - /* 636 */ 's', 'r', 'a', '.', 'b', 9, 0, - /* 643 */ 'n', 'l', 'o', 'c', '.', 'b', 9, 0, - /* 651 */ 'n', 'l', 'z', 'c', '.', 'b', 9, 0, - /* 659 */ 's', 'l', 'd', '.', 'b', 9, 0, - /* 666 */ 'p', 'c', 'k', 'o', 'd', '.', 'b', 9, 0, - /* 675 */ 'i', 'l', 'v', 'o', 'd', '.', 'b', 9, 0, - /* 684 */ 'i', 'n', 's', 'v', 'e', '.', 'b', 9, 0, - /* 693 */ 'v', 's', 'h', 'f', '.', 'b', 9, 0, - /* 701 */ 'b', 'n', 'e', 'g', '.', 'b', 9, 0, - /* 709 */ 's', 'r', 'a', 'i', '.', 'b', 9, 0, - /* 717 */ 's', 'l', 'd', 'i', '.', 'b', 9, 0, - /* 725 */ 'a', 'n', 'd', 'i', '.', 'b', 9, 0, - /* 733 */ 'b', 'n', 'e', 'g', 'i', '.', 'b', 9, 0, - /* 742 */ 'b', 's', 'e', 'l', 'i', '.', 'b', 9, 0, - /* 751 */ 's', 'l', 'l', 'i', '.', 'b', 9, 0, - /* 759 */ 's', 'r', 'l', 'i', '.', 'b', 9, 0, - /* 767 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'b', 9, 0, - /* 777 */ 'c', 'e', 'q', 'i', '.', 'b', 9, 0, - /* 785 */ 's', 'r', 'a', 'r', 'i', '.', 'b', 9, 0, - /* 794 */ 'b', 'c', 'l', 'r', 'i', '.', 'b', 9, 0, - /* 803 */ 's', 'r', 'l', 'r', 'i', '.', 'b', 9, 0, - /* 812 */ 'n', 'o', 'r', 'i', '.', 'b', 9, 0, - /* 820 */ 'x', 'o', 'r', 'i', '.', 'b', 9, 0, - /* 828 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'b', 9, 0, - /* 838 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'b', 9, 0, - /* 848 */ 'b', 's', 'e', 't', 'i', '.', 'b', 9, 0, - /* 857 */ 's', 'u', 'b', 'v', 'i', '.', 'b', 9, 0, - /* 866 */ 'a', 'd', 'd', 'v', 'i', '.', 'b', 9, 0, - /* 875 */ 'b', 'm', 'z', 'i', '.', 'b', 9, 0, - /* 883 */ 'b', 'm', 'n', 'z', 'i', '.', 'b', 9, 0, - /* 892 */ 'f', 'i', 'l', 'l', '.', 'b', 9, 0, - /* 900 */ 's', 'l', 'l', '.', 'b', 9, 0, - /* 907 */ 's', 'r', 'l', '.', 'b', 9, 0, - /* 914 */ 'b', 'i', 'n', 's', 'l', '.', 'b', 9, 0, - /* 923 */ 'i', 'l', 'v', 'l', '.', 'b', 9, 0, - /* 931 */ 'c', 'e', 'q', '.', 'b', 9, 0, - /* 938 */ 's', 'r', 'a', 'r', '.', 'b', 9, 0, - /* 946 */ 'b', 'c', 'l', 'r', '.', 'b', 9, 0, - /* 954 */ 's', 'r', 'l', 'r', '.', 'b', 9, 0, - /* 962 */ 'b', 'i', 'n', 's', 'r', '.', 'b', 9, 0, - /* 971 */ 'i', 'l', 'v', 'r', '.', 'b', 9, 0, - /* 979 */ 'a', 's', 'u', 'b', '_', 's', '.', 'b', 9, 0, - /* 989 */ 'm', 'o', 'd', '_', 's', '.', 'b', 9, 0, - /* 998 */ 'c', 'l', 'e', '_', 's', '.', 'b', 9, 0, - /* 1007 */ 'a', 'v', 'e', '_', 's', '.', 'b', 9, 0, - /* 1016 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'b', 9, 0, - /* 1026 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'b', 9, 0, - /* 1036 */ 'c', 'l', 't', 'i', '_', 's', '.', 'b', 9, 0, - /* 1046 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'b', 9, 0, - /* 1056 */ 'm', 'i', 'n', '_', 's', '.', 'b', 9, 0, - /* 1065 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'b', 9, 0, - /* 1075 */ 's', 'u', 'b', 's', '_', 's', '.', 'b', 9, 0, - /* 1085 */ 'a', 'd', 'd', 's', '_', 's', '.', 'b', 9, 0, - /* 1095 */ 's', 'a', 't', '_', 's', '.', 'b', 9, 0, - /* 1104 */ 'c', 'l', 't', '_', 's', '.', 'b', 9, 0, - /* 1113 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'b', 9, 0, - /* 1125 */ 'd', 'i', 'v', '_', 's', '.', 'b', 9, 0, - /* 1134 */ 'm', 'a', 'x', '_', 's', '.', 'b', 9, 0, - /* 1143 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'b', 9, 0, - /* 1153 */ 's', 'p', 'l', 'a', 't', '.', 'b', 9, 0, - /* 1162 */ 'b', 's', 'e', 't', '.', 'b', 9, 0, - /* 1170 */ 'p', 'c', 'n', 't', '.', 'b', 9, 0, - /* 1178 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'b', 9, 0, - /* 1188 */ 's', 't', '.', 'b', 9, 0, - /* 1194 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'b', 9, 0, - /* 1204 */ 'm', 'o', 'd', '_', 'u', '.', 'b', 9, 0, - /* 1213 */ 'c', 'l', 'e', '_', 'u', '.', 'b', 9, 0, - /* 1222 */ 'a', 'v', 'e', '_', 'u', '.', 'b', 9, 0, - /* 1231 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1241 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1251 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1261 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'b', 9, 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'q', 'b', 9, 0, - /* 1782 */ 's', 'b', 9, 0, - /* 1786 */ 'm', 'o', 'd', 's', 'u', 'b', 9, 0, - /* 1794 */ 'm', 's', 'u', 'b', 9, 0, - /* 1800 */ 'b', 'c', 9, 0, - /* 1804 */ 'b', 'g', 'e', 'c', 9, 0, - /* 1810 */ 'b', 'n', 'e', 'c', 9, 0, - /* 1816 */ 'j', 'i', 'c', 9, 0, - /* 1821 */ 'b', 'a', 'l', 'c', 9, 0, - /* 1827 */ 'j', 'i', 'a', 'l', 'c', 9, 0, - /* 1834 */ 'b', 'g', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1843 */ 'b', 'l', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1852 */ 'b', 'n', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1861 */ 'b', 'e', 'q', 'z', 'a', 'l', 'c', 9, 0, - /* 1870 */ 'b', 'g', 't', 'z', 'a', 'l', 'c', 9, 0, - /* 1879 */ 'b', 'l', 't', 'z', 'a', 'l', 'c', 9, 0, - /* 1888 */ 'l', 'd', 'p', 'c', 9, 0, - /* 1894 */ 'a', 'u', 'i', 'p', 'c', 9, 0, - /* 1901 */ 'a', 'l', 'u', 'i', 'p', 'c', 9, 0, - /* 1909 */ 'a', 'd', 'd', 'i', 'u', 'p', 'c', 9, 0, - /* 1918 */ 'l', 'w', 'u', 'p', 'c', 9, 0, - /* 1925 */ 'l', 'w', 'p', 'c', 9, 0, - /* 1931 */ 'b', 'e', 'q', 'c', 9, 0, - /* 1937 */ 'j', 'r', 'c', 9, 0, - /* 1942 */ 'a', 'd', 'd', 's', 'c', 9, 0, - /* 1949 */ 'b', 'l', 't', 'c', 9, 0, - /* 1955 */ 'b', 'g', 'e', 'u', 'c', 9, 0, - /* 1962 */ 'b', 'l', 't', 'u', 'c', 9, 0, - /* 1969 */ 'b', 'n', 'v', 'c', 9, 0, - /* 1975 */ 'b', 'o', 'v', 'c', 9, 0, - /* 1981 */ 'a', 'd', 'd', 'w', 'c', 9, 0, - /* 1988 */ 'b', 'g', 'e', 'z', 'c', 9, 0, - /* 1995 */ 'b', 'l', 'e', 'z', 'c', 9, 0, - /* 2002 */ 'b', 'n', 'e', 'z', 'c', 9, 0, - /* 2009 */ 'b', 'e', 'q', 'z', 'c', 9, 0, - /* 2016 */ 'b', 'g', 't', 'z', 'c', 9, 0, - /* 2023 */ 'b', 'l', 't', 'z', 'c', 9, 0, - /* 2030 */ 'f', 'l', 'o', 'g', '2', '.', 'd', 9, 0, - /* 2039 */ 'f', 'e', 'x', 'p', '2', '.', 'd', 9, 0, - /* 2048 */ 'a', 'd', 'd', '_', 'a', '.', 'd', 9, 0, - /* 2057 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'd', 9, 0, - /* 2067 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'd', 9, 0, - /* 2077 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'd', 9, 0, - /* 2087 */ 'm', 'i', 'n', 'a', '.', 'd', 9, 0, - /* 2095 */ 's', 'r', 'a', '.', 'd', 9, 0, - /* 2102 */ 'm', 'a', 'x', 'a', '.', 'd', 9, 0, - /* 2110 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, - /* 2118 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, - /* 2127 */ 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, - /* 2136 */ 'n', 'l', 'o', 'c', '.', 'd', 9, 0, - /* 2144 */ 'n', 'l', 'z', 'c', '.', 'd', 9, 0, - /* 2152 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 2160 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 2169 */ 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 2178 */ 's', 'l', 'd', '.', 'd', 9, 0, - /* 2185 */ 'p', 'c', 'k', 'o', 'd', '.', 'd', 9, 0, - /* 2194 */ 'i', 'l', 'v', 'o', 'd', '.', 'd', 9, 0, - /* 2203 */ 'c', '.', 'n', 'g', 'e', '.', 'd', 9, 0, - /* 2212 */ 'c', '.', 'l', 'e', '.', 'd', 9, 0, - /* 2220 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'd', 9, 0, - /* 2230 */ 'f', 'c', 'l', 'e', '.', 'd', 9, 0, - /* 2238 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 'd', 9, 0, - /* 2248 */ 'c', '.', 'o', 'l', 'e', '.', 'd', 9, 0, - /* 2257 */ 'c', 'm', 'p', '.', 's', 'l', 'e', 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2431 */ 'v', 's', 'h', 'f', '.', 'd', 9, 0, - /* 2439 */ 'c', '.', 's', 'f', '.', 'd', 9, 0, - /* 2447 */ 'm', 'o', 'v', 'f', '.', 'd', 9, 0, - /* 2455 */ 'b', 'n', 'e', 'g', '.', 'd', 9, 0, - /* 2463 */ 's', 'r', 'a', 'i', '.', 'd', 9, 0, - /* 2471 */ 's', 'l', 'd', 'i', '.', 'd', 9, 0, - /* 2479 */ 'b', 'n', 'e', 'g', 'i', '.', 'd', 9, 0, - /* 2488 */ 's', 'l', 'l', 'i', '.', 'd', 9, 0, - /* 2496 */ 's', 'r', 'l', 'i', '.', 'd', 9, 0, - /* 2504 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'd', 9, 0, - /* 2514 */ 'c', 'e', 'q', 'i', '.', 'd', 9, 0, - /* 2522 */ 's', 'r', 'a', 'r', 'i', '.', 'd', 9, 0, - /* 2531 */ 'b', 'c', 'l', 'r', 'i', '.', 'd', 9, 0, - /* 2540 */ 's', 'r', 'l', 'r', 'i', '.', 'd', 9, 0, - /* 2549 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'd', 9, 0, - /* 2559 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'd', 9, 0, - /* 2569 */ 'b', 's', 'e', 't', 'i', '.', 'd', 9, 0, - /* 2578 */ 's', 'u', 'b', 'v', 'i', '.', 'd', 9, 0, - /* 2587 */ 'a', 'd', 'd', 'v', 'i', '.', 'd', 9, 0, - /* 2596 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 'd', 9, 0, - /* 2607 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 'd', 9, 0, - /* 2618 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 'd', 9, 0, - /* 2628 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 'd', 9, 0, - /* 2639 */ 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, - /* 2648 */ 's', 'e', 'l', '.', 'd', 9, 0, - /* 2655 */ 'c', '.', 'n', 'g', 'l', '.', 'd', 9, 0, - /* 2664 */ 'f', 'i', 'l', 'l', '.', 'd', 9, 0, - /* 2672 */ 's', 'l', 'l', '.', 'd', 9, 0, - /* 2679 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'd', 9, 0, - /* 2689 */ 'f', 'f', 'q', 'l', '.', 'd', 9, 0, - /* 2697 */ 's', 'r', 'l', '.', 'd', 9, 0, - /* 2704 */ 'b', 'i', 'n', 's', 'l', '.', 'd', 9, 0, - /* 2713 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, - /* 2721 */ 'i', 'l', 'v', 'l', '.', 'd', 9, 0, - /* 2729 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, - /* 2737 */ 'c', '.', 'u', 'n', '.', 'd', 9, 0, - /* 2745 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 'd', 9, 0, - /* 2755 */ 'f', 'c', 'u', 'n', '.', 'd', 9, 0, - /* 2763 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 'd', 9, 0, - /* 2774 */ 'f', 's', 'u', 'n', '.', 'd', 9, 0, - /* 2782 */ 'm', 'o', 'v', 'n', '.', 'd', 9, 0, - /* 2790 */ 'f', 'r', 'c', 'p', '.', 'd', 9, 0, - /* 2798 */ 'c', '.', 'e', 'q', '.', 'd', 9, 0, - /* 2806 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'd', 9, 0, - /* 2816 */ 'f', 'c', 'e', 'q', '.', 'd', 9, 0, - /* 2824 */ 'c', '.', 's', 'e', 'q', '.', 'd', 9, 0, - /* 2833 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 'd', 9, 0, - /* 2844 */ 'f', 's', 'e', 'q', '.', 'd', 9, 0, - /* 2852 */ 'c', '.', 'u', 'e', 'q', '.', 'd', 9, 0, - /* 2861 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 'd', 9, 0, - /* 2872 */ 'f', 'c', 'u', 'e', 'q', '.', 'd', 9, 0, - /* 2881 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 'd', 9, 0, - /* 2893 */ 'f', 's', 'u', 'e', 'q', '.', 'd', 9, 0, - /* 2902 */ 's', 'r', 'a', 'r', '.', 'd', 9, 0, - /* 2910 */ 'b', 'c', 'l', 'r', '.', 'd', 9, 0, - /* 2918 */ 's', 'r', 'l', 'r', '.', 'd', 9, 0, - /* 2926 */ 'f', 'c', 'o', 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6091 */ 'd', 'b', 'i', 't', 's', 'w', 'a', 'p', 9, 0, - /* 6101 */ 's', 'd', 'b', 'b', 'p', 9, 0, - /* 6108 */ 'e', 'x', 't', 'p', 'd', 'p', 9, 0, - /* 6116 */ 'm', 'o', 'v', 'e', 'p', 9, 0, - /* 6123 */ 'm', 't', 'h', 'l', 'i', 'p', 9, 0, - /* 6131 */ 'c', 'm', 'p', 9, 0, - /* 6136 */ 'd', 'p', 'o', 'p', 9, 0, - /* 6142 */ 'a', 'd', 'd', 'i', 'u', 'r', '1', 's', 'p', 9, 0, - /* 6153 */ 'l', 'o', 'a', 'd', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0, - /* 6169 */ 's', 't', 'o', 'r', 'e', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0, - /* 6186 */ 'r', 'd', 'd', 's', 'p', 9, 0, - /* 6193 */ 'w', 'r', 'd', 's', 'p', 9, 0, - /* 6200 */ 'j', 'r', 'a', 'd', 'd', 'i', 'u', 's', 'p', 9, 0, - /* 6211 */ 'e', 'x', 't', 'p', 9, 0, - /* 6217 */ 'l', 'w', 'p', 9, 0, - /* 6222 */ 's', 'w', 'p', 9, 0, - /* 6227 */ 'b', 'e', 'q', 9, 0, - /* 6232 */ 's', 'e', 'q', 9, 0, - /* 6237 */ 't', 'e', 'q', 9, 0, - /* 6242 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0, - /* 6254 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'r', 'v', 9, 0, - /* 7408 */ 'i', 'n', 's', 'v', 9, 0, - /* 7414 */ 'f', 'l', 'o', 'g', '2', '.', 'w', 9, 0, - /* 7423 */ 'f', 'e', 'x', 'p', '2', '.', 'w', 9, 0, - /* 7432 */ 'a', 'd', 'd', '_', 'a', '.', 'w', 9, 0, - /* 7441 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'w', 9, 0, - /* 7451 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'w', 9, 0, - /* 7461 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'w', 9, 0, - /* 7471 */ 's', 'r', 'a', '.', 'w', 9, 0, - /* 7478 */ 'f', 's', 'u', 'b', '.', 'w', 9, 0, - /* 7486 */ 'f', 'm', 's', 'u', 'b', '.', 'w', 9, 0, - /* 7495 */ 'n', 'l', 'o', 'c', '.', 'w', 9, 0, - /* 7503 */ 'n', 'l', 'z', 'c', '.', 'w', 9, 0, - /* 7511 */ 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, - /* 7520 */ 'f', 'a', 'd', 'd', '.', 'w', 9, 0, - /* 7528 */ 'f', 'm', 'a', 'd', 'd', '.', 'w', 9, 0, - /* 7537 */ 's', 'l', 'd', '.', 'w', 9, 0, - /* 7544 */ 'p', 'c', 'k', 'o', 'd', '.', 'w', 9, 0, - /* 7553 */ 'i', 'l', 'v', 'o', 'd', '.', 'w', 9, 0, - /* 7562 */ 'f', 'c', 'l', 'e', '.', 'w', 9, 0, - /* 7570 */ 'f', 's', 'l', 'e', '.', 'w', 9, 0, - /* 7578 */ 'f', 'c', 'u', 'l', 'e', '.', 'w', 9, 0, - /* 7587 */ 'f', 's', 'u', 'l', 'e', '.', 'w', 9, 0, - /* 7596 */ 'f', 'c', 'n', 'e', '.', 'w', 9, 0, - /* 7604 */ 'f', 's', 'n', 'e', '.', 'w', 9, 0, - /* 7612 */ 'f', 'c', 'u', 'n', 'e', '.', 'w', 9, 0, - /* 7621 */ 'f', 's', 'u', 'n', 'e', '.', 'w', 9, 0, - /* 7630 */ 'i', 'n', 's', 'v', 'e', '.', 'w', 9, 0, - /* 7639 */ 'f', 'c', 'a', 'f', '.', 'w', 9, 0, - /* 7647 */ 'f', 's', 'a', 'f', '.', 'w', 9, 0, - /* 7655 */ 'v', 's', 'h', 'f', '.', 'w', 9, 0, - /* 7663 */ 'b', 'n', 'e', 'g', '.', 'w', 9, 0, - /* 7671 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '.', 'p', 'h', '.', 'w', 9, 0, - /* 7687 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'p', 'h', '.', 'w', 9, 0, - /* 7700 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '_', 'r', '.', 'p', 'h', '.', 'w', 9, 0, - /* 7718 */ 'p', 'r', 'e', 'c', 'r', 'q', '_', 'r', 's', '.', 'p', 'h', '.', 'w', 9, 0, - /* 7734 */ 's', 'u', 'b', 'q', 'h', '.', 'w', 9, 0, - /* 7743 */ 'a', 'd', 'd', 'q', 'h', '.', 'w', 9, 0, - /* 7752 */ 's', 'r', 'a', 'i', '.', 'w', 9, 0, - /* 7760 */ 's', 'l', 'd', 'i', '.', 'w', 9, 0, - /* 7768 */ 'b', 'n', 'e', 'g', 'i', '.', 'w', 9, 0, - /* 7777 */ 's', 'l', 'l', 'i', '.', 'w', 9, 0, - /* 7785 */ 's', 'r', 'l', 'i', '.', 'w', 9, 0, - /* 7793 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'w', 9, 0, - /* 7803 */ 'c', 'e', 'q', 'i', '.', 'w', 9, 0, - /* 7811 */ 's', 'r', 'a', 'r', 'i', '.', 'w', 9, 0, - /* 7820 */ 'b', 'c', 'l', 'r', 'i', '.', 'w', 9, 0, - /* 7829 */ 's', 'r', 'l', 'r', 'i', '.', 'w', 9, 0, - /* 7838 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'w', 9, 0, - /* 7848 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'w', 9, 0, - /* 7858 */ 'b', 's', 'e', 't', 'i', '.', 'w', 9, 0, - /* 7867 */ 's', 'u', 'b', 'v', 'i', '.', 'w', 9, 0, - /* 7876 */ 'a', 'd', 'd', 'v', 'i', '.', 'w', 9, 0, - /* 7885 */ 'd', 'p', 'a', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, - /* 7898 */ 'd', 'p', 's', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, - /* 7911 */ 'f', 'i', 'l', 'l', '.', 'w', 9, 0, - /* 7919 */ 's', 'l', 'l', '.', 'w', 9, 0, - /* 7926 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'w', 9, 0, - /* 7936 */ 'f', 'f', 'q', 'l', '.', 'w', 9, 0, - /* 7944 */ 's', 'r', 'l', '.', 'w', 9, 0, - /* 7951 */ 'b', 'i', 'n', 's', 'l', '.', 'w', 9, 0, - /* 7960 */ 'f', 'm', 'u', 'l', '.', 'w', 9, 0, - /* 7968 */ 'i', 'l', 'v', 'l', '.', 'w', 9, 0, - /* 7976 */ 'f', 'm', 'i', 'n', '.', 'w', 9, 0, - /* 7984 */ 'f', 'c', 'u', 'n', '.', 'w', 9, 0, - /* 7992 */ 'f', 's', 'u', 'n', '.', 'w', 9, 0, - /* 8000 */ 'f', 'e', 'x', 'd', 'o', '.', 'w', 9, 0, - /* 8009 */ 'f', 'r', 'c', 'p', '.', 'w', 9, 0, - /* 8017 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'w', 9, 0, - /* 8027 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'w', 9, 0, - /* 8037 */ 'm', 'u', 'l', '_', 'q', '.', 'w', 9, 0, - /* 8046 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'w', 9, 0, - /* 8057 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'w', 9, 0, - /* 8068 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'w', 9, 0, - /* 8078 */ 'f', 'c', 'e', 'q', '.', 'w', 9, 0, - /* 8086 */ 'f', 's', 'e', 'q', '.', 'w', 9, 0, - /* 8094 */ 'f', 'c', 'u', 'e', 'q', '.', 'w', 9, 0, - /* 8103 */ 'f', 's', 'u', 'e', 'q', '.', 'w', 9, 0, - /* 8112 */ 'f', 't', 'q', '.', 'w', 9, 0, - /* 8119 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'w', 9, 0, - /* 8129 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'w', 9, 0, - /* 8140 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'w', 9, 0, - /* 8151 */ 'e', 'x', 't', 'r', '_', 'r', '.', 'w', 9, 0, - /* 8161 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'w', 9, 0, - /* 8172 */ 'e', 'x', 't', 'r', 'v', '_', 'r', '.', 'w', 9, 0, - /* 8183 */ 's', 'r', 'a', 'r', '.', 'w', 9, 0, - /* 8191 */ 'b', 'c', 'l', 'r', '.', 'w', 9, 0, - /* 8199 */ 's', 'r', 'l', 'r', '.', 'w', 9, 0, - /* 8207 */ 'f', 'c', 'o', 'r', '.', 'w', 9, 0, - /* 8215 */ 'f', 's', 'o', 'r', '.', 'w', 9, 0, - /* 8223 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'w', 9, 0, - /* 8233 */ 'f', 'f', 'q', 'r', '.', 'w', 9, 0, - /* 8241 */ 'b', 'i', 'n', 's', 'r', '.', 'w', 9, 0, - /* 8250 */ 'e', 'x', 't', 'r', '.', 'w', 9, 0, - /* 8258 */ 'i', 'l', 'v', 'r', '.', 'w', 9, 0, - /* 8266 */ 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, - /* 8275 */ 'a', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, - /* 8285 */ 'h', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, - /* 8295 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, - /* 8306 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'w', 9, 0, - /* 8318 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, - /* 8328 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, - /* 8339 */ 'm', 'o', 'd', '_', 's', '.', 'w', 9, 0, - /* 8348 */ 'c', 'l', 'e', '_', 's', '.', 'w', 9, 0, - /* 8357 */ 'a', 'v', 'e', '_', 's', '.', 'w', 9, 0, - /* 8366 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'w', 9, 0, - /* 8376 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'w', 9, 0, - /* 8386 */ 'c', 'l', 't', 'i', '_', 's', '.', 'w', 9, 0, - /* 8396 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'w', 9, 0, - /* 8406 */ 's', 'h', 'l', 'l', '_', 's', '.', 'w', 9, 0, - /* 8416 */ 'm', 'i', 'n', '_', 's', '.', 'w', 9, 0, - /* 8425 */ 'd', 'o', 't', 'p', '_', 's', '.', 'w', 9, 0, - /* 8435 */ 's', 'u', 'b', 'q', '_', 's', '.', 'w', 9, 0, - /* 8445 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'w', 9, 0, - /* 8455 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'w', 9, 0, - /* 8465 */ 'a', 'b', 's', 'q', '_', 's', '.', 'w', 9, 0, - /* 8475 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'w', 9, 0, - /* 8485 */ 's', 'u', 'b', 's', '_', 's', '.', 'w', 9, 0, - /* 8495 */ 'a', 'd', 'd', 's', '_', 's', '.', 'w', 9, 0, - /* 8505 */ 's', 'a', 't', '_', 's', '.', 'w', 9, 0, - /* 8514 */ 'c', 'l', 't', '_', 's', '.', 'w', 9, 0, - /* 8523 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, - /* 8534 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, - /* 8545 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'w', 9, 0, - /* 8557 */ 'd', 'i', 'v', '_', 's', '.', 'w', 9, 0, - /* 8566 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'w', 9, 0, - /* 8577 */ 'm', 'a', 'x', '_', 's', '.', 'w', 9, 0, - /* 8586 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'w', 9, 0, - /* 8596 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'w', 9, 0, - /* 8607 */ 'e', 'x', 't', 'r', '_', 'r', 's', '.', 'w', 9, 0, - /* 8618 */ 'e', 'x', 't', 'r', 'v', '_', 'r', 's', '.', 'w', 9, 0, - /* 8630 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'w', 9, 0, - /* 8640 */ 's', 'p', 'l', 'a', 't', '.', 'w', 9, 0, - /* 8649 */ 'b', 's', 'e', 't', '.', 'w', 9, 0, - /* 8657 */ 'f', 'c', 'l', 't', '.', 'w', 9, 0, - /* 8665 */ 'f', 's', 'l', 't', '.', 'w', 9, 0, - /* 8673 */ 'f', 'c', 'u', 'l', 't', '.', 'w', 9, 0, - /* 8682 */ 'f', 's', 'u', 'l', 't', '.', 'w', 9, 0, - /* 8691 */ 'p', 'c', 'n', 't', '.', 'w', 9, 0, - /* 8699 */ 'f', 'r', 'i', 'n', 't', '.', 'w', 9, 0, - /* 8708 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'w', 9, 0, - /* 8718 */ 'f', 's', 'q', 'r', 't', '.', 'w', 9, 0, - /* 8727 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'w', 9, 0, - /* 8737 */ 's', 't', '.', 'w', 9, 0, - /* 8743 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8753 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8763 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8774 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'w', 9, 0, - /* 8786 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8796 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8807 */ 'm', 'o', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8816 */ 'c', 'l', 'e', '_', 'u', '.', 'w', 9, 0, - /* 8825 */ 'a', 'v', 'e', '_', 'u', '.', 'w', 9, 0, - /* 8834 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8844 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8854 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8864 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8874 */ 'm', 'i', 'n', '_', 'u', '.', 'w', 9, 0, - /* 8883 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'w', 9, 0, - /* 8893 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'w', 9, 0, - /* 8903 */ 's', 'u', 'b', 's', '_', 'u', '.', 'w', 9, 0, - /* 8913 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'w', 9, 0, - /* 8923 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'w', 9, 0, - /* 8935 */ 's', 'a', 't', '_', 'u', '.', 'w', 9, 0, - /* 8944 */ 'c', 'l', 't', '_', 'u', '.', 'w', 9, 0, - /* 8953 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, - /* 8964 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, - /* 8975 */ 'd', 'i', 'v', '_', 'u', '.', 'w', 9, 0, - /* 8984 */ 'm', 'a', 'x', '_', 'u', '.', 'w', 9, 0, - /* 8993 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'w', 9, 0, - /* 9003 */ 'm', 's', 'u', 'b', 'v', '.', 'w', 9, 0, - /* 9012 */ 'm', 'a', 'd', 'd', 'v', '.', 'w', 9, 0, - /* 9021 */ 'p', 'c', 'k', 'e', 'v', '.', 'w', 9, 0, - /* 9030 */ 'i', 'l', 'v', 'e', 'v', '.', 'w', 9, 0, - /* 9039 */ 'f', 'd', 'i', 'v', '.', 'w', 9, 0, - /* 9047 */ 'm', 'u', 'l', 'v', '.', 'w', 9, 0, - /* 9055 */ 'e', 'x', 't', 'r', 'v', '.', 'w', 9, 0, - /* 9064 */ 'f', 'm', 'a', 'x', '.', 'w', 9, 0, - /* 9072 */ 'b', 'z', '.', 'w', 9, 0, - /* 9078 */ 'b', 'n', 'z', '.', 'w', 9, 0, - /* 9085 */ 'l', 'w', 9, 0, - /* 9089 */ 's', 'w', 9, 0, - /* 9093 */ 'l', 'h', 'x', 9, 0, - /* 9098 */ 'j', 'a', 'l', 'x', 9, 0, - /* 9104 */ 'l', 'b', 'u', 'x', 9, 0, - /* 9110 */ 'l', 'w', 'x', 9, 0, - /* 9115 */ 'b', 'g', 'e', 'z', 9, 0, - /* 9121 */ 'b', 'l', 'e', 'z', 9, 0, - /* 9127 */ 'b', 'n', 'e', 'z', 9, 0, - /* 9133 */ 's', 'e', 'l', 'n', 'e', 'z', 9, 0, - /* 9141 */ 'b', 't', 'n', 'e', 'z', 9, 0, - /* 9148 */ 'd', 'c', 'l', 'z', 9, 0, - /* 9154 */ 'b', 'e', 'q', 'z', 9, 0, - /* 9160 */ 's', 'e', 'l', 'e', 'q', 'z', 9, 0, - /* 9168 */ 'b', 't', 'e', 'q', 'z', 9, 0, - /* 9175 */ 'b', 'g', 't', 'z', 9, 0, - /* 9181 */ 'b', 'l', 't', 'z', 9, 0, - /* 9187 */ 'm', 'o', 'v', 'z', 9, 0, - /* 9193 */ 's', 'e', 'b', 9, 32, 0, - /* 9199 */ 'j', 'r', 'c', 9, 32, 0, - /* 9205 */ 's', 'e', 'h', 9, 32, 0, - /* 9211 */ 'd', 'd', 'i', 'v', 'u', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, - /* 9225 */ 'd', 'd', 'i', 'v', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, - /* 9238 */ 'a', 'd', 'd', 'i', 'u', 9, '$', 's', 'p', ',', 32, 0, - /* 9250 */ 'c', 'i', 'n', 's', '3', '2', 32, 0, - /* 9258 */ 'e', 'x', 't', 's', '3', '2', 32, 0, - /* 9266 */ 's', 'y', 'n', 'c', 32, 0, - /* 9272 */ 9, '.', 'w', 'o', 'r', 'd', 32, 0, - /* 9280 */ 'd', 'i', 'n', 's', 'm', 32, 0, - /* 9287 */ 'd', 'e', 'x', 't', 'm', 32, 0, - /* 9294 */ 'c', 'i', 'n', 's', 32, 0, - /* 9300 */ 'd', 'i', 'n', 's', 32, 0, - /* 9306 */ 'e', 'x', 't', 's', 32, 0, - /* 9312 */ 'd', 'e', 'x', 't', 32, 0, - /* 9318 */ 'd', 'i', 'n', 's', 'u', 32, 0, - /* 9325 */ 'd', 'e', 'x', 't', 'u', 32, 0, - /* 9332 */ 'b', 'c', '1', 'n', 'e', 'z', 32, 0, - /* 9340 */ 'b', 'c', '2', 'n', 'e', 'z', 32, 0, - /* 9348 */ 'b', 'c', '1', 'e', 'q', 'z', 32, 0, - /* 9356 */ 'b', 'c', '2', 'e', 'q', 'z', 32, 0, - /* 9364 */ 'c', '.', 0, - /* 9367 */ 'b', 'r', 'e', 'a', 'k', 32, '0', 0, - /* 9375 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 9388 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 9395 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 9405 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 9420 */ 'j', 'r', 'c', 9, 32, '$', 'r', 'a', 0, - /* 9429 */ 'j', 'r', 9, 32, '$', 'r', 'a', 0, - /* 9437 */ 'e', 'h', 'b', 0, - /* 9441 */ 'p', 'a', 'u', 's', 'e', 0, - /* 9447 */ 't', 'l', 'b', 'w', 'i', 0, - /* 9453 */ 'f', 'o', 'o', 0, - /* 9457 */ 't', 'l', 'b', 'p', 0, - /* 9462 */ 's', 's', 'n', 'o', 'p', 0, - /* 9468 */ 't', 'l', 'b', 'r', 0, - /* 9473 */ 't', 'l', 'b', 'w', 'r', 0, - /* 9479 */ 'd', 'e', 'r', 'e', 't', 0, - /* 9485 */ 'w', 'a', 'i', 't', 0, + /* 0 */ 'j', + 'a', + 'l', + 'r', + 'c', + 32, + 9, + 0, + /* 8 */ 'd', + 'm', + 'f', + 'c', + '0', + 9, + 0, + /* 15 */ 'd', + 'm', + 't', + 'c', + '0', + 9, + 0, + /* 22 */ 'v', + 'm', + 'm', + '0', + 9, + 0, + /* 28 */ 'm', + 't', + 'm', + '0', + 9, + 0, + /* 34 */ 'm', + 't', + 'p', + '0', + 9, + 0, + /* 40 */ 'b', + 'b', + 'i', + 't', + '0', + 9, + 0, + /* 47 */ 'l', + 'd', + 'c', + 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's', + '.', + 'w', + 9, + 0, + /* 8406 */ 's', + 'h', + 'l', + 'l', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8416 */ 'm', + 'i', + 'n', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8425 */ 'd', + 'o', + 't', + 'p', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8435 */ 's', + 'u', + 'b', + 'q', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8445 */ 'a', + 'd', + 'd', + 'q', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8455 */ 'm', + 'u', + 'l', + 'q', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8465 */ 'a', + 'b', + 's', + 'q', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8475 */ 'a', + 'v', + 'e', + 'r', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8485 */ 's', + 'u', + 'b', + 's', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8495 */ 'a', + 'd', + 'd', + 's', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8505 */ 's', + 'a', + 't', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8514 */ 'c', + 'l', + 't', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8523 */ 'f', + 'f', + 'i', + 'n', + 't', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8534 */ 'f', + 't', + 'i', + 'n', + 't', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8545 */ 's', + 'u', + 'b', + 's', + 'u', + 'u', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8557 */ 'd', + 'i', + 'v', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8566 */ 's', + 'h', + 'l', + 'l', + 'v', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8577 */ 'm', + 'a', + 'x', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8586 */ 'c', + 'o', + 'p', + 'y', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8596 */ 'm', + 'u', + 'l', + 'q', + '_', + 'r', + 's', + '.', + 'w', + 9, + 0, + /* 8607 */ 'e', + 'x', + 't', + 'r', + '_', + 'r', + 's', + '.', + 'w', + 9, + 0, + /* 8618 */ 'e', + 'x', + 't', + 'r', + 'v', + '_', + 'r', + 's', + '.', + 'w', + 9, + 0, + /* 8630 */ 'f', + 'c', + 'l', + 'a', + 's', + 's', + '.', + 'w', + 9, + 0, + /* 8640 */ 's', + 'p', + 'l', + 'a', + 't', + '.', + 'w', + 9, + 0, + /* 8649 */ 'b', + 's', + 'e', + 't', + '.', + 'w', + 9, + 0, + /* 8657 */ 'f', + 'c', + 'l', + 't', + '.', + 'w', + 9, + 0, + /* 8665 */ 'f', + 's', + 'l', + 't', + '.', + 'w', + 9, + 0, + /* 8673 */ 'f', + 'c', + 'u', + 'l', + 't', + '.', + 'w', + 9, + 0, + /* 8682 */ 'f', + 's', + 'u', + 'l', + 't', + '.', + 'w', + 9, + 0, + /* 8691 */ 'p', + 'c', + 'n', + 't', + '.', + 'w', + 9, + 0, + /* 8699 */ 'f', + 'r', + 'i', + 'n', + 't', + '.', + 'w', + 9, + 0, + /* 8708 */ 'i', + 'n', + 's', + 'e', + 'r', + 't', + '.', + 'w', + 9, + 0, + /* 8718 */ 'f', + 's', + 'q', + 'r', + 't', + '.', + 'w', + 9, + 0, + /* 8727 */ 'f', + 'r', + 's', + 'q', + 'r', + 't', + '.', + 'w', + 9, + 0, + /* 8737 */ 's', + 't', + '.', + 'w', + 9, + 0, + /* 8743 */ 'a', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8753 */ 'h', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8763 */ 'd', + 'p', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8774 */ 'f', + 't', + 'r', + 'u', + 'n', + 'c', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8786 */ 'h', + 'a', + 'd', + 'd', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8796 */ 'd', + 'p', + 'a', + 'd', + 'd', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8807 */ 'm', + 'o', + 'd', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8816 */ 'c', + 'l', + 'e', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8825 */ 'a', + 'v', + 'e', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8834 */ 'c', + 'l', + 'e', + 'i', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8844 */ 'm', + 'i', + 'n', + 'i', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8854 */ 'c', + 'l', + 't', + 'i', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8864 */ 'm', + 'a', + 'x', + 'i', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8874 */ 'm', + 'i', + 'n', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8883 */ 'd', + 'o', + 't', + 'p', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8893 */ 'a', + 'v', + 'e', + 'r', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8903 */ 's', + 'u', + 'b', + 's', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8913 */ 'a', + 'd', + 'd', + 's', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8923 */ 's', + 'u', + 'b', + 's', + 'u', + 's', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8935 */ 's', + 'a', + 't', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8944 */ 'c', + 'l', + 't', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8953 */ 'f', + 'f', + 'i', + 'n', + 't', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8964 */ 'f', + 't', + 'i', + 'n', + 't', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8975 */ 'd', + 'i', + 'v', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8984 */ 'm', + 'a', + 'x', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8993 */ 'c', + 'o', + 'p', + 'y', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 9003 */ 'm', + 's', + 'u', + 'b', + 'v', + '.', + 'w', + 9, + 0, + /* 9012 */ 'm', + 'a', + 'd', + 'd', + 'v', + '.', + 'w', + 9, + 0, + /* 9021 */ 'p', + 'c', + 'k', + 'e', + 'v', + '.', + 'w', + 9, + 0, + /* 9030 */ 'i', + 'l', + 'v', + 'e', + 'v', + '.', + 'w', + 9, + 0, + /* 9039 */ 'f', + 'd', + 'i', + 'v', + '.', + 'w', + 9, + 0, + /* 9047 */ 'm', + 'u', + 'l', + 'v', + '.', + 'w', + 9, + 0, + /* 9055 */ 'e', + 'x', + 't', + 'r', + 'v', + '.', + 'w', + 9, + 0, + /* 9064 */ 'f', + 'm', + 'a', + 'x', + '.', + 'w', + 9, + 0, + /* 9072 */ 'b', + 'z', + '.', + 'w', + 9, + 0, + /* 9078 */ 'b', + 'n', + 'z', + '.', + 'w', + 9, + 0, + /* 9085 */ 'l', + 'w', + 9, + 0, + /* 9089 */ 's', + 'w', + 9, + 0, + /* 9093 */ 'l', + 'h', + 'x', + 9, + 0, + /* 9098 */ 'j', + 'a', + 'l', + 'x', + 9, + 0, + /* 9104 */ 'l', + 'b', + 'u', + 'x', + 9, + 0, + /* 9110 */ 'l', + 'w', + 'x', + 9, + 0, + /* 9115 */ 'b', + 'g', + 'e', + 'z', + 9, + 0, + /* 9121 */ 'b', + 'l', + 'e', + 'z', + 9, + 0, + /* 9127 */ 'b', + 'n', + 'e', + 'z', + 9, + 0, + /* 9133 */ 's', + 'e', + 'l', + 'n', + 'e', + 'z', + 9, + 0, + /* 9141 */ 'b', + 't', + 'n', + 'e', + 'z', + 9, + 0, + /* 9148 */ 'd', + 'c', + 'l', + 'z', + 9, + 0, + /* 9154 */ 'b', + 'e', + 'q', + 'z', + 9, + 0, + /* 9160 */ 's', + 'e', + 'l', + 'e', + 'q', + 'z', + 9, + 0, + /* 9168 */ 'b', + 't', + 'e', + 'q', + 'z', + 9, + 0, + /* 9175 */ 'b', + 'g', + 't', + 'z', + 9, + 0, + /* 9181 */ 'b', + 'l', + 't', + 'z', + 9, + 0, + /* 9187 */ 'm', + 'o', + 'v', + 'z', + 9, + 0, + /* 9193 */ 's', + 'e', + 'b', + 9, + 32, + 0, + /* 9199 */ 'j', + 'r', + 'c', + 9, + 32, + 0, + /* 9205 */ 's', + 'e', + 'h', + 9, + 32, + 0, + /* 9211 */ 'd', + 'd', + 'i', + 'v', + 'u', + 9, + '$', + 'z', + 'e', + 'r', + 'o', + ',', + 32, + 0, + /* 9225 */ 'd', + 'd', + 'i', + 'v', + 9, + '$', + 'z', + 'e', + 'r', + 'o', + ',', + 32, + 0, + /* 9238 */ 'a', + 'd', + 'd', + 'i', + 'u', + 9, + '$', + 's', + 'p', + ',', + 32, + 0, + /* 9250 */ 'c', + 'i', + 'n', + 's', + '3', + '2', + 32, + 0, + /* 9258 */ 'e', + 'x', + 't', + 's', + '3', + '2', + 32, + 0, + /* 9266 */ 's', + 'y', + 'n', + 'c', + 32, + 0, + /* 9272 */ 9, + '.', + 'w', + 'o', + 'r', + 'd', + 32, + 0, + /* 9280 */ 'd', + 'i', + 'n', + 's', + 'm', + 32, + 0, + /* 9287 */ 'd', + 'e', + 'x', + 't', + 'm', + 32, + 0, + /* 9294 */ 'c', + 'i', + 'n', + 's', + 32, + 0, + /* 9300 */ 'd', + 'i', + 'n', + 's', + 32, + 0, + /* 9306 */ 'e', + 'x', + 't', + 's', + 32, + 0, + /* 9312 */ 'd', + 'e', + 'x', + 't', + 32, + 0, + /* 9318 */ 'd', + 'i', + 'n', + 's', + 'u', + 32, + 0, + /* 9325 */ 'd', + 'e', + 'x', + 't', + 'u', + 32, + 0, + /* 9332 */ 'b', + 'c', + '1', + 'n', + 'e', + 'z', + 32, + 0, + /* 9340 */ 'b', + 'c', + '2', + 'n', + 'e', + 'z', + 32, + 0, + /* 9348 */ 'b', + 'c', + '1', + 'e', + 'q', + 'z', + 32, + 0, + /* 9356 */ 'b', + 'c', + '2', + 'e', + 'q', + 'z', + 32, + 0, + /* 9364 */ 'c', + '.', + 0, + /* 9367 */ 'b', + 'r', + 'e', + 'a', + 'k', + 32, + '0', + 0, + /* 9375 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'E', + 'N', + 'D', + 0, + /* 9388 */ 'B', + 'U', + 'N', + 'D', + 'L', + 'E', + 0, + /* 9395 */ 'D', + 'B', + 'G', + '_', + 'V', + 'A', + 'L', + 'U', + 'E', + 0, + /* 9405 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'S', + 'T', + 'A', + 'R', + 'T', + 0, + /* 9420 */ 'j', + 'r', + 'c', + 9, + 32, + '$', + 'r', + 'a', + 0, + /* 9429 */ 'j', + 'r', + 9, + 32, + '$', + 'r', + 'a', + 0, + /* 9437 */ 'e', + 'h', + 'b', + 0, + /* 9441 */ 'p', + 'a', + 'u', + 's', + 'e', + 0, + /* 9447 */ 't', + 'l', + 'b', + 'w', + 'i', + 0, + /* 9453 */ 'f', + 'o', + 'o', + 0, + /* 9457 */ 't', + 'l', + 'b', + 'p', + 0, + /* 9462 */ 's', + 's', + 'n', + 'o', + 'p', + 0, + /* 9468 */ 't', + 'l', + 'b', + 'r', + 0, + /* 9473 */ 't', + 'l', + 'b', + 'w', + 'r', + 0, + /* 9479 */ 'd', + 'e', + 'r', + 'e', + 't', + 0, + /* 9485 */ 'w', + 'a', + 'i', + 't', + 0, }; #endif @@ -4697,12 +13088,11 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) uint64_t Bits = (Bits2 << 32) | Bits1; // assert(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 16383)-1); + SStream_concat0(O, AsmStrs + (Bits & 16383) - 1); #endif - // Fragment 0 encoded into 4 bits for 11 unique commands. - //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15); + // printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15); switch ((Bits >> 14) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: @@ -4711,69 +13101,68 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 1: // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - printOperand(MI, 0, O); + printOperand(MI, 0, O); break; case 2: // ADDIUS5_MM, CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHI_DSP,... - printOperand(MI, 1, O); - SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); break; case 3: // AND16_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, OR16_MM, XOR16_MM - printOperand(MI, 2, O); - SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); break; case 4: // BREAK16_MM, SDBBP16_MM - printUnsignedImm8(MI, 0, O); + printUnsignedImm8(MI, 0, O); return; break; case 5: // CACHE, CACHE_MM, CACHE_R6, PREF, PREF_MM, PREF_R6 - printUnsignedImm(MI, 2, O); - SStream_concat0(O, ", "); - printMemOperand(MI, 0, O); + printUnsignedImm(MI, 2, O); + SStream_concat0(O, ", "); + printMemOperand(MI, 0, O); return; break; case 6: // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM - printFCCOperand(MI, 2, O); + printFCCOperand(MI, 2, O); break; case 7: // LWM16_MM, LWM32_MM, LWM_MM, MOVEP_MM, SWM16_MM, SWM32_MM, SWM_MM - printRegisterList(MI, 0, O); - SStream_concat0(O, ", "); + printRegisterList(MI, 0, O); + SStream_concat0(O, ", "); break; case 8: // LWP_MM, SWP_MM - printRegisterPair(MI, 0, O); - SStream_concat0(O, ", "); - printMemOperand(MI, 2, O); + printRegisterPair(MI, 0, O); + SStream_concat0(O, ", "); + printMemOperand(MI, 2, O); return; break; case 9: // SYNCI - printMemOperand(MI, 0, O); + printMemOperand(MI, 0, O); return; break; case 10: // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... - printOperand(MI, 3, O); + printOperand(MI, 3, O); break; } - // Fragment 1 encoded into 5 bits for 17 unique commands. - //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31); + // printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31); switch ((Bits >> 18) & 31) { default: // llvm_unreachable("Invalid command number."); case 0: // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); break; case 1: // ADDIUS5_MM, DAHI, DATI, MOVEP_MM, MultRxRyRz16, MultuRxRyRz16, SltCCRx... - printOperand(MI, 2, O); + printOperand(MI, 2, O); break; case 2: // ADDIUSP_MM, AddiuSpImmX16, B16_MM, BAL, BALC, BC, BPOSGE32, B_MM_Pseud... @@ -4781,95 +13170,94 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 3: // AND16_MM, OR16_MM, XOR16_MM - printOperand(MI, 1, O); + printOperand(MI, 1, O); return; break; case 4: // AddiuRxPcImmX16 - SStream_concat0(O, ", $pc, "); - printOperand(MI, 1, O); + SStream_concat0(O, ", $pc, "); + printOperand(MI, 1, O); return; break; case 5: // AddiuSpImm16, Bimm16 - SStream_concat0(O, " # 16 bit inst"); + SStream_concat0(O, " # 16 bit inst"); return; break; case 6: // Bteqz16, Btnez16 - SStream_concat0(O, " # 16 bit inst"); + SStream_concat0(O, " # 16 bit inst"); return; break; case 7: // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, M... - printOperand(MI, 0, O); + printOperand(MI, 0, O); return; break; case 8: // FCMP_D32, FCMP_D32_MM, FCMP_D64 - SStream_concat0(O, ".d\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); + SStream_concat0(O, ".d\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); return; break; case 9: // FCMP_S32, FCMP_S32_MM - SStream_concat0(O, ".s\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); + SStream_concat0(O, ".s\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); return; break; case 10: // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... - SStream_concat0(O, "["); + SStream_concat0(O, "["); break; case 11: // Jal16 - SStream_concat0(O, "\n\tnop"); + SStream_concat0(O, "\n\tnop"); return; break; case 12: // JalB16 - SStream_concat0(O, "\t# branch\n\tnop"); + SStream_concat0(O, "\t# branch\n\tnop"); return; break; case 13: // LWM16_MM, LWM32_MM, LWM_MM, SWM16_MM, SWM32_MM, SWM_MM - printMemOperand(MI, 1, O); + printMemOperand(MI, 1, O); return; break; case 14: // LwConstant32 - SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); - printOperand(MI, 1, O); - SStream_concat0(O, "\n2:"); + SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); + printOperand(MI, 1, O); + SStream_concat0(O, "\n2:"); return; break; case 15: // SC, SCD, SCD_R6, SC_MM, SC_R6 - printMemOperand(MI, 2, O); + printMemOperand(MI, 2, O); return; break; case 16: // SelBeqZ, SelBneZ - SStream_concat0(O, ", .+4\n\t\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + SStream_concat0(O, ", .+4\n\t\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); return; break; } - // Fragment 2 encoded into 4 bits for 12 unique commands. - //printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15); + // printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15); switch ((Bits >> 23) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - printOperand(MI, 1, O); + printOperand(MI, 1, O); break; case 1: // ADDIUS5_MM, DAHI, DATI @@ -4877,67 +13265,66 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 2: // AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B, BINSLI_D, BINS... - printOperand(MI, 2, O); + printOperand(MI, 2, O); break; case 3: // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM - printMemOperandEA(MI, 1, O); + printMemOperandEA(MI, 1, O); return; break; case 4: // BBIT0, BBIT032, BBIT1, BBIT132, LUi, LUi64, LUi_MM, LoadAddr32Imm, Loa... - printUnsignedImm(MI, 1, O); + printUnsignedImm(MI, 1, O); break; case 5: // INSERT_B, INSERT_D, INSERT_H, INSERT_W - printUnsignedImm(MI, 3, O); - SStream_concat0(O, "], "); - printOperand(MI, 2, O); + printUnsignedImm(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); return; break; case 6: // INSVE_B, INSVE_D, INSVE_H, INSVE_W - printUnsignedImm(MI, 2, O); - SStream_concat0(O, "], "); - printOperand(MI, 3, O); - SStream_concat0(O, "["); - printUnsignedImm(MI, 4, O); - SStream_concat0(O, "]"); + printUnsignedImm(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat0(O, "["); + printUnsignedImm(MI, 4, O); + SStream_concat0(O, "]"); return; break; case 7: // LB, LB64, LBU16_MM, LB_MM, LBu, LBu64, LBu_MM, LD, LDC1, LDC164, LDC1_... - printMemOperand(MI, 1, O); + printMemOperand(MI, 1, O); return; break; case 8: // MOVEP_MM - SStream_concat0(O, ", "); - printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); return; break; case 9: // MultRxRyRz16, MultuRxRyRz16 - SStream_concat0(O, "\n\tmflo\t"); - printOperand(MI, 0, O); + SStream_concat0(O, "\n\tmflo\t"); + printOperand(MI, 0, O); return; break; case 10: // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... - printOperand(MI, 4, O); + printOperand(MI, 4, O); break; case 11: // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... - SStream_concat0(O, "\n\tmove\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", $t8"); + SStream_concat0(O, "\n\tmove\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", $t8"); return; break; } - // Fragment 3 encoded into 4 bits for 15 unique commands. - //printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15); + // printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15); switch ((Bits >> 27) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: @@ -4946,120 +13333,118 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 1: // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); break; case 2: // AddiuRxRxImm16, LwRxPcTcp16 - SStream_concat0(O, "\t# 16 bit inst"); + SStream_concat0(O, "\t# 16 bit inst"); return; break; case 3: // BeqzRxImm16, BnezRxImm16 - SStream_concat0(O, " # 16 bit inst"); + SStream_concat0(O, " # 16 bit inst"); return; break; case 4: // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... - SStream_concat0(O, "\n\tbteqz\t"); - printOperand(MI, 2, O); + SStream_concat0(O, "\n\tbteqz\t"); + printOperand(MI, 2, O); return; break; case 5: // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... - SStream_concat0(O, "\n\tbtnez\t"); - printOperand(MI, 2, O); + SStream_concat0(O, "\n\tbtnez\t"); + printOperand(MI, 2, O); return; break; case 6: // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... - SStream_concat0(O, "["); + SStream_concat0(O, "["); break; case 7: // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 - SStream_concat0(O, " \t# 16 bit inst"); + SStream_concat0(O, " \t# 16 bit inst"); return; break; case 8: // DSLL64_32 - SStream_concat0(O, ", 32"); + SStream_concat0(O, ", 32"); return; break; case 9: // GotPrologue16 - SStream_concat0(O, "\n\taddiu\t"); - printOperand(MI, 1, O); - SStream_concat0(O, ", $pc, "); - printOperand(MI, 3, O); - SStream_concat0(O, "\n "); + SStream_concat0(O, "\n\taddiu\t"); + printOperand(MI, 1, O); + SStream_concat0(O, ", $pc, "); + printOperand(MI, 3, O); + SStream_concat0(O, "\n "); return; break; case 10: // LBUX, LDXC1, LDXC164, LHX, LUXC1, LUXC164, LUXC1_MM, LWX, LWXC1, LWXC1... - SStream_concat0(O, "("); - printOperand(MI, 1, O); - SStream_concat0(O, ")"); + SStream_concat0(O, "("); + printOperand(MI, 1, O); + SStream_concat0(O, ")"); return; break; case 11: // LwRxSpImmX16, SwRxSpImmX16 - SStream_concat0(O, " ( "); - printOperand(MI, 1, O); - SStream_concat0(O, " ); "); + SStream_concat0(O, " ( "); + printOperand(MI, 1, O); + SStream_concat0(O, " ); "); return; break; case 12: // SLL64_32, SLL64_64 - SStream_concat0(O, ", 0"); + SStream_concat0(O, ", 0"); return; break; case 13: // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... - SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); return; break; case 14: // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... - SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); return; break; } - // Fragment 4 encoded into 3 bits for 5 unique commands. - //printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7); + // printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7); switch ((Bits >> 31) & 7) { default: // llvm_unreachable("Invalid command number."); case 0: // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... - printOperand(MI, 2, O); + printOperand(MI, 2, O); break; case 1: // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,... - printUnsignedImm8(MI, 2, O); + printUnsignedImm8(MI, 2, O); break; case 2: // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT... - printUnsignedImm(MI, 2, O); + printUnsignedImm(MI, 2, O); break; case 3: // BINSLI_B, BINSLI_D, BINSLI_H, BINSLI_W, BINSRI_B, BINSRI_D, BINSRI_H, ... - printUnsignedImm8(MI, 3, O); + printUnsignedImm8(MI, 3, O); break; case 4: // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... - printOperand(MI, 3, O); + printOperand(MI, 3, O); break; } - // Fragment 5 encoded into 2 bits for 3 unique commands. - //printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3); + // printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3); switch ((Bits >> 34) & 3) { default: // llvm_unreachable("Invalid command number."); case 0: @@ -5068,211 +13453,212 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 1: // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D... - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); break; case 2: // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... - SStream_concat0(O, "]"); + SStream_concat0(O, "]"); return; break; } - // Fragment 6 encoded into 1 bits for 2 unique commands. - //printf("Frag-6: %"PRIu64"\n", (Bits >> 36) & 1); + // printf("Frag-6: %"PRIu64"\n", (Bits >> 36) & 1); if ((Bits >> 36) & 1) { // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD... - printOperand(MI, 3, O); + printOperand(MI, 3, O); return; } else { // ALIGN, CINS, CINS32, DALIGN, DLSA, DLSA_R6, EXTS, EXTS32, LSA, LSA_R6 - printUnsignedImm(MI, 3, O); + printUnsignedImm(MI, 3, O); return; } } - /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. -static const char *getRegisterName(unsigned RegNo) -{ +static const char *getRegisterName(unsigned RegNo) { // assert(RegNo && RegNo < 394 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'f', '1', '0', 0, - /* 4 */ 'w', '1', '0', 0, - /* 8 */ 'f', '2', '0', 0, - /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, - /* 25 */ 'w', '2', '0', 0, - /* 29 */ 'f', '3', '0', 0, - /* 33 */ 'w', '3', '0', 0, - /* 37 */ 'a', '0', 0, - /* 40 */ 'a', 'c', '0', 0, - /* 44 */ 'f', 'c', 'c', '0', 0, - /* 49 */ 'f', '0', 0, - /* 52 */ 'k', '0', 0, - /* 55 */ 'm', 'p', 'l', '0', 0, - /* 60 */ 'p', '0', 0, - /* 63 */ 's', '0', 0, - /* 66 */ 't', '0', 0, - /* 69 */ 'v', '0', 0, - /* 72 */ 'w', '0', 0, - /* 75 */ 'f', '1', '1', 0, - /* 79 */ 'w', '1', '1', 0, - /* 83 */ 'f', '2', '1', 0, - /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, - /* 100 */ 'w', '2', '1', 0, - /* 104 */ 'f', '3', '1', 0, - /* 108 */ 'w', '3', '1', 0, - /* 112 */ 'a', '1', 0, - /* 115 */ 'a', 'c', '1', 0, - /* 119 */ 'f', 'c', 'c', '1', 0, - /* 124 */ 'f', '1', 0, - /* 127 */ 'k', '1', 0, - /* 130 */ 'm', 'p', 'l', '1', 0, - /* 135 */ 'p', '1', 0, - /* 138 */ 's', '1', 0, - /* 141 */ 't', '1', 0, - /* 144 */ 'v', '1', 0, - /* 147 */ 'w', '1', 0, - /* 150 */ 'f', '1', '2', 0, - /* 154 */ 'w', '1', '2', 0, - /* 158 */ 'f', '2', '2', 0, - /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, - /* 175 */ 'w', '2', '2', 0, - /* 179 */ 'a', '2', 0, - /* 182 */ 'a', 'c', '2', 0, - /* 186 */ 'f', 'c', 'c', '2', 0, - /* 191 */ 'f', '2', 0, - /* 194 */ 'm', 'p', 'l', '2', 0, - /* 199 */ 'p', '2', 0, - /* 202 */ 's', '2', 0, - /* 205 */ 't', '2', 0, - /* 208 */ 'w', '2', 0, - /* 211 */ 'f', '1', '3', 0, - /* 215 */ 'w', '1', '3', 0, - /* 219 */ 'f', '2', '3', 0, - /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, - /* 236 */ 'w', '2', '3', 0, - /* 240 */ 'a', '3', 0, - /* 243 */ 'a', 'c', '3', 0, - /* 247 */ 'f', 'c', 'c', '3', 0, - /* 252 */ 'f', '3', 0, - /* 255 */ 's', '3', 0, - /* 258 */ 't', '3', 0, - /* 261 */ 'w', '3', 0, - /* 264 */ 'f', '1', '4', 0, - /* 268 */ 'w', '1', '4', 0, - /* 272 */ 'f', '2', '4', 0, - /* 276 */ 'w', '2', '4', 0, - /* 280 */ 'f', 'c', 'c', '4', 0, - /* 285 */ 'f', '4', 0, - /* 288 */ 's', '4', 0, - /* 291 */ 't', '4', 0, - /* 294 */ 'w', '4', 0, - /* 297 */ 'f', '1', '5', 0, - /* 301 */ 'w', '1', '5', 0, - /* 305 */ 'f', '2', '5', 0, - /* 309 */ 'w', '2', '5', 0, - /* 313 */ 'f', 'c', 'c', '5', 0, - /* 318 */ 'f', '5', 0, - /* 321 */ 's', '5', 0, - /* 324 */ 't', '5', 0, - /* 327 */ 'w', '5', 0, - /* 330 */ 'f', '1', '6', 0, - /* 334 */ 'w', '1', '6', 0, - /* 338 */ 'f', '2', '6', 0, - /* 342 */ 'w', '2', '6', 0, - /* 346 */ 'f', 'c', 'c', '6', 0, - /* 351 */ 'f', '6', 0, - /* 354 */ 's', '6', 0, - /* 357 */ 't', '6', 0, - /* 360 */ 'w', '6', 0, - /* 363 */ 'f', '1', '7', 0, - /* 367 */ 'w', '1', '7', 0, - /* 371 */ 'f', '2', '7', 0, - /* 375 */ 'w', '2', '7', 0, - /* 379 */ 'f', 'c', 'c', '7', 0, - /* 384 */ 'f', '7', 0, - /* 387 */ 's', '7', 0, - /* 390 */ 't', '7', 0, - /* 393 */ 'w', '7', 0, - /* 396 */ 'f', '1', '8', 0, - /* 400 */ 'w', '1', '8', 0, - /* 404 */ 'f', '2', '8', 0, - /* 408 */ 'w', '2', '8', 0, - /* 412 */ 'f', '8', 0, - /* 415 */ 't', '8', 0, - /* 418 */ 'w', '8', 0, - /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, - /* 437 */ 'f', '1', '9', 0, - /* 441 */ 'w', '1', '9', 0, - /* 445 */ 'f', '2', '9', 0, - /* 449 */ 'w', '2', '9', 0, - /* 453 */ 'f', '9', 0, - /* 456 */ 't', '9', 0, - /* 459 */ 'w', '9', 0, - /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, - /* 469 */ 'r', 'a', 0, - /* 472 */ 'h', 'w', 'r', '_', 'c', 'c', 0, - /* 479 */ 'p', 'c', 0, - /* 482 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, - /* 491 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, - /* 502 */ 'h', 'i', 0, - /* 505 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0, - /* 516 */ 'l', 'o', 0, - /* 519 */ 'z', 'e', 'r', 'o', 0, - /* 524 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', 't', 'e', 'p', 0, - /* 539 */ 'f', 'p', 0, - /* 542 */ 'g', 'p', 0, - /* 545 */ 's', 'p', 0, - /* 548 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0, - /* 558 */ 'D', 'S', 'P', 'P', 'o', 's', 0, - /* 565 */ 'a', 't', 0, - /* 568 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, - /* 578 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, + /* 0 */ 'f', '1', '0', 0, + /* 4 */ 'w', '1', '0', 0, + /* 8 */ 'f', '2', '0', 0, + /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', + '0', 0, + /* 25 */ 'w', '2', '0', 0, + /* 29 */ 'f', '3', '0', 0, + /* 33 */ 'w', '3', '0', 0, + /* 37 */ 'a', '0', 0, + /* 40 */ 'a', 'c', '0', 0, + /* 44 */ 'f', 'c', 'c', '0', 0, + /* 49 */ 'f', '0', 0, + /* 52 */ 'k', '0', 0, + /* 55 */ 'm', 'p', 'l', '0', 0, + /* 60 */ 'p', '0', 0, + /* 63 */ 's', '0', 0, + /* 66 */ 't', '0', 0, + /* 69 */ 'v', '0', 0, + /* 72 */ 'w', '0', 0, + /* 75 */ 'f', '1', '1', 0, + /* 79 */ 'w', '1', '1', 0, + /* 83 */ 'f', '2', '1', 0, + /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', + '1', 0, + /* 100 */ 'w', '2', '1', 0, + /* 104 */ 'f', '3', '1', 0, + /* 108 */ 'w', '3', '1', 0, + /* 112 */ 'a', '1', 0, + /* 115 */ 'a', 'c', '1', 0, + /* 119 */ 'f', 'c', 'c', '1', 0, + /* 124 */ 'f', '1', 0, + /* 127 */ 'k', '1', 0, + /* 130 */ 'm', 'p', 'l', '1', 0, + /* 135 */ 'p', '1', 0, + /* 138 */ 's', '1', 0, + /* 141 */ 't', '1', 0, + /* 144 */ 'v', '1', 0, + /* 147 */ 'w', '1', 0, + /* 150 */ 'f', '1', '2', 0, + /* 154 */ 'w', '1', '2', 0, + /* 158 */ 'f', '2', '2', 0, + /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', + '2', 0, + /* 175 */ 'w', '2', '2', 0, + /* 179 */ 'a', '2', 0, + /* 182 */ 'a', 'c', '2', 0, + /* 186 */ 'f', 'c', 'c', '2', 0, + /* 191 */ 'f', '2', 0, + /* 194 */ 'm', 'p', 'l', '2', 0, + /* 199 */ 'p', '2', 0, + /* 202 */ 's', '2', 0, + /* 205 */ 't', '2', 0, + /* 208 */ 'w', '2', 0, + /* 211 */ 'f', '1', '3', 0, + /* 215 */ 'w', '1', '3', 0, + /* 219 */ 'f', '2', '3', 0, + /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', + '3', 0, + /* 236 */ 'w', '2', '3', 0, + /* 240 */ 'a', '3', 0, + /* 243 */ 'a', 'c', '3', 0, + /* 247 */ 'f', 'c', 'c', '3', 0, + /* 252 */ 'f', '3', 0, + /* 255 */ 's', '3', 0, + /* 258 */ 't', '3', 0, + /* 261 */ 'w', '3', 0, + /* 264 */ 'f', '1', '4', 0, + /* 268 */ 'w', '1', '4', 0, + /* 272 */ 'f', '2', '4', 0, + /* 276 */ 'w', '2', '4', 0, + /* 280 */ 'f', 'c', 'c', '4', 0, + /* 285 */ 'f', '4', 0, + /* 288 */ 's', '4', 0, + /* 291 */ 't', '4', 0, + /* 294 */ 'w', '4', 0, + /* 297 */ 'f', '1', '5', 0, + /* 301 */ 'w', '1', '5', 0, + /* 305 */ 'f', '2', '5', 0, + /* 309 */ 'w', '2', '5', 0, + /* 313 */ 'f', 'c', 'c', '5', 0, + /* 318 */ 'f', '5', 0, + /* 321 */ 's', '5', 0, + /* 324 */ 't', '5', 0, + /* 327 */ 'w', '5', 0, + /* 330 */ 'f', '1', '6', 0, + /* 334 */ 'w', '1', '6', 0, + /* 338 */ 'f', '2', '6', 0, + /* 342 */ 'w', '2', '6', 0, + /* 346 */ 'f', 'c', 'c', '6', 0, + /* 351 */ 'f', '6', 0, + /* 354 */ 's', '6', 0, + /* 357 */ 't', '6', 0, + /* 360 */ 'w', '6', 0, + /* 363 */ 'f', '1', '7', 0, + /* 367 */ 'w', '1', '7', 0, + /* 371 */ 'f', '2', '7', 0, + /* 375 */ 'w', '2', '7', 0, + /* 379 */ 'f', 'c', 'c', '7', 0, + /* 384 */ 'f', '7', 0, + /* 387 */ 's', '7', 0, + /* 390 */ 't', '7', 0, + /* 393 */ 'w', '7', 0, + /* 396 */ 'f', '1', '8', 0, + /* 400 */ 'w', '1', '8', 0, + /* 404 */ 'f', '2', '8', 0, + /* 408 */ 'w', '2', '8', 0, + /* 412 */ 'f', '8', 0, + /* 415 */ 't', '8', 0, + /* 418 */ 'w', '8', 0, + /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', + '6', '_', '1', '9', 0, + /* 437 */ 'f', '1', '9', 0, + /* 441 */ 'w', '1', '9', 0, + /* 445 */ 'f', '2', '9', 0, + /* 449 */ 'w', '2', '9', 0, + /* 453 */ 'f', '9', 0, + /* 456 */ 't', '9', 0, + /* 459 */ 'w', '9', 0, + /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, + /* 469 */ 'r', 'a', 0, + /* 472 */ 'h', 'w', 'r', '_', 'c', 'c', 0, + /* 479 */ 'p', 'c', 0, + /* 482 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, + /* 491 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, + /* 502 */ 'h', 'i', 0, + /* 505 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0, + /* 516 */ 'l', 'o', 0, + /* 519 */ 'z', 'e', 'r', 'o', 0, + /* 524 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', + 't', 'e', 'p', 0, + /* 539 */ 'f', 'p', 0, + /* 542 */ 'g', 'p', 0, + /* 545 */ 's', 'p', 0, + /* 548 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0, + /* 558 */ 'D', 'S', 'P', 'P', 'o', 's', 0, + /* 565 */ 'a', 't', 0, + /* 568 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, + /* 578 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, }; static const uint16_t RegAsmOffset[] = { - 565, 482, 578, 462, 491, 558, 568, 539, 542, 152, 77, 2, 332, 266, - 299, 213, 365, 479, 469, 545, 519, 37, 112, 179, 240, 40, 115, 182, - 243, 565, 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213, - 266, 299, 332, 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365, - 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, - 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 1, 76, 151, 212, - 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, - 405, 446, 30, 105, 49, 191, 285, 351, 412, 0, 150, 264, 330, 396, - 8, 158, 272, 338, 404, 29, 12, 87, 162, 223, 49, 124, 191, 252, - 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363, - 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104, - 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, 213, 266, 299, - 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, - 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 539, 49, - 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, - 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, - 445, 29, 104, 542, 40, 115, 182, 243, 505, 524, 472, 548, 266, 299, - 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, - 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127, - 40, 115, 182, 243, 55, 130, 194, 60, 135, 199, 469, 63, 138, 202, - 255, 288, 321, 354, 387, 545, 66, 141, 205, 258, 291, 324, 357, 390, - 415, 456, 69, 144, 72, 147, 208, 261, 294, 327, 360, 393, 418, 459, - 4, 79, 154, 215, 268, 301, 334, 367, 400, 441, 25, 100, 175, 236, - 276, 309, 342, 375, 408, 449, 33, 108, 519, 37, 112, 179, 240, 40, - 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, - 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, - 404, 445, 29, 104, 421, 502, 52, 127, 516, 63, 138, 202, 255, 288, - 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, - 144, + 565, 482, 578, 462, 491, 558, 568, 539, 542, 152, 77, 2, 332, 266, 299, + 213, 365, 479, 469, 545, 519, 37, 112, 179, 240, 40, 115, 182, 243, 565, + 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213, 266, 299, 332, + 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365, 398, 435, 1, 76, + 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, + 372, 405, 446, 30, 105, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, + 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 49, 191, 285, + 351, 412, 0, 150, 264, 330, 396, 8, 158, 272, 338, 404, 29, 12, 87, + 162, 223, 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, + 211, 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, + 404, 445, 29, 104, 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, + 213, 266, 299, 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, + 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 539, + 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, + 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, + 29, 104, 542, 40, 115, 182, 243, 505, 524, 472, 548, 266, 299, 332, 365, + 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, 159, + 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127, 40, 115, 182, 243, + 55, 130, 194, 60, 135, 199, 469, 63, 138, 202, 255, 288, 321, 354, 387, + 545, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, 144, 72, 147, + 208, 261, 294, 327, 360, 393, 418, 459, 4, 79, 154, 215, 268, 301, 334, + 367, 400, 441, 25, 100, 175, 236, 276, 309, 342, 375, 408, 449, 33, 108, + 519, 37, 112, 179, 240, 40, 49, 124, 191, 252, 285, 318, 351, 384, 412, + 453, 0, 75, 150, 211, 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, + 272, 305, 338, 371, 404, 445, 29, 104, 421, 502, 52, 127, 516, 63, 138, + 202, 255, 288, 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, + 456, 69, 144, }; - //printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]); - //int i; - //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) + // printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]); + // int i; + // for (i = 0; i < sizeof(RegAsmOffset)/2; i++) // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); - //printf("-------------------------\n"); - return AsmStrs+RegAsmOffset[RegNo-1]; + // printf("-------------------------\n"); + return AsmStrs + RegAsmOffset[RegNo - 1]; #else return NULL; #endif @@ -5282,19 +13668,19 @@ static const char *getRegisterName(unsigned RegNo) #undef PRINT_ALIAS_INSTR static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, SStream *OS) -{ -} + unsigned PrintMethodIdx, SStream *OS) {} -static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) -{ - #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) +static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) { +#define GETREGCLASS_CONTAIN(_class, _reg) \ + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), \ + MCOperand_getReg(MCInst_getOperand(MI, _reg))) const char *AsmString; char *tmp, *AsmMnem, *AsmOps, *c; int OpIdx, PrintMethodIdx; MCRegisterInfo *MRI = (MCRegisterInfo *)info; switch (MCInst_getOpcode(MI)) { - default: return NULL; + default: + return NULL; case Mips_ADDu: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && @@ -5693,7 +14079,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) tmp = cs_strdup(AsmString); AsmMnem = tmp; - for(AsmOps = tmp; *AsmOps; AsmOps++) { + for (AsmOps = tmp; *AsmOps; AsmOps++) { if (*AsmOps == ' ' || *AsmOps == '\t') { *AsmOps = '\0'; AsmOps++; diff --git a/arch/Mips/MipsGenDisassemblerTables.inc b/arch/Mips/MipsGenDisassemblerTables.inc index e926f77884..5e2fa8d6c5 100644 --- a/arch/Mips/MipsGenDisassemblerTables.inc +++ b/arch/Mips/MipsGenDisassemblerTables.inc @@ -1,6942 +1,64980 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * Mips Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* By Phosphorus15 , Year 2021 */ +/* This generator is under https://github.com/rizinorg/llvm-capstone */ +/* Automatically generated file, do not edit! */ -#include "../../MCInst.h" #include "../../LEB128.h" +#include "../../MCInst.h" + +#define Mips_FeatureAbs2008 0ULL +#define Mips_FeatureCRC 1ULL +#define Mips_FeatureCnMips 2ULL +#define Mips_FeatureCnMipsP 3ULL +#define Mips_FeatureDSP 4ULL +#define Mips_FeatureDSPR2 5ULL +#define Mips_FeatureDSPR3 6ULL +#define Mips_FeatureEVA 7ULL +#define Mips_FeatureFP64Bit 8ULL +#define Mips_FeatureFPXX 9ULL +#define Mips_FeatureGINV 10ULL +#define Mips_FeatureGP64Bit 11ULL +#define Mips_FeatureLongCalls 12ULL +#define Mips_FeatureMSA 13ULL +#define Mips_FeatureMT 14ULL +#define Mips_FeatureMicroMips 15ULL +#define Mips_FeatureMips1 16ULL +#define Mips_FeatureMips2 17ULL +#define Mips_FeatureMips3 18ULL +#define Mips_FeatureMips3D 19ULL +#define Mips_FeatureMips3_32 20ULL +#define Mips_FeatureMips3_32r2 21ULL +#define Mips_FeatureMips4 22ULL +#define Mips_FeatureMips4_32 23ULL +#define Mips_FeatureMips4_32r2 24ULL +#define Mips_FeatureMips5 25ULL +#define Mips_FeatureMips5_32r2 26ULL +#define Mips_FeatureMips16 27ULL +#define Mips_FeatureMips32 28ULL +#define Mips_FeatureMips32r2 29ULL +#define Mips_FeatureMips32r3 30ULL +#define Mips_FeatureMips32r5 31ULL +#define Mips_FeatureMips32r6 32ULL +#define Mips_FeatureMips64 33ULL +#define Mips_FeatureMips64r2 34ULL +#define Mips_FeatureMips64r3 35ULL +#define Mips_FeatureMips64r5 36ULL +#define Mips_FeatureMips64r6 37ULL +#define Mips_FeatureNaN2008 38ULL +#define Mips_FeatureNoABICalls 39ULL +#define Mips_FeatureNoMadd4 40ULL +#define Mips_FeatureNoOddSPReg 41ULL +#define Mips_FeaturePTR64Bit 42ULL +#define Mips_FeatureSingleFloat 43ULL +#define Mips_FeatureSoftFloat 44ULL +#define Mips_FeatureSym32 45ULL +#define Mips_FeatureUseIndirectJumpsHazard 46ULL +#define Mips_FeatureUseTCCInDIV 47ULL +#define Mips_FeatureVFPU 48ULL +#define Mips_FeatureVirt 49ULL +#define Mips_FeatureXGOT 50ULL +#define Mips_ImplP5600 51ULL +#ifdef MIPS_GET_DISASSEMBLER +#undef MIPS_GET_DISASSEMBLER // Helper function for extracting fields from encoded instructions. -#define FieldFromInstruction(fname, InsnType) \ -static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ -{ \ - InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ - fieldMask = (InsnType)(-1LL); \ - else \ - fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ - return (insn & fieldMask) >> startBit; \ -} +#define FieldFromInstruction(fname, InsnType) \ + static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) { \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ + } + +static const uint8_t DecoderTable16[] = { + /* 0 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 17 + /* 8 */ MCD_OPC_CheckPredicate, + 0, + 71, + 2, + 0, // Skip to: 596 + /* 13 */ MCD_OPC_Decode, + 140, + 8, + 0, // Opcode: Bimm16 + /* 17 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 31 + /* 22 */ MCD_OPC_CheckPredicate, + 0, + 57, + 2, + 0, // Skip to: 596 + /* 27 */ MCD_OPC_Decode, + 138, + 8, + 1, // Opcode: BeqzRxImm16 + /* 31 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 45 + /* 36 */ MCD_OPC_CheckPredicate, + 0, + 43, + 2, + 0, // Skip to: 596 + /* 41 */ MCD_OPC_Decode, + 142, + 8, + 1, // Opcode: BnezRxImm16 + /* 45 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 59 + /* 50 */ MCD_OPC_CheckPredicate, + 0, + 29, + 2, + 0, // Skip to: 596 + /* 55 */ MCD_OPC_Decode, + 191, + 6, + 2, // Opcode: AddiuRxRxImm16 + /* 59 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 73 + /* 64 */ MCD_OPC_CheckPredicate, + 0, + 15, + 2, + 0, // Skip to: 596 + /* 69 */ MCD_OPC_Decode, + 184, + 21, + 1, // Opcode: SltiRxImm16 + /* 73 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 87 + /* 78 */ MCD_OPC_CheckPredicate, + 0, + 1, + 2, + 0, // Skip to: 596 + /* 83 */ MCD_OPC_Decode, + 186, + 21, + 1, // Opcode: SltiuRxImm16 + /* 87 */ MCD_OPC_FilterValue, + 12, + 73, + 0, + 0, // Skip to: 165 + /* 92 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 95 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 109 + /* 100 */ MCD_OPC_CheckPredicate, + 0, + 235, + 1, + 0, // Skip to: 596 + /* 105 */ MCD_OPC_Decode, + 145, + 8, + 0, // Opcode: Bteqz16 + /* 109 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 123 + /* 114 */ MCD_OPC_CheckPredicate, + 0, + 221, + 1, + 0, // Skip to: 596 + /* 119 */ MCD_OPC_Decode, + 147, + 8, + 0, // Opcode: Btnez16 + /* 123 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 137 + /* 128 */ MCD_OPC_CheckPredicate, + 0, + 207, + 1, + 0, // Skip to: 596 + /* 133 */ MCD_OPC_Decode, + 194, + 6, + 0, // Opcode: AddiuSpImm16 + /* 137 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 151 + /* 142 */ MCD_OPC_CheckPredicate, + 0, + 193, + 1, + 0, // Skip to: 596 + /* 147 */ MCD_OPC_Decode, + 190, + 17, + 3, // Opcode: Move32R16 + /* 151 */ MCD_OPC_FilterValue, + 7, + 184, + 1, + 0, // Skip to: 596 + /* 156 */ MCD_OPC_CheckPredicate, + 0, + 179, + 1, + 0, // Skip to: 596 + /* 161 */ MCD_OPC_Decode, + 191, + 17, + 4, // Opcode: MoveR3216 + /* 165 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 179 + /* 170 */ MCD_OPC_CheckPredicate, + 0, + 165, + 1, + 0, // Skip to: 596 + /* 175 */ MCD_OPC_Decode, + 144, + 15, + 1, // Opcode: LiRxImm16 + /* 179 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 193 + /* 184 */ MCD_OPC_CheckPredicate, + 0, + 151, + 1, + 0, // Skip to: 596 + /* 189 */ MCD_OPC_Decode, + 211, + 10, + 1, // Opcode: CmpiRxImm16 + /* 193 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 207 + /* 198 */ MCD_OPC_CheckPredicate, + 0, + 137, + 1, + 0, // Skip to: 596 + /* 203 */ MCD_OPC_Decode, + 147, + 15, + 1, // Opcode: LwRxPcTcp16 + /* 207 */ MCD_OPC_FilterValue, + 28, + 31, + 0, + 0, // Skip to: 243 + /* 212 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 215 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 229 + /* 220 */ MCD_OPC_CheckPredicate, + 0, + 115, + 1, + 0, // Skip to: 596 + /* 225 */ MCD_OPC_Decode, + 196, + 6, + 5, // Opcode: AdduRxRyRz16 + /* 229 */ MCD_OPC_FilterValue, + 3, + 106, + 1, + 0, // Skip to: 596 + /* 234 */ MCD_OPC_CheckPredicate, + 0, + 101, + 1, + 0, // Skip to: 596 + /* 239 */ MCD_OPC_Decode, + 193, + 21, + 5, // Opcode: SubuRxRyRz16 + /* 243 */ MCD_OPC_FilterValue, + 29, + 92, + 1, + 0, // Skip to: 596 + /* 248 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 251 */ MCD_OPC_FilterValue, + 0, + 73, + 0, + 0, // Skip to: 329 + /* 256 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 259 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 273 + /* 264 */ MCD_OPC_CheckPredicate, + 0, + 71, + 1, + 0, // Skip to: 596 + /* 269 */ MCD_OPC_Decode, + 151, + 14, + 0, // Opcode: JumpLinkReg16 + /* 273 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 294 + /* 278 */ MCD_OPC_CheckPredicate, + 0, + 57, + 1, + 0, // Skip to: 596 + /* 283 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 50, + 1, + 0, // Skip to: 596 + /* 290 */ MCD_OPC_Decode, + 148, + 14, + 0, // Opcode: JrRa16 + /* 294 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 308 + /* 299 */ MCD_OPC_CheckPredicate, + 0, + 36, + 1, + 0, // Skip to: 596 + /* 304 */ MCD_OPC_Decode, + 150, + 14, + 1, // Opcode: JrcRx16 + /* 308 */ MCD_OPC_FilterValue, + 7, + 27, + 1, + 0, // Skip to: 596 + /* 313 */ MCD_OPC_CheckPredicate, + 0, + 22, + 1, + 0, // Skip to: 596 + /* 318 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 15, + 1, + 0, // Skip to: 596 + /* 325 */ MCD_OPC_Decode, + 149, + 14, + 0, // Opcode: JrcRa16 + /* 329 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 343 + /* 334 */ MCD_OPC_CheckPredicate, + 0, + 1, + 1, + 0, // Skip to: 596 + /* 339 */ MCD_OPC_Decode, + 183, + 21, + 6, // Opcode: SltRxRy16 + /* 343 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 357 + /* 348 */ MCD_OPC_CheckPredicate, + 0, + 243, + 0, + 0, // Skip to: 596 + /* 353 */ MCD_OPC_Decode, + 188, + 21, + 6, // Opcode: SltuRxRy16 + /* 357 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 371 + /* 362 */ MCD_OPC_CheckPredicate, + 0, + 229, + 0, + 0, // Skip to: 596 + /* 367 */ MCD_OPC_Decode, + 182, + 21, + 7, // Opcode: SllvRxRy16 + /* 371 */ MCD_OPC_FilterValue, + 5, + 16, + 0, + 0, // Skip to: 392 + /* 376 */ MCD_OPC_CheckPredicate, + 0, + 215, + 0, + 0, // Skip to: 596 + /* 381 */ MCD_OPC_CheckField, + 5, + 6, + 0, + 208, + 0, + 0, // Skip to: 596 + /* 388 */ MCD_OPC_Decode, + 144, + 8, + 0, // Opcode: Break16 + /* 392 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 406 + /* 397 */ MCD_OPC_CheckPredicate, + 0, + 194, + 0, + 0, // Skip to: 596 + /* 402 */ MCD_OPC_Decode, + 192, + 21, + 7, // Opcode: SrlvRxRy16 + /* 406 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 420 + /* 411 */ MCD_OPC_CheckPredicate, + 0, + 180, + 0, + 0, // Skip to: 596 + /* 416 */ MCD_OPC_Decode, + 190, + 21, + 7, // Opcode: SravRxRy16 + /* 420 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 434 + /* 425 */ MCD_OPC_CheckPredicate, + 0, + 166, + 0, + 0, // Skip to: 596 + /* 430 */ MCD_OPC_Decode, + 210, + 10, + 6, // Opcode: CmpRxRy16 + /* 434 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 448 + /* 439 */ MCD_OPC_CheckPredicate, + 0, + 152, + 0, + 0, // Skip to: 596 + /* 444 */ MCD_OPC_Decode, + 197, + 6, + 7, // Opcode: AndRxRxRy16 + /* 448 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 462 + /* 453 */ MCD_OPC_CheckPredicate, + 0, + 138, + 0, + 0, // Skip to: 596 + /* 458 */ MCD_OPC_Decode, + 232, + 17, + 7, // Opcode: OrRxRxRy16 + /* 462 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 476 + /* 467 */ MCD_OPC_CheckPredicate, + 0, + 124, + 0, + 0, // Skip to: 596 + /* 472 */ MCD_OPC_Decode, + 157, + 22, + 7, // Opcode: XorRxRxRy16 + /* 476 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 490 + /* 481 */ MCD_OPC_CheckPredicate, + 0, + 110, + 0, + 0, // Skip to: 596 + /* 486 */ MCD_OPC_Decode, + 219, + 17, + 6, // Opcode: NotRxRy16 + /* 490 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 504 + /* 495 */ MCD_OPC_CheckPredicate, + 0, + 96, + 0, + 0, // Skip to: 596 + /* 500 */ MCD_OPC_Decode, + 188, + 17, + 1, // Opcode: Mfhi16 + /* 504 */ MCD_OPC_FilterValue, + 17, + 31, + 0, + 0, // Skip to: 540 + /* 509 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 512 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 526 + /* 517 */ MCD_OPC_CheckPredicate, + 0, + 74, + 0, + 0, // Skip to: 596 + /* 522 */ MCD_OPC_Decode, + 178, + 21, + 2, // Opcode: SebRx16 + /* 526 */ MCD_OPC_FilterValue, + 5, + 65, + 0, + 0, // Skip to: 596 + /* 531 */ MCD_OPC_CheckPredicate, + 0, + 60, + 0, + 0, // Skip to: 596 + /* 536 */ MCD_OPC_Decode, + 179, + 21, + 2, // Opcode: SehRx16 + /* 540 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 554 + /* 545 */ MCD_OPC_CheckPredicate, + 0, + 46, + 0, + 0, // Skip to: 596 + /* 550 */ MCD_OPC_Decode, + 189, + 17, + 1, // Opcode: Mflo16 + /* 554 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 568 + /* 559 */ MCD_OPC_CheckPredicate, + 0, + 32, + 0, + 0, // Skip to: 596 + /* 564 */ MCD_OPC_Decode, + 220, + 11, + 6, // Opcode: DivRxRy16 + /* 568 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 582 + /* 573 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 596 + /* 578 */ MCD_OPC_Decode, + 221, + 11, + 6, // Opcode: DivuRxRy16 + /* 582 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 596 + /* 587 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 596 + /* 592 */ MCD_OPC_Decode, + 218, + 17, + 6, // Opcode: NegRxRy16 + /* 596 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTable32[] = { + /* 0 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 31 + /* 8 */ MCD_OPC_CheckPredicate, + 0, + 2, + 2, + 0, // Skip to: 527 + /* 13 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 251, + 1, + 0, // Skip to: 527 + /* 20 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 244, + 1, + 0, // Skip to: 527 + /* 27 */ MCD_OPC_Decode, + 190, + 6, + 1, // Opcode: AddiuRxPcImmX16 + /* 31 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 59 + /* 36 */ MCD_OPC_CheckPredicate, + 0, + 230, + 1, + 0, // Skip to: 527 + /* 41 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 223, + 1, + 0, // Skip to: 527 + /* 48 */ MCD_OPC_CheckField, + 5, + 6, + 0, + 216, + 1, + 0, // Skip to: 527 + /* 55 */ MCD_OPC_Decode, + 141, + 8, + 8, // Opcode: BimmX16 + /* 59 */ MCD_OPC_FilterValue, + 4, + 23, + 0, + 0, // Skip to: 87 + /* 64 */ MCD_OPC_CheckPredicate, + 0, + 202, + 1, + 0, // Skip to: 527 + /* 69 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 195, + 1, + 0, // Skip to: 527 + /* 76 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 188, + 1, + 0, // Skip to: 527 + /* 83 */ MCD_OPC_Decode, + 139, + 8, + 1, // Opcode: BeqzRxImmX16 + /* 87 */ MCD_OPC_FilterValue, + 5, + 23, + 0, + 0, // Skip to: 115 + /* 92 */ MCD_OPC_CheckPredicate, + 0, + 174, + 1, + 0, // Skip to: 527 + /* 97 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 167, + 1, + 0, // Skip to: 527 + /* 104 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 160, + 1, + 0, // Skip to: 527 + /* 111 */ MCD_OPC_Decode, + 143, + 8, + 1, // Opcode: BnezRxImmX16 + /* 115 */ MCD_OPC_FilterValue, + 6, + 106, + 0, + 0, // Skip to: 226 + /* 120 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 123 */ MCD_OPC_FilterValue, + 30, + 143, + 1, + 0, // Skip to: 527 + /* 128 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 131 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 181 + /* 136 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 139 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 153 + /* 144 */ MCD_OPC_CheckPredicate, + 0, + 32, + 0, + 0, // Skip to: 181 + /* 149 */ MCD_OPC_Decode, + 181, + 21, + 6, // Opcode: SllX16 + /* 153 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 167 + /* 158 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 181 + /* 163 */ MCD_OPC_Decode, + 191, + 21, + 6, // Opcode: SrlX16 + /* 167 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 181 + /* 172 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 181 + /* 177 */ MCD_OPC_Decode, + 189, + 21, + 6, // Opcode: SraX16 + /* 181 */ MCD_OPC_ExtractField, + 5, + 6, // Inst{10-5} ... + /* 184 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 198 + /* 189 */ MCD_OPC_CheckPredicate, + 0, + 77, + 1, + 0, // Skip to: 527 + /* 194 */ MCD_OPC_Decode, + 146, + 8, + 0, // Opcode: BteqzX16 + /* 198 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 212 + /* 203 */ MCD_OPC_CheckPredicate, + 0, + 63, + 1, + 0, // Skip to: 527 + /* 208 */ MCD_OPC_Decode, + 148, + 8, + 0, // Opcode: BtnezX16 + /* 212 */ MCD_OPC_FilterValue, + 24, + 54, + 1, + 0, // Skip to: 527 + /* 217 */ MCD_OPC_CheckPredicate, + 0, + 49, + 1, + 0, // Skip to: 527 + /* 222 */ MCD_OPC_Decode, + 195, + 6, + 0, // Opcode: AddiuSpImmX16 + /* 226 */ MCD_OPC_FilterValue, + 8, + 23, + 0, + 0, // Skip to: 254 + /* 231 */ MCD_OPC_CheckPredicate, + 0, + 35, + 1, + 0, // Skip to: 527 + /* 236 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 28, + 1, + 0, // Skip to: 527 + /* 243 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 21, + 1, + 0, // Skip to: 527 + /* 250 */ MCD_OPC_Decode, + 193, + 6, + 9, // Opcode: AddiuRxRyOffMemX16 + /* 254 */ MCD_OPC_FilterValue, + 9, + 23, + 0, + 0, // Skip to: 282 + /* 259 */ MCD_OPC_CheckPredicate, + 0, + 7, + 1, + 0, // Skip to: 527 + /* 264 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 0, + 1, + 0, // Skip to: 527 + /* 271 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 249, + 0, + 0, // Skip to: 527 + /* 278 */ MCD_OPC_Decode, + 189, + 6, + 1, // Opcode: AddiuRxImmX16 + /* 282 */ MCD_OPC_FilterValue, + 10, + 23, + 0, + 0, // Skip to: 310 + /* 287 */ MCD_OPC_CheckPredicate, + 0, + 235, + 0, + 0, // Skip to: 527 + /* 292 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 228, + 0, + 0, // Skip to: 527 + /* 299 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 221, + 0, + 0, // Skip to: 527 + /* 306 */ MCD_OPC_Decode, + 185, + 21, + 1, // Opcode: SltiRxImmX16 + /* 310 */ MCD_OPC_FilterValue, + 11, + 23, + 0, + 0, // Skip to: 338 + /* 315 */ MCD_OPC_CheckPredicate, + 0, + 207, + 0, + 0, // Skip to: 527 + /* 320 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 200, + 0, + 0, // Skip to: 527 + /* 327 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 193, + 0, + 0, // Skip to: 527 + /* 334 */ MCD_OPC_Decode, + 187, + 21, + 1, // Opcode: SltiuRxImmX16 + /* 338 */ MCD_OPC_FilterValue, + 13, + 23, + 0, + 0, // Skip to: 366 + /* 343 */ MCD_OPC_CheckPredicate, + 0, + 179, + 0, + 0, // Skip to: 527 + /* 348 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 172, + 0, + 0, // Skip to: 527 + /* 355 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 165, + 0, + 0, // Skip to: 527 + /* 362 */ MCD_OPC_Decode, + 146, + 15, + 1, // Opcode: LiRxImmX16 + /* 366 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 394 + /* 371 */ MCD_OPC_CheckPredicate, + 0, + 151, + 0, + 0, // Skip to: 527 + /* 376 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 144, + 0, + 0, // Skip to: 527 + /* 383 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 137, + 0, + 0, // Skip to: 527 + /* 390 */ MCD_OPC_Decode, + 212, + 10, + 1, // Opcode: CmpiRxImmX16 + /* 394 */ MCD_OPC_FilterValue, + 18, + 16, + 0, + 0, // Skip to: 415 + /* 399 */ MCD_OPC_CheckPredicate, + 0, + 123, + 0, + 0, // Skip to: 527 + /* 404 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 116, + 0, + 0, // Skip to: 527 + /* 411 */ MCD_OPC_Decode, + 150, + 15, + 9, // Opcode: LwRxSpImmX16 + /* 415 */ MCD_OPC_FilterValue, + 22, + 23, + 0, + 0, // Skip to: 443 + /* 420 */ MCD_OPC_CheckPredicate, + 0, + 102, + 0, + 0, // Skip to: 527 + /* 425 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 95, + 0, + 0, // Skip to: 527 + /* 432 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 88, + 0, + 0, // Skip to: 527 + /* 439 */ MCD_OPC_Decode, + 148, + 15, + 1, // Opcode: LwRxPcTcpX16 + /* 443 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 464 + /* 448 */ MCD_OPC_CheckPredicate, + 0, + 74, + 0, + 0, // Skip to: 527 + /* 453 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 67, + 0, + 0, // Skip to: 527 + /* 460 */ MCD_OPC_Decode, + 177, + 21, + 9, // Opcode: SbRxRyOffMemX16 + /* 464 */ MCD_OPC_FilterValue, + 25, + 16, + 0, + 0, // Skip to: 485 + /* 469 */ MCD_OPC_CheckPredicate, + 0, + 53, + 0, + 0, // Skip to: 527 + /* 474 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 46, + 0, + 0, // Skip to: 527 + /* 481 */ MCD_OPC_Decode, + 180, + 21, + 9, // Opcode: ShRxRyOffMemX16 + /* 485 */ MCD_OPC_FilterValue, + 26, + 16, + 0, + 0, // Skip to: 506 + /* 490 */ MCD_OPC_CheckPredicate, + 0, + 32, + 0, + 0, // Skip to: 527 + /* 495 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 25, + 0, + 0, // Skip to: 527 + /* 502 */ MCD_OPC_Decode, + 195, + 21, + 9, // Opcode: SwRxSpImmX16 + /* 506 */ MCD_OPC_FilterValue, + 27, + 16, + 0, + 0, // Skip to: 527 + /* 511 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 527 + /* 516 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 4, + 0, + 0, // Skip to: 527 + /* 523 */ MCD_OPC_Decode, + 194, + 21, + 9, // Opcode: SwRxRyOffMemX16 + /* 527 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableCOP3_32[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15 -/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51 -/* 11 */ MCD_OPC_Decode, 220, 7, 10, // Opcode: LWC3 -/* 15 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 27 -/* 19 */ MCD_OPC_CheckPredicate, 2, 28, 0, // Skip to: 51 -/* 23 */ MCD_OPC_Decode, 167, 7, 10, // Opcode: LDC3 -/* 27 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 39 -/* 31 */ MCD_OPC_CheckPredicate, 1, 16, 0, // Skip to: 51 -/* 35 */ MCD_OPC_Decode, 242, 12, 10, // Opcode: SWC3 -/* 39 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 51 -/* 43 */ MCD_OPC_CheckPredicate, 2, 4, 0, // Skip to: 51 -/* 47 */ MCD_OPC_Decode, 161, 11, 10, // Opcode: SDC3 -/* 51 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, 51, 9, 0, 0, // Skip to: 17 + /* 8 */ MCD_OPC_CheckPredicate, 1, 46, 0, 0, // Skip to: 59 + /* 13 */ MCD_OPC_Decode, 235, 14, 10, // Opcode: LWC3 + /* 17 */ MCD_OPC_FilterValue, 55, 9, 0, 0, // Skip to: 31 + /* 22 */ MCD_OPC_CheckPredicate, 2, 32, 0, 0, // Skip to: 59 + /* 27 */ MCD_OPC_Decode, 175, 14, 10, // Opcode: LDC3 + /* 31 */ MCD_OPC_FilterValue, 59, 9, 0, 0, // Skip to: 45 + /* 36 */ MCD_OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 59 + /* 41 */ MCD_OPC_Decode, 142, 21, 10, // Opcode: SWC3 + /* 45 */ MCD_OPC_FilterValue, 63, 9, 0, 0, // Skip to: 59 + /* 50 */ MCD_OPC_CheckPredicate, 2, 4, 0, 0, // Skip to: 59 + /* 55 */ MCD_OPC_Decode, 138, 19, 10, // Opcode: SDC3 + /* 59 */ MCD_OPC_Fail, 0}; + +static const uint8_t DecoderTableCnMips32[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 18, + 31, + 0, + 0, // Skip to: 39 + /* 8 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 11 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 25 + /* 16 */ MCD_OPC_CheckPredicate, + 3, + 239, + 1, + 0, // Skip to: 516 + /* 21 */ MCD_OPC_Decode, + 130, + 11, + 11, // Opcode: DMFC2_OCTEON + /* 25 */ MCD_OPC_FilterValue, + 5, + 230, + 1, + 0, // Skip to: 516 + /* 30 */ MCD_OPC_CheckPredicate, + 3, + 225, + 1, + 0, // Skip to: 516 + /* 35 */ MCD_OPC_Decode, + 138, + 11, + 11, // Opcode: DMTC2_OCTEON + /* 39 */ MCD_OPC_FilterValue, + 28, + 160, + 1, + 0, // Skip to: 460 + /* 44 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 47 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 68 + /* 52 */ MCD_OPC_CheckPredicate, + 3, + 203, + 1, + 0, // Skip to: 516 + /* 57 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 196, + 1, + 0, // Skip to: 516 + /* 64 */ MCD_OPC_Decode, + 142, + 11, + 12, // Opcode: DMUL + /* 68 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 89 + /* 73 */ MCD_OPC_CheckPredicate, + 3, + 182, + 1, + 0, // Skip to: 516 + /* 78 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 175, + 1, + 0, // Skip to: 516 + /* 85 */ MCD_OPC_Decode, + 130, + 17, + 13, // Opcode: MTM0 + /* 89 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 110 + /* 94 */ MCD_OPC_CheckPredicate, + 3, + 161, + 1, + 0, // Skip to: 516 + /* 99 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 154, + 1, + 0, // Skip to: 516 + /* 106 */ MCD_OPC_Decode, + 133, + 17, + 13, // Opcode: MTP0 + /* 110 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 131 + /* 115 */ MCD_OPC_CheckPredicate, + 3, + 140, + 1, + 0, // Skip to: 516 + /* 120 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 133, + 1, + 0, // Skip to: 516 + /* 127 */ MCD_OPC_Decode, + 134, + 17, + 13, // Opcode: MTP1 + /* 131 */ MCD_OPC_FilterValue, + 11, + 16, + 0, + 0, // Skip to: 152 + /* 136 */ MCD_OPC_CheckPredicate, + 3, + 119, + 1, + 0, // Skip to: 516 + /* 141 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 112, + 1, + 0, // Skip to: 516 + /* 148 */ MCD_OPC_Decode, + 135, + 17, + 13, // Opcode: MTP2 + /* 152 */ MCD_OPC_FilterValue, + 12, + 16, + 0, + 0, // Skip to: 173 + /* 157 */ MCD_OPC_CheckPredicate, + 3, + 98, + 1, + 0, // Skip to: 516 + /* 162 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 91, + 1, + 0, // Skip to: 516 + /* 169 */ MCD_OPC_Decode, + 131, + 17, + 13, // Opcode: MTM1 + /* 173 */ MCD_OPC_FilterValue, + 13, + 16, + 0, + 0, // Skip to: 194 + /* 178 */ MCD_OPC_CheckPredicate, + 3, + 77, + 1, + 0, // Skip to: 516 + /* 183 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 70, + 1, + 0, // Skip to: 516 + /* 190 */ MCD_OPC_Decode, + 132, + 17, + 13, // Opcode: MTM2 + /* 194 */ MCD_OPC_FilterValue, + 15, + 16, + 0, + 0, // Skip to: 215 + /* 199 */ MCD_OPC_CheckPredicate, + 3, + 56, + 1, + 0, // Skip to: 516 + /* 204 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 49, + 1, + 0, // Skip to: 516 + /* 211 */ MCD_OPC_Decode, + 131, + 22, + 12, // Opcode: VMULU + /* 215 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 236 + /* 220 */ MCD_OPC_CheckPredicate, + 3, + 35, + 1, + 0, // Skip to: 516 + /* 225 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 28, + 1, + 0, // Skip to: 516 + /* 232 */ MCD_OPC_Decode, + 130, + 22, + 12, // Opcode: VMM0 + /* 236 */ MCD_OPC_FilterValue, + 17, + 16, + 0, + 0, // Skip to: 257 + /* 241 */ MCD_OPC_CheckPredicate, + 3, + 14, + 1, + 0, // Skip to: 516 + /* 246 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 7, + 1, + 0, // Skip to: 516 + /* 253 */ MCD_OPC_Decode, + 129, + 22, + 12, // Opcode: V3MULU + /* 257 */ MCD_OPC_FilterValue, + 40, + 16, + 0, + 0, // Skip to: 278 + /* 262 */ MCD_OPC_CheckPredicate, + 3, + 249, + 0, + 0, // Skip to: 516 + /* 267 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 242, + 0, + 0, // Skip to: 516 + /* 274 */ MCD_OPC_Decode, + 199, + 6, + 12, // Opcode: BADDu + /* 278 */ MCD_OPC_FilterValue, + 42, + 16, + 0, + 0, // Skip to: 299 + /* 283 */ MCD_OPC_CheckPredicate, + 3, + 228, + 0, + 0, // Skip to: 516 + /* 288 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 221, + 0, + 0, // Skip to: 516 + /* 295 */ MCD_OPC_Decode, + 169, + 19, + 12, // Opcode: SEQ + /* 299 */ MCD_OPC_FilterValue, + 43, + 16, + 0, + 0, // Skip to: 320 + /* 304 */ MCD_OPC_CheckPredicate, + 3, + 207, + 0, + 0, // Skip to: 516 + /* 309 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 200, + 0, + 0, // Skip to: 516 + /* 316 */ MCD_OPC_Decode, + 141, + 20, + 12, // Opcode: SNE + /* 320 */ MCD_OPC_FilterValue, + 44, + 23, + 0, + 0, // Skip to: 348 + /* 325 */ MCD_OPC_CheckPredicate, + 3, + 186, + 0, + 0, // Skip to: 516 + /* 330 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 179, + 0, + 0, // Skip to: 516 + /* 337 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 172, + 0, + 0, // Skip to: 516 + /* 344 */ MCD_OPC_Decode, + 128, + 18, + 14, // Opcode: POP + /* 348 */ MCD_OPC_FilterValue, + 45, + 23, + 0, + 0, // Skip to: 376 + /* 353 */ MCD_OPC_CheckPredicate, + 3, + 158, + 0, + 0, // Skip to: 516 + /* 358 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 151, + 0, + 0, // Skip to: 516 + /* 365 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 144, + 0, + 0, // Skip to: 516 + /* 372 */ MCD_OPC_Decode, + 175, + 11, + 15, // Opcode: DPOP + /* 376 */ MCD_OPC_FilterValue, + 46, + 9, + 0, + 0, // Skip to: 390 + /* 381 */ MCD_OPC_CheckPredicate, + 3, + 130, + 0, + 0, // Skip to: 516 + /* 386 */ MCD_OPC_Decode, + 170, + 19, + 16, // Opcode: SEQi + /* 390 */ MCD_OPC_FilterValue, + 47, + 9, + 0, + 0, // Skip to: 404 + /* 395 */ MCD_OPC_CheckPredicate, + 3, + 116, + 0, + 0, // Skip to: 516 + /* 400 */ MCD_OPC_Decode, + 142, + 20, + 16, // Opcode: SNEi + /* 404 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 418 + /* 409 */ MCD_OPC_CheckPredicate, + 4, + 102, + 0, + 0, // Skip to: 516 + /* 414 */ MCD_OPC_Decode, + 178, + 8, + 17, // Opcode: CINS + /* 418 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 432 + /* 423 */ MCD_OPC_CheckPredicate, + 4, + 88, + 0, + 0, // Skip to: 516 + /* 428 */ MCD_OPC_Decode, + 179, + 8, + 17, // Opcode: CINS32 + /* 432 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 446 + /* 437 */ MCD_OPC_CheckPredicate, + 4, + 74, + 0, + 0, // Skip to: 516 + /* 442 */ MCD_OPC_Decode, + 134, + 12, + 17, // Opcode: EXTS + /* 446 */ MCD_OPC_FilterValue, + 59, + 65, + 0, + 0, // Skip to: 516 + /* 451 */ MCD_OPC_CheckPredicate, + 4, + 60, + 0, + 0, // Skip to: 516 + /* 456 */ MCD_OPC_Decode, + 135, + 12, + 17, // Opcode: EXTS32 + /* 460 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 474 + /* 465 */ MCD_OPC_CheckPredicate, + 3, + 46, + 0, + 0, // Skip to: 516 + /* 470 */ MCD_OPC_Decode, + 205, + 6, + 18, // Opcode: BBIT0 + /* 474 */ MCD_OPC_FilterValue, + 54, + 9, + 0, + 0, // Skip to: 488 + /* 479 */ MCD_OPC_CheckPredicate, + 3, + 32, + 0, + 0, // Skip to: 516 + /* 484 */ MCD_OPC_Decode, + 206, + 6, + 18, // Opcode: BBIT032 + /* 488 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 502 + /* 493 */ MCD_OPC_CheckPredicate, + 3, + 18, + 0, + 0, // Skip to: 516 + /* 498 */ MCD_OPC_Decode, + 207, + 6, + 18, // Opcode: BBIT1 + /* 502 */ MCD_OPC_FilterValue, + 62, + 9, + 0, + 0, // Skip to: 516 + /* 507 */ MCD_OPC_CheckPredicate, + 3, + 4, + 0, + 0, // Skip to: 516 + /* 512 */ MCD_OPC_Decode, + 208, + 6, + 18, // Opcode: BBIT132 + /* 516 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableCnMipsP32[] = { + /* 0 */ MCD_OPC_ExtractField, + 0, + 16, // Inst{15-0} ... + /* 3 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 24 + /* 8 */ MCD_OPC_CheckPredicate, + 5, + 32, + 0, + 0, // Skip to: 45 + /* 13 */ MCD_OPC_CheckField, + 26, + 6, + 28, + 25, + 0, + 0, // Skip to: 45 + /* 20 */ MCD_OPC_Decode, + 224, + 18, + 19, // Opcode: SAA + /* 24 */ MCD_OPC_FilterValue, + 25, + 16, + 0, + 0, // Skip to: 45 + /* 29 */ MCD_OPC_CheckPredicate, + 5, + 11, + 0, + 0, // Skip to: 45 + /* 34 */ MCD_OPC_CheckField, + 26, + 6, + 28, + 4, + 0, + 0, // Skip to: 45 + /* 41 */ MCD_OPC_Decode, + 225, + 18, + 19, // Opcode: SAAD + /* 45 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableMicroMips16[] = { -/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33 -/* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 21 -/* 14 */ MCD_OPC_CheckPredicate, 3, 19, 2, // Skip to: 549 -/* 18 */ MCD_OPC_Decode, 52, 11, // Opcode: ADDU16_MM -/* 21 */ MCD_OPC_FilterValue, 1, 12, 2, // Skip to: 549 -/* 25 */ MCD_OPC_CheckPredicate, 3, 8, 2, // Skip to: 549 -/* 29 */ MCD_OPC_Decode, 214, 12, 11, // Opcode: SUBU16_MM -/* 33 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 45 -/* 37 */ MCD_OPC_CheckPredicate, 3, 252, 1, // Skip to: 549 -/* 41 */ MCD_OPC_Decode, 155, 7, 12, // Opcode: LBU16_MM -/* 45 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 57 -/* 49 */ MCD_OPC_CheckPredicate, 3, 240, 1, // Skip to: 549 -/* 53 */ MCD_OPC_Decode, 233, 8, 13, // Opcode: MOVE16_MM -/* 57 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 88 -/* 61 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 64 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 76 -/* 68 */ MCD_OPC_CheckPredicate, 3, 221, 1, // Skip to: 549 -/* 72 */ MCD_OPC_Decode, 226, 11, 14, // Opcode: SLL16_MM -/* 76 */ MCD_OPC_FilterValue, 1, 213, 1, // Skip to: 549 -/* 80 */ MCD_OPC_CheckPredicate, 3, 209, 1, // Skip to: 549 -/* 84 */ MCD_OPC_Decode, 160, 12, 14, // Opcode: SRL16_MM -/* 88 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 100 -/* 92 */ MCD_OPC_CheckPredicate, 3, 197, 1, // Skip to: 549 -/* 96 */ MCD_OPC_Decode, 186, 7, 12, // Opcode: LHU16_MM -/* 100 */ MCD_OPC_FilterValue, 11, 7, 0, // Skip to: 111 -/* 104 */ MCD_OPC_CheckPredicate, 3, 185, 1, // Skip to: 549 -/* 108 */ MCD_OPC_Decode, 86, 15, // Opcode: ANDI16_MM -/* 111 */ MCD_OPC_FilterValue, 17, 226, 0, // Skip to: 341 -/* 115 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 -/* 122 */ MCD_OPC_CheckPredicate, 3, 167, 1, // Skip to: 549 -/* 126 */ MCD_OPC_Decode, 130, 10, 16, // Opcode: NOT16_MM -/* 130 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 142 -/* 134 */ MCD_OPC_CheckPredicate, 3, 155, 1, // Skip to: 549 -/* 138 */ MCD_OPC_Decode, 237, 13, 17, // Opcode: XOR16_MM -/* 142 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 153 -/* 146 */ MCD_OPC_CheckPredicate, 3, 143, 1, // Skip to: 549 -/* 150 */ MCD_OPC_Decode, 84, 17, // Opcode: AND16_MM -/* 153 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 165 -/* 157 */ MCD_OPC_CheckPredicate, 3, 132, 1, // Skip to: 549 -/* 161 */ MCD_OPC_Decode, 134, 10, 17, // Opcode: OR16_MM -/* 165 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 177 -/* 169 */ MCD_OPC_CheckPredicate, 3, 120, 1, // Skip to: 549 -/* 173 */ MCD_OPC_Decode, 225, 7, 18, // Opcode: LWM16_MM -/* 177 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 189 -/* 181 */ MCD_OPC_CheckPredicate, 3, 108, 1, // Skip to: 549 -/* 185 */ MCD_OPC_Decode, 246, 12, 18, // Opcode: SWM16_MM -/* 189 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 220 -/* 193 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 196 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 208 -/* 200 */ MCD_OPC_CheckPredicate, 3, 89, 1, // Skip to: 549 -/* 204 */ MCD_OPC_Decode, 137, 7, 19, // Opcode: JR16_MM -/* 208 */ MCD_OPC_FilterValue, 1, 81, 1, // Skip to: 549 -/* 212 */ MCD_OPC_CheckPredicate, 3, 77, 1, // Skip to: 549 -/* 216 */ MCD_OPC_Decode, 140, 7, 19, // Opcode: JRC16_MM -/* 220 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 251 -/* 224 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 227 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 239 -/* 231 */ MCD_OPC_CheckPredicate, 3, 58, 1, // Skip to: 549 -/* 235 */ MCD_OPC_Decode, 250, 6, 19, // Opcode: JALR16_MM -/* 239 */ MCD_OPC_FilterValue, 1, 50, 1, // Skip to: 549 -/* 243 */ MCD_OPC_CheckPredicate, 3, 46, 1, // Skip to: 549 -/* 247 */ MCD_OPC_Decode, 254, 6, 19, // Opcode: JALRS16_MM -/* 251 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 269 -/* 255 */ MCD_OPC_CheckPredicate, 3, 34, 1, // Skip to: 549 -/* 259 */ MCD_OPC_CheckField, 5, 1, 0, 28, 1, // Skip to: 549 -/* 265 */ MCD_OPC_Decode, 187, 8, 19, // Opcode: MFHI16_MM -/* 269 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 287 -/* 273 */ MCD_OPC_CheckPredicate, 3, 16, 1, // Skip to: 549 -/* 277 */ MCD_OPC_CheckField, 5, 1, 0, 10, 1, // Skip to: 549 -/* 283 */ MCD_OPC_Decode, 192, 8, 19, // Opcode: MFLO16_MM -/* 287 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 305 -/* 291 */ MCD_OPC_CheckPredicate, 3, 254, 0, // Skip to: 549 -/* 295 */ MCD_OPC_CheckField, 4, 2, 0, 248, 0, // Skip to: 549 -/* 301 */ MCD_OPC_Decode, 172, 2, 20, // Opcode: BREAK16_MM -/* 305 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 323 -/* 309 */ MCD_OPC_CheckPredicate, 3, 236, 0, // Skip to: 549 -/* 313 */ MCD_OPC_CheckField, 4, 2, 0, 230, 0, // Skip to: 549 -/* 319 */ MCD_OPC_Decode, 153, 11, 20, // Opcode: SDBBP16_MM -/* 323 */ MCD_OPC_FilterValue, 12, 222, 0, // Skip to: 549 -/* 327 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 549 -/* 331 */ MCD_OPC_CheckField, 5, 1, 0, 212, 0, // Skip to: 549 -/* 337 */ MCD_OPC_Decode, 139, 7, 21, // Opcode: JRADDIUSP -/* 341 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 353 -/* 345 */ MCD_OPC_CheckPredicate, 3, 200, 0, // Skip to: 549 -/* 349 */ MCD_OPC_Decode, 233, 7, 22, // Opcode: LWSP_MM -/* 353 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 382 -/* 357 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 360 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 371 -/* 364 */ MCD_OPC_CheckPredicate, 3, 181, 0, // Skip to: 549 -/* 368 */ MCD_OPC_Decode, 30, 23, // Opcode: ADDIUS5_MM -/* 371 */ MCD_OPC_FilterValue, 1, 174, 0, // Skip to: 549 -/* 375 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 549 -/* 379 */ MCD_OPC_Decode, 31, 24, // Opcode: ADDIUSP_MM -/* 382 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 394 -/* 386 */ MCD_OPC_CheckPredicate, 3, 159, 0, // Skip to: 549 -/* 390 */ MCD_OPC_Decode, 221, 7, 25, // Opcode: LWGP_MM -/* 394 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 406 -/* 398 */ MCD_OPC_CheckPredicate, 3, 147, 0, // Skip to: 549 -/* 402 */ MCD_OPC_Decode, 214, 7, 12, // Opcode: LW16_MM -/* 406 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 435 -/* 410 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 413 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 424 -/* 417 */ MCD_OPC_CheckPredicate, 3, 128, 0, // Skip to: 549 -/* 421 */ MCD_OPC_Decode, 29, 26, // Opcode: ADDIUR2_MM -/* 424 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 549 -/* 428 */ MCD_OPC_CheckPredicate, 3, 117, 0, // Skip to: 549 -/* 432 */ MCD_OPC_Decode, 28, 27, // Opcode: ADDIUR1SP_MM -/* 435 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 453 -/* 439 */ MCD_OPC_CheckPredicate, 3, 106, 0, // Skip to: 549 -/* 443 */ MCD_OPC_CheckField, 0, 1, 0, 100, 0, // Skip to: 549 -/* 449 */ MCD_OPC_Decode, 234, 8, 28, // Opcode: MOVEP_MM -/* 453 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 465 -/* 457 */ MCD_OPC_CheckPredicate, 3, 88, 0, // Skip to: 549 -/* 461 */ MCD_OPC_Decode, 143, 11, 12, // Opcode: SB16_MM -/* 465 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 477 -/* 469 */ MCD_OPC_CheckPredicate, 3, 76, 0, // Skip to: 549 -/* 473 */ MCD_OPC_Decode, 210, 1, 29, // Opcode: BEQZ16_MM -/* 477 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 489 -/* 481 */ MCD_OPC_CheckPredicate, 3, 64, 0, // Skip to: 549 -/* 485 */ MCD_OPC_Decode, 187, 11, 12, // Opcode: SH16_MM -/* 489 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 501 -/* 493 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 549 -/* 497 */ MCD_OPC_Decode, 157, 2, 29, // Opcode: BNEZ16_MM -/* 501 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 513 -/* 505 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 549 -/* 509 */ MCD_OPC_Decode, 253, 12, 22, // Opcode: SWSP_MM -/* 513 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 525 -/* 517 */ MCD_OPC_CheckPredicate, 4, 28, 0, // Skip to: 549 -/* 521 */ MCD_OPC_Decode, 165, 1, 30, // Opcode: B16_MM -/* 525 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 537 -/* 529 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 549 -/* 533 */ MCD_OPC_Decode, 236, 12, 12, // Opcode: SW16_MM -/* 537 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 549 -/* 541 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 549 -/* 545 */ MCD_OPC_Decode, 192, 7, 31, // Opcode: LI16_MM -/* 549 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 3 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 39 + /* 8 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 25 + /* 16 */ MCD_OPC_CheckPredicate, + 6, + 114, + 2, + 0, // Skip to: 647 + /* 21 */ MCD_OPC_Decode, + 232, + 5, + 20, // Opcode: ADDU16_MM + /* 25 */ MCD_OPC_FilterValue, + 1, + 105, + 2, + 0, // Skip to: 647 + /* 30 */ MCD_OPC_CheckPredicate, + 6, + 100, + 2, + 0, // Skip to: 647 + /* 35 */ MCD_OPC_Decode, + 231, + 20, + 20, // Opcode: SUBU16_MM + /* 39 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 53 + /* 44 */ MCD_OPC_CheckPredicate, + 7, + 86, + 2, + 0, // Skip to: 647 + /* 49 */ MCD_OPC_Decode, + 156, + 14, + 21, // Opcode: LBU16_MM + /* 53 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 67 + /* 58 */ MCD_OPC_CheckPredicate, + 6, + 72, + 2, + 0, // Skip to: 647 + /* 63 */ MCD_OPC_Decode, + 157, + 16, + 22, // Opcode: MOVE16_MM + /* 67 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 103 + /* 72 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 75 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 89 + /* 80 */ MCD_OPC_CheckPredicate, + 6, + 50, + 2, + 0, // Skip to: 647 + /* 85 */ MCD_OPC_Decode, + 241, + 19, + 23, // Opcode: SLL16_MM + /* 89 */ MCD_OPC_FilterValue, + 1, + 41, + 2, + 0, // Skip to: 647 + /* 94 */ MCD_OPC_CheckPredicate, + 6, + 36, + 2, + 0, // Skip to: 647 + /* 99 */ MCD_OPC_Decode, + 172, + 20, + 23, // Opcode: SRL16_MM + /* 103 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 117 + /* 108 */ MCD_OPC_CheckPredicate, + 7, + 22, + 2, + 0, // Skip to: 647 + /* 113 */ MCD_OPC_Decode, + 196, + 14, + 21, // Opcode: LHU16_MM + /* 117 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 131 + /* 122 */ MCD_OPC_CheckPredicate, + 6, + 8, + 2, + 0, // Skip to: 647 + /* 127 */ MCD_OPC_Decode, + 149, + 6, + 24, // Opcode: ANDI16_MM + /* 131 */ MCD_OPC_FilterValue, + 17, + 8, + 1, + 0, // Skip to: 400 + /* 136 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 139 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 153 + /* 144 */ MCD_OPC_CheckPredicate, + 6, + 242, + 1, + 0, // Skip to: 647 + /* 149 */ MCD_OPC_Decode, + 216, + 17, + 25, // Opcode: NOT16_MM + /* 153 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 167 + /* 158 */ MCD_OPC_CheckPredicate, + 6, + 228, + 1, + 0, // Skip to: 647 + /* 163 */ MCD_OPC_Decode, + 146, + 22, + 26, // Opcode: XOR16_MM + /* 167 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 181 + /* 172 */ MCD_OPC_CheckPredicate, + 6, + 214, + 1, + 0, // Skip to: 647 + /* 177 */ MCD_OPC_Decode, + 146, + 6, + 26, // Opcode: AND16_MM + /* 181 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 195 + /* 186 */ MCD_OPC_CheckPredicate, + 6, + 200, + 1, + 0, // Skip to: 647 + /* 191 */ MCD_OPC_Decode, + 221, + 17, + 26, // Opcode: OR16_MM + /* 195 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 209 + /* 200 */ MCD_OPC_CheckPredicate, + 6, + 186, + 1, + 0, // Skip to: 647 + /* 205 */ MCD_OPC_Decode, + 246, + 14, + 27, // Opcode: LWM16_MM + /* 209 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 223 + /* 214 */ MCD_OPC_CheckPredicate, + 6, + 172, + 1, + 0, // Skip to: 647 + /* 219 */ MCD_OPC_Decode, + 152, + 21, + 27, // Opcode: SWM16_MM + /* 223 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 259 + /* 228 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 231 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 245 + /* 236 */ MCD_OPC_CheckPredicate, + 6, + 150, + 1, + 0, // Skip to: 647 + /* 241 */ MCD_OPC_Decode, + 134, + 14, + 28, // Opcode: JR16_MM + /* 245 */ MCD_OPC_FilterValue, + 1, + 141, + 1, + 0, // Skip to: 647 + /* 250 */ MCD_OPC_CheckPredicate, + 6, + 136, + 1, + 0, // Skip to: 647 + /* 255 */ MCD_OPC_Decode, + 137, + 14, + 28, // Opcode: JRC16_MM + /* 259 */ MCD_OPC_FilterValue, + 7, + 31, + 0, + 0, // Skip to: 295 + /* 264 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 267 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 281 + /* 272 */ MCD_OPC_CheckPredicate, + 6, + 114, + 1, + 0, // Skip to: 647 + /* 277 */ MCD_OPC_Decode, + 241, + 13, + 28, // Opcode: JALR16_MM + /* 281 */ MCD_OPC_FilterValue, + 1, + 105, + 1, + 0, // Skip to: 647 + /* 286 */ MCD_OPC_CheckPredicate, + 6, + 100, + 1, + 0, // Skip to: 647 + /* 291 */ MCD_OPC_Decode, + 246, + 13, + 28, // Opcode: JALRS16_MM + /* 295 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 316 + /* 300 */ MCD_OPC_CheckPredicate, + 6, + 86, + 1, + 0, // Skip to: 647 + /* 305 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 79, + 1, + 0, // Skip to: 647 + /* 312 */ MCD_OPC_Decode, + 231, + 15, + 28, // Opcode: MFHI16_MM + /* 316 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 337 + /* 321 */ MCD_OPC_CheckPredicate, + 6, + 65, + 1, + 0, // Skip to: 647 + /* 326 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 58, + 1, + 0, // Skip to: 647 + /* 333 */ MCD_OPC_Decode, + 237, + 15, + 28, // Opcode: MFLO16_MM + /* 337 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 358 + /* 342 */ MCD_OPC_CheckPredicate, + 6, + 44, + 1, + 0, // Skip to: 647 + /* 347 */ MCD_OPC_CheckField, + 4, + 2, + 0, + 37, + 1, + 0, // Skip to: 647 + /* 354 */ MCD_OPC_Decode, + 247, + 7, + 29, // Opcode: BREAK16_MM + /* 358 */ MCD_OPC_FilterValue, + 11, + 16, + 0, + 0, // Skip to: 379 + /* 363 */ MCD_OPC_CheckPredicate, + 6, + 23, + 1, + 0, // Skip to: 647 + /* 368 */ MCD_OPC_CheckField, + 4, + 2, + 0, + 16, + 1, + 0, // Skip to: 647 + /* 375 */ MCD_OPC_Decode, + 254, + 18, + 29, // Opcode: SDBBP16_MM + /* 379 */ MCD_OPC_FilterValue, + 12, + 7, + 1, + 0, // Skip to: 647 + /* 384 */ MCD_OPC_CheckPredicate, + 6, + 2, + 1, + 0, // Skip to: 647 + /* 389 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 251, + 0, + 0, // Skip to: 647 + /* 396 */ MCD_OPC_Decode, + 136, + 14, + 30, // Opcode: JRADDIUSP + /* 400 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 414 + /* 405 */ MCD_OPC_CheckPredicate, + 7, + 237, + 0, + 0, // Skip to: 647 + /* 410 */ MCD_OPC_Decode, + 129, + 15, + 31, // Opcode: LWSP_MM + /* 414 */ MCD_OPC_FilterValue, + 19, + 31, + 0, + 0, // Skip to: 450 + /* 419 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 422 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 436 + /* 427 */ MCD_OPC_CheckPredicate, + 7, + 215, + 0, + 0, // Skip to: 647 + /* 432 */ MCD_OPC_Decode, + 200, + 5, + 32, // Opcode: ADDIUS5_MM + /* 436 */ MCD_OPC_FilterValue, + 1, + 206, + 0, + 0, // Skip to: 647 + /* 441 */ MCD_OPC_CheckPredicate, + 7, + 201, + 0, + 0, // Skip to: 647 + /* 446 */ MCD_OPC_Decode, + 201, + 5, + 33, // Opcode: ADDIUSP_MM + /* 450 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 464 + /* 455 */ MCD_OPC_CheckPredicate, + 7, + 187, + 0, + 0, // Skip to: 647 + /* 460 */ MCD_OPC_Decode, + 240, + 14, + 34, // Opcode: LWGP_MM + /* 464 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 478 + /* 469 */ MCD_OPC_CheckPredicate, + 7, + 173, + 0, + 0, // Skip to: 647 + /* 474 */ MCD_OPC_Decode, + 228, + 14, + 21, // Opcode: LW16_MM + /* 478 */ MCD_OPC_FilterValue, + 27, + 31, + 0, + 0, // Skip to: 514 + /* 483 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 486 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 500 + /* 491 */ MCD_OPC_CheckPredicate, + 7, + 151, + 0, + 0, // Skip to: 647 + /* 496 */ MCD_OPC_Decode, + 199, + 5, + 35, // Opcode: ADDIUR2_MM + /* 500 */ MCD_OPC_FilterValue, + 1, + 142, + 0, + 0, // Skip to: 647 + /* 505 */ MCD_OPC_CheckPredicate, + 7, + 137, + 0, + 0, // Skip to: 647 + /* 510 */ MCD_OPC_Decode, + 198, + 5, + 36, // Opcode: ADDIUR1SP_MM + /* 514 */ MCD_OPC_FilterValue, + 33, + 16, + 0, + 0, // Skip to: 535 + /* 519 */ MCD_OPC_CheckPredicate, + 6, + 123, + 0, + 0, // Skip to: 647 + /* 524 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 116, + 0, + 0, // Skip to: 647 + /* 531 */ MCD_OPC_Decode, + 159, + 16, + 37, // Opcode: MOVEP_MM + /* 535 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 549 + /* 540 */ MCD_OPC_CheckPredicate, + 6, + 102, + 0, + 0, // Skip to: 647 + /* 545 */ MCD_OPC_Decode, + 235, + 18, + 21, // Opcode: SB16_MM + /* 549 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 563 + /* 554 */ MCD_OPC_CheckPredicate, + 6, + 88, + 0, + 0, // Skip to: 647 + /* 559 */ MCD_OPC_Decode, + 250, + 6, + 38, // Opcode: BEQZ16_MM + /* 563 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 577 + /* 568 */ MCD_OPC_CheckPredicate, + 6, + 74, + 0, + 0, // Skip to: 647 + /* 573 */ MCD_OPC_Decode, + 172, + 19, + 21, // Opcode: SH16_MM + /* 577 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 591 + /* 582 */ MCD_OPC_CheckPredicate, + 6, + 60, + 0, + 0, // Skip to: 647 + /* 587 */ MCD_OPC_Decode, + 225, + 7, + 38, // Opcode: BNEZ16_MM + /* 591 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 605 + /* 596 */ MCD_OPC_CheckPredicate, + 6, + 46, + 0, + 0, // Skip to: 647 + /* 601 */ MCD_OPC_Decode, + 161, + 21, + 31, // Opcode: SWSP_MM + /* 605 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 619 + /* 610 */ MCD_OPC_CheckPredicate, + 7, + 32, + 0, + 0, // Skip to: 647 + /* 615 */ MCD_OPC_Decode, + 198, + 6, + 39, // Opcode: B16_MM + /* 619 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 633 + /* 624 */ MCD_OPC_CheckPredicate, + 6, + 18, + 0, + 0, // Skip to: 647 + /* 629 */ MCD_OPC_Decode, + 134, + 21, + 21, // Opcode: SW16_MM + /* 633 */ MCD_OPC_FilterValue, + 59, + 9, + 0, + 0, // Skip to: 647 + /* 638 */ MCD_OPC_CheckPredicate, + 6, + 4, + 0, + 0, // Skip to: 647 + /* 643 */ MCD_OPC_Decode, + 205, + 14, + 40, // Opcode: LI16_MM + /* 647 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableMicroMips32[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 189, 3, // Skip to: 964 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 90, 0, // Skip to: 104 -/* 14 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 17 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 68 -/* 21 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... -/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 -/* 28 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 60 -/* 32 */ MCD_OPC_Decode, 181, 12, 0, // Opcode: SSNOP_MM -/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 -/* 40 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 60 -/* 44 */ MCD_OPC_Decode, 140, 5, 0, // Opcode: EHB_MM -/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 -/* 52 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 60 -/* 56 */ MCD_OPC_Decode, 148, 10, 0, // Opcode: PAUSE_MM -/* 60 */ MCD_OPC_CheckPredicate, 3, 38, 6, // Skip to: 1638 -/* 64 */ MCD_OPC_Decode, 238, 11, 32, // Opcode: SLL_MM -/* 68 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 80 -/* 72 */ MCD_OPC_CheckPredicate, 3, 26, 6, // Skip to: 1638 -/* 76 */ MCD_OPC_Decode, 178, 12, 32, // Opcode: SRL_MM -/* 80 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 92 -/* 84 */ MCD_OPC_CheckPredicate, 3, 14, 6, // Skip to: 1638 -/* 88 */ MCD_OPC_Decode, 157, 12, 32, // Opcode: SRA_MM -/* 92 */ MCD_OPC_FilterValue, 3, 6, 6, // Skip to: 1638 -/* 96 */ MCD_OPC_CheckPredicate, 3, 2, 6, // Skip to: 1638 -/* 100 */ MCD_OPC_Decode, 250, 10, 32, // Opcode: ROTR_MM -/* 104 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 116 -/* 108 */ MCD_OPC_CheckPredicate, 3, 246, 5, // Skip to: 1638 -/* 112 */ MCD_OPC_Decode, 173, 2, 33, // Opcode: BREAK_MM -/* 116 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 128 -/* 120 */ MCD_OPC_CheckPredicate, 3, 234, 5, // Skip to: 1638 -/* 124 */ MCD_OPC_Decode, 246, 6, 34, // Opcode: INS_MM -/* 128 */ MCD_OPC_FilterValue, 16, 180, 0, // Skip to: 312 -/* 132 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 135 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 147 -/* 139 */ MCD_OPC_CheckPredicate, 3, 215, 5, // Skip to: 1638 -/* 143 */ MCD_OPC_Decode, 234, 11, 35, // Opcode: SLLV_MM -/* 147 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 159 -/* 151 */ MCD_OPC_CheckPredicate, 3, 203, 5, // Skip to: 1638 -/* 155 */ MCD_OPC_Decode, 174, 12, 35, // Opcode: SRLV_MM -/* 159 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 171 -/* 163 */ MCD_OPC_CheckPredicate, 3, 191, 5, // Skip to: 1638 -/* 167 */ MCD_OPC_Decode, 153, 12, 35, // Opcode: SRAV_MM -/* 171 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 183 -/* 175 */ MCD_OPC_CheckPredicate, 3, 179, 5, // Skip to: 1638 -/* 179 */ MCD_OPC_Decode, 249, 10, 35, // Opcode: ROTRV_MM -/* 183 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 194 -/* 187 */ MCD_OPC_CheckPredicate, 3, 167, 5, // Skip to: 1638 -/* 191 */ MCD_OPC_Decode, 72, 36, // Opcode: ADD_MM -/* 194 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 205 -/* 198 */ MCD_OPC_CheckPredicate, 3, 156, 5, // Skip to: 1638 -/* 202 */ MCD_OPC_Decode, 78, 36, // Opcode: ADDu_MM -/* 205 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 217 -/* 209 */ MCD_OPC_CheckPredicate, 3, 145, 5, // Skip to: 1638 -/* 213 */ MCD_OPC_Decode, 229, 12, 36, // Opcode: SUB_MM -/* 217 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 229 -/* 221 */ MCD_OPC_CheckPredicate, 3, 133, 5, // Skip to: 1638 -/* 225 */ MCD_OPC_Decode, 231, 12, 36, // Opcode: SUBu_MM -/* 229 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 241 -/* 233 */ MCD_OPC_CheckPredicate, 3, 121, 5, // Skip to: 1638 -/* 237 */ MCD_OPC_Decode, 217, 9, 36, // Opcode: MUL_MM -/* 241 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 252 -/* 245 */ MCD_OPC_CheckPredicate, 3, 109, 5, // Skip to: 1638 -/* 249 */ MCD_OPC_Decode, 88, 36, // Opcode: AND_MM -/* 252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 264 -/* 256 */ MCD_OPC_CheckPredicate, 3, 98, 5, // Skip to: 1638 -/* 260 */ MCD_OPC_Decode, 137, 10, 36, // Opcode: OR_MM -/* 264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 276 -/* 268 */ MCD_OPC_CheckPredicate, 3, 86, 5, // Skip to: 1638 -/* 272 */ MCD_OPC_Decode, 253, 9, 36, // Opcode: NOR_MM -/* 276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 288 -/* 280 */ MCD_OPC_CheckPredicate, 3, 74, 5, // Skip to: 1638 -/* 284 */ MCD_OPC_Decode, 240, 13, 36, // Opcode: XOR_MM -/* 288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 300 -/* 292 */ MCD_OPC_CheckPredicate, 3, 62, 5, // Skip to: 1638 -/* 296 */ MCD_OPC_Decode, 242, 11, 36, // Opcode: SLT_MM -/* 300 */ MCD_OPC_FilterValue, 14, 54, 5, // Skip to: 1638 -/* 304 */ MCD_OPC_CheckPredicate, 3, 50, 5, // Skip to: 1638 -/* 308 */ MCD_OPC_Decode, 251, 11, 36, // Opcode: SLTu_MM -/* 312 */ MCD_OPC_FilterValue, 24, 39, 0, // Skip to: 355 -/* 316 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 319 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 331 -/* 323 */ MCD_OPC_CheckPredicate, 3, 31, 5, // Skip to: 1638 -/* 327 */ MCD_OPC_Decode, 253, 8, 37, // Opcode: MOVN_I_MM -/* 331 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 343 -/* 335 */ MCD_OPC_CheckPredicate, 3, 19, 5, // Skip to: 1638 -/* 339 */ MCD_OPC_Decode, 145, 9, 37, // Opcode: MOVZ_I_MM -/* 343 */ MCD_OPC_FilterValue, 4, 11, 5, // Skip to: 1638 -/* 347 */ MCD_OPC_CheckPredicate, 3, 7, 5, // Skip to: 1638 -/* 351 */ MCD_OPC_Decode, 239, 7, 38, // Opcode: LWXS_MM -/* 355 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 367 -/* 359 */ MCD_OPC_CheckPredicate, 3, 251, 4, // Skip to: 1638 -/* 363 */ MCD_OPC_Decode, 160, 5, 39, // Opcode: EXT_MM -/* 367 */ MCD_OPC_FilterValue, 60, 243, 4, // Skip to: 1638 -/* 371 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... -/* 374 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 386 -/* 378 */ MCD_OPC_CheckPredicate, 3, 232, 4, // Skip to: 1638 -/* 382 */ MCD_OPC_Decode, 185, 13, 40, // Opcode: TEQ_MM -/* 386 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 398 -/* 390 */ MCD_OPC_CheckPredicate, 3, 220, 4, // Skip to: 1638 -/* 394 */ MCD_OPC_Decode, 193, 13, 40, // Opcode: TGE_MM -/* 398 */ MCD_OPC_FilterValue, 13, 123, 0, // Skip to: 525 -/* 402 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 405 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 423 -/* 409 */ MCD_OPC_CheckPredicate, 3, 201, 4, // Skip to: 1638 -/* 413 */ MCD_OPC_CheckField, 16, 10, 0, 195, 4, // Skip to: 1638 -/* 419 */ MCD_OPC_Decode, 195, 13, 0, // Opcode: TLBP_MM -/* 423 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 441 -/* 427 */ MCD_OPC_CheckPredicate, 3, 183, 4, // Skip to: 1638 -/* 431 */ MCD_OPC_CheckField, 16, 10, 0, 177, 4, // Skip to: 1638 -/* 437 */ MCD_OPC_Decode, 197, 13, 0, // Opcode: TLBR_MM -/* 441 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 459 -/* 445 */ MCD_OPC_CheckPredicate, 3, 165, 4, // Skip to: 1638 -/* 449 */ MCD_OPC_CheckField, 16, 10, 0, 159, 4, // Skip to: 1638 -/* 455 */ MCD_OPC_Decode, 199, 13, 0, // Opcode: TLBWI_MM -/* 459 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 477 -/* 463 */ MCD_OPC_CheckPredicate, 3, 147, 4, // Skip to: 1638 -/* 467 */ MCD_OPC_CheckField, 16, 10, 0, 141, 4, // Skip to: 1638 -/* 473 */ MCD_OPC_Decode, 201, 13, 0, // Opcode: TLBWR_MM -/* 477 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 489 -/* 481 */ MCD_OPC_CheckPredicate, 3, 129, 4, // Skip to: 1638 -/* 485 */ MCD_OPC_Decode, 232, 13, 41, // Opcode: WAIT_MM -/* 489 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 507 -/* 493 */ MCD_OPC_CheckPredicate, 3, 117, 4, // Skip to: 1638 -/* 497 */ MCD_OPC_CheckField, 16, 10, 0, 111, 4, // Skip to: 1638 -/* 503 */ MCD_OPC_Decode, 175, 4, 0, // Opcode: DERET_MM -/* 507 */ MCD_OPC_FilterValue, 15, 103, 4, // Skip to: 1638 -/* 511 */ MCD_OPC_CheckPredicate, 3, 99, 4, // Skip to: 1638 -/* 515 */ MCD_OPC_CheckField, 16, 10, 0, 93, 4, // Skip to: 1638 -/* 521 */ MCD_OPC_Decode, 144, 5, 0, // Opcode: ERET_MM -/* 525 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 537 -/* 529 */ MCD_OPC_CheckPredicate, 3, 81, 4, // Skip to: 1638 -/* 533 */ MCD_OPC_Decode, 192, 13, 40, // Opcode: TGEU_MM -/* 537 */ MCD_OPC_FilterValue, 29, 39, 0, // Skip to: 580 -/* 541 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 544 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 562 -/* 548 */ MCD_OPC_CheckPredicate, 3, 62, 4, // Skip to: 1638 -/* 552 */ MCD_OPC_CheckField, 21, 5, 0, 56, 4, // Skip to: 1638 -/* 558 */ MCD_OPC_Decode, 193, 4, 42, // Opcode: DI_MM -/* 562 */ MCD_OPC_FilterValue, 5, 48, 4, // Skip to: 1638 -/* 566 */ MCD_OPC_CheckPredicate, 3, 44, 4, // Skip to: 1638 -/* 570 */ MCD_OPC_CheckField, 21, 5, 0, 38, 4, // Skip to: 1638 -/* 576 */ MCD_OPC_Decode, 142, 5, 42, // Opcode: EI_MM -/* 580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 592 -/* 584 */ MCD_OPC_CheckPredicate, 3, 26, 4, // Skip to: 1638 -/* 588 */ MCD_OPC_Decode, 208, 13, 40, // Opcode: TLT_MM -/* 592 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 604 -/* 596 */ MCD_OPC_CheckPredicate, 3, 14, 4, // Skip to: 1638 -/* 600 */ MCD_OPC_Decode, 207, 13, 40, // Opcode: TLTU_MM -/* 604 */ MCD_OPC_FilterValue, 44, 171, 0, // Skip to: 779 -/* 608 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 611 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 623 -/* 615 */ MCD_OPC_CheckPredicate, 3, 251, 3, // Skip to: 1638 -/* 619 */ MCD_OPC_Decode, 170, 11, 43, // Opcode: SEB_MM -/* 623 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 635 -/* 627 */ MCD_OPC_CheckPredicate, 3, 239, 3, // Skip to: 1638 -/* 631 */ MCD_OPC_Decode, 173, 11, 43, // Opcode: SEH_MM -/* 635 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 647 -/* 639 */ MCD_OPC_CheckPredicate, 3, 227, 3, // Skip to: 1638 -/* 643 */ MCD_OPC_Decode, 134, 3, 43, // Opcode: CLO_MM -/* 647 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 659 -/* 651 */ MCD_OPC_CheckPredicate, 3, 215, 3, // Skip to: 1638 -/* 655 */ MCD_OPC_Decode, 153, 3, 43, // Opcode: CLZ_MM -/* 659 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 671 -/* 663 */ MCD_OPC_CheckPredicate, 3, 203, 3, // Skip to: 1638 -/* 667 */ MCD_OPC_Decode, 240, 10, 44, // Opcode: RDHWR_MM -/* 671 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 683 -/* 675 */ MCD_OPC_CheckPredicate, 3, 191, 3, // Skip to: 1638 -/* 679 */ MCD_OPC_Decode, 235, 13, 43, // Opcode: WSBH_MM -/* 683 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 695 -/* 687 */ MCD_OPC_CheckPredicate, 3, 179, 3, // Skip to: 1638 -/* 691 */ MCD_OPC_Decode, 209, 9, 45, // Opcode: MULT_MM -/* 695 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 707 -/* 699 */ MCD_OPC_CheckPredicate, 3, 167, 3, // Skip to: 1638 -/* 703 */ MCD_OPC_Decode, 211, 9, 45, // Opcode: MULTu_MM -/* 707 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 719 -/* 711 */ MCD_OPC_CheckPredicate, 3, 155, 3, // Skip to: 1638 -/* 715 */ MCD_OPC_Decode, 163, 11, 45, // Opcode: SDIV_MM -/* 719 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 731 -/* 723 */ MCD_OPC_CheckPredicate, 3, 143, 3, // Skip to: 1638 -/* 727 */ MCD_OPC_Decode, 223, 13, 45, // Opcode: UDIV_MM -/* 731 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 743 -/* 735 */ MCD_OPC_CheckPredicate, 3, 131, 3, // Skip to: 1638 -/* 739 */ MCD_OPC_Decode, 146, 8, 45, // Opcode: MADD_MM -/* 743 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 755 -/* 747 */ MCD_OPC_CheckPredicate, 3, 119, 3, // Skip to: 1638 -/* 751 */ MCD_OPC_Decode, 137, 8, 45, // Opcode: MADDU_MM -/* 755 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 767 -/* 759 */ MCD_OPC_CheckPredicate, 3, 107, 3, // Skip to: 1638 -/* 763 */ MCD_OPC_Decode, 164, 9, 45, // Opcode: MSUB_MM -/* 767 */ MCD_OPC_FilterValue, 15, 99, 3, // Skip to: 1638 -/* 771 */ MCD_OPC_CheckPredicate, 3, 95, 3, // Skip to: 1638 -/* 775 */ MCD_OPC_Decode, 155, 9, 45, // Opcode: MSUBU_MM -/* 779 */ MCD_OPC_FilterValue, 45, 45, 0, // Skip to: 828 -/* 783 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 786 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 804 -/* 790 */ MCD_OPC_CheckPredicate, 3, 76, 3, // Skip to: 1638 -/* 794 */ MCD_OPC_CheckField, 21, 5, 0, 70, 3, // Skip to: 1638 -/* 800 */ MCD_OPC_Decode, 131, 13, 46, // Opcode: SYNC_MM -/* 804 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 816 -/* 808 */ MCD_OPC_CheckPredicate, 3, 58, 3, // Skip to: 1638 -/* 812 */ MCD_OPC_Decode, 133, 13, 41, // Opcode: SYSCALL_MM -/* 816 */ MCD_OPC_FilterValue, 13, 50, 3, // Skip to: 1638 -/* 820 */ MCD_OPC_CheckPredicate, 3, 46, 3, // Skip to: 1638 -/* 824 */ MCD_OPC_Decode, 154, 11, 41, // Opcode: SDBBP_MM -/* 828 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 840 -/* 832 */ MCD_OPC_CheckPredicate, 3, 34, 3, // Skip to: 1638 -/* 836 */ MCD_OPC_Decode, 212, 13, 40, // Opcode: TNE_MM -/* 840 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 919 -/* 844 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 847 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 865 -/* 851 */ MCD_OPC_CheckPredicate, 3, 15, 3, // Skip to: 1638 -/* 855 */ MCD_OPC_CheckField, 21, 5, 0, 9, 3, // Skip to: 1638 -/* 861 */ MCD_OPC_Decode, 190, 8, 42, // Opcode: MFHI_MM -/* 865 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 883 -/* 869 */ MCD_OPC_CheckPredicate, 3, 253, 2, // Skip to: 1638 -/* 873 */ MCD_OPC_CheckField, 21, 5, 0, 247, 2, // Skip to: 1638 -/* 879 */ MCD_OPC_Decode, 195, 8, 42, // Opcode: MFLO_MM -/* 883 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 901 -/* 887 */ MCD_OPC_CheckPredicate, 3, 235, 2, // Skip to: 1638 -/* 891 */ MCD_OPC_CheckField, 21, 5, 0, 229, 2, // Skip to: 1638 -/* 897 */ MCD_OPC_Decode, 179, 9, 42, // Opcode: MTHI_MM -/* 901 */ MCD_OPC_FilterValue, 3, 221, 2, // Skip to: 1638 -/* 905 */ MCD_OPC_CheckPredicate, 3, 217, 2, // Skip to: 1638 -/* 909 */ MCD_OPC_CheckField, 21, 5, 0, 211, 2, // Skip to: 1638 -/* 915 */ MCD_OPC_Decode, 184, 9, 42, // Opcode: MTLO_MM -/* 919 */ MCD_OPC_FilterValue, 60, 203, 2, // Skip to: 1638 -/* 923 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 926 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 952 -/* 930 */ MCD_OPC_CheckPredicate, 3, 10, 0, // Skip to: 944 -/* 934 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 944 -/* 940 */ MCD_OPC_Decode, 143, 7, 42, // Opcode: JR_MM -/* 944 */ MCD_OPC_CheckPredicate, 3, 178, 2, // Skip to: 1638 -/* 948 */ MCD_OPC_Decode, 129, 7, 43, // Opcode: JALR_MM -/* 952 */ MCD_OPC_FilterValue, 4, 170, 2, // Skip to: 1638 -/* 956 */ MCD_OPC_CheckPredicate, 3, 166, 2, // Skip to: 1638 -/* 960 */ MCD_OPC_Decode, 255, 6, 43, // Opcode: JALRS_MM -/* 964 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 975 -/* 968 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 1638 -/* 972 */ MCD_OPC_Decode, 74, 47, // Opcode: ADDi_MM -/* 975 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 987 -/* 979 */ MCD_OPC_CheckPredicate, 3, 143, 2, // Skip to: 1638 -/* 983 */ MCD_OPC_Decode, 160, 7, 48, // Opcode: LBu_MM -/* 987 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 999 -/* 991 */ MCD_OPC_CheckPredicate, 3, 131, 2, // Skip to: 1638 -/* 995 */ MCD_OPC_Decode, 145, 11, 48, // Opcode: SB_MM -/* 999 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1011 -/* 1003 */ MCD_OPC_CheckPredicate, 3, 119, 2, // Skip to: 1638 -/* 1007 */ MCD_OPC_Decode, 157, 7, 48, // Opcode: LB_MM -/* 1011 */ MCD_OPC_FilterValue, 8, 63, 0, // Skip to: 1078 -/* 1015 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 1018 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1030 -/* 1022 */ MCD_OPC_CheckPredicate, 3, 100, 2, // Skip to: 1638 -/* 1026 */ MCD_OPC_Decode, 229, 7, 49, // Opcode: LWP_MM -/* 1030 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1042 -/* 1034 */ MCD_OPC_CheckPredicate, 3, 88, 2, // Skip to: 1638 -/* 1038 */ MCD_OPC_Decode, 226, 7, 49, // Opcode: LWM32_MM -/* 1042 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1054 -/* 1046 */ MCD_OPC_CheckPredicate, 3, 76, 2, // Skip to: 1638 -/* 1050 */ MCD_OPC_Decode, 221, 2, 50, // Opcode: CACHE_MM -/* 1054 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1066 -/* 1058 */ MCD_OPC_CheckPredicate, 3, 64, 2, // Skip to: 1638 -/* 1062 */ MCD_OPC_Decode, 249, 12, 49, // Opcode: SWP_MM -/* 1066 */ MCD_OPC_FilterValue, 13, 56, 2, // Skip to: 1638 -/* 1070 */ MCD_OPC_CheckPredicate, 3, 52, 2, // Skip to: 1638 -/* 1074 */ MCD_OPC_Decode, 247, 12, 49, // Opcode: SWM32_MM -/* 1078 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1089 -/* 1082 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 1638 -/* 1086 */ MCD_OPC_Decode, 76, 47, // Opcode: ADDiu_MM -/* 1089 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1101 -/* 1093 */ MCD_OPC_CheckPredicate, 3, 29, 2, // Skip to: 1638 -/* 1097 */ MCD_OPC_Decode, 191, 7, 48, // Opcode: LHu_MM -/* 1101 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1113 -/* 1105 */ MCD_OPC_CheckPredicate, 3, 17, 2, // Skip to: 1638 -/* 1109 */ MCD_OPC_Decode, 216, 11, 48, // Opcode: SH_MM -/* 1113 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1125 -/* 1117 */ MCD_OPC_CheckPredicate, 3, 5, 2, // Skip to: 1638 -/* 1121 */ MCD_OPC_Decode, 188, 7, 48, // Opcode: LH_MM -/* 1125 */ MCD_OPC_FilterValue, 16, 207, 0, // Skip to: 1336 -/* 1129 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1144 -/* 1136 */ MCD_OPC_CheckPredicate, 3, 242, 1, // Skip to: 1638 -/* 1140 */ MCD_OPC_Decode, 140, 2, 51, // Opcode: BLTZ_MM -/* 1144 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1156 -/* 1148 */ MCD_OPC_CheckPredicate, 3, 230, 1, // Skip to: 1638 -/* 1152 */ MCD_OPC_Decode, 137, 2, 51, // Opcode: BLTZAL_MM -/* 1156 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1168 -/* 1160 */ MCD_OPC_CheckPredicate, 3, 218, 1, // Skip to: 1638 -/* 1164 */ MCD_OPC_Decode, 226, 1, 51, // Opcode: BGEZ_MM -/* 1168 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1180 -/* 1172 */ MCD_OPC_CheckPredicate, 3, 206, 1, // Skip to: 1638 -/* 1176 */ MCD_OPC_Decode, 223, 1, 51, // Opcode: BGEZAL_MM -/* 1180 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1192 -/* 1184 */ MCD_OPC_CheckPredicate, 3, 194, 1, // Skip to: 1638 -/* 1188 */ MCD_OPC_Decode, 128, 2, 51, // Opcode: BLEZ_MM -/* 1192 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1204 -/* 1196 */ MCD_OPC_CheckPredicate, 3, 182, 1, // Skip to: 1638 -/* 1200 */ MCD_OPC_Decode, 160, 2, 51, // Opcode: BNEZC_MM -/* 1204 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1216 -/* 1208 */ MCD_OPC_CheckPredicate, 3, 170, 1, // Skip to: 1638 -/* 1212 */ MCD_OPC_Decode, 232, 1, 51, // Opcode: BGTZ_MM -/* 1216 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1228 -/* 1220 */ MCD_OPC_CheckPredicate, 3, 158, 1, // Skip to: 1638 -/* 1224 */ MCD_OPC_Decode, 213, 1, 51, // Opcode: BEQZC_MM -/* 1228 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1240 -/* 1232 */ MCD_OPC_CheckPredicate, 3, 146, 1, // Skip to: 1638 -/* 1236 */ MCD_OPC_Decode, 205, 13, 52, // Opcode: TLTI_MM -/* 1240 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1252 -/* 1244 */ MCD_OPC_CheckPredicate, 3, 134, 1, // Skip to: 1638 -/* 1248 */ MCD_OPC_Decode, 190, 13, 52, // Opcode: TGEI_MM -/* 1252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1264 -/* 1256 */ MCD_OPC_CheckPredicate, 3, 122, 1, // Skip to: 1638 -/* 1260 */ MCD_OPC_Decode, 204, 13, 52, // Opcode: TLTIU_MM -/* 1264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1276 -/* 1268 */ MCD_OPC_CheckPredicate, 3, 110, 1, // Skip to: 1638 -/* 1272 */ MCD_OPC_Decode, 189, 13, 52, // Opcode: TGEIU_MM -/* 1276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1288 -/* 1280 */ MCD_OPC_CheckPredicate, 3, 98, 1, // Skip to: 1638 -/* 1284 */ MCD_OPC_Decode, 211, 13, 52, // Opcode: TNEI_MM -/* 1288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1300 -/* 1292 */ MCD_OPC_CheckPredicate, 3, 86, 1, // Skip to: 1638 -/* 1296 */ MCD_OPC_Decode, 212, 7, 52, // Opcode: LUi_MM -/* 1300 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1312 -/* 1304 */ MCD_OPC_CheckPredicate, 3, 74, 1, // Skip to: 1638 -/* 1308 */ MCD_OPC_Decode, 184, 13, 52, // Opcode: TEQI_MM -/* 1312 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1324 -/* 1316 */ MCD_OPC_CheckPredicate, 3, 62, 1, // Skip to: 1638 -/* 1320 */ MCD_OPC_Decode, 136, 2, 51, // Opcode: BLTZALS_MM -/* 1324 */ MCD_OPC_FilterValue, 19, 54, 1, // Skip to: 1638 -/* 1328 */ MCD_OPC_CheckPredicate, 3, 50, 1, // Skip to: 1638 -/* 1332 */ MCD_OPC_Decode, 222, 1, 51, // Opcode: BGEZALS_MM -/* 1336 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 1348 -/* 1340 */ MCD_OPC_CheckPredicate, 3, 38, 1, // Skip to: 1638 -/* 1344 */ MCD_OPC_Decode, 144, 10, 53, // Opcode: ORi_MM -/* 1348 */ MCD_OPC_FilterValue, 21, 29, 0, // Skip to: 1381 -/* 1352 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ... -/* 1355 */ MCD_OPC_FilterValue, 251, 2, 8, 0, // Skip to: 1368 -/* 1360 */ MCD_OPC_CheckPredicate, 3, 18, 1, // Skip to: 1638 -/* 1364 */ MCD_OPC_Decode, 241, 8, 54, // Opcode: MOVF_I_MM -/* 1368 */ MCD_OPC_FilterValue, 251, 18, 9, 1, // Skip to: 1638 -/* 1373 */ MCD_OPC_CheckPredicate, 3, 5, 1, // Skip to: 1638 -/* 1377 */ MCD_OPC_Decode, 133, 9, 54, // Opcode: MOVT_I_MM -/* 1381 */ MCD_OPC_FilterValue, 24, 99, 0, // Skip to: 1484 -/* 1385 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 1388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1400 -/* 1392 */ MCD_OPC_CheckPredicate, 3, 242, 0, // Skip to: 1638 -/* 1396 */ MCD_OPC_Decode, 224, 7, 49, // Opcode: LWL_MM -/* 1400 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1412 -/* 1404 */ MCD_OPC_CheckPredicate, 3, 230, 0, // Skip to: 1638 -/* 1408 */ MCD_OPC_Decode, 232, 7, 49, // Opcode: LWR_MM -/* 1412 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1424 -/* 1416 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 1638 -/* 1420 */ MCD_OPC_Decode, 182, 10, 50, // Opcode: PREF_MM -/* 1424 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1436 -/* 1428 */ MCD_OPC_CheckPredicate, 3, 206, 0, // Skip to: 1638 -/* 1432 */ MCD_OPC_Decode, 196, 7, 49, // Opcode: LL_MM -/* 1436 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1448 -/* 1440 */ MCD_OPC_CheckPredicate, 3, 194, 0, // Skip to: 1638 -/* 1444 */ MCD_OPC_Decode, 245, 12, 49, // Opcode: SWL_MM -/* 1448 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1460 -/* 1452 */ MCD_OPC_CheckPredicate, 3, 182, 0, // Skip to: 1638 -/* 1456 */ MCD_OPC_Decode, 252, 12, 49, // Opcode: SWR_MM -/* 1460 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1472 -/* 1464 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 1638 -/* 1468 */ MCD_OPC_Decode, 149, 11, 49, // Opcode: SC_MM -/* 1472 */ MCD_OPC_FilterValue, 14, 162, 0, // Skip to: 1638 -/* 1476 */ MCD_OPC_CheckPredicate, 3, 158, 0, // Skip to: 1638 -/* 1480 */ MCD_OPC_Decode, 235, 7, 49, // Opcode: LWU_MM -/* 1484 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1496 -/* 1488 */ MCD_OPC_CheckPredicate, 3, 146, 0, // Skip to: 1638 -/* 1492 */ MCD_OPC_Decode, 247, 13, 53, // Opcode: XORi_MM -/* 1496 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1508 -/* 1500 */ MCD_OPC_CheckPredicate, 3, 134, 0, // Skip to: 1638 -/* 1504 */ MCD_OPC_Decode, 130, 7, 55, // Opcode: JALS_MM -/* 1508 */ MCD_OPC_FilterValue, 30, 7, 0, // Skip to: 1519 -/* 1512 */ MCD_OPC_CheckPredicate, 3, 122, 0, // Skip to: 1638 -/* 1516 */ MCD_OPC_Decode, 27, 56, // Opcode: ADDIUPC_MM -/* 1519 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 1531 -/* 1523 */ MCD_OPC_CheckPredicate, 3, 111, 0, // Skip to: 1638 -/* 1527 */ MCD_OPC_Decode, 245, 11, 47, // Opcode: SLTi_MM -/* 1531 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 1543 -/* 1535 */ MCD_OPC_CheckPredicate, 3, 99, 0, // Skip to: 1638 -/* 1539 */ MCD_OPC_Decode, 214, 1, 57, // Opcode: BEQ_MM -/* 1543 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 1555 -/* 1547 */ MCD_OPC_CheckPredicate, 3, 87, 0, // Skip to: 1638 -/* 1551 */ MCD_OPC_Decode, 248, 11, 47, // Opcode: SLTiu_MM -/* 1555 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 1567 -/* 1559 */ MCD_OPC_CheckPredicate, 3, 75, 0, // Skip to: 1638 -/* 1563 */ MCD_OPC_Decode, 161, 2, 57, // Opcode: BNE_MM -/* 1567 */ MCD_OPC_FilterValue, 52, 7, 0, // Skip to: 1578 -/* 1571 */ MCD_OPC_CheckPredicate, 3, 63, 0, // Skip to: 1638 -/* 1575 */ MCD_OPC_Decode, 95, 53, // Opcode: ANDi_MM -/* 1578 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 1590 -/* 1582 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 1638 -/* 1586 */ MCD_OPC_Decode, 144, 7, 55, // Opcode: J_MM -/* 1590 */ MCD_OPC_FilterValue, 60, 8, 0, // Skip to: 1602 -/* 1594 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 1638 -/* 1598 */ MCD_OPC_Decode, 132, 7, 55, // Opcode: JALX_MM -/* 1602 */ MCD_OPC_FilterValue, 61, 8, 0, // Skip to: 1614 -/* 1606 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 1638 -/* 1610 */ MCD_OPC_Decode, 133, 7, 55, // Opcode: JAL_MM -/* 1614 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 1626 -/* 1618 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 1638 -/* 1622 */ MCD_OPC_Decode, 128, 13, 48, // Opcode: SW_MM -/* 1626 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 1638 -/* 1630 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 1638 -/* 1634 */ MCD_OPC_Decode, 240, 7, 48, // Opcode: LW_MM -/* 1638 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 238, + 14, + 0, // Skip to: 3830 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 104, + 0, + 0, // Skip to: 120 + /* 16 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 78 + /* 24 */ MCD_OPC_ExtractField, + 11, + 15, // Inst{25-11} ... + /* 27 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 41 + /* 32 */ MCD_OPC_CheckPredicate, + 7, + 32, + 0, + 0, // Skip to: 69 + /* 37 */ MCD_OPC_Decode, + 194, + 20, + 0, // Opcode: SSNOP_MM + /* 41 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 55 + /* 46 */ MCD_OPC_CheckPredicate, + 7, + 18, + 0, + 0, // Skip to: 69 + /* 51 */ MCD_OPC_Decode, + 223, + 11, + 0, // Opcode: EHB_MM + /* 55 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 69 + /* 60 */ MCD_OPC_CheckPredicate, + 7, + 4, + 0, + 0, // Skip to: 69 + /* 65 */ MCD_OPC_Decode, + 236, + 17, + 0, // Opcode: PAUSE_MM + /* 69 */ MCD_OPC_CheckPredicate, + 7, + 42, + 25, + 0, // Skip to: 6516 + /* 74 */ MCD_OPC_Decode, + 254, + 19, + 41, // Opcode: SLL_MM + /* 78 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 92 + /* 83 */ MCD_OPC_CheckPredicate, + 7, + 28, + 25, + 0, // Skip to: 6516 + /* 88 */ MCD_OPC_Decode, + 191, + 20, + 41, // Opcode: SRL_MM + /* 92 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 106 + /* 97 */ MCD_OPC_CheckPredicate, + 7, + 14, + 25, + 0, // Skip to: 6516 + /* 102 */ MCD_OPC_Decode, + 169, + 20, + 41, // Opcode: SRA_MM + /* 106 */ MCD_OPC_FilterValue, + 3, + 5, + 25, + 0, // Skip to: 6516 + /* 111 */ MCD_OPC_CheckPredicate, + 7, + 0, + 25, + 0, // Skip to: 6516 + /* 116 */ MCD_OPC_Decode, + 204, + 18, + 41, // Opcode: ROTR_MM + /* 120 */ MCD_OPC_FilterValue, + 5, + 227, + 0, + 0, // Skip to: 352 + /* 125 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 128 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 149 + /* 133 */ MCD_OPC_CheckPredicate, + 8, + 234, + 24, + 0, // Skip to: 6516 + /* 138 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 227, + 24, + 0, // Skip to: 6516 + /* 145 */ MCD_OPC_Decode, + 249, + 8, + 42, // Opcode: CMP_EQ_PH_MM + /* 149 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 170 + /* 154 */ MCD_OPC_CheckPredicate, + 8, + 213, + 24, + 0, // Skip to: 6516 + /* 159 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 206, + 24, + 0, // Skip to: 6516 + /* 166 */ MCD_OPC_Decode, + 135, + 9, + 42, // Opcode: CMP_LT_PH_MM + /* 170 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 191 + /* 175 */ MCD_OPC_CheckPredicate, + 8, + 192, + 24, + 0, // Skip to: 6516 + /* 180 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 185, + 24, + 0, // Skip to: 6516 + /* 187 */ MCD_OPC_Decode, + 129, + 9, + 42, // Opcode: CMP_LE_PH_MM + /* 191 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 205 + /* 196 */ MCD_OPC_CheckPredicate, + 9, + 171, + 24, + 0, // Skip to: 6516 + /* 201 */ MCD_OPC_Decode, + 227, + 8, + 43, // Opcode: CMPGDU_EQ_QB_MMR2 + /* 205 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 219 + /* 210 */ MCD_OPC_CheckPredicate, + 9, + 157, + 24, + 0, // Skip to: 6516 + /* 215 */ MCD_OPC_Decode, + 231, + 8, + 43, // Opcode: CMPGDU_LT_QB_MMR2 + /* 219 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 233 + /* 224 */ MCD_OPC_CheckPredicate, + 9, + 143, + 24, + 0, // Skip to: 6516 + /* 229 */ MCD_OPC_Decode, + 229, + 8, + 43, // Opcode: CMPGDU_LE_QB_MMR2 + /* 233 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 254 + /* 238 */ MCD_OPC_CheckPredicate, + 8, + 129, + 24, + 0, // Skip to: 6516 + /* 243 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 122, + 24, + 0, // Skip to: 6516 + /* 250 */ MCD_OPC_Decode, + 239, + 8, + 42, // Opcode: CMPU_EQ_QB_MM + /* 254 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 275 + /* 259 */ MCD_OPC_CheckPredicate, + 8, + 108, + 24, + 0, // Skip to: 6516 + /* 264 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 101, + 24, + 0, // Skip to: 6516 + /* 271 */ MCD_OPC_Decode, + 243, + 8, + 42, // Opcode: CMPU_LT_QB_MM + /* 275 */ MCD_OPC_FilterValue, + 11, + 16, + 0, + 0, // Skip to: 296 + /* 280 */ MCD_OPC_CheckPredicate, + 8, + 87, + 24, + 0, // Skip to: 6516 + /* 285 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 80, + 24, + 0, // Skip to: 6516 + /* 292 */ MCD_OPC_Decode, + 241, + 8, + 42, // Opcode: CMPU_LE_QB_MM + /* 296 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 310 + /* 301 */ MCD_OPC_CheckPredicate, + 8, + 66, + 24, + 0, // Skip to: 6516 + /* 306 */ MCD_OPC_Decode, + 216, + 5, + 44, // Opcode: ADDQ_S_W_MM + /* 310 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 324 + /* 315 */ MCD_OPC_CheckPredicate, + 8, + 52, + 24, + 0, // Skip to: 6516 + /* 320 */ MCD_OPC_Decode, + 214, + 20, + 44, // Opcode: SUBQ_S_W_MM + /* 324 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 338 + /* 329 */ MCD_OPC_CheckPredicate, + 8, + 38, + 24, + 0, // Skip to: 6516 + /* 334 */ MCD_OPC_Decode, + 219, + 5, + 44, // Opcode: ADDSC_MM + /* 338 */ MCD_OPC_FilterValue, + 15, + 29, + 24, + 0, // Skip to: 6516 + /* 343 */ MCD_OPC_CheckPredicate, + 8, + 24, + 24, + 0, // Skip to: 6516 + /* 348 */ MCD_OPC_Decode, + 128, + 6, + 44, // Opcode: ADDWC_MM + /* 352 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 366 + /* 357 */ MCD_OPC_CheckPredicate, + 7, + 10, + 24, + 0, // Skip to: 6516 + /* 362 */ MCD_OPC_Decode, + 249, + 7, + 45, // Opcode: BREAK_MM + /* 366 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 380 + /* 371 */ MCD_OPC_CheckPredicate, + 6, + 252, + 23, + 0, // Skip to: 6516 + /* 376 */ MCD_OPC_Decode, + 236, + 13, + 46, // Opcode: INS_MM + /* 380 */ MCD_OPC_FilterValue, + 13, + 167, + 1, + 0, // Skip to: 808 + /* 385 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 388 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 402 + /* 393 */ MCD_OPC_CheckPredicate, + 8, + 230, + 23, + 0, // Skip to: 6516 + /* 398 */ MCD_OPC_Decode, + 212, + 5, + 47, // Opcode: ADDQ_PH_MM + /* 402 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 416 + /* 407 */ MCD_OPC_CheckPredicate, + 9, + 216, + 23, + 0, // Skip to: 6516 + /* 412 */ MCD_OPC_Decode, + 204, + 5, + 47, // Opcode: ADDQH_PH_MMR2 + /* 416 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 430 + /* 421 */ MCD_OPC_CheckPredicate, + 9, + 202, + 23, + 0, // Skip to: 6516 + /* 426 */ MCD_OPC_Decode, + 210, + 5, + 44, // Opcode: ADDQH_W_MMR2 + /* 430 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 444 + /* 435 */ MCD_OPC_CheckPredicate, + 8, + 188, + 23, + 0, // Skip to: 6516 + /* 440 */ MCD_OPC_Decode, + 242, + 5, + 47, // Opcode: ADDU_QB_MM + /* 444 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 458 + /* 449 */ MCD_OPC_CheckPredicate, + 9, + 174, + 23, + 0, // Skip to: 6516 + /* 454 */ MCD_OPC_Decode, + 240, + 5, + 47, // Opcode: ADDU_PH_MMR2 + /* 458 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 472 + /* 463 */ MCD_OPC_CheckPredicate, + 9, + 160, + 23, + 0, // Skip to: 6516 + /* 468 */ MCD_OPC_Decode, + 235, + 5, + 47, // Opcode: ADDUH_QB_MMR2 + /* 472 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 486 + /* 477 */ MCD_OPC_CheckPredicate, + 8, + 146, + 23, + 0, // Skip to: 6516 + /* 482 */ MCD_OPC_Decode, + 201, + 19, + 48, // Opcode: SHRAV_PH_MM + /* 486 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 500 + /* 491 */ MCD_OPC_CheckPredicate, + 9, + 132, + 23, + 0, // Skip to: 6516 + /* 496 */ MCD_OPC_Decode, + 203, + 19, + 48, // Opcode: SHRAV_QB_MMR2 + /* 500 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 514 + /* 505 */ MCD_OPC_CheckPredicate, + 8, + 118, + 23, + 0, // Skip to: 6516 + /* 510 */ MCD_OPC_Decode, + 210, + 20, + 47, // Opcode: SUBQ_PH_MM + /* 514 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 528 + /* 519 */ MCD_OPC_CheckPredicate, + 9, + 104, + 23, + 0, // Skip to: 6516 + /* 524 */ MCD_OPC_Decode, + 202, + 20, + 47, // Opcode: SUBQH_PH_MMR2 + /* 528 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 542 + /* 533 */ MCD_OPC_CheckPredicate, + 9, + 90, + 23, + 0, // Skip to: 6516 + /* 538 */ MCD_OPC_Decode, + 208, + 20, + 44, // Opcode: SUBQH_W_MMR2 + /* 542 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 556 + /* 547 */ MCD_OPC_CheckPredicate, + 8, + 76, + 23, + 0, // Skip to: 6516 + /* 552 */ MCD_OPC_Decode, + 241, + 20, + 47, // Opcode: SUBU_QB_MM + /* 556 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 570 + /* 561 */ MCD_OPC_CheckPredicate, + 9, + 62, + 23, + 0, // Skip to: 6516 + /* 566 */ MCD_OPC_Decode, + 239, + 20, + 47, // Opcode: SUBU_PH_MMR2 + /* 570 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 584 + /* 575 */ MCD_OPC_CheckPredicate, + 9, + 48, + 23, + 0, // Skip to: 6516 + /* 580 */ MCD_OPC_Decode, + 234, + 20, + 47, // Opcode: SUBUH_QB_MMR2 + /* 584 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 598 + /* 589 */ MCD_OPC_CheckPredicate, + 9, + 34, + 23, + 0, // Skip to: 6516 + /* 594 */ MCD_OPC_Decode, + 160, + 18, + 49, // Opcode: PRECR_SRA_PH_W_MMR2 + /* 598 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 612 + /* 603 */ MCD_OPC_CheckPredicate, + 8, + 20, + 23, + 0, // Skip to: 6516 + /* 608 */ MCD_OPC_Decode, + 214, + 5, + 47, // Opcode: ADDQ_S_PH_MM + /* 612 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 626 + /* 617 */ MCD_OPC_CheckPredicate, + 9, + 6, + 23, + 0, // Skip to: 6516 + /* 622 */ MCD_OPC_Decode, + 206, + 5, + 47, // Opcode: ADDQH_R_PH_MMR2 + /* 626 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 640 + /* 631 */ MCD_OPC_CheckPredicate, + 9, + 248, + 22, + 0, // Skip to: 6516 + /* 636 */ MCD_OPC_Decode, + 208, + 5, + 44, // Opcode: ADDQH_R_W_MMR2 + /* 640 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 654 + /* 645 */ MCD_OPC_CheckPredicate, + 8, + 234, + 22, + 0, // Skip to: 6516 + /* 650 */ MCD_OPC_Decode, + 246, + 5, + 47, // Opcode: ADDU_S_QB_MM + /* 654 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 668 + /* 659 */ MCD_OPC_CheckPredicate, + 9, + 220, + 22, + 0, // Skip to: 6516 + /* 664 */ MCD_OPC_Decode, + 244, + 5, + 47, // Opcode: ADDU_S_PH_MMR2 + /* 668 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 682 + /* 673 */ MCD_OPC_CheckPredicate, + 9, + 206, + 22, + 0, // Skip to: 6516 + /* 678 */ MCD_OPC_Decode, + 237, + 5, + 47, // Opcode: ADDUH_R_QB_MMR2 + /* 682 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 696 + /* 687 */ MCD_OPC_CheckPredicate, + 8, + 192, + 22, + 0, // Skip to: 6516 + /* 692 */ MCD_OPC_Decode, + 205, + 19, + 48, // Opcode: SHRAV_R_PH_MM + /* 696 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 710 + /* 701 */ MCD_OPC_CheckPredicate, + 9, + 178, + 22, + 0, // Skip to: 6516 + /* 706 */ MCD_OPC_Decode, + 207, + 19, + 48, // Opcode: SHRAV_R_QB_MMR2 + /* 710 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 724 + /* 715 */ MCD_OPC_CheckPredicate, + 8, + 164, + 22, + 0, // Skip to: 6516 + /* 720 */ MCD_OPC_Decode, + 212, + 20, + 47, // Opcode: SUBQ_S_PH_MM + /* 724 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 738 + /* 729 */ MCD_OPC_CheckPredicate, + 9, + 150, + 22, + 0, // Skip to: 6516 + /* 734 */ MCD_OPC_Decode, + 204, + 20, + 47, // Opcode: SUBQH_R_PH_MMR2 + /* 738 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 752 + /* 743 */ MCD_OPC_CheckPredicate, + 9, + 136, + 22, + 0, // Skip to: 6516 + /* 748 */ MCD_OPC_Decode, + 206, + 20, + 44, // Opcode: SUBQH_R_W_MMR2 + /* 752 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 766 + /* 757 */ MCD_OPC_CheckPredicate, + 8, + 122, + 22, + 0, // Skip to: 6516 + /* 762 */ MCD_OPC_Decode, + 245, + 20, + 47, // Opcode: SUBU_S_QB_MM + /* 766 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 780 + /* 771 */ MCD_OPC_CheckPredicate, + 9, + 108, + 22, + 0, // Skip to: 6516 + /* 776 */ MCD_OPC_Decode, + 243, + 20, + 47, // Opcode: SUBU_S_PH_MMR2 + /* 780 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 794 + /* 785 */ MCD_OPC_CheckPredicate, + 9, + 94, + 22, + 0, // Skip to: 6516 + /* 790 */ MCD_OPC_Decode, + 236, + 20, + 47, // Opcode: SUBUH_R_QB_MMR2 + /* 794 */ MCD_OPC_FilterValue, + 31, + 85, + 22, + 0, // Skip to: 6516 + /* 799 */ MCD_OPC_CheckPredicate, + 9, + 80, + 22, + 0, // Skip to: 6516 + /* 804 */ MCD_OPC_Decode, + 162, + 18, + 49, // Opcode: PRECR_SRA_R_PH_W_MMR2 + /* 808 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 844 + /* 813 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 816 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 830 + /* 821 */ MCD_OPC_CheckPredicate, + 8, + 58, + 22, + 0, // Skip to: 6516 + /* 826 */ MCD_OPC_Decode, + 185, + 19, + 48, // Opcode: SHLLV_PH_MM + /* 830 */ MCD_OPC_FilterValue, + 16, + 49, + 22, + 0, // Skip to: 6516 + /* 835 */ MCD_OPC_CheckPredicate, + 8, + 44, + 22, + 0, // Skip to: 6516 + /* 840 */ MCD_OPC_Decode, + 189, + 19, + 48, // Opcode: SHLLV_S_PH_MM + /* 844 */ MCD_OPC_FilterValue, + 16, + 213, + 0, + 0, // Skip to: 1062 + /* 849 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 852 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 866 + /* 857 */ MCD_OPC_CheckPredicate, + 7, + 22, + 22, + 0, // Skip to: 6516 + /* 862 */ MCD_OPC_Decode, + 250, + 19, + 50, // Opcode: SLLV_MM + /* 866 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 880 + /* 871 */ MCD_OPC_CheckPredicate, + 7, + 8, + 22, + 0, // Skip to: 6516 + /* 876 */ MCD_OPC_Decode, + 187, + 20, + 50, // Opcode: SRLV_MM + /* 880 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 894 + /* 885 */ MCD_OPC_CheckPredicate, + 7, + 250, + 21, + 0, // Skip to: 6516 + /* 890 */ MCD_OPC_Decode, + 165, + 20, + 50, // Opcode: SRAV_MM + /* 894 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 908 + /* 899 */ MCD_OPC_CheckPredicate, + 7, + 236, + 21, + 0, // Skip to: 6516 + /* 904 */ MCD_OPC_Decode, + 203, + 18, + 50, // Opcode: ROTRV_MM + /* 908 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 922 + /* 913 */ MCD_OPC_CheckPredicate, + 6, + 222, + 21, + 0, // Skip to: 6516 + /* 918 */ MCD_OPC_Decode, + 133, + 6, + 44, // Opcode: ADD_MM + /* 922 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 936 + /* 927 */ MCD_OPC_CheckPredicate, + 6, + 208, + 21, + 0, // Skip to: 6516 + /* 932 */ MCD_OPC_Decode, + 140, + 6, + 44, // Opcode: ADDu_MM + /* 936 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 950 + /* 941 */ MCD_OPC_CheckPredicate, + 6, + 194, + 21, + 0, // Skip to: 6516 + /* 946 */ MCD_OPC_Decode, + 254, + 20, + 44, // Opcode: SUB_MM + /* 950 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 964 + /* 955 */ MCD_OPC_CheckPredicate, + 6, + 180, + 21, + 0, // Skip to: 6516 + /* 960 */ MCD_OPC_Decode, + 129, + 21, + 44, // Opcode: SUBu_MM + /* 964 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 978 + /* 969 */ MCD_OPC_CheckPredicate, + 6, + 166, + 21, + 0, // Skip to: 6516 + /* 974 */ MCD_OPC_Decode, + 179, + 17, + 44, // Opcode: MUL_MM + /* 978 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 992 + /* 983 */ MCD_OPC_CheckPredicate, + 6, + 152, + 21, + 0, // Skip to: 6516 + /* 988 */ MCD_OPC_Decode, + 153, + 6, + 44, // Opcode: AND_MM + /* 992 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 1006 + /* 997 */ MCD_OPC_CheckPredicate, + 6, + 138, + 21, + 0, // Skip to: 6516 + /* 1002 */ MCD_OPC_Decode, + 226, + 17, + 44, // Opcode: OR_MM + /* 1006 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 1020 + /* 1011 */ MCD_OPC_CheckPredicate, + 6, + 124, + 21, + 0, // Skip to: 6516 + /* 1016 */ MCD_OPC_Decode, + 213, + 17, + 44, // Opcode: NOR_MM + /* 1020 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 1034 + /* 1025 */ MCD_OPC_CheckPredicate, + 6, + 110, + 21, + 0, // Skip to: 6516 + /* 1030 */ MCD_OPC_Decode, + 151, + 22, + 44, // Opcode: XOR_MM + /* 1034 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 1048 + /* 1039 */ MCD_OPC_CheckPredicate, + 7, + 96, + 21, + 0, // Skip to: 6516 + /* 1044 */ MCD_OPC_Decode, + 131, + 20, + 44, // Opcode: SLT_MM + /* 1048 */ MCD_OPC_FilterValue, + 14, + 87, + 21, + 0, // Skip to: 6516 + /* 1053 */ MCD_OPC_CheckPredicate, + 7, + 82, + 21, + 0, // Skip to: 6516 + /* 1058 */ MCD_OPC_Decode, + 140, + 20, + 44, // Opcode: SLTu_MM + /* 1062 */ MCD_OPC_FilterValue, + 21, + 199, + 0, + 0, // Skip to: 1266 + /* 1067 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1070 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 1084 + /* 1075 */ MCD_OPC_CheckPredicate, + 8, + 60, + 21, + 0, // Skip to: 6516 + /* 1080 */ MCD_OPC_Decode, + 147, + 17, + 47, // Opcode: MULEU_S_PH_QBL_MM + /* 1084 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 1098 + /* 1089 */ MCD_OPC_CheckPredicate, + 8, + 46, + 21, + 0, // Skip to: 6516 + /* 1094 */ MCD_OPC_Decode, + 149, + 17, + 47, // Opcode: MULEU_S_PH_QBR_MM + /* 1098 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1112 + /* 1103 */ MCD_OPC_CheckPredicate, + 8, + 32, + 21, + 0, // Skip to: 6516 + /* 1108 */ MCD_OPC_Decode, + 151, + 17, + 47, // Opcode: MULQ_RS_PH_MM + /* 1112 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 1126 + /* 1117 */ MCD_OPC_CheckPredicate, + 9, + 18, + 21, + 0, // Skip to: 6516 + /* 1122 */ MCD_OPC_Decode, + 155, + 17, + 47, // Opcode: MULQ_S_PH_MMR2 + /* 1126 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1140 + /* 1131 */ MCD_OPC_CheckPredicate, + 9, + 4, + 21, + 0, // Skip to: 6516 + /* 1136 */ MCD_OPC_Decode, + 153, + 17, + 44, // Opcode: MULQ_RS_W_MMR2 + /* 1140 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 1154 + /* 1145 */ MCD_OPC_CheckPredicate, + 9, + 246, + 20, + 0, // Skip to: 6516 + /* 1150 */ MCD_OPC_Decode, + 157, + 17, + 44, // Opcode: MULQ_S_W_MMR2 + /* 1154 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 1168 + /* 1159 */ MCD_OPC_CheckPredicate, + 9, + 232, + 20, + 0, // Skip to: 6516 + /* 1164 */ MCD_OPC_Decode, + 160, + 6, + 51, // Opcode: APPEND_MMR2 + /* 1168 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 1182 + /* 1173 */ MCD_OPC_CheckPredicate, + 9, + 218, + 20, + 0, // Skip to: 6516 + /* 1178 */ MCD_OPC_Decode, + 171, + 18, + 51, // Opcode: PREPEND_MMR2 + /* 1182 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 1196 + /* 1187 */ MCD_OPC_CheckPredicate, + 8, + 204, + 20, + 0, // Skip to: 6516 + /* 1192 */ MCD_OPC_Decode, + 145, + 16, + 44, // Opcode: MODSUB_MM + /* 1196 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 1210 + /* 1201 */ MCD_OPC_CheckPredicate, + 8, + 190, + 20, + 0, // Skip to: 6516 + /* 1206 */ MCD_OPC_Decode, + 209, + 19, + 50, // Opcode: SHRAV_R_W_MM + /* 1210 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 1224 + /* 1215 */ MCD_OPC_CheckPredicate, + 9, + 176, + 20, + 0, // Skip to: 6516 + /* 1220 */ MCD_OPC_Decode, + 221, + 19, + 48, // Opcode: SHRLV_PH_MMR2 + /* 1224 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 1238 + /* 1229 */ MCD_OPC_CheckPredicate, + 8, + 162, + 20, + 0, // Skip to: 6516 + /* 1234 */ MCD_OPC_Decode, + 223, + 19, + 48, // Opcode: SHRLV_QB_MM + /* 1238 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 1252 + /* 1243 */ MCD_OPC_CheckPredicate, + 8, + 148, + 20, + 0, // Skip to: 6516 + /* 1248 */ MCD_OPC_Decode, + 187, + 19, + 48, // Opcode: SHLLV_QB_MM + /* 1252 */ MCD_OPC_FilterValue, + 15, + 139, + 20, + 0, // Skip to: 6516 + /* 1257 */ MCD_OPC_CheckPredicate, + 8, + 134, + 20, + 0, // Skip to: 6516 + /* 1262 */ MCD_OPC_Decode, + 191, + 19, + 50, // Opcode: SHLLV_S_W_MM + /* 1266 */ MCD_OPC_FilterValue, + 24, + 45, + 0, + 0, // Skip to: 1316 + /* 1271 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1274 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1288 + /* 1279 */ MCD_OPC_CheckPredicate, + 6, + 112, + 20, + 0, // Skip to: 6516 + /* 1284 */ MCD_OPC_Decode, + 179, + 16, + 52, // Opcode: MOVN_I_MM + /* 1288 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1302 + /* 1293 */ MCD_OPC_CheckPredicate, + 6, + 98, + 20, + 0, // Skip to: 6516 + /* 1298 */ MCD_OPC_Decode, + 199, + 16, + 52, // Opcode: MOVZ_I_MM + /* 1302 */ MCD_OPC_FilterValue, + 4, + 89, + 20, + 0, // Skip to: 6516 + /* 1307 */ MCD_OPC_CheckPredicate, + 7, + 84, + 20, + 0, // Skip to: 6516 + /* 1312 */ MCD_OPC_Decode, + 135, + 15, + 53, // Opcode: LWXS_MM + /* 1316 */ MCD_OPC_FilterValue, + 29, + 23, + 0, + 0, // Skip to: 1344 + /* 1321 */ MCD_OPC_CheckPredicate, + 8, + 70, + 20, + 0, // Skip to: 6516 + /* 1326 */ MCD_OPC_CheckField, + 22, + 4, + 0, + 63, + 20, + 0, // Skip to: 6516 + /* 1333 */ MCD_OPC_CheckField, + 6, + 8, + 0, + 56, + 20, + 0, // Skip to: 6516 + /* 1340 */ MCD_OPC_Decode, + 183, + 19, + 54, // Opcode: SHILO_MM + /* 1344 */ MCD_OPC_FilterValue, + 37, + 73, + 0, + 0, // Skip to: 1422 + /* 1349 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1352 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1366 + /* 1357 */ MCD_OPC_CheckPredicate, + 8, + 34, + 20, + 0, // Skip to: 6516 + /* 1362 */ MCD_OPC_Decode, + 143, + 17, + 43, // Opcode: MULEQ_S_W_PHL_MM + /* 1366 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1380 + /* 1371 */ MCD_OPC_CheckPredicate, + 8, + 20, + 20, + 0, // Skip to: 6516 + /* 1376 */ MCD_OPC_Decode, + 145, + 17, + 43, // Opcode: MULEQ_S_W_PHR_MM + /* 1380 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 1394 + /* 1385 */ MCD_OPC_CheckPredicate, + 8, + 6, + 20, + 0, // Skip to: 6516 + /* 1390 */ MCD_OPC_Decode, + 198, + 14, + 53, // Opcode: LHX_MM + /* 1394 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1408 + /* 1399 */ MCD_OPC_CheckPredicate, + 8, + 248, + 19, + 0, // Skip to: 6516 + /* 1404 */ MCD_OPC_Decode, + 136, + 15, + 53, // Opcode: LWX_MM + /* 1408 */ MCD_OPC_FilterValue, + 8, + 239, + 19, + 0, // Skip to: 6516 + /* 1413 */ MCD_OPC_CheckPredicate, + 8, + 234, + 19, + 0, // Skip to: 6516 + /* 1418 */ MCD_OPC_Decode, + 158, + 14, + 53, // Opcode: LBUX_MM + /* 1422 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 1436 + /* 1427 */ MCD_OPC_CheckPredicate, + 6, + 220, + 19, + 0, // Skip to: 6516 + /* 1432 */ MCD_OPC_Decode, + 136, + 12, + 55, // Opcode: EXT_MM + /* 1436 */ MCD_OPC_FilterValue, + 45, + 143, + 0, + 0, // Skip to: 1584 + /* 1441 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1444 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1458 + /* 1449 */ MCD_OPC_CheckPredicate, + 9, + 198, + 19, + 0, // Skip to: 6516 + /* 1454 */ MCD_OPC_Decode, + 182, + 17, + 47, // Opcode: MUL_PH_MMR2 + /* 1458 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1472 + /* 1463 */ MCD_OPC_CheckPredicate, + 9, + 184, + 19, + 0, // Skip to: 6516 + /* 1468 */ MCD_OPC_Decode, + 158, + 18, + 47, // Opcode: PRECR_QB_PH_MMR2 + /* 1472 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 1486 + /* 1477 */ MCD_OPC_CheckPredicate, + 8, + 170, + 19, + 0, // Skip to: 6516 + /* 1482 */ MCD_OPC_Decode, + 154, + 18, + 47, // Opcode: PRECRQ_QB_PH_MM + /* 1486 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 1500 + /* 1491 */ MCD_OPC_CheckPredicate, + 8, + 156, + 19, + 0, // Skip to: 6516 + /* 1496 */ MCD_OPC_Decode, + 152, + 18, + 56, // Opcode: PRECRQ_PH_W_MM + /* 1500 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1514 + /* 1505 */ MCD_OPC_CheckPredicate, + 8, + 142, + 19, + 0, // Skip to: 6516 + /* 1510 */ MCD_OPC_Decode, + 156, + 18, + 56, // Opcode: PRECRQ_RS_PH_W_MM + /* 1514 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 1528 + /* 1519 */ MCD_OPC_CheckPredicate, + 8, + 128, + 19, + 0, // Skip to: 6516 + /* 1524 */ MCD_OPC_Decode, + 150, + 18, + 47, // Opcode: PRECRQU_S_QB_PH_MM + /* 1528 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1542 + /* 1533 */ MCD_OPC_CheckPredicate, + 8, + 114, + 19, + 0, // Skip to: 6516 + /* 1538 */ MCD_OPC_Decode, + 234, + 17, + 47, // Opcode: PACKRL_PH_MM + /* 1542 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 1556 + /* 1547 */ MCD_OPC_CheckPredicate, + 8, + 100, + 19, + 0, // Skip to: 6516 + /* 1552 */ MCD_OPC_Decode, + 253, + 17, + 47, // Opcode: PICK_QB_MM + /* 1556 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 1570 + /* 1561 */ MCD_OPC_CheckPredicate, + 8, + 86, + 19, + 0, // Skip to: 6516 + /* 1566 */ MCD_OPC_Decode, + 251, + 17, + 47, // Opcode: PICK_PH_MM + /* 1570 */ MCD_OPC_FilterValue, + 16, + 77, + 19, + 0, // Skip to: 6516 + /* 1575 */ MCD_OPC_CheckPredicate, + 9, + 72, + 19, + 0, // Skip to: 6516 + /* 1580 */ MCD_OPC_Decode, + 187, + 17, + 47, // Opcode: MUL_S_PH_MMR2 + /* 1584 */ MCD_OPC_FilterValue, + 52, + 45, + 0, + 0, // Skip to: 1634 + /* 1589 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1592 */ MCD_OPC_FilterValue, + 19, + 16, + 0, + 0, // Skip to: 1613 + /* 1597 */ MCD_OPC_CheckPredicate, + 10, + 50, + 19, + 0, // Skip to: 6516 + /* 1602 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 43, + 19, + 0, // Skip to: 6516 + /* 1609 */ MCD_OPC_Decode, + 229, + 15, + 57, // Opcode: MFHGC0_MM + /* 1613 */ MCD_OPC_FilterValue, + 27, + 34, + 19, + 0, // Skip to: 6516 + /* 1618 */ MCD_OPC_CheckPredicate, + 10, + 29, + 19, + 0, // Skip to: 6516 + /* 1623 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 22, + 19, + 0, // Skip to: 6516 + /* 1630 */ MCD_OPC_Decode, + 245, + 16, + 58, // Opcode: MTHGC0_MM + /* 1634 */ MCD_OPC_FilterValue, + 53, + 109, + 0, + 0, // Skip to: 1748 + /* 1639 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1642 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 1656 + /* 1647 */ MCD_OPC_CheckPredicate, + 8, + 0, + 19, + 0, // Skip to: 6516 + /* 1652 */ MCD_OPC_Decode, + 219, + 19, + 41, // Opcode: SHRA_R_W_MM + /* 1656 */ MCD_OPC_FilterValue, + 12, + 16, + 0, + 0, // Skip to: 1677 + /* 1661 */ MCD_OPC_CheckPredicate, + 8, + 242, + 18, + 0, // Skip to: 6516 + /* 1666 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 235, + 18, + 0, // Skip to: 6516 + /* 1673 */ MCD_OPC_Decode, + 211, + 19, + 59, // Opcode: SHRA_PH_MM + /* 1677 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 1713 + /* 1682 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 1685 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1699 + /* 1690 */ MCD_OPC_CheckPredicate, + 8, + 213, + 18, + 0, // Skip to: 6516 + /* 1695 */ MCD_OPC_Decode, + 193, + 19, + 59, // Opcode: SHLL_PH_MM + /* 1699 */ MCD_OPC_FilterValue, + 1, + 204, + 18, + 0, // Skip to: 6516 + /* 1704 */ MCD_OPC_CheckPredicate, + 8, + 199, + 18, + 0, // Skip to: 6516 + /* 1709 */ MCD_OPC_Decode, + 197, + 19, + 59, // Opcode: SHLL_S_PH_MM + /* 1713 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 1727 + /* 1718 */ MCD_OPC_CheckPredicate, + 8, + 185, + 18, + 0, // Skip to: 6516 + /* 1723 */ MCD_OPC_Decode, + 199, + 19, + 41, // Opcode: SHLL_S_W_MM + /* 1727 */ MCD_OPC_FilterValue, + 28, + 176, + 18, + 0, // Skip to: 6516 + /* 1732 */ MCD_OPC_CheckPredicate, + 8, + 171, + 18, + 0, // Skip to: 6516 + /* 1737 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 164, + 18, + 0, // Skip to: 6516 + /* 1744 */ MCD_OPC_Decode, + 215, + 19, + 59, // Opcode: SHRA_R_PH_MM + /* 1748 */ MCD_OPC_FilterValue, + 60, + 8, + 8, + 0, // Skip to: 3809 + /* 1753 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1756 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 1792 + /* 1761 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 1764 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1778 + /* 1769 */ MCD_OPC_CheckPredicate, + 7, + 134, + 18, + 0, // Skip to: 6516 + /* 1774 */ MCD_OPC_Decode, + 199, + 21, + 60, // Opcode: TEQ_MM + /* 1778 */ MCD_OPC_FilterValue, + 1, + 125, + 18, + 0, // Skip to: 6516 + /* 1783 */ MCD_OPC_CheckPredicate, + 7, + 120, + 18, + 0, // Skip to: 6516 + /* 1788 */ MCD_OPC_Decode, + 238, + 21, + 60, // Opcode: TLT_MM + /* 1792 */ MCD_OPC_FilterValue, + 1, + 131, + 0, + 0, // Skip to: 1928 + /* 1797 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 1800 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 1850 + /* 1805 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1808 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1829 + /* 1813 */ MCD_OPC_CheckPredicate, + 8, + 90, + 18, + 0, // Skip to: 6516 + /* 1818 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 83, + 18, + 0, // Skip to: 6516 + /* 1825 */ MCD_OPC_Decode, + 234, + 15, + 61, // Opcode: MFHI_DSP_MM + /* 1829 */ MCD_OPC_FilterValue, + 1, + 74, + 18, + 0, // Skip to: 6516 + /* 1834 */ MCD_OPC_CheckPredicate, + 8, + 69, + 18, + 0, // Skip to: 6516 + /* 1839 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 62, + 18, + 0, // Skip to: 6516 + /* 1846 */ MCD_OPC_Decode, + 249, + 16, + 62, // Opcode: MTHI_DSP_MM + /* 1850 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1864 + /* 1855 */ MCD_OPC_CheckPredicate, + 8, + 48, + 18, + 0, // Skip to: 6516 + /* 1860 */ MCD_OPC_Decode, + 195, + 19, + 63, // Opcode: SHLL_QB_MM + /* 1864 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 1914 + /* 1869 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1872 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1893 + /* 1877 */ MCD_OPC_CheckPredicate, + 8, + 26, + 18, + 0, // Skip to: 6516 + /* 1882 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 19, + 18, + 0, // Skip to: 6516 + /* 1889 */ MCD_OPC_Decode, + 240, + 15, + 61, // Opcode: MFLO_DSP_MM + /* 1893 */ MCD_OPC_FilterValue, + 1, + 10, + 18, + 0, // Skip to: 6516 + /* 1898 */ MCD_OPC_CheckPredicate, + 8, + 5, + 18, + 0, // Skip to: 6516 + /* 1903 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 254, + 17, + 0, // Skip to: 6516 + /* 1910 */ MCD_OPC_Decode, + 128, + 17, + 64, // Opcode: MTLO_DSP_MM + /* 1914 */ MCD_OPC_FilterValue, + 3, + 245, + 17, + 0, // Skip to: 6516 + /* 1919 */ MCD_OPC_CheckPredicate, + 8, + 240, + 17, + 0, // Skip to: 6516 + /* 1924 */ MCD_OPC_Decode, + 227, + 19, + 63, // Opcode: SHRL_QB_MM + /* 1928 */ MCD_OPC_FilterValue, + 2, + 101, + 0, + 0, // Skip to: 2034 + /* 1933 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 1936 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1950 + /* 1941 */ MCD_OPC_CheckPredicate, + 9, + 218, + 17, + 0, // Skip to: 6516 + /* 1946 */ MCD_OPC_Decode, + 174, + 11, + 65, // Opcode: DPA_W_PH_MMR2 + /* 1950 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1964 + /* 1955 */ MCD_OPC_CheckPredicate, + 9, + 204, + 17, + 0, // Skip to: 6516 + /* 1960 */ MCD_OPC_Decode, + 204, + 6, + 66, // Opcode: BALIGN_MMR2 + /* 1964 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 1978 + /* 1969 */ MCD_OPC_CheckPredicate, + 9, + 190, + 17, + 0, // Skip to: 6516 + /* 1974 */ MCD_OPC_Decode, + 172, + 11, + 65, // Opcode: DPAX_W_PH_MMR2 + /* 1978 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1992 + /* 1983 */ MCD_OPC_CheckPredicate, + 8, + 176, + 17, + 0, // Skip to: 6516 + /* 1988 */ MCD_OPC_Decode, + 168, + 11, + 65, // Opcode: DPAU_H_QBL_MM + /* 1992 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2006 + /* 1997 */ MCD_OPC_CheckPredicate, + 8, + 162, + 17, + 0, // Skip to: 6516 + /* 2002 */ MCD_OPC_Decode, + 244, + 11, + 67, // Opcode: EXTPV_MM + /* 2006 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 2020 + /* 2011 */ MCD_OPC_CheckPredicate, + 8, + 148, + 17, + 0, // Skip to: 6516 + /* 2016 */ MCD_OPC_Decode, + 170, + 11, + 65, // Opcode: DPAU_H_QBR_MM + /* 2020 */ MCD_OPC_FilterValue, + 7, + 139, + 17, + 0, // Skip to: 6516 + /* 2025 */ MCD_OPC_CheckPredicate, + 8, + 134, + 17, + 0, // Skip to: 6516 + /* 2030 */ MCD_OPC_Decode, + 241, + 11, + 67, // Opcode: EXTPDPV_MM + /* 2034 */ MCD_OPC_FilterValue, + 4, + 171, + 0, + 0, // Skip to: 2210 + /* 2039 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 2042 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2056 + /* 2047 */ MCD_OPC_CheckPredicate, + 9, + 112, + 17, + 0, // Skip to: 6516 + /* 2052 */ MCD_OPC_Decode, + 191, + 5, + 68, // Opcode: ABSQ_S_QB_MMR2 + /* 2056 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2070 + /* 2061 */ MCD_OPC_CheckPredicate, + 8, + 98, + 17, + 0, // Skip to: 6516 + /* 2066 */ MCD_OPC_Decode, + 189, + 5, + 68, // Opcode: ABSQ_S_PH_MM + /* 2070 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 2084 + /* 2075 */ MCD_OPC_CheckPredicate, + 8, + 84, + 17, + 0, // Skip to: 6516 + /* 2080 */ MCD_OPC_Decode, + 193, + 5, + 69, // Opcode: ABSQ_S_W_MM + /* 2084 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 2098 + /* 2089 */ MCD_OPC_CheckPredicate, + 8, + 70, + 17, + 0, // Skip to: 6516 + /* 2094 */ MCD_OPC_Decode, + 176, + 7, + 69, // Opcode: BITREV_MM + /* 2098 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 2112 + /* 2103 */ MCD_OPC_CheckPredicate, + 8, + 56, + 17, + 0, // Skip to: 6516 + /* 2108 */ MCD_OPC_Decode, + 235, + 13, + 70, // Opcode: INSV_MM + /* 2112 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 2126 + /* 2117 */ MCD_OPC_CheckPredicate, + 8, + 42, + 17, + 0, // Skip to: 6516 + /* 2122 */ MCD_OPC_Decode, + 138, + 18, + 71, // Opcode: PRECEQ_W_PHL_MM + /* 2126 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 2140 + /* 2131 */ MCD_OPC_CheckPredicate, + 8, + 28, + 17, + 0, // Skip to: 6516 + /* 2136 */ MCD_OPC_Decode, + 140, + 18, + 71, // Opcode: PRECEQ_W_PHR_MM + /* 2140 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 2154 + /* 2145 */ MCD_OPC_CheckPredicate, + 8, + 14, + 17, + 0, // Skip to: 6516 + /* 2150 */ MCD_OPC_Decode, + 132, + 18, + 68, // Opcode: PRECEQU_PH_QBL_MM + /* 2154 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 2168 + /* 2159 */ MCD_OPC_CheckPredicate, + 8, + 0, + 17, + 0, // Skip to: 6516 + /* 2164 */ MCD_OPC_Decode, + 136, + 18, + 68, // Opcode: PRECEQU_PH_QBR_MM + /* 2168 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 2182 + /* 2173 */ MCD_OPC_CheckPredicate, + 8, + 242, + 16, + 0, // Skip to: 6516 + /* 2178 */ MCD_OPC_Decode, + 144, + 18, + 68, // Opcode: PRECEU_PH_QBL_MM + /* 2182 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 2196 + /* 2187 */ MCD_OPC_CheckPredicate, + 8, + 228, + 16, + 0, // Skip to: 6516 + /* 2192 */ MCD_OPC_Decode, + 148, + 18, + 68, // Opcode: PRECEU_PH_QBR_MM + /* 2196 */ MCD_OPC_FilterValue, + 30, + 219, + 16, + 0, // Skip to: 6516 + /* 2201 */ MCD_OPC_CheckPredicate, + 8, + 214, + 16, + 0, // Skip to: 6516 + /* 2206 */ MCD_OPC_Decode, + 175, + 18, + 71, // Opcode: RADDU_W_QB_MM + /* 2210 */ MCD_OPC_FilterValue, + 5, + 87, + 0, + 0, // Skip to: 2302 + /* 2215 */ MCD_OPC_ExtractField, + 11, + 15, // Inst{25-11} ... + /* 2218 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2232 + /* 2223 */ MCD_OPC_CheckPredicate, + 10, + 192, + 16, + 0, // Skip to: 6516 + /* 2228 */ MCD_OPC_Decode, + 213, + 21, + 0, // Opcode: TLBGP_MM + /* 2232 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2246 + /* 2237 */ MCD_OPC_CheckPredicate, + 10, + 178, + 16, + 0, // Skip to: 6516 + /* 2242 */ MCD_OPC_Decode, + 215, + 21, + 0, // Opcode: TLBGR_MM + /* 2246 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 2260 + /* 2251 */ MCD_OPC_CheckPredicate, + 10, + 164, + 16, + 0, // Skip to: 6516 + /* 2256 */ MCD_OPC_Decode, + 217, + 21, + 0, // Opcode: TLBGWI_MM + /* 2260 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 2274 + /* 2265 */ MCD_OPC_CheckPredicate, + 10, + 150, + 16, + 0, // Skip to: 6516 + /* 2270 */ MCD_OPC_Decode, + 219, + 21, + 0, // Opcode: TLBGWR_MM + /* 2274 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 2288 + /* 2279 */ MCD_OPC_CheckPredicate, + 10, + 136, + 16, + 0, // Skip to: 6516 + /* 2284 */ MCD_OPC_Decode, + 211, + 21, + 0, // Opcode: TLBGINV_MM + /* 2288 */ MCD_OPC_FilterValue, + 10, + 127, + 16, + 0, // Skip to: 6516 + /* 2293 */ MCD_OPC_CheckPredicate, + 10, + 122, + 16, + 0, // Skip to: 6516 + /* 2298 */ MCD_OPC_Decode, + 210, + 21, + 0, // Opcode: TLBGINVF_MM + /* 2302 */ MCD_OPC_FilterValue, + 7, + 31, + 0, + 0, // Skip to: 2338 + /* 2307 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 2310 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2324 + /* 2315 */ MCD_OPC_CheckPredicate, + 9, + 100, + 16, + 0, // Skip to: 6516 + /* 2320 */ MCD_OPC_Decode, + 213, + 19, + 63, // Opcode: SHRA_QB_MMR2 + /* 2324 */ MCD_OPC_FilterValue, + 2, + 91, + 16, + 0, // Skip to: 6516 + /* 2329 */ MCD_OPC_CheckPredicate, + 9, + 86, + 16, + 0, // Skip to: 6516 + /* 2334 */ MCD_OPC_Decode, + 217, + 19, + 63, // Opcode: SHRA_R_QB_MMR2 + /* 2338 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 2374 + /* 2343 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 2346 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2360 + /* 2351 */ MCD_OPC_CheckPredicate, + 7, + 64, + 16, + 0, // Skip to: 6516 + /* 2356 */ MCD_OPC_Decode, + 207, + 21, + 60, // Opcode: TGE_MM + /* 2360 */ MCD_OPC_FilterValue, + 1, + 55, + 16, + 0, // Skip to: 6516 + /* 2365 */ MCD_OPC_CheckPredicate, + 7, + 50, + 16, + 0, // Skip to: 6516 + /* 2370 */ MCD_OPC_Decode, + 237, + 21, + 60, // Opcode: TLTU_MM + /* 2374 */ MCD_OPC_FilterValue, + 9, + 101, + 0, + 0, // Skip to: 2480 + /* 2379 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 2382 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 2403 + /* 2387 */ MCD_OPC_CheckPredicate, + 8, + 28, + 16, + 0, // Skip to: 6516 + /* 2392 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 21, + 16, + 0, // Skip to: 6516 + /* 2399 */ MCD_OPC_Decode, + 252, + 16, + 72, // Opcode: MTHLIP_MM + /* 2403 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2417 + /* 2408 */ MCD_OPC_CheckPredicate, + 8, + 7, + 16, + 0, // Skip to: 6516 + /* 2413 */ MCD_OPC_Decode, + 183, + 15, + 65, // Opcode: MAQ_S_W_PHR_MM + /* 2417 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 2438 + /* 2422 */ MCD_OPC_CheckPredicate, + 8, + 249, + 15, + 0, // Skip to: 6516 + /* 2427 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 242, + 15, + 0, // Skip to: 6516 + /* 2434 */ MCD_OPC_Decode, + 182, + 19, + 72, // Opcode: SHILOV_MM + /* 2438 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 2452 + /* 2443 */ MCD_OPC_CheckPredicate, + 8, + 228, + 15, + 0, // Skip to: 6516 + /* 2448 */ MCD_OPC_Decode, + 181, + 15, + 65, // Opcode: MAQ_S_W_PHL_MM + /* 2452 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2466 + /* 2457 */ MCD_OPC_CheckPredicate, + 8, + 214, + 15, + 0, // Skip to: 6516 + /* 2462 */ MCD_OPC_Decode, + 179, + 15, + 65, // Opcode: MAQ_SA_W_PHR_MM + /* 2466 */ MCD_OPC_FilterValue, + 7, + 205, + 15, + 0, // Skip to: 6516 + /* 2471 */ MCD_OPC_CheckPredicate, + 8, + 200, + 15, + 0, // Skip to: 6516 + /* 2476 */ MCD_OPC_Decode, + 177, + 15, + 65, // Opcode: MAQ_SA_W_PHL_MM + /* 2480 */ MCD_OPC_FilterValue, + 10, + 115, + 0, + 0, // Skip to: 2600 + /* 2485 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 2488 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2502 + /* 2493 */ MCD_OPC_CheckPredicate, + 8, + 178, + 15, + 0, // Skip to: 6516 + /* 2498 */ MCD_OPC_Decode, + 166, + 11, + 65, // Opcode: DPAQ_S_W_PH_MM + /* 2502 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2516 + /* 2507 */ MCD_OPC_CheckPredicate, + 8, + 164, + 15, + 0, // Skip to: 6516 + /* 2512 */ MCD_OPC_Decode, + 170, + 15, + 65, // Opcode: MADD_DSP_MM + /* 2516 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2530 + /* 2521 */ MCD_OPC_CheckPredicate, + 8, + 150, + 15, + 0, // Skip to: 6516 + /* 2526 */ MCD_OPC_Decode, + 164, + 11, + 65, // Opcode: DPAQ_SA_L_W_MM + /* 2530 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 2544 + /* 2535 */ MCD_OPC_CheckPredicate, + 8, + 136, + 15, + 0, // Skip to: 6516 + /* 2540 */ MCD_OPC_Decode, + 160, + 15, + 65, // Opcode: MADDU_DSP_MM + /* 2544 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 2558 + /* 2549 */ MCD_OPC_CheckPredicate, + 9, + 122, + 15, + 0, // Skip to: 6516 + /* 2554 */ MCD_OPC_Decode, + 162, + 11, + 65, // Opcode: DPAQX_S_W_PH_MMR2 + /* 2558 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2572 + /* 2563 */ MCD_OPC_CheckPredicate, + 8, + 108, + 15, + 0, // Skip to: 6516 + /* 2568 */ MCD_OPC_Decode, + 221, + 16, + 65, // Opcode: MSUB_DSP_MM + /* 2572 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 2586 + /* 2577 */ MCD_OPC_CheckPredicate, + 9, + 94, + 15, + 0, // Skip to: 6516 + /* 2582 */ MCD_OPC_Decode, + 160, + 11, + 65, // Opcode: DPAQX_SA_W_PH_MMR2 + /* 2586 */ MCD_OPC_FilterValue, + 7, + 85, + 15, + 0, // Skip to: 6516 + /* 2591 */ MCD_OPC_CheckPredicate, + 8, + 80, + 15, + 0, // Skip to: 6516 + /* 2596 */ MCD_OPC_Decode, + 211, + 16, + 65, // Opcode: MSUBU_DSP_MM + /* 2600 */ MCD_OPC_FilterValue, + 12, + 27, + 1, + 0, // Skip to: 2888 + /* 2605 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 2608 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2622 + /* 2613 */ MCD_OPC_CheckPredicate, + 8, + 58, + 15, + 0, // Skip to: 6516 + /* 2618 */ MCD_OPC_Decode, + 190, + 18, + 73, // Opcode: REPLV_PH_MM + /* 2622 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2636 + /* 2627 */ MCD_OPC_CheckPredicate, + 8, + 44, + 15, + 0, // Skip to: 6516 + /* 2632 */ MCD_OPC_Decode, + 192, + 18, + 73, // Opcode: REPLV_QB_MM + /* 2636 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2650 + /* 2641 */ MCD_OPC_CheckPredicate, + 7, + 30, + 15, + 0, // Skip to: 6516 + /* 2646 */ MCD_OPC_Decode, + 147, + 19, + 69, // Opcode: SEB_MM + /* 2650 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 2664 + /* 2655 */ MCD_OPC_CheckPredicate, + 7, + 16, + 15, + 0, // Skip to: 6516 + /* 2660 */ MCD_OPC_Decode, + 150, + 19, + 69, // Opcode: SEH_MM + /* 2664 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 2678 + /* 2669 */ MCD_OPC_CheckPredicate, + 7, + 2, + 15, + 0, // Skip to: 6516 + /* 2674 */ MCD_OPC_Decode, + 203, + 8, + 69, // Opcode: CLO_MM + /* 2678 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 2692 + /* 2683 */ MCD_OPC_CheckPredicate, + 7, + 244, + 14, + 0, // Skip to: 6516 + /* 2688 */ MCD_OPC_Decode, + 223, + 8, + 69, // Opcode: CLZ_MM + /* 2692 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 2706 + /* 2697 */ MCD_OPC_CheckPredicate, + 6, + 230, + 14, + 0, // Skip to: 6516 + /* 2702 */ MCD_OPC_Decode, + 180, + 18, + 74, // Opcode: RDHWR_MM + /* 2706 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 2720 + /* 2711 */ MCD_OPC_CheckPredicate, + 8, + 216, + 14, + 0, // Skip to: 6516 + /* 2716 */ MCD_OPC_Decode, + 131, + 18, + 68, // Opcode: PRECEQU_PH_QBLA_MM + /* 2720 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 2734 + /* 2725 */ MCD_OPC_CheckPredicate, + 7, + 202, + 14, + 0, // Skip to: 6516 + /* 2730 */ MCD_OPC_Decode, + 143, + 22, + 69, // Opcode: WSBH_MM + /* 2734 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 2748 + /* 2739 */ MCD_OPC_CheckPredicate, + 6, + 188, + 14, + 0, // Skip to: 6516 + /* 2744 */ MCD_OPC_Decode, + 170, + 17, + 75, // Opcode: MULT_MM + /* 2748 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 2762 + /* 2753 */ MCD_OPC_CheckPredicate, + 8, + 174, + 14, + 0, // Skip to: 6516 + /* 2758 */ MCD_OPC_Decode, + 135, + 18, + 68, // Opcode: PRECEQU_PH_QBRA_MM + /* 2762 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 2776 + /* 2767 */ MCD_OPC_CheckPredicate, + 6, + 160, + 14, + 0, // Skip to: 6516 + /* 2772 */ MCD_OPC_Decode, + 172, + 17, + 75, // Opcode: MULTu_MM + /* 2776 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 2790 + /* 2781 */ MCD_OPC_CheckPredicate, + 6, + 146, + 14, + 0, // Skip to: 6516 + /* 2786 */ MCD_OPC_Decode, + 140, + 19, + 75, // Opcode: SDIV_MM + /* 2790 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 2804 + /* 2795 */ MCD_OPC_CheckPredicate, + 8, + 132, + 14, + 0, // Skip to: 6516 + /* 2800 */ MCD_OPC_Decode, + 143, + 18, + 68, // Opcode: PRECEU_PH_QBLA_MM + /* 2804 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 2818 + /* 2809 */ MCD_OPC_CheckPredicate, + 6, + 118, + 14, + 0, // Skip to: 6516 + /* 2814 */ MCD_OPC_Decode, + 128, + 22, + 75, // Opcode: UDIV_MM + /* 2818 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 2832 + /* 2823 */ MCD_OPC_CheckPredicate, + 6, + 104, + 14, + 0, // Skip to: 6516 + /* 2828 */ MCD_OPC_Decode, + 171, + 15, + 75, // Opcode: MADD_MM + /* 2832 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 2846 + /* 2837 */ MCD_OPC_CheckPredicate, + 8, + 90, + 14, + 0, // Skip to: 6516 + /* 2842 */ MCD_OPC_Decode, + 147, + 18, + 68, // Opcode: PRECEU_PH_QBRA_MM + /* 2846 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 2860 + /* 2851 */ MCD_OPC_CheckPredicate, + 6, + 76, + 14, + 0, // Skip to: 6516 + /* 2856 */ MCD_OPC_Decode, + 161, + 15, + 75, // Opcode: MADDU_MM + /* 2860 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 2874 + /* 2865 */ MCD_OPC_CheckPredicate, + 6, + 62, + 14, + 0, // Skip to: 6516 + /* 2870 */ MCD_OPC_Decode, + 222, + 16, + 75, // Opcode: MSUB_MM + /* 2874 */ MCD_OPC_FilterValue, + 31, + 53, + 14, + 0, // Skip to: 6516 + /* 2879 */ MCD_OPC_CheckPredicate, + 6, + 48, + 14, + 0, // Skip to: 6516 + /* 2884 */ MCD_OPC_Decode, + 212, + 16, + 75, // Opcode: MSUBU_MM + /* 2888 */ MCD_OPC_FilterValue, + 13, + 206, + 0, + 0, // Skip to: 3099 + /* 2893 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 2896 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 2917 + /* 2901 */ MCD_OPC_CheckPredicate, + 7, + 26, + 14, + 0, // Skip to: 6516 + /* 2906 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 19, + 14, + 0, // Skip to: 6516 + /* 2913 */ MCD_OPC_Decode, + 225, + 21, + 0, // Opcode: TLBP_MM + /* 2917 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 2938 + /* 2922 */ MCD_OPC_CheckPredicate, + 7, + 5, + 14, + 0, // Skip to: 6516 + /* 2927 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 254, + 13, + 0, // Skip to: 6516 + /* 2934 */ MCD_OPC_Decode, + 227, + 21, + 0, // Opcode: TLBR_MM + /* 2938 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 2959 + /* 2943 */ MCD_OPC_CheckPredicate, + 7, + 240, + 13, + 0, // Skip to: 6516 + /* 2948 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 233, + 13, + 0, // Skip to: 6516 + /* 2955 */ MCD_OPC_Decode, + 229, + 21, + 0, // Opcode: TLBWI_MM + /* 2959 */ MCD_OPC_FilterValue, + 6, + 16, + 0, + 0, // Skip to: 2980 + /* 2964 */ MCD_OPC_CheckPredicate, + 7, + 219, + 13, + 0, // Skip to: 6516 + /* 2969 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 212, + 13, + 0, // Skip to: 6516 + /* 2976 */ MCD_OPC_Decode, + 231, + 21, + 0, // Opcode: TLBWR_MM + /* 2980 */ MCD_OPC_FilterValue, + 13, + 16, + 0, + 0, // Skip to: 3001 + /* 2985 */ MCD_OPC_CheckPredicate, + 7, + 198, + 13, + 0, // Skip to: 6516 + /* 2990 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 191, + 13, + 0, // Skip to: 6516 + /* 2997 */ MCD_OPC_Decode, + 171, + 21, + 76, // Opcode: SYNC_MM + /* 3001 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 3015 + /* 3006 */ MCD_OPC_CheckPredicate, + 7, + 177, + 13, + 0, // Skip to: 6516 + /* 3011 */ MCD_OPC_Decode, + 174, + 21, + 77, // Opcode: SYSCALL_MM + /* 3015 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 3029 + /* 3020 */ MCD_OPC_CheckPredicate, + 7, + 163, + 13, + 0, // Skip to: 6516 + /* 3025 */ MCD_OPC_Decode, + 137, + 22, + 77, // Opcode: WAIT_MM + /* 3029 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 3043 + /* 3034 */ MCD_OPC_CheckPredicate, + 10, + 149, + 13, + 0, // Skip to: 6516 + /* 3039 */ MCD_OPC_Decode, + 208, + 13, + 77, // Opcode: HYPCALL_MM + /* 3043 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 3057 + /* 3048 */ MCD_OPC_CheckPredicate, + 7, + 135, + 13, + 0, // Skip to: 6516 + /* 3053 */ MCD_OPC_Decode, + 128, + 19, + 77, // Opcode: SDBBP_MM + /* 3057 */ MCD_OPC_FilterValue, + 28, + 16, + 0, + 0, // Skip to: 3078 + /* 3062 */ MCD_OPC_CheckPredicate, + 7, + 121, + 13, + 0, // Skip to: 6516 + /* 3067 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 114, + 13, + 0, // Skip to: 6516 + /* 3074 */ MCD_OPC_Decode, + 229, + 10, + 0, // Opcode: DERET_MM + /* 3078 */ MCD_OPC_FilterValue, + 30, + 105, + 13, + 0, // Skip to: 6516 + /* 3083 */ MCD_OPC_CheckPredicate, + 7, + 100, + 13, + 0, // Skip to: 6516 + /* 3088 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 93, + 13, + 0, // Skip to: 6516 + /* 3095 */ MCD_OPC_Decode, + 232, + 11, + 0, // Opcode: ERET_MM + /* 3099 */ MCD_OPC_FilterValue, + 15, + 16, + 0, + 0, // Skip to: 3120 + /* 3104 */ MCD_OPC_CheckPredicate, + 9, + 79, + 13, + 0, // Skip to: 6516 + /* 3109 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 72, + 13, + 0, // Skip to: 6516 + /* 3116 */ MCD_OPC_Decode, + 225, + 19, + 59, // Opcode: SHRL_PH_MMR2 + /* 3120 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 3156 + /* 3125 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 3128 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3142 + /* 3133 */ MCD_OPC_CheckPredicate, + 7, + 50, + 13, + 0, // Skip to: 6516 + /* 3138 */ MCD_OPC_Decode, + 206, + 21, + 60, // Opcode: TGEU_MM + /* 3142 */ MCD_OPC_FilterValue, + 1, + 41, + 13, + 0, // Skip to: 6516 + /* 3147 */ MCD_OPC_CheckPredicate, + 7, + 36, + 13, + 0, // Skip to: 6516 + /* 3152 */ MCD_OPC_Decode, + 242, + 21, + 60, // Opcode: TNE_MM + /* 3156 */ MCD_OPC_FilterValue, + 18, + 115, + 0, + 0, // Skip to: 3276 + /* 3161 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 3164 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3178 + /* 3169 */ MCD_OPC_CheckPredicate, + 9, + 14, + 13, + 0, // Skip to: 6516 + /* 3174 */ MCD_OPC_Decode, + 197, + 11, + 65, // Opcode: DPS_W_PH_MMR2 + /* 3178 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3192 + /* 3183 */ MCD_OPC_CheckPredicate, + 8, + 0, + 13, + 0, // Skip to: 6516 + /* 3188 */ MCD_OPC_Decode, + 169, + 17, + 78, // Opcode: MULT_DSP_MM + /* 3192 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3206 + /* 3197 */ MCD_OPC_CheckPredicate, + 9, + 242, + 12, + 0, // Skip to: 6516 + /* 3202 */ MCD_OPC_Decode, + 195, + 11, + 65, // Opcode: DPSX_W_PH_MMR2 + /* 3206 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3220 + /* 3211 */ MCD_OPC_CheckPredicate, + 8, + 228, + 12, + 0, // Skip to: 6516 + /* 3216 */ MCD_OPC_Decode, + 167, + 17, + 78, // Opcode: MULTU_DSP_MM + /* 3220 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 3234 + /* 3225 */ MCD_OPC_CheckPredicate, + 8, + 214, + 12, + 0, // Skip to: 6516 + /* 3230 */ MCD_OPC_Decode, + 191, + 11, + 65, // Opcode: DPSU_H_QBL_MM + /* 3234 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3248 + /* 3239 */ MCD_OPC_CheckPredicate, + 9, + 200, + 12, + 0, // Skip to: 6516 + /* 3244 */ MCD_OPC_Decode, + 164, + 17, + 65, // Opcode: MULSA_W_PH_MMR2 + /* 3248 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 3262 + /* 3253 */ MCD_OPC_CheckPredicate, + 8, + 186, + 12, + 0, // Skip to: 6516 + /* 3258 */ MCD_OPC_Decode, + 193, + 11, + 65, // Opcode: DPSU_H_QBR_MM + /* 3262 */ MCD_OPC_FilterValue, + 7, + 177, + 12, + 0, // Skip to: 6516 + /* 3267 */ MCD_OPC_CheckPredicate, + 8, + 172, + 12, + 0, // Skip to: 6516 + /* 3272 */ MCD_OPC_Decode, + 162, + 17, + 65, // Opcode: MULSAQ_S_W_PH_MM + /* 3276 */ MCD_OPC_FilterValue, + 19, + 16, + 0, + 0, // Skip to: 3297 + /* 3281 */ MCD_OPC_CheckPredicate, + 10, + 158, + 12, + 0, // Skip to: 6516 + /* 3286 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 151, + 12, + 0, // Skip to: 6516 + /* 3293 */ MCD_OPC_Decode, + 221, + 15, + 57, // Opcode: MFGC0_MM + /* 3297 */ MCD_OPC_FilterValue, + 20, + 31, + 0, + 0, // Skip to: 3333 + /* 3302 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3305 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 3319 + /* 3310 */ MCD_OPC_CheckPredicate, + 7, + 129, + 12, + 0, // Skip to: 6516 + /* 3315 */ MCD_OPC_Decode, + 176, + 8, + 79, // Opcode: CFC2_MM + /* 3319 */ MCD_OPC_FilterValue, + 27, + 120, + 12, + 0, // Skip to: 6516 + /* 3324 */ MCD_OPC_CheckPredicate, + 7, + 115, + 12, + 0, // Skip to: 6516 + /* 3329 */ MCD_OPC_Decode, + 203, + 9, + 80, // Opcode: CTC2_MM + /* 3333 */ MCD_OPC_FilterValue, + 21, + 87, + 0, + 0, // Skip to: 3425 + /* 3338 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3341 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 3362 + /* 3346 */ MCD_OPC_CheckPredicate, + 6, + 93, + 12, + 0, // Skip to: 6516 + /* 3351 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 86, + 12, + 0, // Skip to: 6516 + /* 3358 */ MCD_OPC_Decode, + 235, + 15, + 81, // Opcode: MFHI_MM + /* 3362 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 3383 + /* 3367 */ MCD_OPC_CheckPredicate, + 6, + 72, + 12, + 0, // Skip to: 6516 + /* 3372 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 65, + 12, + 0, // Skip to: 6516 + /* 3379 */ MCD_OPC_Decode, + 241, + 15, + 81, // Opcode: MFLO_MM + /* 3383 */ MCD_OPC_FilterValue, + 5, + 16, + 0, + 0, // Skip to: 3404 + /* 3388 */ MCD_OPC_CheckPredicate, + 6, + 51, + 12, + 0, // Skip to: 6516 + /* 3393 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 44, + 12, + 0, // Skip to: 6516 + /* 3400 */ MCD_OPC_Decode, + 250, + 16, + 81, // Opcode: MTHI_MM + /* 3404 */ MCD_OPC_FilterValue, + 7, + 35, + 12, + 0, // Skip to: 6516 + /* 3409 */ MCD_OPC_CheckPredicate, + 6, + 30, + 12, + 0, // Skip to: 6516 + /* 3414 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 23, + 12, + 0, // Skip to: 6516 + /* 3421 */ MCD_OPC_Decode, + 129, + 17, + 81, // Opcode: MTLO_MM + /* 3425 */ MCD_OPC_FilterValue, + 23, + 16, + 0, + 0, // Skip to: 3446 + /* 3430 */ MCD_OPC_CheckPredicate, + 8, + 9, + 12, + 0, // Skip to: 6516 + /* 3435 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 2, + 12, + 0, // Skip to: 6516 + /* 3442 */ MCD_OPC_Decode, + 196, + 18, + 82, // Opcode: REPL_QB_MM + /* 3446 */ MCD_OPC_FilterValue, + 25, + 115, + 0, + 0, // Skip to: 3566 + /* 3451 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 3454 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3468 + /* 3459 */ MCD_OPC_CheckPredicate, + 8, + 236, + 11, + 0, // Skip to: 6516 + /* 3464 */ MCD_OPC_Decode, + 177, + 18, + 83, // Opcode: RDDSP_MM + /* 3468 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3482 + /* 3473 */ MCD_OPC_CheckPredicate, + 8, + 222, + 11, + 0, // Skip to: 6516 + /* 3478 */ MCD_OPC_Decode, + 133, + 12, + 84, // Opcode: EXTR_W_MM + /* 3482 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3496 + /* 3487 */ MCD_OPC_CheckPredicate, + 8, + 208, + 11, + 0, // Skip to: 6516 + /* 3492 */ MCD_OPC_Decode, + 140, + 22, + 83, // Opcode: WRDSP_MM + /* 3496 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3510 + /* 3501 */ MCD_OPC_CheckPredicate, + 8, + 194, + 11, + 0, // Skip to: 6516 + /* 3506 */ MCD_OPC_Decode, + 129, + 12, + 84, // Opcode: EXTR_R_W_MM + /* 3510 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 3524 + /* 3515 */ MCD_OPC_CheckPredicate, + 8, + 180, + 11, + 0, // Skip to: 6516 + /* 3520 */ MCD_OPC_Decode, + 245, + 11, + 84, // Opcode: EXTP_MM + /* 3524 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3538 + /* 3529 */ MCD_OPC_CheckPredicate, + 8, + 166, + 11, + 0, // Skip to: 6516 + /* 3534 */ MCD_OPC_Decode, + 255, + 11, + 84, // Opcode: EXTR_RS_W_MM + /* 3538 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 3552 + /* 3543 */ MCD_OPC_CheckPredicate, + 8, + 152, + 11, + 0, // Skip to: 6516 + /* 3548 */ MCD_OPC_Decode, + 242, + 11, + 84, // Opcode: EXTPDP_MM + /* 3552 */ MCD_OPC_FilterValue, + 7, + 143, + 11, + 0, // Skip to: 6516 + /* 3557 */ MCD_OPC_CheckPredicate, + 8, + 138, + 11, + 0, // Skip to: 6516 + /* 3562 */ MCD_OPC_Decode, + 131, + 12, + 84, // Opcode: EXTR_S_H_MM + /* 3566 */ MCD_OPC_FilterValue, + 26, + 115, + 0, + 0, // Skip to: 3686 + /* 3571 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 3574 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3588 + /* 3579 */ MCD_OPC_CheckPredicate, + 8, + 116, + 11, + 0, // Skip to: 6516 + /* 3584 */ MCD_OPC_Decode, + 183, + 11, + 65, // Opcode: DPSQ_S_W_PH_MM + /* 3588 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3602 + /* 3593 */ MCD_OPC_CheckPredicate, + 8, + 102, + 11, + 0, // Skip to: 6516 + /* 3598 */ MCD_OPC_Decode, + 253, + 11, + 67, // Opcode: EXTRV_W_MM + /* 3602 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3616 + /* 3607 */ MCD_OPC_CheckPredicate, + 8, + 88, + 11, + 0, // Skip to: 6516 + /* 3612 */ MCD_OPC_Decode, + 181, + 11, + 65, // Opcode: DPSQ_SA_L_W_MM + /* 3616 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3630 + /* 3621 */ MCD_OPC_CheckPredicate, + 8, + 74, + 11, + 0, // Skip to: 6516 + /* 3626 */ MCD_OPC_Decode, + 249, + 11, + 67, // Opcode: EXTRV_R_W_MM + /* 3630 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 3644 + /* 3635 */ MCD_OPC_CheckPredicate, + 9, + 60, + 11, + 0, // Skip to: 6516 + /* 3640 */ MCD_OPC_Decode, + 179, + 11, + 65, // Opcode: DPSQX_S_W_PH_MMR2 + /* 3644 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3658 + /* 3649 */ MCD_OPC_CheckPredicate, + 8, + 46, + 11, + 0, // Skip to: 6516 + /* 3654 */ MCD_OPC_Decode, + 247, + 11, + 67, // Opcode: EXTRV_RS_W_MM + /* 3658 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 3672 + /* 3663 */ MCD_OPC_CheckPredicate, + 9, + 32, + 11, + 0, // Skip to: 6516 + /* 3668 */ MCD_OPC_Decode, + 177, + 11, + 65, // Opcode: DPSQX_SA_W_PH_MMR2 + /* 3672 */ MCD_OPC_FilterValue, + 7, + 23, + 11, + 0, // Skip to: 6516 + /* 3677 */ MCD_OPC_CheckPredicate, + 8, + 18, + 11, + 0, // Skip to: 6516 + /* 3682 */ MCD_OPC_Decode, + 251, + 11, + 67, // Opcode: EXTRV_S_H_MM + /* 3686 */ MCD_OPC_FilterValue, + 27, + 16, + 0, + 0, // Skip to: 3707 + /* 3691 */ MCD_OPC_CheckPredicate, + 10, + 4, + 11, + 0, // Skip to: 6516 + /* 3696 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 253, + 10, + 0, // Skip to: 6516 + /* 3703 */ MCD_OPC_Decode, + 237, + 16, + 58, // Opcode: MTGC0_MM + /* 3707 */ MCD_OPC_FilterValue, + 28, + 47, + 0, + 0, // Skip to: 3759 + /* 3712 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3715 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 3745 + /* 3720 */ MCD_OPC_CheckPredicate, + 6, + 11, + 0, + 0, // Skip to: 3736 + /* 3725 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 3736 + /* 3732 */ MCD_OPC_Decode, + 144, + 14, + 81, // Opcode: JR_MM + /* 3736 */ MCD_OPC_CheckPredicate, + 6, + 215, + 10, + 0, // Skip to: 6516 + /* 3741 */ MCD_OPC_Decode, + 250, + 13, + 69, // Opcode: JALR_MM + /* 3745 */ MCD_OPC_FilterValue, + 9, + 206, + 10, + 0, // Skip to: 6516 + /* 3750 */ MCD_OPC_CheckPredicate, + 6, + 201, + 10, + 0, // Skip to: 6516 + /* 3755 */ MCD_OPC_Decode, + 247, + 13, + 69, // Opcode: JALRS_MM + /* 3759 */ MCD_OPC_FilterValue, + 29, + 192, + 10, + 0, // Skip to: 6516 + /* 3764 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3767 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 3788 + /* 3772 */ MCD_OPC_CheckPredicate, + 7, + 179, + 10, + 0, // Skip to: 6516 + /* 3777 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 172, + 10, + 0, // Skip to: 6516 + /* 3784 */ MCD_OPC_Decode, + 251, + 10, + 81, // Opcode: DI_MM + /* 3788 */ MCD_OPC_FilterValue, + 10, + 163, + 10, + 0, // Skip to: 6516 + /* 3793 */ MCD_OPC_CheckPredicate, + 7, + 158, + 10, + 0, // Skip to: 6516 + /* 3798 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 151, + 10, + 0, // Skip to: 6516 + /* 3805 */ MCD_OPC_Decode, + 226, + 11, + 81, // Opcode: EI_MM + /* 3809 */ MCD_OPC_FilterValue, + 61, + 142, + 10, + 0, // Skip to: 6516 + /* 3814 */ MCD_OPC_CheckPredicate, + 8, + 137, + 10, + 0, // Skip to: 6516 + /* 3819 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 130, + 10, + 0, // Skip to: 6516 + /* 3826 */ MCD_OPC_Decode, + 194, + 18, + 85, // Opcode: REPL_PH_MM + /* 3830 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 3844 + /* 3835 */ MCD_OPC_CheckPredicate, + 6, + 116, + 10, + 0, // Skip to: 6516 + /* 3840 */ MCD_OPC_Decode, + 136, + 6, + 86, // Opcode: ADDi_MM + /* 3844 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3858 + /* 3849 */ MCD_OPC_CheckPredicate, + 7, + 102, + 10, + 0, // Skip to: 6516 + /* 3854 */ MCD_OPC_Decode, + 166, + 14, + 87, // Opcode: LBu_MM + /* 3858 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 3872 + /* 3863 */ MCD_OPC_CheckPredicate, + 7, + 88, + 10, + 0, // Skip to: 6516 + /* 3868 */ MCD_OPC_Decode, + 240, + 18, + 87, // Opcode: SB_MM + /* 3872 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 3886 + /* 3877 */ MCD_OPC_CheckPredicate, + 7, + 74, + 10, + 0, // Skip to: 6516 + /* 3882 */ MCD_OPC_Decode, + 160, + 14, + 87, // Opcode: LB_MM + /* 3886 */ MCD_OPC_FilterValue, + 8, + 73, + 0, + 0, // Skip to: 3964 + /* 3891 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 3894 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3908 + /* 3899 */ MCD_OPC_CheckPredicate, + 7, + 52, + 10, + 0, // Skip to: 6516 + /* 3904 */ MCD_OPC_Decode, + 251, + 14, + 88, // Opcode: LWP_MM + /* 3908 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3922 + /* 3913 */ MCD_OPC_CheckPredicate, + 7, + 38, + 10, + 0, // Skip to: 6516 + /* 3918 */ MCD_OPC_Decode, + 248, + 14, + 88, // Opcode: LWM32_MM + /* 3922 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 3936 + /* 3927 */ MCD_OPC_CheckPredicate, + 6, + 24, + 10, + 0, // Skip to: 6516 + /* 3932 */ MCD_OPC_Decode, + 152, + 8, + 89, // Opcode: CACHE_MM + /* 3936 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 3950 + /* 3941 */ MCD_OPC_CheckPredicate, + 7, + 10, + 10, + 0, // Skip to: 6516 + /* 3946 */ MCD_OPC_Decode, + 155, + 21, + 88, // Opcode: SWP_MM + /* 3950 */ MCD_OPC_FilterValue, + 13, + 1, + 10, + 0, // Skip to: 6516 + /* 3955 */ MCD_OPC_CheckPredicate, + 7, + 252, + 9, + 0, // Skip to: 6516 + /* 3960 */ MCD_OPC_Decode, + 154, + 21, + 88, // Opcode: SWM32_MM + /* 3964 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 3978 + /* 3969 */ MCD_OPC_CheckPredicate, + 6, + 238, + 9, + 0, // Skip to: 6516 + /* 3974 */ MCD_OPC_Decode, + 138, + 6, + 86, // Opcode: ADDiu_MM + /* 3978 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 3992 + /* 3983 */ MCD_OPC_CheckPredicate, + 7, + 224, + 9, + 0, // Skip to: 6516 + /* 3988 */ MCD_OPC_Decode, + 204, + 14, + 87, // Opcode: LHu_MM + /* 3992 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 4006 + /* 3997 */ MCD_OPC_CheckPredicate, + 7, + 210, + 9, + 0, // Skip to: 6516 + /* 4002 */ MCD_OPC_Decode, + 228, + 19, + 87, // Opcode: SH_MM + /* 4006 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 4020 + /* 4011 */ MCD_OPC_CheckPredicate, + 7, + 196, + 9, + 0, // Skip to: 6516 + /* 4016 */ MCD_OPC_Decode, + 199, + 14, + 87, // Opcode: LH_MM + /* 4020 */ MCD_OPC_FilterValue, + 16, + 83, + 1, + 0, // Skip to: 4364 + /* 4025 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 4028 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4042 + /* 4033 */ MCD_OPC_CheckPredicate, + 6, + 174, + 9, + 0, // Skip to: 6516 + /* 4038 */ MCD_OPC_Decode, + 206, + 7, + 90, // Opcode: BLTZ_MM + /* 4042 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4056 + /* 4047 */ MCD_OPC_CheckPredicate, + 6, + 160, + 9, + 0, // Skip to: 6516 + /* 4052 */ MCD_OPC_Decode, + 201, + 7, + 90, // Opcode: BLTZAL_MM + /* 4056 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4070 + /* 4061 */ MCD_OPC_CheckPredicate, + 6, + 146, + 9, + 0, // Skip to: 6516 + /* 4066 */ MCD_OPC_Decode, + 149, + 7, + 90, // Opcode: BGEZ_MM + /* 4070 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 4084 + /* 4075 */ MCD_OPC_CheckPredicate, + 6, + 132, + 9, + 0, // Skip to: 6516 + /* 4080 */ MCD_OPC_Decode, + 144, + 7, + 90, // Opcode: BGEZAL_MM + /* 4084 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 4098 + /* 4089 */ MCD_OPC_CheckPredicate, + 6, + 118, + 9, + 0, // Skip to: 6516 + /* 4094 */ MCD_OPC_Decode, + 187, + 7, + 90, // Opcode: BLEZ_MM + /* 4098 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 4112 + /* 4103 */ MCD_OPC_CheckPredicate, + 6, + 104, + 9, + 0, // Skip to: 6516 + /* 4108 */ MCD_OPC_Decode, + 231, + 7, + 90, // Opcode: BNEZC_MM + /* 4112 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 4126 + /* 4117 */ MCD_OPC_CheckPredicate, + 6, + 90, + 9, + 0, // Skip to: 6516 + /* 4122 */ MCD_OPC_Decode, + 158, + 7, + 90, // Opcode: BGTZ_MM + /* 4126 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 4140 + /* 4131 */ MCD_OPC_CheckPredicate, + 6, + 76, + 9, + 0, // Skip to: 6516 + /* 4136 */ MCD_OPC_Decode, + 128, + 7, + 90, // Opcode: BEQZC_MM + /* 4140 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 4154 + /* 4145 */ MCD_OPC_CheckPredicate, + 6, + 62, + 9, + 0, // Skip to: 6516 + /* 4150 */ MCD_OPC_Decode, + 235, + 21, + 91, // Opcode: TLTI_MM + /* 4154 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 4168 + /* 4159 */ MCD_OPC_CheckPredicate, + 6, + 48, + 9, + 0, // Skip to: 6516 + /* 4164 */ MCD_OPC_Decode, + 204, + 21, + 91, // Opcode: TGEI_MM + /* 4168 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 4182 + /* 4173 */ MCD_OPC_CheckPredicate, + 6, + 34, + 9, + 0, // Skip to: 6516 + /* 4178 */ MCD_OPC_Decode, + 234, + 21, + 91, // Opcode: TLTIU_MM + /* 4182 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 4196 + /* 4187 */ MCD_OPC_CheckPredicate, + 6, + 20, + 9, + 0, // Skip to: 6516 + /* 4192 */ MCD_OPC_Decode, + 203, + 21, + 91, // Opcode: TGEIU_MM + /* 4196 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 4210 + /* 4201 */ MCD_OPC_CheckPredicate, + 6, + 6, + 9, + 0, // Skip to: 6516 + /* 4206 */ MCD_OPC_Decode, + 241, + 21, + 91, // Opcode: TNEI_MM + /* 4210 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 4224 + /* 4215 */ MCD_OPC_CheckPredicate, + 6, + 248, + 8, + 0, // Skip to: 6516 + /* 4220 */ MCD_OPC_Decode, + 226, + 14, + 92, // Opcode: LUi_MM + /* 4224 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 4238 + /* 4229 */ MCD_OPC_CheckPredicate, + 6, + 234, + 8, + 0, // Skip to: 6516 + /* 4234 */ MCD_OPC_Decode, + 198, + 21, + 91, // Opcode: TEQI_MM + /* 4238 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 4252 + /* 4243 */ MCD_OPC_CheckPredicate, + 6, + 220, + 8, + 0, // Skip to: 6516 + /* 4248 */ MCD_OPC_Decode, + 169, + 21, + 93, // Opcode: SYNCI_MM + /* 4252 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 4266 + /* 4257 */ MCD_OPC_CheckPredicate, + 6, + 206, + 8, + 0, // Skip to: 6516 + /* 4262 */ MCD_OPC_Decode, + 200, + 7, + 90, // Opcode: BLTZALS_MM + /* 4266 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 4280 + /* 4271 */ MCD_OPC_CheckPredicate, + 6, + 192, + 8, + 0, // Skip to: 6516 + /* 4276 */ MCD_OPC_Decode, + 143, + 7, + 90, // Opcode: BGEZALS_MM + /* 4280 */ MCD_OPC_FilterValue, + 25, + 16, + 0, + 0, // Skip to: 4301 + /* 4285 */ MCD_OPC_CheckPredicate, + 11, + 178, + 8, + 0, // Skip to: 6516 + /* 4290 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 171, + 8, + 0, // Skip to: 6516 + /* 4297 */ MCD_OPC_Decode, + 244, + 7, + 94, // Opcode: BPOSGE32C_MMR3 + /* 4301 */ MCD_OPC_FilterValue, + 27, + 16, + 0, + 0, // Skip to: 4322 + /* 4306 */ MCD_OPC_CheckPredicate, + 12, + 157, + 8, + 0, // Skip to: 6516 + /* 4311 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 150, + 8, + 0, // Skip to: 6516 + /* 4318 */ MCD_OPC_Decode, + 245, + 7, + 95, // Opcode: BPOSGE32_MM + /* 4322 */ MCD_OPC_FilterValue, + 28, + 16, + 0, + 0, // Skip to: 4343 + /* 4327 */ MCD_OPC_CheckPredicate, + 13, + 136, + 8, + 0, // Skip to: 6516 + /* 4332 */ MCD_OPC_CheckField, + 16, + 2, + 0, + 129, + 8, + 0, // Skip to: 6516 + /* 4339 */ MCD_OPC_Decode, + 217, + 6, + 96, // Opcode: BC1F_MM + /* 4343 */ MCD_OPC_FilterValue, + 29, + 120, + 8, + 0, // Skip to: 6516 + /* 4348 */ MCD_OPC_CheckPredicate, + 13, + 115, + 8, + 0, // Skip to: 6516 + /* 4353 */ MCD_OPC_CheckField, + 16, + 2, + 0, + 108, + 8, + 0, // Skip to: 6516 + /* 4360 */ MCD_OPC_Decode, + 222, + 6, + 96, // Opcode: BC1T_MM + /* 4364 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 4378 + /* 4369 */ MCD_OPC_CheckPredicate, + 6, + 94, + 8, + 0, // Skip to: 6516 + /* 4374 */ MCD_OPC_Decode, + 231, + 17, + 97, // Opcode: ORi_MM + /* 4378 */ MCD_OPC_FilterValue, + 21, + 197, + 5, + 0, // Skip to: 5860 + /* 4383 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 4386 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4400 + /* 4391 */ MCD_OPC_CheckPredicate, + 14, + 72, + 8, + 0, // Skip to: 6516 + /* 4396 */ MCD_OPC_Decode, + 175, + 15, + 98, // Opcode: MADD_S_MM + /* 4400 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4414 + /* 4405 */ MCD_OPC_CheckPredicate, + 14, + 58, + 8, + 0, // Skip to: 6516 + /* 4410 */ MCD_OPC_Decode, + 204, + 17, + 98, // Opcode: NMADD_S_MM + /* 4414 */ MCD_OPC_FilterValue, + 8, + 59, + 0, + 0, // Skip to: 4478 + /* 4419 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 4422 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4436 + /* 4427 */ MCD_OPC_CheckPredicate, + 13, + 36, + 8, + 0, // Skip to: 6516 + /* 4432 */ MCD_OPC_Decode, + 134, + 15, + 99, // Opcode: LWXC1_MM + /* 4436 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4450 + /* 4441 */ MCD_OPC_CheckPredicate, + 13, + 22, + 8, + 0, // Skip to: 6516 + /* 4446 */ MCD_OPC_Decode, + 164, + 21, + 99, // Opcode: SWXC1_MM + /* 4450 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 4464 + /* 4455 */ MCD_OPC_CheckPredicate, + 15, + 8, + 8, + 0, // Skip to: 6516 + /* 4460 */ MCD_OPC_Decode, + 223, + 14, + 100, // Opcode: LUXC1_MM + /* 4464 */ MCD_OPC_FilterValue, + 6, + 255, + 7, + 0, // Skip to: 6516 + /* 4469 */ MCD_OPC_CheckPredicate, + 15, + 250, + 7, + 0, // Skip to: 6516 + /* 4474 */ MCD_OPC_Decode, + 132, + 21, + 100, // Opcode: SUXC1_MM + /* 4478 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 4492 + /* 4483 */ MCD_OPC_CheckPredicate, + 16, + 236, + 7, + 0, // Skip to: 6516 + /* 4488 */ MCD_OPC_Decode, + 167, + 15, + 101, // Opcode: MADD_D32_MM + /* 4492 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 4506 + /* 4497 */ MCD_OPC_CheckPredicate, + 16, + 222, + 7, + 0, // Skip to: 6516 + /* 4502 */ MCD_OPC_Decode, + 201, + 17, + 101, // Opcode: NMADD_D32_MM + /* 4506 */ MCD_OPC_FilterValue, + 32, + 101, + 0, + 0, // Skip to: 4612 + /* 4511 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 4514 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4535 + /* 4519 */ MCD_OPC_CheckPredicate, + 13, + 200, + 7, + 0, // Skip to: 6516 + /* 4524 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 193, + 7, + 0, // Skip to: 6516 + /* 4531 */ MCD_OPC_Decode, + 169, + 16, + 102, // Opcode: MOVF_S_MM + /* 4535 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 4556 + /* 4540 */ MCD_OPC_CheckPredicate, + 13, + 179, + 7, + 0, // Skip to: 6516 + /* 4545 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 172, + 7, + 0, // Skip to: 6516 + /* 4552 */ MCD_OPC_Decode, + 189, + 16, + 102, // Opcode: MOVT_S_MM + /* 4556 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 4570 + /* 4561 */ MCD_OPC_CheckPredicate, + 6, + 158, + 7, + 0, // Skip to: 6516 + /* 4566 */ MCD_OPC_Decode, + 166, + 18, + 103, // Opcode: PREFX_MM + /* 4570 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 4591 + /* 4575 */ MCD_OPC_CheckPredicate, + 17, + 144, + 7, + 0, // Skip to: 6516 + /* 4580 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 137, + 7, + 0, // Skip to: 6516 + /* 4587 */ MCD_OPC_Decode, + 163, + 16, + 104, // Opcode: MOVF_D32_MM + /* 4591 */ MCD_OPC_FilterValue, + 9, + 128, + 7, + 0, // Skip to: 6516 + /* 4596 */ MCD_OPC_CheckPredicate, + 17, + 123, + 7, + 0, // Skip to: 6516 + /* 4601 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 116, + 7, + 0, // Skip to: 6516 + /* 4608 */ MCD_OPC_Decode, + 183, + 16, + 104, // Opcode: MOVT_D32_MM + /* 4612 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 4626 + /* 4617 */ MCD_OPC_CheckPredicate, + 14, + 102, + 7, + 0, // Skip to: 6516 + /* 4622 */ MCD_OPC_Decode, + 226, + 16, + 98, // Opcode: MSUB_S_MM + /* 4626 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 4640 + /* 4631 */ MCD_OPC_CheckPredicate, + 14, + 88, + 7, + 0, // Skip to: 6516 + /* 4636 */ MCD_OPC_Decode, + 209, + 17, + 98, // Opcode: NMSUB_S_MM + /* 4640 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 4654 + /* 4645 */ MCD_OPC_CheckPredicate, + 16, + 74, + 7, + 0, // Skip to: 6516 + /* 4650 */ MCD_OPC_Decode, + 218, + 16, + 101, // Opcode: MSUB_D32_MM + /* 4654 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 4668 + /* 4659 */ MCD_OPC_CheckPredicate, + 16, + 60, + 7, + 0, // Skip to: 6516 + /* 4664 */ MCD_OPC_Decode, + 206, + 17, + 101, // Opcode: NMSUB_D32_MM + /* 4668 */ MCD_OPC_FilterValue, + 48, + 59, + 0, + 0, // Skip to: 4732 + /* 4673 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 4676 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 4690 + /* 4681 */ MCD_OPC_CheckPredicate, + 18, + 38, + 7, + 0, // Skip to: 6516 + /* 4686 */ MCD_OPC_Decode, + 146, + 12, + 105, // Opcode: FADD_D32_MM + /* 4690 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 4704 + /* 4695 */ MCD_OPC_CheckPredicate, + 18, + 24, + 7, + 0, // Skip to: 6516 + /* 4700 */ MCD_OPC_Decode, + 163, + 13, + 105, // Opcode: FSUB_D32_MM + /* 4704 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 4718 + /* 4709 */ MCD_OPC_CheckPredicate, + 18, + 10, + 7, + 0, // Skip to: 6516 + /* 4714 */ MCD_OPC_Decode, + 247, + 12, + 105, // Opcode: FMUL_D32_MM + /* 4718 */ MCD_OPC_FilterValue, + 7, + 1, + 7, + 0, // Skip to: 6516 + /* 4723 */ MCD_OPC_CheckPredicate, + 18, + 252, + 6, + 0, // Skip to: 6516 + /* 4728 */ MCD_OPC_Decode, + 185, + 12, + 105, // Opcode: FDIV_D32_MM + /* 4732 */ MCD_OPC_FilterValue, + 56, + 59, + 0, + 0, // Skip to: 4796 + /* 4737 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 4740 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4754 + /* 4745 */ MCD_OPC_CheckPredicate, + 13, + 230, + 6, + 0, // Skip to: 6516 + /* 4750 */ MCD_OPC_Decode, + 181, + 16, + 106, // Opcode: MOVN_I_S_MM + /* 4754 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4768 + /* 4759 */ MCD_OPC_CheckPredicate, + 13, + 216, + 6, + 0, // Skip to: 6516 + /* 4764 */ MCD_OPC_Decode, + 201, + 16, + 106, // Opcode: MOVZ_I_S_MM + /* 4768 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 4782 + /* 4773 */ MCD_OPC_CheckPredicate, + 17, + 202, + 6, + 0, // Skip to: 6516 + /* 4778 */ MCD_OPC_Decode, + 175, + 16, + 107, // Opcode: MOVN_I_D32_MM + /* 4782 */ MCD_OPC_FilterValue, + 5, + 193, + 6, + 0, // Skip to: 6516 + /* 4787 */ MCD_OPC_CheckPredicate, + 17, + 188, + 6, + 0, // Skip to: 6516 + /* 4792 */ MCD_OPC_Decode, + 195, + 16, + 107, // Opcode: MOVZ_I_D32_MM + /* 4796 */ MCD_OPC_FilterValue, + 59, + 91, + 2, + 0, // Skip to: 5404 + /* 4801 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 4804 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4825 + /* 4809 */ MCD_OPC_CheckPredicate, + 19, + 166, + 6, + 0, // Skip to: 6516 + /* 4814 */ MCD_OPC_CheckField, + 13, + 3, + 1, + 159, + 6, + 0, // Skip to: 6516 + /* 4821 */ MCD_OPC_Decode, + 216, + 15, + 108, // Opcode: MFC1_MM + /* 4825 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 4846 + /* 4830 */ MCD_OPC_CheckPredicate, + 18, + 145, + 6, + 0, // Skip to: 6516 + /* 4835 */ MCD_OPC_CheckField, + 13, + 3, + 1, + 138, + 6, + 0, // Skip to: 6516 + /* 4842 */ MCD_OPC_Decode, + 236, + 12, + 109, // Opcode: FMOV_D32_MM + /* 4846 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 4882 + /* 4851 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4854 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4868 + /* 4859 */ MCD_OPC_CheckPredicate, + 20, + 116, + 6, + 0, // Skip to: 6516 + /* 4864 */ MCD_OPC_Decode, + 219, + 9, + 110, // Opcode: CVT_L_S_MM + /* 4868 */ MCD_OPC_FilterValue, + 2, + 107, + 6, + 0, // Skip to: 6516 + /* 4873 */ MCD_OPC_CheckPredicate, + 20, + 102, + 6, + 0, // Skip to: 6516 + /* 4878 */ MCD_OPC_Decode, + 216, + 9, + 111, // Opcode: CVT_L_D64_MM + /* 4882 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 4896 + /* 4887 */ MCD_OPC_CheckPredicate, + 13, + 88, + 6, + 0, // Skip to: 6516 + /* 4892 */ MCD_OPC_Decode, + 167, + 16, + 112, // Opcode: MOVF_I_MM + /* 4896 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 4932 + /* 4901 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4904 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4918 + /* 4909 */ MCD_OPC_CheckPredicate, + 19, + 66, + 6, + 0, // Skip to: 6516 + /* 4914 */ MCD_OPC_Decode, + 221, + 18, + 113, // Opcode: RSQRT_S_MM + /* 4918 */ MCD_OPC_FilterValue, + 2, + 57, + 6, + 0, // Skip to: 6516 + /* 4923 */ MCD_OPC_CheckPredicate, + 18, + 52, + 6, + 0, // Skip to: 6516 + /* 4928 */ MCD_OPC_Decode, + 217, + 18, + 109, // Opcode: RSQRT_D32_MM + /* 4932 */ MCD_OPC_FilterValue, + 13, + 31, + 0, + 0, // Skip to: 4968 + /* 4937 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4940 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4954 + /* 4945 */ MCD_OPC_CheckPredicate, + 19, + 30, + 6, + 0, // Skip to: 6516 + /* 4950 */ MCD_OPC_Decode, + 143, + 12, + 113, // Opcode: FABS_S_MM + /* 4954 */ MCD_OPC_FilterValue, + 1, + 21, + 6, + 0, // Skip to: 6516 + /* 4959 */ MCD_OPC_CheckPredicate, + 18, + 16, + 6, + 0, // Skip to: 6516 + /* 4964 */ MCD_OPC_Decode, + 139, + 12, + 109, // Opcode: FABS_D32_MM + /* 4968 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 4989 + /* 4973 */ MCD_OPC_CheckPredicate, + 19, + 2, + 6, + 0, // Skip to: 6516 + /* 4978 */ MCD_OPC_CheckField, + 13, + 3, + 1, + 251, + 5, + 0, // Skip to: 6516 + /* 4985 */ MCD_OPC_Decode, + 232, + 16, + 114, // Opcode: MTC1_MM + /* 4989 */ MCD_OPC_FilterValue, + 36, + 31, + 0, + 0, // Skip to: 5025 + /* 4994 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4997 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5011 + /* 5002 */ MCD_OPC_CheckPredicate, + 19, + 229, + 5, + 0, // Skip to: 6516 + /* 5007 */ MCD_OPC_Decode, + 240, + 9, + 113, // Opcode: CVT_W_S_MM + /* 5011 */ MCD_OPC_FilterValue, + 2, + 220, + 5, + 0, // Skip to: 6516 + /* 5016 */ MCD_OPC_CheckPredicate, + 18, + 215, + 5, + 0, // Skip to: 6516 + /* 5021 */ MCD_OPC_Decode, + 236, + 9, + 115, // Opcode: CVT_W_D32_MM + /* 5025 */ MCD_OPC_FilterValue, + 37, + 9, + 0, + 0, // Skip to: 5039 + /* 5030 */ MCD_OPC_CheckPredicate, + 13, + 201, + 5, + 0, // Skip to: 6516 + /* 5035 */ MCD_OPC_Decode, + 187, + 16, + 112, // Opcode: MOVT_I_MM + /* 5039 */ MCD_OPC_FilterValue, + 40, + 31, + 0, + 0, // Skip to: 5075 + /* 5044 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5047 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5061 + /* 5052 */ MCD_OPC_CheckPredicate, + 19, + 179, + 5, + 0, // Skip to: 6516 + /* 5057 */ MCD_OPC_Decode, + 159, + 13, + 113, // Opcode: FSQRT_S_MM + /* 5061 */ MCD_OPC_FilterValue, + 2, + 170, + 5, + 0, // Skip to: 6516 + /* 5066 */ MCD_OPC_CheckPredicate, + 18, + 165, + 5, + 0, // Skip to: 6516 + /* 5071 */ MCD_OPC_Decode, + 155, + 13, + 109, // Opcode: FSQRT_D32_MM + /* 5075 */ MCD_OPC_FilterValue, + 44, + 59, + 0, + 0, // Skip to: 5139 + /* 5080 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5083 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5097 + /* 5088 */ MCD_OPC_CheckPredicate, + 19, + 143, + 5, + 0, // Skip to: 6516 + /* 5093 */ MCD_OPC_Decode, + 223, + 12, + 113, // Opcode: FLOOR_W_S_MM + /* 5097 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5111 + /* 5102 */ MCD_OPC_CheckPredicate, + 19, + 129, + 5, + 0, // Skip to: 6516 + /* 5107 */ MCD_OPC_Decode, + 252, + 21, + 113, // Opcode: TRUNC_W_S_MM + /* 5111 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 5125 + /* 5116 */ MCD_OPC_CheckPredicate, + 18, + 115, + 5, + 0, // Skip to: 6516 + /* 5121 */ MCD_OPC_Decode, + 221, + 12, + 115, // Opcode: FLOOR_W_MM + /* 5125 */ MCD_OPC_FilterValue, + 3, + 106, + 5, + 0, // Skip to: 6516 + /* 5130 */ MCD_OPC_CheckPredicate, + 18, + 101, + 5, + 0, // Skip to: 6516 + /* 5135 */ MCD_OPC_Decode, + 250, + 21, + 115, // Opcode: TRUNC_W_MM + /* 5139 */ MCD_OPC_FilterValue, + 45, + 16, + 0, + 0, // Skip to: 5160 + /* 5144 */ MCD_OPC_CheckPredicate, + 18, + 87, + 5, + 0, // Skip to: 6516 + /* 5149 */ MCD_OPC_CheckField, + 13, + 3, + 1, + 80, + 5, + 0, // Skip to: 6516 + /* 5156 */ MCD_OPC_Decode, + 128, + 13, + 109, // Opcode: FNEG_D32_MM + /* 5160 */ MCD_OPC_FilterValue, + 64, + 31, + 0, + 0, // Skip to: 5196 + /* 5165 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5168 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5182 + /* 5173 */ MCD_OPC_CheckPredicate, + 19, + 58, + 5, + 0, // Skip to: 6516 + /* 5178 */ MCD_OPC_Decode, + 175, + 8, + 116, // Opcode: CFC1_MM + /* 5182 */ MCD_OPC_FilterValue, + 1, + 49, + 5, + 0, // Skip to: 6516 + /* 5187 */ MCD_OPC_CheckPredicate, + 18, + 44, + 5, + 0, // Skip to: 6516 + /* 5192 */ MCD_OPC_Decode, + 224, + 15, + 117, // Opcode: MFHC1_D32_MM + /* 5196 */ MCD_OPC_FilterValue, + 72, + 31, + 0, + 0, // Skip to: 5232 + /* 5201 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5204 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5218 + /* 5209 */ MCD_OPC_CheckPredicate, + 19, + 22, + 5, + 0, // Skip to: 6516 + /* 5214 */ MCD_OPC_Decode, + 188, + 18, + 113, // Opcode: RECIP_S_MM + /* 5218 */ MCD_OPC_FilterValue, + 2, + 13, + 5, + 0, // Skip to: 6516 + /* 5223 */ MCD_OPC_CheckPredicate, + 18, + 8, + 5, + 0, // Skip to: 6516 + /* 5228 */ MCD_OPC_Decode, + 184, + 18, + 109, // Opcode: RECIP_D32_MM + /* 5232 */ MCD_OPC_FilterValue, + 77, + 31, + 0, + 0, // Skip to: 5268 + /* 5237 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5240 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5254 + /* 5245 */ MCD_OPC_CheckPredicate, + 18, + 242, + 4, + 0, // Skip to: 6516 + /* 5250 */ MCD_OPC_Decode, + 206, + 9, + 118, // Opcode: CVT_D32_S_MM + /* 5254 */ MCD_OPC_FilterValue, + 1, + 233, + 4, + 0, // Skip to: 6516 + /* 5259 */ MCD_OPC_CheckPredicate, + 18, + 228, + 4, + 0, // Skip to: 6516 + /* 5264 */ MCD_OPC_Decode, + 208, + 9, + 118, // Opcode: CVT_D32_W_MM + /* 5268 */ MCD_OPC_FilterValue, + 96, + 31, + 0, + 0, // Skip to: 5304 + /* 5273 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5276 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5290 + /* 5281 */ MCD_OPC_CheckPredicate, + 19, + 206, + 4, + 0, // Skip to: 6516 + /* 5286 */ MCD_OPC_Decode, + 202, + 9, + 119, // Opcode: CTC1_MM + /* 5290 */ MCD_OPC_FilterValue, + 1, + 197, + 4, + 0, // Skip to: 6516 + /* 5295 */ MCD_OPC_CheckPredicate, + 18, + 192, + 4, + 0, // Skip to: 6516 + /* 5300 */ MCD_OPC_Decode, + 240, + 16, + 120, // Opcode: MTHC1_D32_MM + /* 5304 */ MCD_OPC_FilterValue, + 108, + 59, + 0, + 0, // Skip to: 5368 + /* 5309 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5312 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5326 + /* 5317 */ MCD_OPC_CheckPredicate, + 19, + 170, + 4, + 0, // Skip to: 6516 + /* 5322 */ MCD_OPC_Decode, + 164, + 8, + 113, // Opcode: CEIL_W_S_MM + /* 5326 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5340 + /* 5331 */ MCD_OPC_CheckPredicate, + 19, + 156, + 4, + 0, // Skip to: 6516 + /* 5336 */ MCD_OPC_Decode, + 214, + 18, + 113, // Opcode: ROUND_W_S_MM + /* 5340 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 5354 + /* 5345 */ MCD_OPC_CheckPredicate, + 18, + 142, + 4, + 0, // Skip to: 6516 + /* 5350 */ MCD_OPC_Decode, + 162, + 8, + 115, // Opcode: CEIL_W_MM + /* 5354 */ MCD_OPC_FilterValue, + 3, + 133, + 4, + 0, // Skip to: 6516 + /* 5359 */ MCD_OPC_CheckPredicate, + 18, + 128, + 4, + 0, // Skip to: 6516 + /* 5364 */ MCD_OPC_Decode, + 212, + 18, + 115, // Opcode: ROUND_W_MM + /* 5368 */ MCD_OPC_FilterValue, + 109, + 119, + 4, + 0, // Skip to: 6516 + /* 5373 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5376 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5390 + /* 5381 */ MCD_OPC_CheckPredicate, + 18, + 106, + 4, + 0, // Skip to: 6516 + /* 5386 */ MCD_OPC_Decode, + 225, + 9, + 115, // Opcode: CVT_S_D32_MM + /* 5390 */ MCD_OPC_FilterValue, + 1, + 97, + 4, + 0, // Skip to: 6516 + /* 5395 */ MCD_OPC_CheckPredicate, + 19, + 92, + 4, + 0, // Skip to: 6516 + /* 5400 */ MCD_OPC_Decode, + 233, + 9, + 113, // Opcode: CVT_S_W_MM + /* 5404 */ MCD_OPC_FilterValue, + 60, + 83, + 4, + 0, // Skip to: 6516 + /* 5409 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 5412 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5426 + /* 5417 */ MCD_OPC_CheckPredicate, + 13, + 70, + 4, + 0, // Skip to: 6516 + /* 5422 */ MCD_OPC_Decode, + 253, + 9, + 121, // Opcode: C_F_S_MM + /* 5426 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5440 + /* 5431 */ MCD_OPC_CheckPredicate, + 13, + 56, + 4, + 0, // Skip to: 6516 + /* 5436 */ MCD_OPC_Decode, + 209, + 10, + 121, // Opcode: C_UN_S_MM + /* 5440 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 5454 + /* 5445 */ MCD_OPC_CheckPredicate, + 13, + 42, + 4, + 0, // Skip to: 6516 + /* 5450 */ MCD_OPC_Decode, + 247, + 9, + 121, // Opcode: C_EQ_S_MM + /* 5454 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 5468 + /* 5459 */ MCD_OPC_CheckPredicate, + 13, + 28, + 4, + 0, // Skip to: 6516 + /* 5464 */ MCD_OPC_Decode, + 191, + 10, + 121, // Opcode: C_UEQ_S_MM + /* 5468 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 5482 + /* 5473 */ MCD_OPC_CheckPredicate, + 13, + 14, + 4, + 0, // Skip to: 6516 + /* 5478 */ MCD_OPC_Decode, + 173, + 10, + 121, // Opcode: C_OLT_S_MM + /* 5482 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 5496 + /* 5487 */ MCD_OPC_CheckPredicate, + 13, + 0, + 4, + 0, // Skip to: 6516 + /* 5492 */ MCD_OPC_Decode, + 203, + 10, + 121, // Opcode: C_ULT_S_MM + /* 5496 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 5510 + /* 5501 */ MCD_OPC_CheckPredicate, + 13, + 242, + 3, + 0, // Skip to: 6516 + /* 5506 */ MCD_OPC_Decode, + 167, + 10, + 121, // Opcode: C_OLE_S_MM + /* 5510 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 5524 + /* 5515 */ MCD_OPC_CheckPredicate, + 13, + 228, + 3, + 0, // Skip to: 6516 + /* 5520 */ MCD_OPC_Decode, + 197, + 10, + 121, // Opcode: C_ULE_S_MM + /* 5524 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 5538 + /* 5529 */ MCD_OPC_CheckPredicate, + 13, + 214, + 3, + 0, // Skip to: 6516 + /* 5534 */ MCD_OPC_Decode, + 185, + 10, + 121, // Opcode: C_SF_S_MM + /* 5538 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 5552 + /* 5543 */ MCD_OPC_CheckPredicate, + 13, + 200, + 3, + 0, // Skip to: 6516 + /* 5548 */ MCD_OPC_Decode, + 149, + 10, + 121, // Opcode: C_NGLE_S_MM + /* 5552 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 5566 + /* 5557 */ MCD_OPC_CheckPredicate, + 13, + 186, + 3, + 0, // Skip to: 6516 + /* 5562 */ MCD_OPC_Decode, + 179, + 10, + 121, // Opcode: C_SEQ_S_MM + /* 5566 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 5580 + /* 5571 */ MCD_OPC_CheckPredicate, + 13, + 172, + 3, + 0, // Skip to: 6516 + /* 5576 */ MCD_OPC_Decode, + 155, + 10, + 121, // Opcode: C_NGL_S_MM + /* 5580 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 5594 + /* 5585 */ MCD_OPC_CheckPredicate, + 13, + 158, + 3, + 0, // Skip to: 6516 + /* 5590 */ MCD_OPC_Decode, + 137, + 10, + 121, // Opcode: C_LT_S_MM + /* 5594 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 5608 + /* 5599 */ MCD_OPC_CheckPredicate, + 13, + 144, + 3, + 0, // Skip to: 6516 + /* 5604 */ MCD_OPC_Decode, + 143, + 10, + 121, // Opcode: C_NGE_S_MM + /* 5608 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 5622 + /* 5613 */ MCD_OPC_CheckPredicate, + 13, + 130, + 3, + 0, // Skip to: 6516 + /* 5618 */ MCD_OPC_Decode, + 131, + 10, + 121, // Opcode: C_LE_S_MM + /* 5622 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 5636 + /* 5627 */ MCD_OPC_CheckPredicate, + 13, + 116, + 3, + 0, // Skip to: 6516 + /* 5632 */ MCD_OPC_Decode, + 161, + 10, + 121, // Opcode: C_NGT_S_MM + /* 5636 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 5650 + /* 5641 */ MCD_OPC_CheckPredicate, + 17, + 102, + 3, + 0, // Skip to: 6516 + /* 5646 */ MCD_OPC_Decode, + 249, + 9, + 122, // Opcode: C_F_D32_MM + /* 5650 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 5664 + /* 5655 */ MCD_OPC_CheckPredicate, + 17, + 88, + 3, + 0, // Skip to: 6516 + /* 5660 */ MCD_OPC_Decode, + 205, + 10, + 122, // Opcode: C_UN_D32_MM + /* 5664 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 5678 + /* 5669 */ MCD_OPC_CheckPredicate, + 17, + 74, + 3, + 0, // Skip to: 6516 + /* 5674 */ MCD_OPC_Decode, + 243, + 9, + 122, // Opcode: C_EQ_D32_MM + /* 5678 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 5692 + /* 5683 */ MCD_OPC_CheckPredicate, + 17, + 60, + 3, + 0, // Skip to: 6516 + /* 5688 */ MCD_OPC_Decode, + 187, + 10, + 122, // Opcode: C_UEQ_D32_MM + /* 5692 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 5706 + /* 5697 */ MCD_OPC_CheckPredicate, + 17, + 46, + 3, + 0, // Skip to: 6516 + /* 5702 */ MCD_OPC_Decode, + 169, + 10, + 122, // Opcode: C_OLT_D32_MM + /* 5706 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 5720 + /* 5711 */ MCD_OPC_CheckPredicate, + 17, + 32, + 3, + 0, // Skip to: 6516 + /* 5716 */ MCD_OPC_Decode, + 199, + 10, + 122, // Opcode: C_ULT_D32_MM + /* 5720 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 5734 + /* 5725 */ MCD_OPC_CheckPredicate, + 17, + 18, + 3, + 0, // Skip to: 6516 + /* 5730 */ MCD_OPC_Decode, + 163, + 10, + 122, // Opcode: C_OLE_D32_MM + /* 5734 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 5748 + /* 5739 */ MCD_OPC_CheckPredicate, + 17, + 4, + 3, + 0, // Skip to: 6516 + /* 5744 */ MCD_OPC_Decode, + 193, + 10, + 122, // Opcode: C_ULE_D32_MM + /* 5748 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 5762 + /* 5753 */ MCD_OPC_CheckPredicate, + 17, + 246, + 2, + 0, // Skip to: 6516 + /* 5758 */ MCD_OPC_Decode, + 181, + 10, + 122, // Opcode: C_SF_D32_MM + /* 5762 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 5776 + /* 5767 */ MCD_OPC_CheckPredicate, + 17, + 232, + 2, + 0, // Skip to: 6516 + /* 5772 */ MCD_OPC_Decode, + 145, + 10, + 122, // Opcode: C_NGLE_D32_MM + /* 5776 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 5790 + /* 5781 */ MCD_OPC_CheckPredicate, + 17, + 218, + 2, + 0, // Skip to: 6516 + /* 5786 */ MCD_OPC_Decode, + 175, + 10, + 122, // Opcode: C_SEQ_D32_MM + /* 5790 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 5804 + /* 5795 */ MCD_OPC_CheckPredicate, + 17, + 204, + 2, + 0, // Skip to: 6516 + /* 5800 */ MCD_OPC_Decode, + 151, + 10, + 122, // Opcode: C_NGL_D32_MM + /* 5804 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 5818 + /* 5809 */ MCD_OPC_CheckPredicate, + 17, + 190, + 2, + 0, // Skip to: 6516 + /* 5814 */ MCD_OPC_Decode, + 133, + 10, + 122, // Opcode: C_LT_D32_MM + /* 5818 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 5832 + /* 5823 */ MCD_OPC_CheckPredicate, + 17, + 176, + 2, + 0, // Skip to: 6516 + /* 5828 */ MCD_OPC_Decode, + 139, + 10, + 122, // Opcode: C_NGE_D32_MM + /* 5832 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 5846 + /* 5837 */ MCD_OPC_CheckPredicate, + 17, + 162, + 2, + 0, // Skip to: 6516 + /* 5842 */ MCD_OPC_Decode, + 255, + 9, + 122, // Opcode: C_LE_D32_MM + /* 5846 */ MCD_OPC_FilterValue, + 31, + 153, + 2, + 0, // Skip to: 6516 + /* 5851 */ MCD_OPC_CheckPredicate, + 17, + 148, + 2, + 0, // Skip to: 6516 + /* 5856 */ MCD_OPC_Decode, + 157, + 10, + 122, // Opcode: C_NGT_D32_MM + /* 5860 */ MCD_OPC_FilterValue, + 22, + 48, + 0, + 0, // Skip to: 5913 + /* 5865 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 5868 */ MCD_OPC_FilterValue, + 197, + 1, + 9, + 0, + 0, // Skip to: 5883 + /* 5874 */ MCD_OPC_CheckPredicate, + 8, + 125, + 2, + 0, // Skip to: 6516 + /* 5879 */ MCD_OPC_Decode, + 233, + 8, + 43, // Opcode: CMPGU_EQ_QB_MM + /* 5883 */ MCD_OPC_FilterValue, + 133, + 2, + 9, + 0, + 0, // Skip to: 5898 + /* 5889 */ MCD_OPC_CheckPredicate, + 8, + 110, + 2, + 0, // Skip to: 6516 + /* 5894 */ MCD_OPC_Decode, + 237, + 8, + 43, // Opcode: CMPGU_LT_QB_MM + /* 5898 */ MCD_OPC_FilterValue, + 197, + 2, + 100, + 2, + 0, // Skip to: 6516 + /* 5904 */ MCD_OPC_CheckPredicate, + 8, + 95, + 2, + 0, // Skip to: 6516 + /* 5909 */ MCD_OPC_Decode, + 235, + 8, + 43, // Opcode: CMPGU_LE_QB_MM + /* 5913 */ MCD_OPC_FilterValue, + 24, + 99, + 1, + 0, // Skip to: 6273 + /* 5918 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5921 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5935 + /* 5926 */ MCD_OPC_CheckPredicate, + 6, + 73, + 2, + 0, // Skip to: 6516 + /* 5931 */ MCD_OPC_Decode, + 245, + 14, + 88, // Opcode: LWL_MM + /* 5935 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5949 + /* 5940 */ MCD_OPC_CheckPredicate, + 6, + 59, + 2, + 0, // Skip to: 6516 + /* 5945 */ MCD_OPC_Decode, + 128, + 15, + 88, // Opcode: LWR_MM + /* 5949 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 5963 + /* 5954 */ MCD_OPC_CheckPredicate, + 6, + 45, + 2, + 0, // Skip to: 6516 + /* 5959 */ MCD_OPC_Decode, + 167, + 18, + 89, // Opcode: PREF_MM + /* 5963 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 5977 + /* 5968 */ MCD_OPC_CheckPredicate, + 6, + 31, + 2, + 0, // Skip to: 6516 + /* 5973 */ MCD_OPC_Decode, + 214, + 14, + 88, // Opcode: LL_MM + /* 5977 */ MCD_OPC_FilterValue, + 6, + 115, + 0, + 0, // Skip to: 6097 + /* 5982 */ MCD_OPC_ExtractField, + 9, + 3, // Inst{11-9} ... + /* 5985 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5999 + /* 5990 */ MCD_OPC_CheckPredicate, + 21, + 9, + 2, + 0, // Skip to: 6516 + /* 5995 */ MCD_OPC_Decode, + 165, + 14, + 123, // Opcode: LBuE_MM + /* 5999 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6013 + /* 6004 */ MCD_OPC_CheckPredicate, + 21, + 251, + 1, + 0, // Skip to: 6516 + /* 6009 */ MCD_OPC_Decode, + 203, + 14, + 123, // Opcode: LHuE_MM + /* 6013 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6027 + /* 6018 */ MCD_OPC_CheckPredicate, + 22, + 237, + 1, + 0, // Skip to: 6516 + /* 6023 */ MCD_OPC_Decode, + 244, + 14, + 123, // Opcode: LWLE_MM + /* 6027 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 6041 + /* 6032 */ MCD_OPC_CheckPredicate, + 22, + 223, + 1, + 0, // Skip to: 6516 + /* 6037 */ MCD_OPC_Decode, + 255, + 14, + 123, // Opcode: LWRE_MM + /* 6041 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 6055 + /* 6046 */ MCD_OPC_CheckPredicate, + 21, + 209, + 1, + 0, // Skip to: 6516 + /* 6051 */ MCD_OPC_Decode, + 155, + 14, + 123, // Opcode: LBE_MM + /* 6055 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 6069 + /* 6060 */ MCD_OPC_CheckPredicate, + 21, + 195, + 1, + 0, // Skip to: 6516 + /* 6065 */ MCD_OPC_Decode, + 195, + 14, + 123, // Opcode: LHE_MM + /* 6069 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 6083 + /* 6074 */ MCD_OPC_CheckPredicate, + 21, + 181, + 1, + 0, // Skip to: 6516 + /* 6079 */ MCD_OPC_Decode, + 213, + 14, + 123, // Opcode: LLE_MM + /* 6083 */ MCD_OPC_FilterValue, + 7, + 172, + 1, + 0, // Skip to: 6516 + /* 6088 */ MCD_OPC_CheckPredicate, + 21, + 167, + 1, + 0, // Skip to: 6516 + /* 6093 */ MCD_OPC_Decode, + 239, + 14, + 123, // Opcode: LWE_MM + /* 6097 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 6111 + /* 6102 */ MCD_OPC_CheckPredicate, + 6, + 153, + 1, + 0, // Skip to: 6516 + /* 6107 */ MCD_OPC_Decode, + 151, + 21, + 88, // Opcode: SWL_MM + /* 6111 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 6125 + /* 6116 */ MCD_OPC_CheckPredicate, + 6, + 139, + 1, + 0, // Skip to: 6516 + /* 6121 */ MCD_OPC_Decode, + 160, + 21, + 88, // Opcode: SWR_MM + /* 6125 */ MCD_OPC_FilterValue, + 10, + 115, + 0, + 0, // Skip to: 6245 + /* 6130 */ MCD_OPC_ExtractField, + 9, + 3, // Inst{11-9} ... + /* 6133 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6147 + /* 6138 */ MCD_OPC_CheckPredicate, + 22, + 117, + 1, + 0, // Skip to: 6516 + /* 6143 */ MCD_OPC_Decode, + 150, + 21, + 123, // Opcode: SWLE_MM + /* 6147 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6161 + /* 6152 */ MCD_OPC_CheckPredicate, + 22, + 103, + 1, + 0, // Skip to: 6516 + /* 6157 */ MCD_OPC_Decode, + 159, + 21, + 123, // Opcode: SWRE_MM + /* 6161 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6175 + /* 6166 */ MCD_OPC_CheckPredicate, + 21, + 89, + 1, + 0, // Skip to: 6516 + /* 6171 */ MCD_OPC_Decode, + 165, + 18, + 124, // Opcode: PREFE_MM + /* 6175 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 6189 + /* 6180 */ MCD_OPC_CheckPredicate, + 21, + 75, + 1, + 0, // Skip to: 6516 + /* 6185 */ MCD_OPC_Decode, + 151, + 8, + 124, // Opcode: CACHEE_MM + /* 6189 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 6203 + /* 6194 */ MCD_OPC_CheckPredicate, + 21, + 61, + 1, + 0, // Skip to: 6516 + /* 6199 */ MCD_OPC_Decode, + 239, + 18, + 123, // Opcode: SBE_MM + /* 6203 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 6217 + /* 6208 */ MCD_OPC_CheckPredicate, + 21, + 47, + 1, + 0, // Skip to: 6516 + /* 6213 */ MCD_OPC_Decode, + 176, + 19, + 123, // Opcode: SHE_MM + /* 6217 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 6231 + /* 6222 */ MCD_OPC_CheckPredicate, + 21, + 33, + 1, + 0, // Skip to: 6516 + /* 6227 */ MCD_OPC_Decode, + 248, + 18, + 123, // Opcode: SCE_MM + /* 6231 */ MCD_OPC_FilterValue, + 7, + 24, + 1, + 0, // Skip to: 6516 + /* 6236 */ MCD_OPC_CheckPredicate, + 21, + 19, + 1, + 0, // Skip to: 6516 + /* 6241 */ MCD_OPC_Decode, + 146, + 21, + 123, // Opcode: SWE_MM + /* 6245 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 6259 + /* 6250 */ MCD_OPC_CheckPredicate, + 6, + 5, + 1, + 0, // Skip to: 6516 + /* 6255 */ MCD_OPC_Decode, + 249, + 18, + 88, // Opcode: SC_MM + /* 6259 */ MCD_OPC_FilterValue, + 14, + 252, + 0, + 0, // Skip to: 6516 + /* 6264 */ MCD_OPC_CheckPredicate, + 6, + 247, + 0, + 0, // Skip to: 6516 + /* 6269 */ MCD_OPC_Decode, + 131, + 15, + 88, // Opcode: LWU_MM + /* 6273 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 6287 + /* 6278 */ MCD_OPC_CheckPredicate, + 6, + 233, + 0, + 0, // Skip to: 6516 + /* 6283 */ MCD_OPC_Decode, + 156, + 22, + 97, // Opcode: XORi_MM + /* 6287 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 6301 + /* 6292 */ MCD_OPC_CheckPredicate, + 6, + 219, + 0, + 0, // Skip to: 6516 + /* 6297 */ MCD_OPC_Decode, + 251, + 13, + 125, // Opcode: JALS_MM + /* 6301 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 6315 + /* 6306 */ MCD_OPC_CheckPredicate, + 6, + 205, + 0, + 0, // Skip to: 6516 + /* 6311 */ MCD_OPC_Decode, + 196, + 5, + 126, // Opcode: ADDIUPC_MM + /* 6315 */ MCD_OPC_FilterValue, + 36, + 9, + 0, + 0, // Skip to: 6329 + /* 6320 */ MCD_OPC_CheckPredicate, + 7, + 191, + 0, + 0, // Skip to: 6516 + /* 6325 */ MCD_OPC_Decode, + 134, + 20, + 86, // Opcode: SLTi_MM + /* 6329 */ MCD_OPC_FilterValue, + 37, + 9, + 0, + 0, // Skip to: 6343 + /* 6334 */ MCD_OPC_CheckPredicate, + 6, + 177, + 0, + 0, // Skip to: 6516 + /* 6339 */ MCD_OPC_Decode, + 130, + 7, + 127, // Opcode: BEQ_MM + /* 6343 */ MCD_OPC_FilterValue, + 38, + 10, + 0, + 0, // Skip to: 6358 + /* 6348 */ MCD_OPC_CheckPredicate, + 19, + 163, + 0, + 0, // Skip to: 6516 + /* 6353 */ MCD_OPC_Decode, + 138, + 21, + 128, + 1, // Opcode: SWC1_MM + /* 6358 */ MCD_OPC_FilterValue, + 39, + 10, + 0, + 0, // Skip to: 6373 + /* 6363 */ MCD_OPC_CheckPredicate, + 19, + 148, + 0, + 0, // Skip to: 6516 + /* 6368 */ MCD_OPC_Decode, + 231, + 14, + 128, + 1, // Opcode: LWC1_MM + /* 6373 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 6387 + /* 6378 */ MCD_OPC_CheckPredicate, + 7, + 133, + 0, + 0, // Skip to: 6516 + /* 6383 */ MCD_OPC_Decode, + 137, + 20, + 86, // Opcode: SLTiu_MM + /* 6387 */ MCD_OPC_FilterValue, + 45, + 9, + 0, + 0, // Skip to: 6401 + /* 6392 */ MCD_OPC_CheckPredicate, + 6, + 119, + 0, + 0, // Skip to: 6516 + /* 6397 */ MCD_OPC_Decode, + 233, + 7, + 127, // Opcode: BNE_MM + /* 6401 */ MCD_OPC_FilterValue, + 46, + 10, + 0, + 0, // Skip to: 6416 + /* 6406 */ MCD_OPC_CheckPredicate, + 18, + 105, + 0, + 0, // Skip to: 6516 + /* 6411 */ MCD_OPC_Decode, + 134, + 19, + 128, + 1, // Opcode: SDC1_MM + /* 6416 */ MCD_OPC_FilterValue, + 47, + 10, + 0, + 0, // Skip to: 6431 + /* 6421 */ MCD_OPC_CheckPredicate, + 18, + 90, + 0, + 0, // Skip to: 6516 + /* 6426 */ MCD_OPC_Decode, + 171, + 14, + 128, + 1, // Opcode: LDC1_MM + /* 6431 */ MCD_OPC_FilterValue, + 52, + 9, + 0, + 0, // Skip to: 6445 + /* 6436 */ MCD_OPC_CheckPredicate, + 6, + 75, + 0, + 0, // Skip to: 6516 + /* 6441 */ MCD_OPC_Decode, + 158, + 6, + 97, // Opcode: ANDi_MM + /* 6445 */ MCD_OPC_FilterValue, + 53, + 9, + 0, + 0, // Skip to: 6459 + /* 6450 */ MCD_OPC_CheckPredicate, + 6, + 61, + 0, + 0, // Skip to: 6516 + /* 6455 */ MCD_OPC_Decode, + 145, + 14, + 125, // Opcode: J_MM + /* 6459 */ MCD_OPC_FilterValue, + 60, + 10, + 0, + 0, // Skip to: 6474 + /* 6464 */ MCD_OPC_CheckPredicate, + 6, + 47, + 0, + 0, // Skip to: 6516 + /* 6469 */ MCD_OPC_Decode, + 253, + 13, + 129, + 1, // Opcode: JALX_MM + /* 6474 */ MCD_OPC_FilterValue, + 61, + 9, + 0, + 0, // Skip to: 6488 + /* 6479 */ MCD_OPC_CheckPredicate, + 6, + 32, + 0, + 0, // Skip to: 6516 + /* 6484 */ MCD_OPC_Decode, + 254, + 13, + 125, // Opcode: JAL_MM + /* 6488 */ MCD_OPC_FilterValue, + 62, + 9, + 0, + 0, // Skip to: 6502 + /* 6493 */ MCD_OPC_CheckPredicate, + 7, + 18, + 0, + 0, // Skip to: 6516 + /* 6498 */ MCD_OPC_Decode, + 165, + 21, + 87, // Opcode: SW_MM + /* 6502 */ MCD_OPC_FilterValue, + 63, + 9, + 0, + 0, // Skip to: 6516 + /* 6507 */ MCD_OPC_CheckPredicate, + 7, + 4, + 0, + 0, // Skip to: 6516 + /* 6512 */ MCD_OPC_Decode, + 137, + 15, + 87, // Opcode: LW_MM + /* 6516 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMicroMipsDSP32[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 62, + 10, + 0, + 0, // Skip to: 18 + /* 8 */ MCD_OPC_CheckPredicate, + 8, + 20, + 0, + 0, // Skip to: 33 + /* 13 */ MCD_OPC_Decode, + 144, + 21, + 130, + 1, // Opcode: SWDSP_MM + /* 18 */ MCD_OPC_FilterValue, + 63, + 10, + 0, + 0, // Skip to: 33 + /* 23 */ MCD_OPC_CheckPredicate, + 8, + 5, + 0, + 0, // Skip to: 33 + /* 28 */ MCD_OPC_Decode, + 237, + 14, + 130, + 1, // Opcode: LWDSP_MM + /* 33 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMicroMipsFP6432[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 21, + 39, + 1, + 0, // Skip to: 303 + /* 8 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 11 */ MCD_OPC_FilterValue, + 59, + 48, + 0, + 0, // Skip to: 64 + /* 16 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 19 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 34 + /* 24 */ MCD_OPC_CheckPredicate, + 20, + 48, + 1, + 0, // Skip to: 333 + /* 29 */ MCD_OPC_Decode, + 231, + 16, + 131, + 1, // Opcode: MTC1_D64_MM + /* 34 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 49 + /* 39 */ MCD_OPC_CheckPredicate, + 20, + 33, + 1, + 0, // Skip to: 333 + /* 44 */ MCD_OPC_Decode, + 226, + 15, + 132, + 1, // Opcode: MFHC1_D64_MM + /* 49 */ MCD_OPC_FilterValue, + 7, + 23, + 1, + 0, // Skip to: 333 + /* 54 */ MCD_OPC_CheckPredicate, + 20, + 18, + 1, + 0, // Skip to: 333 + /* 59 */ MCD_OPC_Decode, + 242, + 16, + 133, + 1, // Opcode: MTHC1_D64_MM + /* 64 */ MCD_OPC_FilterValue, + 123, + 16, + 0, + 0, // Skip to: 85 + /* 69 */ MCD_OPC_CheckPredicate, + 20, + 3, + 1, + 0, // Skip to: 333 + /* 74 */ MCD_OPC_CheckField, + 11, + 5, + 4, + 252, + 0, + 0, // Skip to: 333 + /* 81 */ MCD_OPC_Decode, + 238, + 12, + 111, // Opcode: FMOV_D64_MM + /* 85 */ MCD_OPC_FilterValue, + 176, + 2, + 10, + 0, + 0, // Skip to: 101 + /* 91 */ MCD_OPC_CheckPredicate, + 20, + 237, + 0, + 0, // Skip to: 333 + /* 96 */ MCD_OPC_Decode, + 148, + 12, + 134, + 1, // Opcode: FADD_D64_MM + /* 101 */ MCD_OPC_FilterValue, + 187, + 2, + 17, + 0, + 0, // Skip to: 124 + /* 107 */ MCD_OPC_CheckPredicate, + 20, + 221, + 0, + 0, // Skip to: 333 + /* 112 */ MCD_OPC_CheckField, + 11, + 5, + 9, + 214, + 0, + 0, // Skip to: 333 + /* 119 */ MCD_OPC_Decode, + 238, + 9, + 135, + 1, // Opcode: CVT_W_D64_MM + /* 124 */ MCD_OPC_FilterValue, + 240, + 2, + 10, + 0, + 0, // Skip to: 140 + /* 130 */ MCD_OPC_CheckPredicate, + 20, + 198, + 0, + 0, // Skip to: 333 + /* 135 */ MCD_OPC_Decode, + 165, + 13, + 134, + 1, // Opcode: FSUB_D64_MM + /* 140 */ MCD_OPC_FilterValue, + 176, + 3, + 10, + 0, + 0, // Skip to: 156 + /* 146 */ MCD_OPC_CheckPredicate, + 20, + 182, + 0, + 0, // Skip to: 333 + /* 151 */ MCD_OPC_Decode, + 249, + 12, + 134, + 1, // Opcode: FMUL_D64_MM + /* 156 */ MCD_OPC_FilterValue, + 240, + 3, + 10, + 0, + 0, // Skip to: 172 + /* 162 */ MCD_OPC_CheckPredicate, + 20, + 166, + 0, + 0, // Skip to: 333 + /* 167 */ MCD_OPC_Decode, + 187, + 12, + 134, + 1, // Opcode: FDIV_D64_MM + /* 172 */ MCD_OPC_FilterValue, + 187, + 4, + 45, + 0, + 0, // Skip to: 223 + /* 178 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 181 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 195 + /* 186 */ MCD_OPC_CheckPredicate, + 20, + 142, + 0, + 0, // Skip to: 333 + /* 191 */ MCD_OPC_Decode, + 219, + 18, + 111, // Opcode: RSQRT_D64_MM + /* 195 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 209 + /* 200 */ MCD_OPC_CheckPredicate, + 20, + 128, + 0, + 0, // Skip to: 333 + /* 205 */ MCD_OPC_Decode, + 157, + 13, + 111, // Opcode: FSQRT_D64_MM + /* 209 */ MCD_OPC_FilterValue, + 10, + 119, + 0, + 0, // Skip to: 333 + /* 214 */ MCD_OPC_CheckPredicate, + 20, + 114, + 0, + 0, // Skip to: 333 + /* 219 */ MCD_OPC_Decode, + 186, + 18, + 111, // Opcode: RECIP_D64_MM + /* 223 */ MCD_OPC_FilterValue, + 251, + 6, + 104, + 0, + 0, // Skip to: 333 + /* 229 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 232 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 246 + /* 237 */ MCD_OPC_CheckPredicate, + 20, + 91, + 0, + 0, // Skip to: 333 + /* 242 */ MCD_OPC_Decode, + 211, + 9, + 110, // Opcode: CVT_D64_S_MM + /* 246 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 261 + /* 251 */ MCD_OPC_CheckPredicate, + 20, + 77, + 0, + 0, // Skip to: 333 + /* 256 */ MCD_OPC_Decode, + 227, + 9, + 135, + 1, // Opcode: CVT_S_D64_MM + /* 261 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 275 + /* 266 */ MCD_OPC_CheckPredicate, + 20, + 62, + 0, + 0, // Skip to: 333 + /* 271 */ MCD_OPC_Decode, + 141, + 12, + 111, // Opcode: FABS_D64_MM + /* 275 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 289 + /* 280 */ MCD_OPC_CheckPredicate, + 20, + 48, + 0, + 0, // Skip to: 333 + /* 285 */ MCD_OPC_Decode, + 130, + 13, + 111, // Opcode: FNEG_D64_MM + /* 289 */ MCD_OPC_FilterValue, + 6, + 39, + 0, + 0, // Skip to: 333 + /* 294 */ MCD_OPC_CheckPredicate, + 20, + 34, + 0, + 0, // Skip to: 333 + /* 299 */ MCD_OPC_Decode, + 213, + 9, + 110, // Opcode: CVT_D64_W_MM + /* 303 */ MCD_OPC_FilterValue, + 46, + 10, + 0, + 0, // Skip to: 318 + /* 308 */ MCD_OPC_CheckPredicate, + 23, + 20, + 0, + 0, // Skip to: 333 + /* 313 */ MCD_OPC_Decode, + 133, + 19, + 128, + 1, // Opcode: SDC1_D64_MMR6 + /* 318 */ MCD_OPC_FilterValue, + 47, + 10, + 0, + 0, // Skip to: 333 + /* 323 */ MCD_OPC_CheckPredicate, + 23, + 5, + 0, + 0, // Skip to: 333 + /* 328 */ MCD_OPC_Decode, + 170, + 14, + 128, + 1, // Opcode: LDC1_D64_MMR6 + /* 333 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMicroMipsR616[] = { + /* 0 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 3 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 41 + /* 8 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 26 + /* 16 */ MCD_OPC_CheckPredicate, + 24, + 173, + 1, + 0, // Skip to: 450 + /* 21 */ MCD_OPC_Decode, + 233, + 5, + 136, + 1, // Opcode: ADDU16_MMR6 + /* 26 */ MCD_OPC_FilterValue, + 1, + 163, + 1, + 0, // Skip to: 450 + /* 31 */ MCD_OPC_CheckPredicate, + 24, + 158, + 1, + 0, // Skip to: 450 + /* 36 */ MCD_OPC_Decode, + 232, + 20, + 136, + 1, // Opcode: SUBU16_MMR6 + /* 41 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 55 + /* 46 */ MCD_OPC_CheckPredicate, + 24, + 143, + 1, + 0, // Skip to: 450 + /* 51 */ MCD_OPC_Decode, + 158, + 16, + 22, // Opcode: MOVE16_MMR6 + /* 55 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 91 + /* 60 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 63 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 77 + /* 68 */ MCD_OPC_CheckPredicate, + 24, + 121, + 1, + 0, // Skip to: 450 + /* 73 */ MCD_OPC_Decode, + 242, + 19, + 23, // Opcode: SLL16_MMR6 + /* 77 */ MCD_OPC_FilterValue, + 1, + 112, + 1, + 0, // Skip to: 450 + /* 82 */ MCD_OPC_CheckPredicate, + 24, + 107, + 1, + 0, // Skip to: 450 + /* 87 */ MCD_OPC_Decode, + 173, + 20, + 23, // Opcode: SRL16_MMR6 + /* 91 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 105 + /* 96 */ MCD_OPC_CheckPredicate, + 24, + 93, + 1, + 0, // Skip to: 450 + /* 101 */ MCD_OPC_Decode, + 150, + 6, + 24, // Opcode: ANDI16_MMR6 + /* 105 */ MCD_OPC_FilterValue, + 17, + 228, + 0, + 0, // Skip to: 338 + /* 110 */ MCD_OPC_ExtractField, + 2, + 1, // Inst{2} ... + /* 113 */ MCD_OPC_FilterValue, + 0, + 206, + 0, + 0, // Skip to: 324 + /* 118 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 121 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 159 + /* 126 */ MCD_OPC_ExtractField, + 3, + 1, // Inst{3} ... + /* 129 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 144 + /* 134 */ MCD_OPC_CheckPredicate, + 24, + 55, + 1, + 0, // Skip to: 450 + /* 139 */ MCD_OPC_Decode, + 217, + 17, + 137, + 1, // Opcode: NOT16_MMR6 + /* 144 */ MCD_OPC_FilterValue, + 1, + 45, + 1, + 0, // Skip to: 450 + /* 149 */ MCD_OPC_CheckPredicate, + 24, + 40, + 1, + 0, // Skip to: 450 + /* 154 */ MCD_OPC_Decode, + 147, + 22, + 138, + 1, // Opcode: XOR16_MMR6 + /* 159 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 197 + /* 164 */ MCD_OPC_ExtractField, + 3, + 1, // Inst{3} ... + /* 167 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 182 + /* 172 */ MCD_OPC_CheckPredicate, + 24, + 17, + 1, + 0, // Skip to: 450 + /* 177 */ MCD_OPC_Decode, + 147, + 6, + 138, + 1, // Opcode: AND16_MMR6 + /* 182 */ MCD_OPC_FilterValue, + 1, + 7, + 1, + 0, // Skip to: 450 + /* 187 */ MCD_OPC_CheckPredicate, + 24, + 2, + 1, + 0, // Skip to: 450 + /* 192 */ MCD_OPC_Decode, + 222, + 17, + 138, + 1, // Opcode: OR16_MMR6 + /* 197 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 233 + /* 202 */ MCD_OPC_ExtractField, + 3, + 1, // Inst{3} ... + /* 205 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 219 + /* 210 */ MCD_OPC_CheckPredicate, + 24, + 235, + 0, + 0, // Skip to: 450 + /* 215 */ MCD_OPC_Decode, + 247, + 14, + 27, // Opcode: LWM16_MMR6 + /* 219 */ MCD_OPC_FilterValue, + 1, + 226, + 0, + 0, // Skip to: 450 + /* 224 */ MCD_OPC_CheckPredicate, + 24, + 221, + 0, + 0, // Skip to: 450 + /* 229 */ MCD_OPC_Decode, + 153, + 21, + 27, // Opcode: SWM16_MMR6 + /* 233 */ MCD_OPC_FilterValue, + 3, + 212, + 0, + 0, // Skip to: 450 + /* 238 */ MCD_OPC_ExtractField, + 3, + 2, // Inst{4-3} ... + /* 241 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 256 + /* 246 */ MCD_OPC_CheckPredicate, + 24, + 199, + 0, + 0, // Skip to: 450 + /* 251 */ MCD_OPC_Decode, + 138, + 14, + 139, + 1, // Opcode: JRC16_MMR6 + /* 256 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 271 + /* 261 */ MCD_OPC_CheckPredicate, + 24, + 184, + 0, + 0, // Skip to: 450 + /* 266 */ MCD_OPC_Decode, + 243, + 13, + 139, + 1, // Opcode: JALRC16_MMR6 + /* 271 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 286 + /* 276 */ MCD_OPC_CheckPredicate, + 24, + 169, + 0, + 0, // Skip to: 450 + /* 281 */ MCD_OPC_Decode, + 139, + 14, + 140, + 1, // Opcode: JRCADDIUSP_MMR6 + /* 286 */ MCD_OPC_FilterValue, + 3, + 159, + 0, + 0, // Skip to: 450 + /* 291 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 294 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 309 + /* 299 */ MCD_OPC_CheckPredicate, + 24, + 146, + 0, + 0, // Skip to: 450 + /* 304 */ MCD_OPC_Decode, + 248, + 7, + 141, + 1, // Opcode: BREAK16_MMR6 + /* 309 */ MCD_OPC_FilterValue, + 1, + 136, + 0, + 0, // Skip to: 450 + /* 314 */ MCD_OPC_CheckPredicate, + 24, + 131, + 0, + 0, // Skip to: 450 + /* 319 */ MCD_OPC_Decode, + 255, + 18, + 141, + 1, // Opcode: SDBBP16_MMR6 + /* 324 */ MCD_OPC_FilterValue, + 1, + 121, + 0, + 0, // Skip to: 450 + /* 329 */ MCD_OPC_CheckPredicate, + 24, + 116, + 0, + 0, // Skip to: 450 + /* 334 */ MCD_OPC_Decode, + 160, + 16, + 37, // Opcode: MOVEP_MMR6 + /* 338 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 352 + /* 343 */ MCD_OPC_CheckPredicate, + 24, + 102, + 0, + 0, // Skip to: 450 + /* 348 */ MCD_OPC_Decode, + 236, + 18, + 21, // Opcode: SB16_MMR6 + /* 352 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 366 + /* 357 */ MCD_OPC_CheckPredicate, + 24, + 88, + 0, + 0, // Skip to: 450 + /* 362 */ MCD_OPC_Decode, + 254, + 6, + 38, // Opcode: BEQZC16_MMR6 + /* 366 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 380 + /* 371 */ MCD_OPC_CheckPredicate, + 24, + 74, + 0, + 0, // Skip to: 450 + /* 376 */ MCD_OPC_Decode, + 173, + 19, + 21, // Opcode: SH16_MMR6 + /* 380 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 394 + /* 385 */ MCD_OPC_CheckPredicate, + 24, + 60, + 0, + 0, // Skip to: 450 + /* 390 */ MCD_OPC_Decode, + 229, + 7, + 38, // Opcode: BNEZC16_MMR6 + /* 394 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 408 + /* 399 */ MCD_OPC_CheckPredicate, + 24, + 46, + 0, + 0, // Skip to: 450 + /* 404 */ MCD_OPC_Decode, + 162, + 21, + 31, // Opcode: SWSP_MMR6 + /* 408 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 422 + /* 413 */ MCD_OPC_CheckPredicate, + 24, + 32, + 0, + 0, // Skip to: 450 + /* 418 */ MCD_OPC_Decode, + 212, + 6, + 39, // Opcode: BC16_MMR6 + /* 422 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 436 + /* 427 */ MCD_OPC_CheckPredicate, + 24, + 18, + 0, + 0, // Skip to: 450 + /* 432 */ MCD_OPC_Decode, + 135, + 21, + 21, // Opcode: SW16_MMR6 + /* 436 */ MCD_OPC_FilterValue, + 59, + 9, + 0, + 0, // Skip to: 450 + /* 441 */ MCD_OPC_CheckPredicate, + 24, + 4, + 0, + 0, // Skip to: 450 + /* 446 */ MCD_OPC_Decode, + 206, + 14, + 40, // Opcode: LI16_MMR6 + /* 450 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMicroMipsR632[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 98, + 4, + 0, // Skip to: 1130 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 112, + 0, + 0, // Skip to: 128 + /* 16 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 78 + /* 24 */ MCD_OPC_ExtractField, + 11, + 15, // Inst{25-11} ... + /* 27 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 41 + /* 32 */ MCD_OPC_CheckPredicate, + 24, + 32, + 0, + 0, // Skip to: 69 + /* 37 */ MCD_OPC_Decode, + 195, + 20, + 0, // Opcode: SSNOP_MMR6 + /* 41 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 55 + /* 46 */ MCD_OPC_CheckPredicate, + 24, + 18, + 0, + 0, // Skip to: 69 + /* 51 */ MCD_OPC_Decode, + 224, + 11, + 0, // Opcode: EHB_MMR6 + /* 55 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 69 + /* 60 */ MCD_OPC_CheckPredicate, + 24, + 4, + 0, + 0, // Skip to: 69 + /* 65 */ MCD_OPC_Decode, + 237, + 17, + 0, // Opcode: PAUSE_MMR6 + /* 69 */ MCD_OPC_CheckPredicate, + 24, + 78, + 12, + 0, // Skip to: 3224 + /* 74 */ MCD_OPC_Decode, + 255, + 19, + 41, // Opcode: SLL_MMR6 + /* 78 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 92 + /* 83 */ MCD_OPC_CheckPredicate, + 24, + 64, + 12, + 0, // Skip to: 3224 + /* 88 */ MCD_OPC_Decode, + 155, + 19, + 44, // Opcode: SELEQZ_MMR6 + /* 92 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 106 + /* 97 */ MCD_OPC_CheckPredicate, + 24, + 50, + 12, + 0, // Skip to: 3224 + /* 102 */ MCD_OPC_Decode, + 162, + 19, + 44, // Opcode: SELNEZ_MMR6 + /* 106 */ MCD_OPC_FilterValue, + 7, + 41, + 12, + 0, // Skip to: 3224 + /* 111 */ MCD_OPC_CheckPredicate, + 24, + 36, + 12, + 0, // Skip to: 3224 + /* 116 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 29, + 12, + 0, // Skip to: 3224 + /* 123 */ MCD_OPC_Decode, + 181, + 18, + 142, + 1, // Opcode: RDHWR_MMR6 + /* 128 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 142 + /* 133 */ MCD_OPC_CheckPredicate, + 24, + 14, + 12, + 0, // Skip to: 3224 + /* 138 */ MCD_OPC_Decode, + 250, + 7, + 45, // Opcode: BREAK_MMR6 + /* 142 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 156 + /* 147 */ MCD_OPC_CheckPredicate, + 24, + 0, + 12, + 0, // Skip to: 3224 + /* 152 */ MCD_OPC_Decode, + 237, + 13, + 46, // Opcode: INS_MMR6 + /* 156 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 178 + /* 161 */ MCD_OPC_CheckPredicate, + 24, + 242, + 11, + 0, // Skip to: 3224 + /* 166 */ MCD_OPC_CheckField, + 6, + 3, + 0, + 235, + 11, + 0, // Skip to: 3224 + /* 173 */ MCD_OPC_Decode, + 218, + 14, + 143, + 1, // Opcode: LSA_MMR6 + /* 178 */ MCD_OPC_FilterValue, + 16, + 136, + 0, + 0, // Skip to: 319 + /* 183 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 186 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 207 + /* 191 */ MCD_OPC_CheckPredicate, + 24, + 212, + 11, + 0, // Skip to: 3224 + /* 196 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 205, + 11, + 0, // Skip to: 3224 + /* 203 */ MCD_OPC_Decode, + 224, + 8, + 14, // Opcode: CLZ_MMR6 + /* 207 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 221 + /* 212 */ MCD_OPC_CheckPredicate, + 24, + 191, + 11, + 0, // Skip to: 3224 + /* 217 */ MCD_OPC_Decode, + 134, + 6, + 44, // Opcode: ADD_MMR6 + /* 221 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 235 + /* 226 */ MCD_OPC_CheckPredicate, + 24, + 177, + 11, + 0, // Skip to: 3224 + /* 231 */ MCD_OPC_Decode, + 238, + 5, + 44, // Opcode: ADDU_MMR6 + /* 235 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 249 + /* 240 */ MCD_OPC_CheckPredicate, + 24, + 163, + 11, + 0, // Skip to: 3224 + /* 245 */ MCD_OPC_Decode, + 255, + 20, + 44, // Opcode: SUB_MMR6 + /* 249 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 263 + /* 254 */ MCD_OPC_CheckPredicate, + 24, + 149, + 11, + 0, // Skip to: 3224 + /* 259 */ MCD_OPC_Decode, + 237, + 20, + 44, // Opcode: SUBU_MMR6 + /* 263 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 277 + /* 268 */ MCD_OPC_CheckPredicate, + 24, + 135, + 11, + 0, // Skip to: 3224 + /* 273 */ MCD_OPC_Decode, + 154, + 6, + 44, // Opcode: AND_MMR6 + /* 277 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 291 + /* 282 */ MCD_OPC_CheckPredicate, + 24, + 121, + 11, + 0, // Skip to: 3224 + /* 287 */ MCD_OPC_Decode, + 227, + 17, + 44, // Opcode: OR_MMR6 + /* 291 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 305 + /* 296 */ MCD_OPC_CheckPredicate, + 24, + 107, + 11, + 0, // Skip to: 3224 + /* 301 */ MCD_OPC_Decode, + 214, + 17, + 44, // Opcode: NOR_MMR6 + /* 305 */ MCD_OPC_FilterValue, + 12, + 98, + 11, + 0, // Skip to: 3224 + /* 310 */ MCD_OPC_CheckPredicate, + 24, + 93, + 11, + 0, // Skip to: 3224 + /* 315 */ MCD_OPC_Decode, + 152, + 22, + 44, // Opcode: XOR_MMR6 + /* 319 */ MCD_OPC_FilterValue, + 24, + 115, + 0, + 0, // Skip to: 439 + /* 324 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 327 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 341 + /* 332 */ MCD_OPC_CheckPredicate, + 24, + 71, + 11, + 0, // Skip to: 3224 + /* 337 */ MCD_OPC_Decode, + 180, + 17, + 44, // Opcode: MUL_MMR6 + /* 341 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 355 + /* 346 */ MCD_OPC_CheckPredicate, + 24, + 57, + 11, + 0, // Skip to: 3224 + /* 351 */ MCD_OPC_Decode, + 140, + 17, + 44, // Opcode: MUH_MMR6 + /* 355 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 369 + /* 360 */ MCD_OPC_CheckPredicate, + 24, + 43, + 11, + 0, // Skip to: 3224 + /* 365 */ MCD_OPC_Decode, + 174, + 17, + 44, // Opcode: MULU_MMR6 + /* 369 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 383 + /* 374 */ MCD_OPC_CheckPredicate, + 24, + 29, + 11, + 0, // Skip to: 3224 + /* 379 */ MCD_OPC_Decode, + 139, + 17, + 44, // Opcode: MUHU_MMR6 + /* 383 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 397 + /* 388 */ MCD_OPC_CheckPredicate, + 24, + 15, + 11, + 0, // Skip to: 3224 + /* 393 */ MCD_OPC_Decode, + 242, + 10, + 44, // Opcode: DIV_MMR6 + /* 397 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 411 + /* 402 */ MCD_OPC_CheckPredicate, + 24, + 1, + 11, + 0, // Skip to: 3224 + /* 407 */ MCD_OPC_Decode, + 148, + 16, + 44, // Opcode: MOD_MMR6 + /* 411 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 425 + /* 416 */ MCD_OPC_CheckPredicate, + 24, + 243, + 10, + 0, // Skip to: 3224 + /* 421 */ MCD_OPC_Decode, + 241, + 10, + 44, // Opcode: DIVU_MMR6 + /* 425 */ MCD_OPC_FilterValue, + 7, + 234, + 10, + 0, // Skip to: 3224 + /* 430 */ MCD_OPC_CheckPredicate, + 24, + 229, + 10, + 0, // Skip to: 3224 + /* 435 */ MCD_OPC_Decode, + 147, + 16, + 44, // Opcode: MODU_MMR6 + /* 439 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 461 + /* 444 */ MCD_OPC_CheckPredicate, + 24, + 215, + 10, + 0, // Skip to: 3224 + /* 449 */ MCD_OPC_CheckField, + 6, + 3, + 0, + 208, + 10, + 0, // Skip to: 3224 + /* 456 */ MCD_OPC_Decode, + 142, + 6, + 144, + 1, // Opcode: ALIGN_MMR6 + /* 461 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 475 + /* 466 */ MCD_OPC_CheckPredicate, + 24, + 193, + 10, + 0, // Skip to: 3224 + /* 471 */ MCD_OPC_Decode, + 137, + 12, + 55, // Opcode: EXT_MMR6 + /* 475 */ MCD_OPC_FilterValue, + 52, + 45, + 0, + 0, // Skip to: 525 + /* 480 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 483 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 504 + /* 488 */ MCD_OPC_CheckPredicate, + 24, + 171, + 10, + 0, // Skip to: 3224 + /* 493 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 164, + 10, + 0, // Skip to: 3224 + /* 500 */ MCD_OPC_Decode, + 222, + 15, + 57, // Opcode: MFHC0_MMR6 + /* 504 */ MCD_OPC_FilterValue, + 11, + 155, + 10, + 0, // Skip to: 3224 + /* 509 */ MCD_OPC_CheckPredicate, + 24, + 150, + 10, + 0, // Skip to: 3224 + /* 514 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 143, + 10, + 0, // Skip to: 3224 + /* 521 */ MCD_OPC_Decode, + 238, + 16, + 58, // Opcode: MTHC0_MMR6 + /* 525 */ MCD_OPC_FilterValue, + 60, + 66, + 2, + 0, // Skip to: 1108 + /* 530 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 533 */ MCD_OPC_FilterValue, + 0, + 138, + 0, + 0, // Skip to: 676 + /* 538 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 541 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 555 + /* 546 */ MCD_OPC_CheckPredicate, + 24, + 113, + 10, + 0, // Skip to: 3224 + /* 551 */ MCD_OPC_Decode, + 213, + 15, + 57, // Opcode: MFC0_MMR6 + /* 555 */ MCD_OPC_FilterValue, + 5, + 45, + 0, + 0, // Skip to: 605 + /* 560 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 563 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 584 + /* 568 */ MCD_OPC_CheckPredicate, + 24, + 91, + 10, + 0, // Skip to: 3224 + /* 573 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 84, + 10, + 0, // Skip to: 3224 + /* 580 */ MCD_OPC_Decode, + 219, + 11, + 81, // Opcode: DVP_MMR6 + /* 584 */ MCD_OPC_FilterValue, + 7, + 75, + 10, + 0, // Skip to: 3224 + /* 589 */ MCD_OPC_CheckPredicate, + 24, + 70, + 10, + 0, // Skip to: 3224 + /* 594 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 63, + 10, + 0, // Skip to: 3224 + /* 601 */ MCD_OPC_Decode, + 236, + 11, + 81, // Opcode: EVP_MMR6 + /* 605 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 619 + /* 610 */ MCD_OPC_CheckPredicate, + 24, + 49, + 10, + 0, // Skip to: 3224 + /* 615 */ MCD_OPC_Decode, + 228, + 16, + 58, // Opcode: MTC0_MMR6 + /* 619 */ MCD_OPC_FilterValue, + 12, + 16, + 0, + 0, // Skip to: 640 + /* 624 */ MCD_OPC_CheckPredicate, + 24, + 35, + 10, + 0, // Skip to: 3224 + /* 629 */ MCD_OPC_CheckField, + 11, + 3, + 1, + 28, + 10, + 0, // Skip to: 3224 + /* 636 */ MCD_OPC_Decode, + 178, + 7, + 75, // Opcode: BITSWAP_MMR6 + /* 640 */ MCD_OPC_FilterValue, + 28, + 19, + 10, + 0, // Skip to: 3224 + /* 645 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 648 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 662 + /* 653 */ MCD_OPC_CheckPredicate, + 24, + 6, + 10, + 0, // Skip to: 3224 + /* 658 */ MCD_OPC_Decode, + 245, + 13, + 69, // Opcode: JALRC_MMR6 + /* 662 */ MCD_OPC_FilterValue, + 3, + 253, + 9, + 0, // Skip to: 3224 + /* 667 */ MCD_OPC_CheckPredicate, + 24, + 248, + 9, + 0, // Skip to: 3224 + /* 672 */ MCD_OPC_Decode, + 244, + 13, + 69, // Opcode: JALRC_HB_MMR6 + /* 676 */ MCD_OPC_FilterValue, + 1, + 10, + 1, + 0, // Skip to: 947 + /* 681 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 684 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 734 + /* 689 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 692 */ MCD_OPC_FilterValue, + 13, + 16, + 0, + 0, // Skip to: 713 + /* 697 */ MCD_OPC_CheckPredicate, + 24, + 218, + 9, + 0, // Skip to: 3224 + /* 702 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 211, + 9, + 0, // Skip to: 3224 + /* 709 */ MCD_OPC_Decode, + 223, + 21, + 0, // Opcode: TLBINV_MMR6 + /* 713 */ MCD_OPC_FilterValue, + 29, + 202, + 9, + 0, // Skip to: 3224 + /* 718 */ MCD_OPC_CheckPredicate, + 24, + 197, + 9, + 0, // Skip to: 3224 + /* 723 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 190, + 9, + 0, // Skip to: 3224 + /* 730 */ MCD_OPC_Decode, + 252, + 10, + 81, // Opcode: DI_MMR6 + /* 734 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 770 + /* 739 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 742 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 756 + /* 747 */ MCD_OPC_CheckPredicate, + 24, + 168, + 9, + 0, // Skip to: 3224 + /* 752 */ MCD_OPC_Decode, + 204, + 8, + 69, // Opcode: CLO_MMR6 + /* 756 */ MCD_OPC_FilterValue, + 20, + 159, + 9, + 0, // Skip to: 3224 + /* 761 */ MCD_OPC_CheckPredicate, + 24, + 154, + 9, + 0, // Skip to: 3224 + /* 766 */ MCD_OPC_Decode, + 219, + 15, + 79, // Opcode: MFC2_MMR6 + /* 770 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 820 + /* 775 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 778 */ MCD_OPC_FilterValue, + 13, + 16, + 0, + 0, // Skip to: 799 + /* 783 */ MCD_OPC_CheckPredicate, + 24, + 132, + 9, + 0, // Skip to: 3224 + /* 788 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 125, + 9, + 0, // Skip to: 3224 + /* 795 */ MCD_OPC_Decode, + 222, + 21, + 0, // Opcode: TLBINVF_MMR6 + /* 799 */ MCD_OPC_FilterValue, + 29, + 116, + 9, + 0, // Skip to: 3224 + /* 804 */ MCD_OPC_CheckPredicate, + 24, + 111, + 9, + 0, // Skip to: 3224 + /* 809 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 104, + 9, + 0, // Skip to: 3224 + /* 816 */ MCD_OPC_Decode, + 227, + 11, + 81, // Opcode: EI_MMR6 + /* 820 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 841 + /* 825 */ MCD_OPC_CheckPredicate, + 24, + 90, + 9, + 0, // Skip to: 3224 + /* 830 */ MCD_OPC_CheckField, + 6, + 5, + 20, + 83, + 9, + 0, // Skip to: 3224 + /* 837 */ MCD_OPC_Decode, + 235, + 16, + 80, // Opcode: MTC2_MMR6 + /* 841 */ MCD_OPC_FilterValue, + 4, + 23, + 0, + 0, // Skip to: 869 + /* 846 */ MCD_OPC_CheckPredicate, + 25, + 69, + 9, + 0, // Skip to: 3224 + /* 851 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 62, + 9, + 0, // Skip to: 3224 + /* 858 */ MCD_OPC_CheckField, + 6, + 3, + 5, + 55, + 9, + 0, // Skip to: 3224 + /* 865 */ MCD_OPC_Decode, + 192, + 13, + 81, // Opcode: GINVI_MMR6 + /* 869 */ MCD_OPC_FilterValue, + 5, + 23, + 0, + 0, // Skip to: 897 + /* 874 */ MCD_OPC_CheckPredicate, + 24, + 41, + 9, + 0, // Skip to: 3224 + /* 879 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 34, + 9, + 0, // Skip to: 3224 + /* 886 */ MCD_OPC_CheckField, + 6, + 5, + 13, + 27, + 9, + 0, // Skip to: 3224 + /* 893 */ MCD_OPC_Decode, + 172, + 21, + 76, // Opcode: SYNC_MMR6 + /* 897 */ MCD_OPC_FilterValue, + 6, + 24, + 0, + 0, // Skip to: 926 + /* 902 */ MCD_OPC_CheckPredicate, + 25, + 13, + 9, + 0, // Skip to: 3224 + /* 907 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 6, + 9, + 0, // Skip to: 3224 + /* 914 */ MCD_OPC_CheckField, + 6, + 3, + 5, + 255, + 8, + 0, // Skip to: 3224 + /* 921 */ MCD_OPC_Decode, + 194, + 13, + 145, + 1, // Opcode: GINVT_MMR6 + /* 926 */ MCD_OPC_FilterValue, + 7, + 245, + 8, + 0, // Skip to: 3224 + /* 931 */ MCD_OPC_CheckPredicate, + 24, + 240, + 8, + 0, // Skip to: 3224 + /* 936 */ MCD_OPC_CheckField, + 6, + 5, + 12, + 233, + 8, + 0, // Skip to: 3224 + /* 943 */ MCD_OPC_Decode, + 144, + 22, + 69, // Opcode: WSBH_MMR6 + /* 947 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 997 + /* 952 */ MCD_OPC_ExtractField, + 6, + 8, // Inst{13-6} ... + /* 955 */ MCD_OPC_FilterValue, + 52, + 9, + 0, + 0, // Skip to: 969 + /* 960 */ MCD_OPC_CheckPredicate, + 24, + 211, + 8, + 0, // Skip to: 3224 + /* 965 */ MCD_OPC_Decode, + 227, + 15, + 79, // Opcode: MFHC2_MMR6 + /* 969 */ MCD_OPC_FilterValue, + 77, + 9, + 0, + 0, // Skip to: 983 + /* 974 */ MCD_OPC_CheckPredicate, + 24, + 197, + 8, + 0, // Skip to: 3224 + /* 979 */ MCD_OPC_Decode, + 138, + 22, + 77, // Opcode: WAIT_MMR6 + /* 983 */ MCD_OPC_FilterValue, + 116, + 188, + 8, + 0, // Skip to: 3224 + /* 988 */ MCD_OPC_CheckPredicate, + 24, + 183, + 8, + 0, // Skip to: 3224 + /* 993 */ MCD_OPC_Decode, + 243, + 16, + 80, // Opcode: MTHC2_MMR6 + /* 997 */ MCD_OPC_FilterValue, + 3, + 174, + 8, + 0, // Skip to: 3224 + /* 1002 */ MCD_OPC_ExtractField, + 6, + 8, // Inst{13-6} ... + /* 1005 */ MCD_OPC_FilterValue, + 109, + 9, + 0, + 0, // Skip to: 1019 + /* 1010 */ MCD_OPC_CheckPredicate, + 24, + 161, + 8, + 0, // Skip to: 3224 + /* 1015 */ MCD_OPC_Decode, + 129, + 19, + 77, // Opcode: SDBBP_MMR6 + /* 1019 */ MCD_OPC_FilterValue, + 133, + 1, + 9, + 0, + 0, // Skip to: 1034 + /* 1025 */ MCD_OPC_CheckPredicate, + 24, + 146, + 8, + 0, // Skip to: 3224 + /* 1030 */ MCD_OPC_Decode, + 182, + 18, + 69, // Opcode: RDPGPR_MMR6 + /* 1034 */ MCD_OPC_FilterValue, + 141, + 1, + 16, + 0, + 0, // Skip to: 1056 + /* 1040 */ MCD_OPC_CheckPredicate, + 24, + 131, + 8, + 0, // Skip to: 3224 + /* 1045 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 124, + 8, + 0, // Skip to: 3224 + /* 1052 */ MCD_OPC_Decode, + 230, + 10, + 0, // Opcode: DERET_MMR6 + /* 1056 */ MCD_OPC_FilterValue, + 197, + 1, + 9, + 0, + 0, // Skip to: 1071 + /* 1062 */ MCD_OPC_CheckPredicate, + 24, + 109, + 8, + 0, // Skip to: 3224 + /* 1067 */ MCD_OPC_Decode, + 141, + 22, + 69, // Opcode: WRPGPR_MMR6 + /* 1071 */ MCD_OPC_FilterValue, + 205, + 1, + 99, + 8, + 0, // Skip to: 3224 + /* 1077 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 1080 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1094 + /* 1085 */ MCD_OPC_CheckPredicate, + 24, + 86, + 8, + 0, // Skip to: 3224 + /* 1090 */ MCD_OPC_Decode, + 233, + 11, + 0, // Opcode: ERET_MMR6 + /* 1094 */ MCD_OPC_FilterValue, + 1, + 77, + 8, + 0, // Skip to: 3224 + /* 1099 */ MCD_OPC_CheckPredicate, + 24, + 72, + 8, + 0, // Skip to: 3224 + /* 1104 */ MCD_OPC_Decode, + 231, + 11, + 0, // Opcode: ERETNC_MMR6 + /* 1108 */ MCD_OPC_FilterValue, + 63, + 63, + 8, + 0, // Skip to: 3224 + /* 1113 */ MCD_OPC_CheckPredicate, + 24, + 58, + 8, + 0, // Skip to: 3224 + /* 1118 */ MCD_OPC_CheckField, + 22, + 4, + 0, + 51, + 8, + 0, // Skip to: 3224 + /* 1125 */ MCD_OPC_Decode, + 231, + 19, + 146, + 1, // Opcode: SIGRIE_MMR6 + /* 1130 */ MCD_OPC_FilterValue, + 4, + 26, + 0, + 0, // Skip to: 1161 + /* 1135 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 1152 + /* 1140 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 1152 + /* 1147 */ MCD_OPC_Decode, + 220, + 14, + 147, + 1, // Opcode: LUI_MMR6 + /* 1152 */ MCD_OPC_CheckPredicate, + 24, + 19, + 8, + 0, // Skip to: 3224 + /* 1157 */ MCD_OPC_Decode, + 172, + 6, + 97, // Opcode: AUI_MMR6 + /* 1161 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1176 + /* 1166 */ MCD_OPC_CheckPredicate, + 24, + 5, + 8, + 0, // Skip to: 3224 + /* 1171 */ MCD_OPC_Decode, + 159, + 14, + 148, + 1, // Opcode: LBU_MMR6 + /* 1176 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1190 + /* 1181 */ MCD_OPC_CheckPredicate, + 24, + 246, + 7, + 0, // Skip to: 3224 + /* 1186 */ MCD_OPC_Decode, + 241, + 18, + 87, // Opcode: SB_MMR6 + /* 1190 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1205 + /* 1195 */ MCD_OPC_CheckPredicate, + 24, + 232, + 7, + 0, // Skip to: 3224 + /* 1200 */ MCD_OPC_Decode, + 161, + 14, + 148, + 1, // Opcode: LB_MMR6 + /* 1205 */ MCD_OPC_FilterValue, + 8, + 105, + 0, + 0, // Skip to: 1315 + /* 1210 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 1213 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1235 + /* 1218 */ MCD_OPC_CheckPredicate, + 24, + 209, + 7, + 0, // Skip to: 3224 + /* 1223 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 202, + 7, + 0, // Skip to: 3224 + /* 1230 */ MCD_OPC_Decode, + 233, + 14, + 149, + 1, // Opcode: LWC2_MMR6 + /* 1235 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 1257 + /* 1240 */ MCD_OPC_CheckPredicate, + 24, + 187, + 7, + 0, // Skip to: 3224 + /* 1245 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 180, + 7, + 0, // Skip to: 3224 + /* 1252 */ MCD_OPC_Decode, + 173, + 14, + 149, + 1, // Opcode: LDC2_MMR6 + /* 1257 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1271 + /* 1262 */ MCD_OPC_CheckPredicate, + 24, + 165, + 7, + 0, // Skip to: 3224 + /* 1267 */ MCD_OPC_Decode, + 153, + 8, + 89, // Opcode: CACHE_MMR6 + /* 1271 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 1293 + /* 1276 */ MCD_OPC_CheckPredicate, + 24, + 151, + 7, + 0, // Skip to: 3224 + /* 1281 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 144, + 7, + 0, // Skip to: 3224 + /* 1288 */ MCD_OPC_Decode, + 140, + 21, + 149, + 1, // Opcode: SWC2_MMR6 + /* 1293 */ MCD_OPC_FilterValue, + 10, + 134, + 7, + 0, // Skip to: 3224 + /* 1298 */ MCD_OPC_CheckPredicate, + 24, + 129, + 7, + 0, // Skip to: 3224 + /* 1303 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 122, + 7, + 0, // Skip to: 3224 + /* 1310 */ MCD_OPC_Decode, + 136, + 19, + 149, + 1, // Opcode: SDC2_MMR6 + /* 1315 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 1329 + /* 1320 */ MCD_OPC_CheckPredicate, + 24, + 107, + 7, + 0, // Skip to: 3224 + /* 1325 */ MCD_OPC_Decode, + 202, + 5, + 86, // Opcode: ADDIU_MMR6 + /* 1329 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 1343 + /* 1334 */ MCD_OPC_CheckPredicate, + 24, + 93, + 7, + 0, // Skip to: 3224 + /* 1339 */ MCD_OPC_Decode, + 229, + 19, + 87, // Opcode: SH_MMR6 + /* 1343 */ MCD_OPC_FilterValue, + 16, + 78, + 0, + 0, // Skip to: 1426 + /* 1348 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 1351 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1366 + /* 1356 */ MCD_OPC_CheckPredicate, + 26, + 71, + 7, + 0, // Skip to: 3224 + /* 1361 */ MCD_OPC_Decode, + 214, + 6, + 150, + 1, // Opcode: BC1EQZC_MMR6 + /* 1366 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1381 + /* 1371 */ MCD_OPC_CheckPredicate, + 26, + 56, + 7, + 0, // Skip to: 3224 + /* 1376 */ MCD_OPC_Decode, + 219, + 6, + 150, + 1, // Opcode: BC1NEZC_MMR6 + /* 1381 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1396 + /* 1386 */ MCD_OPC_CheckPredicate, + 24, + 41, + 7, + 0, // Skip to: 3224 + /* 1391 */ MCD_OPC_Decode, + 224, + 6, + 151, + 1, // Opcode: BC2EQZC_MMR6 + /* 1396 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1411 + /* 1401 */ MCD_OPC_CheckPredicate, + 24, + 26, + 7, + 0, // Skip to: 3224 + /* 1406 */ MCD_OPC_Decode, + 228, + 6, + 151, + 1, // Opcode: BC2NEZC_MMR6 + /* 1411 */ MCD_OPC_FilterValue, + 12, + 16, + 7, + 0, // Skip to: 3224 + /* 1416 */ MCD_OPC_CheckPredicate, + 24, + 11, + 7, + 0, // Skip to: 3224 + /* 1421 */ MCD_OPC_Decode, + 170, + 21, + 152, + 1, // Opcode: SYNCI_MMR6 + /* 1426 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 1440 + /* 1431 */ MCD_OPC_CheckPredicate, + 24, + 252, + 6, + 0, // Skip to: 3224 + /* 1436 */ MCD_OPC_Decode, + 225, + 17, + 97, // Opcode: ORI_MMR6 + /* 1440 */ MCD_OPC_FilterValue, + 21, + 87, + 5, + 0, // Skip to: 2812 + /* 1445 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 1448 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1463 + /* 1453 */ MCD_OPC_CheckPredicate, + 26, + 230, + 6, + 0, // Skip to: 3224 + /* 1458 */ MCD_OPC_Decode, + 137, + 16, + 153, + 1, // Opcode: MIN_S_MMR6 + /* 1463 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1478 + /* 1468 */ MCD_OPC_CheckPredicate, + 26, + 215, + 6, + 0, // Skip to: 3224 + /* 1473 */ MCD_OPC_Decode, + 245, + 8, + 154, + 1, // Opcode: CMP_AF_S_MMR6 + /* 1478 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1493 + /* 1483 */ MCD_OPC_CheckPredicate, + 26, + 200, + 6, + 0, // Skip to: 3224 + /* 1488 */ MCD_OPC_Decode, + 206, + 15, + 153, + 1, // Opcode: MAX_S_MMR6 + /* 1493 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 1508 + /* 1498 */ MCD_OPC_CheckPredicate, + 26, + 185, + 6, + 0, // Skip to: 3224 + /* 1503 */ MCD_OPC_Decode, + 244, + 8, + 155, + 1, // Opcode: CMP_AF_D_MMR6 + /* 1508 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 1530 + /* 1513 */ MCD_OPC_CheckPredicate, + 24, + 170, + 6, + 0, // Skip to: 3224 + /* 1518 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 163, + 6, + 0, // Skip to: 3224 + /* 1525 */ MCD_OPC_Decode, + 200, + 18, + 156, + 1, // Opcode: RINT_S_MMR6 + /* 1530 */ MCD_OPC_FilterValue, + 35, + 10, + 0, + 0, // Skip to: 1545 + /* 1535 */ MCD_OPC_CheckPredicate, + 26, + 148, + 6, + 0, // Skip to: 3224 + /* 1540 */ MCD_OPC_Decode, + 246, + 15, + 153, + 1, // Opcode: MINA_S_MMR6 + /* 1545 */ MCD_OPC_FilterValue, + 43, + 10, + 0, + 0, // Skip to: 1560 + /* 1550 */ MCD_OPC_CheckPredicate, + 26, + 133, + 6, + 0, // Skip to: 3224 + /* 1555 */ MCD_OPC_Decode, + 187, + 15, + 153, + 1, // Opcode: MAXA_S_MMR6 + /* 1560 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 1575 + /* 1565 */ MCD_OPC_CheckPredicate, + 26, + 118, + 6, + 0, // Skip to: 3224 + /* 1570 */ MCD_OPC_Decode, + 152, + 12, + 157, + 1, // Opcode: FADD_S_MMR6 + /* 1575 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 1590 + /* 1580 */ MCD_OPC_CheckPredicate, + 24, + 103, + 6, + 0, // Skip to: 3224 + /* 1585 */ MCD_OPC_Decode, + 157, + 19, + 153, + 1, // Opcode: SELEQZ_S_MMR6 + /* 1590 */ MCD_OPC_FilterValue, + 59, + 31, + 0, + 0, // Skip to: 1626 + /* 1595 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 1598 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1612 + /* 1603 */ MCD_OPC_CheckPredicate, + 26, + 80, + 6, + 0, // Skip to: 3224 + /* 1608 */ MCD_OPC_Decode, + 217, + 15, + 108, // Opcode: MFC1_MMR6 + /* 1612 */ MCD_OPC_FilterValue, + 5, + 71, + 6, + 0, // Skip to: 3224 + /* 1617 */ MCD_OPC_CheckPredicate, + 26, + 66, + 6, + 0, // Skip to: 3224 + /* 1622 */ MCD_OPC_Decode, + 233, + 16, + 114, // Opcode: MTC1_MMR6 + /* 1626 */ MCD_OPC_FilterValue, + 69, + 10, + 0, + 0, // Skip to: 1641 + /* 1631 */ MCD_OPC_CheckPredicate, + 26, + 52, + 6, + 0, // Skip to: 3224 + /* 1636 */ MCD_OPC_Decode, + 185, + 9, + 154, + 1, // Opcode: CMP_UN_S_MMR6 + /* 1641 */ MCD_OPC_FilterValue, + 85, + 10, + 0, + 0, // Skip to: 1656 + /* 1646 */ MCD_OPC_CheckPredicate, + 26, + 37, + 6, + 0, // Skip to: 3224 + /* 1651 */ MCD_OPC_Decode, + 183, + 9, + 155, + 1, // Opcode: CMP_UN_D_MMR6 + /* 1656 */ MCD_OPC_FilterValue, + 96, + 17, + 0, + 0, // Skip to: 1678 + /* 1661 */ MCD_OPC_CheckPredicate, + 24, + 22, + 6, + 0, // Skip to: 3224 + /* 1666 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 15, + 6, + 0, // Skip to: 3224 + /* 1673 */ MCD_OPC_Decode, + 185, + 8, + 156, + 1, // Opcode: CLASS_S_MMR6 + /* 1678 */ MCD_OPC_FilterValue, + 112, + 10, + 0, + 0, // Skip to: 1693 + /* 1683 */ MCD_OPC_CheckPredicate, + 26, + 0, + 6, + 0, // Skip to: 3224 + /* 1688 */ MCD_OPC_Decode, + 169, + 13, + 157, + 1, // Opcode: FSUB_S_MMR6 + /* 1693 */ MCD_OPC_FilterValue, + 120, + 10, + 0, + 0, // Skip to: 1708 + /* 1698 */ MCD_OPC_CheckPredicate, + 24, + 241, + 5, + 0, // Skip to: 3224 + /* 1703 */ MCD_OPC_Decode, + 164, + 19, + 153, + 1, // Opcode: SELNEZ_S_MMR6 + /* 1708 */ MCD_OPC_FilterValue, + 123, + 31, + 0, + 0, // Skip to: 1744 + /* 1713 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 1716 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1730 + /* 1721 */ MCD_OPC_CheckPredicate, + 26, + 218, + 5, + 0, // Skip to: 3224 + /* 1726 */ MCD_OPC_Decode, + 242, + 12, + 113, // Opcode: FMOV_S_MMR6 + /* 1730 */ MCD_OPC_FilterValue, + 4, + 209, + 5, + 0, // Skip to: 3224 + /* 1735 */ MCD_OPC_CheckPredicate, + 26, + 204, + 5, + 0, // Skip to: 3224 + /* 1740 */ MCD_OPC_Decode, + 239, + 12, + 111, // Opcode: FMOV_D_MMR6 + /* 1744 */ MCD_OPC_FilterValue, + 133, + 1, + 10, + 0, + 0, // Skip to: 1760 + /* 1750 */ MCD_OPC_CheckPredicate, + 26, + 189, + 5, + 0, // Skip to: 3224 + /* 1755 */ MCD_OPC_Decode, + 251, + 8, + 154, + 1, // Opcode: CMP_EQ_S_MMR6 + /* 1760 */ MCD_OPC_FilterValue, + 149, + 1, + 10, + 0, + 0, // Skip to: 1776 + /* 1766 */ MCD_OPC_CheckPredicate, + 26, + 173, + 5, + 0, // Skip to: 3224 + /* 1771 */ MCD_OPC_Decode, + 247, + 8, + 155, + 1, // Opcode: CMP_EQ_D_MMR6 + /* 1776 */ MCD_OPC_FilterValue, + 176, + 1, + 10, + 0, + 0, // Skip to: 1792 + /* 1782 */ MCD_OPC_CheckPredicate, + 26, + 157, + 5, + 0, // Skip to: 3224 + /* 1787 */ MCD_OPC_Decode, + 253, + 12, + 157, + 1, // Opcode: FMUL_S_MMR6 + /* 1792 */ MCD_OPC_FilterValue, + 184, + 1, + 10, + 0, + 0, // Skip to: 1808 + /* 1798 */ MCD_OPC_CheckPredicate, + 24, + 141, + 5, + 0, // Skip to: 3224 + /* 1803 */ MCD_OPC_Decode, + 168, + 19, + 158, + 1, // Opcode: SEL_S_MMR6 + /* 1808 */ MCD_OPC_FilterValue, + 197, + 1, + 10, + 0, + 0, // Skip to: 1824 + /* 1814 */ MCD_OPC_CheckPredicate, + 26, + 125, + 5, + 0, // Skip to: 3224 + /* 1819 */ MCD_OPC_Decode, + 173, + 9, + 154, + 1, // Opcode: CMP_UEQ_S_MMR6 + /* 1824 */ MCD_OPC_FilterValue, + 213, + 1, + 10, + 0, + 0, // Skip to: 1840 + /* 1830 */ MCD_OPC_CheckPredicate, + 26, + 109, + 5, + 0, // Skip to: 3224 + /* 1835 */ MCD_OPC_Decode, + 171, + 9, + 155, + 1, // Opcode: CMP_UEQ_D_MMR6 + /* 1840 */ MCD_OPC_FilterValue, + 240, + 1, + 10, + 0, + 0, // Skip to: 1856 + /* 1846 */ MCD_OPC_CheckPredicate, + 26, + 93, + 5, + 0, // Skip to: 3224 + /* 1851 */ MCD_OPC_Decode, + 190, + 12, + 157, + 1, // Opcode: FDIV_S_MMR6 + /* 1856 */ MCD_OPC_FilterValue, + 133, + 2, + 10, + 0, + 0, // Skip to: 1872 + /* 1862 */ MCD_OPC_CheckPredicate, + 26, + 77, + 5, + 0, // Skip to: 3224 + /* 1867 */ MCD_OPC_Decode, + 137, + 9, + 154, + 1, // Opcode: CMP_LT_S_MMR6 + /* 1872 */ MCD_OPC_FilterValue, + 149, + 2, + 10, + 0, + 0, // Skip to: 1888 + /* 1878 */ MCD_OPC_CheckPredicate, + 26, + 61, + 5, + 0, // Skip to: 3224 + /* 1883 */ MCD_OPC_Decode, + 133, + 9, + 155, + 1, // Opcode: CMP_LT_D_MMR6 + /* 1888 */ MCD_OPC_FilterValue, + 187, + 2, + 45, + 0, + 0, // Skip to: 1939 + /* 1894 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 1897 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1911 + /* 1902 */ MCD_OPC_CheckPredicate, + 26, + 37, + 5, + 0, // Skip to: 3224 + /* 1907 */ MCD_OPC_Decode, + 220, + 9, + 110, // Opcode: CVT_L_S_MMR6 + /* 1911 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1925 + /* 1916 */ MCD_OPC_CheckPredicate, + 26, + 23, + 5, + 0, // Skip to: 3224 + /* 1921 */ MCD_OPC_Decode, + 241, + 9, + 113, // Opcode: CVT_W_S_MMR6 + /* 1925 */ MCD_OPC_FilterValue, + 8, + 14, + 5, + 0, // Skip to: 3224 + /* 1930 */ MCD_OPC_CheckPredicate, + 26, + 9, + 5, + 0, // Skip to: 3224 + /* 1935 */ MCD_OPC_Decode, + 217, + 9, + 111, // Opcode: CVT_L_D_MMR6 + /* 1939 */ MCD_OPC_FilterValue, + 197, + 2, + 10, + 0, + 0, // Skip to: 1955 + /* 1945 */ MCD_OPC_CheckPredicate, + 26, + 250, + 4, + 0, // Skip to: 3224 + /* 1950 */ MCD_OPC_Decode, + 181, + 9, + 154, + 1, // Opcode: CMP_ULT_S_MMR6 + /* 1955 */ MCD_OPC_FilterValue, + 213, + 2, + 10, + 0, + 0, // Skip to: 1971 + /* 1961 */ MCD_OPC_CheckPredicate, + 26, + 234, + 4, + 0, // Skip to: 3224 + /* 1966 */ MCD_OPC_Decode, + 179, + 9, + 155, + 1, // Opcode: CMP_ULT_D_MMR6 + /* 1971 */ MCD_OPC_FilterValue, + 133, + 3, + 10, + 0, + 0, // Skip to: 1987 + /* 1977 */ MCD_OPC_CheckPredicate, + 26, + 218, + 4, + 0, // Skip to: 3224 + /* 1982 */ MCD_OPC_Decode, + 131, + 9, + 154, + 1, // Opcode: CMP_LE_S_MMR6 + /* 1987 */ MCD_OPC_FilterValue, + 149, + 3, + 10, + 0, + 0, // Skip to: 2003 + /* 1993 */ MCD_OPC_CheckPredicate, + 26, + 202, + 4, + 0, // Skip to: 3224 + /* 1998 */ MCD_OPC_Decode, + 255, + 8, + 155, + 1, // Opcode: CMP_LE_D_MMR6 + /* 2003 */ MCD_OPC_FilterValue, + 184, + 3, + 10, + 0, + 0, // Skip to: 2019 + /* 2009 */ MCD_OPC_CheckPredicate, + 26, + 186, + 4, + 0, // Skip to: 3224 + /* 2014 */ MCD_OPC_Decode, + 155, + 15, + 159, + 1, // Opcode: MADDF_S_MMR6 + /* 2019 */ MCD_OPC_FilterValue, + 197, + 3, + 10, + 0, + 0, // Skip to: 2035 + /* 2025 */ MCD_OPC_CheckPredicate, + 26, + 170, + 4, + 0, // Skip to: 3224 + /* 2030 */ MCD_OPC_Decode, + 177, + 9, + 154, + 1, // Opcode: CMP_ULE_S_MMR6 + /* 2035 */ MCD_OPC_FilterValue, + 213, + 3, + 10, + 0, + 0, // Skip to: 2051 + /* 2041 */ MCD_OPC_CheckPredicate, + 26, + 154, + 4, + 0, // Skip to: 3224 + /* 2046 */ MCD_OPC_Decode, + 175, + 9, + 155, + 1, // Opcode: CMP_ULE_D_MMR6 + /* 2051 */ MCD_OPC_FilterValue, + 248, + 3, + 10, + 0, + 0, // Skip to: 2067 + /* 2057 */ MCD_OPC_CheckPredicate, + 26, + 138, + 4, + 0, // Skip to: 3224 + /* 2062 */ MCD_OPC_Decode, + 206, + 16, + 159, + 1, // Opcode: MSUBF_S_MMR6 + /* 2067 */ MCD_OPC_FilterValue, + 131, + 4, + 10, + 0, + 0, // Skip to: 2083 + /* 2073 */ MCD_OPC_CheckPredicate, + 26, + 122, + 4, + 0, // Skip to: 3224 + /* 2078 */ MCD_OPC_Decode, + 132, + 16, + 134, + 1, // Opcode: MIN_D_MMR6 + /* 2083 */ MCD_OPC_FilterValue, + 133, + 4, + 10, + 0, + 0, // Skip to: 2099 + /* 2089 */ MCD_OPC_CheckPredicate, + 26, + 106, + 4, + 0, // Skip to: 3224 + /* 2094 */ MCD_OPC_Decode, + 141, + 9, + 154, + 1, // Opcode: CMP_SAF_S_MMR6 + /* 2099 */ MCD_OPC_FilterValue, + 139, + 4, + 10, + 0, + 0, // Skip to: 2115 + /* 2105 */ MCD_OPC_CheckPredicate, + 26, + 90, + 4, + 0, // Skip to: 3224 + /* 2110 */ MCD_OPC_Decode, + 201, + 15, + 134, + 1, // Opcode: MAX_D_MMR6 + /* 2115 */ MCD_OPC_FilterValue, + 149, + 4, + 10, + 0, + 0, // Skip to: 2131 + /* 2121 */ MCD_OPC_CheckPredicate, + 26, + 74, + 4, + 0, // Skip to: 3224 + /* 2126 */ MCD_OPC_Decode, + 139, + 9, + 155, + 1, // Opcode: CMP_SAF_D_MMR6 + /* 2131 */ MCD_OPC_FilterValue, + 160, + 4, + 17, + 0, + 0, // Skip to: 2154 + /* 2137 */ MCD_OPC_CheckPredicate, + 24, + 58, + 4, + 0, // Skip to: 3224 + /* 2142 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 51, + 4, + 0, // Skip to: 3224 + /* 2149 */ MCD_OPC_Decode, + 198, + 18, + 160, + 1, // Opcode: RINT_D_MMR6 + /* 2154 */ MCD_OPC_FilterValue, + 163, + 4, + 10, + 0, + 0, // Skip to: 2170 + /* 2160 */ MCD_OPC_CheckPredicate, + 26, + 35, + 4, + 0, // Skip to: 3224 + /* 2165 */ MCD_OPC_Decode, + 244, + 15, + 134, + 1, // Opcode: MINA_D_MMR6 + /* 2170 */ MCD_OPC_FilterValue, + 171, + 4, + 10, + 0, + 0, // Skip to: 2186 + /* 2176 */ MCD_OPC_CheckPredicate, + 26, + 19, + 4, + 0, // Skip to: 3224 + /* 2181 */ MCD_OPC_Decode, + 185, + 15, + 134, + 1, // Opcode: MAXA_D_MMR6 + /* 2186 */ MCD_OPC_FilterValue, + 184, + 4, + 10, + 0, + 0, // Skip to: 2202 + /* 2192 */ MCD_OPC_CheckPredicate, + 24, + 3, + 4, + 0, // Skip to: 3224 + /* 2197 */ MCD_OPC_Decode, + 154, + 19, + 134, + 1, // Opcode: SELEQZ_D_MMR6 + /* 2202 */ MCD_OPC_FilterValue, + 197, + 4, + 10, + 0, + 0, // Skip to: 2218 + /* 2208 */ MCD_OPC_CheckPredicate, + 26, + 243, + 3, + 0, // Skip to: 3224 + /* 2213 */ MCD_OPC_Decode, + 169, + 9, + 154, + 1, // Opcode: CMP_SUN_S_MMR6 + /* 2218 */ MCD_OPC_FilterValue, + 213, + 4, + 10, + 0, + 0, // Skip to: 2234 + /* 2224 */ MCD_OPC_CheckPredicate, + 26, + 227, + 3, + 0, // Skip to: 3224 + /* 2229 */ MCD_OPC_Decode, + 167, + 9, + 155, + 1, // Opcode: CMP_SUN_D_MMR6 + /* 2234 */ MCD_OPC_FilterValue, + 224, + 4, + 17, + 0, + 0, // Skip to: 2257 + /* 2240 */ MCD_OPC_CheckPredicate, + 24, + 211, + 3, + 0, // Skip to: 3224 + /* 2245 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 204, + 3, + 0, // Skip to: 3224 + /* 2252 */ MCD_OPC_Decode, + 183, + 8, + 160, + 1, // Opcode: CLASS_D_MMR6 + /* 2257 */ MCD_OPC_FilterValue, + 248, + 4, + 10, + 0, + 0, // Skip to: 2273 + /* 2263 */ MCD_OPC_CheckPredicate, + 24, + 188, + 3, + 0, // Skip to: 3224 + /* 2268 */ MCD_OPC_Decode, + 161, + 19, + 134, + 1, // Opcode: SELNEZ_D_MMR6 + /* 2273 */ MCD_OPC_FilterValue, + 133, + 5, + 10, + 0, + 0, // Skip to: 2289 + /* 2279 */ MCD_OPC_CheckPredicate, + 26, + 172, + 3, + 0, // Skip to: 3224 + /* 2284 */ MCD_OPC_Decode, + 145, + 9, + 154, + 1, // Opcode: CMP_SEQ_S_MMR6 + /* 2289 */ MCD_OPC_FilterValue, + 149, + 5, + 10, + 0, + 0, // Skip to: 2305 + /* 2295 */ MCD_OPC_CheckPredicate, + 26, + 156, + 3, + 0, // Skip to: 3224 + /* 2300 */ MCD_OPC_Decode, + 143, + 9, + 155, + 1, // Opcode: CMP_SEQ_D_MMR6 + /* 2305 */ MCD_OPC_FilterValue, + 184, + 5, + 10, + 0, + 0, // Skip to: 2321 + /* 2311 */ MCD_OPC_CheckPredicate, + 24, + 140, + 3, + 0, // Skip to: 3224 + /* 2316 */ MCD_OPC_Decode, + 166, + 19, + 161, + 1, // Opcode: SEL_D_MMR6 + /* 2321 */ MCD_OPC_FilterValue, + 197, + 5, + 10, + 0, + 0, // Skip to: 2337 + /* 2327 */ MCD_OPC_CheckPredicate, + 26, + 124, + 3, + 0, // Skip to: 3224 + /* 2332 */ MCD_OPC_Decode, + 157, + 9, + 154, + 1, // Opcode: CMP_SUEQ_S_MMR6 + /* 2337 */ MCD_OPC_FilterValue, + 213, + 5, + 10, + 0, + 0, // Skip to: 2353 + /* 2343 */ MCD_OPC_CheckPredicate, + 26, + 108, + 3, + 0, // Skip to: 3224 + /* 2348 */ MCD_OPC_Decode, + 155, + 9, + 155, + 1, // Opcode: CMP_SUEQ_D_MMR6 + /* 2353 */ MCD_OPC_FilterValue, + 133, + 6, + 10, + 0, + 0, // Skip to: 2369 + /* 2359 */ MCD_OPC_CheckPredicate, + 26, + 92, + 3, + 0, // Skip to: 3224 + /* 2364 */ MCD_OPC_Decode, + 153, + 9, + 154, + 1, // Opcode: CMP_SLT_S_MMR6 + /* 2369 */ MCD_OPC_FilterValue, + 149, + 6, + 10, + 0, + 0, // Skip to: 2385 + /* 2375 */ MCD_OPC_CheckPredicate, + 26, + 76, + 3, + 0, // Skip to: 3224 + /* 2380 */ MCD_OPC_Decode, + 151, + 9, + 155, + 1, // Opcode: CMP_SLT_D_MMR6 + /* 2385 */ MCD_OPC_FilterValue, + 187, + 6, + 228, + 0, + 0, // Skip to: 2619 + /* 2391 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 2394 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2408 + /* 2399 */ MCD_OPC_CheckPredicate, + 26, + 52, + 3, + 0, // Skip to: 3224 + /* 2404 */ MCD_OPC_Decode, + 217, + 12, + 110, // Opcode: FLOOR_L_S_MMR6 + /* 2408 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2422 + /* 2413 */ MCD_OPC_CheckPredicate, + 26, + 38, + 3, + 0, // Skip to: 3224 + /* 2418 */ MCD_OPC_Decode, + 224, + 12, + 113, // Opcode: FLOOR_W_S_MMR6 + /* 2422 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2436 + /* 2427 */ MCD_OPC_CheckPredicate, + 26, + 24, + 3, + 0, // Skip to: 3224 + /* 2432 */ MCD_OPC_Decode, + 158, + 8, + 110, // Opcode: CEIL_L_S_MMR6 + /* 2436 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 2450 + /* 2441 */ MCD_OPC_CheckPredicate, + 26, + 10, + 3, + 0, // Skip to: 3224 + /* 2446 */ MCD_OPC_Decode, + 165, + 8, + 113, // Opcode: CEIL_W_S_MMR6 + /* 2450 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 2464 + /* 2455 */ MCD_OPC_CheckPredicate, + 26, + 252, + 2, + 0, // Skip to: 3224 + /* 2460 */ MCD_OPC_Decode, + 246, + 21, + 110, // Opcode: TRUNC_L_S_MMR6 + /* 2464 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2478 + /* 2469 */ MCD_OPC_CheckPredicate, + 26, + 238, + 2, + 0, // Skip to: 3224 + /* 2474 */ MCD_OPC_Decode, + 253, + 21, + 113, // Opcode: TRUNC_W_S_MMR6 + /* 2478 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 2492 + /* 2483 */ MCD_OPC_CheckPredicate, + 26, + 224, + 2, + 0, // Skip to: 3224 + /* 2488 */ MCD_OPC_Decode, + 208, + 18, + 110, // Opcode: ROUND_L_S_MMR6 + /* 2492 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 2506 + /* 2497 */ MCD_OPC_CheckPredicate, + 26, + 210, + 2, + 0, // Skip to: 3224 + /* 2502 */ MCD_OPC_Decode, + 215, + 18, + 113, // Opcode: ROUND_W_S_MMR6 + /* 2506 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 2520 + /* 2511 */ MCD_OPC_CheckPredicate, + 26, + 196, + 2, + 0, // Skip to: 3224 + /* 2516 */ MCD_OPC_Decode, + 215, + 12, + 111, // Opcode: FLOOR_L_D_MMR6 + /* 2520 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 2534 + /* 2525 */ MCD_OPC_CheckPredicate, + 26, + 182, + 2, + 0, // Skip to: 3224 + /* 2530 */ MCD_OPC_Decode, + 220, + 12, + 115, // Opcode: FLOOR_W_D_MMR6 + /* 2534 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 2548 + /* 2539 */ MCD_OPC_CheckPredicate, + 26, + 168, + 2, + 0, // Skip to: 3224 + /* 2544 */ MCD_OPC_Decode, + 156, + 8, + 111, // Opcode: CEIL_L_D_MMR6 + /* 2548 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 2562 + /* 2553 */ MCD_OPC_CheckPredicate, + 26, + 154, + 2, + 0, // Skip to: 3224 + /* 2558 */ MCD_OPC_Decode, + 161, + 8, + 115, // Opcode: CEIL_W_D_MMR6 + /* 2562 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 2576 + /* 2567 */ MCD_OPC_CheckPredicate, + 26, + 140, + 2, + 0, // Skip to: 3224 + /* 2572 */ MCD_OPC_Decode, + 244, + 21, + 111, // Opcode: TRUNC_L_D_MMR6 + /* 2576 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2591 + /* 2581 */ MCD_OPC_CheckPredicate, + 26, + 126, + 2, + 0, // Skip to: 3224 + /* 2586 */ MCD_OPC_Decode, + 249, + 21, + 135, + 1, // Opcode: TRUNC_W_D_MMR6 + /* 2591 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 2605 + /* 2596 */ MCD_OPC_CheckPredicate, + 26, + 111, + 2, + 0, // Skip to: 3224 + /* 2601 */ MCD_OPC_Decode, + 206, + 18, + 111, // Opcode: ROUND_L_D_MMR6 + /* 2605 */ MCD_OPC_FilterValue, + 15, + 102, + 2, + 0, // Skip to: 3224 + /* 2610 */ MCD_OPC_CheckPredicate, + 26, + 97, + 2, + 0, // Skip to: 3224 + /* 2615 */ MCD_OPC_Decode, + 211, + 18, + 111, // Opcode: ROUND_W_D_MMR6 + /* 2619 */ MCD_OPC_FilterValue, + 197, + 6, + 10, + 0, + 0, // Skip to: 2635 + /* 2625 */ MCD_OPC_CheckPredicate, + 26, + 82, + 2, + 0, // Skip to: 3224 + /* 2630 */ MCD_OPC_Decode, + 165, + 9, + 154, + 1, // Opcode: CMP_SULT_S_MMR6 + /* 2635 */ MCD_OPC_FilterValue, + 213, + 6, + 10, + 0, + 0, // Skip to: 2651 + /* 2641 */ MCD_OPC_CheckPredicate, + 26, + 66, + 2, + 0, // Skip to: 3224 + /* 2646 */ MCD_OPC_Decode, + 163, + 9, + 155, + 1, // Opcode: CMP_SULT_D_MMR6 + /* 2651 */ MCD_OPC_FilterValue, + 251, + 6, + 59, + 0, + 0, // Skip to: 2716 + /* 2657 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 2660 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2674 + /* 2665 */ MCD_OPC_CheckPredicate, + 26, + 42, + 2, + 0, // Skip to: 3224 + /* 2670 */ MCD_OPC_Decode, + 133, + 13, + 113, // Opcode: FNEG_S_MMR6 + /* 2674 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 2688 + /* 2679 */ MCD_OPC_CheckPredicate, + 26, + 28, + 2, + 0, // Skip to: 3224 + /* 2684 */ MCD_OPC_Decode, + 234, + 9, + 113, // Opcode: CVT_S_W_MMR6 + /* 2688 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 2702 + /* 2693 */ MCD_OPC_CheckPredicate, + 23, + 14, + 2, + 0, // Skip to: 3224 + /* 2698 */ MCD_OPC_Decode, + 214, + 9, + 111, // Opcode: CVT_D_L_MMR6 + /* 2702 */ MCD_OPC_FilterValue, + 11, + 5, + 2, + 0, // Skip to: 3224 + /* 2707 */ MCD_OPC_CheckPredicate, + 23, + 0, + 2, + 0, // Skip to: 3224 + /* 2712 */ MCD_OPC_Decode, + 229, + 9, + 110, // Opcode: CVT_S_L_MMR6 + /* 2716 */ MCD_OPC_FilterValue, + 133, + 7, + 10, + 0, + 0, // Skip to: 2732 + /* 2722 */ MCD_OPC_CheckPredicate, + 26, + 241, + 1, + 0, // Skip to: 3224 + /* 2727 */ MCD_OPC_Decode, + 149, + 9, + 154, + 1, // Opcode: CMP_SLE_S_MMR6 + /* 2732 */ MCD_OPC_FilterValue, + 149, + 7, + 10, + 0, + 0, // Skip to: 2748 + /* 2738 */ MCD_OPC_CheckPredicate, + 26, + 225, + 1, + 0, // Skip to: 3224 + /* 2743 */ MCD_OPC_Decode, + 147, + 9, + 155, + 1, // Opcode: CMP_SLE_D_MMR6 + /* 2748 */ MCD_OPC_FilterValue, + 184, + 7, + 10, + 0, + 0, // Skip to: 2764 + /* 2754 */ MCD_OPC_CheckPredicate, + 26, + 209, + 1, + 0, // Skip to: 3224 + /* 2759 */ MCD_OPC_Decode, + 153, + 15, + 161, + 1, // Opcode: MADDF_D_MMR6 + /* 2764 */ MCD_OPC_FilterValue, + 197, + 7, + 10, + 0, + 0, // Skip to: 2780 + /* 2770 */ MCD_OPC_CheckPredicate, + 26, + 193, + 1, + 0, // Skip to: 3224 + /* 2775 */ MCD_OPC_Decode, + 161, + 9, + 154, + 1, // Opcode: CMP_SULE_S_MMR6 + /* 2780 */ MCD_OPC_FilterValue, + 213, + 7, + 10, + 0, + 0, // Skip to: 2796 + /* 2786 */ MCD_OPC_CheckPredicate, + 26, + 177, + 1, + 0, // Skip to: 3224 + /* 2791 */ MCD_OPC_Decode, + 159, + 9, + 155, + 1, // Opcode: CMP_SULE_D_MMR6 + /* 2796 */ MCD_OPC_FilterValue, + 248, + 7, + 166, + 1, + 0, // Skip to: 3224 + /* 2802 */ MCD_OPC_CheckPredicate, + 26, + 161, + 1, + 0, // Skip to: 3224 + /* 2807 */ MCD_OPC_Decode, + 204, + 16, + 161, + 1, // Opcode: MSUBF_D_MMR6 + /* 2812 */ MCD_OPC_FilterValue, + 24, + 59, + 0, + 0, // Skip to: 2876 + /* 2817 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 2820 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2834 + /* 2825 */ MCD_OPC_CheckPredicate, + 24, + 138, + 1, + 0, // Skip to: 3224 + /* 2830 */ MCD_OPC_Decode, + 168, + 18, + 89, // Opcode: PREF_MMR6 + /* 2834 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 2855 + /* 2839 */ MCD_OPC_CheckPredicate, + 24, + 124, + 1, + 0, // Skip to: 3224 + /* 2844 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 117, + 1, + 0, // Skip to: 3224 + /* 2851 */ MCD_OPC_Decode, + 215, + 14, + 123, // Opcode: LL_MMR6 + /* 2855 */ MCD_OPC_FilterValue, + 11, + 108, + 1, + 0, // Skip to: 3224 + /* 2860 */ MCD_OPC_CheckPredicate, + 24, + 103, + 1, + 0, // Skip to: 3224 + /* 2865 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 96, + 1, + 0, // Skip to: 3224 + /* 2872 */ MCD_OPC_Decode, + 250, + 18, + 123, // Opcode: SC_MMR6 + /* 2876 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 2890 + /* 2881 */ MCD_OPC_CheckPredicate, + 24, + 82, + 1, + 0, // Skip to: 3224 + /* 2886 */ MCD_OPC_Decode, + 150, + 22, + 97, // Opcode: XORI_MMR6 + /* 2890 */ MCD_OPC_FilterValue, + 29, + 27, + 0, + 0, // Skip to: 2922 + /* 2895 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 2912 + /* 2900 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 2912 + /* 2907 */ MCD_OPC_Decode, + 252, + 6, + 162, + 1, // Opcode: BEQZALC_MMR6 + /* 2912 */ MCD_OPC_CheckPredicate, + 24, + 51, + 1, + 0, // Skip to: 3224 + /* 2917 */ MCD_OPC_Decode, + 248, + 6, + 162, + 1, // Opcode: BEQC_MMR6 + /* 2922 */ MCD_OPC_FilterValue, + 30, + 71, + 0, + 0, // Skip to: 2998 + /* 2927 */ MCD_OPC_ExtractField, + 19, + 2, // Inst{20-19} ... + /* 2930 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2945 + /* 2935 */ MCD_OPC_CheckPredicate, + 24, + 28, + 1, + 0, // Skip to: 3224 + /* 2940 */ MCD_OPC_Decode, + 197, + 5, + 163, + 1, // Opcode: ADDIUPC_MMR6 + /* 2945 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2960 + /* 2950 */ MCD_OPC_CheckPredicate, + 24, + 13, + 1, + 0, // Skip to: 3224 + /* 2955 */ MCD_OPC_Decode, + 250, + 14, + 163, + 1, // Opcode: LWPC_MMR6 + /* 2960 */ MCD_OPC_FilterValue, + 3, + 3, + 1, + 0, // Skip to: 3224 + /* 2965 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 2968 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 2983 + /* 2973 */ MCD_OPC_CheckPredicate, + 24, + 246, + 0, + 0, // Skip to: 3224 + /* 2978 */ MCD_OPC_Decode, + 171, + 6, + 164, + 1, // Opcode: AUIPC_MMR6 + /* 2983 */ MCD_OPC_FilterValue, + 7, + 236, + 0, + 0, // Skip to: 3224 + /* 2988 */ MCD_OPC_CheckPredicate, + 24, + 231, + 0, + 0, // Skip to: 3224 + /* 2993 */ MCD_OPC_Decode, + 144, + 6, + 164, + 1, // Opcode: ALUIPC_MMR6 + /* 2998 */ MCD_OPC_FilterValue, + 31, + 27, + 0, + 0, // Skip to: 3030 + /* 3003 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 3020 + /* 3008 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 3020 + /* 3015 */ MCD_OPC_Decode, + 227, + 7, + 165, + 1, // Opcode: BNEZALC_MMR6 + /* 3020 */ MCD_OPC_CheckPredicate, + 24, + 199, + 0, + 0, // Skip to: 3224 + /* 3025 */ MCD_OPC_Decode, + 215, + 7, + 165, + 1, // Opcode: BNEC_MMR6 + /* 3030 */ MCD_OPC_FilterValue, + 32, + 26, + 0, + 0, // Skip to: 3061 + /* 3035 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 3051 + /* 3040 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 3051 + /* 3047 */ MCD_OPC_Decode, + 129, + 14, + 92, // Opcode: JIALC_MMR6 + /* 3051 */ MCD_OPC_CheckPredicate, + 24, + 168, + 0, + 0, // Skip to: 3224 + /* 3056 */ MCD_OPC_Decode, + 129, + 7, + 166, + 1, // Opcode: BEQZC_MMR6 + /* 3061 */ MCD_OPC_FilterValue, + 37, + 10, + 0, + 0, // Skip to: 3076 + /* 3066 */ MCD_OPC_CheckPredicate, + 24, + 153, + 0, + 0, // Skip to: 3224 + /* 3071 */ MCD_OPC_Decode, + 243, + 6, + 167, + 1, // Opcode: BC_MMR6 + /* 3076 */ MCD_OPC_FilterValue, + 40, + 26, + 0, + 0, // Skip to: 3107 + /* 3081 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 3097 + /* 3086 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 3097 + /* 3093 */ MCD_OPC_Decode, + 132, + 14, + 92, // Opcode: JIC_MMR6 + /* 3097 */ MCD_OPC_CheckPredicate, + 24, + 122, + 0, + 0, // Skip to: 3224 + /* 3102 */ MCD_OPC_Decode, + 232, + 7, + 166, + 1, // Opcode: BNEZC_MMR6 + /* 3107 */ MCD_OPC_FilterValue, + 45, + 10, + 0, + 0, // Skip to: 3122 + /* 3112 */ MCD_OPC_CheckPredicate, + 24, + 107, + 0, + 0, // Skip to: 3224 + /* 3117 */ MCD_OPC_Decode, + 202, + 6, + 167, + 1, // Opcode: BALC_MMR6 + /* 3122 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 3137 + /* 3127 */ MCD_OPC_CheckPredicate, + 24, + 92, + 0, + 0, // Skip to: 3224 + /* 3132 */ MCD_OPC_Decode, + 136, + 7, + 168, + 1, // Opcode: BGEUC_MMR6 + /* 3137 */ MCD_OPC_FilterValue, + 52, + 9, + 0, + 0, // Skip to: 3151 + /* 3142 */ MCD_OPC_CheckPredicate, + 24, + 77, + 0, + 0, // Skip to: 3224 + /* 3147 */ MCD_OPC_Decode, + 152, + 6, + 97, // Opcode: ANDI_MMR6 + /* 3151 */ MCD_OPC_FilterValue, + 53, + 10, + 0, + 0, // Skip to: 3166 + /* 3156 */ MCD_OPC_CheckPredicate, + 24, + 63, + 0, + 0, // Skip to: 3224 + /* 3161 */ MCD_OPC_Decode, + 190, + 7, + 169, + 1, // Opcode: BLTC_MMR6 + /* 3166 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 3181 + /* 3171 */ MCD_OPC_CheckPredicate, + 24, + 48, + 0, + 0, // Skip to: 3224 + /* 3176 */ MCD_OPC_Decode, + 193, + 7, + 170, + 1, // Opcode: BLTUC_MMR6 + /* 3181 */ MCD_OPC_FilterValue, + 61, + 10, + 0, + 0, // Skip to: 3196 + /* 3186 */ MCD_OPC_CheckPredicate, + 24, + 33, + 0, + 0, // Skip to: 3224 + /* 3191 */ MCD_OPC_Decode, + 133, + 7, + 171, + 1, // Opcode: BGEC_MMR6 + /* 3196 */ MCD_OPC_FilterValue, + 62, + 9, + 0, + 0, // Skip to: 3210 + /* 3201 */ MCD_OPC_CheckPredicate, + 24, + 18, + 0, + 0, // Skip to: 3224 + /* 3206 */ MCD_OPC_Decode, + 166, + 21, + 87, // Opcode: SW_MMR6 + /* 3210 */ MCD_OPC_FilterValue, + 63, + 9, + 0, + 0, // Skip to: 3224 + /* 3215 */ MCD_OPC_CheckPredicate, + 24, + 4, + 0, + 0, // Skip to: 3224 + /* 3220 */ MCD_OPC_Decode, + 138, + 15, + 87, // Opcode: LW_MMR6 + /* 3224 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMicroMipsR6_Ambiguous32[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 18 + /* 8 */ MCD_OPC_CheckPredicate, + 24, + 84, + 0, + 0, // Skip to: 97 + /* 13 */ MCD_OPC_Decode, + 242, + 7, + 162, + 1, // Opcode: BOVC_MMR6 + /* 18 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 33 + /* 23 */ MCD_OPC_CheckPredicate, + 24, + 69, + 0, + 0, // Skip to: 97 + /* 28 */ MCD_OPC_Decode, + 235, + 7, + 165, + 1, // Opcode: BNVC_MMR6 + /* 33 */ MCD_OPC_FilterValue, + 48, + 27, + 0, + 0, // Skip to: 65 + /* 38 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 55 + /* 43 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 55 + /* 50 */ MCD_OPC_Decode, + 182, + 7, + 168, + 1, // Opcode: BLEZALC_MMR6 + /* 55 */ MCD_OPC_CheckPredicate, + 24, + 37, + 0, + 0, // Skip to: 97 + /* 60 */ MCD_OPC_Decode, + 141, + 7, + 168, + 1, // Opcode: BGEZALC_MMR6 + /* 65 */ MCD_OPC_FilterValue, + 56, + 27, + 0, + 0, // Skip to: 97 + /* 70 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 87 + /* 75 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 87 + /* 82 */ MCD_OPC_Decode, + 153, + 7, + 170, + 1, // Opcode: BGTZALC_MMR6 + /* 87 */ MCD_OPC_CheckPredicate, + 24, + 5, + 0, + 0, // Skip to: 97 + /* 92 */ MCD_OPC_Decode, + 198, + 7, + 170, + 1, // Opcode: BLTZALC_MMR6 + /* 97 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableMips32[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 68 -/* 14 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 17 */ MCD_OPC_FilterValue, 0, 137, 53, // Skip to: 13726 -/* 21 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... -/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 -/* 28 */ MCD_OPC_CheckPredicate, 5, 28, 0, // Skip to: 60 -/* 32 */ MCD_OPC_Decode, 180, 12, 0, // Opcode: SSNOP -/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 -/* 40 */ MCD_OPC_CheckPredicate, 5, 16, 0, // Skip to: 60 -/* 44 */ MCD_OPC_Decode, 139, 5, 0, // Opcode: EHB -/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 -/* 52 */ MCD_OPC_CheckPredicate, 6, 4, 0, // Skip to: 60 -/* 56 */ MCD_OPC_Decode, 147, 10, 0, // Opcode: PAUSE -/* 60 */ MCD_OPC_CheckPredicate, 1, 94, 53, // Skip to: 13726 -/* 64 */ MCD_OPC_Decode, 225, 11, 58, // Opcode: SLL -/* 68 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 111 -/* 72 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 75 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 93 -/* 79 */ MCD_OPC_CheckPredicate, 7, 75, 53, // Skip to: 13726 -/* 83 */ MCD_OPC_CheckField, 6, 5, 0, 69, 53, // Skip to: 13726 -/* 89 */ MCD_OPC_Decode, 239, 8, 59, // Opcode: MOVF_I -/* 93 */ MCD_OPC_FilterValue, 1, 61, 53, // Skip to: 13726 -/* 97 */ MCD_OPC_CheckPredicate, 7, 57, 53, // Skip to: 13726 -/* 101 */ MCD_OPC_CheckField, 6, 5, 0, 51, 53, // Skip to: 13726 -/* 107 */ MCD_OPC_Decode, 131, 9, 59, // Opcode: MOVT_I -/* 111 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 142 -/* 115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 -/* 122 */ MCD_OPC_CheckPredicate, 1, 32, 53, // Skip to: 13726 -/* 126 */ MCD_OPC_Decode, 159, 12, 58, // Opcode: SRL -/* 130 */ MCD_OPC_FilterValue, 1, 24, 53, // Skip to: 13726 -/* 134 */ MCD_OPC_CheckPredicate, 6, 20, 53, // Skip to: 13726 -/* 138 */ MCD_OPC_Decode, 247, 10, 58, // Opcode: ROTR -/* 142 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 160 -/* 146 */ MCD_OPC_CheckPredicate, 5, 8, 53, // Skip to: 13726 -/* 150 */ MCD_OPC_CheckField, 21, 5, 0, 2, 53, // Skip to: 13726 -/* 156 */ MCD_OPC_Decode, 139, 12, 58, // Opcode: SRA -/* 160 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 178 -/* 164 */ MCD_OPC_CheckPredicate, 5, 246, 52, // Skip to: 13726 -/* 168 */ MCD_OPC_CheckField, 6, 5, 0, 240, 52, // Skip to: 13726 -/* 174 */ MCD_OPC_Decode, 233, 11, 36, // Opcode: SLLV -/* 178 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 196 -/* 182 */ MCD_OPC_CheckPredicate, 8, 228, 52, // Skip to: 13726 -/* 186 */ MCD_OPC_CheckField, 8, 3, 0, 222, 52, // Skip to: 13726 -/* 192 */ MCD_OPC_Decode, 205, 7, 60, // Opcode: LSA -/* 196 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 227 -/* 200 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 215 -/* 207 */ MCD_OPC_CheckPredicate, 5, 203, 52, // Skip to: 13726 -/* 211 */ MCD_OPC_Decode, 173, 12, 36, // Opcode: SRLV -/* 215 */ MCD_OPC_FilterValue, 1, 195, 52, // Skip to: 13726 -/* 219 */ MCD_OPC_CheckPredicate, 6, 191, 52, // Skip to: 13726 -/* 223 */ MCD_OPC_Decode, 248, 10, 36, // Opcode: ROTRV -/* 227 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 245 -/* 231 */ MCD_OPC_CheckPredicate, 5, 179, 52, // Skip to: 13726 -/* 235 */ MCD_OPC_CheckField, 6, 5, 0, 173, 52, // Skip to: 13726 -/* 241 */ MCD_OPC_Decode, 152, 12, 36, // Opcode: SRAV -/* 245 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 276 -/* 249 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... -/* 252 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 264 -/* 256 */ MCD_OPC_CheckPredicate, 5, 154, 52, // Skip to: 13726 -/* 260 */ MCD_OPC_Decode, 136, 7, 61, // Opcode: JR -/* 264 */ MCD_OPC_FilterValue, 16, 146, 52, // Skip to: 13726 -/* 268 */ MCD_OPC_CheckPredicate, 9, 142, 52, // Skip to: 13726 -/* 272 */ MCD_OPC_Decode, 141, 7, 61, // Opcode: JR_HB -/* 276 */ MCD_OPC_FilterValue, 9, 39, 0, // Skip to: 319 -/* 280 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 283 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 301 -/* 287 */ MCD_OPC_CheckPredicate, 1, 123, 52, // Skip to: 13726 -/* 291 */ MCD_OPC_CheckField, 16, 5, 0, 117, 52, // Skip to: 13726 -/* 297 */ MCD_OPC_Decode, 249, 6, 62, // Opcode: JALR -/* 301 */ MCD_OPC_FilterValue, 16, 109, 52, // Skip to: 13726 -/* 305 */ MCD_OPC_CheckPredicate, 10, 105, 52, // Skip to: 13726 -/* 309 */ MCD_OPC_CheckField, 16, 5, 0, 99, 52, // Skip to: 13726 -/* 315 */ MCD_OPC_Decode, 128, 7, 62, // Opcode: JALR_HB -/* 319 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 337 -/* 323 */ MCD_OPC_CheckPredicate, 7, 87, 52, // Skip to: 13726 -/* 327 */ MCD_OPC_CheckField, 6, 5, 0, 81, 52, // Skip to: 13726 -/* 333 */ MCD_OPC_Decode, 143, 9, 63, // Opcode: MOVZ_I_I -/* 337 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 355 -/* 341 */ MCD_OPC_CheckPredicate, 7, 69, 52, // Skip to: 13726 -/* 345 */ MCD_OPC_CheckField, 6, 5, 0, 63, 52, // Skip to: 13726 -/* 351 */ MCD_OPC_Decode, 251, 8, 63, // Opcode: MOVN_I_I -/* 355 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 367 -/* 359 */ MCD_OPC_CheckPredicate, 5, 51, 52, // Skip to: 13726 -/* 363 */ MCD_OPC_Decode, 132, 13, 64, // Opcode: SYSCALL -/* 367 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 379 -/* 371 */ MCD_OPC_CheckPredicate, 5, 39, 52, // Skip to: 13726 -/* 375 */ MCD_OPC_Decode, 171, 2, 33, // Opcode: BREAK -/* 379 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 391 -/* 383 */ MCD_OPC_CheckPredicate, 10, 27, 52, // Skip to: 13726 -/* 387 */ MCD_OPC_Decode, 129, 13, 65, // Opcode: SYNC -/* 391 */ MCD_OPC_FilterValue, 16, 43, 0, // Skip to: 438 -/* 395 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 398 */ MCD_OPC_FilterValue, 0, 12, 52, // Skip to: 13726 -/* 402 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 405 */ MCD_OPC_FilterValue, 0, 5, 52, // Skip to: 13726 -/* 409 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 412 */ MCD_OPC_FilterValue, 0, 254, 51, // Skip to: 13726 -/* 416 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 430 -/* 420 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 430 -/* 426 */ MCD_OPC_Decode, 186, 8, 66, // Opcode: MFHI -/* 430 */ MCD_OPC_CheckPredicate, 12, 236, 51, // Skip to: 13726 -/* 434 */ MCD_OPC_Decode, 189, 8, 67, // Opcode: MFHI_DSP -/* 438 */ MCD_OPC_FilterValue, 17, 36, 0, // Skip to: 478 -/* 442 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 445 */ MCD_OPC_FilterValue, 0, 221, 51, // Skip to: 13726 -/* 449 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... -/* 452 */ MCD_OPC_FilterValue, 0, 214, 51, // Skip to: 13726 -/* 456 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 470 -/* 460 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 470 -/* 466 */ MCD_OPC_Decode, 176, 9, 61, // Opcode: MTHI -/* 470 */ MCD_OPC_CheckPredicate, 12, 196, 51, // Skip to: 13726 -/* 474 */ MCD_OPC_Decode, 178, 9, 68, // Opcode: MTHI_DSP -/* 478 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 525 -/* 482 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 485 */ MCD_OPC_FilterValue, 0, 181, 51, // Skip to: 13726 -/* 489 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 492 */ MCD_OPC_FilterValue, 0, 174, 51, // Skip to: 13726 -/* 496 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 499 */ MCD_OPC_FilterValue, 0, 167, 51, // Skip to: 13726 -/* 503 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 517 -/* 507 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 517 -/* 513 */ MCD_OPC_Decode, 191, 8, 66, // Opcode: MFLO -/* 517 */ MCD_OPC_CheckPredicate, 12, 149, 51, // Skip to: 13726 -/* 521 */ MCD_OPC_Decode, 194, 8, 67, // Opcode: MFLO_DSP -/* 525 */ MCD_OPC_FilterValue, 19, 36, 0, // Skip to: 565 -/* 529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 532 */ MCD_OPC_FilterValue, 0, 134, 51, // Skip to: 13726 -/* 536 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... -/* 539 */ MCD_OPC_FilterValue, 0, 127, 51, // Skip to: 13726 -/* 543 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 557 -/* 547 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 557 -/* 553 */ MCD_OPC_Decode, 181, 9, 61, // Opcode: MTLO -/* 557 */ MCD_OPC_CheckPredicate, 12, 109, 51, // Skip to: 13726 -/* 561 */ MCD_OPC_Decode, 183, 9, 69, // Opcode: MTLO_DSP -/* 565 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 583 -/* 569 */ MCD_OPC_CheckPredicate, 14, 97, 51, // Skip to: 13726 -/* 573 */ MCD_OPC_CheckField, 8, 3, 0, 91, 51, // Skip to: 13726 -/* 579 */ MCD_OPC_Decode, 194, 4, 70, // Opcode: DLSA -/* 583 */ MCD_OPC_FilterValue, 24, 36, 0, // Skip to: 623 -/* 587 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 590 */ MCD_OPC_FilterValue, 0, 76, 51, // Skip to: 13726 -/* 594 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 597 */ MCD_OPC_FilterValue, 0, 69, 51, // Skip to: 13726 -/* 601 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 615 -/* 605 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 615 -/* 611 */ MCD_OPC_Decode, 206, 9, 43, // Opcode: MULT -/* 615 */ MCD_OPC_CheckPredicate, 12, 51, 51, // Skip to: 13726 -/* 619 */ MCD_OPC_Decode, 208, 9, 71, // Opcode: MULT_DSP -/* 623 */ MCD_OPC_FilterValue, 25, 36, 0, // Skip to: 663 -/* 627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 630 */ MCD_OPC_FilterValue, 0, 36, 51, // Skip to: 13726 -/* 634 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 637 */ MCD_OPC_FilterValue, 0, 29, 51, // Skip to: 13726 -/* 641 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 655 -/* 645 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 655 -/* 651 */ MCD_OPC_Decode, 210, 9, 43, // Opcode: MULTu -/* 655 */ MCD_OPC_CheckPredicate, 12, 11, 51, // Skip to: 13726 -/* 659 */ MCD_OPC_Decode, 207, 9, 71, // Opcode: MULTU_DSP -/* 663 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 681 -/* 667 */ MCD_OPC_CheckPredicate, 13, 255, 50, // Skip to: 13726 -/* 671 */ MCD_OPC_CheckField, 6, 10, 0, 249, 50, // Skip to: 13726 -/* 677 */ MCD_OPC_Decode, 162, 11, 43, // Opcode: SDIV -/* 681 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 699 -/* 685 */ MCD_OPC_CheckPredicate, 13, 237, 50, // Skip to: 13726 -/* 689 */ MCD_OPC_CheckField, 6, 10, 0, 231, 50, // Skip to: 13726 -/* 695 */ MCD_OPC_Decode, 222, 13, 43, // Opcode: UDIV -/* 699 */ MCD_OPC_FilterValue, 32, 13, 0, // Skip to: 716 -/* 703 */ MCD_OPC_CheckPredicate, 5, 219, 50, // Skip to: 13726 -/* 707 */ MCD_OPC_CheckField, 6, 5, 0, 213, 50, // Skip to: 13726 -/* 713 */ MCD_OPC_Decode, 25, 35, // Opcode: ADD -/* 716 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 733 -/* 720 */ MCD_OPC_CheckPredicate, 5, 202, 50, // Skip to: 13726 -/* 724 */ MCD_OPC_CheckField, 6, 5, 0, 196, 50, // Skip to: 13726 -/* 730 */ MCD_OPC_Decode, 77, 35, // Opcode: ADDu -/* 733 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 751 -/* 737 */ MCD_OPC_CheckPredicate, 5, 185, 50, // Skip to: 13726 -/* 741 */ MCD_OPC_CheckField, 6, 5, 0, 179, 50, // Skip to: 13726 -/* 747 */ MCD_OPC_Decode, 190, 12, 35, // Opcode: SUB -/* 751 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 769 -/* 755 */ MCD_OPC_CheckPredicate, 5, 167, 50, // Skip to: 13726 -/* 759 */ MCD_OPC_CheckField, 6, 5, 0, 161, 50, // Skip to: 13726 -/* 765 */ MCD_OPC_Decode, 230, 12, 35, // Opcode: SUBu -/* 769 */ MCD_OPC_FilterValue, 36, 13, 0, // Skip to: 786 -/* 773 */ MCD_OPC_CheckPredicate, 1, 149, 50, // Skip to: 13726 -/* 777 */ MCD_OPC_CheckField, 6, 5, 0, 143, 50, // Skip to: 13726 -/* 783 */ MCD_OPC_Decode, 83, 35, // Opcode: AND -/* 786 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 804 -/* 790 */ MCD_OPC_CheckPredicate, 1, 132, 50, // Skip to: 13726 -/* 794 */ MCD_OPC_CheckField, 6, 5, 0, 126, 50, // Skip to: 13726 -/* 800 */ MCD_OPC_Decode, 133, 10, 35, // Opcode: OR -/* 804 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 822 -/* 808 */ MCD_OPC_CheckPredicate, 1, 114, 50, // Skip to: 13726 -/* 812 */ MCD_OPC_CheckField, 6, 5, 0, 108, 50, // Skip to: 13726 -/* 818 */ MCD_OPC_Decode, 236, 13, 35, // Opcode: XOR -/* 822 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 840 -/* 826 */ MCD_OPC_CheckPredicate, 5, 96, 50, // Skip to: 13726 -/* 830 */ MCD_OPC_CheckField, 6, 5, 0, 90, 50, // Skip to: 13726 -/* 836 */ MCD_OPC_Decode, 250, 9, 35, // Opcode: NOR -/* 840 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 858 -/* 844 */ MCD_OPC_CheckPredicate, 5, 78, 50, // Skip to: 13726 -/* 848 */ MCD_OPC_CheckField, 6, 5, 0, 72, 50, // Skip to: 13726 -/* 854 */ MCD_OPC_Decode, 240, 11, 35, // Opcode: SLT -/* 858 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 876 -/* 862 */ MCD_OPC_CheckPredicate, 5, 60, 50, // Skip to: 13726 -/* 866 */ MCD_OPC_CheckField, 6, 5, 0, 54, 50, // Skip to: 13726 -/* 872 */ MCD_OPC_Decode, 249, 11, 35, // Opcode: SLTu -/* 876 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 888 -/* 880 */ MCD_OPC_CheckPredicate, 15, 42, 50, // Skip to: 13726 -/* 884 */ MCD_OPC_Decode, 186, 13, 72, // Opcode: TGE -/* 888 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 900 -/* 892 */ MCD_OPC_CheckPredicate, 15, 30, 50, // Skip to: 13726 -/* 896 */ MCD_OPC_Decode, 191, 13, 72, // Opcode: TGEU -/* 900 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 912 -/* 904 */ MCD_OPC_CheckPredicate, 15, 18, 50, // Skip to: 13726 -/* 908 */ MCD_OPC_Decode, 202, 13, 72, // Opcode: TLT -/* 912 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 924 -/* 916 */ MCD_OPC_CheckPredicate, 15, 6, 50, // Skip to: 13726 -/* 920 */ MCD_OPC_Decode, 206, 13, 72, // Opcode: TLTU -/* 924 */ MCD_OPC_FilterValue, 52, 8, 0, // Skip to: 936 -/* 928 */ MCD_OPC_CheckPredicate, 15, 250, 49, // Skip to: 13726 -/* 932 */ MCD_OPC_Decode, 182, 13, 72, // Opcode: TEQ -/* 936 */ MCD_OPC_FilterValue, 54, 242, 49, // Skip to: 13726 -/* 940 */ MCD_OPC_CheckPredicate, 15, 238, 49, // Skip to: 13726 -/* 944 */ MCD_OPC_Decode, 209, 13, 72, // Opcode: TNE -/* 948 */ MCD_OPC_FilterValue, 1, 201, 0, // Skip to: 1153 -/* 952 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967 -/* 959 */ MCD_OPC_CheckPredicate, 5, 219, 49, // Skip to: 13726 -/* 963 */ MCD_OPC_Decode, 131, 2, 73, // Opcode: BLTZ -/* 967 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 979 -/* 971 */ MCD_OPC_CheckPredicate, 5, 207, 49, // Skip to: 13726 -/* 975 */ MCD_OPC_Decode, 217, 1, 73, // Opcode: BGEZ -/* 979 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 991 -/* 983 */ MCD_OPC_CheckPredicate, 16, 195, 49, // Skip to: 13726 -/* 987 */ MCD_OPC_Decode, 139, 2, 73, // Opcode: BLTZL -/* 991 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1003 -/* 995 */ MCD_OPC_CheckPredicate, 16, 183, 49, // Skip to: 13726 -/* 999 */ MCD_OPC_Decode, 225, 1, 73, // Opcode: BGEZL -/* 1003 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1015 -/* 1007 */ MCD_OPC_CheckPredicate, 16, 171, 49, // Skip to: 13726 -/* 1011 */ MCD_OPC_Decode, 187, 13, 74, // Opcode: TGEI -/* 1015 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1027 -/* 1019 */ MCD_OPC_CheckPredicate, 16, 159, 49, // Skip to: 13726 -/* 1023 */ MCD_OPC_Decode, 188, 13, 74, // Opcode: TGEIU -/* 1027 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1039 -/* 1031 */ MCD_OPC_CheckPredicate, 16, 147, 49, // Skip to: 13726 -/* 1035 */ MCD_OPC_Decode, 203, 13, 74, // Opcode: TLTI -/* 1039 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1051 -/* 1043 */ MCD_OPC_CheckPredicate, 16, 135, 49, // Skip to: 13726 -/* 1047 */ MCD_OPC_Decode, 221, 13, 74, // Opcode: TTLTIU -/* 1051 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1063 -/* 1055 */ MCD_OPC_CheckPredicate, 16, 123, 49, // Skip to: 13726 -/* 1059 */ MCD_OPC_Decode, 183, 13, 74, // Opcode: TEQI -/* 1063 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1075 -/* 1067 */ MCD_OPC_CheckPredicate, 16, 111, 49, // Skip to: 13726 -/* 1071 */ MCD_OPC_Decode, 210, 13, 74, // Opcode: TNEI -/* 1075 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1087 -/* 1079 */ MCD_OPC_CheckPredicate, 13, 99, 49, // Skip to: 13726 -/* 1083 */ MCD_OPC_Decode, 133, 2, 73, // Opcode: BLTZAL -/* 1087 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1099 -/* 1091 */ MCD_OPC_CheckPredicate, 13, 87, 49, // Skip to: 13726 -/* 1095 */ MCD_OPC_Decode, 219, 1, 73, // Opcode: BGEZAL -/* 1099 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1111 -/* 1103 */ MCD_OPC_CheckPredicate, 16, 75, 49, // Skip to: 13726 -/* 1107 */ MCD_OPC_Decode, 135, 2, 73, // Opcode: BLTZALL -/* 1111 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1123 -/* 1115 */ MCD_OPC_CheckPredicate, 16, 63, 49, // Skip to: 13726 -/* 1119 */ MCD_OPC_Decode, 221, 1, 73, // Opcode: BGEZALL -/* 1123 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 1141 -/* 1127 */ MCD_OPC_CheckPredicate, 12, 51, 49, // Skip to: 13726 -/* 1131 */ MCD_OPC_CheckField, 21, 5, 0, 45, 49, // Skip to: 13726 -/* 1137 */ MCD_OPC_Decode, 169, 2, 75, // Opcode: BPOSGE32 -/* 1141 */ MCD_OPC_FilterValue, 31, 37, 49, // Skip to: 13726 -/* 1145 */ MCD_OPC_CheckPredicate, 6, 33, 49, // Skip to: 13726 -/* 1149 */ MCD_OPC_Decode, 130, 13, 76, // Opcode: SYNCI -/* 1153 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1165 -/* 1157 */ MCD_OPC_CheckPredicate, 10, 21, 49, // Skip to: 13726 -/* 1161 */ MCD_OPC_Decode, 247, 6, 77, // Opcode: J -/* 1165 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1177 -/* 1169 */ MCD_OPC_CheckPredicate, 5, 9, 49, // Skip to: 13726 -/* 1173 */ MCD_OPC_Decode, 248, 6, 77, // Opcode: JAL -/* 1177 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1189 -/* 1181 */ MCD_OPC_CheckPredicate, 5, 253, 48, // Skip to: 13726 -/* 1185 */ MCD_OPC_Decode, 206, 1, 78, // Opcode: BEQ -/* 1189 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1201 -/* 1193 */ MCD_OPC_CheckPredicate, 5, 241, 48, // Skip to: 13726 -/* 1197 */ MCD_OPC_Decode, 145, 2, 78, // Opcode: BNE -/* 1201 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1219 -/* 1205 */ MCD_OPC_CheckPredicate, 5, 229, 48, // Skip to: 13726 -/* 1209 */ MCD_OPC_CheckField, 16, 5, 0, 223, 48, // Skip to: 13726 -/* 1215 */ MCD_OPC_Decode, 251, 1, 73, // Opcode: BLEZ -/* 1219 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1237 -/* 1223 */ MCD_OPC_CheckPredicate, 5, 211, 48, // Skip to: 13726 -/* 1227 */ MCD_OPC_CheckField, 16, 5, 0, 205, 48, // Skip to: 13726 -/* 1233 */ MCD_OPC_Decode, 227, 1, 73, // Opcode: BGTZ -/* 1237 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 1248 -/* 1241 */ MCD_OPC_CheckPredicate, 13, 193, 48, // Skip to: 13726 -/* 1245 */ MCD_OPC_Decode, 73, 79, // Opcode: ADDi -/* 1248 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 1259 -/* 1252 */ MCD_OPC_CheckPredicate, 1, 182, 48, // Skip to: 13726 -/* 1256 */ MCD_OPC_Decode, 75, 79, // Opcode: ADDiu -/* 1259 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1271 -/* 1263 */ MCD_OPC_CheckPredicate, 5, 171, 48, // Skip to: 13726 -/* 1267 */ MCD_OPC_Decode, 243, 11, 79, // Opcode: SLTi -/* 1271 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1283 -/* 1275 */ MCD_OPC_CheckPredicate, 5, 159, 48, // Skip to: 13726 -/* 1279 */ MCD_OPC_Decode, 246, 11, 79, // Opcode: SLTiu -/* 1283 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1294 -/* 1287 */ MCD_OPC_CheckPredicate, 1, 147, 48, // Skip to: 13726 -/* 1291 */ MCD_OPC_Decode, 93, 80, // Opcode: ANDi -/* 1294 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1306 -/* 1298 */ MCD_OPC_CheckPredicate, 5, 136, 48, // Skip to: 13726 -/* 1302 */ MCD_OPC_Decode, 142, 10, 80, // Opcode: ORi -/* 1306 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1318 -/* 1310 */ MCD_OPC_CheckPredicate, 5, 124, 48, // Skip to: 13726 -/* 1314 */ MCD_OPC_Decode, 245, 13, 80, // Opcode: XORi -/* 1318 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1336 -/* 1322 */ MCD_OPC_CheckPredicate, 5, 112, 48, // Skip to: 13726 -/* 1326 */ MCD_OPC_CheckField, 21, 5, 0, 106, 48, // Skip to: 13726 -/* 1332 */ MCD_OPC_Decode, 210, 7, 52, // Opcode: LUi -/* 1336 */ MCD_OPC_FilterValue, 16, 220, 0, // Skip to: 1560 -/* 1340 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1343 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1361 -/* 1347 */ MCD_OPC_CheckPredicate, 10, 87, 48, // Skip to: 13726 -/* 1351 */ MCD_OPC_CheckField, 3, 8, 0, 81, 48, // Skip to: 13726 -/* 1357 */ MCD_OPC_Decode, 179, 8, 81, // Opcode: MFC0 -/* 1361 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1379 -/* 1365 */ MCD_OPC_CheckPredicate, 10, 69, 48, // Skip to: 13726 -/* 1369 */ MCD_OPC_CheckField, 3, 8, 0, 63, 48, // Skip to: 13726 -/* 1375 */ MCD_OPC_Decode, 169, 9, 81, // Opcode: MTC0 -/* 1379 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1434 -/* 1383 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1386 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1398 -/* 1390 */ MCD_OPC_CheckPredicate, 13, 44, 48, // Skip to: 13726 -/* 1394 */ MCD_OPC_Decode, 176, 1, 82, // Opcode: BC0F -/* 1398 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1410 -/* 1402 */ MCD_OPC_CheckPredicate, 13, 32, 48, // Skip to: 13726 -/* 1406 */ MCD_OPC_Decode, 178, 1, 82, // Opcode: BC0T -/* 1410 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1422 -/* 1414 */ MCD_OPC_CheckPredicate, 13, 20, 48, // Skip to: 13726 -/* 1418 */ MCD_OPC_Decode, 177, 1, 82, // Opcode: BC0FL -/* 1422 */ MCD_OPC_FilterValue, 3, 12, 48, // Skip to: 13726 -/* 1426 */ MCD_OPC_CheckPredicate, 13, 8, 48, // Skip to: 13726 -/* 1430 */ MCD_OPC_Decode, 179, 1, 82, // Opcode: BC0TL -/* 1434 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 1469 -/* 1438 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... -/* 1441 */ MCD_OPC_FilterValue, 128, 192, 1, 8, 0, // Skip to: 1455 -/* 1447 */ MCD_OPC_CheckPredicate, 6, 243, 47, // Skip to: 13726 -/* 1451 */ MCD_OPC_Decode, 179, 4, 42, // Opcode: DI -/* 1455 */ MCD_OPC_FilterValue, 160, 192, 1, 233, 47, // Skip to: 13726 -/* 1461 */ MCD_OPC_CheckPredicate, 6, 229, 47, // Skip to: 13726 -/* 1465 */ MCD_OPC_Decode, 141, 5, 42, // Opcode: EI -/* 1469 */ MCD_OPC_FilterValue, 16, 221, 47, // Skip to: 13726 -/* 1473 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... -/* 1476 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1488 -/* 1480 */ MCD_OPC_CheckPredicate, 5, 210, 47, // Skip to: 13726 -/* 1484 */ MCD_OPC_Decode, 196, 13, 0, // Opcode: TLBR -/* 1488 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1500 -/* 1492 */ MCD_OPC_CheckPredicate, 5, 198, 47, // Skip to: 13726 -/* 1496 */ MCD_OPC_Decode, 198, 13, 0, // Opcode: TLBWI -/* 1500 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1512 -/* 1504 */ MCD_OPC_CheckPredicate, 5, 186, 47, // Skip to: 13726 -/* 1508 */ MCD_OPC_Decode, 200, 13, 0, // Opcode: TLBWR -/* 1512 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1524 -/* 1516 */ MCD_OPC_CheckPredicate, 5, 174, 47, // Skip to: 13726 -/* 1520 */ MCD_OPC_Decode, 194, 13, 0, // Opcode: TLBP -/* 1524 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1536 -/* 1528 */ MCD_OPC_CheckPredicate, 17, 162, 47, // Skip to: 13726 -/* 1532 */ MCD_OPC_Decode, 143, 5, 0, // Opcode: ERET -/* 1536 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1548 -/* 1540 */ MCD_OPC_CheckPredicate, 10, 150, 47, // Skip to: 13726 -/* 1544 */ MCD_OPC_Decode, 174, 4, 0, // Opcode: DERET -/* 1548 */ MCD_OPC_FilterValue, 32, 142, 47, // Skip to: 13726 -/* 1552 */ MCD_OPC_CheckPredicate, 18, 138, 47, // Skip to: 13726 -/* 1556 */ MCD_OPC_Decode, 231, 13, 0, // Opcode: WAIT -/* 1560 */ MCD_OPC_FilterValue, 17, 21, 6, // Skip to: 3121 -/* 1564 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1567 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1585 -/* 1571 */ MCD_OPC_CheckPredicate, 5, 119, 47, // Skip to: 13726 -/* 1575 */ MCD_OPC_CheckField, 0, 11, 0, 113, 47, // Skip to: 13726 -/* 1581 */ MCD_OPC_Decode, 180, 8, 83, // Opcode: MFC1 -/* 1585 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1603 -/* 1589 */ MCD_OPC_CheckPredicate, 19, 101, 47, // Skip to: 13726 -/* 1593 */ MCD_OPC_CheckField, 0, 11, 0, 95, 47, // Skip to: 13726 -/* 1599 */ MCD_OPC_Decode, 197, 4, 84, // Opcode: DMFC1 -/* 1603 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 1621 -/* 1607 */ MCD_OPC_CheckPredicate, 5, 83, 47, // Skip to: 13726 -/* 1611 */ MCD_OPC_CheckField, 0, 11, 0, 77, 47, // Skip to: 13726 -/* 1617 */ MCD_OPC_Decode, 238, 2, 85, // Opcode: CFC1 -/* 1621 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 1639 -/* 1625 */ MCD_OPC_CheckPredicate, 20, 65, 47, // Skip to: 13726 -/* 1629 */ MCD_OPC_CheckField, 0, 11, 0, 59, 47, // Skip to: 13726 -/* 1635 */ MCD_OPC_Decode, 183, 8, 86, // Opcode: MFHC1_D32 -/* 1639 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1657 -/* 1643 */ MCD_OPC_CheckPredicate, 5, 47, 47, // Skip to: 13726 -/* 1647 */ MCD_OPC_CheckField, 0, 11, 0, 41, 47, // Skip to: 13726 -/* 1653 */ MCD_OPC_Decode, 170, 9, 87, // Opcode: MTC1 -/* 1657 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1675 -/* 1661 */ MCD_OPC_CheckPredicate, 19, 29, 47, // Skip to: 13726 -/* 1665 */ MCD_OPC_CheckField, 0, 11, 0, 23, 47, // Skip to: 13726 -/* 1671 */ MCD_OPC_Decode, 202, 4, 88, // Opcode: DMTC1 -/* 1675 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1693 -/* 1679 */ MCD_OPC_CheckPredicate, 5, 11, 47, // Skip to: 13726 -/* 1683 */ MCD_OPC_CheckField, 0, 11, 0, 5, 47, // Skip to: 13726 -/* 1689 */ MCD_OPC_Decode, 210, 3, 89, // Opcode: CTC1 -/* 1693 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1711 -/* 1697 */ MCD_OPC_CheckPredicate, 20, 249, 46, // Skip to: 13726 -/* 1701 */ MCD_OPC_CheckField, 0, 11, 0, 243, 46, // Skip to: 13726 -/* 1707 */ MCD_OPC_Decode, 173, 9, 90, // Opcode: MTHC1_D32 -/* 1711 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1766 -/* 1715 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1718 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1730 -/* 1722 */ MCD_OPC_CheckPredicate, 13, 224, 46, // Skip to: 13726 -/* 1726 */ MCD_OPC_Decode, 181, 1, 91, // Opcode: BC1F -/* 1730 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1742 -/* 1734 */ MCD_OPC_CheckPredicate, 13, 212, 46, // Skip to: 13726 -/* 1738 */ MCD_OPC_Decode, 185, 1, 91, // Opcode: BC1T -/* 1742 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1754 -/* 1746 */ MCD_OPC_CheckPredicate, 16, 200, 46, // Skip to: 13726 -/* 1750 */ MCD_OPC_Decode, 182, 1, 91, // Opcode: BC1FL -/* 1754 */ MCD_OPC_FilterValue, 3, 192, 46, // Skip to: 13726 -/* 1758 */ MCD_OPC_CheckPredicate, 16, 188, 46, // Skip to: 13726 -/* 1762 */ MCD_OPC_Decode, 186, 1, 91, // Opcode: BC1TL -/* 1766 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1778 -/* 1770 */ MCD_OPC_CheckPredicate, 8, 176, 46, // Skip to: 13726 -/* 1774 */ MCD_OPC_Decode, 192, 2, 92, // Opcode: BZ_V -/* 1778 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1790 -/* 1782 */ MCD_OPC_CheckPredicate, 8, 164, 46, // Skip to: 13726 -/* 1786 */ MCD_OPC_Decode, 166, 2, 92, // Opcode: BNZ_V -/* 1790 */ MCD_OPC_FilterValue, 16, 80, 2, // Skip to: 2386 -/* 1794 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1797 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1809 -/* 1801 */ MCD_OPC_CheckPredicate, 5, 145, 46, // Skip to: 13726 -/* 1805 */ MCD_OPC_Decode, 174, 5, 93, // Opcode: FADD_S -/* 1809 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1821 -/* 1813 */ MCD_OPC_CheckPredicate, 5, 133, 46, // Skip to: 13726 -/* 1817 */ MCD_OPC_Decode, 176, 6, 93, // Opcode: FSUB_S -/* 1821 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1833 -/* 1825 */ MCD_OPC_CheckPredicate, 5, 121, 46, // Skip to: 13726 -/* 1829 */ MCD_OPC_Decode, 139, 6, 93, // Opcode: FMUL_S -/* 1833 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1845 -/* 1837 */ MCD_OPC_CheckPredicate, 5, 109, 46, // Skip to: 13726 -/* 1841 */ MCD_OPC_Decode, 210, 5, 93, // Opcode: FDIV_S -/* 1845 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1863 -/* 1849 */ MCD_OPC_CheckPredicate, 15, 97, 46, // Skip to: 13726 -/* 1853 */ MCD_OPC_CheckField, 16, 5, 0, 91, 46, // Skip to: 13726 -/* 1859 */ MCD_OPC_Decode, 169, 6, 94, // Opcode: FSQRT_S -/* 1863 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1881 -/* 1867 */ MCD_OPC_CheckPredicate, 5, 79, 46, // Skip to: 13726 -/* 1871 */ MCD_OPC_CheckField, 16, 5, 0, 73, 46, // Skip to: 13726 -/* 1877 */ MCD_OPC_Decode, 167, 5, 94, // Opcode: FABS_S -/* 1881 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1899 -/* 1885 */ MCD_OPC_CheckPredicate, 5, 61, 46, // Skip to: 13726 -/* 1889 */ MCD_OPC_CheckField, 16, 5, 0, 55, 46, // Skip to: 13726 -/* 1895 */ MCD_OPC_Decode, 131, 6, 94, // Opcode: FMOV_S -/* 1899 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1917 -/* 1903 */ MCD_OPC_CheckPredicate, 5, 43, 46, // Skip to: 13726 -/* 1907 */ MCD_OPC_CheckField, 16, 5, 0, 37, 46, // Skip to: 13726 -/* 1913 */ MCD_OPC_Decode, 145, 6, 94, // Opcode: FNEG_S -/* 1917 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 1935 -/* 1921 */ MCD_OPC_CheckPredicate, 15, 25, 46, // Skip to: 13726 -/* 1925 */ MCD_OPC_CheckField, 16, 5, 0, 19, 46, // Skip to: 13726 -/* 1931 */ MCD_OPC_Decode, 128, 11, 94, // Opcode: ROUND_W_S -/* 1935 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 1953 -/* 1939 */ MCD_OPC_CheckPredicate, 15, 7, 46, // Skip to: 13726 -/* 1943 */ MCD_OPC_CheckField, 16, 5, 0, 1, 46, // Skip to: 13726 -/* 1949 */ MCD_OPC_Decode, 219, 13, 94, // Opcode: TRUNC_W_S -/* 1953 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 1971 -/* 1957 */ MCD_OPC_CheckPredicate, 15, 245, 45, // Skip to: 13726 -/* 1961 */ MCD_OPC_CheckField, 16, 5, 0, 239, 45, // Skip to: 13726 -/* 1967 */ MCD_OPC_Decode, 228, 2, 94, // Opcode: CEIL_W_S -/* 1971 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1989 -/* 1975 */ MCD_OPC_CheckPredicate, 15, 227, 45, // Skip to: 13726 -/* 1979 */ MCD_OPC_CheckField, 16, 5, 0, 221, 45, // Skip to: 13726 -/* 1985 */ MCD_OPC_Decode, 244, 5, 94, // Opcode: FLOOR_W_S -/* 1989 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2020 -/* 1993 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1996 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2008 -/* 2000 */ MCD_OPC_CheckPredicate, 7, 202, 45, // Skip to: 13726 -/* 2004 */ MCD_OPC_Decode, 242, 8, 95, // Opcode: MOVF_S -/* 2008 */ MCD_OPC_FilterValue, 1, 194, 45, // Skip to: 13726 -/* 2012 */ MCD_OPC_CheckPredicate, 7, 190, 45, // Skip to: 13726 -/* 2016 */ MCD_OPC_Decode, 134, 9, 95, // Opcode: MOVT_S -/* 2020 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2032 -/* 2024 */ MCD_OPC_CheckPredicate, 7, 178, 45, // Skip to: 13726 -/* 2028 */ MCD_OPC_Decode, 146, 9, 96, // Opcode: MOVZ_I_S -/* 2032 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2044 -/* 2036 */ MCD_OPC_CheckPredicate, 7, 166, 45, // Skip to: 13726 -/* 2040 */ MCD_OPC_Decode, 254, 8, 96, // Opcode: MOVN_I_S -/* 2044 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2062 -/* 2048 */ MCD_OPC_CheckPredicate, 21, 154, 45, // Skip to: 13726 -/* 2052 */ MCD_OPC_CheckField, 16, 5, 0, 148, 45, // Skip to: 13726 -/* 2058 */ MCD_OPC_Decode, 213, 3, 97, // Opcode: CVT_D32_S -/* 2062 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2080 -/* 2066 */ MCD_OPC_CheckPredicate, 5, 136, 45, // Skip to: 13726 -/* 2070 */ MCD_OPC_CheckField, 16, 5, 0, 130, 45, // Skip to: 13726 -/* 2076 */ MCD_OPC_Decode, 233, 3, 94, // Opcode: CVT_W_S -/* 2080 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2098 -/* 2084 */ MCD_OPC_CheckPredicate, 22, 118, 45, // Skip to: 13726 -/* 2088 */ MCD_OPC_CheckField, 16, 5, 0, 112, 45, // Skip to: 13726 -/* 2094 */ MCD_OPC_Decode, 222, 3, 98, // Opcode: CVT_L_S -/* 2098 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2116 -/* 2102 */ MCD_OPC_CheckPredicate, 13, 100, 45, // Skip to: 13726 -/* 2106 */ MCD_OPC_CheckField, 6, 5, 0, 94, 45, // Skip to: 13726 -/* 2112 */ MCD_OPC_Decode, 240, 3, 99, // Opcode: C_F_S -/* 2116 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2134 -/* 2120 */ MCD_OPC_CheckPredicate, 13, 82, 45, // Skip to: 13726 -/* 2124 */ MCD_OPC_CheckField, 6, 5, 0, 76, 45, // Skip to: 13726 -/* 2130 */ MCD_OPC_Decode, 154, 4, 99, // Opcode: C_UN_S -/* 2134 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2152 -/* 2138 */ MCD_OPC_CheckPredicate, 13, 64, 45, // Skip to: 13726 -/* 2142 */ MCD_OPC_CheckField, 6, 5, 0, 58, 45, // Skip to: 13726 -/* 2148 */ MCD_OPC_Decode, 237, 3, 99, // Opcode: C_EQ_S -/* 2152 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2170 -/* 2156 */ MCD_OPC_CheckPredicate, 13, 46, 45, // Skip to: 13726 -/* 2160 */ MCD_OPC_CheckField, 6, 5, 0, 40, 45, // Skip to: 13726 -/* 2166 */ MCD_OPC_Decode, 145, 4, 99, // Opcode: C_UEQ_S -/* 2170 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2188 -/* 2174 */ MCD_OPC_CheckPredicate, 13, 28, 45, // Skip to: 13726 -/* 2178 */ MCD_OPC_CheckField, 6, 5, 0, 22, 45, // Skip to: 13726 -/* 2184 */ MCD_OPC_Decode, 136, 4, 99, // Opcode: C_OLT_S -/* 2188 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2206 -/* 2192 */ MCD_OPC_CheckPredicate, 13, 10, 45, // Skip to: 13726 -/* 2196 */ MCD_OPC_CheckField, 6, 5, 0, 4, 45, // Skip to: 13726 -/* 2202 */ MCD_OPC_Decode, 151, 4, 99, // Opcode: C_ULT_S -/* 2206 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2224 -/* 2210 */ MCD_OPC_CheckPredicate, 13, 248, 44, // Skip to: 13726 -/* 2214 */ MCD_OPC_CheckField, 6, 5, 0, 242, 44, // Skip to: 13726 -/* 2220 */ MCD_OPC_Decode, 133, 4, 99, // Opcode: C_OLE_S -/* 2224 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2242 -/* 2228 */ MCD_OPC_CheckPredicate, 13, 230, 44, // Skip to: 13726 -/* 2232 */ MCD_OPC_CheckField, 6, 5, 0, 224, 44, // Skip to: 13726 -/* 2238 */ MCD_OPC_Decode, 148, 4, 99, // Opcode: C_ULE_S -/* 2242 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2260 -/* 2246 */ MCD_OPC_CheckPredicate, 13, 212, 44, // Skip to: 13726 -/* 2250 */ MCD_OPC_CheckField, 6, 5, 0, 206, 44, // Skip to: 13726 -/* 2256 */ MCD_OPC_Decode, 142, 4, 99, // Opcode: C_SF_S -/* 2260 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2278 -/* 2264 */ MCD_OPC_CheckPredicate, 13, 194, 44, // Skip to: 13726 -/* 2268 */ MCD_OPC_CheckField, 6, 5, 0, 188, 44, // Skip to: 13726 -/* 2274 */ MCD_OPC_Decode, 252, 3, 99, // Opcode: C_NGLE_S -/* 2278 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2296 -/* 2282 */ MCD_OPC_CheckPredicate, 13, 176, 44, // Skip to: 13726 -/* 2286 */ MCD_OPC_CheckField, 6, 5, 0, 170, 44, // Skip to: 13726 -/* 2292 */ MCD_OPC_Decode, 139, 4, 99, // Opcode: C_SEQ_S -/* 2296 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2314 -/* 2300 */ MCD_OPC_CheckPredicate, 13, 158, 44, // Skip to: 13726 -/* 2304 */ MCD_OPC_CheckField, 6, 5, 0, 152, 44, // Skip to: 13726 -/* 2310 */ MCD_OPC_Decode, 255, 3, 99, // Opcode: C_NGL_S -/* 2314 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2332 -/* 2318 */ MCD_OPC_CheckPredicate, 13, 140, 44, // Skip to: 13726 -/* 2322 */ MCD_OPC_CheckField, 6, 5, 0, 134, 44, // Skip to: 13726 -/* 2328 */ MCD_OPC_Decode, 246, 3, 99, // Opcode: C_LT_S -/* 2332 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2350 -/* 2336 */ MCD_OPC_CheckPredicate, 13, 122, 44, // Skip to: 13726 -/* 2340 */ MCD_OPC_CheckField, 6, 5, 0, 116, 44, // Skip to: 13726 -/* 2346 */ MCD_OPC_Decode, 249, 3, 99, // Opcode: C_NGE_S -/* 2350 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2368 -/* 2354 */ MCD_OPC_CheckPredicate, 13, 104, 44, // Skip to: 13726 -/* 2358 */ MCD_OPC_CheckField, 6, 5, 0, 98, 44, // Skip to: 13726 -/* 2364 */ MCD_OPC_Decode, 243, 3, 99, // Opcode: C_LE_S -/* 2368 */ MCD_OPC_FilterValue, 63, 90, 44, // Skip to: 13726 -/* 2372 */ MCD_OPC_CheckPredicate, 13, 86, 44, // Skip to: 13726 -/* 2376 */ MCD_OPC_CheckField, 6, 5, 0, 80, 44, // Skip to: 13726 -/* 2382 */ MCD_OPC_Decode, 130, 4, 99, // Opcode: C_NGT_S -/* 2386 */ MCD_OPC_FilterValue, 17, 80, 2, // Skip to: 2982 -/* 2390 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2393 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2405 -/* 2397 */ MCD_OPC_CheckPredicate, 21, 61, 44, // Skip to: 13726 -/* 2401 */ MCD_OPC_Decode, 171, 5, 100, // Opcode: FADD_D32 -/* 2405 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2417 -/* 2409 */ MCD_OPC_CheckPredicate, 21, 49, 44, // Skip to: 13726 -/* 2413 */ MCD_OPC_Decode, 173, 6, 100, // Opcode: FSUB_D32 -/* 2417 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2429 -/* 2421 */ MCD_OPC_CheckPredicate, 21, 37, 44, // Skip to: 13726 -/* 2425 */ MCD_OPC_Decode, 136, 6, 100, // Opcode: FMUL_D32 -/* 2429 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2441 -/* 2433 */ MCD_OPC_CheckPredicate, 21, 25, 44, // Skip to: 13726 -/* 2437 */ MCD_OPC_Decode, 207, 5, 100, // Opcode: FDIV_D32 -/* 2441 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2459 -/* 2445 */ MCD_OPC_CheckPredicate, 23, 13, 44, // Skip to: 13726 -/* 2449 */ MCD_OPC_CheckField, 16, 5, 0, 7, 44, // Skip to: 13726 -/* 2455 */ MCD_OPC_Decode, 166, 6, 101, // Opcode: FSQRT_D32 -/* 2459 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2477 -/* 2463 */ MCD_OPC_CheckPredicate, 21, 251, 43, // Skip to: 13726 -/* 2467 */ MCD_OPC_CheckField, 16, 5, 0, 245, 43, // Skip to: 13726 -/* 2473 */ MCD_OPC_Decode, 164, 5, 101, // Opcode: FABS_D32 -/* 2477 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2495 -/* 2481 */ MCD_OPC_CheckPredicate, 21, 233, 43, // Skip to: 13726 -/* 2485 */ MCD_OPC_CheckField, 16, 5, 0, 227, 43, // Skip to: 13726 -/* 2491 */ MCD_OPC_Decode, 128, 6, 101, // Opcode: FMOV_D32 -/* 2495 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2513 -/* 2499 */ MCD_OPC_CheckPredicate, 21, 215, 43, // Skip to: 13726 -/* 2503 */ MCD_OPC_CheckField, 16, 5, 0, 209, 43, // Skip to: 13726 -/* 2509 */ MCD_OPC_Decode, 142, 6, 101, // Opcode: FNEG_D32 -/* 2513 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 2531 -/* 2517 */ MCD_OPC_CheckPredicate, 23, 197, 43, // Skip to: 13726 -/* 2521 */ MCD_OPC_CheckField, 16, 5, 0, 191, 43, // Skip to: 13726 -/* 2527 */ MCD_OPC_Decode, 253, 10, 102, // Opcode: ROUND_W_D32 -/* 2531 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 2549 -/* 2535 */ MCD_OPC_CheckPredicate, 23, 179, 43, // Skip to: 13726 -/* 2539 */ MCD_OPC_CheckField, 16, 5, 0, 173, 43, // Skip to: 13726 -/* 2545 */ MCD_OPC_Decode, 216, 13, 102, // Opcode: TRUNC_W_D32 -/* 2549 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 2567 -/* 2553 */ MCD_OPC_CheckPredicate, 23, 161, 43, // Skip to: 13726 -/* 2557 */ MCD_OPC_CheckField, 16, 5, 0, 155, 43, // Skip to: 13726 -/* 2563 */ MCD_OPC_Decode, 225, 2, 102, // Opcode: CEIL_W_D32 -/* 2567 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 2585 -/* 2571 */ MCD_OPC_CheckPredicate, 23, 143, 43, // Skip to: 13726 -/* 2575 */ MCD_OPC_CheckField, 16, 5, 0, 137, 43, // Skip to: 13726 -/* 2581 */ MCD_OPC_Decode, 241, 5, 102, // Opcode: FLOOR_W_D32 -/* 2585 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2616 -/* 2589 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 2592 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2604 -/* 2596 */ MCD_OPC_CheckPredicate, 24, 118, 43, // Skip to: 13726 -/* 2600 */ MCD_OPC_Decode, 236, 8, 103, // Opcode: MOVF_D32 -/* 2604 */ MCD_OPC_FilterValue, 1, 110, 43, // Skip to: 13726 -/* 2608 */ MCD_OPC_CheckPredicate, 24, 106, 43, // Skip to: 13726 -/* 2612 */ MCD_OPC_Decode, 128, 9, 103, // Opcode: MOVT_D32 -/* 2616 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2628 -/* 2620 */ MCD_OPC_CheckPredicate, 24, 94, 43, // Skip to: 13726 -/* 2624 */ MCD_OPC_Decode, 140, 9, 104, // Opcode: MOVZ_I_D32 -/* 2628 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2640 -/* 2632 */ MCD_OPC_CheckPredicate, 24, 82, 43, // Skip to: 13726 -/* 2636 */ MCD_OPC_Decode, 248, 8, 104, // Opcode: MOVN_I_D32 -/* 2640 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2658 -/* 2644 */ MCD_OPC_CheckPredicate, 21, 70, 43, // Skip to: 13726 -/* 2648 */ MCD_OPC_CheckField, 16, 5, 0, 64, 43, // Skip to: 13726 -/* 2654 */ MCD_OPC_Decode, 224, 3, 102, // Opcode: CVT_S_D32 -/* 2658 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2676 -/* 2662 */ MCD_OPC_CheckPredicate, 21, 52, 43, // Skip to: 13726 -/* 2666 */ MCD_OPC_CheckField, 16, 5, 0, 46, 43, // Skip to: 13726 -/* 2672 */ MCD_OPC_Decode, 230, 3, 102, // Opcode: CVT_W_D32 -/* 2676 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2694 -/* 2680 */ MCD_OPC_CheckPredicate, 22, 34, 43, // Skip to: 13726 -/* 2684 */ MCD_OPC_CheckField, 16, 5, 0, 28, 43, // Skip to: 13726 -/* 2690 */ MCD_OPC_Decode, 220, 3, 105, // Opcode: CVT_L_D64 -/* 2694 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2712 -/* 2698 */ MCD_OPC_CheckPredicate, 25, 16, 43, // Skip to: 13726 -/* 2702 */ MCD_OPC_CheckField, 6, 5, 0, 10, 43, // Skip to: 13726 -/* 2708 */ MCD_OPC_Decode, 238, 3, 106, // Opcode: C_F_D32 -/* 2712 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2730 -/* 2716 */ MCD_OPC_CheckPredicate, 25, 254, 42, // Skip to: 13726 -/* 2720 */ MCD_OPC_CheckField, 6, 5, 0, 248, 42, // Skip to: 13726 -/* 2726 */ MCD_OPC_Decode, 152, 4, 106, // Opcode: C_UN_D32 -/* 2730 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2748 -/* 2734 */ MCD_OPC_CheckPredicate, 25, 236, 42, // Skip to: 13726 -/* 2738 */ MCD_OPC_CheckField, 6, 5, 0, 230, 42, // Skip to: 13726 -/* 2744 */ MCD_OPC_Decode, 235, 3, 106, // Opcode: C_EQ_D32 -/* 2748 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2766 -/* 2752 */ MCD_OPC_CheckPredicate, 25, 218, 42, // Skip to: 13726 -/* 2756 */ MCD_OPC_CheckField, 6, 5, 0, 212, 42, // Skip to: 13726 -/* 2762 */ MCD_OPC_Decode, 143, 4, 106, // Opcode: C_UEQ_D32 -/* 2766 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2784 -/* 2770 */ MCD_OPC_CheckPredicate, 25, 200, 42, // Skip to: 13726 -/* 2774 */ MCD_OPC_CheckField, 6, 5, 0, 194, 42, // Skip to: 13726 -/* 2780 */ MCD_OPC_Decode, 134, 4, 106, // Opcode: C_OLT_D32 -/* 2784 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2802 -/* 2788 */ MCD_OPC_CheckPredicate, 25, 182, 42, // Skip to: 13726 -/* 2792 */ MCD_OPC_CheckField, 6, 5, 0, 176, 42, // Skip to: 13726 -/* 2798 */ MCD_OPC_Decode, 149, 4, 106, // Opcode: C_ULT_D32 -/* 2802 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2820 -/* 2806 */ MCD_OPC_CheckPredicate, 25, 164, 42, // Skip to: 13726 -/* 2810 */ MCD_OPC_CheckField, 6, 5, 0, 158, 42, // Skip to: 13726 -/* 2816 */ MCD_OPC_Decode, 131, 4, 106, // Opcode: C_OLE_D32 -/* 2820 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2838 -/* 2824 */ MCD_OPC_CheckPredicate, 25, 146, 42, // Skip to: 13726 -/* 2828 */ MCD_OPC_CheckField, 6, 5, 0, 140, 42, // Skip to: 13726 -/* 2834 */ MCD_OPC_Decode, 146, 4, 106, // Opcode: C_ULE_D32 -/* 2838 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2856 -/* 2842 */ MCD_OPC_CheckPredicate, 25, 128, 42, // Skip to: 13726 -/* 2846 */ MCD_OPC_CheckField, 6, 5, 0, 122, 42, // Skip to: 13726 -/* 2852 */ MCD_OPC_Decode, 140, 4, 106, // Opcode: C_SF_D32 -/* 2856 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2874 -/* 2860 */ MCD_OPC_CheckPredicate, 25, 110, 42, // Skip to: 13726 -/* 2864 */ MCD_OPC_CheckField, 6, 5, 0, 104, 42, // Skip to: 13726 -/* 2870 */ MCD_OPC_Decode, 250, 3, 106, // Opcode: C_NGLE_D32 -/* 2874 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2892 -/* 2878 */ MCD_OPC_CheckPredicate, 25, 92, 42, // Skip to: 13726 -/* 2882 */ MCD_OPC_CheckField, 6, 5, 0, 86, 42, // Skip to: 13726 -/* 2888 */ MCD_OPC_Decode, 137, 4, 106, // Opcode: C_SEQ_D32 -/* 2892 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2910 -/* 2896 */ MCD_OPC_CheckPredicate, 25, 74, 42, // Skip to: 13726 -/* 2900 */ MCD_OPC_CheckField, 6, 5, 0, 68, 42, // Skip to: 13726 -/* 2906 */ MCD_OPC_Decode, 253, 3, 106, // Opcode: C_NGL_D32 -/* 2910 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2928 -/* 2914 */ MCD_OPC_CheckPredicate, 25, 56, 42, // Skip to: 13726 -/* 2918 */ MCD_OPC_CheckField, 6, 5, 0, 50, 42, // Skip to: 13726 -/* 2924 */ MCD_OPC_Decode, 244, 3, 106, // Opcode: C_LT_D32 -/* 2928 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2946 -/* 2932 */ MCD_OPC_CheckPredicate, 25, 38, 42, // Skip to: 13726 -/* 2936 */ MCD_OPC_CheckField, 6, 5, 0, 32, 42, // Skip to: 13726 -/* 2942 */ MCD_OPC_Decode, 247, 3, 106, // Opcode: C_NGE_D32 -/* 2946 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2964 -/* 2950 */ MCD_OPC_CheckPredicate, 25, 20, 42, // Skip to: 13726 -/* 2954 */ MCD_OPC_CheckField, 6, 5, 0, 14, 42, // Skip to: 13726 -/* 2960 */ MCD_OPC_Decode, 241, 3, 106, // Opcode: C_LE_D32 -/* 2964 */ MCD_OPC_FilterValue, 63, 6, 42, // Skip to: 13726 -/* 2968 */ MCD_OPC_CheckPredicate, 25, 2, 42, // Skip to: 13726 -/* 2972 */ MCD_OPC_CheckField, 6, 5, 0, 252, 41, // Skip to: 13726 -/* 2978 */ MCD_OPC_Decode, 128, 4, 106, // Opcode: C_NGT_D32 -/* 2982 */ MCD_OPC_FilterValue, 20, 39, 0, // Skip to: 3025 -/* 2986 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2989 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3007 -/* 2993 */ MCD_OPC_CheckPredicate, 5, 233, 41, // Skip to: 13726 -/* 2997 */ MCD_OPC_CheckField, 16, 5, 0, 227, 41, // Skip to: 13726 -/* 3003 */ MCD_OPC_Decode, 228, 3, 94, // Opcode: CVT_S_W -/* 3007 */ MCD_OPC_FilterValue, 33, 219, 41, // Skip to: 13726 -/* 3011 */ MCD_OPC_CheckPredicate, 21, 215, 41, // Skip to: 13726 -/* 3015 */ MCD_OPC_CheckField, 16, 5, 0, 209, 41, // Skip to: 13726 -/* 3021 */ MCD_OPC_Decode, 214, 3, 97, // Opcode: CVT_D32_W -/* 3025 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 3037 -/* 3029 */ MCD_OPC_CheckPredicate, 8, 197, 41, // Skip to: 13726 -/* 3033 */ MCD_OPC_Decode, 189, 2, 92, // Opcode: BZ_B -/* 3037 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 3049 -/* 3041 */ MCD_OPC_CheckPredicate, 8, 185, 41, // Skip to: 13726 -/* 3045 */ MCD_OPC_Decode, 191, 2, 107, // Opcode: BZ_H -/* 3049 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 3061 -/* 3053 */ MCD_OPC_CheckPredicate, 8, 173, 41, // Skip to: 13726 -/* 3057 */ MCD_OPC_Decode, 193, 2, 108, // Opcode: BZ_W -/* 3061 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 3073 -/* 3065 */ MCD_OPC_CheckPredicate, 8, 161, 41, // Skip to: 13726 -/* 3069 */ MCD_OPC_Decode, 190, 2, 109, // Opcode: BZ_D -/* 3073 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 3085 -/* 3077 */ MCD_OPC_CheckPredicate, 8, 149, 41, // Skip to: 13726 -/* 3081 */ MCD_OPC_Decode, 163, 2, 92, // Opcode: BNZ_B -/* 3085 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3097 -/* 3089 */ MCD_OPC_CheckPredicate, 8, 137, 41, // Skip to: 13726 -/* 3093 */ MCD_OPC_Decode, 165, 2, 107, // Opcode: BNZ_H -/* 3097 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 3109 -/* 3101 */ MCD_OPC_CheckPredicate, 8, 125, 41, // Skip to: 13726 -/* 3105 */ MCD_OPC_Decode, 167, 2, 108, // Opcode: BNZ_W -/* 3109 */ MCD_OPC_FilterValue, 31, 117, 41, // Skip to: 13726 -/* 3113 */ MCD_OPC_CheckPredicate, 8, 113, 41, // Skip to: 13726 -/* 3117 */ MCD_OPC_Decode, 164, 2, 109, // Opcode: BNZ_D -/* 3121 */ MCD_OPC_FilterValue, 18, 94, 0, // Skip to: 3219 -/* 3125 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3128 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3146 -/* 3132 */ MCD_OPC_CheckPredicate, 5, 94, 41, // Skip to: 13726 -/* 3136 */ MCD_OPC_CheckField, 3, 8, 0, 88, 41, // Skip to: 13726 -/* 3142 */ MCD_OPC_Decode, 182, 8, 81, // Opcode: MFC2 -/* 3146 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 3164 -/* 3150 */ MCD_OPC_CheckPredicate, 5, 76, 41, // Skip to: 13726 -/* 3154 */ MCD_OPC_CheckField, 3, 8, 0, 70, 41, // Skip to: 13726 -/* 3160 */ MCD_OPC_Decode, 172, 9, 81, // Opcode: MTC2 -/* 3164 */ MCD_OPC_FilterValue, 8, 62, 41, // Skip to: 13726 -/* 3168 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 3171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3183 -/* 3175 */ MCD_OPC_CheckPredicate, 13, 51, 41, // Skip to: 13726 -/* 3179 */ MCD_OPC_Decode, 189, 1, 82, // Opcode: BC2F -/* 3183 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3195 -/* 3187 */ MCD_OPC_CheckPredicate, 13, 39, 41, // Skip to: 13726 -/* 3191 */ MCD_OPC_Decode, 192, 1, 82, // Opcode: BC2T -/* 3195 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3207 -/* 3199 */ MCD_OPC_CheckPredicate, 13, 27, 41, // Skip to: 13726 -/* 3203 */ MCD_OPC_Decode, 190, 1, 82, // Opcode: BC2FL -/* 3207 */ MCD_OPC_FilterValue, 3, 19, 41, // Skip to: 13726 -/* 3211 */ MCD_OPC_CheckPredicate, 13, 15, 41, // Skip to: 13726 -/* 3215 */ MCD_OPC_Decode, 193, 1, 82, // Opcode: BC2TL -/* 3219 */ MCD_OPC_FilterValue, 19, 9, 1, // Skip to: 3488 -/* 3223 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3226 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 3281 -/* 3230 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 3233 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3245 -/* 3237 */ MCD_OPC_CheckPredicate, 13, 40, 0, // Skip to: 3281 -/* 3241 */ MCD_OPC_Decode, 194, 1, 82, // Opcode: BC3F -/* 3245 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3257 -/* 3249 */ MCD_OPC_CheckPredicate, 13, 28, 0, // Skip to: 3281 -/* 3253 */ MCD_OPC_Decode, 196, 1, 82, // Opcode: BC3T -/* 3257 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3269 -/* 3261 */ MCD_OPC_CheckPredicate, 13, 16, 0, // Skip to: 3281 -/* 3265 */ MCD_OPC_Decode, 195, 1, 82, // Opcode: BC3FL -/* 3269 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3281 -/* 3273 */ MCD_OPC_CheckPredicate, 13, 4, 0, // Skip to: 3281 -/* 3277 */ MCD_OPC_Decode, 197, 1, 82, // Opcode: BC3TL -/* 3281 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3302 -/* 3288 */ MCD_OPC_CheckPredicate, 26, 194, 40, // Skip to: 13726 -/* 3292 */ MCD_OPC_CheckField, 11, 5, 0, 188, 40, // Skip to: 13726 -/* 3298 */ MCD_OPC_Decode, 237, 7, 110, // Opcode: LWXC1 -/* 3302 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3320 -/* 3306 */ MCD_OPC_CheckPredicate, 27, 176, 40, // Skip to: 13726 -/* 3310 */ MCD_OPC_CheckField, 11, 5, 0, 170, 40, // Skip to: 13726 -/* 3316 */ MCD_OPC_Decode, 175, 7, 111, // Opcode: LDXC1 -/* 3320 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 3338 -/* 3324 */ MCD_OPC_CheckPredicate, 28, 158, 40, // Skip to: 13726 -/* 3328 */ MCD_OPC_CheckField, 11, 5, 0, 152, 40, // Skip to: 13726 -/* 3334 */ MCD_OPC_Decode, 207, 7, 111, // Opcode: LUXC1 -/* 3338 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3356 -/* 3342 */ MCD_OPC_CheckPredicate, 26, 140, 40, // Skip to: 13726 -/* 3346 */ MCD_OPC_CheckField, 6, 5, 0, 134, 40, // Skip to: 13726 -/* 3352 */ MCD_OPC_Decode, 254, 12, 112, // Opcode: SWXC1 -/* 3356 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3374 -/* 3360 */ MCD_OPC_CheckPredicate, 27, 122, 40, // Skip to: 13726 -/* 3364 */ MCD_OPC_CheckField, 6, 5, 0, 116, 40, // Skip to: 13726 -/* 3370 */ MCD_OPC_Decode, 166, 11, 113, // Opcode: SDXC1 -/* 3374 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 3392 -/* 3378 */ MCD_OPC_CheckPredicate, 28, 104, 40, // Skip to: 13726 -/* 3382 */ MCD_OPC_CheckField, 6, 5, 0, 98, 40, // Skip to: 13726 -/* 3388 */ MCD_OPC_Decode, 232, 12, 113, // Opcode: SUXC1 -/* 3392 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3404 -/* 3396 */ MCD_OPC_CheckPredicate, 26, 86, 40, // Skip to: 13726 -/* 3400 */ MCD_OPC_Decode, 149, 8, 114, // Opcode: MADD_S -/* 3404 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3416 -/* 3408 */ MCD_OPC_CheckPredicate, 29, 74, 40, // Skip to: 13726 -/* 3412 */ MCD_OPC_Decode, 142, 8, 115, // Opcode: MADD_D32 -/* 3416 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3428 -/* 3420 */ MCD_OPC_CheckPredicate, 26, 62, 40, // Skip to: 13726 -/* 3424 */ MCD_OPC_Decode, 167, 9, 114, // Opcode: MSUB_S -/* 3428 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3440 -/* 3432 */ MCD_OPC_CheckPredicate, 29, 50, 40, // Skip to: 13726 -/* 3436 */ MCD_OPC_Decode, 160, 9, 115, // Opcode: MSUB_D32 -/* 3440 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 3452 -/* 3444 */ MCD_OPC_CheckPredicate, 26, 38, 40, // Skip to: 13726 -/* 3448 */ MCD_OPC_Decode, 242, 9, 114, // Opcode: NMADD_S -/* 3452 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3464 -/* 3456 */ MCD_OPC_CheckPredicate, 29, 26, 40, // Skip to: 13726 -/* 3460 */ MCD_OPC_Decode, 239, 9, 115, // Opcode: NMADD_D32 -/* 3464 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 3476 -/* 3468 */ MCD_OPC_CheckPredicate, 26, 14, 40, // Skip to: 13726 -/* 3472 */ MCD_OPC_Decode, 247, 9, 114, // Opcode: NMSUB_S -/* 3476 */ MCD_OPC_FilterValue, 57, 6, 40, // Skip to: 13726 -/* 3480 */ MCD_OPC_CheckPredicate, 29, 2, 40, // Skip to: 13726 -/* 3484 */ MCD_OPC_Decode, 244, 9, 115, // Opcode: NMSUB_D32 -/* 3488 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 3500 -/* 3492 */ MCD_OPC_CheckPredicate, 16, 246, 39, // Skip to: 13726 -/* 3496 */ MCD_OPC_Decode, 209, 1, 78, // Opcode: BEQL -/* 3500 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 3512 -/* 3504 */ MCD_OPC_CheckPredicate, 16, 234, 39, // Skip to: 13726 -/* 3508 */ MCD_OPC_Decode, 156, 2, 78, // Opcode: BNEL -/* 3512 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 3530 -/* 3516 */ MCD_OPC_CheckPredicate, 16, 222, 39, // Skip to: 13726 -/* 3520 */ MCD_OPC_CheckField, 16, 5, 0, 216, 39, // Skip to: 13726 -/* 3526 */ MCD_OPC_Decode, 255, 1, 73, // Opcode: BLEZL -/* 3530 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3548 -/* 3534 */ MCD_OPC_CheckPredicate, 16, 204, 39, // Skip to: 13726 -/* 3538 */ MCD_OPC_CheckField, 16, 5, 0, 198, 39, // Skip to: 13726 -/* 3544 */ MCD_OPC_Decode, 231, 1, 73, // Opcode: BGTZL -/* 3548 */ MCD_OPC_FilterValue, 28, 229, 0, // Skip to: 3781 -/* 3552 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3555 */ MCD_OPC_FilterValue, 0, 36, 0, // Skip to: 3595 -/* 3559 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3562 */ MCD_OPC_FilterValue, 0, 176, 39, // Skip to: 13726 -/* 3566 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3569 */ MCD_OPC_FilterValue, 0, 169, 39, // Skip to: 13726 -/* 3573 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3587 -/* 3577 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3587 -/* 3583 */ MCD_OPC_Decode, 130, 8, 43, // Opcode: MADD -/* 3587 */ MCD_OPC_CheckPredicate, 12, 151, 39, // Skip to: 13726 -/* 3591 */ MCD_OPC_Decode, 145, 8, 116, // Opcode: MADD_DSP -/* 3595 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 3635 -/* 3599 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3602 */ MCD_OPC_FilterValue, 0, 136, 39, // Skip to: 13726 -/* 3606 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3609 */ MCD_OPC_FilterValue, 0, 129, 39, // Skip to: 13726 -/* 3613 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3627 -/* 3617 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3627 -/* 3623 */ MCD_OPC_Decode, 135, 8, 43, // Opcode: MADDU -/* 3627 */ MCD_OPC_CheckPredicate, 12, 111, 39, // Skip to: 13726 -/* 3631 */ MCD_OPC_Decode, 136, 8, 116, // Opcode: MADDU_DSP -/* 3635 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3653 -/* 3639 */ MCD_OPC_CheckPredicate, 9, 99, 39, // Skip to: 13726 -/* 3643 */ MCD_OPC_CheckField, 6, 5, 0, 93, 39, // Skip to: 13726 -/* 3649 */ MCD_OPC_Decode, 193, 9, 35, // Opcode: MUL -/* 3653 */ MCD_OPC_FilterValue, 4, 36, 0, // Skip to: 3693 -/* 3657 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3660 */ MCD_OPC_FilterValue, 0, 78, 39, // Skip to: 13726 -/* 3664 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3667 */ MCD_OPC_FilterValue, 0, 71, 39, // Skip to: 13726 -/* 3671 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3685 -/* 3675 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3685 -/* 3681 */ MCD_OPC_Decode, 148, 9, 43, // Opcode: MSUB -/* 3685 */ MCD_OPC_CheckPredicate, 12, 53, 39, // Skip to: 13726 -/* 3689 */ MCD_OPC_Decode, 163, 9, 116, // Opcode: MSUB_DSP -/* 3693 */ MCD_OPC_FilterValue, 5, 36, 0, // Skip to: 3733 -/* 3697 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3700 */ MCD_OPC_FilterValue, 0, 38, 39, // Skip to: 13726 -/* 3704 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3707 */ MCD_OPC_FilterValue, 0, 31, 39, // Skip to: 13726 -/* 3711 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3725 -/* 3715 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3725 -/* 3721 */ MCD_OPC_Decode, 153, 9, 43, // Opcode: MSUBU -/* 3725 */ MCD_OPC_CheckPredicate, 12, 13, 39, // Skip to: 13726 -/* 3729 */ MCD_OPC_Decode, 154, 9, 116, // Opcode: MSUBU_DSP -/* 3733 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3751 -/* 3737 */ MCD_OPC_CheckPredicate, 9, 1, 39, // Skip to: 13726 -/* 3741 */ MCD_OPC_CheckField, 6, 5, 0, 251, 38, // Skip to: 13726 -/* 3747 */ MCD_OPC_Decode, 152, 3, 117, // Opcode: CLZ -/* 3751 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3769 -/* 3755 */ MCD_OPC_CheckPredicate, 9, 239, 38, // Skip to: 13726 -/* 3759 */ MCD_OPC_CheckField, 6, 5, 0, 233, 38, // Skip to: 13726 -/* 3765 */ MCD_OPC_Decode, 133, 3, 117, // Opcode: CLO -/* 3769 */ MCD_OPC_FilterValue, 63, 225, 38, // Skip to: 13726 -/* 3773 */ MCD_OPC_CheckPredicate, 9, 221, 38, // Skip to: 13726 -/* 3777 */ MCD_OPC_Decode, 152, 11, 64, // Opcode: SDBBP -/* 3781 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3793 -/* 3785 */ MCD_OPC_CheckPredicate, 9, 209, 38, // Skip to: 13726 -/* 3789 */ MCD_OPC_Decode, 131, 7, 77, // Opcode: JALX -/* 3793 */ MCD_OPC_FilterValue, 30, 28, 28, // Skip to: 10993 -/* 3797 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3800 */ MCD_OPC_FilterValue, 0, 50, 0, // Skip to: 3854 -/* 3804 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3807 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3818 -/* 3811 */ MCD_OPC_CheckPredicate, 8, 183, 38, // Skip to: 13726 -/* 3815 */ MCD_OPC_Decode, 87, 118, // Opcode: ANDI_B -/* 3818 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3830 -/* 3822 */ MCD_OPC_CheckPredicate, 8, 172, 38, // Skip to: 13726 -/* 3826 */ MCD_OPC_Decode, 136, 10, 118, // Opcode: ORI_B -/* 3830 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3842 -/* 3834 */ MCD_OPC_CheckPredicate, 8, 160, 38, // Skip to: 13726 -/* 3838 */ MCD_OPC_Decode, 252, 9, 118, // Opcode: NORI_B -/* 3842 */ MCD_OPC_FilterValue, 3, 152, 38, // Skip to: 13726 -/* 3846 */ MCD_OPC_CheckPredicate, 8, 148, 38, // Skip to: 13726 -/* 3850 */ MCD_OPC_Decode, 239, 13, 118, // Opcode: XORI_B -/* 3854 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 3897 -/* 3858 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3861 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3873 -/* 3865 */ MCD_OPC_CheckPredicate, 8, 129, 38, // Skip to: 13726 -/* 3869 */ MCD_OPC_Decode, 141, 2, 119, // Opcode: BMNZI_B -/* 3873 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3885 -/* 3877 */ MCD_OPC_CheckPredicate, 8, 117, 38, // Skip to: 13726 -/* 3881 */ MCD_OPC_Decode, 143, 2, 119, // Opcode: BMZI_B -/* 3885 */ MCD_OPC_FilterValue, 2, 109, 38, // Skip to: 13726 -/* 3889 */ MCD_OPC_CheckPredicate, 8, 105, 38, // Skip to: 13726 -/* 3893 */ MCD_OPC_Decode, 174, 2, 119, // Opcode: BSELI_B -/* 3897 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 3940 -/* 3901 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3904 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3916 -/* 3908 */ MCD_OPC_CheckPredicate, 8, 86, 38, // Skip to: 13726 -/* 3912 */ MCD_OPC_Decode, 189, 11, 118, // Opcode: SHF_B -/* 3916 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3928 -/* 3920 */ MCD_OPC_CheckPredicate, 8, 74, 38, // Skip to: 13726 -/* 3924 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: SHF_H -/* 3928 */ MCD_OPC_FilterValue, 2, 66, 38, // Skip to: 13726 -/* 3932 */ MCD_OPC_CheckPredicate, 8, 62, 38, // Skip to: 13726 -/* 3936 */ MCD_OPC_Decode, 191, 11, 121, // Opcode: SHF_W -/* 3940 */ MCD_OPC_FilterValue, 6, 31, 1, // Skip to: 4231 -/* 3944 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3947 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3958 -/* 3951 */ MCD_OPC_CheckPredicate, 8, 43, 38, // Skip to: 13726 -/* 3955 */ MCD_OPC_Decode, 59, 122, // Opcode: ADDVI_B -/* 3958 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 3969 -/* 3962 */ MCD_OPC_CheckPredicate, 8, 32, 38, // Skip to: 13726 -/* 3966 */ MCD_OPC_Decode, 61, 123, // Opcode: ADDVI_H -/* 3969 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3980 -/* 3973 */ MCD_OPC_CheckPredicate, 8, 21, 38, // Skip to: 13726 -/* 3977 */ MCD_OPC_Decode, 62, 124, // Opcode: ADDVI_W -/* 3980 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 3991 -/* 3984 */ MCD_OPC_CheckPredicate, 8, 10, 38, // Skip to: 13726 -/* 3988 */ MCD_OPC_Decode, 60, 125, // Opcode: ADDVI_D -/* 3991 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 4003 -/* 3995 */ MCD_OPC_CheckPredicate, 8, 255, 37, // Skip to: 13726 -/* 3999 */ MCD_OPC_Decode, 221, 12, 122, // Opcode: SUBVI_B -/* 4003 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 4015 -/* 4007 */ MCD_OPC_CheckPredicate, 8, 243, 37, // Skip to: 13726 -/* 4011 */ MCD_OPC_Decode, 223, 12, 123, // Opcode: SUBVI_H -/* 4015 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 4027 -/* 4019 */ MCD_OPC_CheckPredicate, 8, 231, 37, // Skip to: 13726 -/* 4023 */ MCD_OPC_Decode, 224, 12, 124, // Opcode: SUBVI_W -/* 4027 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 4039 -/* 4031 */ MCD_OPC_CheckPredicate, 8, 219, 37, // Skip to: 13726 -/* 4035 */ MCD_OPC_Decode, 222, 12, 125, // Opcode: SUBVI_D -/* 4039 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4051 -/* 4043 */ MCD_OPC_CheckPredicate, 8, 207, 37, // Skip to: 13726 -/* 4047 */ MCD_OPC_Decode, 157, 8, 122, // Opcode: MAXI_S_B -/* 4051 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4063 -/* 4055 */ MCD_OPC_CheckPredicate, 8, 195, 37, // Skip to: 13726 -/* 4059 */ MCD_OPC_Decode, 159, 8, 123, // Opcode: MAXI_S_H -/* 4063 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4075 -/* 4067 */ MCD_OPC_CheckPredicate, 8, 183, 37, // Skip to: 13726 -/* 4071 */ MCD_OPC_Decode, 160, 8, 124, // Opcode: MAXI_S_W -/* 4075 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4087 -/* 4079 */ MCD_OPC_CheckPredicate, 8, 171, 37, // Skip to: 13726 -/* 4083 */ MCD_OPC_Decode, 158, 8, 125, // Opcode: MAXI_S_D -/* 4087 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4099 -/* 4091 */ MCD_OPC_CheckPredicate, 8, 159, 37, // Skip to: 13726 -/* 4095 */ MCD_OPC_Decode, 161, 8, 122, // Opcode: MAXI_U_B -/* 4099 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4111 -/* 4103 */ MCD_OPC_CheckPredicate, 8, 147, 37, // Skip to: 13726 -/* 4107 */ MCD_OPC_Decode, 163, 8, 123, // Opcode: MAXI_U_H -/* 4111 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4123 -/* 4115 */ MCD_OPC_CheckPredicate, 8, 135, 37, // Skip to: 13726 -/* 4119 */ MCD_OPC_Decode, 164, 8, 124, // Opcode: MAXI_U_W -/* 4123 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4135 -/* 4127 */ MCD_OPC_CheckPredicate, 8, 123, 37, // Skip to: 13726 -/* 4131 */ MCD_OPC_Decode, 162, 8, 125, // Opcode: MAXI_U_D -/* 4135 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4147 -/* 4139 */ MCD_OPC_CheckPredicate, 8, 111, 37, // Skip to: 13726 -/* 4143 */ MCD_OPC_Decode, 198, 8, 122, // Opcode: MINI_S_B -/* 4147 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4159 -/* 4151 */ MCD_OPC_CheckPredicate, 8, 99, 37, // Skip to: 13726 -/* 4155 */ MCD_OPC_Decode, 200, 8, 123, // Opcode: MINI_S_H -/* 4159 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4171 -/* 4163 */ MCD_OPC_CheckPredicate, 8, 87, 37, // Skip to: 13726 -/* 4167 */ MCD_OPC_Decode, 201, 8, 124, // Opcode: MINI_S_W -/* 4171 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4183 -/* 4175 */ MCD_OPC_CheckPredicate, 8, 75, 37, // Skip to: 13726 -/* 4179 */ MCD_OPC_Decode, 199, 8, 125, // Opcode: MINI_S_D -/* 4183 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4195 -/* 4187 */ MCD_OPC_CheckPredicate, 8, 63, 37, // Skip to: 13726 -/* 4191 */ MCD_OPC_Decode, 202, 8, 122, // Opcode: MINI_U_B -/* 4195 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4207 -/* 4199 */ MCD_OPC_CheckPredicate, 8, 51, 37, // Skip to: 13726 -/* 4203 */ MCD_OPC_Decode, 204, 8, 123, // Opcode: MINI_U_H -/* 4207 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4219 -/* 4211 */ MCD_OPC_CheckPredicate, 8, 39, 37, // Skip to: 13726 -/* 4215 */ MCD_OPC_Decode, 205, 8, 124, // Opcode: MINI_U_W -/* 4219 */ MCD_OPC_FilterValue, 23, 31, 37, // Skip to: 13726 -/* 4223 */ MCD_OPC_CheckPredicate, 8, 27, 37, // Skip to: 13726 -/* 4227 */ MCD_OPC_Decode, 203, 8, 125, // Opcode: MINI_U_D -/* 4231 */ MCD_OPC_FilterValue, 7, 37, 1, // Skip to: 4528 -/* 4235 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 4238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4250 -/* 4242 */ MCD_OPC_CheckPredicate, 8, 8, 37, // Skip to: 13726 -/* 4246 */ MCD_OPC_Decode, 230, 2, 122, // Opcode: CEQI_B -/* 4250 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 4262 -/* 4254 */ MCD_OPC_CheckPredicate, 8, 252, 36, // Skip to: 13726 -/* 4258 */ MCD_OPC_Decode, 232, 2, 123, // Opcode: CEQI_H -/* 4262 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 4274 -/* 4266 */ MCD_OPC_CheckPredicate, 8, 240, 36, // Skip to: 13726 -/* 4270 */ MCD_OPC_Decode, 233, 2, 124, // Opcode: CEQI_W -/* 4274 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 4286 -/* 4278 */ MCD_OPC_CheckPredicate, 8, 228, 36, // Skip to: 13726 -/* 4282 */ MCD_OPC_Decode, 231, 2, 125, // Opcode: CEQI_D -/* 4286 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4298 -/* 4290 */ MCD_OPC_CheckPredicate, 8, 216, 36, // Skip to: 13726 -/* 4294 */ MCD_OPC_Decode, 136, 3, 122, // Opcode: CLTI_S_B -/* 4298 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4310 -/* 4302 */ MCD_OPC_CheckPredicate, 8, 204, 36, // Skip to: 13726 -/* 4306 */ MCD_OPC_Decode, 138, 3, 123, // Opcode: CLTI_S_H -/* 4310 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4322 -/* 4314 */ MCD_OPC_CheckPredicate, 8, 192, 36, // Skip to: 13726 -/* 4318 */ MCD_OPC_Decode, 139, 3, 124, // Opcode: CLTI_S_W -/* 4322 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4334 -/* 4326 */ MCD_OPC_CheckPredicate, 8, 180, 36, // Skip to: 13726 -/* 4330 */ MCD_OPC_Decode, 137, 3, 125, // Opcode: CLTI_S_D -/* 4334 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4346 -/* 4338 */ MCD_OPC_CheckPredicate, 8, 168, 36, // Skip to: 13726 -/* 4342 */ MCD_OPC_Decode, 140, 3, 122, // Opcode: CLTI_U_B -/* 4346 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4358 -/* 4350 */ MCD_OPC_CheckPredicate, 8, 156, 36, // Skip to: 13726 -/* 4354 */ MCD_OPC_Decode, 142, 3, 123, // Opcode: CLTI_U_H -/* 4358 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4370 -/* 4362 */ MCD_OPC_CheckPredicate, 8, 144, 36, // Skip to: 13726 -/* 4366 */ MCD_OPC_Decode, 143, 3, 124, // Opcode: CLTI_U_W -/* 4370 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4382 -/* 4374 */ MCD_OPC_CheckPredicate, 8, 132, 36, // Skip to: 13726 -/* 4378 */ MCD_OPC_Decode, 141, 3, 125, // Opcode: CLTI_U_D -/* 4382 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4394 -/* 4386 */ MCD_OPC_CheckPredicate, 8, 120, 36, // Skip to: 13726 -/* 4390 */ MCD_OPC_Decode, 245, 2, 122, // Opcode: CLEI_S_B -/* 4394 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4406 -/* 4398 */ MCD_OPC_CheckPredicate, 8, 108, 36, // Skip to: 13726 -/* 4402 */ MCD_OPC_Decode, 247, 2, 123, // Opcode: CLEI_S_H -/* 4406 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4418 -/* 4410 */ MCD_OPC_CheckPredicate, 8, 96, 36, // Skip to: 13726 -/* 4414 */ MCD_OPC_Decode, 248, 2, 124, // Opcode: CLEI_S_W -/* 4418 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4430 -/* 4422 */ MCD_OPC_CheckPredicate, 8, 84, 36, // Skip to: 13726 -/* 4426 */ MCD_OPC_Decode, 246, 2, 125, // Opcode: CLEI_S_D -/* 4430 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4442 -/* 4434 */ MCD_OPC_CheckPredicate, 8, 72, 36, // Skip to: 13726 -/* 4438 */ MCD_OPC_Decode, 249, 2, 122, // Opcode: CLEI_U_B -/* 4442 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4454 -/* 4446 */ MCD_OPC_CheckPredicate, 8, 60, 36, // Skip to: 13726 -/* 4450 */ MCD_OPC_Decode, 251, 2, 123, // Opcode: CLEI_U_H -/* 4454 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4466 -/* 4458 */ MCD_OPC_CheckPredicate, 8, 48, 36, // Skip to: 13726 -/* 4462 */ MCD_OPC_Decode, 252, 2, 124, // Opcode: CLEI_U_W -/* 4466 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 4478 -/* 4470 */ MCD_OPC_CheckPredicate, 8, 36, 36, // Skip to: 13726 -/* 4474 */ MCD_OPC_Decode, 250, 2, 125, // Opcode: CLEI_U_D -/* 4478 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 4490 -/* 4482 */ MCD_OPC_CheckPredicate, 8, 24, 36, // Skip to: 13726 -/* 4486 */ MCD_OPC_Decode, 168, 7, 126, // Opcode: LDI_B -/* 4490 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 4502 -/* 4494 */ MCD_OPC_CheckPredicate, 8, 12, 36, // Skip to: 13726 -/* 4498 */ MCD_OPC_Decode, 170, 7, 127, // Opcode: LDI_H -/* 4502 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 4515 -/* 4506 */ MCD_OPC_CheckPredicate, 8, 0, 36, // Skip to: 13726 -/* 4510 */ MCD_OPC_Decode, 171, 7, 128, 1, // Opcode: LDI_W -/* 4515 */ MCD_OPC_FilterValue, 27, 247, 35, // Skip to: 13726 -/* 4519 */ MCD_OPC_CheckPredicate, 8, 243, 35, // Skip to: 13726 -/* 4523 */ MCD_OPC_Decode, 169, 7, 129, 1, // Opcode: LDI_D -/* 4528 */ MCD_OPC_FilterValue, 9, 61, 2, // Skip to: 5105 -/* 4532 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 4535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4548 -/* 4539 */ MCD_OPC_CheckPredicate, 8, 223, 35, // Skip to: 13726 -/* 4543 */ MCD_OPC_Decode, 230, 11, 130, 1, // Opcode: SLLI_D -/* 4548 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 4606 -/* 4552 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4555 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4567 -/* 4559 */ MCD_OPC_CheckPredicate, 8, 203, 35, // Skip to: 13726 -/* 4563 */ MCD_OPC_Decode, 232, 11, 124, // Opcode: SLLI_W -/* 4567 */ MCD_OPC_FilterValue, 1, 195, 35, // Skip to: 13726 -/* 4571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4574 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4587 -/* 4578 */ MCD_OPC_CheckPredicate, 8, 184, 35, // Skip to: 13726 -/* 4582 */ MCD_OPC_Decode, 231, 11, 131, 1, // Opcode: SLLI_H -/* 4587 */ MCD_OPC_FilterValue, 1, 175, 35, // Skip to: 13726 -/* 4591 */ MCD_OPC_CheckPredicate, 8, 171, 35, // Skip to: 13726 -/* 4595 */ MCD_OPC_CheckField, 19, 1, 0, 165, 35, // Skip to: 13726 -/* 4601 */ MCD_OPC_Decode, 229, 11, 132, 1, // Opcode: SLLI_B -/* 4606 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4619 -/* 4610 */ MCD_OPC_CheckPredicate, 8, 152, 35, // Skip to: 13726 -/* 4614 */ MCD_OPC_Decode, 141, 12, 130, 1, // Opcode: SRAI_D -/* 4619 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 4677 -/* 4623 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4626 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4638 -/* 4630 */ MCD_OPC_CheckPredicate, 8, 132, 35, // Skip to: 13726 -/* 4634 */ MCD_OPC_Decode, 143, 12, 124, // Opcode: SRAI_W -/* 4638 */ MCD_OPC_FilterValue, 1, 124, 35, // Skip to: 13726 -/* 4642 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4645 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4658 -/* 4649 */ MCD_OPC_CheckPredicate, 8, 113, 35, // Skip to: 13726 -/* 4653 */ MCD_OPC_Decode, 142, 12, 131, 1, // Opcode: SRAI_H -/* 4658 */ MCD_OPC_FilterValue, 1, 104, 35, // Skip to: 13726 -/* 4662 */ MCD_OPC_CheckPredicate, 8, 100, 35, // Skip to: 13726 -/* 4666 */ MCD_OPC_CheckField, 19, 1, 0, 94, 35, // Skip to: 13726 -/* 4672 */ MCD_OPC_Decode, 140, 12, 132, 1, // Opcode: SRAI_B -/* 4677 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 4690 -/* 4681 */ MCD_OPC_CheckPredicate, 8, 81, 35, // Skip to: 13726 -/* 4685 */ MCD_OPC_Decode, 162, 12, 130, 1, // Opcode: SRLI_D -/* 4690 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 4748 -/* 4694 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4697 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4709 -/* 4701 */ MCD_OPC_CheckPredicate, 8, 61, 35, // Skip to: 13726 -/* 4705 */ MCD_OPC_Decode, 164, 12, 124, // Opcode: SRLI_W -/* 4709 */ MCD_OPC_FilterValue, 1, 53, 35, // Skip to: 13726 -/* 4713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4716 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4729 -/* 4720 */ MCD_OPC_CheckPredicate, 8, 42, 35, // Skip to: 13726 -/* 4724 */ MCD_OPC_Decode, 163, 12, 131, 1, // Opcode: SRLI_H -/* 4729 */ MCD_OPC_FilterValue, 1, 33, 35, // Skip to: 13726 -/* 4733 */ MCD_OPC_CheckPredicate, 8, 29, 35, // Skip to: 13726 -/* 4737 */ MCD_OPC_CheckField, 19, 1, 0, 23, 35, // Skip to: 13726 -/* 4743 */ MCD_OPC_Decode, 161, 12, 132, 1, // Opcode: SRLI_B -/* 4748 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 4761 -/* 4752 */ MCD_OPC_CheckPredicate, 8, 10, 35, // Skip to: 13726 -/* 4756 */ MCD_OPC_Decode, 199, 1, 130, 1, // Opcode: BCLRI_D -/* 4761 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 4819 -/* 4765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4768 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4780 -/* 4772 */ MCD_OPC_CheckPredicate, 8, 246, 34, // Skip to: 13726 -/* 4776 */ MCD_OPC_Decode, 201, 1, 124, // Opcode: BCLRI_W -/* 4780 */ MCD_OPC_FilterValue, 1, 238, 34, // Skip to: 13726 -/* 4784 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4787 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4800 -/* 4791 */ MCD_OPC_CheckPredicate, 8, 227, 34, // Skip to: 13726 -/* 4795 */ MCD_OPC_Decode, 200, 1, 131, 1, // Opcode: BCLRI_H -/* 4800 */ MCD_OPC_FilterValue, 1, 218, 34, // Skip to: 13726 -/* 4804 */ MCD_OPC_CheckPredicate, 8, 214, 34, // Skip to: 13726 -/* 4808 */ MCD_OPC_CheckField, 19, 1, 0, 208, 34, // Skip to: 13726 -/* 4814 */ MCD_OPC_Decode, 198, 1, 132, 1, // Opcode: BCLRI_B -/* 4819 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 4832 -/* 4823 */ MCD_OPC_CheckPredicate, 8, 195, 34, // Skip to: 13726 -/* 4827 */ MCD_OPC_Decode, 182, 2, 130, 1, // Opcode: BSETI_D -/* 4832 */ MCD_OPC_FilterValue, 9, 54, 0, // Skip to: 4890 -/* 4836 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4839 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4851 -/* 4843 */ MCD_OPC_CheckPredicate, 8, 175, 34, // Skip to: 13726 -/* 4847 */ MCD_OPC_Decode, 184, 2, 124, // Opcode: BSETI_W -/* 4851 */ MCD_OPC_FilterValue, 1, 167, 34, // Skip to: 13726 -/* 4855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4858 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4871 -/* 4862 */ MCD_OPC_CheckPredicate, 8, 156, 34, // Skip to: 13726 -/* 4866 */ MCD_OPC_Decode, 183, 2, 131, 1, // Opcode: BSETI_H -/* 4871 */ MCD_OPC_FilterValue, 1, 147, 34, // Skip to: 13726 -/* 4875 */ MCD_OPC_CheckPredicate, 8, 143, 34, // Skip to: 13726 -/* 4879 */ MCD_OPC_CheckField, 19, 1, 0, 137, 34, // Skip to: 13726 -/* 4885 */ MCD_OPC_Decode, 181, 2, 132, 1, // Opcode: BSETI_B -/* 4890 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 4903 -/* 4894 */ MCD_OPC_CheckPredicate, 8, 124, 34, // Skip to: 13726 -/* 4898 */ MCD_OPC_Decode, 149, 2, 130, 1, // Opcode: BNEGI_D -/* 4903 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 4961 -/* 4907 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4910 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4922 -/* 4914 */ MCD_OPC_CheckPredicate, 8, 104, 34, // Skip to: 13726 -/* 4918 */ MCD_OPC_Decode, 151, 2, 124, // Opcode: BNEGI_W -/* 4922 */ MCD_OPC_FilterValue, 1, 96, 34, // Skip to: 13726 -/* 4926 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4929 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4942 -/* 4933 */ MCD_OPC_CheckPredicate, 8, 85, 34, // Skip to: 13726 -/* 4937 */ MCD_OPC_Decode, 150, 2, 131, 1, // Opcode: BNEGI_H -/* 4942 */ MCD_OPC_FilterValue, 1, 76, 34, // Skip to: 13726 -/* 4946 */ MCD_OPC_CheckPredicate, 8, 72, 34, // Skip to: 13726 -/* 4950 */ MCD_OPC_CheckField, 19, 1, 0, 66, 34, // Skip to: 13726 -/* 4956 */ MCD_OPC_Decode, 148, 2, 132, 1, // Opcode: BNEGI_B -/* 4961 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 4974 -/* 4965 */ MCD_OPC_CheckPredicate, 8, 53, 34, // Skip to: 13726 -/* 4969 */ MCD_OPC_Decode, 234, 1, 133, 1, // Opcode: BINSLI_D -/* 4974 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 5033 -/* 4978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4981 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4994 -/* 4985 */ MCD_OPC_CheckPredicate, 8, 33, 34, // Skip to: 13726 -/* 4989 */ MCD_OPC_Decode, 236, 1, 134, 1, // Opcode: BINSLI_W -/* 4994 */ MCD_OPC_FilterValue, 1, 24, 34, // Skip to: 13726 -/* 4998 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5001 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5014 -/* 5005 */ MCD_OPC_CheckPredicate, 8, 13, 34, // Skip to: 13726 -/* 5009 */ MCD_OPC_Decode, 235, 1, 135, 1, // Opcode: BINSLI_H -/* 5014 */ MCD_OPC_FilterValue, 1, 4, 34, // Skip to: 13726 -/* 5018 */ MCD_OPC_CheckPredicate, 8, 0, 34, // Skip to: 13726 -/* 5022 */ MCD_OPC_CheckField, 19, 1, 0, 250, 33, // Skip to: 13726 -/* 5028 */ MCD_OPC_Decode, 233, 1, 136, 1, // Opcode: BINSLI_B -/* 5033 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5046 -/* 5037 */ MCD_OPC_CheckPredicate, 8, 237, 33, // Skip to: 13726 -/* 5041 */ MCD_OPC_Decode, 242, 1, 133, 1, // Opcode: BINSRI_D -/* 5046 */ MCD_OPC_FilterValue, 15, 228, 33, // Skip to: 13726 -/* 5050 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5053 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5066 -/* 5057 */ MCD_OPC_CheckPredicate, 8, 217, 33, // Skip to: 13726 -/* 5061 */ MCD_OPC_Decode, 244, 1, 134, 1, // Opcode: BINSRI_W -/* 5066 */ MCD_OPC_FilterValue, 1, 208, 33, // Skip to: 13726 -/* 5070 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5073 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5086 -/* 5077 */ MCD_OPC_CheckPredicate, 8, 197, 33, // Skip to: 13726 -/* 5081 */ MCD_OPC_Decode, 243, 1, 135, 1, // Opcode: BINSRI_H -/* 5086 */ MCD_OPC_FilterValue, 1, 188, 33, // Skip to: 13726 -/* 5090 */ MCD_OPC_CheckPredicate, 8, 184, 33, // Skip to: 13726 -/* 5094 */ MCD_OPC_CheckField, 19, 1, 0, 178, 33, // Skip to: 13726 -/* 5100 */ MCD_OPC_Decode, 241, 1, 136, 1, // Opcode: BINSRI_B -/* 5105 */ MCD_OPC_FilterValue, 10, 31, 1, // Skip to: 5396 -/* 5109 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5112 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5125 -/* 5116 */ MCD_OPC_CheckPredicate, 8, 158, 33, // Skip to: 13726 -/* 5120 */ MCD_OPC_Decode, 135, 11, 130, 1, // Opcode: SAT_S_D -/* 5125 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 5183 -/* 5129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5144 -/* 5136 */ MCD_OPC_CheckPredicate, 8, 138, 33, // Skip to: 13726 -/* 5140 */ MCD_OPC_Decode, 137, 11, 124, // Opcode: SAT_S_W -/* 5144 */ MCD_OPC_FilterValue, 1, 130, 33, // Skip to: 13726 -/* 5148 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5164 -/* 5155 */ MCD_OPC_CheckPredicate, 8, 119, 33, // Skip to: 13726 -/* 5159 */ MCD_OPC_Decode, 136, 11, 131, 1, // Opcode: SAT_S_H -/* 5164 */ MCD_OPC_FilterValue, 1, 110, 33, // Skip to: 13726 -/* 5168 */ MCD_OPC_CheckPredicate, 8, 106, 33, // Skip to: 13726 -/* 5172 */ MCD_OPC_CheckField, 19, 1, 0, 100, 33, // Skip to: 13726 -/* 5178 */ MCD_OPC_Decode, 134, 11, 132, 1, // Opcode: SAT_S_B -/* 5183 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5196 -/* 5187 */ MCD_OPC_CheckPredicate, 8, 87, 33, // Skip to: 13726 -/* 5191 */ MCD_OPC_Decode, 139, 11, 130, 1, // Opcode: SAT_U_D -/* 5196 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 5254 -/* 5200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5215 -/* 5207 */ MCD_OPC_CheckPredicate, 8, 67, 33, // Skip to: 13726 -/* 5211 */ MCD_OPC_Decode, 141, 11, 124, // Opcode: SAT_U_W -/* 5215 */ MCD_OPC_FilterValue, 1, 59, 33, // Skip to: 13726 -/* 5219 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5222 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5235 -/* 5226 */ MCD_OPC_CheckPredicate, 8, 48, 33, // Skip to: 13726 -/* 5230 */ MCD_OPC_Decode, 140, 11, 131, 1, // Opcode: SAT_U_H -/* 5235 */ MCD_OPC_FilterValue, 1, 39, 33, // Skip to: 13726 -/* 5239 */ MCD_OPC_CheckPredicate, 8, 35, 33, // Skip to: 13726 -/* 5243 */ MCD_OPC_CheckField, 19, 1, 0, 29, 33, // Skip to: 13726 -/* 5249 */ MCD_OPC_Decode, 138, 11, 132, 1, // Opcode: SAT_U_B -/* 5254 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5267 -/* 5258 */ MCD_OPC_CheckPredicate, 8, 16, 33, // Skip to: 13726 -/* 5262 */ MCD_OPC_Decode, 145, 12, 130, 1, // Opcode: SRARI_D -/* 5267 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 5325 -/* 5271 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5274 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5286 -/* 5278 */ MCD_OPC_CheckPredicate, 8, 252, 32, // Skip to: 13726 -/* 5282 */ MCD_OPC_Decode, 147, 12, 124, // Opcode: SRARI_W -/* 5286 */ MCD_OPC_FilterValue, 1, 244, 32, // Skip to: 13726 -/* 5290 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5293 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5306 -/* 5297 */ MCD_OPC_CheckPredicate, 8, 233, 32, // Skip to: 13726 -/* 5301 */ MCD_OPC_Decode, 146, 12, 131, 1, // Opcode: SRARI_H -/* 5306 */ MCD_OPC_FilterValue, 1, 224, 32, // Skip to: 13726 -/* 5310 */ MCD_OPC_CheckPredicate, 8, 220, 32, // Skip to: 13726 -/* 5314 */ MCD_OPC_CheckField, 19, 1, 0, 214, 32, // Skip to: 13726 -/* 5320 */ MCD_OPC_Decode, 144, 12, 132, 1, // Opcode: SRARI_B -/* 5325 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5338 -/* 5329 */ MCD_OPC_CheckPredicate, 8, 201, 32, // Skip to: 13726 -/* 5333 */ MCD_OPC_Decode, 166, 12, 130, 1, // Opcode: SRLRI_D -/* 5338 */ MCD_OPC_FilterValue, 7, 192, 32, // Skip to: 13726 -/* 5342 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5345 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5357 -/* 5349 */ MCD_OPC_CheckPredicate, 8, 181, 32, // Skip to: 13726 -/* 5353 */ MCD_OPC_Decode, 168, 12, 124, // Opcode: SRLRI_W -/* 5357 */ MCD_OPC_FilterValue, 1, 173, 32, // Skip to: 13726 -/* 5361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5364 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5377 -/* 5368 */ MCD_OPC_CheckPredicate, 8, 162, 32, // Skip to: 13726 -/* 5372 */ MCD_OPC_Decode, 167, 12, 131, 1, // Opcode: SRLRI_H -/* 5377 */ MCD_OPC_FilterValue, 1, 153, 32, // Skip to: 13726 -/* 5381 */ MCD_OPC_CheckPredicate, 8, 149, 32, // Skip to: 13726 -/* 5385 */ MCD_OPC_CheckField, 19, 1, 0, 143, 32, // Skip to: 13726 -/* 5391 */ MCD_OPC_Decode, 165, 12, 132, 1, // Opcode: SRLRI_B -/* 5396 */ MCD_OPC_FilterValue, 13, 163, 1, // Skip to: 5819 -/* 5400 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 5403 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5416 -/* 5407 */ MCD_OPC_CheckPredicate, 8, 123, 32, // Skip to: 13726 -/* 5411 */ MCD_OPC_Decode, 235, 11, 137, 1, // Opcode: SLL_B -/* 5416 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5429 -/* 5420 */ MCD_OPC_CheckPredicate, 8, 110, 32, // Skip to: 13726 -/* 5424 */ MCD_OPC_Decode, 237, 11, 138, 1, // Opcode: SLL_H -/* 5429 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5442 -/* 5433 */ MCD_OPC_CheckPredicate, 8, 97, 32, // Skip to: 13726 -/* 5437 */ MCD_OPC_Decode, 239, 11, 139, 1, // Opcode: SLL_W -/* 5442 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5455 -/* 5446 */ MCD_OPC_CheckPredicate, 8, 84, 32, // Skip to: 13726 -/* 5450 */ MCD_OPC_Decode, 236, 11, 140, 1, // Opcode: SLL_D -/* 5455 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5468 -/* 5459 */ MCD_OPC_CheckPredicate, 8, 71, 32, // Skip to: 13726 -/* 5463 */ MCD_OPC_Decode, 154, 12, 137, 1, // Opcode: SRA_B -/* 5468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5481 -/* 5472 */ MCD_OPC_CheckPredicate, 8, 58, 32, // Skip to: 13726 -/* 5476 */ MCD_OPC_Decode, 156, 12, 138, 1, // Opcode: SRA_H -/* 5481 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5494 -/* 5485 */ MCD_OPC_CheckPredicate, 8, 45, 32, // Skip to: 13726 -/* 5489 */ MCD_OPC_Decode, 158, 12, 139, 1, // Opcode: SRA_W -/* 5494 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5507 -/* 5498 */ MCD_OPC_CheckPredicate, 8, 32, 32, // Skip to: 13726 -/* 5502 */ MCD_OPC_Decode, 155, 12, 140, 1, // Opcode: SRA_D -/* 5507 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5520 -/* 5511 */ MCD_OPC_CheckPredicate, 8, 19, 32, // Skip to: 13726 -/* 5515 */ MCD_OPC_Decode, 175, 12, 137, 1, // Opcode: SRL_B -/* 5520 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5533 -/* 5524 */ MCD_OPC_CheckPredicate, 8, 6, 32, // Skip to: 13726 -/* 5528 */ MCD_OPC_Decode, 177, 12, 138, 1, // Opcode: SRL_H -/* 5533 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5546 -/* 5537 */ MCD_OPC_CheckPredicate, 8, 249, 31, // Skip to: 13726 -/* 5541 */ MCD_OPC_Decode, 179, 12, 139, 1, // Opcode: SRL_W -/* 5546 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5559 -/* 5550 */ MCD_OPC_CheckPredicate, 8, 236, 31, // Skip to: 13726 -/* 5554 */ MCD_OPC_Decode, 176, 12, 140, 1, // Opcode: SRL_D -/* 5559 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5572 -/* 5563 */ MCD_OPC_CheckPredicate, 8, 223, 31, // Skip to: 13726 -/* 5567 */ MCD_OPC_Decode, 202, 1, 137, 1, // Opcode: BCLR_B -/* 5572 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5585 -/* 5576 */ MCD_OPC_CheckPredicate, 8, 210, 31, // Skip to: 13726 -/* 5580 */ MCD_OPC_Decode, 204, 1, 138, 1, // Opcode: BCLR_H -/* 5585 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5598 -/* 5589 */ MCD_OPC_CheckPredicate, 8, 197, 31, // Skip to: 13726 -/* 5593 */ MCD_OPC_Decode, 205, 1, 139, 1, // Opcode: BCLR_W -/* 5598 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5611 -/* 5602 */ MCD_OPC_CheckPredicate, 8, 184, 31, // Skip to: 13726 -/* 5606 */ MCD_OPC_Decode, 203, 1, 140, 1, // Opcode: BCLR_D -/* 5611 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 5624 -/* 5615 */ MCD_OPC_CheckPredicate, 8, 171, 31, // Skip to: 13726 -/* 5619 */ MCD_OPC_Decode, 185, 2, 137, 1, // Opcode: BSET_B -/* 5624 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 5637 -/* 5628 */ MCD_OPC_CheckPredicate, 8, 158, 31, // Skip to: 13726 -/* 5632 */ MCD_OPC_Decode, 187, 2, 138, 1, // Opcode: BSET_H -/* 5637 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 5650 -/* 5641 */ MCD_OPC_CheckPredicate, 8, 145, 31, // Skip to: 13726 -/* 5645 */ MCD_OPC_Decode, 188, 2, 139, 1, // Opcode: BSET_W -/* 5650 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 5663 -/* 5654 */ MCD_OPC_CheckPredicate, 8, 132, 31, // Skip to: 13726 -/* 5658 */ MCD_OPC_Decode, 186, 2, 140, 1, // Opcode: BSET_D -/* 5663 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 5676 -/* 5667 */ MCD_OPC_CheckPredicate, 8, 119, 31, // Skip to: 13726 -/* 5671 */ MCD_OPC_Decode, 152, 2, 137, 1, // Opcode: BNEG_B -/* 5676 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 5689 -/* 5680 */ MCD_OPC_CheckPredicate, 8, 106, 31, // Skip to: 13726 -/* 5684 */ MCD_OPC_Decode, 154, 2, 138, 1, // Opcode: BNEG_H -/* 5689 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 5702 -/* 5693 */ MCD_OPC_CheckPredicate, 8, 93, 31, // Skip to: 13726 -/* 5697 */ MCD_OPC_Decode, 155, 2, 139, 1, // Opcode: BNEG_W -/* 5702 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 5715 -/* 5706 */ MCD_OPC_CheckPredicate, 8, 80, 31, // Skip to: 13726 -/* 5710 */ MCD_OPC_Decode, 153, 2, 140, 1, // Opcode: BNEG_D -/* 5715 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 5728 -/* 5719 */ MCD_OPC_CheckPredicate, 8, 67, 31, // Skip to: 13726 -/* 5723 */ MCD_OPC_Decode, 237, 1, 141, 1, // Opcode: BINSL_B -/* 5728 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 5741 -/* 5732 */ MCD_OPC_CheckPredicate, 8, 54, 31, // Skip to: 13726 -/* 5736 */ MCD_OPC_Decode, 239, 1, 142, 1, // Opcode: BINSL_H -/* 5741 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 5754 -/* 5745 */ MCD_OPC_CheckPredicate, 8, 41, 31, // Skip to: 13726 -/* 5749 */ MCD_OPC_Decode, 240, 1, 143, 1, // Opcode: BINSL_W -/* 5754 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 5767 -/* 5758 */ MCD_OPC_CheckPredicate, 8, 28, 31, // Skip to: 13726 -/* 5762 */ MCD_OPC_Decode, 238, 1, 144, 1, // Opcode: BINSL_D -/* 5767 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 5780 -/* 5771 */ MCD_OPC_CheckPredicate, 8, 15, 31, // Skip to: 13726 -/* 5775 */ MCD_OPC_Decode, 245, 1, 141, 1, // Opcode: BINSR_B -/* 5780 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 5793 -/* 5784 */ MCD_OPC_CheckPredicate, 8, 2, 31, // Skip to: 13726 -/* 5788 */ MCD_OPC_Decode, 247, 1, 142, 1, // Opcode: BINSR_H -/* 5793 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 5806 -/* 5797 */ MCD_OPC_CheckPredicate, 8, 245, 30, // Skip to: 13726 -/* 5801 */ MCD_OPC_Decode, 248, 1, 143, 1, // Opcode: BINSR_W -/* 5806 */ MCD_OPC_FilterValue, 31, 236, 30, // Skip to: 13726 -/* 5810 */ MCD_OPC_CheckPredicate, 8, 232, 30, // Skip to: 13726 -/* 5814 */ MCD_OPC_Decode, 246, 1, 144, 1, // Opcode: BINSR_D -/* 5819 */ MCD_OPC_FilterValue, 14, 159, 1, // Skip to: 6238 -/* 5823 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 5826 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5838 -/* 5830 */ MCD_OPC_CheckPredicate, 8, 212, 30, // Skip to: 13726 -/* 5834 */ MCD_OPC_Decode, 63, 137, 1, // Opcode: ADDV_B -/* 5838 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5850 -/* 5842 */ MCD_OPC_CheckPredicate, 8, 200, 30, // Skip to: 13726 -/* 5846 */ MCD_OPC_Decode, 65, 138, 1, // Opcode: ADDV_H -/* 5850 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5862 -/* 5854 */ MCD_OPC_CheckPredicate, 8, 188, 30, // Skip to: 13726 -/* 5858 */ MCD_OPC_Decode, 66, 139, 1, // Opcode: ADDV_W -/* 5862 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 5874 -/* 5866 */ MCD_OPC_CheckPredicate, 8, 176, 30, // Skip to: 13726 -/* 5870 */ MCD_OPC_Decode, 64, 140, 1, // Opcode: ADDV_D -/* 5874 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5887 -/* 5878 */ MCD_OPC_CheckPredicate, 8, 164, 30, // Skip to: 13726 -/* 5882 */ MCD_OPC_Decode, 225, 12, 137, 1, // Opcode: SUBV_B -/* 5887 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5900 -/* 5891 */ MCD_OPC_CheckPredicate, 8, 151, 30, // Skip to: 13726 -/* 5895 */ MCD_OPC_Decode, 227, 12, 138, 1, // Opcode: SUBV_H -/* 5900 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5913 -/* 5904 */ MCD_OPC_CheckPredicate, 8, 138, 30, // Skip to: 13726 -/* 5908 */ MCD_OPC_Decode, 228, 12, 139, 1, // Opcode: SUBV_W -/* 5913 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5926 -/* 5917 */ MCD_OPC_CheckPredicate, 8, 125, 30, // Skip to: 13726 -/* 5921 */ MCD_OPC_Decode, 226, 12, 140, 1, // Opcode: SUBV_D -/* 5926 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5939 -/* 5930 */ MCD_OPC_CheckPredicate, 8, 112, 30, // Skip to: 13726 -/* 5934 */ MCD_OPC_Decode, 171, 8, 137, 1, // Opcode: MAX_S_B -/* 5939 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5952 -/* 5943 */ MCD_OPC_CheckPredicate, 8, 99, 30, // Skip to: 13726 -/* 5947 */ MCD_OPC_Decode, 173, 8, 138, 1, // Opcode: MAX_S_H -/* 5952 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5965 -/* 5956 */ MCD_OPC_CheckPredicate, 8, 86, 30, // Skip to: 13726 -/* 5960 */ MCD_OPC_Decode, 174, 8, 139, 1, // Opcode: MAX_S_W -/* 5965 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5978 -/* 5969 */ MCD_OPC_CheckPredicate, 8, 73, 30, // Skip to: 13726 -/* 5973 */ MCD_OPC_Decode, 172, 8, 140, 1, // Opcode: MAX_S_D -/* 5978 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5991 -/* 5982 */ MCD_OPC_CheckPredicate, 8, 60, 30, // Skip to: 13726 -/* 5986 */ MCD_OPC_Decode, 175, 8, 137, 1, // Opcode: MAX_U_B -/* 5991 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6004 -/* 5995 */ MCD_OPC_CheckPredicate, 8, 47, 30, // Skip to: 13726 -/* 5999 */ MCD_OPC_Decode, 177, 8, 138, 1, // Opcode: MAX_U_H -/* 6004 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6017 -/* 6008 */ MCD_OPC_CheckPredicate, 8, 34, 30, // Skip to: 13726 -/* 6012 */ MCD_OPC_Decode, 178, 8, 139, 1, // Opcode: MAX_U_W -/* 6017 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6030 -/* 6021 */ MCD_OPC_CheckPredicate, 8, 21, 30, // Skip to: 13726 -/* 6025 */ MCD_OPC_Decode, 176, 8, 140, 1, // Opcode: MAX_U_D -/* 6030 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6043 -/* 6034 */ MCD_OPC_CheckPredicate, 8, 8, 30, // Skip to: 13726 -/* 6038 */ MCD_OPC_Decode, 212, 8, 137, 1, // Opcode: MIN_S_B -/* 6043 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6056 -/* 6047 */ MCD_OPC_CheckPredicate, 8, 251, 29, // Skip to: 13726 -/* 6051 */ MCD_OPC_Decode, 214, 8, 138, 1, // Opcode: MIN_S_H -/* 6056 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6069 -/* 6060 */ MCD_OPC_CheckPredicate, 8, 238, 29, // Skip to: 13726 -/* 6064 */ MCD_OPC_Decode, 215, 8, 139, 1, // Opcode: MIN_S_W -/* 6069 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6082 -/* 6073 */ MCD_OPC_CheckPredicate, 8, 225, 29, // Skip to: 13726 -/* 6077 */ MCD_OPC_Decode, 213, 8, 140, 1, // Opcode: MIN_S_D -/* 6082 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6095 -/* 6086 */ MCD_OPC_CheckPredicate, 8, 212, 29, // Skip to: 13726 -/* 6090 */ MCD_OPC_Decode, 216, 8, 137, 1, // Opcode: MIN_U_B -/* 6095 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6108 -/* 6099 */ MCD_OPC_CheckPredicate, 8, 199, 29, // Skip to: 13726 -/* 6103 */ MCD_OPC_Decode, 218, 8, 138, 1, // Opcode: MIN_U_H -/* 6108 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6121 -/* 6112 */ MCD_OPC_CheckPredicate, 8, 186, 29, // Skip to: 13726 -/* 6116 */ MCD_OPC_Decode, 219, 8, 139, 1, // Opcode: MIN_U_W -/* 6121 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6134 -/* 6125 */ MCD_OPC_CheckPredicate, 8, 173, 29, // Skip to: 13726 -/* 6129 */ MCD_OPC_Decode, 217, 8, 140, 1, // Opcode: MIN_U_D -/* 6134 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6147 -/* 6138 */ MCD_OPC_CheckPredicate, 8, 160, 29, // Skip to: 13726 -/* 6142 */ MCD_OPC_Decode, 165, 8, 137, 1, // Opcode: MAX_A_B -/* 6147 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6160 -/* 6151 */ MCD_OPC_CheckPredicate, 8, 147, 29, // Skip to: 13726 -/* 6155 */ MCD_OPC_Decode, 167, 8, 138, 1, // Opcode: MAX_A_H -/* 6160 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6173 -/* 6164 */ MCD_OPC_CheckPredicate, 8, 134, 29, // Skip to: 13726 -/* 6168 */ MCD_OPC_Decode, 168, 8, 139, 1, // Opcode: MAX_A_W -/* 6173 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6186 -/* 6177 */ MCD_OPC_CheckPredicate, 8, 121, 29, // Skip to: 13726 -/* 6181 */ MCD_OPC_Decode, 166, 8, 140, 1, // Opcode: MAX_A_D -/* 6186 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6199 -/* 6190 */ MCD_OPC_CheckPredicate, 8, 108, 29, // Skip to: 13726 -/* 6194 */ MCD_OPC_Decode, 206, 8, 137, 1, // Opcode: MIN_A_B -/* 6199 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6212 -/* 6203 */ MCD_OPC_CheckPredicate, 8, 95, 29, // Skip to: 13726 -/* 6207 */ MCD_OPC_Decode, 208, 8, 138, 1, // Opcode: MIN_A_H -/* 6212 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6225 -/* 6216 */ MCD_OPC_CheckPredicate, 8, 82, 29, // Skip to: 13726 -/* 6220 */ MCD_OPC_Decode, 209, 8, 139, 1, // Opcode: MIN_A_W -/* 6225 */ MCD_OPC_FilterValue, 31, 73, 29, // Skip to: 13726 -/* 6229 */ MCD_OPC_CheckPredicate, 8, 69, 29, // Skip to: 13726 -/* 6233 */ MCD_OPC_Decode, 207, 8, 140, 1, // Opcode: MIN_A_D -/* 6238 */ MCD_OPC_FilterValue, 15, 7, 1, // Skip to: 6505 -/* 6242 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6245 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6258 -/* 6249 */ MCD_OPC_CheckPredicate, 8, 49, 29, // Skip to: 13726 -/* 6253 */ MCD_OPC_Decode, 234, 2, 137, 1, // Opcode: CEQ_B -/* 6258 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6271 -/* 6262 */ MCD_OPC_CheckPredicate, 8, 36, 29, // Skip to: 13726 -/* 6266 */ MCD_OPC_Decode, 236, 2, 138, 1, // Opcode: CEQ_H -/* 6271 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6284 -/* 6275 */ MCD_OPC_CheckPredicate, 8, 23, 29, // Skip to: 13726 -/* 6279 */ MCD_OPC_Decode, 237, 2, 139, 1, // Opcode: CEQ_W -/* 6284 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6297 -/* 6288 */ MCD_OPC_CheckPredicate, 8, 10, 29, // Skip to: 13726 -/* 6292 */ MCD_OPC_Decode, 235, 2, 140, 1, // Opcode: CEQ_D -/* 6297 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 6310 -/* 6301 */ MCD_OPC_CheckPredicate, 8, 253, 28, // Skip to: 13726 -/* 6305 */ MCD_OPC_Decode, 144, 3, 137, 1, // Opcode: CLT_S_B -/* 6310 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 6323 -/* 6314 */ MCD_OPC_CheckPredicate, 8, 240, 28, // Skip to: 13726 -/* 6318 */ MCD_OPC_Decode, 146, 3, 138, 1, // Opcode: CLT_S_H -/* 6323 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 6336 -/* 6327 */ MCD_OPC_CheckPredicate, 8, 227, 28, // Skip to: 13726 -/* 6331 */ MCD_OPC_Decode, 147, 3, 139, 1, // Opcode: CLT_S_W -/* 6336 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 6349 -/* 6340 */ MCD_OPC_CheckPredicate, 8, 214, 28, // Skip to: 13726 -/* 6344 */ MCD_OPC_Decode, 145, 3, 140, 1, // Opcode: CLT_S_D -/* 6349 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6362 -/* 6353 */ MCD_OPC_CheckPredicate, 8, 201, 28, // Skip to: 13726 -/* 6357 */ MCD_OPC_Decode, 148, 3, 137, 1, // Opcode: CLT_U_B -/* 6362 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6375 -/* 6366 */ MCD_OPC_CheckPredicate, 8, 188, 28, // Skip to: 13726 -/* 6370 */ MCD_OPC_Decode, 150, 3, 138, 1, // Opcode: CLT_U_H -/* 6375 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6388 -/* 6379 */ MCD_OPC_CheckPredicate, 8, 175, 28, // Skip to: 13726 -/* 6383 */ MCD_OPC_Decode, 151, 3, 139, 1, // Opcode: CLT_U_W -/* 6388 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6401 -/* 6392 */ MCD_OPC_CheckPredicate, 8, 162, 28, // Skip to: 13726 -/* 6396 */ MCD_OPC_Decode, 149, 3, 140, 1, // Opcode: CLT_U_D -/* 6401 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6414 -/* 6405 */ MCD_OPC_CheckPredicate, 8, 149, 28, // Skip to: 13726 -/* 6409 */ MCD_OPC_Decode, 253, 2, 137, 1, // Opcode: CLE_S_B -/* 6414 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6427 -/* 6418 */ MCD_OPC_CheckPredicate, 8, 136, 28, // Skip to: 13726 -/* 6422 */ MCD_OPC_Decode, 255, 2, 138, 1, // Opcode: CLE_S_H -/* 6427 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6440 -/* 6431 */ MCD_OPC_CheckPredicate, 8, 123, 28, // Skip to: 13726 -/* 6435 */ MCD_OPC_Decode, 128, 3, 139, 1, // Opcode: CLE_S_W -/* 6440 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6453 -/* 6444 */ MCD_OPC_CheckPredicate, 8, 110, 28, // Skip to: 13726 -/* 6448 */ MCD_OPC_Decode, 254, 2, 140, 1, // Opcode: CLE_S_D -/* 6453 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6466 -/* 6457 */ MCD_OPC_CheckPredicate, 8, 97, 28, // Skip to: 13726 -/* 6461 */ MCD_OPC_Decode, 129, 3, 137, 1, // Opcode: CLE_U_B -/* 6466 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6479 -/* 6470 */ MCD_OPC_CheckPredicate, 8, 84, 28, // Skip to: 13726 -/* 6474 */ MCD_OPC_Decode, 131, 3, 138, 1, // Opcode: CLE_U_H -/* 6479 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6492 -/* 6483 */ MCD_OPC_CheckPredicate, 8, 71, 28, // Skip to: 13726 -/* 6487 */ MCD_OPC_Decode, 132, 3, 139, 1, // Opcode: CLE_U_W -/* 6492 */ MCD_OPC_FilterValue, 23, 62, 28, // Skip to: 13726 -/* 6496 */ MCD_OPC_CheckPredicate, 8, 58, 28, // Skip to: 13726 -/* 6500 */ MCD_OPC_Decode, 130, 3, 140, 1, // Opcode: CLE_U_D -/* 6505 */ MCD_OPC_FilterValue, 16, 147, 1, // Skip to: 6912 -/* 6509 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6512 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6524 -/* 6516 */ MCD_OPC_CheckPredicate, 8, 38, 28, // Skip to: 13726 -/* 6520 */ MCD_OPC_Decode, 68, 137, 1, // Opcode: ADD_A_B -/* 6524 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6536 -/* 6528 */ MCD_OPC_CheckPredicate, 8, 26, 28, // Skip to: 13726 -/* 6532 */ MCD_OPC_Decode, 70, 138, 1, // Opcode: ADD_A_H -/* 6536 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6548 -/* 6540 */ MCD_OPC_CheckPredicate, 8, 14, 28, // Skip to: 13726 -/* 6544 */ MCD_OPC_Decode, 71, 139, 1, // Opcode: ADD_A_W -/* 6548 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6560 -/* 6552 */ MCD_OPC_CheckPredicate, 8, 2, 28, // Skip to: 13726 -/* 6556 */ MCD_OPC_Decode, 69, 140, 1, // Opcode: ADD_A_D -/* 6560 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6572 -/* 6564 */ MCD_OPC_CheckPredicate, 8, 246, 27, // Skip to: 13726 -/* 6568 */ MCD_OPC_Decode, 40, 137, 1, // Opcode: ADDS_A_B -/* 6572 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6584 -/* 6576 */ MCD_OPC_CheckPredicate, 8, 234, 27, // Skip to: 13726 -/* 6580 */ MCD_OPC_Decode, 42, 138, 1, // Opcode: ADDS_A_H -/* 6584 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6596 -/* 6588 */ MCD_OPC_CheckPredicate, 8, 222, 27, // Skip to: 13726 -/* 6592 */ MCD_OPC_Decode, 43, 139, 1, // Opcode: ADDS_A_W -/* 6596 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6608 -/* 6600 */ MCD_OPC_CheckPredicate, 8, 210, 27, // Skip to: 13726 -/* 6604 */ MCD_OPC_Decode, 41, 140, 1, // Opcode: ADDS_A_D -/* 6608 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6620 -/* 6612 */ MCD_OPC_CheckPredicate, 8, 198, 27, // Skip to: 13726 -/* 6616 */ MCD_OPC_Decode, 44, 137, 1, // Opcode: ADDS_S_B -/* 6620 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6632 -/* 6624 */ MCD_OPC_CheckPredicate, 8, 186, 27, // Skip to: 13726 -/* 6628 */ MCD_OPC_Decode, 46, 138, 1, // Opcode: ADDS_S_H -/* 6632 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6644 -/* 6636 */ MCD_OPC_CheckPredicate, 8, 174, 27, // Skip to: 13726 -/* 6640 */ MCD_OPC_Decode, 47, 139, 1, // Opcode: ADDS_S_W -/* 6644 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6656 -/* 6648 */ MCD_OPC_CheckPredicate, 8, 162, 27, // Skip to: 13726 -/* 6652 */ MCD_OPC_Decode, 45, 140, 1, // Opcode: ADDS_S_D -/* 6656 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6668 -/* 6660 */ MCD_OPC_CheckPredicate, 8, 150, 27, // Skip to: 13726 -/* 6664 */ MCD_OPC_Decode, 48, 137, 1, // Opcode: ADDS_U_B -/* 6668 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6680 -/* 6672 */ MCD_OPC_CheckPredicate, 8, 138, 27, // Skip to: 13726 -/* 6676 */ MCD_OPC_Decode, 50, 138, 1, // Opcode: ADDS_U_H -/* 6680 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6692 -/* 6684 */ MCD_OPC_CheckPredicate, 8, 126, 27, // Skip to: 13726 -/* 6688 */ MCD_OPC_Decode, 51, 139, 1, // Opcode: ADDS_U_W -/* 6692 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6704 -/* 6696 */ MCD_OPC_CheckPredicate, 8, 114, 27, // Skip to: 13726 -/* 6700 */ MCD_OPC_Decode, 49, 140, 1, // Opcode: ADDS_U_D -/* 6704 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6717 -/* 6708 */ MCD_OPC_CheckPredicate, 8, 102, 27, // Skip to: 13726 -/* 6712 */ MCD_OPC_Decode, 147, 1, 137, 1, // Opcode: AVE_S_B -/* 6717 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6730 -/* 6721 */ MCD_OPC_CheckPredicate, 8, 89, 27, // Skip to: 13726 -/* 6725 */ MCD_OPC_Decode, 149, 1, 138, 1, // Opcode: AVE_S_H -/* 6730 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6743 -/* 6734 */ MCD_OPC_CheckPredicate, 8, 76, 27, // Skip to: 13726 -/* 6738 */ MCD_OPC_Decode, 150, 1, 139, 1, // Opcode: AVE_S_W -/* 6743 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6756 -/* 6747 */ MCD_OPC_CheckPredicate, 8, 63, 27, // Skip to: 13726 -/* 6751 */ MCD_OPC_Decode, 148, 1, 140, 1, // Opcode: AVE_S_D -/* 6756 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6769 -/* 6760 */ MCD_OPC_CheckPredicate, 8, 50, 27, // Skip to: 13726 -/* 6764 */ MCD_OPC_Decode, 151, 1, 137, 1, // Opcode: AVE_U_B -/* 6769 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6782 -/* 6773 */ MCD_OPC_CheckPredicate, 8, 37, 27, // Skip to: 13726 -/* 6777 */ MCD_OPC_Decode, 153, 1, 138, 1, // Opcode: AVE_U_H -/* 6782 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6795 -/* 6786 */ MCD_OPC_CheckPredicate, 8, 24, 27, // Skip to: 13726 -/* 6790 */ MCD_OPC_Decode, 154, 1, 139, 1, // Opcode: AVE_U_W -/* 6795 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6808 -/* 6799 */ MCD_OPC_CheckPredicate, 8, 11, 27, // Skip to: 13726 -/* 6803 */ MCD_OPC_Decode, 152, 1, 140, 1, // Opcode: AVE_U_D -/* 6808 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6821 -/* 6812 */ MCD_OPC_CheckPredicate, 8, 254, 26, // Skip to: 13726 -/* 6816 */ MCD_OPC_Decode, 139, 1, 137, 1, // Opcode: AVER_S_B -/* 6821 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6834 -/* 6825 */ MCD_OPC_CheckPredicate, 8, 241, 26, // Skip to: 13726 -/* 6829 */ MCD_OPC_Decode, 141, 1, 138, 1, // Opcode: AVER_S_H -/* 6834 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6847 -/* 6838 */ MCD_OPC_CheckPredicate, 8, 228, 26, // Skip to: 13726 -/* 6842 */ MCD_OPC_Decode, 142, 1, 139, 1, // Opcode: AVER_S_W -/* 6847 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6860 -/* 6851 */ MCD_OPC_CheckPredicate, 8, 215, 26, // Skip to: 13726 -/* 6855 */ MCD_OPC_Decode, 140, 1, 140, 1, // Opcode: AVER_S_D -/* 6860 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6873 -/* 6864 */ MCD_OPC_CheckPredicate, 8, 202, 26, // Skip to: 13726 -/* 6868 */ MCD_OPC_Decode, 143, 1, 137, 1, // Opcode: AVER_U_B -/* 6873 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6886 -/* 6877 */ MCD_OPC_CheckPredicate, 8, 189, 26, // Skip to: 13726 -/* 6881 */ MCD_OPC_Decode, 145, 1, 138, 1, // Opcode: AVER_U_H -/* 6886 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6899 -/* 6890 */ MCD_OPC_CheckPredicate, 8, 176, 26, // Skip to: 13726 -/* 6894 */ MCD_OPC_Decode, 146, 1, 139, 1, // Opcode: AVER_U_W -/* 6899 */ MCD_OPC_FilterValue, 31, 167, 26, // Skip to: 13726 -/* 6903 */ MCD_OPC_CheckPredicate, 8, 163, 26, // Skip to: 13726 -/* 6907 */ MCD_OPC_Decode, 144, 1, 140, 1, // Opcode: AVER_U_D -/* 6912 */ MCD_OPC_FilterValue, 17, 51, 1, // Skip to: 7223 -/* 6916 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6919 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6932 -/* 6923 */ MCD_OPC_CheckPredicate, 8, 143, 26, // Skip to: 13726 -/* 6927 */ MCD_OPC_Decode, 206, 12, 137, 1, // Opcode: SUBS_S_B -/* 6932 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6945 -/* 6936 */ MCD_OPC_CheckPredicate, 8, 130, 26, // Skip to: 13726 -/* 6940 */ MCD_OPC_Decode, 208, 12, 138, 1, // Opcode: SUBS_S_H -/* 6945 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6958 -/* 6949 */ MCD_OPC_CheckPredicate, 8, 117, 26, // Skip to: 13726 -/* 6953 */ MCD_OPC_Decode, 209, 12, 139, 1, // Opcode: SUBS_S_W -/* 6958 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6971 -/* 6962 */ MCD_OPC_CheckPredicate, 8, 104, 26, // Skip to: 13726 -/* 6966 */ MCD_OPC_Decode, 207, 12, 140, 1, // Opcode: SUBS_S_D -/* 6971 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 6984 -/* 6975 */ MCD_OPC_CheckPredicate, 8, 91, 26, // Skip to: 13726 -/* 6979 */ MCD_OPC_Decode, 210, 12, 137, 1, // Opcode: SUBS_U_B -/* 6984 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 6997 -/* 6988 */ MCD_OPC_CheckPredicate, 8, 78, 26, // Skip to: 13726 -/* 6992 */ MCD_OPC_Decode, 212, 12, 138, 1, // Opcode: SUBS_U_H -/* 6997 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7010 -/* 7001 */ MCD_OPC_CheckPredicate, 8, 65, 26, // Skip to: 13726 -/* 7005 */ MCD_OPC_Decode, 213, 12, 139, 1, // Opcode: SUBS_U_W -/* 7010 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7023 -/* 7014 */ MCD_OPC_CheckPredicate, 8, 52, 26, // Skip to: 13726 -/* 7018 */ MCD_OPC_Decode, 211, 12, 140, 1, // Opcode: SUBS_U_D -/* 7023 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7036 -/* 7027 */ MCD_OPC_CheckPredicate, 8, 39, 26, // Skip to: 13726 -/* 7031 */ MCD_OPC_Decode, 198, 12, 137, 1, // Opcode: SUBSUS_U_B -/* 7036 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7049 -/* 7040 */ MCD_OPC_CheckPredicate, 8, 26, 26, // Skip to: 13726 -/* 7044 */ MCD_OPC_Decode, 200, 12, 138, 1, // Opcode: SUBSUS_U_H -/* 7049 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7062 -/* 7053 */ MCD_OPC_CheckPredicate, 8, 13, 26, // Skip to: 13726 -/* 7057 */ MCD_OPC_Decode, 201, 12, 139, 1, // Opcode: SUBSUS_U_W -/* 7062 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7075 -/* 7066 */ MCD_OPC_CheckPredicate, 8, 0, 26, // Skip to: 13726 -/* 7070 */ MCD_OPC_Decode, 199, 12, 140, 1, // Opcode: SUBSUS_U_D -/* 7075 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7088 -/* 7079 */ MCD_OPC_CheckPredicate, 8, 243, 25, // Skip to: 13726 -/* 7083 */ MCD_OPC_Decode, 202, 12, 137, 1, // Opcode: SUBSUU_S_B -/* 7088 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7101 -/* 7092 */ MCD_OPC_CheckPredicate, 8, 230, 25, // Skip to: 13726 -/* 7096 */ MCD_OPC_Decode, 204, 12, 138, 1, // Opcode: SUBSUU_S_H -/* 7101 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7114 -/* 7105 */ MCD_OPC_CheckPredicate, 8, 217, 25, // Skip to: 13726 -/* 7109 */ MCD_OPC_Decode, 205, 12, 139, 1, // Opcode: SUBSUU_S_W -/* 7114 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7127 -/* 7118 */ MCD_OPC_CheckPredicate, 8, 204, 25, // Skip to: 13726 -/* 7122 */ MCD_OPC_Decode, 203, 12, 140, 1, // Opcode: SUBSUU_S_D -/* 7127 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 7139 -/* 7131 */ MCD_OPC_CheckPredicate, 8, 191, 25, // Skip to: 13726 -/* 7135 */ MCD_OPC_Decode, 97, 137, 1, // Opcode: ASUB_S_B -/* 7139 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7151 -/* 7143 */ MCD_OPC_CheckPredicate, 8, 179, 25, // Skip to: 13726 -/* 7147 */ MCD_OPC_Decode, 99, 138, 1, // Opcode: ASUB_S_H -/* 7151 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7163 -/* 7155 */ MCD_OPC_CheckPredicate, 8, 167, 25, // Skip to: 13726 -/* 7159 */ MCD_OPC_Decode, 100, 139, 1, // Opcode: ASUB_S_W -/* 7163 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7175 -/* 7167 */ MCD_OPC_CheckPredicate, 8, 155, 25, // Skip to: 13726 -/* 7171 */ MCD_OPC_Decode, 98, 140, 1, // Opcode: ASUB_S_D -/* 7175 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 7187 -/* 7179 */ MCD_OPC_CheckPredicate, 8, 143, 25, // Skip to: 13726 -/* 7183 */ MCD_OPC_Decode, 101, 137, 1, // Opcode: ASUB_U_B -/* 7187 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7199 -/* 7191 */ MCD_OPC_CheckPredicate, 8, 131, 25, // Skip to: 13726 -/* 7195 */ MCD_OPC_Decode, 103, 138, 1, // Opcode: ASUB_U_H -/* 7199 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7211 -/* 7203 */ MCD_OPC_CheckPredicate, 8, 119, 25, // Skip to: 13726 -/* 7207 */ MCD_OPC_Decode, 104, 139, 1, // Opcode: ASUB_U_W -/* 7211 */ MCD_OPC_FilterValue, 23, 111, 25, // Skip to: 13726 -/* 7215 */ MCD_OPC_CheckPredicate, 8, 107, 25, // Skip to: 13726 -/* 7219 */ MCD_OPC_Decode, 102, 140, 1, // Opcode: ASUB_U_D -/* 7223 */ MCD_OPC_FilterValue, 18, 111, 1, // Skip to: 7594 -/* 7227 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7230 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7243 -/* 7234 */ MCD_OPC_CheckPredicate, 8, 88, 25, // Skip to: 13726 -/* 7238 */ MCD_OPC_Decode, 213, 9, 137, 1, // Opcode: MULV_B -/* 7243 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7256 -/* 7247 */ MCD_OPC_CheckPredicate, 8, 75, 25, // Skip to: 13726 -/* 7251 */ MCD_OPC_Decode, 215, 9, 138, 1, // Opcode: MULV_H -/* 7256 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7269 -/* 7260 */ MCD_OPC_CheckPredicate, 8, 62, 25, // Skip to: 13726 -/* 7264 */ MCD_OPC_Decode, 216, 9, 139, 1, // Opcode: MULV_W -/* 7269 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7282 -/* 7273 */ MCD_OPC_CheckPredicate, 8, 49, 25, // Skip to: 13726 -/* 7277 */ MCD_OPC_Decode, 214, 9, 140, 1, // Opcode: MULV_D -/* 7282 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7295 -/* 7286 */ MCD_OPC_CheckPredicate, 8, 36, 25, // Skip to: 13726 -/* 7290 */ MCD_OPC_Decode, 138, 8, 141, 1, // Opcode: MADDV_B -/* 7295 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7308 -/* 7299 */ MCD_OPC_CheckPredicate, 8, 23, 25, // Skip to: 13726 -/* 7303 */ MCD_OPC_Decode, 140, 8, 142, 1, // Opcode: MADDV_H -/* 7308 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7321 -/* 7312 */ MCD_OPC_CheckPredicate, 8, 10, 25, // Skip to: 13726 -/* 7316 */ MCD_OPC_Decode, 141, 8, 143, 1, // Opcode: MADDV_W -/* 7321 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7334 -/* 7325 */ MCD_OPC_CheckPredicate, 8, 253, 24, // Skip to: 13726 -/* 7329 */ MCD_OPC_Decode, 139, 8, 144, 1, // Opcode: MADDV_D -/* 7334 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7347 -/* 7338 */ MCD_OPC_CheckPredicate, 8, 240, 24, // Skip to: 13726 -/* 7342 */ MCD_OPC_Decode, 156, 9, 141, 1, // Opcode: MSUBV_B -/* 7347 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7360 -/* 7351 */ MCD_OPC_CheckPredicate, 8, 227, 24, // Skip to: 13726 -/* 7355 */ MCD_OPC_Decode, 158, 9, 142, 1, // Opcode: MSUBV_H -/* 7360 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7373 -/* 7364 */ MCD_OPC_CheckPredicate, 8, 214, 24, // Skip to: 13726 -/* 7368 */ MCD_OPC_Decode, 159, 9, 143, 1, // Opcode: MSUBV_W -/* 7373 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7386 -/* 7377 */ MCD_OPC_CheckPredicate, 8, 201, 24, // Skip to: 13726 -/* 7381 */ MCD_OPC_Decode, 157, 9, 144, 1, // Opcode: MSUBV_D -/* 7386 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 7399 -/* 7390 */ MCD_OPC_CheckPredicate, 8, 188, 24, // Skip to: 13726 -/* 7394 */ MCD_OPC_Decode, 185, 4, 137, 1, // Opcode: DIV_S_B -/* 7399 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7412 -/* 7403 */ MCD_OPC_CheckPredicate, 8, 175, 24, // Skip to: 13726 -/* 7407 */ MCD_OPC_Decode, 187, 4, 138, 1, // Opcode: DIV_S_H -/* 7412 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7425 -/* 7416 */ MCD_OPC_CheckPredicate, 8, 162, 24, // Skip to: 13726 -/* 7420 */ MCD_OPC_Decode, 188, 4, 139, 1, // Opcode: DIV_S_W -/* 7425 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7438 -/* 7429 */ MCD_OPC_CheckPredicate, 8, 149, 24, // Skip to: 13726 -/* 7433 */ MCD_OPC_Decode, 186, 4, 140, 1, // Opcode: DIV_S_D -/* 7438 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 7451 -/* 7442 */ MCD_OPC_CheckPredicate, 8, 136, 24, // Skip to: 13726 -/* 7446 */ MCD_OPC_Decode, 189, 4, 137, 1, // Opcode: DIV_U_B -/* 7451 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7464 -/* 7455 */ MCD_OPC_CheckPredicate, 8, 123, 24, // Skip to: 13726 -/* 7459 */ MCD_OPC_Decode, 191, 4, 138, 1, // Opcode: DIV_U_H -/* 7464 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7477 -/* 7468 */ MCD_OPC_CheckPredicate, 8, 110, 24, // Skip to: 13726 -/* 7472 */ MCD_OPC_Decode, 192, 4, 139, 1, // Opcode: DIV_U_W -/* 7477 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 7490 -/* 7481 */ MCD_OPC_CheckPredicate, 8, 97, 24, // Skip to: 13726 -/* 7485 */ MCD_OPC_Decode, 190, 4, 140, 1, // Opcode: DIV_U_D -/* 7490 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 7503 -/* 7494 */ MCD_OPC_CheckPredicate, 8, 84, 24, // Skip to: 13726 -/* 7498 */ MCD_OPC_Decode, 225, 8, 137, 1, // Opcode: MOD_S_B -/* 7503 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 7516 -/* 7507 */ MCD_OPC_CheckPredicate, 8, 71, 24, // Skip to: 13726 -/* 7511 */ MCD_OPC_Decode, 227, 8, 138, 1, // Opcode: MOD_S_H -/* 7516 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 7529 -/* 7520 */ MCD_OPC_CheckPredicate, 8, 58, 24, // Skip to: 13726 -/* 7524 */ MCD_OPC_Decode, 228, 8, 139, 1, // Opcode: MOD_S_W -/* 7529 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 7542 -/* 7533 */ MCD_OPC_CheckPredicate, 8, 45, 24, // Skip to: 13726 -/* 7537 */ MCD_OPC_Decode, 226, 8, 140, 1, // Opcode: MOD_S_D -/* 7542 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 7555 -/* 7546 */ MCD_OPC_CheckPredicate, 8, 32, 24, // Skip to: 13726 -/* 7550 */ MCD_OPC_Decode, 229, 8, 137, 1, // Opcode: MOD_U_B -/* 7555 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 7568 -/* 7559 */ MCD_OPC_CheckPredicate, 8, 19, 24, // Skip to: 13726 -/* 7563 */ MCD_OPC_Decode, 231, 8, 138, 1, // Opcode: MOD_U_H -/* 7568 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 7581 -/* 7572 */ MCD_OPC_CheckPredicate, 8, 6, 24, // Skip to: 13726 -/* 7576 */ MCD_OPC_Decode, 232, 8, 139, 1, // Opcode: MOD_U_W -/* 7581 */ MCD_OPC_FilterValue, 31, 253, 23, // Skip to: 13726 -/* 7585 */ MCD_OPC_CheckPredicate, 8, 249, 23, // Skip to: 13726 -/* 7589 */ MCD_OPC_Decode, 230, 8, 140, 1, // Opcode: MOD_U_D -/* 7594 */ MCD_OPC_FilterValue, 19, 237, 0, // Skip to: 7835 -/* 7598 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7601 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7614 -/* 7605 */ MCD_OPC_CheckPredicate, 8, 229, 23, // Skip to: 13726 -/* 7609 */ MCD_OPC_Decode, 212, 4, 145, 1, // Opcode: DOTP_S_H -/* 7614 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7627 -/* 7618 */ MCD_OPC_CheckPredicate, 8, 216, 23, // Skip to: 13726 -/* 7622 */ MCD_OPC_Decode, 213, 4, 146, 1, // Opcode: DOTP_S_W -/* 7627 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7640 -/* 7631 */ MCD_OPC_CheckPredicate, 8, 203, 23, // Skip to: 13726 -/* 7635 */ MCD_OPC_Decode, 211, 4, 147, 1, // Opcode: DOTP_S_D -/* 7640 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7653 -/* 7644 */ MCD_OPC_CheckPredicate, 8, 190, 23, // Skip to: 13726 -/* 7648 */ MCD_OPC_Decode, 215, 4, 145, 1, // Opcode: DOTP_U_H -/* 7653 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7666 -/* 7657 */ MCD_OPC_CheckPredicate, 8, 177, 23, // Skip to: 13726 -/* 7661 */ MCD_OPC_Decode, 216, 4, 146, 1, // Opcode: DOTP_U_W -/* 7666 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7679 -/* 7670 */ MCD_OPC_CheckPredicate, 8, 164, 23, // Skip to: 13726 -/* 7674 */ MCD_OPC_Decode, 214, 4, 147, 1, // Opcode: DOTP_U_D -/* 7679 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7692 -/* 7683 */ MCD_OPC_CheckPredicate, 8, 151, 23, // Skip to: 13726 -/* 7687 */ MCD_OPC_Decode, 218, 4, 148, 1, // Opcode: DPADD_S_H -/* 7692 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7705 -/* 7696 */ MCD_OPC_CheckPredicate, 8, 138, 23, // Skip to: 13726 -/* 7700 */ MCD_OPC_Decode, 219, 4, 149, 1, // Opcode: DPADD_S_W -/* 7705 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7718 -/* 7709 */ MCD_OPC_CheckPredicate, 8, 125, 23, // Skip to: 13726 -/* 7713 */ MCD_OPC_Decode, 217, 4, 150, 1, // Opcode: DPADD_S_D -/* 7718 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7731 -/* 7722 */ MCD_OPC_CheckPredicate, 8, 112, 23, // Skip to: 13726 -/* 7726 */ MCD_OPC_Decode, 221, 4, 148, 1, // Opcode: DPADD_U_H -/* 7731 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7744 -/* 7735 */ MCD_OPC_CheckPredicate, 8, 99, 23, // Skip to: 13726 -/* 7739 */ MCD_OPC_Decode, 222, 4, 149, 1, // Opcode: DPADD_U_W -/* 7744 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7757 -/* 7748 */ MCD_OPC_CheckPredicate, 8, 86, 23, // Skip to: 13726 -/* 7752 */ MCD_OPC_Decode, 220, 4, 150, 1, // Opcode: DPADD_U_D -/* 7757 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7770 -/* 7761 */ MCD_OPC_CheckPredicate, 8, 73, 23, // Skip to: 13726 -/* 7765 */ MCD_OPC_Decode, 237, 4, 148, 1, // Opcode: DPSUB_S_H -/* 7770 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7783 -/* 7774 */ MCD_OPC_CheckPredicate, 8, 60, 23, // Skip to: 13726 -/* 7778 */ MCD_OPC_Decode, 238, 4, 149, 1, // Opcode: DPSUB_S_W -/* 7783 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7796 -/* 7787 */ MCD_OPC_CheckPredicate, 8, 47, 23, // Skip to: 13726 -/* 7791 */ MCD_OPC_Decode, 236, 4, 150, 1, // Opcode: DPSUB_S_D -/* 7796 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7809 -/* 7800 */ MCD_OPC_CheckPredicate, 8, 34, 23, // Skip to: 13726 -/* 7804 */ MCD_OPC_Decode, 240, 4, 148, 1, // Opcode: DPSUB_U_H -/* 7809 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7822 -/* 7813 */ MCD_OPC_CheckPredicate, 8, 21, 23, // Skip to: 13726 -/* 7817 */ MCD_OPC_Decode, 241, 4, 149, 1, // Opcode: DPSUB_U_W -/* 7822 */ MCD_OPC_FilterValue, 23, 12, 23, // Skip to: 13726 -/* 7826 */ MCD_OPC_CheckPredicate, 8, 8, 23, // Skip to: 13726 -/* 7830 */ MCD_OPC_Decode, 239, 4, 150, 1, // Opcode: DPSUB_U_D -/* 7835 */ MCD_OPC_FilterValue, 20, 163, 1, // Skip to: 8258 -/* 7839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7842 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7855 -/* 7846 */ MCD_OPC_CheckPredicate, 8, 244, 22, // Skip to: 13726 -/* 7850 */ MCD_OPC_Decode, 221, 11, 151, 1, // Opcode: SLD_B -/* 7855 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7868 -/* 7859 */ MCD_OPC_CheckPredicate, 8, 231, 22, // Skip to: 13726 -/* 7863 */ MCD_OPC_Decode, 223, 11, 152, 1, // Opcode: SLD_H -/* 7868 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7881 -/* 7872 */ MCD_OPC_CheckPredicate, 8, 218, 22, // Skip to: 13726 -/* 7876 */ MCD_OPC_Decode, 224, 11, 153, 1, // Opcode: SLD_W -/* 7881 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7894 -/* 7885 */ MCD_OPC_CheckPredicate, 8, 205, 22, // Skip to: 13726 -/* 7889 */ MCD_OPC_Decode, 222, 11, 154, 1, // Opcode: SLD_D -/* 7894 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7907 -/* 7898 */ MCD_OPC_CheckPredicate, 8, 192, 22, // Skip to: 13726 -/* 7902 */ MCD_OPC_Decode, 135, 12, 155, 1, // Opcode: SPLAT_B -/* 7907 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7920 -/* 7911 */ MCD_OPC_CheckPredicate, 8, 179, 22, // Skip to: 13726 -/* 7915 */ MCD_OPC_Decode, 137, 12, 156, 1, // Opcode: SPLAT_H -/* 7920 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7933 -/* 7924 */ MCD_OPC_CheckPredicate, 8, 166, 22, // Skip to: 13726 -/* 7928 */ MCD_OPC_Decode, 138, 12, 157, 1, // Opcode: SPLAT_W -/* 7933 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7946 -/* 7937 */ MCD_OPC_CheckPredicate, 8, 153, 22, // Skip to: 13726 -/* 7941 */ MCD_OPC_Decode, 136, 12, 158, 1, // Opcode: SPLAT_D -/* 7946 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7959 -/* 7950 */ MCD_OPC_CheckPredicate, 8, 140, 22, // Skip to: 13726 -/* 7954 */ MCD_OPC_Decode, 149, 10, 137, 1, // Opcode: PCKEV_B -/* 7959 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7972 -/* 7963 */ MCD_OPC_CheckPredicate, 8, 127, 22, // Skip to: 13726 -/* 7967 */ MCD_OPC_Decode, 151, 10, 138, 1, // Opcode: PCKEV_H -/* 7972 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7985 -/* 7976 */ MCD_OPC_CheckPredicate, 8, 114, 22, // Skip to: 13726 -/* 7980 */ MCD_OPC_Decode, 152, 10, 139, 1, // Opcode: PCKEV_W -/* 7985 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7998 -/* 7989 */ MCD_OPC_CheckPredicate, 8, 101, 22, // Skip to: 13726 -/* 7993 */ MCD_OPC_Decode, 150, 10, 140, 1, // Opcode: PCKEV_D -/* 7998 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8011 -/* 8002 */ MCD_OPC_CheckPredicate, 8, 88, 22, // Skip to: 13726 -/* 8006 */ MCD_OPC_Decode, 153, 10, 137, 1, // Opcode: PCKOD_B -/* 8011 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 8024 -/* 8015 */ MCD_OPC_CheckPredicate, 8, 75, 22, // Skip to: 13726 -/* 8019 */ MCD_OPC_Decode, 155, 10, 138, 1, // Opcode: PCKOD_H -/* 8024 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 8037 -/* 8028 */ MCD_OPC_CheckPredicate, 8, 62, 22, // Skip to: 13726 -/* 8032 */ MCD_OPC_Decode, 156, 10, 139, 1, // Opcode: PCKOD_W -/* 8037 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 8050 -/* 8041 */ MCD_OPC_CheckPredicate, 8, 49, 22, // Skip to: 13726 -/* 8045 */ MCD_OPC_Decode, 154, 10, 140, 1, // Opcode: PCKOD_D -/* 8050 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8063 -/* 8054 */ MCD_OPC_CheckPredicate, 8, 36, 22, // Skip to: 13726 -/* 8058 */ MCD_OPC_Decode, 216, 6, 137, 1, // Opcode: ILVL_B -/* 8063 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8076 -/* 8067 */ MCD_OPC_CheckPredicate, 8, 23, 22, // Skip to: 13726 -/* 8071 */ MCD_OPC_Decode, 218, 6, 138, 1, // Opcode: ILVL_H -/* 8076 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8089 -/* 8080 */ MCD_OPC_CheckPredicate, 8, 10, 22, // Skip to: 13726 -/* 8084 */ MCD_OPC_Decode, 219, 6, 139, 1, // Opcode: ILVL_W -/* 8089 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8102 -/* 8093 */ MCD_OPC_CheckPredicate, 8, 253, 21, // Skip to: 13726 -/* 8097 */ MCD_OPC_Decode, 217, 6, 140, 1, // Opcode: ILVL_D -/* 8102 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 8115 -/* 8106 */ MCD_OPC_CheckPredicate, 8, 240, 21, // Skip to: 13726 -/* 8110 */ MCD_OPC_Decode, 224, 6, 137, 1, // Opcode: ILVR_B -/* 8115 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8128 -/* 8119 */ MCD_OPC_CheckPredicate, 8, 227, 21, // Skip to: 13726 -/* 8123 */ MCD_OPC_Decode, 226, 6, 138, 1, // Opcode: ILVR_H -/* 8128 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8141 -/* 8132 */ MCD_OPC_CheckPredicate, 8, 214, 21, // Skip to: 13726 -/* 8136 */ MCD_OPC_Decode, 227, 6, 139, 1, // Opcode: ILVR_W -/* 8141 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8154 -/* 8145 */ MCD_OPC_CheckPredicate, 8, 201, 21, // Skip to: 13726 -/* 8149 */ MCD_OPC_Decode, 225, 6, 140, 1, // Opcode: ILVR_D -/* 8154 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 8167 -/* 8158 */ MCD_OPC_CheckPredicate, 8, 188, 21, // Skip to: 13726 -/* 8162 */ MCD_OPC_Decode, 212, 6, 137, 1, // Opcode: ILVEV_B -/* 8167 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8180 -/* 8171 */ MCD_OPC_CheckPredicate, 8, 175, 21, // Skip to: 13726 -/* 8175 */ MCD_OPC_Decode, 214, 6, 138, 1, // Opcode: ILVEV_H -/* 8180 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8193 -/* 8184 */ MCD_OPC_CheckPredicate, 8, 162, 21, // Skip to: 13726 -/* 8188 */ MCD_OPC_Decode, 215, 6, 139, 1, // Opcode: ILVEV_W -/* 8193 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8206 -/* 8197 */ MCD_OPC_CheckPredicate, 8, 149, 21, // Skip to: 13726 -/* 8201 */ MCD_OPC_Decode, 213, 6, 140, 1, // Opcode: ILVEV_D -/* 8206 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 8219 -/* 8210 */ MCD_OPC_CheckPredicate, 8, 136, 21, // Skip to: 13726 -/* 8214 */ MCD_OPC_Decode, 220, 6, 137, 1, // Opcode: ILVOD_B -/* 8219 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8232 -/* 8223 */ MCD_OPC_CheckPredicate, 8, 123, 21, // Skip to: 13726 -/* 8227 */ MCD_OPC_Decode, 222, 6, 138, 1, // Opcode: ILVOD_H -/* 8232 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8245 -/* 8236 */ MCD_OPC_CheckPredicate, 8, 110, 21, // Skip to: 13726 -/* 8240 */ MCD_OPC_Decode, 223, 6, 139, 1, // Opcode: ILVOD_W -/* 8245 */ MCD_OPC_FilterValue, 31, 101, 21, // Skip to: 13726 -/* 8249 */ MCD_OPC_CheckPredicate, 8, 97, 21, // Skip to: 13726 -/* 8253 */ MCD_OPC_Decode, 221, 6, 140, 1, // Opcode: ILVOD_D -/* 8258 */ MCD_OPC_FilterValue, 21, 59, 1, // Skip to: 8577 -/* 8262 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 8265 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8278 -/* 8269 */ MCD_OPC_CheckPredicate, 8, 77, 21, // Skip to: 13726 -/* 8273 */ MCD_OPC_Decode, 227, 13, 141, 1, // Opcode: VSHF_B -/* 8278 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8291 -/* 8282 */ MCD_OPC_CheckPredicate, 8, 64, 21, // Skip to: 13726 -/* 8286 */ MCD_OPC_Decode, 229, 13, 142, 1, // Opcode: VSHF_H -/* 8291 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8304 -/* 8295 */ MCD_OPC_CheckPredicate, 8, 51, 21, // Skip to: 13726 -/* 8299 */ MCD_OPC_Decode, 230, 13, 143, 1, // Opcode: VSHF_W -/* 8304 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8317 -/* 8308 */ MCD_OPC_CheckPredicate, 8, 38, 21, // Skip to: 13726 -/* 8312 */ MCD_OPC_Decode, 228, 13, 144, 1, // Opcode: VSHF_D -/* 8317 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8330 -/* 8321 */ MCD_OPC_CheckPredicate, 8, 25, 21, // Skip to: 13726 -/* 8325 */ MCD_OPC_Decode, 148, 12, 137, 1, // Opcode: SRAR_B -/* 8330 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 8343 -/* 8334 */ MCD_OPC_CheckPredicate, 8, 12, 21, // Skip to: 13726 -/* 8338 */ MCD_OPC_Decode, 150, 12, 138, 1, // Opcode: SRAR_H -/* 8343 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 8356 -/* 8347 */ MCD_OPC_CheckPredicate, 8, 255, 20, // Skip to: 13726 -/* 8351 */ MCD_OPC_Decode, 151, 12, 139, 1, // Opcode: SRAR_W -/* 8356 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 8369 -/* 8360 */ MCD_OPC_CheckPredicate, 8, 242, 20, // Skip to: 13726 -/* 8364 */ MCD_OPC_Decode, 149, 12, 140, 1, // Opcode: SRAR_D -/* 8369 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8382 -/* 8373 */ MCD_OPC_CheckPredicate, 8, 229, 20, // Skip to: 13726 -/* 8377 */ MCD_OPC_Decode, 169, 12, 137, 1, // Opcode: SRLR_B -/* 8382 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 8395 -/* 8386 */ MCD_OPC_CheckPredicate, 8, 216, 20, // Skip to: 13726 -/* 8390 */ MCD_OPC_Decode, 171, 12, 138, 1, // Opcode: SRLR_H -/* 8395 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 8408 -/* 8399 */ MCD_OPC_CheckPredicate, 8, 203, 20, // Skip to: 13726 -/* 8403 */ MCD_OPC_Decode, 172, 12, 139, 1, // Opcode: SRLR_W -/* 8408 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 8421 -/* 8412 */ MCD_OPC_CheckPredicate, 8, 190, 20, // Skip to: 13726 -/* 8416 */ MCD_OPC_Decode, 170, 12, 140, 1, // Opcode: SRLR_D -/* 8421 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8434 -/* 8425 */ MCD_OPC_CheckPredicate, 8, 177, 20, // Skip to: 13726 -/* 8429 */ MCD_OPC_Decode, 201, 6, 145, 1, // Opcode: HADD_S_H -/* 8434 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8447 -/* 8438 */ MCD_OPC_CheckPredicate, 8, 164, 20, // Skip to: 13726 -/* 8442 */ MCD_OPC_Decode, 202, 6, 146, 1, // Opcode: HADD_S_W -/* 8447 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8460 -/* 8451 */ MCD_OPC_CheckPredicate, 8, 151, 20, // Skip to: 13726 -/* 8455 */ MCD_OPC_Decode, 200, 6, 147, 1, // Opcode: HADD_S_D -/* 8460 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8473 -/* 8464 */ MCD_OPC_CheckPredicate, 8, 138, 20, // Skip to: 13726 -/* 8468 */ MCD_OPC_Decode, 204, 6, 145, 1, // Opcode: HADD_U_H -/* 8473 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8486 -/* 8477 */ MCD_OPC_CheckPredicate, 8, 125, 20, // Skip to: 13726 -/* 8481 */ MCD_OPC_Decode, 205, 6, 146, 1, // Opcode: HADD_U_W -/* 8486 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8499 -/* 8490 */ MCD_OPC_CheckPredicate, 8, 112, 20, // Skip to: 13726 -/* 8494 */ MCD_OPC_Decode, 203, 6, 147, 1, // Opcode: HADD_U_D -/* 8499 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8512 -/* 8503 */ MCD_OPC_CheckPredicate, 8, 99, 20, // Skip to: 13726 -/* 8507 */ MCD_OPC_Decode, 207, 6, 145, 1, // Opcode: HSUB_S_H -/* 8512 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8525 -/* 8516 */ MCD_OPC_CheckPredicate, 8, 86, 20, // Skip to: 13726 -/* 8520 */ MCD_OPC_Decode, 208, 6, 146, 1, // Opcode: HSUB_S_W -/* 8525 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8538 -/* 8529 */ MCD_OPC_CheckPredicate, 8, 73, 20, // Skip to: 13726 -/* 8533 */ MCD_OPC_Decode, 206, 6, 147, 1, // Opcode: HSUB_S_D -/* 8538 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8551 -/* 8542 */ MCD_OPC_CheckPredicate, 8, 60, 20, // Skip to: 13726 -/* 8546 */ MCD_OPC_Decode, 210, 6, 145, 1, // Opcode: HSUB_U_H -/* 8551 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8564 -/* 8555 */ MCD_OPC_CheckPredicate, 8, 47, 20, // Skip to: 13726 -/* 8559 */ MCD_OPC_Decode, 211, 6, 146, 1, // Opcode: HSUB_U_W -/* 8564 */ MCD_OPC_FilterValue, 31, 38, 20, // Skip to: 13726 -/* 8568 */ MCD_OPC_CheckPredicate, 8, 34, 20, // Skip to: 13726 -/* 8572 */ MCD_OPC_Decode, 209, 6, 147, 1, // Opcode: HSUB_U_D -/* 8577 */ MCD_OPC_FilterValue, 25, 230, 1, // Skip to: 9067 -/* 8581 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ... -/* 8584 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8597 -/* 8588 */ MCD_OPC_CheckPredicate, 8, 14, 20, // Skip to: 13726 -/* 8592 */ MCD_OPC_Decode, 217, 11, 159, 1, // Opcode: SLDI_B -/* 8597 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8616 -/* 8601 */ MCD_OPC_CheckPredicate, 8, 1, 20, // Skip to: 13726 -/* 8605 */ MCD_OPC_CheckField, 19, 1, 0, 251, 19, // Skip to: 13726 -/* 8611 */ MCD_OPC_Decode, 219, 11, 160, 1, // Opcode: SLDI_H -/* 8616 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 8674 -/* 8620 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8623 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8636 -/* 8627 */ MCD_OPC_CheckPredicate, 8, 231, 19, // Skip to: 13726 -/* 8631 */ MCD_OPC_Decode, 220, 11, 161, 1, // Opcode: SLDI_W -/* 8636 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8655 -/* 8640 */ MCD_OPC_CheckPredicate, 8, 218, 19, // Skip to: 13726 -/* 8644 */ MCD_OPC_CheckField, 17, 1, 0, 212, 19, // Skip to: 13726 -/* 8650 */ MCD_OPC_Decode, 218, 11, 162, 1, // Opcode: SLDI_D -/* 8655 */ MCD_OPC_FilterValue, 3, 203, 19, // Skip to: 13726 -/* 8659 */ MCD_OPC_CheckPredicate, 8, 199, 19, // Skip to: 13726 -/* 8663 */ MCD_OPC_CheckField, 16, 2, 2, 193, 19, // Skip to: 13726 -/* 8669 */ MCD_OPC_Decode, 212, 3, 163, 1, // Opcode: CTCMSA -/* 8674 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8687 -/* 8678 */ MCD_OPC_CheckPredicate, 8, 180, 19, // Skip to: 13726 -/* 8682 */ MCD_OPC_Decode, 131, 12, 164, 1, // Opcode: SPLATI_B -/* 8687 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 8706 -/* 8691 */ MCD_OPC_CheckPredicate, 8, 167, 19, // Skip to: 13726 -/* 8695 */ MCD_OPC_CheckField, 19, 1, 0, 161, 19, // Skip to: 13726 -/* 8701 */ MCD_OPC_Decode, 133, 12, 165, 1, // Opcode: SPLATI_H -/* 8706 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 8764 -/* 8710 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8713 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8726 -/* 8717 */ MCD_OPC_CheckPredicate, 8, 141, 19, // Skip to: 13726 -/* 8721 */ MCD_OPC_Decode, 134, 12, 166, 1, // Opcode: SPLATI_W -/* 8726 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8745 -/* 8730 */ MCD_OPC_CheckPredicate, 8, 128, 19, // Skip to: 13726 -/* 8734 */ MCD_OPC_CheckField, 17, 1, 0, 122, 19, // Skip to: 13726 -/* 8740 */ MCD_OPC_Decode, 132, 12, 167, 1, // Opcode: SPLATI_D -/* 8745 */ MCD_OPC_FilterValue, 3, 113, 19, // Skip to: 13726 -/* 8749 */ MCD_OPC_CheckPredicate, 8, 109, 19, // Skip to: 13726 -/* 8753 */ MCD_OPC_CheckField, 16, 2, 2, 103, 19, // Skip to: 13726 -/* 8759 */ MCD_OPC_Decode, 240, 2, 168, 1, // Opcode: CFCMSA -/* 8764 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8777 -/* 8768 */ MCD_OPC_CheckPredicate, 8, 90, 19, // Skip to: 13726 -/* 8772 */ MCD_OPC_Decode, 202, 3, 169, 1, // Opcode: COPY_S_B -/* 8777 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 8796 -/* 8781 */ MCD_OPC_CheckPredicate, 8, 77, 19, // Skip to: 13726 -/* 8785 */ MCD_OPC_CheckField, 19, 1, 0, 71, 19, // Skip to: 13726 -/* 8791 */ MCD_OPC_Decode, 204, 3, 170, 1, // Opcode: COPY_S_H -/* 8796 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 8854 -/* 8800 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8803 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8816 -/* 8807 */ MCD_OPC_CheckPredicate, 8, 51, 19, // Skip to: 13726 -/* 8811 */ MCD_OPC_Decode, 205, 3, 171, 1, // Opcode: COPY_S_W -/* 8816 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8835 -/* 8820 */ MCD_OPC_CheckPredicate, 14, 38, 19, // Skip to: 13726 -/* 8824 */ MCD_OPC_CheckField, 17, 1, 0, 32, 19, // Skip to: 13726 -/* 8830 */ MCD_OPC_Decode, 203, 3, 172, 1, // Opcode: COPY_S_D -/* 8835 */ MCD_OPC_FilterValue, 3, 23, 19, // Skip to: 13726 -/* 8839 */ MCD_OPC_CheckPredicate, 8, 19, 19, // Skip to: 13726 -/* 8843 */ MCD_OPC_CheckField, 16, 2, 2, 13, 19, // Skip to: 13726 -/* 8849 */ MCD_OPC_Decode, 235, 8, 173, 1, // Opcode: MOVE_V -/* 8854 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8867 -/* 8858 */ MCD_OPC_CheckPredicate, 8, 0, 19, // Skip to: 13726 -/* 8862 */ MCD_OPC_Decode, 206, 3, 169, 1, // Opcode: COPY_U_B -/* 8867 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 8886 -/* 8871 */ MCD_OPC_CheckPredicate, 8, 243, 18, // Skip to: 13726 -/* 8875 */ MCD_OPC_CheckField, 19, 1, 0, 237, 18, // Skip to: 13726 -/* 8881 */ MCD_OPC_Decode, 208, 3, 170, 1, // Opcode: COPY_U_H -/* 8886 */ MCD_OPC_FilterValue, 15, 35, 0, // Skip to: 8925 -/* 8890 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8893 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8906 -/* 8897 */ MCD_OPC_CheckPredicate, 8, 217, 18, // Skip to: 13726 -/* 8901 */ MCD_OPC_Decode, 209, 3, 171, 1, // Opcode: COPY_U_W -/* 8906 */ MCD_OPC_FilterValue, 2, 208, 18, // Skip to: 13726 -/* 8910 */ MCD_OPC_CheckPredicate, 14, 204, 18, // Skip to: 13726 -/* 8914 */ MCD_OPC_CheckField, 17, 1, 0, 198, 18, // Skip to: 13726 -/* 8920 */ MCD_OPC_Decode, 207, 3, 172, 1, // Opcode: COPY_U_D -/* 8925 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8938 -/* 8929 */ MCD_OPC_CheckPredicate, 8, 185, 18, // Skip to: 13726 -/* 8933 */ MCD_OPC_Decode, 229, 6, 174, 1, // Opcode: INSERT_B -/* 8938 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 8957 -/* 8942 */ MCD_OPC_CheckPredicate, 8, 172, 18, // Skip to: 13726 -/* 8946 */ MCD_OPC_CheckField, 19, 1, 0, 166, 18, // Skip to: 13726 -/* 8952 */ MCD_OPC_Decode, 237, 6, 175, 1, // Opcode: INSERT_H -/* 8957 */ MCD_OPC_FilterValue, 19, 35, 0, // Skip to: 8996 -/* 8961 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8964 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8977 -/* 8968 */ MCD_OPC_CheckPredicate, 8, 146, 18, // Skip to: 13726 -/* 8972 */ MCD_OPC_Decode, 239, 6, 176, 1, // Opcode: INSERT_W -/* 8977 */ MCD_OPC_FilterValue, 2, 137, 18, // Skip to: 13726 -/* 8981 */ MCD_OPC_CheckPredicate, 14, 133, 18, // Skip to: 13726 -/* 8985 */ MCD_OPC_CheckField, 17, 1, 0, 127, 18, // Skip to: 13726 -/* 8991 */ MCD_OPC_Decode, 231, 6, 177, 1, // Opcode: INSERT_D -/* 8996 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9009 -/* 9000 */ MCD_OPC_CheckPredicate, 8, 114, 18, // Skip to: 13726 -/* 9004 */ MCD_OPC_Decode, 242, 6, 178, 1, // Opcode: INSVE_B -/* 9009 */ MCD_OPC_FilterValue, 22, 15, 0, // Skip to: 9028 -/* 9013 */ MCD_OPC_CheckPredicate, 8, 101, 18, // Skip to: 13726 -/* 9017 */ MCD_OPC_CheckField, 19, 1, 0, 95, 18, // Skip to: 13726 -/* 9023 */ MCD_OPC_Decode, 244, 6, 178, 1, // Opcode: INSVE_H -/* 9028 */ MCD_OPC_FilterValue, 23, 86, 18, // Skip to: 13726 -/* 9032 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 9035 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9048 -/* 9039 */ MCD_OPC_CheckPredicate, 8, 75, 18, // Skip to: 13726 -/* 9043 */ MCD_OPC_Decode, 245, 6, 178, 1, // Opcode: INSVE_W -/* 9048 */ MCD_OPC_FilterValue, 2, 66, 18, // Skip to: 13726 -/* 9052 */ MCD_OPC_CheckPredicate, 8, 62, 18, // Skip to: 13726 -/* 9056 */ MCD_OPC_CheckField, 17, 1, 0, 56, 18, // Skip to: 13726 -/* 9062 */ MCD_OPC_Decode, 243, 6, 178, 1, // Opcode: INSVE_D -/* 9067 */ MCD_OPC_FilterValue, 26, 163, 1, // Skip to: 9490 -/* 9071 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9074 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9087 -/* 9078 */ MCD_OPC_CheckPredicate, 8, 36, 18, // Skip to: 13726 -/* 9082 */ MCD_OPC_Decode, 178, 5, 139, 1, // Opcode: FCAF_W -/* 9087 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9100 -/* 9091 */ MCD_OPC_CheckPredicate, 8, 23, 18, // Skip to: 13726 -/* 9095 */ MCD_OPC_Decode, 177, 5, 140, 1, // Opcode: FCAF_D -/* 9100 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9113 -/* 9104 */ MCD_OPC_CheckPredicate, 8, 10, 18, // Skip to: 13726 -/* 9108 */ MCD_OPC_Decode, 205, 5, 139, 1, // Opcode: FCUN_W -/* 9113 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9126 -/* 9117 */ MCD_OPC_CheckPredicate, 8, 253, 17, // Skip to: 13726 -/* 9121 */ MCD_OPC_Decode, 204, 5, 140, 1, // Opcode: FCUN_D -/* 9126 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9139 -/* 9130 */ MCD_OPC_CheckPredicate, 8, 240, 17, // Skip to: 13726 -/* 9134 */ MCD_OPC_Decode, 180, 5, 139, 1, // Opcode: FCEQ_W -/* 9139 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9152 -/* 9143 */ MCD_OPC_CheckPredicate, 8, 227, 17, // Skip to: 13726 -/* 9147 */ MCD_OPC_Decode, 179, 5, 140, 1, // Opcode: FCEQ_D -/* 9152 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9165 -/* 9156 */ MCD_OPC_CheckPredicate, 8, 214, 17, // Skip to: 13726 -/* 9160 */ MCD_OPC_Decode, 197, 5, 139, 1, // Opcode: FCUEQ_W -/* 9165 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9178 -/* 9169 */ MCD_OPC_CheckPredicate, 8, 201, 17, // Skip to: 13726 -/* 9173 */ MCD_OPC_Decode, 196, 5, 140, 1, // Opcode: FCUEQ_D -/* 9178 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9191 -/* 9182 */ MCD_OPC_CheckPredicate, 8, 188, 17, // Skip to: 13726 -/* 9186 */ MCD_OPC_Decode, 186, 5, 139, 1, // Opcode: FCLT_W -/* 9191 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9204 -/* 9195 */ MCD_OPC_CheckPredicate, 8, 175, 17, // Skip to: 13726 -/* 9199 */ MCD_OPC_Decode, 185, 5, 140, 1, // Opcode: FCLT_D -/* 9204 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9217 -/* 9208 */ MCD_OPC_CheckPredicate, 8, 162, 17, // Skip to: 13726 -/* 9212 */ MCD_OPC_Decode, 201, 5, 139, 1, // Opcode: FCULT_W -/* 9217 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9230 -/* 9221 */ MCD_OPC_CheckPredicate, 8, 149, 17, // Skip to: 13726 -/* 9225 */ MCD_OPC_Decode, 200, 5, 140, 1, // Opcode: FCULT_D -/* 9230 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9243 -/* 9234 */ MCD_OPC_CheckPredicate, 8, 136, 17, // Skip to: 13726 -/* 9238 */ MCD_OPC_Decode, 184, 5, 139, 1, // Opcode: FCLE_W -/* 9243 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9256 -/* 9247 */ MCD_OPC_CheckPredicate, 8, 123, 17, // Skip to: 13726 -/* 9251 */ MCD_OPC_Decode, 183, 5, 140, 1, // Opcode: FCLE_D -/* 9256 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9269 -/* 9260 */ MCD_OPC_CheckPredicate, 8, 110, 17, // Skip to: 13726 -/* 9264 */ MCD_OPC_Decode, 199, 5, 139, 1, // Opcode: FCULE_W -/* 9269 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9282 -/* 9273 */ MCD_OPC_CheckPredicate, 8, 97, 17, // Skip to: 13726 -/* 9277 */ MCD_OPC_Decode, 198, 5, 140, 1, // Opcode: FCULE_D -/* 9282 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9295 -/* 9286 */ MCD_OPC_CheckPredicate, 8, 84, 17, // Skip to: 13726 -/* 9290 */ MCD_OPC_Decode, 154, 6, 139, 1, // Opcode: FSAF_W -/* 9295 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9308 -/* 9299 */ MCD_OPC_CheckPredicate, 8, 71, 17, // Skip to: 13726 -/* 9303 */ MCD_OPC_Decode, 153, 6, 140, 1, // Opcode: FSAF_D -/* 9308 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 9321 -/* 9312 */ MCD_OPC_CheckPredicate, 8, 58, 17, // Skip to: 13726 -/* 9316 */ MCD_OPC_Decode, 188, 6, 139, 1, // Opcode: FSUN_W -/* 9321 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 9334 -/* 9325 */ MCD_OPC_CheckPredicate, 8, 45, 17, // Skip to: 13726 -/* 9329 */ MCD_OPC_Decode, 187, 6, 140, 1, // Opcode: FSUN_D -/* 9334 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9347 -/* 9338 */ MCD_OPC_CheckPredicate, 8, 32, 17, // Skip to: 13726 -/* 9342 */ MCD_OPC_Decode, 156, 6, 139, 1, // Opcode: FSEQ_W -/* 9347 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9360 -/* 9351 */ MCD_OPC_CheckPredicate, 8, 19, 17, // Skip to: 13726 -/* 9355 */ MCD_OPC_Decode, 155, 6, 140, 1, // Opcode: FSEQ_D -/* 9360 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 9373 -/* 9364 */ MCD_OPC_CheckPredicate, 8, 6, 17, // Skip to: 13726 -/* 9368 */ MCD_OPC_Decode, 180, 6, 139, 1, // Opcode: FSUEQ_W -/* 9373 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 9386 -/* 9377 */ MCD_OPC_CheckPredicate, 8, 249, 16, // Skip to: 13726 -/* 9381 */ MCD_OPC_Decode, 179, 6, 140, 1, // Opcode: FSUEQ_D -/* 9386 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9399 -/* 9390 */ MCD_OPC_CheckPredicate, 8, 236, 16, // Skip to: 13726 -/* 9394 */ MCD_OPC_Decode, 160, 6, 139, 1, // Opcode: FSLT_W -/* 9399 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9412 -/* 9403 */ MCD_OPC_CheckPredicate, 8, 223, 16, // Skip to: 13726 -/* 9407 */ MCD_OPC_Decode, 159, 6, 140, 1, // Opcode: FSLT_D -/* 9412 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9425 -/* 9416 */ MCD_OPC_CheckPredicate, 8, 210, 16, // Skip to: 13726 -/* 9420 */ MCD_OPC_Decode, 184, 6, 139, 1, // Opcode: FSULT_W -/* 9425 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9438 -/* 9429 */ MCD_OPC_CheckPredicate, 8, 197, 16, // Skip to: 13726 -/* 9433 */ MCD_OPC_Decode, 183, 6, 140, 1, // Opcode: FSULT_D -/* 9438 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9451 -/* 9442 */ MCD_OPC_CheckPredicate, 8, 184, 16, // Skip to: 13726 -/* 9446 */ MCD_OPC_Decode, 158, 6, 139, 1, // Opcode: FSLE_W -/* 9451 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9464 -/* 9455 */ MCD_OPC_CheckPredicate, 8, 171, 16, // Skip to: 13726 -/* 9459 */ MCD_OPC_Decode, 157, 6, 140, 1, // Opcode: FSLE_D -/* 9464 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9477 -/* 9468 */ MCD_OPC_CheckPredicate, 8, 158, 16, // Skip to: 13726 -/* 9472 */ MCD_OPC_Decode, 182, 6, 139, 1, // Opcode: FSULE_W -/* 9477 */ MCD_OPC_FilterValue, 31, 149, 16, // Skip to: 13726 -/* 9481 */ MCD_OPC_CheckPredicate, 8, 145, 16, // Skip to: 13726 -/* 9485 */ MCD_OPC_Decode, 181, 6, 140, 1, // Opcode: FSULE_D -/* 9490 */ MCD_OPC_FilterValue, 27, 85, 1, // Skip to: 9835 -/* 9494 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9497 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9510 -/* 9501 */ MCD_OPC_CheckPredicate, 8, 125, 16, // Skip to: 13726 -/* 9505 */ MCD_OPC_Decode, 176, 5, 139, 1, // Opcode: FADD_W -/* 9510 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9523 -/* 9514 */ MCD_OPC_CheckPredicate, 8, 112, 16, // Skip to: 13726 -/* 9518 */ MCD_OPC_Decode, 170, 5, 140, 1, // Opcode: FADD_D -/* 9523 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9536 -/* 9527 */ MCD_OPC_CheckPredicate, 8, 99, 16, // Skip to: 13726 -/* 9531 */ MCD_OPC_Decode, 178, 6, 139, 1, // Opcode: FSUB_W -/* 9536 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9549 -/* 9540 */ MCD_OPC_CheckPredicate, 8, 86, 16, // Skip to: 13726 -/* 9544 */ MCD_OPC_Decode, 172, 6, 140, 1, // Opcode: FSUB_D -/* 9549 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9562 -/* 9553 */ MCD_OPC_CheckPredicate, 8, 73, 16, // Skip to: 13726 -/* 9557 */ MCD_OPC_Decode, 141, 6, 139, 1, // Opcode: FMUL_W -/* 9562 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9575 -/* 9566 */ MCD_OPC_CheckPredicate, 8, 60, 16, // Skip to: 13726 -/* 9570 */ MCD_OPC_Decode, 135, 6, 140, 1, // Opcode: FMUL_D -/* 9575 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9588 -/* 9579 */ MCD_OPC_CheckPredicate, 8, 47, 16, // Skip to: 13726 -/* 9583 */ MCD_OPC_Decode, 212, 5, 139, 1, // Opcode: FDIV_W -/* 9588 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9601 -/* 9592 */ MCD_OPC_CheckPredicate, 8, 34, 16, // Skip to: 13726 -/* 9596 */ MCD_OPC_Decode, 206, 5, 140, 1, // Opcode: FDIV_D -/* 9601 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9614 -/* 9605 */ MCD_OPC_CheckPredicate, 8, 21, 16, // Skip to: 13726 -/* 9609 */ MCD_OPC_Decode, 247, 5, 143, 1, // Opcode: FMADD_W -/* 9614 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9627 -/* 9618 */ MCD_OPC_CheckPredicate, 8, 8, 16, // Skip to: 13726 -/* 9622 */ MCD_OPC_Decode, 246, 5, 144, 1, // Opcode: FMADD_D -/* 9627 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9640 -/* 9631 */ MCD_OPC_CheckPredicate, 8, 251, 15, // Skip to: 13726 -/* 9635 */ MCD_OPC_Decode, 134, 6, 143, 1, // Opcode: FMSUB_W -/* 9640 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9653 -/* 9644 */ MCD_OPC_CheckPredicate, 8, 238, 15, // Skip to: 13726 -/* 9648 */ MCD_OPC_Decode, 133, 6, 144, 1, // Opcode: FMSUB_D -/* 9653 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9666 -/* 9657 */ MCD_OPC_CheckPredicate, 8, 225, 15, // Skip to: 13726 -/* 9661 */ MCD_OPC_Decode, 217, 5, 139, 1, // Opcode: FEXP2_W -/* 9666 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9679 -/* 9670 */ MCD_OPC_CheckPredicate, 8, 212, 15, // Skip to: 13726 -/* 9674 */ MCD_OPC_Decode, 215, 5, 140, 1, // Opcode: FEXP2_D -/* 9679 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9692 -/* 9683 */ MCD_OPC_CheckPredicate, 8, 199, 15, // Skip to: 13726 -/* 9687 */ MCD_OPC_Decode, 213, 5, 179, 1, // Opcode: FEXDO_H -/* 9692 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9705 -/* 9696 */ MCD_OPC_CheckPredicate, 8, 186, 15, // Skip to: 13726 -/* 9700 */ MCD_OPC_Decode, 214, 5, 180, 1, // Opcode: FEXDO_W -/* 9705 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9718 -/* 9709 */ MCD_OPC_CheckPredicate, 8, 173, 15, // Skip to: 13726 -/* 9713 */ MCD_OPC_Decode, 193, 6, 179, 1, // Opcode: FTQ_H -/* 9718 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9731 -/* 9722 */ MCD_OPC_CheckPredicate, 8, 160, 15, // Skip to: 13726 -/* 9726 */ MCD_OPC_Decode, 194, 6, 180, 1, // Opcode: FTQ_W -/* 9731 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9744 -/* 9735 */ MCD_OPC_CheckPredicate, 8, 147, 15, // Skip to: 13726 -/* 9739 */ MCD_OPC_Decode, 255, 5, 139, 1, // Opcode: FMIN_W -/* 9744 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9757 -/* 9748 */ MCD_OPC_CheckPredicate, 8, 134, 15, // Skip to: 13726 -/* 9752 */ MCD_OPC_Decode, 254, 5, 140, 1, // Opcode: FMIN_D -/* 9757 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9770 -/* 9761 */ MCD_OPC_CheckPredicate, 8, 121, 15, // Skip to: 13726 -/* 9765 */ MCD_OPC_Decode, 253, 5, 139, 1, // Opcode: FMIN_A_W -/* 9770 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9783 -/* 9774 */ MCD_OPC_CheckPredicate, 8, 108, 15, // Skip to: 13726 -/* 9778 */ MCD_OPC_Decode, 252, 5, 140, 1, // Opcode: FMIN_A_D -/* 9783 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9796 -/* 9787 */ MCD_OPC_CheckPredicate, 8, 95, 15, // Skip to: 13726 -/* 9791 */ MCD_OPC_Decode, 251, 5, 139, 1, // Opcode: FMAX_W -/* 9796 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9809 -/* 9800 */ MCD_OPC_CheckPredicate, 8, 82, 15, // Skip to: 13726 -/* 9804 */ MCD_OPC_Decode, 250, 5, 140, 1, // Opcode: FMAX_D -/* 9809 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9822 -/* 9813 */ MCD_OPC_CheckPredicate, 8, 69, 15, // Skip to: 13726 -/* 9817 */ MCD_OPC_Decode, 249, 5, 139, 1, // Opcode: FMAX_A_W -/* 9822 */ MCD_OPC_FilterValue, 31, 60, 15, // Skip to: 13726 -/* 9826 */ MCD_OPC_CheckPredicate, 8, 56, 15, // Skip to: 13726 -/* 9830 */ MCD_OPC_Decode, 248, 5, 140, 1, // Opcode: FMAX_A_D -/* 9835 */ MCD_OPC_FilterValue, 28, 59, 1, // Skip to: 10154 -/* 9839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9842 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9855 -/* 9846 */ MCD_OPC_CheckPredicate, 8, 36, 15, // Skip to: 13726 -/* 9850 */ MCD_OPC_Decode, 195, 5, 139, 1, // Opcode: FCOR_W -/* 9855 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9868 -/* 9859 */ MCD_OPC_CheckPredicate, 8, 23, 15, // Skip to: 13726 -/* 9863 */ MCD_OPC_Decode, 194, 5, 140, 1, // Opcode: FCOR_D -/* 9868 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9881 -/* 9872 */ MCD_OPC_CheckPredicate, 8, 10, 15, // Skip to: 13726 -/* 9876 */ MCD_OPC_Decode, 203, 5, 139, 1, // Opcode: FCUNE_W -/* 9881 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9894 -/* 9885 */ MCD_OPC_CheckPredicate, 8, 253, 14, // Skip to: 13726 -/* 9889 */ MCD_OPC_Decode, 202, 5, 140, 1, // Opcode: FCUNE_D -/* 9894 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9907 -/* 9898 */ MCD_OPC_CheckPredicate, 8, 240, 14, // Skip to: 13726 -/* 9902 */ MCD_OPC_Decode, 193, 5, 139, 1, // Opcode: FCNE_W -/* 9907 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9920 -/* 9911 */ MCD_OPC_CheckPredicate, 8, 227, 14, // Skip to: 13726 -/* 9915 */ MCD_OPC_Decode, 192, 5, 140, 1, // Opcode: FCNE_D -/* 9920 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9933 -/* 9924 */ MCD_OPC_CheckPredicate, 8, 214, 14, // Skip to: 13726 -/* 9928 */ MCD_OPC_Decode, 219, 9, 138, 1, // Opcode: MUL_Q_H -/* 9933 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9946 -/* 9937 */ MCD_OPC_CheckPredicate, 8, 201, 14, // Skip to: 13726 -/* 9941 */ MCD_OPC_Decode, 220, 9, 139, 1, // Opcode: MUL_Q_W -/* 9946 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9959 -/* 9950 */ MCD_OPC_CheckPredicate, 8, 188, 14, // Skip to: 13726 -/* 9954 */ MCD_OPC_Decode, 147, 8, 142, 1, // Opcode: MADD_Q_H -/* 9959 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9972 -/* 9963 */ MCD_OPC_CheckPredicate, 8, 175, 14, // Skip to: 13726 -/* 9967 */ MCD_OPC_Decode, 148, 8, 143, 1, // Opcode: MADD_Q_W -/* 9972 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9985 -/* 9976 */ MCD_OPC_CheckPredicate, 8, 162, 14, // Skip to: 13726 -/* 9980 */ MCD_OPC_Decode, 165, 9, 142, 1, // Opcode: MSUB_Q_H -/* 9985 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9998 -/* 9989 */ MCD_OPC_CheckPredicate, 8, 149, 14, // Skip to: 13726 -/* 9993 */ MCD_OPC_Decode, 166, 9, 143, 1, // Opcode: MSUB_Q_W -/* 9998 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10011 -/* 10002 */ MCD_OPC_CheckPredicate, 8, 136, 14, // Skip to: 13726 -/* 10006 */ MCD_OPC_Decode, 164, 6, 139, 1, // Opcode: FSOR_W -/* 10011 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10024 -/* 10015 */ MCD_OPC_CheckPredicate, 8, 123, 14, // Skip to: 13726 -/* 10019 */ MCD_OPC_Decode, 163, 6, 140, 1, // Opcode: FSOR_D -/* 10024 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10037 -/* 10028 */ MCD_OPC_CheckPredicate, 8, 110, 14, // Skip to: 13726 -/* 10032 */ MCD_OPC_Decode, 186, 6, 139, 1, // Opcode: FSUNE_W -/* 10037 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10050 -/* 10041 */ MCD_OPC_CheckPredicate, 8, 97, 14, // Skip to: 13726 -/* 10045 */ MCD_OPC_Decode, 185, 6, 140, 1, // Opcode: FSUNE_D -/* 10050 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10063 -/* 10054 */ MCD_OPC_CheckPredicate, 8, 84, 14, // Skip to: 13726 -/* 10058 */ MCD_OPC_Decode, 162, 6, 139, 1, // Opcode: FSNE_W -/* 10063 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10076 -/* 10067 */ MCD_OPC_CheckPredicate, 8, 71, 14, // Skip to: 13726 -/* 10071 */ MCD_OPC_Decode, 161, 6, 140, 1, // Opcode: FSNE_D -/* 10076 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10089 -/* 10080 */ MCD_OPC_CheckPredicate, 8, 58, 14, // Skip to: 13726 -/* 10084 */ MCD_OPC_Decode, 202, 9, 138, 1, // Opcode: MULR_Q_H -/* 10089 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10102 -/* 10093 */ MCD_OPC_CheckPredicate, 8, 45, 14, // Skip to: 13726 -/* 10097 */ MCD_OPC_Decode, 203, 9, 139, 1, // Opcode: MULR_Q_W -/* 10102 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10115 -/* 10106 */ MCD_OPC_CheckPredicate, 8, 32, 14, // Skip to: 13726 -/* 10110 */ MCD_OPC_Decode, 133, 8, 142, 1, // Opcode: MADDR_Q_H -/* 10115 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10128 -/* 10119 */ MCD_OPC_CheckPredicate, 8, 19, 14, // Skip to: 13726 -/* 10123 */ MCD_OPC_Decode, 134, 8, 143, 1, // Opcode: MADDR_Q_W -/* 10128 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10141 -/* 10132 */ MCD_OPC_CheckPredicate, 8, 6, 14, // Skip to: 13726 -/* 10136 */ MCD_OPC_Decode, 151, 9, 142, 1, // Opcode: MSUBR_Q_H -/* 10141 */ MCD_OPC_FilterValue, 29, 253, 13, // Skip to: 13726 -/* 10145 */ MCD_OPC_CheckPredicate, 8, 249, 13, // Skip to: 13726 -/* 10149 */ MCD_OPC_Decode, 152, 9, 143, 1, // Opcode: MSUBR_Q_W -/* 10154 */ MCD_OPC_FilterValue, 30, 219, 2, // Skip to: 10889 -/* 10158 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 10161 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10173 -/* 10165 */ MCD_OPC_CheckPredicate, 8, 229, 13, // Skip to: 13726 -/* 10169 */ MCD_OPC_Decode, 89, 137, 1, // Opcode: AND_V -/* 10173 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10186 -/* 10177 */ MCD_OPC_CheckPredicate, 8, 217, 13, // Skip to: 13726 -/* 10181 */ MCD_OPC_Decode, 138, 10, 137, 1, // Opcode: OR_V -/* 10186 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10199 -/* 10190 */ MCD_OPC_CheckPredicate, 8, 204, 13, // Skip to: 13726 -/* 10194 */ MCD_OPC_Decode, 254, 9, 137, 1, // Opcode: NOR_V -/* 10199 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10212 -/* 10203 */ MCD_OPC_CheckPredicate, 8, 191, 13, // Skip to: 13726 -/* 10207 */ MCD_OPC_Decode, 241, 13, 137, 1, // Opcode: XOR_V -/* 10212 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10225 -/* 10216 */ MCD_OPC_CheckPredicate, 8, 178, 13, // Skip to: 13726 -/* 10220 */ MCD_OPC_Decode, 142, 2, 141, 1, // Opcode: BMNZ_V -/* 10225 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10238 -/* 10229 */ MCD_OPC_CheckPredicate, 8, 165, 13, // Skip to: 13726 -/* 10233 */ MCD_OPC_Decode, 144, 2, 141, 1, // Opcode: BMZ_V -/* 10238 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10251 -/* 10242 */ MCD_OPC_CheckPredicate, 8, 152, 13, // Skip to: 13726 -/* 10246 */ MCD_OPC_Decode, 179, 2, 141, 1, // Opcode: BSEL_V -/* 10251 */ MCD_OPC_FilterValue, 24, 211, 0, // Skip to: 10466 -/* 10255 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10258 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10271 -/* 10262 */ MCD_OPC_CheckPredicate, 8, 132, 13, // Skip to: 13726 -/* 10266 */ MCD_OPC_Decode, 231, 5, 181, 1, // Opcode: FILL_B -/* 10271 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10284 -/* 10275 */ MCD_OPC_CheckPredicate, 8, 119, 13, // Skip to: 13726 -/* 10279 */ MCD_OPC_Decode, 235, 5, 182, 1, // Opcode: FILL_H -/* 10284 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10297 -/* 10288 */ MCD_OPC_CheckPredicate, 8, 106, 13, // Skip to: 13726 -/* 10292 */ MCD_OPC_Decode, 236, 5, 183, 1, // Opcode: FILL_W -/* 10297 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10310 -/* 10301 */ MCD_OPC_CheckPredicate, 14, 93, 13, // Skip to: 13726 -/* 10305 */ MCD_OPC_Decode, 232, 5, 184, 1, // Opcode: FILL_D -/* 10310 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10323 -/* 10314 */ MCD_OPC_CheckPredicate, 8, 80, 13, // Skip to: 13726 -/* 10318 */ MCD_OPC_Decode, 157, 10, 173, 1, // Opcode: PCNT_B -/* 10323 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10336 -/* 10327 */ MCD_OPC_CheckPredicate, 8, 67, 13, // Skip to: 13726 -/* 10331 */ MCD_OPC_Decode, 159, 10, 185, 1, // Opcode: PCNT_H -/* 10336 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10349 -/* 10340 */ MCD_OPC_CheckPredicate, 8, 54, 13, // Skip to: 13726 -/* 10344 */ MCD_OPC_Decode, 160, 10, 186, 1, // Opcode: PCNT_W -/* 10349 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10362 -/* 10353 */ MCD_OPC_CheckPredicate, 8, 41, 13, // Skip to: 13726 -/* 10357 */ MCD_OPC_Decode, 158, 10, 187, 1, // Opcode: PCNT_D -/* 10362 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10375 -/* 10366 */ MCD_OPC_CheckPredicate, 8, 28, 13, // Skip to: 13726 -/* 10370 */ MCD_OPC_Decode, 231, 9, 173, 1, // Opcode: NLOC_B -/* 10375 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10388 -/* 10379 */ MCD_OPC_CheckPredicate, 8, 15, 13, // Skip to: 13726 -/* 10383 */ MCD_OPC_Decode, 233, 9, 185, 1, // Opcode: NLOC_H -/* 10388 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10401 -/* 10392 */ MCD_OPC_CheckPredicate, 8, 2, 13, // Skip to: 13726 -/* 10396 */ MCD_OPC_Decode, 234, 9, 186, 1, // Opcode: NLOC_W -/* 10401 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10414 -/* 10405 */ MCD_OPC_CheckPredicate, 8, 245, 12, // Skip to: 13726 -/* 10409 */ MCD_OPC_Decode, 232, 9, 187, 1, // Opcode: NLOC_D -/* 10414 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10427 -/* 10418 */ MCD_OPC_CheckPredicate, 8, 232, 12, // Skip to: 13726 -/* 10422 */ MCD_OPC_Decode, 235, 9, 173, 1, // Opcode: NLZC_B -/* 10427 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10440 -/* 10431 */ MCD_OPC_CheckPredicate, 8, 219, 12, // Skip to: 13726 -/* 10435 */ MCD_OPC_Decode, 237, 9, 185, 1, // Opcode: NLZC_H -/* 10440 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10453 -/* 10444 */ MCD_OPC_CheckPredicate, 8, 206, 12, // Skip to: 13726 -/* 10448 */ MCD_OPC_Decode, 238, 9, 186, 1, // Opcode: NLZC_W -/* 10453 */ MCD_OPC_FilterValue, 15, 197, 12, // Skip to: 13726 -/* 10457 */ MCD_OPC_CheckPredicate, 8, 193, 12, // Skip to: 13726 -/* 10461 */ MCD_OPC_Decode, 236, 9, 187, 1, // Opcode: NLZC_D -/* 10466 */ MCD_OPC_FilterValue, 25, 184, 12, // Skip to: 13726 -/* 10470 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10473 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10486 -/* 10477 */ MCD_OPC_CheckPredicate, 8, 173, 12, // Skip to: 13726 -/* 10481 */ MCD_OPC_Decode, 182, 5, 186, 1, // Opcode: FCLASS_W -/* 10486 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10499 -/* 10490 */ MCD_OPC_CheckPredicate, 8, 160, 12, // Skip to: 13726 -/* 10494 */ MCD_OPC_Decode, 181, 5, 187, 1, // Opcode: FCLASS_D -/* 10499 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10512 -/* 10503 */ MCD_OPC_CheckPredicate, 8, 147, 12, // Skip to: 13726 -/* 10507 */ MCD_OPC_Decode, 196, 6, 186, 1, // Opcode: FTRUNC_S_W -/* 10512 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10525 -/* 10516 */ MCD_OPC_CheckPredicate, 8, 134, 12, // Skip to: 13726 -/* 10520 */ MCD_OPC_Decode, 195, 6, 187, 1, // Opcode: FTRUNC_S_D -/* 10525 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10538 -/* 10529 */ MCD_OPC_CheckPredicate, 8, 121, 12, // Skip to: 13726 -/* 10533 */ MCD_OPC_Decode, 198, 6, 186, 1, // Opcode: FTRUNC_U_W -/* 10538 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10551 -/* 10542 */ MCD_OPC_CheckPredicate, 8, 108, 12, // Skip to: 13726 -/* 10546 */ MCD_OPC_Decode, 197, 6, 187, 1, // Opcode: FTRUNC_U_D -/* 10551 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10564 -/* 10555 */ MCD_OPC_CheckPredicate, 8, 95, 12, // Skip to: 13726 -/* 10559 */ MCD_OPC_Decode, 171, 6, 186, 1, // Opcode: FSQRT_W -/* 10564 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10577 -/* 10568 */ MCD_OPC_CheckPredicate, 8, 82, 12, // Skip to: 13726 -/* 10572 */ MCD_OPC_Decode, 165, 6, 187, 1, // Opcode: FSQRT_D -/* 10577 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10590 -/* 10581 */ MCD_OPC_CheckPredicate, 8, 69, 12, // Skip to: 13726 -/* 10585 */ MCD_OPC_Decode, 152, 6, 186, 1, // Opcode: FRSQRT_W -/* 10590 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10603 -/* 10594 */ MCD_OPC_CheckPredicate, 8, 56, 12, // Skip to: 13726 -/* 10598 */ MCD_OPC_Decode, 151, 6, 187, 1, // Opcode: FRSQRT_D -/* 10603 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10616 -/* 10607 */ MCD_OPC_CheckPredicate, 8, 43, 12, // Skip to: 13726 -/* 10611 */ MCD_OPC_Decode, 148, 6, 186, 1, // Opcode: FRCP_W -/* 10616 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10629 -/* 10620 */ MCD_OPC_CheckPredicate, 8, 30, 12, // Skip to: 13726 -/* 10624 */ MCD_OPC_Decode, 147, 6, 187, 1, // Opcode: FRCP_D -/* 10629 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10642 -/* 10633 */ MCD_OPC_CheckPredicate, 8, 17, 12, // Skip to: 13726 -/* 10637 */ MCD_OPC_Decode, 150, 6, 186, 1, // Opcode: FRINT_W -/* 10642 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10655 -/* 10646 */ MCD_OPC_CheckPredicate, 8, 4, 12, // Skip to: 13726 -/* 10650 */ MCD_OPC_Decode, 149, 6, 187, 1, // Opcode: FRINT_D -/* 10655 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10668 -/* 10659 */ MCD_OPC_CheckPredicate, 8, 247, 11, // Skip to: 13726 -/* 10663 */ MCD_OPC_Decode, 238, 5, 186, 1, // Opcode: FLOG2_W -/* 10668 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 10681 -/* 10672 */ MCD_OPC_CheckPredicate, 8, 234, 11, // Skip to: 13726 -/* 10676 */ MCD_OPC_Decode, 237, 5, 187, 1, // Opcode: FLOG2_D -/* 10681 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 10694 -/* 10685 */ MCD_OPC_CheckPredicate, 8, 221, 11, // Skip to: 13726 -/* 10689 */ MCD_OPC_Decode, 220, 5, 188, 1, // Opcode: FEXUPL_W -/* 10694 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 10707 -/* 10698 */ MCD_OPC_CheckPredicate, 8, 208, 11, // Skip to: 13726 -/* 10702 */ MCD_OPC_Decode, 219, 5, 189, 1, // Opcode: FEXUPL_D -/* 10707 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10720 -/* 10711 */ MCD_OPC_CheckPredicate, 8, 195, 11, // Skip to: 13726 -/* 10715 */ MCD_OPC_Decode, 222, 5, 188, 1, // Opcode: FEXUPR_W -/* 10720 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10733 -/* 10724 */ MCD_OPC_CheckPredicate, 8, 182, 11, // Skip to: 13726 -/* 10728 */ MCD_OPC_Decode, 221, 5, 189, 1, // Opcode: FEXUPR_D -/* 10733 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10746 -/* 10737 */ MCD_OPC_CheckPredicate, 8, 169, 11, // Skip to: 13726 -/* 10741 */ MCD_OPC_Decode, 228, 5, 188, 1, // Opcode: FFQL_W -/* 10746 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10759 -/* 10750 */ MCD_OPC_CheckPredicate, 8, 156, 11, // Skip to: 13726 -/* 10754 */ MCD_OPC_Decode, 227, 5, 189, 1, // Opcode: FFQL_D -/* 10759 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10772 -/* 10763 */ MCD_OPC_CheckPredicate, 8, 143, 11, // Skip to: 13726 -/* 10767 */ MCD_OPC_Decode, 230, 5, 188, 1, // Opcode: FFQR_W -/* 10772 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10785 -/* 10776 */ MCD_OPC_CheckPredicate, 8, 130, 11, // Skip to: 13726 -/* 10780 */ MCD_OPC_Decode, 229, 5, 189, 1, // Opcode: FFQR_D -/* 10785 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10798 -/* 10789 */ MCD_OPC_CheckPredicate, 8, 117, 11, // Skip to: 13726 -/* 10793 */ MCD_OPC_Decode, 190, 6, 186, 1, // Opcode: FTINT_S_W -/* 10798 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10811 -/* 10802 */ MCD_OPC_CheckPredicate, 8, 104, 11, // Skip to: 13726 -/* 10806 */ MCD_OPC_Decode, 189, 6, 187, 1, // Opcode: FTINT_S_D -/* 10811 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10824 -/* 10815 */ MCD_OPC_CheckPredicate, 8, 91, 11, // Skip to: 13726 -/* 10819 */ MCD_OPC_Decode, 192, 6, 186, 1, // Opcode: FTINT_U_W -/* 10824 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10837 -/* 10828 */ MCD_OPC_CheckPredicate, 8, 78, 11, // Skip to: 13726 -/* 10832 */ MCD_OPC_Decode, 191, 6, 187, 1, // Opcode: FTINT_U_D -/* 10837 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10850 -/* 10841 */ MCD_OPC_CheckPredicate, 8, 65, 11, // Skip to: 13726 -/* 10845 */ MCD_OPC_Decode, 224, 5, 186, 1, // Opcode: FFINT_S_W -/* 10850 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 10863 -/* 10854 */ MCD_OPC_CheckPredicate, 8, 52, 11, // Skip to: 13726 -/* 10858 */ MCD_OPC_Decode, 223, 5, 187, 1, // Opcode: FFINT_S_D -/* 10863 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 10876 -/* 10867 */ MCD_OPC_CheckPredicate, 8, 39, 11, // Skip to: 13726 -/* 10871 */ MCD_OPC_Decode, 226, 5, 186, 1, // Opcode: FFINT_U_W -/* 10876 */ MCD_OPC_FilterValue, 31, 30, 11, // Skip to: 13726 -/* 10880 */ MCD_OPC_CheckPredicate, 8, 26, 11, // Skip to: 13726 -/* 10884 */ MCD_OPC_Decode, 225, 5, 187, 1, // Opcode: FFINT_U_D -/* 10889 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 10902 -/* 10893 */ MCD_OPC_CheckPredicate, 8, 13, 11, // Skip to: 13726 -/* 10897 */ MCD_OPC_Decode, 177, 7, 190, 1, // Opcode: LD_B -/* 10902 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 10915 -/* 10906 */ MCD_OPC_CheckPredicate, 8, 0, 11, // Skip to: 13726 -/* 10910 */ MCD_OPC_Decode, 179, 7, 190, 1, // Opcode: LD_H -/* 10915 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 10928 -/* 10919 */ MCD_OPC_CheckPredicate, 8, 243, 10, // Skip to: 13726 -/* 10923 */ MCD_OPC_Decode, 180, 7, 190, 1, // Opcode: LD_W -/* 10928 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 10941 -/* 10932 */ MCD_OPC_CheckPredicate, 8, 230, 10, // Skip to: 13726 -/* 10936 */ MCD_OPC_Decode, 178, 7, 190, 1, // Opcode: LD_D -/* 10941 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 10954 -/* 10945 */ MCD_OPC_CheckPredicate, 8, 217, 10, // Skip to: 13726 -/* 10949 */ MCD_OPC_Decode, 186, 12, 190, 1, // Opcode: ST_B -/* 10954 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 10967 -/* 10958 */ MCD_OPC_CheckPredicate, 8, 204, 10, // Skip to: 13726 -/* 10962 */ MCD_OPC_Decode, 188, 12, 190, 1, // Opcode: ST_H -/* 10967 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 10980 -/* 10971 */ MCD_OPC_CheckPredicate, 8, 191, 10, // Skip to: 13726 -/* 10975 */ MCD_OPC_Decode, 189, 12, 190, 1, // Opcode: ST_W -/* 10980 */ MCD_OPC_FilterValue, 39, 182, 10, // Skip to: 13726 -/* 10984 */ MCD_OPC_CheckPredicate, 8, 178, 10, // Skip to: 13726 -/* 10988 */ MCD_OPC_Decode, 187, 12, 190, 1, // Opcode: ST_D -/* 10993 */ MCD_OPC_FilterValue, 31, 113, 9, // Skip to: 13414 -/* 10997 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 11000 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11013 -/* 11004 */ MCD_OPC_CheckPredicate, 6, 158, 10, // Skip to: 13726 -/* 11008 */ MCD_OPC_Decode, 145, 5, 191, 1, // Opcode: EXT -/* 11013 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11026 -/* 11017 */ MCD_OPC_CheckPredicate, 6, 145, 10, // Skip to: 13726 -/* 11021 */ MCD_OPC_Decode, 228, 6, 192, 1, // Opcode: INS -/* 11026 */ MCD_OPC_FilterValue, 10, 42, 0, // Skip to: 11072 -/* 11030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11033 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11046 -/* 11037 */ MCD_OPC_CheckPredicate, 12, 125, 10, // Skip to: 13726 -/* 11041 */ MCD_OPC_Decode, 236, 7, 193, 1, // Opcode: LWX -/* 11046 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11059 -/* 11050 */ MCD_OPC_CheckPredicate, 12, 112, 10, // Skip to: 13726 -/* 11054 */ MCD_OPC_Decode, 187, 7, 193, 1, // Opcode: LHX -/* 11059 */ MCD_OPC_FilterValue, 6, 103, 10, // Skip to: 13726 -/* 11063 */ MCD_OPC_CheckPredicate, 12, 99, 10, // Skip to: 13726 -/* 11067 */ MCD_OPC_Decode, 156, 7, 193, 1, // Opcode: LBUX -/* 11072 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11091 -/* 11076 */ MCD_OPC_CheckPredicate, 12, 86, 10, // Skip to: 13726 -/* 11080 */ MCD_OPC_CheckField, 6, 10, 0, 80, 10, // Skip to: 13726 -/* 11086 */ MCD_OPC_Decode, 241, 6, 194, 1, // Opcode: INSV -/* 11091 */ MCD_OPC_FilterValue, 16, 51, 1, // Skip to: 11402 -/* 11095 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11098 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11110 -/* 11102 */ MCD_OPC_CheckPredicate, 12, 60, 10, // Skip to: 13726 -/* 11106 */ MCD_OPC_Decode, 56, 195, 1, // Opcode: ADDU_QB -/* 11110 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 11123 -/* 11114 */ MCD_OPC_CheckPredicate, 12, 48, 10, // Skip to: 13726 -/* 11118 */ MCD_OPC_Decode, 218, 12, 195, 1, // Opcode: SUBU_QB -/* 11123 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11135 -/* 11127 */ MCD_OPC_CheckPredicate, 12, 35, 10, // Skip to: 13726 -/* 11131 */ MCD_OPC_Decode, 58, 195, 1, // Opcode: ADDU_S_QB -/* 11135 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11148 -/* 11139 */ MCD_OPC_CheckPredicate, 12, 23, 10, // Skip to: 13726 -/* 11143 */ MCD_OPC_Decode, 220, 12, 195, 1, // Opcode: SUBU_S_QB -/* 11148 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11161 -/* 11152 */ MCD_OPC_CheckPredicate, 12, 10, 10, // Skip to: 13726 -/* 11156 */ MCD_OPC_Decode, 196, 9, 195, 1, // Opcode: MULEU_S_PH_QBL -/* 11161 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 11174 -/* 11165 */ MCD_OPC_CheckPredicate, 12, 253, 9, // Skip to: 13726 -/* 11169 */ MCD_OPC_Decode, 197, 9, 195, 1, // Opcode: MULEU_S_PH_QBR -/* 11174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11186 -/* 11178 */ MCD_OPC_CheckPredicate, 30, 240, 9, // Skip to: 13726 -/* 11182 */ MCD_OPC_Decode, 55, 195, 1, // Opcode: ADDU_PH -/* 11186 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 11199 -/* 11190 */ MCD_OPC_CheckPredicate, 30, 228, 9, // Skip to: 13726 -/* 11194 */ MCD_OPC_Decode, 217, 12, 195, 1, // Opcode: SUBU_PH -/* 11199 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11211 -/* 11203 */ MCD_OPC_CheckPredicate, 12, 215, 9, // Skip to: 13726 -/* 11207 */ MCD_OPC_Decode, 36, 195, 1, // Opcode: ADDQ_PH -/* 11211 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11224 -/* 11215 */ MCD_OPC_CheckPredicate, 12, 203, 9, // Skip to: 13726 -/* 11219 */ MCD_OPC_Decode, 195, 12, 195, 1, // Opcode: SUBQ_PH -/* 11224 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11236 -/* 11228 */ MCD_OPC_CheckPredicate, 30, 190, 9, // Skip to: 13726 -/* 11232 */ MCD_OPC_Decode, 57, 195, 1, // Opcode: ADDU_S_PH -/* 11236 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11249 -/* 11240 */ MCD_OPC_CheckPredicate, 30, 178, 9, // Skip to: 13726 -/* 11244 */ MCD_OPC_Decode, 219, 12, 195, 1, // Opcode: SUBU_S_PH -/* 11249 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 11261 -/* 11253 */ MCD_OPC_CheckPredicate, 12, 165, 9, // Skip to: 13726 -/* 11257 */ MCD_OPC_Decode, 37, 195, 1, // Opcode: ADDQ_S_PH -/* 11261 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11274 -/* 11265 */ MCD_OPC_CheckPredicate, 12, 153, 9, // Skip to: 13726 -/* 11269 */ MCD_OPC_Decode, 196, 12, 195, 1, // Opcode: SUBQ_S_PH -/* 11274 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 11285 -/* 11278 */ MCD_OPC_CheckPredicate, 12, 140, 9, // Skip to: 13726 -/* 11282 */ MCD_OPC_Decode, 39, 35, // Opcode: ADDSC -/* 11285 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 11296 -/* 11289 */ MCD_OPC_CheckPredicate, 12, 129, 9, // Skip to: 13726 -/* 11293 */ MCD_OPC_Decode, 67, 35, // Opcode: ADDWC -/* 11296 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 11308 -/* 11300 */ MCD_OPC_CheckPredicate, 12, 118, 9, // Skip to: 13726 -/* 11304 */ MCD_OPC_Decode, 223, 8, 35, // Opcode: MODSUB -/* 11308 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 11327 -/* 11312 */ MCD_OPC_CheckPredicate, 12, 106, 9, // Skip to: 13726 -/* 11316 */ MCD_OPC_CheckField, 16, 5, 0, 100, 9, // Skip to: 13726 -/* 11322 */ MCD_OPC_Decode, 236, 10, 196, 1, // Opcode: RADDU_W_QB -/* 11327 */ MCD_OPC_FilterValue, 22, 7, 0, // Skip to: 11338 -/* 11331 */ MCD_OPC_CheckPredicate, 12, 87, 9, // Skip to: 13726 -/* 11335 */ MCD_OPC_Decode, 38, 35, // Opcode: ADDQ_S_W -/* 11338 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 11350 -/* 11342 */ MCD_OPC_CheckPredicate, 12, 76, 9, // Skip to: 13726 -/* 11346 */ MCD_OPC_Decode, 197, 12, 35, // Opcode: SUBQ_S_W -/* 11350 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 11363 -/* 11354 */ MCD_OPC_CheckPredicate, 12, 64, 9, // Skip to: 13726 -/* 11358 */ MCD_OPC_Decode, 194, 9, 197, 1, // Opcode: MULEQ_S_W_PHL -/* 11363 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 11376 -/* 11367 */ MCD_OPC_CheckPredicate, 12, 51, 9, // Skip to: 13726 -/* 11371 */ MCD_OPC_Decode, 195, 9, 197, 1, // Opcode: MULEQ_S_W_PHR -/* 11376 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11389 -/* 11380 */ MCD_OPC_CheckPredicate, 30, 38, 9, // Skip to: 13726 -/* 11384 */ MCD_OPC_Decode, 200, 9, 195, 1, // Opcode: MULQ_S_PH -/* 11389 */ MCD_OPC_FilterValue, 31, 29, 9, // Skip to: 13726 -/* 11393 */ MCD_OPC_CheckPredicate, 12, 25, 9, // Skip to: 13726 -/* 11397 */ MCD_OPC_Decode, 198, 9, 195, 1, // Opcode: MULQ_RS_PH -/* 11402 */ MCD_OPC_FilterValue, 17, 69, 1, // Skip to: 11731 -/* 11406 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11409 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11428 -/* 11413 */ MCD_OPC_CheckPredicate, 12, 5, 9, // Skip to: 13726 -/* 11417 */ MCD_OPC_CheckField, 11, 5, 0, 255, 8, // Skip to: 13726 -/* 11423 */ MCD_OPC_Decode, 161, 3, 198, 1, // Opcode: CMPU_EQ_QB -/* 11428 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11447 -/* 11432 */ MCD_OPC_CheckPredicate, 12, 242, 8, // Skip to: 13726 -/* 11436 */ MCD_OPC_CheckField, 11, 5, 0, 236, 8, // Skip to: 13726 -/* 11442 */ MCD_OPC_Decode, 163, 3, 198, 1, // Opcode: CMPU_LT_QB -/* 11447 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 11466 -/* 11451 */ MCD_OPC_CheckPredicate, 12, 223, 8, // Skip to: 13726 -/* 11455 */ MCD_OPC_CheckField, 11, 5, 0, 217, 8, // Skip to: 13726 -/* 11461 */ MCD_OPC_Decode, 162, 3, 198, 1, // Opcode: CMPU_LE_QB -/* 11466 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11479 -/* 11470 */ MCD_OPC_CheckPredicate, 12, 204, 8, // Skip to: 13726 -/* 11474 */ MCD_OPC_Decode, 162, 10, 195, 1, // Opcode: PICK_QB -/* 11479 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11492 -/* 11483 */ MCD_OPC_CheckPredicate, 12, 191, 8, // Skip to: 13726 -/* 11487 */ MCD_OPC_Decode, 158, 3, 197, 1, // Opcode: CMPGU_EQ_QB -/* 11492 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11505 -/* 11496 */ MCD_OPC_CheckPredicate, 12, 178, 8, // Skip to: 13726 -/* 11500 */ MCD_OPC_Decode, 160, 3, 197, 1, // Opcode: CMPGU_LT_QB -/* 11505 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11518 -/* 11509 */ MCD_OPC_CheckPredicate, 12, 165, 8, // Skip to: 13726 -/* 11513 */ MCD_OPC_Decode, 159, 3, 197, 1, // Opcode: CMPGU_LE_QB -/* 11518 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 11537 -/* 11522 */ MCD_OPC_CheckPredicate, 12, 152, 8, // Skip to: 13726 -/* 11526 */ MCD_OPC_CheckField, 11, 5, 0, 146, 8, // Skip to: 13726 -/* 11532 */ MCD_OPC_Decode, 165, 3, 198, 1, // Opcode: CMP_EQ_PH -/* 11537 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 11556 -/* 11541 */ MCD_OPC_CheckPredicate, 12, 133, 8, // Skip to: 13726 -/* 11545 */ MCD_OPC_CheckField, 11, 5, 0, 127, 8, // Skip to: 13726 -/* 11551 */ MCD_OPC_Decode, 173, 3, 198, 1, // Opcode: CMP_LT_PH -/* 11556 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 11575 -/* 11560 */ MCD_OPC_CheckPredicate, 12, 114, 8, // Skip to: 13726 -/* 11564 */ MCD_OPC_CheckField, 11, 5, 0, 108, 8, // Skip to: 13726 -/* 11570 */ MCD_OPC_Decode, 170, 3, 198, 1, // Opcode: CMP_LE_PH -/* 11575 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11588 -/* 11579 */ MCD_OPC_CheckPredicate, 12, 95, 8, // Skip to: 13726 -/* 11583 */ MCD_OPC_Decode, 161, 10, 195, 1, // Opcode: PICK_PH -/* 11588 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 11601 -/* 11592 */ MCD_OPC_CheckPredicate, 12, 82, 8, // Skip to: 13726 -/* 11596 */ MCD_OPC_Decode, 176, 10, 195, 1, // Opcode: PRECRQ_QB_PH -/* 11601 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11614 -/* 11605 */ MCD_OPC_CheckPredicate, 30, 69, 8, // Skip to: 13726 -/* 11609 */ MCD_OPC_Decode, 178, 10, 195, 1, // Opcode: PRECR_QB_PH -/* 11614 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 11627 -/* 11618 */ MCD_OPC_CheckPredicate, 12, 56, 8, // Skip to: 13726 -/* 11622 */ MCD_OPC_Decode, 146, 10, 195, 1, // Opcode: PACKRL_PH -/* 11627 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11640 -/* 11631 */ MCD_OPC_CheckPredicate, 12, 43, 8, // Skip to: 13726 -/* 11635 */ MCD_OPC_Decode, 174, 10, 195, 1, // Opcode: PRECRQU_S_QB_PH -/* 11640 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 11653 -/* 11644 */ MCD_OPC_CheckPredicate, 12, 30, 8, // Skip to: 13726 -/* 11648 */ MCD_OPC_Decode, 175, 10, 199, 1, // Opcode: PRECRQ_PH_W -/* 11653 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 11666 -/* 11657 */ MCD_OPC_CheckPredicate, 12, 17, 8, // Skip to: 13726 -/* 11661 */ MCD_OPC_Decode, 177, 10, 199, 1, // Opcode: PRECRQ_RS_PH_W -/* 11666 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 11679 -/* 11670 */ MCD_OPC_CheckPredicate, 30, 4, 8, // Skip to: 13726 -/* 11674 */ MCD_OPC_Decode, 155, 3, 197, 1, // Opcode: CMPGDU_EQ_QB -/* 11679 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 11692 -/* 11683 */ MCD_OPC_CheckPredicate, 30, 247, 7, // Skip to: 13726 -/* 11687 */ MCD_OPC_Decode, 157, 3, 197, 1, // Opcode: CMPGDU_LT_QB -/* 11692 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 11705 -/* 11696 */ MCD_OPC_CheckPredicate, 30, 234, 7, // Skip to: 13726 -/* 11700 */ MCD_OPC_Decode, 156, 3, 197, 1, // Opcode: CMPGDU_LE_QB -/* 11705 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11718 -/* 11709 */ MCD_OPC_CheckPredicate, 30, 221, 7, // Skip to: 13726 -/* 11713 */ MCD_OPC_Decode, 179, 10, 200, 1, // Opcode: PRECR_SRA_PH_W -/* 11718 */ MCD_OPC_FilterValue, 31, 212, 7, // Skip to: 13726 -/* 11722 */ MCD_OPC_CheckPredicate, 30, 208, 7, // Skip to: 13726 -/* 11726 */ MCD_OPC_Decode, 180, 10, 200, 1, // Opcode: PRECR_SRA_R_PH_W -/* 11731 */ MCD_OPC_FilterValue, 18, 74, 1, // Skip to: 12065 -/* 11735 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11738 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11756 -/* 11742 */ MCD_OPC_CheckPredicate, 30, 188, 7, // Skip to: 13726 -/* 11746 */ MCD_OPC_CheckField, 21, 5, 0, 182, 7, // Skip to: 13726 -/* 11752 */ MCD_OPC_Decode, 23, 201, 1, // Opcode: ABSQ_S_QB -/* 11756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11769 -/* 11760 */ MCD_OPC_CheckPredicate, 12, 170, 7, // Skip to: 13726 -/* 11764 */ MCD_OPC_Decode, 244, 10, 202, 1, // Opcode: REPL_QB -/* 11769 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 11788 -/* 11773 */ MCD_OPC_CheckPredicate, 12, 157, 7, // Skip to: 13726 -/* 11777 */ MCD_OPC_CheckField, 21, 5, 0, 151, 7, // Skip to: 13726 -/* 11783 */ MCD_OPC_Decode, 242, 10, 203, 1, // Opcode: REPLV_QB -/* 11788 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 11807 -/* 11792 */ MCD_OPC_CheckPredicate, 12, 138, 7, // Skip to: 13726 -/* 11796 */ MCD_OPC_CheckField, 21, 5, 0, 132, 7, // Skip to: 13726 -/* 11802 */ MCD_OPC_Decode, 164, 10, 201, 1, // Opcode: PRECEQU_PH_QBL -/* 11807 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 11826 -/* 11811 */ MCD_OPC_CheckPredicate, 12, 119, 7, // Skip to: 13726 -/* 11815 */ MCD_OPC_CheckField, 21, 5, 0, 113, 7, // Skip to: 13726 -/* 11821 */ MCD_OPC_Decode, 166, 10, 201, 1, // Opcode: PRECEQU_PH_QBR -/* 11826 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 11845 -/* 11830 */ MCD_OPC_CheckPredicate, 12, 100, 7, // Skip to: 13726 -/* 11834 */ MCD_OPC_CheckField, 21, 5, 0, 94, 7, // Skip to: 13726 -/* 11840 */ MCD_OPC_Decode, 165, 10, 201, 1, // Opcode: PRECEQU_PH_QBLA -/* 11845 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 11864 -/* 11849 */ MCD_OPC_CheckPredicate, 12, 81, 7, // Skip to: 13726 -/* 11853 */ MCD_OPC_CheckField, 21, 5, 0, 75, 7, // Skip to: 13726 -/* 11859 */ MCD_OPC_Decode, 167, 10, 201, 1, // Opcode: PRECEQU_PH_QBRA -/* 11864 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 11882 -/* 11868 */ MCD_OPC_CheckPredicate, 12, 62, 7, // Skip to: 13726 -/* 11872 */ MCD_OPC_CheckField, 21, 5, 0, 56, 7, // Skip to: 13726 -/* 11878 */ MCD_OPC_Decode, 22, 201, 1, // Opcode: ABSQ_S_PH -/* 11882 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 11895 -/* 11886 */ MCD_OPC_CheckPredicate, 12, 44, 7, // Skip to: 13726 -/* 11890 */ MCD_OPC_Decode, 243, 10, 202, 1, // Opcode: REPL_PH -/* 11895 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 11914 -/* 11899 */ MCD_OPC_CheckPredicate, 12, 31, 7, // Skip to: 13726 -/* 11903 */ MCD_OPC_CheckField, 21, 5, 0, 25, 7, // Skip to: 13726 -/* 11909 */ MCD_OPC_Decode, 241, 10, 203, 1, // Opcode: REPLV_PH -/* 11914 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11933 -/* 11918 */ MCD_OPC_CheckPredicate, 12, 12, 7, // Skip to: 13726 -/* 11922 */ MCD_OPC_CheckField, 21, 5, 0, 6, 7, // Skip to: 13726 -/* 11928 */ MCD_OPC_Decode, 168, 10, 204, 1, // Opcode: PRECEQ_W_PHL -/* 11933 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 11952 -/* 11937 */ MCD_OPC_CheckPredicate, 12, 249, 6, // Skip to: 13726 -/* 11941 */ MCD_OPC_CheckField, 21, 5, 0, 243, 6, // Skip to: 13726 -/* 11947 */ MCD_OPC_Decode, 169, 10, 204, 1, // Opcode: PRECEQ_W_PHR -/* 11952 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 11970 -/* 11956 */ MCD_OPC_CheckPredicate, 12, 230, 6, // Skip to: 13726 -/* 11960 */ MCD_OPC_CheckField, 21, 5, 0, 224, 6, // Skip to: 13726 -/* 11966 */ MCD_OPC_Decode, 24, 205, 1, // Opcode: ABSQ_S_W -/* 11970 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 11989 -/* 11974 */ MCD_OPC_CheckPredicate, 12, 212, 6, // Skip to: 13726 -/* 11978 */ MCD_OPC_CheckField, 21, 5, 0, 206, 6, // Skip to: 13726 -/* 11984 */ MCD_OPC_Decode, 249, 1, 205, 1, // Opcode: BITREV -/* 11989 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 12008 -/* 11993 */ MCD_OPC_CheckPredicate, 12, 193, 6, // Skip to: 13726 -/* 11997 */ MCD_OPC_CheckField, 21, 5, 0, 187, 6, // Skip to: 13726 -/* 12003 */ MCD_OPC_Decode, 170, 10, 201, 1, // Opcode: PRECEU_PH_QBL -/* 12008 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 12027 -/* 12012 */ MCD_OPC_CheckPredicate, 12, 174, 6, // Skip to: 13726 -/* 12016 */ MCD_OPC_CheckField, 21, 5, 0, 168, 6, // Skip to: 13726 -/* 12022 */ MCD_OPC_Decode, 172, 10, 201, 1, // Opcode: PRECEU_PH_QBR -/* 12027 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 12046 -/* 12031 */ MCD_OPC_CheckPredicate, 12, 155, 6, // Skip to: 13726 -/* 12035 */ MCD_OPC_CheckField, 21, 5, 0, 149, 6, // Skip to: 13726 -/* 12041 */ MCD_OPC_Decode, 171, 10, 201, 1, // Opcode: PRECEU_PH_QBLA -/* 12046 */ MCD_OPC_FilterValue, 31, 140, 6, // Skip to: 13726 -/* 12050 */ MCD_OPC_CheckPredicate, 12, 136, 6, // Skip to: 13726 -/* 12054 */ MCD_OPC_CheckField, 21, 5, 0, 130, 6, // Skip to: 13726 -/* 12060 */ MCD_OPC_Decode, 173, 10, 201, 1, // Opcode: PRECEU_PH_QBRA -/* 12065 */ MCD_OPC_FilterValue, 19, 31, 1, // Skip to: 12356 -/* 12069 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12072 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12085 -/* 12076 */ MCD_OPC_CheckPredicate, 12, 110, 6, // Skip to: 13726 -/* 12080 */ MCD_OPC_Decode, 199, 11, 206, 1, // Opcode: SHLL_QB -/* 12085 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12098 -/* 12089 */ MCD_OPC_CheckPredicate, 12, 97, 6, // Skip to: 13726 -/* 12093 */ MCD_OPC_Decode, 215, 11, 206, 1, // Opcode: SHRL_QB -/* 12098 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12111 -/* 12102 */ MCD_OPC_CheckPredicate, 12, 84, 6, // Skip to: 13726 -/* 12106 */ MCD_OPC_Decode, 195, 11, 207, 1, // Opcode: SHLLV_QB -/* 12111 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12124 -/* 12115 */ MCD_OPC_CheckPredicate, 12, 71, 6, // Skip to: 13726 -/* 12119 */ MCD_OPC_Decode, 213, 11, 207, 1, // Opcode: SHRLV_QB -/* 12124 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12137 -/* 12128 */ MCD_OPC_CheckPredicate, 30, 58, 6, // Skip to: 13726 -/* 12132 */ MCD_OPC_Decode, 208, 11, 206, 1, // Opcode: SHRA_QB -/* 12137 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 12150 -/* 12141 */ MCD_OPC_CheckPredicate, 30, 45, 6, // Skip to: 13726 -/* 12145 */ MCD_OPC_Decode, 210, 11, 206, 1, // Opcode: SHRA_R_QB -/* 12150 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 12163 -/* 12154 */ MCD_OPC_CheckPredicate, 30, 32, 6, // Skip to: 13726 -/* 12158 */ MCD_OPC_Decode, 203, 11, 207, 1, // Opcode: SHRAV_QB -/* 12163 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 12176 -/* 12167 */ MCD_OPC_CheckPredicate, 30, 19, 6, // Skip to: 13726 -/* 12171 */ MCD_OPC_Decode, 205, 11, 207, 1, // Opcode: SHRAV_R_QB -/* 12176 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 12189 -/* 12180 */ MCD_OPC_CheckPredicate, 12, 6, 6, // Skip to: 13726 -/* 12184 */ MCD_OPC_Decode, 198, 11, 206, 1, // Opcode: SHLL_PH -/* 12189 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12202 -/* 12193 */ MCD_OPC_CheckPredicate, 12, 249, 5, // Skip to: 13726 -/* 12197 */ MCD_OPC_Decode, 207, 11, 206, 1, // Opcode: SHRA_PH -/* 12202 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 12215 -/* 12206 */ MCD_OPC_CheckPredicate, 12, 236, 5, // Skip to: 13726 -/* 12210 */ MCD_OPC_Decode, 194, 11, 207, 1, // Opcode: SHLLV_PH -/* 12215 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12228 -/* 12219 */ MCD_OPC_CheckPredicate, 12, 223, 5, // Skip to: 13726 -/* 12223 */ MCD_OPC_Decode, 202, 11, 207, 1, // Opcode: SHRAV_PH -/* 12228 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12241 -/* 12232 */ MCD_OPC_CheckPredicate, 12, 210, 5, // Skip to: 13726 -/* 12236 */ MCD_OPC_Decode, 200, 11, 206, 1, // Opcode: SHLL_S_PH -/* 12241 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 12254 -/* 12245 */ MCD_OPC_CheckPredicate, 12, 197, 5, // Skip to: 13726 -/* 12249 */ MCD_OPC_Decode, 209, 11, 206, 1, // Opcode: SHRA_R_PH -/* 12254 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12267 -/* 12258 */ MCD_OPC_CheckPredicate, 12, 184, 5, // Skip to: 13726 -/* 12262 */ MCD_OPC_Decode, 196, 11, 207, 1, // Opcode: SHLLV_S_PH -/* 12267 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 12280 -/* 12271 */ MCD_OPC_CheckPredicate, 12, 171, 5, // Skip to: 13726 -/* 12275 */ MCD_OPC_Decode, 204, 11, 207, 1, // Opcode: SHRAV_R_PH -/* 12280 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 12293 -/* 12284 */ MCD_OPC_CheckPredicate, 12, 158, 5, // Skip to: 13726 -/* 12288 */ MCD_OPC_Decode, 201, 11, 208, 1, // Opcode: SHLL_S_W -/* 12293 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 12306 -/* 12297 */ MCD_OPC_CheckPredicate, 12, 145, 5, // Skip to: 13726 -/* 12301 */ MCD_OPC_Decode, 211, 11, 208, 1, // Opcode: SHRA_R_W -/* 12306 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12318 -/* 12310 */ MCD_OPC_CheckPredicate, 12, 132, 5, // Skip to: 13726 -/* 12314 */ MCD_OPC_Decode, 197, 11, 36, // Opcode: SHLLV_S_W -/* 12318 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 12330 -/* 12322 */ MCD_OPC_CheckPredicate, 12, 120, 5, // Skip to: 13726 -/* 12326 */ MCD_OPC_Decode, 206, 11, 36, // Opcode: SHRAV_R_W -/* 12330 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 12343 -/* 12334 */ MCD_OPC_CheckPredicate, 30, 108, 5, // Skip to: 13726 -/* 12338 */ MCD_OPC_Decode, 214, 11, 206, 1, // Opcode: SHRL_PH -/* 12343 */ MCD_OPC_FilterValue, 27, 99, 5, // Skip to: 13726 -/* 12347 */ MCD_OPC_CheckPredicate, 30, 95, 5, // Skip to: 13726 -/* 12351 */ MCD_OPC_Decode, 212, 11, 207, 1, // Opcode: SHRLV_PH -/* 12356 */ MCD_OPC_FilterValue, 24, 199, 0, // Skip to: 12559 -/* 12360 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12363 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12375 -/* 12367 */ MCD_OPC_CheckPredicate, 30, 75, 5, // Skip to: 13726 -/* 12371 */ MCD_OPC_Decode, 53, 195, 1, // Opcode: ADDUH_QB -/* 12375 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12388 -/* 12379 */ MCD_OPC_CheckPredicate, 30, 63, 5, // Skip to: 13726 -/* 12383 */ MCD_OPC_Decode, 215, 12, 195, 1, // Opcode: SUBUH_QB -/* 12388 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12400 -/* 12392 */ MCD_OPC_CheckPredicate, 30, 50, 5, // Skip to: 13726 -/* 12396 */ MCD_OPC_Decode, 54, 195, 1, // Opcode: ADDUH_R_QB -/* 12400 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12413 -/* 12404 */ MCD_OPC_CheckPredicate, 30, 38, 5, // Skip to: 13726 -/* 12408 */ MCD_OPC_Decode, 216, 12, 195, 1, // Opcode: SUBUH_R_QB -/* 12413 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12425 -/* 12417 */ MCD_OPC_CheckPredicate, 30, 25, 5, // Skip to: 13726 -/* 12421 */ MCD_OPC_Decode, 32, 195, 1, // Opcode: ADDQH_PH -/* 12425 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12438 -/* 12429 */ MCD_OPC_CheckPredicate, 30, 13, 5, // Skip to: 13726 -/* 12433 */ MCD_OPC_Decode, 191, 12, 195, 1, // Opcode: SUBQH_PH -/* 12438 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12450 -/* 12442 */ MCD_OPC_CheckPredicate, 30, 0, 5, // Skip to: 13726 -/* 12446 */ MCD_OPC_Decode, 33, 195, 1, // Opcode: ADDQH_R_PH -/* 12450 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12463 -/* 12454 */ MCD_OPC_CheckPredicate, 30, 244, 4, // Skip to: 13726 -/* 12458 */ MCD_OPC_Decode, 192, 12, 195, 1, // Opcode: SUBQH_R_PH -/* 12463 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12476 -/* 12467 */ MCD_OPC_CheckPredicate, 30, 231, 4, // Skip to: 13726 -/* 12471 */ MCD_OPC_Decode, 218, 9, 195, 1, // Opcode: MUL_PH -/* 12476 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12489 -/* 12480 */ MCD_OPC_CheckPredicate, 30, 218, 4, // Skip to: 13726 -/* 12484 */ MCD_OPC_Decode, 222, 9, 195, 1, // Opcode: MUL_S_PH -/* 12489 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 12500 -/* 12493 */ MCD_OPC_CheckPredicate, 30, 205, 4, // Skip to: 13726 -/* 12497 */ MCD_OPC_Decode, 35, 35, // Opcode: ADDQH_W -/* 12500 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 12512 -/* 12504 */ MCD_OPC_CheckPredicate, 30, 194, 4, // Skip to: 13726 -/* 12508 */ MCD_OPC_Decode, 194, 12, 35, // Opcode: SUBQH_W -/* 12512 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 12523 -/* 12516 */ MCD_OPC_CheckPredicate, 30, 182, 4, // Skip to: 13726 -/* 12520 */ MCD_OPC_Decode, 34, 35, // Opcode: ADDQH_R_W -/* 12523 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 12535 -/* 12527 */ MCD_OPC_CheckPredicate, 30, 171, 4, // Skip to: 13726 -/* 12531 */ MCD_OPC_Decode, 193, 12, 35, // Opcode: SUBQH_R_W -/* 12535 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12547 -/* 12539 */ MCD_OPC_CheckPredicate, 30, 159, 4, // Skip to: 13726 -/* 12543 */ MCD_OPC_Decode, 201, 9, 35, // Opcode: MULQ_S_W -/* 12547 */ MCD_OPC_FilterValue, 23, 151, 4, // Skip to: 13726 -/* 12551 */ MCD_OPC_CheckPredicate, 30, 147, 4, // Skip to: 13726 -/* 12555 */ MCD_OPC_Decode, 199, 9, 35, // Opcode: MULQ_RS_W -/* 12559 */ MCD_OPC_FilterValue, 32, 60, 0, // Skip to: 12623 -/* 12563 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12566 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 12585 -/* 12570 */ MCD_OPC_CheckPredicate, 6, 128, 4, // Skip to: 13726 -/* 12574 */ MCD_OPC_CheckField, 21, 5, 0, 122, 4, // Skip to: 13726 -/* 12580 */ MCD_OPC_Decode, 234, 13, 205, 1, // Opcode: WSBH -/* 12585 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 12604 -/* 12589 */ MCD_OPC_CheckPredicate, 6, 109, 4, // Skip to: 13726 -/* 12593 */ MCD_OPC_CheckField, 21, 5, 0, 103, 4, // Skip to: 13726 -/* 12599 */ MCD_OPC_Decode, 168, 11, 205, 1, // Opcode: SEB -/* 12604 */ MCD_OPC_FilterValue, 24, 94, 4, // Skip to: 13726 -/* 12608 */ MCD_OPC_CheckPredicate, 6, 90, 4, // Skip to: 13726 -/* 12612 */ MCD_OPC_CheckField, 21, 5, 0, 84, 4, // Skip to: 13726 -/* 12618 */ MCD_OPC_Decode, 171, 11, 205, 1, // Opcode: SEH -/* 12623 */ MCD_OPC_FilterValue, 48, 143, 1, // Skip to: 13026 -/* 12627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12630 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12648 -/* 12634 */ MCD_OPC_CheckPredicate, 30, 64, 4, // Skip to: 13726 -/* 12638 */ MCD_OPC_CheckField, 13, 3, 0, 58, 4, // Skip to: 13726 -/* 12644 */ MCD_OPC_Decode, 230, 4, 116, // Opcode: DPA_W_PH -/* 12648 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12666 -/* 12652 */ MCD_OPC_CheckPredicate, 30, 46, 4, // Skip to: 13726 -/* 12656 */ MCD_OPC_CheckField, 13, 3, 0, 40, 4, // Skip to: 13726 -/* 12662 */ MCD_OPC_Decode, 245, 4, 116, // Opcode: DPS_W_PH -/* 12666 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12684 -/* 12670 */ MCD_OPC_CheckPredicate, 30, 28, 4, // Skip to: 13726 -/* 12674 */ MCD_OPC_CheckField, 13, 3, 0, 22, 4, // Skip to: 13726 -/* 12680 */ MCD_OPC_Decode, 205, 9, 116, // Opcode: MULSA_W_PH -/* 12684 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12702 -/* 12688 */ MCD_OPC_CheckPredicate, 12, 10, 4, // Skip to: 13726 -/* 12692 */ MCD_OPC_CheckField, 13, 3, 0, 4, 4, // Skip to: 13726 -/* 12698 */ MCD_OPC_Decode, 227, 4, 116, // Opcode: DPAU_H_QBL -/* 12702 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12720 -/* 12706 */ MCD_OPC_CheckPredicate, 12, 248, 3, // Skip to: 13726 -/* 12710 */ MCD_OPC_CheckField, 13, 3, 0, 242, 3, // Skip to: 13726 -/* 12716 */ MCD_OPC_Decode, 226, 4, 116, // Opcode: DPAQ_S_W_PH -/* 12720 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12738 -/* 12724 */ MCD_OPC_CheckPredicate, 12, 230, 3, // Skip to: 13726 -/* 12728 */ MCD_OPC_CheckField, 13, 3, 0, 224, 3, // Skip to: 13726 -/* 12734 */ MCD_OPC_Decode, 235, 4, 116, // Opcode: DPSQ_S_W_PH -/* 12738 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 12756 -/* 12742 */ MCD_OPC_CheckPredicate, 12, 212, 3, // Skip to: 13726 -/* 12746 */ MCD_OPC_CheckField, 13, 3, 0, 206, 3, // Skip to: 13726 -/* 12752 */ MCD_OPC_Decode, 204, 9, 116, // Opcode: MULSAQ_S_W_PH -/* 12756 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 12774 -/* 12760 */ MCD_OPC_CheckPredicate, 12, 194, 3, // Skip to: 13726 -/* 12764 */ MCD_OPC_CheckField, 13, 3, 0, 188, 3, // Skip to: 13726 -/* 12770 */ MCD_OPC_Decode, 228, 4, 116, // Opcode: DPAU_H_QBR -/* 12774 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12792 -/* 12778 */ MCD_OPC_CheckPredicate, 30, 176, 3, // Skip to: 13726 -/* 12782 */ MCD_OPC_CheckField, 13, 3, 0, 170, 3, // Skip to: 13726 -/* 12788 */ MCD_OPC_Decode, 229, 4, 116, // Opcode: DPAX_W_PH -/* 12792 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 12810 -/* 12796 */ MCD_OPC_CheckPredicate, 30, 158, 3, // Skip to: 13726 -/* 12800 */ MCD_OPC_CheckField, 13, 3, 0, 152, 3, // Skip to: 13726 -/* 12806 */ MCD_OPC_Decode, 244, 4, 116, // Opcode: DPSX_W_PH -/* 12810 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12828 -/* 12814 */ MCD_OPC_CheckPredicate, 12, 140, 3, // Skip to: 13726 -/* 12818 */ MCD_OPC_CheckField, 13, 3, 0, 134, 3, // Skip to: 13726 -/* 12824 */ MCD_OPC_Decode, 242, 4, 116, // Opcode: DPSU_H_QBL -/* 12828 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12846 -/* 12832 */ MCD_OPC_CheckPredicate, 12, 122, 3, // Skip to: 13726 -/* 12836 */ MCD_OPC_CheckField, 13, 3, 0, 116, 3, // Skip to: 13726 -/* 12842 */ MCD_OPC_Decode, 225, 4, 116, // Opcode: DPAQ_SA_L_W -/* 12846 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12864 -/* 12850 */ MCD_OPC_CheckPredicate, 12, 104, 3, // Skip to: 13726 -/* 12854 */ MCD_OPC_CheckField, 13, 3, 0, 98, 3, // Skip to: 13726 -/* 12860 */ MCD_OPC_Decode, 234, 4, 116, // Opcode: DPSQ_SA_L_W -/* 12864 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 12882 -/* 12868 */ MCD_OPC_CheckPredicate, 12, 86, 3, // Skip to: 13726 -/* 12872 */ MCD_OPC_CheckField, 13, 3, 0, 80, 3, // Skip to: 13726 -/* 12878 */ MCD_OPC_Decode, 243, 4, 116, // Opcode: DPSU_H_QBR -/* 12882 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 12900 -/* 12886 */ MCD_OPC_CheckPredicate, 12, 68, 3, // Skip to: 13726 -/* 12890 */ MCD_OPC_CheckField, 13, 3, 0, 62, 3, // Skip to: 13726 -/* 12896 */ MCD_OPC_Decode, 151, 8, 116, // Opcode: MAQ_SA_W_PHL -/* 12900 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 12918 -/* 12904 */ MCD_OPC_CheckPredicate, 12, 50, 3, // Skip to: 13726 -/* 12908 */ MCD_OPC_CheckField, 13, 3, 0, 44, 3, // Skip to: 13726 -/* 12914 */ MCD_OPC_Decode, 152, 8, 116, // Opcode: MAQ_SA_W_PHR -/* 12918 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 12936 -/* 12922 */ MCD_OPC_CheckPredicate, 12, 32, 3, // Skip to: 13726 -/* 12926 */ MCD_OPC_CheckField, 13, 3, 0, 26, 3, // Skip to: 13726 -/* 12932 */ MCD_OPC_Decode, 153, 8, 116, // Opcode: MAQ_S_W_PHL -/* 12936 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 12954 -/* 12940 */ MCD_OPC_CheckPredicate, 12, 14, 3, // Skip to: 13726 -/* 12944 */ MCD_OPC_CheckField, 13, 3, 0, 8, 3, // Skip to: 13726 -/* 12950 */ MCD_OPC_Decode, 154, 8, 116, // Opcode: MAQ_S_W_PHR -/* 12954 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 12972 -/* 12958 */ MCD_OPC_CheckPredicate, 30, 252, 2, // Skip to: 13726 -/* 12962 */ MCD_OPC_CheckField, 13, 3, 0, 246, 2, // Skip to: 13726 -/* 12968 */ MCD_OPC_Decode, 224, 4, 116, // Opcode: DPAQX_S_W_PH -/* 12972 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 12990 -/* 12976 */ MCD_OPC_CheckPredicate, 30, 234, 2, // Skip to: 13726 -/* 12980 */ MCD_OPC_CheckField, 13, 3, 0, 228, 2, // Skip to: 13726 -/* 12986 */ MCD_OPC_Decode, 233, 4, 116, // Opcode: DPSQX_S_W_PH -/* 12990 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 13008 -/* 12994 */ MCD_OPC_CheckPredicate, 30, 216, 2, // Skip to: 13726 -/* 12998 */ MCD_OPC_CheckField, 13, 3, 0, 210, 2, // Skip to: 13726 -/* 13004 */ MCD_OPC_Decode, 223, 4, 116, // Opcode: DPAQX_SA_W_PH -/* 13008 */ MCD_OPC_FilterValue, 27, 202, 2, // Skip to: 13726 -/* 13012 */ MCD_OPC_CheckPredicate, 30, 198, 2, // Skip to: 13726 -/* 13016 */ MCD_OPC_CheckField, 13, 3, 0, 192, 2, // Skip to: 13726 -/* 13022 */ MCD_OPC_Decode, 232, 4, 116, // Opcode: DPSQX_SA_W_PH -/* 13026 */ MCD_OPC_FilterValue, 49, 41, 0, // Skip to: 13071 -/* 13030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 13033 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13045 -/* 13037 */ MCD_OPC_CheckPredicate, 30, 173, 2, // Skip to: 13726 -/* 13041 */ MCD_OPC_Decode, 96, 209, 1, // Opcode: APPEND -/* 13045 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13058 -/* 13049 */ MCD_OPC_CheckPredicate, 30, 161, 2, // Skip to: 13726 -/* 13053 */ MCD_OPC_Decode, 184, 10, 209, 1, // Opcode: PREPEND -/* 13058 */ MCD_OPC_FilterValue, 16, 152, 2, // Skip to: 13726 -/* 13062 */ MCD_OPC_CheckPredicate, 30, 148, 2, // Skip to: 13726 -/* 13066 */ MCD_OPC_Decode, 169, 1, 209, 1, // Opcode: BALIGN -/* 13071 */ MCD_OPC_FilterValue, 56, 58, 1, // Skip to: 13389 -/* 13075 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 13078 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13097 -/* 13082 */ MCD_OPC_CheckPredicate, 12, 128, 2, // Skip to: 13726 -/* 13086 */ MCD_OPC_CheckField, 13, 3, 0, 122, 2, // Skip to: 13726 -/* 13092 */ MCD_OPC_Decode, 157, 5, 210, 1, // Opcode: EXTR_W -/* 13097 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 13116 -/* 13101 */ MCD_OPC_CheckPredicate, 12, 109, 2, // Skip to: 13726 -/* 13105 */ MCD_OPC_CheckField, 13, 3, 0, 103, 2, // Skip to: 13726 -/* 13111 */ MCD_OPC_Decode, 153, 5, 211, 1, // Opcode: EXTRV_W -/* 13116 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 13135 -/* 13120 */ MCD_OPC_CheckPredicate, 12, 90, 2, // Skip to: 13726 -/* 13124 */ MCD_OPC_CheckField, 13, 3, 0, 84, 2, // Skip to: 13726 -/* 13130 */ MCD_OPC_Decode, 146, 5, 210, 1, // Opcode: EXTP -/* 13135 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 13154 -/* 13139 */ MCD_OPC_CheckPredicate, 12, 71, 2, // Skip to: 13726 -/* 13143 */ MCD_OPC_CheckField, 13, 3, 0, 65, 2, // Skip to: 13726 -/* 13149 */ MCD_OPC_Decode, 149, 5, 211, 1, // Opcode: EXTPV -/* 13154 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 13173 -/* 13158 */ MCD_OPC_CheckPredicate, 12, 52, 2, // Skip to: 13726 -/* 13162 */ MCD_OPC_CheckField, 13, 3, 0, 46, 2, // Skip to: 13726 -/* 13168 */ MCD_OPC_Decode, 155, 5, 210, 1, // Opcode: EXTR_R_W -/* 13173 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 13192 -/* 13177 */ MCD_OPC_CheckPredicate, 12, 33, 2, // Skip to: 13726 -/* 13181 */ MCD_OPC_CheckField, 13, 3, 0, 27, 2, // Skip to: 13726 -/* 13187 */ MCD_OPC_Decode, 151, 5, 211, 1, // Opcode: EXTRV_R_W -/* 13192 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 13211 -/* 13196 */ MCD_OPC_CheckPredicate, 12, 14, 2, // Skip to: 13726 -/* 13200 */ MCD_OPC_CheckField, 13, 3, 0, 8, 2, // Skip to: 13726 -/* 13206 */ MCD_OPC_Decode, 154, 5, 210, 1, // Opcode: EXTR_RS_W -/* 13211 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 13230 -/* 13215 */ MCD_OPC_CheckPredicate, 12, 251, 1, // Skip to: 13726 -/* 13219 */ MCD_OPC_CheckField, 13, 3, 0, 245, 1, // Skip to: 13726 -/* 13225 */ MCD_OPC_Decode, 150, 5, 211, 1, // Opcode: EXTRV_RS_W -/* 13230 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 13249 -/* 13234 */ MCD_OPC_CheckPredicate, 12, 232, 1, // Skip to: 13726 -/* 13238 */ MCD_OPC_CheckField, 13, 3, 0, 226, 1, // Skip to: 13726 -/* 13244 */ MCD_OPC_Decode, 147, 5, 210, 1, // Opcode: EXTPDP -/* 13249 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 13268 -/* 13253 */ MCD_OPC_CheckPredicate, 12, 213, 1, // Skip to: 13726 -/* 13257 */ MCD_OPC_CheckField, 13, 3, 0, 207, 1, // Skip to: 13726 -/* 13263 */ MCD_OPC_Decode, 148, 5, 211, 1, // Opcode: EXTPDPV -/* 13268 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 13287 -/* 13272 */ MCD_OPC_CheckPredicate, 12, 194, 1, // Skip to: 13726 -/* 13276 */ MCD_OPC_CheckField, 13, 3, 0, 188, 1, // Skip to: 13726 -/* 13282 */ MCD_OPC_Decode, 156, 5, 210, 1, // Opcode: EXTR_S_H -/* 13287 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 13306 -/* 13291 */ MCD_OPC_CheckPredicate, 12, 175, 1, // Skip to: 13726 -/* 13295 */ MCD_OPC_CheckField, 13, 3, 0, 169, 1, // Skip to: 13726 -/* 13301 */ MCD_OPC_Decode, 152, 5, 211, 1, // Opcode: EXTRV_S_H -/* 13306 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 13319 -/* 13310 */ MCD_OPC_CheckPredicate, 12, 156, 1, // Skip to: 13726 -/* 13314 */ MCD_OPC_Decode, 237, 10, 212, 1, // Opcode: RDDSP -/* 13319 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 13332 -/* 13323 */ MCD_OPC_CheckPredicate, 12, 143, 1, // Skip to: 13726 -/* 13327 */ MCD_OPC_Decode, 233, 13, 213, 1, // Opcode: WRDSP -/* 13332 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 13351 -/* 13336 */ MCD_OPC_CheckPredicate, 12, 130, 1, // Skip to: 13726 -/* 13340 */ MCD_OPC_CheckField, 13, 7, 0, 124, 1, // Skip to: 13726 -/* 13346 */ MCD_OPC_Decode, 192, 11, 214, 1, // Opcode: SHILO -/* 13351 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 13370 -/* 13355 */ MCD_OPC_CheckPredicate, 12, 111, 1, // Skip to: 13726 -/* 13359 */ MCD_OPC_CheckField, 13, 8, 0, 105, 1, // Skip to: 13726 -/* 13365 */ MCD_OPC_Decode, 193, 11, 215, 1, // Opcode: SHILOV -/* 13370 */ MCD_OPC_FilterValue, 31, 96, 1, // Skip to: 13726 -/* 13374 */ MCD_OPC_CheckPredicate, 12, 92, 1, // Skip to: 13726 -/* 13378 */ MCD_OPC_CheckField, 13, 8, 0, 86, 1, // Skip to: 13726 -/* 13384 */ MCD_OPC_Decode, 180, 9, 215, 1, // Opcode: MTHLIP -/* 13389 */ MCD_OPC_FilterValue, 59, 77, 1, // Skip to: 13726 -/* 13393 */ MCD_OPC_CheckPredicate, 5, 73, 1, // Skip to: 13726 -/* 13397 */ MCD_OPC_CheckField, 21, 5, 0, 67, 1, // Skip to: 13726 -/* 13403 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, // Skip to: 13726 -/* 13409 */ MCD_OPC_Decode, 238, 10, 216, 1, // Opcode: RDHWR -/* 13414 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 13427 -/* 13418 */ MCD_OPC_CheckPredicate, 5, 48, 1, // Skip to: 13726 -/* 13422 */ MCD_OPC_Decode, 153, 7, 217, 1, // Opcode: LB -/* 13427 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 13440 -/* 13431 */ MCD_OPC_CheckPredicate, 5, 35, 1, // Skip to: 13726 -/* 13435 */ MCD_OPC_Decode, 184, 7, 217, 1, // Opcode: LH -/* 13440 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 13453 -/* 13444 */ MCD_OPC_CheckPredicate, 11, 22, 1, // Skip to: 13726 -/* 13448 */ MCD_OPC_Decode, 222, 7, 217, 1, // Opcode: LWL -/* 13453 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 13466 -/* 13457 */ MCD_OPC_CheckPredicate, 1, 9, 1, // Skip to: 13726 -/* 13461 */ MCD_OPC_Decode, 213, 7, 217, 1, // Opcode: LW -/* 13466 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 13479 -/* 13470 */ MCD_OPC_CheckPredicate, 5, 252, 0, // Skip to: 13726 -/* 13474 */ MCD_OPC_Decode, 158, 7, 217, 1, // Opcode: LBu -/* 13479 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 13492 -/* 13483 */ MCD_OPC_CheckPredicate, 5, 239, 0, // Skip to: 13726 -/* 13487 */ MCD_OPC_Decode, 189, 7, 217, 1, // Opcode: LHu -/* 13492 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 13505 -/* 13496 */ MCD_OPC_CheckPredicate, 11, 226, 0, // Skip to: 13726 -/* 13500 */ MCD_OPC_Decode, 230, 7, 217, 1, // Opcode: LWR -/* 13505 */ MCD_OPC_FilterValue, 40, 9, 0, // Skip to: 13518 -/* 13509 */ MCD_OPC_CheckPredicate, 5, 213, 0, // Skip to: 13726 -/* 13513 */ MCD_OPC_Decode, 142, 11, 217, 1, // Opcode: SB -/* 13518 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 13531 -/* 13522 */ MCD_OPC_CheckPredicate, 5, 200, 0, // Skip to: 13726 -/* 13526 */ MCD_OPC_Decode, 186, 11, 217, 1, // Opcode: SH -/* 13531 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 13544 -/* 13535 */ MCD_OPC_CheckPredicate, 11, 187, 0, // Skip to: 13726 -/* 13539 */ MCD_OPC_Decode, 243, 12, 217, 1, // Opcode: SWL -/* 13544 */ MCD_OPC_FilterValue, 43, 9, 0, // Skip to: 13557 -/* 13548 */ MCD_OPC_CheckPredicate, 1, 174, 0, // Skip to: 13726 -/* 13552 */ MCD_OPC_Decode, 235, 12, 217, 1, // Opcode: SW -/* 13557 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 13570 -/* 13561 */ MCD_OPC_CheckPredicate, 11, 161, 0, // Skip to: 13726 -/* 13565 */ MCD_OPC_Decode, 250, 12, 217, 1, // Opcode: SWR -/* 13570 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 13583 -/* 13574 */ MCD_OPC_CheckPredicate, 31, 148, 0, // Skip to: 13726 -/* 13578 */ MCD_OPC_Decode, 220, 2, 218, 1, // Opcode: CACHE -/* 13583 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 13596 -/* 13587 */ MCD_OPC_CheckPredicate, 32, 135, 0, // Skip to: 13726 -/* 13591 */ MCD_OPC_Decode, 193, 7, 217, 1, // Opcode: LL -/* 13596 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 13609 -/* 13600 */ MCD_OPC_CheckPredicate, 5, 122, 0, // Skip to: 13726 -/* 13604 */ MCD_OPC_Decode, 216, 7, 219, 1, // Opcode: LWC1 -/* 13609 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 13622 -/* 13613 */ MCD_OPC_CheckPredicate, 33, 109, 0, // Skip to: 13726 -/* 13617 */ MCD_OPC_Decode, 218, 7, 220, 1, // Opcode: LWC2 -/* 13622 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 13635 -/* 13626 */ MCD_OPC_CheckPredicate, 31, 96, 0, // Skip to: 13726 -/* 13630 */ MCD_OPC_Decode, 181, 10, 218, 1, // Opcode: PREF -/* 13635 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 13648 -/* 13639 */ MCD_OPC_CheckPredicate, 34, 83, 0, // Skip to: 13726 -/* 13643 */ MCD_OPC_Decode, 162, 7, 219, 1, // Opcode: LDC1 -/* 13648 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 13661 -/* 13652 */ MCD_OPC_CheckPredicate, 35, 70, 0, // Skip to: 13726 -/* 13656 */ MCD_OPC_Decode, 165, 7, 220, 1, // Opcode: LDC2 -/* 13661 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 13674 -/* 13665 */ MCD_OPC_CheckPredicate, 32, 57, 0, // Skip to: 13726 -/* 13669 */ MCD_OPC_Decode, 146, 11, 217, 1, // Opcode: SC -/* 13674 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 13687 -/* 13678 */ MCD_OPC_CheckPredicate, 5, 44, 0, // Skip to: 13726 -/* 13682 */ MCD_OPC_Decode, 238, 12, 219, 1, // Opcode: SWC1 -/* 13687 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 13700 -/* 13691 */ MCD_OPC_CheckPredicate, 33, 31, 0, // Skip to: 13726 -/* 13695 */ MCD_OPC_Decode, 240, 12, 220, 1, // Opcode: SWC2 -/* 13700 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 13713 -/* 13704 */ MCD_OPC_CheckPredicate, 34, 18, 0, // Skip to: 13726 -/* 13708 */ MCD_OPC_Decode, 156, 11, 219, 1, // Opcode: SDC1 -/* 13713 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 13726 -/* 13717 */ MCD_OPC_CheckPredicate, 35, 5, 0, // Skip to: 13726 -/* 13721 */ MCD_OPC_Decode, 159, 11, 220, 1, // Opcode: SDC2 -/* 13726 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 101, + 4, + 0, // Skip to: 1133 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 79 + /* 16 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 29, + 67, + 0, // Skip to: 17205 + /* 24 */ MCD_OPC_ExtractField, + 6, + 15, // Inst{20-6} ... + /* 27 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 41 + /* 32 */ MCD_OPC_CheckPredicate, + 27, + 32, + 0, + 0, // Skip to: 69 + /* 37 */ MCD_OPC_Decode, + 193, + 20, + 0, // Opcode: SSNOP + /* 41 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 55 + /* 46 */ MCD_OPC_CheckPredicate, + 27, + 18, + 0, + 0, // Skip to: 69 + /* 51 */ MCD_OPC_Decode, + 222, + 11, + 0, // Opcode: EHB + /* 55 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 69 + /* 60 */ MCD_OPC_CheckPredicate, + 28, + 4, + 0, + 0, // Skip to: 69 + /* 65 */ MCD_OPC_Decode, + 235, + 17, + 0, // Opcode: PAUSE + /* 69 */ MCD_OPC_CheckPredicate, + 27, + 235, + 66, + 0, // Skip to: 17205 + /* 74 */ MCD_OPC_Decode, + 240, + 19, + 172, + 1, // Opcode: SLL + /* 79 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 131 + /* 84 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 87 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 109 + /* 92 */ MCD_OPC_CheckPredicate, + 29, + 212, + 66, + 0, // Skip to: 17205 + /* 97 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 205, + 66, + 0, // Skip to: 17205 + /* 104 */ MCD_OPC_Decode, + 165, + 16, + 173, + 1, // Opcode: MOVF_I + /* 109 */ MCD_OPC_FilterValue, + 1, + 195, + 66, + 0, // Skip to: 17205 + /* 114 */ MCD_OPC_CheckPredicate, + 29, + 190, + 66, + 0, // Skip to: 17205 + /* 119 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 183, + 66, + 0, // Skip to: 17205 + /* 126 */ MCD_OPC_Decode, + 185, + 16, + 173, + 1, // Opcode: MOVT_I + /* 131 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 169 + /* 136 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 139 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 154 + /* 144 */ MCD_OPC_CheckPredicate, + 27, + 160, + 66, + 0, // Skip to: 17205 + /* 149 */ MCD_OPC_Decode, + 171, + 20, + 172, + 1, // Opcode: SRL + /* 154 */ MCD_OPC_FilterValue, + 1, + 150, + 66, + 0, // Skip to: 17205 + /* 159 */ MCD_OPC_CheckPredicate, + 28, + 145, + 66, + 0, // Skip to: 17205 + /* 164 */ MCD_OPC_Decode, + 201, + 18, + 172, + 1, // Opcode: ROTR + /* 169 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 191 + /* 174 */ MCD_OPC_CheckPredicate, + 27, + 130, + 66, + 0, // Skip to: 17205 + /* 179 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 123, + 66, + 0, // Skip to: 17205 + /* 186 */ MCD_OPC_Decode, + 151, + 20, + 172, + 1, // Opcode: SRA + /* 191 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 212 + /* 196 */ MCD_OPC_CheckPredicate, + 27, + 108, + 66, + 0, // Skip to: 17205 + /* 201 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 101, + 66, + 0, // Skip to: 17205 + /* 208 */ MCD_OPC_Decode, + 249, + 19, + 44, // Opcode: SLLV + /* 212 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 234 + /* 217 */ MCD_OPC_CheckPredicate, + 30, + 87, + 66, + 0, // Skip to: 17205 + /* 222 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 80, + 66, + 0, // Skip to: 17205 + /* 229 */ MCD_OPC_Decode, + 217, + 14, + 174, + 1, // Opcode: LSA + /* 234 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 270 + /* 239 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 242 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 256 + /* 247 */ MCD_OPC_CheckPredicate, + 27, + 57, + 66, + 0, // Skip to: 17205 + /* 252 */ MCD_OPC_Decode, + 186, + 20, + 44, // Opcode: SRLV + /* 256 */ MCD_OPC_FilterValue, + 1, + 48, + 66, + 0, // Skip to: 17205 + /* 261 */ MCD_OPC_CheckPredicate, + 28, + 43, + 66, + 0, // Skip to: 17205 + /* 266 */ MCD_OPC_Decode, + 202, + 18, + 44, // Opcode: ROTRV + /* 270 */ MCD_OPC_FilterValue, + 7, + 16, + 0, + 0, // Skip to: 291 + /* 275 */ MCD_OPC_CheckPredicate, + 27, + 29, + 66, + 0, // Skip to: 17205 + /* 280 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 22, + 66, + 0, // Skip to: 17205 + /* 287 */ MCD_OPC_Decode, + 164, + 20, + 44, // Opcode: SRAV + /* 291 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 329 + /* 296 */ MCD_OPC_ExtractField, + 6, + 15, // Inst{20-6} ... + /* 299 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 314 + /* 304 */ MCD_OPC_CheckPredicate, + 31, + 0, + 66, + 0, // Skip to: 17205 + /* 309 */ MCD_OPC_Decode, + 133, + 14, + 175, + 1, // Opcode: JR + /* 314 */ MCD_OPC_FilterValue, + 16, + 246, + 65, + 0, // Skip to: 17205 + /* 319 */ MCD_OPC_CheckPredicate, + 32, + 241, + 65, + 0, // Skip to: 17205 + /* 324 */ MCD_OPC_Decode, + 140, + 14, + 175, + 1, // Opcode: JR_HB + /* 329 */ MCD_OPC_FilterValue, + 9, + 45, + 0, + 0, // Skip to: 379 + /* 334 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 337 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 358 + /* 342 */ MCD_OPC_CheckPredicate, + 33, + 218, + 65, + 0, // Skip to: 17205 + /* 347 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 211, + 65, + 0, // Skip to: 17205 + /* 354 */ MCD_OPC_Decode, + 240, + 13, + 14, // Opcode: JALR + /* 358 */ MCD_OPC_FilterValue, + 16, + 202, + 65, + 0, // Skip to: 17205 + /* 363 */ MCD_OPC_CheckPredicate, + 34, + 197, + 65, + 0, // Skip to: 17205 + /* 368 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 190, + 65, + 0, // Skip to: 17205 + /* 375 */ MCD_OPC_Decode, + 248, + 13, + 14, // Opcode: JALR_HB + /* 379 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 401 + /* 384 */ MCD_OPC_CheckPredicate, + 35, + 176, + 65, + 0, // Skip to: 17205 + /* 389 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 169, + 65, + 0, // Skip to: 17205 + /* 396 */ MCD_OPC_Decode, + 197, + 16, + 176, + 1, // Opcode: MOVZ_I_I + /* 401 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 423 + /* 406 */ MCD_OPC_CheckPredicate, + 35, + 154, + 65, + 0, // Skip to: 17205 + /* 411 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 147, + 65, + 0, // Skip to: 17205 + /* 418 */ MCD_OPC_Decode, + 177, + 16, + 176, + 1, // Opcode: MOVN_I_I + /* 423 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 438 + /* 428 */ MCD_OPC_CheckPredicate, + 27, + 132, + 65, + 0, // Skip to: 17205 + /* 433 */ MCD_OPC_Decode, + 173, + 21, + 177, + 1, // Opcode: SYSCALL + /* 438 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 452 + /* 443 */ MCD_OPC_CheckPredicate, + 27, + 117, + 65, + 0, // Skip to: 17205 + /* 448 */ MCD_OPC_Decode, + 246, + 7, + 45, // Opcode: BREAK + /* 452 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 467 + /* 457 */ MCD_OPC_CheckPredicate, + 36, + 103, + 65, + 0, // Skip to: 17205 + /* 462 */ MCD_OPC_Decode, + 167, + 21, + 178, + 1, // Opcode: SYNC + /* 467 */ MCD_OPC_FilterValue, + 16, + 51, + 0, + 0, // Skip to: 523 + /* 472 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 475 */ MCD_OPC_FilterValue, + 0, + 85, + 65, + 0, // Skip to: 17205 + /* 480 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 483 */ MCD_OPC_FilterValue, + 0, + 77, + 65, + 0, // Skip to: 17205 + /* 488 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 491 */ MCD_OPC_FilterValue, + 0, + 69, + 65, + 0, // Skip to: 17205 + /* 496 */ MCD_OPC_CheckPredicate, + 31, + 12, + 0, + 0, // Skip to: 513 + /* 501 */ MCD_OPC_CheckField, + 21, + 2, + 0, + 5, + 0, + 0, // Skip to: 513 + /* 508 */ MCD_OPC_Decode, + 230, + 15, + 179, + 1, // Opcode: MFHI + /* 513 */ MCD_OPC_CheckPredicate, + 37, + 47, + 65, + 0, // Skip to: 17205 + /* 518 */ MCD_OPC_Decode, + 233, + 15, + 180, + 1, // Opcode: MFHI_DSP + /* 523 */ MCD_OPC_FilterValue, + 17, + 43, + 0, + 0, // Skip to: 571 + /* 528 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 531 */ MCD_OPC_FilterValue, + 0, + 29, + 65, + 0, // Skip to: 17205 + /* 536 */ MCD_OPC_ExtractField, + 13, + 8, // Inst{20-13} ... + /* 539 */ MCD_OPC_FilterValue, + 0, + 21, + 65, + 0, // Skip to: 17205 + /* 544 */ MCD_OPC_CheckPredicate, + 31, + 12, + 0, + 0, // Skip to: 561 + /* 549 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 5, + 0, + 0, // Skip to: 561 + /* 556 */ MCD_OPC_Decode, + 246, + 16, + 175, + 1, // Opcode: MTHI + /* 561 */ MCD_OPC_CheckPredicate, + 37, + 255, + 64, + 0, // Skip to: 17205 + /* 566 */ MCD_OPC_Decode, + 248, + 16, + 181, + 1, // Opcode: MTHI_DSP + /* 571 */ MCD_OPC_FilterValue, + 18, + 51, + 0, + 0, // Skip to: 627 + /* 576 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 579 */ MCD_OPC_FilterValue, + 0, + 237, + 64, + 0, // Skip to: 17205 + /* 584 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 587 */ MCD_OPC_FilterValue, + 0, + 229, + 64, + 0, // Skip to: 17205 + /* 592 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 595 */ MCD_OPC_FilterValue, + 0, + 221, + 64, + 0, // Skip to: 17205 + /* 600 */ MCD_OPC_CheckPredicate, + 31, + 12, + 0, + 0, // Skip to: 617 + /* 605 */ MCD_OPC_CheckField, + 21, + 2, + 0, + 5, + 0, + 0, // Skip to: 617 + /* 612 */ MCD_OPC_Decode, + 236, + 15, + 179, + 1, // Opcode: MFLO + /* 617 */ MCD_OPC_CheckPredicate, + 37, + 199, + 64, + 0, // Skip to: 17205 + /* 622 */ MCD_OPC_Decode, + 239, + 15, + 180, + 1, // Opcode: MFLO_DSP + /* 627 */ MCD_OPC_FilterValue, + 19, + 43, + 0, + 0, // Skip to: 675 + /* 632 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 635 */ MCD_OPC_FilterValue, + 0, + 181, + 64, + 0, // Skip to: 17205 + /* 640 */ MCD_OPC_ExtractField, + 13, + 8, // Inst{20-13} ... + /* 643 */ MCD_OPC_FilterValue, + 0, + 173, + 64, + 0, // Skip to: 17205 + /* 648 */ MCD_OPC_CheckPredicate, + 31, + 12, + 0, + 0, // Skip to: 665 + /* 653 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 5, + 0, + 0, // Skip to: 665 + /* 660 */ MCD_OPC_Decode, + 253, + 16, + 175, + 1, // Opcode: MTLO + /* 665 */ MCD_OPC_CheckPredicate, + 37, + 151, + 64, + 0, // Skip to: 17205 + /* 670 */ MCD_OPC_Decode, + 255, + 16, + 182, + 1, // Opcode: MTLO_DSP + /* 675 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 697 + /* 680 */ MCD_OPC_CheckPredicate, + 38, + 136, + 64, + 0, // Skip to: 17205 + /* 685 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 129, + 64, + 0, // Skip to: 17205 + /* 692 */ MCD_OPC_Decode, + 253, + 10, + 183, + 1, // Opcode: DLSA + /* 697 */ MCD_OPC_FilterValue, + 24, + 42, + 0, + 0, // Skip to: 744 + /* 702 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 705 */ MCD_OPC_FilterValue, + 0, + 111, + 64, + 0, // Skip to: 17205 + /* 710 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 713 */ MCD_OPC_FilterValue, + 0, + 103, + 64, + 0, // Skip to: 17205 + /* 718 */ MCD_OPC_CheckPredicate, + 31, + 11, + 0, + 0, // Skip to: 734 + /* 723 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 734 + /* 730 */ MCD_OPC_Decode, + 165, + 17, + 69, // Opcode: MULT + /* 734 */ MCD_OPC_CheckPredicate, + 37, + 82, + 64, + 0, // Skip to: 17205 + /* 739 */ MCD_OPC_Decode, + 168, + 17, + 184, + 1, // Opcode: MULT_DSP + /* 744 */ MCD_OPC_FilterValue, + 25, + 42, + 0, + 0, // Skip to: 791 + /* 749 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 752 */ MCD_OPC_FilterValue, + 0, + 64, + 64, + 0, // Skip to: 17205 + /* 757 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 760 */ MCD_OPC_FilterValue, + 0, + 56, + 64, + 0, // Skip to: 17205 + /* 765 */ MCD_OPC_CheckPredicate, + 31, + 11, + 0, + 0, // Skip to: 781 + /* 770 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 781 + /* 777 */ MCD_OPC_Decode, + 171, + 17, + 69, // Opcode: MULTu + /* 781 */ MCD_OPC_CheckPredicate, + 37, + 35, + 64, + 0, // Skip to: 17205 + /* 786 */ MCD_OPC_Decode, + 166, + 17, + 184, + 1, // Opcode: MULTU_DSP + /* 791 */ MCD_OPC_FilterValue, + 26, + 16, + 0, + 0, // Skip to: 812 + /* 796 */ MCD_OPC_CheckPredicate, + 31, + 20, + 64, + 0, // Skip to: 17205 + /* 801 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 13, + 64, + 0, // Skip to: 17205 + /* 808 */ MCD_OPC_Decode, + 139, + 19, + 69, // Opcode: SDIV + /* 812 */ MCD_OPC_FilterValue, + 27, + 16, + 0, + 0, // Skip to: 833 + /* 817 */ MCD_OPC_CheckPredicate, + 31, + 255, + 63, + 0, // Skip to: 17205 + /* 822 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 248, + 63, + 0, // Skip to: 17205 + /* 829 */ MCD_OPC_Decode, + 255, + 21, + 69, // Opcode: UDIV + /* 833 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 854 + /* 838 */ MCD_OPC_CheckPredicate, + 27, + 234, + 63, + 0, // Skip to: 17205 + /* 843 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 227, + 63, + 0, // Skip to: 17205 + /* 850 */ MCD_OPC_Decode, + 194, + 5, + 50, // Opcode: ADD + /* 854 */ MCD_OPC_FilterValue, + 33, + 16, + 0, + 0, // Skip to: 875 + /* 859 */ MCD_OPC_CheckPredicate, + 27, + 213, + 63, + 0, // Skip to: 17205 + /* 864 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 206, + 63, + 0, // Skip to: 17205 + /* 871 */ MCD_OPC_Decode, + 139, + 6, + 50, // Opcode: ADDu + /* 875 */ MCD_OPC_FilterValue, + 34, + 16, + 0, + 0, // Skip to: 896 + /* 880 */ MCD_OPC_CheckPredicate, + 27, + 192, + 63, + 0, // Skip to: 17205 + /* 885 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 185, + 63, + 0, // Skip to: 17205 + /* 892 */ MCD_OPC_Decode, + 200, + 20, + 50, // Opcode: SUB + /* 896 */ MCD_OPC_FilterValue, + 35, + 16, + 0, + 0, // Skip to: 917 + /* 901 */ MCD_OPC_CheckPredicate, + 27, + 171, + 63, + 0, // Skip to: 17205 + /* 906 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 164, + 63, + 0, // Skip to: 17205 + /* 913 */ MCD_OPC_Decode, + 128, + 21, + 50, // Opcode: SUBu + /* 917 */ MCD_OPC_FilterValue, + 36, + 16, + 0, + 0, // Skip to: 938 + /* 922 */ MCD_OPC_CheckPredicate, + 27, + 150, + 63, + 0, // Skip to: 17205 + /* 927 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 143, + 63, + 0, // Skip to: 17205 + /* 934 */ MCD_OPC_Decode, + 145, + 6, + 50, // Opcode: AND + /* 938 */ MCD_OPC_FilterValue, + 37, + 16, + 0, + 0, // Skip to: 959 + /* 943 */ MCD_OPC_CheckPredicate, + 27, + 129, + 63, + 0, // Skip to: 17205 + /* 948 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 122, + 63, + 0, // Skip to: 17205 + /* 955 */ MCD_OPC_Decode, + 220, + 17, + 50, // Opcode: OR + /* 959 */ MCD_OPC_FilterValue, + 38, + 16, + 0, + 0, // Skip to: 980 + /* 964 */ MCD_OPC_CheckPredicate, + 27, + 108, + 63, + 0, // Skip to: 17205 + /* 969 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 101, + 63, + 0, // Skip to: 17205 + /* 976 */ MCD_OPC_Decode, + 145, + 22, + 50, // Opcode: XOR + /* 980 */ MCD_OPC_FilterValue, + 39, + 16, + 0, + 0, // Skip to: 1001 + /* 985 */ MCD_OPC_CheckPredicate, + 27, + 87, + 63, + 0, // Skip to: 17205 + /* 990 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 80, + 63, + 0, // Skip to: 17205 + /* 997 */ MCD_OPC_Decode, + 210, + 17, + 50, // Opcode: NOR + /* 1001 */ MCD_OPC_FilterValue, + 42, + 16, + 0, + 0, // Skip to: 1022 + /* 1006 */ MCD_OPC_CheckPredicate, + 27, + 66, + 63, + 0, // Skip to: 17205 + /* 1011 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 59, + 63, + 0, // Skip to: 17205 + /* 1018 */ MCD_OPC_Decode, + 129, + 20, + 50, // Opcode: SLT + /* 1022 */ MCD_OPC_FilterValue, + 43, + 16, + 0, + 0, // Skip to: 1043 + /* 1027 */ MCD_OPC_CheckPredicate, + 27, + 45, + 63, + 0, // Skip to: 17205 + /* 1032 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 38, + 63, + 0, // Skip to: 17205 + /* 1039 */ MCD_OPC_Decode, + 138, + 20, + 50, // Opcode: SLTu + /* 1043 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 1058 + /* 1048 */ MCD_OPC_CheckPredicate, + 36, + 24, + 63, + 0, // Skip to: 17205 + /* 1053 */ MCD_OPC_Decode, + 200, + 21, + 185, + 1, // Opcode: TGE + /* 1058 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 1073 + /* 1063 */ MCD_OPC_CheckPredicate, + 36, + 9, + 63, + 0, // Skip to: 17205 + /* 1068 */ MCD_OPC_Decode, + 205, + 21, + 185, + 1, // Opcode: TGEU + /* 1073 */ MCD_OPC_FilterValue, + 50, + 10, + 0, + 0, // Skip to: 1088 + /* 1078 */ MCD_OPC_CheckPredicate, + 36, + 250, + 62, + 0, // Skip to: 17205 + /* 1083 */ MCD_OPC_Decode, + 232, + 21, + 185, + 1, // Opcode: TLT + /* 1088 */ MCD_OPC_FilterValue, + 51, + 10, + 0, + 0, // Skip to: 1103 + /* 1093 */ MCD_OPC_CheckPredicate, + 36, + 235, + 62, + 0, // Skip to: 17205 + /* 1098 */ MCD_OPC_Decode, + 236, + 21, + 185, + 1, // Opcode: TLTU + /* 1103 */ MCD_OPC_FilterValue, + 52, + 10, + 0, + 0, // Skip to: 1118 + /* 1108 */ MCD_OPC_CheckPredicate, + 36, + 220, + 62, + 0, // Skip to: 17205 + /* 1113 */ MCD_OPC_Decode, + 196, + 21, + 185, + 1, // Opcode: TEQ + /* 1118 */ MCD_OPC_FilterValue, + 54, + 210, + 62, + 0, // Skip to: 17205 + /* 1123 */ MCD_OPC_CheckPredicate, + 36, + 205, + 62, + 0, // Skip to: 17205 + /* 1128 */ MCD_OPC_Decode, + 239, + 21, + 185, + 1, // Opcode: TNE + /* 1133 */ MCD_OPC_FilterValue, + 1, + 250, + 0, + 0, // Skip to: 1388 + /* 1138 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 1141 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1156 + /* 1146 */ MCD_OPC_CheckPredicate, + 27, + 182, + 62, + 0, // Skip to: 17205 + /* 1151 */ MCD_OPC_Decode, + 194, + 7, + 186, + 1, // Opcode: BLTZ + /* 1156 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1171 + /* 1161 */ MCD_OPC_CheckPredicate, + 27, + 167, + 62, + 0, // Skip to: 17205 + /* 1166 */ MCD_OPC_Decode, + 137, + 7, + 186, + 1, // Opcode: BGEZ + /* 1171 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1186 + /* 1176 */ MCD_OPC_CheckPredicate, + 39, + 152, + 62, + 0, // Skip to: 17205 + /* 1181 */ MCD_OPC_Decode, + 205, + 7, + 186, + 1, // Opcode: BLTZL + /* 1186 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1201 + /* 1191 */ MCD_OPC_CheckPredicate, + 39, + 137, + 62, + 0, // Skip to: 17205 + /* 1196 */ MCD_OPC_Decode, + 148, + 7, + 186, + 1, // Opcode: BGEZL + /* 1201 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1216 + /* 1206 */ MCD_OPC_CheckPredicate, + 39, + 122, + 62, + 0, // Skip to: 17205 + /* 1211 */ MCD_OPC_Decode, + 201, + 21, + 164, + 1, // Opcode: TGEI + /* 1216 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1231 + /* 1221 */ MCD_OPC_CheckPredicate, + 39, + 107, + 62, + 0, // Skip to: 17205 + /* 1226 */ MCD_OPC_Decode, + 202, + 21, + 164, + 1, // Opcode: TGEIU + /* 1231 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1246 + /* 1236 */ MCD_OPC_CheckPredicate, + 39, + 92, + 62, + 0, // Skip to: 17205 + /* 1241 */ MCD_OPC_Decode, + 233, + 21, + 164, + 1, // Opcode: TLTI + /* 1246 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1261 + /* 1251 */ MCD_OPC_CheckPredicate, + 39, + 77, + 62, + 0, // Skip to: 17205 + /* 1256 */ MCD_OPC_Decode, + 254, + 21, + 164, + 1, // Opcode: TTLTIU + /* 1261 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 1276 + /* 1266 */ MCD_OPC_CheckPredicate, + 39, + 62, + 62, + 0, // Skip to: 17205 + /* 1271 */ MCD_OPC_Decode, + 197, + 21, + 164, + 1, // Opcode: TEQI + /* 1276 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1291 + /* 1281 */ MCD_OPC_CheckPredicate, + 39, + 47, + 62, + 0, // Skip to: 17205 + /* 1286 */ MCD_OPC_Decode, + 240, + 21, + 164, + 1, // Opcode: TNEI + /* 1291 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 1306 + /* 1296 */ MCD_OPC_CheckPredicate, + 31, + 32, + 62, + 0, // Skip to: 17205 + /* 1301 */ MCD_OPC_Decode, + 196, + 7, + 186, + 1, // Opcode: BLTZAL + /* 1306 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 1321 + /* 1311 */ MCD_OPC_CheckPredicate, + 31, + 17, + 62, + 0, // Skip to: 17205 + /* 1316 */ MCD_OPC_Decode, + 139, + 7, + 186, + 1, // Opcode: BGEZAL + /* 1321 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 1336 + /* 1326 */ MCD_OPC_CheckPredicate, + 39, + 2, + 62, + 0, // Skip to: 17205 + /* 1331 */ MCD_OPC_Decode, + 199, + 7, + 186, + 1, // Opcode: BLTZALL + /* 1336 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 1351 + /* 1341 */ MCD_OPC_CheckPredicate, + 39, + 243, + 61, + 0, // Skip to: 17205 + /* 1346 */ MCD_OPC_Decode, + 142, + 7, + 186, + 1, // Opcode: BGEZALL + /* 1351 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 1373 + /* 1356 */ MCD_OPC_CheckPredicate, + 40, + 228, + 61, + 0, // Skip to: 17205 + /* 1361 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 221, + 61, + 0, // Skip to: 17205 + /* 1368 */ MCD_OPC_Decode, + 243, + 7, + 187, + 1, // Opcode: BPOSGE32 + /* 1373 */ MCD_OPC_FilterValue, + 31, + 211, + 61, + 0, // Skip to: 17205 + /* 1378 */ MCD_OPC_CheckPredicate, + 28, + 206, + 61, + 0, // Skip to: 17205 + /* 1383 */ MCD_OPC_Decode, + 168, + 21, + 188, + 1, // Opcode: SYNCI + /* 1388 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1403 + /* 1393 */ MCD_OPC_CheckPredicate, + 27, + 191, + 61, + 0, // Skip to: 17205 + /* 1398 */ MCD_OPC_Decode, + 238, + 13, + 189, + 1, // Opcode: J + /* 1403 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1418 + /* 1408 */ MCD_OPC_CheckPredicate, + 27, + 176, + 61, + 0, // Skip to: 17205 + /* 1413 */ MCD_OPC_Decode, + 239, + 13, + 189, + 1, // Opcode: JAL + /* 1418 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 1433 + /* 1423 */ MCD_OPC_CheckPredicate, + 27, + 161, + 61, + 0, // Skip to: 17205 + /* 1428 */ MCD_OPC_Decode, + 244, + 6, + 190, + 1, // Opcode: BEQ + /* 1433 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1448 + /* 1438 */ MCD_OPC_CheckPredicate, + 27, + 146, + 61, + 0, // Skip to: 17205 + /* 1443 */ MCD_OPC_Decode, + 211, + 7, + 190, + 1, // Opcode: BNE + /* 1448 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 1470 + /* 1453 */ MCD_OPC_CheckPredicate, + 27, + 131, + 61, + 0, // Skip to: 17205 + /* 1458 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 124, + 61, + 0, // Skip to: 17205 + /* 1465 */ MCD_OPC_Decode, + 179, + 7, + 186, + 1, // Opcode: BLEZ + /* 1470 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 1492 + /* 1475 */ MCD_OPC_CheckPredicate, + 27, + 109, + 61, + 0, // Skip to: 17205 + /* 1480 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 102, + 61, + 0, // Skip to: 17205 + /* 1487 */ MCD_OPC_Decode, + 150, + 7, + 186, + 1, // Opcode: BGTZ + /* 1492 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1507 + /* 1497 */ MCD_OPC_CheckPredicate, + 31, + 87, + 61, + 0, // Skip to: 17205 + /* 1502 */ MCD_OPC_Decode, + 135, + 6, + 191, + 1, // Opcode: ADDi + /* 1507 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1522 + /* 1512 */ MCD_OPC_CheckPredicate, + 27, + 72, + 61, + 0, // Skip to: 17205 + /* 1517 */ MCD_OPC_Decode, + 137, + 6, + 191, + 1, // Opcode: ADDiu + /* 1522 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1537 + /* 1527 */ MCD_OPC_CheckPredicate, + 27, + 57, + 61, + 0, // Skip to: 17205 + /* 1532 */ MCD_OPC_Decode, + 132, + 20, + 191, + 1, // Opcode: SLTi + /* 1537 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1552 + /* 1542 */ MCD_OPC_CheckPredicate, + 27, + 42, + 61, + 0, // Skip to: 17205 + /* 1547 */ MCD_OPC_Decode, + 135, + 20, + 191, + 1, // Opcode: SLTiu + /* 1552 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 1567 + /* 1557 */ MCD_OPC_CheckPredicate, + 27, + 27, + 61, + 0, // Skip to: 17205 + /* 1562 */ MCD_OPC_Decode, + 156, + 6, + 192, + 1, // Opcode: ANDi + /* 1567 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1582 + /* 1572 */ MCD_OPC_CheckPredicate, + 27, + 12, + 61, + 0, // Skip to: 17205 + /* 1577 */ MCD_OPC_Decode, + 229, + 17, + 192, + 1, // Opcode: ORi + /* 1582 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1597 + /* 1587 */ MCD_OPC_CheckPredicate, + 27, + 253, + 60, + 0, // Skip to: 17205 + /* 1592 */ MCD_OPC_Decode, + 154, + 22, + 192, + 1, // Opcode: XORi + /* 1597 */ MCD_OPC_FilterValue, + 15, + 16, + 0, + 0, // Skip to: 1618 + /* 1602 */ MCD_OPC_CheckPredicate, + 27, + 238, + 60, + 0, // Skip to: 17205 + /* 1607 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 231, + 60, + 0, // Skip to: 17205 + /* 1614 */ MCD_OPC_Decode, + 224, + 14, + 92, // Opcode: LUi + /* 1618 */ MCD_OPC_FilterValue, + 16, + 155, + 2, + 0, // Skip to: 2290 + /* 1623 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 1626 */ MCD_OPC_FilterValue, + 0, + 50, + 1, + 0, // Skip to: 1937 + /* 1631 */ MCD_OPC_ExtractField, + 21, + 4, // Inst{24-21} ... + /* 1634 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1656 + /* 1639 */ MCD_OPC_CheckPredicate, + 27, + 201, + 60, + 0, // Skip to: 17205 + /* 1644 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 194, + 60, + 0, // Skip to: 17205 + /* 1651 */ MCD_OPC_Decode, + 212, + 15, + 193, + 1, // Opcode: MFC0 + /* 1656 */ MCD_OPC_FilterValue, + 3, + 65, + 0, + 0, // Skip to: 1726 + /* 1661 */ MCD_OPC_ExtractField, + 3, + 8, // Inst{10-3} ... + /* 1664 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1679 + /* 1669 */ MCD_OPC_CheckPredicate, + 41, + 171, + 60, + 0, // Skip to: 17205 + /* 1674 */ MCD_OPC_Decode, + 220, + 15, + 193, + 1, // Opcode: MFGC0 + /* 1679 */ MCD_OPC_FilterValue, + 64, + 10, + 0, + 0, // Skip to: 1694 + /* 1684 */ MCD_OPC_CheckPredicate, + 41, + 156, + 60, + 0, // Skip to: 17205 + /* 1689 */ MCD_OPC_Decode, + 236, + 16, + 194, + 1, // Opcode: MTGC0 + /* 1694 */ MCD_OPC_FilterValue, + 128, + 1, + 10, + 0, + 0, // Skip to: 1710 + /* 1700 */ MCD_OPC_CheckPredicate, + 41, + 140, + 60, + 0, // Skip to: 17205 + /* 1705 */ MCD_OPC_Decode, + 228, + 15, + 193, + 1, // Opcode: MFHGC0 + /* 1710 */ MCD_OPC_FilterValue, + 192, + 1, + 129, + 60, + 0, // Skip to: 17205 + /* 1716 */ MCD_OPC_CheckPredicate, + 41, + 124, + 60, + 0, // Skip to: 17205 + /* 1721 */ MCD_OPC_Decode, + 244, + 16, + 194, + 1, // Opcode: MTHGC0 + /* 1726 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 1748 + /* 1731 */ MCD_OPC_CheckPredicate, + 27, + 109, + 60, + 0, // Skip to: 17205 + /* 1736 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 102, + 60, + 0, // Skip to: 17205 + /* 1743 */ MCD_OPC_Decode, + 227, + 16, + 194, + 1, // Opcode: MTC0 + /* 1748 */ MCD_OPC_FilterValue, + 8, + 57, + 0, + 0, // Skip to: 1810 + /* 1753 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 1756 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1771 + /* 1761 */ MCD_OPC_CheckPredicate, + 31, + 20, + 0, + 0, // Skip to: 1786 + /* 1766 */ MCD_OPC_Decode, + 210, + 6, + 187, + 1, // Opcode: BC0F + /* 1771 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1786 + /* 1776 */ MCD_OPC_CheckPredicate, + 31, + 5, + 0, + 0, // Skip to: 1786 + /* 1781 */ MCD_OPC_Decode, + 211, + 6, + 187, + 1, // Opcode: BC0T + /* 1786 */ MCD_OPC_CheckPredicate, + 42, + 54, + 60, + 0, // Skip to: 17205 + /* 1791 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 47, + 60, + 0, // Skip to: 17205 + /* 1798 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 40, + 60, + 0, // Skip to: 17205 + /* 1805 */ MCD_OPC_Decode, + 242, + 15, + 195, + 1, // Opcode: MFTR + /* 1810 */ MCD_OPC_FilterValue, + 11, + 93, + 0, + 0, // Skip to: 1908 + /* 1815 */ MCD_OPC_ExtractField, + 0, + 16, // Inst{15-0} ... + /* 1818 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1832 + /* 1823 */ MCD_OPC_CheckPredicate, + 42, + 17, + 60, + 0, // Skip to: 17205 + /* 1828 */ MCD_OPC_Decode, + 218, + 11, + 81, // Opcode: DVPE + /* 1832 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 1846 + /* 1837 */ MCD_OPC_CheckPredicate, + 42, + 3, + 60, + 0, // Skip to: 17205 + /* 1842 */ MCD_OPC_Decode, + 235, + 11, + 81, // Opcode: EVPE + /* 1846 */ MCD_OPC_FilterValue, + 193, + 23, + 9, + 0, + 0, // Skip to: 1861 + /* 1852 */ MCD_OPC_CheckPredicate, + 42, + 244, + 59, + 0, // Skip to: 17205 + /* 1857 */ MCD_OPC_Decode, + 134, + 11, + 81, // Opcode: DMT + /* 1861 */ MCD_OPC_FilterValue, + 225, + 23, + 9, + 0, + 0, // Skip to: 1876 + /* 1867 */ MCD_OPC_CheckPredicate, + 42, + 229, + 59, + 0, // Skip to: 17205 + /* 1872 */ MCD_OPC_Decode, + 228, + 11, + 81, // Opcode: EMT + /* 1876 */ MCD_OPC_FilterValue, + 128, + 192, + 1, + 9, + 0, + 0, // Skip to: 1892 + /* 1883 */ MCD_OPC_CheckPredicate, + 28, + 213, + 59, + 0, // Skip to: 17205 + /* 1888 */ MCD_OPC_Decode, + 235, + 10, + 81, // Opcode: DI + /* 1892 */ MCD_OPC_FilterValue, + 160, + 192, + 1, + 202, + 59, + 0, // Skip to: 17205 + /* 1899 */ MCD_OPC_CheckPredicate, + 28, + 197, + 59, + 0, // Skip to: 17205 + /* 1904 */ MCD_OPC_Decode, + 225, + 11, + 81, // Opcode: EI + /* 1908 */ MCD_OPC_FilterValue, + 12, + 188, + 59, + 0, // Skip to: 17205 + /* 1913 */ MCD_OPC_CheckPredicate, + 42, + 183, + 59, + 0, // Skip to: 17205 + /* 1918 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 176, + 59, + 0, // Skip to: 17205 + /* 1925 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 169, + 59, + 0, // Skip to: 17205 + /* 1932 */ MCD_OPC_Decode, + 136, + 17, + 195, + 1, // Opcode: MTTR + /* 1937 */ MCD_OPC_FilterValue, + 1, + 159, + 59, + 0, // Skip to: 17205 + /* 1942 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1945 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 1966 + /* 1950 */ MCD_OPC_CheckPredicate, + 27, + 146, + 59, + 0, // Skip to: 17205 + /* 1955 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 139, + 59, + 0, // Skip to: 17205 + /* 1962 */ MCD_OPC_Decode, + 226, + 21, + 0, // Opcode: TLBR + /* 1966 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 1987 + /* 1971 */ MCD_OPC_CheckPredicate, + 27, + 125, + 59, + 0, // Skip to: 17205 + /* 1976 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 118, + 59, + 0, // Skip to: 17205 + /* 1983 */ MCD_OPC_Decode, + 228, + 21, + 0, // Opcode: TLBWI + /* 1987 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 2008 + /* 1992 */ MCD_OPC_CheckPredicate, + 43, + 104, + 59, + 0, // Skip to: 17205 + /* 1997 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 97, + 59, + 0, // Skip to: 17205 + /* 2004 */ MCD_OPC_Decode, + 220, + 21, + 0, // Opcode: TLBINV + /* 2008 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 2029 + /* 2013 */ MCD_OPC_CheckPredicate, + 43, + 83, + 59, + 0, // Skip to: 17205 + /* 2018 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 76, + 59, + 0, // Skip to: 17205 + /* 2025 */ MCD_OPC_Decode, + 221, + 21, + 0, // Opcode: TLBINVF + /* 2029 */ MCD_OPC_FilterValue, + 6, + 16, + 0, + 0, // Skip to: 2050 + /* 2034 */ MCD_OPC_CheckPredicate, + 27, + 62, + 59, + 0, // Skip to: 17205 + /* 2039 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 55, + 59, + 0, // Skip to: 17205 + /* 2046 */ MCD_OPC_Decode, + 230, + 21, + 0, // Opcode: TLBWR + /* 2050 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 2071 + /* 2055 */ MCD_OPC_CheckPredicate, + 27, + 41, + 59, + 0, // Skip to: 17205 + /* 2060 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 34, + 59, + 0, // Skip to: 17205 + /* 2067 */ MCD_OPC_Decode, + 224, + 21, + 0, // Opcode: TLBP + /* 2071 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 2092 + /* 2076 */ MCD_OPC_CheckPredicate, + 41, + 20, + 59, + 0, // Skip to: 17205 + /* 2081 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 13, + 59, + 0, // Skip to: 17205 + /* 2088 */ MCD_OPC_Decode, + 214, + 21, + 0, // Opcode: TLBGR + /* 2092 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 2113 + /* 2097 */ MCD_OPC_CheckPredicate, + 41, + 255, + 58, + 0, // Skip to: 17205 + /* 2102 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 248, + 58, + 0, // Skip to: 17205 + /* 2109 */ MCD_OPC_Decode, + 216, + 21, + 0, // Opcode: TLBGWI + /* 2113 */ MCD_OPC_FilterValue, + 11, + 16, + 0, + 0, // Skip to: 2134 + /* 2118 */ MCD_OPC_CheckPredicate, + 41, + 234, + 58, + 0, // Skip to: 17205 + /* 2123 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 227, + 58, + 0, // Skip to: 17205 + /* 2130 */ MCD_OPC_Decode, + 208, + 21, + 0, // Opcode: TLBGINV + /* 2134 */ MCD_OPC_FilterValue, + 12, + 16, + 0, + 0, // Skip to: 2155 + /* 2139 */ MCD_OPC_CheckPredicate, + 41, + 213, + 58, + 0, // Skip to: 17205 + /* 2144 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 206, + 58, + 0, // Skip to: 17205 + /* 2151 */ MCD_OPC_Decode, + 209, + 21, + 0, // Opcode: TLBGINVF + /* 2155 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 2176 + /* 2160 */ MCD_OPC_CheckPredicate, + 41, + 192, + 58, + 0, // Skip to: 17205 + /* 2165 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 185, + 58, + 0, // Skip to: 17205 + /* 2172 */ MCD_OPC_Decode, + 218, + 21, + 0, // Opcode: TLBGWR + /* 2176 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 2197 + /* 2181 */ MCD_OPC_CheckPredicate, + 41, + 171, + 58, + 0, // Skip to: 17205 + /* 2186 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 164, + 58, + 0, // Skip to: 17205 + /* 2193 */ MCD_OPC_Decode, + 212, + 21, + 0, // Opcode: TLBGP + /* 2197 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 2233 + /* 2202 */ MCD_OPC_ExtractField, + 6, + 19, // Inst{24-6} ... + /* 2205 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2219 + /* 2210 */ MCD_OPC_CheckPredicate, + 44, + 142, + 58, + 0, // Skip to: 17205 + /* 2215 */ MCD_OPC_Decode, + 229, + 11, + 0, // Opcode: ERET + /* 2219 */ MCD_OPC_FilterValue, + 1, + 133, + 58, + 0, // Skip to: 17205 + /* 2224 */ MCD_OPC_CheckPredicate, + 45, + 128, + 58, + 0, // Skip to: 17205 + /* 2229 */ MCD_OPC_Decode, + 230, + 11, + 0, // Opcode: ERETNC + /* 2233 */ MCD_OPC_FilterValue, + 31, + 16, + 0, + 0, // Skip to: 2254 + /* 2238 */ MCD_OPC_CheckPredicate, + 46, + 114, + 58, + 0, // Skip to: 17205 + /* 2243 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 107, + 58, + 0, // Skip to: 17205 + /* 2250 */ MCD_OPC_Decode, + 228, + 10, + 0, // Opcode: DERET + /* 2254 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 2275 + /* 2259 */ MCD_OPC_CheckPredicate, + 44, + 93, + 58, + 0, // Skip to: 17205 + /* 2264 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 86, + 58, + 0, // Skip to: 17205 + /* 2271 */ MCD_OPC_Decode, + 136, + 22, + 0, // Opcode: WAIT + /* 2275 */ MCD_OPC_FilterValue, + 40, + 77, + 58, + 0, // Skip to: 17205 + /* 2280 */ MCD_OPC_CheckPredicate, + 41, + 72, + 58, + 0, // Skip to: 17205 + /* 2285 */ MCD_OPC_Decode, + 207, + 13, + 196, + 1, // Opcode: HYPCALL + /* 2290 */ MCD_OPC_FilterValue, + 17, + 205, + 7, + 0, // Skip to: 4292 + /* 2295 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 2298 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2320 + /* 2303 */ MCD_OPC_CheckPredicate, + 47, + 49, + 58, + 0, // Skip to: 17205 + /* 2308 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 42, + 58, + 0, // Skip to: 17205 + /* 2315 */ MCD_OPC_Decode, + 214, + 15, + 197, + 1, // Opcode: MFC1 + /* 2320 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 2342 + /* 2325 */ MCD_OPC_CheckPredicate, + 48, + 27, + 58, + 0, // Skip to: 17205 + /* 2330 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 20, + 58, + 0, // Skip to: 17205 + /* 2337 */ MCD_OPC_Decode, + 128, + 11, + 198, + 1, // Opcode: DMFC1 + /* 2342 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 2364 + /* 2347 */ MCD_OPC_CheckPredicate, + 47, + 5, + 58, + 0, // Skip to: 17205 + /* 2352 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 254, + 57, + 0, // Skip to: 17205 + /* 2359 */ MCD_OPC_Decode, + 174, + 8, + 199, + 1, // Opcode: CFC1 + /* 2364 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 2386 + /* 2369 */ MCD_OPC_CheckPredicate, + 49, + 239, + 57, + 0, // Skip to: 17205 + /* 2374 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 232, + 57, + 0, // Skip to: 17205 + /* 2381 */ MCD_OPC_Decode, + 223, + 15, + 200, + 1, // Opcode: MFHC1_D32 + /* 2386 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 2408 + /* 2391 */ MCD_OPC_CheckPredicate, + 47, + 217, + 57, + 0, // Skip to: 17205 + /* 2396 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 210, + 57, + 0, // Skip to: 17205 + /* 2403 */ MCD_OPC_Decode, + 229, + 16, + 201, + 1, // Opcode: MTC1 + /* 2408 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 2430 + /* 2413 */ MCD_OPC_CheckPredicate, + 48, + 195, + 57, + 0, // Skip to: 17205 + /* 2418 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 188, + 57, + 0, // Skip to: 17205 + /* 2425 */ MCD_OPC_Decode, + 136, + 11, + 202, + 1, // Opcode: DMTC1 + /* 2430 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 2452 + /* 2435 */ MCD_OPC_CheckPredicate, + 47, + 173, + 57, + 0, // Skip to: 17205 + /* 2440 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 166, + 57, + 0, // Skip to: 17205 + /* 2447 */ MCD_OPC_Decode, + 201, + 9, + 203, + 1, // Opcode: CTC1 + /* 2452 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 2474 + /* 2457 */ MCD_OPC_CheckPredicate, + 49, + 151, + 57, + 0, // Skip to: 17205 + /* 2462 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 144, + 57, + 0, // Skip to: 17205 + /* 2469 */ MCD_OPC_Decode, + 239, + 16, + 204, + 1, // Opcode: MTHC1_D32 + /* 2474 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 2542 + /* 2479 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 2482 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2497 + /* 2487 */ MCD_OPC_CheckPredicate, + 50, + 121, + 57, + 0, // Skip to: 17205 + /* 2492 */ MCD_OPC_Decode, + 215, + 6, + 205, + 1, // Opcode: BC1F + /* 2497 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2512 + /* 2502 */ MCD_OPC_CheckPredicate, + 50, + 106, + 57, + 0, // Skip to: 17205 + /* 2507 */ MCD_OPC_Decode, + 220, + 6, + 205, + 1, // Opcode: BC1T + /* 2512 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2527 + /* 2517 */ MCD_OPC_CheckPredicate, + 51, + 91, + 57, + 0, // Skip to: 17205 + /* 2522 */ MCD_OPC_Decode, + 216, + 6, + 205, + 1, // Opcode: BC1FL + /* 2527 */ MCD_OPC_FilterValue, + 3, + 81, + 57, + 0, // Skip to: 17205 + /* 2532 */ MCD_OPC_CheckPredicate, + 51, + 76, + 57, + 0, // Skip to: 17205 + /* 2537 */ MCD_OPC_Decode, + 221, + 6, + 205, + 1, // Opcode: BC1TL + /* 2542 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 2557 + /* 2547 */ MCD_OPC_CheckPredicate, + 30, + 61, + 57, + 0, // Skip to: 17205 + /* 2552 */ MCD_OPC_Decode, + 136, + 8, + 206, + 1, // Opcode: BZ_V + /* 2557 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2572 + /* 2562 */ MCD_OPC_CheckPredicate, + 30, + 46, + 57, + 0, // Skip to: 17205 + /* 2567 */ MCD_OPC_Decode, + 239, + 7, + 206, + 1, // Opcode: BNZ_V + /* 2572 */ MCD_OPC_FilterValue, + 16, + 1, + 3, + 0, // Skip to: 3346 + /* 2577 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 2580 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2595 + /* 2585 */ MCD_OPC_CheckPredicate, + 47, + 23, + 57, + 0, // Skip to: 17205 + /* 2590 */ MCD_OPC_Decode, + 150, + 12, + 207, + 1, // Opcode: FADD_S + /* 2595 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2610 + /* 2600 */ MCD_OPC_CheckPredicate, + 47, + 8, + 57, + 0, // Skip to: 17205 + /* 2605 */ MCD_OPC_Decode, + 167, + 13, + 207, + 1, // Opcode: FSUB_S + /* 2610 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2625 + /* 2615 */ MCD_OPC_CheckPredicate, + 47, + 249, + 56, + 0, // Skip to: 17205 + /* 2620 */ MCD_OPC_Decode, + 251, + 12, + 207, + 1, // Opcode: FMUL_S + /* 2625 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 2640 + /* 2630 */ MCD_OPC_CheckPredicate, + 47, + 234, + 56, + 0, // Skip to: 17205 + /* 2635 */ MCD_OPC_Decode, + 188, + 12, + 207, + 1, // Opcode: FDIV_S + /* 2640 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 2662 + /* 2645 */ MCD_OPC_CheckPredicate, + 52, + 219, + 56, + 0, // Skip to: 17205 + /* 2650 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 212, + 56, + 0, // Skip to: 17205 + /* 2657 */ MCD_OPC_Decode, + 158, + 13, + 208, + 1, // Opcode: FSQRT_S + /* 2662 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 2684 + /* 2667 */ MCD_OPC_CheckPredicate, + 47, + 197, + 56, + 0, // Skip to: 17205 + /* 2672 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 190, + 56, + 0, // Skip to: 17205 + /* 2679 */ MCD_OPC_Decode, + 142, + 12, + 208, + 1, // Opcode: FABS_S + /* 2684 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 2706 + /* 2689 */ MCD_OPC_CheckPredicate, + 47, + 175, + 56, + 0, // Skip to: 17205 + /* 2694 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 168, + 56, + 0, // Skip to: 17205 + /* 2701 */ MCD_OPC_Decode, + 240, + 12, + 208, + 1, // Opcode: FMOV_S + /* 2706 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 2728 + /* 2711 */ MCD_OPC_CheckPredicate, + 53, + 153, + 56, + 0, // Skip to: 17205 + /* 2716 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 146, + 56, + 0, // Skip to: 17205 + /* 2723 */ MCD_OPC_Decode, + 131, + 13, + 208, + 1, // Opcode: FNEG_S + /* 2728 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 2750 + /* 2733 */ MCD_OPC_CheckPredicate, + 52, + 131, + 56, + 0, // Skip to: 17205 + /* 2738 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 124, + 56, + 0, // Skip to: 17205 + /* 2745 */ MCD_OPC_Decode, + 213, + 18, + 208, + 1, // Opcode: ROUND_W_S + /* 2750 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 2772 + /* 2755 */ MCD_OPC_CheckPredicate, + 52, + 109, + 56, + 0, // Skip to: 17205 + /* 2760 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 102, + 56, + 0, // Skip to: 17205 + /* 2767 */ MCD_OPC_Decode, + 251, + 21, + 208, + 1, // Opcode: TRUNC_W_S + /* 2772 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 2794 + /* 2777 */ MCD_OPC_CheckPredicate, + 52, + 87, + 56, + 0, // Skip to: 17205 + /* 2782 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 80, + 56, + 0, // Skip to: 17205 + /* 2789 */ MCD_OPC_Decode, + 163, + 8, + 208, + 1, // Opcode: CEIL_W_S + /* 2794 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2816 + /* 2799 */ MCD_OPC_CheckPredicate, + 52, + 65, + 56, + 0, // Skip to: 17205 + /* 2804 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 58, + 56, + 0, // Skip to: 17205 + /* 2811 */ MCD_OPC_Decode, + 222, + 12, + 208, + 1, // Opcode: FLOOR_W_S + /* 2816 */ MCD_OPC_FilterValue, + 17, + 33, + 0, + 0, // Skip to: 2854 + /* 2821 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 2824 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2839 + /* 2829 */ MCD_OPC_CheckPredicate, + 29, + 35, + 56, + 0, // Skip to: 17205 + /* 2834 */ MCD_OPC_Decode, + 168, + 16, + 209, + 1, // Opcode: MOVF_S + /* 2839 */ MCD_OPC_FilterValue, + 1, + 25, + 56, + 0, // Skip to: 17205 + /* 2844 */ MCD_OPC_CheckPredicate, + 29, + 20, + 56, + 0, // Skip to: 17205 + /* 2849 */ MCD_OPC_Decode, + 188, + 16, + 209, + 1, // Opcode: MOVT_S + /* 2854 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 2869 + /* 2859 */ MCD_OPC_CheckPredicate, + 29, + 5, + 56, + 0, // Skip to: 17205 + /* 2864 */ MCD_OPC_Decode, + 200, + 16, + 210, + 1, // Opcode: MOVZ_I_S + /* 2869 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 2884 + /* 2874 */ MCD_OPC_CheckPredicate, + 29, + 246, + 55, + 0, // Skip to: 17205 + /* 2879 */ MCD_OPC_Decode, + 180, + 16, + 210, + 1, // Opcode: MOVN_I_S + /* 2884 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 2906 + /* 2889 */ MCD_OPC_CheckPredicate, + 54, + 231, + 55, + 0, // Skip to: 17205 + /* 2894 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 224, + 55, + 0, // Skip to: 17205 + /* 2901 */ MCD_OPC_Decode, + 187, + 18, + 208, + 1, // Opcode: RECIP_S + /* 2906 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 2928 + /* 2911 */ MCD_OPC_CheckPredicate, + 54, + 209, + 55, + 0, // Skip to: 17205 + /* 2916 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 202, + 55, + 0, // Skip to: 17205 + /* 2923 */ MCD_OPC_Decode, + 220, + 18, + 208, + 1, // Opcode: RSQRT_S + /* 2928 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 2950 + /* 2933 */ MCD_OPC_CheckPredicate, + 55, + 187, + 55, + 0, // Skip to: 17205 + /* 2938 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 180, + 55, + 0, // Skip to: 17205 + /* 2945 */ MCD_OPC_Decode, + 205, + 9, + 211, + 1, // Opcode: CVT_D32_S + /* 2950 */ MCD_OPC_FilterValue, + 36, + 17, + 0, + 0, // Skip to: 2972 + /* 2955 */ MCD_OPC_CheckPredicate, + 47, + 165, + 55, + 0, // Skip to: 17205 + /* 2960 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 158, + 55, + 0, // Skip to: 17205 + /* 2967 */ MCD_OPC_Decode, + 239, + 9, + 208, + 1, // Opcode: CVT_W_S + /* 2972 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 2994 + /* 2977 */ MCD_OPC_CheckPredicate, + 56, + 143, + 55, + 0, // Skip to: 17205 + /* 2982 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 136, + 55, + 0, // Skip to: 17205 + /* 2989 */ MCD_OPC_Decode, + 218, + 9, + 212, + 1, // Opcode: CVT_L_S + /* 2994 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 3016 + /* 2999 */ MCD_OPC_CheckPredicate, + 50, + 121, + 55, + 0, // Skip to: 17205 + /* 3004 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 114, + 55, + 0, // Skip to: 17205 + /* 3011 */ MCD_OPC_Decode, + 252, + 9, + 213, + 1, // Opcode: C_F_S + /* 3016 */ MCD_OPC_FilterValue, + 49, + 17, + 0, + 0, // Skip to: 3038 + /* 3021 */ MCD_OPC_CheckPredicate, + 50, + 99, + 55, + 0, // Skip to: 17205 + /* 3026 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 92, + 55, + 0, // Skip to: 17205 + /* 3033 */ MCD_OPC_Decode, + 208, + 10, + 213, + 1, // Opcode: C_UN_S + /* 3038 */ MCD_OPC_FilterValue, + 50, + 17, + 0, + 0, // Skip to: 3060 + /* 3043 */ MCD_OPC_CheckPredicate, + 50, + 77, + 55, + 0, // Skip to: 17205 + /* 3048 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 70, + 55, + 0, // Skip to: 17205 + /* 3055 */ MCD_OPC_Decode, + 246, + 9, + 213, + 1, // Opcode: C_EQ_S + /* 3060 */ MCD_OPC_FilterValue, + 51, + 17, + 0, + 0, // Skip to: 3082 + /* 3065 */ MCD_OPC_CheckPredicate, + 50, + 55, + 55, + 0, // Skip to: 17205 + /* 3070 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 48, + 55, + 0, // Skip to: 17205 + /* 3077 */ MCD_OPC_Decode, + 190, + 10, + 213, + 1, // Opcode: C_UEQ_S + /* 3082 */ MCD_OPC_FilterValue, + 52, + 17, + 0, + 0, // Skip to: 3104 + /* 3087 */ MCD_OPC_CheckPredicate, + 50, + 33, + 55, + 0, // Skip to: 17205 + /* 3092 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 26, + 55, + 0, // Skip to: 17205 + /* 3099 */ MCD_OPC_Decode, + 172, + 10, + 213, + 1, // Opcode: C_OLT_S + /* 3104 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 3126 + /* 3109 */ MCD_OPC_CheckPredicate, + 50, + 11, + 55, + 0, // Skip to: 17205 + /* 3114 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 4, + 55, + 0, // Skip to: 17205 + /* 3121 */ MCD_OPC_Decode, + 202, + 10, + 213, + 1, // Opcode: C_ULT_S + /* 3126 */ MCD_OPC_FilterValue, + 54, + 17, + 0, + 0, // Skip to: 3148 + /* 3131 */ MCD_OPC_CheckPredicate, + 50, + 245, + 54, + 0, // Skip to: 17205 + /* 3136 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 238, + 54, + 0, // Skip to: 17205 + /* 3143 */ MCD_OPC_Decode, + 166, + 10, + 213, + 1, // Opcode: C_OLE_S + /* 3148 */ MCD_OPC_FilterValue, + 55, + 17, + 0, + 0, // Skip to: 3170 + /* 3153 */ MCD_OPC_CheckPredicate, + 50, + 223, + 54, + 0, // Skip to: 17205 + /* 3158 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 216, + 54, + 0, // Skip to: 17205 + /* 3165 */ MCD_OPC_Decode, + 196, + 10, + 213, + 1, // Opcode: C_ULE_S + /* 3170 */ MCD_OPC_FilterValue, + 56, + 17, + 0, + 0, // Skip to: 3192 + /* 3175 */ MCD_OPC_CheckPredicate, + 50, + 201, + 54, + 0, // Skip to: 17205 + /* 3180 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 194, + 54, + 0, // Skip to: 17205 + /* 3187 */ MCD_OPC_Decode, + 184, + 10, + 213, + 1, // Opcode: C_SF_S + /* 3192 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 3214 + /* 3197 */ MCD_OPC_CheckPredicate, + 50, + 179, + 54, + 0, // Skip to: 17205 + /* 3202 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 172, + 54, + 0, // Skip to: 17205 + /* 3209 */ MCD_OPC_Decode, + 148, + 10, + 213, + 1, // Opcode: C_NGLE_S + /* 3214 */ MCD_OPC_FilterValue, + 58, + 17, + 0, + 0, // Skip to: 3236 + /* 3219 */ MCD_OPC_CheckPredicate, + 50, + 157, + 54, + 0, // Skip to: 17205 + /* 3224 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 150, + 54, + 0, // Skip to: 17205 + /* 3231 */ MCD_OPC_Decode, + 178, + 10, + 213, + 1, // Opcode: C_SEQ_S + /* 3236 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 3258 + /* 3241 */ MCD_OPC_CheckPredicate, + 50, + 135, + 54, + 0, // Skip to: 17205 + /* 3246 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 128, + 54, + 0, // Skip to: 17205 + /* 3253 */ MCD_OPC_Decode, + 154, + 10, + 213, + 1, // Opcode: C_NGL_S + /* 3258 */ MCD_OPC_FilterValue, + 60, + 17, + 0, + 0, // Skip to: 3280 + /* 3263 */ MCD_OPC_CheckPredicate, + 50, + 113, + 54, + 0, // Skip to: 17205 + /* 3268 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 106, + 54, + 0, // Skip to: 17205 + /* 3275 */ MCD_OPC_Decode, + 136, + 10, + 213, + 1, // Opcode: C_LT_S + /* 3280 */ MCD_OPC_FilterValue, + 61, + 17, + 0, + 0, // Skip to: 3302 + /* 3285 */ MCD_OPC_CheckPredicate, + 50, + 91, + 54, + 0, // Skip to: 17205 + /* 3290 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 84, + 54, + 0, // Skip to: 17205 + /* 3297 */ MCD_OPC_Decode, + 142, + 10, + 213, + 1, // Opcode: C_NGE_S + /* 3302 */ MCD_OPC_FilterValue, + 62, + 17, + 0, + 0, // Skip to: 3324 + /* 3307 */ MCD_OPC_CheckPredicate, + 50, + 69, + 54, + 0, // Skip to: 17205 + /* 3312 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 62, + 54, + 0, // Skip to: 17205 + /* 3319 */ MCD_OPC_Decode, + 130, + 10, + 213, + 1, // Opcode: C_LE_S + /* 3324 */ MCD_OPC_FilterValue, + 63, + 52, + 54, + 0, // Skip to: 17205 + /* 3329 */ MCD_OPC_CheckPredicate, + 50, + 47, + 54, + 0, // Skip to: 17205 + /* 3334 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 40, + 54, + 0, // Skip to: 17205 + /* 3341 */ MCD_OPC_Decode, + 160, + 10, + 213, + 1, // Opcode: C_NGT_S + /* 3346 */ MCD_OPC_FilterValue, + 17, + 1, + 3, + 0, // Skip to: 4120 + /* 3351 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 3354 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3369 + /* 3359 */ MCD_OPC_CheckPredicate, + 55, + 17, + 54, + 0, // Skip to: 17205 + /* 3364 */ MCD_OPC_Decode, + 145, + 12, + 214, + 1, // Opcode: FADD_D32 + /* 3369 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 3384 + /* 3374 */ MCD_OPC_CheckPredicate, + 55, + 2, + 54, + 0, // Skip to: 17205 + /* 3379 */ MCD_OPC_Decode, + 162, + 13, + 214, + 1, // Opcode: FSUB_D32 + /* 3384 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 3399 + /* 3389 */ MCD_OPC_CheckPredicate, + 55, + 243, + 53, + 0, // Skip to: 17205 + /* 3394 */ MCD_OPC_Decode, + 246, + 12, + 214, + 1, // Opcode: FMUL_D32 + /* 3399 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 3414 + /* 3404 */ MCD_OPC_CheckPredicate, + 55, + 228, + 53, + 0, // Skip to: 17205 + /* 3409 */ MCD_OPC_Decode, + 184, + 12, + 214, + 1, // Opcode: FDIV_D32 + /* 3414 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 3436 + /* 3419 */ MCD_OPC_CheckPredicate, + 57, + 213, + 53, + 0, // Skip to: 17205 + /* 3424 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 206, + 53, + 0, // Skip to: 17205 + /* 3431 */ MCD_OPC_Decode, + 154, + 13, + 215, + 1, // Opcode: FSQRT_D32 + /* 3436 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 3458 + /* 3441 */ MCD_OPC_CheckPredicate, + 55, + 191, + 53, + 0, // Skip to: 17205 + /* 3446 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 184, + 53, + 0, // Skip to: 17205 + /* 3453 */ MCD_OPC_Decode, + 138, + 12, + 215, + 1, // Opcode: FABS_D32 + /* 3458 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 3480 + /* 3463 */ MCD_OPC_CheckPredicate, + 55, + 169, + 53, + 0, // Skip to: 17205 + /* 3468 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 162, + 53, + 0, // Skip to: 17205 + /* 3475 */ MCD_OPC_Decode, + 235, + 12, + 215, + 1, // Opcode: FMOV_D32 + /* 3480 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 3502 + /* 3485 */ MCD_OPC_CheckPredicate, + 55, + 147, + 53, + 0, // Skip to: 17205 + /* 3490 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 140, + 53, + 0, // Skip to: 17205 + /* 3497 */ MCD_OPC_Decode, + 255, + 12, + 215, + 1, // Opcode: FNEG_D32 + /* 3502 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 3524 + /* 3507 */ MCD_OPC_CheckPredicate, + 57, + 125, + 53, + 0, // Skip to: 17205 + /* 3512 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 118, + 53, + 0, // Skip to: 17205 + /* 3519 */ MCD_OPC_Decode, + 209, + 18, + 216, + 1, // Opcode: ROUND_W_D32 + /* 3524 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 3546 + /* 3529 */ MCD_OPC_CheckPredicate, + 57, + 103, + 53, + 0, // Skip to: 17205 + /* 3534 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 96, + 53, + 0, // Skip to: 17205 + /* 3541 */ MCD_OPC_Decode, + 247, + 21, + 216, + 1, // Opcode: TRUNC_W_D32 + /* 3546 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 3568 + /* 3551 */ MCD_OPC_CheckPredicate, + 57, + 81, + 53, + 0, // Skip to: 17205 + /* 3556 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 74, + 53, + 0, // Skip to: 17205 + /* 3563 */ MCD_OPC_Decode, + 159, + 8, + 216, + 1, // Opcode: CEIL_W_D32 + /* 3568 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 3590 + /* 3573 */ MCD_OPC_CheckPredicate, + 57, + 59, + 53, + 0, // Skip to: 17205 + /* 3578 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 52, + 53, + 0, // Skip to: 17205 + /* 3585 */ MCD_OPC_Decode, + 218, + 12, + 216, + 1, // Opcode: FLOOR_W_D32 + /* 3590 */ MCD_OPC_FilterValue, + 17, + 33, + 0, + 0, // Skip to: 3628 + /* 3595 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 3598 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3613 + /* 3603 */ MCD_OPC_CheckPredicate, + 58, + 29, + 53, + 0, // Skip to: 17205 + /* 3608 */ MCD_OPC_Decode, + 162, + 16, + 217, + 1, // Opcode: MOVF_D32 + /* 3613 */ MCD_OPC_FilterValue, + 1, + 19, + 53, + 0, // Skip to: 17205 + /* 3618 */ MCD_OPC_CheckPredicate, + 58, + 14, + 53, + 0, // Skip to: 17205 + /* 3623 */ MCD_OPC_Decode, + 182, + 16, + 217, + 1, // Opcode: MOVT_D32 + /* 3628 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 3643 + /* 3633 */ MCD_OPC_CheckPredicate, + 58, + 255, + 52, + 0, // Skip to: 17205 + /* 3638 */ MCD_OPC_Decode, + 194, + 16, + 218, + 1, // Opcode: MOVZ_I_D32 + /* 3643 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 3658 + /* 3648 */ MCD_OPC_CheckPredicate, + 58, + 240, + 52, + 0, // Skip to: 17205 + /* 3653 */ MCD_OPC_Decode, + 174, + 16, + 218, + 1, // Opcode: MOVN_I_D32 + /* 3658 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 3680 + /* 3663 */ MCD_OPC_CheckPredicate, + 59, + 225, + 52, + 0, // Skip to: 17205 + /* 3668 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 218, + 52, + 0, // Skip to: 17205 + /* 3675 */ MCD_OPC_Decode, + 183, + 18, + 215, + 1, // Opcode: RECIP_D32 + /* 3680 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 3702 + /* 3685 */ MCD_OPC_CheckPredicate, + 59, + 203, + 52, + 0, // Skip to: 17205 + /* 3690 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 196, + 52, + 0, // Skip to: 17205 + /* 3697 */ MCD_OPC_Decode, + 216, + 18, + 215, + 1, // Opcode: RSQRT_D32 + /* 3702 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 3724 + /* 3707 */ MCD_OPC_CheckPredicate, + 55, + 181, + 52, + 0, // Skip to: 17205 + /* 3712 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 174, + 52, + 0, // Skip to: 17205 + /* 3719 */ MCD_OPC_Decode, + 224, + 9, + 216, + 1, // Opcode: CVT_S_D32 + /* 3724 */ MCD_OPC_FilterValue, + 36, + 17, + 0, + 0, // Skip to: 3746 + /* 3729 */ MCD_OPC_CheckPredicate, + 55, + 159, + 52, + 0, // Skip to: 17205 + /* 3734 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 152, + 52, + 0, // Skip to: 17205 + /* 3741 */ MCD_OPC_Decode, + 235, + 9, + 216, + 1, // Opcode: CVT_W_D32 + /* 3746 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 3768 + /* 3751 */ MCD_OPC_CheckPredicate, + 56, + 137, + 52, + 0, // Skip to: 17205 + /* 3756 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 130, + 52, + 0, // Skip to: 17205 + /* 3763 */ MCD_OPC_Decode, + 215, + 9, + 219, + 1, // Opcode: CVT_L_D64 + /* 3768 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 3790 + /* 3773 */ MCD_OPC_CheckPredicate, + 60, + 115, + 52, + 0, // Skip to: 17205 + /* 3778 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 108, + 52, + 0, // Skip to: 17205 + /* 3785 */ MCD_OPC_Decode, + 248, + 9, + 220, + 1, // Opcode: C_F_D32 + /* 3790 */ MCD_OPC_FilterValue, + 49, + 17, + 0, + 0, // Skip to: 3812 + /* 3795 */ MCD_OPC_CheckPredicate, + 60, + 93, + 52, + 0, // Skip to: 17205 + /* 3800 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 86, + 52, + 0, // Skip to: 17205 + /* 3807 */ MCD_OPC_Decode, + 204, + 10, + 220, + 1, // Opcode: C_UN_D32 + /* 3812 */ MCD_OPC_FilterValue, + 50, + 17, + 0, + 0, // Skip to: 3834 + /* 3817 */ MCD_OPC_CheckPredicate, + 60, + 71, + 52, + 0, // Skip to: 17205 + /* 3822 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 64, + 52, + 0, // Skip to: 17205 + /* 3829 */ MCD_OPC_Decode, + 242, + 9, + 220, + 1, // Opcode: C_EQ_D32 + /* 3834 */ MCD_OPC_FilterValue, + 51, + 17, + 0, + 0, // Skip to: 3856 + /* 3839 */ MCD_OPC_CheckPredicate, + 60, + 49, + 52, + 0, // Skip to: 17205 + /* 3844 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 42, + 52, + 0, // Skip to: 17205 + /* 3851 */ MCD_OPC_Decode, + 186, + 10, + 220, + 1, // Opcode: C_UEQ_D32 + /* 3856 */ MCD_OPC_FilterValue, + 52, + 17, + 0, + 0, // Skip to: 3878 + /* 3861 */ MCD_OPC_CheckPredicate, + 60, + 27, + 52, + 0, // Skip to: 17205 + /* 3866 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 20, + 52, + 0, // Skip to: 17205 + /* 3873 */ MCD_OPC_Decode, + 168, + 10, + 220, + 1, // Opcode: C_OLT_D32 + /* 3878 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 3900 + /* 3883 */ MCD_OPC_CheckPredicate, + 60, + 5, + 52, + 0, // Skip to: 17205 + /* 3888 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 254, + 51, + 0, // Skip to: 17205 + /* 3895 */ MCD_OPC_Decode, + 198, + 10, + 220, + 1, // Opcode: C_ULT_D32 + /* 3900 */ MCD_OPC_FilterValue, + 54, + 17, + 0, + 0, // Skip to: 3922 + /* 3905 */ MCD_OPC_CheckPredicate, + 60, + 239, + 51, + 0, // Skip to: 17205 + /* 3910 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 232, + 51, + 0, // Skip to: 17205 + /* 3917 */ MCD_OPC_Decode, + 162, + 10, + 220, + 1, // Opcode: C_OLE_D32 + /* 3922 */ MCD_OPC_FilterValue, + 55, + 17, + 0, + 0, // Skip to: 3944 + /* 3927 */ MCD_OPC_CheckPredicate, + 60, + 217, + 51, + 0, // Skip to: 17205 + /* 3932 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 210, + 51, + 0, // Skip to: 17205 + /* 3939 */ MCD_OPC_Decode, + 192, + 10, + 220, + 1, // Opcode: C_ULE_D32 + /* 3944 */ MCD_OPC_FilterValue, + 56, + 17, + 0, + 0, // Skip to: 3966 + /* 3949 */ MCD_OPC_CheckPredicate, + 60, + 195, + 51, + 0, // Skip to: 17205 + /* 3954 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 188, + 51, + 0, // Skip to: 17205 + /* 3961 */ MCD_OPC_Decode, + 180, + 10, + 220, + 1, // Opcode: C_SF_D32 + /* 3966 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 3988 + /* 3971 */ MCD_OPC_CheckPredicate, + 60, + 173, + 51, + 0, // Skip to: 17205 + /* 3976 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 166, + 51, + 0, // Skip to: 17205 + /* 3983 */ MCD_OPC_Decode, + 144, + 10, + 220, + 1, // Opcode: C_NGLE_D32 + /* 3988 */ MCD_OPC_FilterValue, + 58, + 17, + 0, + 0, // Skip to: 4010 + /* 3993 */ MCD_OPC_CheckPredicate, + 60, + 151, + 51, + 0, // Skip to: 17205 + /* 3998 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 144, + 51, + 0, // Skip to: 17205 + /* 4005 */ MCD_OPC_Decode, + 174, + 10, + 220, + 1, // Opcode: C_SEQ_D32 + /* 4010 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 4032 + /* 4015 */ MCD_OPC_CheckPredicate, + 60, + 129, + 51, + 0, // Skip to: 17205 + /* 4020 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 122, + 51, + 0, // Skip to: 17205 + /* 4027 */ MCD_OPC_Decode, + 150, + 10, + 220, + 1, // Opcode: C_NGL_D32 + /* 4032 */ MCD_OPC_FilterValue, + 60, + 17, + 0, + 0, // Skip to: 4054 + /* 4037 */ MCD_OPC_CheckPredicate, + 60, + 107, + 51, + 0, // Skip to: 17205 + /* 4042 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 100, + 51, + 0, // Skip to: 17205 + /* 4049 */ MCD_OPC_Decode, + 132, + 10, + 220, + 1, // Opcode: C_LT_D32 + /* 4054 */ MCD_OPC_FilterValue, + 61, + 17, + 0, + 0, // Skip to: 4076 + /* 4059 */ MCD_OPC_CheckPredicate, + 60, + 85, + 51, + 0, // Skip to: 17205 + /* 4064 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 78, + 51, + 0, // Skip to: 17205 + /* 4071 */ MCD_OPC_Decode, + 138, + 10, + 220, + 1, // Opcode: C_NGE_D32 + /* 4076 */ MCD_OPC_FilterValue, + 62, + 17, + 0, + 0, // Skip to: 4098 + /* 4081 */ MCD_OPC_CheckPredicate, + 60, + 63, + 51, + 0, // Skip to: 17205 + /* 4086 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 56, + 51, + 0, // Skip to: 17205 + /* 4093 */ MCD_OPC_Decode, + 254, + 9, + 220, + 1, // Opcode: C_LE_D32 + /* 4098 */ MCD_OPC_FilterValue, + 63, + 46, + 51, + 0, // Skip to: 17205 + /* 4103 */ MCD_OPC_CheckPredicate, + 60, + 41, + 51, + 0, // Skip to: 17205 + /* 4108 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 34, + 51, + 0, // Skip to: 17205 + /* 4115 */ MCD_OPC_Decode, + 156, + 10, + 220, + 1, // Opcode: C_NGT_D32 + /* 4120 */ MCD_OPC_FilterValue, + 20, + 47, + 0, + 0, // Skip to: 4172 + /* 4125 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 4128 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 4150 + /* 4133 */ MCD_OPC_CheckPredicate, + 47, + 11, + 51, + 0, // Skip to: 17205 + /* 4138 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 4, + 51, + 0, // Skip to: 17205 + /* 4145 */ MCD_OPC_Decode, + 232, + 9, + 208, + 1, // Opcode: CVT_S_W + /* 4150 */ MCD_OPC_FilterValue, + 33, + 250, + 50, + 0, // Skip to: 17205 + /* 4155 */ MCD_OPC_CheckPredicate, + 55, + 245, + 50, + 0, // Skip to: 17205 + /* 4160 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 238, + 50, + 0, // Skip to: 17205 + /* 4167 */ MCD_OPC_Decode, + 207, + 9, + 211, + 1, // Opcode: CVT_D32_W + /* 4172 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 4187 + /* 4177 */ MCD_OPC_CheckPredicate, + 30, + 223, + 50, + 0, // Skip to: 17205 + /* 4182 */ MCD_OPC_Decode, + 133, + 8, + 206, + 1, // Opcode: BZ_B + /* 4187 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 4202 + /* 4192 */ MCD_OPC_CheckPredicate, + 30, + 208, + 50, + 0, // Skip to: 17205 + /* 4197 */ MCD_OPC_Decode, + 135, + 8, + 221, + 1, // Opcode: BZ_H + /* 4202 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 4217 + /* 4207 */ MCD_OPC_CheckPredicate, + 30, + 193, + 50, + 0, // Skip to: 17205 + /* 4212 */ MCD_OPC_Decode, + 137, + 8, + 222, + 1, // Opcode: BZ_W + /* 4217 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 4232 + /* 4222 */ MCD_OPC_CheckPredicate, + 30, + 178, + 50, + 0, // Skip to: 17205 + /* 4227 */ MCD_OPC_Decode, + 134, + 8, + 223, + 1, // Opcode: BZ_D + /* 4232 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 4247 + /* 4237 */ MCD_OPC_CheckPredicate, + 30, + 163, + 50, + 0, // Skip to: 17205 + /* 4242 */ MCD_OPC_Decode, + 236, + 7, + 206, + 1, // Opcode: BNZ_B + /* 4247 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 4262 + /* 4252 */ MCD_OPC_CheckPredicate, + 30, + 148, + 50, + 0, // Skip to: 17205 + /* 4257 */ MCD_OPC_Decode, + 238, + 7, + 221, + 1, // Opcode: BNZ_H + /* 4262 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 4277 + /* 4267 */ MCD_OPC_CheckPredicate, + 30, + 133, + 50, + 0, // Skip to: 17205 + /* 4272 */ MCD_OPC_Decode, + 240, + 7, + 222, + 1, // Opcode: BNZ_W + /* 4277 */ MCD_OPC_FilterValue, + 31, + 123, + 50, + 0, // Skip to: 17205 + /* 4282 */ MCD_OPC_CheckPredicate, + 30, + 118, + 50, + 0, // Skip to: 17205 + /* 4287 */ MCD_OPC_Decode, + 237, + 7, + 223, + 1, // Opcode: BNZ_D + /* 4292 */ MCD_OPC_FilterValue, + 18, + 115, + 0, + 0, // Skip to: 4412 + /* 4297 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 4300 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4322 + /* 4305 */ MCD_OPC_CheckPredicate, + 27, + 95, + 50, + 0, // Skip to: 17205 + /* 4310 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 88, + 50, + 0, // Skip to: 17205 + /* 4317 */ MCD_OPC_Decode, + 218, + 15, + 224, + 1, // Opcode: MFC2 + /* 4322 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 4344 + /* 4327 */ MCD_OPC_CheckPredicate, + 27, + 73, + 50, + 0, // Skip to: 17205 + /* 4332 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 66, + 50, + 0, // Skip to: 17205 + /* 4339 */ MCD_OPC_Decode, + 234, + 16, + 225, + 1, // Opcode: MTC2 + /* 4344 */ MCD_OPC_FilterValue, + 8, + 56, + 50, + 0, // Skip to: 17205 + /* 4349 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 4352 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4367 + /* 4357 */ MCD_OPC_CheckPredicate, + 50, + 43, + 50, + 0, // Skip to: 17205 + /* 4362 */ MCD_OPC_Decode, + 225, + 6, + 205, + 1, // Opcode: BC2F + /* 4367 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4382 + /* 4372 */ MCD_OPC_CheckPredicate, + 50, + 28, + 50, + 0, // Skip to: 17205 + /* 4377 */ MCD_OPC_Decode, + 229, + 6, + 205, + 1, // Opcode: BC2T + /* 4382 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 4397 + /* 4387 */ MCD_OPC_CheckPredicate, + 51, + 13, + 50, + 0, // Skip to: 17205 + /* 4392 */ MCD_OPC_Decode, + 226, + 6, + 205, + 1, // Opcode: BC2FL + /* 4397 */ MCD_OPC_FilterValue, + 3, + 3, + 50, + 0, // Skip to: 17205 + /* 4402 */ MCD_OPC_CheckPredicate, + 51, + 254, + 49, + 0, // Skip to: 17205 + /* 4407 */ MCD_OPC_Decode, + 230, + 6, + 205, + 1, // Opcode: BC2TL + /* 4412 */ MCD_OPC_FilterValue, + 19, + 70, + 1, + 0, // Skip to: 4743 + /* 4417 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 4420 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 4488 + /* 4425 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 4428 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4443 + /* 4433 */ MCD_OPC_CheckPredicate, + 50, + 50, + 0, + 0, // Skip to: 4488 + /* 4438 */ MCD_OPC_Decode, + 231, + 6, + 205, + 1, // Opcode: BC3F + /* 4443 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4458 + /* 4448 */ MCD_OPC_CheckPredicate, + 50, + 35, + 0, + 0, // Skip to: 4488 + /* 4453 */ MCD_OPC_Decode, + 233, + 6, + 205, + 1, // Opcode: BC3T + /* 4458 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 4473 + /* 4463 */ MCD_OPC_CheckPredicate, + 51, + 20, + 0, + 0, // Skip to: 4488 + /* 4468 */ MCD_OPC_Decode, + 232, + 6, + 205, + 1, // Opcode: BC3FL + /* 4473 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 4488 + /* 4478 */ MCD_OPC_CheckPredicate, + 51, + 5, + 0, + 0, // Skip to: 4488 + /* 4483 */ MCD_OPC_Decode, + 234, + 6, + 205, + 1, // Opcode: BC3TL + /* 4488 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 4491 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4513 + /* 4496 */ MCD_OPC_CheckPredicate, + 61, + 160, + 49, + 0, // Skip to: 17205 + /* 4501 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 153, + 49, + 0, // Skip to: 17205 + /* 4508 */ MCD_OPC_Decode, + 133, + 15, + 226, + 1, // Opcode: LWXC1 + /* 4513 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 4535 + /* 4518 */ MCD_OPC_CheckPredicate, + 62, + 138, + 49, + 0, // Skip to: 17205 + /* 4523 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 131, + 49, + 0, // Skip to: 17205 + /* 4530 */ MCD_OPC_Decode, + 183, + 14, + 227, + 1, // Opcode: LDXC1 + /* 4535 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 4557 + /* 4540 */ MCD_OPC_CheckPredicate, + 63, + 116, + 49, + 0, // Skip to: 17205 + /* 4545 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 109, + 49, + 0, // Skip to: 17205 + /* 4552 */ MCD_OPC_Decode, + 221, + 14, + 227, + 1, // Opcode: LUXC1 + /* 4557 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 4579 + /* 4562 */ MCD_OPC_CheckPredicate, + 61, + 94, + 49, + 0, // Skip to: 17205 + /* 4567 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 87, + 49, + 0, // Skip to: 17205 + /* 4574 */ MCD_OPC_Decode, + 163, + 21, + 228, + 1, // Opcode: SWXC1 + /* 4579 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 4601 + /* 4584 */ MCD_OPC_CheckPredicate, + 62, + 72, + 49, + 0, // Skip to: 17205 + /* 4589 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 65, + 49, + 0, // Skip to: 17205 + /* 4596 */ MCD_OPC_Decode, + 143, + 19, + 229, + 1, // Opcode: SDXC1 + /* 4601 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 4623 + /* 4606 */ MCD_OPC_CheckPredicate, + 63, + 50, + 49, + 0, // Skip to: 17205 + /* 4611 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 43, + 49, + 0, // Skip to: 17205 + /* 4618 */ MCD_OPC_Decode, + 130, + 21, + 229, + 1, // Opcode: SUXC1 + /* 4623 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 4638 + /* 4628 */ MCD_OPC_CheckPredicate, + 64, + 28, + 49, + 0, // Skip to: 17205 + /* 4633 */ MCD_OPC_Decode, + 174, + 15, + 230, + 1, // Opcode: MADD_S + /* 4638 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 4653 + /* 4643 */ MCD_OPC_CheckPredicate, + 65, + 13, + 49, + 0, // Skip to: 17205 + /* 4648 */ MCD_OPC_Decode, + 166, + 15, + 231, + 1, // Opcode: MADD_D32 + /* 4653 */ MCD_OPC_FilterValue, + 40, + 10, + 0, + 0, // Skip to: 4668 + /* 4658 */ MCD_OPC_CheckPredicate, + 64, + 254, + 48, + 0, // Skip to: 17205 + /* 4663 */ MCD_OPC_Decode, + 225, + 16, + 230, + 1, // Opcode: MSUB_S + /* 4668 */ MCD_OPC_FilterValue, + 41, + 10, + 0, + 0, // Skip to: 4683 + /* 4673 */ MCD_OPC_CheckPredicate, + 65, + 239, + 48, + 0, // Skip to: 17205 + /* 4678 */ MCD_OPC_Decode, + 217, + 16, + 231, + 1, // Opcode: MSUB_D32 + /* 4683 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 4698 + /* 4688 */ MCD_OPC_CheckPredicate, + 66, + 224, + 48, + 0, // Skip to: 17205 + /* 4693 */ MCD_OPC_Decode, + 203, + 17, + 230, + 1, // Opcode: NMADD_S + /* 4698 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 4713 + /* 4703 */ MCD_OPC_CheckPredicate, + 67, + 209, + 48, + 0, // Skip to: 17205 + /* 4708 */ MCD_OPC_Decode, + 200, + 17, + 231, + 1, // Opcode: NMADD_D32 + /* 4713 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 4728 + /* 4718 */ MCD_OPC_CheckPredicate, + 66, + 194, + 48, + 0, // Skip to: 17205 + /* 4723 */ MCD_OPC_Decode, + 208, + 17, + 230, + 1, // Opcode: NMSUB_S + /* 4728 */ MCD_OPC_FilterValue, + 57, + 184, + 48, + 0, // Skip to: 17205 + /* 4733 */ MCD_OPC_CheckPredicate, + 67, + 179, + 48, + 0, // Skip to: 17205 + /* 4738 */ MCD_OPC_Decode, + 205, + 17, + 231, + 1, // Opcode: NMSUB_D32 + /* 4743 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 4758 + /* 4748 */ MCD_OPC_CheckPredicate, + 39, + 164, + 48, + 0, // Skip to: 17205 + /* 4753 */ MCD_OPC_Decode, + 249, + 6, + 190, + 1, // Opcode: BEQL + /* 4758 */ MCD_OPC_FilterValue, + 21, + 107, + 0, + 0, // Skip to: 4870 + /* 4763 */ MCD_OPC_ExtractField, + 0, + 16, // Inst{15-0} ... + /* 4766 */ MCD_OPC_FilterValue, + 123, + 9, + 0, + 0, // Skip to: 4780 + /* 4771 */ MCD_OPC_CheckPredicate, + 19, + 19, + 0, + 0, // Skip to: 4795 + /* 4776 */ MCD_OPC_Decode, + 241, + 12, + 113, // Opcode: FMOV_S_MM + /* 4780 */ MCD_OPC_FilterValue, + 251, + 22, + 9, + 0, + 0, // Skip to: 4795 + /* 4786 */ MCD_OPC_CheckPredicate, + 19, + 4, + 0, + 0, // Skip to: 4795 + /* 4791 */ MCD_OPC_Decode, + 132, + 13, + 113, // Opcode: FNEG_S_MM + /* 4795 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 4798 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 4813 + /* 4803 */ MCD_OPC_CheckPredicate, + 19, + 52, + 0, + 0, // Skip to: 4860 + /* 4808 */ MCD_OPC_Decode, + 151, + 12, + 153, + 1, // Opcode: FADD_S_MM + /* 4813 */ MCD_OPC_FilterValue, + 112, + 10, + 0, + 0, // Skip to: 4828 + /* 4818 */ MCD_OPC_CheckPredicate, + 19, + 37, + 0, + 0, // Skip to: 4860 + /* 4823 */ MCD_OPC_Decode, + 168, + 13, + 153, + 1, // Opcode: FSUB_S_MM + /* 4828 */ MCD_OPC_FilterValue, + 176, + 1, + 10, + 0, + 0, // Skip to: 4844 + /* 4834 */ MCD_OPC_CheckPredicate, + 19, + 21, + 0, + 0, // Skip to: 4860 + /* 4839 */ MCD_OPC_Decode, + 252, + 12, + 153, + 1, // Opcode: FMUL_S_MM + /* 4844 */ MCD_OPC_FilterValue, + 240, + 1, + 10, + 0, + 0, // Skip to: 4860 + /* 4850 */ MCD_OPC_CheckPredicate, + 19, + 5, + 0, + 0, // Skip to: 4860 + /* 4855 */ MCD_OPC_Decode, + 189, + 12, + 153, + 1, // Opcode: FDIV_S_MM + /* 4860 */ MCD_OPC_CheckPredicate, + 39, + 52, + 48, + 0, // Skip to: 17205 + /* 4865 */ MCD_OPC_Decode, + 224, + 7, + 190, + 1, // Opcode: BNEL + /* 4870 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 4892 + /* 4875 */ MCD_OPC_CheckPredicate, + 39, + 37, + 48, + 0, // Skip to: 17205 + /* 4880 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 30, + 48, + 0, // Skip to: 17205 + /* 4887 */ MCD_OPC_Decode, + 186, + 7, + 186, + 1, // Opcode: BLEZL + /* 4892 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 4914 + /* 4897 */ MCD_OPC_CheckPredicate, + 39, + 15, + 48, + 0, // Skip to: 17205 + /* 4902 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 8, + 48, + 0, // Skip to: 17205 + /* 4909 */ MCD_OPC_Decode, + 157, + 7, + 186, + 1, // Opcode: BGTZL + /* 4914 */ MCD_OPC_FilterValue, + 28, + 15, + 1, + 0, // Skip to: 5190 + /* 4919 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 4922 */ MCD_OPC_FilterValue, + 0, + 42, + 0, + 0, // Skip to: 4969 + /* 4927 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 4930 */ MCD_OPC_FilterValue, + 0, + 238, + 47, + 0, // Skip to: 17205 + /* 4935 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4938 */ MCD_OPC_FilterValue, + 0, + 230, + 47, + 0, // Skip to: 17205 + /* 4943 */ MCD_OPC_CheckPredicate, + 68, + 11, + 0, + 0, // Skip to: 4959 + /* 4948 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 4959 + /* 4955 */ MCD_OPC_Decode, + 151, + 15, + 69, // Opcode: MADD + /* 4959 */ MCD_OPC_CheckPredicate, + 37, + 209, + 47, + 0, // Skip to: 17205 + /* 4964 */ MCD_OPC_Decode, + 169, + 15, + 232, + 1, // Opcode: MADD_DSP + /* 4969 */ MCD_OPC_FilterValue, + 1, + 42, + 0, + 0, // Skip to: 5016 + /* 4974 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 4977 */ MCD_OPC_FilterValue, + 0, + 191, + 47, + 0, // Skip to: 17205 + /* 4982 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4985 */ MCD_OPC_FilterValue, + 0, + 183, + 47, + 0, // Skip to: 17205 + /* 4990 */ MCD_OPC_CheckPredicate, + 68, + 11, + 0, + 0, // Skip to: 5006 + /* 4995 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 5006 + /* 5002 */ MCD_OPC_Decode, + 158, + 15, + 69, // Opcode: MADDU + /* 5006 */ MCD_OPC_CheckPredicate, + 37, + 162, + 47, + 0, // Skip to: 17205 + /* 5011 */ MCD_OPC_Decode, + 159, + 15, + 232, + 1, // Opcode: MADDU_DSP + /* 5016 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 5037 + /* 5021 */ MCD_OPC_CheckPredicate, + 68, + 147, + 47, + 0, // Skip to: 17205 + /* 5026 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 140, + 47, + 0, // Skip to: 17205 + /* 5033 */ MCD_OPC_Decode, + 141, + 17, + 50, // Opcode: MUL + /* 5037 */ MCD_OPC_FilterValue, + 4, + 42, + 0, + 0, // Skip to: 5084 + /* 5042 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 5045 */ MCD_OPC_FilterValue, + 0, + 123, + 47, + 0, // Skip to: 17205 + /* 5050 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5053 */ MCD_OPC_FilterValue, + 0, + 115, + 47, + 0, // Skip to: 17205 + /* 5058 */ MCD_OPC_CheckPredicate, + 68, + 11, + 0, + 0, // Skip to: 5074 + /* 5063 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 5074 + /* 5070 */ MCD_OPC_Decode, + 202, + 16, + 69, // Opcode: MSUB + /* 5074 */ MCD_OPC_CheckPredicate, + 37, + 94, + 47, + 0, // Skip to: 17205 + /* 5079 */ MCD_OPC_Decode, + 220, + 16, + 232, + 1, // Opcode: MSUB_DSP + /* 5084 */ MCD_OPC_FilterValue, + 5, + 42, + 0, + 0, // Skip to: 5131 + /* 5089 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 5092 */ MCD_OPC_FilterValue, + 0, + 76, + 47, + 0, // Skip to: 17205 + /* 5097 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5100 */ MCD_OPC_FilterValue, + 0, + 68, + 47, + 0, // Skip to: 17205 + /* 5105 */ MCD_OPC_CheckPredicate, + 68, + 11, + 0, + 0, // Skip to: 5121 + /* 5110 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 5121 + /* 5117 */ MCD_OPC_Decode, + 209, + 16, + 69, // Opcode: MSUBU + /* 5121 */ MCD_OPC_CheckPredicate, + 37, + 47, + 47, + 0, // Skip to: 17205 + /* 5126 */ MCD_OPC_Decode, + 210, + 16, + 232, + 1, // Opcode: MSUBU_DSP + /* 5131 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 5153 + /* 5136 */ MCD_OPC_CheckPredicate, + 68, + 32, + 47, + 0, // Skip to: 17205 + /* 5141 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 25, + 47, + 0, // Skip to: 17205 + /* 5148 */ MCD_OPC_Decode, + 222, + 8, + 233, + 1, // Opcode: CLZ + /* 5153 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 5175 + /* 5158 */ MCD_OPC_CheckPredicate, + 68, + 10, + 47, + 0, // Skip to: 17205 + /* 5163 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 3, + 47, + 0, // Skip to: 17205 + /* 5170 */ MCD_OPC_Decode, + 202, + 8, + 233, + 1, // Opcode: CLO + /* 5175 */ MCD_OPC_FilterValue, + 63, + 249, + 46, + 0, // Skip to: 17205 + /* 5180 */ MCD_OPC_CheckPredicate, + 68, + 244, + 46, + 0, // Skip to: 17205 + /* 5185 */ MCD_OPC_Decode, + 253, + 18, + 177, + 1, // Opcode: SDBBP + /* 5190 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 5205 + /* 5195 */ MCD_OPC_CheckPredicate, + 68, + 229, + 46, + 0, // Skip to: 17205 + /* 5200 */ MCD_OPC_Decode, + 252, + 13, + 189, + 1, // Opcode: JALX + /* 5205 */ MCD_OPC_FilterValue, + 30, + 201, + 32, + 0, // Skip to: 13603 + /* 5210 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 5213 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 5281 + /* 5218 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 5221 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5236 + /* 5226 */ MCD_OPC_CheckPredicate, + 30, + 198, + 46, + 0, // Skip to: 17205 + /* 5231 */ MCD_OPC_Decode, + 151, + 6, + 234, + 1, // Opcode: ANDI_B + /* 5236 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5251 + /* 5241 */ MCD_OPC_CheckPredicate, + 30, + 183, + 46, + 0, // Skip to: 17205 + /* 5246 */ MCD_OPC_Decode, + 224, + 17, + 234, + 1, // Opcode: ORI_B + /* 5251 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5266 + /* 5256 */ MCD_OPC_CheckPredicate, + 30, + 168, + 46, + 0, // Skip to: 17205 + /* 5261 */ MCD_OPC_Decode, + 212, + 17, + 234, + 1, // Opcode: NORI_B + /* 5266 */ MCD_OPC_FilterValue, + 3, + 158, + 46, + 0, // Skip to: 17205 + /* 5271 */ MCD_OPC_CheckPredicate, + 30, + 153, + 46, + 0, // Skip to: 17205 + /* 5276 */ MCD_OPC_Decode, + 149, + 22, + 234, + 1, // Opcode: XORI_B + /* 5281 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 5334 + /* 5286 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 5289 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5304 + /* 5294 */ MCD_OPC_CheckPredicate, + 30, + 130, + 46, + 0, // Skip to: 17205 + /* 5299 */ MCD_OPC_Decode, + 207, + 7, + 235, + 1, // Opcode: BMNZI_B + /* 5304 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5319 + /* 5309 */ MCD_OPC_CheckPredicate, + 30, + 115, + 46, + 0, // Skip to: 17205 + /* 5314 */ MCD_OPC_Decode, + 209, + 7, + 235, + 1, // Opcode: BMZI_B + /* 5319 */ MCD_OPC_FilterValue, + 2, + 105, + 46, + 0, // Skip to: 17205 + /* 5324 */ MCD_OPC_CheckPredicate, + 30, + 100, + 46, + 0, // Skip to: 17205 + /* 5329 */ MCD_OPC_Decode, + 251, + 7, + 235, + 1, // Opcode: BSELI_B + /* 5334 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 5387 + /* 5339 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 5342 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5357 + /* 5347 */ MCD_OPC_CheckPredicate, + 30, + 77, + 46, + 0, // Skip to: 17205 + /* 5352 */ MCD_OPC_Decode, + 177, + 19, + 234, + 1, // Opcode: SHF_B + /* 5357 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5372 + /* 5362 */ MCD_OPC_CheckPredicate, + 30, + 62, + 46, + 0, // Skip to: 17205 + /* 5367 */ MCD_OPC_Decode, + 178, + 19, + 236, + 1, // Opcode: SHF_H + /* 5372 */ MCD_OPC_FilterValue, + 2, + 52, + 46, + 0, // Skip to: 17205 + /* 5377 */ MCD_OPC_CheckPredicate, + 30, + 47, + 46, + 0, // Skip to: 17205 + /* 5382 */ MCD_OPC_Decode, + 179, + 19, + 237, + 1, // Opcode: SHF_W + /* 5387 */ MCD_OPC_FilterValue, + 6, + 107, + 1, + 0, // Skip to: 5755 + /* 5392 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 5395 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5410 + /* 5400 */ MCD_OPC_CheckPredicate, + 30, + 24, + 46, + 0, // Skip to: 17205 + /* 5405 */ MCD_OPC_Decode, + 247, + 5, + 238, + 1, // Opcode: ADDVI_B + /* 5410 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5425 + /* 5415 */ MCD_OPC_CheckPredicate, + 30, + 9, + 46, + 0, // Skip to: 17205 + /* 5420 */ MCD_OPC_Decode, + 249, + 5, + 239, + 1, // Opcode: ADDVI_H + /* 5425 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5440 + /* 5430 */ MCD_OPC_CheckPredicate, + 30, + 250, + 45, + 0, // Skip to: 17205 + /* 5435 */ MCD_OPC_Decode, + 250, + 5, + 240, + 1, // Opcode: ADDVI_W + /* 5440 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 5455 + /* 5445 */ MCD_OPC_CheckPredicate, + 30, + 235, + 45, + 0, // Skip to: 17205 + /* 5450 */ MCD_OPC_Decode, + 248, + 5, + 241, + 1, // Opcode: ADDVI_D + /* 5455 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 5470 + /* 5460 */ MCD_OPC_CheckPredicate, + 30, + 220, + 45, + 0, // Skip to: 17205 + /* 5465 */ MCD_OPC_Decode, + 246, + 20, + 238, + 1, // Opcode: SUBVI_B + /* 5470 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 5485 + /* 5475 */ MCD_OPC_CheckPredicate, + 30, + 205, + 45, + 0, // Skip to: 17205 + /* 5480 */ MCD_OPC_Decode, + 248, + 20, + 239, + 1, // Opcode: SUBVI_H + /* 5485 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 5500 + /* 5490 */ MCD_OPC_CheckPredicate, + 30, + 190, + 45, + 0, // Skip to: 17205 + /* 5495 */ MCD_OPC_Decode, + 249, + 20, + 240, + 1, // Opcode: SUBVI_W + /* 5500 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 5515 + /* 5505 */ MCD_OPC_CheckPredicate, + 30, + 175, + 45, + 0, // Skip to: 17205 + /* 5510 */ MCD_OPC_Decode, + 247, + 20, + 241, + 1, // Opcode: SUBVI_D + /* 5515 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 5530 + /* 5520 */ MCD_OPC_CheckPredicate, + 30, + 160, + 45, + 0, // Skip to: 17205 + /* 5525 */ MCD_OPC_Decode, + 188, + 15, + 238, + 1, // Opcode: MAXI_S_B + /* 5530 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 5545 + /* 5535 */ MCD_OPC_CheckPredicate, + 30, + 145, + 45, + 0, // Skip to: 17205 + /* 5540 */ MCD_OPC_Decode, + 190, + 15, + 239, + 1, // Opcode: MAXI_S_H + /* 5545 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 5560 + /* 5550 */ MCD_OPC_CheckPredicate, + 30, + 130, + 45, + 0, // Skip to: 17205 + /* 5555 */ MCD_OPC_Decode, + 191, + 15, + 240, + 1, // Opcode: MAXI_S_W + /* 5560 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 5575 + /* 5565 */ MCD_OPC_CheckPredicate, + 30, + 115, + 45, + 0, // Skip to: 17205 + /* 5570 */ MCD_OPC_Decode, + 189, + 15, + 241, + 1, // Opcode: MAXI_S_D + /* 5575 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 5590 + /* 5580 */ MCD_OPC_CheckPredicate, + 30, + 100, + 45, + 0, // Skip to: 17205 + /* 5585 */ MCD_OPC_Decode, + 192, + 15, + 238, + 1, // Opcode: MAXI_U_B + /* 5590 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5605 + /* 5595 */ MCD_OPC_CheckPredicate, + 30, + 85, + 45, + 0, // Skip to: 17205 + /* 5600 */ MCD_OPC_Decode, + 194, + 15, + 239, + 1, // Opcode: MAXI_U_H + /* 5605 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 5620 + /* 5610 */ MCD_OPC_CheckPredicate, + 30, + 70, + 45, + 0, // Skip to: 17205 + /* 5615 */ MCD_OPC_Decode, + 195, + 15, + 240, + 1, // Opcode: MAXI_U_W + /* 5620 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5635 + /* 5625 */ MCD_OPC_CheckPredicate, + 30, + 55, + 45, + 0, // Skip to: 17205 + /* 5630 */ MCD_OPC_Decode, + 193, + 15, + 241, + 1, // Opcode: MAXI_U_D + /* 5635 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 5650 + /* 5640 */ MCD_OPC_CheckPredicate, + 30, + 40, + 45, + 0, // Skip to: 17205 + /* 5645 */ MCD_OPC_Decode, + 247, + 15, + 238, + 1, // Opcode: MINI_S_B + /* 5650 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 5665 + /* 5655 */ MCD_OPC_CheckPredicate, + 30, + 25, + 45, + 0, // Skip to: 17205 + /* 5660 */ MCD_OPC_Decode, + 249, + 15, + 239, + 1, // Opcode: MINI_S_H + /* 5665 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 5680 + /* 5670 */ MCD_OPC_CheckPredicate, + 30, + 10, + 45, + 0, // Skip to: 17205 + /* 5675 */ MCD_OPC_Decode, + 250, + 15, + 240, + 1, // Opcode: MINI_S_W + /* 5680 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 5695 + /* 5685 */ MCD_OPC_CheckPredicate, + 30, + 251, + 44, + 0, // Skip to: 17205 + /* 5690 */ MCD_OPC_Decode, + 248, + 15, + 241, + 1, // Opcode: MINI_S_D + /* 5695 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 5710 + /* 5700 */ MCD_OPC_CheckPredicate, + 30, + 236, + 44, + 0, // Skip to: 17205 + /* 5705 */ MCD_OPC_Decode, + 251, + 15, + 238, + 1, // Opcode: MINI_U_B + /* 5710 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 5725 + /* 5715 */ MCD_OPC_CheckPredicate, + 30, + 221, + 44, + 0, // Skip to: 17205 + /* 5720 */ MCD_OPC_Decode, + 253, + 15, + 239, + 1, // Opcode: MINI_U_H + /* 5725 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 5740 + /* 5730 */ MCD_OPC_CheckPredicate, + 30, + 206, + 44, + 0, // Skip to: 17205 + /* 5735 */ MCD_OPC_Decode, + 254, + 15, + 240, + 1, // Opcode: MINI_U_W + /* 5740 */ MCD_OPC_FilterValue, + 23, + 196, + 44, + 0, // Skip to: 17205 + /* 5745 */ MCD_OPC_CheckPredicate, + 30, + 191, + 44, + 0, // Skip to: 17205 + /* 5750 */ MCD_OPC_Decode, + 252, + 15, + 241, + 1, // Opcode: MINI_U_D + /* 5755 */ MCD_OPC_FilterValue, + 7, + 107, + 1, + 0, // Skip to: 6123 + /* 5760 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 5763 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5778 + /* 5768 */ MCD_OPC_CheckPredicate, + 30, + 168, + 44, + 0, // Skip to: 17205 + /* 5773 */ MCD_OPC_Decode, + 166, + 8, + 238, + 1, // Opcode: CEQI_B + /* 5778 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5793 + /* 5783 */ MCD_OPC_CheckPredicate, + 30, + 153, + 44, + 0, // Skip to: 17205 + /* 5788 */ MCD_OPC_Decode, + 168, + 8, + 239, + 1, // Opcode: CEQI_H + /* 5793 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5808 + /* 5798 */ MCD_OPC_CheckPredicate, + 30, + 138, + 44, + 0, // Skip to: 17205 + /* 5803 */ MCD_OPC_Decode, + 169, + 8, + 240, + 1, // Opcode: CEQI_W + /* 5808 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 5823 + /* 5813 */ MCD_OPC_CheckPredicate, + 30, + 123, + 44, + 0, // Skip to: 17205 + /* 5818 */ MCD_OPC_Decode, + 167, + 8, + 241, + 1, // Opcode: CEQI_D + /* 5823 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 5838 + /* 5828 */ MCD_OPC_CheckPredicate, + 30, + 108, + 44, + 0, // Skip to: 17205 + /* 5833 */ MCD_OPC_Decode, + 206, + 8, + 238, + 1, // Opcode: CLTI_S_B + /* 5838 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 5853 + /* 5843 */ MCD_OPC_CheckPredicate, + 30, + 93, + 44, + 0, // Skip to: 17205 + /* 5848 */ MCD_OPC_Decode, + 208, + 8, + 239, + 1, // Opcode: CLTI_S_H + /* 5853 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 5868 + /* 5858 */ MCD_OPC_CheckPredicate, + 30, + 78, + 44, + 0, // Skip to: 17205 + /* 5863 */ MCD_OPC_Decode, + 209, + 8, + 240, + 1, // Opcode: CLTI_S_W + /* 5868 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 5883 + /* 5873 */ MCD_OPC_CheckPredicate, + 30, + 63, + 44, + 0, // Skip to: 17205 + /* 5878 */ MCD_OPC_Decode, + 207, + 8, + 241, + 1, // Opcode: CLTI_S_D + /* 5883 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 5898 + /* 5888 */ MCD_OPC_CheckPredicate, + 30, + 48, + 44, + 0, // Skip to: 17205 + /* 5893 */ MCD_OPC_Decode, + 210, + 8, + 238, + 1, // Opcode: CLTI_U_B + /* 5898 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5913 + /* 5903 */ MCD_OPC_CheckPredicate, + 30, + 33, + 44, + 0, // Skip to: 17205 + /* 5908 */ MCD_OPC_Decode, + 212, + 8, + 239, + 1, // Opcode: CLTI_U_H + /* 5913 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 5928 + /* 5918 */ MCD_OPC_CheckPredicate, + 30, + 18, + 44, + 0, // Skip to: 17205 + /* 5923 */ MCD_OPC_Decode, + 213, + 8, + 240, + 1, // Opcode: CLTI_U_W + /* 5928 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5943 + /* 5933 */ MCD_OPC_CheckPredicate, + 30, + 3, + 44, + 0, // Skip to: 17205 + /* 5938 */ MCD_OPC_Decode, + 211, + 8, + 241, + 1, // Opcode: CLTI_U_D + /* 5943 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 5958 + /* 5948 */ MCD_OPC_CheckPredicate, + 30, + 244, + 43, + 0, // Skip to: 17205 + /* 5953 */ MCD_OPC_Decode, + 186, + 8, + 238, + 1, // Opcode: CLEI_S_B + /* 5958 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 5973 + /* 5963 */ MCD_OPC_CheckPredicate, + 30, + 229, + 43, + 0, // Skip to: 17205 + /* 5968 */ MCD_OPC_Decode, + 188, + 8, + 239, + 1, // Opcode: CLEI_S_H + /* 5973 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 5988 + /* 5978 */ MCD_OPC_CheckPredicate, + 30, + 214, + 43, + 0, // Skip to: 17205 + /* 5983 */ MCD_OPC_Decode, + 189, + 8, + 240, + 1, // Opcode: CLEI_S_W + /* 5988 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 6003 + /* 5993 */ MCD_OPC_CheckPredicate, + 30, + 199, + 43, + 0, // Skip to: 17205 + /* 5998 */ MCD_OPC_Decode, + 187, + 8, + 241, + 1, // Opcode: CLEI_S_D + /* 6003 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 6018 + /* 6008 */ MCD_OPC_CheckPredicate, + 30, + 184, + 43, + 0, // Skip to: 17205 + /* 6013 */ MCD_OPC_Decode, + 190, + 8, + 238, + 1, // Opcode: CLEI_U_B + /* 6018 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 6033 + /* 6023 */ MCD_OPC_CheckPredicate, + 30, + 169, + 43, + 0, // Skip to: 17205 + /* 6028 */ MCD_OPC_Decode, + 192, + 8, + 239, + 1, // Opcode: CLEI_U_H + /* 6033 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 6048 + /* 6038 */ MCD_OPC_CheckPredicate, + 30, + 154, + 43, + 0, // Skip to: 17205 + /* 6043 */ MCD_OPC_Decode, + 193, + 8, + 240, + 1, // Opcode: CLEI_U_W + /* 6048 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 6063 + /* 6053 */ MCD_OPC_CheckPredicate, + 30, + 139, + 43, + 0, // Skip to: 17205 + /* 6058 */ MCD_OPC_Decode, + 191, + 8, + 241, + 1, // Opcode: CLEI_U_D + /* 6063 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 6078 + /* 6068 */ MCD_OPC_CheckPredicate, + 30, + 124, + 43, + 0, // Skip to: 17205 + /* 6073 */ MCD_OPC_Decode, + 176, + 14, + 242, + 1, // Opcode: LDI_B + /* 6078 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 6093 + /* 6083 */ MCD_OPC_CheckPredicate, + 30, + 109, + 43, + 0, // Skip to: 17205 + /* 6088 */ MCD_OPC_Decode, + 178, + 14, + 243, + 1, // Opcode: LDI_H + /* 6093 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 6108 + /* 6098 */ MCD_OPC_CheckPredicate, + 30, + 94, + 43, + 0, // Skip to: 17205 + /* 6103 */ MCD_OPC_Decode, + 179, + 14, + 244, + 1, // Opcode: LDI_W + /* 6108 */ MCD_OPC_FilterValue, + 27, + 84, + 43, + 0, // Skip to: 17205 + /* 6113 */ MCD_OPC_CheckPredicate, + 30, + 79, + 43, + 0, // Skip to: 17205 + /* 6118 */ MCD_OPC_Decode, + 177, + 14, + 245, + 1, // Opcode: LDI_D + /* 6123 */ MCD_OPC_FilterValue, + 9, + 155, + 2, + 0, // Skip to: 6795 + /* 6128 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 6131 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6146 + /* 6136 */ MCD_OPC_CheckPredicate, + 30, + 56, + 43, + 0, // Skip to: 17205 + /* 6141 */ MCD_OPC_Decode, + 246, + 19, + 246, + 1, // Opcode: SLLI_D + /* 6146 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 6214 + /* 6151 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6154 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6169 + /* 6159 */ MCD_OPC_CheckPredicate, + 30, + 33, + 43, + 0, // Skip to: 17205 + /* 6164 */ MCD_OPC_Decode, + 248, + 19, + 240, + 1, // Opcode: SLLI_W + /* 6169 */ MCD_OPC_FilterValue, + 1, + 23, + 43, + 0, // Skip to: 17205 + /* 6174 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6177 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6192 + /* 6182 */ MCD_OPC_CheckPredicate, + 30, + 10, + 43, + 0, // Skip to: 17205 + /* 6187 */ MCD_OPC_Decode, + 247, + 19, + 247, + 1, // Opcode: SLLI_H + /* 6192 */ MCD_OPC_FilterValue, + 1, + 0, + 43, + 0, // Skip to: 17205 + /* 6197 */ MCD_OPC_CheckPredicate, + 30, + 251, + 42, + 0, // Skip to: 17205 + /* 6202 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 244, + 42, + 0, // Skip to: 17205 + /* 6209 */ MCD_OPC_Decode, + 245, + 19, + 248, + 1, // Opcode: SLLI_B + /* 6214 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6229 + /* 6219 */ MCD_OPC_CheckPredicate, + 30, + 229, + 42, + 0, // Skip to: 17205 + /* 6224 */ MCD_OPC_Decode, + 153, + 20, + 246, + 1, // Opcode: SRAI_D + /* 6229 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 6297 + /* 6234 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6237 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6252 + /* 6242 */ MCD_OPC_CheckPredicate, + 30, + 206, + 42, + 0, // Skip to: 17205 + /* 6247 */ MCD_OPC_Decode, + 155, + 20, + 240, + 1, // Opcode: SRAI_W + /* 6252 */ MCD_OPC_FilterValue, + 1, + 196, + 42, + 0, // Skip to: 17205 + /* 6257 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6260 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6275 + /* 6265 */ MCD_OPC_CheckPredicate, + 30, + 183, + 42, + 0, // Skip to: 17205 + /* 6270 */ MCD_OPC_Decode, + 154, + 20, + 247, + 1, // Opcode: SRAI_H + /* 6275 */ MCD_OPC_FilterValue, + 1, + 173, + 42, + 0, // Skip to: 17205 + /* 6280 */ MCD_OPC_CheckPredicate, + 30, + 168, + 42, + 0, // Skip to: 17205 + /* 6285 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 161, + 42, + 0, // Skip to: 17205 + /* 6292 */ MCD_OPC_Decode, + 152, + 20, + 248, + 1, // Opcode: SRAI_B + /* 6297 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 6312 + /* 6302 */ MCD_OPC_CheckPredicate, + 30, + 146, + 42, + 0, // Skip to: 17205 + /* 6307 */ MCD_OPC_Decode, + 175, + 20, + 246, + 1, // Opcode: SRLI_D + /* 6312 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 6380 + /* 6317 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6320 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6335 + /* 6325 */ MCD_OPC_CheckPredicate, + 30, + 123, + 42, + 0, // Skip to: 17205 + /* 6330 */ MCD_OPC_Decode, + 177, + 20, + 240, + 1, // Opcode: SRLI_W + /* 6335 */ MCD_OPC_FilterValue, + 1, + 113, + 42, + 0, // Skip to: 17205 + /* 6340 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6343 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6358 + /* 6348 */ MCD_OPC_CheckPredicate, + 30, + 100, + 42, + 0, // Skip to: 17205 + /* 6353 */ MCD_OPC_Decode, + 176, + 20, + 247, + 1, // Opcode: SRLI_H + /* 6358 */ MCD_OPC_FilterValue, + 1, + 90, + 42, + 0, // Skip to: 17205 + /* 6363 */ MCD_OPC_CheckPredicate, + 30, + 85, + 42, + 0, // Skip to: 17205 + /* 6368 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 78, + 42, + 0, // Skip to: 17205 + /* 6375 */ MCD_OPC_Decode, + 174, + 20, + 248, + 1, // Opcode: SRLI_B + /* 6380 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 6395 + /* 6385 */ MCD_OPC_CheckPredicate, + 30, + 63, + 42, + 0, // Skip to: 17205 + /* 6390 */ MCD_OPC_Decode, + 236, + 6, + 246, + 1, // Opcode: BCLRI_D + /* 6395 */ MCD_OPC_FilterValue, + 7, + 63, + 0, + 0, // Skip to: 6463 + /* 6400 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6403 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6418 + /* 6408 */ MCD_OPC_CheckPredicate, + 30, + 40, + 42, + 0, // Skip to: 17205 + /* 6413 */ MCD_OPC_Decode, + 238, + 6, + 240, + 1, // Opcode: BCLRI_W + /* 6418 */ MCD_OPC_FilterValue, + 1, + 30, + 42, + 0, // Skip to: 17205 + /* 6423 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6426 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6441 + /* 6431 */ MCD_OPC_CheckPredicate, + 30, + 17, + 42, + 0, // Skip to: 17205 + /* 6436 */ MCD_OPC_Decode, + 237, + 6, + 247, + 1, // Opcode: BCLRI_H + /* 6441 */ MCD_OPC_FilterValue, + 1, + 7, + 42, + 0, // Skip to: 17205 + /* 6446 */ MCD_OPC_CheckPredicate, + 30, + 2, + 42, + 0, // Skip to: 17205 + /* 6451 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 251, + 41, + 0, // Skip to: 17205 + /* 6458 */ MCD_OPC_Decode, + 235, + 6, + 248, + 1, // Opcode: BCLRI_B + /* 6463 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 6478 + /* 6468 */ MCD_OPC_CheckPredicate, + 30, + 236, + 41, + 0, // Skip to: 17205 + /* 6473 */ MCD_OPC_Decode, + 254, + 7, + 246, + 1, // Opcode: BSETI_D + /* 6478 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 6546 + /* 6483 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6486 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6501 + /* 6491 */ MCD_OPC_CheckPredicate, + 30, + 213, + 41, + 0, // Skip to: 17205 + /* 6496 */ MCD_OPC_Decode, + 128, + 8, + 240, + 1, // Opcode: BSETI_W + /* 6501 */ MCD_OPC_FilterValue, + 1, + 203, + 41, + 0, // Skip to: 17205 + /* 6506 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6509 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6524 + /* 6514 */ MCD_OPC_CheckPredicate, + 30, + 190, + 41, + 0, // Skip to: 17205 + /* 6519 */ MCD_OPC_Decode, + 255, + 7, + 247, + 1, // Opcode: BSETI_H + /* 6524 */ MCD_OPC_FilterValue, + 1, + 180, + 41, + 0, // Skip to: 17205 + /* 6529 */ MCD_OPC_CheckPredicate, + 30, + 175, + 41, + 0, // Skip to: 17205 + /* 6534 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 168, + 41, + 0, // Skip to: 17205 + /* 6541 */ MCD_OPC_Decode, + 253, + 7, + 248, + 1, // Opcode: BSETI_B + /* 6546 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 6561 + /* 6551 */ MCD_OPC_CheckPredicate, + 30, + 153, + 41, + 0, // Skip to: 17205 + /* 6556 */ MCD_OPC_Decode, + 217, + 7, + 246, + 1, // Opcode: BNEGI_D + /* 6561 */ MCD_OPC_FilterValue, + 11, + 63, + 0, + 0, // Skip to: 6629 + /* 6566 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6569 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6584 + /* 6574 */ MCD_OPC_CheckPredicate, + 30, + 130, + 41, + 0, // Skip to: 17205 + /* 6579 */ MCD_OPC_Decode, + 219, + 7, + 240, + 1, // Opcode: BNEGI_W + /* 6584 */ MCD_OPC_FilterValue, + 1, + 120, + 41, + 0, // Skip to: 17205 + /* 6589 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6592 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6607 + /* 6597 */ MCD_OPC_CheckPredicate, + 30, + 107, + 41, + 0, // Skip to: 17205 + /* 6602 */ MCD_OPC_Decode, + 218, + 7, + 247, + 1, // Opcode: BNEGI_H + /* 6607 */ MCD_OPC_FilterValue, + 1, + 97, + 41, + 0, // Skip to: 17205 + /* 6612 */ MCD_OPC_CheckPredicate, + 30, + 92, + 41, + 0, // Skip to: 17205 + /* 6617 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 85, + 41, + 0, // Skip to: 17205 + /* 6624 */ MCD_OPC_Decode, + 216, + 7, + 248, + 1, // Opcode: BNEGI_B + /* 6629 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 6644 + /* 6634 */ MCD_OPC_CheckPredicate, + 30, + 70, + 41, + 0, // Skip to: 17205 + /* 6639 */ MCD_OPC_Decode, + 160, + 7, + 249, + 1, // Opcode: BINSLI_D + /* 6644 */ MCD_OPC_FilterValue, + 13, + 63, + 0, + 0, // Skip to: 6712 + /* 6649 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6652 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6667 + /* 6657 */ MCD_OPC_CheckPredicate, + 30, + 47, + 41, + 0, // Skip to: 17205 + /* 6662 */ MCD_OPC_Decode, + 162, + 7, + 250, + 1, // Opcode: BINSLI_W + /* 6667 */ MCD_OPC_FilterValue, + 1, + 37, + 41, + 0, // Skip to: 17205 + /* 6672 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6675 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6690 + /* 6680 */ MCD_OPC_CheckPredicate, + 30, + 24, + 41, + 0, // Skip to: 17205 + /* 6685 */ MCD_OPC_Decode, + 161, + 7, + 251, + 1, // Opcode: BINSLI_H + /* 6690 */ MCD_OPC_FilterValue, + 1, + 14, + 41, + 0, // Skip to: 17205 + /* 6695 */ MCD_OPC_CheckPredicate, + 30, + 9, + 41, + 0, // Skip to: 17205 + /* 6700 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 2, + 41, + 0, // Skip to: 17205 + /* 6707 */ MCD_OPC_Decode, + 159, + 7, + 252, + 1, // Opcode: BINSLI_B + /* 6712 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 6727 + /* 6717 */ MCD_OPC_CheckPredicate, + 30, + 243, + 40, + 0, // Skip to: 17205 + /* 6722 */ MCD_OPC_Decode, + 168, + 7, + 249, + 1, // Opcode: BINSRI_D + /* 6727 */ MCD_OPC_FilterValue, + 15, + 233, + 40, + 0, // Skip to: 17205 + /* 6732 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6735 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6750 + /* 6740 */ MCD_OPC_CheckPredicate, + 30, + 220, + 40, + 0, // Skip to: 17205 + /* 6745 */ MCD_OPC_Decode, + 170, + 7, + 250, + 1, // Opcode: BINSRI_W + /* 6750 */ MCD_OPC_FilterValue, + 1, + 210, + 40, + 0, // Skip to: 17205 + /* 6755 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6758 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6773 + /* 6763 */ MCD_OPC_CheckPredicate, + 30, + 197, + 40, + 0, // Skip to: 17205 + /* 6768 */ MCD_OPC_Decode, + 169, + 7, + 251, + 1, // Opcode: BINSRI_H + /* 6773 */ MCD_OPC_FilterValue, + 1, + 187, + 40, + 0, // Skip to: 17205 + /* 6778 */ MCD_OPC_CheckPredicate, + 30, + 182, + 40, + 0, // Skip to: 17205 + /* 6783 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 175, + 40, + 0, // Skip to: 17205 + /* 6790 */ MCD_OPC_Decode, + 167, + 7, + 252, + 1, // Opcode: BINSRI_B + /* 6795 */ MCD_OPC_FilterValue, + 10, + 79, + 1, + 0, // Skip to: 7135 + /* 6800 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 6803 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6818 + /* 6808 */ MCD_OPC_CheckPredicate, + 30, + 152, + 40, + 0, // Skip to: 17205 + /* 6813 */ MCD_OPC_Decode, + 227, + 18, + 246, + 1, // Opcode: SAT_S_D + /* 6818 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 6886 + /* 6823 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6826 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6841 + /* 6831 */ MCD_OPC_CheckPredicate, + 30, + 129, + 40, + 0, // Skip to: 17205 + /* 6836 */ MCD_OPC_Decode, + 229, + 18, + 240, + 1, // Opcode: SAT_S_W + /* 6841 */ MCD_OPC_FilterValue, + 1, + 119, + 40, + 0, // Skip to: 17205 + /* 6846 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6849 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6864 + /* 6854 */ MCD_OPC_CheckPredicate, + 30, + 106, + 40, + 0, // Skip to: 17205 + /* 6859 */ MCD_OPC_Decode, + 228, + 18, + 247, + 1, // Opcode: SAT_S_H + /* 6864 */ MCD_OPC_FilterValue, + 1, + 96, + 40, + 0, // Skip to: 17205 + /* 6869 */ MCD_OPC_CheckPredicate, + 30, + 91, + 40, + 0, // Skip to: 17205 + /* 6874 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 84, + 40, + 0, // Skip to: 17205 + /* 6881 */ MCD_OPC_Decode, + 226, + 18, + 248, + 1, // Opcode: SAT_S_B + /* 6886 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6901 + /* 6891 */ MCD_OPC_CheckPredicate, + 30, + 69, + 40, + 0, // Skip to: 17205 + /* 6896 */ MCD_OPC_Decode, + 231, + 18, + 246, + 1, // Opcode: SAT_U_D + /* 6901 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 6969 + /* 6906 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6909 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6924 + /* 6914 */ MCD_OPC_CheckPredicate, + 30, + 46, + 40, + 0, // Skip to: 17205 + /* 6919 */ MCD_OPC_Decode, + 233, + 18, + 240, + 1, // Opcode: SAT_U_W + /* 6924 */ MCD_OPC_FilterValue, + 1, + 36, + 40, + 0, // Skip to: 17205 + /* 6929 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6932 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6947 + /* 6937 */ MCD_OPC_CheckPredicate, + 30, + 23, + 40, + 0, // Skip to: 17205 + /* 6942 */ MCD_OPC_Decode, + 232, + 18, + 247, + 1, // Opcode: SAT_U_H + /* 6947 */ MCD_OPC_FilterValue, + 1, + 13, + 40, + 0, // Skip to: 17205 + /* 6952 */ MCD_OPC_CheckPredicate, + 30, + 8, + 40, + 0, // Skip to: 17205 + /* 6957 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 1, + 40, + 0, // Skip to: 17205 + /* 6964 */ MCD_OPC_Decode, + 230, + 18, + 248, + 1, // Opcode: SAT_U_B + /* 6969 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 6984 + /* 6974 */ MCD_OPC_CheckPredicate, + 30, + 242, + 39, + 0, // Skip to: 17205 + /* 6979 */ MCD_OPC_Decode, + 157, + 20, + 246, + 1, // Opcode: SRARI_D + /* 6984 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 7052 + /* 6989 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6992 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7007 + /* 6997 */ MCD_OPC_CheckPredicate, + 30, + 219, + 39, + 0, // Skip to: 17205 + /* 7002 */ MCD_OPC_Decode, + 159, + 20, + 240, + 1, // Opcode: SRARI_W + /* 7007 */ MCD_OPC_FilterValue, + 1, + 209, + 39, + 0, // Skip to: 17205 + /* 7012 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7015 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7030 + /* 7020 */ MCD_OPC_CheckPredicate, + 30, + 196, + 39, + 0, // Skip to: 17205 + /* 7025 */ MCD_OPC_Decode, + 158, + 20, + 247, + 1, // Opcode: SRARI_H + /* 7030 */ MCD_OPC_FilterValue, + 1, + 186, + 39, + 0, // Skip to: 17205 + /* 7035 */ MCD_OPC_CheckPredicate, + 30, + 181, + 39, + 0, // Skip to: 17205 + /* 7040 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 174, + 39, + 0, // Skip to: 17205 + /* 7047 */ MCD_OPC_Decode, + 156, + 20, + 248, + 1, // Opcode: SRARI_B + /* 7052 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 7067 + /* 7057 */ MCD_OPC_CheckPredicate, + 30, + 159, + 39, + 0, // Skip to: 17205 + /* 7062 */ MCD_OPC_Decode, + 179, + 20, + 246, + 1, // Opcode: SRLRI_D + /* 7067 */ MCD_OPC_FilterValue, + 7, + 149, + 39, + 0, // Skip to: 17205 + /* 7072 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 7075 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7090 + /* 7080 */ MCD_OPC_CheckPredicate, + 30, + 136, + 39, + 0, // Skip to: 17205 + /* 7085 */ MCD_OPC_Decode, + 181, + 20, + 240, + 1, // Opcode: SRLRI_W + /* 7090 */ MCD_OPC_FilterValue, + 1, + 126, + 39, + 0, // Skip to: 17205 + /* 7095 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7098 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7113 + /* 7103 */ MCD_OPC_CheckPredicate, + 30, + 113, + 39, + 0, // Skip to: 17205 + /* 7108 */ MCD_OPC_Decode, + 180, + 20, + 247, + 1, // Opcode: SRLRI_H + /* 7113 */ MCD_OPC_FilterValue, + 1, + 103, + 39, + 0, // Skip to: 17205 + /* 7118 */ MCD_OPC_CheckPredicate, + 30, + 98, + 39, + 0, // Skip to: 17205 + /* 7123 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 91, + 39, + 0, // Skip to: 17205 + /* 7130 */ MCD_OPC_Decode, + 178, + 20, + 248, + 1, // Opcode: SRLRI_B + /* 7135 */ MCD_OPC_FilterValue, + 13, + 227, + 1, + 0, // Skip to: 7623 + /* 7140 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 7143 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7158 + /* 7148 */ MCD_OPC_CheckPredicate, + 30, + 68, + 39, + 0, // Skip to: 17205 + /* 7153 */ MCD_OPC_Decode, + 251, + 19, + 253, + 1, // Opcode: SLL_B + /* 7158 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7173 + /* 7163 */ MCD_OPC_CheckPredicate, + 30, + 53, + 39, + 0, // Skip to: 17205 + /* 7168 */ MCD_OPC_Decode, + 253, + 19, + 254, + 1, // Opcode: SLL_H + /* 7173 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7188 + /* 7178 */ MCD_OPC_CheckPredicate, + 30, + 38, + 39, + 0, // Skip to: 17205 + /* 7183 */ MCD_OPC_Decode, + 128, + 20, + 255, + 1, // Opcode: SLL_W + /* 7188 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 7203 + /* 7193 */ MCD_OPC_CheckPredicate, + 30, + 23, + 39, + 0, // Skip to: 17205 + /* 7198 */ MCD_OPC_Decode, + 252, + 19, + 128, + 2, // Opcode: SLL_D + /* 7203 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 7218 + /* 7208 */ MCD_OPC_CheckPredicate, + 30, + 8, + 39, + 0, // Skip to: 17205 + /* 7213 */ MCD_OPC_Decode, + 166, + 20, + 253, + 1, // Opcode: SRA_B + /* 7218 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 7233 + /* 7223 */ MCD_OPC_CheckPredicate, + 30, + 249, + 38, + 0, // Skip to: 17205 + /* 7228 */ MCD_OPC_Decode, + 168, + 20, + 254, + 1, // Opcode: SRA_H + /* 7233 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 7248 + /* 7238 */ MCD_OPC_CheckPredicate, + 30, + 234, + 38, + 0, // Skip to: 17205 + /* 7243 */ MCD_OPC_Decode, + 170, + 20, + 255, + 1, // Opcode: SRA_W + /* 7248 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 7263 + /* 7253 */ MCD_OPC_CheckPredicate, + 30, + 219, + 38, + 0, // Skip to: 17205 + /* 7258 */ MCD_OPC_Decode, + 167, + 20, + 128, + 2, // Opcode: SRA_D + /* 7263 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 7278 + /* 7268 */ MCD_OPC_CheckPredicate, + 30, + 204, + 38, + 0, // Skip to: 17205 + /* 7273 */ MCD_OPC_Decode, + 188, + 20, + 253, + 1, // Opcode: SRL_B + /* 7278 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 7293 + /* 7283 */ MCD_OPC_CheckPredicate, + 30, + 189, + 38, + 0, // Skip to: 17205 + /* 7288 */ MCD_OPC_Decode, + 190, + 20, + 254, + 1, // Opcode: SRL_H + /* 7293 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 7308 + /* 7298 */ MCD_OPC_CheckPredicate, + 30, + 174, + 38, + 0, // Skip to: 17205 + /* 7303 */ MCD_OPC_Decode, + 192, + 20, + 255, + 1, // Opcode: SRL_W + /* 7308 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 7323 + /* 7313 */ MCD_OPC_CheckPredicate, + 30, + 159, + 38, + 0, // Skip to: 17205 + /* 7318 */ MCD_OPC_Decode, + 189, + 20, + 128, + 2, // Opcode: SRL_D + /* 7323 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 7338 + /* 7328 */ MCD_OPC_CheckPredicate, + 30, + 144, + 38, + 0, // Skip to: 17205 + /* 7333 */ MCD_OPC_Decode, + 239, + 6, + 253, + 1, // Opcode: BCLR_B + /* 7338 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 7353 + /* 7343 */ MCD_OPC_CheckPredicate, + 30, + 129, + 38, + 0, // Skip to: 17205 + /* 7348 */ MCD_OPC_Decode, + 241, + 6, + 254, + 1, // Opcode: BCLR_H + /* 7353 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7368 + /* 7358 */ MCD_OPC_CheckPredicate, + 30, + 114, + 38, + 0, // Skip to: 17205 + /* 7363 */ MCD_OPC_Decode, + 242, + 6, + 255, + 1, // Opcode: BCLR_W + /* 7368 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 7383 + /* 7373 */ MCD_OPC_CheckPredicate, + 30, + 99, + 38, + 0, // Skip to: 17205 + /* 7378 */ MCD_OPC_Decode, + 240, + 6, + 128, + 2, // Opcode: BCLR_D + /* 7383 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 7398 + /* 7388 */ MCD_OPC_CheckPredicate, + 30, + 84, + 38, + 0, // Skip to: 17205 + /* 7393 */ MCD_OPC_Decode, + 129, + 8, + 253, + 1, // Opcode: BSET_B + /* 7398 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 7413 + /* 7403 */ MCD_OPC_CheckPredicate, + 30, + 69, + 38, + 0, // Skip to: 17205 + /* 7408 */ MCD_OPC_Decode, + 131, + 8, + 254, + 1, // Opcode: BSET_H + /* 7413 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 7428 + /* 7418 */ MCD_OPC_CheckPredicate, + 30, + 54, + 38, + 0, // Skip to: 17205 + /* 7423 */ MCD_OPC_Decode, + 132, + 8, + 255, + 1, // Opcode: BSET_W + /* 7428 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 7443 + /* 7433 */ MCD_OPC_CheckPredicate, + 30, + 39, + 38, + 0, // Skip to: 17205 + /* 7438 */ MCD_OPC_Decode, + 130, + 8, + 128, + 2, // Opcode: BSET_D + /* 7443 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 7458 + /* 7448 */ MCD_OPC_CheckPredicate, + 30, + 24, + 38, + 0, // Skip to: 17205 + /* 7453 */ MCD_OPC_Decode, + 220, + 7, + 253, + 1, // Opcode: BNEG_B + /* 7458 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 7473 + /* 7463 */ MCD_OPC_CheckPredicate, + 30, + 9, + 38, + 0, // Skip to: 17205 + /* 7468 */ MCD_OPC_Decode, + 222, + 7, + 254, + 1, // Opcode: BNEG_H + /* 7473 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 7488 + /* 7478 */ MCD_OPC_CheckPredicate, + 30, + 250, + 37, + 0, // Skip to: 17205 + /* 7483 */ MCD_OPC_Decode, + 223, + 7, + 255, + 1, // Opcode: BNEG_W + /* 7488 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 7503 + /* 7493 */ MCD_OPC_CheckPredicate, + 30, + 235, + 37, + 0, // Skip to: 17205 + /* 7498 */ MCD_OPC_Decode, + 221, + 7, + 128, + 2, // Opcode: BNEG_D + /* 7503 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 7518 + /* 7508 */ MCD_OPC_CheckPredicate, + 30, + 220, + 37, + 0, // Skip to: 17205 + /* 7513 */ MCD_OPC_Decode, + 163, + 7, + 129, + 2, // Opcode: BINSL_B + /* 7518 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 7533 + /* 7523 */ MCD_OPC_CheckPredicate, + 30, + 205, + 37, + 0, // Skip to: 17205 + /* 7528 */ MCD_OPC_Decode, + 165, + 7, + 130, + 2, // Opcode: BINSL_H + /* 7533 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 7548 + /* 7538 */ MCD_OPC_CheckPredicate, + 30, + 190, + 37, + 0, // Skip to: 17205 + /* 7543 */ MCD_OPC_Decode, + 166, + 7, + 131, + 2, // Opcode: BINSL_W + /* 7548 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 7563 + /* 7553 */ MCD_OPC_CheckPredicate, + 30, + 175, + 37, + 0, // Skip to: 17205 + /* 7558 */ MCD_OPC_Decode, + 164, + 7, + 132, + 2, // Opcode: BINSL_D + /* 7563 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 7578 + /* 7568 */ MCD_OPC_CheckPredicate, + 30, + 160, + 37, + 0, // Skip to: 17205 + /* 7573 */ MCD_OPC_Decode, + 171, + 7, + 129, + 2, // Opcode: BINSR_B + /* 7578 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 7593 + /* 7583 */ MCD_OPC_CheckPredicate, + 30, + 145, + 37, + 0, // Skip to: 17205 + /* 7588 */ MCD_OPC_Decode, + 173, + 7, + 130, + 2, // Opcode: BINSR_H + /* 7593 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 7608 + /* 7598 */ MCD_OPC_CheckPredicate, + 30, + 130, + 37, + 0, // Skip to: 17205 + /* 7603 */ MCD_OPC_Decode, + 174, + 7, + 131, + 2, // Opcode: BINSR_W + /* 7608 */ MCD_OPC_FilterValue, + 31, + 120, + 37, + 0, // Skip to: 17205 + /* 7613 */ MCD_OPC_CheckPredicate, + 30, + 115, + 37, + 0, // Skip to: 17205 + /* 7618 */ MCD_OPC_Decode, + 172, + 7, + 132, + 2, // Opcode: BINSR_D + /* 7623 */ MCD_OPC_FilterValue, + 14, + 227, + 1, + 0, // Skip to: 8111 + /* 7628 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 7631 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7646 + /* 7636 */ MCD_OPC_CheckPredicate, + 30, + 92, + 37, + 0, // Skip to: 17205 + /* 7641 */ MCD_OPC_Decode, + 251, + 5, + 253, + 1, // Opcode: ADDV_B + /* 7646 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7661 + /* 7651 */ MCD_OPC_CheckPredicate, + 30, + 77, + 37, + 0, // Skip to: 17205 + /* 7656 */ MCD_OPC_Decode, + 253, + 5, + 254, + 1, // Opcode: ADDV_H + /* 7661 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7676 + /* 7666 */ MCD_OPC_CheckPredicate, + 30, + 62, + 37, + 0, // Skip to: 17205 + /* 7671 */ MCD_OPC_Decode, + 254, + 5, + 255, + 1, // Opcode: ADDV_W + /* 7676 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 7691 + /* 7681 */ MCD_OPC_CheckPredicate, + 30, + 47, + 37, + 0, // Skip to: 17205 + /* 7686 */ MCD_OPC_Decode, + 252, + 5, + 128, + 2, // Opcode: ADDV_D + /* 7691 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 7706 + /* 7696 */ MCD_OPC_CheckPredicate, + 30, + 32, + 37, + 0, // Skip to: 17205 + /* 7701 */ MCD_OPC_Decode, + 250, + 20, + 253, + 1, // Opcode: SUBV_B + /* 7706 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 7721 + /* 7711 */ MCD_OPC_CheckPredicate, + 30, + 17, + 37, + 0, // Skip to: 17205 + /* 7716 */ MCD_OPC_Decode, + 252, + 20, + 254, + 1, // Opcode: SUBV_H + /* 7721 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 7736 + /* 7726 */ MCD_OPC_CheckPredicate, + 30, + 2, + 37, + 0, // Skip to: 17205 + /* 7731 */ MCD_OPC_Decode, + 253, + 20, + 255, + 1, // Opcode: SUBV_W + /* 7736 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 7751 + /* 7741 */ MCD_OPC_CheckPredicate, + 30, + 243, + 36, + 0, // Skip to: 17205 + /* 7746 */ MCD_OPC_Decode, + 251, + 20, + 128, + 2, // Opcode: SUBV_D + /* 7751 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 7766 + /* 7756 */ MCD_OPC_CheckPredicate, + 30, + 228, + 36, + 0, // Skip to: 17205 + /* 7761 */ MCD_OPC_Decode, + 203, + 15, + 253, + 1, // Opcode: MAX_S_B + /* 7766 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 7781 + /* 7771 */ MCD_OPC_CheckPredicate, + 30, + 213, + 36, + 0, // Skip to: 17205 + /* 7776 */ MCD_OPC_Decode, + 205, + 15, + 254, + 1, // Opcode: MAX_S_H + /* 7781 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 7796 + /* 7786 */ MCD_OPC_CheckPredicate, + 30, + 198, + 36, + 0, // Skip to: 17205 + /* 7791 */ MCD_OPC_Decode, + 207, + 15, + 255, + 1, // Opcode: MAX_S_W + /* 7796 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 7811 + /* 7801 */ MCD_OPC_CheckPredicate, + 30, + 183, + 36, + 0, // Skip to: 17205 + /* 7806 */ MCD_OPC_Decode, + 204, + 15, + 128, + 2, // Opcode: MAX_S_D + /* 7811 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 7826 + /* 7816 */ MCD_OPC_CheckPredicate, + 30, + 168, + 36, + 0, // Skip to: 17205 + /* 7821 */ MCD_OPC_Decode, + 208, + 15, + 253, + 1, // Opcode: MAX_U_B + /* 7826 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 7841 + /* 7831 */ MCD_OPC_CheckPredicate, + 30, + 153, + 36, + 0, // Skip to: 17205 + /* 7836 */ MCD_OPC_Decode, + 210, + 15, + 254, + 1, // Opcode: MAX_U_H + /* 7841 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7856 + /* 7846 */ MCD_OPC_CheckPredicate, + 30, + 138, + 36, + 0, // Skip to: 17205 + /* 7851 */ MCD_OPC_Decode, + 211, + 15, + 255, + 1, // Opcode: MAX_U_W + /* 7856 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 7871 + /* 7861 */ MCD_OPC_CheckPredicate, + 30, + 123, + 36, + 0, // Skip to: 17205 + /* 7866 */ MCD_OPC_Decode, + 209, + 15, + 128, + 2, // Opcode: MAX_U_D + /* 7871 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 7886 + /* 7876 */ MCD_OPC_CheckPredicate, + 30, + 108, + 36, + 0, // Skip to: 17205 + /* 7881 */ MCD_OPC_Decode, + 134, + 16, + 253, + 1, // Opcode: MIN_S_B + /* 7886 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 7901 + /* 7891 */ MCD_OPC_CheckPredicate, + 30, + 93, + 36, + 0, // Skip to: 17205 + /* 7896 */ MCD_OPC_Decode, + 136, + 16, + 254, + 1, // Opcode: MIN_S_H + /* 7901 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 7916 + /* 7906 */ MCD_OPC_CheckPredicate, + 30, + 78, + 36, + 0, // Skip to: 17205 + /* 7911 */ MCD_OPC_Decode, + 138, + 16, + 255, + 1, // Opcode: MIN_S_W + /* 7916 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 7931 + /* 7921 */ MCD_OPC_CheckPredicate, + 30, + 63, + 36, + 0, // Skip to: 17205 + /* 7926 */ MCD_OPC_Decode, + 135, + 16, + 128, + 2, // Opcode: MIN_S_D + /* 7931 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 7946 + /* 7936 */ MCD_OPC_CheckPredicate, + 30, + 48, + 36, + 0, // Skip to: 17205 + /* 7941 */ MCD_OPC_Decode, + 139, + 16, + 253, + 1, // Opcode: MIN_U_B + /* 7946 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 7961 + /* 7951 */ MCD_OPC_CheckPredicate, + 30, + 33, + 36, + 0, // Skip to: 17205 + /* 7956 */ MCD_OPC_Decode, + 141, + 16, + 254, + 1, // Opcode: MIN_U_H + /* 7961 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 7976 + /* 7966 */ MCD_OPC_CheckPredicate, + 30, + 18, + 36, + 0, // Skip to: 17205 + /* 7971 */ MCD_OPC_Decode, + 142, + 16, + 255, + 1, // Opcode: MIN_U_W + /* 7976 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 7991 + /* 7981 */ MCD_OPC_CheckPredicate, + 30, + 3, + 36, + 0, // Skip to: 17205 + /* 7986 */ MCD_OPC_Decode, + 140, + 16, + 128, + 2, // Opcode: MIN_U_D + /* 7991 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 8006 + /* 7996 */ MCD_OPC_CheckPredicate, + 30, + 244, + 35, + 0, // Skip to: 17205 + /* 8001 */ MCD_OPC_Decode, + 196, + 15, + 253, + 1, // Opcode: MAX_A_B + /* 8006 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 8021 + /* 8011 */ MCD_OPC_CheckPredicate, + 30, + 229, + 35, + 0, // Skip to: 17205 + /* 8016 */ MCD_OPC_Decode, + 198, + 15, + 254, + 1, // Opcode: MAX_A_H + /* 8021 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 8036 + /* 8026 */ MCD_OPC_CheckPredicate, + 30, + 214, + 35, + 0, // Skip to: 17205 + /* 8031 */ MCD_OPC_Decode, + 199, + 15, + 255, + 1, // Opcode: MAX_A_W + /* 8036 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 8051 + /* 8041 */ MCD_OPC_CheckPredicate, + 30, + 199, + 35, + 0, // Skip to: 17205 + /* 8046 */ MCD_OPC_Decode, + 197, + 15, + 128, + 2, // Opcode: MAX_A_D + /* 8051 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 8066 + /* 8056 */ MCD_OPC_CheckPredicate, + 30, + 184, + 35, + 0, // Skip to: 17205 + /* 8061 */ MCD_OPC_Decode, + 255, + 15, + 253, + 1, // Opcode: MIN_A_B + /* 8066 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 8081 + /* 8071 */ MCD_OPC_CheckPredicate, + 30, + 169, + 35, + 0, // Skip to: 17205 + /* 8076 */ MCD_OPC_Decode, + 129, + 16, + 254, + 1, // Opcode: MIN_A_H + /* 8081 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 8096 + /* 8086 */ MCD_OPC_CheckPredicate, + 30, + 154, + 35, + 0, // Skip to: 17205 + /* 8091 */ MCD_OPC_Decode, + 130, + 16, + 255, + 1, // Opcode: MIN_A_W + /* 8096 */ MCD_OPC_FilterValue, + 31, + 144, + 35, + 0, // Skip to: 17205 + /* 8101 */ MCD_OPC_CheckPredicate, + 30, + 139, + 35, + 0, // Skip to: 17205 + /* 8106 */ MCD_OPC_Decode, + 128, + 16, + 128, + 2, // Opcode: MIN_A_D + /* 8111 */ MCD_OPC_FilterValue, + 15, + 47, + 1, + 0, // Skip to: 8419 + /* 8116 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 8119 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8134 + /* 8124 */ MCD_OPC_CheckPredicate, + 30, + 116, + 35, + 0, // Skip to: 17205 + /* 8129 */ MCD_OPC_Decode, + 170, + 8, + 253, + 1, // Opcode: CEQ_B + /* 8134 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8149 + /* 8139 */ MCD_OPC_CheckPredicate, + 30, + 101, + 35, + 0, // Skip to: 17205 + /* 8144 */ MCD_OPC_Decode, + 172, + 8, + 254, + 1, // Opcode: CEQ_H + /* 8149 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8164 + /* 8154 */ MCD_OPC_CheckPredicate, + 30, + 86, + 35, + 0, // Skip to: 17205 + /* 8159 */ MCD_OPC_Decode, + 173, + 8, + 255, + 1, // Opcode: CEQ_W + /* 8164 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8179 + /* 8169 */ MCD_OPC_CheckPredicate, + 30, + 71, + 35, + 0, // Skip to: 17205 + /* 8174 */ MCD_OPC_Decode, + 171, + 8, + 128, + 2, // Opcode: CEQ_D + /* 8179 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 8194 + /* 8184 */ MCD_OPC_CheckPredicate, + 30, + 56, + 35, + 0, // Skip to: 17205 + /* 8189 */ MCD_OPC_Decode, + 214, + 8, + 253, + 1, // Opcode: CLT_S_B + /* 8194 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 8209 + /* 8199 */ MCD_OPC_CheckPredicate, + 30, + 41, + 35, + 0, // Skip to: 17205 + /* 8204 */ MCD_OPC_Decode, + 216, + 8, + 254, + 1, // Opcode: CLT_S_H + /* 8209 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 8224 + /* 8214 */ MCD_OPC_CheckPredicate, + 30, + 26, + 35, + 0, // Skip to: 17205 + /* 8219 */ MCD_OPC_Decode, + 217, + 8, + 255, + 1, // Opcode: CLT_S_W + /* 8224 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 8239 + /* 8229 */ MCD_OPC_CheckPredicate, + 30, + 11, + 35, + 0, // Skip to: 17205 + /* 8234 */ MCD_OPC_Decode, + 215, + 8, + 128, + 2, // Opcode: CLT_S_D + /* 8239 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 8254 + /* 8244 */ MCD_OPC_CheckPredicate, + 30, + 252, + 34, + 0, // Skip to: 17205 + /* 8249 */ MCD_OPC_Decode, + 218, + 8, + 253, + 1, // Opcode: CLT_U_B + /* 8254 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 8269 + /* 8259 */ MCD_OPC_CheckPredicate, + 30, + 237, + 34, + 0, // Skip to: 17205 + /* 8264 */ MCD_OPC_Decode, + 220, + 8, + 254, + 1, // Opcode: CLT_U_H + /* 8269 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 8284 + /* 8274 */ MCD_OPC_CheckPredicate, + 30, + 222, + 34, + 0, // Skip to: 17205 + /* 8279 */ MCD_OPC_Decode, + 221, + 8, + 255, + 1, // Opcode: CLT_U_W + /* 8284 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 8299 + /* 8289 */ MCD_OPC_CheckPredicate, + 30, + 207, + 34, + 0, // Skip to: 17205 + /* 8294 */ MCD_OPC_Decode, + 219, + 8, + 128, + 2, // Opcode: CLT_U_D + /* 8299 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 8314 + /* 8304 */ MCD_OPC_CheckPredicate, + 30, + 192, + 34, + 0, // Skip to: 17205 + /* 8309 */ MCD_OPC_Decode, + 194, + 8, + 253, + 1, // Opcode: CLE_S_B + /* 8314 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 8329 + /* 8319 */ MCD_OPC_CheckPredicate, + 30, + 177, + 34, + 0, // Skip to: 17205 + /* 8324 */ MCD_OPC_Decode, + 196, + 8, + 254, + 1, // Opcode: CLE_S_H + /* 8329 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 8344 + /* 8334 */ MCD_OPC_CheckPredicate, + 30, + 162, + 34, + 0, // Skip to: 17205 + /* 8339 */ MCD_OPC_Decode, + 197, + 8, + 255, + 1, // Opcode: CLE_S_W + /* 8344 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 8359 + /* 8349 */ MCD_OPC_CheckPredicate, + 30, + 147, + 34, + 0, // Skip to: 17205 + /* 8354 */ MCD_OPC_Decode, + 195, + 8, + 128, + 2, // Opcode: CLE_S_D + /* 8359 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 8374 + /* 8364 */ MCD_OPC_CheckPredicate, + 30, + 132, + 34, + 0, // Skip to: 17205 + /* 8369 */ MCD_OPC_Decode, + 198, + 8, + 253, + 1, // Opcode: CLE_U_B + /* 8374 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 8389 + /* 8379 */ MCD_OPC_CheckPredicate, + 30, + 117, + 34, + 0, // Skip to: 17205 + /* 8384 */ MCD_OPC_Decode, + 200, + 8, + 254, + 1, // Opcode: CLE_U_H + /* 8389 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 8404 + /* 8394 */ MCD_OPC_CheckPredicate, + 30, + 102, + 34, + 0, // Skip to: 17205 + /* 8399 */ MCD_OPC_Decode, + 201, + 8, + 255, + 1, // Opcode: CLE_U_W + /* 8404 */ MCD_OPC_FilterValue, + 23, + 92, + 34, + 0, // Skip to: 17205 + /* 8409 */ MCD_OPC_CheckPredicate, + 30, + 87, + 34, + 0, // Skip to: 17205 + /* 8414 */ MCD_OPC_Decode, + 199, + 8, + 128, + 2, // Opcode: CLE_U_D + /* 8419 */ MCD_OPC_FilterValue, + 16, + 227, + 1, + 0, // Skip to: 8907 + /* 8424 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 8427 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8442 + /* 8432 */ MCD_OPC_CheckPredicate, + 30, + 64, + 34, + 0, // Skip to: 17205 + /* 8437 */ MCD_OPC_Decode, + 129, + 6, + 253, + 1, // Opcode: ADD_A_B + /* 8442 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8457 + /* 8447 */ MCD_OPC_CheckPredicate, + 30, + 49, + 34, + 0, // Skip to: 17205 + /* 8452 */ MCD_OPC_Decode, + 131, + 6, + 254, + 1, // Opcode: ADD_A_H + /* 8457 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8472 + /* 8462 */ MCD_OPC_CheckPredicate, + 30, + 34, + 34, + 0, // Skip to: 17205 + /* 8467 */ MCD_OPC_Decode, + 132, + 6, + 255, + 1, // Opcode: ADD_A_W + /* 8472 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8487 + /* 8477 */ MCD_OPC_CheckPredicate, + 30, + 19, + 34, + 0, // Skip to: 17205 + /* 8482 */ MCD_OPC_Decode, + 130, + 6, + 128, + 2, // Opcode: ADD_A_D + /* 8487 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 8502 + /* 8492 */ MCD_OPC_CheckPredicate, + 30, + 4, + 34, + 0, // Skip to: 17205 + /* 8497 */ MCD_OPC_Decode, + 220, + 5, + 253, + 1, // Opcode: ADDS_A_B + /* 8502 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 8517 + /* 8507 */ MCD_OPC_CheckPredicate, + 30, + 245, + 33, + 0, // Skip to: 17205 + /* 8512 */ MCD_OPC_Decode, + 222, + 5, + 254, + 1, // Opcode: ADDS_A_H + /* 8517 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 8532 + /* 8522 */ MCD_OPC_CheckPredicate, + 30, + 230, + 33, + 0, // Skip to: 17205 + /* 8527 */ MCD_OPC_Decode, + 223, + 5, + 255, + 1, // Opcode: ADDS_A_W + /* 8532 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 8547 + /* 8537 */ MCD_OPC_CheckPredicate, + 30, + 215, + 33, + 0, // Skip to: 17205 + /* 8542 */ MCD_OPC_Decode, + 221, + 5, + 128, + 2, // Opcode: ADDS_A_D + /* 8547 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 8562 + /* 8552 */ MCD_OPC_CheckPredicate, + 30, + 200, + 33, + 0, // Skip to: 17205 + /* 8557 */ MCD_OPC_Decode, + 224, + 5, + 253, + 1, // Opcode: ADDS_S_B + /* 8562 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 8577 + /* 8567 */ MCD_OPC_CheckPredicate, + 30, + 185, + 33, + 0, // Skip to: 17205 + /* 8572 */ MCD_OPC_Decode, + 226, + 5, + 254, + 1, // Opcode: ADDS_S_H + /* 8577 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 8592 + /* 8582 */ MCD_OPC_CheckPredicate, + 30, + 170, + 33, + 0, // Skip to: 17205 + /* 8587 */ MCD_OPC_Decode, + 227, + 5, + 255, + 1, // Opcode: ADDS_S_W + /* 8592 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 8607 + /* 8597 */ MCD_OPC_CheckPredicate, + 30, + 155, + 33, + 0, // Skip to: 17205 + /* 8602 */ MCD_OPC_Decode, + 225, + 5, + 128, + 2, // Opcode: ADDS_S_D + /* 8607 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 8622 + /* 8612 */ MCD_OPC_CheckPredicate, + 30, + 140, + 33, + 0, // Skip to: 17205 + /* 8617 */ MCD_OPC_Decode, + 228, + 5, + 253, + 1, // Opcode: ADDS_U_B + /* 8622 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 8637 + /* 8627 */ MCD_OPC_CheckPredicate, + 30, + 125, + 33, + 0, // Skip to: 17205 + /* 8632 */ MCD_OPC_Decode, + 230, + 5, + 254, + 1, // Opcode: ADDS_U_H + /* 8637 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 8652 + /* 8642 */ MCD_OPC_CheckPredicate, + 30, + 110, + 33, + 0, // Skip to: 17205 + /* 8647 */ MCD_OPC_Decode, + 231, + 5, + 255, + 1, // Opcode: ADDS_U_W + /* 8652 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 8667 + /* 8657 */ MCD_OPC_CheckPredicate, + 30, + 95, + 33, + 0, // Skip to: 17205 + /* 8662 */ MCD_OPC_Decode, + 229, + 5, + 128, + 2, // Opcode: ADDS_U_D + /* 8667 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 8682 + /* 8672 */ MCD_OPC_CheckPredicate, + 30, + 80, + 33, + 0, // Skip to: 17205 + /* 8677 */ MCD_OPC_Decode, + 181, + 6, + 253, + 1, // Opcode: AVE_S_B + /* 8682 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 8697 + /* 8687 */ MCD_OPC_CheckPredicate, + 30, + 65, + 33, + 0, // Skip to: 17205 + /* 8692 */ MCD_OPC_Decode, + 183, + 6, + 254, + 1, // Opcode: AVE_S_H + /* 8697 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 8712 + /* 8702 */ MCD_OPC_CheckPredicate, + 30, + 50, + 33, + 0, // Skip to: 17205 + /* 8707 */ MCD_OPC_Decode, + 184, + 6, + 255, + 1, // Opcode: AVE_S_W + /* 8712 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 8727 + /* 8717 */ MCD_OPC_CheckPredicate, + 30, + 35, + 33, + 0, // Skip to: 17205 + /* 8722 */ MCD_OPC_Decode, + 182, + 6, + 128, + 2, // Opcode: AVE_S_D + /* 8727 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 8742 + /* 8732 */ MCD_OPC_CheckPredicate, + 30, + 20, + 33, + 0, // Skip to: 17205 + /* 8737 */ MCD_OPC_Decode, + 185, + 6, + 253, + 1, // Opcode: AVE_U_B + /* 8742 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 8757 + /* 8747 */ MCD_OPC_CheckPredicate, + 30, + 5, + 33, + 0, // Skip to: 17205 + /* 8752 */ MCD_OPC_Decode, + 187, + 6, + 254, + 1, // Opcode: AVE_U_H + /* 8757 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 8772 + /* 8762 */ MCD_OPC_CheckPredicate, + 30, + 246, + 32, + 0, // Skip to: 17205 + /* 8767 */ MCD_OPC_Decode, + 188, + 6, + 255, + 1, // Opcode: AVE_U_W + /* 8772 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 8787 + /* 8777 */ MCD_OPC_CheckPredicate, + 30, + 231, + 32, + 0, // Skip to: 17205 + /* 8782 */ MCD_OPC_Decode, + 186, + 6, + 128, + 2, // Opcode: AVE_U_D + /* 8787 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 8802 + /* 8792 */ MCD_OPC_CheckPredicate, + 30, + 216, + 32, + 0, // Skip to: 17205 + /* 8797 */ MCD_OPC_Decode, + 173, + 6, + 253, + 1, // Opcode: AVER_S_B + /* 8802 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 8817 + /* 8807 */ MCD_OPC_CheckPredicate, + 30, + 201, + 32, + 0, // Skip to: 17205 + /* 8812 */ MCD_OPC_Decode, + 175, + 6, + 254, + 1, // Opcode: AVER_S_H + /* 8817 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 8832 + /* 8822 */ MCD_OPC_CheckPredicate, + 30, + 186, + 32, + 0, // Skip to: 17205 + /* 8827 */ MCD_OPC_Decode, + 176, + 6, + 255, + 1, // Opcode: AVER_S_W + /* 8832 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 8847 + /* 8837 */ MCD_OPC_CheckPredicate, + 30, + 171, + 32, + 0, // Skip to: 17205 + /* 8842 */ MCD_OPC_Decode, + 174, + 6, + 128, + 2, // Opcode: AVER_S_D + /* 8847 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 8862 + /* 8852 */ MCD_OPC_CheckPredicate, + 30, + 156, + 32, + 0, // Skip to: 17205 + /* 8857 */ MCD_OPC_Decode, + 177, + 6, + 253, + 1, // Opcode: AVER_U_B + /* 8862 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 8877 + /* 8867 */ MCD_OPC_CheckPredicate, + 30, + 141, + 32, + 0, // Skip to: 17205 + /* 8872 */ MCD_OPC_Decode, + 179, + 6, + 254, + 1, // Opcode: AVER_U_H + /* 8877 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 8892 + /* 8882 */ MCD_OPC_CheckPredicate, + 30, + 126, + 32, + 0, // Skip to: 17205 + /* 8887 */ MCD_OPC_Decode, + 180, + 6, + 255, + 1, // Opcode: AVER_U_W + /* 8892 */ MCD_OPC_FilterValue, + 31, + 116, + 32, + 0, // Skip to: 17205 + /* 8897 */ MCD_OPC_CheckPredicate, + 30, + 111, + 32, + 0, // Skip to: 17205 + /* 8902 */ MCD_OPC_Decode, + 178, + 6, + 128, + 2, // Opcode: AVER_U_D + /* 8907 */ MCD_OPC_FilterValue, + 17, + 107, + 1, + 0, // Skip to: 9275 + /* 8912 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 8915 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8930 + /* 8920 */ MCD_OPC_CheckPredicate, + 30, + 88, + 32, + 0, // Skip to: 17205 + /* 8925 */ MCD_OPC_Decode, + 223, + 20, + 253, + 1, // Opcode: SUBS_S_B + /* 8930 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8945 + /* 8935 */ MCD_OPC_CheckPredicate, + 30, + 73, + 32, + 0, // Skip to: 17205 + /* 8940 */ MCD_OPC_Decode, + 225, + 20, + 254, + 1, // Opcode: SUBS_S_H + /* 8945 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8960 + /* 8950 */ MCD_OPC_CheckPredicate, + 30, + 58, + 32, + 0, // Skip to: 17205 + /* 8955 */ MCD_OPC_Decode, + 226, + 20, + 255, + 1, // Opcode: SUBS_S_W + /* 8960 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8975 + /* 8965 */ MCD_OPC_CheckPredicate, + 30, + 43, + 32, + 0, // Skip to: 17205 + /* 8970 */ MCD_OPC_Decode, + 224, + 20, + 128, + 2, // Opcode: SUBS_S_D + /* 8975 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 8990 + /* 8980 */ MCD_OPC_CheckPredicate, + 30, + 28, + 32, + 0, // Skip to: 17205 + /* 8985 */ MCD_OPC_Decode, + 227, + 20, + 253, + 1, // Opcode: SUBS_U_B + /* 8990 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 9005 + /* 8995 */ MCD_OPC_CheckPredicate, + 30, + 13, + 32, + 0, // Skip to: 17205 + /* 9000 */ MCD_OPC_Decode, + 229, + 20, + 254, + 1, // Opcode: SUBS_U_H + /* 9005 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 9020 + /* 9010 */ MCD_OPC_CheckPredicate, + 30, + 254, + 31, + 0, // Skip to: 17205 + /* 9015 */ MCD_OPC_Decode, + 230, + 20, + 255, + 1, // Opcode: SUBS_U_W + /* 9020 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 9035 + /* 9025 */ MCD_OPC_CheckPredicate, + 30, + 239, + 31, + 0, // Skip to: 17205 + /* 9030 */ MCD_OPC_Decode, + 228, + 20, + 128, + 2, // Opcode: SUBS_U_D + /* 9035 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 9050 + /* 9040 */ MCD_OPC_CheckPredicate, + 30, + 224, + 31, + 0, // Skip to: 17205 + /* 9045 */ MCD_OPC_Decode, + 215, + 20, + 253, + 1, // Opcode: SUBSUS_U_B + /* 9050 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 9065 + /* 9055 */ MCD_OPC_CheckPredicate, + 30, + 209, + 31, + 0, // Skip to: 17205 + /* 9060 */ MCD_OPC_Decode, + 217, + 20, + 254, + 1, // Opcode: SUBSUS_U_H + /* 9065 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 9080 + /* 9070 */ MCD_OPC_CheckPredicate, + 30, + 194, + 31, + 0, // Skip to: 17205 + /* 9075 */ MCD_OPC_Decode, + 218, + 20, + 255, + 1, // Opcode: SUBSUS_U_W + /* 9080 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 9095 + /* 9085 */ MCD_OPC_CheckPredicate, + 30, + 179, + 31, + 0, // Skip to: 17205 + /* 9090 */ MCD_OPC_Decode, + 216, + 20, + 128, + 2, // Opcode: SUBSUS_U_D + /* 9095 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 9110 + /* 9100 */ MCD_OPC_CheckPredicate, + 30, + 164, + 31, + 0, // Skip to: 17205 + /* 9105 */ MCD_OPC_Decode, + 219, + 20, + 253, + 1, // Opcode: SUBSUU_S_B + /* 9110 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 9125 + /* 9115 */ MCD_OPC_CheckPredicate, + 30, + 149, + 31, + 0, // Skip to: 17205 + /* 9120 */ MCD_OPC_Decode, + 221, + 20, + 254, + 1, // Opcode: SUBSUU_S_H + /* 9125 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9140 + /* 9130 */ MCD_OPC_CheckPredicate, + 30, + 134, + 31, + 0, // Skip to: 17205 + /* 9135 */ MCD_OPC_Decode, + 222, + 20, + 255, + 1, // Opcode: SUBSUU_S_W + /* 9140 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 9155 + /* 9145 */ MCD_OPC_CheckPredicate, + 30, + 119, + 31, + 0, // Skip to: 17205 + /* 9150 */ MCD_OPC_Decode, + 220, + 20, + 128, + 2, // Opcode: SUBSUU_S_D + /* 9155 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 9170 + /* 9160 */ MCD_OPC_CheckPredicate, + 30, + 104, + 31, + 0, // Skip to: 17205 + /* 9165 */ MCD_OPC_Decode, + 161, + 6, + 253, + 1, // Opcode: ASUB_S_B + /* 9170 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 9185 + /* 9175 */ MCD_OPC_CheckPredicate, + 30, + 89, + 31, + 0, // Skip to: 17205 + /* 9180 */ MCD_OPC_Decode, + 163, + 6, + 254, + 1, // Opcode: ASUB_S_H + /* 9185 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 9200 + /* 9190 */ MCD_OPC_CheckPredicate, + 30, + 74, + 31, + 0, // Skip to: 17205 + /* 9195 */ MCD_OPC_Decode, + 164, + 6, + 255, + 1, // Opcode: ASUB_S_W + /* 9200 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 9215 + /* 9205 */ MCD_OPC_CheckPredicate, + 30, + 59, + 31, + 0, // Skip to: 17205 + /* 9210 */ MCD_OPC_Decode, + 162, + 6, + 128, + 2, // Opcode: ASUB_S_D + /* 9215 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 9230 + /* 9220 */ MCD_OPC_CheckPredicate, + 30, + 44, + 31, + 0, // Skip to: 17205 + /* 9225 */ MCD_OPC_Decode, + 165, + 6, + 253, + 1, // Opcode: ASUB_U_B + /* 9230 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 9245 + /* 9235 */ MCD_OPC_CheckPredicate, + 30, + 29, + 31, + 0, // Skip to: 17205 + /* 9240 */ MCD_OPC_Decode, + 167, + 6, + 254, + 1, // Opcode: ASUB_U_H + /* 9245 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 9260 + /* 9250 */ MCD_OPC_CheckPredicate, + 30, + 14, + 31, + 0, // Skip to: 17205 + /* 9255 */ MCD_OPC_Decode, + 168, + 6, + 255, + 1, // Opcode: ASUB_U_W + /* 9260 */ MCD_OPC_FilterValue, + 23, + 4, + 31, + 0, // Skip to: 17205 + /* 9265 */ MCD_OPC_CheckPredicate, + 30, + 255, + 30, + 0, // Skip to: 17205 + /* 9270 */ MCD_OPC_Decode, + 166, + 6, + 128, + 2, // Opcode: ASUB_U_D + /* 9275 */ MCD_OPC_FilterValue, + 18, + 167, + 1, + 0, // Skip to: 9703 + /* 9280 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 9283 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9298 + /* 9288 */ MCD_OPC_CheckPredicate, + 30, + 232, + 30, + 0, // Skip to: 17205 + /* 9293 */ MCD_OPC_Decode, + 175, + 17, + 253, + 1, // Opcode: MULV_B + /* 9298 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9313 + /* 9303 */ MCD_OPC_CheckPredicate, + 30, + 217, + 30, + 0, // Skip to: 17205 + /* 9308 */ MCD_OPC_Decode, + 177, + 17, + 254, + 1, // Opcode: MULV_H + /* 9313 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9328 + /* 9318 */ MCD_OPC_CheckPredicate, + 30, + 202, + 30, + 0, // Skip to: 17205 + /* 9323 */ MCD_OPC_Decode, + 178, + 17, + 255, + 1, // Opcode: MULV_W + /* 9328 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 9343 + /* 9333 */ MCD_OPC_CheckPredicate, + 30, + 187, + 30, + 0, // Skip to: 17205 + /* 9338 */ MCD_OPC_Decode, + 176, + 17, + 128, + 2, // Opcode: MULV_D + /* 9343 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 9358 + /* 9348 */ MCD_OPC_CheckPredicate, + 30, + 172, + 30, + 0, // Skip to: 17205 + /* 9353 */ MCD_OPC_Decode, + 162, + 15, + 129, + 2, // Opcode: MADDV_B + /* 9358 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 9373 + /* 9363 */ MCD_OPC_CheckPredicate, + 30, + 157, + 30, + 0, // Skip to: 17205 + /* 9368 */ MCD_OPC_Decode, + 164, + 15, + 130, + 2, // Opcode: MADDV_H + /* 9373 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 9388 + /* 9378 */ MCD_OPC_CheckPredicate, + 30, + 142, + 30, + 0, // Skip to: 17205 + /* 9383 */ MCD_OPC_Decode, + 165, + 15, + 131, + 2, // Opcode: MADDV_W + /* 9388 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 9403 + /* 9393 */ MCD_OPC_CheckPredicate, + 30, + 127, + 30, + 0, // Skip to: 17205 + /* 9398 */ MCD_OPC_Decode, + 163, + 15, + 132, + 2, // Opcode: MADDV_D + /* 9403 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 9418 + /* 9408 */ MCD_OPC_CheckPredicate, + 30, + 112, + 30, + 0, // Skip to: 17205 + /* 9413 */ MCD_OPC_Decode, + 213, + 16, + 129, + 2, // Opcode: MSUBV_B + /* 9418 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 9433 + /* 9423 */ MCD_OPC_CheckPredicate, + 30, + 97, + 30, + 0, // Skip to: 17205 + /* 9428 */ MCD_OPC_Decode, + 215, + 16, + 130, + 2, // Opcode: MSUBV_H + /* 9433 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 9448 + /* 9438 */ MCD_OPC_CheckPredicate, + 30, + 82, + 30, + 0, // Skip to: 17205 + /* 9443 */ MCD_OPC_Decode, + 216, + 16, + 131, + 2, // Opcode: MSUBV_W + /* 9448 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 9463 + /* 9453 */ MCD_OPC_CheckPredicate, + 30, + 67, + 30, + 0, // Skip to: 17205 + /* 9458 */ MCD_OPC_Decode, + 214, + 16, + 132, + 2, // Opcode: MSUBV_D + /* 9463 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 9478 + /* 9468 */ MCD_OPC_CheckPredicate, + 30, + 52, + 30, + 0, // Skip to: 17205 + /* 9473 */ MCD_OPC_Decode, + 243, + 10, + 253, + 1, // Opcode: DIV_S_B + /* 9478 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 9493 + /* 9483 */ MCD_OPC_CheckPredicate, + 30, + 37, + 30, + 0, // Skip to: 17205 + /* 9488 */ MCD_OPC_Decode, + 245, + 10, + 254, + 1, // Opcode: DIV_S_H + /* 9493 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 9508 + /* 9498 */ MCD_OPC_CheckPredicate, + 30, + 22, + 30, + 0, // Skip to: 17205 + /* 9503 */ MCD_OPC_Decode, + 246, + 10, + 255, + 1, // Opcode: DIV_S_W + /* 9508 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 9523 + /* 9513 */ MCD_OPC_CheckPredicate, + 30, + 7, + 30, + 0, // Skip to: 17205 + /* 9518 */ MCD_OPC_Decode, + 244, + 10, + 128, + 2, // Opcode: DIV_S_D + /* 9523 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 9538 + /* 9528 */ MCD_OPC_CheckPredicate, + 30, + 248, + 29, + 0, // Skip to: 17205 + /* 9533 */ MCD_OPC_Decode, + 247, + 10, + 253, + 1, // Opcode: DIV_U_B + /* 9538 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 9553 + /* 9543 */ MCD_OPC_CheckPredicate, + 30, + 233, + 29, + 0, // Skip to: 17205 + /* 9548 */ MCD_OPC_Decode, + 249, + 10, + 254, + 1, // Opcode: DIV_U_H + /* 9553 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 9568 + /* 9558 */ MCD_OPC_CheckPredicate, + 30, + 218, + 29, + 0, // Skip to: 17205 + /* 9563 */ MCD_OPC_Decode, + 250, + 10, + 255, + 1, // Opcode: DIV_U_W + /* 9568 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 9583 + /* 9573 */ MCD_OPC_CheckPredicate, + 30, + 203, + 29, + 0, // Skip to: 17205 + /* 9578 */ MCD_OPC_Decode, + 248, + 10, + 128, + 2, // Opcode: DIV_U_D + /* 9583 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 9598 + /* 9588 */ MCD_OPC_CheckPredicate, + 30, + 188, + 29, + 0, // Skip to: 17205 + /* 9593 */ MCD_OPC_Decode, + 149, + 16, + 253, + 1, // Opcode: MOD_S_B + /* 9598 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 9613 + /* 9603 */ MCD_OPC_CheckPredicate, + 30, + 173, + 29, + 0, // Skip to: 17205 + /* 9608 */ MCD_OPC_Decode, + 151, + 16, + 254, + 1, // Opcode: MOD_S_H + /* 9613 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 9628 + /* 9618 */ MCD_OPC_CheckPredicate, + 30, + 158, + 29, + 0, // Skip to: 17205 + /* 9623 */ MCD_OPC_Decode, + 152, + 16, + 255, + 1, // Opcode: MOD_S_W + /* 9628 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 9643 + /* 9633 */ MCD_OPC_CheckPredicate, + 30, + 143, + 29, + 0, // Skip to: 17205 + /* 9638 */ MCD_OPC_Decode, + 150, + 16, + 128, + 2, // Opcode: MOD_S_D + /* 9643 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 9658 + /* 9648 */ MCD_OPC_CheckPredicate, + 30, + 128, + 29, + 0, // Skip to: 17205 + /* 9653 */ MCD_OPC_Decode, + 153, + 16, + 253, + 1, // Opcode: MOD_U_B + /* 9658 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 9673 + /* 9663 */ MCD_OPC_CheckPredicate, + 30, + 113, + 29, + 0, // Skip to: 17205 + /* 9668 */ MCD_OPC_Decode, + 155, + 16, + 254, + 1, // Opcode: MOD_U_H + /* 9673 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 9688 + /* 9678 */ MCD_OPC_CheckPredicate, + 30, + 98, + 29, + 0, // Skip to: 17205 + /* 9683 */ MCD_OPC_Decode, + 156, + 16, + 255, + 1, // Opcode: MOD_U_W + /* 9688 */ MCD_OPC_FilterValue, + 31, + 88, + 29, + 0, // Skip to: 17205 + /* 9693 */ MCD_OPC_CheckPredicate, + 30, + 83, + 29, + 0, // Skip to: 17205 + /* 9698 */ MCD_OPC_Decode, + 154, + 16, + 128, + 2, // Opcode: MOD_U_D + /* 9703 */ MCD_OPC_FilterValue, + 19, + 17, + 1, + 0, // Skip to: 9981 + /* 9708 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 9711 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9726 + /* 9716 */ MCD_OPC_CheckPredicate, + 30, + 60, + 29, + 0, // Skip to: 17205 + /* 9721 */ MCD_OPC_Decode, + 148, + 11, + 133, + 2, // Opcode: DOTP_S_H + /* 9726 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9741 + /* 9731 */ MCD_OPC_CheckPredicate, + 30, + 45, + 29, + 0, // Skip to: 17205 + /* 9736 */ MCD_OPC_Decode, + 149, + 11, + 134, + 2, // Opcode: DOTP_S_W + /* 9741 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 9756 + /* 9746 */ MCD_OPC_CheckPredicate, + 30, + 30, + 29, + 0, // Skip to: 17205 + /* 9751 */ MCD_OPC_Decode, + 147, + 11, + 135, + 2, // Opcode: DOTP_S_D + /* 9756 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 9771 + /* 9761 */ MCD_OPC_CheckPredicate, + 30, + 15, + 29, + 0, // Skip to: 17205 + /* 9766 */ MCD_OPC_Decode, + 151, + 11, + 133, + 2, // Opcode: DOTP_U_H + /* 9771 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 9786 + /* 9776 */ MCD_OPC_CheckPredicate, + 30, + 0, + 29, + 0, // Skip to: 17205 + /* 9781 */ MCD_OPC_Decode, + 152, + 11, + 134, + 2, // Opcode: DOTP_U_W + /* 9786 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 9801 + /* 9791 */ MCD_OPC_CheckPredicate, + 30, + 241, + 28, + 0, // Skip to: 17205 + /* 9796 */ MCD_OPC_Decode, + 150, + 11, + 135, + 2, // Opcode: DOTP_U_D + /* 9801 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 9816 + /* 9806 */ MCD_OPC_CheckPredicate, + 30, + 226, + 28, + 0, // Skip to: 17205 + /* 9811 */ MCD_OPC_Decode, + 154, + 11, + 136, + 2, // Opcode: DPADD_S_H + /* 9816 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 9831 + /* 9821 */ MCD_OPC_CheckPredicate, + 30, + 211, + 28, + 0, // Skip to: 17205 + /* 9826 */ MCD_OPC_Decode, + 155, + 11, + 137, + 2, // Opcode: DPADD_S_W + /* 9831 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 9846 + /* 9836 */ MCD_OPC_CheckPredicate, + 30, + 196, + 28, + 0, // Skip to: 17205 + /* 9841 */ MCD_OPC_Decode, + 153, + 11, + 138, + 2, // Opcode: DPADD_S_D + /* 9846 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 9861 + /* 9851 */ MCD_OPC_CheckPredicate, + 30, + 181, + 28, + 0, // Skip to: 17205 + /* 9856 */ MCD_OPC_Decode, + 157, + 11, + 136, + 2, // Opcode: DPADD_U_H + /* 9861 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9876 + /* 9866 */ MCD_OPC_CheckPredicate, + 30, + 166, + 28, + 0, // Skip to: 17205 + /* 9871 */ MCD_OPC_Decode, + 158, + 11, + 137, + 2, // Opcode: DPADD_U_W + /* 9876 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 9891 + /* 9881 */ MCD_OPC_CheckPredicate, + 30, + 151, + 28, + 0, // Skip to: 17205 + /* 9886 */ MCD_OPC_Decode, + 156, + 11, + 138, + 2, // Opcode: DPADD_U_D + /* 9891 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 9906 + /* 9896 */ MCD_OPC_CheckPredicate, + 30, + 136, + 28, + 0, // Skip to: 17205 + /* 9901 */ MCD_OPC_Decode, + 185, + 11, + 136, + 2, // Opcode: DPSUB_S_H + /* 9906 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 9921 + /* 9911 */ MCD_OPC_CheckPredicate, + 30, + 121, + 28, + 0, // Skip to: 17205 + /* 9916 */ MCD_OPC_Decode, + 186, + 11, + 137, + 2, // Opcode: DPSUB_S_W + /* 9921 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 9936 + /* 9926 */ MCD_OPC_CheckPredicate, + 30, + 106, + 28, + 0, // Skip to: 17205 + /* 9931 */ MCD_OPC_Decode, + 184, + 11, + 138, + 2, // Opcode: DPSUB_S_D + /* 9936 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 9951 + /* 9941 */ MCD_OPC_CheckPredicate, + 30, + 91, + 28, + 0, // Skip to: 17205 + /* 9946 */ MCD_OPC_Decode, + 188, + 11, + 136, + 2, // Opcode: DPSUB_U_H + /* 9951 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 9966 + /* 9956 */ MCD_OPC_CheckPredicate, + 30, + 76, + 28, + 0, // Skip to: 17205 + /* 9961 */ MCD_OPC_Decode, + 189, + 11, + 137, + 2, // Opcode: DPSUB_U_W + /* 9966 */ MCD_OPC_FilterValue, + 23, + 66, + 28, + 0, // Skip to: 17205 + /* 9971 */ MCD_OPC_CheckPredicate, + 30, + 61, + 28, + 0, // Skip to: 17205 + /* 9976 */ MCD_OPC_Decode, + 187, + 11, + 138, + 2, // Opcode: DPSUB_U_D + /* 9981 */ MCD_OPC_FilterValue, + 20, + 227, + 1, + 0, // Skip to: 10469 + /* 9986 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 9989 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10004 + /* 9994 */ MCD_OPC_CheckPredicate, + 30, + 38, + 28, + 0, // Skip to: 17205 + /* 9999 */ MCD_OPC_Decode, + 236, + 19, + 139, + 2, // Opcode: SLD_B + /* 10004 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10019 + /* 10009 */ MCD_OPC_CheckPredicate, + 30, + 23, + 28, + 0, // Skip to: 17205 + /* 10014 */ MCD_OPC_Decode, + 238, + 19, + 140, + 2, // Opcode: SLD_H + /* 10019 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10034 + /* 10024 */ MCD_OPC_CheckPredicate, + 30, + 8, + 28, + 0, // Skip to: 17205 + /* 10029 */ MCD_OPC_Decode, + 239, + 19, + 141, + 2, // Opcode: SLD_W + /* 10034 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 10049 + /* 10039 */ MCD_OPC_CheckPredicate, + 30, + 249, + 27, + 0, // Skip to: 17205 + /* 10044 */ MCD_OPC_Decode, + 237, + 19, + 142, + 2, // Opcode: SLD_D + /* 10049 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 10064 + /* 10054 */ MCD_OPC_CheckPredicate, + 30, + 234, + 27, + 0, // Skip to: 17205 + /* 10059 */ MCD_OPC_Decode, + 147, + 20, + 143, + 2, // Opcode: SPLAT_B + /* 10064 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 10079 + /* 10069 */ MCD_OPC_CheckPredicate, + 30, + 219, + 27, + 0, // Skip to: 17205 + /* 10074 */ MCD_OPC_Decode, + 149, + 20, + 144, + 2, // Opcode: SPLAT_H + /* 10079 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 10094 + /* 10084 */ MCD_OPC_CheckPredicate, + 30, + 204, + 27, + 0, // Skip to: 17205 + /* 10089 */ MCD_OPC_Decode, + 150, + 20, + 145, + 2, // Opcode: SPLAT_W + /* 10094 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 10109 + /* 10099 */ MCD_OPC_CheckPredicate, + 30, + 189, + 27, + 0, // Skip to: 17205 + /* 10104 */ MCD_OPC_Decode, + 148, + 20, + 146, + 2, // Opcode: SPLAT_D + /* 10109 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 10124 + /* 10114 */ MCD_OPC_CheckPredicate, + 30, + 174, + 27, + 0, // Skip to: 17205 + /* 10119 */ MCD_OPC_Decode, + 238, + 17, + 253, + 1, // Opcode: PCKEV_B + /* 10124 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 10139 + /* 10129 */ MCD_OPC_CheckPredicate, + 30, + 159, + 27, + 0, // Skip to: 17205 + /* 10134 */ MCD_OPC_Decode, + 240, + 17, + 254, + 1, // Opcode: PCKEV_H + /* 10139 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 10154 + /* 10144 */ MCD_OPC_CheckPredicate, + 30, + 144, + 27, + 0, // Skip to: 17205 + /* 10149 */ MCD_OPC_Decode, + 241, + 17, + 255, + 1, // Opcode: PCKEV_W + /* 10154 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 10169 + /* 10159 */ MCD_OPC_CheckPredicate, + 30, + 129, + 27, + 0, // Skip to: 17205 + /* 10164 */ MCD_OPC_Decode, + 239, + 17, + 128, + 2, // Opcode: PCKEV_D + /* 10169 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 10184 + /* 10174 */ MCD_OPC_CheckPredicate, + 30, + 114, + 27, + 0, // Skip to: 17205 + /* 10179 */ MCD_OPC_Decode, + 242, + 17, + 253, + 1, // Opcode: PCKOD_B + /* 10184 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 10199 + /* 10189 */ MCD_OPC_CheckPredicate, + 30, + 99, + 27, + 0, // Skip to: 17205 + /* 10194 */ MCD_OPC_Decode, + 244, + 17, + 254, + 1, // Opcode: PCKOD_H + /* 10199 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10214 + /* 10204 */ MCD_OPC_CheckPredicate, + 30, + 84, + 27, + 0, // Skip to: 17205 + /* 10209 */ MCD_OPC_Decode, + 245, + 17, + 255, + 1, // Opcode: PCKOD_W + /* 10214 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 10229 + /* 10219 */ MCD_OPC_CheckPredicate, + 30, + 69, + 27, + 0, // Skip to: 17205 + /* 10224 */ MCD_OPC_Decode, + 243, + 17, + 128, + 2, // Opcode: PCKOD_D + /* 10229 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 10244 + /* 10234 */ MCD_OPC_CheckPredicate, + 30, + 54, + 27, + 0, // Skip to: 17205 + /* 10239 */ MCD_OPC_Decode, + 213, + 13, + 253, + 1, // Opcode: ILVL_B + /* 10244 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 10259 + /* 10249 */ MCD_OPC_CheckPredicate, + 30, + 39, + 27, + 0, // Skip to: 17205 + /* 10254 */ MCD_OPC_Decode, + 215, + 13, + 254, + 1, // Opcode: ILVL_H + /* 10259 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 10274 + /* 10264 */ MCD_OPC_CheckPredicate, + 30, + 24, + 27, + 0, // Skip to: 17205 + /* 10269 */ MCD_OPC_Decode, + 216, + 13, + 255, + 1, // Opcode: ILVL_W + /* 10274 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 10289 + /* 10279 */ MCD_OPC_CheckPredicate, + 30, + 9, + 27, + 0, // Skip to: 17205 + /* 10284 */ MCD_OPC_Decode, + 214, + 13, + 128, + 2, // Opcode: ILVL_D + /* 10289 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 10304 + /* 10294 */ MCD_OPC_CheckPredicate, + 30, + 250, + 26, + 0, // Skip to: 17205 + /* 10299 */ MCD_OPC_Decode, + 221, + 13, + 253, + 1, // Opcode: ILVR_B + /* 10304 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 10319 + /* 10309 */ MCD_OPC_CheckPredicate, + 30, + 235, + 26, + 0, // Skip to: 17205 + /* 10314 */ MCD_OPC_Decode, + 223, + 13, + 254, + 1, // Opcode: ILVR_H + /* 10319 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 10334 + /* 10324 */ MCD_OPC_CheckPredicate, + 30, + 220, + 26, + 0, // Skip to: 17205 + /* 10329 */ MCD_OPC_Decode, + 224, + 13, + 255, + 1, // Opcode: ILVR_W + /* 10334 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 10349 + /* 10339 */ MCD_OPC_CheckPredicate, + 30, + 205, + 26, + 0, // Skip to: 17205 + /* 10344 */ MCD_OPC_Decode, + 222, + 13, + 128, + 2, // Opcode: ILVR_D + /* 10349 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 10364 + /* 10354 */ MCD_OPC_CheckPredicate, + 30, + 190, + 26, + 0, // Skip to: 17205 + /* 10359 */ MCD_OPC_Decode, + 209, + 13, + 253, + 1, // Opcode: ILVEV_B + /* 10364 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 10379 + /* 10369 */ MCD_OPC_CheckPredicate, + 30, + 175, + 26, + 0, // Skip to: 17205 + /* 10374 */ MCD_OPC_Decode, + 211, + 13, + 254, + 1, // Opcode: ILVEV_H + /* 10379 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 10394 + /* 10384 */ MCD_OPC_CheckPredicate, + 30, + 160, + 26, + 0, // Skip to: 17205 + /* 10389 */ MCD_OPC_Decode, + 212, + 13, + 255, + 1, // Opcode: ILVEV_W + /* 10394 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 10409 + /* 10399 */ MCD_OPC_CheckPredicate, + 30, + 145, + 26, + 0, // Skip to: 17205 + /* 10404 */ MCD_OPC_Decode, + 210, + 13, + 128, + 2, // Opcode: ILVEV_D + /* 10409 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 10424 + /* 10414 */ MCD_OPC_CheckPredicate, + 30, + 130, + 26, + 0, // Skip to: 17205 + /* 10419 */ MCD_OPC_Decode, + 217, + 13, + 253, + 1, // Opcode: ILVOD_B + /* 10424 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 10439 + /* 10429 */ MCD_OPC_CheckPredicate, + 30, + 115, + 26, + 0, // Skip to: 17205 + /* 10434 */ MCD_OPC_Decode, + 219, + 13, + 254, + 1, // Opcode: ILVOD_H + /* 10439 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 10454 + /* 10444 */ MCD_OPC_CheckPredicate, + 30, + 100, + 26, + 0, // Skip to: 17205 + /* 10449 */ MCD_OPC_Decode, + 220, + 13, + 255, + 1, // Opcode: ILVOD_W + /* 10454 */ MCD_OPC_FilterValue, + 31, + 90, + 26, + 0, // Skip to: 17205 + /* 10459 */ MCD_OPC_CheckPredicate, + 30, + 85, + 26, + 0, // Skip to: 17205 + /* 10464 */ MCD_OPC_Decode, + 218, + 13, + 128, + 2, // Opcode: ILVOD_D + /* 10469 */ MCD_OPC_FilterValue, + 21, + 107, + 1, + 0, // Skip to: 10837 + /* 10474 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 10477 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10492 + /* 10482 */ MCD_OPC_CheckPredicate, + 30, + 62, + 26, + 0, // Skip to: 17205 + /* 10487 */ MCD_OPC_Decode, + 132, + 22, + 129, + 2, // Opcode: VSHF_B + /* 10492 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10507 + /* 10497 */ MCD_OPC_CheckPredicate, + 30, + 47, + 26, + 0, // Skip to: 17205 + /* 10502 */ MCD_OPC_Decode, + 134, + 22, + 130, + 2, // Opcode: VSHF_H + /* 10507 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10522 + /* 10512 */ MCD_OPC_CheckPredicate, + 30, + 32, + 26, + 0, // Skip to: 17205 + /* 10517 */ MCD_OPC_Decode, + 135, + 22, + 131, + 2, // Opcode: VSHF_W + /* 10522 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 10537 + /* 10527 */ MCD_OPC_CheckPredicate, + 30, + 17, + 26, + 0, // Skip to: 17205 + /* 10532 */ MCD_OPC_Decode, + 133, + 22, + 132, + 2, // Opcode: VSHF_D + /* 10537 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 10552 + /* 10542 */ MCD_OPC_CheckPredicate, + 30, + 2, + 26, + 0, // Skip to: 17205 + /* 10547 */ MCD_OPC_Decode, + 160, + 20, + 253, + 1, // Opcode: SRAR_B + /* 10552 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 10567 + /* 10557 */ MCD_OPC_CheckPredicate, + 30, + 243, + 25, + 0, // Skip to: 17205 + /* 10562 */ MCD_OPC_Decode, + 162, + 20, + 254, + 1, // Opcode: SRAR_H + /* 10567 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 10582 + /* 10572 */ MCD_OPC_CheckPredicate, + 30, + 228, + 25, + 0, // Skip to: 17205 + /* 10577 */ MCD_OPC_Decode, + 163, + 20, + 255, + 1, // Opcode: SRAR_W + /* 10582 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 10597 + /* 10587 */ MCD_OPC_CheckPredicate, + 30, + 213, + 25, + 0, // Skip to: 17205 + /* 10592 */ MCD_OPC_Decode, + 161, + 20, + 128, + 2, // Opcode: SRAR_D + /* 10597 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 10612 + /* 10602 */ MCD_OPC_CheckPredicate, + 30, + 198, + 25, + 0, // Skip to: 17205 + /* 10607 */ MCD_OPC_Decode, + 182, + 20, + 253, + 1, // Opcode: SRLR_B + /* 10612 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 10627 + /* 10617 */ MCD_OPC_CheckPredicate, + 30, + 183, + 25, + 0, // Skip to: 17205 + /* 10622 */ MCD_OPC_Decode, + 184, + 20, + 254, + 1, // Opcode: SRLR_H + /* 10627 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 10642 + /* 10632 */ MCD_OPC_CheckPredicate, + 30, + 168, + 25, + 0, // Skip to: 17205 + /* 10637 */ MCD_OPC_Decode, + 185, + 20, + 255, + 1, // Opcode: SRLR_W + /* 10642 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 10657 + /* 10647 */ MCD_OPC_CheckPredicate, + 30, + 153, + 25, + 0, // Skip to: 17205 + /* 10652 */ MCD_OPC_Decode, + 183, + 20, + 128, + 2, // Opcode: SRLR_D + /* 10657 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 10672 + /* 10662 */ MCD_OPC_CheckPredicate, + 30, + 138, + 25, + 0, // Skip to: 17205 + /* 10667 */ MCD_OPC_Decode, + 196, + 13, + 133, + 2, // Opcode: HADD_S_H + /* 10672 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 10687 + /* 10677 */ MCD_OPC_CheckPredicate, + 30, + 123, + 25, + 0, // Skip to: 17205 + /* 10682 */ MCD_OPC_Decode, + 197, + 13, + 134, + 2, // Opcode: HADD_S_W + /* 10687 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 10702 + /* 10692 */ MCD_OPC_CheckPredicate, + 30, + 108, + 25, + 0, // Skip to: 17205 + /* 10697 */ MCD_OPC_Decode, + 195, + 13, + 135, + 2, // Opcode: HADD_S_D + /* 10702 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 10717 + /* 10707 */ MCD_OPC_CheckPredicate, + 30, + 93, + 25, + 0, // Skip to: 17205 + /* 10712 */ MCD_OPC_Decode, + 199, + 13, + 133, + 2, // Opcode: HADD_U_H + /* 10717 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 10732 + /* 10722 */ MCD_OPC_CheckPredicate, + 30, + 78, + 25, + 0, // Skip to: 17205 + /* 10727 */ MCD_OPC_Decode, + 200, + 13, + 134, + 2, // Opcode: HADD_U_W + /* 10732 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 10747 + /* 10737 */ MCD_OPC_CheckPredicate, + 30, + 63, + 25, + 0, // Skip to: 17205 + /* 10742 */ MCD_OPC_Decode, + 198, + 13, + 135, + 2, // Opcode: HADD_U_D + /* 10747 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 10762 + /* 10752 */ MCD_OPC_CheckPredicate, + 30, + 48, + 25, + 0, // Skip to: 17205 + /* 10757 */ MCD_OPC_Decode, + 202, + 13, + 133, + 2, // Opcode: HSUB_S_H + /* 10762 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 10777 + /* 10767 */ MCD_OPC_CheckPredicate, + 30, + 33, + 25, + 0, // Skip to: 17205 + /* 10772 */ MCD_OPC_Decode, + 203, + 13, + 134, + 2, // Opcode: HSUB_S_W + /* 10777 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 10792 + /* 10782 */ MCD_OPC_CheckPredicate, + 30, + 18, + 25, + 0, // Skip to: 17205 + /* 10787 */ MCD_OPC_Decode, + 201, + 13, + 135, + 2, // Opcode: HSUB_S_D + /* 10792 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 10807 + /* 10797 */ MCD_OPC_CheckPredicate, + 30, + 3, + 25, + 0, // Skip to: 17205 + /* 10802 */ MCD_OPC_Decode, + 205, + 13, + 133, + 2, // Opcode: HSUB_U_H + /* 10807 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 10822 + /* 10812 */ MCD_OPC_CheckPredicate, + 30, + 244, + 24, + 0, // Skip to: 17205 + /* 10817 */ MCD_OPC_Decode, + 206, + 13, + 134, + 2, // Opcode: HSUB_U_W + /* 10822 */ MCD_OPC_FilterValue, + 31, + 234, + 24, + 0, // Skip to: 17205 + /* 10827 */ MCD_OPC_CheckPredicate, + 30, + 229, + 24, + 0, // Skip to: 17205 + /* 10832 */ MCD_OPC_Decode, + 204, + 13, + 135, + 2, // Opcode: HSUB_U_D + /* 10837 */ MCD_OPC_FilterValue, + 25, + 26, + 2, + 0, // Skip to: 11380 + /* 10842 */ MCD_OPC_ExtractField, + 20, + 6, // Inst{25-20} ... + /* 10845 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10860 + /* 10850 */ MCD_OPC_CheckPredicate, + 30, + 206, + 24, + 0, // Skip to: 17205 + /* 10855 */ MCD_OPC_Decode, + 232, + 19, + 147, + 2, // Opcode: SLDI_B + /* 10860 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 10882 + /* 10865 */ MCD_OPC_CheckPredicate, + 30, + 191, + 24, + 0, // Skip to: 17205 + /* 10870 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 184, + 24, + 0, // Skip to: 17205 + /* 10877 */ MCD_OPC_Decode, + 234, + 19, + 148, + 2, // Opcode: SLDI_H + /* 10882 */ MCD_OPC_FilterValue, + 3, + 62, + 0, + 0, // Skip to: 10949 + /* 10887 */ MCD_OPC_ExtractField, + 18, + 2, // Inst{19-18} ... + /* 10890 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10905 + /* 10895 */ MCD_OPC_CheckPredicate, + 30, + 161, + 24, + 0, // Skip to: 17205 + /* 10900 */ MCD_OPC_Decode, + 235, + 19, + 149, + 2, // Opcode: SLDI_W + /* 10905 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 10927 + /* 10910 */ MCD_OPC_CheckPredicate, + 30, + 146, + 24, + 0, // Skip to: 17205 + /* 10915 */ MCD_OPC_CheckField, + 17, + 1, + 0, + 139, + 24, + 0, // Skip to: 17205 + /* 10922 */ MCD_OPC_Decode, + 233, + 19, + 150, + 2, // Opcode: SLDI_D + /* 10927 */ MCD_OPC_FilterValue, + 3, + 129, + 24, + 0, // Skip to: 17205 + /* 10932 */ MCD_OPC_CheckPredicate, + 30, + 124, + 24, + 0, // Skip to: 17205 + /* 10937 */ MCD_OPC_CheckField, + 16, + 2, + 2, + 117, + 24, + 0, // Skip to: 17205 + /* 10944 */ MCD_OPC_Decode, + 204, + 9, + 151, + 2, // Opcode: CTCMSA + /* 10949 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 10964 + /* 10954 */ MCD_OPC_CheckPredicate, + 30, + 102, + 24, + 0, // Skip to: 17205 + /* 10959 */ MCD_OPC_Decode, + 143, + 20, + 152, + 2, // Opcode: SPLATI_B + /* 10964 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 10986 + /* 10969 */ MCD_OPC_CheckPredicate, + 30, + 87, + 24, + 0, // Skip to: 17205 + /* 10974 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 80, + 24, + 0, // Skip to: 17205 + /* 10981 */ MCD_OPC_Decode, + 145, + 20, + 153, + 2, // Opcode: SPLATI_H + /* 10986 */ MCD_OPC_FilterValue, + 7, + 62, + 0, + 0, // Skip to: 11053 + /* 10991 */ MCD_OPC_ExtractField, + 18, + 2, // Inst{19-18} ... + /* 10994 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11009 + /* 10999 */ MCD_OPC_CheckPredicate, + 30, + 57, + 24, + 0, // Skip to: 17205 + /* 11004 */ MCD_OPC_Decode, + 146, + 20, + 154, + 2, // Opcode: SPLATI_W + /* 11009 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 11031 + /* 11014 */ MCD_OPC_CheckPredicate, + 30, + 42, + 24, + 0, // Skip to: 17205 + /* 11019 */ MCD_OPC_CheckField, + 17, + 1, + 0, + 35, + 24, + 0, // Skip to: 17205 + /* 11026 */ MCD_OPC_Decode, + 144, + 20, + 155, + 2, // Opcode: SPLATI_D + /* 11031 */ MCD_OPC_FilterValue, + 3, + 25, + 24, + 0, // Skip to: 17205 + /* 11036 */ MCD_OPC_CheckPredicate, + 30, + 20, + 24, + 0, // Skip to: 17205 + /* 11041 */ MCD_OPC_CheckField, + 16, + 2, + 2, + 13, + 24, + 0, // Skip to: 17205 + /* 11048 */ MCD_OPC_Decode, + 177, + 8, + 156, + 2, // Opcode: CFCMSA + /* 11053 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 11068 + /* 11058 */ MCD_OPC_CheckPredicate, + 30, + 254, + 23, + 0, // Skip to: 17205 + /* 11063 */ MCD_OPC_Decode, + 186, + 9, + 157, + 2, // Opcode: COPY_S_B + /* 11068 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 11090 + /* 11073 */ MCD_OPC_CheckPredicate, + 30, + 239, + 23, + 0, // Skip to: 17205 + /* 11078 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 232, + 23, + 0, // Skip to: 17205 + /* 11085 */ MCD_OPC_Decode, + 188, + 9, + 158, + 2, // Opcode: COPY_S_H + /* 11090 */ MCD_OPC_FilterValue, + 11, + 62, + 0, + 0, // Skip to: 11157 + /* 11095 */ MCD_OPC_ExtractField, + 18, + 2, // Inst{19-18} ... + /* 11098 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11113 + /* 11103 */ MCD_OPC_CheckPredicate, + 30, + 209, + 23, + 0, // Skip to: 17205 + /* 11108 */ MCD_OPC_Decode, + 189, + 9, + 159, + 2, // Opcode: COPY_S_W + /* 11113 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 11135 + /* 11118 */ MCD_OPC_CheckPredicate, + 38, + 194, + 23, + 0, // Skip to: 17205 + /* 11123 */ MCD_OPC_CheckField, + 17, + 1, + 0, + 187, + 23, + 0, // Skip to: 17205 + /* 11130 */ MCD_OPC_Decode, + 187, + 9, + 160, + 2, // Opcode: COPY_S_D + /* 11135 */ MCD_OPC_FilterValue, + 3, + 177, + 23, + 0, // Skip to: 17205 + /* 11140 */ MCD_OPC_CheckPredicate, + 30, + 172, + 23, + 0, // Skip to: 17205 + /* 11145 */ MCD_OPC_CheckField, + 16, + 2, + 2, + 165, + 23, + 0, // Skip to: 17205 + /* 11152 */ MCD_OPC_Decode, + 161, + 16, + 161, + 2, // Opcode: MOVE_V + /* 11157 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 11172 + /* 11162 */ MCD_OPC_CheckPredicate, + 30, + 150, + 23, + 0, // Skip to: 17205 + /* 11167 */ MCD_OPC_Decode, + 190, + 9, + 157, + 2, // Opcode: COPY_U_B + /* 11172 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 11194 + /* 11177 */ MCD_OPC_CheckPredicate, + 30, + 135, + 23, + 0, // Skip to: 17205 + /* 11182 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 128, + 23, + 0, // Skip to: 17205 + /* 11189 */ MCD_OPC_Decode, + 191, + 9, + 158, + 2, // Opcode: COPY_U_H + /* 11194 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 11216 + /* 11199 */ MCD_OPC_CheckPredicate, + 38, + 113, + 23, + 0, // Skip to: 17205 + /* 11204 */ MCD_OPC_CheckField, + 18, + 2, + 0, + 106, + 23, + 0, // Skip to: 17205 + /* 11211 */ MCD_OPC_Decode, + 192, + 9, + 159, + 2, // Opcode: COPY_U_W + /* 11216 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 11231 + /* 11221 */ MCD_OPC_CheckPredicate, + 30, + 91, + 23, + 0, // Skip to: 17205 + /* 11226 */ MCD_OPC_Decode, + 226, + 13, + 162, + 2, // Opcode: INSERT_B + /* 11231 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 11253 + /* 11236 */ MCD_OPC_CheckPredicate, + 30, + 76, + 23, + 0, // Skip to: 17205 + /* 11241 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 69, + 23, + 0, // Skip to: 17205 + /* 11248 */ MCD_OPC_Decode, + 228, + 13, + 163, + 2, // Opcode: INSERT_H + /* 11253 */ MCD_OPC_FilterValue, + 19, + 40, + 0, + 0, // Skip to: 11298 + /* 11258 */ MCD_OPC_ExtractField, + 18, + 2, // Inst{19-18} ... + /* 11261 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11276 + /* 11266 */ MCD_OPC_CheckPredicate, + 30, + 46, + 23, + 0, // Skip to: 17205 + /* 11271 */ MCD_OPC_Decode, + 229, + 13, + 164, + 2, // Opcode: INSERT_W + /* 11276 */ MCD_OPC_FilterValue, + 2, + 36, + 23, + 0, // Skip to: 17205 + /* 11281 */ MCD_OPC_CheckPredicate, + 38, + 31, + 23, + 0, // Skip to: 17205 + /* 11286 */ MCD_OPC_CheckField, + 17, + 1, + 0, + 24, + 23, + 0, // Skip to: 17205 + /* 11293 */ MCD_OPC_Decode, + 227, + 13, + 165, + 2, // Opcode: INSERT_D + /* 11298 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 11313 + /* 11303 */ MCD_OPC_CheckPredicate, + 30, + 9, + 23, + 0, // Skip to: 17205 + /* 11308 */ MCD_OPC_Decode, + 231, + 13, + 166, + 2, // Opcode: INSVE_B + /* 11313 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 11335 + /* 11318 */ MCD_OPC_CheckPredicate, + 30, + 250, + 22, + 0, // Skip to: 17205 + /* 11323 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 243, + 22, + 0, // Skip to: 17205 + /* 11330 */ MCD_OPC_Decode, + 233, + 13, + 166, + 2, // Opcode: INSVE_H + /* 11335 */ MCD_OPC_FilterValue, + 23, + 233, + 22, + 0, // Skip to: 17205 + /* 11340 */ MCD_OPC_ExtractField, + 18, + 2, // Inst{19-18} ... + /* 11343 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11358 + /* 11348 */ MCD_OPC_CheckPredicate, + 30, + 220, + 22, + 0, // Skip to: 17205 + /* 11353 */ MCD_OPC_Decode, + 234, + 13, + 166, + 2, // Opcode: INSVE_W + /* 11358 */ MCD_OPC_FilterValue, + 2, + 210, + 22, + 0, // Skip to: 17205 + /* 11363 */ MCD_OPC_CheckPredicate, + 30, + 205, + 22, + 0, // Skip to: 17205 + /* 11368 */ MCD_OPC_CheckField, + 17, + 1, + 0, + 198, + 22, + 0, // Skip to: 17205 + /* 11375 */ MCD_OPC_Decode, + 232, + 13, + 166, + 2, // Opcode: INSVE_D + /* 11380 */ MCD_OPC_FilterValue, + 26, + 227, + 1, + 0, // Skip to: 11868 + /* 11385 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 11388 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11403 + /* 11393 */ MCD_OPC_CheckPredicate, + 30, + 175, + 22, + 0, // Skip to: 17205 + /* 11398 */ MCD_OPC_Decode, + 155, + 12, + 255, + 1, // Opcode: FCAF_W + /* 11403 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11418 + /* 11408 */ MCD_OPC_CheckPredicate, + 30, + 160, + 22, + 0, // Skip to: 17205 + /* 11413 */ MCD_OPC_Decode, + 154, + 12, + 128, + 2, // Opcode: FCAF_D + /* 11418 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11433 + /* 11423 */ MCD_OPC_CheckPredicate, + 30, + 145, + 22, + 0, // Skip to: 17205 + /* 11428 */ MCD_OPC_Decode, + 182, + 12, + 255, + 1, // Opcode: FCUN_W + /* 11433 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 11448 + /* 11438 */ MCD_OPC_CheckPredicate, + 30, + 130, + 22, + 0, // Skip to: 17205 + /* 11443 */ MCD_OPC_Decode, + 181, + 12, + 128, + 2, // Opcode: FCUN_D + /* 11448 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 11463 + /* 11453 */ MCD_OPC_CheckPredicate, + 30, + 115, + 22, + 0, // Skip to: 17205 + /* 11458 */ MCD_OPC_Decode, + 157, + 12, + 255, + 1, // Opcode: FCEQ_W + /* 11463 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 11478 + /* 11468 */ MCD_OPC_CheckPredicate, + 30, + 100, + 22, + 0, // Skip to: 17205 + /* 11473 */ MCD_OPC_Decode, + 156, + 12, + 128, + 2, // Opcode: FCEQ_D + /* 11478 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 11493 + /* 11483 */ MCD_OPC_CheckPredicate, + 30, + 85, + 22, + 0, // Skip to: 17205 + /* 11488 */ MCD_OPC_Decode, + 174, + 12, + 255, + 1, // Opcode: FCUEQ_W + /* 11493 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 11508 + /* 11498 */ MCD_OPC_CheckPredicate, + 30, + 70, + 22, + 0, // Skip to: 17205 + /* 11503 */ MCD_OPC_Decode, + 173, + 12, + 128, + 2, // Opcode: FCUEQ_D + /* 11508 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 11523 + /* 11513 */ MCD_OPC_CheckPredicate, + 30, + 55, + 22, + 0, // Skip to: 17205 + /* 11518 */ MCD_OPC_Decode, + 163, + 12, + 255, + 1, // Opcode: FCLT_W + /* 11523 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 11538 + /* 11528 */ MCD_OPC_CheckPredicate, + 30, + 40, + 22, + 0, // Skip to: 17205 + /* 11533 */ MCD_OPC_Decode, + 162, + 12, + 128, + 2, // Opcode: FCLT_D + /* 11538 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 11553 + /* 11543 */ MCD_OPC_CheckPredicate, + 30, + 25, + 22, + 0, // Skip to: 17205 + /* 11548 */ MCD_OPC_Decode, + 178, + 12, + 255, + 1, // Opcode: FCULT_W + /* 11553 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 11568 + /* 11558 */ MCD_OPC_CheckPredicate, + 30, + 10, + 22, + 0, // Skip to: 17205 + /* 11563 */ MCD_OPC_Decode, + 177, + 12, + 128, + 2, // Opcode: FCULT_D + /* 11568 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 11583 + /* 11573 */ MCD_OPC_CheckPredicate, + 30, + 251, + 21, + 0, // Skip to: 17205 + /* 11578 */ MCD_OPC_Decode, + 161, + 12, + 255, + 1, // Opcode: FCLE_W + /* 11583 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 11598 + /* 11588 */ MCD_OPC_CheckPredicate, + 30, + 236, + 21, + 0, // Skip to: 17205 + /* 11593 */ MCD_OPC_Decode, + 160, + 12, + 128, + 2, // Opcode: FCLE_D + /* 11598 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11613 + /* 11603 */ MCD_OPC_CheckPredicate, + 30, + 221, + 21, + 0, // Skip to: 17205 + /* 11608 */ MCD_OPC_Decode, + 176, + 12, + 255, + 1, // Opcode: FCULE_W + /* 11613 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 11628 + /* 11618 */ MCD_OPC_CheckPredicate, + 30, + 206, + 21, + 0, // Skip to: 17205 + /* 11623 */ MCD_OPC_Decode, + 175, + 12, + 128, + 2, // Opcode: FCULE_D + /* 11628 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 11643 + /* 11633 */ MCD_OPC_CheckPredicate, + 30, + 191, + 21, + 0, // Skip to: 17205 + /* 11638 */ MCD_OPC_Decode, + 142, + 13, + 255, + 1, // Opcode: FSAF_W + /* 11643 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 11658 + /* 11648 */ MCD_OPC_CheckPredicate, + 30, + 176, + 21, + 0, // Skip to: 17205 + /* 11653 */ MCD_OPC_Decode, + 141, + 13, + 128, + 2, // Opcode: FSAF_D + /* 11658 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 11673 + /* 11663 */ MCD_OPC_CheckPredicate, + 30, + 161, + 21, + 0, // Skip to: 17205 + /* 11668 */ MCD_OPC_Decode, + 180, + 13, + 255, + 1, // Opcode: FSUN_W + /* 11673 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 11688 + /* 11678 */ MCD_OPC_CheckPredicate, + 30, + 146, + 21, + 0, // Skip to: 17205 + /* 11683 */ MCD_OPC_Decode, + 179, + 13, + 128, + 2, // Opcode: FSUN_D + /* 11688 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 11703 + /* 11693 */ MCD_OPC_CheckPredicate, + 30, + 131, + 21, + 0, // Skip to: 17205 + /* 11698 */ MCD_OPC_Decode, + 144, + 13, + 255, + 1, // Opcode: FSEQ_W + /* 11703 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 11718 + /* 11708 */ MCD_OPC_CheckPredicate, + 30, + 116, + 21, + 0, // Skip to: 17205 + /* 11713 */ MCD_OPC_Decode, + 143, + 13, + 128, + 2, // Opcode: FSEQ_D + /* 11718 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 11733 + /* 11723 */ MCD_OPC_CheckPredicate, + 30, + 101, + 21, + 0, // Skip to: 17205 + /* 11728 */ MCD_OPC_Decode, + 172, + 13, + 255, + 1, // Opcode: FSUEQ_W + /* 11733 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 11748 + /* 11738 */ MCD_OPC_CheckPredicate, + 30, + 86, + 21, + 0, // Skip to: 17205 + /* 11743 */ MCD_OPC_Decode, + 171, + 13, + 128, + 2, // Opcode: FSUEQ_D + /* 11748 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 11763 + /* 11753 */ MCD_OPC_CheckPredicate, + 30, + 71, + 21, + 0, // Skip to: 17205 + /* 11758 */ MCD_OPC_Decode, + 148, + 13, + 255, + 1, // Opcode: FSLT_W + /* 11763 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 11778 + /* 11768 */ MCD_OPC_CheckPredicate, + 30, + 56, + 21, + 0, // Skip to: 17205 + /* 11773 */ MCD_OPC_Decode, + 147, + 13, + 128, + 2, // Opcode: FSLT_D + /* 11778 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 11793 + /* 11783 */ MCD_OPC_CheckPredicate, + 30, + 41, + 21, + 0, // Skip to: 17205 + /* 11788 */ MCD_OPC_Decode, + 176, + 13, + 255, + 1, // Opcode: FSULT_W + /* 11793 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 11808 + /* 11798 */ MCD_OPC_CheckPredicate, + 30, + 26, + 21, + 0, // Skip to: 17205 + /* 11803 */ MCD_OPC_Decode, + 175, + 13, + 128, + 2, // Opcode: FSULT_D + /* 11808 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 11823 + /* 11813 */ MCD_OPC_CheckPredicate, + 30, + 11, + 21, + 0, // Skip to: 17205 + /* 11818 */ MCD_OPC_Decode, + 146, + 13, + 255, + 1, // Opcode: FSLE_W + /* 11823 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 11838 + /* 11828 */ MCD_OPC_CheckPredicate, + 30, + 252, + 20, + 0, // Skip to: 17205 + /* 11833 */ MCD_OPC_Decode, + 145, + 13, + 128, + 2, // Opcode: FSLE_D + /* 11838 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 11853 + /* 11843 */ MCD_OPC_CheckPredicate, + 30, + 237, + 20, + 0, // Skip to: 17205 + /* 11848 */ MCD_OPC_Decode, + 174, + 13, + 255, + 1, // Opcode: FSULE_W + /* 11853 */ MCD_OPC_FilterValue, + 31, + 227, + 20, + 0, // Skip to: 17205 + /* 11858 */ MCD_OPC_CheckPredicate, + 30, + 222, + 20, + 0, // Skip to: 17205 + /* 11863 */ MCD_OPC_Decode, + 173, + 13, + 128, + 2, // Opcode: FSULE_D + /* 11868 */ MCD_OPC_FilterValue, + 27, + 137, + 1, + 0, // Skip to: 12266 + /* 11873 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 11876 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11891 + /* 11881 */ MCD_OPC_CheckPredicate, + 30, + 199, + 20, + 0, // Skip to: 17205 + /* 11886 */ MCD_OPC_Decode, + 153, + 12, + 255, + 1, // Opcode: FADD_W + /* 11891 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11906 + /* 11896 */ MCD_OPC_CheckPredicate, + 30, + 184, + 20, + 0, // Skip to: 17205 + /* 11901 */ MCD_OPC_Decode, + 144, + 12, + 128, + 2, // Opcode: FADD_D + /* 11906 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11921 + /* 11911 */ MCD_OPC_CheckPredicate, + 30, + 169, + 20, + 0, // Skip to: 17205 + /* 11916 */ MCD_OPC_Decode, + 170, + 13, + 255, + 1, // Opcode: FSUB_W + /* 11921 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 11936 + /* 11926 */ MCD_OPC_CheckPredicate, + 30, + 154, + 20, + 0, // Skip to: 17205 + /* 11931 */ MCD_OPC_Decode, + 161, + 13, + 128, + 2, // Opcode: FSUB_D + /* 11936 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 11951 + /* 11941 */ MCD_OPC_CheckPredicate, + 30, + 139, + 20, + 0, // Skip to: 17205 + /* 11946 */ MCD_OPC_Decode, + 254, + 12, + 255, + 1, // Opcode: FMUL_W + /* 11951 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 11966 + /* 11956 */ MCD_OPC_CheckPredicate, + 30, + 124, + 20, + 0, // Skip to: 17205 + /* 11961 */ MCD_OPC_Decode, + 245, + 12, + 128, + 2, // Opcode: FMUL_D + /* 11966 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 11981 + /* 11971 */ MCD_OPC_CheckPredicate, + 30, + 109, + 20, + 0, // Skip to: 17205 + /* 11976 */ MCD_OPC_Decode, + 191, + 12, + 255, + 1, // Opcode: FDIV_W + /* 11981 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 11996 + /* 11986 */ MCD_OPC_CheckPredicate, + 30, + 94, + 20, + 0, // Skip to: 17205 + /* 11991 */ MCD_OPC_Decode, + 183, + 12, + 128, + 2, // Opcode: FDIV_D + /* 11996 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 12011 + /* 12001 */ MCD_OPC_CheckPredicate, + 30, + 79, + 20, + 0, // Skip to: 17205 + /* 12006 */ MCD_OPC_Decode, + 226, + 12, + 131, + 2, // Opcode: FMADD_W + /* 12011 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 12026 + /* 12016 */ MCD_OPC_CheckPredicate, + 30, + 64, + 20, + 0, // Skip to: 17205 + /* 12021 */ MCD_OPC_Decode, + 225, + 12, + 132, + 2, // Opcode: FMADD_D + /* 12026 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 12041 + /* 12031 */ MCD_OPC_CheckPredicate, + 30, + 49, + 20, + 0, // Skip to: 17205 + /* 12036 */ MCD_OPC_Decode, + 244, + 12, + 131, + 2, // Opcode: FMSUB_W + /* 12041 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 12056 + /* 12046 */ MCD_OPC_CheckPredicate, + 30, + 34, + 20, + 0, // Skip to: 17205 + /* 12051 */ MCD_OPC_Decode, + 243, + 12, + 132, + 2, // Opcode: FMSUB_D + /* 12056 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12071 + /* 12061 */ MCD_OPC_CheckPredicate, + 30, + 19, + 20, + 0, // Skip to: 17205 + /* 12066 */ MCD_OPC_Decode, + 195, + 12, + 255, + 1, // Opcode: FEXP2_W + /* 12071 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 12086 + /* 12076 */ MCD_OPC_CheckPredicate, + 30, + 4, + 20, + 0, // Skip to: 17205 + /* 12081 */ MCD_OPC_Decode, + 194, + 12, + 128, + 2, // Opcode: FEXP2_D + /* 12086 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 12101 + /* 12091 */ MCD_OPC_CheckPredicate, + 30, + 245, + 19, + 0, // Skip to: 17205 + /* 12096 */ MCD_OPC_Decode, + 192, + 12, + 167, + 2, // Opcode: FEXDO_H + /* 12101 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 12116 + /* 12106 */ MCD_OPC_CheckPredicate, + 30, + 230, + 19, + 0, // Skip to: 17205 + /* 12111 */ MCD_OPC_Decode, + 193, + 12, + 168, + 2, // Opcode: FEXDO_W + /* 12116 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 12131 + /* 12121 */ MCD_OPC_CheckPredicate, + 30, + 215, + 19, + 0, // Skip to: 17205 + /* 12126 */ MCD_OPC_Decode, + 185, + 13, + 167, + 2, // Opcode: FTQ_H + /* 12131 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 12146 + /* 12136 */ MCD_OPC_CheckPredicate, + 30, + 200, + 19, + 0, // Skip to: 17205 + /* 12141 */ MCD_OPC_Decode, + 186, + 13, + 168, + 2, // Opcode: FTQ_W + /* 12146 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 12161 + /* 12151 */ MCD_OPC_CheckPredicate, + 30, + 185, + 19, + 0, // Skip to: 17205 + /* 12156 */ MCD_OPC_Decode, + 234, + 12, + 255, + 1, // Opcode: FMIN_W + /* 12161 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 12176 + /* 12166 */ MCD_OPC_CheckPredicate, + 30, + 170, + 19, + 0, // Skip to: 17205 + /* 12171 */ MCD_OPC_Decode, + 233, + 12, + 128, + 2, // Opcode: FMIN_D + /* 12176 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 12191 + /* 12181 */ MCD_OPC_CheckPredicate, + 30, + 155, + 19, + 0, // Skip to: 17205 + /* 12186 */ MCD_OPC_Decode, + 232, + 12, + 255, + 1, // Opcode: FMIN_A_W + /* 12191 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 12206 + /* 12196 */ MCD_OPC_CheckPredicate, + 30, + 140, + 19, + 0, // Skip to: 17205 + /* 12201 */ MCD_OPC_Decode, + 231, + 12, + 128, + 2, // Opcode: FMIN_A_D + /* 12206 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 12221 + /* 12211 */ MCD_OPC_CheckPredicate, + 30, + 125, + 19, + 0, // Skip to: 17205 + /* 12216 */ MCD_OPC_Decode, + 230, + 12, + 255, + 1, // Opcode: FMAX_W + /* 12221 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 12236 + /* 12226 */ MCD_OPC_CheckPredicate, + 30, + 110, + 19, + 0, // Skip to: 17205 + /* 12231 */ MCD_OPC_Decode, + 229, + 12, + 128, + 2, // Opcode: FMAX_D + /* 12236 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 12251 + /* 12241 */ MCD_OPC_CheckPredicate, + 30, + 95, + 19, + 0, // Skip to: 17205 + /* 12246 */ MCD_OPC_Decode, + 228, + 12, + 255, + 1, // Opcode: FMAX_A_W + /* 12251 */ MCD_OPC_FilterValue, + 31, + 85, + 19, + 0, // Skip to: 17205 + /* 12256 */ MCD_OPC_CheckPredicate, + 30, + 80, + 19, + 0, // Skip to: 17205 + /* 12261 */ MCD_OPC_Decode, + 227, + 12, + 128, + 2, // Opcode: FMAX_A_D + /* 12266 */ MCD_OPC_FilterValue, + 28, + 107, + 1, + 0, // Skip to: 12634 + /* 12271 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 12274 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12289 + /* 12279 */ MCD_OPC_CheckPredicate, + 30, + 57, + 19, + 0, // Skip to: 17205 + /* 12284 */ MCD_OPC_Decode, + 172, + 12, + 255, + 1, // Opcode: FCOR_W + /* 12289 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 12304 + /* 12294 */ MCD_OPC_CheckPredicate, + 30, + 42, + 19, + 0, // Skip to: 17205 + /* 12299 */ MCD_OPC_Decode, + 171, + 12, + 128, + 2, // Opcode: FCOR_D + /* 12304 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 12319 + /* 12309 */ MCD_OPC_CheckPredicate, + 30, + 27, + 19, + 0, // Skip to: 17205 + /* 12314 */ MCD_OPC_Decode, + 180, + 12, + 255, + 1, // Opcode: FCUNE_W + /* 12319 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 12334 + /* 12324 */ MCD_OPC_CheckPredicate, + 30, + 12, + 19, + 0, // Skip to: 17205 + /* 12329 */ MCD_OPC_Decode, + 179, + 12, + 128, + 2, // Opcode: FCUNE_D + /* 12334 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 12349 + /* 12339 */ MCD_OPC_CheckPredicate, + 30, + 253, + 18, + 0, // Skip to: 17205 + /* 12344 */ MCD_OPC_Decode, + 170, + 12, + 255, + 1, // Opcode: FCNE_W + /* 12349 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 12364 + /* 12354 */ MCD_OPC_CheckPredicate, + 30, + 238, + 18, + 0, // Skip to: 17205 + /* 12359 */ MCD_OPC_Decode, + 169, + 12, + 128, + 2, // Opcode: FCNE_D + /* 12364 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 12379 + /* 12369 */ MCD_OPC_CheckPredicate, + 30, + 223, + 18, + 0, // Skip to: 17205 + /* 12374 */ MCD_OPC_Decode, + 183, + 17, + 254, + 1, // Opcode: MUL_Q_H + /* 12379 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 12394 + /* 12384 */ MCD_OPC_CheckPredicate, + 30, + 208, + 18, + 0, // Skip to: 17205 + /* 12389 */ MCD_OPC_Decode, + 184, + 17, + 255, + 1, // Opcode: MUL_Q_W + /* 12394 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 12409 + /* 12399 */ MCD_OPC_CheckPredicate, + 30, + 193, + 18, + 0, // Skip to: 17205 + /* 12404 */ MCD_OPC_Decode, + 172, + 15, + 130, + 2, // Opcode: MADD_Q_H + /* 12409 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 12424 + /* 12414 */ MCD_OPC_CheckPredicate, + 30, + 178, + 18, + 0, // Skip to: 17205 + /* 12419 */ MCD_OPC_Decode, + 173, + 15, + 131, + 2, // Opcode: MADD_Q_W + /* 12424 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 12439 + /* 12429 */ MCD_OPC_CheckPredicate, + 30, + 163, + 18, + 0, // Skip to: 17205 + /* 12434 */ MCD_OPC_Decode, + 223, + 16, + 130, + 2, // Opcode: MSUB_Q_H + /* 12439 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 12454 + /* 12444 */ MCD_OPC_CheckPredicate, + 30, + 148, + 18, + 0, // Skip to: 17205 + /* 12449 */ MCD_OPC_Decode, + 224, + 16, + 131, + 2, // Opcode: MSUB_Q_W + /* 12454 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 12469 + /* 12459 */ MCD_OPC_CheckPredicate, + 30, + 133, + 18, + 0, // Skip to: 17205 + /* 12464 */ MCD_OPC_Decode, + 152, + 13, + 255, + 1, // Opcode: FSOR_W + /* 12469 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 12484 + /* 12474 */ MCD_OPC_CheckPredicate, + 30, + 118, + 18, + 0, // Skip to: 17205 + /* 12479 */ MCD_OPC_Decode, + 151, + 13, + 128, + 2, // Opcode: FSOR_D + /* 12484 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 12499 + /* 12489 */ MCD_OPC_CheckPredicate, + 30, + 103, + 18, + 0, // Skip to: 17205 + /* 12494 */ MCD_OPC_Decode, + 178, + 13, + 255, + 1, // Opcode: FSUNE_W + /* 12499 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 12514 + /* 12504 */ MCD_OPC_CheckPredicate, + 30, + 88, + 18, + 0, // Skip to: 17205 + /* 12509 */ MCD_OPC_Decode, + 177, + 13, + 128, + 2, // Opcode: FSUNE_D + /* 12514 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 12529 + /* 12519 */ MCD_OPC_CheckPredicate, + 30, + 73, + 18, + 0, // Skip to: 17205 + /* 12524 */ MCD_OPC_Decode, + 150, + 13, + 255, + 1, // Opcode: FSNE_W + /* 12529 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 12544 + /* 12534 */ MCD_OPC_CheckPredicate, + 30, + 58, + 18, + 0, // Skip to: 17205 + /* 12539 */ MCD_OPC_Decode, + 149, + 13, + 128, + 2, // Opcode: FSNE_D + /* 12544 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 12559 + /* 12549 */ MCD_OPC_CheckPredicate, + 30, + 43, + 18, + 0, // Skip to: 17205 + /* 12554 */ MCD_OPC_Decode, + 159, + 17, + 254, + 1, // Opcode: MULR_Q_H + /* 12559 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 12574 + /* 12564 */ MCD_OPC_CheckPredicate, + 30, + 28, + 18, + 0, // Skip to: 17205 + /* 12569 */ MCD_OPC_Decode, + 160, + 17, + 255, + 1, // Opcode: MULR_Q_W + /* 12574 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 12589 + /* 12579 */ MCD_OPC_CheckPredicate, + 30, + 13, + 18, + 0, // Skip to: 17205 + /* 12584 */ MCD_OPC_Decode, + 156, + 15, + 130, + 2, // Opcode: MADDR_Q_H + /* 12589 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 12604 + /* 12594 */ MCD_OPC_CheckPredicate, + 30, + 254, + 17, + 0, // Skip to: 17205 + /* 12599 */ MCD_OPC_Decode, + 157, + 15, + 131, + 2, // Opcode: MADDR_Q_W + /* 12604 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 12619 + /* 12609 */ MCD_OPC_CheckPredicate, + 30, + 239, + 17, + 0, // Skip to: 17205 + /* 12614 */ MCD_OPC_Decode, + 207, + 16, + 130, + 2, // Opcode: MSUBR_Q_H + /* 12619 */ MCD_OPC_FilterValue, + 29, + 229, + 17, + 0, // Skip to: 17205 + /* 12624 */ MCD_OPC_CheckPredicate, + 30, + 224, + 17, + 0, // Skip to: 17205 + /* 12629 */ MCD_OPC_Decode, + 208, + 16, + 131, + 2, // Opcode: MSUBR_Q_W + /* 12634 */ MCD_OPC_FilterValue, + 30, + 76, + 3, + 0, // Skip to: 13483 + /* 12639 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 12642 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 12657 + /* 12647 */ MCD_OPC_CheckPredicate, + 30, + 201, + 17, + 0, // Skip to: 17205 + /* 12652 */ MCD_OPC_Decode, + 155, + 6, + 253, + 1, // Opcode: AND_V + /* 12657 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 12672 + /* 12662 */ MCD_OPC_CheckPredicate, + 30, + 186, + 17, + 0, // Skip to: 17205 + /* 12667 */ MCD_OPC_Decode, + 228, + 17, + 253, + 1, // Opcode: OR_V + /* 12672 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12687 + /* 12677 */ MCD_OPC_CheckPredicate, + 30, + 171, + 17, + 0, // Skip to: 17205 + /* 12682 */ MCD_OPC_Decode, + 215, + 17, + 253, + 1, // Opcode: NOR_V + /* 12687 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 12702 + /* 12692 */ MCD_OPC_CheckPredicate, + 30, + 156, + 17, + 0, // Skip to: 17205 + /* 12697 */ MCD_OPC_Decode, + 153, + 22, + 253, + 1, // Opcode: XOR_V + /* 12702 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 12717 + /* 12707 */ MCD_OPC_CheckPredicate, + 30, + 141, + 17, + 0, // Skip to: 17205 + /* 12712 */ MCD_OPC_Decode, + 208, + 7, + 129, + 2, // Opcode: BMNZ_V + /* 12717 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 12732 + /* 12722 */ MCD_OPC_CheckPredicate, + 30, + 126, + 17, + 0, // Skip to: 17205 + /* 12727 */ MCD_OPC_Decode, + 210, + 7, + 129, + 2, // Opcode: BMZ_V + /* 12732 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 12747 + /* 12737 */ MCD_OPC_CheckPredicate, + 30, + 111, + 17, + 0, // Skip to: 17205 + /* 12742 */ MCD_OPC_Decode, + 252, + 7, + 129, + 2, // Opcode: BSEL_V + /* 12747 */ MCD_OPC_FilterValue, + 24, + 243, + 0, + 0, // Skip to: 12995 + /* 12752 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 12755 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 12770 + /* 12760 */ MCD_OPC_CheckPredicate, + 30, + 88, + 17, + 0, // Skip to: 17205 + /* 12765 */ MCD_OPC_Decode, + 208, + 12, + 169, + 2, // Opcode: FILL_B + /* 12770 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 12785 + /* 12775 */ MCD_OPC_CheckPredicate, + 30, + 73, + 17, + 0, // Skip to: 17205 + /* 12780 */ MCD_OPC_Decode, + 210, + 12, + 170, + 2, // Opcode: FILL_H + /* 12785 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12800 + /* 12790 */ MCD_OPC_CheckPredicate, + 30, + 58, + 17, + 0, // Skip to: 17205 + /* 12795 */ MCD_OPC_Decode, + 211, + 12, + 171, + 2, // Opcode: FILL_W + /* 12800 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 12815 + /* 12805 */ MCD_OPC_CheckPredicate, + 38, + 43, + 17, + 0, // Skip to: 17205 + /* 12810 */ MCD_OPC_Decode, + 209, + 12, + 172, + 2, // Opcode: FILL_D + /* 12815 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 12830 + /* 12820 */ MCD_OPC_CheckPredicate, + 30, + 28, + 17, + 0, // Skip to: 17205 + /* 12825 */ MCD_OPC_Decode, + 246, + 17, + 161, + 2, // Opcode: PCNT_B + /* 12830 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 12845 + /* 12835 */ MCD_OPC_CheckPredicate, + 30, + 13, + 17, + 0, // Skip to: 17205 + /* 12840 */ MCD_OPC_Decode, + 248, + 17, + 173, + 2, // Opcode: PCNT_H + /* 12845 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 12860 + /* 12850 */ MCD_OPC_CheckPredicate, + 30, + 254, + 16, + 0, // Skip to: 17205 + /* 12855 */ MCD_OPC_Decode, + 249, + 17, + 174, + 2, // Opcode: PCNT_W + /* 12860 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 12875 + /* 12865 */ MCD_OPC_CheckPredicate, + 30, + 239, + 16, + 0, // Skip to: 17205 + /* 12870 */ MCD_OPC_Decode, + 247, + 17, + 175, + 2, // Opcode: PCNT_D + /* 12875 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 12890 + /* 12880 */ MCD_OPC_CheckPredicate, + 30, + 224, + 16, + 0, // Skip to: 17205 + /* 12885 */ MCD_OPC_Decode, + 192, + 17, + 161, + 2, // Opcode: NLOC_B + /* 12890 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 12905 + /* 12895 */ MCD_OPC_CheckPredicate, + 30, + 209, + 16, + 0, // Skip to: 17205 + /* 12900 */ MCD_OPC_Decode, + 194, + 17, + 173, + 2, // Opcode: NLOC_H + /* 12905 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 12920 + /* 12910 */ MCD_OPC_CheckPredicate, + 30, + 194, + 16, + 0, // Skip to: 17205 + /* 12915 */ MCD_OPC_Decode, + 195, + 17, + 174, + 2, // Opcode: NLOC_W + /* 12920 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 12935 + /* 12925 */ MCD_OPC_CheckPredicate, + 30, + 179, + 16, + 0, // Skip to: 17205 + /* 12930 */ MCD_OPC_Decode, + 193, + 17, + 175, + 2, // Opcode: NLOC_D + /* 12935 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 12950 + /* 12940 */ MCD_OPC_CheckPredicate, + 30, + 164, + 16, + 0, // Skip to: 17205 + /* 12945 */ MCD_OPC_Decode, + 196, + 17, + 161, + 2, // Opcode: NLZC_B + /* 12950 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 12965 + /* 12955 */ MCD_OPC_CheckPredicate, + 30, + 149, + 16, + 0, // Skip to: 17205 + /* 12960 */ MCD_OPC_Decode, + 198, + 17, + 173, + 2, // Opcode: NLZC_H + /* 12965 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12980 + /* 12970 */ MCD_OPC_CheckPredicate, + 30, + 134, + 16, + 0, // Skip to: 17205 + /* 12975 */ MCD_OPC_Decode, + 199, + 17, + 174, + 2, // Opcode: NLZC_W + /* 12980 */ MCD_OPC_FilterValue, + 15, + 124, + 16, + 0, // Skip to: 17205 + /* 12985 */ MCD_OPC_CheckPredicate, + 30, + 119, + 16, + 0, // Skip to: 17205 + /* 12990 */ MCD_OPC_Decode, + 197, + 17, + 175, + 2, // Opcode: NLZC_D + /* 12995 */ MCD_OPC_FilterValue, + 25, + 109, + 16, + 0, // Skip to: 17205 + /* 13000 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 13003 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13018 + /* 13008 */ MCD_OPC_CheckPredicate, + 30, + 96, + 16, + 0, // Skip to: 17205 + /* 13013 */ MCD_OPC_Decode, + 159, + 12, + 174, + 2, // Opcode: FCLASS_W + /* 13018 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13033 + /* 13023 */ MCD_OPC_CheckPredicate, + 30, + 81, + 16, + 0, // Skip to: 17205 + /* 13028 */ MCD_OPC_Decode, + 158, + 12, + 175, + 2, // Opcode: FCLASS_D + /* 13033 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13048 + /* 13038 */ MCD_OPC_CheckPredicate, + 30, + 66, + 16, + 0, // Skip to: 17205 + /* 13043 */ MCD_OPC_Decode, + 188, + 13, + 174, + 2, // Opcode: FTRUNC_S_W + /* 13048 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 13063 + /* 13053 */ MCD_OPC_CheckPredicate, + 30, + 51, + 16, + 0, // Skip to: 17205 + /* 13058 */ MCD_OPC_Decode, + 187, + 13, + 175, + 2, // Opcode: FTRUNC_S_D + /* 13063 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 13078 + /* 13068 */ MCD_OPC_CheckPredicate, + 30, + 36, + 16, + 0, // Skip to: 17205 + /* 13073 */ MCD_OPC_Decode, + 190, + 13, + 174, + 2, // Opcode: FTRUNC_U_W + /* 13078 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 13093 + /* 13083 */ MCD_OPC_CheckPredicate, + 30, + 21, + 16, + 0, // Skip to: 17205 + /* 13088 */ MCD_OPC_Decode, + 189, + 13, + 175, + 2, // Opcode: FTRUNC_U_D + /* 13093 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 13108 + /* 13098 */ MCD_OPC_CheckPredicate, + 30, + 6, + 16, + 0, // Skip to: 17205 + /* 13103 */ MCD_OPC_Decode, + 160, + 13, + 174, + 2, // Opcode: FSQRT_W + /* 13108 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 13123 + /* 13113 */ MCD_OPC_CheckPredicate, + 30, + 247, + 15, + 0, // Skip to: 17205 + /* 13118 */ MCD_OPC_Decode, + 153, + 13, + 175, + 2, // Opcode: FSQRT_D + /* 13123 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 13138 + /* 13128 */ MCD_OPC_CheckPredicate, + 30, + 232, + 15, + 0, // Skip to: 17205 + /* 13133 */ MCD_OPC_Decode, + 140, + 13, + 174, + 2, // Opcode: FRSQRT_W + /* 13138 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 13153 + /* 13143 */ MCD_OPC_CheckPredicate, + 30, + 217, + 15, + 0, // Skip to: 17205 + /* 13148 */ MCD_OPC_Decode, + 139, + 13, + 175, + 2, // Opcode: FRSQRT_D + /* 13153 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 13168 + /* 13158 */ MCD_OPC_CheckPredicate, + 30, + 202, + 15, + 0, // Skip to: 17205 + /* 13163 */ MCD_OPC_Decode, + 136, + 13, + 174, + 2, // Opcode: FRCP_W + /* 13168 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 13183 + /* 13173 */ MCD_OPC_CheckPredicate, + 30, + 187, + 15, + 0, // Skip to: 17205 + /* 13178 */ MCD_OPC_Decode, + 135, + 13, + 175, + 2, // Opcode: FRCP_D + /* 13183 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 13198 + /* 13188 */ MCD_OPC_CheckPredicate, + 30, + 172, + 15, + 0, // Skip to: 17205 + /* 13193 */ MCD_OPC_Decode, + 138, + 13, + 174, + 2, // Opcode: FRINT_W + /* 13198 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 13213 + /* 13203 */ MCD_OPC_CheckPredicate, + 30, + 157, + 15, + 0, // Skip to: 17205 + /* 13208 */ MCD_OPC_Decode, + 137, + 13, + 175, + 2, // Opcode: FRINT_D + /* 13213 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 13228 + /* 13218 */ MCD_OPC_CheckPredicate, + 30, + 142, + 15, + 0, // Skip to: 17205 + /* 13223 */ MCD_OPC_Decode, + 213, + 12, + 174, + 2, // Opcode: FLOG2_W + /* 13228 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 13243 + /* 13233 */ MCD_OPC_CheckPredicate, + 30, + 127, + 15, + 0, // Skip to: 17205 + /* 13238 */ MCD_OPC_Decode, + 212, + 12, + 175, + 2, // Opcode: FLOG2_D + /* 13243 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 13258 + /* 13248 */ MCD_OPC_CheckPredicate, + 30, + 112, + 15, + 0, // Skip to: 17205 + /* 13253 */ MCD_OPC_Decode, + 197, + 12, + 176, + 2, // Opcode: FEXUPL_W + /* 13258 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 13273 + /* 13263 */ MCD_OPC_CheckPredicate, + 30, + 97, + 15, + 0, // Skip to: 17205 + /* 13268 */ MCD_OPC_Decode, + 196, + 12, + 177, + 2, // Opcode: FEXUPL_D + /* 13273 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 13288 + /* 13278 */ MCD_OPC_CheckPredicate, + 30, + 82, + 15, + 0, // Skip to: 17205 + /* 13283 */ MCD_OPC_Decode, + 199, + 12, + 176, + 2, // Opcode: FEXUPR_W + /* 13288 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 13303 + /* 13293 */ MCD_OPC_CheckPredicate, + 30, + 67, + 15, + 0, // Skip to: 17205 + /* 13298 */ MCD_OPC_Decode, + 198, + 12, + 177, + 2, // Opcode: FEXUPR_D + /* 13303 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 13318 + /* 13308 */ MCD_OPC_CheckPredicate, + 30, + 52, + 15, + 0, // Skip to: 17205 + /* 13313 */ MCD_OPC_Decode, + 205, + 12, + 176, + 2, // Opcode: FFQL_W + /* 13318 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 13333 + /* 13323 */ MCD_OPC_CheckPredicate, + 30, + 37, + 15, + 0, // Skip to: 17205 + /* 13328 */ MCD_OPC_Decode, + 204, + 12, + 177, + 2, // Opcode: FFQL_D + /* 13333 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 13348 + /* 13338 */ MCD_OPC_CheckPredicate, + 30, + 22, + 15, + 0, // Skip to: 17205 + /* 13343 */ MCD_OPC_Decode, + 207, + 12, + 176, + 2, // Opcode: FFQR_W + /* 13348 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 13363 + /* 13353 */ MCD_OPC_CheckPredicate, + 30, + 7, + 15, + 0, // Skip to: 17205 + /* 13358 */ MCD_OPC_Decode, + 206, + 12, + 177, + 2, // Opcode: FFQR_D + /* 13363 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 13378 + /* 13368 */ MCD_OPC_CheckPredicate, + 30, + 248, + 14, + 0, // Skip to: 17205 + /* 13373 */ MCD_OPC_Decode, + 182, + 13, + 174, + 2, // Opcode: FTINT_S_W + /* 13378 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 13393 + /* 13383 */ MCD_OPC_CheckPredicate, + 30, + 233, + 14, + 0, // Skip to: 17205 + /* 13388 */ MCD_OPC_Decode, + 181, + 13, + 175, + 2, // Opcode: FTINT_S_D + /* 13393 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 13408 + /* 13398 */ MCD_OPC_CheckPredicate, + 30, + 218, + 14, + 0, // Skip to: 17205 + /* 13403 */ MCD_OPC_Decode, + 184, + 13, + 174, + 2, // Opcode: FTINT_U_W + /* 13408 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 13423 + /* 13413 */ MCD_OPC_CheckPredicate, + 30, + 203, + 14, + 0, // Skip to: 17205 + /* 13418 */ MCD_OPC_Decode, + 183, + 13, + 175, + 2, // Opcode: FTINT_U_D + /* 13423 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 13438 + /* 13428 */ MCD_OPC_CheckPredicate, + 30, + 188, + 14, + 0, // Skip to: 17205 + /* 13433 */ MCD_OPC_Decode, + 201, + 12, + 174, + 2, // Opcode: FFINT_S_W + /* 13438 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 13453 + /* 13443 */ MCD_OPC_CheckPredicate, + 30, + 173, + 14, + 0, // Skip to: 17205 + /* 13448 */ MCD_OPC_Decode, + 200, + 12, + 175, + 2, // Opcode: FFINT_S_D + /* 13453 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 13468 + /* 13458 */ MCD_OPC_CheckPredicate, + 30, + 158, + 14, + 0, // Skip to: 17205 + /* 13463 */ MCD_OPC_Decode, + 203, + 12, + 174, + 2, // Opcode: FFINT_U_W + /* 13468 */ MCD_OPC_FilterValue, + 31, + 148, + 14, + 0, // Skip to: 17205 + /* 13473 */ MCD_OPC_CheckPredicate, + 30, + 143, + 14, + 0, // Skip to: 17205 + /* 13478 */ MCD_OPC_Decode, + 202, + 12, + 175, + 2, // Opcode: FFINT_U_D + /* 13483 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 13498 + /* 13488 */ MCD_OPC_CheckPredicate, + 30, + 128, + 14, + 0, // Skip to: 17205 + /* 13493 */ MCD_OPC_Decode, + 185, + 14, + 178, + 2, // Opcode: LD_B + /* 13498 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 13513 + /* 13503 */ MCD_OPC_CheckPredicate, + 30, + 113, + 14, + 0, // Skip to: 17205 + /* 13508 */ MCD_OPC_Decode, + 187, + 14, + 178, + 2, // Opcode: LD_H + /* 13513 */ MCD_OPC_FilterValue, + 34, + 10, + 0, + 0, // Skip to: 13528 + /* 13518 */ MCD_OPC_CheckPredicate, + 30, + 98, + 14, + 0, // Skip to: 17205 + /* 13523 */ MCD_OPC_Decode, + 188, + 14, + 178, + 2, // Opcode: LD_W + /* 13528 */ MCD_OPC_FilterValue, + 35, + 10, + 0, + 0, // Skip to: 13543 + /* 13533 */ MCD_OPC_CheckPredicate, + 30, + 83, + 14, + 0, // Skip to: 17205 + /* 13538 */ MCD_OPC_Decode, + 186, + 14, + 178, + 2, // Opcode: LD_D + /* 13543 */ MCD_OPC_FilterValue, + 36, + 10, + 0, + 0, // Skip to: 13558 + /* 13548 */ MCD_OPC_CheckPredicate, + 30, + 68, + 14, + 0, // Skip to: 17205 + /* 13553 */ MCD_OPC_Decode, + 196, + 20, + 178, + 2, // Opcode: ST_B + /* 13558 */ MCD_OPC_FilterValue, + 37, + 10, + 0, + 0, // Skip to: 13573 + /* 13563 */ MCD_OPC_CheckPredicate, + 30, + 53, + 14, + 0, // Skip to: 17205 + /* 13568 */ MCD_OPC_Decode, + 198, + 20, + 178, + 2, // Opcode: ST_H + /* 13573 */ MCD_OPC_FilterValue, + 38, + 10, + 0, + 0, // Skip to: 13588 + /* 13578 */ MCD_OPC_CheckPredicate, + 30, + 38, + 14, + 0, // Skip to: 17205 + /* 13583 */ MCD_OPC_Decode, + 199, + 20, + 178, + 2, // Opcode: ST_W + /* 13588 */ MCD_OPC_FilterValue, + 39, + 28, + 14, + 0, // Skip to: 17205 + /* 13593 */ MCD_OPC_CheckPredicate, + 30, + 23, + 14, + 0, // Skip to: 17205 + /* 13598 */ MCD_OPC_Decode, + 197, + 20, + 178, + 2, // Opcode: ST_D + /* 13603 */ MCD_OPC_FilterValue, + 31, + 165, + 12, + 0, // Skip to: 16845 + /* 13608 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 13611 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13626 + /* 13616 */ MCD_OPC_CheckPredicate, + 28, + 0, + 14, + 0, // Skip to: 17205 + /* 13621 */ MCD_OPC_Decode, + 237, + 11, + 179, + 2, // Opcode: EXT + /* 13626 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 13641 + /* 13631 */ MCD_OPC_CheckPredicate, + 28, + 241, + 13, + 0, // Skip to: 17205 + /* 13636 */ MCD_OPC_Decode, + 225, + 13, + 180, + 2, // Opcode: INS + /* 13641 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 13663 + /* 13646 */ MCD_OPC_CheckPredicate, + 42, + 226, + 13, + 0, // Skip to: 17205 + /* 13651 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 219, + 13, + 0, // Skip to: 17205 + /* 13658 */ MCD_OPC_Decode, + 134, + 13, + 181, + 2, // Opcode: FORK + /* 13663 */ MCD_OPC_FilterValue, + 9, + 23, + 0, + 0, // Skip to: 13691 + /* 13668 */ MCD_OPC_CheckPredicate, + 42, + 204, + 13, + 0, // Skip to: 17205 + /* 13673 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 197, + 13, + 0, // Skip to: 17205 + /* 13680 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 190, + 13, + 0, // Skip to: 17205 + /* 13687 */ MCD_OPC_Decode, + 158, + 22, + 14, // Opcode: YIELD + /* 13691 */ MCD_OPC_FilterValue, + 10, + 48, + 0, + 0, // Skip to: 13744 + /* 13696 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 13699 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13714 + /* 13704 */ MCD_OPC_CheckPredicate, + 37, + 168, + 13, + 0, // Skip to: 17205 + /* 13709 */ MCD_OPC_Decode, + 132, + 15, + 182, + 2, // Opcode: LWX + /* 13714 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 13729 + /* 13719 */ MCD_OPC_CheckPredicate, + 37, + 153, + 13, + 0, // Skip to: 17205 + /* 13724 */ MCD_OPC_Decode, + 197, + 14, + 182, + 2, // Opcode: LHX + /* 13729 */ MCD_OPC_FilterValue, + 6, + 143, + 13, + 0, // Skip to: 17205 + /* 13734 */ MCD_OPC_CheckPredicate, + 37, + 138, + 13, + 0, // Skip to: 17205 + /* 13739 */ MCD_OPC_Decode, + 157, + 14, + 182, + 2, // Opcode: LBUX + /* 13744 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 13766 + /* 13749 */ MCD_OPC_CheckPredicate, + 37, + 123, + 13, + 0, // Skip to: 17205 + /* 13754 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 116, + 13, + 0, // Skip to: 17205 + /* 13761 */ MCD_OPC_Decode, + 230, + 13, + 183, + 2, // Opcode: INSV + /* 13766 */ MCD_OPC_FilterValue, + 16, + 109, + 1, + 0, // Skip to: 14136 + /* 13771 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 13774 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13789 + /* 13779 */ MCD_OPC_CheckPredicate, + 37, + 93, + 13, + 0, // Skip to: 17205 + /* 13784 */ MCD_OPC_Decode, + 241, + 5, + 184, + 2, // Opcode: ADDU_QB + /* 13789 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13804 + /* 13794 */ MCD_OPC_CheckPredicate, + 37, + 78, + 13, + 0, // Skip to: 17205 + /* 13799 */ MCD_OPC_Decode, + 240, + 20, + 184, + 2, // Opcode: SUBU_QB + /* 13804 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 13819 + /* 13809 */ MCD_OPC_CheckPredicate, + 37, + 63, + 13, + 0, // Skip to: 17205 + /* 13814 */ MCD_OPC_Decode, + 245, + 5, + 184, + 2, // Opcode: ADDU_S_QB + /* 13819 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 13834 + /* 13824 */ MCD_OPC_CheckPredicate, + 37, + 48, + 13, + 0, // Skip to: 17205 + /* 13829 */ MCD_OPC_Decode, + 244, + 20, + 184, + 2, // Opcode: SUBU_S_QB + /* 13834 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 13849 + /* 13839 */ MCD_OPC_CheckPredicate, + 37, + 33, + 13, + 0, // Skip to: 17205 + /* 13844 */ MCD_OPC_Decode, + 146, + 17, + 184, + 2, // Opcode: MULEU_S_PH_QBL + /* 13849 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 13864 + /* 13854 */ MCD_OPC_CheckPredicate, + 37, + 18, + 13, + 0, // Skip to: 17205 + /* 13859 */ MCD_OPC_Decode, + 148, + 17, + 184, + 2, // Opcode: MULEU_S_PH_QBR + /* 13864 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 13879 + /* 13869 */ MCD_OPC_CheckPredicate, + 69, + 3, + 13, + 0, // Skip to: 17205 + /* 13874 */ MCD_OPC_Decode, + 239, + 5, + 184, + 2, // Opcode: ADDU_PH + /* 13879 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 13894 + /* 13884 */ MCD_OPC_CheckPredicate, + 69, + 244, + 12, + 0, // Skip to: 17205 + /* 13889 */ MCD_OPC_Decode, + 238, + 20, + 184, + 2, // Opcode: SUBU_PH + /* 13894 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 13909 + /* 13899 */ MCD_OPC_CheckPredicate, + 37, + 229, + 12, + 0, // Skip to: 17205 + /* 13904 */ MCD_OPC_Decode, + 211, + 5, + 184, + 2, // Opcode: ADDQ_PH + /* 13909 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 13924 + /* 13914 */ MCD_OPC_CheckPredicate, + 37, + 214, + 12, + 0, // Skip to: 17205 + /* 13919 */ MCD_OPC_Decode, + 209, + 20, + 184, + 2, // Opcode: SUBQ_PH + /* 13924 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 13939 + /* 13929 */ MCD_OPC_CheckPredicate, + 69, + 199, + 12, + 0, // Skip to: 17205 + /* 13934 */ MCD_OPC_Decode, + 243, + 5, + 184, + 2, // Opcode: ADDU_S_PH + /* 13939 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 13954 + /* 13944 */ MCD_OPC_CheckPredicate, + 69, + 184, + 12, + 0, // Skip to: 17205 + /* 13949 */ MCD_OPC_Decode, + 242, + 20, + 184, + 2, // Opcode: SUBU_S_PH + /* 13954 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 13969 + /* 13959 */ MCD_OPC_CheckPredicate, + 37, + 169, + 12, + 0, // Skip to: 17205 + /* 13964 */ MCD_OPC_Decode, + 213, + 5, + 184, + 2, // Opcode: ADDQ_S_PH + /* 13969 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 13984 + /* 13974 */ MCD_OPC_CheckPredicate, + 37, + 154, + 12, + 0, // Skip to: 17205 + /* 13979 */ MCD_OPC_Decode, + 211, + 20, + 184, + 2, // Opcode: SUBQ_S_PH + /* 13984 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 13998 + /* 13989 */ MCD_OPC_CheckPredicate, + 37, + 139, + 12, + 0, // Skip to: 17205 + /* 13994 */ MCD_OPC_Decode, + 218, + 5, + 50, // Opcode: ADDSC + /* 13998 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 14012 + /* 14003 */ MCD_OPC_CheckPredicate, + 37, + 125, + 12, + 0, // Skip to: 17205 + /* 14008 */ MCD_OPC_Decode, + 255, + 5, + 50, // Opcode: ADDWC + /* 14012 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 14026 + /* 14017 */ MCD_OPC_CheckPredicate, + 37, + 111, + 12, + 0, // Skip to: 17205 + /* 14022 */ MCD_OPC_Decode, + 144, + 16, + 50, // Opcode: MODSUB + /* 14026 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 14048 + /* 14031 */ MCD_OPC_CheckPredicate, + 37, + 97, + 12, + 0, // Skip to: 17205 + /* 14036 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 90, + 12, + 0, // Skip to: 17205 + /* 14043 */ MCD_OPC_Decode, + 174, + 18, + 185, + 2, // Opcode: RADDU_W_QB + /* 14048 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 14062 + /* 14053 */ MCD_OPC_CheckPredicate, + 37, + 75, + 12, + 0, // Skip to: 17205 + /* 14058 */ MCD_OPC_Decode, + 215, + 5, + 50, // Opcode: ADDQ_S_W + /* 14062 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 14076 + /* 14067 */ MCD_OPC_CheckPredicate, + 37, + 61, + 12, + 0, // Skip to: 17205 + /* 14072 */ MCD_OPC_Decode, + 213, + 20, + 50, // Opcode: SUBQ_S_W + /* 14076 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 14091 + /* 14081 */ MCD_OPC_CheckPredicate, + 37, + 47, + 12, + 0, // Skip to: 17205 + /* 14086 */ MCD_OPC_Decode, + 142, + 17, + 186, + 2, // Opcode: MULEQ_S_W_PHL + /* 14091 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 14106 + /* 14096 */ MCD_OPC_CheckPredicate, + 37, + 32, + 12, + 0, // Skip to: 17205 + /* 14101 */ MCD_OPC_Decode, + 144, + 17, + 186, + 2, // Opcode: MULEQ_S_W_PHR + /* 14106 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 14121 + /* 14111 */ MCD_OPC_CheckPredicate, + 69, + 17, + 12, + 0, // Skip to: 17205 + /* 14116 */ MCD_OPC_Decode, + 154, + 17, + 184, + 2, // Opcode: MULQ_S_PH + /* 14121 */ MCD_OPC_FilterValue, + 31, + 7, + 12, + 0, // Skip to: 17205 + /* 14126 */ MCD_OPC_CheckPredicate, + 37, + 2, + 12, + 0, // Skip to: 17205 + /* 14131 */ MCD_OPC_Decode, + 150, + 17, + 184, + 2, // Opcode: MULQ_RS_PH + /* 14136 */ MCD_OPC_FilterValue, + 17, + 113, + 1, + 0, // Skip to: 14510 + /* 14141 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 14144 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 14165 + /* 14149 */ MCD_OPC_CheckPredicate, + 37, + 235, + 11, + 0, // Skip to: 17205 + /* 14154 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 228, + 11, + 0, // Skip to: 17205 + /* 14161 */ MCD_OPC_Decode, + 238, + 8, + 68, // Opcode: CMPU_EQ_QB + /* 14165 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 14186 + /* 14170 */ MCD_OPC_CheckPredicate, + 37, + 214, + 11, + 0, // Skip to: 17205 + /* 14175 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 207, + 11, + 0, // Skip to: 17205 + /* 14182 */ MCD_OPC_Decode, + 242, + 8, + 68, // Opcode: CMPU_LT_QB + /* 14186 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 14207 + /* 14191 */ MCD_OPC_CheckPredicate, + 37, + 193, + 11, + 0, // Skip to: 17205 + /* 14196 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 186, + 11, + 0, // Skip to: 17205 + /* 14203 */ MCD_OPC_Decode, + 240, + 8, + 68, // Opcode: CMPU_LE_QB + /* 14207 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 14222 + /* 14212 */ MCD_OPC_CheckPredicate, + 37, + 172, + 11, + 0, // Skip to: 17205 + /* 14217 */ MCD_OPC_Decode, + 252, + 17, + 184, + 2, // Opcode: PICK_QB + /* 14222 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 14237 + /* 14227 */ MCD_OPC_CheckPredicate, + 37, + 157, + 11, + 0, // Skip to: 17205 + /* 14232 */ MCD_OPC_Decode, + 232, + 8, + 186, + 2, // Opcode: CMPGU_EQ_QB + /* 14237 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 14252 + /* 14242 */ MCD_OPC_CheckPredicate, + 37, + 142, + 11, + 0, // Skip to: 17205 + /* 14247 */ MCD_OPC_Decode, + 236, + 8, + 186, + 2, // Opcode: CMPGU_LT_QB + /* 14252 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 14267 + /* 14257 */ MCD_OPC_CheckPredicate, + 37, + 127, + 11, + 0, // Skip to: 17205 + /* 14262 */ MCD_OPC_Decode, + 234, + 8, + 186, + 2, // Opcode: CMPGU_LE_QB + /* 14267 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 14288 + /* 14272 */ MCD_OPC_CheckPredicate, + 37, + 112, + 11, + 0, // Skip to: 17205 + /* 14277 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 105, + 11, + 0, // Skip to: 17205 + /* 14284 */ MCD_OPC_Decode, + 248, + 8, + 68, // Opcode: CMP_EQ_PH + /* 14288 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 14309 + /* 14293 */ MCD_OPC_CheckPredicate, + 37, + 91, + 11, + 0, // Skip to: 17205 + /* 14298 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 84, + 11, + 0, // Skip to: 17205 + /* 14305 */ MCD_OPC_Decode, + 134, + 9, + 68, // Opcode: CMP_LT_PH + /* 14309 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 14330 + /* 14314 */ MCD_OPC_CheckPredicate, + 37, + 70, + 11, + 0, // Skip to: 17205 + /* 14319 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 63, + 11, + 0, // Skip to: 17205 + /* 14326 */ MCD_OPC_Decode, + 128, + 9, + 68, // Opcode: CMP_LE_PH + /* 14330 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 14345 + /* 14335 */ MCD_OPC_CheckPredicate, + 37, + 49, + 11, + 0, // Skip to: 17205 + /* 14340 */ MCD_OPC_Decode, + 250, + 17, + 184, + 2, // Opcode: PICK_PH + /* 14345 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 14360 + /* 14350 */ MCD_OPC_CheckPredicate, + 37, + 34, + 11, + 0, // Skip to: 17205 + /* 14355 */ MCD_OPC_Decode, + 153, + 18, + 184, + 2, // Opcode: PRECRQ_QB_PH + /* 14360 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 14375 + /* 14365 */ MCD_OPC_CheckPredicate, + 69, + 19, + 11, + 0, // Skip to: 17205 + /* 14370 */ MCD_OPC_Decode, + 157, + 18, + 184, + 2, // Opcode: PRECR_QB_PH + /* 14375 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14390 + /* 14380 */ MCD_OPC_CheckPredicate, + 37, + 4, + 11, + 0, // Skip to: 17205 + /* 14385 */ MCD_OPC_Decode, + 233, + 17, + 184, + 2, // Opcode: PACKRL_PH + /* 14390 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 14405 + /* 14395 */ MCD_OPC_CheckPredicate, + 37, + 245, + 10, + 0, // Skip to: 17205 + /* 14400 */ MCD_OPC_Decode, + 149, + 18, + 184, + 2, // Opcode: PRECRQU_S_QB_PH + /* 14405 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 14420 + /* 14410 */ MCD_OPC_CheckPredicate, + 37, + 230, + 10, + 0, // Skip to: 17205 + /* 14415 */ MCD_OPC_Decode, + 151, + 18, + 187, + 2, // Opcode: PRECRQ_PH_W + /* 14420 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 14435 + /* 14425 */ MCD_OPC_CheckPredicate, + 37, + 215, + 10, + 0, // Skip to: 17205 + /* 14430 */ MCD_OPC_Decode, + 155, + 18, + 187, + 2, // Opcode: PRECRQ_RS_PH_W + /* 14435 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 14450 + /* 14440 */ MCD_OPC_CheckPredicate, + 69, + 200, + 10, + 0, // Skip to: 17205 + /* 14445 */ MCD_OPC_Decode, + 226, + 8, + 186, + 2, // Opcode: CMPGDU_EQ_QB + /* 14450 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 14465 + /* 14455 */ MCD_OPC_CheckPredicate, + 69, + 185, + 10, + 0, // Skip to: 17205 + /* 14460 */ MCD_OPC_Decode, + 230, + 8, + 186, + 2, // Opcode: CMPGDU_LT_QB + /* 14465 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 14480 + /* 14470 */ MCD_OPC_CheckPredicate, + 69, + 170, + 10, + 0, // Skip to: 17205 + /* 14475 */ MCD_OPC_Decode, + 228, + 8, + 186, + 2, // Opcode: CMPGDU_LE_QB + /* 14480 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 14495 + /* 14485 */ MCD_OPC_CheckPredicate, + 69, + 155, + 10, + 0, // Skip to: 17205 + /* 14490 */ MCD_OPC_Decode, + 159, + 18, + 188, + 2, // Opcode: PRECR_SRA_PH_W + /* 14495 */ MCD_OPC_FilterValue, + 31, + 145, + 10, + 0, // Skip to: 17205 + /* 14500 */ MCD_OPC_CheckPredicate, + 69, + 140, + 10, + 0, // Skip to: 17205 + /* 14505 */ MCD_OPC_Decode, + 161, + 18, + 188, + 2, // Opcode: PRECR_SRA_R_PH_W + /* 14510 */ MCD_OPC_FilterValue, + 18, + 128, + 1, + 0, // Skip to: 14899 + /* 14515 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 14518 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 14540 + /* 14523 */ MCD_OPC_CheckPredicate, + 69, + 117, + 10, + 0, // Skip to: 17205 + /* 14528 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 110, + 10, + 0, // Skip to: 17205 + /* 14535 */ MCD_OPC_Decode, + 190, + 5, + 189, + 2, // Opcode: ABSQ_S_QB + /* 14540 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 14555 + /* 14545 */ MCD_OPC_CheckPredicate, + 37, + 95, + 10, + 0, // Skip to: 17205 + /* 14550 */ MCD_OPC_Decode, + 195, + 18, + 190, + 2, // Opcode: REPL_QB + /* 14555 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 14577 + /* 14560 */ MCD_OPC_CheckPredicate, + 37, + 80, + 10, + 0, // Skip to: 17205 + /* 14565 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 73, + 10, + 0, // Skip to: 17205 + /* 14572 */ MCD_OPC_Decode, + 191, + 18, + 191, + 2, // Opcode: REPLV_QB + /* 14577 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 14599 + /* 14582 */ MCD_OPC_CheckPredicate, + 37, + 58, + 10, + 0, // Skip to: 17205 + /* 14587 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 51, + 10, + 0, // Skip to: 17205 + /* 14594 */ MCD_OPC_Decode, + 129, + 18, + 189, + 2, // Opcode: PRECEQU_PH_QBL + /* 14599 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 14621 + /* 14604 */ MCD_OPC_CheckPredicate, + 37, + 36, + 10, + 0, // Skip to: 17205 + /* 14609 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 29, + 10, + 0, // Skip to: 17205 + /* 14616 */ MCD_OPC_Decode, + 133, + 18, + 189, + 2, // Opcode: PRECEQU_PH_QBR + /* 14621 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 14643 + /* 14626 */ MCD_OPC_CheckPredicate, + 37, + 14, + 10, + 0, // Skip to: 17205 + /* 14631 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 7, + 10, + 0, // Skip to: 17205 + /* 14638 */ MCD_OPC_Decode, + 130, + 18, + 189, + 2, // Opcode: PRECEQU_PH_QBLA + /* 14643 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 14665 + /* 14648 */ MCD_OPC_CheckPredicate, + 37, + 248, + 9, + 0, // Skip to: 17205 + /* 14653 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 241, + 9, + 0, // Skip to: 17205 + /* 14660 */ MCD_OPC_Decode, + 134, + 18, + 189, + 2, // Opcode: PRECEQU_PH_QBRA + /* 14665 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 14687 + /* 14670 */ MCD_OPC_CheckPredicate, + 37, + 226, + 9, + 0, // Skip to: 17205 + /* 14675 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 219, + 9, + 0, // Skip to: 17205 + /* 14682 */ MCD_OPC_Decode, + 188, + 5, + 189, + 2, // Opcode: ABSQ_S_PH + /* 14687 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 14701 + /* 14692 */ MCD_OPC_CheckPredicate, + 37, + 204, + 9, + 0, // Skip to: 17205 + /* 14697 */ MCD_OPC_Decode, + 193, + 18, + 85, // Opcode: REPL_PH + /* 14701 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 14723 + /* 14706 */ MCD_OPC_CheckPredicate, + 37, + 190, + 9, + 0, // Skip to: 17205 + /* 14711 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 183, + 9, + 0, // Skip to: 17205 + /* 14718 */ MCD_OPC_Decode, + 189, + 18, + 191, + 2, // Opcode: REPLV_PH + /* 14723 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 14745 + /* 14728 */ MCD_OPC_CheckPredicate, + 37, + 168, + 9, + 0, // Skip to: 17205 + /* 14733 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 161, + 9, + 0, // Skip to: 17205 + /* 14740 */ MCD_OPC_Decode, + 137, + 18, + 192, + 2, // Opcode: PRECEQ_W_PHL + /* 14745 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 14767 + /* 14750 */ MCD_OPC_CheckPredicate, + 37, + 146, + 9, + 0, // Skip to: 17205 + /* 14755 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 139, + 9, + 0, // Skip to: 17205 + /* 14762 */ MCD_OPC_Decode, + 139, + 18, + 192, + 2, // Opcode: PRECEQ_W_PHR + /* 14767 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 14789 + /* 14772 */ MCD_OPC_CheckPredicate, + 37, + 124, + 9, + 0, // Skip to: 17205 + /* 14777 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 117, + 9, + 0, // Skip to: 17205 + /* 14784 */ MCD_OPC_Decode, + 192, + 5, + 193, + 2, // Opcode: ABSQ_S_W + /* 14789 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 14811 + /* 14794 */ MCD_OPC_CheckPredicate, + 37, + 102, + 9, + 0, // Skip to: 17205 + /* 14799 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 95, + 9, + 0, // Skip to: 17205 + /* 14806 */ MCD_OPC_Decode, + 175, + 7, + 193, + 2, // Opcode: BITREV + /* 14811 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 14833 + /* 14816 */ MCD_OPC_CheckPredicate, + 37, + 80, + 9, + 0, // Skip to: 17205 + /* 14821 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 73, + 9, + 0, // Skip to: 17205 + /* 14828 */ MCD_OPC_Decode, + 141, + 18, + 189, + 2, // Opcode: PRECEU_PH_QBL + /* 14833 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 14855 + /* 14838 */ MCD_OPC_CheckPredicate, + 37, + 58, + 9, + 0, // Skip to: 17205 + /* 14843 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 51, + 9, + 0, // Skip to: 17205 + /* 14850 */ MCD_OPC_Decode, + 145, + 18, + 189, + 2, // Opcode: PRECEU_PH_QBR + /* 14855 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 14877 + /* 14860 */ MCD_OPC_CheckPredicate, + 37, + 36, + 9, + 0, // Skip to: 17205 + /* 14865 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 29, + 9, + 0, // Skip to: 17205 + /* 14872 */ MCD_OPC_Decode, + 142, + 18, + 189, + 2, // Opcode: PRECEU_PH_QBLA + /* 14877 */ MCD_OPC_FilterValue, + 31, + 19, + 9, + 0, // Skip to: 17205 + /* 14882 */ MCD_OPC_CheckPredicate, + 37, + 14, + 9, + 0, // Skip to: 17205 + /* 14887 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 7, + 9, + 0, // Skip to: 17205 + /* 14894 */ MCD_OPC_Decode, + 146, + 18, + 189, + 2, // Opcode: PRECEU_PH_QBRA + /* 14899 */ MCD_OPC_FilterValue, + 19, + 75, + 1, + 0, // Skip to: 15235 + /* 14904 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 14907 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14922 + /* 14912 */ MCD_OPC_CheckPredicate, + 37, + 240, + 8, + 0, // Skip to: 17205 + /* 14917 */ MCD_OPC_Decode, + 194, + 19, + 194, + 2, // Opcode: SHLL_QB + /* 14922 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 14937 + /* 14927 */ MCD_OPC_CheckPredicate, + 37, + 225, + 8, + 0, // Skip to: 17205 + /* 14932 */ MCD_OPC_Decode, + 226, + 19, + 194, + 2, // Opcode: SHRL_QB + /* 14937 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 14952 + /* 14942 */ MCD_OPC_CheckPredicate, + 37, + 210, + 8, + 0, // Skip to: 17205 + /* 14947 */ MCD_OPC_Decode, + 186, + 19, + 195, + 2, // Opcode: SHLLV_QB + /* 14952 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 14967 + /* 14957 */ MCD_OPC_CheckPredicate, + 37, + 195, + 8, + 0, // Skip to: 17205 + /* 14962 */ MCD_OPC_Decode, + 222, + 19, + 195, + 2, // Opcode: SHRLV_QB + /* 14967 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 14982 + /* 14972 */ MCD_OPC_CheckPredicate, + 69, + 180, + 8, + 0, // Skip to: 17205 + /* 14977 */ MCD_OPC_Decode, + 212, + 19, + 194, + 2, // Opcode: SHRA_QB + /* 14982 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 14997 + /* 14987 */ MCD_OPC_CheckPredicate, + 69, + 165, + 8, + 0, // Skip to: 17205 + /* 14992 */ MCD_OPC_Decode, + 216, + 19, + 194, + 2, // Opcode: SHRA_R_QB + /* 14997 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 15012 + /* 15002 */ MCD_OPC_CheckPredicate, + 69, + 150, + 8, + 0, // Skip to: 17205 + /* 15007 */ MCD_OPC_Decode, + 202, + 19, + 195, + 2, // Opcode: SHRAV_QB + /* 15012 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 15027 + /* 15017 */ MCD_OPC_CheckPredicate, + 69, + 135, + 8, + 0, // Skip to: 17205 + /* 15022 */ MCD_OPC_Decode, + 206, + 19, + 195, + 2, // Opcode: SHRAV_R_QB + /* 15027 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 15042 + /* 15032 */ MCD_OPC_CheckPredicate, + 37, + 120, + 8, + 0, // Skip to: 17205 + /* 15037 */ MCD_OPC_Decode, + 192, + 19, + 194, + 2, // Opcode: SHLL_PH + /* 15042 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 15057 + /* 15047 */ MCD_OPC_CheckPredicate, + 37, + 105, + 8, + 0, // Skip to: 17205 + /* 15052 */ MCD_OPC_Decode, + 210, + 19, + 194, + 2, // Opcode: SHRA_PH + /* 15057 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 15072 + /* 15062 */ MCD_OPC_CheckPredicate, + 37, + 90, + 8, + 0, // Skip to: 17205 + /* 15067 */ MCD_OPC_Decode, + 184, + 19, + 195, + 2, // Opcode: SHLLV_PH + /* 15072 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 15087 + /* 15077 */ MCD_OPC_CheckPredicate, + 37, + 75, + 8, + 0, // Skip to: 17205 + /* 15082 */ MCD_OPC_Decode, + 200, + 19, + 195, + 2, // Opcode: SHRAV_PH + /* 15087 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 15102 + /* 15092 */ MCD_OPC_CheckPredicate, + 37, + 60, + 8, + 0, // Skip to: 17205 + /* 15097 */ MCD_OPC_Decode, + 196, + 19, + 194, + 2, // Opcode: SHLL_S_PH + /* 15102 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 15117 + /* 15107 */ MCD_OPC_CheckPredicate, + 37, + 45, + 8, + 0, // Skip to: 17205 + /* 15112 */ MCD_OPC_Decode, + 214, + 19, + 194, + 2, // Opcode: SHRA_R_PH + /* 15117 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 15132 + /* 15122 */ MCD_OPC_CheckPredicate, + 37, + 30, + 8, + 0, // Skip to: 17205 + /* 15127 */ MCD_OPC_Decode, + 188, + 19, + 195, + 2, // Opcode: SHLLV_S_PH + /* 15132 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 15147 + /* 15137 */ MCD_OPC_CheckPredicate, + 37, + 15, + 8, + 0, // Skip to: 17205 + /* 15142 */ MCD_OPC_Decode, + 204, + 19, + 195, + 2, // Opcode: SHRAV_R_PH + /* 15147 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 15162 + /* 15152 */ MCD_OPC_CheckPredicate, + 37, + 0, + 8, + 0, // Skip to: 17205 + /* 15157 */ MCD_OPC_Decode, + 198, + 19, + 196, + 2, // Opcode: SHLL_S_W + /* 15162 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 15177 + /* 15167 */ MCD_OPC_CheckPredicate, + 37, + 241, + 7, + 0, // Skip to: 17205 + /* 15172 */ MCD_OPC_Decode, + 218, + 19, + 196, + 2, // Opcode: SHRA_R_W + /* 15177 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 15191 + /* 15182 */ MCD_OPC_CheckPredicate, + 37, + 226, + 7, + 0, // Skip to: 17205 + /* 15187 */ MCD_OPC_Decode, + 190, + 19, + 44, // Opcode: SHLLV_S_W + /* 15191 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 15205 + /* 15196 */ MCD_OPC_CheckPredicate, + 37, + 212, + 7, + 0, // Skip to: 17205 + /* 15201 */ MCD_OPC_Decode, + 208, + 19, + 44, // Opcode: SHRAV_R_W + /* 15205 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 15220 + /* 15210 */ MCD_OPC_CheckPredicate, + 69, + 198, + 7, + 0, // Skip to: 17205 + /* 15215 */ MCD_OPC_Decode, + 224, + 19, + 194, + 2, // Opcode: SHRL_PH + /* 15220 */ MCD_OPC_FilterValue, + 27, + 188, + 7, + 0, // Skip to: 17205 + /* 15225 */ MCD_OPC_CheckPredicate, + 69, + 183, + 7, + 0, // Skip to: 17205 + /* 15230 */ MCD_OPC_Decode, + 220, + 19, + 195, + 2, // Opcode: SHRLV_PH + /* 15235 */ MCD_OPC_FilterValue, + 24, + 237, + 0, + 0, // Skip to: 15477 + /* 15240 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 15243 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 15258 + /* 15248 */ MCD_OPC_CheckPredicate, + 69, + 160, + 7, + 0, // Skip to: 17205 + /* 15253 */ MCD_OPC_Decode, + 234, + 5, + 184, + 2, // Opcode: ADDUH_QB + /* 15258 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 15273 + /* 15263 */ MCD_OPC_CheckPredicate, + 69, + 145, + 7, + 0, // Skip to: 17205 + /* 15268 */ MCD_OPC_Decode, + 233, + 20, + 184, + 2, // Opcode: SUBUH_QB + /* 15273 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 15288 + /* 15278 */ MCD_OPC_CheckPredicate, + 69, + 130, + 7, + 0, // Skip to: 17205 + /* 15283 */ MCD_OPC_Decode, + 236, + 5, + 184, + 2, // Opcode: ADDUH_R_QB + /* 15288 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 15303 + /* 15293 */ MCD_OPC_CheckPredicate, + 69, + 115, + 7, + 0, // Skip to: 17205 + /* 15298 */ MCD_OPC_Decode, + 235, + 20, + 184, + 2, // Opcode: SUBUH_R_QB + /* 15303 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 15318 + /* 15308 */ MCD_OPC_CheckPredicate, + 69, + 100, + 7, + 0, // Skip to: 17205 + /* 15313 */ MCD_OPC_Decode, + 203, + 5, + 184, + 2, // Opcode: ADDQH_PH + /* 15318 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 15333 + /* 15323 */ MCD_OPC_CheckPredicate, + 69, + 85, + 7, + 0, // Skip to: 17205 + /* 15328 */ MCD_OPC_Decode, + 201, + 20, + 184, + 2, // Opcode: SUBQH_PH + /* 15333 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 15348 + /* 15338 */ MCD_OPC_CheckPredicate, + 69, + 70, + 7, + 0, // Skip to: 17205 + /* 15343 */ MCD_OPC_Decode, + 205, + 5, + 184, + 2, // Opcode: ADDQH_R_PH + /* 15348 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 15363 + /* 15353 */ MCD_OPC_CheckPredicate, + 69, + 55, + 7, + 0, // Skip to: 17205 + /* 15358 */ MCD_OPC_Decode, + 203, + 20, + 184, + 2, // Opcode: SUBQH_R_PH + /* 15363 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 15378 + /* 15368 */ MCD_OPC_CheckPredicate, + 69, + 40, + 7, + 0, // Skip to: 17205 + /* 15373 */ MCD_OPC_Decode, + 181, + 17, + 184, + 2, // Opcode: MUL_PH + /* 15378 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 15393 + /* 15383 */ MCD_OPC_CheckPredicate, + 69, + 25, + 7, + 0, // Skip to: 17205 + /* 15388 */ MCD_OPC_Decode, + 186, + 17, + 184, + 2, // Opcode: MUL_S_PH + /* 15393 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 15407 + /* 15398 */ MCD_OPC_CheckPredicate, + 69, + 10, + 7, + 0, // Skip to: 17205 + /* 15403 */ MCD_OPC_Decode, + 209, + 5, + 50, // Opcode: ADDQH_W + /* 15407 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 15421 + /* 15412 */ MCD_OPC_CheckPredicate, + 69, + 252, + 6, + 0, // Skip to: 17205 + /* 15417 */ MCD_OPC_Decode, + 207, + 20, + 50, // Opcode: SUBQH_W + /* 15421 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 15435 + /* 15426 */ MCD_OPC_CheckPredicate, + 69, + 238, + 6, + 0, // Skip to: 17205 + /* 15431 */ MCD_OPC_Decode, + 207, + 5, + 50, // Opcode: ADDQH_R_W + /* 15435 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 15449 + /* 15440 */ MCD_OPC_CheckPredicate, + 69, + 224, + 6, + 0, // Skip to: 17205 + /* 15445 */ MCD_OPC_Decode, + 205, + 20, + 50, // Opcode: SUBQH_R_W + /* 15449 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 15463 + /* 15454 */ MCD_OPC_CheckPredicate, + 69, + 210, + 6, + 0, // Skip to: 17205 + /* 15459 */ MCD_OPC_Decode, + 156, + 17, + 50, // Opcode: MULQ_S_W + /* 15463 */ MCD_OPC_FilterValue, + 23, + 201, + 6, + 0, // Skip to: 17205 + /* 15468 */ MCD_OPC_CheckPredicate, + 69, + 196, + 6, + 0, // Skip to: 17205 + /* 15473 */ MCD_OPC_Decode, + 152, + 17, + 50, // Opcode: MULQ_RS_W + /* 15477 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 15499 + /* 15482 */ MCD_OPC_CheckPredicate, + 70, + 182, + 6, + 0, // Skip to: 17205 + /* 15487 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 175, + 6, + 0, // Skip to: 17205 + /* 15494 */ MCD_OPC_Decode, + 243, + 14, + 197, + 2, // Opcode: LWLE + /* 15499 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 15521 + /* 15504 */ MCD_OPC_CheckPredicate, + 70, + 160, + 6, + 0, // Skip to: 17205 + /* 15509 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 153, + 6, + 0, // Skip to: 17205 + /* 15516 */ MCD_OPC_Decode, + 254, + 14, + 197, + 2, // Opcode: LWRE + /* 15521 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 15543 + /* 15526 */ MCD_OPC_CheckPredicate, + 43, + 138, + 6, + 0, // Skip to: 17205 + /* 15531 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 131, + 6, + 0, // Skip to: 17205 + /* 15538 */ MCD_OPC_Decode, + 150, + 8, + 198, + 2, // Opcode: CACHEE + /* 15543 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 15565 + /* 15548 */ MCD_OPC_CheckPredicate, + 43, + 116, + 6, + 0, // Skip to: 17205 + /* 15553 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 109, + 6, + 0, // Skip to: 17205 + /* 15560 */ MCD_OPC_Decode, + 238, + 18, + 197, + 2, // Opcode: SBE + /* 15565 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 15587 + /* 15570 */ MCD_OPC_CheckPredicate, + 43, + 94, + 6, + 0, // Skip to: 17205 + /* 15575 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 87, + 6, + 0, // Skip to: 17205 + /* 15582 */ MCD_OPC_Decode, + 175, + 19, + 197, + 2, // Opcode: SHE + /* 15587 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 15609 + /* 15592 */ MCD_OPC_CheckPredicate, + 43, + 72, + 6, + 0, // Skip to: 17205 + /* 15597 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 65, + 6, + 0, // Skip to: 17205 + /* 15604 */ MCD_OPC_Decode, + 247, + 18, + 197, + 2, // Opcode: SCE + /* 15609 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 15631 + /* 15614 */ MCD_OPC_CheckPredicate, + 43, + 50, + 6, + 0, // Skip to: 17205 + /* 15619 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 43, + 6, + 0, // Skip to: 17205 + /* 15626 */ MCD_OPC_Decode, + 145, + 21, + 197, + 2, // Opcode: SWE + /* 15631 */ MCD_OPC_FilterValue, + 32, + 69, + 0, + 0, // Skip to: 15705 + /* 15636 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 15639 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 15661 + /* 15644 */ MCD_OPC_CheckPredicate, + 28, + 20, + 6, + 0, // Skip to: 17205 + /* 15649 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 13, + 6, + 0, // Skip to: 17205 + /* 15656 */ MCD_OPC_Decode, + 142, + 22, + 193, + 2, // Opcode: WSBH + /* 15661 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 15683 + /* 15666 */ MCD_OPC_CheckPredicate, + 28, + 254, + 5, + 0, // Skip to: 17205 + /* 15671 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 247, + 5, + 0, // Skip to: 17205 + /* 15678 */ MCD_OPC_Decode, + 145, + 19, + 193, + 2, // Opcode: SEB + /* 15683 */ MCD_OPC_FilterValue, + 24, + 237, + 5, + 0, // Skip to: 17205 + /* 15688 */ MCD_OPC_CheckPredicate, + 28, + 232, + 5, + 0, // Skip to: 17205 + /* 15693 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 225, + 5, + 0, // Skip to: 17205 + /* 15700 */ MCD_OPC_Decode, + 148, + 19, + 193, + 2, // Opcode: SEH + /* 15705 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 15727 + /* 15710 */ MCD_OPC_CheckPredicate, + 70, + 210, + 5, + 0, // Skip to: 17205 + /* 15715 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 203, + 5, + 0, // Skip to: 17205 + /* 15722 */ MCD_OPC_Decode, + 149, + 21, + 197, + 2, // Opcode: SWLE + /* 15727 */ MCD_OPC_FilterValue, + 34, + 17, + 0, + 0, // Skip to: 15749 + /* 15732 */ MCD_OPC_CheckPredicate, + 70, + 188, + 5, + 0, // Skip to: 17205 + /* 15737 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 181, + 5, + 0, // Skip to: 17205 + /* 15744 */ MCD_OPC_Decode, + 158, + 21, + 197, + 2, // Opcode: SWRE + /* 15749 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 15771 + /* 15754 */ MCD_OPC_CheckPredicate, + 43, + 166, + 5, + 0, // Skip to: 17205 + /* 15759 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 159, + 5, + 0, // Skip to: 17205 + /* 15766 */ MCD_OPC_Decode, + 164, + 18, + 198, + 2, // Opcode: PREFE + /* 15771 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 15793 + /* 15776 */ MCD_OPC_CheckPredicate, + 43, + 144, + 5, + 0, // Skip to: 17205 + /* 15781 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 137, + 5, + 0, // Skip to: 17205 + /* 15788 */ MCD_OPC_Decode, + 164, + 14, + 197, + 2, // Opcode: LBuE + /* 15793 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 15815 + /* 15798 */ MCD_OPC_CheckPredicate, + 43, + 122, + 5, + 0, // Skip to: 17205 + /* 15803 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 115, + 5, + 0, // Skip to: 17205 + /* 15810 */ MCD_OPC_Decode, + 202, + 14, + 197, + 2, // Opcode: LHuE + /* 15815 */ MCD_OPC_FilterValue, + 44, + 17, + 0, + 0, // Skip to: 15837 + /* 15820 */ MCD_OPC_CheckPredicate, + 43, + 100, + 5, + 0, // Skip to: 17205 + /* 15825 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 93, + 5, + 0, // Skip to: 17205 + /* 15832 */ MCD_OPC_Decode, + 154, + 14, + 197, + 2, // Opcode: LBE + /* 15837 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 15859 + /* 15842 */ MCD_OPC_CheckPredicate, + 43, + 78, + 5, + 0, // Skip to: 17205 + /* 15847 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 71, + 5, + 0, // Skip to: 17205 + /* 15854 */ MCD_OPC_Decode, + 194, + 14, + 197, + 2, // Opcode: LHE + /* 15859 */ MCD_OPC_FilterValue, + 46, + 17, + 0, + 0, // Skip to: 15881 + /* 15864 */ MCD_OPC_CheckPredicate, + 43, + 56, + 5, + 0, // Skip to: 17205 + /* 15869 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 49, + 5, + 0, // Skip to: 17205 + /* 15876 */ MCD_OPC_Decode, + 212, + 14, + 197, + 2, // Opcode: LLE + /* 15881 */ MCD_OPC_FilterValue, + 47, + 17, + 0, + 0, // Skip to: 15903 + /* 15886 */ MCD_OPC_CheckPredicate, + 43, + 34, + 5, + 0, // Skip to: 17205 + /* 15891 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 27, + 5, + 0, // Skip to: 17205 + /* 15898 */ MCD_OPC_Decode, + 238, + 14, + 197, + 2, // Opcode: LWE + /* 15903 */ MCD_OPC_FilterValue, + 48, + 231, + 1, + 0, // Skip to: 16395 + /* 15908 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 15911 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 15933 + /* 15916 */ MCD_OPC_CheckPredicate, + 69, + 4, + 5, + 0, // Skip to: 17205 + /* 15921 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 253, + 4, + 0, // Skip to: 17205 + /* 15928 */ MCD_OPC_Decode, + 173, + 11, + 232, + 1, // Opcode: DPA_W_PH + /* 15933 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 15955 + /* 15938 */ MCD_OPC_CheckPredicate, + 69, + 238, + 4, + 0, // Skip to: 17205 + /* 15943 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 231, + 4, + 0, // Skip to: 17205 + /* 15950 */ MCD_OPC_Decode, + 196, + 11, + 232, + 1, // Opcode: DPS_W_PH + /* 15955 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 15977 + /* 15960 */ MCD_OPC_CheckPredicate, + 69, + 216, + 4, + 0, // Skip to: 17205 + /* 15965 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 209, + 4, + 0, // Skip to: 17205 + /* 15972 */ MCD_OPC_Decode, + 163, + 17, + 232, + 1, // Opcode: MULSA_W_PH + /* 15977 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 15999 + /* 15982 */ MCD_OPC_CheckPredicate, + 37, + 194, + 4, + 0, // Skip to: 17205 + /* 15987 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 187, + 4, + 0, // Skip to: 17205 + /* 15994 */ MCD_OPC_Decode, + 167, + 11, + 232, + 1, // Opcode: DPAU_H_QBL + /* 15999 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 16021 + /* 16004 */ MCD_OPC_CheckPredicate, + 37, + 172, + 4, + 0, // Skip to: 17205 + /* 16009 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 165, + 4, + 0, // Skip to: 17205 + /* 16016 */ MCD_OPC_Decode, + 165, + 11, + 232, + 1, // Opcode: DPAQ_S_W_PH + /* 16021 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 16043 + /* 16026 */ MCD_OPC_CheckPredicate, + 37, + 150, + 4, + 0, // Skip to: 17205 + /* 16031 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 143, + 4, + 0, // Skip to: 17205 + /* 16038 */ MCD_OPC_Decode, + 182, + 11, + 232, + 1, // Opcode: DPSQ_S_W_PH + /* 16043 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 16065 + /* 16048 */ MCD_OPC_CheckPredicate, + 37, + 128, + 4, + 0, // Skip to: 17205 + /* 16053 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 121, + 4, + 0, // Skip to: 17205 + /* 16060 */ MCD_OPC_Decode, + 161, + 17, + 232, + 1, // Opcode: MULSAQ_S_W_PH + /* 16065 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 16087 + /* 16070 */ MCD_OPC_CheckPredicate, + 37, + 106, + 4, + 0, // Skip to: 17205 + /* 16075 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 99, + 4, + 0, // Skip to: 17205 + /* 16082 */ MCD_OPC_Decode, + 169, + 11, + 232, + 1, // Opcode: DPAU_H_QBR + /* 16087 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 16109 + /* 16092 */ MCD_OPC_CheckPredicate, + 69, + 84, + 4, + 0, // Skip to: 17205 + /* 16097 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 77, + 4, + 0, // Skip to: 17205 + /* 16104 */ MCD_OPC_Decode, + 171, + 11, + 232, + 1, // Opcode: DPAX_W_PH + /* 16109 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 16131 + /* 16114 */ MCD_OPC_CheckPredicate, + 69, + 62, + 4, + 0, // Skip to: 17205 + /* 16119 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 55, + 4, + 0, // Skip to: 17205 + /* 16126 */ MCD_OPC_Decode, + 194, + 11, + 232, + 1, // Opcode: DPSX_W_PH + /* 16131 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 16153 + /* 16136 */ MCD_OPC_CheckPredicate, + 37, + 40, + 4, + 0, // Skip to: 17205 + /* 16141 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 33, + 4, + 0, // Skip to: 17205 + /* 16148 */ MCD_OPC_Decode, + 190, + 11, + 232, + 1, // Opcode: DPSU_H_QBL + /* 16153 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 16175 + /* 16158 */ MCD_OPC_CheckPredicate, + 37, + 18, + 4, + 0, // Skip to: 17205 + /* 16163 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 11, + 4, + 0, // Skip to: 17205 + /* 16170 */ MCD_OPC_Decode, + 163, + 11, + 232, + 1, // Opcode: DPAQ_SA_L_W + /* 16175 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 16197 + /* 16180 */ MCD_OPC_CheckPredicate, + 37, + 252, + 3, + 0, // Skip to: 17205 + /* 16185 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 245, + 3, + 0, // Skip to: 17205 + /* 16192 */ MCD_OPC_Decode, + 180, + 11, + 232, + 1, // Opcode: DPSQ_SA_L_W + /* 16197 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 16219 + /* 16202 */ MCD_OPC_CheckPredicate, + 37, + 230, + 3, + 0, // Skip to: 17205 + /* 16207 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 223, + 3, + 0, // Skip to: 17205 + /* 16214 */ MCD_OPC_Decode, + 192, + 11, + 232, + 1, // Opcode: DPSU_H_QBR + /* 16219 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 16241 + /* 16224 */ MCD_OPC_CheckPredicate, + 37, + 208, + 3, + 0, // Skip to: 17205 + /* 16229 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 201, + 3, + 0, // Skip to: 17205 + /* 16236 */ MCD_OPC_Decode, + 176, + 15, + 232, + 1, // Opcode: MAQ_SA_W_PHL + /* 16241 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 16263 + /* 16246 */ MCD_OPC_CheckPredicate, + 37, + 186, + 3, + 0, // Skip to: 17205 + /* 16251 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 179, + 3, + 0, // Skip to: 17205 + /* 16258 */ MCD_OPC_Decode, + 178, + 15, + 232, + 1, // Opcode: MAQ_SA_W_PHR + /* 16263 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 16285 + /* 16268 */ MCD_OPC_CheckPredicate, + 37, + 164, + 3, + 0, // Skip to: 17205 + /* 16273 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 157, + 3, + 0, // Skip to: 17205 + /* 16280 */ MCD_OPC_Decode, + 180, + 15, + 232, + 1, // Opcode: MAQ_S_W_PHL + /* 16285 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 16307 + /* 16290 */ MCD_OPC_CheckPredicate, + 37, + 142, + 3, + 0, // Skip to: 17205 + /* 16295 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 135, + 3, + 0, // Skip to: 17205 + /* 16302 */ MCD_OPC_Decode, + 182, + 15, + 232, + 1, // Opcode: MAQ_S_W_PHR + /* 16307 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 16329 + /* 16312 */ MCD_OPC_CheckPredicate, + 69, + 120, + 3, + 0, // Skip to: 17205 + /* 16317 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 113, + 3, + 0, // Skip to: 17205 + /* 16324 */ MCD_OPC_Decode, + 161, + 11, + 232, + 1, // Opcode: DPAQX_S_W_PH + /* 16329 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 16351 + /* 16334 */ MCD_OPC_CheckPredicate, + 69, + 98, + 3, + 0, // Skip to: 17205 + /* 16339 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 91, + 3, + 0, // Skip to: 17205 + /* 16346 */ MCD_OPC_Decode, + 178, + 11, + 232, + 1, // Opcode: DPSQX_S_W_PH + /* 16351 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 16373 + /* 16356 */ MCD_OPC_CheckPredicate, + 69, + 76, + 3, + 0, // Skip to: 17205 + /* 16361 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 69, + 3, + 0, // Skip to: 17205 + /* 16368 */ MCD_OPC_Decode, + 159, + 11, + 232, + 1, // Opcode: DPAQX_SA_W_PH + /* 16373 */ MCD_OPC_FilterValue, + 27, + 59, + 3, + 0, // Skip to: 17205 + /* 16378 */ MCD_OPC_CheckPredicate, + 69, + 54, + 3, + 0, // Skip to: 17205 + /* 16383 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 47, + 3, + 0, // Skip to: 17205 + /* 16390 */ MCD_OPC_Decode, + 176, + 11, + 232, + 1, // Opcode: DPSQX_SA_W_PH + /* 16395 */ MCD_OPC_FilterValue, + 49, + 48, + 0, + 0, // Skip to: 16448 + /* 16400 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 16403 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16418 + /* 16408 */ MCD_OPC_CheckPredicate, + 69, + 24, + 3, + 0, // Skip to: 17205 + /* 16413 */ MCD_OPC_Decode, + 159, + 6, + 199, + 2, // Opcode: APPEND + /* 16418 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 16433 + /* 16423 */ MCD_OPC_CheckPredicate, + 69, + 9, + 3, + 0, // Skip to: 17205 + /* 16428 */ MCD_OPC_Decode, + 170, + 18, + 199, + 2, // Opcode: PREPEND + /* 16433 */ MCD_OPC_FilterValue, + 16, + 255, + 2, + 0, // Skip to: 17205 + /* 16438 */ MCD_OPC_CheckPredicate, + 69, + 250, + 2, + 0, // Skip to: 17205 + /* 16443 */ MCD_OPC_Decode, + 203, + 6, + 199, + 2, // Opcode: BALIGN + /* 16448 */ MCD_OPC_FilterValue, + 56, + 107, + 1, + 0, // Skip to: 16816 + /* 16453 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 16456 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 16478 + /* 16461 */ MCD_OPC_CheckPredicate, + 37, + 227, + 2, + 0, // Skip to: 17205 + /* 16466 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 220, + 2, + 0, // Skip to: 17205 + /* 16473 */ MCD_OPC_Decode, + 132, + 12, + 200, + 2, // Opcode: EXTR_W + /* 16478 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 16500 + /* 16483 */ MCD_OPC_CheckPredicate, + 37, + 205, + 2, + 0, // Skip to: 17205 + /* 16488 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 198, + 2, + 0, // Skip to: 17205 + /* 16495 */ MCD_OPC_Decode, + 252, + 11, + 201, + 2, // Opcode: EXTRV_W + /* 16500 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 16522 + /* 16505 */ MCD_OPC_CheckPredicate, + 37, + 183, + 2, + 0, // Skip to: 17205 + /* 16510 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 176, + 2, + 0, // Skip to: 17205 + /* 16517 */ MCD_OPC_Decode, + 238, + 11, + 200, + 2, // Opcode: EXTP + /* 16522 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 16544 + /* 16527 */ MCD_OPC_CheckPredicate, + 37, + 161, + 2, + 0, // Skip to: 17205 + /* 16532 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 154, + 2, + 0, // Skip to: 17205 + /* 16539 */ MCD_OPC_Decode, + 243, + 11, + 201, + 2, // Opcode: EXTPV + /* 16544 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 16566 + /* 16549 */ MCD_OPC_CheckPredicate, + 37, + 139, + 2, + 0, // Skip to: 17205 + /* 16554 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 132, + 2, + 0, // Skip to: 17205 + /* 16561 */ MCD_OPC_Decode, + 128, + 12, + 200, + 2, // Opcode: EXTR_R_W + /* 16566 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 16588 + /* 16571 */ MCD_OPC_CheckPredicate, + 37, + 117, + 2, + 0, // Skip to: 17205 + /* 16576 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 110, + 2, + 0, // Skip to: 17205 + /* 16583 */ MCD_OPC_Decode, + 248, + 11, + 201, + 2, // Opcode: EXTRV_R_W + /* 16588 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 16610 + /* 16593 */ MCD_OPC_CheckPredicate, + 37, + 95, + 2, + 0, // Skip to: 17205 + /* 16598 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 88, + 2, + 0, // Skip to: 17205 + /* 16605 */ MCD_OPC_Decode, + 254, + 11, + 200, + 2, // Opcode: EXTR_RS_W + /* 16610 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 16632 + /* 16615 */ MCD_OPC_CheckPredicate, + 37, + 73, + 2, + 0, // Skip to: 17205 + /* 16620 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 66, + 2, + 0, // Skip to: 17205 + /* 16627 */ MCD_OPC_Decode, + 246, + 11, + 201, + 2, // Opcode: EXTRV_RS_W + /* 16632 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 16654 + /* 16637 */ MCD_OPC_CheckPredicate, + 37, + 51, + 2, + 0, // Skip to: 17205 + /* 16642 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 44, + 2, + 0, // Skip to: 17205 + /* 16649 */ MCD_OPC_Decode, + 239, + 11, + 200, + 2, // Opcode: EXTPDP + /* 16654 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 16676 + /* 16659 */ MCD_OPC_CheckPredicate, + 37, + 29, + 2, + 0, // Skip to: 17205 + /* 16664 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 22, + 2, + 0, // Skip to: 17205 + /* 16671 */ MCD_OPC_Decode, + 240, + 11, + 201, + 2, // Opcode: EXTPDPV + /* 16676 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16698 + /* 16681 */ MCD_OPC_CheckPredicate, + 37, + 7, + 2, + 0, // Skip to: 17205 + /* 16686 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 0, + 2, + 0, // Skip to: 17205 + /* 16693 */ MCD_OPC_Decode, + 130, + 12, + 200, + 2, // Opcode: EXTR_S_H + /* 16698 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 16720 + /* 16703 */ MCD_OPC_CheckPredicate, + 37, + 241, + 1, + 0, // Skip to: 17205 + /* 16708 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 234, + 1, + 0, // Skip to: 17205 + /* 16715 */ MCD_OPC_Decode, + 250, + 11, + 201, + 2, // Opcode: EXTRV_S_H + /* 16720 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 16735 + /* 16725 */ MCD_OPC_CheckPredicate, + 37, + 219, + 1, + 0, // Skip to: 17205 + /* 16730 */ MCD_OPC_Decode, + 176, + 18, + 202, + 2, // Opcode: RDDSP + /* 16735 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 16750 + /* 16740 */ MCD_OPC_CheckPredicate, + 40, + 204, + 1, + 0, // Skip to: 17205 + /* 16745 */ MCD_OPC_Decode, + 139, + 22, + 203, + 2, // Opcode: WRDSP + /* 16750 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 16772 + /* 16755 */ MCD_OPC_CheckPredicate, + 37, + 189, + 1, + 0, // Skip to: 17205 + /* 16760 */ MCD_OPC_CheckField, + 13, + 7, + 0, + 182, + 1, + 0, // Skip to: 17205 + /* 16767 */ MCD_OPC_Decode, + 180, + 19, + 204, + 2, // Opcode: SHILO + /* 16772 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 16794 + /* 16777 */ MCD_OPC_CheckPredicate, + 37, + 167, + 1, + 0, // Skip to: 17205 + /* 16782 */ MCD_OPC_CheckField, + 13, + 8, + 0, + 160, + 1, + 0, // Skip to: 17205 + /* 16789 */ MCD_OPC_Decode, + 181, + 19, + 205, + 2, // Opcode: SHILOV + /* 16794 */ MCD_OPC_FilterValue, + 31, + 150, + 1, + 0, // Skip to: 17205 + /* 16799 */ MCD_OPC_CheckPredicate, + 37, + 145, + 1, + 0, // Skip to: 17205 + /* 16804 */ MCD_OPC_CheckField, + 13, + 8, + 0, + 138, + 1, + 0, // Skip to: 17205 + /* 16811 */ MCD_OPC_Decode, + 251, + 16, + 205, + 2, // Opcode: MTHLIP + /* 16816 */ MCD_OPC_FilterValue, + 59, + 128, + 1, + 0, // Skip to: 17205 + /* 16821 */ MCD_OPC_CheckPredicate, + 27, + 123, + 1, + 0, // Skip to: 17205 + /* 16826 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 116, + 1, + 0, // Skip to: 17205 + /* 16833 */ MCD_OPC_CheckField, + 9, + 2, + 0, + 109, + 1, + 0, // Skip to: 17205 + /* 16840 */ MCD_OPC_Decode, + 178, + 18, + 206, + 2, // Opcode: RDHWR + /* 16845 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 16860 + /* 16850 */ MCD_OPC_CheckPredicate, + 27, + 94, + 1, + 0, // Skip to: 17205 + /* 16855 */ MCD_OPC_Decode, + 152, + 14, + 130, + 1, // Opcode: LB + /* 16860 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 16875 + /* 16865 */ MCD_OPC_CheckPredicate, + 27, + 79, + 1, + 0, // Skip to: 17205 + /* 16870 */ MCD_OPC_Decode, + 192, + 14, + 130, + 1, // Opcode: LH + /* 16875 */ MCD_OPC_FilterValue, + 34, + 10, + 0, + 0, // Skip to: 16890 + /* 16880 */ MCD_OPC_CheckPredicate, + 31, + 64, + 1, + 0, // Skip to: 17205 + /* 16885 */ MCD_OPC_Decode, + 241, + 14, + 130, + 1, // Opcode: LWL + /* 16890 */ MCD_OPC_FilterValue, + 35, + 10, + 0, + 0, // Skip to: 16905 + /* 16895 */ MCD_OPC_CheckPredicate, + 27, + 49, + 1, + 0, // Skip to: 17205 + /* 16900 */ MCD_OPC_Decode, + 227, + 14, + 130, + 1, // Opcode: LW + /* 16905 */ MCD_OPC_FilterValue, + 36, + 10, + 0, + 0, // Skip to: 16920 + /* 16910 */ MCD_OPC_CheckPredicate, + 27, + 34, + 1, + 0, // Skip to: 17205 + /* 16915 */ MCD_OPC_Decode, + 162, + 14, + 130, + 1, // Opcode: LBu + /* 16920 */ MCD_OPC_FilterValue, + 37, + 10, + 0, + 0, // Skip to: 16935 + /* 16925 */ MCD_OPC_CheckPredicate, + 27, + 19, + 1, + 0, // Skip to: 17205 + /* 16930 */ MCD_OPC_Decode, + 200, + 14, + 130, + 1, // Opcode: LHu + /* 16935 */ MCD_OPC_FilterValue, + 38, + 10, + 0, + 0, // Skip to: 16950 + /* 16940 */ MCD_OPC_CheckPredicate, + 31, + 4, + 1, + 0, // Skip to: 17205 + /* 16945 */ MCD_OPC_Decode, + 252, + 14, + 130, + 1, // Opcode: LWR + /* 16950 */ MCD_OPC_FilterValue, + 40, + 10, + 0, + 0, // Skip to: 16965 + /* 16955 */ MCD_OPC_CheckPredicate, + 27, + 245, + 0, + 0, // Skip to: 17205 + /* 16960 */ MCD_OPC_Decode, + 234, + 18, + 130, + 1, // Opcode: SB + /* 16965 */ MCD_OPC_FilterValue, + 41, + 10, + 0, + 0, // Skip to: 16980 + /* 16970 */ MCD_OPC_CheckPredicate, + 27, + 230, + 0, + 0, // Skip to: 17205 + /* 16975 */ MCD_OPC_Decode, + 171, + 19, + 130, + 1, // Opcode: SH + /* 16980 */ MCD_OPC_FilterValue, + 42, + 10, + 0, + 0, // Skip to: 16995 + /* 16985 */ MCD_OPC_CheckPredicate, + 31, + 215, + 0, + 0, // Skip to: 17205 + /* 16990 */ MCD_OPC_Decode, + 147, + 21, + 130, + 1, // Opcode: SWL + /* 16995 */ MCD_OPC_FilterValue, + 43, + 10, + 0, + 0, // Skip to: 17010 + /* 17000 */ MCD_OPC_CheckPredicate, + 27, + 200, + 0, + 0, // Skip to: 17205 + /* 17005 */ MCD_OPC_Decode, + 133, + 21, + 130, + 1, // Opcode: SW + /* 17010 */ MCD_OPC_FilterValue, + 46, + 10, + 0, + 0, // Skip to: 17025 + /* 17015 */ MCD_OPC_CheckPredicate, + 31, + 185, + 0, + 0, // Skip to: 17205 + /* 17020 */ MCD_OPC_Decode, + 156, + 21, + 130, + 1, // Opcode: SWR + /* 17025 */ MCD_OPC_FilterValue, + 47, + 10, + 0, + 0, // Skip to: 17040 + /* 17030 */ MCD_OPC_CheckPredicate, + 71, + 170, + 0, + 0, // Skip to: 17205 + /* 17035 */ MCD_OPC_Decode, + 149, + 8, + 207, + 2, // Opcode: CACHE + /* 17040 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 17055 + /* 17045 */ MCD_OPC_CheckPredicate, + 72, + 155, + 0, + 0, // Skip to: 17205 + /* 17050 */ MCD_OPC_Decode, + 207, + 14, + 130, + 1, // Opcode: LL + /* 17055 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 17070 + /* 17060 */ MCD_OPC_CheckPredicate, + 47, + 140, + 0, + 0, // Skip to: 17205 + /* 17065 */ MCD_OPC_Decode, + 230, + 14, + 208, + 2, // Opcode: LWC1 + /* 17070 */ MCD_OPC_FilterValue, + 50, + 10, + 0, + 0, // Skip to: 17085 + /* 17075 */ MCD_OPC_CheckPredicate, + 31, + 125, + 0, + 0, // Skip to: 17205 + /* 17080 */ MCD_OPC_Decode, + 232, + 14, + 209, + 2, // Opcode: LWC2 + /* 17085 */ MCD_OPC_FilterValue, + 51, + 10, + 0, + 0, // Skip to: 17100 + /* 17090 */ MCD_OPC_CheckPredicate, + 71, + 110, + 0, + 0, // Skip to: 17205 + /* 17095 */ MCD_OPC_Decode, + 163, + 18, + 207, + 2, // Opcode: PREF + /* 17100 */ MCD_OPC_FilterValue, + 53, + 10, + 0, + 0, // Skip to: 17115 + /* 17105 */ MCD_OPC_CheckPredicate, + 57, + 95, + 0, + 0, // Skip to: 17205 + /* 17110 */ MCD_OPC_Decode, + 168, + 14, + 208, + 2, // Opcode: LDC1 + /* 17115 */ MCD_OPC_FilterValue, + 54, + 10, + 0, + 0, // Skip to: 17130 + /* 17120 */ MCD_OPC_CheckPredicate, + 39, + 80, + 0, + 0, // Skip to: 17205 + /* 17125 */ MCD_OPC_Decode, + 172, + 14, + 209, + 2, // Opcode: LDC2 + /* 17130 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 17145 + /* 17135 */ MCD_OPC_CheckPredicate, + 72, + 65, + 0, + 0, // Skip to: 17205 + /* 17140 */ MCD_OPC_Decode, + 242, + 18, + 130, + 1, // Opcode: SC + /* 17145 */ MCD_OPC_FilterValue, + 57, + 10, + 0, + 0, // Skip to: 17160 + /* 17150 */ MCD_OPC_CheckPredicate, + 47, + 50, + 0, + 0, // Skip to: 17205 + /* 17155 */ MCD_OPC_Decode, + 137, + 21, + 208, + 2, // Opcode: SWC1 + /* 17160 */ MCD_OPC_FilterValue, + 58, + 10, + 0, + 0, // Skip to: 17175 + /* 17165 */ MCD_OPC_CheckPredicate, + 31, + 35, + 0, + 0, // Skip to: 17205 + /* 17170 */ MCD_OPC_Decode, + 139, + 21, + 209, + 2, // Opcode: SWC2 + /* 17175 */ MCD_OPC_FilterValue, + 61, + 10, + 0, + 0, // Skip to: 17190 + /* 17180 */ MCD_OPC_CheckPredicate, + 57, + 20, + 0, + 0, // Skip to: 17205 + /* 17185 */ MCD_OPC_Decode, + 131, + 19, + 208, + 2, // Opcode: SDC1 + /* 17190 */ MCD_OPC_FilterValue, + 62, + 10, + 0, + 0, // Skip to: 17205 + /* 17195 */ MCD_OPC_CheckPredicate, + 39, + 5, + 0, + 0, // Skip to: 17205 + /* 17200 */ MCD_OPC_Decode, + 135, + 19, + 209, + 2, // Opcode: SDC2 + /* 17205 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMips32_64_PTR6432[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 24 + /* 8 */ MCD_OPC_CheckPredicate, + 73, + 41, + 0, + 0, // Skip to: 54 + /* 13 */ MCD_OPC_CheckField, + 0, + 21, + 8, + 34, + 0, + 0, // Skip to: 54 + /* 20 */ MCD_OPC_Decode, + 135, + 14, + 13, // Opcode: JR64 + /* 24 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 39 + /* 29 */ MCD_OPC_CheckPredicate, + 74, + 20, + 0, + 0, // Skip to: 54 + /* 34 */ MCD_OPC_Decode, + 208, + 14, + 130, + 1, // Opcode: LL64 + /* 39 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 54 + /* 44 */ MCD_OPC_CheckPredicate, + 74, + 5, + 0, + 0, // Skip to: 54 + /* 49 */ MCD_OPC_Decode, + 243, + 18, + 130, + 1, // Opcode: SC64 + /* 54 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableMips32r6_64r632[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 29 -/* 14 */ MCD_OPC_CheckPredicate, 36, 37, 7, // Skip to: 1847 -/* 18 */ MCD_OPC_CheckField, 8, 3, 0, 31, 7, // Skip to: 1847 -/* 24 */ MCD_OPC_Decode, 206, 7, 221, 1, // Opcode: LSA_R6 -/* 29 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 47 -/* 33 */ MCD_OPC_CheckPredicate, 36, 18, 7, // Skip to: 1847 -/* 37 */ MCD_OPC_CheckField, 6, 15, 16, 12, 7, // Skip to: 1847 -/* 43 */ MCD_OPC_Decode, 142, 7, 61, // Opcode: JR_HB_R6 -/* 47 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 59 -/* 51 */ MCD_OPC_CheckPredicate, 36, 0, 7, // Skip to: 1847 -/* 55 */ MCD_OPC_Decode, 155, 11, 64, // Opcode: SDBBP_R6 -/* 59 */ MCD_OPC_FilterValue, 16, 20, 0, // Skip to: 83 -/* 63 */ MCD_OPC_CheckPredicate, 36, 244, 6, // Skip to: 1847 -/* 67 */ MCD_OPC_CheckField, 16, 5, 0, 238, 6, // Skip to: 1847 -/* 73 */ MCD_OPC_CheckField, 6, 5, 1, 232, 6, // Skip to: 1847 -/* 79 */ MCD_OPC_Decode, 154, 3, 62, // Opcode: CLZ_R6 -/* 83 */ MCD_OPC_FilterValue, 17, 20, 0, // Skip to: 107 -/* 87 */ MCD_OPC_CheckPredicate, 36, 220, 6, // Skip to: 1847 -/* 91 */ MCD_OPC_CheckField, 16, 5, 0, 214, 6, // Skip to: 1847 -/* 97 */ MCD_OPC_CheckField, 6, 5, 1, 208, 6, // Skip to: 1847 -/* 103 */ MCD_OPC_Decode, 135, 3, 62, // Opcode: CLO_R6 -/* 107 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 132 -/* 111 */ MCD_OPC_CheckPredicate, 37, 196, 6, // Skip to: 1847 -/* 115 */ MCD_OPC_CheckField, 16, 5, 0, 190, 6, // Skip to: 1847 -/* 121 */ MCD_OPC_CheckField, 6, 5, 1, 184, 6, // Skip to: 1847 -/* 127 */ MCD_OPC_Decode, 171, 4, 222, 1, // Opcode: DCLZ_R6 -/* 132 */ MCD_OPC_FilterValue, 19, 21, 0, // Skip to: 157 -/* 136 */ MCD_OPC_CheckPredicate, 37, 171, 6, // Skip to: 1847 -/* 140 */ MCD_OPC_CheckField, 16, 5, 0, 165, 6, // Skip to: 1847 -/* 146 */ MCD_OPC_CheckField, 6, 5, 1, 159, 6, // Skip to: 1847 -/* 152 */ MCD_OPC_Decode, 169, 4, 222, 1, // Opcode: DCLO_R6 -/* 157 */ MCD_OPC_FilterValue, 21, 15, 0, // Skip to: 176 -/* 161 */ MCD_OPC_CheckPredicate, 37, 146, 6, // Skip to: 1847 -/* 165 */ MCD_OPC_CheckField, 8, 3, 0, 140, 6, // Skip to: 1847 -/* 171 */ MCD_OPC_Decode, 195, 4, 223, 1, // Opcode: DLSA_R6 -/* 176 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 207 -/* 180 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 183 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 195 -/* 187 */ MCD_OPC_CheckPredicate, 36, 120, 6, // Skip to: 1847 -/* 191 */ MCD_OPC_Decode, 221, 9, 35, // Opcode: MUL_R6 -/* 195 */ MCD_OPC_FilterValue, 3, 112, 6, // Skip to: 1847 -/* 199 */ MCD_OPC_CheckPredicate, 36, 108, 6, // Skip to: 1847 -/* 203 */ MCD_OPC_Decode, 191, 9, 35, // Opcode: MUH -/* 207 */ MCD_OPC_FilterValue, 25, 27, 0, // Skip to: 238 -/* 211 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 214 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 226 -/* 218 */ MCD_OPC_CheckPredicate, 36, 89, 6, // Skip to: 1847 -/* 222 */ MCD_OPC_Decode, 212, 9, 35, // Opcode: MULU -/* 226 */ MCD_OPC_FilterValue, 3, 81, 6, // Skip to: 1847 -/* 230 */ MCD_OPC_CheckPredicate, 36, 77, 6, // Skip to: 1847 -/* 234 */ MCD_OPC_Decode, 192, 9, 35, // Opcode: MUHU -/* 238 */ MCD_OPC_FilterValue, 26, 27, 0, // Skip to: 269 -/* 242 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 245 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 257 -/* 249 */ MCD_OPC_CheckPredicate, 36, 58, 6, // Skip to: 1847 -/* 253 */ MCD_OPC_Decode, 183, 4, 35, // Opcode: DIV -/* 257 */ MCD_OPC_FilterValue, 3, 50, 6, // Skip to: 1847 -/* 261 */ MCD_OPC_CheckPredicate, 36, 46, 6, // Skip to: 1847 -/* 265 */ MCD_OPC_Decode, 222, 8, 35, // Opcode: MOD -/* 269 */ MCD_OPC_FilterValue, 27, 27, 0, // Skip to: 300 -/* 273 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 276 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 288 -/* 280 */ MCD_OPC_CheckPredicate, 36, 27, 6, // Skip to: 1847 -/* 284 */ MCD_OPC_Decode, 184, 4, 35, // Opcode: DIVU -/* 288 */ MCD_OPC_FilterValue, 3, 19, 6, // Skip to: 1847 -/* 292 */ MCD_OPC_CheckPredicate, 36, 15, 6, // Skip to: 1847 -/* 296 */ MCD_OPC_Decode, 224, 8, 35, // Opcode: MODU -/* 300 */ MCD_OPC_FilterValue, 28, 29, 0, // Skip to: 333 -/* 304 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 307 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 320 -/* 311 */ MCD_OPC_CheckPredicate, 37, 252, 5, // Skip to: 1847 -/* 315 */ MCD_OPC_Decode, 210, 4, 224, 1, // Opcode: DMUL_R6 -/* 320 */ MCD_OPC_FilterValue, 3, 243, 5, // Skip to: 1847 -/* 324 */ MCD_OPC_CheckPredicate, 37, 239, 5, // Skip to: 1847 -/* 328 */ MCD_OPC_Decode, 204, 4, 224, 1, // Opcode: DMUH -/* 333 */ MCD_OPC_FilterValue, 29, 29, 0, // Skip to: 366 -/* 337 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 353 -/* 344 */ MCD_OPC_CheckPredicate, 37, 219, 5, // Skip to: 1847 -/* 348 */ MCD_OPC_Decode, 209, 4, 224, 1, // Opcode: DMULU -/* 353 */ MCD_OPC_FilterValue, 3, 210, 5, // Skip to: 1847 -/* 357 */ MCD_OPC_CheckPredicate, 37, 206, 5, // Skip to: 1847 -/* 361 */ MCD_OPC_Decode, 205, 4, 224, 1, // Opcode: DMUHU -/* 366 */ MCD_OPC_FilterValue, 30, 29, 0, // Skip to: 399 -/* 370 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 386 -/* 377 */ MCD_OPC_CheckPredicate, 37, 186, 5, // Skip to: 1847 -/* 381 */ MCD_OPC_Decode, 172, 4, 224, 1, // Opcode: DDIV -/* 386 */ MCD_OPC_FilterValue, 3, 177, 5, // Skip to: 1847 -/* 390 */ MCD_OPC_CheckPredicate, 37, 173, 5, // Skip to: 1847 -/* 394 */ MCD_OPC_Decode, 199, 4, 224, 1, // Opcode: DMOD -/* 399 */ MCD_OPC_FilterValue, 31, 29, 0, // Skip to: 432 -/* 403 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 406 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 419 -/* 410 */ MCD_OPC_CheckPredicate, 37, 153, 5, // Skip to: 1847 -/* 414 */ MCD_OPC_Decode, 173, 4, 224, 1, // Opcode: DDIVU -/* 419 */ MCD_OPC_FilterValue, 3, 144, 5, // Skip to: 1847 -/* 423 */ MCD_OPC_CheckPredicate, 37, 140, 5, // Skip to: 1847 -/* 427 */ MCD_OPC_Decode, 200, 4, 224, 1, // Opcode: DMODU -/* 432 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 450 -/* 436 */ MCD_OPC_CheckPredicate, 38, 127, 5, // Skip to: 1847 -/* 440 */ MCD_OPC_CheckField, 6, 5, 0, 121, 5, // Skip to: 1847 -/* 446 */ MCD_OPC_Decode, 174, 11, 35, // Opcode: SELEQZ -/* 450 */ MCD_OPC_FilterValue, 55, 113, 5, // Skip to: 1847 -/* 454 */ MCD_OPC_CheckPredicate, 38, 109, 5, // Skip to: 1847 -/* 458 */ MCD_OPC_CheckField, 6, 5, 0, 103, 5, // Skip to: 1847 -/* 464 */ MCD_OPC_Decode, 178, 11, 35, // Opcode: SELNEZ -/* 468 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 519 -/* 472 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 475 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 488 -/* 479 */ MCD_OPC_CheckPredicate, 37, 84, 5, // Skip to: 1847 -/* 483 */ MCD_OPC_Decode, 163, 4, 225, 1, // Opcode: DAHI -/* 488 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 506 -/* 492 */ MCD_OPC_CheckPredicate, 36, 71, 5, // Skip to: 1847 -/* 496 */ MCD_OPC_CheckField, 21, 5, 0, 65, 5, // Skip to: 1847 -/* 502 */ MCD_OPC_Decode, 167, 1, 75, // Opcode: BAL -/* 506 */ MCD_OPC_FilterValue, 30, 57, 5, // Skip to: 1847 -/* 510 */ MCD_OPC_CheckPredicate, 37, 53, 5, // Skip to: 1847 -/* 514 */ MCD_OPC_Decode, 165, 4, 225, 1, // Opcode: DATI -/* 519 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 532 -/* 523 */ MCD_OPC_CheckPredicate, 36, 40, 5, // Skip to: 1847 -/* 527 */ MCD_OPC_Decode, 220, 1, 226, 1, // Opcode: BGEZALC -/* 532 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 545 -/* 536 */ MCD_OPC_CheckPredicate, 36, 27, 5, // Skip to: 1847 -/* 540 */ MCD_OPC_Decode, 134, 2, 227, 1, // Opcode: BLTZALC -/* 545 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 558 -/* 549 */ MCD_OPC_CheckPredicate, 36, 14, 5, // Skip to: 1847 -/* 553 */ MCD_OPC_Decode, 208, 1, 228, 1, // Opcode: BEQC -/* 558 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 570 -/* 562 */ MCD_OPC_CheckPredicate, 36, 1, 5, // Skip to: 1847 -/* 566 */ MCD_OPC_Decode, 137, 1, 47, // Opcode: AUI -/* 570 */ MCD_OPC_FilterValue, 17, 5, 3, // Skip to: 1347 -/* 574 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 577 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 590 -/* 581 */ MCD_OPC_CheckPredicate, 36, 238, 4, // Skip to: 1847 -/* 585 */ MCD_OPC_Decode, 180, 1, 229, 1, // Opcode: BC1EQZ -/* 590 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 603 -/* 594 */ MCD_OPC_CheckPredicate, 36, 225, 4, // Skip to: 1847 -/* 598 */ MCD_OPC_Decode, 184, 1, 229, 1, // Opcode: BC1NEZ -/* 603 */ MCD_OPC_FilterValue, 16, 150, 0, // Skip to: 757 -/* 607 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 610 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 623 -/* 614 */ MCD_OPC_CheckPredicate, 36, 205, 4, // Skip to: 1847 -/* 618 */ MCD_OPC_Decode, 183, 11, 230, 1, // Opcode: SEL_S -/* 623 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 635 -/* 627 */ MCD_OPC_CheckPredicate, 36, 192, 4, // Skip to: 1847 -/* 631 */ MCD_OPC_Decode, 177, 11, 93, // Opcode: SELEQZ_S -/* 635 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 647 -/* 639 */ MCD_OPC_CheckPredicate, 36, 180, 4, // Skip to: 1847 -/* 643 */ MCD_OPC_Decode, 181, 11, 93, // Opcode: SELNEZ_S -/* 647 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 660 -/* 651 */ MCD_OPC_CheckPredicate, 36, 168, 4, // Skip to: 1847 -/* 655 */ MCD_OPC_Decode, 132, 8, 231, 1, // Opcode: MADDF_S -/* 660 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 673 -/* 664 */ MCD_OPC_CheckPredicate, 36, 155, 4, // Skip to: 1847 -/* 668 */ MCD_OPC_Decode, 150, 9, 231, 1, // Opcode: MSUBF_S -/* 673 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 691 -/* 677 */ MCD_OPC_CheckPredicate, 36, 142, 4, // Skip to: 1847 -/* 681 */ MCD_OPC_CheckField, 16, 5, 0, 136, 4, // Skip to: 1847 -/* 687 */ MCD_OPC_Decode, 246, 10, 94, // Opcode: RINT_S -/* 691 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 709 -/* 695 */ MCD_OPC_CheckPredicate, 36, 124, 4, // Skip to: 1847 -/* 699 */ MCD_OPC_CheckField, 16, 5, 0, 118, 4, // Skip to: 1847 -/* 705 */ MCD_OPC_Decode, 244, 2, 94, // Opcode: CLASS_S -/* 709 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 721 -/* 713 */ MCD_OPC_CheckPredicate, 36, 106, 4, // Skip to: 1847 -/* 717 */ MCD_OPC_Decode, 211, 8, 93, // Opcode: MIN_S -/* 721 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 733 -/* 725 */ MCD_OPC_CheckPredicate, 36, 94, 4, // Skip to: 1847 -/* 729 */ MCD_OPC_Decode, 170, 8, 93, // Opcode: MAX_S -/* 733 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 745 -/* 737 */ MCD_OPC_CheckPredicate, 36, 82, 4, // Skip to: 1847 -/* 741 */ MCD_OPC_Decode, 197, 8, 93, // Opcode: MINA_S -/* 745 */ MCD_OPC_FilterValue, 31, 74, 4, // Skip to: 1847 -/* 749 */ MCD_OPC_CheckPredicate, 36, 70, 4, // Skip to: 1847 -/* 753 */ MCD_OPC_Decode, 156, 8, 93, // Opcode: MAXA_S -/* 757 */ MCD_OPC_FilterValue, 17, 156, 0, // Skip to: 917 -/* 761 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 764 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 777 -/* 768 */ MCD_OPC_CheckPredicate, 36, 51, 4, // Skip to: 1847 -/* 772 */ MCD_OPC_Decode, 182, 11, 232, 1, // Opcode: SEL_D -/* 777 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 790 -/* 781 */ MCD_OPC_CheckPredicate, 36, 38, 4, // Skip to: 1847 -/* 785 */ MCD_OPC_Decode, 176, 11, 233, 1, // Opcode: SELEQZ_D -/* 790 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 803 -/* 794 */ MCD_OPC_CheckPredicate, 36, 25, 4, // Skip to: 1847 -/* 798 */ MCD_OPC_Decode, 180, 11, 233, 1, // Opcode: SELNEZ_D -/* 803 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 816 -/* 807 */ MCD_OPC_CheckPredicate, 36, 12, 4, // Skip to: 1847 -/* 811 */ MCD_OPC_Decode, 131, 8, 234, 1, // Opcode: MADDF_D -/* 816 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 829 -/* 820 */ MCD_OPC_CheckPredicate, 36, 255, 3, // Skip to: 1847 -/* 824 */ MCD_OPC_Decode, 149, 9, 234, 1, // Opcode: MSUBF_D -/* 829 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 847 -/* 833 */ MCD_OPC_CheckPredicate, 36, 242, 3, // Skip to: 1847 -/* 837 */ MCD_OPC_CheckField, 16, 5, 0, 236, 3, // Skip to: 1847 -/* 843 */ MCD_OPC_Decode, 245, 10, 105, // Opcode: RINT_D -/* 847 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 865 -/* 851 */ MCD_OPC_CheckPredicate, 36, 224, 3, // Skip to: 1847 -/* 855 */ MCD_OPC_CheckField, 16, 5, 0, 218, 3, // Skip to: 1847 -/* 861 */ MCD_OPC_Decode, 243, 2, 105, // Opcode: CLASS_D -/* 865 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 878 -/* 869 */ MCD_OPC_CheckPredicate, 36, 206, 3, // Skip to: 1847 -/* 873 */ MCD_OPC_Decode, 210, 8, 233, 1, // Opcode: MIN_D -/* 878 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 891 -/* 882 */ MCD_OPC_CheckPredicate, 36, 193, 3, // Skip to: 1847 -/* 886 */ MCD_OPC_Decode, 169, 8, 233, 1, // Opcode: MAX_D -/* 891 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 904 -/* 895 */ MCD_OPC_CheckPredicate, 36, 180, 3, // Skip to: 1847 -/* 899 */ MCD_OPC_Decode, 196, 8, 233, 1, // Opcode: MINA_D -/* 904 */ MCD_OPC_FilterValue, 31, 171, 3, // Skip to: 1847 -/* 908 */ MCD_OPC_CheckPredicate, 36, 167, 3, // Skip to: 1847 -/* 912 */ MCD_OPC_Decode, 155, 8, 233, 1, // Opcode: MAXA_D -/* 917 */ MCD_OPC_FilterValue, 20, 211, 0, // Skip to: 1132 -/* 921 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 924 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 937 -/* 928 */ MCD_OPC_CheckPredicate, 36, 147, 3, // Skip to: 1847 -/* 932 */ MCD_OPC_Decode, 168, 3, 235, 1, // Opcode: CMP_F_S -/* 937 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 950 -/* 941 */ MCD_OPC_CheckPredicate, 36, 134, 3, // Skip to: 1847 -/* 945 */ MCD_OPC_Decode, 198, 3, 235, 1, // Opcode: CMP_UN_S -/* 950 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 963 -/* 954 */ MCD_OPC_CheckPredicate, 36, 121, 3, // Skip to: 1847 -/* 958 */ MCD_OPC_Decode, 166, 3, 235, 1, // Opcode: CMP_EQ_S -/* 963 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 976 -/* 967 */ MCD_OPC_CheckPredicate, 36, 108, 3, // Skip to: 1847 -/* 971 */ MCD_OPC_Decode, 192, 3, 235, 1, // Opcode: CMP_UEQ_S -/* 976 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 989 -/* 980 */ MCD_OPC_CheckPredicate, 36, 95, 3, // Skip to: 1847 -/* 984 */ MCD_OPC_Decode, 174, 3, 235, 1, // Opcode: CMP_LT_S -/* 989 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1002 -/* 993 */ MCD_OPC_CheckPredicate, 36, 82, 3, // Skip to: 1847 -/* 997 */ MCD_OPC_Decode, 196, 3, 235, 1, // Opcode: CMP_ULT_S -/* 1002 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1015 -/* 1006 */ MCD_OPC_CheckPredicate, 36, 69, 3, // Skip to: 1847 -/* 1010 */ MCD_OPC_Decode, 171, 3, 235, 1, // Opcode: CMP_LE_S -/* 1015 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1028 -/* 1019 */ MCD_OPC_CheckPredicate, 36, 56, 3, // Skip to: 1847 -/* 1023 */ MCD_OPC_Decode, 194, 3, 235, 1, // Opcode: CMP_ULE_S -/* 1028 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1041 -/* 1032 */ MCD_OPC_CheckPredicate, 36, 43, 3, // Skip to: 1847 -/* 1036 */ MCD_OPC_Decode, 176, 3, 235, 1, // Opcode: CMP_SAF_S -/* 1041 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1054 -/* 1045 */ MCD_OPC_CheckPredicate, 36, 30, 3, // Skip to: 1847 -/* 1049 */ MCD_OPC_Decode, 190, 3, 235, 1, // Opcode: CMP_SUN_S -/* 1054 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1067 -/* 1058 */ MCD_OPC_CheckPredicate, 36, 17, 3, // Skip to: 1847 -/* 1062 */ MCD_OPC_Decode, 178, 3, 235, 1, // Opcode: CMP_SEQ_S -/* 1067 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1080 -/* 1071 */ MCD_OPC_CheckPredicate, 36, 4, 3, // Skip to: 1847 -/* 1075 */ MCD_OPC_Decode, 184, 3, 235, 1, // Opcode: CMP_SUEQ_S -/* 1080 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1093 -/* 1084 */ MCD_OPC_CheckPredicate, 36, 247, 2, // Skip to: 1847 -/* 1088 */ MCD_OPC_Decode, 182, 3, 235, 1, // Opcode: CMP_SLT_S -/* 1093 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1106 -/* 1097 */ MCD_OPC_CheckPredicate, 36, 234, 2, // Skip to: 1847 -/* 1101 */ MCD_OPC_Decode, 188, 3, 235, 1, // Opcode: CMP_SULT_S -/* 1106 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1119 -/* 1110 */ MCD_OPC_CheckPredicate, 36, 221, 2, // Skip to: 1847 -/* 1114 */ MCD_OPC_Decode, 180, 3, 235, 1, // Opcode: CMP_SLE_S -/* 1119 */ MCD_OPC_FilterValue, 15, 212, 2, // Skip to: 1847 -/* 1123 */ MCD_OPC_CheckPredicate, 36, 208, 2, // Skip to: 1847 -/* 1127 */ MCD_OPC_Decode, 186, 3, 235, 1, // Opcode: CMP_SULE_S -/* 1132 */ MCD_OPC_FilterValue, 21, 199, 2, // Skip to: 1847 -/* 1136 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1139 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1152 -/* 1143 */ MCD_OPC_CheckPredicate, 36, 188, 2, // Skip to: 1847 -/* 1147 */ MCD_OPC_Decode, 167, 3, 236, 1, // Opcode: CMP_F_D -/* 1152 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1165 -/* 1156 */ MCD_OPC_CheckPredicate, 36, 175, 2, // Skip to: 1847 -/* 1160 */ MCD_OPC_Decode, 197, 3, 236, 1, // Opcode: CMP_UN_D -/* 1165 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1178 -/* 1169 */ MCD_OPC_CheckPredicate, 36, 162, 2, // Skip to: 1847 -/* 1173 */ MCD_OPC_Decode, 164, 3, 236, 1, // Opcode: CMP_EQ_D -/* 1178 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1191 -/* 1182 */ MCD_OPC_CheckPredicate, 36, 149, 2, // Skip to: 1847 -/* 1186 */ MCD_OPC_Decode, 191, 3, 236, 1, // Opcode: CMP_UEQ_D -/* 1191 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1204 -/* 1195 */ MCD_OPC_CheckPredicate, 36, 136, 2, // Skip to: 1847 -/* 1199 */ MCD_OPC_Decode, 172, 3, 236, 1, // Opcode: CMP_LT_D -/* 1204 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1217 -/* 1208 */ MCD_OPC_CheckPredicate, 36, 123, 2, // Skip to: 1847 -/* 1212 */ MCD_OPC_Decode, 195, 3, 236, 1, // Opcode: CMP_ULT_D -/* 1217 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1230 -/* 1221 */ MCD_OPC_CheckPredicate, 36, 110, 2, // Skip to: 1847 -/* 1225 */ MCD_OPC_Decode, 169, 3, 236, 1, // Opcode: CMP_LE_D -/* 1230 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1243 -/* 1234 */ MCD_OPC_CheckPredicate, 36, 97, 2, // Skip to: 1847 -/* 1238 */ MCD_OPC_Decode, 193, 3, 236, 1, // Opcode: CMP_ULE_D -/* 1243 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1256 -/* 1247 */ MCD_OPC_CheckPredicate, 36, 84, 2, // Skip to: 1847 -/* 1251 */ MCD_OPC_Decode, 175, 3, 236, 1, // Opcode: CMP_SAF_D -/* 1256 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1269 -/* 1260 */ MCD_OPC_CheckPredicate, 36, 71, 2, // Skip to: 1847 -/* 1264 */ MCD_OPC_Decode, 189, 3, 236, 1, // Opcode: CMP_SUN_D -/* 1269 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1282 -/* 1273 */ MCD_OPC_CheckPredicate, 36, 58, 2, // Skip to: 1847 -/* 1277 */ MCD_OPC_Decode, 177, 3, 236, 1, // Opcode: CMP_SEQ_D -/* 1282 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1295 -/* 1286 */ MCD_OPC_CheckPredicate, 36, 45, 2, // Skip to: 1847 -/* 1290 */ MCD_OPC_Decode, 183, 3, 236, 1, // Opcode: CMP_SUEQ_D -/* 1295 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1308 -/* 1299 */ MCD_OPC_CheckPredicate, 36, 32, 2, // Skip to: 1847 -/* 1303 */ MCD_OPC_Decode, 181, 3, 236, 1, // Opcode: CMP_SLT_D -/* 1308 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1321 -/* 1312 */ MCD_OPC_CheckPredicate, 36, 19, 2, // Skip to: 1847 -/* 1316 */ MCD_OPC_Decode, 187, 3, 236, 1, // Opcode: CMP_SULT_D -/* 1321 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1334 -/* 1325 */ MCD_OPC_CheckPredicate, 36, 6, 2, // Skip to: 1847 -/* 1329 */ MCD_OPC_Decode, 179, 3, 236, 1, // Opcode: CMP_SLE_D -/* 1334 */ MCD_OPC_FilterValue, 15, 253, 1, // Skip to: 1847 -/* 1338 */ MCD_OPC_CheckPredicate, 36, 249, 1, // Skip to: 1847 -/* 1342 */ MCD_OPC_Decode, 185, 3, 236, 1, // Opcode: CMP_SULE_D -/* 1347 */ MCD_OPC_FilterValue, 18, 81, 0, // Skip to: 1432 -/* 1351 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1354 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1367 -/* 1358 */ MCD_OPC_CheckPredicate, 36, 229, 1, // Skip to: 1847 -/* 1362 */ MCD_OPC_Decode, 188, 1, 237, 1, // Opcode: BC2EQZ -/* 1367 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1380 -/* 1371 */ MCD_OPC_CheckPredicate, 36, 216, 1, // Skip to: 1847 -/* 1375 */ MCD_OPC_Decode, 219, 7, 238, 1, // Opcode: LWC2_R6 -/* 1380 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1393 -/* 1384 */ MCD_OPC_CheckPredicate, 36, 203, 1, // Skip to: 1847 -/* 1388 */ MCD_OPC_Decode, 241, 12, 238, 1, // Opcode: SWC2_R6 -/* 1393 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1406 -/* 1397 */ MCD_OPC_CheckPredicate, 36, 190, 1, // Skip to: 1847 -/* 1401 */ MCD_OPC_Decode, 191, 1, 237, 1, // Opcode: BC2NEZ -/* 1406 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1419 -/* 1410 */ MCD_OPC_CheckPredicate, 36, 177, 1, // Skip to: 1847 -/* 1414 */ MCD_OPC_Decode, 166, 7, 238, 1, // Opcode: LDC2_R6 -/* 1419 */ MCD_OPC_FilterValue, 15, 168, 1, // Skip to: 1847 -/* 1423 */ MCD_OPC_CheckPredicate, 36, 164, 1, // Skip to: 1847 -/* 1427 */ MCD_OPC_Decode, 160, 11, 238, 1, // Opcode: SDC2_R6 -/* 1432 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 1445 -/* 1436 */ MCD_OPC_CheckPredicate, 36, 151, 1, // Skip to: 1847 -/* 1440 */ MCD_OPC_Decode, 224, 1, 239, 1, // Opcode: BGEZC -/* 1445 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 1458 -/* 1449 */ MCD_OPC_CheckPredicate, 36, 138, 1, // Skip to: 1847 -/* 1453 */ MCD_OPC_Decode, 138, 2, 240, 1, // Opcode: BLTZC -/* 1458 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1471 -/* 1462 */ MCD_OPC_CheckPredicate, 36, 125, 1, // Skip to: 1847 -/* 1466 */ MCD_OPC_Decode, 147, 2, 241, 1, // Opcode: BNEC -/* 1471 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 1484 -/* 1475 */ MCD_OPC_CheckPredicate, 37, 112, 1, // Skip to: 1847 -/* 1479 */ MCD_OPC_Decode, 166, 4, 242, 1, // Opcode: DAUI -/* 1484 */ MCD_OPC_FilterValue, 31, 182, 0, // Skip to: 1670 -/* 1488 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1491 */ MCD_OPC_FilterValue, 32, 40, 0, // Skip to: 1535 -/* 1495 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 1498 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1523 -/* 1502 */ MCD_OPC_CheckPredicate, 36, 85, 1, // Skip to: 1847 -/* 1506 */ MCD_OPC_CheckField, 21, 5, 0, 79, 1, // Skip to: 1847 -/* 1512 */ MCD_OPC_CheckField, 6, 2, 0, 73, 1, // Skip to: 1847 -/* 1518 */ MCD_OPC_Decode, 250, 1, 205, 1, // Opcode: BITSWAP -/* 1523 */ MCD_OPC_FilterValue, 2, 64, 1, // Skip to: 1847 -/* 1527 */ MCD_OPC_CheckPredicate, 36, 60, 1, // Skip to: 1847 -/* 1531 */ MCD_OPC_Decode, 81, 221, 1, // Opcode: ALIGN -/* 1535 */ MCD_OPC_FilterValue, 36, 41, 0, // Skip to: 1580 -/* 1539 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 1542 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1567 -/* 1546 */ MCD_OPC_CheckPredicate, 37, 41, 1, // Skip to: 1847 -/* 1550 */ MCD_OPC_CheckField, 21, 5, 0, 35, 1, // Skip to: 1847 -/* 1556 */ MCD_OPC_CheckField, 6, 3, 0, 29, 1, // Skip to: 1847 -/* 1562 */ MCD_OPC_Decode, 167, 4, 243, 1, // Opcode: DBITSWAP -/* 1567 */ MCD_OPC_FilterValue, 1, 20, 1, // Skip to: 1847 -/* 1571 */ MCD_OPC_CheckPredicate, 37, 16, 1, // Skip to: 1847 -/* 1575 */ MCD_OPC_Decode, 164, 4, 244, 1, // Opcode: DALIGN -/* 1580 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1599 -/* 1584 */ MCD_OPC_CheckPredicate, 36, 3, 1, // Skip to: 1847 -/* 1588 */ MCD_OPC_CheckField, 6, 1, 0, 253, 0, // Skip to: 1847 -/* 1594 */ MCD_OPC_Decode, 222, 2, 245, 1, // Opcode: CACHE_R6 -/* 1599 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 1612 -/* 1603 */ MCD_OPC_CheckPredicate, 36, 240, 0, // Skip to: 1847 -/* 1607 */ MCD_OPC_Decode, 150, 11, 246, 1, // Opcode: SC_R6 -/* 1612 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 1625 -/* 1616 */ MCD_OPC_CheckPredicate, 36, 227, 0, // Skip to: 1847 -/* 1620 */ MCD_OPC_Decode, 148, 11, 246, 1, // Opcode: SCD_R6 -/* 1625 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 1644 -/* 1629 */ MCD_OPC_CheckPredicate, 36, 214, 0, // Skip to: 1847 -/* 1633 */ MCD_OPC_CheckField, 6, 1, 0, 208, 0, // Skip to: 1847 -/* 1639 */ MCD_OPC_Decode, 183, 10, 245, 1, // Opcode: PREF_R6 -/* 1644 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 1657 -/* 1648 */ MCD_OPC_CheckPredicate, 36, 195, 0, // Skip to: 1847 -/* 1652 */ MCD_OPC_Decode, 197, 7, 246, 1, // Opcode: LL_R6 -/* 1657 */ MCD_OPC_FilterValue, 55, 186, 0, // Skip to: 1847 -/* 1661 */ MCD_OPC_CheckPredicate, 36, 182, 0, // Skip to: 1847 -/* 1665 */ MCD_OPC_Decode, 195, 7, 246, 1, // Opcode: LLD_R6 -/* 1670 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 1683 -/* 1674 */ MCD_OPC_CheckPredicate, 36, 169, 0, // Skip to: 1847 -/* 1678 */ MCD_OPC_Decode, 175, 1, 247, 1, // Opcode: BC -/* 1683 */ MCD_OPC_FilterValue, 54, 23, 0, // Skip to: 1710 -/* 1687 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1701 -/* 1691 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1701 -/* 1697 */ MCD_OPC_Decode, 135, 7, 52, // Opcode: JIC -/* 1701 */ MCD_OPC_CheckPredicate, 36, 142, 0, // Skip to: 1847 -/* 1705 */ MCD_OPC_Decode, 212, 1, 248, 1, // Opcode: BEQZC -/* 1710 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1723 -/* 1714 */ MCD_OPC_CheckPredicate, 36, 129, 0, // Skip to: 1847 -/* 1718 */ MCD_OPC_Decode, 168, 1, 247, 1, // Opcode: BALC -/* 1723 */ MCD_OPC_FilterValue, 59, 93, 0, // Skip to: 1820 -/* 1727 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... -/* 1730 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1742 -/* 1734 */ MCD_OPC_CheckPredicate, 36, 109, 0, // Skip to: 1847 -/* 1738 */ MCD_OPC_Decode, 26, 249, 1, // Opcode: ADDIUPC -/* 1742 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1755 -/* 1746 */ MCD_OPC_CheckPredicate, 36, 97, 0, // Skip to: 1847 -/* 1750 */ MCD_OPC_Decode, 228, 7, 249, 1, // Opcode: LWPC -/* 1755 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1768 -/* 1759 */ MCD_OPC_CheckPredicate, 36, 84, 0, // Skip to: 1847 -/* 1763 */ MCD_OPC_Decode, 234, 7, 249, 1, // Opcode: LWUPC -/* 1768 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 1847 -/* 1772 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 1775 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1788 -/* 1779 */ MCD_OPC_CheckPredicate, 37, 64, 0, // Skip to: 1847 -/* 1783 */ MCD_OPC_Decode, 173, 7, 250, 1, // Opcode: LDPC -/* 1788 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 1847 -/* 1792 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1808 -/* 1799 */ MCD_OPC_CheckPredicate, 36, 44, 0, // Skip to: 1847 -/* 1803 */ MCD_OPC_Decode, 138, 1, 251, 1, // Opcode: AUIPC -/* 1808 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 1847 -/* 1812 */ MCD_OPC_CheckPredicate, 36, 31, 0, // Skip to: 1847 -/* 1816 */ MCD_OPC_Decode, 82, 251, 1, // Opcode: ALUIPC -/* 1820 */ MCD_OPC_FilterValue, 62, 23, 0, // Skip to: 1847 -/* 1824 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1838 -/* 1828 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1838 -/* 1834 */ MCD_OPC_Decode, 134, 7, 52, // Opcode: JIALC -/* 1838 */ MCD_OPC_CheckPredicate, 36, 5, 0, // Skip to: 1847 -/* 1842 */ MCD_OPC_Decode, 159, 2, 248, 1, // Opcode: BNEZC -/* 1847 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 14, + 2, + 0, // Skip to: 534 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 33 + /* 16 */ MCD_OPC_CheckPredicate, + 75, + 133, + 9, + 0, // Skip to: 2458 + /* 21 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 126, + 9, + 0, // Skip to: 2458 + /* 28 */ MCD_OPC_Decode, + 219, + 14, + 174, + 1, // Opcode: LSA_R6 + /* 33 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 55 + /* 38 */ MCD_OPC_CheckPredicate, + 75, + 111, + 9, + 0, // Skip to: 2458 + /* 43 */ MCD_OPC_CheckField, + 6, + 15, + 16, + 104, + 9, + 0, // Skip to: 2458 + /* 50 */ MCD_OPC_Decode, + 143, + 14, + 175, + 1, // Opcode: JR_HB_R6 + /* 55 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 70 + /* 60 */ MCD_OPC_CheckPredicate, + 76, + 89, + 9, + 0, // Skip to: 2458 + /* 65 */ MCD_OPC_Decode, + 130, + 19, + 177, + 1, // Opcode: SDBBP_R6 + /* 70 */ MCD_OPC_FilterValue, + 16, + 23, + 0, + 0, // Skip to: 98 + /* 75 */ MCD_OPC_CheckPredicate, + 75, + 74, + 9, + 0, // Skip to: 2458 + /* 80 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 67, + 9, + 0, // Skip to: 2458 + /* 87 */ MCD_OPC_CheckField, + 6, + 5, + 1, + 60, + 9, + 0, // Skip to: 2458 + /* 94 */ MCD_OPC_Decode, + 225, + 8, + 14, // Opcode: CLZ_R6 + /* 98 */ MCD_OPC_FilterValue, + 17, + 23, + 0, + 0, // Skip to: 126 + /* 103 */ MCD_OPC_CheckPredicate, + 75, + 46, + 9, + 0, // Skip to: 2458 + /* 108 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 39, + 9, + 0, // Skip to: 2458 + /* 115 */ MCD_OPC_CheckField, + 6, + 5, + 1, + 32, + 9, + 0, // Skip to: 2458 + /* 122 */ MCD_OPC_Decode, + 205, + 8, + 14, // Opcode: CLO_R6 + /* 126 */ MCD_OPC_FilterValue, + 18, + 23, + 0, + 0, // Skip to: 154 + /* 131 */ MCD_OPC_CheckPredicate, + 77, + 18, + 9, + 0, // Skip to: 2458 + /* 136 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 11, + 9, + 0, // Skip to: 2458 + /* 143 */ MCD_OPC_CheckField, + 6, + 5, + 1, + 4, + 9, + 0, // Skip to: 2458 + /* 150 */ MCD_OPC_Decode, + 225, + 10, + 15, // Opcode: DCLZ_R6 + /* 154 */ MCD_OPC_FilterValue, + 19, + 23, + 0, + 0, // Skip to: 182 + /* 159 */ MCD_OPC_CheckPredicate, + 77, + 246, + 8, + 0, // Skip to: 2458 + /* 164 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 239, + 8, + 0, // Skip to: 2458 + /* 171 */ MCD_OPC_CheckField, + 6, + 5, + 1, + 232, + 8, + 0, // Skip to: 2458 + /* 178 */ MCD_OPC_Decode, + 223, + 10, + 15, // Opcode: DCLO_R6 + /* 182 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 204 + /* 187 */ MCD_OPC_CheckPredicate, + 77, + 218, + 8, + 0, // Skip to: 2458 + /* 192 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 211, + 8, + 0, // Skip to: 2458 + /* 199 */ MCD_OPC_Decode, + 254, + 10, + 183, + 1, // Opcode: DLSA_R6 + /* 204 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 240 + /* 209 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 212 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 226 + /* 217 */ MCD_OPC_CheckPredicate, + 76, + 188, + 8, + 0, // Skip to: 2458 + /* 222 */ MCD_OPC_Decode, + 185, + 17, + 50, // Opcode: MUL_R6 + /* 226 */ MCD_OPC_FilterValue, + 3, + 179, + 8, + 0, // Skip to: 2458 + /* 231 */ MCD_OPC_CheckPredicate, + 76, + 174, + 8, + 0, // Skip to: 2458 + /* 236 */ MCD_OPC_Decode, + 137, + 17, + 50, // Opcode: MUH + /* 240 */ MCD_OPC_FilterValue, + 25, + 31, + 0, + 0, // Skip to: 276 + /* 245 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 248 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 262 + /* 253 */ MCD_OPC_CheckPredicate, + 76, + 152, + 8, + 0, // Skip to: 2458 + /* 258 */ MCD_OPC_Decode, + 173, + 17, + 50, // Opcode: MULU + /* 262 */ MCD_OPC_FilterValue, + 3, + 143, + 8, + 0, // Skip to: 2458 + /* 267 */ MCD_OPC_CheckPredicate, + 76, + 138, + 8, + 0, // Skip to: 2458 + /* 272 */ MCD_OPC_Decode, + 138, + 17, + 50, // Opcode: MUHU + /* 276 */ MCD_OPC_FilterValue, + 26, + 31, + 0, + 0, // Skip to: 312 + /* 281 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 284 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 298 + /* 289 */ MCD_OPC_CheckPredicate, + 76, + 116, + 8, + 0, // Skip to: 2458 + /* 294 */ MCD_OPC_Decode, + 239, + 10, + 50, // Opcode: DIV + /* 298 */ MCD_OPC_FilterValue, + 3, + 107, + 8, + 0, // Skip to: 2458 + /* 303 */ MCD_OPC_CheckPredicate, + 76, + 102, + 8, + 0, // Skip to: 2458 + /* 308 */ MCD_OPC_Decode, + 143, + 16, + 50, // Opcode: MOD + /* 312 */ MCD_OPC_FilterValue, + 27, + 31, + 0, + 0, // Skip to: 348 + /* 317 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 320 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 334 + /* 325 */ MCD_OPC_CheckPredicate, + 76, + 80, + 8, + 0, // Skip to: 2458 + /* 330 */ MCD_OPC_Decode, + 240, + 10, + 50, // Opcode: DIVU + /* 334 */ MCD_OPC_FilterValue, + 3, + 71, + 8, + 0, // Skip to: 2458 + /* 339 */ MCD_OPC_CheckPredicate, + 76, + 66, + 8, + 0, // Skip to: 2458 + /* 344 */ MCD_OPC_Decode, + 146, + 16, + 50, // Opcode: MODU + /* 348 */ MCD_OPC_FilterValue, + 28, + 31, + 0, + 0, // Skip to: 384 + /* 353 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 356 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 370 + /* 361 */ MCD_OPC_CheckPredicate, + 77, + 44, + 8, + 0, // Skip to: 2458 + /* 366 */ MCD_OPC_Decode, + 146, + 11, + 12, // Opcode: DMUL_R6 + /* 370 */ MCD_OPC_FilterValue, + 3, + 35, + 8, + 0, // Skip to: 2458 + /* 375 */ MCD_OPC_CheckPredicate, + 77, + 30, + 8, + 0, // Skip to: 2458 + /* 380 */ MCD_OPC_Decode, + 140, + 11, + 12, // Opcode: DMUH + /* 384 */ MCD_OPC_FilterValue, + 29, + 31, + 0, + 0, // Skip to: 420 + /* 389 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 392 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 406 + /* 397 */ MCD_OPC_CheckPredicate, + 77, + 8, + 8, + 0, // Skip to: 2458 + /* 402 */ MCD_OPC_Decode, + 145, + 11, + 12, // Opcode: DMULU + /* 406 */ MCD_OPC_FilterValue, + 3, + 255, + 7, + 0, // Skip to: 2458 + /* 411 */ MCD_OPC_CheckPredicate, + 77, + 250, + 7, + 0, // Skip to: 2458 + /* 416 */ MCD_OPC_Decode, + 141, + 11, + 12, // Opcode: DMUHU + /* 420 */ MCD_OPC_FilterValue, + 30, + 31, + 0, + 0, // Skip to: 456 + /* 425 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 428 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 442 + /* 433 */ MCD_OPC_CheckPredicate, + 77, + 228, + 7, + 0, // Skip to: 2458 + /* 438 */ MCD_OPC_Decode, + 226, + 10, + 12, // Opcode: DDIV + /* 442 */ MCD_OPC_FilterValue, + 3, + 219, + 7, + 0, // Skip to: 2458 + /* 447 */ MCD_OPC_CheckPredicate, + 77, + 214, + 7, + 0, // Skip to: 2458 + /* 452 */ MCD_OPC_Decode, + 132, + 11, + 12, // Opcode: DMOD + /* 456 */ MCD_OPC_FilterValue, + 31, + 31, + 0, + 0, // Skip to: 492 + /* 461 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 464 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 478 + /* 469 */ MCD_OPC_CheckPredicate, + 77, + 192, + 7, + 0, // Skip to: 2458 + /* 474 */ MCD_OPC_Decode, + 227, + 10, + 12, // Opcode: DDIVU + /* 478 */ MCD_OPC_FilterValue, + 3, + 183, + 7, + 0, // Skip to: 2458 + /* 483 */ MCD_OPC_CheckPredicate, + 77, + 178, + 7, + 0, // Skip to: 2458 + /* 488 */ MCD_OPC_Decode, + 133, + 11, + 12, // Opcode: DMODU + /* 492 */ MCD_OPC_FilterValue, + 53, + 16, + 0, + 0, // Skip to: 513 + /* 497 */ MCD_OPC_CheckPredicate, + 78, + 164, + 7, + 0, // Skip to: 2458 + /* 502 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 157, + 7, + 0, // Skip to: 2458 + /* 509 */ MCD_OPC_Decode, + 151, + 19, + 50, // Opcode: SELEQZ + /* 513 */ MCD_OPC_FilterValue, + 55, + 148, + 7, + 0, // Skip to: 2458 + /* 518 */ MCD_OPC_CheckPredicate, + 78, + 143, + 7, + 0, // Skip to: 2458 + /* 523 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 136, + 7, + 0, // Skip to: 2458 + /* 530 */ MCD_OPC_Decode, + 158, + 19, + 50, // Opcode: SELNEZ + /* 534 */ MCD_OPC_FilterValue, + 1, + 77, + 0, + 0, // Skip to: 616 + /* 539 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 542 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 557 + /* 547 */ MCD_OPC_CheckPredicate, + 77, + 114, + 7, + 0, // Skip to: 2458 + /* 552 */ MCD_OPC_Decode, + 217, + 10, + 210, + 2, // Opcode: DAHI + /* 557 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 579 + /* 562 */ MCD_OPC_CheckPredicate, + 75, + 99, + 7, + 0, // Skip to: 2458 + /* 567 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 92, + 7, + 0, // Skip to: 2458 + /* 574 */ MCD_OPC_Decode, + 200, + 6, + 187, + 1, // Opcode: BAL + /* 579 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 601 + /* 584 */ MCD_OPC_CheckPredicate, + 76, + 77, + 7, + 0, // Skip to: 2458 + /* 589 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 70, + 7, + 0, // Skip to: 2458 + /* 596 */ MCD_OPC_Decode, + 230, + 19, + 211, + 2, // Opcode: SIGRIE + /* 601 */ MCD_OPC_FilterValue, + 30, + 60, + 7, + 0, // Skip to: 2458 + /* 606 */ MCD_OPC_CheckPredicate, + 77, + 55, + 7, + 0, // Skip to: 2458 + /* 611 */ MCD_OPC_Decode, + 219, + 10, + 210, + 2, // Opcode: DATI + /* 616 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 631 + /* 621 */ MCD_OPC_CheckPredicate, + 76, + 40, + 7, + 0, // Skip to: 2458 + /* 626 */ MCD_OPC_Decode, + 140, + 7, + 212, + 2, // Opcode: BGEZALC + /* 631 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 646 + /* 636 */ MCD_OPC_CheckPredicate, + 76, + 25, + 7, + 0, // Skip to: 2458 + /* 641 */ MCD_OPC_Decode, + 197, + 7, + 213, + 2, // Opcode: BLTZALC + /* 646 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 661 + /* 651 */ MCD_OPC_CheckPredicate, + 76, + 10, + 7, + 0, // Skip to: 2458 + /* 656 */ MCD_OPC_Decode, + 246, + 6, + 214, + 2, // Opcode: BEQC + /* 661 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 676 + /* 666 */ MCD_OPC_CheckPredicate, + 75, + 251, + 6, + 0, // Skip to: 2458 + /* 671 */ MCD_OPC_Decode, + 169, + 6, + 192, + 1, // Opcode: AUI + /* 676 */ MCD_OPC_FilterValue, + 16, + 45, + 0, + 0, // Skip to: 726 + /* 681 */ MCD_OPC_ExtractField, + 0, + 16, // Inst{15-0} ... + /* 684 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 705 + /* 689 */ MCD_OPC_CheckPredicate, + 75, + 228, + 6, + 0, // Skip to: 2458 + /* 694 */ MCD_OPC_CheckField, + 21, + 5, + 11, + 221, + 6, + 0, // Skip to: 2458 + /* 701 */ MCD_OPC_Decode, + 234, + 11, + 81, // Opcode: EVP + /* 705 */ MCD_OPC_FilterValue, + 36, + 212, + 6, + 0, // Skip to: 2458 + /* 710 */ MCD_OPC_CheckPredicate, + 75, + 207, + 6, + 0, // Skip to: 2458 + /* 715 */ MCD_OPC_CheckField, + 21, + 5, + 11, + 200, + 6, + 0, // Skip to: 2458 + /* 722 */ MCD_OPC_Decode, + 217, + 11, + 81, // Opcode: DVP + /* 726 */ MCD_OPC_FilterValue, + 17, + 135, + 3, + 0, // Skip to: 1634 + /* 731 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 734 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 749 + /* 739 */ MCD_OPC_CheckPredicate, + 79, + 178, + 6, + 0, // Skip to: 2458 + /* 744 */ MCD_OPC_Decode, + 213, + 6, + 215, + 2, // Opcode: BC1EQZ + /* 749 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 764 + /* 754 */ MCD_OPC_CheckPredicate, + 79, + 163, + 6, + 0, // Skip to: 2458 + /* 759 */ MCD_OPC_Decode, + 218, + 6, + 215, + 2, // Opcode: BC1NEZ + /* 764 */ MCD_OPC_FilterValue, + 16, + 182, + 0, + 0, // Skip to: 951 + /* 769 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 772 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 787 + /* 777 */ MCD_OPC_CheckPredicate, + 79, + 140, + 6, + 0, // Skip to: 2458 + /* 782 */ MCD_OPC_Decode, + 167, + 19, + 216, + 2, // Opcode: SEL_S + /* 787 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 802 + /* 792 */ MCD_OPC_CheckPredicate, + 79, + 125, + 6, + 0, // Skip to: 2458 + /* 797 */ MCD_OPC_Decode, + 156, + 19, + 207, + 1, // Opcode: SELEQZ_S + /* 802 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 817 + /* 807 */ MCD_OPC_CheckPredicate, + 79, + 110, + 6, + 0, // Skip to: 2458 + /* 812 */ MCD_OPC_Decode, + 163, + 19, + 207, + 1, // Opcode: SELNEZ_S + /* 817 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 832 + /* 822 */ MCD_OPC_CheckPredicate, + 79, + 95, + 6, + 0, // Skip to: 2458 + /* 827 */ MCD_OPC_Decode, + 154, + 15, + 217, + 2, // Opcode: MADDF_S + /* 832 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 847 + /* 837 */ MCD_OPC_CheckPredicate, + 79, + 80, + 6, + 0, // Skip to: 2458 + /* 842 */ MCD_OPC_Decode, + 205, + 16, + 217, + 2, // Opcode: MSUBF_S + /* 847 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 869 + /* 852 */ MCD_OPC_CheckPredicate, + 79, + 65, + 6, + 0, // Skip to: 2458 + /* 857 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 58, + 6, + 0, // Skip to: 2458 + /* 864 */ MCD_OPC_Decode, + 199, + 18, + 208, + 1, // Opcode: RINT_S + /* 869 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 891 + /* 874 */ MCD_OPC_CheckPredicate, + 79, + 43, + 6, + 0, // Skip to: 2458 + /* 879 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 36, + 6, + 0, // Skip to: 2458 + /* 886 */ MCD_OPC_Decode, + 184, + 8, + 208, + 1, // Opcode: CLASS_S + /* 891 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 906 + /* 896 */ MCD_OPC_CheckPredicate, + 79, + 21, + 6, + 0, // Skip to: 2458 + /* 901 */ MCD_OPC_Decode, + 133, + 16, + 207, + 1, // Opcode: MIN_S + /* 906 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 921 + /* 911 */ MCD_OPC_CheckPredicate, + 79, + 6, + 6, + 0, // Skip to: 2458 + /* 916 */ MCD_OPC_Decode, + 202, + 15, + 207, + 1, // Opcode: MAX_S + /* 921 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 936 + /* 926 */ MCD_OPC_CheckPredicate, + 79, + 247, + 5, + 0, // Skip to: 2458 + /* 931 */ MCD_OPC_Decode, + 245, + 15, + 207, + 1, // Opcode: MINA_S + /* 936 */ MCD_OPC_FilterValue, + 31, + 237, + 5, + 0, // Skip to: 2458 + /* 941 */ MCD_OPC_CheckPredicate, + 79, + 232, + 5, + 0, // Skip to: 2458 + /* 946 */ MCD_OPC_Decode, + 186, + 15, + 207, + 1, // Opcode: MAXA_S + /* 951 */ MCD_OPC_FilterValue, + 17, + 182, + 0, + 0, // Skip to: 1138 + /* 956 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 959 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 974 + /* 964 */ MCD_OPC_CheckPredicate, + 79, + 209, + 5, + 0, // Skip to: 2458 + /* 969 */ MCD_OPC_Decode, + 165, + 19, + 218, + 2, // Opcode: SEL_D + /* 974 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 989 + /* 979 */ MCD_OPC_CheckPredicate, + 79, + 194, + 5, + 0, // Skip to: 2458 + /* 984 */ MCD_OPC_Decode, + 153, + 19, + 219, + 2, // Opcode: SELEQZ_D + /* 989 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 1004 + /* 994 */ MCD_OPC_CheckPredicate, + 79, + 179, + 5, + 0, // Skip to: 2458 + /* 999 */ MCD_OPC_Decode, + 160, + 19, + 219, + 2, // Opcode: SELNEZ_D + /* 1004 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 1019 + /* 1009 */ MCD_OPC_CheckPredicate, + 79, + 164, + 5, + 0, // Skip to: 2458 + /* 1014 */ MCD_OPC_Decode, + 152, + 15, + 218, + 2, // Opcode: MADDF_D + /* 1019 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 1034 + /* 1024 */ MCD_OPC_CheckPredicate, + 79, + 149, + 5, + 0, // Skip to: 2458 + /* 1029 */ MCD_OPC_Decode, + 203, + 16, + 218, + 2, // Opcode: MSUBF_D + /* 1034 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 1056 + /* 1039 */ MCD_OPC_CheckPredicate, + 79, + 134, + 5, + 0, // Skip to: 2458 + /* 1044 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 127, + 5, + 0, // Skip to: 2458 + /* 1051 */ MCD_OPC_Decode, + 197, + 18, + 219, + 1, // Opcode: RINT_D + /* 1056 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 1078 + /* 1061 */ MCD_OPC_CheckPredicate, + 79, + 112, + 5, + 0, // Skip to: 2458 + /* 1066 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 105, + 5, + 0, // Skip to: 2458 + /* 1073 */ MCD_OPC_Decode, + 182, + 8, + 219, + 1, // Opcode: CLASS_D + /* 1078 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 1093 + /* 1083 */ MCD_OPC_CheckPredicate, + 79, + 90, + 5, + 0, // Skip to: 2458 + /* 1088 */ MCD_OPC_Decode, + 131, + 16, + 219, + 2, // Opcode: MIN_D + /* 1093 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 1108 + /* 1098 */ MCD_OPC_CheckPredicate, + 79, + 75, + 5, + 0, // Skip to: 2458 + /* 1103 */ MCD_OPC_Decode, + 200, + 15, + 219, + 2, // Opcode: MAX_D + /* 1108 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 1123 + /* 1113 */ MCD_OPC_CheckPredicate, + 79, + 60, + 5, + 0, // Skip to: 2458 + /* 1118 */ MCD_OPC_Decode, + 243, + 15, + 219, + 2, // Opcode: MINA_D + /* 1123 */ MCD_OPC_FilterValue, + 31, + 50, + 5, + 0, // Skip to: 2458 + /* 1128 */ MCD_OPC_CheckPredicate, + 79, + 45, + 5, + 0, // Skip to: 2458 + /* 1133 */ MCD_OPC_Decode, + 184, + 15, + 219, + 2, // Opcode: MAXA_D + /* 1138 */ MCD_OPC_FilterValue, + 20, + 243, + 0, + 0, // Skip to: 1386 + /* 1143 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1146 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1161 + /* 1151 */ MCD_OPC_CheckPredicate, + 79, + 22, + 5, + 0, // Skip to: 2458 + /* 1156 */ MCD_OPC_Decode, + 253, + 8, + 220, + 2, // Opcode: CMP_F_S + /* 1161 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1176 + /* 1166 */ MCD_OPC_CheckPredicate, + 79, + 7, + 5, + 0, // Skip to: 2458 + /* 1171 */ MCD_OPC_Decode, + 184, + 9, + 220, + 2, // Opcode: CMP_UN_S + /* 1176 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1191 + /* 1181 */ MCD_OPC_CheckPredicate, + 79, + 248, + 4, + 0, // Skip to: 2458 + /* 1186 */ MCD_OPC_Decode, + 250, + 8, + 220, + 2, // Opcode: CMP_EQ_S + /* 1191 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1206 + /* 1196 */ MCD_OPC_CheckPredicate, + 79, + 233, + 4, + 0, // Skip to: 2458 + /* 1201 */ MCD_OPC_Decode, + 172, + 9, + 220, + 2, // Opcode: CMP_UEQ_S + /* 1206 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 1221 + /* 1211 */ MCD_OPC_CheckPredicate, + 79, + 218, + 4, + 0, // Skip to: 2458 + /* 1216 */ MCD_OPC_Decode, + 136, + 9, + 220, + 2, // Opcode: CMP_LT_S + /* 1221 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1236 + /* 1226 */ MCD_OPC_CheckPredicate, + 79, + 203, + 4, + 0, // Skip to: 2458 + /* 1231 */ MCD_OPC_Decode, + 180, + 9, + 220, + 2, // Opcode: CMP_ULT_S + /* 1236 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 1251 + /* 1241 */ MCD_OPC_CheckPredicate, + 79, + 188, + 4, + 0, // Skip to: 2458 + /* 1246 */ MCD_OPC_Decode, + 130, + 9, + 220, + 2, // Opcode: CMP_LE_S + /* 1251 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1266 + /* 1256 */ MCD_OPC_CheckPredicate, + 79, + 173, + 4, + 0, // Skip to: 2458 + /* 1261 */ MCD_OPC_Decode, + 176, + 9, + 220, + 2, // Opcode: CMP_ULE_S + /* 1266 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1281 + /* 1271 */ MCD_OPC_CheckPredicate, + 79, + 158, + 4, + 0, // Skip to: 2458 + /* 1276 */ MCD_OPC_Decode, + 140, + 9, + 220, + 2, // Opcode: CMP_SAF_S + /* 1281 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1296 + /* 1286 */ MCD_OPC_CheckPredicate, + 79, + 143, + 4, + 0, // Skip to: 2458 + /* 1291 */ MCD_OPC_Decode, + 168, + 9, + 220, + 2, // Opcode: CMP_SUN_S + /* 1296 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1311 + /* 1301 */ MCD_OPC_CheckPredicate, + 79, + 128, + 4, + 0, // Skip to: 2458 + /* 1306 */ MCD_OPC_Decode, + 144, + 9, + 220, + 2, // Opcode: CMP_SEQ_S + /* 1311 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1326 + /* 1316 */ MCD_OPC_CheckPredicate, + 79, + 113, + 4, + 0, // Skip to: 2458 + /* 1321 */ MCD_OPC_Decode, + 156, + 9, + 220, + 2, // Opcode: CMP_SUEQ_S + /* 1326 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 1341 + /* 1331 */ MCD_OPC_CheckPredicate, + 79, + 98, + 4, + 0, // Skip to: 2458 + /* 1336 */ MCD_OPC_Decode, + 152, + 9, + 220, + 2, // Opcode: CMP_SLT_S + /* 1341 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1356 + /* 1346 */ MCD_OPC_CheckPredicate, + 79, + 83, + 4, + 0, // Skip to: 2458 + /* 1351 */ MCD_OPC_Decode, + 164, + 9, + 220, + 2, // Opcode: CMP_SULT_S + /* 1356 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1371 + /* 1361 */ MCD_OPC_CheckPredicate, + 79, + 68, + 4, + 0, // Skip to: 2458 + /* 1366 */ MCD_OPC_Decode, + 148, + 9, + 220, + 2, // Opcode: CMP_SLE_S + /* 1371 */ MCD_OPC_FilterValue, + 15, + 58, + 4, + 0, // Skip to: 2458 + /* 1376 */ MCD_OPC_CheckPredicate, + 79, + 53, + 4, + 0, // Skip to: 2458 + /* 1381 */ MCD_OPC_Decode, + 160, + 9, + 220, + 2, // Opcode: CMP_SULE_S + /* 1386 */ MCD_OPC_FilterValue, + 21, + 43, + 4, + 0, // Skip to: 2458 + /* 1391 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1394 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1409 + /* 1399 */ MCD_OPC_CheckPredicate, + 79, + 30, + 4, + 0, // Skip to: 2458 + /* 1404 */ MCD_OPC_Decode, + 252, + 8, + 221, + 2, // Opcode: CMP_F_D + /* 1409 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1424 + /* 1414 */ MCD_OPC_CheckPredicate, + 79, + 15, + 4, + 0, // Skip to: 2458 + /* 1419 */ MCD_OPC_Decode, + 182, + 9, + 221, + 2, // Opcode: CMP_UN_D + /* 1424 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1439 + /* 1429 */ MCD_OPC_CheckPredicate, + 79, + 0, + 4, + 0, // Skip to: 2458 + /* 1434 */ MCD_OPC_Decode, + 246, + 8, + 221, + 2, // Opcode: CMP_EQ_D + /* 1439 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1454 + /* 1444 */ MCD_OPC_CheckPredicate, + 79, + 241, + 3, + 0, // Skip to: 2458 + /* 1449 */ MCD_OPC_Decode, + 170, + 9, + 221, + 2, // Opcode: CMP_UEQ_D + /* 1454 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 1469 + /* 1459 */ MCD_OPC_CheckPredicate, + 79, + 226, + 3, + 0, // Skip to: 2458 + /* 1464 */ MCD_OPC_Decode, + 132, + 9, + 221, + 2, // Opcode: CMP_LT_D + /* 1469 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1484 + /* 1474 */ MCD_OPC_CheckPredicate, + 79, + 211, + 3, + 0, // Skip to: 2458 + /* 1479 */ MCD_OPC_Decode, + 178, + 9, + 221, + 2, // Opcode: CMP_ULT_D + /* 1484 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 1499 + /* 1489 */ MCD_OPC_CheckPredicate, + 79, + 196, + 3, + 0, // Skip to: 2458 + /* 1494 */ MCD_OPC_Decode, + 254, + 8, + 221, + 2, // Opcode: CMP_LE_D + /* 1499 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1514 + /* 1504 */ MCD_OPC_CheckPredicate, + 79, + 181, + 3, + 0, // Skip to: 2458 + /* 1509 */ MCD_OPC_Decode, + 174, + 9, + 221, + 2, // Opcode: CMP_ULE_D + /* 1514 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1529 + /* 1519 */ MCD_OPC_CheckPredicate, + 79, + 166, + 3, + 0, // Skip to: 2458 + /* 1524 */ MCD_OPC_Decode, + 138, + 9, + 221, + 2, // Opcode: CMP_SAF_D + /* 1529 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1544 + /* 1534 */ MCD_OPC_CheckPredicate, + 79, + 151, + 3, + 0, // Skip to: 2458 + /* 1539 */ MCD_OPC_Decode, + 166, + 9, + 221, + 2, // Opcode: CMP_SUN_D + /* 1544 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1559 + /* 1549 */ MCD_OPC_CheckPredicate, + 79, + 136, + 3, + 0, // Skip to: 2458 + /* 1554 */ MCD_OPC_Decode, + 142, + 9, + 221, + 2, // Opcode: CMP_SEQ_D + /* 1559 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1574 + /* 1564 */ MCD_OPC_CheckPredicate, + 79, + 121, + 3, + 0, // Skip to: 2458 + /* 1569 */ MCD_OPC_Decode, + 154, + 9, + 221, + 2, // Opcode: CMP_SUEQ_D + /* 1574 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 1589 + /* 1579 */ MCD_OPC_CheckPredicate, + 79, + 106, + 3, + 0, // Skip to: 2458 + /* 1584 */ MCD_OPC_Decode, + 150, + 9, + 221, + 2, // Opcode: CMP_SLT_D + /* 1589 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1604 + /* 1594 */ MCD_OPC_CheckPredicate, + 79, + 91, + 3, + 0, // Skip to: 2458 + /* 1599 */ MCD_OPC_Decode, + 162, + 9, + 221, + 2, // Opcode: CMP_SULT_D + /* 1604 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1619 + /* 1609 */ MCD_OPC_CheckPredicate, + 79, + 76, + 3, + 0, // Skip to: 2458 + /* 1614 */ MCD_OPC_Decode, + 146, + 9, + 221, + 2, // Opcode: CMP_SLE_D + /* 1619 */ MCD_OPC_FilterValue, + 15, + 66, + 3, + 0, // Skip to: 2458 + /* 1624 */ MCD_OPC_CheckPredicate, + 79, + 61, + 3, + 0, // Skip to: 2458 + /* 1629 */ MCD_OPC_Decode, + 158, + 9, + 221, + 2, // Opcode: CMP_SULE_D + /* 1634 */ MCD_OPC_FilterValue, + 18, + 93, + 0, + 0, // Skip to: 1732 + /* 1639 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 1642 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1657 + /* 1647 */ MCD_OPC_CheckPredicate, + 76, + 38, + 3, + 0, // Skip to: 2458 + /* 1652 */ MCD_OPC_Decode, + 223, + 6, + 222, + 2, // Opcode: BC2EQZ + /* 1657 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1672 + /* 1662 */ MCD_OPC_CheckPredicate, + 76, + 23, + 3, + 0, // Skip to: 2458 + /* 1667 */ MCD_OPC_Decode, + 234, + 14, + 223, + 2, // Opcode: LWC2_R6 + /* 1672 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1687 + /* 1677 */ MCD_OPC_CheckPredicate, + 76, + 8, + 3, + 0, // Skip to: 2458 + /* 1682 */ MCD_OPC_Decode, + 141, + 21, + 223, + 2, // Opcode: SWC2_R6 + /* 1687 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1702 + /* 1692 */ MCD_OPC_CheckPredicate, + 76, + 249, + 2, + 0, // Skip to: 2458 + /* 1697 */ MCD_OPC_Decode, + 227, + 6, + 222, + 2, // Opcode: BC2NEZ + /* 1702 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1717 + /* 1707 */ MCD_OPC_CheckPredicate, + 76, + 234, + 2, + 0, // Skip to: 2458 + /* 1712 */ MCD_OPC_Decode, + 174, + 14, + 223, + 2, // Opcode: LDC2_R6 + /* 1717 */ MCD_OPC_FilterValue, + 15, + 224, + 2, + 0, // Skip to: 2458 + /* 1722 */ MCD_OPC_CheckPredicate, + 76, + 219, + 2, + 0, // Skip to: 2458 + /* 1727 */ MCD_OPC_Decode, + 137, + 19, + 223, + 2, // Opcode: SDC2_R6 + /* 1732 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 1747 + /* 1737 */ MCD_OPC_CheckPredicate, + 76, + 204, + 2, + 0, // Skip to: 2458 + /* 1742 */ MCD_OPC_Decode, + 145, + 7, + 224, + 2, // Opcode: BGEZC + /* 1747 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 1762 + /* 1752 */ MCD_OPC_CheckPredicate, + 76, + 189, + 2, + 0, // Skip to: 2458 + /* 1757 */ MCD_OPC_Decode, + 202, + 7, + 225, + 2, // Opcode: BLTZC + /* 1762 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 1777 + /* 1767 */ MCD_OPC_CheckPredicate, + 76, + 174, + 2, + 0, // Skip to: 2458 + /* 1772 */ MCD_OPC_Decode, + 213, + 7, + 226, + 2, // Opcode: BNEC + /* 1777 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 1792 + /* 1782 */ MCD_OPC_CheckPredicate, + 77, + 159, + 2, + 0, // Skip to: 2458 + /* 1787 */ MCD_OPC_Decode, + 220, + 10, + 227, + 2, // Opcode: DAUI + /* 1792 */ MCD_OPC_FilterValue, + 31, + 135, + 1, + 0, // Skip to: 2188 + /* 1797 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1800 */ MCD_OPC_FilterValue, + 15, + 123, + 0, + 0, // Skip to: 1928 + /* 1805 */ MCD_OPC_ExtractField, + 6, + 10, // Inst{15-6} ... + /* 1808 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1823 + /* 1813 */ MCD_OPC_CheckPredicate, + 80, + 128, + 2, + 0, // Skip to: 2458 + /* 1818 */ MCD_OPC_Decode, + 193, + 9, + 228, + 2, // Opcode: CRC32B + /* 1823 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1838 + /* 1828 */ MCD_OPC_CheckPredicate, + 80, + 113, + 2, + 0, // Skip to: 2458 + /* 1833 */ MCD_OPC_Decode, + 199, + 9, + 228, + 2, // Opcode: CRC32H + /* 1838 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1853 + /* 1843 */ MCD_OPC_CheckPredicate, + 80, + 98, + 2, + 0, // Skip to: 2458 + /* 1848 */ MCD_OPC_Decode, + 200, + 9, + 228, + 2, // Opcode: CRC32W + /* 1853 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1868 + /* 1858 */ MCD_OPC_CheckPredicate, + 81, + 83, + 2, + 0, // Skip to: 2458 + /* 1863 */ MCD_OPC_Decode, + 198, + 9, + 228, + 2, // Opcode: CRC32D + /* 1868 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 1883 + /* 1873 */ MCD_OPC_CheckPredicate, + 80, + 68, + 2, + 0, // Skip to: 2458 + /* 1878 */ MCD_OPC_Decode, + 194, + 9, + 228, + 2, // Opcode: CRC32CB + /* 1883 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1898 + /* 1888 */ MCD_OPC_CheckPredicate, + 80, + 53, + 2, + 0, // Skip to: 2458 + /* 1893 */ MCD_OPC_Decode, + 196, + 9, + 228, + 2, // Opcode: CRC32CH + /* 1898 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 1913 + /* 1903 */ MCD_OPC_CheckPredicate, + 80, + 38, + 2, + 0, // Skip to: 2458 + /* 1908 */ MCD_OPC_Decode, + 197, + 9, + 228, + 2, // Opcode: CRC32CW + /* 1913 */ MCD_OPC_FilterValue, + 7, + 28, + 2, + 0, // Skip to: 2458 + /* 1918 */ MCD_OPC_CheckPredicate, + 81, + 23, + 2, + 0, // Skip to: 2458 + /* 1923 */ MCD_OPC_Decode, + 195, + 9, + 228, + 2, // Opcode: CRC32CD + /* 1928 */ MCD_OPC_FilterValue, + 32, + 47, + 0, + 0, // Skip to: 1980 + /* 1933 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 1936 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 1965 + /* 1941 */ MCD_OPC_CheckPredicate, + 75, + 0, + 2, + 0, // Skip to: 2458 + /* 1946 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 249, + 1, + 0, // Skip to: 2458 + /* 1953 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 242, + 1, + 0, // Skip to: 2458 + /* 1960 */ MCD_OPC_Decode, + 177, + 7, + 193, + 2, // Opcode: BITSWAP + /* 1965 */ MCD_OPC_FilterValue, + 2, + 232, + 1, + 0, // Skip to: 2458 + /* 1970 */ MCD_OPC_CheckPredicate, + 75, + 227, + 1, + 0, // Skip to: 2458 + /* 1975 */ MCD_OPC_Decode, + 141, + 6, + 229, + 2, // Opcode: ALIGN + /* 1980 */ MCD_OPC_FilterValue, + 36, + 47, + 0, + 0, // Skip to: 2032 + /* 1985 */ MCD_OPC_ExtractField, + 9, + 2, // Inst{10-9} ... + /* 1988 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 2017 + /* 1993 */ MCD_OPC_CheckPredicate, + 77, + 204, + 1, + 0, // Skip to: 2458 + /* 1998 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 197, + 1, + 0, // Skip to: 2458 + /* 2005 */ MCD_OPC_CheckField, + 6, + 3, + 0, + 190, + 1, + 0, // Skip to: 2458 + /* 2012 */ MCD_OPC_Decode, + 221, + 10, + 230, + 2, // Opcode: DBITSWAP + /* 2017 */ MCD_OPC_FilterValue, + 1, + 180, + 1, + 0, // Skip to: 2458 + /* 2022 */ MCD_OPC_CheckPredicate, + 77, + 175, + 1, + 0, // Skip to: 2458 + /* 2027 */ MCD_OPC_Decode, + 218, + 10, + 231, + 2, // Opcode: DALIGN + /* 2032 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 2054 + /* 2037 */ MCD_OPC_CheckPredicate, + 76, + 160, + 1, + 0, // Skip to: 2458 + /* 2042 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 153, + 1, + 0, // Skip to: 2458 + /* 2049 */ MCD_OPC_Decode, + 154, + 8, + 198, + 2, // Opcode: CACHE_R6 + /* 2054 */ MCD_OPC_FilterValue, + 38, + 10, + 0, + 0, // Skip to: 2069 + /* 2059 */ MCD_OPC_CheckPredicate, + 82, + 138, + 1, + 0, // Skip to: 2458 + /* 2064 */ MCD_OPC_Decode, + 251, + 18, + 232, + 2, // Opcode: SC_R6 + /* 2069 */ MCD_OPC_FilterValue, + 39, + 10, + 0, + 0, // Skip to: 2084 + /* 2074 */ MCD_OPC_CheckPredicate, + 75, + 123, + 1, + 0, // Skip to: 2458 + /* 2079 */ MCD_OPC_Decode, + 246, + 18, + 232, + 2, // Opcode: SCD_R6 + /* 2084 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 2106 + /* 2089 */ MCD_OPC_CheckPredicate, + 76, + 108, + 1, + 0, // Skip to: 2458 + /* 2094 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 101, + 1, + 0, // Skip to: 2458 + /* 2101 */ MCD_OPC_Decode, + 169, + 18, + 198, + 2, // Opcode: PREF_R6 + /* 2106 */ MCD_OPC_FilterValue, + 54, + 10, + 0, + 0, // Skip to: 2121 + /* 2111 */ MCD_OPC_CheckPredicate, + 82, + 86, + 1, + 0, // Skip to: 2458 + /* 2116 */ MCD_OPC_Decode, + 216, + 14, + 232, + 2, // Opcode: LL_R6 + /* 2121 */ MCD_OPC_FilterValue, + 55, + 10, + 0, + 0, // Skip to: 2136 + /* 2126 */ MCD_OPC_CheckPredicate, + 77, + 71, + 1, + 0, // Skip to: 2458 + /* 2131 */ MCD_OPC_Decode, + 211, + 14, + 232, + 2, // Opcode: LLD_R6 + /* 2136 */ MCD_OPC_FilterValue, + 61, + 61, + 1, + 0, // Skip to: 2458 + /* 2141 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2144 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2166 + /* 2149 */ MCD_OPC_CheckPredicate, + 83, + 48, + 1, + 0, // Skip to: 2458 + /* 2154 */ MCD_OPC_CheckField, + 10, + 11, + 0, + 41, + 1, + 0, // Skip to: 2458 + /* 2161 */ MCD_OPC_Decode, + 191, + 13, + 175, + 1, // Opcode: GINVI + /* 2166 */ MCD_OPC_FilterValue, + 2, + 31, + 1, + 0, // Skip to: 2458 + /* 2171 */ MCD_OPC_CheckPredicate, + 83, + 26, + 1, + 0, // Skip to: 2458 + /* 2176 */ MCD_OPC_CheckField, + 10, + 11, + 0, + 19, + 1, + 0, // Skip to: 2458 + /* 2183 */ MCD_OPC_Decode, + 193, + 13, + 233, + 2, // Opcode: GINVT + /* 2188 */ MCD_OPC_FilterValue, + 50, + 10, + 0, + 0, // Skip to: 2203 + /* 2193 */ MCD_OPC_CheckPredicate, + 76, + 4, + 1, + 0, // Skip to: 2458 + /* 2198 */ MCD_OPC_Decode, + 209, + 6, + 234, + 2, // Opcode: BC + /* 2203 */ MCD_OPC_FilterValue, + 53, + 27, + 0, + 0, // Skip to: 2235 + /* 2208 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 2225 + /* 2213 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 2225 + /* 2220 */ MCD_OPC_Decode, + 156, + 7, + 169, + 1, // Opcode: BGTZC_MMR6 + /* 2225 */ MCD_OPC_CheckPredicate, + 24, + 228, + 0, + 0, // Skip to: 2458 + /* 2230 */ MCD_OPC_Decode, + 204, + 7, + 169, + 1, // Opcode: BLTZC_MMR6 + /* 2235 */ MCD_OPC_FilterValue, + 54, + 26, + 0, + 0, // Skip to: 2266 + /* 2240 */ MCD_OPC_CheckPredicate, + 75, + 11, + 0, + 0, // Skip to: 2256 + /* 2245 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 2256 + /* 2252 */ MCD_OPC_Decode, + 130, + 14, + 92, // Opcode: JIC + /* 2256 */ MCD_OPC_CheckPredicate, + 76, + 197, + 0, + 0, // Skip to: 2458 + /* 2261 */ MCD_OPC_Decode, + 253, + 6, + 235, + 2, // Opcode: BEQZC + /* 2266 */ MCD_OPC_FilterValue, + 58, + 10, + 0, + 0, // Skip to: 2281 + /* 2271 */ MCD_OPC_CheckPredicate, + 75, + 182, + 0, + 0, // Skip to: 2458 + /* 2276 */ MCD_OPC_Decode, + 201, + 6, + 234, + 2, // Opcode: BALC + /* 2281 */ MCD_OPC_FilterValue, + 59, + 109, + 0, + 0, // Skip to: 2395 + /* 2286 */ MCD_OPC_ExtractField, + 19, + 2, // Inst{20-19} ... + /* 2289 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2304 + /* 2294 */ MCD_OPC_CheckPredicate, + 75, + 159, + 0, + 0, // Skip to: 2458 + /* 2299 */ MCD_OPC_Decode, + 195, + 5, + 163, + 1, // Opcode: ADDIUPC + /* 2304 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2319 + /* 2309 */ MCD_OPC_CheckPredicate, + 75, + 144, + 0, + 0, // Skip to: 2458 + /* 2314 */ MCD_OPC_Decode, + 249, + 14, + 163, + 1, // Opcode: LWPC + /* 2319 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2334 + /* 2324 */ MCD_OPC_CheckPredicate, + 84, + 129, + 0, + 0, // Skip to: 2458 + /* 2329 */ MCD_OPC_Decode, + 130, + 15, + 163, + 1, // Opcode: LWUPC + /* 2334 */ MCD_OPC_FilterValue, + 3, + 119, + 0, + 0, // Skip to: 2458 + /* 2339 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 2342 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2357 + /* 2347 */ MCD_OPC_CheckPredicate, + 84, + 106, + 0, + 0, // Skip to: 2458 + /* 2352 */ MCD_OPC_Decode, + 181, + 14, + 236, + 2, // Opcode: LDPC + /* 2357 */ MCD_OPC_FilterValue, + 1, + 96, + 0, + 0, // Skip to: 2458 + /* 2362 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 2365 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2380 + /* 2370 */ MCD_OPC_CheckPredicate, + 75, + 83, + 0, + 0, // Skip to: 2458 + /* 2375 */ MCD_OPC_Decode, + 170, + 6, + 164, + 1, // Opcode: AUIPC + /* 2380 */ MCD_OPC_FilterValue, + 3, + 73, + 0, + 0, // Skip to: 2458 + /* 2385 */ MCD_OPC_CheckPredicate, + 75, + 68, + 0, + 0, // Skip to: 2458 + /* 2390 */ MCD_OPC_Decode, + 143, + 6, + 164, + 1, // Opcode: ALUIPC + /* 2395 */ MCD_OPC_FilterValue, + 61, + 27, + 0, + 0, // Skip to: 2427 + /* 2400 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 2417 + /* 2405 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 2417 + /* 2412 */ MCD_OPC_Decode, + 185, + 7, + 171, + 1, // Opcode: BLEZC_MMR6 + /* 2417 */ MCD_OPC_CheckPredicate, + 24, + 36, + 0, + 0, // Skip to: 2458 + /* 2422 */ MCD_OPC_Decode, + 147, + 7, + 171, + 1, // Opcode: BGEZC_MMR6 + /* 2427 */ MCD_OPC_FilterValue, + 62, + 26, + 0, + 0, // Skip to: 2458 + /* 2432 */ MCD_OPC_CheckPredicate, + 75, + 11, + 0, + 0, // Skip to: 2448 + /* 2437 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 2448 + /* 2444 */ MCD_OPC_Decode, + 255, + 13, + 92, // Opcode: JIALC + /* 2448 */ MCD_OPC_CheckPredicate, + 76, + 5, + 0, + 0, // Skip to: 2458 + /* 2453 */ MCD_OPC_Decode, + 228, + 7, + 235, + 2, // Opcode: BNEZC + /* 2458 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMips32r6_64r6_Ambiguous32[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 6, + 27, + 0, + 0, // Skip to: 35 + /* 8 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 25 + /* 13 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 25 + /* 20 */ MCD_OPC_Decode, + 181, + 7, + 212, + 2, // Opcode: BLEZALC + /* 25 */ MCD_OPC_CheckPredicate, + 76, + 165, + 0, + 0, // Skip to: 195 + /* 30 */ MCD_OPC_Decode, + 134, + 7, + 212, + 2, // Opcode: BGEUC + /* 35 */ MCD_OPC_FilterValue, + 7, + 27, + 0, + 0, // Skip to: 67 + /* 40 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 57 + /* 45 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 57 + /* 52 */ MCD_OPC_Decode, + 152, + 7, + 213, + 2, // Opcode: BGTZALC + /* 57 */ MCD_OPC_CheckPredicate, + 76, + 133, + 0, + 0, // Skip to: 195 + /* 62 */ MCD_OPC_Decode, + 191, + 7, + 213, + 2, // Opcode: BLTUC + /* 67 */ MCD_OPC_FilterValue, + 8, + 27, + 0, + 0, // Skip to: 99 + /* 72 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 89 + /* 77 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 89 + /* 84 */ MCD_OPC_Decode, + 251, + 6, + 226, + 2, // Opcode: BEQZALC + /* 89 */ MCD_OPC_CheckPredicate, + 76, + 101, + 0, + 0, // Skip to: 195 + /* 94 */ MCD_OPC_Decode, + 241, + 7, + 214, + 2, // Opcode: BOVC + /* 99 */ MCD_OPC_FilterValue, + 22, + 27, + 0, + 0, // Skip to: 131 + /* 104 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 121 + /* 109 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 121 + /* 116 */ MCD_OPC_Decode, + 183, + 7, + 224, + 2, // Opcode: BLEZC + /* 121 */ MCD_OPC_CheckPredicate, + 76, + 69, + 0, + 0, // Skip to: 195 + /* 126 */ MCD_OPC_Decode, + 131, + 7, + 224, + 2, // Opcode: BGEC + /* 131 */ MCD_OPC_FilterValue, + 23, + 27, + 0, + 0, // Skip to: 163 + /* 136 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 153 + /* 141 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 153 + /* 148 */ MCD_OPC_Decode, + 154, + 7, + 225, + 2, // Opcode: BGTZC + /* 153 */ MCD_OPC_CheckPredicate, + 76, + 37, + 0, + 0, // Skip to: 195 + /* 158 */ MCD_OPC_Decode, + 188, + 7, + 225, + 2, // Opcode: BLTC + /* 163 */ MCD_OPC_FilterValue, + 24, + 27, + 0, + 0, // Skip to: 195 + /* 168 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 185 + /* 173 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 185 + /* 180 */ MCD_OPC_Decode, + 226, + 7, + 226, + 2, // Opcode: BNEZALC + /* 185 */ MCD_OPC_CheckPredicate, + 76, + 5, + 0, + 0, // Skip to: 195 + /* 190 */ MCD_OPC_Decode, + 234, + 7, + 226, + 2, // Opcode: BNVC + /* 195 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMips32r6_64r6_BranchZero32[] = { + /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 18 + /* 8 */ MCD_OPC_CheckPredicate, 85, 20, 0, 0, // Skip to: 33 + /* 13 */ MCD_OPC_Decode, 146, 7, 224, 2, // Opcode: BGEZC64 + /* 18 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 33 + /* 23 */ MCD_OPC_CheckPredicate, 85, 5, 0, 0, // Skip to: 33 + /* 28 */ MCD_OPC_Decode, 203, 7, 225, 2, // Opcode: BLTZC64 + /* 33 */ MCD_OPC_Fail, 0}; static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = { -/* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... -/* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22 -/* 7 */ MCD_OPC_CheckPredicate, 39, 30, 0, // Skip to: 41 -/* 11 */ MCD_OPC_CheckField, 26, 6, 0, 24, 0, // Skip to: 41 -/* 17 */ MCD_OPC_Decode, 175, 11, 224, 1, // Opcode: SELEQZ64 -/* 22 */ MCD_OPC_FilterValue, 55, 15, 0, // Skip to: 41 -/* 26 */ MCD_OPC_CheckPredicate, 39, 11, 0, // Skip to: 41 -/* 30 */ MCD_OPC_CheckField, 26, 6, 0, 5, 0, // Skip to: 41 -/* 36 */ MCD_OPC_Decode, 179, 11, 224, 1, // Opcode: SELNEZ64 -/* 41 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 61 + /* 8 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 11 */ MCD_OPC_FilterValue, + 53, + 9, + 0, + 0, // Skip to: 25 + /* 16 */ MCD_OPC_CheckPredicate, + 86, + 226, + 0, + 0, // Skip to: 247 + /* 21 */ MCD_OPC_Decode, + 152, + 19, + 12, // Opcode: SELEQZ64 + /* 25 */ MCD_OPC_FilterValue, + 55, + 9, + 0, + 0, // Skip to: 39 + /* 30 */ MCD_OPC_CheckPredicate, + 86, + 212, + 0, + 0, // Skip to: 247 + /* 35 */ MCD_OPC_Decode, + 159, + 19, + 12, // Opcode: SELNEZ64 + /* 39 */ MCD_OPC_FilterValue, + 137, + 8, + 202, + 0, + 0, // Skip to: 247 + /* 45 */ MCD_OPC_CheckPredicate, + 75, + 197, + 0, + 0, // Skip to: 247 + /* 50 */ MCD_OPC_CheckField, + 11, + 10, + 0, + 190, + 0, + 0, // Skip to: 247 + /* 57 */ MCD_OPC_Decode, + 142, + 14, + 13, // Opcode: JR_HB64_R6 + /* 61 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 76 + /* 66 */ MCD_OPC_CheckPredicate, + 85, + 176, + 0, + 0, // Skip to: 247 + /* 71 */ MCD_OPC_Decode, + 135, + 7, + 212, + 2, // Opcode: BGEUC64 + /* 76 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 91 + /* 81 */ MCD_OPC_CheckPredicate, + 85, + 161, + 0, + 0, // Skip to: 247 + /* 86 */ MCD_OPC_Decode, + 192, + 7, + 213, + 2, // Opcode: BLTUC64 + /* 91 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 106 + /* 96 */ MCD_OPC_CheckPredicate, + 85, + 146, + 0, + 0, // Skip to: 247 + /* 101 */ MCD_OPC_Decode, + 247, + 6, + 214, + 2, // Opcode: BEQC64 + /* 106 */ MCD_OPC_FilterValue, + 22, + 27, + 0, + 0, // Skip to: 138 + /* 111 */ MCD_OPC_CheckPredicate, + 85, + 12, + 0, + 0, // Skip to: 128 + /* 116 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 128 + /* 123 */ MCD_OPC_Decode, + 184, + 7, + 224, + 2, // Opcode: BLEZC64 + /* 128 */ MCD_OPC_CheckPredicate, + 85, + 114, + 0, + 0, // Skip to: 247 + /* 133 */ MCD_OPC_Decode, + 132, + 7, + 224, + 2, // Opcode: BGEC64 + /* 138 */ MCD_OPC_FilterValue, + 23, + 27, + 0, + 0, // Skip to: 170 + /* 143 */ MCD_OPC_CheckPredicate, + 85, + 12, + 0, + 0, // Skip to: 160 + /* 148 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 160 + /* 155 */ MCD_OPC_Decode, + 155, + 7, + 225, + 2, // Opcode: BGTZC64 + /* 160 */ MCD_OPC_CheckPredicate, + 85, + 82, + 0, + 0, // Skip to: 247 + /* 165 */ MCD_OPC_Decode, + 189, + 7, + 225, + 2, // Opcode: BLTC64 + /* 170 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 185 + /* 175 */ MCD_OPC_CheckPredicate, + 85, + 67, + 0, + 0, // Skip to: 247 + /* 180 */ MCD_OPC_Decode, + 214, + 7, + 226, + 2, // Opcode: BNEC64 + /* 185 */ MCD_OPC_FilterValue, + 54, + 26, + 0, + 0, // Skip to: 216 + /* 190 */ MCD_OPC_CheckPredicate, + 85, + 11, + 0, + 0, // Skip to: 206 + /* 195 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 206 + /* 202 */ MCD_OPC_Decode, + 131, + 14, + 11, // Opcode: JIC64 + /* 206 */ MCD_OPC_CheckPredicate, + 85, + 36, + 0, + 0, // Skip to: 247 + /* 211 */ MCD_OPC_Decode, + 255, + 6, + 237, + 2, // Opcode: BEQZC64 + /* 216 */ MCD_OPC_FilterValue, + 62, + 26, + 0, + 0, // Skip to: 247 + /* 221 */ MCD_OPC_CheckPredicate, + 85, + 11, + 0, + 0, // Skip to: 237 + /* 226 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 237 + /* 233 */ MCD_OPC_Decode, + 128, + 14, + 11, // Opcode: JIALC64 + /* 237 */ MCD_OPC_CheckPredicate, + 85, + 5, + 0, + 0, // Skip to: 247 + /* 242 */ MCD_OPC_Decode, + 230, + 7, + 237, + 2, // Opcode: BNEZC64 + /* 247 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMips32r6_64r6_PTR6432[] = { + /* 0 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 3 */ MCD_OPC_FilterValue, + 38, + 17, + 0, + 0, // Skip to: 25 + /* 8 */ MCD_OPC_CheckPredicate, + 87, + 34, + 0, + 0, // Skip to: 47 + /* 13 */ MCD_OPC_CheckField, + 26, + 6, + 31, + 27, + 0, + 0, // Skip to: 47 + /* 20 */ MCD_OPC_Decode, + 244, + 18, + 232, + 2, // Opcode: SC64_R6 + /* 25 */ MCD_OPC_FilterValue, + 54, + 17, + 0, + 0, // Skip to: 47 + /* 30 */ MCD_OPC_CheckPredicate, + 87, + 12, + 0, + 0, // Skip to: 47 + /* 35 */ MCD_OPC_CheckField, + 26, + 6, + 31, + 5, + 0, + 0, // Skip to: 47 + /* 42 */ MCD_OPC_Decode, + 209, + 14, + 232, + 2, // Opcode: LL64_R6 + /* 47 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableMips6432[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 29 -/* 14 */ MCD_OPC_CheckPredicate, 19, 42, 9, // Skip to: 2364 -/* 18 */ MCD_OPC_CheckField, 6, 5, 0, 36, 9, // Skip to: 2364 -/* 24 */ MCD_OPC_Decode, 255, 4, 252, 1, // Opcode: DSLLV -/* 29 */ MCD_OPC_FilterValue, 22, 29, 0, // Skip to: 62 -/* 33 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 36 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 49 -/* 40 */ MCD_OPC_CheckPredicate, 19, 16, 9, // Skip to: 2364 -/* 44 */ MCD_OPC_Decode, 133, 5, 252, 1, // Opcode: DSRLV -/* 49 */ MCD_OPC_FilterValue, 1, 7, 9, // Skip to: 2364 -/* 53 */ MCD_OPC_CheckPredicate, 40, 3, 9, // Skip to: 2364 -/* 57 */ MCD_OPC_Decode, 248, 4, 252, 1, // Opcode: DROTRV -/* 62 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 81 -/* 66 */ MCD_OPC_CheckPredicate, 19, 246, 8, // Skip to: 2364 -/* 70 */ MCD_OPC_CheckField, 6, 5, 0, 240, 8, // Skip to: 2364 -/* 76 */ MCD_OPC_Decode, 130, 5, 252, 1, // Opcode: DSRAV -/* 81 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 100 -/* 85 */ MCD_OPC_CheckPredicate, 41, 227, 8, // Skip to: 2364 -/* 89 */ MCD_OPC_CheckField, 6, 10, 0, 221, 8, // Skip to: 2364 -/* 95 */ MCD_OPC_Decode, 207, 4, 253, 1, // Opcode: DMULT -/* 100 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 119 -/* 104 */ MCD_OPC_CheckPredicate, 41, 208, 8, // Skip to: 2364 -/* 108 */ MCD_OPC_CheckField, 6, 10, 0, 202, 8, // Skip to: 2364 -/* 114 */ MCD_OPC_Decode, 208, 4, 253, 1, // Opcode: DMULTu -/* 119 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 138 -/* 123 */ MCD_OPC_CheckPredicate, 41, 189, 8, // Skip to: 2364 -/* 127 */ MCD_OPC_CheckField, 6, 10, 0, 183, 8, // Skip to: 2364 -/* 133 */ MCD_OPC_Decode, 250, 4, 253, 1, // Opcode: DSDIV -/* 138 */ MCD_OPC_FilterValue, 31, 15, 0, // Skip to: 157 -/* 142 */ MCD_OPC_CheckPredicate, 41, 170, 8, // Skip to: 2364 -/* 146 */ MCD_OPC_CheckField, 6, 10, 0, 164, 8, // Skip to: 2364 -/* 152 */ MCD_OPC_Decode, 136, 5, 253, 1, // Opcode: DUDIV -/* 157 */ MCD_OPC_FilterValue, 44, 15, 0, // Skip to: 176 -/* 161 */ MCD_OPC_CheckPredicate, 19, 151, 8, // Skip to: 2364 -/* 165 */ MCD_OPC_CheckField, 6, 5, 0, 145, 8, // Skip to: 2364 -/* 171 */ MCD_OPC_Decode, 159, 4, 224, 1, // Opcode: DADD -/* 176 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 195 -/* 180 */ MCD_OPC_CheckPredicate, 19, 132, 8, // Skip to: 2364 -/* 184 */ MCD_OPC_CheckField, 6, 5, 0, 126, 8, // Skip to: 2364 -/* 190 */ MCD_OPC_Decode, 162, 4, 224, 1, // Opcode: DADDu -/* 195 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 214 -/* 199 */ MCD_OPC_CheckPredicate, 19, 113, 8, // Skip to: 2364 -/* 203 */ MCD_OPC_CheckField, 6, 5, 0, 107, 8, // Skip to: 2364 -/* 209 */ MCD_OPC_Decode, 134, 5, 224, 1, // Opcode: DSUB -/* 214 */ MCD_OPC_FilterValue, 47, 15, 0, // Skip to: 233 -/* 218 */ MCD_OPC_CheckPredicate, 19, 94, 8, // Skip to: 2364 -/* 222 */ MCD_OPC_CheckField, 6, 5, 0, 88, 8, // Skip to: 2364 -/* 228 */ MCD_OPC_Decode, 135, 5, 224, 1, // Opcode: DSUBu -/* 233 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 252 -/* 237 */ MCD_OPC_CheckPredicate, 19, 75, 8, // Skip to: 2364 -/* 241 */ MCD_OPC_CheckField, 21, 5, 0, 69, 8, // Skip to: 2364 -/* 247 */ MCD_OPC_Decode, 252, 4, 254, 1, // Opcode: DSLL -/* 252 */ MCD_OPC_FilterValue, 58, 29, 0, // Skip to: 285 -/* 256 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 259 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 272 -/* 263 */ MCD_OPC_CheckPredicate, 19, 49, 8, // Skip to: 2364 -/* 267 */ MCD_OPC_Decode, 131, 5, 254, 1, // Opcode: DSRL -/* 272 */ MCD_OPC_FilterValue, 1, 40, 8, // Skip to: 2364 -/* 276 */ MCD_OPC_CheckPredicate, 40, 36, 8, // Skip to: 2364 -/* 280 */ MCD_OPC_Decode, 246, 4, 254, 1, // Opcode: DROTR -/* 285 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 304 -/* 289 */ MCD_OPC_CheckPredicate, 19, 23, 8, // Skip to: 2364 -/* 293 */ MCD_OPC_CheckField, 21, 5, 0, 17, 8, // Skip to: 2364 -/* 299 */ MCD_OPC_Decode, 128, 5, 254, 1, // Opcode: DSRA -/* 304 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 323 -/* 308 */ MCD_OPC_CheckPredicate, 19, 4, 8, // Skip to: 2364 -/* 312 */ MCD_OPC_CheckField, 21, 5, 0, 254, 7, // Skip to: 2364 -/* 318 */ MCD_OPC_Decode, 253, 4, 254, 1, // Opcode: DSLL32 -/* 323 */ MCD_OPC_FilterValue, 62, 29, 0, // Skip to: 356 -/* 327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 330 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 343 -/* 334 */ MCD_OPC_CheckPredicate, 19, 234, 7, // Skip to: 2364 -/* 338 */ MCD_OPC_Decode, 132, 5, 254, 1, // Opcode: DSRL32 -/* 343 */ MCD_OPC_FilterValue, 1, 225, 7, // Skip to: 2364 -/* 347 */ MCD_OPC_CheckPredicate, 40, 221, 7, // Skip to: 2364 -/* 351 */ MCD_OPC_Decode, 247, 4, 254, 1, // Opcode: DROTR32 -/* 356 */ MCD_OPC_FilterValue, 63, 212, 7, // Skip to: 2364 -/* 360 */ MCD_OPC_CheckPredicate, 19, 208, 7, // Skip to: 2364 -/* 364 */ MCD_OPC_CheckField, 21, 5, 0, 202, 7, // Skip to: 2364 -/* 370 */ MCD_OPC_Decode, 129, 5, 254, 1, // Opcode: DSRA32 -/* 375 */ MCD_OPC_FilterValue, 16, 41, 0, // Skip to: 420 -/* 379 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 382 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 401 -/* 386 */ MCD_OPC_CheckPredicate, 42, 182, 7, // Skip to: 2364 -/* 390 */ MCD_OPC_CheckField, 3, 8, 0, 176, 7, // Skip to: 2364 -/* 396 */ MCD_OPC_Decode, 196, 4, 255, 1, // Opcode: DMFC0 -/* 401 */ MCD_OPC_FilterValue, 5, 167, 7, // Skip to: 2364 -/* 405 */ MCD_OPC_CheckPredicate, 42, 163, 7, // Skip to: 2364 -/* 409 */ MCD_OPC_CheckField, 3, 8, 0, 157, 7, // Skip to: 2364 -/* 415 */ MCD_OPC_Decode, 201, 4, 255, 1, // Opcode: DMTC0 -/* 420 */ MCD_OPC_FilterValue, 17, 222, 3, // Skip to: 1414 -/* 424 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 427 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 485 -/* 431 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 434 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 453 -/* 438 */ MCD_OPC_CheckPredicate, 43, 130, 7, // Skip to: 2364 -/* 442 */ MCD_OPC_CheckField, 6, 5, 0, 124, 7, // Skip to: 2364 -/* 448 */ MCD_OPC_Decode, 184, 8, 128, 2, // Opcode: MFHC1_D64 -/* 453 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 472 -/* 457 */ MCD_OPC_CheckPredicate, 43, 111, 7, // Skip to: 2364 -/* 461 */ MCD_OPC_CheckField, 6, 5, 0, 105, 7, // Skip to: 2364 -/* 467 */ MCD_OPC_Decode, 174, 9, 129, 2, // Opcode: MTHC1_D64 -/* 472 */ MCD_OPC_FilterValue, 17, 96, 7, // Skip to: 2364 -/* 476 */ MCD_OPC_CheckPredicate, 44, 92, 7, // Skip to: 2364 -/* 480 */ MCD_OPC_Decode, 172, 5, 233, 1, // Opcode: FADD_D64 -/* 485 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 504 -/* 489 */ MCD_OPC_CheckPredicate, 44, 79, 7, // Skip to: 2364 -/* 493 */ MCD_OPC_CheckField, 21, 5, 17, 73, 7, // Skip to: 2364 -/* 499 */ MCD_OPC_Decode, 174, 6, 233, 1, // Opcode: FSUB_D64 -/* 504 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 523 -/* 508 */ MCD_OPC_CheckPredicate, 44, 60, 7, // Skip to: 2364 -/* 512 */ MCD_OPC_CheckField, 21, 5, 17, 54, 7, // Skip to: 2364 -/* 518 */ MCD_OPC_Decode, 137, 6, 233, 1, // Opcode: FMUL_D64 -/* 523 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 542 -/* 527 */ MCD_OPC_CheckPredicate, 44, 41, 7, // Skip to: 2364 -/* 531 */ MCD_OPC_CheckField, 21, 5, 17, 35, 7, // Skip to: 2364 -/* 537 */ MCD_OPC_Decode, 208, 5, 233, 1, // Opcode: FDIV_D64 -/* 542 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 561 -/* 546 */ MCD_OPC_CheckPredicate, 45, 22, 7, // Skip to: 2364 -/* 550 */ MCD_OPC_CheckField, 16, 10, 160, 4, 15, 7, // Skip to: 2364 -/* 557 */ MCD_OPC_Decode, 167, 6, 105, // Opcode: FSQRT_D64 -/* 561 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 580 -/* 565 */ MCD_OPC_CheckPredicate, 44, 3, 7, // Skip to: 2364 -/* 569 */ MCD_OPC_CheckField, 16, 10, 160, 4, 252, 6, // Skip to: 2364 -/* 576 */ MCD_OPC_Decode, 165, 5, 105, // Opcode: FABS_D64 -/* 580 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 599 -/* 584 */ MCD_OPC_CheckPredicate, 44, 240, 6, // Skip to: 2364 -/* 588 */ MCD_OPC_CheckField, 16, 10, 160, 4, 233, 6, // Skip to: 2364 -/* 595 */ MCD_OPC_Decode, 130, 6, 105, // Opcode: FMOV_D64 -/* 599 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 618 -/* 603 */ MCD_OPC_CheckPredicate, 44, 221, 6, // Skip to: 2364 -/* 607 */ MCD_OPC_CheckField, 16, 10, 160, 4, 214, 6, // Skip to: 2364 -/* 614 */ MCD_OPC_Decode, 143, 6, 105, // Opcode: FNEG_D64 -/* 618 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 651 -/* 622 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 625 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 638 -/* 630 */ MCD_OPC_CheckPredicate, 44, 194, 6, // Skip to: 2364 -/* 634 */ MCD_OPC_Decode, 252, 10, 98, // Opcode: ROUND_L_S -/* 638 */ MCD_OPC_FilterValue, 160, 4, 185, 6, // Skip to: 2364 -/* 643 */ MCD_OPC_CheckPredicate, 44, 181, 6, // Skip to: 2364 -/* 647 */ MCD_OPC_Decode, 251, 10, 105, // Opcode: ROUND_L_D64 -/* 651 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 684 -/* 655 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 658 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 671 -/* 663 */ MCD_OPC_CheckPredicate, 44, 161, 6, // Skip to: 2364 -/* 667 */ MCD_OPC_Decode, 215, 13, 98, // Opcode: TRUNC_L_S -/* 671 */ MCD_OPC_FilterValue, 160, 4, 152, 6, // Skip to: 2364 -/* 676 */ MCD_OPC_CheckPredicate, 44, 148, 6, // Skip to: 2364 -/* 680 */ MCD_OPC_Decode, 214, 13, 105, // Opcode: TRUNC_L_D64 -/* 684 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 717 -/* 688 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 691 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 704 -/* 696 */ MCD_OPC_CheckPredicate, 44, 128, 6, // Skip to: 2364 -/* 700 */ MCD_OPC_Decode, 224, 2, 98, // Opcode: CEIL_L_S -/* 704 */ MCD_OPC_FilterValue, 160, 4, 119, 6, // Skip to: 2364 -/* 709 */ MCD_OPC_CheckPredicate, 44, 115, 6, // Skip to: 2364 -/* 713 */ MCD_OPC_Decode, 223, 2, 105, // Opcode: CEIL_L_D64 -/* 717 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 750 -/* 721 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 724 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 737 -/* 729 */ MCD_OPC_CheckPredicate, 44, 95, 6, // Skip to: 2364 -/* 733 */ MCD_OPC_Decode, 240, 5, 98, // Opcode: FLOOR_L_S -/* 737 */ MCD_OPC_FilterValue, 160, 4, 86, 6, // Skip to: 2364 -/* 742 */ MCD_OPC_CheckPredicate, 44, 82, 6, // Skip to: 2364 -/* 746 */ MCD_OPC_Decode, 239, 5, 105, // Opcode: FLOOR_L_D64 -/* 750 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 770 -/* 754 */ MCD_OPC_CheckPredicate, 45, 70, 6, // Skip to: 2364 -/* 758 */ MCD_OPC_CheckField, 16, 10, 160, 4, 63, 6, // Skip to: 2364 -/* 765 */ MCD_OPC_Decode, 254, 10, 130, 2, // Opcode: ROUND_W_D64 -/* 770 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 790 -/* 774 */ MCD_OPC_CheckPredicate, 45, 50, 6, // Skip to: 2364 -/* 778 */ MCD_OPC_CheckField, 16, 10, 160, 4, 43, 6, // Skip to: 2364 -/* 785 */ MCD_OPC_Decode, 217, 13, 130, 2, // Opcode: TRUNC_W_D64 -/* 790 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 810 -/* 794 */ MCD_OPC_CheckPredicate, 45, 30, 6, // Skip to: 2364 -/* 798 */ MCD_OPC_CheckField, 16, 10, 160, 4, 23, 6, // Skip to: 2364 -/* 805 */ MCD_OPC_Decode, 226, 2, 130, 2, // Opcode: CEIL_W_D64 -/* 810 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 830 -/* 814 */ MCD_OPC_CheckPredicate, 45, 10, 6, // Skip to: 2364 -/* 818 */ MCD_OPC_CheckField, 16, 10, 160, 4, 3, 6, // Skip to: 2364 -/* 825 */ MCD_OPC_Decode, 242, 5, 130, 2, // Opcode: FLOOR_W_D64 -/* 830 */ MCD_OPC_FilterValue, 17, 41, 0, // Skip to: 875 -/* 834 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 837 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 856 -/* 841 */ MCD_OPC_CheckPredicate, 46, 239, 5, // Skip to: 2364 -/* 845 */ MCD_OPC_CheckField, 21, 5, 17, 233, 5, // Skip to: 2364 -/* 851 */ MCD_OPC_Decode, 238, 8, 131, 2, // Opcode: MOVF_D64 -/* 856 */ MCD_OPC_FilterValue, 1, 224, 5, // Skip to: 2364 -/* 860 */ MCD_OPC_CheckPredicate, 46, 220, 5, // Skip to: 2364 -/* 864 */ MCD_OPC_CheckField, 21, 5, 17, 214, 5, // Skip to: 2364 -/* 870 */ MCD_OPC_Decode, 130, 9, 131, 2, // Opcode: MOVT_D64 -/* 875 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 894 -/* 879 */ MCD_OPC_CheckPredicate, 46, 201, 5, // Skip to: 2364 -/* 883 */ MCD_OPC_CheckField, 21, 5, 17, 195, 5, // Skip to: 2364 -/* 889 */ MCD_OPC_Decode, 142, 9, 132, 2, // Opcode: MOVZ_I_D64 -/* 894 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 913 -/* 898 */ MCD_OPC_CheckPredicate, 46, 182, 5, // Skip to: 2364 -/* 902 */ MCD_OPC_CheckField, 21, 5, 17, 176, 5, // Skip to: 2364 -/* 908 */ MCD_OPC_Decode, 250, 8, 132, 2, // Opcode: MOVN_I_D64 -/* 913 */ MCD_OPC_FilterValue, 32, 31, 0, // Skip to: 948 -/* 917 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 920 */ MCD_OPC_FilterValue, 160, 4, 9, 0, // Skip to: 934 -/* 925 */ MCD_OPC_CheckPredicate, 44, 155, 5, // Skip to: 2364 -/* 929 */ MCD_OPC_Decode, 226, 3, 130, 2, // Opcode: CVT_S_D64 -/* 934 */ MCD_OPC_FilterValue, 160, 5, 145, 5, // Skip to: 2364 -/* 939 */ MCD_OPC_CheckPredicate, 44, 141, 5, // Skip to: 2364 -/* 943 */ MCD_OPC_Decode, 227, 3, 130, 2, // Opcode: CVT_S_L -/* 948 */ MCD_OPC_FilterValue, 33, 42, 0, // Skip to: 994 -/* 952 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 955 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 968 -/* 960 */ MCD_OPC_CheckPredicate, 44, 120, 5, // Skip to: 2364 -/* 964 */ MCD_OPC_Decode, 217, 3, 98, // Opcode: CVT_D64_S -/* 968 */ MCD_OPC_FilterValue, 128, 5, 8, 0, // Skip to: 981 -/* 973 */ MCD_OPC_CheckPredicate, 44, 107, 5, // Skip to: 2364 -/* 977 */ MCD_OPC_Decode, 218, 3, 98, // Opcode: CVT_D64_W -/* 981 */ MCD_OPC_FilterValue, 160, 5, 98, 5, // Skip to: 2364 -/* 986 */ MCD_OPC_CheckPredicate, 44, 94, 5, // Skip to: 2364 -/* 990 */ MCD_OPC_Decode, 216, 3, 105, // Opcode: CVT_D64_L -/* 994 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1014 -/* 998 */ MCD_OPC_CheckPredicate, 44, 82, 5, // Skip to: 2364 -/* 1002 */ MCD_OPC_CheckField, 16, 10, 160, 4, 75, 5, // Skip to: 2364 -/* 1009 */ MCD_OPC_Decode, 231, 3, 130, 2, // Opcode: CVT_W_D64 -/* 1014 */ MCD_OPC_FilterValue, 48, 21, 0, // Skip to: 1039 -/* 1018 */ MCD_OPC_CheckPredicate, 47, 62, 5, // Skip to: 2364 -/* 1022 */ MCD_OPC_CheckField, 21, 5, 17, 56, 5, // Skip to: 2364 -/* 1028 */ MCD_OPC_CheckField, 6, 5, 0, 50, 5, // Skip to: 2364 -/* 1034 */ MCD_OPC_Decode, 239, 3, 133, 2, // Opcode: C_F_D64 -/* 1039 */ MCD_OPC_FilterValue, 49, 21, 0, // Skip to: 1064 -/* 1043 */ MCD_OPC_CheckPredicate, 47, 37, 5, // Skip to: 2364 -/* 1047 */ MCD_OPC_CheckField, 21, 5, 17, 31, 5, // Skip to: 2364 -/* 1053 */ MCD_OPC_CheckField, 6, 5, 0, 25, 5, // Skip to: 2364 -/* 1059 */ MCD_OPC_Decode, 153, 4, 133, 2, // Opcode: C_UN_D64 -/* 1064 */ MCD_OPC_FilterValue, 50, 21, 0, // Skip to: 1089 -/* 1068 */ MCD_OPC_CheckPredicate, 47, 12, 5, // Skip to: 2364 -/* 1072 */ MCD_OPC_CheckField, 21, 5, 17, 6, 5, // Skip to: 2364 -/* 1078 */ MCD_OPC_CheckField, 6, 5, 0, 0, 5, // Skip to: 2364 -/* 1084 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: C_EQ_D64 -/* 1089 */ MCD_OPC_FilterValue, 51, 21, 0, // Skip to: 1114 -/* 1093 */ MCD_OPC_CheckPredicate, 47, 243, 4, // Skip to: 2364 -/* 1097 */ MCD_OPC_CheckField, 21, 5, 17, 237, 4, // Skip to: 2364 -/* 1103 */ MCD_OPC_CheckField, 6, 5, 0, 231, 4, // Skip to: 2364 -/* 1109 */ MCD_OPC_Decode, 144, 4, 133, 2, // Opcode: C_UEQ_D64 -/* 1114 */ MCD_OPC_FilterValue, 52, 21, 0, // Skip to: 1139 -/* 1118 */ MCD_OPC_CheckPredicate, 47, 218, 4, // Skip to: 2364 -/* 1122 */ MCD_OPC_CheckField, 21, 5, 17, 212, 4, // Skip to: 2364 -/* 1128 */ MCD_OPC_CheckField, 6, 5, 0, 206, 4, // Skip to: 2364 -/* 1134 */ MCD_OPC_Decode, 135, 4, 133, 2, // Opcode: C_OLT_D64 -/* 1139 */ MCD_OPC_FilterValue, 53, 21, 0, // Skip to: 1164 -/* 1143 */ MCD_OPC_CheckPredicate, 47, 193, 4, // Skip to: 2364 -/* 1147 */ MCD_OPC_CheckField, 21, 5, 17, 187, 4, // Skip to: 2364 -/* 1153 */ MCD_OPC_CheckField, 6, 5, 0, 181, 4, // Skip to: 2364 -/* 1159 */ MCD_OPC_Decode, 150, 4, 133, 2, // Opcode: C_ULT_D64 -/* 1164 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 1189 -/* 1168 */ MCD_OPC_CheckPredicate, 47, 168, 4, // Skip to: 2364 -/* 1172 */ MCD_OPC_CheckField, 21, 5, 17, 162, 4, // Skip to: 2364 -/* 1178 */ MCD_OPC_CheckField, 6, 5, 0, 156, 4, // Skip to: 2364 -/* 1184 */ MCD_OPC_Decode, 132, 4, 133, 2, // Opcode: C_OLE_D64 -/* 1189 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 1214 -/* 1193 */ MCD_OPC_CheckPredicate, 47, 143, 4, // Skip to: 2364 -/* 1197 */ MCD_OPC_CheckField, 21, 5, 17, 137, 4, // Skip to: 2364 -/* 1203 */ MCD_OPC_CheckField, 6, 5, 0, 131, 4, // Skip to: 2364 -/* 1209 */ MCD_OPC_Decode, 147, 4, 133, 2, // Opcode: C_ULE_D64 -/* 1214 */ MCD_OPC_FilterValue, 56, 21, 0, // Skip to: 1239 -/* 1218 */ MCD_OPC_CheckPredicate, 47, 118, 4, // Skip to: 2364 -/* 1222 */ MCD_OPC_CheckField, 21, 5, 17, 112, 4, // Skip to: 2364 -/* 1228 */ MCD_OPC_CheckField, 6, 5, 0, 106, 4, // Skip to: 2364 -/* 1234 */ MCD_OPC_Decode, 141, 4, 133, 2, // Opcode: C_SF_D64 -/* 1239 */ MCD_OPC_FilterValue, 57, 21, 0, // Skip to: 1264 -/* 1243 */ MCD_OPC_CheckPredicate, 47, 93, 4, // Skip to: 2364 -/* 1247 */ MCD_OPC_CheckField, 21, 5, 17, 87, 4, // Skip to: 2364 -/* 1253 */ MCD_OPC_CheckField, 6, 5, 0, 81, 4, // Skip to: 2364 -/* 1259 */ MCD_OPC_Decode, 251, 3, 133, 2, // Opcode: C_NGLE_D64 -/* 1264 */ MCD_OPC_FilterValue, 58, 21, 0, // Skip to: 1289 -/* 1268 */ MCD_OPC_CheckPredicate, 47, 68, 4, // Skip to: 2364 -/* 1272 */ MCD_OPC_CheckField, 21, 5, 17, 62, 4, // Skip to: 2364 -/* 1278 */ MCD_OPC_CheckField, 6, 5, 0, 56, 4, // Skip to: 2364 -/* 1284 */ MCD_OPC_Decode, 138, 4, 133, 2, // Opcode: C_SEQ_D64 -/* 1289 */ MCD_OPC_FilterValue, 59, 21, 0, // Skip to: 1314 -/* 1293 */ MCD_OPC_CheckPredicate, 47, 43, 4, // Skip to: 2364 -/* 1297 */ MCD_OPC_CheckField, 21, 5, 17, 37, 4, // Skip to: 2364 -/* 1303 */ MCD_OPC_CheckField, 6, 5, 0, 31, 4, // Skip to: 2364 -/* 1309 */ MCD_OPC_Decode, 254, 3, 133, 2, // Opcode: C_NGL_D64 -/* 1314 */ MCD_OPC_FilterValue, 60, 21, 0, // Skip to: 1339 -/* 1318 */ MCD_OPC_CheckPredicate, 47, 18, 4, // Skip to: 2364 -/* 1322 */ MCD_OPC_CheckField, 21, 5, 17, 12, 4, // Skip to: 2364 -/* 1328 */ MCD_OPC_CheckField, 6, 5, 0, 6, 4, // Skip to: 2364 -/* 1334 */ MCD_OPC_Decode, 245, 3, 133, 2, // Opcode: C_LT_D64 -/* 1339 */ MCD_OPC_FilterValue, 61, 21, 0, // Skip to: 1364 -/* 1343 */ MCD_OPC_CheckPredicate, 47, 249, 3, // Skip to: 2364 -/* 1347 */ MCD_OPC_CheckField, 21, 5, 17, 243, 3, // Skip to: 2364 -/* 1353 */ MCD_OPC_CheckField, 6, 5, 0, 237, 3, // Skip to: 2364 -/* 1359 */ MCD_OPC_Decode, 248, 3, 133, 2, // Opcode: C_NGE_D64 -/* 1364 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 1389 -/* 1368 */ MCD_OPC_CheckPredicate, 47, 224, 3, // Skip to: 2364 -/* 1372 */ MCD_OPC_CheckField, 21, 5, 17, 218, 3, // Skip to: 2364 -/* 1378 */ MCD_OPC_CheckField, 6, 5, 0, 212, 3, // Skip to: 2364 -/* 1384 */ MCD_OPC_Decode, 242, 3, 133, 2, // Opcode: C_LE_D64 -/* 1389 */ MCD_OPC_FilterValue, 63, 203, 3, // Skip to: 2364 -/* 1393 */ MCD_OPC_CheckPredicate, 47, 199, 3, // Skip to: 2364 -/* 1397 */ MCD_OPC_CheckField, 21, 5, 17, 193, 3, // Skip to: 2364 -/* 1403 */ MCD_OPC_CheckField, 6, 5, 0, 187, 3, // Skip to: 2364 -/* 1409 */ MCD_OPC_Decode, 129, 4, 133, 2, // Opcode: C_NGT_D64 -/* 1414 */ MCD_OPC_FilterValue, 18, 41, 0, // Skip to: 1459 -/* 1418 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1421 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1440 -/* 1425 */ MCD_OPC_CheckPredicate, 42, 167, 3, // Skip to: 2364 -/* 1429 */ MCD_OPC_CheckField, 3, 8, 0, 161, 3, // Skip to: 2364 -/* 1435 */ MCD_OPC_Decode, 198, 4, 255, 1, // Opcode: DMFC2 -/* 1440 */ MCD_OPC_FilterValue, 5, 152, 3, // Skip to: 2364 -/* 1444 */ MCD_OPC_CheckPredicate, 42, 148, 3, // Skip to: 2364 -/* 1448 */ MCD_OPC_CheckField, 3, 8, 0, 142, 3, // Skip to: 2364 -/* 1454 */ MCD_OPC_Decode, 203, 4, 255, 1, // Opcode: DMTC2 -/* 1459 */ MCD_OPC_FilterValue, 19, 131, 0, // Skip to: 1594 -/* 1463 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1466 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1485 -/* 1470 */ MCD_OPC_CheckPredicate, 48, 122, 3, // Skip to: 2364 -/* 1474 */ MCD_OPC_CheckField, 11, 5, 0, 116, 3, // Skip to: 2364 -/* 1480 */ MCD_OPC_Decode, 176, 7, 134, 2, // Opcode: LDXC164 -/* 1485 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1504 -/* 1489 */ MCD_OPC_CheckPredicate, 49, 103, 3, // Skip to: 2364 -/* 1493 */ MCD_OPC_CheckField, 11, 5, 0, 97, 3, // Skip to: 2364 -/* 1499 */ MCD_OPC_Decode, 208, 7, 134, 2, // Opcode: LUXC164 -/* 1504 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1523 -/* 1508 */ MCD_OPC_CheckPredicate, 48, 84, 3, // Skip to: 2364 -/* 1512 */ MCD_OPC_CheckField, 6, 5, 0, 78, 3, // Skip to: 2364 -/* 1518 */ MCD_OPC_Decode, 167, 11, 135, 2, // Opcode: SDXC164 -/* 1523 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1542 -/* 1527 */ MCD_OPC_CheckPredicate, 49, 65, 3, // Skip to: 2364 -/* 1531 */ MCD_OPC_CheckField, 6, 5, 0, 59, 3, // Skip to: 2364 -/* 1537 */ MCD_OPC_Decode, 233, 12, 135, 2, // Opcode: SUXC164 -/* 1542 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 1555 -/* 1546 */ MCD_OPC_CheckPredicate, 48, 46, 3, // Skip to: 2364 -/* 1550 */ MCD_OPC_Decode, 144, 8, 136, 2, // Opcode: MADD_D64 -/* 1555 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 1568 -/* 1559 */ MCD_OPC_CheckPredicate, 48, 33, 3, // Skip to: 2364 -/* 1563 */ MCD_OPC_Decode, 162, 9, 136, 2, // Opcode: MSUB_D64 -/* 1568 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 1581 -/* 1572 */ MCD_OPC_CheckPredicate, 48, 20, 3, // Skip to: 2364 -/* 1576 */ MCD_OPC_Decode, 241, 9, 136, 2, // Opcode: NMADD_D64 -/* 1581 */ MCD_OPC_FilterValue, 57, 11, 3, // Skip to: 2364 -/* 1585 */ MCD_OPC_CheckPredicate, 48, 7, 3, // Skip to: 2364 -/* 1589 */ MCD_OPC_Decode, 246, 9, 136, 2, // Opcode: NMSUB_D64 -/* 1594 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1607 -/* 1598 */ MCD_OPC_CheckPredicate, 41, 250, 2, // Skip to: 2364 -/* 1602 */ MCD_OPC_Decode, 160, 4, 137, 2, // Opcode: DADDi -/* 1607 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 1620 -/* 1611 */ MCD_OPC_CheckPredicate, 19, 237, 2, // Skip to: 2364 -/* 1615 */ MCD_OPC_Decode, 161, 4, 137, 2, // Opcode: DADDiu -/* 1620 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 1633 -/* 1624 */ MCD_OPC_CheckPredicate, 41, 224, 2, // Skip to: 2364 -/* 1628 */ MCD_OPC_Decode, 172, 7, 217, 1, // Opcode: LDL -/* 1633 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 1646 -/* 1637 */ MCD_OPC_CheckPredicate, 41, 211, 2, // Skip to: 2364 -/* 1641 */ MCD_OPC_Decode, 174, 7, 217, 1, // Opcode: LDR -/* 1646 */ MCD_OPC_FilterValue, 28, 159, 1, // Skip to: 2065 -/* 1650 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1653 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1672 -/* 1657 */ MCD_OPC_CheckPredicate, 50, 191, 2, // Skip to: 2364 -/* 1661 */ MCD_OPC_CheckField, 6, 5, 0, 185, 2, // Skip to: 2364 -/* 1667 */ MCD_OPC_Decode, 206, 4, 224, 1, // Opcode: DMUL -/* 1672 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1691 -/* 1676 */ MCD_OPC_CheckPredicate, 50, 172, 2, // Skip to: 2364 -/* 1680 */ MCD_OPC_CheckField, 6, 15, 0, 166, 2, // Skip to: 2364 -/* 1686 */ MCD_OPC_Decode, 185, 9, 138, 2, // Opcode: MTM0 -/* 1691 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1710 -/* 1695 */ MCD_OPC_CheckPredicate, 50, 153, 2, // Skip to: 2364 -/* 1699 */ MCD_OPC_CheckField, 6, 15, 0, 147, 2, // Skip to: 2364 -/* 1705 */ MCD_OPC_Decode, 188, 9, 138, 2, // Opcode: MTP0 -/* 1710 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1729 -/* 1714 */ MCD_OPC_CheckPredicate, 50, 134, 2, // Skip to: 2364 -/* 1718 */ MCD_OPC_CheckField, 6, 15, 0, 128, 2, // Skip to: 2364 -/* 1724 */ MCD_OPC_Decode, 189, 9, 138, 2, // Opcode: MTP1 -/* 1729 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1748 -/* 1733 */ MCD_OPC_CheckPredicate, 50, 115, 2, // Skip to: 2364 -/* 1737 */ MCD_OPC_CheckField, 6, 15, 0, 109, 2, // Skip to: 2364 -/* 1743 */ MCD_OPC_Decode, 190, 9, 138, 2, // Opcode: MTP2 -/* 1748 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1767 -/* 1752 */ MCD_OPC_CheckPredicate, 50, 96, 2, // Skip to: 2364 -/* 1756 */ MCD_OPC_CheckField, 6, 15, 0, 90, 2, // Skip to: 2364 -/* 1762 */ MCD_OPC_Decode, 186, 9, 138, 2, // Opcode: MTM1 -/* 1767 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1786 -/* 1771 */ MCD_OPC_CheckPredicate, 50, 77, 2, // Skip to: 2364 -/* 1775 */ MCD_OPC_CheckField, 6, 15, 0, 71, 2, // Skip to: 2364 -/* 1781 */ MCD_OPC_Decode, 187, 9, 138, 2, // Opcode: MTM2 -/* 1786 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 1805 -/* 1790 */ MCD_OPC_CheckPredicate, 50, 58, 2, // Skip to: 2364 -/* 1794 */ MCD_OPC_CheckField, 6, 5, 0, 52, 2, // Skip to: 2364 -/* 1800 */ MCD_OPC_Decode, 226, 13, 224, 1, // Opcode: VMULU -/* 1805 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 1824 -/* 1809 */ MCD_OPC_CheckPredicate, 50, 39, 2, // Skip to: 2364 -/* 1813 */ MCD_OPC_CheckField, 6, 5, 0, 33, 2, // Skip to: 2364 -/* 1819 */ MCD_OPC_Decode, 225, 13, 224, 1, // Opcode: VMM0 -/* 1824 */ MCD_OPC_FilterValue, 17, 15, 0, // Skip to: 1843 -/* 1828 */ MCD_OPC_CheckPredicate, 50, 20, 2, // Skip to: 2364 -/* 1832 */ MCD_OPC_CheckField, 6, 5, 0, 14, 2, // Skip to: 2364 -/* 1838 */ MCD_OPC_Decode, 224, 13, 224, 1, // Opcode: V3MULU -/* 1843 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 1862 -/* 1847 */ MCD_OPC_CheckPredicate, 51, 1, 2, // Skip to: 2364 -/* 1851 */ MCD_OPC_CheckField, 6, 5, 0, 251, 1, // Skip to: 2364 -/* 1857 */ MCD_OPC_Decode, 170, 4, 139, 2, // Opcode: DCLZ -/* 1862 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1881 -/* 1866 */ MCD_OPC_CheckPredicate, 51, 238, 1, // Skip to: 2364 -/* 1870 */ MCD_OPC_CheckField, 6, 5, 0, 232, 1, // Skip to: 2364 -/* 1876 */ MCD_OPC_Decode, 168, 4, 139, 2, // Opcode: DCLO -/* 1881 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 1900 -/* 1885 */ MCD_OPC_CheckPredicate, 50, 219, 1, // Skip to: 2364 -/* 1889 */ MCD_OPC_CheckField, 6, 5, 0, 213, 1, // Skip to: 2364 -/* 1895 */ MCD_OPC_Decode, 166, 1, 224, 1, // Opcode: BADDu -/* 1900 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 1919 -/* 1904 */ MCD_OPC_CheckPredicate, 50, 200, 1, // Skip to: 2364 -/* 1908 */ MCD_OPC_CheckField, 6, 5, 0, 194, 1, // Skip to: 2364 -/* 1914 */ MCD_OPC_Decode, 184, 11, 224, 1, // Opcode: SEQ -/* 1919 */ MCD_OPC_FilterValue, 43, 15, 0, // Skip to: 1938 -/* 1923 */ MCD_OPC_CheckPredicate, 50, 181, 1, // Skip to: 2364 -/* 1927 */ MCD_OPC_CheckField, 6, 5, 0, 175, 1, // Skip to: 2364 -/* 1933 */ MCD_OPC_Decode, 252, 11, 224, 1, // Opcode: SNE -/* 1938 */ MCD_OPC_FilterValue, 44, 20, 0, // Skip to: 1962 -/* 1942 */ MCD_OPC_CheckPredicate, 50, 162, 1, // Skip to: 2364 -/* 1946 */ MCD_OPC_CheckField, 16, 5, 0, 156, 1, // Skip to: 2364 -/* 1952 */ MCD_OPC_CheckField, 6, 5, 0, 150, 1, // Skip to: 2364 -/* 1958 */ MCD_OPC_Decode, 163, 10, 62, // Opcode: POP -/* 1962 */ MCD_OPC_FilterValue, 45, 21, 0, // Skip to: 1987 -/* 1966 */ MCD_OPC_CheckPredicate, 50, 138, 1, // Skip to: 2364 -/* 1970 */ MCD_OPC_CheckField, 16, 5, 0, 132, 1, // Skip to: 2364 -/* 1976 */ MCD_OPC_CheckField, 6, 5, 0, 126, 1, // Skip to: 2364 -/* 1982 */ MCD_OPC_Decode, 231, 4, 222, 1, // Opcode: DPOP -/* 1987 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 2000 -/* 1991 */ MCD_OPC_CheckPredicate, 50, 113, 1, // Skip to: 2364 -/* 1995 */ MCD_OPC_Decode, 185, 11, 140, 2, // Opcode: SEQi -/* 2000 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 2013 -/* 2004 */ MCD_OPC_CheckPredicate, 50, 100, 1, // Skip to: 2364 -/* 2008 */ MCD_OPC_Decode, 253, 11, 140, 2, // Opcode: SNEi -/* 2013 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2026 -/* 2017 */ MCD_OPC_CheckPredicate, 50, 87, 1, // Skip to: 2364 -/* 2021 */ MCD_OPC_Decode, 241, 2, 141, 2, // Opcode: CINS -/* 2026 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 2039 -/* 2030 */ MCD_OPC_CheckPredicate, 50, 74, 1, // Skip to: 2364 -/* 2034 */ MCD_OPC_Decode, 242, 2, 141, 2, // Opcode: CINS32 -/* 2039 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2052 -/* 2043 */ MCD_OPC_CheckPredicate, 50, 61, 1, // Skip to: 2364 -/* 2047 */ MCD_OPC_Decode, 158, 5, 141, 2, // Opcode: EXTS -/* 2052 */ MCD_OPC_FilterValue, 59, 52, 1, // Skip to: 2364 -/* 2056 */ MCD_OPC_CheckPredicate, 50, 48, 1, // Skip to: 2364 -/* 2060 */ MCD_OPC_Decode, 159, 5, 141, 2, // Opcode: EXTS32 -/* 2065 */ MCD_OPC_FilterValue, 31, 126, 0, // Skip to: 2195 -/* 2069 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2072 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2085 -/* 2076 */ MCD_OPC_CheckPredicate, 6, 28, 1, // Skip to: 2364 -/* 2080 */ MCD_OPC_Decode, 177, 4, 142, 2, // Opcode: DEXTM -/* 2085 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2098 -/* 2089 */ MCD_OPC_CheckPredicate, 6, 15, 1, // Skip to: 2364 -/* 2093 */ MCD_OPC_Decode, 178, 4, 142, 2, // Opcode: DEXTU -/* 2098 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2111 -/* 2102 */ MCD_OPC_CheckPredicate, 6, 2, 1, // Skip to: 2364 -/* 2106 */ MCD_OPC_Decode, 176, 4, 142, 2, // Opcode: DEXT -/* 2111 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 2124 -/* 2115 */ MCD_OPC_CheckPredicate, 6, 245, 0, // Skip to: 2364 -/* 2119 */ MCD_OPC_Decode, 181, 4, 143, 2, // Opcode: DINSM -/* 2124 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 2137 -/* 2128 */ MCD_OPC_CheckPredicate, 6, 232, 0, // Skip to: 2364 -/* 2132 */ MCD_OPC_Decode, 182, 4, 143, 2, // Opcode: DINSU -/* 2137 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 2150 -/* 2141 */ MCD_OPC_CheckPredicate, 6, 219, 0, // Skip to: 2364 -/* 2145 */ MCD_OPC_Decode, 180, 4, 143, 2, // Opcode: DINS -/* 2150 */ MCD_OPC_FilterValue, 36, 210, 0, // Skip to: 2364 -/* 2154 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 2157 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2176 -/* 2161 */ MCD_OPC_CheckPredicate, 40, 199, 0, // Skip to: 2364 -/* 2165 */ MCD_OPC_CheckField, 21, 5, 0, 193, 0, // Skip to: 2364 -/* 2171 */ MCD_OPC_Decode, 249, 4, 243, 1, // Opcode: DSBH -/* 2176 */ MCD_OPC_FilterValue, 5, 184, 0, // Skip to: 2364 -/* 2180 */ MCD_OPC_CheckPredicate, 40, 180, 0, // Skip to: 2364 -/* 2184 */ MCD_OPC_CheckField, 21, 5, 0, 174, 0, // Skip to: 2364 -/* 2190 */ MCD_OPC_Decode, 251, 4, 243, 1, // Opcode: DSHD -/* 2195 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 2208 -/* 2199 */ MCD_OPC_CheckPredicate, 19, 161, 0, // Skip to: 2364 -/* 2203 */ MCD_OPC_Decode, 241, 7, 217, 1, // Opcode: LWu -/* 2208 */ MCD_OPC_FilterValue, 44, 9, 0, // Skip to: 2221 -/* 2212 */ MCD_OPC_CheckPredicate, 41, 148, 0, // Skip to: 2364 -/* 2216 */ MCD_OPC_Decode, 164, 11, 217, 1, // Opcode: SDL -/* 2221 */ MCD_OPC_FilterValue, 45, 9, 0, // Skip to: 2234 -/* 2225 */ MCD_OPC_CheckPredicate, 41, 135, 0, // Skip to: 2364 -/* 2229 */ MCD_OPC_Decode, 165, 11, 217, 1, // Opcode: SDR -/* 2234 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2247 -/* 2238 */ MCD_OPC_CheckPredicate, 50, 122, 0, // Skip to: 2364 -/* 2242 */ MCD_OPC_Decode, 171, 1, 144, 2, // Opcode: BBIT0 -/* 2247 */ MCD_OPC_FilterValue, 52, 9, 0, // Skip to: 2260 -/* 2251 */ MCD_OPC_CheckPredicate, 41, 109, 0, // Skip to: 2364 -/* 2255 */ MCD_OPC_Decode, 194, 7, 217, 1, // Opcode: LLD -/* 2260 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 2273 -/* 2264 */ MCD_OPC_CheckPredicate, 52, 96, 0, // Skip to: 2364 -/* 2268 */ MCD_OPC_Decode, 163, 7, 219, 1, // Opcode: LDC164 -/* 2273 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 2286 -/* 2277 */ MCD_OPC_CheckPredicate, 50, 83, 0, // Skip to: 2364 -/* 2281 */ MCD_OPC_Decode, 172, 1, 144, 2, // Opcode: BBIT032 -/* 2286 */ MCD_OPC_FilterValue, 55, 9, 0, // Skip to: 2299 -/* 2290 */ MCD_OPC_CheckPredicate, 19, 70, 0, // Skip to: 2364 -/* 2294 */ MCD_OPC_Decode, 161, 7, 217, 1, // Opcode: LD -/* 2299 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2312 -/* 2303 */ MCD_OPC_CheckPredicate, 50, 57, 0, // Skip to: 2364 -/* 2307 */ MCD_OPC_Decode, 173, 1, 144, 2, // Opcode: BBIT1 -/* 2312 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 2325 -/* 2316 */ MCD_OPC_CheckPredicate, 41, 44, 0, // Skip to: 2364 -/* 2320 */ MCD_OPC_Decode, 147, 11, 217, 1, // Opcode: SCD -/* 2325 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 2338 -/* 2329 */ MCD_OPC_CheckPredicate, 52, 31, 0, // Skip to: 2364 -/* 2333 */ MCD_OPC_Decode, 157, 11, 219, 1, // Opcode: SDC164 -/* 2338 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 2351 -/* 2342 */ MCD_OPC_CheckPredicate, 50, 18, 0, // Skip to: 2364 -/* 2346 */ MCD_OPC_Decode, 174, 1, 144, 2, // Opcode: BBIT132 -/* 2351 */ MCD_OPC_FilterValue, 63, 9, 0, // Skip to: 2364 -/* 2355 */ MCD_OPC_CheckPredicate, 19, 5, 0, // Skip to: 2364 -/* 2359 */ MCD_OPC_Decode, 151, 11, 217, 1, // Opcode: SD -/* 2364 */ MCD_OPC_Fail, - 0 -}; - -static bool getbool(uint64_t b) -{ - return b != 0; -} + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 236, + 1, + 0, // Skip to: 500 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 32 + /* 16 */ MCD_OPC_CheckPredicate, + 88, + 214, + 4, + 0, // Skip to: 1259 + /* 21 */ MCD_OPC_CheckField, + 6, + 15, + 16, + 207, + 4, + 0, // Skip to: 1259 + /* 28 */ MCD_OPC_Decode, + 141, + 14, + 13, // Opcode: JR_HB64 + /* 32 */ MCD_OPC_FilterValue, + 9, + 45, + 0, + 0, // Skip to: 82 + /* 37 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 40 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 61 + /* 45 */ MCD_OPC_CheckPredicate, + 89, + 185, + 4, + 0, // Skip to: 1259 + /* 50 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 178, + 4, + 0, // Skip to: 1259 + /* 57 */ MCD_OPC_Decode, + 242, + 13, + 15, // Opcode: JALR64 + /* 61 */ MCD_OPC_FilterValue, + 16, + 169, + 4, + 0, // Skip to: 1259 + /* 66 */ MCD_OPC_CheckPredicate, + 90, + 164, + 4, + 0, // Skip to: 1259 + /* 71 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 157, + 4, + 0, // Skip to: 1259 + /* 78 */ MCD_OPC_Decode, + 249, + 13, + 15, // Opcode: JALR_HB64 + /* 82 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 104 + /* 87 */ MCD_OPC_CheckPredicate, + 91, + 143, + 4, + 0, // Skip to: 1259 + /* 92 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 136, + 4, + 0, // Skip to: 1259 + /* 99 */ MCD_OPC_Decode, + 207, + 11, + 238, + 2, // Opcode: DSLLV + /* 104 */ MCD_OPC_FilterValue, + 22, + 33, + 0, + 0, // Skip to: 142 + /* 109 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 112 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 127 + /* 117 */ MCD_OPC_CheckPredicate, + 91, + 113, + 4, + 0, // Skip to: 1259 + /* 122 */ MCD_OPC_Decode, + 213, + 11, + 238, + 2, // Opcode: DSRLV + /* 127 */ MCD_OPC_FilterValue, + 1, + 103, + 4, + 0, // Skip to: 1259 + /* 132 */ MCD_OPC_CheckPredicate, + 90, + 98, + 4, + 0, // Skip to: 1259 + /* 137 */ MCD_OPC_Decode, + 200, + 11, + 238, + 2, // Opcode: DROTRV + /* 142 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 164 + /* 147 */ MCD_OPC_CheckPredicate, + 91, + 83, + 4, + 0, // Skip to: 1259 + /* 152 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 76, + 4, + 0, // Skip to: 1259 + /* 159 */ MCD_OPC_Decode, + 210, + 11, + 238, + 2, // Opcode: DSRAV + /* 164 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 186 + /* 169 */ MCD_OPC_CheckPredicate, + 92, + 61, + 4, + 0, // Skip to: 1259 + /* 174 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 54, + 4, + 0, // Skip to: 1259 + /* 181 */ MCD_OPC_Decode, + 143, + 11, + 239, + 2, // Opcode: DMULT + /* 186 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 208 + /* 191 */ MCD_OPC_CheckPredicate, + 92, + 39, + 4, + 0, // Skip to: 1259 + /* 196 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 32, + 4, + 0, // Skip to: 1259 + /* 203 */ MCD_OPC_Decode, + 144, + 11, + 239, + 2, // Opcode: DMULTu + /* 208 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 230 + /* 213 */ MCD_OPC_CheckPredicate, + 92, + 17, + 4, + 0, // Skip to: 1259 + /* 218 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 10, + 4, + 0, // Skip to: 1259 + /* 225 */ MCD_OPC_Decode, + 202, + 11, + 239, + 2, // Opcode: DSDIV + /* 230 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 252 + /* 235 */ MCD_OPC_CheckPredicate, + 92, + 251, + 3, + 0, // Skip to: 1259 + /* 240 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 244, + 3, + 0, // Skip to: 1259 + /* 247 */ MCD_OPC_Decode, + 216, + 11, + 239, + 2, // Opcode: DUDIV + /* 252 */ MCD_OPC_FilterValue, + 44, + 16, + 0, + 0, // Skip to: 273 + /* 257 */ MCD_OPC_CheckPredicate, + 91, + 229, + 3, + 0, // Skip to: 1259 + /* 262 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 222, + 3, + 0, // Skip to: 1259 + /* 269 */ MCD_OPC_Decode, + 213, + 10, + 12, // Opcode: DADD + /* 273 */ MCD_OPC_FilterValue, + 45, + 16, + 0, + 0, // Skip to: 294 + /* 278 */ MCD_OPC_CheckPredicate, + 91, + 208, + 3, + 0, // Skip to: 1259 + /* 283 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 201, + 3, + 0, // Skip to: 1259 + /* 290 */ MCD_OPC_Decode, + 216, + 10, + 12, // Opcode: DADDu + /* 294 */ MCD_OPC_FilterValue, + 46, + 16, + 0, + 0, // Skip to: 315 + /* 299 */ MCD_OPC_CheckPredicate, + 91, + 187, + 3, + 0, // Skip to: 1259 + /* 304 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 180, + 3, + 0, // Skip to: 1259 + /* 311 */ MCD_OPC_Decode, + 214, + 11, + 12, // Opcode: DSUB + /* 315 */ MCD_OPC_FilterValue, + 47, + 16, + 0, + 0, // Skip to: 336 + /* 320 */ MCD_OPC_CheckPredicate, + 91, + 166, + 3, + 0, // Skip to: 1259 + /* 325 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 159, + 3, + 0, // Skip to: 1259 + /* 332 */ MCD_OPC_Decode, + 215, + 11, + 12, // Opcode: DSUBu + /* 336 */ MCD_OPC_FilterValue, + 56, + 17, + 0, + 0, // Skip to: 358 + /* 341 */ MCD_OPC_CheckPredicate, + 91, + 145, + 3, + 0, // Skip to: 1259 + /* 346 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 138, + 3, + 0, // Skip to: 1259 + /* 353 */ MCD_OPC_Decode, + 204, + 11, + 240, + 2, // Opcode: DSLL + /* 358 */ MCD_OPC_FilterValue, + 58, + 33, + 0, + 0, // Skip to: 396 + /* 363 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 366 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 381 + /* 371 */ MCD_OPC_CheckPredicate, + 91, + 115, + 3, + 0, // Skip to: 1259 + /* 376 */ MCD_OPC_Decode, + 211, + 11, + 240, + 2, // Opcode: DSRL + /* 381 */ MCD_OPC_FilterValue, + 1, + 105, + 3, + 0, // Skip to: 1259 + /* 386 */ MCD_OPC_CheckPredicate, + 90, + 100, + 3, + 0, // Skip to: 1259 + /* 391 */ MCD_OPC_Decode, + 198, + 11, + 240, + 2, // Opcode: DROTR + /* 396 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 418 + /* 401 */ MCD_OPC_CheckPredicate, + 91, + 85, + 3, + 0, // Skip to: 1259 + /* 406 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 78, + 3, + 0, // Skip to: 1259 + /* 413 */ MCD_OPC_Decode, + 208, + 11, + 240, + 2, // Opcode: DSRA + /* 418 */ MCD_OPC_FilterValue, + 60, + 17, + 0, + 0, // Skip to: 440 + /* 423 */ MCD_OPC_CheckPredicate, + 91, + 63, + 3, + 0, // Skip to: 1259 + /* 428 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 56, + 3, + 0, // Skip to: 1259 + /* 435 */ MCD_OPC_Decode, + 205, + 11, + 240, + 2, // Opcode: DSLL32 + /* 440 */ MCD_OPC_FilterValue, + 62, + 33, + 0, + 0, // Skip to: 478 + /* 445 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 448 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 463 + /* 453 */ MCD_OPC_CheckPredicate, + 91, + 33, + 3, + 0, // Skip to: 1259 + /* 458 */ MCD_OPC_Decode, + 212, + 11, + 240, + 2, // Opcode: DSRL32 + /* 463 */ MCD_OPC_FilterValue, + 1, + 23, + 3, + 0, // Skip to: 1259 + /* 468 */ MCD_OPC_CheckPredicate, + 90, + 18, + 3, + 0, // Skip to: 1259 + /* 473 */ MCD_OPC_Decode, + 199, + 11, + 240, + 2, // Opcode: DROTR32 + /* 478 */ MCD_OPC_FilterValue, + 63, + 8, + 3, + 0, // Skip to: 1259 + /* 483 */ MCD_OPC_CheckPredicate, + 91, + 3, + 3, + 0, // Skip to: 1259 + /* 488 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 252, + 2, + 0, // Skip to: 1259 + /* 495 */ MCD_OPC_Decode, + 209, + 11, + 240, + 2, // Opcode: DSRA32 + /* 500 */ MCD_OPC_FilterValue, + 16, + 85, + 0, + 0, // Skip to: 590 + /* 505 */ MCD_OPC_ExtractField, + 3, + 8, // Inst{10-3} ... + /* 508 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 546 + /* 513 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 516 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 531 + /* 521 */ MCD_OPC_CheckPredicate, + 93, + 221, + 2, + 0, // Skip to: 1259 + /* 526 */ MCD_OPC_Decode, + 255, + 10, + 241, + 2, // Opcode: DMFC0 + /* 531 */ MCD_OPC_FilterValue, + 5, + 211, + 2, + 0, // Skip to: 1259 + /* 536 */ MCD_OPC_CheckPredicate, + 93, + 206, + 2, + 0, // Skip to: 1259 + /* 541 */ MCD_OPC_Decode, + 135, + 11, + 242, + 2, // Opcode: DMTC0 + /* 546 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 568 + /* 551 */ MCD_OPC_CheckPredicate, + 94, + 191, + 2, + 0, // Skip to: 1259 + /* 556 */ MCD_OPC_CheckField, + 21, + 5, + 3, + 184, + 2, + 0, // Skip to: 1259 + /* 563 */ MCD_OPC_Decode, + 131, + 11, + 241, + 2, // Opcode: DMFGC0 + /* 568 */ MCD_OPC_FilterValue, + 96, + 174, + 2, + 0, // Skip to: 1259 + /* 573 */ MCD_OPC_CheckPredicate, + 94, + 169, + 2, + 0, // Skip to: 1259 + /* 578 */ MCD_OPC_CheckField, + 21, + 5, + 3, + 162, + 2, + 0, // Skip to: 1259 + /* 585 */ MCD_OPC_Decode, + 139, + 11, + 242, + 2, // Opcode: DMTGC0 + /* 590 */ MCD_OPC_FilterValue, + 18, + 47, + 0, + 0, // Skip to: 642 + /* 595 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 598 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 620 + /* 603 */ MCD_OPC_CheckPredicate, + 93, + 139, + 2, + 0, // Skip to: 1259 + /* 608 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 132, + 2, + 0, // Skip to: 1259 + /* 615 */ MCD_OPC_Decode, + 129, + 11, + 243, + 2, // Opcode: DMFC2 + /* 620 */ MCD_OPC_FilterValue, + 5, + 122, + 2, + 0, // Skip to: 1259 + /* 625 */ MCD_OPC_CheckPredicate, + 93, + 117, + 2, + 0, // Skip to: 1259 + /* 630 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 110, + 2, + 0, // Skip to: 1259 + /* 637 */ MCD_OPC_Decode, + 137, + 11, + 244, + 2, // Opcode: DMTC2 + /* 642 */ MCD_OPC_FilterValue, + 21, + 3, + 1, + 0, // Skip to: 906 + /* 647 */ MCD_OPC_ExtractField, + 0, + 13, // Inst{12-0} ... + /* 650 */ MCD_OPC_FilterValue, + 188, + 8, + 10, + 0, + 0, // Skip to: 666 + /* 656 */ MCD_OPC_CheckPredicate, + 15, + 86, + 2, + 0, // Skip to: 1259 + /* 661 */ MCD_OPC_Decode, + 251, + 9, + 245, + 2, // Opcode: C_F_D64_MM + /* 666 */ MCD_OPC_FilterValue, + 252, + 8, + 10, + 0, + 0, // Skip to: 682 + /* 672 */ MCD_OPC_CheckPredicate, + 15, + 70, + 2, + 0, // Skip to: 1259 + /* 677 */ MCD_OPC_Decode, + 207, + 10, + 245, + 2, // Opcode: C_UN_D64_MM + /* 682 */ MCD_OPC_FilterValue, + 188, + 9, + 10, + 0, + 0, // Skip to: 698 + /* 688 */ MCD_OPC_CheckPredicate, + 15, + 54, + 2, + 0, // Skip to: 1259 + /* 693 */ MCD_OPC_Decode, + 245, + 9, + 245, + 2, // Opcode: C_EQ_D64_MM + /* 698 */ MCD_OPC_FilterValue, + 252, + 9, + 10, + 0, + 0, // Skip to: 714 + /* 704 */ MCD_OPC_CheckPredicate, + 15, + 38, + 2, + 0, // Skip to: 1259 + /* 709 */ MCD_OPC_Decode, + 189, + 10, + 245, + 2, // Opcode: C_UEQ_D64_MM + /* 714 */ MCD_OPC_FilterValue, + 188, + 10, + 10, + 0, + 0, // Skip to: 730 + /* 720 */ MCD_OPC_CheckPredicate, + 15, + 22, + 2, + 0, // Skip to: 1259 + /* 725 */ MCD_OPC_Decode, + 171, + 10, + 245, + 2, // Opcode: C_OLT_D64_MM + /* 730 */ MCD_OPC_FilterValue, + 252, + 10, + 10, + 0, + 0, // Skip to: 746 + /* 736 */ MCD_OPC_CheckPredicate, + 15, + 6, + 2, + 0, // Skip to: 1259 + /* 741 */ MCD_OPC_Decode, + 201, + 10, + 245, + 2, // Opcode: C_ULT_D64_MM + /* 746 */ MCD_OPC_FilterValue, + 188, + 11, + 10, + 0, + 0, // Skip to: 762 + /* 752 */ MCD_OPC_CheckPredicate, + 15, + 246, + 1, + 0, // Skip to: 1259 + /* 757 */ MCD_OPC_Decode, + 165, + 10, + 245, + 2, // Opcode: C_OLE_D64_MM + /* 762 */ MCD_OPC_FilterValue, + 252, + 11, + 10, + 0, + 0, // Skip to: 778 + /* 768 */ MCD_OPC_CheckPredicate, + 15, + 230, + 1, + 0, // Skip to: 1259 + /* 773 */ MCD_OPC_Decode, + 195, + 10, + 245, + 2, // Opcode: C_ULE_D64_MM + /* 778 */ MCD_OPC_FilterValue, + 188, + 12, + 10, + 0, + 0, // Skip to: 794 + /* 784 */ MCD_OPC_CheckPredicate, + 15, + 214, + 1, + 0, // Skip to: 1259 + /* 789 */ MCD_OPC_Decode, + 183, + 10, + 245, + 2, // Opcode: C_SF_D64_MM + /* 794 */ MCD_OPC_FilterValue, + 252, + 12, + 10, + 0, + 0, // Skip to: 810 + /* 800 */ MCD_OPC_CheckPredicate, + 15, + 198, + 1, + 0, // Skip to: 1259 + /* 805 */ MCD_OPC_Decode, + 147, + 10, + 245, + 2, // Opcode: C_NGLE_D64_MM + /* 810 */ MCD_OPC_FilterValue, + 188, + 13, + 10, + 0, + 0, // Skip to: 826 + /* 816 */ MCD_OPC_CheckPredicate, + 15, + 182, + 1, + 0, // Skip to: 1259 + /* 821 */ MCD_OPC_Decode, + 177, + 10, + 245, + 2, // Opcode: C_SEQ_D64_MM + /* 826 */ MCD_OPC_FilterValue, + 252, + 13, + 10, + 0, + 0, // Skip to: 842 + /* 832 */ MCD_OPC_CheckPredicate, + 15, + 166, + 1, + 0, // Skip to: 1259 + /* 837 */ MCD_OPC_Decode, + 153, + 10, + 245, + 2, // Opcode: C_NGL_D64_MM + /* 842 */ MCD_OPC_FilterValue, + 188, + 14, + 10, + 0, + 0, // Skip to: 858 + /* 848 */ MCD_OPC_CheckPredicate, + 15, + 150, + 1, + 0, // Skip to: 1259 + /* 853 */ MCD_OPC_Decode, + 135, + 10, + 245, + 2, // Opcode: C_LT_D64_MM + /* 858 */ MCD_OPC_FilterValue, + 252, + 14, + 10, + 0, + 0, // Skip to: 874 + /* 864 */ MCD_OPC_CheckPredicate, + 15, + 134, + 1, + 0, // Skip to: 1259 + /* 869 */ MCD_OPC_Decode, + 141, + 10, + 245, + 2, // Opcode: C_NGE_D64_MM + /* 874 */ MCD_OPC_FilterValue, + 188, + 15, + 10, + 0, + 0, // Skip to: 890 + /* 880 */ MCD_OPC_CheckPredicate, + 15, + 118, + 1, + 0, // Skip to: 1259 + /* 885 */ MCD_OPC_Decode, + 129, + 10, + 245, + 2, // Opcode: C_LE_D64_MM + /* 890 */ MCD_OPC_FilterValue, + 252, + 15, + 107, + 1, + 0, // Skip to: 1259 + /* 896 */ MCD_OPC_CheckPredicate, + 15, + 102, + 1, + 0, // Skip to: 1259 + /* 901 */ MCD_OPC_Decode, + 159, + 10, + 245, + 2, // Opcode: C_NGT_D64_MM + /* 906 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 921 + /* 911 */ MCD_OPC_CheckPredicate, + 95, + 87, + 1, + 0, // Skip to: 1259 + /* 916 */ MCD_OPC_Decode, + 214, + 10, + 246, + 2, // Opcode: DADDi + /* 921 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 936 + /* 926 */ MCD_OPC_CheckPredicate, + 91, + 72, + 1, + 0, // Skip to: 1259 + /* 931 */ MCD_OPC_Decode, + 215, + 10, + 246, + 2, // Opcode: DADDiu + /* 936 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 951 + /* 941 */ MCD_OPC_CheckPredicate, + 95, + 57, + 1, + 0, // Skip to: 1259 + /* 946 */ MCD_OPC_Decode, + 180, + 14, + 130, + 1, // Opcode: LDL + /* 951 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 966 + /* 956 */ MCD_OPC_CheckPredicate, + 95, + 42, + 1, + 0, // Skip to: 1259 + /* 961 */ MCD_OPC_Decode, + 182, + 14, + 130, + 1, // Opcode: LDR + /* 966 */ MCD_OPC_FilterValue, + 28, + 33, + 0, + 0, // Skip to: 1004 + /* 971 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 974 */ MCD_OPC_FilterValue, + 36, + 10, + 0, + 0, // Skip to: 989 + /* 979 */ MCD_OPC_CheckPredicate, + 96, + 19, + 1, + 0, // Skip to: 1259 + /* 984 */ MCD_OPC_Decode, + 224, + 10, + 247, + 2, // Opcode: DCLZ + /* 989 */ MCD_OPC_FilterValue, + 37, + 9, + 1, + 0, // Skip to: 1259 + /* 994 */ MCD_OPC_CheckPredicate, + 96, + 4, + 1, + 0, // Skip to: 1259 + /* 999 */ MCD_OPC_Decode, + 222, + 10, + 247, + 2, // Opcode: DCLO + /* 1004 */ MCD_OPC_FilterValue, + 31, + 145, + 0, + 0, // Skip to: 1154 + /* 1009 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1012 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1027 + /* 1017 */ MCD_OPC_CheckPredicate, + 90, + 237, + 0, + 0, // Skip to: 1259 + /* 1022 */ MCD_OPC_Decode, + 233, + 10, + 248, + 2, // Opcode: DEXTM + /* 1027 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1042 + /* 1032 */ MCD_OPC_CheckPredicate, + 90, + 222, + 0, + 0, // Skip to: 1259 + /* 1037 */ MCD_OPC_Decode, + 234, + 10, + 248, + 2, // Opcode: DEXTU + /* 1042 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1057 + /* 1047 */ MCD_OPC_CheckPredicate, + 90, + 207, + 0, + 0, // Skip to: 1259 + /* 1052 */ MCD_OPC_Decode, + 231, + 10, + 248, + 2, // Opcode: DEXT + /* 1057 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1072 + /* 1062 */ MCD_OPC_CheckPredicate, + 90, + 192, + 0, + 0, // Skip to: 1259 + /* 1067 */ MCD_OPC_Decode, + 237, + 10, + 249, + 2, // Opcode: DINSM + /* 1072 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 1087 + /* 1077 */ MCD_OPC_CheckPredicate, + 90, + 177, + 0, + 0, // Skip to: 1259 + /* 1082 */ MCD_OPC_Decode, + 238, + 10, + 249, + 2, // Opcode: DINSU + /* 1087 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1102 + /* 1092 */ MCD_OPC_CheckPredicate, + 90, + 162, + 0, + 0, // Skip to: 1259 + /* 1097 */ MCD_OPC_Decode, + 236, + 10, + 249, + 2, // Opcode: DINS + /* 1102 */ MCD_OPC_FilterValue, + 36, + 152, + 0, + 0, // Skip to: 1259 + /* 1107 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1110 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 1132 + /* 1115 */ MCD_OPC_CheckPredicate, + 90, + 139, + 0, + 0, // Skip to: 1259 + /* 1120 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 132, + 0, + 0, // Skip to: 1259 + /* 1127 */ MCD_OPC_Decode, + 201, + 11, + 230, + 2, // Opcode: DSBH + /* 1132 */ MCD_OPC_FilterValue, + 5, + 122, + 0, + 0, // Skip to: 1259 + /* 1137 */ MCD_OPC_CheckPredicate, + 90, + 117, + 0, + 0, // Skip to: 1259 + /* 1142 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 110, + 0, + 0, // Skip to: 1259 + /* 1149 */ MCD_OPC_Decode, + 203, + 11, + 230, + 2, // Opcode: DSHD + /* 1154 */ MCD_OPC_FilterValue, + 39, + 10, + 0, + 0, // Skip to: 1169 + /* 1159 */ MCD_OPC_CheckPredicate, + 91, + 95, + 0, + 0, // Skip to: 1259 + /* 1164 */ MCD_OPC_Decode, + 139, + 15, + 130, + 1, // Opcode: LWu + /* 1169 */ MCD_OPC_FilterValue, + 44, + 10, + 0, + 0, // Skip to: 1184 + /* 1174 */ MCD_OPC_CheckPredicate, + 95, + 80, + 0, + 0, // Skip to: 1259 + /* 1179 */ MCD_OPC_Decode, + 141, + 19, + 130, + 1, // Opcode: SDL + /* 1184 */ MCD_OPC_FilterValue, + 45, + 10, + 0, + 0, // Skip to: 1199 + /* 1189 */ MCD_OPC_CheckPredicate, + 95, + 65, + 0, + 0, // Skip to: 1259 + /* 1194 */ MCD_OPC_Decode, + 142, + 19, + 130, + 1, // Opcode: SDR + /* 1199 */ MCD_OPC_FilterValue, + 52, + 10, + 0, + 0, // Skip to: 1214 + /* 1204 */ MCD_OPC_CheckPredicate, + 92, + 50, + 0, + 0, // Skip to: 1259 + /* 1209 */ MCD_OPC_Decode, + 210, + 14, + 130, + 1, // Opcode: LLD + /* 1214 */ MCD_OPC_FilterValue, + 55, + 10, + 0, + 0, // Skip to: 1229 + /* 1219 */ MCD_OPC_CheckPredicate, + 91, + 35, + 0, + 0, // Skip to: 1259 + /* 1224 */ MCD_OPC_Decode, + 167, + 14, + 130, + 1, // Opcode: LD + /* 1229 */ MCD_OPC_FilterValue, + 60, + 10, + 0, + 0, // Skip to: 1244 + /* 1234 */ MCD_OPC_CheckPredicate, + 95, + 20, + 0, + 0, // Skip to: 1259 + /* 1239 */ MCD_OPC_Decode, + 245, + 18, + 130, + 1, // Opcode: SCD + /* 1244 */ MCD_OPC_FilterValue, + 63, + 10, + 0, + 0, // Skip to: 1259 + /* 1249 */ MCD_OPC_CheckPredicate, + 91, + 5, + 0, + 0, // Skip to: 1259 + /* 1254 */ MCD_OPC_Decode, + 252, + 18, + 130, + 1, // Opcode: SD + /* 1259 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMipsDSP32[] = { + /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 18 + /* 8 */ MCD_OPC_CheckPredicate, 97, 20, 0, 0, // Skip to: 33 + /* 13 */ MCD_OPC_Decode, 236, 14, 130, 1, // Opcode: LWDSP + /* 18 */ MCD_OPC_FilterValue, 43, 10, 0, 0, // Skip to: 33 + /* 23 */ MCD_OPC_CheckPredicate, 97, 5, 0, 0, // Skip to: 33 + /* 28 */ MCD_OPC_Decode, 143, 21, 130, 1, // Opcode: SWDSP + /* 33 */ MCD_OPC_Fail, 0}; + +static const uint8_t DecoderTableMipsFP6432[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 17, + 249, + 5, + 0, // Skip to: 1537 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 121, + 0, + 0, // Skip to: 137 + /* 16 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 41 + /* 24 */ MCD_OPC_CheckPredicate, + 98, + 158, + 6, + 0, // Skip to: 1723 + /* 29 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 151, + 6, + 0, // Skip to: 1723 + /* 36 */ MCD_OPC_Decode, + 215, + 15, + 250, + 2, // Opcode: MFC1_D64 + /* 41 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 63 + /* 46 */ MCD_OPC_CheckPredicate, + 99, + 136, + 6, + 0, // Skip to: 1723 + /* 51 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 129, + 6, + 0, // Skip to: 1723 + /* 58 */ MCD_OPC_Decode, + 225, + 15, + 250, + 2, // Opcode: MFHC1_D64 + /* 63 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 85 + /* 68 */ MCD_OPC_CheckPredicate, + 98, + 114, + 6, + 0, // Skip to: 1723 + /* 73 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 107, + 6, + 0, // Skip to: 1723 + /* 80 */ MCD_OPC_Decode, + 230, + 16, + 251, + 2, // Opcode: MTC1_D64 + /* 85 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 107 + /* 90 */ MCD_OPC_CheckPredicate, + 99, + 92, + 6, + 0, // Skip to: 1723 + /* 95 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 85, + 6, + 0, // Skip to: 1723 + /* 102 */ MCD_OPC_Decode, + 241, + 16, + 252, + 2, // Opcode: MTHC1_D64 + /* 107 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 122 + /* 112 */ MCD_OPC_CheckPredicate, + 98, + 70, + 6, + 0, // Skip to: 1723 + /* 117 */ MCD_OPC_Decode, + 147, + 12, + 219, + 2, // Opcode: FADD_D64 + /* 122 */ MCD_OPC_FilterValue, + 22, + 60, + 6, + 0, // Skip to: 1723 + /* 127 */ MCD_OPC_CheckPredicate, + 100, + 55, + 6, + 0, // Skip to: 1723 + /* 132 */ MCD_OPC_Decode, + 149, + 12, + 219, + 2, // Opcode: FADD_PS64 + /* 137 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 175 + /* 142 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 145 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 160 + /* 150 */ MCD_OPC_CheckPredicate, + 98, + 32, + 6, + 0, // Skip to: 1723 + /* 155 */ MCD_OPC_Decode, + 164, + 13, + 219, + 2, // Opcode: FSUB_D64 + /* 160 */ MCD_OPC_FilterValue, + 22, + 22, + 6, + 0, // Skip to: 1723 + /* 165 */ MCD_OPC_CheckPredicate, + 100, + 17, + 6, + 0, // Skip to: 1723 + /* 170 */ MCD_OPC_Decode, + 166, + 13, + 219, + 2, // Opcode: FSUB_PS64 + /* 175 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 213 + /* 180 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 183 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 198 + /* 188 */ MCD_OPC_CheckPredicate, + 98, + 250, + 5, + 0, // Skip to: 1723 + /* 193 */ MCD_OPC_Decode, + 248, + 12, + 219, + 2, // Opcode: FMUL_D64 + /* 198 */ MCD_OPC_FilterValue, + 22, + 240, + 5, + 0, // Skip to: 1723 + /* 203 */ MCD_OPC_CheckPredicate, + 100, + 235, + 5, + 0, // Skip to: 1723 + /* 208 */ MCD_OPC_Decode, + 250, + 12, + 219, + 2, // Opcode: FMUL_PS64 + /* 213 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 235 + /* 218 */ MCD_OPC_CheckPredicate, + 98, + 220, + 5, + 0, // Skip to: 1723 + /* 223 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 213, + 5, + 0, // Skip to: 1723 + /* 230 */ MCD_OPC_Decode, + 186, + 12, + 219, + 2, // Opcode: FDIV_D64 + /* 235 */ MCD_OPC_FilterValue, + 4, + 18, + 0, + 0, // Skip to: 258 + /* 240 */ MCD_OPC_CheckPredicate, + 101, + 198, + 5, + 0, // Skip to: 1723 + /* 245 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 190, + 5, + 0, // Skip to: 1723 + /* 253 */ MCD_OPC_Decode, + 156, + 13, + 219, + 1, // Opcode: FSQRT_D64 + /* 258 */ MCD_OPC_FilterValue, + 5, + 18, + 0, + 0, // Skip to: 281 + /* 263 */ MCD_OPC_CheckPredicate, + 98, + 175, + 5, + 0, // Skip to: 1723 + /* 268 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 167, + 5, + 0, // Skip to: 1723 + /* 276 */ MCD_OPC_Decode, + 140, + 12, + 219, + 1, // Opcode: FABS_D64 + /* 281 */ MCD_OPC_FilterValue, + 6, + 18, + 0, + 0, // Skip to: 304 + /* 286 */ MCD_OPC_CheckPredicate, + 98, + 152, + 5, + 0, // Skip to: 1723 + /* 291 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 144, + 5, + 0, // Skip to: 1723 + /* 299 */ MCD_OPC_Decode, + 237, + 12, + 219, + 1, // Opcode: FMOV_D64 + /* 304 */ MCD_OPC_FilterValue, + 7, + 18, + 0, + 0, // Skip to: 327 + /* 309 */ MCD_OPC_CheckPredicate, + 98, + 129, + 5, + 0, // Skip to: 1723 + /* 314 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 121, + 5, + 0, // Skip to: 1723 + /* 322 */ MCD_OPC_Decode, + 129, + 13, + 219, + 1, // Opcode: FNEG_D64 + /* 327 */ MCD_OPC_FilterValue, + 8, + 35, + 0, + 0, // Skip to: 367 + /* 332 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 335 */ MCD_OPC_FilterValue, + 128, + 4, + 10, + 0, + 0, // Skip to: 351 + /* 341 */ MCD_OPC_CheckPredicate, + 101, + 97, + 5, + 0, // Skip to: 1723 + /* 346 */ MCD_OPC_Decode, + 207, + 18, + 212, + 1, // Opcode: ROUND_L_S + /* 351 */ MCD_OPC_FilterValue, + 160, + 4, + 86, + 5, + 0, // Skip to: 1723 + /* 357 */ MCD_OPC_CheckPredicate, + 102, + 81, + 5, + 0, // Skip to: 1723 + /* 362 */ MCD_OPC_Decode, + 205, + 18, + 219, + 1, // Opcode: ROUND_L_D64 + /* 367 */ MCD_OPC_FilterValue, + 9, + 35, + 0, + 0, // Skip to: 407 + /* 372 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 375 */ MCD_OPC_FilterValue, + 128, + 4, + 10, + 0, + 0, // Skip to: 391 + /* 381 */ MCD_OPC_CheckPredicate, + 101, + 57, + 5, + 0, // Skip to: 1723 + /* 386 */ MCD_OPC_Decode, + 245, + 21, + 212, + 1, // Opcode: TRUNC_L_S + /* 391 */ MCD_OPC_FilterValue, + 160, + 4, + 46, + 5, + 0, // Skip to: 1723 + /* 397 */ MCD_OPC_CheckPredicate, + 102, + 41, + 5, + 0, // Skip to: 1723 + /* 402 */ MCD_OPC_Decode, + 243, + 21, + 219, + 1, // Opcode: TRUNC_L_D64 + /* 407 */ MCD_OPC_FilterValue, + 10, + 35, + 0, + 0, // Skip to: 447 + /* 412 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 415 */ MCD_OPC_FilterValue, + 128, + 4, + 10, + 0, + 0, // Skip to: 431 + /* 421 */ MCD_OPC_CheckPredicate, + 101, + 17, + 5, + 0, // Skip to: 1723 + /* 426 */ MCD_OPC_Decode, + 157, + 8, + 212, + 1, // Opcode: CEIL_L_S + /* 431 */ MCD_OPC_FilterValue, + 160, + 4, + 6, + 5, + 0, // Skip to: 1723 + /* 437 */ MCD_OPC_CheckPredicate, + 102, + 1, + 5, + 0, // Skip to: 1723 + /* 442 */ MCD_OPC_Decode, + 155, + 8, + 219, + 1, // Opcode: CEIL_L_D64 + /* 447 */ MCD_OPC_FilterValue, + 11, + 35, + 0, + 0, // Skip to: 487 + /* 452 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 455 */ MCD_OPC_FilterValue, + 128, + 4, + 10, + 0, + 0, // Skip to: 471 + /* 461 */ MCD_OPC_CheckPredicate, + 101, + 233, + 4, + 0, // Skip to: 1723 + /* 466 */ MCD_OPC_Decode, + 216, + 12, + 212, + 1, // Opcode: FLOOR_L_S + /* 471 */ MCD_OPC_FilterValue, + 160, + 4, + 222, + 4, + 0, // Skip to: 1723 + /* 477 */ MCD_OPC_CheckPredicate, + 102, + 217, + 4, + 0, // Skip to: 1723 + /* 482 */ MCD_OPC_Decode, + 214, + 12, + 219, + 1, // Opcode: FLOOR_L_D64 + /* 487 */ MCD_OPC_FilterValue, + 12, + 18, + 0, + 0, // Skip to: 510 + /* 492 */ MCD_OPC_CheckPredicate, + 101, + 202, + 4, + 0, // Skip to: 1723 + /* 497 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 194, + 4, + 0, // Skip to: 1723 + /* 505 */ MCD_OPC_Decode, + 210, + 18, + 253, + 2, // Opcode: ROUND_W_D64 + /* 510 */ MCD_OPC_FilterValue, + 13, + 18, + 0, + 0, // Skip to: 533 + /* 515 */ MCD_OPC_CheckPredicate, + 101, + 179, + 4, + 0, // Skip to: 1723 + /* 520 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 171, + 4, + 0, // Skip to: 1723 + /* 528 */ MCD_OPC_Decode, + 248, + 21, + 253, + 2, // Opcode: TRUNC_W_D64 + /* 533 */ MCD_OPC_FilterValue, + 14, + 18, + 0, + 0, // Skip to: 556 + /* 538 */ MCD_OPC_CheckPredicate, + 101, + 156, + 4, + 0, // Skip to: 1723 + /* 543 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 148, + 4, + 0, // Skip to: 1723 + /* 551 */ MCD_OPC_Decode, + 160, + 8, + 253, + 2, // Opcode: CEIL_W_D64 + /* 556 */ MCD_OPC_FilterValue, + 15, + 18, + 0, + 0, // Skip to: 579 + /* 561 */ MCD_OPC_CheckPredicate, + 101, + 133, + 4, + 0, // Skip to: 1723 + /* 566 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 125, + 4, + 0, // Skip to: 1723 + /* 574 */ MCD_OPC_Decode, + 219, + 12, + 253, + 2, // Opcode: FLOOR_W_D64 + /* 579 */ MCD_OPC_FilterValue, + 17, + 47, + 0, + 0, // Skip to: 631 + /* 584 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 587 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 609 + /* 592 */ MCD_OPC_CheckPredicate, + 103, + 102, + 4, + 0, // Skip to: 1723 + /* 597 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 95, + 4, + 0, // Skip to: 1723 + /* 604 */ MCD_OPC_Decode, + 164, + 16, + 254, + 2, // Opcode: MOVF_D64 + /* 609 */ MCD_OPC_FilterValue, + 1, + 85, + 4, + 0, // Skip to: 1723 + /* 614 */ MCD_OPC_CheckPredicate, + 103, + 80, + 4, + 0, // Skip to: 1723 + /* 619 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 73, + 4, + 0, // Skip to: 1723 + /* 626 */ MCD_OPC_Decode, + 184, + 16, + 254, + 2, // Opcode: MOVT_D64 + /* 631 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 653 + /* 636 */ MCD_OPC_CheckPredicate, + 103, + 58, + 4, + 0, // Skip to: 1723 + /* 641 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 51, + 4, + 0, // Skip to: 1723 + /* 648 */ MCD_OPC_Decode, + 196, + 16, + 255, + 2, // Opcode: MOVZ_I_D64 + /* 653 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 675 + /* 658 */ MCD_OPC_CheckPredicate, + 103, + 36, + 4, + 0, // Skip to: 1723 + /* 663 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 29, + 4, + 0, // Skip to: 1723 + /* 670 */ MCD_OPC_Decode, + 176, + 16, + 255, + 2, // Opcode: MOVN_I_D64 + /* 675 */ MCD_OPC_FilterValue, + 21, + 18, + 0, + 0, // Skip to: 698 + /* 680 */ MCD_OPC_CheckPredicate, + 104, + 14, + 4, + 0, // Skip to: 1723 + /* 685 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 6, + 4, + 0, // Skip to: 1723 + /* 693 */ MCD_OPC_Decode, + 185, + 18, + 219, + 1, // Opcode: RECIP_D64 + /* 698 */ MCD_OPC_FilterValue, + 22, + 18, + 0, + 0, // Skip to: 721 + /* 703 */ MCD_OPC_CheckPredicate, + 104, + 247, + 3, + 0, // Skip to: 1723 + /* 708 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 239, + 3, + 0, // Skip to: 1723 + /* 716 */ MCD_OPC_Decode, + 218, + 18, + 219, + 1, // Opcode: RSQRT_D64 + /* 721 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 743 + /* 726 */ MCD_OPC_CheckPredicate, + 105, + 224, + 3, + 0, // Skip to: 1723 + /* 731 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 217, + 3, + 0, // Skip to: 1723 + /* 738 */ MCD_OPC_Decode, + 217, + 5, + 219, + 2, // Opcode: ADDR_PS64 + /* 743 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 765 + /* 748 */ MCD_OPC_CheckPredicate, + 105, + 202, + 3, + 0, // Skip to: 1723 + /* 753 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 195, + 3, + 0, // Skip to: 1723 + /* 760 */ MCD_OPC_Decode, + 158, + 17, + 219, + 2, // Opcode: MULR_PS64 + /* 765 */ MCD_OPC_FilterValue, + 32, + 51, + 0, + 0, // Skip to: 821 + /* 770 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 773 */ MCD_OPC_FilterValue, + 160, + 4, + 10, + 0, + 0, // Skip to: 789 + /* 779 */ MCD_OPC_CheckPredicate, + 98, + 171, + 3, + 0, // Skip to: 1723 + /* 784 */ MCD_OPC_Decode, + 226, + 9, + 253, + 2, // Opcode: CVT_S_D64 + /* 789 */ MCD_OPC_FilterValue, + 160, + 5, + 10, + 0, + 0, // Skip to: 805 + /* 795 */ MCD_OPC_CheckPredicate, + 106, + 155, + 3, + 0, // Skip to: 1723 + /* 800 */ MCD_OPC_Decode, + 228, + 9, + 253, + 2, // Opcode: CVT_S_L + /* 805 */ MCD_OPC_FilterValue, + 192, + 5, + 144, + 3, + 0, // Skip to: 1723 + /* 811 */ MCD_OPC_CheckPredicate, + 100, + 139, + 3, + 0, // Skip to: 1723 + /* 816 */ MCD_OPC_Decode, + 231, + 9, + 253, + 2, // Opcode: CVT_S_PU64 + /* 821 */ MCD_OPC_FilterValue, + 33, + 51, + 0, + 0, // Skip to: 877 + /* 826 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 829 */ MCD_OPC_FilterValue, + 128, + 4, + 10, + 0, + 0, // Skip to: 845 + /* 835 */ MCD_OPC_CheckPredicate, + 98, + 115, + 3, + 0, // Skip to: 1723 + /* 840 */ MCD_OPC_Decode, + 210, + 9, + 212, + 1, // Opcode: CVT_D64_S + /* 845 */ MCD_OPC_FilterValue, + 128, + 5, + 10, + 0, + 0, // Skip to: 861 + /* 851 */ MCD_OPC_CheckPredicate, + 98, + 99, + 3, + 0, // Skip to: 1723 + /* 856 */ MCD_OPC_Decode, + 212, + 9, + 212, + 1, // Opcode: CVT_D64_W + /* 861 */ MCD_OPC_FilterValue, + 160, + 5, + 88, + 3, + 0, // Skip to: 1723 + /* 867 */ MCD_OPC_CheckPredicate, + 106, + 83, + 3, + 0, // Skip to: 1723 + /* 872 */ MCD_OPC_Decode, + 209, + 9, + 219, + 1, // Opcode: CVT_D64_L + /* 877 */ MCD_OPC_FilterValue, + 36, + 35, + 0, + 0, // Skip to: 917 + /* 882 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 885 */ MCD_OPC_FilterValue, + 160, + 4, + 10, + 0, + 0, // Skip to: 901 + /* 891 */ MCD_OPC_CheckPredicate, + 98, + 59, + 3, + 0, // Skip to: 1723 + /* 896 */ MCD_OPC_Decode, + 237, + 9, + 253, + 2, // Opcode: CVT_W_D64 + /* 901 */ MCD_OPC_FilterValue, + 192, + 5, + 48, + 3, + 0, // Skip to: 1723 + /* 907 */ MCD_OPC_CheckPredicate, + 105, + 43, + 3, + 0, // Skip to: 1723 + /* 912 */ MCD_OPC_Decode, + 223, + 9, + 219, + 1, // Opcode: CVT_PW_PS64 + /* 917 */ MCD_OPC_FilterValue, + 38, + 40, + 0, + 0, // Skip to: 962 + /* 922 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 925 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 940 + /* 930 */ MCD_OPC_CheckPredicate, + 100, + 20, + 3, + 0, // Skip to: 1723 + /* 935 */ MCD_OPC_Decode, + 222, + 9, + 128, + 3, // Opcode: CVT_PS_S64 + /* 940 */ MCD_OPC_FilterValue, + 20, + 10, + 3, + 0, // Skip to: 1723 + /* 945 */ MCD_OPC_CheckPredicate, + 105, + 5, + 3, + 0, // Skip to: 1723 + /* 950 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 254, + 2, + 0, // Skip to: 1723 + /* 957 */ MCD_OPC_Decode, + 221, + 9, + 219, + 1, // Opcode: CVT_PS_PW64 + /* 962 */ MCD_OPC_FilterValue, + 40, + 18, + 0, + 0, // Skip to: 985 + /* 967 */ MCD_OPC_CheckPredicate, + 100, + 239, + 2, + 0, // Skip to: 1723 + /* 972 */ MCD_OPC_CheckField, + 16, + 10, + 192, + 5, + 231, + 2, + 0, // Skip to: 1723 + /* 980 */ MCD_OPC_Decode, + 230, + 9, + 253, + 2, // Opcode: CVT_S_PL64 + /* 985 */ MCD_OPC_FilterValue, + 44, + 17, + 0, + 0, // Skip to: 1007 + /* 990 */ MCD_OPC_CheckPredicate, + 100, + 216, + 2, + 0, // Skip to: 1723 + /* 995 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 209, + 2, + 0, // Skip to: 1723 + /* 1002 */ MCD_OPC_Decode, + 254, + 17, + 219, + 2, // Opcode: PLL_PS64 + /* 1007 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 1029 + /* 1012 */ MCD_OPC_CheckPredicate, + 100, + 194, + 2, + 0, // Skip to: 1723 + /* 1017 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 187, + 2, + 0, // Skip to: 1723 + /* 1024 */ MCD_OPC_Decode, + 255, + 17, + 219, + 2, // Opcode: PLU_PS64 + /* 1029 */ MCD_OPC_FilterValue, + 46, + 17, + 0, + 0, // Skip to: 1051 + /* 1034 */ MCD_OPC_CheckPredicate, + 100, + 172, + 2, + 0, // Skip to: 1723 + /* 1039 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 165, + 2, + 0, // Skip to: 1723 + /* 1046 */ MCD_OPC_Decode, + 172, + 18, + 219, + 2, // Opcode: PUL_PS64 + /* 1051 */ MCD_OPC_FilterValue, + 47, + 17, + 0, + 0, // Skip to: 1073 + /* 1056 */ MCD_OPC_CheckPredicate, + 100, + 150, + 2, + 0, // Skip to: 1723 + /* 1061 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 143, + 2, + 0, // Skip to: 1723 + /* 1068 */ MCD_OPC_Decode, + 173, + 18, + 219, + 2, // Opcode: PUU_PS64 + /* 1073 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 1102 + /* 1078 */ MCD_OPC_CheckPredicate, + 107, + 128, + 2, + 0, // Skip to: 1723 + /* 1083 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 121, + 2, + 0, // Skip to: 1723 + /* 1090 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 114, + 2, + 0, // Skip to: 1723 + /* 1097 */ MCD_OPC_Decode, + 250, + 9, + 129, + 3, // Opcode: C_F_D64 + /* 1102 */ MCD_OPC_FilterValue, + 49, + 24, + 0, + 0, // Skip to: 1131 + /* 1107 */ MCD_OPC_CheckPredicate, + 107, + 99, + 2, + 0, // Skip to: 1723 + /* 1112 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 92, + 2, + 0, // Skip to: 1723 + /* 1119 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 85, + 2, + 0, // Skip to: 1723 + /* 1126 */ MCD_OPC_Decode, + 206, + 10, + 129, + 3, // Opcode: C_UN_D64 + /* 1131 */ MCD_OPC_FilterValue, + 50, + 24, + 0, + 0, // Skip to: 1160 + /* 1136 */ MCD_OPC_CheckPredicate, + 107, + 70, + 2, + 0, // Skip to: 1723 + /* 1141 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 63, + 2, + 0, // Skip to: 1723 + /* 1148 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 56, + 2, + 0, // Skip to: 1723 + /* 1155 */ MCD_OPC_Decode, + 244, + 9, + 129, + 3, // Opcode: C_EQ_D64 + /* 1160 */ MCD_OPC_FilterValue, + 51, + 24, + 0, + 0, // Skip to: 1189 + /* 1165 */ MCD_OPC_CheckPredicate, + 107, + 41, + 2, + 0, // Skip to: 1723 + /* 1170 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 34, + 2, + 0, // Skip to: 1723 + /* 1177 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 27, + 2, + 0, // Skip to: 1723 + /* 1184 */ MCD_OPC_Decode, + 188, + 10, + 129, + 3, // Opcode: C_UEQ_D64 + /* 1189 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 1218 + /* 1194 */ MCD_OPC_CheckPredicate, + 107, + 12, + 2, + 0, // Skip to: 1723 + /* 1199 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 5, + 2, + 0, // Skip to: 1723 + /* 1206 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 254, + 1, + 0, // Skip to: 1723 + /* 1213 */ MCD_OPC_Decode, + 170, + 10, + 129, + 3, // Opcode: C_OLT_D64 + /* 1218 */ MCD_OPC_FilterValue, + 53, + 24, + 0, + 0, // Skip to: 1247 + /* 1223 */ MCD_OPC_CheckPredicate, + 107, + 239, + 1, + 0, // Skip to: 1723 + /* 1228 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 232, + 1, + 0, // Skip to: 1723 + /* 1235 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 225, + 1, + 0, // Skip to: 1723 + /* 1242 */ MCD_OPC_Decode, + 200, + 10, + 129, + 3, // Opcode: C_ULT_D64 + /* 1247 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 1276 + /* 1252 */ MCD_OPC_CheckPredicate, + 107, + 210, + 1, + 0, // Skip to: 1723 + /* 1257 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 203, + 1, + 0, // Skip to: 1723 + /* 1264 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 196, + 1, + 0, // Skip to: 1723 + /* 1271 */ MCD_OPC_Decode, + 164, + 10, + 129, + 3, // Opcode: C_OLE_D64 + /* 1276 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 1305 + /* 1281 */ MCD_OPC_CheckPredicate, + 107, + 181, + 1, + 0, // Skip to: 1723 + /* 1286 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 174, + 1, + 0, // Skip to: 1723 + /* 1293 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 167, + 1, + 0, // Skip to: 1723 + /* 1300 */ MCD_OPC_Decode, + 194, + 10, + 129, + 3, // Opcode: C_ULE_D64 + /* 1305 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 1334 + /* 1310 */ MCD_OPC_CheckPredicate, + 107, + 152, + 1, + 0, // Skip to: 1723 + /* 1315 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 145, + 1, + 0, // Skip to: 1723 + /* 1322 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 138, + 1, + 0, // Skip to: 1723 + /* 1329 */ MCD_OPC_Decode, + 182, + 10, + 129, + 3, // Opcode: C_SF_D64 + /* 1334 */ MCD_OPC_FilterValue, + 57, + 24, + 0, + 0, // Skip to: 1363 + /* 1339 */ MCD_OPC_CheckPredicate, + 107, + 123, + 1, + 0, // Skip to: 1723 + /* 1344 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 116, + 1, + 0, // Skip to: 1723 + /* 1351 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 109, + 1, + 0, // Skip to: 1723 + /* 1358 */ MCD_OPC_Decode, + 146, + 10, + 129, + 3, // Opcode: C_NGLE_D64 + /* 1363 */ MCD_OPC_FilterValue, + 58, + 24, + 0, + 0, // Skip to: 1392 + /* 1368 */ MCD_OPC_CheckPredicate, + 107, + 94, + 1, + 0, // Skip to: 1723 + /* 1373 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 87, + 1, + 0, // Skip to: 1723 + /* 1380 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 80, + 1, + 0, // Skip to: 1723 + /* 1387 */ MCD_OPC_Decode, + 176, + 10, + 129, + 3, // Opcode: C_SEQ_D64 + /* 1392 */ MCD_OPC_FilterValue, + 59, + 24, + 0, + 0, // Skip to: 1421 + /* 1397 */ MCD_OPC_CheckPredicate, + 107, + 65, + 1, + 0, // Skip to: 1723 + /* 1402 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 58, + 1, + 0, // Skip to: 1723 + /* 1409 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 51, + 1, + 0, // Skip to: 1723 + /* 1416 */ MCD_OPC_Decode, + 152, + 10, + 129, + 3, // Opcode: C_NGL_D64 + /* 1421 */ MCD_OPC_FilterValue, + 60, + 24, + 0, + 0, // Skip to: 1450 + /* 1426 */ MCD_OPC_CheckPredicate, + 107, + 36, + 1, + 0, // Skip to: 1723 + /* 1431 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 29, + 1, + 0, // Skip to: 1723 + /* 1438 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 22, + 1, + 0, // Skip to: 1723 + /* 1445 */ MCD_OPC_Decode, + 134, + 10, + 129, + 3, // Opcode: C_LT_D64 + /* 1450 */ MCD_OPC_FilterValue, + 61, + 24, + 0, + 0, // Skip to: 1479 + /* 1455 */ MCD_OPC_CheckPredicate, + 107, + 7, + 1, + 0, // Skip to: 1723 + /* 1460 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 0, + 1, + 0, // Skip to: 1723 + /* 1467 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 249, + 0, + 0, // Skip to: 1723 + /* 1474 */ MCD_OPC_Decode, + 140, + 10, + 129, + 3, // Opcode: C_NGE_D64 + /* 1479 */ MCD_OPC_FilterValue, + 62, + 24, + 0, + 0, // Skip to: 1508 + /* 1484 */ MCD_OPC_CheckPredicate, + 107, + 234, + 0, + 0, // Skip to: 1723 + /* 1489 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 227, + 0, + 0, // Skip to: 1723 + /* 1496 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 220, + 0, + 0, // Skip to: 1723 + /* 1503 */ MCD_OPC_Decode, + 128, + 10, + 129, + 3, // Opcode: C_LE_D64 + /* 1508 */ MCD_OPC_FilterValue, + 63, + 210, + 0, + 0, // Skip to: 1723 + /* 1513 */ MCD_OPC_CheckPredicate, + 107, + 205, + 0, + 0, // Skip to: 1723 + /* 1518 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 198, + 0, + 0, // Skip to: 1723 + /* 1525 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 191, + 0, + 0, // Skip to: 1723 + /* 1532 */ MCD_OPC_Decode, + 158, + 10, + 129, + 3, // Opcode: C_NGT_D64 + /* 1537 */ MCD_OPC_FilterValue, + 19, + 151, + 0, + 0, // Skip to: 1693 + /* 1542 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1545 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 1567 + /* 1550 */ MCD_OPC_CheckPredicate, + 108, + 168, + 0, + 0, // Skip to: 1723 + /* 1555 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 161, + 0, + 0, // Skip to: 1723 + /* 1562 */ MCD_OPC_Decode, + 184, + 14, + 130, + 3, // Opcode: LDXC164 + /* 1567 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 1589 + /* 1572 */ MCD_OPC_CheckPredicate, + 109, + 146, + 0, + 0, // Skip to: 1723 + /* 1577 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 139, + 0, + 0, // Skip to: 1723 + /* 1584 */ MCD_OPC_Decode, + 222, + 14, + 130, + 3, // Opcode: LUXC164 + /* 1589 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 1611 + /* 1594 */ MCD_OPC_CheckPredicate, + 108, + 124, + 0, + 0, // Skip to: 1723 + /* 1599 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 117, + 0, + 0, // Skip to: 1723 + /* 1606 */ MCD_OPC_Decode, + 144, + 19, + 131, + 3, // Opcode: SDXC164 + /* 1611 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 1633 + /* 1616 */ MCD_OPC_CheckPredicate, + 109, + 102, + 0, + 0, // Skip to: 1723 + /* 1621 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 95, + 0, + 0, // Skip to: 1723 + /* 1628 */ MCD_OPC_Decode, + 131, + 21, + 131, + 3, // Opcode: SUXC164 + /* 1633 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 1648 + /* 1638 */ MCD_OPC_CheckPredicate, + 110, + 80, + 0, + 0, // Skip to: 1723 + /* 1643 */ MCD_OPC_Decode, + 168, + 15, + 132, + 3, // Opcode: MADD_D64 + /* 1648 */ MCD_OPC_FilterValue, + 41, + 10, + 0, + 0, // Skip to: 1663 + /* 1653 */ MCD_OPC_CheckPredicate, + 110, + 65, + 0, + 0, // Skip to: 1723 + /* 1658 */ MCD_OPC_Decode, + 219, + 16, + 132, + 3, // Opcode: MSUB_D64 + /* 1663 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 1678 + /* 1668 */ MCD_OPC_CheckPredicate, + 111, + 50, + 0, + 0, // Skip to: 1723 + /* 1673 */ MCD_OPC_Decode, + 202, + 17, + 132, + 3, // Opcode: NMADD_D64 + /* 1678 */ MCD_OPC_FilterValue, + 57, + 40, + 0, + 0, // Skip to: 1723 + /* 1683 */ MCD_OPC_CheckPredicate, + 111, + 35, + 0, + 0, // Skip to: 1723 + /* 1688 */ MCD_OPC_Decode, + 207, + 17, + 132, + 3, // Opcode: NMSUB_D64 + /* 1693 */ MCD_OPC_FilterValue, + 53, + 10, + 0, + 0, // Skip to: 1708 + /* 1698 */ MCD_OPC_CheckPredicate, + 101, + 20, + 0, + 0, // Skip to: 1723 + /* 1703 */ MCD_OPC_Decode, + 169, + 14, + 208, + 2, // Opcode: LDC164 + /* 1708 */ MCD_OPC_FilterValue, + 61, + 10, + 0, + 0, // Skip to: 1723 + /* 1713 */ MCD_OPC_CheckPredicate, + 101, + 5, + 0, + 0, // Skip to: 1723 + /* 1718 */ MCD_OPC_Decode, + 132, + 19, + 208, + 2, // Opcode: SDC164 + /* 1723 */ MCD_OPC_Fail, + 0}; -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) -{ +static bool getbool(uint64_t b) { return b != 0; } +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { - default: // llvm_unreachable("Invalid index!"); + default: + llvm_unreachable("Invalid index!"); case 0: - return getbool((Bits & Mips_FeatureMips16)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 1)); case 1: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureCnMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 2: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureCnMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 3: - return getbool((Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureCnMips, 1)); case 4: - return getbool((Bits & Mips_FeatureMips32) && (Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips64, 1) && + checkFeatureRequired(Bits, Mips_FeatureCnMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 5: - return getbool(!(Bits & Mips_FeatureMips16)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureCnMipsP, 1)); case 6: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0)); case 7: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1)); case 8: - return getbool((Bits & Mips_FeatureMSA)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureDSP, 1)); case 9: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureDSPR2, 1)); case 10: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r5, 1) && + checkFeatureRequired(Bits, Mips_FeatureVirt, 1)); case 11: - return getbool(!(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureDSPR3, 1)); case 12: - return getbool((Bits & Mips_FeatureDSP)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureDSP, 1)); case 13: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 14: - return getbool((Bits & Mips_FeatureMSA) && (Bits & Mips_FeatureMips64)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0)); case 15: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 16: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0)); case 17: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 18: - return getbool(!(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 19: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 20: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 21: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureEVA, 1)); case 22: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32r2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureEVA, 1)); case 23: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 24: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1)); case 25: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureGINV, 1)); case 26: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 27: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 28: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 29: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 30: - return getbool((Bits & Mips_FeatureDSPR2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMSA, 1)); case 31: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 32: - return getbool((Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0)); case 33: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return getbool( + checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureUseIndirectJumpsHazard, 0)); case 34: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32, 1)); case 35: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 36: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 37: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureDSP, 1)); case 38: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMSA, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64, 1)); case 39: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 40: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureDSP, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 41: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r5, 1) && + checkFeatureRequired(Bits, Mips_FeatureVirt, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 42: - return getbool((Bits & Mips_FeatureMips64)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMT, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 43: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && (Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureEVA, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 44: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 45: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && (Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r5, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 46: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 47: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && (Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 48: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 49: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 50: - return getbool((Bits & Mips_FeatureCnMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 51: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 52: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 53: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); + case 54: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 55: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 56: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 57: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 58: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 59: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 60: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 61: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); + case 62: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 63: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips5_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 64: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0)); + case 65: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0)); + case 66: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 67: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 68: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 69: + return getbool(checkFeatureRequired(Bits, Mips_FeatureDSPR2, 1)); + case 70: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureEVA, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 71: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 72: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 73: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 74: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 75: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1)); + case 76: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 77: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 78: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureGP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 79: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 80: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureCRC, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 81: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureCRC, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 82: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 83: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureGINV, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 84: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 1)); + case 85: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureGP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 1)); + case 86: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureGP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1)); + case 87: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 88: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 89: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 1)); + case 90: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 91: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 92: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 93: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureGP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips3, 1)); + case 94: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r5, 1) && + checkFeatureRequired(Bits, Mips_FeatureVirt, 1)); + case 95: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0)); + case 96: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureGP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 97: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureDSP, 1)); + case 98: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 99: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 100: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 101: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 102: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips3_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 103: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 104: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 105: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3D, 1)); + case 106: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips3_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 107: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 108: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); + case 109: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips5_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 110: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0)); + case 111: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); } } -#define DecodeToMCInst(fname,fieldname, InsnType) \ -static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, void *Decoder) \ -{ \ - InsnType tmp; \ - switch (Idx) { \ - default: \ - case 0: \ - return S; \ - case 1: \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 2: \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 3: \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 2) << 3; \ - tmp |= fieldname(insn, 5, 3) << 0; \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 4: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 5: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 6: \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 7: \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 8: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 11; \ - tmp |= fieldname(insn, 21, 6) << 5; \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 9: \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 10: \ - if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 11: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 12: \ - if (DecodeMemMMImm4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 13: \ - tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 14: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 15: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 16: \ - tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 17: \ - tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 18: \ - if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 19: \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 20: \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 21: \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeUImm5lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 22: \ - if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 23: \ - tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 4); \ - if (DecodeSimm4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 24: \ - tmp = fieldname(insn, 1, 9); \ - if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 25: \ - if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 26: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 27: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 6); \ - if (DecodeUImm6Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 28: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeMovePRegPair(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 29: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 7); \ - if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 30: \ - tmp = fieldname(insn, 0, 10); \ - if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 31: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 7); \ - if (DecodeLiSimm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 32: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 33: \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 6, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 34: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 35: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 36: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 37: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 38: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 39: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 40: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 41: \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 42: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 43: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 44: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 45: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 46: \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 47: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 48: \ - if (DecodeMemMMImm16(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 49: \ - if (DecodeMemMMImm12(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 50: \ - if (DecodeCacheOpMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 51: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 52: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 53: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 54: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 13, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 55: \ - if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 56: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 23); \ - if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 57: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 58: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 59: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 60: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 61: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 62: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 63: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 64: \ - tmp = fieldname(insn, 6, 20); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 65: \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 66: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 67: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 68: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 69: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 70: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 71: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 72: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 73: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 74: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 75: \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 76: \ - if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 77: \ - if (DecodeJumpTarget(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 78: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 79: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 80: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 81: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 82: \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 83: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 84: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 85: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 86: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 87: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 88: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 89: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 90: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 91: \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 92: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 93: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 94: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 95: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 96: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 97: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 98: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 99: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 100: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 101: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 102: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 103: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 104: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 105: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 106: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 107: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 108: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 109: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 110: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 111: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 112: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 113: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 114: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 115: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 116: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 117: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 118: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 119: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 120: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 121: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 122: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 123: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 124: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 125: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 126: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 127: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 128: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 129: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 130: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 131: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 132: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 133: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 134: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 135: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 136: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 137: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 138: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 139: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 140: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 141: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 142: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 143: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 144: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 145: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 146: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 147: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 148: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 149: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 150: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 151: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 152: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 153: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 154: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 155: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 156: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 157: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 158: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 159: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 160: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 161: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 162: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 163: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 164: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 165: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 166: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 167: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 168: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 169: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 170: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 171: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 172: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 173: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 174: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 175: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 176: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 177: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 178: \ - if (DecodeINSVE_DF_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 179: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 180: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 181: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 182: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 183: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 184: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 185: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 186: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 187: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 188: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 189: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 190: \ - if (DecodeMSA128Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 191: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 192: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 193: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 194: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 195: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 196: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 197: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 198: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 199: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 200: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 201: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 202: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 203: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 204: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 205: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 206: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 207: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 208: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 209: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 210: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 211: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 212: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 213: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 214: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 6); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 215: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 216: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 217: \ - if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 218: \ - if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 219: \ - if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 220: \ - if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 221: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 222: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 223: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 224: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 225: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 226: \ - if (DecodeBlezGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 227: \ - if (DecodeBgtzGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 228: \ - if (DecodeAddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 229: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 230: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 231: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 232: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 233: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 234: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 235: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 236: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 237: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 238: \ - if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 239: \ - if (DecodeBlezlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 240: \ - if (DecodeBgtzlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 241: \ - if (DecodeDaddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 242: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 243: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 244: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 245: \ - if (DecodeCacheOpR6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 246: \ - if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 247: \ - tmp = fieldname(insn, 0, 26); \ - if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 248: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 21); \ - if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 249: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 19); \ - if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 250: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 18); \ - if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 251: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 252: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 253: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 254: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 255: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 256: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 257: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 258: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 259: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 260: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 261: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 262: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 263: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 264: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 265: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 266: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 267: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 268: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 269: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 270: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 271: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 272: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - } \ -} +#define DecodeToMCInst(fname, fieldname, InsnType) \ + static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, \ + MCInst *MI, uint64_t Address, bool *Decoder) { \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + llvm_unreachable("Invalid index!"); \ + case 0: \ + return S; \ + case 1: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 2: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 3: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 2) << 3; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 4: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 5: \ + tmp = fieldname(insn, 2, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 6: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 7: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 8: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 9: \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 10: \ + if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 11: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 12: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 13: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 14: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 15: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 16: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 10); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 10) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 17: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 18: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 19: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 21: \ + if (DecodeMemMMImm4(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 22: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 23: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodePOOL16BEncodedField(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 24: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 3, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 26: \ + tmp = fieldname(insn, 3, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 27: \ + if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 30: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeUImmWithOffsetAndScale(MI, tmp, Address, Decoder, 5, 0, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 31: \ + if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 32: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 4); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 1, 9); \ + if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 34: \ + if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 35: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 36: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 6); \ + if (DecodeUImmWithOffsetAndScale(MI, tmp, Address, Decoder, 6, 0, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 37: \ + if (DecodeMovePOperands(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 38: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 7); \ + if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 39: \ + tmp = fieldname(insn, 0, 10); \ + if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 40: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 7); \ + if (DecodeLi16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 41: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 42: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 43: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 44: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 45: \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 6, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 46: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 47: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 48: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 49: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 50: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 51: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 52: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 53: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 55: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeUImmWithOffset(MI, tmp, Address, Decoder, 5, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 56: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 57: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 58: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 59: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 60: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 61: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 62: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 63: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 64: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 65: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 66: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 67: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 68: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 69: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 70: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 71: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 72: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 73: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 74: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 75: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 76: \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 77: \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 78: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 79: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 80: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 81: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 82: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 83: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 7); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 84: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 85: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 10); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 10) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 86: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 87: \ + if (DecodeMemMMImm16(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 88: \ + if (DecodeMemMMImm12(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 89: \ + if (DecodeCacheOpMM(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 90: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 91: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 92: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 93: \ + if (DecodeSyncI_MM(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 94: \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget1SImm16(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 95: \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 96: \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 97: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 98: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 99: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 100: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 101: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 102: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 103: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 104: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 105: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 106: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 107: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 108: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 109: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 110: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 111: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 112: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 113: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 114: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 115: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 116: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 117: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 118: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 119: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 120: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 121: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 122: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 123: \ + if (DecodeMemMMImm9(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 124: \ + if (DecodePrefeOpMM(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 125: \ + if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 126: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 23); \ + if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 127: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 128: \ + if (DecodeFMemMMR2(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 129: \ + if (DecodeJumpTargetXMM(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 130: \ + if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 131: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 132: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 133: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 134: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 135: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 136: \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 137: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 138: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 139: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 140: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeUImmWithOffsetAndScale(MI, tmp, Address, Decoder, 5, 0, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 141: \ + tmp = fieldname(insn, 6, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 142: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 143: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 2); \ + if (DecodeUImmWithOffset(MI, tmp, Address, Decoder, 2, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 144: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 145: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 146: \ + tmp = fieldname(insn, 6, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 147: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 148: \ + if (DecodeLoadByte15(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 149: \ + if (DecodeFMemCop2MMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 150: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 151: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 152: \ + if (DecodeSynciR6(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 153: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 154: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 155: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 156: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 157: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 158: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 159: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 160: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 161: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 162: \ + if (DecodePOP35GroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 163: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 19); \ + if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 164: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 165: \ + if (DecodePOP37GroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 166: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 21); \ + if (DecodeBranchTarget21MM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 167: \ + tmp = fieldname(insn, 0, 26); \ + if (DecodeBranchTarget26MM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 168: \ + if (DecodeBlezGroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 169: \ + if (DecodePOP65GroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 170: \ + if (DecodeBgtzGroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 171: \ + if (DecodePOP75GroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 172: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 173: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 174: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 2); \ + if (DecodeUImmWithOffset(MI, tmp, Address, Decoder, 2, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 175: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 176: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 177: \ + tmp = fieldname(insn, 6, 20); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 178: \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 179: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 180: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 181: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 182: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 183: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 2); \ + if (DecodeUImmWithOffset(MI, tmp, Address, Decoder, 2, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 184: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 185: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 186: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 187: \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 188: \ + if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 189: \ + if (DecodeJumpTarget(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 190: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 191: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 192: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 193: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 194: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 195: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 4, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 196: \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 197: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 198: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 199: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 200: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 201: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 202: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 203: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 204: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 205: \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 206: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 207: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 208: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 209: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 210: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 211: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 212: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 213: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 214: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 215: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 216: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 217: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 218: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 219: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 220: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 221: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 222: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 223: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 224: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 225: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 226: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 227: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 228: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 229: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 230: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 231: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 232: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 233: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 234: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 235: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 236: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 237: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 238: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 239: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 240: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 241: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 242: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 243: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 244: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 245: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 246: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 247: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 248: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 249: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 250: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 251: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 252: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 253: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 254: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 255: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 256: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 257: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 258: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 259: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 260: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 261: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 262: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 263: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 264: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 265: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 266: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 267: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 268: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 269: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 270: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 271: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 272: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 273: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 274: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 275: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 276: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 277: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 278: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 279: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 280: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 281: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 282: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 283: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 284: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 285: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 286: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 287: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 288: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 289: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 290: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 291: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 292: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 293: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 294: \ + if (DecodeINSVE_DF(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 295: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 296: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 297: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 298: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 299: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 300: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 301: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 302: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 303: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 304: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 305: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 306: \ + if (DecodeMSA128Mem(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 307: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeUImmWithOffset(MI, tmp, Address, Decoder, 5, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 308: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 309: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 310: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 311: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 312: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 313: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 314: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 315: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 316: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 317: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 318: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 319: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 320: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 321: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 322: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 323: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 324: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 325: \ + if (DecodeMemEVA(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 326: \ + if (DecodeCacheeOp_CacheOpR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 327: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 328: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 329: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 330: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 331: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 332: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 6); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 333: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 334: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 335: \ + if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 336: \ + if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 337: \ + if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 338: \ + if (DecodeDAHIDATI(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 339: \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 340: \ + if (DecodeBlezGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 341: \ + if (DecodeBgtzGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 342: \ + if (DecodeAddiGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 343: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 344: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 345: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 346: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 347: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 348: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 349: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 350: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 351: \ + if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 352: \ + if (DecodeBlezlGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 353: \ + if (DecodeBgtzlGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 354: \ + if (DecodeDaddiGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 355: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 356: \ + if (DecodeCRC(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 357: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 358: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 359: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 360: \ + if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 361: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 362: \ + tmp = fieldname(insn, 0, 26); \ + if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 363: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 21); \ + if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 364: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 18); \ + if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 365: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 21); \ + if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 366: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 367: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 368: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 369: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 370: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 371: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 372: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 373: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 374: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 375: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 376: \ + if (DecodeDEXT(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 377: \ + if (DecodeDINS(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 378: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 379: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 380: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 381: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 382: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 383: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 384: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 385: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 386: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 387: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 388: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + } \ + } -#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ -static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \ -{ \ - uint64_t Bits = getFeatureBits(feature); \ - const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0, ExpectedValue; \ - DecodeStatus S = MCDisassembler_Success; \ - unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ - InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail; \ - for (;;) { \ - switch (*Ptr) { \ - default: \ - return MCDisassembler_Fail; \ - case MCD_OPC_ExtractField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - ++Ptr; \ - CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ - break; \ - } \ - case MCD_OPC_FilterValue: { \ - Val = (InsnType)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - if (Val != CurFieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - FieldValue = fieldname(insn, Start, Len); \ - ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - if (ExpectedValue != FieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckPredicate: { \ - PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - Pred = checkDecoderPredicate(PIdx, Bits); \ - if (!Pred) \ - Ptr += NumToSkip; \ - (void)Pred; \ - break; \ - } \ - case MCD_OPC_Decode: { \ - Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - MCInst_setOpcode(MI, Opc); \ - return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ - } \ - case MCD_OPC_SoftFail: { \ - PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ - if (Fail) \ - S = MCDisassembler_SoftFail; \ - break; \ - } \ - case MCD_OPC_Fail: { \ - return MCDisassembler_Fail; \ - } \ - } \ - } \ -} +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ + static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, \ + MCRegisterInfo *MRI, int feature) { \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail, DecodeComplete = true; \ + uint32_t ExpectedValue; \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + ExpectedValue = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + /* Decode the Predicate Index value. */ \ + PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + if (!(Pred = checkDecoderPredicate(PIdx, feature))) \ + Ptr += NumToSkip; \ + /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + /* assert(DecodeComplete); */ \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* assert(S == MCDisassembler_Fail); */ \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could \ + * be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + PositiveMask = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ + } FieldFromInstruction(fieldFromInstruction, uint32_t) -DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) -DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) + DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) + DecodeInstruction(decodeInstruction, fieldFromInstruction, + decodeToMCInst, uint32_t) + +#endif // MIPS_GET_DISASSEMBLER +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +#define Mips_AT 1 +#define Mips_DSPCCond 2 +#define Mips_DSPCarry 3 +#define Mips_DSPEFI 4 +#define Mips_DSPOutFlag 5 +#define Mips_DSPPos 6 +#define Mips_DSPSCount 7 +#define Mips_FP 8 +#define Mips_GP 9 +#define Mips_MSAAccess 10 +#define Mips_MSACSR 11 +#define Mips_MSAIR 12 +#define Mips_MSAMap 13 +#define Mips_MSAModify 14 +#define Mips_MSARequest 15 +#define Mips_MSASave 16 +#define Mips_MSAUnmap 17 +#define Mips_PC 18 +#define Mips_RA 19 +#define Mips_SP 20 +#define Mips_ZERO 21 +#define Mips_A0 22 +#define Mips_A1 23 +#define Mips_A2 24 +#define Mips_A3 25 +#define Mips_AC0 26 +#define Mips_AC1 27 +#define Mips_AC2 28 +#define Mips_AC3 29 +#define Mips_AT_64 30 +#define Mips_COP00 31 +#define Mips_COP01 32 +#define Mips_COP02 33 +#define Mips_COP03 34 +#define Mips_COP04 35 +#define Mips_COP05 36 +#define Mips_COP06 37 +#define Mips_COP07 38 +#define Mips_COP08 39 +#define Mips_COP09 40 +#define Mips_COP20 41 +#define Mips_COP21 42 +#define Mips_COP22 43 +#define Mips_COP23 44 +#define Mips_COP24 45 +#define Mips_COP25 46 +#define Mips_COP26 47 +#define Mips_COP27 48 +#define Mips_COP28 49 +#define Mips_COP29 50 +#define Mips_COP30 51 +#define Mips_COP31 52 +#define Mips_COP32 53 +#define Mips_COP33 54 +#define Mips_COP34 55 +#define Mips_COP35 56 +#define Mips_COP36 57 +#define Mips_COP37 58 +#define Mips_COP38 59 +#define Mips_COP39 60 +#define Mips_COP010 61 +#define Mips_COP011 62 +#define Mips_COP012 63 +#define Mips_COP013 64 +#define Mips_COP014 65 +#define Mips_COP015 66 +#define Mips_COP016 67 +#define Mips_COP017 68 +#define Mips_COP018 69 +#define Mips_COP019 70 +#define Mips_COP020 71 +#define Mips_COP021 72 +#define Mips_COP022 73 +#define Mips_COP023 74 +#define Mips_COP024 75 +#define Mips_COP025 76 +#define Mips_COP026 77 +#define Mips_COP027 78 +#define Mips_COP028 79 +#define Mips_COP029 80 +#define Mips_COP030 81 +#define Mips_COP031 82 +#define Mips_COP210 83 +#define Mips_COP211 84 +#define Mips_COP212 85 +#define Mips_COP213 86 +#define Mips_COP214 87 +#define Mips_COP215 88 +#define Mips_COP216 89 +#define Mips_COP217 90 +#define Mips_COP218 91 +#define Mips_COP219 92 +#define Mips_COP220 93 +#define Mips_COP221 94 +#define Mips_COP222 95 +#define Mips_COP223 96 +#define Mips_COP224 97 +#define Mips_COP225 98 +#define Mips_COP226 99 +#define Mips_COP227 100 +#define Mips_COP228 101 +#define Mips_COP229 102 +#define Mips_COP230 103 +#define Mips_COP231 104 +#define Mips_COP310 105 +#define Mips_COP311 106 +#define Mips_COP312 107 +#define Mips_COP313 108 +#define Mips_COP314 109 +#define Mips_COP315 110 +#define Mips_COP316 111 +#define Mips_COP317 112 +#define Mips_COP318 113 +#define Mips_COP319 114 +#define Mips_COP320 115 +#define Mips_COP321 116 +#define Mips_COP322 117 +#define Mips_COP323 118 +#define Mips_COP324 119 +#define Mips_COP325 120 +#define Mips_COP326 121 +#define Mips_COP327 122 +#define Mips_COP328 123 +#define Mips_COP329 124 +#define Mips_COP330 125 +#define Mips_COP331 126 +#define Mips_D0 127 +#define Mips_D1 128 +#define Mips_D2 129 +#define Mips_D3 130 +#define Mips_D4 131 +#define Mips_D5 132 +#define Mips_D6 133 +#define Mips_D7 134 +#define Mips_D8 135 +#define Mips_D9 136 +#define Mips_D10 137 +#define Mips_D11 138 +#define Mips_D12 139 +#define Mips_D13 140 +#define Mips_D14 141 +#define Mips_D15 142 +#define Mips_DSPOutFlag20 143 +#define Mips_DSPOutFlag21 144 +#define Mips_DSPOutFlag22 145 +#define Mips_DSPOutFlag23 146 +#define Mips_F0 147 +#define Mips_F1 148 +#define Mips_F2 149 +#define Mips_F3 150 +#define Mips_F4 151 +#define Mips_F5 152 +#define Mips_F6 153 +#define Mips_F7 154 +#define Mips_F8 155 +#define Mips_F9 156 +#define Mips_F10 157 +#define Mips_F11 158 +#define Mips_F12 159 +#define Mips_F13 160 +#define Mips_F14 161 +#define Mips_F15 162 +#define Mips_F16 163 +#define Mips_F17 164 +#define Mips_F18 165 +#define Mips_F19 166 +#define Mips_F20 167 +#define Mips_F21 168 +#define Mips_F22 169 +#define Mips_F23 170 +#define Mips_F24 171 +#define Mips_F25 172 +#define Mips_F26 173 +#define Mips_F27 174 +#define Mips_F28 175 +#define Mips_F29 176 +#define Mips_F30 177 +#define Mips_F31 178 +#define Mips_FCC0 179 +#define Mips_FCC1 180 +#define Mips_FCC2 181 +#define Mips_FCC3 182 +#define Mips_FCC4 183 +#define Mips_FCC5 184 +#define Mips_FCC6 185 +#define Mips_FCC7 186 +#define Mips_FCR0 187 +#define Mips_FCR1 188 +#define Mips_FCR2 189 +#define Mips_FCR3 190 +#define Mips_FCR4 191 +#define Mips_FCR5 192 +#define Mips_FCR6 193 +#define Mips_FCR7 194 +#define Mips_FCR8 195 +#define Mips_FCR9 196 +#define Mips_FCR10 197 +#define Mips_FCR11 198 +#define Mips_FCR12 199 +#define Mips_FCR13 200 +#define Mips_FCR14 201 +#define Mips_FCR15 202 +#define Mips_FCR16 203 +#define Mips_FCR17 204 +#define Mips_FCR18 205 +#define Mips_FCR19 206 +#define Mips_FCR20 207 +#define Mips_FCR21 208 +#define Mips_FCR22 209 +#define Mips_FCR23 210 +#define Mips_FCR24 211 +#define Mips_FCR25 212 +#define Mips_FCR26 213 +#define Mips_FCR27 214 +#define Mips_FCR28 215 +#define Mips_FCR29 216 +#define Mips_FCR30 217 +#define Mips_FCR31 218 +#define Mips_FP_64 219 +#define Mips_F_HI0 220 +#define Mips_F_HI1 221 +#define Mips_F_HI2 222 +#define Mips_F_HI3 223 +#define Mips_F_HI4 224 +#define Mips_F_HI5 225 +#define Mips_F_HI6 226 +#define Mips_F_HI7 227 +#define Mips_F_HI8 228 +#define Mips_F_HI9 229 +#define Mips_F_HI10 230 +#define Mips_F_HI11 231 +#define Mips_F_HI12 232 +#define Mips_F_HI13 233 +#define Mips_F_HI14 234 +#define Mips_F_HI15 235 +#define Mips_F_HI16 236 +#define Mips_F_HI17 237 +#define Mips_F_HI18 238 +#define Mips_F_HI19 239 +#define Mips_F_HI20 240 +#define Mips_F_HI21 241 +#define Mips_F_HI22 242 +#define Mips_F_HI23 243 +#define Mips_F_HI24 244 +#define Mips_F_HI25 245 +#define Mips_F_HI26 246 +#define Mips_F_HI27 247 +#define Mips_F_HI28 248 +#define Mips_F_HI29 249 +#define Mips_F_HI30 250 +#define Mips_F_HI31 251 +#define Mips_GP_64 252 +#define Mips_HI0 253 +#define Mips_HI1 254 +#define Mips_HI2 255 +#define Mips_HI3 256 +#define Mips_HWR0 257 +#define Mips_HWR1 258 +#define Mips_HWR2 259 +#define Mips_HWR3 260 +#define Mips_HWR4 261 +#define Mips_HWR5 262 +#define Mips_HWR6 263 +#define Mips_HWR7 264 +#define Mips_HWR8 265 +#define Mips_HWR9 266 +#define Mips_HWR10 267 +#define Mips_HWR11 268 +#define Mips_HWR12 269 +#define Mips_HWR13 270 +#define Mips_HWR14 271 +#define Mips_HWR15 272 +#define Mips_HWR16 273 +#define Mips_HWR17 274 +#define Mips_HWR18 275 +#define Mips_HWR19 276 +#define Mips_HWR20 277 +#define Mips_HWR21 278 +#define Mips_HWR22 279 +#define Mips_HWR23 280 +#define Mips_HWR24 281 +#define Mips_HWR25 282 +#define Mips_HWR26 283 +#define Mips_HWR27 284 +#define Mips_HWR28 285 +#define Mips_HWR29 286 +#define Mips_HWR30 287 +#define Mips_HWR31 288 +#define Mips_K0 289 +#define Mips_K1 290 +#define Mips_LO0 291 +#define Mips_LO1 292 +#define Mips_LO2 293 +#define Mips_LO3 294 +#define Mips_MPL0 295 +#define Mips_MPL1 296 +#define Mips_MPL2 297 +#define Mips_MSA8 298 +#define Mips_MSA9 299 +#define Mips_MSA10 300 +#define Mips_MSA11 301 +#define Mips_MSA12 302 +#define Mips_MSA13 303 +#define Mips_MSA14 304 +#define Mips_MSA15 305 +#define Mips_MSA16 306 +#define Mips_MSA17 307 +#define Mips_MSA18 308 +#define Mips_MSA19 309 +#define Mips_MSA20 310 +#define Mips_MSA21 311 +#define Mips_MSA22 312 +#define Mips_MSA23 313 +#define Mips_MSA24 314 +#define Mips_MSA25 315 +#define Mips_MSA26 316 +#define Mips_MSA27 317 +#define Mips_MSA28 318 +#define Mips_MSA29 319 +#define Mips_MSA30 320 +#define Mips_MSA31 321 +#define Mips_P0 322 +#define Mips_P1 323 +#define Mips_P2 324 +#define Mips_RA_64 325 +#define Mips_S0 326 +#define Mips_S1 327 +#define Mips_S2 328 +#define Mips_S3 329 +#define Mips_S4 330 +#define Mips_S5 331 +#define Mips_S6 332 +#define Mips_S7 333 +#define Mips_SP_64 334 +#define Mips_T0 335 +#define Mips_T1 336 +#define Mips_T2 337 +#define Mips_T3 338 +#define Mips_T4 339 +#define Mips_T5 340 +#define Mips_T6 341 +#define Mips_T7 342 +#define Mips_T8 343 +#define Mips_T9 344 +#define Mips_V0 345 +#define Mips_V1 346 +#define Mips_W0 347 +#define Mips_W1 348 +#define Mips_W2 349 +#define Mips_W3 350 +#define Mips_W4 351 +#define Mips_W5 352 +#define Mips_W6 353 +#define Mips_W7 354 +#define Mips_W8 355 +#define Mips_W9 356 +#define Mips_W10 357 +#define Mips_W11 358 +#define Mips_W12 359 +#define Mips_W13 360 +#define Mips_W14 361 +#define Mips_W15 362 +#define Mips_W16 363 +#define Mips_W17 364 +#define Mips_W18 365 +#define Mips_W19 366 +#define Mips_W20 367 +#define Mips_W21 368 +#define Mips_W22 369 +#define Mips_W23 370 +#define Mips_W24 371 +#define Mips_W25 372 +#define Mips_W26 373 +#define Mips_W27 374 +#define Mips_W28 375 +#define Mips_W29 376 +#define Mips_W30 377 +#define Mips_W31 378 +#define Mips_ZERO_64 379 +#define Mips_A0_64 380 +#define Mips_A1_64 381 +#define Mips_A2_64 382 +#define Mips_A3_64 383 +#define Mips_AC0_64 384 +#define Mips_D0_64 385 +#define Mips_D1_64 386 +#define Mips_D2_64 387 +#define Mips_D3_64 388 +#define Mips_D4_64 389 +#define Mips_D5_64 390 +#define Mips_D6_64 391 +#define Mips_D7_64 392 +#define Mips_D8_64 393 +#define Mips_D9_64 394 +#define Mips_D10_64 395 +#define Mips_D11_64 396 +#define Mips_D12_64 397 +#define Mips_D13_64 398 +#define Mips_D14_64 399 +#define Mips_D15_64 400 +#define Mips_D16_64 401 +#define Mips_D17_64 402 +#define Mips_D18_64 403 +#define Mips_D19_64 404 +#define Mips_D20_64 405 +#define Mips_D21_64 406 +#define Mips_D22_64 407 +#define Mips_D23_64 408 +#define Mips_D24_64 409 +#define Mips_D25_64 410 +#define Mips_D26_64 411 +#define Mips_D27_64 412 +#define Mips_D28_64 413 +#define Mips_D29_64 414 +#define Mips_D30_64 415 +#define Mips_D31_64 416 +#define Mips_DSPOutFlag16_19 417 +#define Mips_HI0_64 418 +#define Mips_K0_64 419 +#define Mips_K1_64 420 +#define Mips_LO0_64 421 +#define Mips_S0_64 422 +#define Mips_S1_64 423 +#define Mips_S2_64 424 +#define Mips_S3_64 425 +#define Mips_S4_64 426 +#define Mips_S5_64 427 +#define Mips_S6_64 428 +#define Mips_S7_64 429 +#define Mips_T0_64 430 +#define Mips_T1_64 431 +#define Mips_T2_64 432 +#define Mips_T3_64 433 +#define Mips_T4_64 434 +#define Mips_T5_64 435 +#define Mips_T6_64 436 +#define Mips_T7_64 437 +#define Mips_T8_64 438 +#define Mips_T9_64 439 +#define Mips_V0_64 440 +#define Mips_V1_64 441 +#define Mips_NUM_TARGET_REGS 442 + +// Register classes + +#define Mips_MSA128F16RegClassID 0 +#define Mips_CCRRegClassID 1 +#define Mips_COP0RegClassID 2 +#define Mips_COP2RegClassID 3 +#define Mips_COP3RegClassID 4 +#define Mips_DSPRRegClassID 5 +#define Mips_FGR32RegClassID 6 +#define Mips_FGRCCRegClassID 7 +#define Mips_GPR32RegClassID 8 +#define Mips_HWRegsRegClassID 9 +#define Mips_MSACtrlRegClassID 10 +#define Mips_GPR32NONZERORegClassID 11 +#define Mips_CPU16RegsPlusSPRegClassID 12 +#define Mips_CPU16RegsRegClassID 13 +#define Mips_FCCRegClassID 14 +#define Mips_GPRMM16RegClassID 15 +#define Mips_GPRMM16MovePRegClassID 16 +#define Mips_GPRMM16ZeroRegClassID 17 +#define Mips_CPU16Regs_and_GPRMM16ZeroRegClassID 18 +#define Mips_GPR32NONZERO_and_GPRMM16MovePRegClassID 19 +#define Mips_GPRMM16MovePPairSecondRegClassID 20 +#define Mips_CPU16Regs_and_GPRMM16MovePRegClassID 21 +#define Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID 22 +#define Mips_HI32DSPRegClassID 23 +#define Mips_LO32DSPRegClassID 24 +#define Mips_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID 25 +#define Mips_GPRMM16MovePPairFirstRegClassID 26 +#define Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID 27 +#define Mips_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID 28 +#define Mips_CPURARegRegClassID 29 +#define Mips_CPUSPRegRegClassID 30 +#define Mips_DSPCCRegClassID 31 +#define Mips_GP32RegClassID 32 +#define Mips_GPR32ZERORegClassID 33 +#define Mips_HI32RegClassID 34 +#define Mips_LO32RegClassID 35 +#define Mips_SP32RegClassID 36 +#define Mips_FGR64RegClassID 37 +#define Mips_GPR64RegClassID 38 +#define Mips_GPR64_with_sub_32_in_GPR32NONZERORegClassID 39 +#define Mips_AFGR64RegClassID 40 +#define Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID 41 +#define Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID 42 +#define Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID 43 +#define Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID 44 +#define Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID 45 +#define Mips_GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID 46 +#define Mips_GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID 47 +#define Mips_ACC64DSPRegClassID 48 +#define Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID 49 +#define Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID 50 +#define Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID \ + 51 +#define Mips_GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID 52 +#define Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID \ + 53 +#define Mips_OCTEON_MPLRegClassID 54 +#define Mips_OCTEON_PRegClassID 55 +#define Mips_GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID \ + 56 +#define Mips_ACC64RegClassID 57 +#define Mips_GP64RegClassID 58 +#define Mips_GPR64_with_sub_32_in_CPURARegRegClassID 59 +#define Mips_GPR64_with_sub_32_in_GPR32ZERORegClassID 60 +#define Mips_HI64RegClassID 61 +#define Mips_LO64RegClassID 62 +#define Mips_SP64RegClassID 63 +#define Mips_MSA128BRegClassID 64 +#define Mips_MSA128DRegClassID 65 +#define Mips_MSA128HRegClassID 66 +#define Mips_MSA128WRegClassID 67 +#define Mips_MSA128WEvensRegClassID 68 +#define Mips_ACC128RegClassID 69 + +#endif // GET_REGINFO_ENUM + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM +#define Mips_PHI 0 +#define Mips_INLINEASM 1 +#define Mips_INLINEASM_BR 2 +#define Mips_CFI_INSTRUCTION 3 +#define Mips_EH_LABEL 4 +#define Mips_GC_LABEL 5 +#define Mips_ANNOTATION_LABEL 6 +#define Mips_KILL 7 +#define Mips_EXTRACT_SUBREG 8 +#define Mips_INSERT_SUBREG 9 +#define Mips_IMPLICIT_DEF 10 +#define Mips_SUBREG_TO_REG 11 +#define Mips_COPY_TO_REGCLASS 12 +#define Mips_DBG_VALUE 13 +#define Mips_DBG_VALUE_LIST 14 +#define Mips_DBG_INSTR_REF 15 +#define Mips_DBG_PHI 16 +#define Mips_DBG_LABEL 17 +#define Mips_REG_SEQUENCE 18 +#define Mips_COPY 19 +#define Mips_BUNDLE 20 +#define Mips_LIFETIME_START 21 +#define Mips_LIFETIME_END 22 +#define Mips_PSEUDO_PROBE 23 +#define Mips_ARITH_FENCE 24 +#define Mips_STACKMAP 25 +#define Mips_FENTRY_CALL 26 +#define Mips_PATCHPOINT 27 +#define Mips_LOAD_STACK_GUARD 28 +#define Mips_PREALLOCATED_SETUP 29 +#define Mips_PREALLOCATED_ARG 30 +#define Mips_STATEPOINT 31 +#define Mips_LOCAL_ESCAPE 32 +#define Mips_FAULTING_OP 33 +#define Mips_PATCHABLE_OP 34 +#define Mips_PATCHABLE_FUNCTION_ENTER 35 +#define Mips_PATCHABLE_RET 36 +#define Mips_PATCHABLE_FUNCTION_EXIT 37 +#define Mips_PATCHABLE_TAIL_CALL 38 +#define Mips_PATCHABLE_EVENT_CALL 39 +#define Mips_PATCHABLE_TYPED_EVENT_CALL 40 +#define Mips_ICALL_BRANCH_FUNNEL 41 +#define Mips_G_ASSERT_SEXT 42 +#define Mips_G_ASSERT_ZEXT 43 +#define Mips_G_ADD 44 +#define Mips_G_SUB 45 +#define Mips_G_MUL 46 +#define Mips_G_SDIV 47 +#define Mips_G_UDIV 48 +#define Mips_G_SREM 49 +#define Mips_G_UREM 50 +#define Mips_G_SDIVREM 51 +#define Mips_G_UDIVREM 52 +#define Mips_G_AND 53 +#define Mips_G_OR 54 +#define Mips_G_XOR 55 +#define Mips_G_IMPLICIT_DEF 56 +#define Mips_G_PHI 57 +#define Mips_G_FRAME_INDEX 58 +#define Mips_G_GLOBAL_VALUE 59 +#define Mips_G_EXTRACT 60 +#define Mips_G_UNMERGE_VALUES 61 +#define Mips_G_INSERT 62 +#define Mips_G_MERGE_VALUES 63 +#define Mips_G_BUILD_VECTOR 64 +#define Mips_G_BUILD_VECTOR_TRUNC 65 +#define Mips_G_CONCAT_VECTORS 66 +#define Mips_G_PTRTOINT 67 +#define Mips_G_INTTOPTR 68 +#define Mips_G_BITCAST 69 +#define Mips_G_FREEZE 70 +#define Mips_G_INTRINSIC_TRUNC 71 +#define Mips_G_INTRINSIC_ROUND 72 +#define Mips_G_INTRINSIC_LRINT 73 +#define Mips_G_INTRINSIC_ROUNDEVEN 74 +#define Mips_G_READCYCLECOUNTER 75 +#define Mips_G_LOAD 76 +#define Mips_G_SEXTLOAD 77 +#define Mips_G_ZEXTLOAD 78 +#define Mips_G_INDEXED_LOAD 79 +#define Mips_G_INDEXED_SEXTLOAD 80 +#define Mips_G_INDEXED_ZEXTLOAD 81 +#define Mips_G_STORE 82 +#define Mips_G_INDEXED_STORE 83 +#define Mips_G_ATOMIC_CMPXCHG_WITH_SUCCESS 84 +#define Mips_G_ATOMIC_CMPXCHG 85 +#define Mips_G_ATOMICRMW_XCHG 86 +#define Mips_G_ATOMICRMW_ADD 87 +#define Mips_G_ATOMICRMW_SUB 88 +#define Mips_G_ATOMICRMW_AND 89 +#define Mips_G_ATOMICRMW_NAND 90 +#define Mips_G_ATOMICRMW_OR 91 +#define Mips_G_ATOMICRMW_XOR 92 +#define Mips_G_ATOMICRMW_MAX 93 +#define Mips_G_ATOMICRMW_MIN 94 +#define Mips_G_ATOMICRMW_UMAX 95 +#define Mips_G_ATOMICRMW_UMIN 96 +#define Mips_G_ATOMICRMW_FADD 97 +#define Mips_G_ATOMICRMW_FSUB 98 +#define Mips_G_FENCE 99 +#define Mips_G_BRCOND 100 +#define Mips_G_BRINDIRECT 101 +#define Mips_G_INTRINSIC 102 +#define Mips_G_INTRINSIC_W_SIDE_EFFECTS 103 +#define Mips_G_ANYEXT 104 +#define Mips_G_TRUNC 105 +#define Mips_G_CONSTANT 106 +#define Mips_G_FCONSTANT 107 +#define Mips_G_VASTART 108 +#define Mips_G_VAARG 109 +#define Mips_G_SEXT 110 +#define Mips_G_SEXT_INREG 111 +#define Mips_G_ZEXT 112 +#define Mips_G_SHL 113 +#define Mips_G_LSHR 114 +#define Mips_G_ASHR 115 +#define Mips_G_FSHL 116 +#define Mips_G_FSHR 117 +#define Mips_G_ROTR 118 +#define Mips_G_ROTL 119 +#define Mips_G_ICMP 120 +#define Mips_G_FCMP 121 +#define Mips_G_SELECT 122 +#define Mips_G_UADDO 123 +#define Mips_G_UADDE 124 +#define Mips_G_USUBO 125 +#define Mips_G_USUBE 126 +#define Mips_G_SADDO 127 +#define Mips_G_SADDE 128 +#define Mips_G_SSUBO 129 +#define Mips_G_SSUBE 130 +#define Mips_G_UMULO 131 +#define Mips_G_SMULO 132 +#define Mips_G_UMULH 133 +#define Mips_G_SMULH 134 +#define Mips_G_UADDSAT 135 +#define Mips_G_SADDSAT 136 +#define Mips_G_USUBSAT 137 +#define Mips_G_SSUBSAT 138 +#define Mips_G_USHLSAT 139 +#define Mips_G_SSHLSAT 140 +#define Mips_G_SMULFIX 141 +#define Mips_G_UMULFIX 142 +#define Mips_G_SMULFIXSAT 143 +#define Mips_G_UMULFIXSAT 144 +#define Mips_G_SDIVFIX 145 +#define Mips_G_UDIVFIX 146 +#define Mips_G_SDIVFIXSAT 147 +#define Mips_G_UDIVFIXSAT 148 +#define Mips_G_FADD 149 +#define Mips_G_FSUB 150 +#define Mips_G_FMUL 151 +#define Mips_G_FMA 152 +#define Mips_G_FMAD 153 +#define Mips_G_FDIV 154 +#define Mips_G_FREM 155 +#define Mips_G_FPOW 156 +#define Mips_G_FPOWI 157 +#define Mips_G_FEXP 158 +#define Mips_G_FEXP2 159 +#define Mips_G_FLOG 160 +#define Mips_G_FLOG2 161 +#define Mips_G_FLOG10 162 +#define Mips_G_FNEG 163 +#define Mips_G_FPEXT 164 +#define Mips_G_FPTRUNC 165 +#define Mips_G_FPTOSI 166 +#define Mips_G_FPTOUI 167 +#define Mips_G_SITOFP 168 +#define Mips_G_UITOFP 169 +#define Mips_G_FABS 170 +#define Mips_G_FCOPYSIGN 171 +#define Mips_G_FCANONICALIZE 172 +#define Mips_G_FMINNUM 173 +#define Mips_G_FMAXNUM 174 +#define Mips_G_FMINNUM_IEEE 175 +#define Mips_G_FMAXNUM_IEEE 176 +#define Mips_G_FMINIMUM 177 +#define Mips_G_FMAXIMUM 178 +#define Mips_G_PTR_ADD 179 +#define Mips_G_PTRMASK 180 +#define Mips_G_SMIN 181 +#define Mips_G_SMAX 182 +#define Mips_G_UMIN 183 +#define Mips_G_UMAX 184 +#define Mips_G_ABS 185 +#define Mips_G_LROUND 186 +#define Mips_G_LLROUND 187 +#define Mips_G_BR 188 +#define Mips_G_BRJT 189 +#define Mips_G_INSERT_VECTOR_ELT 190 +#define Mips_G_EXTRACT_VECTOR_ELT 191 +#define Mips_G_SHUFFLE_VECTOR 192 +#define Mips_G_CTTZ 193 +#define Mips_G_CTTZ_ZERO_UNDEF 194 +#define Mips_G_CTLZ 195 +#define Mips_G_CTLZ_ZERO_UNDEF 196 +#define Mips_G_CTPOP 197 +#define Mips_G_BSWAP 198 +#define Mips_G_BITREVERSE 199 +#define Mips_G_FCEIL 200 +#define Mips_G_FCOS 201 +#define Mips_G_FSIN 202 +#define Mips_G_FSQRT 203 +#define Mips_G_FFLOOR 204 +#define Mips_G_FRINT 205 +#define Mips_G_FNEARBYINT 206 +#define Mips_G_ADDRSPACE_CAST 207 +#define Mips_G_BLOCK_ADDR 208 +#define Mips_G_JUMP_TABLE 209 +#define Mips_G_DYN_STACKALLOC 210 +#define Mips_G_STRICT_FADD 211 +#define Mips_G_STRICT_FSUB 212 +#define Mips_G_STRICT_FMUL 213 +#define Mips_G_STRICT_FDIV 214 +#define Mips_G_STRICT_FREM 215 +#define Mips_G_STRICT_FMA 216 +#define Mips_G_STRICT_FSQRT 217 +#define Mips_G_READ_REGISTER 218 +#define Mips_G_WRITE_REGISTER 219 +#define Mips_G_MEMCPY 220 +#define Mips_G_MEMCPY_INLINE 221 +#define Mips_G_MEMMOVE 222 +#define Mips_G_MEMSET 223 +#define Mips_G_BZERO 224 +#define Mips_G_VECREDUCE_SEQ_FADD 225 +#define Mips_G_VECREDUCE_SEQ_FMUL 226 +#define Mips_G_VECREDUCE_FADD 227 +#define Mips_G_VECREDUCE_FMUL 228 +#define Mips_G_VECREDUCE_FMAX 229 +#define Mips_G_VECREDUCE_FMIN 230 +#define Mips_G_VECREDUCE_ADD 231 +#define Mips_G_VECREDUCE_MUL 232 +#define Mips_G_VECREDUCE_AND 233 +#define Mips_G_VECREDUCE_OR 234 +#define Mips_G_VECREDUCE_XOR 235 +#define Mips_G_VECREDUCE_SMAX 236 +#define Mips_G_VECREDUCE_SMIN 237 +#define Mips_G_VECREDUCE_UMAX 238 +#define Mips_G_VECREDUCE_UMIN 239 +#define Mips_G_SBFX 240 +#define Mips_G_UBFX 241 +#define Mips_ABSMacro 242 +#define Mips_ADJCALLSTACKDOWN 243 +#define Mips_ADJCALLSTACKUP 244 +#define Mips_AND_V_D_PSEUDO 245 +#define Mips_AND_V_H_PSEUDO 246 +#define Mips_AND_V_W_PSEUDO 247 +#define Mips_ATOMIC_CMP_SWAP_I16 248 +#define Mips_ATOMIC_CMP_SWAP_I16_POSTRA 249 +#define Mips_ATOMIC_CMP_SWAP_I32 250 +#define Mips_ATOMIC_CMP_SWAP_I32_POSTRA 251 +#define Mips_ATOMIC_CMP_SWAP_I64 252 +#define Mips_ATOMIC_CMP_SWAP_I64_POSTRA 253 +#define Mips_ATOMIC_CMP_SWAP_I8 254 +#define Mips_ATOMIC_CMP_SWAP_I8_POSTRA 255 +#define Mips_ATOMIC_LOAD_ADD_I16 256 +#define Mips_ATOMIC_LOAD_ADD_I16_POSTRA 257 +#define Mips_ATOMIC_LOAD_ADD_I32 258 +#define Mips_ATOMIC_LOAD_ADD_I32_POSTRA 259 +#define Mips_ATOMIC_LOAD_ADD_I64 260 +#define Mips_ATOMIC_LOAD_ADD_I64_POSTRA 261 +#define Mips_ATOMIC_LOAD_ADD_I8 262 +#define Mips_ATOMIC_LOAD_ADD_I8_POSTRA 263 +#define Mips_ATOMIC_LOAD_AND_I16 264 +#define Mips_ATOMIC_LOAD_AND_I16_POSTRA 265 +#define Mips_ATOMIC_LOAD_AND_I32 266 +#define Mips_ATOMIC_LOAD_AND_I32_POSTRA 267 +#define Mips_ATOMIC_LOAD_AND_I64 268 +#define Mips_ATOMIC_LOAD_AND_I64_POSTRA 269 +#define Mips_ATOMIC_LOAD_AND_I8 270 +#define Mips_ATOMIC_LOAD_AND_I8_POSTRA 271 +#define Mips_ATOMIC_LOAD_MAX_I16 272 +#define Mips_ATOMIC_LOAD_MAX_I16_POSTRA 273 +#define Mips_ATOMIC_LOAD_MAX_I32 274 +#define Mips_ATOMIC_LOAD_MAX_I32_POSTRA 275 +#define Mips_ATOMIC_LOAD_MAX_I64 276 +#define Mips_ATOMIC_LOAD_MAX_I64_POSTRA 277 +#define Mips_ATOMIC_LOAD_MAX_I8 278 +#define Mips_ATOMIC_LOAD_MAX_I8_POSTRA 279 +#define Mips_ATOMIC_LOAD_MIN_I16 280 +#define Mips_ATOMIC_LOAD_MIN_I16_POSTRA 281 +#define Mips_ATOMIC_LOAD_MIN_I32 282 +#define Mips_ATOMIC_LOAD_MIN_I32_POSTRA 283 +#define Mips_ATOMIC_LOAD_MIN_I64 284 +#define Mips_ATOMIC_LOAD_MIN_I64_POSTRA 285 +#define Mips_ATOMIC_LOAD_MIN_I8 286 +#define Mips_ATOMIC_LOAD_MIN_I8_POSTRA 287 +#define Mips_ATOMIC_LOAD_NAND_I16 288 +#define Mips_ATOMIC_LOAD_NAND_I16_POSTRA 289 +#define Mips_ATOMIC_LOAD_NAND_I32 290 +#define Mips_ATOMIC_LOAD_NAND_I32_POSTRA 291 +#define Mips_ATOMIC_LOAD_NAND_I64 292 +#define Mips_ATOMIC_LOAD_NAND_I64_POSTRA 293 +#define Mips_ATOMIC_LOAD_NAND_I8 294 +#define Mips_ATOMIC_LOAD_NAND_I8_POSTRA 295 +#define Mips_ATOMIC_LOAD_OR_I16 296 +#define Mips_ATOMIC_LOAD_OR_I16_POSTRA 297 +#define Mips_ATOMIC_LOAD_OR_I32 298 +#define Mips_ATOMIC_LOAD_OR_I32_POSTRA 299 +#define Mips_ATOMIC_LOAD_OR_I64 300 +#define Mips_ATOMIC_LOAD_OR_I64_POSTRA 301 +#define Mips_ATOMIC_LOAD_OR_I8 302 +#define Mips_ATOMIC_LOAD_OR_I8_POSTRA 303 +#define Mips_ATOMIC_LOAD_SUB_I16 304 +#define Mips_ATOMIC_LOAD_SUB_I16_POSTRA 305 +#define Mips_ATOMIC_LOAD_SUB_I32 306 +#define Mips_ATOMIC_LOAD_SUB_I32_POSTRA 307 +#define Mips_ATOMIC_LOAD_SUB_I64 308 +#define Mips_ATOMIC_LOAD_SUB_I64_POSTRA 309 +#define Mips_ATOMIC_LOAD_SUB_I8 310 +#define Mips_ATOMIC_LOAD_SUB_I8_POSTRA 311 +#define Mips_ATOMIC_LOAD_UMAX_I16 312 +#define Mips_ATOMIC_LOAD_UMAX_I16_POSTRA 313 +#define Mips_ATOMIC_LOAD_UMAX_I32 314 +#define Mips_ATOMIC_LOAD_UMAX_I32_POSTRA 315 +#define Mips_ATOMIC_LOAD_UMAX_I64 316 +#define Mips_ATOMIC_LOAD_UMAX_I64_POSTRA 317 +#define Mips_ATOMIC_LOAD_UMAX_I8 318 +#define Mips_ATOMIC_LOAD_UMAX_I8_POSTRA 319 +#define Mips_ATOMIC_LOAD_UMIN_I16 320 +#define Mips_ATOMIC_LOAD_UMIN_I16_POSTRA 321 +#define Mips_ATOMIC_LOAD_UMIN_I32 322 +#define Mips_ATOMIC_LOAD_UMIN_I32_POSTRA 323 +#define Mips_ATOMIC_LOAD_UMIN_I64 324 +#define Mips_ATOMIC_LOAD_UMIN_I64_POSTRA 325 +#define Mips_ATOMIC_LOAD_UMIN_I8 326 +#define Mips_ATOMIC_LOAD_UMIN_I8_POSTRA 327 +#define Mips_ATOMIC_LOAD_XOR_I16 328 +#define Mips_ATOMIC_LOAD_XOR_I16_POSTRA 329 +#define Mips_ATOMIC_LOAD_XOR_I32 330 +#define Mips_ATOMIC_LOAD_XOR_I32_POSTRA 331 +#define Mips_ATOMIC_LOAD_XOR_I64 332 +#define Mips_ATOMIC_LOAD_XOR_I64_POSTRA 333 +#define Mips_ATOMIC_LOAD_XOR_I8 334 +#define Mips_ATOMIC_LOAD_XOR_I8_POSTRA 335 +#define Mips_ATOMIC_SWAP_I16 336 +#define Mips_ATOMIC_SWAP_I16_POSTRA 337 +#define Mips_ATOMIC_SWAP_I32 338 +#define Mips_ATOMIC_SWAP_I32_POSTRA 339 +#define Mips_ATOMIC_SWAP_I64 340 +#define Mips_ATOMIC_SWAP_I64_POSTRA 341 +#define Mips_ATOMIC_SWAP_I8 342 +#define Mips_ATOMIC_SWAP_I8_POSTRA 343 +#define Mips_B 344 +#define Mips_BAL_BR 345 +#define Mips_BAL_BR_MM 346 +#define Mips_BEQLImmMacro 347 +#define Mips_BGE 348 +#define Mips_BGEImmMacro 349 +#define Mips_BGEL 350 +#define Mips_BGELImmMacro 351 +#define Mips_BGEU 352 +#define Mips_BGEUImmMacro 353 +#define Mips_BGEUL 354 +#define Mips_BGEULImmMacro 355 +#define Mips_BGT 356 +#define Mips_BGTImmMacro 357 +#define Mips_BGTL 358 +#define Mips_BGTLImmMacro 359 +#define Mips_BGTU 360 +#define Mips_BGTUImmMacro 361 +#define Mips_BGTUL 362 +#define Mips_BGTULImmMacro 363 +#define Mips_BLE 364 +#define Mips_BLEImmMacro 365 +#define Mips_BLEL 366 +#define Mips_BLELImmMacro 367 +#define Mips_BLEU 368 +#define Mips_BLEUImmMacro 369 +#define Mips_BLEUL 370 +#define Mips_BLEULImmMacro 371 +#define Mips_BLT 372 +#define Mips_BLTImmMacro 373 +#define Mips_BLTL 374 +#define Mips_BLTLImmMacro 375 +#define Mips_BLTU 376 +#define Mips_BLTUImmMacro 377 +#define Mips_BLTUL 378 +#define Mips_BLTULImmMacro 379 +#define Mips_BNELImmMacro 380 +#define Mips_BPOSGE32_PSEUDO 381 +#define Mips_BSEL_D_PSEUDO 382 +#define Mips_BSEL_FD_PSEUDO 383 +#define Mips_BSEL_FW_PSEUDO 384 +#define Mips_BSEL_H_PSEUDO 385 +#define Mips_BSEL_W_PSEUDO 386 +#define Mips_B_MM 387 +#define Mips_B_MMR6_Pseudo 388 +#define Mips_B_MM_Pseudo 389 +#define Mips_BeqImm 390 +#define Mips_BneImm 391 +#define Mips_BteqzT8CmpX16 392 +#define Mips_BteqzT8CmpiX16 393 +#define Mips_BteqzT8SltX16 394 +#define Mips_BteqzT8SltiX16 395 +#define Mips_BteqzT8SltiuX16 396 +#define Mips_BteqzT8SltuX16 397 +#define Mips_BtnezT8CmpX16 398 +#define Mips_BtnezT8CmpiX16 399 +#define Mips_BtnezT8SltX16 400 +#define Mips_BtnezT8SltiX16 401 +#define Mips_BtnezT8SltiuX16 402 +#define Mips_BtnezT8SltuX16 403 +#define Mips_BuildPairF64 404 +#define Mips_BuildPairF64_64 405 +#define Mips_CFTC1 406 +#define Mips_CONSTPOOL_ENTRY 407 +#define Mips_COPY_FD_PSEUDO 408 +#define Mips_COPY_FW_PSEUDO 409 +#define Mips_CTTC1 410 +#define Mips_Constant32 411 +#define Mips_DMULImmMacro 412 +#define Mips_DMULMacro 413 +#define Mips_DMULOMacro 414 +#define Mips_DMULOUMacro 415 +#define Mips_DROL 416 +#define Mips_DROLImm 417 +#define Mips_DROR 418 +#define Mips_DRORImm 419 +#define Mips_DSDivIMacro 420 +#define Mips_DSDivMacro 421 +#define Mips_DSRemIMacro 422 +#define Mips_DSRemMacro 423 +#define Mips_DUDivIMacro 424 +#define Mips_DUDivMacro 425 +#define Mips_DURemIMacro 426 +#define Mips_DURemMacro 427 +#define Mips_ERet 428 +#define Mips_ExtractElementF64 429 +#define Mips_ExtractElementF64_64 430 +#define Mips_FABS_D 431 +#define Mips_FABS_W 432 +#define Mips_FEXP2_D_1_PSEUDO 433 +#define Mips_FEXP2_W_1_PSEUDO 434 +#define Mips_FILL_FD_PSEUDO 435 +#define Mips_FILL_FW_PSEUDO 436 +#define Mips_GotPrologue16 437 +#define Mips_INSERT_B_VIDX64_PSEUDO 438 +#define Mips_INSERT_B_VIDX_PSEUDO 439 +#define Mips_INSERT_D_VIDX64_PSEUDO 440 +#define Mips_INSERT_D_VIDX_PSEUDO 441 +#define Mips_INSERT_FD_PSEUDO 442 +#define Mips_INSERT_FD_VIDX64_PSEUDO 443 +#define Mips_INSERT_FD_VIDX_PSEUDO 444 +#define Mips_INSERT_FW_PSEUDO 445 +#define Mips_INSERT_FW_VIDX64_PSEUDO 446 +#define Mips_INSERT_FW_VIDX_PSEUDO 447 +#define Mips_INSERT_H_VIDX64_PSEUDO 448 +#define Mips_INSERT_H_VIDX_PSEUDO 449 +#define Mips_INSERT_W_VIDX64_PSEUDO 450 +#define Mips_INSERT_W_VIDX_PSEUDO 451 +#define Mips_JALR64Pseudo 452 +#define Mips_JALRHB64Pseudo 453 +#define Mips_JALRHBPseudo 454 +#define Mips_JALRPseudo 455 +#define Mips_JAL_MMR6 456 +#define Mips_JalOneReg 457 +#define Mips_JalTwoReg 458 +#define Mips_LDMacro 459 +#define Mips_LDR_D 460 +#define Mips_LDR_W 461 +#define Mips_LD_F16 462 +#define Mips_LOAD_ACC128 463 +#define Mips_LOAD_ACC64 464 +#define Mips_LOAD_ACC64DSP 465 +#define Mips_LOAD_CCOND_DSP 466 +#define Mips_LONG_BRANCH_ADDiu 467 +#define Mips_LONG_BRANCH_ADDiu2Op 468 +#define Mips_LONG_BRANCH_DADDiu 469 +#define Mips_LONG_BRANCH_DADDiu2Op 470 +#define Mips_LONG_BRANCH_LUi 471 +#define Mips_LONG_BRANCH_LUi2Op 472 +#define Mips_LONG_BRANCH_LUi2Op_64 473 +#define Mips_LWM_MM 474 +#define Mips_LoadAddrImm32 475 +#define Mips_LoadAddrImm64 476 +#define Mips_LoadAddrReg32 477 +#define Mips_LoadAddrReg64 478 +#define Mips_LoadImm32 479 +#define Mips_LoadImm64 480 +#define Mips_LoadImmDoubleFGR 481 +#define Mips_LoadImmDoubleFGR_32 482 +#define Mips_LoadImmDoubleGPR 483 +#define Mips_LoadImmSingleFGR 484 +#define Mips_LoadImmSingleGPR 485 +#define Mips_LwConstant32 486 +#define Mips_MFTACX 487 +#define Mips_MFTC0 488 +#define Mips_MFTC1 489 +#define Mips_MFTDSP 490 +#define Mips_MFTGPR 491 +#define Mips_MFTHC1 492 +#define Mips_MFTHI 493 +#define Mips_MFTLO 494 +#define Mips_MIPSeh_return32 495 +#define Mips_MIPSeh_return64 496 +#define Mips_MSA_FP_EXTEND_D_PSEUDO 497 +#define Mips_MSA_FP_EXTEND_W_PSEUDO 498 +#define Mips_MSA_FP_ROUND_D_PSEUDO 499 +#define Mips_MSA_FP_ROUND_W_PSEUDO 500 +#define Mips_MTTACX 501 +#define Mips_MTTC0 502 +#define Mips_MTTC1 503 +#define Mips_MTTDSP 504 +#define Mips_MTTGPR 505 +#define Mips_MTTHC1 506 +#define Mips_MTTHI 507 +#define Mips_MTTLO 508 +#define Mips_MULImmMacro 509 +#define Mips_MULOMacro 510 +#define Mips_MULOUMacro 511 +#define Mips_MultRxRy16 512 +#define Mips_MultRxRyRz16 513 +#define Mips_MultuRxRy16 514 +#define Mips_MultuRxRyRz16 515 +#define Mips_NOP 516 +#define Mips_NORImm 517 +#define Mips_NORImm64 518 +#define Mips_NOR_V_D_PSEUDO 519 +#define Mips_NOR_V_H_PSEUDO 520 +#define Mips_NOR_V_W_PSEUDO 521 +#define Mips_OR_V_D_PSEUDO 522 +#define Mips_OR_V_H_PSEUDO 523 +#define Mips_OR_V_W_PSEUDO 524 +#define Mips_PseudoCMPU_EQ_QB 525 +#define Mips_PseudoCMPU_LE_QB 526 +#define Mips_PseudoCMPU_LT_QB 527 +#define Mips_PseudoCMP_EQ_PH 528 +#define Mips_PseudoCMP_LE_PH 529 +#define Mips_PseudoCMP_LT_PH 530 +#define Mips_PseudoCVT_D32_W 531 +#define Mips_PseudoCVT_D64_L 532 +#define Mips_PseudoCVT_D64_W 533 +#define Mips_PseudoCVT_S_L 534 +#define Mips_PseudoCVT_S_W 535 +#define Mips_PseudoDMULT 536 +#define Mips_PseudoDMULTu 537 +#define Mips_PseudoDSDIV 538 +#define Mips_PseudoDUDIV 539 +#define Mips_PseudoD_SELECT_I 540 +#define Mips_PseudoD_SELECT_I64 541 +#define Mips_PseudoIndirectBranch 542 +#define Mips_PseudoIndirectBranch64 543 +#define Mips_PseudoIndirectBranch64R6 544 +#define Mips_PseudoIndirectBranchR6 545 +#define Mips_PseudoIndirectBranch_MM 546 +#define Mips_PseudoIndirectBranch_MMR6 547 +#define Mips_PseudoIndirectHazardBranch 548 +#define Mips_PseudoIndirectHazardBranch64 549 +#define Mips_PseudoIndrectHazardBranch64R6 550 +#define Mips_PseudoIndrectHazardBranchR6 551 +#define Mips_PseudoMADD 552 +#define Mips_PseudoMADDU 553 +#define Mips_PseudoMADDU_MM 554 +#define Mips_PseudoMADD_MM 555 +#define Mips_PseudoMFHI 556 +#define Mips_PseudoMFHI64 557 +#define Mips_PseudoMFHI_MM 558 +#define Mips_PseudoMFLO 559 +#define Mips_PseudoMFLO64 560 +#define Mips_PseudoMFLO_MM 561 +#define Mips_PseudoMSUB 562 +#define Mips_PseudoMSUBU 563 +#define Mips_PseudoMSUBU_MM 564 +#define Mips_PseudoMSUB_MM 565 +#define Mips_PseudoMTLOHI 566 +#define Mips_PseudoMTLOHI64 567 +#define Mips_PseudoMTLOHI_DSP 568 +#define Mips_PseudoMTLOHI_MM 569 +#define Mips_PseudoMULT 570 +#define Mips_PseudoMULT_MM 571 +#define Mips_PseudoMULTu 572 +#define Mips_PseudoMULTu_MM 573 +#define Mips_PseudoPICK_PH 574 +#define Mips_PseudoPICK_QB 575 +#define Mips_PseudoReturn 576 +#define Mips_PseudoReturn64 577 +#define Mips_PseudoSDIV 578 +#define Mips_PseudoSELECTFP_F_D32 579 +#define Mips_PseudoSELECTFP_F_D64 580 +#define Mips_PseudoSELECTFP_F_I 581 +#define Mips_PseudoSELECTFP_F_I64 582 +#define Mips_PseudoSELECTFP_F_S 583 +#define Mips_PseudoSELECTFP_T_D32 584 +#define Mips_PseudoSELECTFP_T_D64 585 +#define Mips_PseudoSELECTFP_T_I 586 +#define Mips_PseudoSELECTFP_T_I64 587 +#define Mips_PseudoSELECTFP_T_S 588 +#define Mips_PseudoSELECT_D32 589 +#define Mips_PseudoSELECT_D64 590 +#define Mips_PseudoSELECT_I 591 +#define Mips_PseudoSELECT_I64 592 +#define Mips_PseudoSELECT_S 593 +#define Mips_PseudoTRUNC_W_D 594 +#define Mips_PseudoTRUNC_W_D32 595 +#define Mips_PseudoTRUNC_W_S 596 +#define Mips_PseudoUDIV 597 +#define Mips_ROL 598 +#define Mips_ROLImm 599 +#define Mips_ROR 600 +#define Mips_RORImm 601 +#define Mips_RetRA 602 +#define Mips_RetRA16 603 +#define Mips_SDC1_M1 604 +#define Mips_SDIV_MM_Pseudo 605 +#define Mips_SDMacro 606 +#define Mips_SDivIMacro 607 +#define Mips_SDivMacro 608 +#define Mips_SEQIMacro 609 +#define Mips_SEQMacro 610 +#define Mips_SGE 611 +#define Mips_SGEImm 612 +#define Mips_SGEImm64 613 +#define Mips_SGEU 614 +#define Mips_SGEUImm 615 +#define Mips_SGEUImm64 616 +#define Mips_SGTImm 617 +#define Mips_SGTImm64 618 +#define Mips_SGTUImm 619 +#define Mips_SGTUImm64 620 +#define Mips_SLE 621 +#define Mips_SLEImm 622 +#define Mips_SLEImm64 623 +#define Mips_SLEU 624 +#define Mips_SLEUImm 625 +#define Mips_SLEUImm64 626 +#define Mips_SLTImm64 627 +#define Mips_SLTUImm64 628 +#define Mips_SNEIMacro 629 +#define Mips_SNEMacro 630 +#define Mips_SNZ_B_PSEUDO 631 +#define Mips_SNZ_D_PSEUDO 632 +#define Mips_SNZ_H_PSEUDO 633 +#define Mips_SNZ_V_PSEUDO 634 +#define Mips_SNZ_W_PSEUDO 635 +#define Mips_SRemIMacro 636 +#define Mips_SRemMacro 637 +#define Mips_STORE_ACC128 638 +#define Mips_STORE_ACC64 639 +#define Mips_STORE_ACC64DSP 640 +#define Mips_STORE_CCOND_DSP 641 +#define Mips_STR_D 642 +#define Mips_STR_W 643 +#define Mips_ST_F16 644 +#define Mips_SWM_MM 645 +#define Mips_SZ_B_PSEUDO 646 +#define Mips_SZ_D_PSEUDO 647 +#define Mips_SZ_H_PSEUDO 648 +#define Mips_SZ_V_PSEUDO 649 +#define Mips_SZ_W_PSEUDO 650 +#define Mips_SaaAddr 651 +#define Mips_SaadAddr 652 +#define Mips_SelBeqZ 653 +#define Mips_SelBneZ 654 +#define Mips_SelTBteqZCmp 655 +#define Mips_SelTBteqZCmpi 656 +#define Mips_SelTBteqZSlt 657 +#define Mips_SelTBteqZSlti 658 +#define Mips_SelTBteqZSltiu 659 +#define Mips_SelTBteqZSltu 660 +#define Mips_SelTBtneZCmp 661 +#define Mips_SelTBtneZCmpi 662 +#define Mips_SelTBtneZSlt 663 +#define Mips_SelTBtneZSlti 664 +#define Mips_SelTBtneZSltiu 665 +#define Mips_SelTBtneZSltu 666 +#define Mips_SltCCRxRy16 667 +#define Mips_SltiCCRxImmX16 668 +#define Mips_SltiuCCRxImmX16 669 +#define Mips_SltuCCRxRy16 670 +#define Mips_SltuRxRyRz16 671 +#define Mips_TAILCALL 672 +#define Mips_TAILCALL64R6REG 673 +#define Mips_TAILCALLHB64R6REG 674 +#define Mips_TAILCALLHBR6REG 675 +#define Mips_TAILCALLR6REG 676 +#define Mips_TAILCALLREG 677 +#define Mips_TAILCALLREG64 678 +#define Mips_TAILCALLREGHB 679 +#define Mips_TAILCALLREGHB64 680 +#define Mips_TAILCALLREG_MM 681 +#define Mips_TAILCALLREG_MMR6 682 +#define Mips_TAILCALL_MM 683 +#define Mips_TAILCALL_MMR6 684 +#define Mips_TRAP 685 +#define Mips_TRAP_MM 686 +#define Mips_UDIV_MM_Pseudo 687 +#define Mips_UDivIMacro 688 +#define Mips_UDivMacro 689 +#define Mips_URemIMacro 690 +#define Mips_URemMacro 691 +#define Mips_Ulh 692 +#define Mips_Ulhu 693 +#define Mips_Ulw 694 +#define Mips_Ush 695 +#define Mips_Usw 696 +#define Mips_XOR_V_D_PSEUDO 697 +#define Mips_XOR_V_H_PSEUDO 698 +#define Mips_XOR_V_W_PSEUDO 699 +#define Mips_ABSQ_S_PH 700 +#define Mips_ABSQ_S_PH_MM 701 +#define Mips_ABSQ_S_QB 702 +#define Mips_ABSQ_S_QB_MMR2 703 +#define Mips_ABSQ_S_W 704 +#define Mips_ABSQ_S_W_MM 705 +#define Mips_ADD 706 +#define Mips_ADDIUPC 707 +#define Mips_ADDIUPC_MM 708 +#define Mips_ADDIUPC_MMR6 709 +#define Mips_ADDIUR1SP_MM 710 +#define Mips_ADDIUR2_MM 711 +#define Mips_ADDIUS5_MM 712 +#define Mips_ADDIUSP_MM 713 +#define Mips_ADDIU_MMR6 714 +#define Mips_ADDQH_PH 715 +#define Mips_ADDQH_PH_MMR2 716 +#define Mips_ADDQH_R_PH 717 +#define Mips_ADDQH_R_PH_MMR2 718 +#define Mips_ADDQH_R_W 719 +#define Mips_ADDQH_R_W_MMR2 720 +#define Mips_ADDQH_W 721 +#define Mips_ADDQH_W_MMR2 722 +#define Mips_ADDQ_PH 723 +#define Mips_ADDQ_PH_MM 724 +#define Mips_ADDQ_S_PH 725 +#define Mips_ADDQ_S_PH_MM 726 +#define Mips_ADDQ_S_W 727 +#define Mips_ADDQ_S_W_MM 728 +#define Mips_ADDR_PS64 729 +#define Mips_ADDSC 730 +#define Mips_ADDSC_MM 731 +#define Mips_ADDS_A_B 732 +#define Mips_ADDS_A_D 733 +#define Mips_ADDS_A_H 734 +#define Mips_ADDS_A_W 735 +#define Mips_ADDS_S_B 736 +#define Mips_ADDS_S_D 737 +#define Mips_ADDS_S_H 738 +#define Mips_ADDS_S_W 739 +#define Mips_ADDS_U_B 740 +#define Mips_ADDS_U_D 741 +#define Mips_ADDS_U_H 742 +#define Mips_ADDS_U_W 743 +#define Mips_ADDU16_MM 744 +#define Mips_ADDU16_MMR6 745 +#define Mips_ADDUH_QB 746 +#define Mips_ADDUH_QB_MMR2 747 +#define Mips_ADDUH_R_QB 748 +#define Mips_ADDUH_R_QB_MMR2 749 +#define Mips_ADDU_MMR6 750 +#define Mips_ADDU_PH 751 +#define Mips_ADDU_PH_MMR2 752 +#define Mips_ADDU_QB 753 +#define Mips_ADDU_QB_MM 754 +#define Mips_ADDU_S_PH 755 +#define Mips_ADDU_S_PH_MMR2 756 +#define Mips_ADDU_S_QB 757 +#define Mips_ADDU_S_QB_MM 758 +#define Mips_ADDVI_B 759 +#define Mips_ADDVI_D 760 +#define Mips_ADDVI_H 761 +#define Mips_ADDVI_W 762 +#define Mips_ADDV_B 763 +#define Mips_ADDV_D 764 +#define Mips_ADDV_H 765 +#define Mips_ADDV_W 766 +#define Mips_ADDWC 767 +#define Mips_ADDWC_MM 768 +#define Mips_ADD_A_B 769 +#define Mips_ADD_A_D 770 +#define Mips_ADD_A_H 771 +#define Mips_ADD_A_W 772 +#define Mips_ADD_MM 773 +#define Mips_ADD_MMR6 774 +#define Mips_ADDi 775 +#define Mips_ADDi_MM 776 +#define Mips_ADDiu 777 +#define Mips_ADDiu_MM 778 +#define Mips_ADDu 779 +#define Mips_ADDu_MM 780 +#define Mips_ALIGN 781 +#define Mips_ALIGN_MMR6 782 +#define Mips_ALUIPC 783 +#define Mips_ALUIPC_MMR6 784 +#define Mips_AND 785 +#define Mips_AND16_MM 786 +#define Mips_AND16_MMR6 787 +#define Mips_AND64 788 +#define Mips_ANDI16_MM 789 +#define Mips_ANDI16_MMR6 790 +#define Mips_ANDI_B 791 +#define Mips_ANDI_MMR6 792 +#define Mips_AND_MM 793 +#define Mips_AND_MMR6 794 +#define Mips_AND_V 795 +#define Mips_ANDi 796 +#define Mips_ANDi64 797 +#define Mips_ANDi_MM 798 +#define Mips_APPEND 799 +#define Mips_APPEND_MMR2 800 +#define Mips_ASUB_S_B 801 +#define Mips_ASUB_S_D 802 +#define Mips_ASUB_S_H 803 +#define Mips_ASUB_S_W 804 +#define Mips_ASUB_U_B 805 +#define Mips_ASUB_U_D 806 +#define Mips_ASUB_U_H 807 +#define Mips_ASUB_U_W 808 +#define Mips_AUI 809 +#define Mips_AUIPC 810 +#define Mips_AUIPC_MMR6 811 +#define Mips_AUI_MMR6 812 +#define Mips_AVER_S_B 813 +#define Mips_AVER_S_D 814 +#define Mips_AVER_S_H 815 +#define Mips_AVER_S_W 816 +#define Mips_AVER_U_B 817 +#define Mips_AVER_U_D 818 +#define Mips_AVER_U_H 819 +#define Mips_AVER_U_W 820 +#define Mips_AVE_S_B 821 +#define Mips_AVE_S_D 822 +#define Mips_AVE_S_H 823 +#define Mips_AVE_S_W 824 +#define Mips_AVE_U_B 825 +#define Mips_AVE_U_D 826 +#define Mips_AVE_U_H 827 +#define Mips_AVE_U_W 828 +#define Mips_AddiuRxImmX16 829 +#define Mips_AddiuRxPcImmX16 830 +#define Mips_AddiuRxRxImm16 831 +#define Mips_AddiuRxRxImmX16 832 +#define Mips_AddiuRxRyOffMemX16 833 +#define Mips_AddiuSpImm16 834 +#define Mips_AddiuSpImmX16 835 +#define Mips_AdduRxRyRz16 836 +#define Mips_AndRxRxRy16 837 +#define Mips_B16_MM 838 +#define Mips_BADDu 839 +#define Mips_BAL 840 +#define Mips_BALC 841 +#define Mips_BALC_MMR6 842 +#define Mips_BALIGN 843 +#define Mips_BALIGN_MMR2 844 +#define Mips_BBIT0 845 +#define Mips_BBIT032 846 +#define Mips_BBIT1 847 +#define Mips_BBIT132 848 +#define Mips_BC 849 +#define Mips_BC0F 850 +#define Mips_BC0T 851 +#define Mips_BC16_MMR6 852 +#define Mips_BC1EQZ 853 +#define Mips_BC1EQZC_MMR6 854 +#define Mips_BC1F 855 +#define Mips_BC1FL 856 +#define Mips_BC1F_MM 857 +#define Mips_BC1NEZ 858 +#define Mips_BC1NEZC_MMR6 859 +#define Mips_BC1T 860 +#define Mips_BC1TL 861 +#define Mips_BC1T_MM 862 +#define Mips_BC2EQZ 863 +#define Mips_BC2EQZC_MMR6 864 +#define Mips_BC2F 865 +#define Mips_BC2FL 866 +#define Mips_BC2NEZ 867 +#define Mips_BC2NEZC_MMR6 868 +#define Mips_BC2T 869 +#define Mips_BC2TL 870 +#define Mips_BC3F 871 +#define Mips_BC3FL 872 +#define Mips_BC3T 873 +#define Mips_BC3TL 874 +#define Mips_BCLRI_B 875 +#define Mips_BCLRI_D 876 +#define Mips_BCLRI_H 877 +#define Mips_BCLRI_W 878 +#define Mips_BCLR_B 879 +#define Mips_BCLR_D 880 +#define Mips_BCLR_H 881 +#define Mips_BCLR_W 882 +#define Mips_BC_MMR6 883 +#define Mips_BEQ 884 +#define Mips_BEQ64 885 +#define Mips_BEQC 886 +#define Mips_BEQC64 887 +#define Mips_BEQC_MMR6 888 +#define Mips_BEQL 889 +#define Mips_BEQZ16_MM 890 +#define Mips_BEQZALC 891 +#define Mips_BEQZALC_MMR6 892 +#define Mips_BEQZC 893 +#define Mips_BEQZC16_MMR6 894 +#define Mips_BEQZC64 895 +#define Mips_BEQZC_MM 896 +#define Mips_BEQZC_MMR6 897 +#define Mips_BEQ_MM 898 +#define Mips_BGEC 899 +#define Mips_BGEC64 900 +#define Mips_BGEC_MMR6 901 +#define Mips_BGEUC 902 +#define Mips_BGEUC64 903 +#define Mips_BGEUC_MMR6 904 +#define Mips_BGEZ 905 +#define Mips_BGEZ64 906 +#define Mips_BGEZAL 907 +#define Mips_BGEZALC 908 +#define Mips_BGEZALC_MMR6 909 +#define Mips_BGEZALL 910 +#define Mips_BGEZALS_MM 911 +#define Mips_BGEZAL_MM 912 +#define Mips_BGEZC 913 +#define Mips_BGEZC64 914 +#define Mips_BGEZC_MMR6 915 +#define Mips_BGEZL 916 +#define Mips_BGEZ_MM 917 +#define Mips_BGTZ 918 +#define Mips_BGTZ64 919 +#define Mips_BGTZALC 920 +#define Mips_BGTZALC_MMR6 921 +#define Mips_BGTZC 922 +#define Mips_BGTZC64 923 +#define Mips_BGTZC_MMR6 924 +#define Mips_BGTZL 925 +#define Mips_BGTZ_MM 926 +#define Mips_BINSLI_B 927 +#define Mips_BINSLI_D 928 +#define Mips_BINSLI_H 929 +#define Mips_BINSLI_W 930 +#define Mips_BINSL_B 931 +#define Mips_BINSL_D 932 +#define Mips_BINSL_H 933 +#define Mips_BINSL_W 934 +#define Mips_BINSRI_B 935 +#define Mips_BINSRI_D 936 +#define Mips_BINSRI_H 937 +#define Mips_BINSRI_W 938 +#define Mips_BINSR_B 939 +#define Mips_BINSR_D 940 +#define Mips_BINSR_H 941 +#define Mips_BINSR_W 942 +#define Mips_BITREV 943 +#define Mips_BITREV_MM 944 +#define Mips_BITSWAP 945 +#define Mips_BITSWAP_MMR6 946 +#define Mips_BLEZ 947 +#define Mips_BLEZ64 948 +#define Mips_BLEZALC 949 +#define Mips_BLEZALC_MMR6 950 +#define Mips_BLEZC 951 +#define Mips_BLEZC64 952 +#define Mips_BLEZC_MMR6 953 +#define Mips_BLEZL 954 +#define Mips_BLEZ_MM 955 +#define Mips_BLTC 956 +#define Mips_BLTC64 957 +#define Mips_BLTC_MMR6 958 +#define Mips_BLTUC 959 +#define Mips_BLTUC64 960 +#define Mips_BLTUC_MMR6 961 +#define Mips_BLTZ 962 +#define Mips_BLTZ64 963 +#define Mips_BLTZAL 964 +#define Mips_BLTZALC 965 +#define Mips_BLTZALC_MMR6 966 +#define Mips_BLTZALL 967 +#define Mips_BLTZALS_MM 968 +#define Mips_BLTZAL_MM 969 +#define Mips_BLTZC 970 +#define Mips_BLTZC64 971 +#define Mips_BLTZC_MMR6 972 +#define Mips_BLTZL 973 +#define Mips_BLTZ_MM 974 +#define Mips_BMNZI_B 975 +#define Mips_BMNZ_V 976 +#define Mips_BMZI_B 977 +#define Mips_BMZ_V 978 +#define Mips_BNE 979 +#define Mips_BNE64 980 +#define Mips_BNEC 981 +#define Mips_BNEC64 982 +#define Mips_BNEC_MMR6 983 +#define Mips_BNEGI_B 984 +#define Mips_BNEGI_D 985 +#define Mips_BNEGI_H 986 +#define Mips_BNEGI_W 987 +#define Mips_BNEG_B 988 +#define Mips_BNEG_D 989 +#define Mips_BNEG_H 990 +#define Mips_BNEG_W 991 +#define Mips_BNEL 992 +#define Mips_BNEZ16_MM 993 +#define Mips_BNEZALC 994 +#define Mips_BNEZALC_MMR6 995 +#define Mips_BNEZC 996 +#define Mips_BNEZC16_MMR6 997 +#define Mips_BNEZC64 998 +#define Mips_BNEZC_MM 999 +#define Mips_BNEZC_MMR6 1000 +#define Mips_BNE_MM 1001 +#define Mips_BNVC 1002 +#define Mips_BNVC_MMR6 1003 +#define Mips_BNZ_B 1004 +#define Mips_BNZ_D 1005 +#define Mips_BNZ_H 1006 +#define Mips_BNZ_V 1007 +#define Mips_BNZ_W 1008 +#define Mips_BOVC 1009 +#define Mips_BOVC_MMR6 1010 +#define Mips_BPOSGE32 1011 +#define Mips_BPOSGE32C_MMR3 1012 +#define Mips_BPOSGE32_MM 1013 +#define Mips_BREAK 1014 +#define Mips_BREAK16_MM 1015 +#define Mips_BREAK16_MMR6 1016 +#define Mips_BREAK_MM 1017 +#define Mips_BREAK_MMR6 1018 +#define Mips_BSELI_B 1019 +#define Mips_BSEL_V 1020 +#define Mips_BSETI_B 1021 +#define Mips_BSETI_D 1022 +#define Mips_BSETI_H 1023 +#define Mips_BSETI_W 1024 +#define Mips_BSET_B 1025 +#define Mips_BSET_D 1026 +#define Mips_BSET_H 1027 +#define Mips_BSET_W 1028 +#define Mips_BZ_B 1029 +#define Mips_BZ_D 1030 +#define Mips_BZ_H 1031 +#define Mips_BZ_V 1032 +#define Mips_BZ_W 1033 +#define Mips_BeqzRxImm16 1034 +#define Mips_BeqzRxImmX16 1035 +#define Mips_Bimm16 1036 +#define Mips_BimmX16 1037 +#define Mips_BnezRxImm16 1038 +#define Mips_BnezRxImmX16 1039 +#define Mips_Break16 1040 +#define Mips_Bteqz16 1041 +#define Mips_BteqzX16 1042 +#define Mips_Btnez16 1043 +#define Mips_BtnezX16 1044 +#define Mips_CACHE 1045 +#define Mips_CACHEE 1046 +#define Mips_CACHEE_MM 1047 +#define Mips_CACHE_MM 1048 +#define Mips_CACHE_MMR6 1049 +#define Mips_CACHE_R6 1050 +#define Mips_CEIL_L_D64 1051 +#define Mips_CEIL_L_D_MMR6 1052 +#define Mips_CEIL_L_S 1053 +#define Mips_CEIL_L_S_MMR6 1054 +#define Mips_CEIL_W_D32 1055 +#define Mips_CEIL_W_D64 1056 +#define Mips_CEIL_W_D_MMR6 1057 +#define Mips_CEIL_W_MM 1058 +#define Mips_CEIL_W_S 1059 +#define Mips_CEIL_W_S_MM 1060 +#define Mips_CEIL_W_S_MMR6 1061 +#define Mips_CEQI_B 1062 +#define Mips_CEQI_D 1063 +#define Mips_CEQI_H 1064 +#define Mips_CEQI_W 1065 +#define Mips_CEQ_B 1066 +#define Mips_CEQ_D 1067 +#define Mips_CEQ_H 1068 +#define Mips_CEQ_W 1069 +#define Mips_CFC1 1070 +#define Mips_CFC1_MM 1071 +#define Mips_CFC2_MM 1072 +#define Mips_CFCMSA 1073 +#define Mips_CINS 1074 +#define Mips_CINS32 1075 +#define Mips_CINS64_32 1076 +#define Mips_CINS_i32 1077 +#define Mips_CLASS_D 1078 +#define Mips_CLASS_D_MMR6 1079 +#define Mips_CLASS_S 1080 +#define Mips_CLASS_S_MMR6 1081 +#define Mips_CLEI_S_B 1082 +#define Mips_CLEI_S_D 1083 +#define Mips_CLEI_S_H 1084 +#define Mips_CLEI_S_W 1085 +#define Mips_CLEI_U_B 1086 +#define Mips_CLEI_U_D 1087 +#define Mips_CLEI_U_H 1088 +#define Mips_CLEI_U_W 1089 +#define Mips_CLE_S_B 1090 +#define Mips_CLE_S_D 1091 +#define Mips_CLE_S_H 1092 +#define Mips_CLE_S_W 1093 +#define Mips_CLE_U_B 1094 +#define Mips_CLE_U_D 1095 +#define Mips_CLE_U_H 1096 +#define Mips_CLE_U_W 1097 +#define Mips_CLO 1098 +#define Mips_CLO_MM 1099 +#define Mips_CLO_MMR6 1100 +#define Mips_CLO_R6 1101 +#define Mips_CLTI_S_B 1102 +#define Mips_CLTI_S_D 1103 +#define Mips_CLTI_S_H 1104 +#define Mips_CLTI_S_W 1105 +#define Mips_CLTI_U_B 1106 +#define Mips_CLTI_U_D 1107 +#define Mips_CLTI_U_H 1108 +#define Mips_CLTI_U_W 1109 +#define Mips_CLT_S_B 1110 +#define Mips_CLT_S_D 1111 +#define Mips_CLT_S_H 1112 +#define Mips_CLT_S_W 1113 +#define Mips_CLT_U_B 1114 +#define Mips_CLT_U_D 1115 +#define Mips_CLT_U_H 1116 +#define Mips_CLT_U_W 1117 +#define Mips_CLZ 1118 +#define Mips_CLZ_MM 1119 +#define Mips_CLZ_MMR6 1120 +#define Mips_CLZ_R6 1121 +#define Mips_CMPGDU_EQ_QB 1122 +#define Mips_CMPGDU_EQ_QB_MMR2 1123 +#define Mips_CMPGDU_LE_QB 1124 +#define Mips_CMPGDU_LE_QB_MMR2 1125 +#define Mips_CMPGDU_LT_QB 1126 +#define Mips_CMPGDU_LT_QB_MMR2 1127 +#define Mips_CMPGU_EQ_QB 1128 +#define Mips_CMPGU_EQ_QB_MM 1129 +#define Mips_CMPGU_LE_QB 1130 +#define Mips_CMPGU_LE_QB_MM 1131 +#define Mips_CMPGU_LT_QB 1132 +#define Mips_CMPGU_LT_QB_MM 1133 +#define Mips_CMPU_EQ_QB 1134 +#define Mips_CMPU_EQ_QB_MM 1135 +#define Mips_CMPU_LE_QB 1136 +#define Mips_CMPU_LE_QB_MM 1137 +#define Mips_CMPU_LT_QB 1138 +#define Mips_CMPU_LT_QB_MM 1139 +#define Mips_CMP_AF_D_MMR6 1140 +#define Mips_CMP_AF_S_MMR6 1141 +#define Mips_CMP_EQ_D 1142 +#define Mips_CMP_EQ_D_MMR6 1143 +#define Mips_CMP_EQ_PH 1144 +#define Mips_CMP_EQ_PH_MM 1145 +#define Mips_CMP_EQ_S 1146 +#define Mips_CMP_EQ_S_MMR6 1147 +#define Mips_CMP_F_D 1148 +#define Mips_CMP_F_S 1149 +#define Mips_CMP_LE_D 1150 +#define Mips_CMP_LE_D_MMR6 1151 +#define Mips_CMP_LE_PH 1152 +#define Mips_CMP_LE_PH_MM 1153 +#define Mips_CMP_LE_S 1154 +#define Mips_CMP_LE_S_MMR6 1155 +#define Mips_CMP_LT_D 1156 +#define Mips_CMP_LT_D_MMR6 1157 +#define Mips_CMP_LT_PH 1158 +#define Mips_CMP_LT_PH_MM 1159 +#define Mips_CMP_LT_S 1160 +#define Mips_CMP_LT_S_MMR6 1161 +#define Mips_CMP_SAF_D 1162 +#define Mips_CMP_SAF_D_MMR6 1163 +#define Mips_CMP_SAF_S 1164 +#define Mips_CMP_SAF_S_MMR6 1165 +#define Mips_CMP_SEQ_D 1166 +#define Mips_CMP_SEQ_D_MMR6 1167 +#define Mips_CMP_SEQ_S 1168 +#define Mips_CMP_SEQ_S_MMR6 1169 +#define Mips_CMP_SLE_D 1170 +#define Mips_CMP_SLE_D_MMR6 1171 +#define Mips_CMP_SLE_S 1172 +#define Mips_CMP_SLE_S_MMR6 1173 +#define Mips_CMP_SLT_D 1174 +#define Mips_CMP_SLT_D_MMR6 1175 +#define Mips_CMP_SLT_S 1176 +#define Mips_CMP_SLT_S_MMR6 1177 +#define Mips_CMP_SUEQ_D 1178 +#define Mips_CMP_SUEQ_D_MMR6 1179 +#define Mips_CMP_SUEQ_S 1180 +#define Mips_CMP_SUEQ_S_MMR6 1181 +#define Mips_CMP_SULE_D 1182 +#define Mips_CMP_SULE_D_MMR6 1183 +#define Mips_CMP_SULE_S 1184 +#define Mips_CMP_SULE_S_MMR6 1185 +#define Mips_CMP_SULT_D 1186 +#define Mips_CMP_SULT_D_MMR6 1187 +#define Mips_CMP_SULT_S 1188 +#define Mips_CMP_SULT_S_MMR6 1189 +#define Mips_CMP_SUN_D 1190 +#define Mips_CMP_SUN_D_MMR6 1191 +#define Mips_CMP_SUN_S 1192 +#define Mips_CMP_SUN_S_MMR6 1193 +#define Mips_CMP_UEQ_D 1194 +#define Mips_CMP_UEQ_D_MMR6 1195 +#define Mips_CMP_UEQ_S 1196 +#define Mips_CMP_UEQ_S_MMR6 1197 +#define Mips_CMP_ULE_D 1198 +#define Mips_CMP_ULE_D_MMR6 1199 +#define Mips_CMP_ULE_S 1200 +#define Mips_CMP_ULE_S_MMR6 1201 +#define Mips_CMP_ULT_D 1202 +#define Mips_CMP_ULT_D_MMR6 1203 +#define Mips_CMP_ULT_S 1204 +#define Mips_CMP_ULT_S_MMR6 1205 +#define Mips_CMP_UN_D 1206 +#define Mips_CMP_UN_D_MMR6 1207 +#define Mips_CMP_UN_S 1208 +#define Mips_CMP_UN_S_MMR6 1209 +#define Mips_COPY_S_B 1210 +#define Mips_COPY_S_D 1211 +#define Mips_COPY_S_H 1212 +#define Mips_COPY_S_W 1213 +#define Mips_COPY_U_B 1214 +#define Mips_COPY_U_H 1215 +#define Mips_COPY_U_W 1216 +#define Mips_CRC32B 1217 +#define Mips_CRC32CB 1218 +#define Mips_CRC32CD 1219 +#define Mips_CRC32CH 1220 +#define Mips_CRC32CW 1221 +#define Mips_CRC32D 1222 +#define Mips_CRC32H 1223 +#define Mips_CRC32W 1224 +#define Mips_CTC1 1225 +#define Mips_CTC1_MM 1226 +#define Mips_CTC2_MM 1227 +#define Mips_CTCMSA 1228 +#define Mips_CVT_D32_S 1229 +#define Mips_CVT_D32_S_MM 1230 +#define Mips_CVT_D32_W 1231 +#define Mips_CVT_D32_W_MM 1232 +#define Mips_CVT_D64_L 1233 +#define Mips_CVT_D64_S 1234 +#define Mips_CVT_D64_S_MM 1235 +#define Mips_CVT_D64_W 1236 +#define Mips_CVT_D64_W_MM 1237 +#define Mips_CVT_D_L_MMR6 1238 +#define Mips_CVT_L_D64 1239 +#define Mips_CVT_L_D64_MM 1240 +#define Mips_CVT_L_D_MMR6 1241 +#define Mips_CVT_L_S 1242 +#define Mips_CVT_L_S_MM 1243 +#define Mips_CVT_L_S_MMR6 1244 +#define Mips_CVT_PS_PW64 1245 +#define Mips_CVT_PS_S64 1246 +#define Mips_CVT_PW_PS64 1247 +#define Mips_CVT_S_D32 1248 +#define Mips_CVT_S_D32_MM 1249 +#define Mips_CVT_S_D64 1250 +#define Mips_CVT_S_D64_MM 1251 +#define Mips_CVT_S_L 1252 +#define Mips_CVT_S_L_MMR6 1253 +#define Mips_CVT_S_PL64 1254 +#define Mips_CVT_S_PU64 1255 +#define Mips_CVT_S_W 1256 +#define Mips_CVT_S_W_MM 1257 +#define Mips_CVT_S_W_MMR6 1258 +#define Mips_CVT_W_D32 1259 +#define Mips_CVT_W_D32_MM 1260 +#define Mips_CVT_W_D64 1261 +#define Mips_CVT_W_D64_MM 1262 +#define Mips_CVT_W_S 1263 +#define Mips_CVT_W_S_MM 1264 +#define Mips_CVT_W_S_MMR6 1265 +#define Mips_C_EQ_D32 1266 +#define Mips_C_EQ_D32_MM 1267 +#define Mips_C_EQ_D64 1268 +#define Mips_C_EQ_D64_MM 1269 +#define Mips_C_EQ_S 1270 +#define Mips_C_EQ_S_MM 1271 +#define Mips_C_F_D32 1272 +#define Mips_C_F_D32_MM 1273 +#define Mips_C_F_D64 1274 +#define Mips_C_F_D64_MM 1275 +#define Mips_C_F_S 1276 +#define Mips_C_F_S_MM 1277 +#define Mips_C_LE_D32 1278 +#define Mips_C_LE_D32_MM 1279 +#define Mips_C_LE_D64 1280 +#define Mips_C_LE_D64_MM 1281 +#define Mips_C_LE_S 1282 +#define Mips_C_LE_S_MM 1283 +#define Mips_C_LT_D32 1284 +#define Mips_C_LT_D32_MM 1285 +#define Mips_C_LT_D64 1286 +#define Mips_C_LT_D64_MM 1287 +#define Mips_C_LT_S 1288 +#define Mips_C_LT_S_MM 1289 +#define Mips_C_NGE_D32 1290 +#define Mips_C_NGE_D32_MM 1291 +#define Mips_C_NGE_D64 1292 +#define Mips_C_NGE_D64_MM 1293 +#define Mips_C_NGE_S 1294 +#define Mips_C_NGE_S_MM 1295 +#define Mips_C_NGLE_D32 1296 +#define Mips_C_NGLE_D32_MM 1297 +#define Mips_C_NGLE_D64 1298 +#define Mips_C_NGLE_D64_MM 1299 +#define Mips_C_NGLE_S 1300 +#define Mips_C_NGLE_S_MM 1301 +#define Mips_C_NGL_D32 1302 +#define Mips_C_NGL_D32_MM 1303 +#define Mips_C_NGL_D64 1304 +#define Mips_C_NGL_D64_MM 1305 +#define Mips_C_NGL_S 1306 +#define Mips_C_NGL_S_MM 1307 +#define Mips_C_NGT_D32 1308 +#define Mips_C_NGT_D32_MM 1309 +#define Mips_C_NGT_D64 1310 +#define Mips_C_NGT_D64_MM 1311 +#define Mips_C_NGT_S 1312 +#define Mips_C_NGT_S_MM 1313 +#define Mips_C_OLE_D32 1314 +#define Mips_C_OLE_D32_MM 1315 +#define Mips_C_OLE_D64 1316 +#define Mips_C_OLE_D64_MM 1317 +#define Mips_C_OLE_S 1318 +#define Mips_C_OLE_S_MM 1319 +#define Mips_C_OLT_D32 1320 +#define Mips_C_OLT_D32_MM 1321 +#define Mips_C_OLT_D64 1322 +#define Mips_C_OLT_D64_MM 1323 +#define Mips_C_OLT_S 1324 +#define Mips_C_OLT_S_MM 1325 +#define Mips_C_SEQ_D32 1326 +#define Mips_C_SEQ_D32_MM 1327 +#define Mips_C_SEQ_D64 1328 +#define Mips_C_SEQ_D64_MM 1329 +#define Mips_C_SEQ_S 1330 +#define Mips_C_SEQ_S_MM 1331 +#define Mips_C_SF_D32 1332 +#define Mips_C_SF_D32_MM 1333 +#define Mips_C_SF_D64 1334 +#define Mips_C_SF_D64_MM 1335 +#define Mips_C_SF_S 1336 +#define Mips_C_SF_S_MM 1337 +#define Mips_C_UEQ_D32 1338 +#define Mips_C_UEQ_D32_MM 1339 +#define Mips_C_UEQ_D64 1340 +#define Mips_C_UEQ_D64_MM 1341 +#define Mips_C_UEQ_S 1342 +#define Mips_C_UEQ_S_MM 1343 +#define Mips_C_ULE_D32 1344 +#define Mips_C_ULE_D32_MM 1345 +#define Mips_C_ULE_D64 1346 +#define Mips_C_ULE_D64_MM 1347 +#define Mips_C_ULE_S 1348 +#define Mips_C_ULE_S_MM 1349 +#define Mips_C_ULT_D32 1350 +#define Mips_C_ULT_D32_MM 1351 +#define Mips_C_ULT_D64 1352 +#define Mips_C_ULT_D64_MM 1353 +#define Mips_C_ULT_S 1354 +#define Mips_C_ULT_S_MM 1355 +#define Mips_C_UN_D32 1356 +#define Mips_C_UN_D32_MM 1357 +#define Mips_C_UN_D64 1358 +#define Mips_C_UN_D64_MM 1359 +#define Mips_C_UN_S 1360 +#define Mips_C_UN_S_MM 1361 +#define Mips_CmpRxRy16 1362 +#define Mips_CmpiRxImm16 1363 +#define Mips_CmpiRxImmX16 1364 +#define Mips_DADD 1365 +#define Mips_DADDi 1366 +#define Mips_DADDiu 1367 +#define Mips_DADDu 1368 +#define Mips_DAHI 1369 +#define Mips_DALIGN 1370 +#define Mips_DATI 1371 +#define Mips_DAUI 1372 +#define Mips_DBITSWAP 1373 +#define Mips_DCLO 1374 +#define Mips_DCLO_R6 1375 +#define Mips_DCLZ 1376 +#define Mips_DCLZ_R6 1377 +#define Mips_DDIV 1378 +#define Mips_DDIVU 1379 +#define Mips_DERET 1380 +#define Mips_DERET_MM 1381 +#define Mips_DERET_MMR6 1382 +#define Mips_DEXT 1383 +#define Mips_DEXT64_32 1384 +#define Mips_DEXTM 1385 +#define Mips_DEXTU 1386 +#define Mips_DI 1387 +#define Mips_DINS 1388 +#define Mips_DINSM 1389 +#define Mips_DINSU 1390 +#define Mips_DIV 1391 +#define Mips_DIVU 1392 +#define Mips_DIVU_MMR6 1393 +#define Mips_DIV_MMR6 1394 +#define Mips_DIV_S_B 1395 +#define Mips_DIV_S_D 1396 +#define Mips_DIV_S_H 1397 +#define Mips_DIV_S_W 1398 +#define Mips_DIV_U_B 1399 +#define Mips_DIV_U_D 1400 +#define Mips_DIV_U_H 1401 +#define Mips_DIV_U_W 1402 +#define Mips_DI_MM 1403 +#define Mips_DI_MMR6 1404 +#define Mips_DLSA 1405 +#define Mips_DLSA_R6 1406 +#define Mips_DMFC0 1407 +#define Mips_DMFC1 1408 +#define Mips_DMFC2 1409 +#define Mips_DMFC2_OCTEON 1410 +#define Mips_DMFGC0 1411 +#define Mips_DMOD 1412 +#define Mips_DMODU 1413 +#define Mips_DMT 1414 +#define Mips_DMTC0 1415 +#define Mips_DMTC1 1416 +#define Mips_DMTC2 1417 +#define Mips_DMTC2_OCTEON 1418 +#define Mips_DMTGC0 1419 +#define Mips_DMUH 1420 +#define Mips_DMUHU 1421 +#define Mips_DMUL 1422 +#define Mips_DMULT 1423 +#define Mips_DMULTu 1424 +#define Mips_DMULU 1425 +#define Mips_DMUL_R6 1426 +#define Mips_DOTP_S_D 1427 +#define Mips_DOTP_S_H 1428 +#define Mips_DOTP_S_W 1429 +#define Mips_DOTP_U_D 1430 +#define Mips_DOTP_U_H 1431 +#define Mips_DOTP_U_W 1432 +#define Mips_DPADD_S_D 1433 +#define Mips_DPADD_S_H 1434 +#define Mips_DPADD_S_W 1435 +#define Mips_DPADD_U_D 1436 +#define Mips_DPADD_U_H 1437 +#define Mips_DPADD_U_W 1438 +#define Mips_DPAQX_SA_W_PH 1439 +#define Mips_DPAQX_SA_W_PH_MMR2 1440 +#define Mips_DPAQX_S_W_PH 1441 +#define Mips_DPAQX_S_W_PH_MMR2 1442 +#define Mips_DPAQ_SA_L_W 1443 +#define Mips_DPAQ_SA_L_W_MM 1444 +#define Mips_DPAQ_S_W_PH 1445 +#define Mips_DPAQ_S_W_PH_MM 1446 +#define Mips_DPAU_H_QBL 1447 +#define Mips_DPAU_H_QBL_MM 1448 +#define Mips_DPAU_H_QBR 1449 +#define Mips_DPAU_H_QBR_MM 1450 +#define Mips_DPAX_W_PH 1451 +#define Mips_DPAX_W_PH_MMR2 1452 +#define Mips_DPA_W_PH 1453 +#define Mips_DPA_W_PH_MMR2 1454 +#define Mips_DPOP 1455 +#define Mips_DPSQX_SA_W_PH 1456 +#define Mips_DPSQX_SA_W_PH_MMR2 1457 +#define Mips_DPSQX_S_W_PH 1458 +#define Mips_DPSQX_S_W_PH_MMR2 1459 +#define Mips_DPSQ_SA_L_W 1460 +#define Mips_DPSQ_SA_L_W_MM 1461 +#define Mips_DPSQ_S_W_PH 1462 +#define Mips_DPSQ_S_W_PH_MM 1463 +#define Mips_DPSUB_S_D 1464 +#define Mips_DPSUB_S_H 1465 +#define Mips_DPSUB_S_W 1466 +#define Mips_DPSUB_U_D 1467 +#define Mips_DPSUB_U_H 1468 +#define Mips_DPSUB_U_W 1469 +#define Mips_DPSU_H_QBL 1470 +#define Mips_DPSU_H_QBL_MM 1471 +#define Mips_DPSU_H_QBR 1472 +#define Mips_DPSU_H_QBR_MM 1473 +#define Mips_DPSX_W_PH 1474 +#define Mips_DPSX_W_PH_MMR2 1475 +#define Mips_DPS_W_PH 1476 +#define Mips_DPS_W_PH_MMR2 1477 +#define Mips_DROTR 1478 +#define Mips_DROTR32 1479 +#define Mips_DROTRV 1480 +#define Mips_DSBH 1481 +#define Mips_DSDIV 1482 +#define Mips_DSHD 1483 +#define Mips_DSLL 1484 +#define Mips_DSLL32 1485 +#define Mips_DSLL64_32 1486 +#define Mips_DSLLV 1487 +#define Mips_DSRA 1488 +#define Mips_DSRA32 1489 +#define Mips_DSRAV 1490 +#define Mips_DSRL 1491 +#define Mips_DSRL32 1492 +#define Mips_DSRLV 1493 +#define Mips_DSUB 1494 +#define Mips_DSUBu 1495 +#define Mips_DUDIV 1496 +#define Mips_DVP 1497 +#define Mips_DVPE 1498 +#define Mips_DVP_MMR6 1499 +#define Mips_DivRxRy16 1500 +#define Mips_DivuRxRy16 1501 +#define Mips_EHB 1502 +#define Mips_EHB_MM 1503 +#define Mips_EHB_MMR6 1504 +#define Mips_EI 1505 +#define Mips_EI_MM 1506 +#define Mips_EI_MMR6 1507 +#define Mips_EMT 1508 +#define Mips_ERET 1509 +#define Mips_ERETNC 1510 +#define Mips_ERETNC_MMR6 1511 +#define Mips_ERET_MM 1512 +#define Mips_ERET_MMR6 1513 +#define Mips_EVP 1514 +#define Mips_EVPE 1515 +#define Mips_EVP_MMR6 1516 +#define Mips_EXT 1517 +#define Mips_EXTP 1518 +#define Mips_EXTPDP 1519 +#define Mips_EXTPDPV 1520 +#define Mips_EXTPDPV_MM 1521 +#define Mips_EXTPDP_MM 1522 +#define Mips_EXTPV 1523 +#define Mips_EXTPV_MM 1524 +#define Mips_EXTP_MM 1525 +#define Mips_EXTRV_RS_W 1526 +#define Mips_EXTRV_RS_W_MM 1527 +#define Mips_EXTRV_R_W 1528 +#define Mips_EXTRV_R_W_MM 1529 +#define Mips_EXTRV_S_H 1530 +#define Mips_EXTRV_S_H_MM 1531 +#define Mips_EXTRV_W 1532 +#define Mips_EXTRV_W_MM 1533 +#define Mips_EXTR_RS_W 1534 +#define Mips_EXTR_RS_W_MM 1535 +#define Mips_EXTR_R_W 1536 +#define Mips_EXTR_R_W_MM 1537 +#define Mips_EXTR_S_H 1538 +#define Mips_EXTR_S_H_MM 1539 +#define Mips_EXTR_W 1540 +#define Mips_EXTR_W_MM 1541 +#define Mips_EXTS 1542 +#define Mips_EXTS32 1543 +#define Mips_EXT_MM 1544 +#define Mips_EXT_MMR6 1545 +#define Mips_FABS_D32 1546 +#define Mips_FABS_D32_MM 1547 +#define Mips_FABS_D64 1548 +#define Mips_FABS_D64_MM 1549 +#define Mips_FABS_S 1550 +#define Mips_FABS_S_MM 1551 +#define Mips_FADD_D 1552 +#define Mips_FADD_D32 1553 +#define Mips_FADD_D32_MM 1554 +#define Mips_FADD_D64 1555 +#define Mips_FADD_D64_MM 1556 +#define Mips_FADD_PS64 1557 +#define Mips_FADD_S 1558 +#define Mips_FADD_S_MM 1559 +#define Mips_FADD_S_MMR6 1560 +#define Mips_FADD_W 1561 +#define Mips_FCAF_D 1562 +#define Mips_FCAF_W 1563 +#define Mips_FCEQ_D 1564 +#define Mips_FCEQ_W 1565 +#define Mips_FCLASS_D 1566 +#define Mips_FCLASS_W 1567 +#define Mips_FCLE_D 1568 +#define Mips_FCLE_W 1569 +#define Mips_FCLT_D 1570 +#define Mips_FCLT_W 1571 +#define Mips_FCMP_D32 1572 +#define Mips_FCMP_D32_MM 1573 +#define Mips_FCMP_D64 1574 +#define Mips_FCMP_S32 1575 +#define Mips_FCMP_S32_MM 1576 +#define Mips_FCNE_D 1577 +#define Mips_FCNE_W 1578 +#define Mips_FCOR_D 1579 +#define Mips_FCOR_W 1580 +#define Mips_FCUEQ_D 1581 +#define Mips_FCUEQ_W 1582 +#define Mips_FCULE_D 1583 +#define Mips_FCULE_W 1584 +#define Mips_FCULT_D 1585 +#define Mips_FCULT_W 1586 +#define Mips_FCUNE_D 1587 +#define Mips_FCUNE_W 1588 +#define Mips_FCUN_D 1589 +#define Mips_FCUN_W 1590 +#define Mips_FDIV_D 1591 +#define Mips_FDIV_D32 1592 +#define Mips_FDIV_D32_MM 1593 +#define Mips_FDIV_D64 1594 +#define Mips_FDIV_D64_MM 1595 +#define Mips_FDIV_S 1596 +#define Mips_FDIV_S_MM 1597 +#define Mips_FDIV_S_MMR6 1598 +#define Mips_FDIV_W 1599 +#define Mips_FEXDO_H 1600 +#define Mips_FEXDO_W 1601 +#define Mips_FEXP2_D 1602 +#define Mips_FEXP2_W 1603 +#define Mips_FEXUPL_D 1604 +#define Mips_FEXUPL_W 1605 +#define Mips_FEXUPR_D 1606 +#define Mips_FEXUPR_W 1607 +#define Mips_FFINT_S_D 1608 +#define Mips_FFINT_S_W 1609 +#define Mips_FFINT_U_D 1610 +#define Mips_FFINT_U_W 1611 +#define Mips_FFQL_D 1612 +#define Mips_FFQL_W 1613 +#define Mips_FFQR_D 1614 +#define Mips_FFQR_W 1615 +#define Mips_FILL_B 1616 +#define Mips_FILL_D 1617 +#define Mips_FILL_H 1618 +#define Mips_FILL_W 1619 +#define Mips_FLOG2_D 1620 +#define Mips_FLOG2_W 1621 +#define Mips_FLOOR_L_D64 1622 +#define Mips_FLOOR_L_D_MMR6 1623 +#define Mips_FLOOR_L_S 1624 +#define Mips_FLOOR_L_S_MMR6 1625 +#define Mips_FLOOR_W_D32 1626 +#define Mips_FLOOR_W_D64 1627 +#define Mips_FLOOR_W_D_MMR6 1628 +#define Mips_FLOOR_W_MM 1629 +#define Mips_FLOOR_W_S 1630 +#define Mips_FLOOR_W_S_MM 1631 +#define Mips_FLOOR_W_S_MMR6 1632 +#define Mips_FMADD_D 1633 +#define Mips_FMADD_W 1634 +#define Mips_FMAX_A_D 1635 +#define Mips_FMAX_A_W 1636 +#define Mips_FMAX_D 1637 +#define Mips_FMAX_W 1638 +#define Mips_FMIN_A_D 1639 +#define Mips_FMIN_A_W 1640 +#define Mips_FMIN_D 1641 +#define Mips_FMIN_W 1642 +#define Mips_FMOV_D32 1643 +#define Mips_FMOV_D32_MM 1644 +#define Mips_FMOV_D64 1645 +#define Mips_FMOV_D64_MM 1646 +#define Mips_FMOV_D_MMR6 1647 +#define Mips_FMOV_S 1648 +#define Mips_FMOV_S_MM 1649 +#define Mips_FMOV_S_MMR6 1650 +#define Mips_FMSUB_D 1651 +#define Mips_FMSUB_W 1652 +#define Mips_FMUL_D 1653 +#define Mips_FMUL_D32 1654 +#define Mips_FMUL_D32_MM 1655 +#define Mips_FMUL_D64 1656 +#define Mips_FMUL_D64_MM 1657 +#define Mips_FMUL_PS64 1658 +#define Mips_FMUL_S 1659 +#define Mips_FMUL_S_MM 1660 +#define Mips_FMUL_S_MMR6 1661 +#define Mips_FMUL_W 1662 +#define Mips_FNEG_D32 1663 +#define Mips_FNEG_D32_MM 1664 +#define Mips_FNEG_D64 1665 +#define Mips_FNEG_D64_MM 1666 +#define Mips_FNEG_S 1667 +#define Mips_FNEG_S_MM 1668 +#define Mips_FNEG_S_MMR6 1669 +#define Mips_FORK 1670 +#define Mips_FRCP_D 1671 +#define Mips_FRCP_W 1672 +#define Mips_FRINT_D 1673 +#define Mips_FRINT_W 1674 +#define Mips_FRSQRT_D 1675 +#define Mips_FRSQRT_W 1676 +#define Mips_FSAF_D 1677 +#define Mips_FSAF_W 1678 +#define Mips_FSEQ_D 1679 +#define Mips_FSEQ_W 1680 +#define Mips_FSLE_D 1681 +#define Mips_FSLE_W 1682 +#define Mips_FSLT_D 1683 +#define Mips_FSLT_W 1684 +#define Mips_FSNE_D 1685 +#define Mips_FSNE_W 1686 +#define Mips_FSOR_D 1687 +#define Mips_FSOR_W 1688 +#define Mips_FSQRT_D 1689 +#define Mips_FSQRT_D32 1690 +#define Mips_FSQRT_D32_MM 1691 +#define Mips_FSQRT_D64 1692 +#define Mips_FSQRT_D64_MM 1693 +#define Mips_FSQRT_S 1694 +#define Mips_FSQRT_S_MM 1695 +#define Mips_FSQRT_W 1696 +#define Mips_FSUB_D 1697 +#define Mips_FSUB_D32 1698 +#define Mips_FSUB_D32_MM 1699 +#define Mips_FSUB_D64 1700 +#define Mips_FSUB_D64_MM 1701 +#define Mips_FSUB_PS64 1702 +#define Mips_FSUB_S 1703 +#define Mips_FSUB_S_MM 1704 +#define Mips_FSUB_S_MMR6 1705 +#define Mips_FSUB_W 1706 +#define Mips_FSUEQ_D 1707 +#define Mips_FSUEQ_W 1708 +#define Mips_FSULE_D 1709 +#define Mips_FSULE_W 1710 +#define Mips_FSULT_D 1711 +#define Mips_FSULT_W 1712 +#define Mips_FSUNE_D 1713 +#define Mips_FSUNE_W 1714 +#define Mips_FSUN_D 1715 +#define Mips_FSUN_W 1716 +#define Mips_FTINT_S_D 1717 +#define Mips_FTINT_S_W 1718 +#define Mips_FTINT_U_D 1719 +#define Mips_FTINT_U_W 1720 +#define Mips_FTQ_H 1721 +#define Mips_FTQ_W 1722 +#define Mips_FTRUNC_S_D 1723 +#define Mips_FTRUNC_S_W 1724 +#define Mips_FTRUNC_U_D 1725 +#define Mips_FTRUNC_U_W 1726 +#define Mips_GINVI 1727 +#define Mips_GINVI_MMR6 1728 +#define Mips_GINVT 1729 +#define Mips_GINVT_MMR6 1730 +#define Mips_HADD_S_D 1731 +#define Mips_HADD_S_H 1732 +#define Mips_HADD_S_W 1733 +#define Mips_HADD_U_D 1734 +#define Mips_HADD_U_H 1735 +#define Mips_HADD_U_W 1736 +#define Mips_HSUB_S_D 1737 +#define Mips_HSUB_S_H 1738 +#define Mips_HSUB_S_W 1739 +#define Mips_HSUB_U_D 1740 +#define Mips_HSUB_U_H 1741 +#define Mips_HSUB_U_W 1742 +#define Mips_HYPCALL 1743 +#define Mips_HYPCALL_MM 1744 +#define Mips_ILVEV_B 1745 +#define Mips_ILVEV_D 1746 +#define Mips_ILVEV_H 1747 +#define Mips_ILVEV_W 1748 +#define Mips_ILVL_B 1749 +#define Mips_ILVL_D 1750 +#define Mips_ILVL_H 1751 +#define Mips_ILVL_W 1752 +#define Mips_ILVOD_B 1753 +#define Mips_ILVOD_D 1754 +#define Mips_ILVOD_H 1755 +#define Mips_ILVOD_W 1756 +#define Mips_ILVR_B 1757 +#define Mips_ILVR_D 1758 +#define Mips_ILVR_H 1759 +#define Mips_ILVR_W 1760 +#define Mips_INS 1761 +#define Mips_INSERT_B 1762 +#define Mips_INSERT_D 1763 +#define Mips_INSERT_H 1764 +#define Mips_INSERT_W 1765 +#define Mips_INSV 1766 +#define Mips_INSVE_B 1767 +#define Mips_INSVE_D 1768 +#define Mips_INSVE_H 1769 +#define Mips_INSVE_W 1770 +#define Mips_INSV_MM 1771 +#define Mips_INS_MM 1772 +#define Mips_INS_MMR6 1773 +#define Mips_J 1774 +#define Mips_JAL 1775 +#define Mips_JALR 1776 +#define Mips_JALR16_MM 1777 +#define Mips_JALR64 1778 +#define Mips_JALRC16_MMR6 1779 +#define Mips_JALRC_HB_MMR6 1780 +#define Mips_JALRC_MMR6 1781 +#define Mips_JALRS16_MM 1782 +#define Mips_JALRS_MM 1783 +#define Mips_JALR_HB 1784 +#define Mips_JALR_HB64 1785 +#define Mips_JALR_MM 1786 +#define Mips_JALS_MM 1787 +#define Mips_JALX 1788 +#define Mips_JALX_MM 1789 +#define Mips_JAL_MM 1790 +#define Mips_JIALC 1791 +#define Mips_JIALC64 1792 +#define Mips_JIALC_MMR6 1793 +#define Mips_JIC 1794 +#define Mips_JIC64 1795 +#define Mips_JIC_MMR6 1796 +#define Mips_JR 1797 +#define Mips_JR16_MM 1798 +#define Mips_JR64 1799 +#define Mips_JRADDIUSP 1800 +#define Mips_JRC16_MM 1801 +#define Mips_JRC16_MMR6 1802 +#define Mips_JRCADDIUSP_MMR6 1803 +#define Mips_JR_HB 1804 +#define Mips_JR_HB64 1805 +#define Mips_JR_HB64_R6 1806 +#define Mips_JR_HB_R6 1807 +#define Mips_JR_MM 1808 +#define Mips_J_MM 1809 +#define Mips_Jal16 1810 +#define Mips_JalB16 1811 +#define Mips_JrRa16 1812 +#define Mips_JrcRa16 1813 +#define Mips_JrcRx16 1814 +#define Mips_JumpLinkReg16 1815 +#define Mips_LB 1816 +#define Mips_LB64 1817 +#define Mips_LBE 1818 +#define Mips_LBE_MM 1819 +#define Mips_LBU16_MM 1820 +#define Mips_LBUX 1821 +#define Mips_LBUX_MM 1822 +#define Mips_LBU_MMR6 1823 +#define Mips_LB_MM 1824 +#define Mips_LB_MMR6 1825 +#define Mips_LBu 1826 +#define Mips_LBu64 1827 +#define Mips_LBuE 1828 +#define Mips_LBuE_MM 1829 +#define Mips_LBu_MM 1830 +#define Mips_LD 1831 +#define Mips_LDC1 1832 +#define Mips_LDC164 1833 +#define Mips_LDC1_D64_MMR6 1834 +#define Mips_LDC1_MM 1835 +#define Mips_LDC2 1836 +#define Mips_LDC2_MMR6 1837 +#define Mips_LDC2_R6 1838 +#define Mips_LDC3 1839 +#define Mips_LDI_B 1840 +#define Mips_LDI_D 1841 +#define Mips_LDI_H 1842 +#define Mips_LDI_W 1843 +#define Mips_LDL 1844 +#define Mips_LDPC 1845 +#define Mips_LDR 1846 +#define Mips_LDXC1 1847 +#define Mips_LDXC164 1848 +#define Mips_LD_B 1849 +#define Mips_LD_D 1850 +#define Mips_LD_H 1851 +#define Mips_LD_W 1852 +#define Mips_LEA_ADDiu 1853 +#define Mips_LEA_ADDiu64 1854 +#define Mips_LEA_ADDiu_MM 1855 +#define Mips_LH 1856 +#define Mips_LH64 1857 +#define Mips_LHE 1858 +#define Mips_LHE_MM 1859 +#define Mips_LHU16_MM 1860 +#define Mips_LHX 1861 +#define Mips_LHX_MM 1862 +#define Mips_LH_MM 1863 +#define Mips_LHu 1864 +#define Mips_LHu64 1865 +#define Mips_LHuE 1866 +#define Mips_LHuE_MM 1867 +#define Mips_LHu_MM 1868 +#define Mips_LI16_MM 1869 +#define Mips_LI16_MMR6 1870 +#define Mips_LL 1871 +#define Mips_LL64 1872 +#define Mips_LL64_R6 1873 +#define Mips_LLD 1874 +#define Mips_LLD_R6 1875 +#define Mips_LLE 1876 +#define Mips_LLE_MM 1877 +#define Mips_LL_MM 1878 +#define Mips_LL_MMR6 1879 +#define Mips_LL_R6 1880 +#define Mips_LSA 1881 +#define Mips_LSA_MMR6 1882 +#define Mips_LSA_R6 1883 +#define Mips_LUI_MMR6 1884 +#define Mips_LUXC1 1885 +#define Mips_LUXC164 1886 +#define Mips_LUXC1_MM 1887 +#define Mips_LUi 1888 +#define Mips_LUi64 1889 +#define Mips_LUi_MM 1890 +#define Mips_LW 1891 +#define Mips_LW16_MM 1892 +#define Mips_LW64 1893 +#define Mips_LWC1 1894 +#define Mips_LWC1_MM 1895 +#define Mips_LWC2 1896 +#define Mips_LWC2_MMR6 1897 +#define Mips_LWC2_R6 1898 +#define Mips_LWC3 1899 +#define Mips_LWDSP 1900 +#define Mips_LWDSP_MM 1901 +#define Mips_LWE 1902 +#define Mips_LWE_MM 1903 +#define Mips_LWGP_MM 1904 +#define Mips_LWL 1905 +#define Mips_LWL64 1906 +#define Mips_LWLE 1907 +#define Mips_LWLE_MM 1908 +#define Mips_LWL_MM 1909 +#define Mips_LWM16_MM 1910 +#define Mips_LWM16_MMR6 1911 +#define Mips_LWM32_MM 1912 +#define Mips_LWPC 1913 +#define Mips_LWPC_MMR6 1914 +#define Mips_LWP_MM 1915 +#define Mips_LWR 1916 +#define Mips_LWR64 1917 +#define Mips_LWRE 1918 +#define Mips_LWRE_MM 1919 +#define Mips_LWR_MM 1920 +#define Mips_LWSP_MM 1921 +#define Mips_LWUPC 1922 +#define Mips_LWU_MM 1923 +#define Mips_LWX 1924 +#define Mips_LWXC1 1925 +#define Mips_LWXC1_MM 1926 +#define Mips_LWXS_MM 1927 +#define Mips_LWX_MM 1928 +#define Mips_LW_MM 1929 +#define Mips_LW_MMR6 1930 +#define Mips_LWu 1931 +#define Mips_LbRxRyOffMemX16 1932 +#define Mips_LbuRxRyOffMemX16 1933 +#define Mips_LhRxRyOffMemX16 1934 +#define Mips_LhuRxRyOffMemX16 1935 +#define Mips_LiRxImm16 1936 +#define Mips_LiRxImmAlignX16 1937 +#define Mips_LiRxImmX16 1938 +#define Mips_LwRxPcTcp16 1939 +#define Mips_LwRxPcTcpX16 1940 +#define Mips_LwRxRyOffMemX16 1941 +#define Mips_LwRxSpImmX16 1942 +#define Mips_MADD 1943 +#define Mips_MADDF_D 1944 +#define Mips_MADDF_D_MMR6 1945 +#define Mips_MADDF_S 1946 +#define Mips_MADDF_S_MMR6 1947 +#define Mips_MADDR_Q_H 1948 +#define Mips_MADDR_Q_W 1949 +#define Mips_MADDU 1950 +#define Mips_MADDU_DSP 1951 +#define Mips_MADDU_DSP_MM 1952 +#define Mips_MADDU_MM 1953 +#define Mips_MADDV_B 1954 +#define Mips_MADDV_D 1955 +#define Mips_MADDV_H 1956 +#define Mips_MADDV_W 1957 +#define Mips_MADD_D32 1958 +#define Mips_MADD_D32_MM 1959 +#define Mips_MADD_D64 1960 +#define Mips_MADD_DSP 1961 +#define Mips_MADD_DSP_MM 1962 +#define Mips_MADD_MM 1963 +#define Mips_MADD_Q_H 1964 +#define Mips_MADD_Q_W 1965 +#define Mips_MADD_S 1966 +#define Mips_MADD_S_MM 1967 +#define Mips_MAQ_SA_W_PHL 1968 +#define Mips_MAQ_SA_W_PHL_MM 1969 +#define Mips_MAQ_SA_W_PHR 1970 +#define Mips_MAQ_SA_W_PHR_MM 1971 +#define Mips_MAQ_S_W_PHL 1972 +#define Mips_MAQ_S_W_PHL_MM 1973 +#define Mips_MAQ_S_W_PHR 1974 +#define Mips_MAQ_S_W_PHR_MM 1975 +#define Mips_MAXA_D 1976 +#define Mips_MAXA_D_MMR6 1977 +#define Mips_MAXA_S 1978 +#define Mips_MAXA_S_MMR6 1979 +#define Mips_MAXI_S_B 1980 +#define Mips_MAXI_S_D 1981 +#define Mips_MAXI_S_H 1982 +#define Mips_MAXI_S_W 1983 +#define Mips_MAXI_U_B 1984 +#define Mips_MAXI_U_D 1985 +#define Mips_MAXI_U_H 1986 +#define Mips_MAXI_U_W 1987 +#define Mips_MAX_A_B 1988 +#define Mips_MAX_A_D 1989 +#define Mips_MAX_A_H 1990 +#define Mips_MAX_A_W 1991 +#define Mips_MAX_D 1992 +#define Mips_MAX_D_MMR6 1993 +#define Mips_MAX_S 1994 +#define Mips_MAX_S_B 1995 +#define Mips_MAX_S_D 1996 +#define Mips_MAX_S_H 1997 +#define Mips_MAX_S_MMR6 1998 +#define Mips_MAX_S_W 1999 +#define Mips_MAX_U_B 2000 +#define Mips_MAX_U_D 2001 +#define Mips_MAX_U_H 2002 +#define Mips_MAX_U_W 2003 +#define Mips_MFC0 2004 +#define Mips_MFC0_MMR6 2005 +#define Mips_MFC1 2006 +#define Mips_MFC1_D64 2007 +#define Mips_MFC1_MM 2008 +#define Mips_MFC1_MMR6 2009 +#define Mips_MFC2 2010 +#define Mips_MFC2_MMR6 2011 +#define Mips_MFGC0 2012 +#define Mips_MFGC0_MM 2013 +#define Mips_MFHC0_MMR6 2014 +#define Mips_MFHC1_D32 2015 +#define Mips_MFHC1_D32_MM 2016 +#define Mips_MFHC1_D64 2017 +#define Mips_MFHC1_D64_MM 2018 +#define Mips_MFHC2_MMR6 2019 +#define Mips_MFHGC0 2020 +#define Mips_MFHGC0_MM 2021 +#define Mips_MFHI 2022 +#define Mips_MFHI16_MM 2023 +#define Mips_MFHI64 2024 +#define Mips_MFHI_DSP 2025 +#define Mips_MFHI_DSP_MM 2026 +#define Mips_MFHI_MM 2027 +#define Mips_MFLO 2028 +#define Mips_MFLO16_MM 2029 +#define Mips_MFLO64 2030 +#define Mips_MFLO_DSP 2031 +#define Mips_MFLO_DSP_MM 2032 +#define Mips_MFLO_MM 2033 +#define Mips_MFTR 2034 +#define Mips_MINA_D 2035 +#define Mips_MINA_D_MMR6 2036 +#define Mips_MINA_S 2037 +#define Mips_MINA_S_MMR6 2038 +#define Mips_MINI_S_B 2039 +#define Mips_MINI_S_D 2040 +#define Mips_MINI_S_H 2041 +#define Mips_MINI_S_W 2042 +#define Mips_MINI_U_B 2043 +#define Mips_MINI_U_D 2044 +#define Mips_MINI_U_H 2045 +#define Mips_MINI_U_W 2046 +#define Mips_MIN_A_B 2047 +#define Mips_MIN_A_D 2048 +#define Mips_MIN_A_H 2049 +#define Mips_MIN_A_W 2050 +#define Mips_MIN_D 2051 +#define Mips_MIN_D_MMR6 2052 +#define Mips_MIN_S 2053 +#define Mips_MIN_S_B 2054 +#define Mips_MIN_S_D 2055 +#define Mips_MIN_S_H 2056 +#define Mips_MIN_S_MMR6 2057 +#define Mips_MIN_S_W 2058 +#define Mips_MIN_U_B 2059 +#define Mips_MIN_U_D 2060 +#define Mips_MIN_U_H 2061 +#define Mips_MIN_U_W 2062 +#define Mips_MOD 2063 +#define Mips_MODSUB 2064 +#define Mips_MODSUB_MM 2065 +#define Mips_MODU 2066 +#define Mips_MODU_MMR6 2067 +#define Mips_MOD_MMR6 2068 +#define Mips_MOD_S_B 2069 +#define Mips_MOD_S_D 2070 +#define Mips_MOD_S_H 2071 +#define Mips_MOD_S_W 2072 +#define Mips_MOD_U_B 2073 +#define Mips_MOD_U_D 2074 +#define Mips_MOD_U_H 2075 +#define Mips_MOD_U_W 2076 +#define Mips_MOVE16_MM 2077 +#define Mips_MOVE16_MMR6 2078 +#define Mips_MOVEP_MM 2079 +#define Mips_MOVEP_MMR6 2080 +#define Mips_MOVE_V 2081 +#define Mips_MOVF_D32 2082 +#define Mips_MOVF_D32_MM 2083 +#define Mips_MOVF_D64 2084 +#define Mips_MOVF_I 2085 +#define Mips_MOVF_I64 2086 +#define Mips_MOVF_I_MM 2087 +#define Mips_MOVF_S 2088 +#define Mips_MOVF_S_MM 2089 +#define Mips_MOVN_I64_D64 2090 +#define Mips_MOVN_I64_I 2091 +#define Mips_MOVN_I64_I64 2092 +#define Mips_MOVN_I64_S 2093 +#define Mips_MOVN_I_D32 2094 +#define Mips_MOVN_I_D32_MM 2095 +#define Mips_MOVN_I_D64 2096 +#define Mips_MOVN_I_I 2097 +#define Mips_MOVN_I_I64 2098 +#define Mips_MOVN_I_MM 2099 +#define Mips_MOVN_I_S 2100 +#define Mips_MOVN_I_S_MM 2101 +#define Mips_MOVT_D32 2102 +#define Mips_MOVT_D32_MM 2103 +#define Mips_MOVT_D64 2104 +#define Mips_MOVT_I 2105 +#define Mips_MOVT_I64 2106 +#define Mips_MOVT_I_MM 2107 +#define Mips_MOVT_S 2108 +#define Mips_MOVT_S_MM 2109 +#define Mips_MOVZ_I64_D64 2110 +#define Mips_MOVZ_I64_I 2111 +#define Mips_MOVZ_I64_I64 2112 +#define Mips_MOVZ_I64_S 2113 +#define Mips_MOVZ_I_D32 2114 +#define Mips_MOVZ_I_D32_MM 2115 +#define Mips_MOVZ_I_D64 2116 +#define Mips_MOVZ_I_I 2117 +#define Mips_MOVZ_I_I64 2118 +#define Mips_MOVZ_I_MM 2119 +#define Mips_MOVZ_I_S 2120 +#define Mips_MOVZ_I_S_MM 2121 +#define Mips_MSUB 2122 +#define Mips_MSUBF_D 2123 +#define Mips_MSUBF_D_MMR6 2124 +#define Mips_MSUBF_S 2125 +#define Mips_MSUBF_S_MMR6 2126 +#define Mips_MSUBR_Q_H 2127 +#define Mips_MSUBR_Q_W 2128 +#define Mips_MSUBU 2129 +#define Mips_MSUBU_DSP 2130 +#define Mips_MSUBU_DSP_MM 2131 +#define Mips_MSUBU_MM 2132 +#define Mips_MSUBV_B 2133 +#define Mips_MSUBV_D 2134 +#define Mips_MSUBV_H 2135 +#define Mips_MSUBV_W 2136 +#define Mips_MSUB_D32 2137 +#define Mips_MSUB_D32_MM 2138 +#define Mips_MSUB_D64 2139 +#define Mips_MSUB_DSP 2140 +#define Mips_MSUB_DSP_MM 2141 +#define Mips_MSUB_MM 2142 +#define Mips_MSUB_Q_H 2143 +#define Mips_MSUB_Q_W 2144 +#define Mips_MSUB_S 2145 +#define Mips_MSUB_S_MM 2146 +#define Mips_MTC0 2147 +#define Mips_MTC0_MMR6 2148 +#define Mips_MTC1 2149 +#define Mips_MTC1_D64 2150 +#define Mips_MTC1_D64_MM 2151 +#define Mips_MTC1_MM 2152 +#define Mips_MTC1_MMR6 2153 +#define Mips_MTC2 2154 +#define Mips_MTC2_MMR6 2155 +#define Mips_MTGC0 2156 +#define Mips_MTGC0_MM 2157 +#define Mips_MTHC0_MMR6 2158 +#define Mips_MTHC1_D32 2159 +#define Mips_MTHC1_D32_MM 2160 +#define Mips_MTHC1_D64 2161 +#define Mips_MTHC1_D64_MM 2162 +#define Mips_MTHC2_MMR6 2163 +#define Mips_MTHGC0 2164 +#define Mips_MTHGC0_MM 2165 +#define Mips_MTHI 2166 +#define Mips_MTHI64 2167 +#define Mips_MTHI_DSP 2168 +#define Mips_MTHI_DSP_MM 2169 +#define Mips_MTHI_MM 2170 +#define Mips_MTHLIP 2171 +#define Mips_MTHLIP_MM 2172 +#define Mips_MTLO 2173 +#define Mips_MTLO64 2174 +#define Mips_MTLO_DSP 2175 +#define Mips_MTLO_DSP_MM 2176 +#define Mips_MTLO_MM 2177 +#define Mips_MTM0 2178 +#define Mips_MTM1 2179 +#define Mips_MTM2 2180 +#define Mips_MTP0 2181 +#define Mips_MTP1 2182 +#define Mips_MTP2 2183 +#define Mips_MTTR 2184 +#define Mips_MUH 2185 +#define Mips_MUHU 2186 +#define Mips_MUHU_MMR6 2187 +#define Mips_MUH_MMR6 2188 +#define Mips_MUL 2189 +#define Mips_MULEQ_S_W_PHL 2190 +#define Mips_MULEQ_S_W_PHL_MM 2191 +#define Mips_MULEQ_S_W_PHR 2192 +#define Mips_MULEQ_S_W_PHR_MM 2193 +#define Mips_MULEU_S_PH_QBL 2194 +#define Mips_MULEU_S_PH_QBL_MM 2195 +#define Mips_MULEU_S_PH_QBR 2196 +#define Mips_MULEU_S_PH_QBR_MM 2197 +#define Mips_MULQ_RS_PH 2198 +#define Mips_MULQ_RS_PH_MM 2199 +#define Mips_MULQ_RS_W 2200 +#define Mips_MULQ_RS_W_MMR2 2201 +#define Mips_MULQ_S_PH 2202 +#define Mips_MULQ_S_PH_MMR2 2203 +#define Mips_MULQ_S_W 2204 +#define Mips_MULQ_S_W_MMR2 2205 +#define Mips_MULR_PS64 2206 +#define Mips_MULR_Q_H 2207 +#define Mips_MULR_Q_W 2208 +#define Mips_MULSAQ_S_W_PH 2209 +#define Mips_MULSAQ_S_W_PH_MM 2210 +#define Mips_MULSA_W_PH 2211 +#define Mips_MULSA_W_PH_MMR2 2212 +#define Mips_MULT 2213 +#define Mips_MULTU_DSP 2214 +#define Mips_MULTU_DSP_MM 2215 +#define Mips_MULT_DSP 2216 +#define Mips_MULT_DSP_MM 2217 +#define Mips_MULT_MM 2218 +#define Mips_MULTu 2219 +#define Mips_MULTu_MM 2220 +#define Mips_MULU 2221 +#define Mips_MULU_MMR6 2222 +#define Mips_MULV_B 2223 +#define Mips_MULV_D 2224 +#define Mips_MULV_H 2225 +#define Mips_MULV_W 2226 +#define Mips_MUL_MM 2227 +#define Mips_MUL_MMR6 2228 +#define Mips_MUL_PH 2229 +#define Mips_MUL_PH_MMR2 2230 +#define Mips_MUL_Q_H 2231 +#define Mips_MUL_Q_W 2232 +#define Mips_MUL_R6 2233 +#define Mips_MUL_S_PH 2234 +#define Mips_MUL_S_PH_MMR2 2235 +#define Mips_Mfhi16 2236 +#define Mips_Mflo16 2237 +#define Mips_Move32R16 2238 +#define Mips_MoveR3216 2239 +#define Mips_NLOC_B 2240 +#define Mips_NLOC_D 2241 +#define Mips_NLOC_H 2242 +#define Mips_NLOC_W 2243 +#define Mips_NLZC_B 2244 +#define Mips_NLZC_D 2245 +#define Mips_NLZC_H 2246 +#define Mips_NLZC_W 2247 +#define Mips_NMADD_D32 2248 +#define Mips_NMADD_D32_MM 2249 +#define Mips_NMADD_D64 2250 +#define Mips_NMADD_S 2251 +#define Mips_NMADD_S_MM 2252 +#define Mips_NMSUB_D32 2253 +#define Mips_NMSUB_D32_MM 2254 +#define Mips_NMSUB_D64 2255 +#define Mips_NMSUB_S 2256 +#define Mips_NMSUB_S_MM 2257 +#define Mips_NOR 2258 +#define Mips_NOR64 2259 +#define Mips_NORI_B 2260 +#define Mips_NOR_MM 2261 +#define Mips_NOR_MMR6 2262 +#define Mips_NOR_V 2263 +#define Mips_NOT16_MM 2264 +#define Mips_NOT16_MMR6 2265 +#define Mips_NegRxRy16 2266 +#define Mips_NotRxRy16 2267 +#define Mips_OR 2268 +#define Mips_OR16_MM 2269 +#define Mips_OR16_MMR6 2270 +#define Mips_OR64 2271 +#define Mips_ORI_B 2272 +#define Mips_ORI_MMR6 2273 +#define Mips_OR_MM 2274 +#define Mips_OR_MMR6 2275 +#define Mips_OR_V 2276 +#define Mips_ORi 2277 +#define Mips_ORi64 2278 +#define Mips_ORi_MM 2279 +#define Mips_OrRxRxRy16 2280 +#define Mips_PACKRL_PH 2281 +#define Mips_PACKRL_PH_MM 2282 +#define Mips_PAUSE 2283 +#define Mips_PAUSE_MM 2284 +#define Mips_PAUSE_MMR6 2285 +#define Mips_PCKEV_B 2286 +#define Mips_PCKEV_D 2287 +#define Mips_PCKEV_H 2288 +#define Mips_PCKEV_W 2289 +#define Mips_PCKOD_B 2290 +#define Mips_PCKOD_D 2291 +#define Mips_PCKOD_H 2292 +#define Mips_PCKOD_W 2293 +#define Mips_PCNT_B 2294 +#define Mips_PCNT_D 2295 +#define Mips_PCNT_H 2296 +#define Mips_PCNT_W 2297 +#define Mips_PICK_PH 2298 +#define Mips_PICK_PH_MM 2299 +#define Mips_PICK_QB 2300 +#define Mips_PICK_QB_MM 2301 +#define Mips_PLL_PS64 2302 +#define Mips_PLU_PS64 2303 +#define Mips_POP 2304 +#define Mips_PRECEQU_PH_QBL 2305 +#define Mips_PRECEQU_PH_QBLA 2306 +#define Mips_PRECEQU_PH_QBLA_MM 2307 +#define Mips_PRECEQU_PH_QBL_MM 2308 +#define Mips_PRECEQU_PH_QBR 2309 +#define Mips_PRECEQU_PH_QBRA 2310 +#define Mips_PRECEQU_PH_QBRA_MM 2311 +#define Mips_PRECEQU_PH_QBR_MM 2312 +#define Mips_PRECEQ_W_PHL 2313 +#define Mips_PRECEQ_W_PHL_MM 2314 +#define Mips_PRECEQ_W_PHR 2315 +#define Mips_PRECEQ_W_PHR_MM 2316 +#define Mips_PRECEU_PH_QBL 2317 +#define Mips_PRECEU_PH_QBLA 2318 +#define Mips_PRECEU_PH_QBLA_MM 2319 +#define Mips_PRECEU_PH_QBL_MM 2320 +#define Mips_PRECEU_PH_QBR 2321 +#define Mips_PRECEU_PH_QBRA 2322 +#define Mips_PRECEU_PH_QBRA_MM 2323 +#define Mips_PRECEU_PH_QBR_MM 2324 +#define Mips_PRECRQU_S_QB_PH 2325 +#define Mips_PRECRQU_S_QB_PH_MM 2326 +#define Mips_PRECRQ_PH_W 2327 +#define Mips_PRECRQ_PH_W_MM 2328 +#define Mips_PRECRQ_QB_PH 2329 +#define Mips_PRECRQ_QB_PH_MM 2330 +#define Mips_PRECRQ_RS_PH_W 2331 +#define Mips_PRECRQ_RS_PH_W_MM 2332 +#define Mips_PRECR_QB_PH 2333 +#define Mips_PRECR_QB_PH_MMR2 2334 +#define Mips_PRECR_SRA_PH_W 2335 +#define Mips_PRECR_SRA_PH_W_MMR2 2336 +#define Mips_PRECR_SRA_R_PH_W 2337 +#define Mips_PRECR_SRA_R_PH_W_MMR2 2338 +#define Mips_PREF 2339 +#define Mips_PREFE 2340 +#define Mips_PREFE_MM 2341 +#define Mips_PREFX_MM 2342 +#define Mips_PREF_MM 2343 +#define Mips_PREF_MMR6 2344 +#define Mips_PREF_R6 2345 +#define Mips_PREPEND 2346 +#define Mips_PREPEND_MMR2 2347 +#define Mips_PUL_PS64 2348 +#define Mips_PUU_PS64 2349 +#define Mips_RADDU_W_QB 2350 +#define Mips_RADDU_W_QB_MM 2351 +#define Mips_RDDSP 2352 +#define Mips_RDDSP_MM 2353 +#define Mips_RDHWR 2354 +#define Mips_RDHWR64 2355 +#define Mips_RDHWR_MM 2356 +#define Mips_RDHWR_MMR6 2357 +#define Mips_RDPGPR_MMR6 2358 +#define Mips_RECIP_D32 2359 +#define Mips_RECIP_D32_MM 2360 +#define Mips_RECIP_D64 2361 +#define Mips_RECIP_D64_MM 2362 +#define Mips_RECIP_S 2363 +#define Mips_RECIP_S_MM 2364 +#define Mips_REPLV_PH 2365 +#define Mips_REPLV_PH_MM 2366 +#define Mips_REPLV_QB 2367 +#define Mips_REPLV_QB_MM 2368 +#define Mips_REPL_PH 2369 +#define Mips_REPL_PH_MM 2370 +#define Mips_REPL_QB 2371 +#define Mips_REPL_QB_MM 2372 +#define Mips_RINT_D 2373 +#define Mips_RINT_D_MMR6 2374 +#define Mips_RINT_S 2375 +#define Mips_RINT_S_MMR6 2376 +#define Mips_ROTR 2377 +#define Mips_ROTRV 2378 +#define Mips_ROTRV_MM 2379 +#define Mips_ROTR_MM 2380 +#define Mips_ROUND_L_D64 2381 +#define Mips_ROUND_L_D_MMR6 2382 +#define Mips_ROUND_L_S 2383 +#define Mips_ROUND_L_S_MMR6 2384 +#define Mips_ROUND_W_D32 2385 +#define Mips_ROUND_W_D64 2386 +#define Mips_ROUND_W_D_MMR6 2387 +#define Mips_ROUND_W_MM 2388 +#define Mips_ROUND_W_S 2389 +#define Mips_ROUND_W_S_MM 2390 +#define Mips_ROUND_W_S_MMR6 2391 +#define Mips_RSQRT_D32 2392 +#define Mips_RSQRT_D32_MM 2393 +#define Mips_RSQRT_D64 2394 +#define Mips_RSQRT_D64_MM 2395 +#define Mips_RSQRT_S 2396 +#define Mips_RSQRT_S_MM 2397 +#define Mips_Restore16 2398 +#define Mips_RestoreX16 2399 +#define Mips_SAA 2400 +#define Mips_SAAD 2401 +#define Mips_SAT_S_B 2402 +#define Mips_SAT_S_D 2403 +#define Mips_SAT_S_H 2404 +#define Mips_SAT_S_W 2405 +#define Mips_SAT_U_B 2406 +#define Mips_SAT_U_D 2407 +#define Mips_SAT_U_H 2408 +#define Mips_SAT_U_W 2409 +#define Mips_SB 2410 +#define Mips_SB16_MM 2411 +#define Mips_SB16_MMR6 2412 +#define Mips_SB64 2413 +#define Mips_SBE 2414 +#define Mips_SBE_MM 2415 +#define Mips_SB_MM 2416 +#define Mips_SB_MMR6 2417 +#define Mips_SC 2418 +#define Mips_SC64 2419 +#define Mips_SC64_R6 2420 +#define Mips_SCD 2421 +#define Mips_SCD_R6 2422 +#define Mips_SCE 2423 +#define Mips_SCE_MM 2424 +#define Mips_SC_MM 2425 +#define Mips_SC_MMR6 2426 +#define Mips_SC_R6 2427 +#define Mips_SD 2428 +#define Mips_SDBBP 2429 +#define Mips_SDBBP16_MM 2430 +#define Mips_SDBBP16_MMR6 2431 +#define Mips_SDBBP_MM 2432 +#define Mips_SDBBP_MMR6 2433 +#define Mips_SDBBP_R6 2434 +#define Mips_SDC1 2435 +#define Mips_SDC164 2436 +#define Mips_SDC1_D64_MMR6 2437 +#define Mips_SDC1_MM 2438 +#define Mips_SDC2 2439 +#define Mips_SDC2_MMR6 2440 +#define Mips_SDC2_R6 2441 +#define Mips_SDC3 2442 +#define Mips_SDIV 2443 +#define Mips_SDIV_MM 2444 +#define Mips_SDL 2445 +#define Mips_SDR 2446 +#define Mips_SDXC1 2447 +#define Mips_SDXC164 2448 +#define Mips_SEB 2449 +#define Mips_SEB64 2450 +#define Mips_SEB_MM 2451 +#define Mips_SEH 2452 +#define Mips_SEH64 2453 +#define Mips_SEH_MM 2454 +#define Mips_SELEQZ 2455 +#define Mips_SELEQZ64 2456 +#define Mips_SELEQZ_D 2457 +#define Mips_SELEQZ_D_MMR6 2458 +#define Mips_SELEQZ_MMR6 2459 +#define Mips_SELEQZ_S 2460 +#define Mips_SELEQZ_S_MMR6 2461 +#define Mips_SELNEZ 2462 +#define Mips_SELNEZ64 2463 +#define Mips_SELNEZ_D 2464 +#define Mips_SELNEZ_D_MMR6 2465 +#define Mips_SELNEZ_MMR6 2466 +#define Mips_SELNEZ_S 2467 +#define Mips_SELNEZ_S_MMR6 2468 +#define Mips_SEL_D 2469 +#define Mips_SEL_D_MMR6 2470 +#define Mips_SEL_S 2471 +#define Mips_SEL_S_MMR6 2472 +#define Mips_SEQ 2473 +#define Mips_SEQi 2474 +#define Mips_SH 2475 +#define Mips_SH16_MM 2476 +#define Mips_SH16_MMR6 2477 +#define Mips_SH64 2478 +#define Mips_SHE 2479 +#define Mips_SHE_MM 2480 +#define Mips_SHF_B 2481 +#define Mips_SHF_H 2482 +#define Mips_SHF_W 2483 +#define Mips_SHILO 2484 +#define Mips_SHILOV 2485 +#define Mips_SHILOV_MM 2486 +#define Mips_SHILO_MM 2487 +#define Mips_SHLLV_PH 2488 +#define Mips_SHLLV_PH_MM 2489 +#define Mips_SHLLV_QB 2490 +#define Mips_SHLLV_QB_MM 2491 +#define Mips_SHLLV_S_PH 2492 +#define Mips_SHLLV_S_PH_MM 2493 +#define Mips_SHLLV_S_W 2494 +#define Mips_SHLLV_S_W_MM 2495 +#define Mips_SHLL_PH 2496 +#define Mips_SHLL_PH_MM 2497 +#define Mips_SHLL_QB 2498 +#define Mips_SHLL_QB_MM 2499 +#define Mips_SHLL_S_PH 2500 +#define Mips_SHLL_S_PH_MM 2501 +#define Mips_SHLL_S_W 2502 +#define Mips_SHLL_S_W_MM 2503 +#define Mips_SHRAV_PH 2504 +#define Mips_SHRAV_PH_MM 2505 +#define Mips_SHRAV_QB 2506 +#define Mips_SHRAV_QB_MMR2 2507 +#define Mips_SHRAV_R_PH 2508 +#define Mips_SHRAV_R_PH_MM 2509 +#define Mips_SHRAV_R_QB 2510 +#define Mips_SHRAV_R_QB_MMR2 2511 +#define Mips_SHRAV_R_W 2512 +#define Mips_SHRAV_R_W_MM 2513 +#define Mips_SHRA_PH 2514 +#define Mips_SHRA_PH_MM 2515 +#define Mips_SHRA_QB 2516 +#define Mips_SHRA_QB_MMR2 2517 +#define Mips_SHRA_R_PH 2518 +#define Mips_SHRA_R_PH_MM 2519 +#define Mips_SHRA_R_QB 2520 +#define Mips_SHRA_R_QB_MMR2 2521 +#define Mips_SHRA_R_W 2522 +#define Mips_SHRA_R_W_MM 2523 +#define Mips_SHRLV_PH 2524 +#define Mips_SHRLV_PH_MMR2 2525 +#define Mips_SHRLV_QB 2526 +#define Mips_SHRLV_QB_MM 2527 +#define Mips_SHRL_PH 2528 +#define Mips_SHRL_PH_MMR2 2529 +#define Mips_SHRL_QB 2530 +#define Mips_SHRL_QB_MM 2531 +#define Mips_SH_MM 2532 +#define Mips_SH_MMR6 2533 +#define Mips_SIGRIE 2534 +#define Mips_SIGRIE_MMR6 2535 +#define Mips_SLDI_B 2536 +#define Mips_SLDI_D 2537 +#define Mips_SLDI_H 2538 +#define Mips_SLDI_W 2539 +#define Mips_SLD_B 2540 +#define Mips_SLD_D 2541 +#define Mips_SLD_H 2542 +#define Mips_SLD_W 2543 +#define Mips_SLL 2544 +#define Mips_SLL16_MM 2545 +#define Mips_SLL16_MMR6 2546 +#define Mips_SLL64_32 2547 +#define Mips_SLL64_64 2548 +#define Mips_SLLI_B 2549 +#define Mips_SLLI_D 2550 +#define Mips_SLLI_H 2551 +#define Mips_SLLI_W 2552 +#define Mips_SLLV 2553 +#define Mips_SLLV_MM 2554 +#define Mips_SLL_B 2555 +#define Mips_SLL_D 2556 +#define Mips_SLL_H 2557 +#define Mips_SLL_MM 2558 +#define Mips_SLL_MMR6 2559 +#define Mips_SLL_W 2560 +#define Mips_SLT 2561 +#define Mips_SLT64 2562 +#define Mips_SLT_MM 2563 +#define Mips_SLTi 2564 +#define Mips_SLTi64 2565 +#define Mips_SLTi_MM 2566 +#define Mips_SLTiu 2567 +#define Mips_SLTiu64 2568 +#define Mips_SLTiu_MM 2569 +#define Mips_SLTu 2570 +#define Mips_SLTu64 2571 +#define Mips_SLTu_MM 2572 +#define Mips_SNE 2573 +#define Mips_SNEi 2574 +#define Mips_SPLATI_B 2575 +#define Mips_SPLATI_D 2576 +#define Mips_SPLATI_H 2577 +#define Mips_SPLATI_W 2578 +#define Mips_SPLAT_B 2579 +#define Mips_SPLAT_D 2580 +#define Mips_SPLAT_H 2581 +#define Mips_SPLAT_W 2582 +#define Mips_SRA 2583 +#define Mips_SRAI_B 2584 +#define Mips_SRAI_D 2585 +#define Mips_SRAI_H 2586 +#define Mips_SRAI_W 2587 +#define Mips_SRARI_B 2588 +#define Mips_SRARI_D 2589 +#define Mips_SRARI_H 2590 +#define Mips_SRARI_W 2591 +#define Mips_SRAR_B 2592 +#define Mips_SRAR_D 2593 +#define Mips_SRAR_H 2594 +#define Mips_SRAR_W 2595 +#define Mips_SRAV 2596 +#define Mips_SRAV_MM 2597 +#define Mips_SRA_B 2598 +#define Mips_SRA_D 2599 +#define Mips_SRA_H 2600 +#define Mips_SRA_MM 2601 +#define Mips_SRA_W 2602 +#define Mips_SRL 2603 +#define Mips_SRL16_MM 2604 +#define Mips_SRL16_MMR6 2605 +#define Mips_SRLI_B 2606 +#define Mips_SRLI_D 2607 +#define Mips_SRLI_H 2608 +#define Mips_SRLI_W 2609 +#define Mips_SRLRI_B 2610 +#define Mips_SRLRI_D 2611 +#define Mips_SRLRI_H 2612 +#define Mips_SRLRI_W 2613 +#define Mips_SRLR_B 2614 +#define Mips_SRLR_D 2615 +#define Mips_SRLR_H 2616 +#define Mips_SRLR_W 2617 +#define Mips_SRLV 2618 +#define Mips_SRLV_MM 2619 +#define Mips_SRL_B 2620 +#define Mips_SRL_D 2621 +#define Mips_SRL_H 2622 +#define Mips_SRL_MM 2623 +#define Mips_SRL_W 2624 +#define Mips_SSNOP 2625 +#define Mips_SSNOP_MM 2626 +#define Mips_SSNOP_MMR6 2627 +#define Mips_ST_B 2628 +#define Mips_ST_D 2629 +#define Mips_ST_H 2630 +#define Mips_ST_W 2631 +#define Mips_SUB 2632 +#define Mips_SUBQH_PH 2633 +#define Mips_SUBQH_PH_MMR2 2634 +#define Mips_SUBQH_R_PH 2635 +#define Mips_SUBQH_R_PH_MMR2 2636 +#define Mips_SUBQH_R_W 2637 +#define Mips_SUBQH_R_W_MMR2 2638 +#define Mips_SUBQH_W 2639 +#define Mips_SUBQH_W_MMR2 2640 +#define Mips_SUBQ_PH 2641 +#define Mips_SUBQ_PH_MM 2642 +#define Mips_SUBQ_S_PH 2643 +#define Mips_SUBQ_S_PH_MM 2644 +#define Mips_SUBQ_S_W 2645 +#define Mips_SUBQ_S_W_MM 2646 +#define Mips_SUBSUS_U_B 2647 +#define Mips_SUBSUS_U_D 2648 +#define Mips_SUBSUS_U_H 2649 +#define Mips_SUBSUS_U_W 2650 +#define Mips_SUBSUU_S_B 2651 +#define Mips_SUBSUU_S_D 2652 +#define Mips_SUBSUU_S_H 2653 +#define Mips_SUBSUU_S_W 2654 +#define Mips_SUBS_S_B 2655 +#define Mips_SUBS_S_D 2656 +#define Mips_SUBS_S_H 2657 +#define Mips_SUBS_S_W 2658 +#define Mips_SUBS_U_B 2659 +#define Mips_SUBS_U_D 2660 +#define Mips_SUBS_U_H 2661 +#define Mips_SUBS_U_W 2662 +#define Mips_SUBU16_MM 2663 +#define Mips_SUBU16_MMR6 2664 +#define Mips_SUBUH_QB 2665 +#define Mips_SUBUH_QB_MMR2 2666 +#define Mips_SUBUH_R_QB 2667 +#define Mips_SUBUH_R_QB_MMR2 2668 +#define Mips_SUBU_MMR6 2669 +#define Mips_SUBU_PH 2670 +#define Mips_SUBU_PH_MMR2 2671 +#define Mips_SUBU_QB 2672 +#define Mips_SUBU_QB_MM 2673 +#define Mips_SUBU_S_PH 2674 +#define Mips_SUBU_S_PH_MMR2 2675 +#define Mips_SUBU_S_QB 2676 +#define Mips_SUBU_S_QB_MM 2677 +#define Mips_SUBVI_B 2678 +#define Mips_SUBVI_D 2679 +#define Mips_SUBVI_H 2680 +#define Mips_SUBVI_W 2681 +#define Mips_SUBV_B 2682 +#define Mips_SUBV_D 2683 +#define Mips_SUBV_H 2684 +#define Mips_SUBV_W 2685 +#define Mips_SUB_MM 2686 +#define Mips_SUB_MMR6 2687 +#define Mips_SUBu 2688 +#define Mips_SUBu_MM 2689 +#define Mips_SUXC1 2690 +#define Mips_SUXC164 2691 +#define Mips_SUXC1_MM 2692 +#define Mips_SW 2693 +#define Mips_SW16_MM 2694 +#define Mips_SW16_MMR6 2695 +#define Mips_SW64 2696 +#define Mips_SWC1 2697 +#define Mips_SWC1_MM 2698 +#define Mips_SWC2 2699 +#define Mips_SWC2_MMR6 2700 +#define Mips_SWC2_R6 2701 +#define Mips_SWC3 2702 +#define Mips_SWDSP 2703 +#define Mips_SWDSP_MM 2704 +#define Mips_SWE 2705 +#define Mips_SWE_MM 2706 +#define Mips_SWL 2707 +#define Mips_SWL64 2708 +#define Mips_SWLE 2709 +#define Mips_SWLE_MM 2710 +#define Mips_SWL_MM 2711 +#define Mips_SWM16_MM 2712 +#define Mips_SWM16_MMR6 2713 +#define Mips_SWM32_MM 2714 +#define Mips_SWP_MM 2715 +#define Mips_SWR 2716 +#define Mips_SWR64 2717 +#define Mips_SWRE 2718 +#define Mips_SWRE_MM 2719 +#define Mips_SWR_MM 2720 +#define Mips_SWSP_MM 2721 +#define Mips_SWSP_MMR6 2722 +#define Mips_SWXC1 2723 +#define Mips_SWXC1_MM 2724 +#define Mips_SW_MM 2725 +#define Mips_SW_MMR6 2726 +#define Mips_SYNC 2727 +#define Mips_SYNCI 2728 +#define Mips_SYNCI_MM 2729 +#define Mips_SYNCI_MMR6 2730 +#define Mips_SYNC_MM 2731 +#define Mips_SYNC_MMR6 2732 +#define Mips_SYSCALL 2733 +#define Mips_SYSCALL_MM 2734 +#define Mips_Save16 2735 +#define Mips_SaveX16 2736 +#define Mips_SbRxRyOffMemX16 2737 +#define Mips_SebRx16 2738 +#define Mips_SehRx16 2739 +#define Mips_ShRxRyOffMemX16 2740 +#define Mips_SllX16 2741 +#define Mips_SllvRxRy16 2742 +#define Mips_SltRxRy16 2743 +#define Mips_SltiRxImm16 2744 +#define Mips_SltiRxImmX16 2745 +#define Mips_SltiuRxImm16 2746 +#define Mips_SltiuRxImmX16 2747 +#define Mips_SltuRxRy16 2748 +#define Mips_SraX16 2749 +#define Mips_SravRxRy16 2750 +#define Mips_SrlX16 2751 +#define Mips_SrlvRxRy16 2752 +#define Mips_SubuRxRyRz16 2753 +#define Mips_SwRxRyOffMemX16 2754 +#define Mips_SwRxSpImmX16 2755 +#define Mips_TEQ 2756 +#define Mips_TEQI 2757 +#define Mips_TEQI_MM 2758 +#define Mips_TEQ_MM 2759 +#define Mips_TGE 2760 +#define Mips_TGEI 2761 +#define Mips_TGEIU 2762 +#define Mips_TGEIU_MM 2763 +#define Mips_TGEI_MM 2764 +#define Mips_TGEU 2765 +#define Mips_TGEU_MM 2766 +#define Mips_TGE_MM 2767 +#define Mips_TLBGINV 2768 +#define Mips_TLBGINVF 2769 +#define Mips_TLBGINVF_MM 2770 +#define Mips_TLBGINV_MM 2771 +#define Mips_TLBGP 2772 +#define Mips_TLBGP_MM 2773 +#define Mips_TLBGR 2774 +#define Mips_TLBGR_MM 2775 +#define Mips_TLBGWI 2776 +#define Mips_TLBGWI_MM 2777 +#define Mips_TLBGWR 2778 +#define Mips_TLBGWR_MM 2779 +#define Mips_TLBINV 2780 +#define Mips_TLBINVF 2781 +#define Mips_TLBINVF_MMR6 2782 +#define Mips_TLBINV_MMR6 2783 +#define Mips_TLBP 2784 +#define Mips_TLBP_MM 2785 +#define Mips_TLBR 2786 +#define Mips_TLBR_MM 2787 +#define Mips_TLBWI 2788 +#define Mips_TLBWI_MM 2789 +#define Mips_TLBWR 2790 +#define Mips_TLBWR_MM 2791 +#define Mips_TLT 2792 +#define Mips_TLTI 2793 +#define Mips_TLTIU_MM 2794 +#define Mips_TLTI_MM 2795 +#define Mips_TLTU 2796 +#define Mips_TLTU_MM 2797 +#define Mips_TLT_MM 2798 +#define Mips_TNE 2799 +#define Mips_TNEI 2800 +#define Mips_TNEI_MM 2801 +#define Mips_TNE_MM 2802 +#define Mips_TRUNC_L_D64 2803 +#define Mips_TRUNC_L_D_MMR6 2804 +#define Mips_TRUNC_L_S 2805 +#define Mips_TRUNC_L_S_MMR6 2806 +#define Mips_TRUNC_W_D32 2807 +#define Mips_TRUNC_W_D64 2808 +#define Mips_TRUNC_W_D_MMR6 2809 +#define Mips_TRUNC_W_MM 2810 +#define Mips_TRUNC_W_S 2811 +#define Mips_TRUNC_W_S_MM 2812 +#define Mips_TRUNC_W_S_MMR6 2813 +#define Mips_TTLTIU 2814 +#define Mips_UDIV 2815 +#define Mips_UDIV_MM 2816 +#define Mips_V3MULU 2817 +#define Mips_VMM0 2818 +#define Mips_VMULU 2819 +#define Mips_VSHF_B 2820 +#define Mips_VSHF_D 2821 +#define Mips_VSHF_H 2822 +#define Mips_VSHF_W 2823 +#define Mips_WAIT 2824 +#define Mips_WAIT_MM 2825 +#define Mips_WAIT_MMR6 2826 +#define Mips_WRDSP 2827 +#define Mips_WRDSP_MM 2828 +#define Mips_WRPGPR_MMR6 2829 +#define Mips_WSBH 2830 +#define Mips_WSBH_MM 2831 +#define Mips_WSBH_MMR6 2832 +#define Mips_XOR 2833 +#define Mips_XOR16_MM 2834 +#define Mips_XOR16_MMR6 2835 +#define Mips_XOR64 2836 +#define Mips_XORI_B 2837 +#define Mips_XORI_MMR6 2838 +#define Mips_XOR_MM 2839 +#define Mips_XOR_MMR6 2840 +#define Mips_XOR_V 2841 +#define Mips_XORi 2842 +#define Mips_XORi64 2843 +#define Mips_XORi_MM 2844 +#define Mips_XorRxRxRy16 2845 +#define Mips_YIELD 2846 +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_REGINFO_EXTRA +#undef GET_REGINFO_EXTRA + + // Subregister indices + + enum { + NoSubRegister, + Mips_sub_32, // 1 + Mips_sub_64, // 2 + Mips_sub_dsp16_19, // 3 + Mips_sub_dsp20, // 4 + Mips_sub_dsp21, // 5 + Mips_sub_dsp22, // 6 + Mips_sub_dsp23, // 7 + Mips_sub_hi, // 8 + Mips_sub_lo, // 9 + Mips_sub_hi_then_sub_32, // 10 + Mips_sub_32_sub_hi_then_sub_32, // 11 + Mips_NUM_TARGET_SUBREGS + }; +#endif // GET_REGINFO_EXTRA + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg MipsRegDiffLists[] = { + /* 0 */ 0, 0, + /* 2 */ 4, 1, 1, 1, 1, 0, + /* 8 */ 412, 65262, 1, 1, 1, 0, + /* 14 */ 20, 1, 0, + /* 17 */ 21, 1, 0, + /* 20 */ 22, 1, 0, + /* 23 */ 23, 1, 0, + /* 26 */ 24, 1, 0, + /* 29 */ 25, 1, 0, + /* 32 */ 26, 1, 0, + /* 35 */ 27, 1, 0, + /* 38 */ 28, 1, 0, + /* 41 */ 29, 1, 0, + /* 44 */ 30, 1, 0, + /* 47 */ 31, 1, 0, + /* 50 */ 32, 1, 0, + /* 53 */ 33, 1, 0, + /* 56 */ 34, 1, 0, + /* 59 */ 35, 1, 0, + /* 62 */ 65415, 1, 0, + /* 65 */ 65513, 1, 0, + /* 68 */ 3, 0, + /* 70 */ 4, 0, + /* 72 */ 6, 0, + /* 74 */ 11, 0, + /* 76 */ 12, 0, + /* 78 */ 22, 0, + /* 80 */ 23, 0, + /* 82 */ 29, 0, + /* 84 */ 30, 0, + /* 86 */ 65284, 72, 0, + /* 89 */ 65322, 72, 0, + /* 92 */ 38, 65298, 73, 0, + /* 96 */ 95, 0, + /* 98 */ 96, 0, + /* 100 */ 130, 0, + /* 102 */ 211, 0, + /* 104 */ 243, 0, + /* 106 */ 306, 0, + /* 108 */ 314, 0, + /* 110 */ 358, 0, + /* 112 */ 64983, 0, + /* 114 */ 65060, 0, + /* 116 */ 65124, 0, + /* 118 */ 65178, 0, + /* 120 */ 65181, 0, + /* 122 */ 65222, 0, + /* 124 */ 65230, 0, + /* 126 */ 65271, 0, + /* 128 */ 65293, 0, + /* 130 */ 37, 65406, 127, 65371, 65309, 0, + /* 136 */ 65325, 0, + /* 138 */ 65371, 0, + /* 140 */ 65386, 0, + /* 142 */ 65395, 0, + /* 144 */ 65396, 0, + /* 146 */ 65397, 0, + /* 148 */ 65398, 0, + /* 150 */ 65406, 0, + /* 152 */ 65415, 0, + /* 154 */ 65440, 0, + /* 156 */ 65441, 0, + /* 158 */ 165, 65498, 0, + /* 161 */ 65516, 258, 65498, 0, + /* 165 */ 65515, 259, 65498, 0, + /* 169 */ 65514, 260, 65498, 0, + /* 173 */ 65513, 261, 65498, 0, + /* 177 */ 65512, 262, 65498, 0, + /* 181 */ 65511, 263, 65498, 0, + /* 185 */ 65510, 264, 65498, 0, + /* 189 */ 65509, 265, 65498, 0, + /* 193 */ 65508, 266, 65498, 0, + /* 197 */ 65507, 267, 65498, 0, + /* 201 */ 65506, 268, 65498, 0, + /* 205 */ 65505, 269, 65498, 0, + /* 209 */ 65504, 270, 65498, 0, + /* 213 */ 65503, 271, 65498, 0, + /* 217 */ 65502, 272, 65498, 0, + /* 221 */ 65501, 273, 65498, 0, + /* 225 */ 65500, 274, 65498, 0, + /* 229 */ 65271, 395, 65499, 0, + /* 233 */ 65309, 392, 65502, 0, + /* 237 */ 65507, 0, + /* 239 */ 65510, 0, + /* 241 */ 65511, 0, + /* 243 */ 65512, 0, + /* 245 */ 65516, 0, + /* 247 */ 65521, 0, + /* 249 */ 65522, 0, + /* 251 */ 65535, 0, +}; + +static const uint16_t MipsSubRegIdxLists[] = { + /* 0 */ 1, 0, + /* 2 */ 3, 4, 5, 6, 7, 0, + /* 8 */ 2, 9, 8, 0, + /* 12 */ 9, 1, 8, 10, 11, 0, +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char MipsRegStrings[] = { + /* 0 */ "COP00\0" + /* 6 */ "COP010\0" + /* 13 */ "COP210\0" + /* 20 */ "COP310\0" + /* 27 */ "MSA10\0" + /* 33 */ "D10\0" + /* 37 */ "F10\0" + /* 41 */ "F_HI10\0" + /* 48 */ "FCR10\0" + /* 54 */ "HWR10\0" + /* 60 */ "W10\0" + /* 64 */ "COP020\0" + /* 71 */ "COP220\0" + /* 78 */ "COP320\0" + /* 85 */ "MSA20\0" + /* 91 */ "F20\0" + /* 95 */ "F_HI20\0" + /* 102 */ "COP20\0" + /* 108 */ "FCR20\0" + /* 114 */ "HWR20\0" + /* 120 */ "W20\0" + /* 124 */ "DSPOutFlag20\0" + /* 137 */ "COP030\0" + /* 144 */ "COP230\0" + /* 151 */ "COP330\0" + /* 158 */ "MSA30\0" + /* 164 */ "F30\0" + /* 168 */ "F_HI30\0" + /* 175 */ "COP30\0" + /* 181 */ "FCR30\0" + /* 187 */ "HWR30\0" + /* 193 */ "W30\0" + /* 197 */ "A0\0" + /* 200 */ "AC0\0" + /* 204 */ "FCC0\0" + /* 209 */ "D0\0" + /* 212 */ "F0\0" + /* 215 */ "F_HI0\0" + /* 221 */ "K0\0" + /* 224 */ "MPL0\0" + /* 229 */ "LO0\0" + /* 233 */ "P0\0" + /* 236 */ "FCR0\0" + /* 241 */ "HWR0\0" + /* 246 */ "S0\0" + /* 249 */ "T0\0" + /* 252 */ "V0\0" + /* 255 */ "W0\0" + /* 258 */ "COP01\0" + /* 264 */ "COP011\0" + /* 271 */ "COP211\0" + /* 278 */ "COP311\0" + /* 285 */ "MSA11\0" + /* 291 */ "D11\0" + /* 295 */ "F11\0" + /* 299 */ "F_HI11\0" + /* 306 */ "FCR11\0" + /* 312 */ "HWR11\0" + /* 318 */ "W11\0" + /* 322 */ "COP021\0" + /* 329 */ "COP221\0" + /* 336 */ "COP321\0" + /* 343 */ "MSA21\0" + /* 349 */ "F21\0" + /* 353 */ "F_HI21\0" + /* 360 */ "COP21\0" + /* 366 */ "FCR21\0" + /* 372 */ "HWR21\0" + /* 378 */ "W21\0" + /* 382 */ "DSPOutFlag21\0" + /* 395 */ "COP031\0" + /* 402 */ "COP231\0" + /* 409 */ "COP331\0" + /* 416 */ "MSA31\0" + /* 422 */ "F31\0" + /* 426 */ "F_HI31\0" + /* 433 */ "COP31\0" + /* 439 */ "FCR31\0" + /* 445 */ "HWR31\0" + /* 451 */ "W31\0" + /* 455 */ "A1\0" + /* 458 */ "AC1\0" + /* 462 */ "FCC1\0" + /* 467 */ "D1\0" + /* 470 */ "F1\0" + /* 473 */ "F_HI1\0" + /* 479 */ "K1\0" + /* 482 */ "MPL1\0" + /* 487 */ "LO1\0" + /* 491 */ "P1\0" + /* 494 */ "FCR1\0" + /* 499 */ "HWR1\0" + /* 504 */ "S1\0" + /* 507 */ "T1\0" + /* 510 */ "V1\0" + /* 513 */ "W1\0" + /* 516 */ "COP02\0" + /* 522 */ "COP012\0" + /* 529 */ "COP212\0" + /* 536 */ "COP312\0" + /* 543 */ "MSA12\0" + /* 549 */ "D12\0" + /* 553 */ "F12\0" + /* 557 */ "F_HI12\0" + /* 564 */ "FCR12\0" + /* 570 */ "HWR12\0" + /* 576 */ "W12\0" + /* 580 */ "COP022\0" + /* 587 */ "COP222\0" + /* 594 */ "COP322\0" + /* 601 */ "MSA22\0" + /* 607 */ "F22\0" + /* 611 */ "F_HI22\0" + /* 618 */ "COP22\0" + /* 624 */ "FCR22\0" + /* 630 */ "HWR22\0" + /* 636 */ "W22\0" + /* 640 */ "DSPOutFlag22\0" + /* 653 */ "COP32\0" + /* 659 */ "A2\0" + /* 662 */ "AC2\0" + /* 666 */ "FCC2\0" + /* 671 */ "D2\0" + /* 674 */ "F2\0" + /* 677 */ "F_HI2\0" + /* 683 */ "MPL2\0" + /* 688 */ "LO2\0" + /* 692 */ "P2\0" + /* 695 */ "FCR2\0" + /* 700 */ "HWR2\0" + /* 705 */ "S2\0" + /* 708 */ "T2\0" + /* 711 */ "W2\0" + /* 714 */ "COP03\0" + /* 720 */ "COP013\0" + /* 727 */ "COP213\0" + /* 734 */ "COP313\0" + /* 741 */ "MSA13\0" + /* 747 */ "D13\0" + /* 751 */ "F13\0" + /* 755 */ "F_HI13\0" + /* 762 */ "FCR13\0" + /* 768 */ "HWR13\0" + /* 774 */ "W13\0" + /* 778 */ "COP023\0" + /* 785 */ "COP223\0" + /* 792 */ "COP323\0" + /* 799 */ "MSA23\0" + /* 805 */ "F23\0" + /* 809 */ "F_HI23\0" + /* 816 */ "COP23\0" + /* 822 */ "FCR23\0" + /* 828 */ "HWR23\0" + /* 834 */ "W23\0" + /* 838 */ "DSPOutFlag23\0" + /* 851 */ "COP33\0" + /* 857 */ "A3\0" + /* 860 */ "AC3\0" + /* 864 */ "FCC3\0" + /* 869 */ "D3\0" + /* 872 */ "F3\0" + /* 875 */ "F_HI3\0" + /* 881 */ "LO3\0" + /* 885 */ "FCR3\0" + /* 890 */ "HWR3\0" + /* 895 */ "S3\0" + /* 898 */ "T3\0" + /* 901 */ "W3\0" + /* 904 */ "COP04\0" + /* 910 */ "COP014\0" + /* 917 */ "COP214\0" + /* 924 */ "COP314\0" + /* 931 */ "MSA14\0" + /* 937 */ "D14\0" + /* 941 */ "F14\0" + /* 945 */ "F_HI14\0" + /* 952 */ "FCR14\0" + /* 958 */ "HWR14\0" + /* 964 */ "W14\0" + /* 968 */ "COP024\0" + /* 975 */ "COP224\0" + /* 982 */ "COP324\0" + /* 989 */ "MSA24\0" + /* 995 */ "F24\0" + /* 999 */ "F_HI24\0" + /* 1006 */ "COP24\0" + /* 1012 */ "FCR24\0" + /* 1018 */ "HWR24\0" + /* 1024 */ "W24\0" + /* 1028 */ "COP34\0" + /* 1034 */ "D10_64\0" + /* 1041 */ "D20_64\0" + /* 1048 */ "D30_64\0" + /* 1055 */ "A0_64\0" + /* 1061 */ "AC0_64\0" + /* 1068 */ "D0_64\0" + /* 1074 */ "HI0_64\0" + /* 1081 */ "K0_64\0" + /* 1087 */ "LO0_64\0" + /* 1094 */ "S0_64\0" + /* 1100 */ "T0_64\0" + /* 1106 */ "V0_64\0" + /* 1112 */ "D11_64\0" + /* 1119 */ "D21_64\0" + /* 1126 */ "D31_64\0" + /* 1133 */ "A1_64\0" + /* 1139 */ "D1_64\0" + /* 1145 */ "K1_64\0" + /* 1151 */ "S1_64\0" + /* 1157 */ "T1_64\0" + /* 1163 */ "V1_64\0" + /* 1169 */ "D12_64\0" + /* 1176 */ "D22_64\0" + /* 1183 */ "A2_64\0" + /* 1189 */ "D2_64\0" + /* 1195 */ "S2_64\0" + /* 1201 */ "T2_64\0" + /* 1207 */ "D13_64\0" + /* 1214 */ "D23_64\0" + /* 1221 */ "A3_64\0" + /* 1227 */ "D3_64\0" + /* 1233 */ "S3_64\0" + /* 1239 */ "T3_64\0" + /* 1245 */ "D14_64\0" + /* 1252 */ "D24_64\0" + /* 1259 */ "D4_64\0" + /* 1265 */ "S4_64\0" + /* 1271 */ "T4_64\0" + /* 1277 */ "D15_64\0" + /* 1284 */ "D25_64\0" + /* 1291 */ "D5_64\0" + /* 1297 */ "S5_64\0" + /* 1303 */ "T5_64\0" + /* 1309 */ "D16_64\0" + /* 1316 */ "D26_64\0" + /* 1323 */ "D6_64\0" + /* 1329 */ "S6_64\0" + /* 1335 */ "T6_64\0" + /* 1341 */ "D17_64\0" + /* 1348 */ "D27_64\0" + /* 1355 */ "D7_64\0" + /* 1361 */ "S7_64\0" + /* 1367 */ "T7_64\0" + /* 1373 */ "D18_64\0" + /* 1380 */ "D28_64\0" + /* 1387 */ "D8_64\0" + /* 1393 */ "T8_64\0" + /* 1399 */ "D19_64\0" + /* 1406 */ "D29_64\0" + /* 1413 */ "D9_64\0" + /* 1419 */ "T9_64\0" + /* 1425 */ "RA_64\0" + /* 1431 */ "ZERO_64\0" + /* 1439 */ "FP_64\0" + /* 1445 */ "GP_64\0" + /* 1451 */ "SP_64\0" + /* 1457 */ "AT_64\0" + /* 1463 */ "FCC4\0" + /* 1468 */ "D4\0" + /* 1471 */ "F4\0" + /* 1474 */ "F_HI4\0" + /* 1480 */ "FCR4\0" + /* 1485 */ "HWR4\0" + /* 1490 */ "S4\0" + /* 1493 */ "T4\0" + /* 1496 */ "W4\0" + /* 1499 */ "COP05\0" + /* 1505 */ "COP015\0" + /* 1512 */ "COP215\0" + /* 1519 */ "COP315\0" + /* 1526 */ "MSA15\0" + /* 1532 */ "D15\0" + /* 1536 */ "F15\0" + /* 1540 */ "F_HI15\0" + /* 1547 */ "FCR15\0" + /* 1553 */ "HWR15\0" + /* 1559 */ "W15\0" + /* 1563 */ "COP025\0" + /* 1570 */ "COP225\0" + /* 1577 */ "COP325\0" + /* 1584 */ "MSA25\0" + /* 1590 */ "F25\0" + /* 1594 */ "F_HI25\0" + /* 1601 */ "COP25\0" + /* 1607 */ "FCR25\0" + /* 1613 */ "HWR25\0" + /* 1619 */ "W25\0" + /* 1623 */ "COP35\0" + /* 1629 */ "FCC5\0" + /* 1634 */ "D5\0" + /* 1637 */ "F5\0" + /* 1640 */ "F_HI5\0" + /* 1646 */ "FCR5\0" + /* 1651 */ "HWR5\0" + /* 1656 */ "S5\0" + /* 1659 */ "T5\0" + /* 1662 */ "W5\0" + /* 1665 */ "COP06\0" + /* 1671 */ "COP016\0" + /* 1678 */ "COP216\0" + /* 1685 */ "COP316\0" + /* 1692 */ "MSA16\0" + /* 1698 */ "F16\0" + /* 1702 */ "F_HI16\0" + /* 1709 */ "FCR16\0" + /* 1715 */ "HWR16\0" + /* 1721 */ "W16\0" + /* 1725 */ "COP026\0" + /* 1732 */ "COP226\0" + /* 1739 */ "COP326\0" + /* 1746 */ "MSA26\0" + /* 1752 */ "F26\0" + /* 1756 */ "F_HI26\0" + /* 1763 */ "COP26\0" + /* 1769 */ "FCR26\0" + /* 1775 */ "HWR26\0" + /* 1781 */ "W26\0" + /* 1785 */ "COP36\0" + /* 1791 */ "FCC6\0" + /* 1796 */ "D6\0" + /* 1799 */ "F6\0" + /* 1802 */ "F_HI6\0" + /* 1808 */ "FCR6\0" + /* 1813 */ "HWR6\0" + /* 1818 */ "S6\0" + /* 1821 */ "T6\0" + /* 1824 */ "W6\0" + /* 1827 */ "COP07\0" + /* 1833 */ "COP017\0" + /* 1840 */ "COP217\0" + /* 1847 */ "COP317\0" + /* 1854 */ "MSA17\0" + /* 1860 */ "F17\0" + /* 1864 */ "F_HI17\0" + /* 1871 */ "FCR17\0" + /* 1877 */ "HWR17\0" + /* 1883 */ "W17\0" + /* 1887 */ "COP027\0" + /* 1894 */ "COP227\0" + /* 1901 */ "COP327\0" + /* 1908 */ "MSA27\0" + /* 1914 */ "F27\0" + /* 1918 */ "F_HI27\0" + /* 1925 */ "COP27\0" + /* 1931 */ "FCR27\0" + /* 1937 */ "HWR27\0" + /* 1943 */ "W27\0" + /* 1947 */ "COP37\0" + /* 1953 */ "FCC7\0" + /* 1958 */ "D7\0" + /* 1961 */ "F7\0" + /* 1964 */ "F_HI7\0" + /* 1970 */ "FCR7\0" + /* 1975 */ "HWR7\0" + /* 1980 */ "S7\0" + /* 1983 */ "T7\0" + /* 1986 */ "W7\0" + /* 1989 */ "COP08\0" + /* 1995 */ "COP018\0" + /* 2002 */ "COP218\0" + /* 2009 */ "COP318\0" + /* 2016 */ "MSA18\0" + /* 2022 */ "F18\0" + /* 2026 */ "F_HI18\0" + /* 2033 */ "FCR18\0" + /* 2039 */ "HWR18\0" + /* 2045 */ "W18\0" + /* 2049 */ "COP028\0" + /* 2056 */ "COP228\0" + /* 2063 */ "COP328\0" + /* 2070 */ "MSA28\0" + /* 2076 */ "F28\0" + /* 2080 */ "F_HI28\0" + /* 2087 */ "COP28\0" + /* 2093 */ "FCR28\0" + /* 2099 */ "HWR28\0" + /* 2105 */ "W28\0" + /* 2109 */ "COP38\0" + /* 2115 */ "MSA8\0" + /* 2120 */ "D8\0" + /* 2123 */ "F8\0" + /* 2126 */ "F_HI8\0" + /* 2132 */ "FCR8\0" + /* 2137 */ "HWR8\0" + /* 2142 */ "T8\0" + /* 2145 */ "W8\0" + /* 2148 */ "COP09\0" + /* 2154 */ "COP019\0" + /* 2161 */ "COP219\0" + /* 2168 */ "COP319\0" + /* 2175 */ "MSA19\0" + /* 2181 */ "F19\0" + /* 2185 */ "F_HI19\0" + /* 2192 */ "FCR19\0" + /* 2198 */ "HWR19\0" + /* 2204 */ "W19\0" + /* 2208 */ "DSPOutFlag16_19\0" + /* 2224 */ "COP029\0" + /* 2231 */ "COP229\0" + /* 2238 */ "COP329\0" + /* 2245 */ "MSA29\0" + /* 2251 */ "F29\0" + /* 2255 */ "F_HI29\0" + /* 2262 */ "COP29\0" + /* 2268 */ "FCR29\0" + /* 2274 */ "HWR29\0" + /* 2280 */ "W29\0" + /* 2284 */ "COP39\0" + /* 2290 */ "MSA9\0" + /* 2295 */ "D9\0" + /* 2298 */ "F9\0" + /* 2301 */ "F_HI9\0" + /* 2307 */ "FCR9\0" + /* 2312 */ "HWR9\0" + /* 2317 */ "T9\0" + /* 2320 */ "W9\0" + /* 2323 */ "RA\0" + /* 2326 */ "PC\0" + /* 2329 */ "DSPEFI\0" + /* 2336 */ "ZERO\0" + /* 2341 */ "FP\0" + /* 2344 */ "GP\0" + /* 2347 */ "SP\0" + /* 2350 */ "MSAIR\0" + /* 2356 */ "MSACSR\0" + /* 2363 */ "AT\0" + /* 2366 */ "DSPCCond\0" + /* 2375 */ "MSASave\0" + /* 2383 */ "DSPOutFlag\0" + /* 2394 */ "MSAMap\0" + /* 2401 */ "MSAUnmap\0" + /* 2410 */ "DSPPos\0" + /* 2417 */ "MSAAccess\0" + /* 2427 */ "DSPSCount\0" + /* 2437 */ "MSARequest\0" + /* 2448 */ "MSAModify\0" + /* 2458 */ "DSPCarry\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterDesc MipsRegDesc[] = { + // Descriptors + {5, 0, 0, 0, 0, 0}, + {2363, 1, 82, 1, 4017, 451}, + {2366, 1, 1, 1, 4017, 434}, + {2458, 1, 1, 1, 4017, 541}, + {2329, 1, 1, 1, 4017, 117}, + {2383, 8, 1, 2, 32, 204}, + {2410, 1, 1, 1, 1089, 54}, + {2427, 1, 1, 1, 1089, 108}, + {2341, 1, 102, 1, 1089, 442}, + {2344, 1, 104, 1, 1089, 440}, + {2417, 1, 1, 1, 1089, 117}, + {2356, 1, 1, 1, 1089, 436}, + {2350, 1, 1, 1, 1089, 117}, + {2394, 1, 1, 1, 1089, 157}, + {2448, 1, 1, 1, 1089, 555}, + {2437, 1, 1, 1, 1089, 139}, + {2375, 1, 1, 1, 1089, 99}, + {2401, 1, 1, 1, 1089, 108}, + {2326, 1, 1, 1, 1089, 449}, + {2323, 1, 106, 1, 1089, 541}, + {2347, 1, 108, 1, 1089, 444}, + {2336, 1, 110, 1, 1089, 438}, + {197, 1, 110, 1, 1089, 117}, + {455, 1, 110, 1, 1089, 139}, + {659, 1, 110, 1, 1089, 1}, + {857, 1, 110, 1, 1089, 36}, + {200, 190, 110, 9, 1042, 119}, + {458, 190, 1, 9, 1042, 119}, + {662, 190, 1, 9, 1042, 104}, + {860, 190, 1, 9, 1042, 42}, + {1457, 237, 1, 0, 0, 498}, + {0, 1, 1, 1, 1153, 56}, + {258, 1, 1, 1, 1153, 1}, + {516, 1, 1, 1, 1153, 117}, + {714, 1, 1, 1, 1153, 117}, + {904, 1, 1, 1, 1153, 1}, + {1499, 1, 1, 1, 1153, 494}, + {1665, 1, 1, 1, 1153, 30}, + {1827, 1, 1, 1, 1153, 110}, + {1989, 1, 1, 1, 1153, 231}, + {2148, 1, 1, 1, 1153, 68}, + {102, 1, 1, 1, 1153, 225}, + {360, 1, 1, 1, 1153, 32}, + {618, 1, 1, 1, 1153, 1}, + {816, 1, 1, 1, 1153, 135}, + {1006, 1, 1, 1, 1153, 1}, + {1601, 1, 1, 1, 1153, 159}, + {1763, 1, 1, 1, 1153, 518}, + {1925, 1, 1, 1, 1153, 1}, + {2087, 1, 1, 1, 1153, 117}, + {2262, 1, 1, 1, 1153, 54}, + {175, 1, 1, 1, 1153, 1}, + {433, 1, 1, 1, 1153, 43}, + {653, 1, 1, 1, 1153, 513}, + {851, 1, 1, 1, 1153, 229}, + {1028, 1, 1, 1, 1153, 496}, + {1623, 1, 1, 1, 1153, 1}, + {1785, 1, 1, 1, 1153, 1}, + {1947, 1, 1, 1, 1153, 1}, + {2109, 1, 1, 1, 1153, 108}, + {2284, 1, 1, 1, 1153, 117}, + {6, 1, 1, 1, 1153, 117}, + {264, 1, 1, 1, 1153, 117}, + {522, 1, 1, 1, 1153, 137}, + {720, 1, 1, 1, 1153, 163}, + {910, 1, 1, 1, 1153, 167}, + {1505, 1, 1, 1, 1153, 171}, + {1671, 1, 1, 1, 1153, 175}, + {1833, 1, 1, 1, 1153, 179}, + {1995, 1, 1, 1, 1153, 183}, + {2154, 1, 1, 1, 1153, 187}, + {64, 1, 1, 1, 1153, 1}, + {322, 1, 1, 1, 1153, 1}, + {580, 1, 1, 1, 1153, 1}, + {778, 1, 1, 1, 1153, 1}, + {968, 1, 1, 1, 1153, 566}, + {1563, 1, 1, 1, 1153, 566}, + {1725, 1, 1, 1, 1153, 566}, + {1887, 1, 1, 1, 1153, 566}, + {2049, 1, 1, 1, 1153, 566}, + {2224, 1, 1, 1, 1153, 566}, + {137, 1, 1, 1, 1153, 566}, + {395, 1, 1, 1, 1153, 566}, + {13, 1, 1, 1, 1153, 566}, + {271, 1, 1, 1, 1153, 566}, + {529, 1, 1, 1, 1153, 566}, + {727, 1, 1, 1, 1153, 566}, + {917, 1, 1, 1, 1153, 145}, + {1512, 1, 1, 1, 1153, 165}, + {1678, 1, 1, 1, 1153, 169}, + {1840, 1, 1, 1, 1153, 173}, + {2002, 1, 1, 1, 1153, 177}, + {2161, 1, 1, 1, 1153, 181}, + {71, 1, 1, 1, 1153, 185}, + {329, 1, 1, 1, 1153, 189}, + {587, 1, 1, 1, 1153, 543}, + {785, 1, 1, 1, 1153, 562}, + {975, 1, 1, 1, 1153, 545}, + {1570, 1, 1, 1, 1153, 564}, + {1732, 1, 1, 1, 1153, 566}, + {1894, 1, 1, 1, 1153, 197}, + {2056, 1, 1, 1, 1153, 191}, + {2231, 1, 1, 1, 1153, 1}, + {144, 1, 1, 1, 1153, 509}, + {402, 1, 1, 1, 1153, 1}, + {20, 1, 1, 1, 1153, 117}, + {278, 1, 1, 1, 1153, 492}, + {536, 1, 1, 1, 1153, 202}, + {734, 1, 1, 1, 1153, 1}, + {924, 1, 1, 1, 1153, 117}, + {1519, 1, 1, 1, 1153, 502}, + {1685, 1, 1, 1, 1153, 56}, + {1847, 1, 1, 1, 1153, 108}, + {2009, 1, 1, 1, 1153, 117}, + {2168, 1, 1, 1, 1153, 24}, + {78, 1, 1, 1, 1153, 108}, + {336, 1, 1, 1, 1153, 500}, + {594, 1, 1, 1, 1153, 34}, + {792, 1, 1, 1, 1153, 504}, + {982, 1, 1, 1, 1153, 1}, + {1577, 1, 1, 1, 1153, 117}, + {1739, 1, 1, 1, 1153, 131}, + {1901, 1, 1, 1, 1153, 133}, + {2063, 1, 1, 1, 1153, 143}, + {2238, 1, 1, 1, 1153, 149}, + {151, 1, 1, 1, 1153, 155}, + {409, 1, 1, 1, 1153, 161}, + {209, 14, 1, 9, 994, 42}, + {467, 17, 1, 9, 994, 0}, + {671, 20, 1, 9, 994, 104}, + {869, 23, 1, 9, 994, 42}, + {1468, 26, 1, 9, 994, 65}, + {1634, 29, 1, 9, 994, 431}, + {1796, 32, 1, 9, 994, 0}, + {1958, 35, 1, 9, 994, 446}, + {2120, 38, 1, 9, 994, 119}, + {2295, 41, 1, 9, 994, 107}, + {33, 44, 1, 9, 994, 523}, + {291, 47, 1, 9, 994, 520}, + {549, 50, 1, 9, 994, 79}, + {747, 53, 1, 9, 994, 0}, + {937, 56, 1, 9, 994, 526}, + {1532, 59, 1, 9, 994, 53}, + {124, 1, 148, 1, 2369, 147}, + {382, 1, 146, 1, 2369, 38}, + {640, 1, 144, 1, 2369, 529}, + {838, 1, 142, 1, 2369, 1}, + {212, 1, 161, 1, 3985, 531}, + {470, 1, 165, 1, 3985, 56}, + {674, 1, 165, 1, 3985, 108}, + {872, 1, 169, 1, 3985, 117}, + {1471, 1, 169, 1, 3985, 117}, + {1637, 1, 173, 1, 3985, 108}, + {1799, 1, 173, 1, 3985, 425}, + {1961, 1, 177, 1, 3985, 421}, + {2123, 1, 177, 1, 3985, 213}, + {2298, 1, 181, 1, 3985, 215}, + {37, 1, 181, 1, 3985, 541}, + {295, 1, 185, 1, 3985, 114}, + {553, 1, 185, 1, 3985, 108}, + {751, 1, 189, 1, 3985, 217}, + {941, 1, 189, 1, 3985, 40}, + {1536, 1, 193, 1, 3985, 219}, + {1698, 1, 193, 1, 3985, 1}, + {1860, 1, 197, 1, 3985, 117}, + {2022, 1, 197, 1, 3985, 453}, + {2181, 1, 201, 1, 3985, 117}, + {91, 1, 201, 1, 3985, 1}, + {349, 1, 205, 1, 3985, 221}, + {607, 1, 205, 1, 3985, 99}, + {805, 1, 209, 1, 3985, 541}, + {995, 1, 209, 1, 3985, 1}, + {1590, 1, 213, 1, 3985, 112}, + {1752, 1, 213, 1, 3985, 1}, + {1914, 1, 217, 1, 3985, 117}, + {2076, 1, 217, 1, 3985, 227}, + {2251, 1, 221, 1, 3985, 223}, + {164, 1, 221, 1, 3985, 88}, + {422, 1, 225, 1, 3985, 474}, + {204, 1, 1, 1, 3985, 117}, + {462, 1, 1, 1, 3985, 24}, + {666, 1, 1, 1, 3985, 1}, + {864, 1, 1, 1, 3985, 476}, + {1463, 1, 1, 1, 3985, 1}, + {1629, 1, 1, 1, 3985, 1}, + {1791, 1, 1, 1, 3985, 1}, + {1953, 1, 1, 1, 3985, 423}, + {236, 1, 1, 1, 3985, 117}, + {494, 1, 1, 1, 3985, 99}, + {695, 1, 1, 1, 3985, 1}, + {885, 1, 1, 1, 3985, 54}, + {1480, 1, 1, 1, 3985, 480}, + {1646, 1, 1, 1, 3985, 84}, + {1808, 1, 1, 1, 3985, 566}, + {1970, 1, 1, 1, 3985, 197}, + {2132, 1, 1, 1, 3985, 195}, + {2307, 1, 1, 1, 3985, 193}, + {48, 1, 1, 1, 3985, 566}, + {306, 1, 1, 1, 3985, 566}, + {564, 1, 1, 1, 3985, 90}, + {762, 1, 1, 1, 3985, 487}, + {952, 1, 1, 1, 3985, 1}, + {1547, 1, 1, 1, 3985, 485}, + {1709, 1, 1, 1, 3985, 423}, + {1871, 1, 1, 1, 3985, 117}, + {2033, 1, 1, 1, 3985, 99}, + {2192, 1, 1, 1, 3985, 1}, + {108, 1, 1, 1, 3985, 54}, + {366, 1, 1, 1, 3985, 1}, + {624, 1, 1, 1, 3985, 38}, + {822, 1, 1, 1, 3985, 117}, + {1012, 1, 1, 1, 3985, 117}, + {1607, 1, 1, 1, 3985, 1}, + {1769, 1, 1, 1, 3985, 141}, + {1931, 1, 1, 1, 3985, 1}, + {2093, 1, 1, 1, 3985, 233}, + {2268, 1, 1, 1, 3985, 429}, + {181, 1, 1, 1, 3985, 117}, + {439, 1, 1, 1, 3985, 110}, + {1439, 136, 1, 0, 1184, 108}, + {215, 1, 158, 1, 3953, 394}, + {473, 1, 158, 1, 3953, 82}, + {677, 1, 158, 1, 3953, 1}, + {875, 1, 158, 1, 3953, 377}, + {1474, 1, 158, 1, 3953, 86}, + {1640, 1, 158, 1, 3953, 375}, + {1802, 1, 158, 1, 3953, 1}, + {1964, 1, 158, 1, 3953, 427}, + {2126, 1, 158, 1, 3953, 453}, + {2301, 1, 158, 1, 3953, 117}, + {41, 1, 158, 1, 3953, 117}, + {299, 1, 158, 1, 3953, 16}, + {557, 1, 158, 1, 3953, 54}, + {755, 1, 158, 1, 3953, 1}, + {945, 1, 158, 1, 3953, 392}, + {1540, 1, 158, 1, 3953, 388}, + {1702, 1, 158, 1, 3953, 390}, + {1864, 1, 158, 1, 3953, 400}, + {2026, 1, 158, 1, 3953, 379}, + {2185, 1, 158, 1, 3953, 398}, + {95, 1, 158, 1, 3953, 108}, + {353, 1, 158, 1, 3953, 117}, + {611, 1, 158, 1, 3953, 24}, + {809, 1, 158, 1, 3953, 108}, + {999, 1, 158, 1, 3953, 402}, + {1594, 1, 158, 1, 3953, 30}, + {1756, 1, 158, 1, 3953, 63}, + {1918, 1, 158, 1, 3953, 1}, + {2080, 1, 158, 1, 3953, 96}, + {2255, 1, 158, 1, 3953, 383}, + {168, 1, 158, 1, 3953, 1}, + {426, 1, 158, 1, 3953, 381}, + {1445, 128, 1, 0, 1216, 453}, + {217, 1, 233, 1, 1826, 117}, + {475, 1, 134, 1, 1826, 117}, + {679, 1, 134, 1, 1826, 16}, + {877, 1, 134, 1, 1826, 54}, + {241, 1, 1, 1, 3921, 404}, + {499, 1, 1, 1, 3921, 396}, + {700, 1, 1, 1, 3921, 1}, + {890, 1, 1, 1, 3921, 411}, + {1485, 1, 1, 1, 3921, 413}, + {1651, 1, 1, 1, 3921, 1}, + {1813, 1, 1, 1, 3921, 415}, + {1975, 1, 1, 1, 3921, 406}, + {2137, 1, 1, 1, 3921, 417}, + {2312, 1, 1, 1, 3921, 419}, + {54, 1, 1, 1, 3921, 36}, + {312, 1, 1, 1, 3921, 117}, + {570, 1, 1, 1, 3921, 1}, + {768, 1, 1, 1, 3921, 117}, + {958, 1, 1, 1, 3921, 153}, + {1553, 1, 1, 1, 3921, 151}, + {1715, 1, 1, 1, 3921, 61}, + {1877, 1, 1, 1, 3921, 241}, + {2039, 1, 1, 1, 3921, 243}, + {2198, 1, 1, 1, 3921, 117}, + {114, 1, 1, 1, 3921, 550}, + {372, 1, 1, 1, 3921, 1}, + {630, 1, 1, 1, 3921, 239}, + {828, 1, 1, 1, 3921, 247}, + {1018, 1, 1, 1, 3921, 245}, + {1613, 1, 1, 1, 3921, 108}, + {1775, 1, 1, 1, 3921, 249}, + {1937, 1, 1, 1, 3921, 251}, + {2099, 1, 1, 1, 3921, 253}, + {2274, 1, 1, 1, 3921, 255}, + {187, 1, 1, 1, 3921, 117}, + {445, 1, 1, 1, 3921, 24}, + {221, 1, 100, 1, 3921, 1}, + {479, 1, 100, 1, 3921, 257}, + {229, 1, 229, 1, 1794, 26}, + {487, 1, 126, 1, 1794, 259}, + {688, 1, 126, 1, 1794, 1}, + {881, 1, 126, 1, 1794, 261}, + {224, 1, 1, 1, 3889, 541}, + {482, 1, 1, 1, 3889, 108}, + {683, 1, 1, 1, 3889, 117}, + {2115, 1, 1, 1, 3889, 1}, + {2290, 1, 1, 1, 3889, 265}, + {27, 1, 1, 1, 3889, 269}, + {285, 1, 1, 1, 3889, 267}, + {543, 1, 1, 1, 3889, 277}, + {741, 1, 1, 1, 3889, 1}, + {931, 1, 1, 1, 3889, 263}, + {1526, 1, 1, 1, 3889, 423}, + {1692, 1, 1, 1, 3889, 117}, + {1854, 1, 1, 1, 3889, 117}, + {2016, 1, 1, 1, 3889, 99}, + {2175, 1, 1, 1, 3889, 54}, + {85, 1, 1, 1, 3889, 273}, + {343, 1, 1, 1, 3889, 94}, + {601, 1, 1, 1, 3889, 271}, + {799, 1, 1, 1, 3889, 1}, + {989, 1, 1, 1, 3889, 235}, + {1584, 1, 1, 1, 3889, 275}, + {1746, 1, 1, 1, 3889, 1}, + {1908, 1, 1, 1, 3889, 279}, + {2070, 1, 1, 1, 3889, 108}, + {2245, 1, 1, 1, 3889, 117}, + {158, 1, 1, 1, 3889, 560}, + {416, 1, 1, 1, 3889, 1}, + {233, 1, 1, 1, 3889, 1}, + {491, 1, 1, 1, 3889, 423}, + {692, 1, 1, 1, 3889, 99}, + {1425, 124, 1, 0, 1248, 16}, + {246, 1, 98, 1, 3857, 541}, + {504, 1, 98, 1, 3857, 283}, + {705, 1, 98, 1, 3857, 117}, + {895, 1, 98, 1, 3857, 117}, + {1490, 1, 98, 1, 3857, 281}, + {1656, 1, 98, 1, 3857, 1}, + {1818, 1, 98, 1, 3857, 117}, + {1980, 1, 98, 1, 3857, 108}, + {1451, 122, 1, 0, 1280, 1}, + {249, 1, 96, 1, 3825, 293}, + {507, 1, 96, 1, 3825, 291}, + {708, 1, 96, 1, 3825, 541}, + {898, 1, 96, 1, 3825, 295}, + {1493, 1, 96, 1, 3825, 48}, + {1659, 1, 96, 1, 3825, 297}, + {1821, 1, 96, 1, 3825, 299}, + {1983, 1, 96, 1, 3825, 28}, + {2142, 1, 96, 1, 3825, 1}, + {2317, 1, 96, 1, 3825, 306}, + {252, 1, 96, 1, 3825, 1}, + {510, 1, 96, 1, 3825, 301}, + {255, 92, 1, 8, 1425, 311}, + {513, 92, 1, 8, 1425, 45}, + {711, 92, 1, 8, 1425, 70}, + {901, 92, 1, 8, 1425, 314}, + {1496, 92, 1, 8, 1425, 317}, + {1662, 92, 1, 8, 1425, 9}, + {1824, 92, 1, 8, 1425, 21}, + {1986, 92, 1, 8, 1425, 98}, + {2145, 92, 1, 8, 1425, 320}, + {2320, 92, 1, 8, 1425, 50}, + {60, 92, 1, 8, 1425, 18}, + {318, 92, 1, 8, 1425, 3}, + {576, 92, 1, 8, 1425, 325}, + {774, 92, 1, 8, 1425, 0}, + {964, 92, 1, 8, 1425, 547}, + {1559, 92, 1, 8, 1425, 119}, + {1721, 92, 1, 8, 1425, 12}, + {1883, 92, 1, 8, 1425, 42}, + {2045, 92, 1, 8, 1425, 6}, + {2204, 92, 1, 8, 1425, 116}, + {120, 92, 1, 8, 1425, 552}, + {378, 92, 1, 8, 1425, 15}, + {636, 92, 1, 8, 1425, 557}, + {834, 92, 1, 8, 1425, 331}, + {1024, 92, 1, 8, 1425, 334}, + {1619, 92, 1, 8, 1425, 337}, + {1781, 92, 1, 8, 1425, 340}, + {1943, 92, 1, 8, 1425, 343}, + {2105, 92, 1, 8, 1425, 73}, + {2280, 92, 1, 8, 1425, 0}, + {193, 92, 1, 8, 1425, 349}, + {451, 92, 1, 8, 1425, 58}, + {1431, 118, 1, 0, 1921, 108}, + {1055, 118, 1, 0, 1921, 117}, + {1133, 118, 1, 0, 1921, 24}, + {1183, 118, 1, 0, 1921, 1}, + {1221, 118, 1, 0, 1921, 352}, + {1061, 130, 1, 12, 656, 354}, + {1068, 93, 159, 9, 1377, 285}, + {1139, 93, 159, 9, 1377, 199}, + {1189, 93, 159, 9, 1377, 408}, + {1227, 93, 159, 9, 1377, 288}, + {1259, 93, 159, 9, 1377, 489}, + {1291, 93, 159, 9, 1377, 385}, + {1323, 93, 159, 9, 1377, 515}, + {1355, 93, 159, 9, 1377, 328}, + {1387, 93, 159, 9, 1377, 308}, + {1413, 93, 159, 9, 1377, 210}, + {1034, 93, 159, 9, 1377, 346}, + {1112, 93, 159, 9, 1377, 482}, + {1169, 93, 159, 9, 1377, 76}, + {1207, 93, 159, 9, 1377, 0}, + {1245, 93, 159, 9, 1377, 357}, + {1277, 93, 159, 9, 1377, 58}, + {1309, 93, 159, 9, 1377, 303}, + {1341, 93, 159, 9, 1377, 360}, + {1373, 93, 159, 9, 1377, 363}, + {1399, 93, 159, 9, 1377, 366}, + {1041, 93, 159, 9, 1377, 369}, + {1119, 93, 159, 9, 1377, 372}, + {1176, 93, 159, 9, 1377, 122}, + {1214, 93, 159, 9, 1377, 455}, + {1252, 93, 159, 9, 1377, 538}, + {1284, 93, 159, 9, 1377, 506}, + {1316, 93, 159, 9, 1377, 128}, + {1348, 93, 159, 9, 1377, 535}, + {1380, 93, 159, 9, 1377, 119}, + {1406, 93, 159, 9, 1377, 125}, + {1048, 93, 159, 9, 1377, 101}, + {1126, 93, 159, 9, 1377, 98}, + {2208, 1, 116, 1, 1120, 466}, + {1074, 138, 235, 0, 1344, 458}, + {1081, 150, 1, 0, 2241, 460}, + {1145, 150, 1, 0, 2241, 460}, + {1087, 150, 231, 0, 1312, 462}, + {1094, 154, 1, 0, 2433, 462}, + {1151, 154, 1, 0, 2433, 468}, + {1195, 154, 1, 0, 2433, 54}, + {1233, 154, 1, 0, 2433, 464}, + {1265, 154, 1, 0, 2433, 92}, + {1297, 154, 1, 0, 2433, 117}, + {1329, 154, 1, 0, 2433, 1}, + {1361, 154, 1, 0, 2433, 533}, + {1100, 156, 1, 0, 2433, 511}, + {1157, 156, 1, 0, 2433, 478}, + {1201, 156, 1, 0, 2433, 237}, + {1239, 156, 1, 0, 2433, 323}, + {1271, 156, 1, 0, 2433, 16}, + {1303, 156, 1, 0, 2433, 470}, + {1335, 156, 1, 0, 2433, 541}, + {1367, 156, 1, 0, 2433, 99}, + {1393, 156, 1, 0, 2433, 117}, + {1419, 156, 1, 0, 2433, 110}, + {1106, 156, 1, 0, 2433, 1}, + {1163, 156, 1, 0, 2433, 472}, +}; + +// MSA128F16 Register Class... +static const MCPhysReg MSA128F16[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, + Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, + Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, + Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, + Mips_W28, Mips_W29, Mips_W30, Mips_W31, +}; + +// MSA128F16 Bit set. +static const uint8_t MSA128F16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// CCR Register Class... +static const MCPhysReg CCR[] = { + Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, + Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, + Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, + Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, + Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, + Mips_FCR30, Mips_FCR31, +}; + +// CCR Bit set. +static const uint8_t CCRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// COP0 Register Class... +static const MCPhysReg COP0[] = { + Mips_COP00, Mips_COP01, Mips_COP02, Mips_COP03, Mips_COP04, + Mips_COP05, Mips_COP06, Mips_COP07, Mips_COP08, Mips_COP09, + Mips_COP010, Mips_COP011, Mips_COP012, Mips_COP013, Mips_COP014, + Mips_COP015, Mips_COP016, Mips_COP017, Mips_COP018, Mips_COP019, + Mips_COP020, Mips_COP021, Mips_COP022, Mips_COP023, Mips_COP024, + Mips_COP025, Mips_COP026, Mips_COP027, Mips_COP028, Mips_COP029, + Mips_COP030, Mips_COP031, +}; + +// COP0 Bit set. +static const uint8_t COP0Bits[] = { + 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07, +}; + +// COP2 Register Class... +static const MCPhysReg COP2[] = { + Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, + Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, + Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, + Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, + Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, + Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, + Mips_COP230, Mips_COP231, +}; + +// COP2 Bit set. +static const uint8_t COP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, + 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, +}; + +// COP3 Register Class... +static const MCPhysReg COP3[] = { + Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, + Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, + Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, + Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, + Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, + Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, + Mips_COP330, Mips_COP331, +}; + +// COP3 Bit set. +static const uint8_t COP3Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, +}; + +// DSPR Register Class... +static const MCPhysReg DSPR[] = { + Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, + Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, + Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, +}; + +// DSPR Bit set. +static const uint8_t DSPRBits[] = { + 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, +}; + +// FGR32 Register Class... +static const MCPhysReg FGR32[] = { + Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, + Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, + Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, + Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, + Mips_F28, Mips_F29, Mips_F30, Mips_F31, +}; + +// FGR32 Bit set. +static const uint8_t FGR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// FGRCC Register Class... +static const MCPhysReg FGRCC[] = { + Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, + Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, + Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, + Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, + Mips_F28, Mips_F29, Mips_F30, Mips_F31, +}; + +// FGRCC Bit set. +static const uint8_t FGRCCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// GPR32 Register Class... +static const MCPhysReg GPR32[] = { + Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, + Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, + Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, +}; + +// GPR32 Bit set. +static const uint8_t GPR32Bits[] = { + 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, +}; + +// HWRegs Register Class... +static const MCPhysReg HWRegs[] = { + Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, + Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, + Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, + Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, + Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, + Mips_HWR30, Mips_HWR31, +}; + +// HWRegs Bit set. +static const uint8_t HWRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, +}; + +// MSACtrl Register Class... +static const MCPhysReg MSACtrl[] = { + Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, + Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, Mips_MSA8, Mips_MSA9, + Mips_MSA10, Mips_MSA11, Mips_MSA12, Mips_MSA13, Mips_MSA14, + Mips_MSA15, Mips_MSA16, Mips_MSA17, Mips_MSA18, Mips_MSA19, + Mips_MSA20, Mips_MSA21, Mips_MSA22, Mips_MSA23, Mips_MSA24, + Mips_MSA25, Mips_MSA26, Mips_MSA27, Mips_MSA28, Mips_MSA29, + Mips_MSA30, Mips_MSA31, +}; + +// MSACtrl Bit set. +static const uint8_t MSACtrlBits[] = { + 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03, +}; + +// GPR32NONZERO Register Class... +static const MCPhysReg GPR32NONZERO[] = { + Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, + Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, + Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, + Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, +}; + +// GPR32NONZERO Bit set. +static const uint8_t GPR32NONZEROBits[] = { + 0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, +}; + +// CPU16RegsPlusSP Register Class... +static const MCPhysReg CPU16RegsPlusSP[] = { + Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, + Mips_A3, Mips_S0, Mips_S1, Mips_SP, +}; + +// CPU16RegsPlusSP Bit set. +static const uint8_t CPU16RegsPlusSPBits[] = { + 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, +}; + +// CPU16Regs Register Class... +static const MCPhysReg CPU16Regs[] = { + Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, +}; + +// CPU16Regs Bit set. +static const uint8_t CPU16RegsBits[] = { + 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, +}; + +// FCC Register Class... +static const MCPhysReg FCC[] = { + Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, + Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, +}; + +// FCC Bit set. +static const uint8_t FCCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, +}; + +// GPRMM16 Register Class... +static const MCPhysReg GPRMM16[] = { + Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, +}; + +// GPRMM16 Bit set. +static const uint8_t GPRMM16Bits[] = { + 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, +}; + +// GPRMM16MoveP Register Class... +static const MCPhysReg GPRMM16MoveP[] = { + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, +}; + +// GPRMM16MoveP Bit set. +static const uint8_t GPRMM16MovePBits[] = { + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, +}; + +// GPRMM16Zero Register Class... +static const MCPhysReg GPRMM16Zero[] = { + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, +}; + +// GPRMM16Zero Bit set. +static const uint8_t GPRMM16ZeroBits[] = { + 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, +}; + +// CPU16Regs_and_GPRMM16Zero Register Class... +static const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { + Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, +}; + +// CPU16Regs_and_GPRMM16Zero Bit set. +static const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, +}; + +// GPR32NONZERO_and_GPRMM16MoveP Register Class... +static const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = { + Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, +}; + +// GPR32NONZERO_and_GPRMM16MoveP Bit set. +static const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, +}; + +// GPRMM16MovePPairSecond Register Class... +static const MCPhysReg GPRMM16MovePPairSecond[] = { + Mips_A1, Mips_A2, Mips_A3, Mips_S5, Mips_S6, +}; + +// GPRMM16MovePPairSecond Bit set. +static const uint8_t GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, +}; + +// CPU16Regs_and_GPRMM16MoveP Register Class... +static const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { + Mips_S1, + Mips_V0, + Mips_V1, + Mips_S0, +}; + +// CPU16Regs_and_GPRMM16MoveP Bit set. +static const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, +}; + +// GPRMM16MoveP_and_GPRMM16Zero Register Class... +static const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { + Mips_ZERO, + Mips_S1, + Mips_V0, + Mips_V1, +}; + +// GPRMM16MoveP_and_GPRMM16Zero Bit set. +static const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, +}; + +// HI32DSP Register Class... +static const MCPhysReg HI32DSP[] = { + Mips_HI0, + Mips_HI1, + Mips_HI2, + Mips_HI3, +}; + +// HI32DSP Bit set. +static const uint8_t HI32DSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, +}; + +// LO32DSP Register Class... +static const MCPhysReg LO32DSP[] = { + Mips_LO0, + Mips_LO1, + Mips_LO2, + Mips_LO3, +}; + +// LO32DSP Bit set. +static const uint8_t LO32DSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, +}; + +// CPU16Regs_and_GPRMM16MovePPairSecond Register Class... +static const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = { + Mips_A1, + Mips_A2, + Mips_A3, +}; + +// CPU16Regs_and_GPRMM16MovePPairSecond Bit set. +static const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = { + 0x00, + 0x00, + 0x80, + 0x03, +}; + +// GPRMM16MovePPairFirst Register Class... +static const MCPhysReg GPRMM16MovePPairFirst[] = { + Mips_A0, + Mips_A1, + Mips_A2, +}; + +// GPRMM16MovePPairFirst Bit set. +static const uint8_t GPRMM16MovePPairFirstBits[] = { + 0x00, + 0x00, + 0xc0, + 0x01, +}; + +// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... +static const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { + Mips_S1, + Mips_V0, + Mips_V1, +}; + +// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. +static const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, +}; + +// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class... +static const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = { + Mips_A1, + Mips_A2, +}; + +// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set. +static const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = { + 0x00, + 0x00, + 0x80, + 0x01, +}; + +// CPURAReg Register Class... +static const MCPhysReg CPURAReg[] = { + Mips_RA, +}; + +// CPURAReg Bit set. +static const uint8_t CPURARegBits[] = { + 0x00, + 0x00, + 0x08, +}; + +// CPUSPReg Register Class... +static const MCPhysReg CPUSPReg[] = { + Mips_SP, +}; + +// CPUSPReg Bit set. +static const uint8_t CPUSPRegBits[] = { + 0x00, + 0x00, + 0x10, +}; + +// DSPCC Register Class... +static const MCPhysReg DSPCC[] = { + Mips_DSPCCond, +}; + +// DSPCC Bit set. +static const uint8_t DSPCCBits[] = { + 0x04, +}; + +// GP32 Register Class... +static const MCPhysReg GP32[] = { + Mips_GP, +}; + +// GP32 Bit set. +static const uint8_t GP32Bits[] = { + 0x00, + 0x02, +}; + +// GPR32ZERO Register Class... +static const MCPhysReg GPR32ZERO[] = { + Mips_ZERO, +}; + +// GPR32ZERO Bit set. +static const uint8_t GPR32ZEROBits[] = { + 0x00, + 0x00, + 0x20, +}; + +// HI32 Register Class... +static const MCPhysReg HI32[] = { + Mips_HI0, +}; + +// HI32 Bit set. +static const uint8_t HI32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, +}; + +// LO32 Register Class... +static const MCPhysReg LO32[] = { + Mips_LO0, +}; + +// LO32 Bit set. +static const uint8_t LO32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, +}; + +// SP32 Register Class... +static const MCPhysReg SP32[] = { + Mips_SP, +}; + +// SP32 Bit set. +static const uint8_t SP32Bits[] = { + 0x00, + 0x00, + 0x10, +}; + +// FGR64 Register Class... +static const MCPhysReg FGR64[] = { + Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, + Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, + Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, + Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, + Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, + Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, + Mips_D30_64, Mips_D31_64, +}; + +// FGR64 Bit set. +static const uint8_t FGR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, +}; + +// GPR64 Register Class... +static const MCPhysReg GPR64[] = { + Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, + Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, + Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, + Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, + Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, + Mips_FP_64, Mips_RA_64, +}; + +// GPR64 Bit set. +static const uint8_t GPR64Bits[] = { + 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, + 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, +}; + +// GPR64_with_sub_32_in_GPR32NONZERO Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = { + Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, + Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, + Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, + Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, + Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, + Mips_RA_64, +}; + +// GPR64_with_sub_32_in_GPR32NONZERO Bit set. +static const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = { + 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, + 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, +}; + +// AFGR64 Register Class... +static const MCPhysReg AFGR64[] = { + Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, + Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, + Mips_D12, Mips_D13, Mips_D14, Mips_D15, +}; + +// AFGR64 Bit set. +static const uint8_t AFGR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, +}; + +// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... +static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, + Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, +}; + +// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. +static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_CPU16Regs Register Class... +static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, + Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, +}; + +// GPR64_with_sub_32_in_CPU16Regs Bit set. +static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, + Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP Bit set. +static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_GPRMM16Zero Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, + Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, +}; + +// GPR64_with_sub_32_in_GPRMM16Zero Bit set. +static const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... +static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, + Mips_A2_64, Mips_A3_64, Mips_S1_64, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. +static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = { + Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, + Mips_S2_64, Mips_S3_64, Mips_S4_64, +}; + +// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set. +static const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = { + Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S5_64, Mips_S6_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set. +static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, +}; + +// ACC64DSP Register Class... +static const MCPhysReg ACC64DSP[] = { + Mips_AC0, + Mips_AC1, + Mips_AC2, + Mips_AC3, +}; + +// ACC64DSP Bit set. +static const uint8_t ACC64DSPBits[] = { + 0x00, + 0x00, + 0x00, + 0x3c, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... +static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { + Mips_V0_64, + Mips_V1_64, + Mips_S0_64, + Mips_S1_64, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. +static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { + Mips_ZERO_64, + Mips_V0_64, + Mips_V1_64, + Mips_S1_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. +static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class... +static const MCPhysReg + GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = { + Mips_A1_64, + Mips_A2_64, + Mips_A3_64, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set. +static const uint8_t + GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = { + Mips_A0_64, + Mips_A1_64, + Mips_A2_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set. +static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register +// Class... +static const MCPhysReg + GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { + Mips_V0_64, + Mips_V1_64, + Mips_S1_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. +static const uint8_t + GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, +}; + +// OCTEON_MPL Register Class... +static const MCPhysReg OCTEON_MPL[] = { + Mips_MPL0, + Mips_MPL1, + Mips_MPL2, +}; + +// OCTEON_MPL Bit set. +static const uint8_t OCTEON_MPLBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, +}; + +// OCTEON_P Register Class... +static const MCPhysReg OCTEON_P[] = { + Mips_P0, + Mips_P1, + Mips_P2, +}; + +// OCTEON_P Bit set. +static const uint8_t OCTEON_PBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond +// Register Class... +static const MCPhysReg + GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = { + Mips_A1_64, + Mips_A2_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit +// set. +static const uint8_t + GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, +}; + +// ACC64 Register Class... +static const MCPhysReg ACC64[] = { + Mips_AC0, +}; + +// ACC64 Bit set. +static const uint8_t ACC64Bits[] = { + 0x00, + 0x00, + 0x00, + 0x04, +}; + +// GP64 Register Class... +static const MCPhysReg GP64[] = { + Mips_GP_64, +}; + +// GP64 Bit set. +static const uint8_t GP64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, +}; + +// GPR64_with_sub_32_in_CPURAReg Register Class... +static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { + Mips_RA_64, +}; + +// GPR64_with_sub_32_in_CPURAReg Bit set. +static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, +}; + +// GPR64_with_sub_32_in_GPR32ZERO Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = { + Mips_ZERO_64, +}; + +// GPR64_with_sub_32_in_GPR32ZERO Bit set. +static const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, +}; + +// HI64 Register Class... +static const MCPhysReg HI64[] = { + Mips_HI0_64, +}; + +// HI64 Bit set. +static const uint8_t HI64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, +}; + +// LO64 Register Class... +static const MCPhysReg LO64[] = { + Mips_LO0_64, +}; + +// LO64 Bit set. +static const uint8_t LO64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, +}; + +// SP64 Register Class... +static const MCPhysReg SP64[] = { + Mips_SP_64, +}; + +// SP64 Bit set. +static const uint8_t SP64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, +}; + +// MSA128B Register Class... +static const MCPhysReg MSA128B[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, + Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, + Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, + Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, + Mips_W28, Mips_W29, Mips_W30, Mips_W31, +}; + +// MSA128B Bit set. +static const uint8_t MSA128BBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// MSA128D Register Class... +static const MCPhysReg MSA128D[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, + Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, + Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, + Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, + Mips_W28, Mips_W29, Mips_W30, Mips_W31, +}; + +// MSA128D Bit set. +static const uint8_t MSA128DBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// MSA128H Register Class... +static const MCPhysReg MSA128H[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, + Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, + Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, + Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, + Mips_W28, Mips_W29, Mips_W30, Mips_W31, +}; + +// MSA128H Bit set. +static const uint8_t MSA128HBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// MSA128W Register Class... +static const MCPhysReg MSA128W[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, + Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, + Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, + Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, + Mips_W28, Mips_W29, Mips_W30, Mips_W31, +}; + +// MSA128W Bit set. +static const uint8_t MSA128WBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// MSA128WEvens Register Class... +static const MCPhysReg MSA128WEvens[] = { + Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, + Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, + Mips_W24, Mips_W26, Mips_W28, Mips_W30, +}; + +// MSA128WEvens Bit set. +static const uint8_t MSA128WEvensBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, +}; + +// ACC128 Register Class... +static const MCPhysReg ACC128[] = { + Mips_AC0_64, +}; + +// ACC128 Bit set. +static const uint8_t ACC128Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, +}; + +// end of register classes misc + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char MipsRegClassStrings[] = { + /* 0 */ "COP0\0" + /* 5 */ "HI32\0" + /* 10 */ "LO32\0" + /* 15 */ "GP32\0" + /* 20 */ "SP32\0" + /* 25 */ "FGR32\0" + /* 31 */ "GPR32\0" + /* 37 */ "COP2\0" + /* 42 */ "COP3\0" + /* 47 */ "ACC64\0" + /* 53 */ "HI64\0" + /* 58 */ "LO64\0" + /* 63 */ "GP64\0" + /* 68 */ "SP64\0" + /* 73 */ "AFGR64\0" + /* 80 */ "GPR64\0" + /* 86 */ "MSA128F16\0" + /* 96 */ "GPRMM16\0" + /* 104 */ "ACC128\0" + /* 111 */ "MSA128B\0" + /* 119 */ "FCC\0" + /* 123 */ "DSPCC\0" + /* 129 */ "FGRCC\0" + /* 135 */ "MSA128D\0" + /* 143 */ "MSA128H\0" + /* 151 */ "OCTEON_MPL\0" + /* 162 */ "GPR64_with_sub_32_in_GPR32ZERO\0" + /* 193 */ "GPR64_with_sub_32_in_GPR32NONZERO\0" + /* 227 */ "HI32DSP\0" + /* 235 */ "LO32DSP\0" + /* 243 */ "ACC64DSP\0" + /* 252 */ "GPR64_with_sub_32_in_CPU16RegsPlusSP\0" + /* 289 */ "OCTEON_P\0" + /* 298 */ "GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP\0" + /* 349 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP\0" + /* 397 */ "GPR64_with_sub_32_in_GPRMM16MoveP\0" + /* 431 */ "CCR\0" + /* 435 */ "DSPR\0" + /* 440 */ "MSA128W\0" + /* 448 */ "GPR64_with_sub_32_in_CPU16Regs_and_" + "GPRMM16MovePPairSecond\0" + /* 506 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_" + "GPRMM16MovePPairSecond\0" + /* 576 */ "GPR64_with_sub_32_in_GPRMM16MovePPairSecond\0" + /* 620 */ "GPR64_with_sub_32_in_CPURAReg\0" + /* 650 */ "CPUSPReg\0" + /* 659 */ "MSACtrl\0" + /* 667 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero\0" + /* 717 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_" + "GPRMM16Zero\0" + /* 781 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero\0" + /* 828 */ "GPR64_with_sub_32_in_GPRMM16Zero\0" + /* 861 */ "GPR64_with_sub_32_in_CPU16Regs\0" + /* 892 */ "HWRegs\0" + /* 899 */ "MSA128WEvens\0" + /* 912 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterClass MipsMCRegisterClasses[] = { + {MSA128F16, MSA128F16Bits, sizeof(MSA128F16Bits)}, + {CCR, CCRBits, sizeof(CCRBits)}, + {COP0, COP0Bits, sizeof(COP0Bits)}, + {COP2, COP2Bits, sizeof(COP2Bits)}, + {COP3, COP3Bits, sizeof(COP3Bits)}, + {DSPR, DSPRBits, sizeof(DSPRBits)}, + {FGR32, FGR32Bits, sizeof(FGR32Bits)}, + {FGRCC, FGRCCBits, sizeof(FGRCCBits)}, + {GPR32, GPR32Bits, sizeof(GPR32Bits)}, + {HWRegs, HWRegsBits, sizeof(HWRegsBits)}, + {MSACtrl, MSACtrlBits, sizeof(MSACtrlBits)}, + {GPR32NONZERO, GPR32NONZEROBits, sizeof(GPR32NONZEROBits)}, + {CPU16RegsPlusSP, CPU16RegsPlusSPBits, sizeof(CPU16RegsPlusSPBits)}, + {CPU16Regs, CPU16RegsBits, sizeof(CPU16RegsBits)}, + {FCC, FCCBits, sizeof(FCCBits)}, + {GPRMM16, GPRMM16Bits, sizeof(GPRMM16Bits)}, + {GPRMM16MoveP, GPRMM16MovePBits, sizeof(GPRMM16MovePBits)}, + {GPRMM16Zero, GPRMM16ZeroBits, sizeof(GPRMM16ZeroBits)}, + {CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, + sizeof(CPU16Regs_and_GPRMM16ZeroBits)}, + {GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, + sizeof(GPR32NONZERO_and_GPRMM16MovePBits)}, + {GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, + sizeof(GPRMM16MovePPairSecondBits)}, + {CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, + sizeof(CPU16Regs_and_GPRMM16MovePBits)}, + {GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, + sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits)}, + {HI32DSP, HI32DSPBits, sizeof(HI32DSPBits)}, + {LO32DSP, LO32DSPBits, sizeof(LO32DSPBits)}, + {CPU16Regs_and_GPRMM16MovePPairSecond, + CPU16Regs_and_GPRMM16MovePPairSecondBits, + sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits)}, + {GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, + sizeof(GPRMM16MovePPairFirstBits)}, + {GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, + GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, + sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits)}, + {GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, + GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, + sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits)}, + {CPURAReg, CPURARegBits, sizeof(CPURARegBits)}, + {CPUSPReg, CPUSPRegBits, sizeof(CPUSPRegBits)}, + {DSPCC, DSPCCBits, sizeof(DSPCCBits)}, + {GP32, GP32Bits, sizeof(GP32Bits)}, + {GPR32ZERO, GPR32ZEROBits, sizeof(GPR32ZEROBits)}, + {HI32, HI32Bits, sizeof(HI32Bits)}, + {LO32, LO32Bits, sizeof(LO32Bits)}, + {SP32, SP32Bits, sizeof(SP32Bits)}, + {FGR64, FGR64Bits, sizeof(FGR64Bits)}, + {GPR64, GPR64Bits, sizeof(GPR64Bits)}, + {GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, + sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits)}, + {AFGR64, AFGR64Bits, sizeof(AFGR64Bits)}, + {GPR64_with_sub_32_in_CPU16RegsPlusSP, + GPR64_with_sub_32_in_CPU16RegsPlusSPBits, + sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits)}, + {GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, + sizeof(GPR64_with_sub_32_in_CPU16RegsBits)}, + {GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, + sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits)}, + {GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, + sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits)}, + {GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, + GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, + sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits)}, + {GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, + GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, + sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits)}, + {GPR64_with_sub_32_in_GPRMM16MovePPairSecond, + GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, + sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits)}, + {ACC64DSP, ACC64DSPBits, sizeof(ACC64DSPBits)}, + {GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, + GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, + sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits)}, + {GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, + GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, + sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits)}, + {GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, + GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, + sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits)}, + {GPR64_with_sub_32_in_GPRMM16MovePPairFirst, + GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, + sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits)}, + {GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, + GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, + sizeof( + GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits)}, + {OCTEON_MPL, OCTEON_MPLBits, sizeof(OCTEON_MPLBits)}, + {OCTEON_P, OCTEON_PBits, sizeof(OCTEON_PBits)}, + {GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, + GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, + sizeof( + GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits)}, + {ACC64, ACC64Bits, sizeof(ACC64Bits)}, + {GP64, GP64Bits, sizeof(GP64Bits)}, + {GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, + sizeof(GPR64_with_sub_32_in_CPURARegBits)}, + {GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, + sizeof(GPR64_with_sub_32_in_GPR32ZEROBits)}, + {HI64, HI64Bits, sizeof(HI64Bits)}, + {LO64, LO64Bits, sizeof(LO64Bits)}, + {SP64, SP64Bits, sizeof(SP64Bits)}, + {MSA128B, MSA128BBits, sizeof(MSA128BBits)}, + {MSA128D, MSA128DBits, sizeof(MSA128DBits)}, + {MSA128H, MSA128HBits, sizeof(MSA128HBits)}, + {MSA128W, MSA128WBits, sizeof(MSA128WBits)}, + {MSA128WEvens, MSA128WEvensBits, sizeof(MSA128WEvensBits)}, + {ACC128, ACC128Bits, sizeof(ACC128Bits)}, +}; + +#endif // GET_REGINFO_MC_DESC + +#ifdef GET_ASM_WRITER +#undef GET_ASM_WRITER + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +typedef struct MCMnemonic { + const char *first; + uint64_t second; +} MCMnemonic; + +static MCMnemonic createMnemonic(const char *first, uint64_t second) { + MCMnemonic mnemonic; + mnemonic.first = first; + mnemonic.second = second; + return mnemonic; +} + +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +MCMnemonic Mips_getMnemonic(const MCInst *MI) { + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = { + /* 0 */ "dmfc0\t\0" + /* 7 */ "dmfgc0\t\0" + /* 15 */ "mfhgc0\t\0" + /* 23 */ "mthgc0\t\0" + /* 31 */ "dmtgc0\t\0" + /* 39 */ "mfhc0\t\0" + /* 46 */ "mthc0\t\0" + /* 53 */ "dmtc0\t\0" + /* 60 */ "vmm0\t\0" + /* 66 */ "mtm0\t\0" + /* 72 */ "mtp0\t\0" + /* 78 */ "bbit0\t\0" + /* 85 */ "ldc1\t\0" + /* 91 */ "sdc1\t\0" + /* 97 */ "cfc1\t\0" + /* 103 */ "dmfc1\t\0" + /* 110 */ "mfhc1\t\0" + /* 117 */ "mthc1\t\0" + /* 124 */ "ctc1\t\0" + /* 130 */ "dmtc1\t\0" + /* 137 */ "lwc1\t\0" + /* 143 */ "swc1\t\0" + /* 149 */ "ldxc1\t\0" + /* 156 */ "sdxc1\t\0" + /* 163 */ "luxc1\t\0" + /* 170 */ "suxc1\t\0" + /* 177 */ "lwxc1\t\0" + /* 184 */ "swxc1\t\0" + /* 191 */ "mtm1\t\0" + /* 197 */ "mtp1\t\0" + /* 203 */ "bbit1\t\0" + /* 210 */ "bbit032\t\0" + /* 219 */ "bbit132\t\0" + /* 228 */ "dsra32\t\0" + /* 236 */ "bposge32\t\0" + /* 246 */ "dsll32\t\0" + /* 254 */ "dsrl32\t\0" + /* 262 */ "lwm32\t\0" + /* 269 */ "swm32\t\0" + /* 276 */ "drotr32\t\0" + /* 285 */ "cins32\t\0" + /* 293 */ "exts32\t\0" + /* 301 */ "ldc2\t\0" + /* 307 */ "sdc2\t\0" + /* 313 */ "cfc2\t\0" + /* 319 */ "dmfc2\t\0" + /* 326 */ "mfhc2\t\0" + /* 333 */ "mthc2\t\0" + /* 340 */ "ctc2\t\0" + /* 346 */ "dmtc2\t\0" + /* 353 */ "lwc2\t\0" + /* 359 */ "swc2\t\0" + /* 365 */ "mtm2\t\0" + /* 371 */ "mtp2\t\0" + /* 377 */ "addiur2\t\0" + /* 386 */ "ldc3\t\0" + /* 392 */ "sdc3\t\0" + /* 398 */ "lwc3\t\0" + /* 404 */ "swc3\t\0" + /* 410 */ "addius5\t\0" + /* 419 */ "sb16\t\0" + /* 425 */ "bc16\t\0" + /* 431 */ "jrc16\t\0" + /* 438 */ "bnezc16\t\0" + /* 447 */ "beqzc16\t\0" + /* 456 */ "and16\t\0" + /* 463 */ "move16\t\0" + /* 471 */ "sh16\t\0" + /* 477 */ "andi16\t\0" + /* 485 */ "mfhi16\t\0" + /* 493 */ "li16\t\0" + /* 499 */ "break16\t\0" + /* 508 */ "sll16\t\0" + /* 515 */ "srl16\t\0" + /* 522 */ "lwm16\t\0" + /* 529 */ "swm16\t\0" + /* 536 */ "mflo16\t\0" + /* 544 */ "sdbbp16\t\0" + /* 553 */ "jr16\t\0" + /* 559 */ "xor16\t\0" + /* 566 */ "jalrs16\t\0" + /* 575 */ "not16\t\0" + /* 582 */ "lbu16\t\0" + /* 589 */ "subu16\t\0" + /* 597 */ "addu16\t\0" + /* 605 */ "lhu16\t\0" + /* 612 */ "lw16\t\0" + /* 618 */ "sw16\t\0" + /* 624 */ "bnez16\t\0" + /* 632 */ "beqz16\t\0" + /* 640 */ "saa\t\0" + /* 645 */ "preceu.ph.qbla\t\0" + /* 661 */ "precequ.ph.qbla\t\0" + /* 678 */ "dla\t\0" + /* 683 */ "preceu.ph.qbra\t\0" + /* 699 */ "precequ.ph.qbra\t\0" + /* 716 */ "dsra\t\0" + /* 722 */ "dlsa\t\0" + /* 728 */ "cfcmsa\t\0" + /* 736 */ "ctcmsa\t\0" + /* 744 */ "add_a.b\t\0" + /* 753 */ "min_a.b\t\0" + /* 762 */ "adds_a.b\t\0" + /* 772 */ "max_a.b\t\0" + /* 781 */ "sra.b\t\0" + /* 788 */ "nloc.b\t\0" + /* 796 */ "nlzc.b\t\0" + /* 804 */ "sld.b\t\0" + /* 811 */ "pckod.b\t\0" + /* 820 */ "ilvod.b\t\0" + /* 829 */ "insve.b\t\0" + /* 838 */ "vshf.b\t\0" + /* 846 */ "bneg.b\t\0" + /* 854 */ "srai.b\t\0" + /* 862 */ "sldi.b\t\0" + /* 870 */ "andi.b\t\0" + /* 878 */ "bnegi.b\t\0" + /* 887 */ "bseli.b\t\0" + /* 896 */ "slli.b\t\0" + /* 904 */ "srli.b\t\0" + /* 912 */ "binsli.b\t\0" + /* 922 */ "ceqi.b\t\0" + /* 930 */ "srari.b\t\0" + /* 939 */ "bclri.b\t\0" + /* 948 */ "srlri.b\t\0" + /* 957 */ "nori.b\t\0" + /* 965 */ "xori.b\t\0" + /* 973 */ "binsri.b\t\0" + /* 983 */ "splati.b\t\0" + /* 993 */ "bseti.b\t\0" + /* 1002 */ "subvi.b\t\0" + /* 1011 */ "addvi.b\t\0" + /* 1020 */ "bmzi.b\t\0" + /* 1028 */ "bmnzi.b\t\0" + /* 1037 */ "fill.b\t\0" + /* 1045 */ "sll.b\t\0" + /* 1052 */ "srl.b\t\0" + /* 1059 */ "binsl.b\t\0" + /* 1068 */ "ilvl.b\t\0" + /* 1076 */ "ceq.b\t\0" + /* 1083 */ "srar.b\t\0" + /* 1091 */ "bclr.b\t\0" + /* 1099 */ "srlr.b\t\0" + /* 1107 */ "binsr.b\t\0" + /* 1116 */ "ilvr.b\t\0" + /* 1124 */ "asub_s.b\t\0" + /* 1134 */ "mod_s.b\t\0" + /* 1143 */ "cle_s.b\t\0" + /* 1152 */ "ave_s.b\t\0" + /* 1161 */ "clei_s.b\t\0" + /* 1171 */ "mini_s.b\t\0" + /* 1181 */ "clti_s.b\t\0" + /* 1191 */ "maxi_s.b\t\0" + /* 1201 */ "min_s.b\t\0" + /* 1210 */ "aver_s.b\t\0" + /* 1220 */ "subs_s.b\t\0" + /* 1230 */ "adds_s.b\t\0" + /* 1240 */ "sat_s.b\t\0" + /* 1249 */ "clt_s.b\t\0" + /* 1258 */ "subsuu_s.b\t\0" + /* 1270 */ "div_s.b\t\0" + /* 1279 */ "max_s.b\t\0" + /* 1288 */ "copy_s.b\t\0" + /* 1298 */ "splat.b\t\0" + /* 1307 */ "bset.b\t\0" + /* 1315 */ "pcnt.b\t\0" + /* 1323 */ "insert.b\t\0" + /* 1333 */ "st.b\t\0" + /* 1339 */ "asub_u.b\t\0" + /* 1349 */ "mod_u.b\t\0" + /* 1358 */ "cle_u.b\t\0" + /* 1367 */ "ave_u.b\t\0" + /* 1376 */ "clei_u.b\t\0" + /* 1386 */ "mini_u.b\t\0" + /* 1396 */ "clti_u.b\t\0" + /* 1406 */ "maxi_u.b\t\0" + /* 1416 */ "min_u.b\t\0" + /* 1425 */ "aver_u.b\t\0" + /* 1435 */ "subs_u.b\t\0" + /* 1445 */ "adds_u.b\t\0" + /* 1455 */ "subsus_u.b\t\0" + /* 1467 */ "sat_u.b\t\0" + /* 1476 */ "clt_u.b\t\0" + /* 1485 */ "div_u.b\t\0" + /* 1494 */ "max_u.b\t\0" + /* 1503 */ "copy_u.b\t\0" + /* 1513 */ "msubv.b\t\0" + /* 1522 */ "maddv.b\t\0" + /* 1531 */ "pckev.b\t\0" + /* 1540 */ "ilvev.b\t\0" + /* 1549 */ "mulv.b\t\0" + /* 1557 */ "bz.b\t\0" + /* 1563 */ "bnz.b\t\0" + /* 1570 */ "crc32b\t\0" + /* 1578 */ "crc32cb\t\0" + /* 1587 */ "seb\t\0" + /* 1592 */ "jalrc.hb\t\0" + /* 1602 */ "jr.hb\t\0" + /* 1609 */ "jalr.hb\t\0" + /* 1618 */ "lb\t\0" + /* 1622 */ "shra.qb\t\0" + /* 1631 */ "cmpgdu.le.qb\t\0" + /* 1645 */ "cmpgu.le.qb\t\0" + /* 1658 */ "cmpu.le.qb\t\0" + /* 1670 */ "subuh.qb\t\0" + /* 1680 */ "adduh.qb\t\0" + /* 1690 */ "pick.qb\t\0" + /* 1699 */ "shll.qb\t\0" + /* 1708 */ "repl.qb\t\0" + /* 1717 */ "shrl.qb\t\0" + /* 1726 */ "cmpgdu.eq.qb\t\0" + /* 1740 */ "cmpgu.eq.qb\t\0" + /* 1753 */ "cmpu.eq.qb\t\0" + /* 1765 */ "shra_r.qb\t\0" + /* 1776 */ "subuh_r.qb\t\0" + /* 1788 */ "adduh_r.qb\t\0" + /* 1800 */ "shrav_r.qb\t\0" + /* 1812 */ "absq_s.qb\t\0" + /* 1823 */ "subu_s.qb\t\0" + /* 1834 */ "addu_s.qb\t\0" + /* 1845 */ "cmpgdu.lt.qb\t\0" + /* 1859 */ "cmpgu.lt.qb\t\0" + /* 1872 */ "cmpu.lt.qb\t\0" + /* 1884 */ "subu.qb\t\0" + /* 1893 */ "addu.qb\t\0" + /* 1902 */ "shrav.qb\t\0" + /* 1912 */ "shllv.qb\t\0" + /* 1922 */ "replv.qb\t\0" + /* 1932 */ "shrlv.qb\t\0" + /* 1942 */ "raddu.w.qb\t\0" + /* 1954 */ "sb\t\0" + /* 1958 */ "modsub\t\0" + /* 1966 */ "msub\t\0" + /* 1972 */ "bposge32c\t\0" + /* 1983 */ "bc\t\0" + /* 1987 */ "bgec\t\0" + /* 1993 */ "bnec\t\0" + /* 1999 */ "jic\t\0" + /* 2004 */ "balc\t\0" + /* 2010 */ "jialc\t\0" + /* 2017 */ "bgezalc\t\0" + /* 2026 */ "blezalc\t\0" + /* 2035 */ "bnezalc\t\0" + /* 2044 */ "beqzalc\t\0" + /* 2053 */ "bgtzalc\t\0" + /* 2062 */ "bltzalc\t\0" + /* 2071 */ "sync\t\0" + /* 2077 */ "ldpc\t\0" + /* 2083 */ "auipc\t\0" + /* 2090 */ "aluipc\t\0" + /* 2098 */ "addiupc\t\0" + /* 2107 */ "lwupc\t\0" + /* 2114 */ "lwpc\t\0" + /* 2120 */ "beqc\t\0" + /* 2126 */ "jrc\t\0" + /* 2131 */ "jalrc\t\0" + /* 2138 */ "addsc\t\0" + /* 2145 */ "bltc\t\0" + /* 2151 */ "bgeuc\t\0" + /* 2158 */ "bltuc\t\0" + /* 2165 */ "bnvc\t\0" + /* 2171 */ "bovc\t\0" + /* 2177 */ "addwc\t\0" + /* 2184 */ "bgezc\t\0" + /* 2191 */ "blezc\t\0" + /* 2198 */ "bc1nezc\t\0" + /* 2207 */ "bc2nezc\t\0" + /* 2216 */ "bnezc\t\0" + /* 2223 */ "bc1eqzc\t\0" + /* 2232 */ "bc2eqzc\t\0" + /* 2241 */ "beqzc\t\0" + /* 2248 */ "bgtzc\t\0" + /* 2255 */ "bltzc\t\0" + /* 2262 */ "flog2.d\t\0" + /* 2271 */ "fexp2.d\t\0" + /* 2280 */ "add_a.d\t\0" + /* 2289 */ "fmin_a.d\t\0" + /* 2299 */ "adds_a.d\t\0" + /* 2309 */ "fmax_a.d\t\0" + /* 2319 */ "mina.d\t\0" + /* 2327 */ "sra.d\t\0" + /* 2334 */ "maxa.d\t\0" + /* 2342 */ "fsub.d\t\0" + /* 2350 */ "fmsub.d\t\0" + /* 2359 */ "nmsub.d\t\0" + /* 2368 */ "nloc.d\t\0" + /* 2376 */ "nlzc.d\t\0" + /* 2384 */ "fadd.d\t\0" + /* 2392 */ "fmadd.d\t\0" + /* 2401 */ "nmadd.d\t\0" + /* 2410 */ "sld.d\t\0" + /* 2417 */ "pckod.d\t\0" + /* 2426 */ "ilvod.d\t\0" + /* 2435 */ "c.nge.d\t\0" + /* 2444 */ "c.le.d\t\0" + /* 2452 */ "cmp.le.d\t\0" + /* 2462 */ "fcle.d\t\0" + /* 2470 */ "c.ngle.d\t\0" + /* 2480 */ "c.ole.d\t\0" + /* 2489 */ "cmp.sle.d\t\0" + /* 2500 */ "fsle.d\t\0" + /* 2508 */ "c.ule.d\t\0" + /* 2517 */ "cmp.ule.d\t\0" + /* 2528 */ "fcule.d\t\0" + /* 2537 */ "cmp.sule.d\t\0" + /* 2549 */ "fsule.d\t\0" + /* 2558 */ "fcne.d\t\0" + /* 2566 */ "fsne.d\t\0" + /* 2574 */ "fcune.d\t\0" + /* 2583 */ "fsune.d\t\0" + /* 2592 */ "insve.d\t\0" + /* 2601 */ "c.f.d\t\0" + /* 2608 */ "cmp.af.d\t\0" + /* 2618 */ "fcaf.d\t\0" + /* 2626 */ "cmp.saf.d\t\0" + /* 2637 */ "fsaf.d\t\0" + /* 2645 */ "msubf.d\t\0" + /* 2654 */ "maddf.d\t\0" + /* 2663 */ "vshf.d\t\0" + /* 2671 */ "c.sf.d\t\0" + /* 2679 */ "movf.d\t\0" + /* 2687 */ "bneg.d\t\0" + /* 2695 */ "srai.d\t\0" + /* 2703 */ "sldi.d\t\0" + /* 2711 */ "bnegi.d\t\0" + /* 2720 */ "slli.d\t\0" + /* 2728 */ "srli.d\t\0" + /* 2736 */ "binsli.d\t\0" + /* 2746 */ "ceqi.d\t\0" + /* 2754 */ "srari.d\t\0" + /* 2763 */ "bclri.d\t\0" + /* 2772 */ "srlri.d\t\0" + /* 2781 */ "binsri.d\t\0" + /* 2791 */ "splati.d\t\0" + /* 2801 */ "bseti.d\t\0" + /* 2810 */ "subvi.d\t\0" + /* 2819 */ "addvi.d\t\0" + /* 2828 */ "trunc.l.d\t\0" + /* 2839 */ "round.l.d\t\0" + /* 2850 */ "ceil.l.d\t\0" + /* 2860 */ "floor.l.d\t\0" + /* 2871 */ "cvt.l.d\t\0" + /* 2880 */ "sel.d\t\0" + /* 2887 */ "c.ngl.d\t\0" + /* 2896 */ "fill.d\t\0" + /* 2904 */ "sll.d\t\0" + /* 2911 */ "fexupl.d\t\0" + /* 2921 */ "ffql.d\t\0" + /* 2929 */ "srl.d\t\0" + /* 2936 */ "binsl.d\t\0" + /* 2945 */ "fmul.d\t\0" + /* 2953 */ "ilvl.d\t\0" + /* 2961 */ "fmin.d\t\0" + /* 2969 */ "c.un.d\t\0" + /* 2977 */ "cmp.un.d\t\0" + /* 2987 */ "fcun.d\t\0" + /* 2995 */ "cmp.sun.d\t\0" + /* 3006 */ "fsun.d\t\0" + /* 3014 */ "movn.d\t\0" + /* 3022 */ "frcp.d\t\0" + /* 3030 */ "recip.d\t\0" + /* 3039 */ "c.eq.d\t\0" + /* 3047 */ "cmp.eq.d\t\0" + /* 3057 */ "fceq.d\t\0" + /* 3065 */ "c.seq.d\t\0" + /* 3074 */ "cmp.seq.d\t\0" + /* 3085 */ "fseq.d\t\0" + /* 3093 */ "c.ueq.d\t\0" + /* 3102 */ "cmp.ueq.d\t\0" + /* 3113 */ "fcueq.d\t\0" + /* 3122 */ "cmp.sueq.d\t\0" + /* 3134 */ "fsueq.d\t\0" + /* 3143 */ "srar.d\t\0" + /* 3151 */ "bclr.d\t\0" + /* 3159 */ "srlr.d\t\0" + /* 3167 */ "fcor.d\t\0" + /* 3175 */ "fsor.d\t\0" + /* 3183 */ "fexupr.d\t\0" + /* 3193 */ "ffqr.d\t\0" + /* 3201 */ "binsr.d\t\0" + /* 3210 */ "ilvr.d\t\0" + /* 3218 */ "cvt.s.d\t\0" + /* 3227 */ "asub_s.d\t\0" + /* 3237 */ "hsub_s.d\t\0" + /* 3247 */ "dpsub_s.d\t\0" + /* 3258 */ "ftrunc_s.d\t\0" + /* 3270 */ "hadd_s.d\t\0" + /* 3280 */ "dpadd_s.d\t\0" + /* 3291 */ "mod_s.d\t\0" + /* 3300 */ "cle_s.d\t\0" + /* 3309 */ "ave_s.d\t\0" + /* 3318 */ "clei_s.d\t\0" + /* 3328 */ "mini_s.d\t\0" + /* 3338 */ "clti_s.d\t\0" + /* 3348 */ "maxi_s.d\t\0" + /* 3358 */ "min_s.d\t\0" + /* 3367 */ "dotp_s.d\t\0" + /* 3377 */ "aver_s.d\t\0" + /* 3387 */ "subs_s.d\t\0" + /* 3397 */ "adds_s.d\t\0" + /* 3407 */ "sat_s.d\t\0" + /* 3416 */ "clt_s.d\t\0" + /* 3425 */ "ffint_s.d\t\0" + /* 3436 */ "ftint_s.d\t\0" + /* 3447 */ "subsuu_s.d\t\0" + /* 3459 */ "div_s.d\t\0" + /* 3468 */ "max_s.d\t\0" + /* 3477 */ "copy_s.d\t\0" + /* 3487 */ "abs.d\t\0" + /* 3494 */ "fclass.d\t\0" + /* 3504 */ "splat.d\t\0" + /* 3513 */ "bset.d\t\0" + /* 3521 */ "c.ngt.d\t\0" + /* 3530 */ "c.lt.d\t\0" + /* 3538 */ "cmp.lt.d\t\0" + /* 3548 */ "fclt.d\t\0" + /* 3556 */ "c.olt.d\t\0" + /* 3565 */ "cmp.slt.d\t\0" + /* 3576 */ "fslt.d\t\0" + /* 3584 */ "c.ult.d\t\0" + /* 3593 */ "cmp.ult.d\t\0" + /* 3604 */ "fcult.d\t\0" + /* 3613 */ "cmp.sult.d\t\0" + /* 3625 */ "fsult.d\t\0" + /* 3634 */ "pcnt.d\t\0" + /* 3642 */ "frint.d\t\0" + /* 3651 */ "insert.d\t\0" + /* 3661 */ "fsqrt.d\t\0" + /* 3670 */ "frsqrt.d\t\0" + /* 3680 */ "st.d\t\0" + /* 3686 */ "movt.d\t\0" + /* 3694 */ "asub_u.d\t\0" + /* 3704 */ "hsub_u.d\t\0" + /* 3714 */ "dpsub_u.d\t\0" + /* 3725 */ "ftrunc_u.d\t\0" + /* 3737 */ "hadd_u.d\t\0" + /* 3747 */ "dpadd_u.d\t\0" + /* 3758 */ "mod_u.d\t\0" + /* 3767 */ "cle_u.d\t\0" + /* 3776 */ "ave_u.d\t\0" + /* 3785 */ "clei_u.d\t\0" + /* 3795 */ "mini_u.d\t\0" + /* 3805 */ "clti_u.d\t\0" + /* 3815 */ "maxi_u.d\t\0" + /* 3825 */ "min_u.d\t\0" + /* 3834 */ "dotp_u.d\t\0" + /* 3844 */ "aver_u.d\t\0" + /* 3854 */ "subs_u.d\t\0" + /* 3864 */ "adds_u.d\t\0" + /* 3874 */ "subsus_u.d\t\0" + /* 3886 */ "sat_u.d\t\0" + /* 3895 */ "clt_u.d\t\0" + /* 3904 */ "ffint_u.d\t\0" + /* 3915 */ "ftint_u.d\t\0" + /* 3926 */ "div_u.d\t\0" + /* 3935 */ "max_u.d\t\0" + /* 3944 */ "msubv.d\t\0" + /* 3953 */ "maddv.d\t\0" + /* 3962 */ "pckev.d\t\0" + /* 3971 */ "ilvev.d\t\0" + /* 3980 */ "fdiv.d\t\0" + /* 3988 */ "mulv.d\t\0" + /* 3996 */ "mov.d\t\0" + /* 4003 */ "trunc.w.d\t\0" + /* 4014 */ "round.w.d\t\0" + /* 4025 */ "ceil.w.d\t\0" + /* 4035 */ "floor.w.d\t\0" + /* 4046 */ "cvt.w.d\t\0" + /* 4055 */ "fmax.d\t\0" + /* 4063 */ "bz.d\t\0" + /* 4069 */ "selnez.d\t\0" + /* 4079 */ "bnz.d\t\0" + /* 4086 */ "seleqz.d\t\0" + /* 4096 */ "movz.d\t\0" + /* 4104 */ "crc32d\t\0" + /* 4112 */ "saad\t\0" + /* 4118 */ "crc32cd\t\0" + /* 4127 */ "scd\t\0" + /* 4132 */ "dadd\t\0" + /* 4138 */ "madd\t\0" + /* 4144 */ "dshd\t\0" + /* 4150 */ "yield\t\0" + /* 4157 */ "lld\t\0" + /* 4162 */ "and\t\0" + /* 4167 */ "prepend\t\0" + /* 4176 */ "append\t\0" + /* 4184 */ "dmod\t\0" + /* 4190 */ "sd\t\0" + /* 4194 */ "lbe\t\0" + /* 4199 */ "sbe\t\0" + /* 4204 */ "sce\t\0" + /* 4209 */ "cachee\t\0" + /* 4217 */ "prefe\t\0" + /* 4224 */ "bge\t\0" + /* 4229 */ "sge\t\0" + /* 4234 */ "tge\t\0" + /* 4239 */ "cache\t\0" + /* 4246 */ "lhe\t\0" + /* 4251 */ "she\t\0" + /* 4256 */ "sigrie\t\0" + /* 4264 */ "ble\t\0" + /* 4269 */ "lle\t\0" + /* 4274 */ "sle\t\0" + /* 4279 */ "lwle\t\0" + /* 4285 */ "swle\t\0" + /* 4291 */ "bne\t\0" + /* 4296 */ "sne\t\0" + /* 4301 */ "tne\t\0" + /* 4306 */ "dvpe\t\0" + /* 4312 */ "evpe\t\0" + /* 4318 */ "lwre\t\0" + /* 4324 */ "swre\t\0" + /* 4330 */ "lbue\t\0" + /* 4336 */ "lhue\t\0" + /* 4342 */ "move\t\0" + /* 4348 */ "lwe\t\0" + /* 4353 */ "swe\t\0" + /* 4358 */ "bc0f\t\0" + /* 4364 */ "bc1f\t\0" + /* 4370 */ "bc2f\t\0" + /* 4376 */ "bc3f\t\0" + /* 4382 */ "pref\t\0" + /* 4388 */ "movf\t\0" + /* 4394 */ "neg\t\0" + /* 4399 */ "add_a.h\t\0" + /* 4408 */ "min_a.h\t\0" + /* 4417 */ "adds_a.h\t\0" + /* 4427 */ "max_a.h\t\0" + /* 4436 */ "sra.h\t\0" + /* 4443 */ "nloc.h\t\0" + /* 4451 */ "nlzc.h\t\0" + /* 4459 */ "sld.h\t\0" + /* 4466 */ "pckod.h\t\0" + /* 4475 */ "ilvod.h\t\0" + /* 4484 */ "insve.h\t\0" + /* 4493 */ "vshf.h\t\0" + /* 4501 */ "bneg.h\t\0" + /* 4509 */ "srai.h\t\0" + /* 4517 */ "sldi.h\t\0" + /* 4525 */ "bnegi.h\t\0" + /* 4534 */ "slli.h\t\0" + /* 4542 */ "srli.h\t\0" + /* 4550 */ "binsli.h\t\0" + /* 4560 */ "ceqi.h\t\0" + /* 4568 */ "srari.h\t\0" + /* 4577 */ "bclri.h\t\0" + /* 4586 */ "srlri.h\t\0" + /* 4595 */ "binsri.h\t\0" + /* 4605 */ "splati.h\t\0" + /* 4615 */ "bseti.h\t\0" + /* 4624 */ "subvi.h\t\0" + /* 4633 */ "addvi.h\t\0" + /* 4642 */ "fill.h\t\0" + /* 4650 */ "sll.h\t\0" + /* 4657 */ "srl.h\t\0" + /* 4664 */ "binsl.h\t\0" + /* 4673 */ "ilvl.h\t\0" + /* 4681 */ "fexdo.h\t\0" + /* 4690 */ "msub_q.h\t\0" + /* 4700 */ "madd_q.h\t\0" + /* 4710 */ "mul_q.h\t\0" + /* 4719 */ "msubr_q.h\t\0" + /* 4730 */ "maddr_q.h\t\0" + /* 4741 */ "mulr_q.h\t\0" + /* 4751 */ "ceq.h\t\0" + /* 4758 */ "ftq.h\t\0" + /* 4765 */ "srar.h\t\0" + /* 4773 */ "bclr.h\t\0" + /* 4781 */ "srlr.h\t\0" + /* 4789 */ "binsr.h\t\0" + /* 4798 */ "ilvr.h\t\0" + /* 4806 */ "asub_s.h\t\0" + /* 4816 */ "hsub_s.h\t\0" + /* 4826 */ "dpsub_s.h\t\0" + /* 4837 */ "hadd_s.h\t\0" + /* 4847 */ "dpadd_s.h\t\0" + /* 4858 */ "mod_s.h\t\0" + /* 4867 */ "cle_s.h\t\0" + /* 4876 */ "ave_s.h\t\0" + /* 4885 */ "clei_s.h\t\0" + /* 4895 */ "mini_s.h\t\0" + /* 4905 */ "clti_s.h\t\0" + /* 4915 */ "maxi_s.h\t\0" + /* 4925 */ "min_s.h\t\0" + /* 4934 */ "dotp_s.h\t\0" + /* 4944 */ "aver_s.h\t\0" + /* 4954 */ "extr_s.h\t\0" + /* 4964 */ "subs_s.h\t\0" + /* 4974 */ "adds_s.h\t\0" + /* 4984 */ "sat_s.h\t\0" + /* 4993 */ "clt_s.h\t\0" + /* 5002 */ "subsuu_s.h\t\0" + /* 5014 */ "div_s.h\t\0" + /* 5023 */ "extrv_s.h\t\0" + /* 5034 */ "max_s.h\t\0" + /* 5043 */ "copy_s.h\t\0" + /* 5053 */ "splat.h\t\0" + /* 5062 */ "bset.h\t\0" + /* 5070 */ "pcnt.h\t\0" + /* 5078 */ "insert.h\t\0" + /* 5088 */ "st.h\t\0" + /* 5094 */ "asub_u.h\t\0" + /* 5104 */ "hsub_u.h\t\0" + /* 5114 */ "dpsub_u.h\t\0" + /* 5125 */ "hadd_u.h\t\0" + /* 5135 */ "dpadd_u.h\t\0" + /* 5146 */ "mod_u.h\t\0" + /* 5155 */ "cle_u.h\t\0" + /* 5164 */ "ave_u.h\t\0" + /* 5173 */ "clei_u.h\t\0" + /* 5183 */ "mini_u.h\t\0" + /* 5193 */ "clti_u.h\t\0" + /* 5203 */ "maxi_u.h\t\0" + /* 5213 */ "min_u.h\t\0" + /* 5222 */ "dotp_u.h\t\0" + /* 5232 */ "aver_u.h\t\0" + /* 5242 */ "subs_u.h\t\0" + /* 5252 */ "adds_u.h\t\0" + /* 5262 */ "subsus_u.h\t\0" + /* 5274 */ "sat_u.h\t\0" + /* 5283 */ "clt_u.h\t\0" + /* 5292 */ "div_u.h\t\0" + /* 5301 */ "max_u.h\t\0" + /* 5310 */ "copy_u.h\t\0" + /* 5320 */ "msubv.h\t\0" + /* 5329 */ "maddv.h\t\0" + /* 5338 */ "pckev.h\t\0" + /* 5347 */ "ilvev.h\t\0" + /* 5356 */ "mulv.h\t\0" + /* 5364 */ "bz.h\t\0" + /* 5370 */ "bnz.h\t\0" + /* 5377 */ "crc32h\t\0" + /* 5385 */ "dsbh\t\0" + /* 5391 */ "wsbh\t\0" + /* 5397 */ "crc32ch\t\0" + /* 5406 */ "seh\t\0" + /* 5411 */ "ulh\t\0" + /* 5416 */ "shra.ph\t\0" + /* 5425 */ "precrq.qb.ph\t\0" + /* 5439 */ "precr.qb.ph\t\0" + /* 5452 */ "precrqu_s.qb.ph\t\0" + /* 5469 */ "cmp.le.ph\t\0" + /* 5480 */ "subqh.ph\t\0" + /* 5490 */ "addqh.ph\t\0" + /* 5500 */ "pick.ph\t\0" + /* 5509 */ "shll.ph\t\0" + /* 5518 */ "repl.ph\t\0" + /* 5527 */ "shrl.ph\t\0" + /* 5536 */ "packrl.ph\t\0" + /* 5547 */ "mul.ph\t\0" + /* 5555 */ "subq.ph\t\0" + /* 5564 */ "addq.ph\t\0" + /* 5573 */ "cmp.eq.ph\t\0" + /* 5584 */ "shra_r.ph\t\0" + /* 5595 */ "subqh_r.ph\t\0" + /* 5607 */ "addqh_r.ph\t\0" + /* 5619 */ "shrav_r.ph\t\0" + /* 5631 */ "shll_s.ph\t\0" + /* 5642 */ "mul_s.ph\t\0" + /* 5652 */ "subq_s.ph\t\0" + /* 5663 */ "addq_s.ph\t\0" + /* 5674 */ "mulq_s.ph\t\0" + /* 5685 */ "absq_s.ph\t\0" + /* 5696 */ "subu_s.ph\t\0" + /* 5707 */ "addu_s.ph\t\0" + /* 5718 */ "shllv_s.ph\t\0" + /* 5730 */ "mulq_rs.ph\t\0" + /* 5742 */ "cmp.lt.ph\t\0" + /* 5753 */ "subu.ph\t\0" + /* 5762 */ "addu.ph\t\0" + /* 5771 */ "shrav.ph\t\0" + /* 5781 */ "shllv.ph\t\0" + /* 5791 */ "replv.ph\t\0" + /* 5801 */ "shrlv.ph\t\0" + /* 5811 */ "dpa.w.ph\t\0" + /* 5821 */ "dpaqx_sa.w.ph\t\0" + /* 5836 */ "dpsqx_sa.w.ph\t\0" + /* 5851 */ "mulsa.w.ph\t\0" + /* 5863 */ "dpaq_s.w.ph\t\0" + /* 5876 */ "mulsaq_s.w.ph\t\0" + /* 5891 */ "dpsq_s.w.ph\t\0" + /* 5904 */ "dpaqx_s.w.ph\t\0" + /* 5918 */ "dpsqx_s.w.ph\t\0" + /* 5932 */ "dps.w.ph\t\0" + /* 5942 */ "dpax.w.ph\t\0" + /* 5953 */ "dpsx.w.ph\t\0" + /* 5964 */ "ush\t\0" + /* 5969 */ "dmuh\t\0" + /* 5975 */ "synci\t\0" + /* 5982 */ "daddi\t\0" + /* 5989 */ "andi\t\0" + /* 5995 */ "tgei\t\0" + /* 6001 */ "snei\t\0" + /* 6007 */ "tnei\t\0" + /* 6013 */ "dahi\t\0" + /* 6019 */ "mfhi\t\0" + /* 6025 */ "mthi\t\0" + /* 6031 */ ".align 2\n\tli\t\0" + /* 6045 */ "dli\t\0" + /* 6050 */ "cmpi\t\0" + /* 6056 */ "seqi\t\0" + /* 6062 */ "teqi\t\0" + /* 6068 */ "xori\t\0" + /* 6074 */ "dati\t\0" + /* 6080 */ "slti\t\0" + /* 6086 */ "tlti\t\0" + /* 6092 */ "daui\t\0" + /* 6098 */ "lui\t\0" + /* 6103 */ "ginvi\t\0" + /* 6110 */ "j\t\0" + /* 6113 */ "break\t\0" + /* 6120 */ "fork\t\0" + /* 6126 */ "cvt.d.l\t\0" + /* 6135 */ "cvt.s.l\t\0" + /* 6144 */ "bal\t\0" + /* 6149 */ "jal\t\0" + /* 6154 */ "bgezal\t\0" + /* 6162 */ "bltzal\t\0" + /* 6170 */ "dpau.h.qbl\t\0" + /* 6182 */ "dpsu.h.qbl\t\0" + /* 6194 */ "muleu_s.ph.qbl\t\0" + /* 6210 */ "preceu.ph.qbl\t\0" + /* 6225 */ "precequ.ph.qbl\t\0" + /* 6241 */ "ldl\t\0" + /* 6246 */ "sdl\t\0" + /* 6251 */ "bgel\t\0" + /* 6257 */ "blel\t\0" + /* 6263 */ "bnel\t\0" + /* 6269 */ "bc1fl\t\0" + /* 6276 */ "bc2fl\t\0" + /* 6283 */ "bc3fl\t\0" + /* 6290 */ "maq_sa.w.phl\t\0" + /* 6304 */ "preceq.w.phl\t\0" + /* 6318 */ "maq_s.w.phl\t\0" + /* 6331 */ "muleq_s.w.phl\t\0" + /* 6346 */ "hypcall\t\0" + /* 6355 */ "syscall\t\0" + /* 6364 */ "bgezall\t\0" + /* 6373 */ "bltzall\t\0" + /* 6382 */ "dsll\t\0" + /* 6388 */ "drol\t\0" + /* 6394 */ "cvt.s.pl\t\0" + /* 6404 */ "beql\t\0" + /* 6410 */ "dsrl\t\0" + /* 6416 */ "bc1tl\t\0" + /* 6423 */ "bc2tl\t\0" + /* 6430 */ "bc3tl\t\0" + /* 6437 */ "bgtl\t\0" + /* 6443 */ "bltl\t\0" + /* 6449 */ "bgeul\t\0" + /* 6456 */ "bleul\t\0" + /* 6463 */ "dmul\t\0" + /* 6469 */ "bgtul\t\0" + /* 6476 */ "bltul\t\0" + /* 6483 */ "lwl\t\0" + /* 6488 */ "swl\t\0" + /* 6493 */ "bgezl\t\0" + /* 6500 */ "blezl\t\0" + /* 6507 */ "bgtzl\t\0" + /* 6514 */ "bltzl\t\0" + /* 6521 */ "drem\t\0" + /* 6527 */ "dinsm\t\0" + /* 6534 */ "dextm\t\0" + /* 6541 */ "lwm\t\0" + /* 6546 */ "swm\t\0" + /* 6551 */ "balign\t\0" + /* 6559 */ "dalign\t\0" + /* 6567 */ "movn\t\0" + /* 6573 */ "dclo\t\0" + /* 6579 */ "mflo\t\0" + /* 6585 */ "shilo\t\0" + /* 6592 */ "mtlo\t\0" + /* 6598 */ "dmulo\t\0" + /* 6605 */ "dbitswap\t\0" + /* 6615 */ "sdbbp\t\0" + /* 6622 */ "extpdp\t\0" + /* 6630 */ "movep\t\0" + /* 6637 */ "mthlip\t\0" + /* 6645 */ "cmp\t\0" + /* 6650 */ "dpop\t\0" + /* 6656 */ "addiur1sp\t\0" + /* 6667 */ "load_ccond_dsp\t\0" + /* 6683 */ "store_ccond_dsp\t\0" + /* 6700 */ "rddsp\t\0" + /* 6707 */ "wrdsp\t\0" + /* 6714 */ "jrcaddiusp\t\0" + /* 6726 */ "jraddiusp\t\0" + /* 6737 */ "swsp\t\0" + /* 6743 */ "extp\t\0" + /* 6749 */ "dvp\t\0" + /* 6754 */ "evp\t\0" + /* 6759 */ "lwp\t\0" + /* 6764 */ "swp\t\0" + /* 6769 */ "beq\t\0" + /* 6774 */ "seq\t\0" + /* 6779 */ "teq\t\0" + /* 6784 */ "dpau.h.qbr\t\0" + /* 6796 */ "dpsu.h.qbr\t\0" + /* 6808 */ "muleu_s.ph.qbr\t\0" + /* 6824 */ "preceu.ph.qbr\t\0" + /* 6839 */ "precequ.ph.qbr\t\0" + /* 6855 */ "ldr\t\0" + /* 6860 */ "sdr\t\0" + /* 6865 */ "maq_sa.w.phr\t\0" + /* 6879 */ "preceq.w.phr\t\0" + /* 6893 */ "maq_s.w.phr\t\0" + /* 6906 */ "muleq_s.w.phr\t\0" + /* 6921 */ "jr\t\0" + /* 6925 */ "jalr\t\0" + /* 6931 */ "nor\t\0" + /* 6936 */ "dror\t\0" + /* 6942 */ "xor\t\0" + /* 6947 */ "rdpgpr\t\0" + /* 6955 */ "wrpgpr\t\0" + /* 6963 */ "mftr\t\0" + /* 6969 */ "drotr\t\0" + /* 6976 */ "mttr\t\0" + /* 6982 */ "rdhwr\t\0" + /* 6989 */ "lwr\t\0" + /* 6994 */ "swr\t\0" + /* 6999 */ "mina.s\t\0" + /* 7007 */ "maxa.s\t\0" + /* 7015 */ "nmsub.s\t\0" + /* 7024 */ "cvt.d.s\t\0" + /* 7033 */ "nmadd.s\t\0" + /* 7042 */ "c.nge.s\t\0" + /* 7051 */ "c.le.s\t\0" + /* 7059 */ "cmp.le.s\t\0" + /* 7069 */ "c.ngle.s\t\0" + /* 7079 */ "c.ole.s\t\0" + /* 7088 */ "cmp.sle.s\t\0" + /* 7099 */ "c.ule.s\t\0" + /* 7108 */ "cmp.ule.s\t\0" + /* 7119 */ "cmp.sule.s\t\0" + /* 7131 */ "c.f.s\t\0" + /* 7138 */ "cmp.af.s\t\0" + /* 7148 */ "cmp.saf.s\t\0" + /* 7159 */ "msubf.s\t\0" + /* 7168 */ "maddf.s\t\0" + /* 7177 */ "c.sf.s\t\0" + /* 7185 */ "movf.s\t\0" + /* 7193 */ "neg.s\t\0" + /* 7200 */ "li.s\t\0" + /* 7206 */ "trunc.l.s\t\0" + /* 7217 */ "round.l.s\t\0" + /* 7228 */ "ceil.l.s\t\0" + /* 7238 */ "floor.l.s\t\0" + /* 7249 */ "cvt.l.s\t\0" + /* 7258 */ "sel.s\t\0" + /* 7265 */ "c.ngl.s\t\0" + /* 7274 */ "mul.s\t\0" + /* 7281 */ "min.s\t\0" + /* 7288 */ "c.un.s\t\0" + /* 7296 */ "cmp.un.s\t\0" + /* 7306 */ "cmp.sun.s\t\0" + /* 7317 */ "movn.s\t\0" + /* 7325 */ "recip.s\t\0" + /* 7334 */ "c.eq.s\t\0" + /* 7342 */ "cmp.eq.s\t\0" + /* 7352 */ "c.seq.s\t\0" + /* 7361 */ "cmp.seq.s\t\0" + /* 7372 */ "c.ueq.s\t\0" + /* 7381 */ "cmp.ueq.s\t\0" + /* 7392 */ "cmp.sueq.s\t\0" + /* 7404 */ "abs.s\t\0" + /* 7411 */ "cvt.ps.s\t\0" + /* 7421 */ "class.s\t\0" + /* 7430 */ "c.ngt.s\t\0" + /* 7439 */ "c.lt.s\t\0" + /* 7447 */ "cmp.lt.s\t\0" + /* 7457 */ "c.olt.s\t\0" + /* 7466 */ "cmp.slt.s\t\0" + /* 7477 */ "c.ult.s\t\0" + /* 7486 */ "cmp.ult.s\t\0" + /* 7497 */ "cmp.sult.s\t\0" + /* 7509 */ "rint.s\t\0" + /* 7517 */ "rsqrt.s\t\0" + /* 7526 */ "movt.s\t\0" + /* 7534 */ "div.s\t\0" + /* 7541 */ "mov.s\t\0" + /* 7548 */ "trunc.w.s\t\0" + /* 7559 */ "round.w.s\t\0" + /* 7570 */ "ceil.w.s\t\0" + /* 7580 */ "floor.w.s\t\0" + /* 7591 */ "cvt.w.s\t\0" + /* 7600 */ "max.s\t\0" + /* 7607 */ "selnez.s\t\0" + /* 7617 */ "seleqz.s\t\0" + /* 7627 */ "movz.s\t\0" + /* 7635 */ "abs\t\0" + /* 7640 */ "jals\t\0" + /* 7646 */ "bgezals\t\0" + /* 7655 */ "bltzals\t\0" + /* 7664 */ "cins\t\0" + /* 7670 */ "dins\t\0" + /* 7676 */ "sub.ps\t\0" + /* 7684 */ "add.ps\t\0" + /* 7692 */ "pll.ps\t\0" + /* 7700 */ "mul.ps\t\0" + /* 7708 */ "pul.ps\t\0" + /* 7716 */ "addr.ps\t\0" + /* 7725 */ "mulr.ps\t\0" + /* 7734 */ "plu.ps\t\0" + /* 7742 */ "puu.ps\t\0" + /* 7750 */ "cvt.pw.ps\t\0" + /* 7761 */ "jalrs\t\0" + /* 7768 */ "exts\t\0" + /* 7774 */ "lwxs\t\0" + /* 7780 */ "bc0t\t\0" + /* 7786 */ "bc1t\t\0" + /* 7792 */ "bc2t\t\0" + /* 7798 */ "bc3t\t\0" + /* 7804 */ "bgt\t\0" + /* 7809 */ "sgt\t\0" + /* 7814 */ "wait\t\0" + /* 7820 */ "blt\t\0" + /* 7825 */ "slt\t\0" + /* 7830 */ "tlt\t\0" + /* 7835 */ "dmult\t\0" + /* 7842 */ "dmt\t\0" + /* 7847 */ "emt\t\0" + /* 7852 */ "not\t\0" + /* 7857 */ "ginvt\t\0" + /* 7864 */ "movt\t\0" + /* 7870 */ "dext\t\0" + /* 7876 */ "lbu\t\0" + /* 7881 */ "dsubu\t\0" + /* 7888 */ "msubu\t\0" + /* 7895 */ "baddu\t\0" + /* 7902 */ "daddu\t\0" + /* 7909 */ "maddu\t\0" + /* 7916 */ "dmodu\t\0" + /* 7923 */ "bgeu\t\0" + /* 7929 */ "sgeu\t\0" + /* 7935 */ "tgeu\t\0" + /* 7941 */ "bleu\t\0" + /* 7947 */ "sleu\t\0" + /* 7953 */ "ulhu\t\0" + /* 7959 */ "dmuhu\t\0" + /* 7966 */ "daddiu\t\0" + /* 7974 */ "tgeiu\t\0" + /* 7981 */ "sltiu\t\0" + /* 7988 */ "tltiu\t\0" + /* 7995 */ "v3mulu\t\0" + /* 8003 */ "dmulu\t\0" + /* 8010 */ "vmulu\t\0" + /* 8017 */ "dremu\t\0" + /* 8024 */ "dmulou\t\0" + /* 8032 */ "cvt.s.pu\t\0" + /* 8042 */ "dinsu\t\0" + /* 8049 */ "bgtu\t\0" + /* 8055 */ "sgtu\t\0" + /* 8061 */ "bltu\t\0" + /* 8067 */ "sltu\t\0" + /* 8073 */ "tltu\t\0" + /* 8079 */ "dmultu\t\0" + /* 8087 */ "dextu\t\0" + /* 8094 */ "ddivu\t\0" + /* 8101 */ "lwu\t\0" + /* 8106 */ "and.v\t\0" + /* 8113 */ "move.v\t\0" + /* 8121 */ "bsel.v\t\0" + /* 8129 */ "nor.v\t\0" + /* 8136 */ "xor.v\t\0" + /* 8143 */ "bz.v\t\0" + /* 8149 */ "bmz.v\t\0" + /* 8156 */ "bnz.v\t\0" + /* 8163 */ "bmnz.v\t\0" + /* 8171 */ "dsrav\t\0" + /* 8178 */ "bitrev\t\0" + /* 8186 */ "ddiv\t\0" + /* 8192 */ "dsllv\t\0" + /* 8199 */ "dsrlv\t\0" + /* 8206 */ "shilov\t\0" + /* 8214 */ "extpdpv\t\0" + /* 8223 */ "extpv\t\0" + /* 8230 */ "drotrv\t\0" + /* 8238 */ "insv\t\0" + /* 8244 */ "flog2.w\t\0" + /* 8253 */ "fexp2.w\t\0" + /* 8262 */ "add_a.w\t\0" + /* 8271 */ "fmin_a.w\t\0" + /* 8281 */ "adds_a.w\t\0" + /* 8291 */ "fmax_a.w\t\0" + /* 8301 */ "sra.w\t\0" + /* 8308 */ "fsub.w\t\0" + /* 8316 */ "fmsub.w\t\0" + /* 8325 */ "nloc.w\t\0" + /* 8333 */ "nlzc.w\t\0" + /* 8341 */ "cvt.d.w\t\0" + /* 8350 */ "fadd.w\t\0" + /* 8358 */ "fmadd.w\t\0" + /* 8367 */ "sld.w\t\0" + /* 8374 */ "pckod.w\t\0" + /* 8383 */ "ilvod.w\t\0" + /* 8392 */ "fcle.w\t\0" + /* 8400 */ "fsle.w\t\0" + /* 8408 */ "fcule.w\t\0" + /* 8417 */ "fsule.w\t\0" + /* 8426 */ "fcne.w\t\0" + /* 8434 */ "fsne.w\t\0" + /* 8442 */ "fcune.w\t\0" + /* 8451 */ "fsune.w\t\0" + /* 8460 */ "insve.w\t\0" + /* 8469 */ "fcaf.w\t\0" + /* 8477 */ "fsaf.w\t\0" + /* 8485 */ "vshf.w\t\0" + /* 8493 */ "bneg.w\t\0" + /* 8501 */ "precr_sra.ph.w\t\0" + /* 8517 */ "precrq.ph.w\t\0" + /* 8530 */ "precr_sra_r.ph.w\t\0" + /* 8548 */ "precrq_rs.ph.w\t\0" + /* 8564 */ "subqh.w\t\0" + /* 8573 */ "addqh.w\t\0" + /* 8582 */ "srai.w\t\0" + /* 8590 */ "sldi.w\t\0" + /* 8598 */ "bnegi.w\t\0" + /* 8607 */ "slli.w\t\0" + /* 8615 */ "srli.w\t\0" + /* 8623 */ "binsli.w\t\0" + /* 8633 */ "ceqi.w\t\0" + /* 8641 */ "srari.w\t\0" + /* 8650 */ "bclri.w\t\0" + /* 8659 */ "srlri.w\t\0" + /* 8668 */ "binsri.w\t\0" + /* 8678 */ "splati.w\t\0" + /* 8688 */ "bseti.w\t\0" + /* 8697 */ "subvi.w\t\0" + /* 8706 */ "addvi.w\t\0" + /* 8715 */ "dpaq_sa.l.w\t\0" + /* 8728 */ "dpsq_sa.l.w\t\0" + /* 8741 */ "fill.w\t\0" + /* 8749 */ "sll.w\t\0" + /* 8756 */ "fexupl.w\t\0" + /* 8766 */ "ffql.w\t\0" + /* 8774 */ "srl.w\t\0" + /* 8781 */ "binsl.w\t\0" + /* 8790 */ "fmul.w\t\0" + /* 8798 */ "ilvl.w\t\0" + /* 8806 */ "fmin.w\t\0" + /* 8814 */ "fcun.w\t\0" + /* 8822 */ "fsun.w\t\0" + /* 8830 */ "fexdo.w\t\0" + /* 8839 */ "frcp.w\t\0" + /* 8847 */ "msub_q.w\t\0" + /* 8857 */ "madd_q.w\t\0" + /* 8867 */ "mul_q.w\t\0" + /* 8876 */ "msubr_q.w\t\0" + /* 8887 */ "maddr_q.w\t\0" + /* 8898 */ "mulr_q.w\t\0" + /* 8908 */ "fceq.w\t\0" + /* 8916 */ "fseq.w\t\0" + /* 8924 */ "fcueq.w\t\0" + /* 8933 */ "fsueq.w\t\0" + /* 8942 */ "ftq.w\t\0" + /* 8949 */ "shra_r.w\t\0" + /* 8959 */ "subqh_r.w\t\0" + /* 8970 */ "addqh_r.w\t\0" + /* 8981 */ "extr_r.w\t\0" + /* 8991 */ "shrav_r.w\t\0" + /* 9002 */ "extrv_r.w\t\0" + /* 9013 */ "srar.w\t\0" + /* 9021 */ "bclr.w\t\0" + /* 9029 */ "srlr.w\t\0" + /* 9037 */ "fcor.w\t\0" + /* 9045 */ "fsor.w\t\0" + /* 9053 */ "fexupr.w\t\0" + /* 9063 */ "ffqr.w\t\0" + /* 9071 */ "binsr.w\t\0" + /* 9080 */ "extr.w\t\0" + /* 9088 */ "ilvr.w\t\0" + /* 9096 */ "cvt.s.w\t\0" + /* 9105 */ "asub_s.w\t\0" + /* 9115 */ "hsub_s.w\t\0" + /* 9125 */ "dpsub_s.w\t\0" + /* 9136 */ "ftrunc_s.w\t\0" + /* 9148 */ "hadd_s.w\t\0" + /* 9158 */ "dpadd_s.w\t\0" + /* 9169 */ "mod_s.w\t\0" + /* 9178 */ "cle_s.w\t\0" + /* 9187 */ "ave_s.w\t\0" + /* 9196 */ "clei_s.w\t\0" + /* 9206 */ "mini_s.w\t\0" + /* 9216 */ "clti_s.w\t\0" + /* 9226 */ "maxi_s.w\t\0" + /* 9236 */ "shll_s.w\t\0" + /* 9246 */ "min_s.w\t\0" + /* 9255 */ "dotp_s.w\t\0" + /* 9265 */ "subq_s.w\t\0" + /* 9275 */ "addq_s.w\t\0" + /* 9285 */ "mulq_s.w\t\0" + /* 9295 */ "absq_s.w\t\0" + /* 9305 */ "aver_s.w\t\0" + /* 9315 */ "subs_s.w\t\0" + /* 9325 */ "adds_s.w\t\0" + /* 9335 */ "sat_s.w\t\0" + /* 9344 */ "clt_s.w\t\0" + /* 9353 */ "ffint_s.w\t\0" + /* 9364 */ "ftint_s.w\t\0" + /* 9375 */ "subsuu_s.w\t\0" + /* 9387 */ "div_s.w\t\0" + /* 9396 */ "shllv_s.w\t\0" + /* 9407 */ "max_s.w\t\0" + /* 9416 */ "copy_s.w\t\0" + /* 9426 */ "mulq_rs.w\t\0" + /* 9437 */ "extr_rs.w\t\0" + /* 9448 */ "extrv_rs.w\t\0" + /* 9460 */ "fclass.w\t\0" + /* 9470 */ "splat.w\t\0" + /* 9479 */ "bset.w\t\0" + /* 9487 */ "fclt.w\t\0" + /* 9495 */ "fslt.w\t\0" + /* 9503 */ "fcult.w\t\0" + /* 9512 */ "fsult.w\t\0" + /* 9521 */ "pcnt.w\t\0" + /* 9529 */ "frint.w\t\0" + /* 9538 */ "insert.w\t\0" + /* 9548 */ "fsqrt.w\t\0" + /* 9557 */ "frsqrt.w\t\0" + /* 9567 */ "st.w\t\0" + /* 9573 */ "asub_u.w\t\0" + /* 9583 */ "hsub_u.w\t\0" + /* 9593 */ "dpsub_u.w\t\0" + /* 9604 */ "ftrunc_u.w\t\0" + /* 9616 */ "hadd_u.w\t\0" + /* 9626 */ "dpadd_u.w\t\0" + /* 9637 */ "mod_u.w\t\0" + /* 9646 */ "cle_u.w\t\0" + /* 9655 */ "ave_u.w\t\0" + /* 9664 */ "clei_u.w\t\0" + /* 9674 */ "mini_u.w\t\0" + /* 9684 */ "clti_u.w\t\0" + /* 9694 */ "maxi_u.w\t\0" + /* 9704 */ "min_u.w\t\0" + /* 9713 */ "dotp_u.w\t\0" + /* 9723 */ "aver_u.w\t\0" + /* 9733 */ "subs_u.w\t\0" + /* 9743 */ "adds_u.w\t\0" + /* 9753 */ "subsus_u.w\t\0" + /* 9765 */ "sat_u.w\t\0" + /* 9774 */ "clt_u.w\t\0" + /* 9783 */ "ffint_u.w\t\0" + /* 9794 */ "ftint_u.w\t\0" + /* 9805 */ "div_u.w\t\0" + /* 9814 */ "max_u.w\t\0" + /* 9823 */ "copy_u.w\t\0" + /* 9833 */ "msubv.w\t\0" + /* 9842 */ "maddv.w\t\0" + /* 9851 */ "pckev.w\t\0" + /* 9860 */ "ilvev.w\t\0" + /* 9869 */ "fdiv.w\t\0" + /* 9877 */ "mulv.w\t\0" + /* 9885 */ "extrv.w\t\0" + /* 9894 */ "fmax.w\t\0" + /* 9902 */ "bz.w\t\0" + /* 9908 */ "bnz.w\t\0" + /* 9915 */ "crc32w\t\0" + /* 9923 */ "crc32cw\t\0" + /* 9932 */ "ulw\t\0" + /* 9937 */ "cvt.ps.pw\t\0" + /* 9948 */ "usw\t\0" + /* 9953 */ "prefx\t\0" + /* 9960 */ "lhx\t\0" + /* 9965 */ "jalx\t\0" + /* 9971 */ "lbux\t\0" + /* 9977 */ "lwx\t\0" + /* 9982 */ "bgez\t\0" + /* 9988 */ "blez\t\0" + /* 9994 */ "bnez\t\0" + /* 10000 */ "selnez\t\0" + /* 10008 */ "btnez\t\0" + /* 10015 */ "dclz\t\0" + /* 10021 */ "beqz\t\0" + /* 10027 */ "seleqz\t\0" + /* 10035 */ "bteqz\t\0" + /* 10042 */ "bgtz\t\0" + /* 10048 */ "bltz\t\0" + /* 10054 */ "movz\t\0" + /* 10060 */ "seb\t \0" + /* 10066 */ "seh\t \0" + /* 10072 */ "ddivu\t$zero, \0" + /* 10086 */ "ddiv\t$zero, \0" + /* 10099 */ "addiu\t$sp, \0" + /* 10111 */ "mftc0 \0" + /* 10118 */ "mttc0 \0" + /* 10125 */ "mfthc1 \0" + /* 10133 */ "mtthc1 \0" + /* 10141 */ "cftc1 \0" + /* 10148 */ "mftc1 \0" + /* 10155 */ "cttc1 \0" + /* 10162 */ "mttc1 \0" + /* 10169 */ "sync \0" + /* 10175 */ "ld \0" + /* 10179 */ "\t.word \0" + /* 10187 */ "sd \0" + /* 10191 */ "sne \0" + /* 10196 */ "mfthi \0" + /* 10203 */ "mtthi \0" + /* 10210 */ "mftlo \0" + /* 10217 */ "mttlo \0" + /* 10224 */ "mftdsp \0" + /* 10232 */ "mttdsp \0" + /* 10240 */ "seq \0" + /* 10245 */ "mftgpr \0" + /* 10253 */ "mttgpr \0" + /* 10261 */ "dext \0" + /* 10267 */ "mftacx \0" + /* 10275 */ "mttacx \0" + /* 10283 */ "bc1nez \0" + /* 10291 */ "bc2nez \0" + /* 10299 */ "bc1eqz \0" + /* 10307 */ "bc2eqz \0" + /* 10315 */ "# XRay Function Patchable RET.\0" + /* 10346 */ "c.\0" + /* 10349 */ "# XRay Typed Event Log.\0" + /* 10373 */ "# XRay Custom Event Log.\0" + /* 10398 */ "# XRay Function Enter.\0" + /* 10421 */ "# XRay Tail Call Exit.\0" + /* 10444 */ "# XRay Function Exit.\0" + /* 10466 */ "break 0\0" + /* 10474 */ "LIFETIME_END\0" + /* 10487 */ "PSEUDO_PROBE\0" + /* 10500 */ "BUNDLE\0" + /* 10507 */ "DBG_VALUE\0" + /* 10517 */ "DBG_INSTR_REF\0" + /* 10531 */ "DBG_PHI\0" + /* 10539 */ "DBG_LABEL\0" + /* 10549 */ "LIFETIME_START\0" + /* 10564 */ "DBG_VALUE_LIST\0" + /* 10579 */ "jrc\t$ra\0" + /* 10587 */ "jr\t$ra\0" + /* 10594 */ "ehb\0" + /* 10598 */ "eretnc\0" + /* 10605 */ "pause\0" + /* 10611 */ "tlbinvf\0" + /* 10619 */ "tlbginvf\0" + /* 10628 */ "tlbwi\0" + /* 10634 */ "tlbgwi\0" + /* 10641 */ "# FEntry call\0" + /* 10655 */ "foo\0" + /* 10659 */ "tlbp\0" + /* 10664 */ "tlbgp\0" + /* 10670 */ "ssnop\0" + /* 10676 */ "tlbr\0" + /* 10681 */ "tlbgr\0" + /* 10687 */ "tlbwr\0" + /* 10693 */ "tlbgwr\0" + /* 10700 */ "deret\0" + /* 10706 */ "wait\0" + /* 10711 */ "tlbinv\0" + /* 10718 */ "tlbginv\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 10508U, // DBG_VALUE + 10565U, // DBG_VALUE_LIST + 10518U, // DBG_INSTR_REF + 10532U, // DBG_PHI + 10540U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 10501U, // BUNDLE + 10550U, // LIFETIME_START + 10475U, // LIFETIME_END + 10488U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 10642U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 10399U, // PATCHABLE_FUNCTION_ENTER + 10316U, // PATCHABLE_RET + 10445U, // PATCHABLE_FUNCTION_EXIT + 10422U, // PATCHABLE_TAIL_CALL + 10374U, // PATCHABLE_EVENT_CALL + 10350U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 24020U, // ABSMacro + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // AND_V_D_PSEUDO + 0U, // AND_V_H_PSEUDO + 0U, // AND_V_W_PSEUDO + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I16_POSTRA + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I32_POSTRA + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I64_POSTRA + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_CMP_SWAP_I8_POSTRA + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I16_POSTRA + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I32_POSTRA + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I64_POSTRA + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_ADD_I8_POSTRA + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I16_POSTRA + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I32_POSTRA + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I64_POSTRA + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_AND_I8_POSTRA + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I16_POSTRA + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I32_POSTRA + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I64_POSTRA + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MAX_I8_POSTRA + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I16_POSTRA + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I32_POSTRA + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I64_POSTRA + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_MIN_I8_POSTRA + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I16_POSTRA + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I32_POSTRA + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I64_POSTRA + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_NAND_I8_POSTRA + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I16_POSTRA + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I32_POSTRA + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I64_POSTRA + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_OR_I8_POSTRA + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I16_POSTRA + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I32_POSTRA + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I64_POSTRA + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_SUB_I8_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I16_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I32_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I64_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMAX_I8_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I16_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I32_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I64_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_UMIN_I8_POSTRA + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I16_POSTRA + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I32_POSTRA + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I64_POSTRA + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_LOAD_XOR_I8_POSTRA + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I16_POSTRA + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I32_POSTRA + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I64_POSTRA + 0U, // ATOMIC_SWAP_I8 + 0U, // ATOMIC_SWAP_I8_POSTRA + 0U, // B + 0U, // BAL_BR + 0U, // BAL_BR_MM + 268458245U, // BEQLImmMacro + 268456065U, // BGE + 268456065U, // BGEImmMacro + 268458092U, // BGEL + 268458092U, // BGELImmMacro + 268459764U, // BGEU + 268459764U, // BGEUImmMacro + 268458290U, // BGEUL + 268458290U, // BGEULImmMacro + 268459645U, // BGT + 268459645U, // BGTImmMacro + 268458278U, // BGTL + 268458278U, // BGTLImmMacro + 268459890U, // BGTU + 268459890U, // BGTUImmMacro + 268458310U, // BGTUL + 268458310U, // BGTULImmMacro + 268456105U, // BLE + 268456105U, // BLEImmMacro + 268458098U, // BLEL + 268458098U, // BLELImmMacro + 268459782U, // BLEU + 268459782U, // BLEUImmMacro + 268458297U, // BLEUL + 268458297U, // BLEULImmMacro + 268459661U, // BLT + 268459661U, // BLTImmMacro + 268458284U, // BLTL + 268458284U, // BLTLImmMacro + 268459902U, // BLTU + 268459902U, // BLTUImmMacro + 268458317U, // BLTUL + 268458317U, // BLTULImmMacro + 268458104U, // BNELImmMacro + 0U, // BPOSGE32_PSEUDO + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 0U, // BSEL_W_PSEUDO + 0U, // B_MM + 279279U, // B_MMR6_Pseudo + 279279U, // B_MM_Pseudo + 268458610U, // BeqImm + 268456132U, // BneImm + 536893942U, // BteqzT8CmpX16 + 536893347U, // BteqzT8CmpiX16 + 536895122U, // BteqzT8SltX16 + 536893377U, // BteqzT8SltiX16 + 536895278U, // BteqzT8SltiuX16 + 536895364U, // BteqzT8SltuX16 + 805329398U, // BtnezT8CmpX16 + 805328803U, // BtnezT8CmpiX16 + 805330578U, // BtnezT8SltX16 + 805328833U, // BtnezT8SltiX16 + 805330734U, // BtnezT8SltiuX16 + 805330820U, // BtnezT8SltuX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 26526U, // CFTC1 + 10656U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 8955820U, // CTTC1 + 288708U, // Constant32 + 268458304U, // DMULImmMacro + 268458304U, // DMULMacro + 268458439U, // DMULOMacro + 268459865U, // DMULOUMacro + 268458229U, // DROL + 268458229U, // DROLImm + 268458777U, // DROR + 268458777U, // DRORImm + 268460027U, // DSDivIMacro + 268460027U, // DSDivMacro + 268458362U, // DSRemIMacro + 268458362U, // DSRemMacro + 268459935U, // DUDivIMacro + 268459935U, // DUDivMacro + 268459858U, // DURemIMacro + 268459858U, // DURemMacro + 0U, // ERet + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 0U, // FABS_W + 0U, // FEXP2_D_1_PSEUDO + 0U, // FEXP2_W_1_PSEUDO + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 1090541466U, // GotPrologue16 + 0U, // INSERT_B_VIDX64_PSEUDO + 0U, // INSERT_B_VIDX_PSEUDO + 0U, // INSERT_D_VIDX64_PSEUDO + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX64_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX64_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 0U, // INSERT_H_VIDX64_PSEUDO + 0U, // INSERT_H_VIDX_PSEUDO + 0U, // INSERT_W_VIDX64_PSEUDO + 0U, // INSERT_W_VIDX_PSEUDO + 0U, // JALR64Pseudo + 0U, // JALRHB64Pseudo + 0U, // JALRHBPseudo + 0U, // JALRPseudo + 0U, // JAL_MMR6 + 284678U, // JalOneReg + 22534U, // JalTwoReg + 25192384U, // LDMacro + 0U, // LDR_D + 0U, // LDR_W + 0U, // LD_F16 + 25182214U, // LOAD_ACC128 + 25182214U, // LOAD_ACC64 + 25182214U, // LOAD_ACC64DSP + 25188876U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_ADDiu2Op + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_DADDiu2Op + 0U, // LONG_BRANCH_LUi + 0U, // LONG_BRANCH_LUi2Op + 0U, // LONG_BRANCH_LUi2Op_64 + 55694U, // LWM_MM + 17042U, // LoadAddrImm32 + 17063U, // LoadAddrImm64 + 25182866U, // LoadAddrReg32 + 25182887U, // LoadAddrReg64 + 22426U, // LoadImm32 + 22430U, // LoadImm64 + 19107U, // LoadImmDoubleFGR + 19107U, // LoadImmDoubleFGR_32 + 19107U, // LoadImmDoubleGPR + 23585U, // LoadImmSingleFGR + 23585U, // LoadImmSingleGPR + 812750U, // LwConstant32 + 26652U, // MFTACX + 268461952U, // MFTC0 + 26533U, // MFTC1 + 288753U, // MFTDSP + 26630U, // MFTGPR + 26510U, // MFTHC1 + 26581U, // MFTHI + 26595U, // MFTLO + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 0U, // MSA_FP_EXTEND_D_PSEUDO + 0U, // MSA_FP_EXTEND_W_PSEUDO + 0U, // MSA_FP_ROUND_D_PSEUDO + 0U, // MSA_FP_ROUND_W_PSEUDO + 8955940U, // MTTACX + 1376298887U, // MTTC0 + 8955827U, // MTTC1 + 288761U, // MTTDSP + 8955918U, // MTTGPR + 8955798U, // MTTHC1 + 8955868U, // MTTHI + 8955882U, // MTTLO + 268458305U, // MULImmMacro + 268458440U, // MULOMacro + 268459866U, // MULOUMacro + 24221U, // MultRxRy16 + 43032221U, // MultRxRyRz16 + 24465U, // MultuRxRy16 + 43032465U, // MultuRxRyRz16 + 0U, // NOP + 268458772U, // NORImm + 268458772U, // NORImm64 + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 16390U, // PseudoCVT_D32_W + 16390U, // PseudoCVT_D64_L + 16390U, // PseudoCVT_D64_W + 16390U, // PseudoCVT_S_L + 16390U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoD_SELECT_I + 0U, // PseudoD_SELECT_I64 + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoIndirectBranch64R6 + 0U, // PseudoIndirectBranchR6 + 0U, // PseudoIndirectBranch_MM + 0U, // PseudoIndirectBranch_MMR6 + 0U, // PseudoIndirectHazardBranch + 0U, // PseudoIndirectHazardBranch64 + 0U, // PseudoIndrectHazardBranch64R6 + 0U, // PseudoIndrectHazardBranchR6 + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMADDU_MM + 0U, // PseudoMADD_MM + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFHI_MM + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMFLO_MM + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMSUBU_MM + 0U, // PseudoMSUB_MM + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMTLOHI_MM + 0U, // PseudoMULT + 0U, // PseudoMULT_MM + 0U, // PseudoMULTu + 0U, // PseudoMULTu_MM + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 268455844U, // PseudoTRUNC_W_D + 268455844U, // PseudoTRUNC_W_D32 + 268459389U, // PseudoTRUNC_W_S + 0U, // PseudoUDIV + 268458230U, // ROL + 268458230U, // ROLImm + 268458778U, // ROR + 268458778U, // RORImm + 0U, // RetRA + 0U, // RetRA16 + 25185431U, // SDC1_M1 + 0U, // SDIV_MM_Pseudo + 25192396U, // SDMacro + 268460028U, // SDivIMacro + 268460028U, // SDivMacro + 268462081U, // SEQIMacro + 268462081U, // SEQMacro + 268456070U, // SGE + 268456070U, // SGEImm + 268456070U, // SGEImm64 + 268459770U, // SGEU + 268459770U, // SGEUImm + 268459770U, // SGEUImm64 + 268459650U, // SGTImm + 268459650U, // SGTImm64 + 268459896U, // SGTUImm + 268459896U, // SGTUImm64 + 268456115U, // SLE + 268456115U, // SLEImm + 268456115U, // SLEImm64 + 268459788U, // SLEU + 268459788U, // SLEUImm + 268459788U, // SLEUImm64 + 268459666U, // SLTImm64 + 268459908U, // SLTUImm64 + 268462032U, // SNEIMacro + 268462032U, // SNEMacro + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 268458363U, // SRemIMacro + 268458363U, // SRemMacro + 25182214U, // STORE_ACC128 + 25182214U, // STORE_ACC64 + 25182214U, // STORE_ACC64DSP + 25188892U, // STORE_CCOND_DSP + 0U, // STR_D + 0U, // STR_W + 0U, // ST_F16 + 55699U, // SWM_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 25182849U, // SaaAddr + 25186321U, // SaadAddr + 1386278U, // SelBeqZ + 1386251U, // SelBneZ + 1661016566U, // SelTBteqZCmp + 1661015971U, // SelTBteqZCmpi + 1661017746U, // SelTBteqZSlt + 1661016001U, // SelTBteqZSlti + 1661017902U, // SelTBteqZSltiu + 1661017988U, // SelTBteqZSltu + 1929452022U, // SelTBtneZCmp + 1929451427U, // SelTBtneZCmpi + 1929453202U, // SelTBtneZSlt + 1929451457U, // SelTBtneZSlti + 1929453358U, // SelTBtneZSltiu + 1929453444U, // SelTBtneZSltu + 59809426U, // SltCCRxRy16 + 59807681U, // SltiCCRxImmX16 + 59809582U, // SltiuCCRxImmX16 + 59809668U, // SltuCCRxRy16 + 59809668U, // SltuRxRyRz16 + 0U, // TAILCALL + 0U, // TAILCALL64R6REG + 0U, // TAILCALLHB64R6REG + 0U, // TAILCALLHBR6REG + 0U, // TAILCALLR6REG + 0U, // TAILCALLREG + 0U, // TAILCALLREG64 + 0U, // TAILCALLREGHB + 0U, // TAILCALLREGHB64 + 0U, // TAILCALLREG_MM + 0U, // TAILCALLREG_MMR6 + 0U, // TAILCALL_MM + 0U, // TAILCALL_MMR6 + 0U, // TRAP + 0U, // TRAP_MM + 0U, // UDIV_MM_Pseudo + 268459936U, // UDivIMacro + 268459936U, // UDivMacro + 268459859U, // URemIMacro + 268459859U, // URemMacro + 25187620U, // Ulh + 25190162U, // Ulhu + 25192141U, // Ulw + 25188173U, // Ush + 25192157U, // Usw + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 22070U, // ABSQ_S_PH + 22070U, // ABSQ_S_PH_MM + 18197U, // ABSQ_S_QB + 18197U, // ABSQ_S_QB_MMR2 + 25680U, // ABSQ_S_W + 25680U, // ABSQ_S_W_MM + 268455974U, // ADD + 18483U, // ADDIUPC + 18483U, // ADDIUPC_MM + 18483U, // ADDIUPC_MMR6 + 23041U, // ADDIUR1SP_MM + 268452218U, // ADDIUR2_MM + 9470363U, // ADDIUS5_MM + 285246U, // ADDIUSP_MM + 268459808U, // ADDIU_MMR6 + 268457331U, // ADDQH_PH + 268457331U, // ADDQH_PH_MMR2 + 268457448U, // ADDQH_R_PH + 268457448U, // ADDQH_R_PH_MMR2 + 268460811U, // ADDQH_R_W + 268460811U, // ADDQH_R_W_MMR2 + 268460414U, // ADDQH_W + 268460414U, // ADDQH_W_MMR2 + 268457405U, // ADDQ_PH + 268457405U, // ADDQ_PH_MM + 268457504U, // ADDQ_S_PH + 268457504U, // ADDQ_S_PH_MM + 268461116U, // ADDQ_S_W + 268461116U, // ADDQ_S_W_MM + 268459557U, // ADDR_PS64 + 268453979U, // ADDSC + 268453979U, // ADDSC_MM + 268452603U, // ADDS_A_B + 268454140U, // ADDS_A_D + 268456258U, // ADDS_A_H + 268460122U, // ADDS_A_W + 268453071U, // ADDS_S_B + 268455238U, // ADDS_S_D + 268456815U, // ADDS_S_H + 268461166U, // ADDS_S_W + 268453286U, // ADDS_U_B + 268455705U, // ADDS_U_D + 268457093U, // ADDS_U_H + 268461584U, // ADDS_U_W + 268452438U, // ADDU16_MM + 268452438U, // ADDU16_MMR6 + 268453521U, // ADDUH_QB + 268453521U, // ADDUH_QB_MMR2 + 268453629U, // ADDUH_R_QB + 268453629U, // ADDUH_R_QB_MMR2 + 268459737U, // ADDU_MMR6 + 268457603U, // ADDU_PH + 268457603U, // ADDU_PH_MMR2 + 268453734U, // ADDU_QB + 268453734U, // ADDU_QB_MM + 268457548U, // ADDU_S_PH + 268457548U, // ADDU_S_PH_MMR2 + 268453675U, // ADDU_S_QB + 268453675U, // ADDU_S_QB_MM + 268452852U, // ADDVI_B + 268454660U, // ADDVI_D + 268456474U, // ADDVI_H + 268460547U, // ADDVI_W + 268453364U, // ADDV_B + 268455795U, // ADDV_D + 268457171U, // ADDV_H + 268461684U, // ADDV_W + 268454018U, // ADDWC + 268454018U, // ADDWC_MM + 268452585U, // ADD_A_B + 268454121U, // ADD_A_D + 268456240U, // ADD_A_H + 268460103U, // ADD_A_W + 268455974U, // ADD_MM + 268455974U, // ADD_MMR6 + 268457824U, // ADDi + 268457824U, // ADDi_MM + 268459808U, // ADDiu + 268459808U, // ADDiu_MM + 268459737U, // ADDu + 268459737U, // ADDu_MM + 268458393U, // ALIGN + 268458393U, // ALIGN_MMR6 + 18475U, // ALUIPC + 18475U, // ALUIPC_MMR6 + 268456003U, // AND + 10043849U, // AND16_MM + 10043849U, // AND16_MMR6 + 268456003U, // AND64 + 268452318U, // ANDI16_MM + 268452318U, // ANDI16_MMR6 + 268452711U, // ANDI_B + 268457830U, // ANDI_MMR6 + 268456003U, // AND_MM + 268456003U, // AND_MMR6 + 268459947U, // AND_V + 268457830U, // ANDi + 268457830U, // ANDi64 + 268457830U, // ANDi_MM + 268456017U, // APPEND + 268456017U, // APPEND_MMR2 + 268452965U, // ASUB_S_B + 268455068U, // ASUB_S_D + 268456647U, // ASUB_S_H + 268460946U, // ASUB_S_W + 268453180U, // ASUB_U_B + 268455535U, // ASUB_U_D + 268456935U, // ASUB_U_H + 268461414U, // ASUB_U_W + 268457934U, // AUI + 18468U, // AUIPC + 18468U, // AUIPC_MMR6 + 268457934U, // AUI_MMR6 + 268453051U, // AVER_S_B + 268455218U, // AVER_S_D + 268456785U, // AVER_S_H + 268461146U, // AVER_S_W + 268453266U, // AVER_U_B + 268455685U, // AVER_U_D + 268457073U, // AVER_U_H + 268461564U, // AVER_U_W + 268452993U, // AVE_S_B + 268455150U, // AVE_S_D + 268456717U, // AVE_S_H + 268461028U, // AVE_S_W + 268453208U, // AVE_U_B + 268455617U, // AVE_U_D + 268457005U, // AVE_U_H + 268461496U, // AVE_U_W + 24352U, // AddiuRxImmX16 + 1859360U, // AddiuRxPcImmX16 + 2164285216U, // AddiuRxRxImm16 + 16801568U, // AddiuRxRxImmX16 + 67133216U, // AddiuRxRyOffMemX16 + 2123636U, // AddiuSpImm16 + 288628U, // AddiuSpImmX16 + 268459737U, // AdduRxRyRz16 + 16797763U, // AndRxRxRy16 + 278949U, // B16_MM + 268459736U, // BADDu + 284673U, // BAL + 280533U, // BALC + 280533U, // BALC_MMR6 + 268458392U, // BALIGN + 268458392U, // BALIGN_MMR2 + 75513935U, // BBIT0 + 75514067U, // BBIT032 + 75514060U, // BBIT1 + 75514076U, // BBIT132 + 280512U, // BC + 282887U, // BC0F + 286309U, // BC0T + 278954U, // BC16_MMR6 + 26684U, // BC1EQZ + 18608U, // BC1EQZC_MMR6 + 20749U, // BC1F + 22654U, // BC1FL + 20749U, // BC1F_MM + 26668U, // BC1NEZ + 18583U, // BC1NEZC_MMR6 + 24171U, // BC1T + 22801U, // BC1TL + 24171U, // BC1T_MM + 26692U, // BC2EQZ + 18617U, // BC2EQZC_MMR6 + 20755U, // BC2F + 22661U, // BC2FL + 26676U, // BC2NEZ + 18592U, // BC2NEZC_MMR6 + 24177U, // BC2T + 22808U, // BC2TL + 20761U, // BC3F + 22668U, // BC3FL + 24183U, // BC3T + 22815U, // BC3TL + 268452780U, // BCLRI_B + 268454604U, // BCLRI_D + 268456418U, // BCLRI_H + 268460491U, // BCLRI_W + 268452932U, // BCLR_B + 268454992U, // BCLR_D + 268456614U, // BCLR_H + 268460862U, // BCLR_W + 280512U, // BC_MMR6 + 268458610U, // BEQ + 268458610U, // BEQ64 + 268453961U, // BEQC + 268453961U, // BEQC64 + 268453961U, // BEQC_MMR6 + 268458245U, // BEQL + 17017U, // BEQZ16_MM + 18429U, // BEQZALC + 18429U, // BEQZALC_MMR6 + 18626U, // BEQZC + 16832U, // BEQZC16_MMR6 + 18626U, // BEQZC64 + 18626U, // BEQZC_MM + 18626U, // BEQZC_MMR6 + 268458610U, // BEQ_MM + 268453828U, // BGEC + 268453828U, // BGEC64 + 268453828U, // BGEC_MMR6 + 268453992U, // BGEUC + 268453992U, // BGEUC64 + 268453992U, // BGEUC_MMR6 + 26367U, // BGEZ + 26367U, // BGEZ64 + 22539U, // BGEZAL + 18402U, // BGEZALC + 18402U, // BGEZALC_MMR6 + 22749U, // BGEZALL + 24031U, // BGEZALS_MM + 22539U, // BGEZAL_MM + 18569U, // BGEZC + 18569U, // BGEZC64 + 18569U, // BGEZC_MMR6 + 22878U, // BGEZL + 26367U, // BGEZ_MM + 26427U, // BGTZ + 26427U, // BGTZ64 + 18438U, // BGTZALC + 18438U, // BGTZALC_MMR6 + 18633U, // BGTZC + 18633U, // BGTZC64 + 18633U, // BGTZC_MMR6 + 22892U, // BGTZL + 26427U, // BGTZ_MM + 285229969U, // BINSLI_B + 285231793U, // BINSLI_D + 285233607U, // BINSLI_H + 285237680U, // BINSLI_W + 285230116U, // BINSL_B + 285231993U, // BINSL_D + 285233721U, // BINSL_H + 285237838U, // BINSL_W + 285230030U, // BINSRI_B + 285231838U, // BINSRI_D + 285233652U, // BINSRI_H + 285237725U, // BINSRI_W + 285230164U, // BINSR_B + 285232258U, // BINSR_D + 285233846U, // BINSR_H + 285238128U, // BINSR_W + 24563U, // BITREV + 24563U, // BITREV_MM + 22991U, // BITSWAP + 22991U, // BITSWAP_MMR6 + 26373U, // BLEZ + 26373U, // BLEZ64 + 18411U, // BLEZALC + 18411U, // BLEZALC_MMR6 + 18576U, // BLEZC + 18576U, // BLEZC64 + 18576U, // BLEZC_MMR6 + 22885U, // BLEZL + 26373U, // BLEZ_MM + 268453986U, // BLTC + 268453986U, // BLTC64 + 268453986U, // BLTC_MMR6 + 268453999U, // BLTUC + 268453999U, // BLTUC64 + 268453999U, // BLTUC_MMR6 + 26433U, // BLTZ + 26433U, // BLTZ64 + 22547U, // BLTZAL + 18447U, // BLTZALC + 18447U, // BLTZALC_MMR6 + 22758U, // BLTZALL + 24040U, // BLTZALS_MM + 22547U, // BLTZAL_MM + 18640U, // BLTZC + 18640U, // BLTZC64 + 18640U, // BLTZC_MMR6 + 22899U, // BLTZL + 26433U, // BLTZ_MM + 285230085U, // BMNZI_B + 285237220U, // BMNZ_V + 285230077U, // BMZI_B + 285237206U, // BMZ_V + 268456132U, // BNE + 268456132U, // BNE64 + 268453834U, // BNEC + 268453834U, // BNEC64 + 268453834U, // BNEC_MMR6 + 268452719U, // BNEGI_B + 268454552U, // BNEGI_D + 268456366U, // BNEGI_H + 268460439U, // BNEGI_W + 268452687U, // BNEG_B + 268454528U, // BNEG_D + 268456342U, // BNEG_H + 268460334U, // BNEG_W + 268458104U, // BNEL + 17009U, // BNEZ16_MM + 18420U, // BNEZALC + 18420U, // BNEZALC_MMR6 + 18601U, // BNEZC + 16823U, // BNEZC16_MMR6 + 18601U, // BNEZC64 + 18601U, // BNEZC_MM + 18601U, // BNEZC_MMR6 + 268456132U, // BNE_MM + 268454006U, // BNVC + 268454006U, // BNVC_MMR6 + 17948U, // BNZ_B + 20464U, // BNZ_D + 21755U, // BNZ_H + 24541U, // BNZ_V + 26293U, // BNZ_W + 268454012U, // BOVC + 268454012U, // BOVC_MMR6 + 278765U, // BPOSGE32 + 280501U, // BPOSGE32C_MMR3 + 278765U, // BPOSGE32_MM + 83990498U, // BREAK + 115188U, // BREAK16_MM + 115188U, // BREAK16_MMR6 + 83990498U, // BREAK_MM + 83990498U, // BREAK_MMR6 + 285229944U, // BSELI_B + 285237178U, // BSEL_V + 268452834U, // BSETI_B + 268454642U, // BSETI_D + 268456456U, // BSETI_H + 268460529U, // BSETI_W + 268453148U, // BSET_B + 268455354U, // BSET_D + 268456903U, // BSET_H + 268461320U, // BSET_W + 17942U, // BZ_B + 20448U, // BZ_D + 21749U, // BZ_H + 24528U, // BZ_V + 26287U, // BZ_W + 2415945510U, // BeqzRxImm16 + 26406U, // BeqzRxImmX16 + 2114287U, // Bimm16 + 279279U, // BimmX16 + 2415945483U, // BnezRxImm16 + 26379U, // BnezRxImmX16 + 10467U, // Break16 + 2385716U, // Bteqz16 + 288564U, // BteqzX16 + 2385689U, // Btnez16 + 288537U, // BtnezX16 + 2756752U, // CACHE + 2756722U, // CACHEE + 2756722U, // CACHEE_MM + 2756752U, // CACHE_MM + 2756752U, // CACHE_MMR6 + 2756752U, // CACHE_R6 + 19235U, // CEIL_L_D64 + 19235U, // CEIL_L_D_MMR6 + 23613U, // CEIL_L_S + 23613U, // CEIL_L_S_MMR6 + 20410U, // CEIL_W_D32 + 20410U, // CEIL_W_D64 + 20410U, // CEIL_W_D_MMR6 + 20410U, // CEIL_W_MM + 23955U, // CEIL_W_S + 23955U, // CEIL_W_S_MM + 23955U, // CEIL_W_S_MMR6 + 268452763U, // CEQI_B + 268454587U, // CEQI_D + 268456401U, // CEQI_H + 268460474U, // CEQI_W + 268452917U, // CEQ_B + 268454899U, // CEQ_D + 268456592U, // CEQ_H + 268460750U, // CEQ_W + 16482U, // CFC1 + 16482U, // CFC1_MM + 16698U, // CFC2_MM + 17113U, // CFCMSA + 268459505U, // CINS + 268452126U, // CINS32 + 268459505U, // CINS64_32 + 268459505U, // CINS_i32 + 19880U, // CLASS_D + 19880U, // CLASS_D_MMR6 + 23806U, // CLASS_S + 23806U, // CLASS_S_MMR6 + 268453002U, // CLEI_S_B + 268455159U, // CLEI_S_D + 268456726U, // CLEI_S_H + 268461037U, // CLEI_S_W + 268453217U, // CLEI_U_B + 268455626U, // CLEI_U_D + 268457014U, // CLEI_U_H + 268461505U, // CLEI_U_W + 268452984U, // CLE_S_B + 268455141U, // CLE_S_D + 268456708U, // CLE_S_H + 268461019U, // CLE_S_W + 268453199U, // CLE_U_B + 268455608U, // CLE_U_D + 268456996U, // CLE_U_H + 268461487U, // CLE_U_W + 22959U, // CLO + 22959U, // CLO_MM + 22959U, // CLO_MMR6 + 22959U, // CLO_R6 + 268453022U, // CLTI_S_B + 268455179U, // CLTI_S_D + 268456746U, // CLTI_S_H + 268461057U, // CLTI_S_W + 268453237U, // CLTI_U_B + 268455646U, // CLTI_U_D + 268457034U, // CLTI_U_H + 268461525U, // CLTI_U_W + 268453090U, // CLT_S_B + 268455257U, // CLT_S_D + 268456834U, // CLT_S_H + 268461185U, // CLT_S_W + 268453317U, // CLT_U_B + 268455736U, // CLT_U_D + 268457124U, // CLT_U_H + 268461615U, // CLT_U_W + 26401U, // CLZ + 26401U, // CLZ_MM + 26401U, // CLZ_MMR6 + 26401U, // CLZ_R6 + 268453567U, // CMPGDU_EQ_QB + 268453567U, // CMPGDU_EQ_QB_MMR2 + 268453472U, // CMPGDU_LE_QB + 268453472U, // CMPGDU_LE_QB_MMR2 + 268453686U, // CMPGDU_LT_QB + 268453686U, // CMPGDU_LT_QB_MMR2 + 268453581U, // CMPGU_EQ_QB + 268453581U, // CMPGU_EQ_QB_MM + 268453486U, // CMPGU_LE_QB + 268453486U, // CMPGU_LE_QB_MM + 268453700U, // CMPGU_LT_QB + 268453700U, // CMPGU_LT_QB_MM + 18138U, // CMPU_EQ_QB + 18138U, // CMPU_EQ_QB_MM + 18043U, // CMPU_LE_QB + 18043U, // CMPU_LE_QB_MM + 18257U, // CMPU_LT_QB + 18257U, // CMPU_LT_QB_MM + 268454449U, // CMP_AF_D_MMR6 + 268458979U, // CMP_AF_S_MMR6 + 268454888U, // CMP_EQ_D + 268454888U, // CMP_EQ_D_MMR6 + 21958U, // CMP_EQ_PH + 21958U, // CMP_EQ_PH_MM + 268459183U, // CMP_EQ_S + 268459183U, // CMP_EQ_S_MMR6 + 268454449U, // CMP_F_D + 268458979U, // CMP_F_S + 268454293U, // CMP_LE_D + 268454293U, // CMP_LE_D_MMR6 + 21854U, // CMP_LE_PH + 21854U, // CMP_LE_PH_MM + 268458900U, // CMP_LE_S + 268458900U, // CMP_LE_S_MMR6 + 268455379U, // CMP_LT_D + 268455379U, // CMP_LT_D_MMR6 + 22127U, // CMP_LT_PH + 22127U, // CMP_LT_PH_MM + 268459288U, // CMP_LT_S + 268459288U, // CMP_LT_S_MMR6 + 268454467U, // CMP_SAF_D + 268454467U, // CMP_SAF_D_MMR6 + 268458989U, // CMP_SAF_S + 268458989U, // CMP_SAF_S_MMR6 + 268454915U, // CMP_SEQ_D + 268454915U, // CMP_SEQ_D_MMR6 + 268459202U, // CMP_SEQ_S + 268459202U, // CMP_SEQ_S_MMR6 + 268454330U, // CMP_SLE_D + 268454330U, // CMP_SLE_D_MMR6 + 268458929U, // CMP_SLE_S + 268458929U, // CMP_SLE_S_MMR6 + 268455406U, // CMP_SLT_D + 268455406U, // CMP_SLT_D_MMR6 + 268459307U, // CMP_SLT_S + 268459307U, // CMP_SLT_S_MMR6 + 268454963U, // CMP_SUEQ_D + 268454963U, // CMP_SUEQ_D_MMR6 + 268459233U, // CMP_SUEQ_S + 268459233U, // CMP_SUEQ_S_MMR6 + 268454378U, // CMP_SULE_D + 268454378U, // CMP_SULE_D_MMR6 + 268458960U, // CMP_SULE_S + 268458960U, // CMP_SULE_S_MMR6 + 268455454U, // CMP_SULT_D + 268455454U, // CMP_SULT_D_MMR6 + 268459338U, // CMP_SULT_S + 268459338U, // CMP_SULT_S_MMR6 + 268454836U, // CMP_SUN_D + 268454836U, // CMP_SUN_D_MMR6 + 268459147U, // CMP_SUN_S + 268459147U, // CMP_SUN_S_MMR6 + 268454943U, // CMP_UEQ_D + 268454943U, // CMP_UEQ_D_MMR6 + 268459222U, // CMP_UEQ_S + 268459222U, // CMP_UEQ_S_MMR6 + 268454358U, // CMP_ULE_D + 268454358U, // CMP_ULE_D_MMR6 + 268458949U, // CMP_ULE_S + 268458949U, // CMP_ULE_S_MMR6 + 268455434U, // CMP_ULT_D + 268455434U, // CMP_ULT_D_MMR6 + 268459327U, // CMP_ULT_S + 268459327U, // CMP_ULT_S_MMR6 + 268454818U, // CMP_UN_D + 268454818U, // CMP_UN_D_MMR6 + 268459137U, // CMP_UN_S + 268459137U, // CMP_UN_S_MMR6 + 2684372233U, // COPY_S_B + 2684374422U, // COPY_S_D + 2684375988U, // COPY_S_H + 2684380361U, // COPY_S_W + 2684372448U, // COPY_U_B + 2684376255U, // COPY_U_H + 2684380768U, // COPY_U_W + 268453411U, // CRC32B + 268453419U, // CRC32CB + 268455959U, // CRC32CD + 268457238U, // CRC32CH + 268461764U, // CRC32CW + 268455945U, // CRC32D + 268457218U, // CRC32H + 268461756U, // CRC32W + 8945789U, // CTC1 + 8945789U, // CTC1_MM + 8946005U, // CTC2_MM + 17121U, // CTCMSA + 23409U, // CVT_D32_S + 23409U, // CVT_D32_S_MM + 24726U, // CVT_D32_W + 24726U, // CVT_D32_W_MM + 22511U, // CVT_D64_L + 23409U, // CVT_D64_S + 23409U, // CVT_D64_S_MM + 24726U, // CVT_D64_W + 24726U, // CVT_D64_W_MM + 22511U, // CVT_D_L_MMR6 + 19256U, // CVT_L_D64 + 19256U, // CVT_L_D64_MM + 19256U, // CVT_L_D_MMR6 + 23634U, // CVT_L_S + 23634U, // CVT_L_S_MM + 23634U, // CVT_L_S_MMR6 + 26322U, // CVT_PS_PW64 + 268459252U, // CVT_PS_S64 + 24135U, // CVT_PW_PS64 + 19603U, // CVT_S_D32 + 19603U, // CVT_S_D32_MM + 19603U, // CVT_S_D64 + 19603U, // CVT_S_D64_MM + 22520U, // CVT_S_L + 22520U, // CVT_S_L_MMR6 + 22779U, // CVT_S_PL64 + 24417U, // CVT_S_PU64 + 25481U, // CVT_S_W + 25481U, // CVT_S_W_MM + 25481U, // CVT_S_W_MMR6 + 20431U, // CVT_W_D32 + 20431U, // CVT_W_D32_MM + 20431U, // CVT_W_D64 + 20431U, // CVT_W_D64_MM + 23976U, // CVT_W_S + 23976U, // CVT_W_S_MM + 23976U, // CVT_W_S_MMR6 + 268454880U, // C_EQ_D32 + 268454880U, // C_EQ_D32_MM + 268454880U, // C_EQ_D64 + 268454880U, // C_EQ_D64_MM + 268459175U, // C_EQ_S + 268459175U, // C_EQ_S_MM + 268454442U, // C_F_D32 + 268454442U, // C_F_D32_MM + 268454442U, // C_F_D64 + 268454442U, // C_F_D64_MM + 268458972U, // C_F_S + 268458972U, // C_F_S_MM + 268454285U, // C_LE_D32 + 268454285U, // C_LE_D32_MM + 268454285U, // C_LE_D64 + 268454285U, // C_LE_D64_MM + 268458892U, // C_LE_S + 268458892U, // C_LE_S_MM + 268455371U, // C_LT_D32 + 268455371U, // C_LT_D32_MM + 268455371U, // C_LT_D64 + 268455371U, // C_LT_D64_MM + 268459280U, // C_LT_S + 268459280U, // C_LT_S_MM + 268454276U, // C_NGE_D32 + 268454276U, // C_NGE_D32_MM + 268454276U, // C_NGE_D64 + 268454276U, // C_NGE_D64_MM + 268458883U, // C_NGE_S + 268458883U, // C_NGE_S_MM + 268454311U, // C_NGLE_D32 + 268454311U, // C_NGLE_D32_MM + 268454311U, // C_NGLE_D64 + 268454311U, // C_NGLE_D64_MM + 268458910U, // C_NGLE_S + 268458910U, // C_NGLE_S_MM + 268454728U, // C_NGL_D32 + 268454728U, // C_NGL_D32_MM + 268454728U, // C_NGL_D64 + 268454728U, // C_NGL_D64_MM + 268459106U, // C_NGL_S + 268459106U, // C_NGL_S_MM + 268455362U, // C_NGT_D32 + 268455362U, // C_NGT_D32_MM + 268455362U, // C_NGT_D64 + 268455362U, // C_NGT_D64_MM + 268459271U, // C_NGT_S + 268459271U, // C_NGT_S_MM + 268454321U, // C_OLE_D32 + 268454321U, // C_OLE_D32_MM + 268454321U, // C_OLE_D64 + 268454321U, // C_OLE_D64_MM + 268458920U, // C_OLE_S + 268458920U, // C_OLE_S_MM + 268455397U, // C_OLT_D32 + 268455397U, // C_OLT_D32_MM + 268455397U, // C_OLT_D64 + 268455397U, // C_OLT_D64_MM + 268459298U, // C_OLT_S + 268459298U, // C_OLT_S_MM + 268454906U, // C_SEQ_D32 + 268454906U, // C_SEQ_D32_MM + 268454906U, // C_SEQ_D64 + 268454906U, // C_SEQ_D64_MM + 268459193U, // C_SEQ_S + 268459193U, // C_SEQ_S_MM + 268454512U, // C_SF_D32 + 268454512U, // C_SF_D32_MM + 268454512U, // C_SF_D64 + 268454512U, // C_SF_D64_MM + 268459018U, // C_SF_S + 268459018U, // C_SF_S_MM + 268454934U, // C_UEQ_D32 + 268454934U, // C_UEQ_D32_MM + 268454934U, // C_UEQ_D64 + 268454934U, // C_UEQ_D64_MM + 268459213U, // C_UEQ_S + 268459213U, // C_UEQ_S_MM + 268454349U, // C_ULE_D32 + 268454349U, // C_ULE_D32_MM + 268454349U, // C_ULE_D64 + 268454349U, // C_ULE_D64_MM + 268458940U, // C_ULE_S + 268458940U, // C_ULE_S_MM + 268455425U, // C_ULT_D32 + 268455425U, // C_ULT_D32_MM + 268455425U, // C_ULT_D64 + 268455425U, // C_ULT_D64_MM + 268459318U, // C_ULT_S + 268459318U, // C_ULT_S_MM + 268454810U, // C_UN_D32 + 268454810U, // C_UN_D32_MM + 268454810U, // C_UN_D64 + 268454810U, // C_UN_D64_MM + 268459129U, // C_UN_S + 268459129U, // C_UN_S_MM + 23030U, // CmpRxRy16 + 2952812451U, // CmpiRxImm16 + 22435U, // CmpiRxImmX16 + 268455973U, // DADD + 268457823U, // DADDi + 268459807U, // DADDiu + 268459743U, // DADDu + 268457854U, // DAHI + 268458400U, // DALIGN + 268457915U, // DATI + 268457933U, // DAUI + 22990U, // DBITSWAP + 22958U, // DCLO + 22958U, // DCLO_R6 + 26400U, // DCLZ + 26400U, // DCLZ_R6 + 268460027U, // DDIV + 268459935U, // DDIVU + 10701U, // DERET + 10701U, // DERET_MM + 10701U, // DERET_MMR6 + 268459711U, // DEXT + 268462102U, // DEXT64_32 + 268458375U, // DEXTM + 268459928U, // DEXTU + 284514U, // DI + 268459511U, // DINS + 268458368U, // DINSM + 268459883U, // DINSU + 268460028U, // DIV + 268459936U, // DIVU + 268459936U, // DIVU_MMR6 + 268460028U, // DIV_MMR6 + 268453111U, // DIV_S_B + 268455300U, // DIV_S_D + 268456855U, // DIV_S_H + 268461228U, // DIV_S_W + 268453326U, // DIV_U_B + 268455767U, // DIV_U_D + 268457133U, // DIV_U_H + 268461646U, // DIV_U_W + 284514U, // DI_MM + 284514U, // DI_MMR6 + 268452563U, // DLSA + 268452563U, // DLSA_R6 + 268451841U, // DMFC0 + 16488U, // DMFC1 + 268452160U, // DMFC2 + 92291392U, // DMFC2_OCTEON + 268451848U, // DMFGC0 + 268456025U, // DMOD + 268459757U, // DMODU + 286371U, // DMT + 1376288822U, // DMTC0 + 8945795U, // DMTC1 + 1376289115U, // DMTC2 + 92291419U, // DMTC2_OCTEON + 1376288800U, // DMTGC0 + 268457810U, // DMUH + 268459800U, // DMUHU + 268458304U, // DMUL + 24220U, // DMULT + 24464U, // DMULTu + 268459844U, // DMULU + 268458304U, // DMUL_R6 + 268455208U, // DOTP_S_D + 268456775U, // DOTP_S_H + 268461096U, // DOTP_S_W + 268455675U, // DOTP_U_D + 268457063U, // DOTP_U_H + 268461554U, // DOTP_U_W + 285232337U, // DPADD_S_D + 285233904U, // DPADD_S_H + 285238215U, // DPADD_S_W + 285232804U, // DPADD_U_D + 285234192U, // DPADD_U_H + 285238683U, // DPADD_U_W + 268457662U, // DPAQX_SA_W_PH + 268457662U, // DPAQX_SA_W_PH_MMR2 + 268457745U, // DPAQX_S_W_PH + 268457745U, // DPAQX_S_W_PH_MMR2 + 268460556U, // DPAQ_SA_L_W + 268460556U, // DPAQ_SA_L_W_MM + 268457704U, // DPAQ_S_W_PH + 268457704U, // DPAQ_S_W_PH_MM + 268458011U, // DPAU_H_QBL + 268458011U, // DPAU_H_QBL_MM + 268458625U, // DPAU_H_QBR + 268458625U, // DPAU_H_QBR_MM + 268457783U, // DPAX_W_PH + 268457783U, // DPAX_W_PH_MMR2 + 268457652U, // DPA_W_PH + 268457652U, // DPA_W_PH_MMR2 + 23035U, // DPOP + 268457677U, // DPSQX_SA_W_PH + 268457677U, // DPSQX_SA_W_PH_MMR2 + 268457759U, // DPSQX_S_W_PH + 268457759U, // DPSQX_S_W_PH_MMR2 + 268460569U, // DPSQ_SA_L_W + 268460569U, // DPSQ_SA_L_W_MM + 268457732U, // DPSQ_S_W_PH + 268457732U, // DPSQ_S_W_PH_MM + 285232304U, // DPSUB_S_D + 285233883U, // DPSUB_S_H + 285238182U, // DPSUB_S_W + 285232771U, // DPSUB_U_D + 285234171U, // DPSUB_U_H + 285238650U, // DPSUB_U_W + 268458023U, // DPSU_H_QBL + 268458023U, // DPSU_H_QBL_MM + 268458637U, // DPSU_H_QBR + 268458637U, // DPSU_H_QBR_MM + 268457794U, // DPSX_W_PH + 268457794U, // DPSX_W_PH_MMR2 + 268457773U, // DPS_W_PH + 268457773U, // DPS_W_PH_MMR2 + 268458810U, // DROTR + 268452117U, // DROTR32 + 268460071U, // DROTRV + 21770U, // DSBH + 26471U, // DSDIV + 20529U, // DSHD + 268458223U, // DSLL + 268452087U, // DSLL32 + 3221248239U, // DSLL64_32 + 268460033U, // DSLLV + 268452557U, // DSRA + 268452069U, // DSRA32 + 268460012U, // DSRAV + 268458251U, // DSRL + 268452095U, // DSRL32 + 268460040U, // DSRLV + 268453801U, // DSUB + 268459722U, // DSUBu + 26457U, // DUDIV + 285278U, // DVP + 282835U, // DVPE + 285278U, // DVP_MMR6 + 26472U, // DivRxRy16 + 26458U, // DivuRxRy16 + 10595U, // EHB + 10595U, // EHB_MM + 10595U, // EHB_MMR6 + 284526U, // EI + 284526U, // EI_MM + 284526U, // EI_MMR6 + 286376U, // EMT + 10702U, // ERET + 10599U, // ERETNC + 10599U, // ERETNC_MMR6 + 10702U, // ERET_MM + 10702U, // ERET_MMR6 + 285283U, // EVP + 282841U, // EVPE + 285283U, // EVP_MMR6 + 268459712U, // EXT + 268458584U, // EXTP + 268458463U, // EXTPDP + 268460055U, // EXTPDPV + 268460055U, // EXTPDPV_MM + 268458463U, // EXTPDP_MM + 268460064U, // EXTPV + 268460064U, // EXTPV_MM + 268458584U, // EXTP_MM + 268461289U, // EXTRV_RS_W + 268461289U, // EXTRV_RS_W_MM + 268460843U, // EXTRV_R_W + 268460843U, // EXTRV_R_W_MM + 268456864U, // EXTRV_S_H + 268456864U, // EXTRV_S_H_MM + 268461726U, // EXTRV_W + 268461726U, // EXTRV_W_MM + 268461278U, // EXTR_RS_W + 268461278U, // EXTR_RS_W_MM + 268460822U, // EXTR_R_W + 268460822U, // EXTR_R_W_MM + 268456795U, // EXTR_S_H + 268456795U, // EXTR_S_H_MM + 268460921U, // EXTR_W + 268460921U, // EXTR_W_MM + 268459609U, // EXTS + 268452134U, // EXTS32 + 268459712U, // EXT_MM + 268459712U, // EXT_MMR6 + 19872U, // FABS_D32 + 19872U, // FABS_D32_MM + 19872U, // FABS_D64 + 19872U, // FABS_D64_MM + 23789U, // FABS_S + 23789U, // FABS_S_MM + 268454225U, // FADD_D + 268454226U, // FADD_D32 + 268454226U, // FADD_D32_MM + 268454226U, // FADD_D64 + 268454226U, // FADD_D64_MM + 268459525U, // FADD_PS64 + 268458876U, // FADD_S + 268458876U, // FADD_S_MM + 285236092U, // FADD_S_MMR6 + 268460191U, // FADD_W + 268454459U, // FCAF_D + 268460310U, // FCAF_W + 268454898U, // FCEQ_D + 268460749U, // FCEQ_W + 19879U, // FCLASS_D + 25845U, // FCLASS_W + 268454303U, // FCLE_D + 268460233U, // FCLE_W + 268455389U, // FCLT_D + 268461328U, // FCLT_W + 3041387U, // FCMP_D32 + 3041387U, // FCMP_D32_MM + 3041387U, // FCMP_D64 + 3303531U, // FCMP_S32 + 3303531U, // FCMP_S32_MM + 268454399U, // FCNE_D + 268460267U, // FCNE_W + 268455008U, // FCOR_D + 268460878U, // FCOR_W + 268454954U, // FCUEQ_D + 268460765U, // FCUEQ_W + 268454369U, // FCULE_D + 268460249U, // FCULE_W + 268455445U, // FCULT_D + 268461344U, // FCULT_W + 268454415U, // FCUNE_D + 268460283U, // FCUNE_W + 268454828U, // FCUN_D + 268460655U, // FCUN_W + 268455821U, // FDIV_D + 268455822U, // FDIV_D32 + 268455822U, // FDIV_D32_MM + 268455822U, // FDIV_D64 + 268455822U, // FDIV_D64_MM + 268459375U, // FDIV_S + 268459375U, // FDIV_S_MM + 285236591U, // FDIV_S_MMR6 + 268461710U, // FDIV_W + 268456522U, // FEXDO_H + 268460671U, // FEXDO_W + 268454112U, // FEXP2_D + 268460094U, // FEXP2_W + 19296U, // FEXUPL_D + 25141U, // FEXUPL_W + 19568U, // FEXUPR_D + 25438U, // FEXUPR_W + 19810U, // FFINT_S_D + 25738U, // FFINT_S_W + 20289U, // FFINT_U_D + 26168U, // FFINT_U_W + 19306U, // FFQL_D + 25151U, // FFQL_W + 19578U, // FFQR_D + 25448U, // FFQR_W + 17422U, // FILL_B + 19281U, // FILL_D + 21027U, // FILL_H + 25126U, // FILL_W + 18647U, // FLOG2_D + 24629U, // FLOG2_W + 19245U, // FLOOR_L_D64 + 19245U, // FLOOR_L_D_MMR6 + 23623U, // FLOOR_L_S + 23623U, // FLOOR_L_S_MMR6 + 20420U, // FLOOR_W_D32 + 20420U, // FLOOR_W_D64 + 20420U, // FLOOR_W_D_MMR6 + 20420U, // FLOOR_W_MM + 23965U, // FLOOR_W_S + 23965U, // FLOOR_W_S_MM + 23965U, // FLOOR_W_S_MMR6 + 285231449U, // FMADD_D + 285237415U, // FMADD_W + 268454150U, // FMAX_A_D + 268460132U, // FMAX_A_W + 268455896U, // FMAX_D + 268461735U, // FMAX_W + 268454130U, // FMIN_A_D + 268460112U, // FMIN_A_W + 268454802U, // FMIN_D + 268460647U, // FMIN_W + 20381U, // FMOV_D32 + 20381U, // FMOV_D32_MM + 20381U, // FMOV_D64 + 20381U, // FMOV_D64_MM + 20381U, // FMOV_D_MMR6 + 23926U, // FMOV_S + 23926U, // FMOV_S_MM + 23926U, // FMOV_S_MMR6 + 285231407U, // FMSUB_D + 285237373U, // FMSUB_W + 268454786U, // FMUL_D + 268454787U, // FMUL_D32 + 268454787U, // FMUL_D32_MM + 268454787U, // FMUL_D64 + 268454787U, // FMUL_D64_MM + 268459541U, // FMUL_PS64 + 268459115U, // FMUL_S + 268459115U, // FMUL_S_MM + 285236331U, // FMUL_S_MMR6 + 268460631U, // FMUL_W + 19073U, // FNEG_D32 + 19073U, // FNEG_D32_MM + 19073U, // FNEG_D64 + 19073U, // FNEG_D64_MM + 23578U, // FNEG_S + 23578U, // FNEG_S_MM + 23578U, // FNEG_S_MMR6 + 3523778537U, // FORK + 19407U, // FRCP_D + 25224U, // FRCP_W + 20027U, // FRINT_D + 25914U, // FRINT_W + 20055U, // FRSQRT_D + 25942U, // FRSQRT_W + 268454478U, // FSAF_D + 268460318U, // FSAF_W + 268454926U, // FSEQ_D + 268460757U, // FSEQ_W + 268454341U, // FSLE_D + 268460241U, // FSLE_W + 268455417U, // FSLT_D + 268461336U, // FSLT_W + 268454407U, // FSNE_D + 268460275U, // FSNE_W + 268455016U, // FSOR_D + 268460886U, // FSOR_W + 20046U, // FSQRT_D + 20047U, // FSQRT_D32 + 20047U, // FSQRT_D32_MM + 20047U, // FSQRT_D64 + 20047U, // FSQRT_D64_MM + 23903U, // FSQRT_S + 23903U, // FSQRT_S_MM + 25933U, // FSQRT_W + 268454183U, // FSUB_D + 268454184U, // FSUB_D32 + 268454184U, // FSUB_D32_MM + 268454184U, // FSUB_D64 + 268454184U, // FSUB_D64_MM + 268459517U, // FSUB_PS64 + 268458858U, // FSUB_S + 268458858U, // FSUB_S_MM + 285236074U, // FSUB_S_MMR6 + 268460149U, // FSUB_W + 268454975U, // FSUEQ_D + 268460774U, // FSUEQ_W + 268454390U, // FSULE_D + 268460258U, // FSULE_W + 268455466U, // FSULT_D + 268461353U, // FSULT_W + 268454424U, // FSUNE_D + 268460292U, // FSUNE_W + 268454847U, // FSUN_D + 268460663U, // FSUN_W + 19821U, // FTINT_S_D + 25749U, // FTINT_S_W + 20300U, // FTINT_U_D + 26179U, // FTINT_U_W + 268456599U, // FTQ_H + 268460783U, // FTQ_W + 19643U, // FTRUNC_S_D + 25521U, // FTRUNC_S_W + 20110U, // FTRUNC_U_D + 25989U, // FTRUNC_U_W + 284632U, // GINVI + 284632U, // GINVI_MMR6 + 100687538U, // GINVT + 100687538U, // GINVT_MMR6 + 268455111U, // HADD_S_D + 268456678U, // HADD_S_H + 268460989U, // HADD_S_W + 268455578U, // HADD_U_D + 268456966U, // HADD_U_H + 268461457U, // HADD_U_W + 268455078U, // HSUB_S_D + 268456657U, // HSUB_S_H + 268460956U, // HSUB_S_W + 268455545U, // HSUB_U_D + 268456945U, // HSUB_U_H + 268461424U, // HSUB_U_W + 366795U, // HYPCALL + 366795U, // HYPCALL_MM + 268453381U, // ILVEV_B + 268455812U, // ILVEV_D + 268457188U, // ILVEV_H + 268461701U, // ILVEV_W + 268452909U, // ILVL_B + 268454794U, // ILVL_D + 268456514U, // ILVL_H + 268460639U, // ILVL_W + 268452661U, // ILVOD_B + 268454267U, // ILVOD_D + 268456316U, // ILVOD_H + 268460224U, // ILVOD_W + 268452957U, // ILVR_B + 268455051U, // ILVR_D + 268456639U, // ILVR_H + 268460929U, // ILVR_W + 268459506U, // INS + 112477484U, // INSERT_B + 120868420U, // INSERT_D + 129258455U, // INSERT_H + 137651523U, // INSERT_W + 16801839U, // INSV + 146031422U, // INSVE_B + 154421793U, // INSVE_D + 162812293U, // INSVE_H + 171204877U, // INSVE_W + 16801839U, // INSV_MM + 268459506U, // INS_MM + 268459506U, // INS_MMR6 + 284639U, // J + 284678U, // JAL + 23310U, // JALR + 285454U, // JALR16_MM + 23310U, // JALR64 + 285454U, // JALRC16_MMR6 + 17977U, // JALRC_HB_MMR6 + 18516U, // JALRC_MMR6 + 279095U, // JALRS16_MM + 24146U, // JALRS_MM + 17994U, // JALR_HB + 17994U, // JALR_HB64 + 23310U, // JALR_MM + 286169U, // JALS_MM + 288494U, // JALX + 288494U, // JALX_MM + 284678U, // JAL_MM + 18395U, // JIALC + 18395U, // JIALC64 + 18395U, // JIALC_MMR6 + 18384U, // JIC + 18384U, // JIC64 + 18384U, // JIC_MMR6 + 285450U, // JR + 279082U, // JR16_MM + 285450U, // JR64 + 285255U, // JRADDIUSP + 280655U, // JRC16_MM + 278960U, // JRC16_MMR6 + 285243U, // JRCADDIUSP_MMR6 + 280131U, // JR_HB + 280131U, // JR_HB64 + 280131U, // JR_HB64_R6 + 280131U, // JR_HB_R6 + 285450U, // JR_MM + 284639U, // J_MM + 3840006U, // Jal16 + 4102150U, // JalB16 + 10588U, // JrRa16 + 10580U, // JrcRa16 + 280655U, // JrcRx16 + 280660U, // JumpLinkReg16 + 25183827U, // LB + 25183827U, // LB64 + 25186403U, // LBE + 25186403U, // LBE_MM + 25182791U, // LBU16_MM + 3774899956U, // LBUX + 3774899956U, // LBUX_MM + 25190085U, // LBU_MMR6 + 25183827U, // LB_MM + 25183827U, // LB_MMR6 + 25190085U, // LBu + 25190085U, // LBu64 + 25186539U, // LBuE + 25186539U, // LBuE_MM + 25190085U, // LBu_MM + 25186362U, // LD + 25182294U, // LDC1 + 25182294U, // LDC164 + 25182294U, // LDC1_D64_MMR6 + 25182294U, // LDC1_MM + 25182510U, // LDC2 + 25182510U, // LDC2_MMR6 + 25182510U, // LDC2_R6 + 25182595U, // LDC3 + 17248U, // LDI_B + 19089U, // LDI_D + 20903U, // LDI_H + 24976U, // LDI_W + 25188450U, // LDL + 18462U, // LDPC + 25189064U, // LDR + 3774890134U, // LDXC1 + 3774890134U, // LDXC164 + 25183014U, // LD_B + 25184620U, // LD_D + 25186669U, // LD_H + 25190577U, // LD_W + 67133216U, // LEA_ADDiu + 67133215U, // LEA_ADDiu64 + 67133216U, // LEA_ADDiu_MM + 25187621U, // LH + 25187621U, // LH64 + 25186455U, // LHE + 25186455U, // LHE_MM + 25182814U, // LHU16_MM + 3774899945U, // LHX + 3774899945U, // LHX_MM + 25187621U, // LH_MM + 25190163U, // LHu + 25190163U, // LHu64 + 25186545U, // LHuE + 25186545U, // LHuE_MM + 25190163U, // LHu_MM + 16878U, // LI16_MM + 16878U, // LI16_MMR6 + 25188560U, // LL + 25188560U, // LL64 + 25188560U, // LL64_R6 + 25186366U, // LLD + 25186366U, // LLD_R6 + 25186478U, // LLE + 25186478U, // LLE_MM + 25188560U, // LL_MM + 25188560U, // LL_MMR6 + 25188560U, // LL_R6 + 268452564U, // LSA + 4061741780U, // LSA_MMR6 + 268452564U, // LSA_R6 + 92297171U, // LUI_MMR6 + 3774890148U, // LUXC1 + 3774890148U, // LUXC164 + 3774890148U, // LUXC1_MM + 92297171U, // LUi + 92297171U, // LUi64 + 92297171U, // LUi_MM + 25192142U, // LW + 25182821U, // LW16_MM + 25192142U, // LW64 + 25182346U, // LWC1 + 25182346U, // LWC1_MM + 25182562U, // LWC2 + 25182562U, // LWC2_MMR6 + 25182562U, // LWC2_R6 + 25182607U, // LWC3 + 25192142U, // LWDSP + 25192142U, // LWDSP_MM + 25186557U, // LWE + 25186557U, // LWE_MM + 25192142U, // LWGP_MM + 25188692U, // LWL + 25188692U, // LWL64 + 25186488U, // LWLE + 25186488U, // LWLE_MM + 25188692U, // LWL_MM + 49675U, // LWM16_MM + 49675U, // LWM16_MMR6 + 49415U, // LWM32_MM + 18499U, // LWPC + 18499U, // LWPC_MMR6 + 176183912U, // LWP_MM + 25189198U, // LWR + 25189198U, // LWR64 + 25186527U, // LWRE + 25186527U, // LWRE_MM + 25189198U, // LWR_MM + 25192142U, // LWSP_MM + 18492U, // LWUPC + 25190310U, // LWU_MM + 3774899962U, // LWX + 3774890162U, // LWXC1 + 3774890162U, // LWXC1_MM + 3774897759U, // LWXS_MM + 3774899962U, // LWX_MM + 25192142U, // LW_MM + 25192142U, // LW_MMR6 + 25190310U, // LWu + 25183827U, // LbRxRyOffMemX16 + 25190085U, // LbuRxRyOffMemX16 + 25187621U, // LhRxRyOffMemX16 + 25190163U, // LhuRxRyOffMemX16 + 2952812442U, // LiRxImm16 + 22416U, // LiRxImmAlignX16 + 22426U, // LiRxImmX16 + 2147509966U, // LwRxPcTcp16 + 26318U, // LwRxPcTcpX16 + 25192142U, // LwRxRyOffMemX16 + 25192142U, // LwRxSpImmX16 + 20523U, // MADD + 285231711U, // MADDF_D + 285231711U, // MADDF_D_MMR6 + 285236225U, // MADDF_S + 285236225U, // MADDF_S_MMR6 + 285233787U, // MADDR_Q_H + 285237944U, // MADDR_Q_W + 24294U, // MADDU + 268459750U, // MADDU_DSP + 268459750U, // MADDU_DSP_MM + 24294U, // MADDU_MM + 285230579U, // MADDV_B + 285233010U, // MADDV_D + 285234386U, // MADDV_H + 285238899U, // MADDV_W + 268454234U, // MADD_D32 + 268454234U, // MADD_D32_MM + 268454234U, // MADD_D64 + 268455979U, // MADD_DSP + 268455979U, // MADD_DSP_MM + 20523U, // MADD_MM + 285233757U, // MADD_Q_H + 285237914U, // MADD_Q_W + 268458875U, // MADD_S + 268458875U, // MADD_S_MM + 268458131U, // MAQ_SA_W_PHL + 268458131U, // MAQ_SA_W_PHL_MM + 268458706U, // MAQ_SA_W_PHR + 268458706U, // MAQ_SA_W_PHR_MM + 268458159U, // MAQ_S_W_PHL + 268458159U, // MAQ_S_W_PHL_MM + 268458734U, // MAQ_S_W_PHR + 268458734U, // MAQ_S_W_PHR_MM + 268454175U, // MAXA_D + 268454175U, // MAXA_D_MMR6 + 268458848U, // MAXA_S + 268458848U, // MAXA_S_MMR6 + 268453032U, // MAXI_S_B + 268455189U, // MAXI_S_D + 268456756U, // MAXI_S_H + 268461067U, // MAXI_S_W + 268453247U, // MAXI_U_B + 268455656U, // MAXI_U_D + 268457044U, // MAXI_U_H + 268461535U, // MAXI_U_W + 268452613U, // MAX_A_B + 268454151U, // MAX_A_D + 268456268U, // MAX_A_H + 268460133U, // MAX_A_W + 268455897U, // MAX_D + 268455897U, // MAX_D_MMR6 + 268459441U, // MAX_S + 268453120U, // MAX_S_B + 268455309U, // MAX_S_D + 268456875U, // MAX_S_H + 268459441U, // MAX_S_MMR6 + 268461248U, // MAX_S_W + 268453335U, // MAX_U_B + 268455776U, // MAX_U_D + 268457142U, // MAX_U_H + 268461655U, // MAX_U_W + 268451842U, // MFC0 + 268451842U, // MFC0_MMR6 + 16489U, // MFC1 + 16489U, // MFC1_D64 + 16489U, // MFC1_MM + 16489U, // MFC1_MMR6 + 268452161U, // MFC2 + 16705U, // MFC2_MMR6 + 268451849U, // MFGC0 + 268451849U, // MFGC0_MM + 268451880U, // MFHC0_MMR6 + 16495U, // MFHC1_D32 + 16495U, // MFHC1_D32_MM + 16495U, // MFHC1_D64 + 16495U, // MFHC1_D64_MM + 16711U, // MFHC2_MMR6 + 268451856U, // MFHGC0 + 268451856U, // MFHGC0_MM + 284548U, // MFHI + 279014U, // MFHI16_MM + 284548U, // MFHI64 + 22404U, // MFHI_DSP + 22404U, // MFHI_DSP_MM + 284548U, // MFHI_MM + 285108U, // MFLO + 279065U, // MFLO16_MM + 285108U, // MFLO64 + 22964U, // MFLO_DSP + 22964U, // MFLO_DSP_MM + 285108U, // MFLO_MM + 268458804U, // MFTR + 268454160U, // MINA_D + 268454160U, // MINA_D_MMR6 + 268458840U, // MINA_S + 268458840U, // MINA_S_MMR6 + 268453012U, // MINI_S_B + 268455169U, // MINI_S_D + 268456736U, // MINI_S_H + 268461047U, // MINI_S_W + 268453227U, // MINI_U_B + 268455636U, // MINI_U_D + 268457024U, // MINI_U_H + 268461515U, // MINI_U_W + 268452594U, // MIN_A_B + 268454131U, // MIN_A_D + 268456249U, // MIN_A_H + 268460113U, // MIN_A_W + 268454803U, // MIN_D + 268454803U, // MIN_D_MMR6 + 268459122U, // MIN_S + 268453042U, // MIN_S_B + 268455199U, // MIN_S_D + 268456766U, // MIN_S_H + 268459122U, // MIN_S_MMR6 + 268461087U, // MIN_S_W + 268453257U, // MIN_U_B + 268455666U, // MIN_U_D + 268457054U, // MIN_U_H + 268461545U, // MIN_U_W + 268456026U, // MOD + 268453799U, // MODSUB + 268453799U, // MODSUB_MM + 268459758U, // MODU + 268459758U, // MODU_MMR6 + 268456026U, // MOD_MMR6 + 268452975U, // MOD_S_B + 268455132U, // MOD_S_D + 268456699U, // MOD_S_H + 268461010U, // MOD_S_W + 268453190U, // MOD_U_B + 268455599U, // MOD_U_D + 268456987U, // MOD_U_H + 268461478U, // MOD_U_W + 20727U, // MOVE16_MM + 16848U, // MOVE16_MMR6 + 268458471U, // MOVEP_MM + 268458471U, // MOVEP_MMR6 + 24498U, // MOVE_V + 268454520U, // MOVF_D32 + 268454520U, // MOVF_D32_MM + 268454520U, // MOVF_D64 + 268456229U, // MOVF_I + 268456229U, // MOVF_I64 + 268456229U, // MOVF_I_MM + 268459026U, // MOVF_S + 268459026U, // MOVF_S_MM + 268454855U, // MOVN_I64_D64 + 268458408U, // MOVN_I64_I + 268458408U, // MOVN_I64_I64 + 268459158U, // MOVN_I64_S + 268454855U, // MOVN_I_D32 + 268454855U, // MOVN_I_D32_MM + 268454855U, // MOVN_I_D64 + 268458408U, // MOVN_I_I + 268458408U, // MOVN_I_I64 + 268458408U, // MOVN_I_MM + 268459158U, // MOVN_I_S + 268459158U, // MOVN_I_S_MM + 268455527U, // MOVT_D32 + 268455527U, // MOVT_D32_MM + 268455527U, // MOVT_D64 + 268459705U, // MOVT_I + 268459705U, // MOVT_I64 + 268459705U, // MOVT_I_MM + 268459367U, // MOVT_S + 268459367U, // MOVT_S_MM + 268455937U, // MOVZ_I64_D64 + 268461895U, // MOVZ_I64_I + 268461895U, // MOVZ_I64_I64 + 268459468U, // MOVZ_I64_S + 268455937U, // MOVZ_I_D32 + 268455937U, // MOVZ_I_D32_MM + 268455937U, // MOVZ_I_D64 + 268461895U, // MOVZ_I_I + 268461895U, // MOVZ_I_I64 + 268461895U, // MOVZ_I_MM + 268459468U, // MOVZ_I_S + 268459468U, // MOVZ_I_S_MM + 18351U, // MSUB + 285231702U, // MSUBF_D + 285231702U, // MSUBF_D_MMR6 + 285236216U, // MSUBF_S + 285236216U, // MSUBF_S_MMR6 + 285233776U, // MSUBR_Q_H + 285237933U, // MSUBR_Q_W + 24273U, // MSUBU + 268459729U, // MSUBU_DSP + 268459729U, // MSUBU_DSP_MM + 24273U, // MSUBU_MM + 285230570U, // MSUBV_B + 285233001U, // MSUBV_D + 285234377U, // MSUBV_H + 285238890U, // MSUBV_W + 268454192U, // MSUB_D32 + 268454192U, // MSUB_D32_MM + 268454192U, // MSUB_D64 + 268453807U, // MSUB_DSP + 268453807U, // MSUB_DSP_MM + 18351U, // MSUB_MM + 285233747U, // MSUB_Q_H + 285237904U, // MSUB_Q_W + 268458857U, // MSUB_S + 268458857U, // MSUB_S_MM + 1376288823U, // MTC0 + 1376288823U, // MTC0_MMR6 + 8945796U, // MTC1 + 8945796U, // MTC1_D64 + 8945796U, // MTC1_D64_MM + 8945796U, // MTC1_MM + 8945796U, // MTC1_MMR6 + 1376289116U, // MTC2 + 8946012U, // MTC2_MMR6 + 1376288801U, // MTGC0 + 1376288801U, // MTGC0_MM + 1376288815U, // MTHC0_MMR6 + 8994934U, // MTHC1_D32 + 8994934U, // MTHC1_D32_MM + 8994934U, // MTHC1_D64 + 8994934U, // MTHC1_D64_MM + 8945998U, // MTHC2_MMR6 + 1376288792U, // MTHGC0 + 1376288792U, // MTHGC0_MM + 284554U, // MTHI + 284554U, // MTHI64 + 8951690U, // MTHI_DSP + 8951690U, // MTHI_DSP_MM + 284554U, // MTHI_MM + 8952302U, // MTHLIP + 8952302U, // MTHLIP_MM + 285121U, // MTLO + 285121U, // MTLO64 + 8952257U, // MTLO_DSP + 8952257U, // MTLO_DSP_MM + 285121U, // MTLO_MM + 278595U, // MTM0 + 278720U, // MTM1 + 278894U, // MTM2 + 278601U, // MTP0 + 278726U, // MTP1 + 278900U, // MTP2 + 34118465U, // MTTR + 268457811U, // MUH + 268459801U, // MUHU + 268459801U, // MUHU_MMR6 + 268457811U, // MUH_MMR6 + 268458305U, // MUL + 268458172U, // MULEQ_S_W_PHL + 268458172U, // MULEQ_S_W_PHL_MM + 268458747U, // MULEQ_S_W_PHR + 268458747U, // MULEQ_S_W_PHR_MM + 268458035U, // MULEU_S_PH_QBL + 268458035U, // MULEU_S_PH_QBL_MM + 268458649U, // MULEU_S_PH_QBR + 268458649U, // MULEU_S_PH_QBR_MM + 268457571U, // MULQ_RS_PH + 268457571U, // MULQ_RS_PH_MM + 268461267U, // MULQ_RS_W + 268461267U, // MULQ_RS_W_MMR2 + 268457515U, // MULQ_S_PH + 268457515U, // MULQ_S_PH_MMR2 + 268461126U, // MULQ_S_W + 268461126U, // MULQ_S_W_MMR2 + 268459566U, // MULR_PS64 + 268456582U, // MULR_Q_H + 268460739U, // MULR_Q_W + 268457717U, // MULSAQ_S_W_PH + 268457717U, // MULSAQ_S_W_PH_MM + 268457692U, // MULSA_W_PH + 268457692U, // MULSA_W_PH_MMR2 + 24221U, // MULT + 268459921U, // MULTU_DSP + 268459921U, // MULTU_DSP_MM + 268459677U, // MULT_DSP + 268459677U, // MULT_DSP_MM + 24221U, // MULT_MM + 24465U, // MULTu + 24465U, // MULTu_MM + 268459838U, // MULU + 268459838U, // MULU_MMR6 + 268453390U, // MULV_B + 268455829U, // MULV_D + 268457197U, // MULV_H + 268461718U, // MULV_W + 268458305U, // MUL_MM + 268458305U, // MUL_MMR6 + 268457388U, // MUL_PH + 268457388U, // MUL_PH_MMR2 + 268456551U, // MUL_Q_H + 268460708U, // MUL_Q_W + 268458305U, // MUL_R6 + 268457483U, // MUL_S_PH + 268457483U, // MUL_S_PH_MMR2 + 284548U, // Mfhi16 + 285108U, // Mflo16 + 20727U, // Move32R16 + 20727U, // MoveR3216 + 17173U, // NLOC_B + 18753U, // NLOC_D + 20828U, // NLOC_H + 24710U, // NLOC_W + 17181U, // NLZC_B + 18761U, // NLZC_D + 20836U, // NLZC_H + 24718U, // NLZC_W + 268454242U, // NMADD_D32 + 268454242U, // NMADD_D32_MM + 268454242U, // NMADD_D64 + 268458874U, // NMADD_S + 268458874U, // NMADD_S_MM + 268454200U, // NMSUB_D32 + 268454200U, // NMSUB_D32_MM + 268454200U, // NMSUB_D64 + 268458856U, // NMSUB_S + 268458856U, // NMSUB_S_MM + 268458772U, // NOR + 268458772U, // NOR64 + 268452798U, // NORI_B + 268458772U, // NOR_MM + 268458772U, // NOR_MMR6 + 268459970U, // NOR_V + 16960U, // NOT16_MM + 16960U, // NOT16_MMR6 + 20779U, // NegRxRy16 + 24237U, // NotRxRy16 + 268458773U, // OR + 10043953U, // OR16_MM + 10043953U, // OR16_MMR6 + 268458773U, // OR64 + 268452799U, // ORI_B + 268457910U, // ORI_MMR6 + 268458773U, // OR_MM + 268458773U, // OR_MMR6 + 268459971U, // OR_V + 268457910U, // ORi + 268457910U, // ORi64 + 268457910U, // ORi_MM + 16800533U, // OrRxRxRy16 + 268457377U, // PACKRL_PH + 268457377U, // PACKRL_PH_MM + 10606U, // PAUSE + 10606U, // PAUSE_MM + 10606U, // PAUSE_MMR6 + 268453372U, // PCKEV_B + 268455803U, // PCKEV_D + 268457179U, // PCKEV_H + 268461692U, // PCKEV_W + 268452652U, // PCKOD_B + 268454258U, // PCKOD_D + 268456307U, // PCKOD_H + 268460215U, // PCKOD_W + 17700U, // PCNT_B + 20019U, // PCNT_D + 21455U, // PCNT_H + 25906U, // PCNT_W + 268457341U, // PICK_PH + 268457341U, // PICK_PH_MM + 268453531U, // PICK_QB + 268453531U, // PICK_QB_MM + 268459533U, // PLL_PS64 + 268459575U, // PLU_PS64 + 23036U, // POP + 22610U, // PRECEQU_PH_QBL + 17046U, // PRECEQU_PH_QBLA + 17046U, // PRECEQU_PH_QBLA_MM + 22610U, // PRECEQU_PH_QBL_MM + 23224U, // PRECEQU_PH_QBR + 17084U, // PRECEQU_PH_QBRA + 17084U, // PRECEQU_PH_QBRA_MM + 23224U, // PRECEQU_PH_QBR_MM + 22689U, // PRECEQ_W_PHL + 22689U, // PRECEQ_W_PHL_MM + 23264U, // PRECEQ_W_PHR + 23264U, // PRECEQ_W_PHR_MM + 22595U, // PRECEU_PH_QBL + 17030U, // PRECEU_PH_QBLA + 17030U, // PRECEU_PH_QBLA_MM + 22595U, // PRECEU_PH_QBL_MM + 23209U, // PRECEU_PH_QBR + 17068U, // PRECEU_PH_QBRA + 17068U, // PRECEU_PH_QBRA_MM + 23209U, // PRECEU_PH_QBR_MM + 268457293U, // PRECRQU_S_QB_PH + 268457293U, // PRECRQU_S_QB_PH_MM + 268460358U, // PRECRQ_PH_W + 268460358U, // PRECRQ_PH_W_MM + 268457266U, // PRECRQ_QB_PH + 268457266U, // PRECRQ_QB_PH_MM + 268460389U, // PRECRQ_RS_PH_W + 268460389U, // PRECRQ_RS_PH_W_MM + 268457280U, // PRECR_QB_PH + 268457280U, // PRECR_QB_PH_MMR2 + 268460342U, // PRECR_SRA_PH_W + 268460342U, // PRECR_SRA_PH_W_MMR2 + 268460371U, // PRECR_SRA_R_PH_W + 268460371U, // PRECR_SRA_R_PH_W_MMR2 + 2756895U, // PREF + 2756730U, // PREFE + 2756730U, // PREFE_MM + 186263266U, // PREFX_MM + 2756895U, // PREF_MM + 2756895U, // PREF_MMR6 + 2756895U, // PREF_R6 + 268456008U, // PREPEND + 268456008U, // PREPEND_MMR2 + 268459549U, // PUL_PS64 + 268459583U, // PUU_PS64 + 18327U, // RADDU_W_QB + 18327U, // RADDU_W_QB_MM + 83909165U, // RDDSP + 192961069U, // RDDSP_MM + 268458823U, // RDHWR + 268458823U, // RDHWR64 + 268458823U, // RDHWR_MM + 268458823U, // RDHWR_MMR6 + 23332U, // RDPGPR_MMR6 + 19415U, // RECIP_D32 + 19415U, // RECIP_D32_MM + 19415U, // RECIP_D64 + 19415U, // RECIP_D64_MM + 23710U, // RECIP_S + 23710U, // RECIP_S_MM + 22176U, // REPLV_PH + 22176U, // REPLV_PH_MM + 18307U, // REPLV_QB + 18307U, // REPLV_QB_MM + 21903U, // REPL_PH + 21903U, // REPL_PH_MM + 201344685U, // REPL_QB + 201344685U, // REPL_QB_MM + 20028U, // RINT_D + 20028U, // RINT_D_MMR6 + 23894U, // RINT_S + 23894U, // RINT_S_MMR6 + 268458811U, // ROTR + 268460072U, // ROTRV + 268460072U, // ROTRV_MM + 268458811U, // ROTR_MM + 19224U, // ROUND_L_D64 + 19224U, // ROUND_L_D_MMR6 + 23602U, // ROUND_L_S + 23602U, // ROUND_L_S_MMR6 + 20399U, // ROUND_W_D32 + 20399U, // ROUND_W_D64 + 20399U, // ROUND_W_D_MMR6 + 20399U, // ROUND_W_MM + 23944U, // ROUND_W_S + 23944U, // ROUND_W_S_MM + 23944U, // ROUND_W_S_MMR6 + 20056U, // RSQRT_D32 + 20056U, // RSQRT_D32_MM + 20056U, // RSQRT_D64 + 20056U, // RSQRT_D64_MM + 23902U, // RSQRT_S + 23902U, // RSQRT_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 4211329U, // SAA + 4214801U, // SAAD + 268453081U, // SAT_S_B + 268455248U, // SAT_S_D + 268456825U, // SAT_S_H + 268461176U, // SAT_S_W + 268453308U, // SAT_U_B + 268455727U, // SAT_U_D + 268457115U, // SAT_U_H + 268461606U, // SAT_U_W + 25184163U, // SB + 25182628U, // SB16_MM + 25182628U, // SB16_MMR6 + 25184163U, // SB64 + 25186408U, // SBE + 25186408U, // SBE_MM + 25184163U, // SB_MM + 25184163U, // SB_MMR6 + 4491358U, // SC + 4491358U, // SC64 + 4491358U, // SC64_R6 + 4493344U, // SCD + 4493344U, // SCD_R6 + 4493421U, // SCE + 4493421U, // SCE_MM + 4491358U, // SC_MM + 4491358U, // SC_MMR6 + 4491358U, // SC_R6 + 25186399U, // SD + 186840U, // SDBBP + 115233U, // SDBBP16_MM + 115233U, // SDBBP16_MMR6 + 367064U, // SDBBP_MM + 186840U, // SDBBP_MMR6 + 186840U, // SDBBP_R6 + 25182300U, // SDC1 + 25182300U, // SDC164 + 25182300U, // SDC1_D64_MMR6 + 25182300U, // SDC1_MM + 25182516U, // SDC2 + 25182516U, // SDC2_MMR6 + 25182516U, // SDC2_R6 + 25182601U, // SDC3 + 26472U, // SDIV + 26472U, // SDIV_MM + 25188455U, // SDL + 25189069U, // SDR + 3774890141U, // SDXC1 + 3774890141U, // SDXC164 + 17972U, // SEB + 17972U, // SEB64 + 17972U, // SEB_MM + 21791U, // SEH + 21791U, // SEH64 + 21791U, // SEH_MM + 268461868U, // SELEQZ + 268461868U, // SELEQZ64 + 268455927U, // SELEQZ_D + 268455927U, // SELEQZ_D_MMR6 + 268461868U, // SELEQZ_MMR6 + 268459458U, // SELEQZ_S + 268459458U, // SELEQZ_S_MMR6 + 268461841U, // SELNEZ + 268461841U, // SELNEZ64 + 268455910U, // SELNEZ_D + 268455910U, // SELNEZ_D_MMR6 + 268461841U, // SELNEZ_MMR6 + 268459448U, // SELNEZ_S + 268459448U, // SELNEZ_S_MMR6 + 285231937U, // SEL_D + 285231937U, // SEL_D_MMR6 + 285236315U, // SEL_S + 285236315U, // SEL_S_MMR6 + 268458615U, // SEQ + 268457897U, // SEQi + 25188174U, // SH + 25182680U, // SH16_MM + 25182680U, // SH16_MMR6 + 25188174U, // SH64 + 25186460U, // SHE + 25186460U, // SHE_MM + 268452680U, // SHF_B + 268456335U, // SHF_H + 268460327U, // SHF_W + 22970U, // SHILO + 24591U, // SHILOV + 24591U, // SHILOV_MM + 22970U, // SHILO_MM + 268457622U, // SHLLV_PH + 268457622U, // SHLLV_PH_MM + 268453753U, // SHLLV_QB + 268453753U, // SHLLV_QB_MM + 268457559U, // SHLLV_S_PH + 268457559U, // SHLLV_S_PH_MM + 268461237U, // SHLLV_S_W + 268461237U, // SHLLV_S_W_MM + 268457350U, // SHLL_PH + 268457350U, // SHLL_PH_MM + 268453540U, // SHLL_QB + 268453540U, // SHLL_QB_MM + 268457472U, // SHLL_S_PH + 268457472U, // SHLL_S_PH_MM + 268461077U, // SHLL_S_W + 268461077U, // SHLL_S_W_MM + 268457612U, // SHRAV_PH + 268457612U, // SHRAV_PH_MM + 268453743U, // SHRAV_QB + 268453743U, // SHRAV_QB_MMR2 + 268457460U, // SHRAV_R_PH + 268457460U, // SHRAV_R_PH_MM + 268453641U, // SHRAV_R_QB + 268453641U, // SHRAV_R_QB_MMR2 + 268460832U, // SHRAV_R_W + 268460832U, // SHRAV_R_W_MM + 268457257U, // SHRA_PH + 268457257U, // SHRA_PH_MM + 268453463U, // SHRA_QB + 268453463U, // SHRA_QB_MMR2 + 268457425U, // SHRA_R_PH + 268457425U, // SHRA_R_PH_MM + 268453606U, // SHRA_R_QB + 268453606U, // SHRA_R_QB_MMR2 + 268460790U, // SHRA_R_W + 268460790U, // SHRA_R_W_MM + 268457642U, // SHRLV_PH + 268457642U, // SHRLV_PH_MMR2 + 268453773U, // SHRLV_QB + 268453773U, // SHRLV_QB_MM + 268457368U, // SHRL_PH + 268457368U, // SHRL_PH_MMR2 + 268453558U, // SHRL_QB + 268453558U, // SHRL_QB_MM + 25188174U, // SH_MM + 25188174U, // SH_MMR6 + 200865U, // SIGRIE + 200865U, // SIGRIE_MMR6 + 2701149023U, // SLDI_B + 2701150864U, // SLDI_D + 2701152678U, // SLDI_H + 2701156751U, // SLDI_W + 2701148965U, // SLD_B + 2701150571U, // SLD_D + 2701152620U, // SLD_H + 2701156528U, // SLD_W + 268458224U, // SLL + 268452349U, // SLL16_MM + 268452349U, // SLL16_MMR6 + 268458224U, // SLL64_32 + 268458224U, // SLL64_64 + 268452737U, // SLLI_B + 268454561U, // SLLI_D + 268456375U, // SLLI_H + 268460448U, // SLLI_W + 268460034U, // SLLV + 268460034U, // SLLV_MM + 268452886U, // SLL_B + 268454745U, // SLL_D + 268456491U, // SLL_H + 268458224U, // SLL_MM + 268458224U, // SLL_MMR6 + 268460590U, // SLL_W + 268459666U, // SLT + 268459666U, // SLT64 + 268459666U, // SLT_MM + 268457921U, // SLTi + 268457921U, // SLTi64 + 268457921U, // SLTi_MM + 268459822U, // SLTiu + 268459822U, // SLTiu64 + 268459822U, // SLTiu_MM + 268459908U, // SLTu + 268459908U, // SLTu64 + 268459908U, // SLTu_MM + 268456137U, // SNE + 268457842U, // SNEi + 2684371928U, // SPLATI_B + 2684373736U, // SPLATI_D + 2684375550U, // SPLATI_H + 2684379623U, // SPLATI_W + 2684372243U, // SPLAT_B + 2684374449U, // SPLAT_D + 2684375998U, // SPLAT_H + 2684380415U, // SPLAT_W + 268452558U, // SRA + 268452695U, // SRAI_B + 268454536U, // SRAI_D + 268456350U, // SRAI_H + 268460423U, // SRAI_W + 268452771U, // SRARI_B + 268454595U, // SRARI_D + 268456409U, // SRARI_H + 268460482U, // SRARI_W + 268452924U, // SRAR_B + 268454984U, // SRAR_D + 268456606U, // SRAR_H + 268460854U, // SRAR_W + 268460013U, // SRAV + 268460013U, // SRAV_MM + 268452622U, // SRA_B + 268454168U, // SRA_D + 268456277U, // SRA_H + 268452558U, // SRA_MM + 268460142U, // SRA_W + 268458252U, // SRL + 268452356U, // SRL16_MM + 268452356U, // SRL16_MMR6 + 268452745U, // SRLI_B + 268454569U, // SRLI_D + 268456383U, // SRLI_H + 268460456U, // SRLI_W + 268452789U, // SRLRI_B + 268454613U, // SRLRI_D + 268456427U, // SRLRI_H + 268460500U, // SRLRI_W + 268452940U, // SRLR_B + 268455000U, // SRLR_D + 268456622U, // SRLR_H + 268460870U, // SRLR_W + 268460041U, // SRLV + 268460041U, // SRLV_MM + 268452893U, // SRL_B + 268454770U, // SRL_D + 268456498U, // SRL_H + 268458252U, // SRL_MM + 268460615U, // SRL_W + 10671U, // SSNOP + 10671U, // SSNOP_MM + 10671U, // SSNOP_MMR6 + 25183542U, // ST_B + 25185889U, // ST_D + 25187297U, // ST_H + 25191776U, // ST_W + 268453802U, // SUB + 268457321U, // SUBQH_PH + 268457321U, // SUBQH_PH_MMR2 + 268457436U, // SUBQH_R_PH + 268457436U, // SUBQH_R_PH_MMR2 + 268460800U, // SUBQH_R_W + 268460800U, // SUBQH_R_W_MMR2 + 268460405U, // SUBQH_W + 268460405U, // SUBQH_W_MMR2 + 268457396U, // SUBQ_PH + 268457396U, // SUBQ_PH_MM + 268457493U, // SUBQ_S_PH + 268457493U, // SUBQ_S_PH_MM + 268461106U, // SUBQ_S_W + 268461106U, // SUBQ_S_W_MM + 268453296U, // SUBSUS_U_B + 268455715U, // SUBSUS_U_D + 268457103U, // SUBSUS_U_H + 268461594U, // SUBSUS_U_W + 268453099U, // SUBSUU_S_B + 268455288U, // SUBSUU_S_D + 268456843U, // SUBSUU_S_H + 268461216U, // SUBSUU_S_W + 268453061U, // SUBS_S_B + 268455228U, // SUBS_S_D + 268456805U, // SUBS_S_H + 268461156U, // SUBS_S_W + 268453276U, // SUBS_U_B + 268455695U, // SUBS_U_D + 268457083U, // SUBS_U_H + 268461574U, // SUBS_U_W + 268452430U, // SUBU16_MM + 268452430U, // SUBU16_MMR6 + 268453511U, // SUBUH_QB + 268453511U, // SUBUH_QB_MMR2 + 268453617U, // SUBUH_R_QB + 268453617U, // SUBUH_R_QB_MMR2 + 268459723U, // SUBU_MMR6 + 268457594U, // SUBU_PH + 268457594U, // SUBU_PH_MMR2 + 268453725U, // SUBU_QB + 268453725U, // SUBU_QB_MM + 268457537U, // SUBU_S_PH + 268457537U, // SUBU_S_PH_MMR2 + 268453664U, // SUBU_S_QB + 268453664U, // SUBU_S_QB_MM + 268452843U, // SUBVI_B + 268454651U, // SUBVI_D + 268456465U, // SUBVI_H + 268460538U, // SUBVI_W + 268453355U, // SUBV_B + 268455786U, // SUBV_D + 268457162U, // SUBV_H + 268461675U, // SUBV_W + 268453802U, // SUB_MM + 268453802U, // SUB_MMR6 + 268459723U, // SUBu + 268459723U, // SUBu_MM + 3774890155U, // SUXC1 + 3774890155U, // SUXC164 + 3774890155U, // SUXC1_MM + 25192158U, // SW + 25182827U, // SW16_MM + 25182827U, // SW16_MMR6 + 25192158U, // SW64 + 25182352U, // SWC1 + 25182352U, // SWC1_MM + 25182568U, // SWC2 + 25182568U, // SWC2_MMR6 + 25182568U, // SWC2_R6 + 25182613U, // SWC3 + 25192158U, // SWDSP + 25192158U, // SWDSP_MM + 25186562U, // SWE + 25186562U, // SWE_MM + 25188697U, // SWL + 25188697U, // SWL64 + 25186494U, // SWLE + 25186494U, // SWLE_MM + 25188697U, // SWL_MM + 49682U, // SWM16_MM + 49682U, // SWM16_MMR6 + 49422U, // SWM32_MM + 176183917U, // SWP_MM + 25189203U, // SWR + 25189203U, // SWR64 + 25186533U, // SWRE + 25186533U, // SWRE_MM + 25189203U, // SWR_MM + 25188946U, // SWSP_MM + 25192158U, // SWSP_MMR6 + 3774890169U, // SWXC1 + 3774890169U, // SWXC1_MM + 25192158U, // SW_MM + 25192158U, // SW_MMR6 + 223162U, // SYNC + 235352U, // SYNCI + 235352U, // SYNCI_MM + 235352U, // SYNCI_MMR6 + 223162U, // SYNC_MM + 215064U, // SYNC_MMR6 + 186580U, // SYSCALL + 366804U, // SYSCALL_MM + 0U, // Save16 + 0U, // SaveX16 + 25184163U, // SbRxRyOffMemX16 + 288589U, // SebRx16 + 288595U, // SehRx16 + 25188174U, // ShRxRyOffMemX16 + 268458224U, // SllX16 + 16801794U, // SllvRxRy16 + 24210U, // SltRxRy16 + 2952812481U, // SltiRxImm16 + 22465U, // SltiRxImmX16 + 2952814382U, // SltiuRxImm16 + 24366U, // SltiuRxImmX16 + 24452U, // SltuRxRy16 + 268452558U, // SraX16 + 16801773U, // SravRxRy16 + 268458252U, // SrlX16 + 16801801U, // SrlvRxRy16 + 268459723U, // SubuRxRyRz16 + 25192158U, // SwRxRyOffMemX16 + 25192158U, // SwRxSpImmX16 + 268458620U, // TEQ + 22447U, // TEQI + 22447U, // TEQI_MM + 268458620U, // TEQ_MM + 268456075U, // TGE + 22380U, // TGEI + 24359U, // TGEIU + 24359U, // TGEIU_MM + 22380U, // TGEI_MM + 268459776U, // TGEU + 268459776U, // TGEU_MM + 268456075U, // TGE_MM + 10719U, // TLBGINV + 10620U, // TLBGINVF + 10620U, // TLBGINVF_MM + 10719U, // TLBGINV_MM + 10665U, // TLBGP + 10665U, // TLBGP_MM + 10682U, // TLBGR + 10682U, // TLBGR_MM + 10635U, // TLBGWI + 10635U, // TLBGWI_MM + 10694U, // TLBGWR + 10694U, // TLBGWR_MM + 10712U, // TLBINV + 10612U, // TLBINVF + 10612U, // TLBINVF_MMR6 + 10712U, // TLBINV_MMR6 + 10660U, // TLBP + 10660U, // TLBP_MM + 10677U, // TLBR + 10677U, // TLBR_MM + 10629U, // TLBWI + 10629U, // TLBWI_MM + 10688U, // TLBWR + 10688U, // TLBWR_MM + 268459671U, // TLT + 22471U, // TLTI + 24373U, // TLTIU_MM + 22471U, // TLTI_MM + 268459914U, // TLTU + 268459914U, // TLTU_MM + 268459671U, // TLT_MM + 268456142U, // TNE + 22392U, // TNEI + 22392U, // TNEI_MM + 268456142U, // TNE_MM + 19213U, // TRUNC_L_D64 + 19213U, // TRUNC_L_D_MMR6 + 23591U, // TRUNC_L_S + 23591U, // TRUNC_L_S_MMR6 + 20388U, // TRUNC_W_D32 + 20388U, // TRUNC_W_D64 + 20388U, // TRUNC_W_D_MMR6 + 20388U, // TRUNC_W_MM + 23933U, // TRUNC_W_S + 23933U, // TRUNC_W_S_MM + 23933U, // TRUNC_W_S_MMR6 + 24373U, // TTLTIU + 26458U, // UDIV + 26458U, // UDIV_MM + 268459836U, // V3MULU + 268451901U, // VMM0 + 268459851U, // VMULU + 285229895U, // VSHF_B + 285231720U, // VSHF_D + 285233550U, // VSHF_H + 285237542U, // VSHF_W + 10707U, // WAIT + 368263U, // WAIT_MM + 368263U, // WAIT_MMR6 + 83909172U, // WRDSP + 192961076U, // WRDSP_MM + 23340U, // WRPGPR_MMR6 + 21776U, // WSBH + 21776U, // WSBH_MM + 21776U, // WSBH_MMR6 + 268458783U, // XOR + 10043952U, // XOR16_MM + 10043952U, // XOR16_MMR6 + 268458783U, // XOR64 + 268452806U, // XORI_B + 268457909U, // XORI_MMR6 + 268458783U, // XOR_MM + 268458783U, // XOR_MMR6 + 268459977U, // XOR_V + 268457909U, // XORi + 268457909U, // XORi64 + 268457909U, // XORi_MM + 16800543U, // XorRxRxRy16 + 20535U, // YIELD + }; + + static const uint16_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ABSMacro + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // AND_V_D_PSEUDO + 0U, // AND_V_H_PSEUDO + 0U, // AND_V_W_PSEUDO + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I16_POSTRA + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I32_POSTRA + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I64_POSTRA + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_CMP_SWAP_I8_POSTRA + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I16_POSTRA + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I32_POSTRA + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I64_POSTRA + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_ADD_I8_POSTRA + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I16_POSTRA + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I32_POSTRA + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I64_POSTRA + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_AND_I8_POSTRA + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I16_POSTRA + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I32_POSTRA + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I64_POSTRA + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MAX_I8_POSTRA + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I16_POSTRA + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I32_POSTRA + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I64_POSTRA + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_MIN_I8_POSTRA + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I16_POSTRA + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I32_POSTRA + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I64_POSTRA + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_NAND_I8_POSTRA + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I16_POSTRA + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I32_POSTRA + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I64_POSTRA + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_OR_I8_POSTRA + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I16_POSTRA + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I32_POSTRA + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I64_POSTRA + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_SUB_I8_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I16_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I32_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I64_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMAX_I8_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I16_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I32_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I64_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_UMIN_I8_POSTRA + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I16_POSTRA + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I32_POSTRA + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I64_POSTRA + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_LOAD_XOR_I8_POSTRA + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I16_POSTRA + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I32_POSTRA + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I64_POSTRA + 0U, // ATOMIC_SWAP_I8 + 0U, // ATOMIC_SWAP_I8_POSTRA + 0U, // B + 0U, // BAL_BR + 0U, // BAL_BR_MM + 0U, // BEQLImmMacro + 0U, // BGE + 0U, // BGEImmMacro + 0U, // BGEL + 0U, // BGELImmMacro + 0U, // BGEU + 0U, // BGEUImmMacro + 0U, // BGEUL + 0U, // BGEULImmMacro + 0U, // BGT + 0U, // BGTImmMacro + 0U, // BGTL + 0U, // BGTLImmMacro + 0U, // BGTU + 0U, // BGTUImmMacro + 0U, // BGTUL + 0U, // BGTULImmMacro + 0U, // BLE + 0U, // BLEImmMacro + 0U, // BLEL + 0U, // BLELImmMacro + 0U, // BLEU + 0U, // BLEUImmMacro + 0U, // BLEUL + 0U, // BLEULImmMacro + 0U, // BLT + 0U, // BLTImmMacro + 0U, // BLTL + 0U, // BLTLImmMacro + 0U, // BLTU + 0U, // BLTUImmMacro + 0U, // BLTUL + 0U, // BLTULImmMacro + 0U, // BNELImmMacro + 0U, // BPOSGE32_PSEUDO + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 0U, // BSEL_W_PSEUDO + 0U, // B_MM + 0U, // B_MMR6_Pseudo + 0U, // B_MM_Pseudo + 0U, // BeqImm + 0U, // BneImm + 0U, // BteqzT8CmpX16 + 0U, // BteqzT8CmpiX16 + 0U, // BteqzT8SltX16 + 0U, // BteqzT8SltiX16 + 0U, // BteqzT8SltiuX16 + 0U, // BteqzT8SltuX16 + 0U, // BtnezT8CmpX16 + 0U, // BtnezT8CmpiX16 + 0U, // BtnezT8SltX16 + 0U, // BtnezT8SltiX16 + 0U, // BtnezT8SltiuX16 + 0U, // BtnezT8SltuX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 0U, // CFTC1 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 0U, // CTTC1 + 0U, // Constant32 + 0U, // DMULImmMacro + 0U, // DMULMacro + 0U, // DMULOMacro + 0U, // DMULOUMacro + 0U, // DROL + 0U, // DROLImm + 0U, // DROR + 0U, // DRORImm + 0U, // DSDivIMacro + 0U, // DSDivMacro + 0U, // DSRemIMacro + 0U, // DSRemMacro + 0U, // DUDivIMacro + 0U, // DUDivMacro + 0U, // DURemIMacro + 0U, // DURemMacro + 0U, // ERet + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 0U, // FABS_W + 0U, // FEXP2_D_1_PSEUDO + 0U, // FEXP2_W_1_PSEUDO + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 0U, // GotPrologue16 + 0U, // INSERT_B_VIDX64_PSEUDO + 0U, // INSERT_B_VIDX_PSEUDO + 0U, // INSERT_D_VIDX64_PSEUDO + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX64_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX64_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 0U, // INSERT_H_VIDX64_PSEUDO + 0U, // INSERT_H_VIDX_PSEUDO + 0U, // INSERT_W_VIDX64_PSEUDO + 0U, // INSERT_W_VIDX_PSEUDO + 0U, // JALR64Pseudo + 0U, // JALRHB64Pseudo + 0U, // JALRHBPseudo + 0U, // JALRPseudo + 0U, // JAL_MMR6 + 0U, // JalOneReg + 0U, // JalTwoReg + 0U, // LDMacro + 0U, // LDR_D + 0U, // LDR_W + 0U, // LD_F16 + 0U, // LOAD_ACC128 + 0U, // LOAD_ACC64 + 0U, // LOAD_ACC64DSP + 0U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_ADDiu2Op + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_DADDiu2Op + 0U, // LONG_BRANCH_LUi + 0U, // LONG_BRANCH_LUi2Op + 0U, // LONG_BRANCH_LUi2Op_64 + 0U, // LWM_MM + 0U, // LoadAddrImm32 + 0U, // LoadAddrImm64 + 0U, // LoadAddrReg32 + 0U, // LoadAddrReg64 + 0U, // LoadImm32 + 0U, // LoadImm64 + 0U, // LoadImmDoubleFGR + 0U, // LoadImmDoubleFGR_32 + 0U, // LoadImmDoubleGPR + 0U, // LoadImmSingleFGR + 0U, // LoadImmSingleGPR + 0U, // LwConstant32 + 0U, // MFTACX + 2U, // MFTC0 + 0U, // MFTC1 + 0U, // MFTDSP + 0U, // MFTGPR + 0U, // MFTHC1 + 0U, // MFTHI + 0U, // MFTLO + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 0U, // MSA_FP_EXTEND_D_PSEUDO + 0U, // MSA_FP_EXTEND_W_PSEUDO + 0U, // MSA_FP_ROUND_D_PSEUDO + 0U, // MSA_FP_ROUND_W_PSEUDO + 0U, // MTTACX + 0U, // MTTC0 + 0U, // MTTC1 + 0U, // MTTDSP + 0U, // MTTGPR + 0U, // MTTHC1 + 0U, // MTTHI + 0U, // MTTLO + 0U, // MULImmMacro + 0U, // MULOMacro + 0U, // MULOUMacro + 0U, // MultRxRy16 + 0U, // MultRxRyRz16 + 0U, // MultuRxRy16 + 0U, // MultuRxRyRz16 + 0U, // NOP + 0U, // NORImm + 0U, // NORImm64 + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 0U, // PseudoCVT_D32_W + 0U, // PseudoCVT_D64_L + 0U, // PseudoCVT_D64_W + 0U, // PseudoCVT_S_L + 0U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoD_SELECT_I + 0U, // PseudoD_SELECT_I64 + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoIndirectBranch64R6 + 0U, // PseudoIndirectBranchR6 + 0U, // PseudoIndirectBranch_MM + 0U, // PseudoIndirectBranch_MMR6 + 0U, // PseudoIndirectHazardBranch + 0U, // PseudoIndirectHazardBranch64 + 0U, // PseudoIndrectHazardBranch64R6 + 0U, // PseudoIndrectHazardBranchR6 + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMADDU_MM + 0U, // PseudoMADD_MM + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFHI_MM + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMFLO_MM + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMSUBU_MM + 0U, // PseudoMSUB_MM + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMTLOHI_MM + 0U, // PseudoMULT + 0U, // PseudoMULT_MM + 0U, // PseudoMULTu + 0U, // PseudoMULTu_MM + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 0U, // PseudoTRUNC_W_D + 0U, // PseudoTRUNC_W_D32 + 0U, // PseudoTRUNC_W_S + 0U, // PseudoUDIV + 0U, // ROL + 0U, // ROLImm + 0U, // ROR + 0U, // RORImm + 0U, // RetRA + 0U, // RetRA16 + 0U, // SDC1_M1 + 0U, // SDIV_MM_Pseudo + 0U, // SDMacro + 0U, // SDivIMacro + 0U, // SDivMacro + 0U, // SEQIMacro + 0U, // SEQMacro + 0U, // SGE + 0U, // SGEImm + 0U, // SGEImm64 + 0U, // SGEU + 0U, // SGEUImm + 0U, // SGEUImm64 + 0U, // SGTImm + 0U, // SGTImm64 + 0U, // SGTUImm + 0U, // SGTUImm64 + 0U, // SLE + 0U, // SLEImm + 0U, // SLEImm64 + 0U, // SLEU + 0U, // SLEUImm + 0U, // SLEUImm64 + 0U, // SLTImm64 + 0U, // SLTUImm64 + 0U, // SNEIMacro + 0U, // SNEMacro + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 0U, // SRemIMacro + 0U, // SRemMacro + 0U, // STORE_ACC128 + 0U, // STORE_ACC64 + 0U, // STORE_ACC64DSP + 0U, // STORE_CCOND_DSP + 0U, // STR_D + 0U, // STR_W + 0U, // ST_F16 + 0U, // SWM_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 0U, // SaaAddr + 0U, // SaadAddr + 0U, // SelBeqZ + 0U, // SelBneZ + 0U, // SelTBteqZCmp + 0U, // SelTBteqZCmpi + 0U, // SelTBteqZSlt + 0U, // SelTBteqZSlti + 0U, // SelTBteqZSltiu + 0U, // SelTBteqZSltu + 0U, // SelTBtneZCmp + 0U, // SelTBtneZCmpi + 0U, // SelTBtneZSlt + 0U, // SelTBtneZSlti + 0U, // SelTBtneZSltiu + 0U, // SelTBtneZSltu + 0U, // SltCCRxRy16 + 0U, // SltiCCRxImmX16 + 0U, // SltiuCCRxImmX16 + 0U, // SltuCCRxRy16 + 0U, // SltuRxRyRz16 + 0U, // TAILCALL + 0U, // TAILCALL64R6REG + 0U, // TAILCALLHB64R6REG + 0U, // TAILCALLHBR6REG + 0U, // TAILCALLR6REG + 0U, // TAILCALLREG + 0U, // TAILCALLREG64 + 0U, // TAILCALLREGHB + 0U, // TAILCALLREGHB64 + 0U, // TAILCALLREG_MM + 0U, // TAILCALLREG_MMR6 + 0U, // TAILCALL_MM + 0U, // TAILCALL_MMR6 + 0U, // TRAP + 0U, // TRAP_MM + 0U, // UDIV_MM_Pseudo + 0U, // UDivIMacro + 0U, // UDivMacro + 0U, // URemIMacro + 0U, // URemMacro + 0U, // Ulh + 0U, // Ulhu + 0U, // Ulw + 0U, // Ush + 0U, // Usw + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 0U, // ABSQ_S_PH + 0U, // ABSQ_S_PH_MM + 0U, // ABSQ_S_QB + 0U, // ABSQ_S_QB_MMR2 + 0U, // ABSQ_S_W + 0U, // ABSQ_S_W_MM + 0U, // ADD + 0U, // ADDIUPC + 0U, // ADDIUPC_MM + 0U, // ADDIUPC_MMR6 + 0U, // ADDIUR1SP_MM + 0U, // ADDIUR2_MM + 0U, // ADDIUS5_MM + 0U, // ADDIUSP_MM + 0U, // ADDIU_MMR6 + 0U, // ADDQH_PH + 0U, // ADDQH_PH_MMR2 + 0U, // ADDQH_R_PH + 0U, // ADDQH_R_PH_MMR2 + 0U, // ADDQH_R_W + 0U, // ADDQH_R_W_MMR2 + 0U, // ADDQH_W + 0U, // ADDQH_W_MMR2 + 0U, // ADDQ_PH + 0U, // ADDQ_PH_MM + 0U, // ADDQ_S_PH + 0U, // ADDQ_S_PH_MM + 0U, // ADDQ_S_W + 0U, // ADDQ_S_W_MM + 0U, // ADDR_PS64 + 0U, // ADDSC + 0U, // ADDSC_MM + 0U, // ADDS_A_B + 0U, // ADDS_A_D + 0U, // ADDS_A_H + 0U, // ADDS_A_W + 0U, // ADDS_S_B + 0U, // ADDS_S_D + 0U, // ADDS_S_H + 0U, // ADDS_S_W + 0U, // ADDS_U_B + 0U, // ADDS_U_D + 0U, // ADDS_U_H + 0U, // ADDS_U_W + 0U, // ADDU16_MM + 0U, // ADDU16_MMR6 + 0U, // ADDUH_QB + 0U, // ADDUH_QB_MMR2 + 0U, // ADDUH_R_QB + 0U, // ADDUH_R_QB_MMR2 + 0U, // ADDU_MMR6 + 0U, // ADDU_PH + 0U, // ADDU_PH_MMR2 + 0U, // ADDU_QB + 0U, // ADDU_QB_MM + 0U, // ADDU_S_PH + 0U, // ADDU_S_PH_MMR2 + 0U, // ADDU_S_QB + 0U, // ADDU_S_QB_MM + 4U, // ADDVI_B + 4U, // ADDVI_D + 4U, // ADDVI_H + 4U, // ADDVI_W + 0U, // ADDV_B + 0U, // ADDV_D + 0U, // ADDV_H + 0U, // ADDV_W + 0U, // ADDWC + 0U, // ADDWC_MM + 0U, // ADD_A_B + 0U, // ADD_A_D + 0U, // ADD_A_H + 0U, // ADD_A_W + 0U, // ADD_MM + 0U, // ADD_MMR6 + 0U, // ADDi + 0U, // ADDi_MM + 0U, // ADDiu + 0U, // ADDiu_MM + 0U, // ADDu + 0U, // ADDu_MM + 64U, // ALIGN + 64U, // ALIGN_MMR6 + 0U, // ALUIPC + 0U, // ALUIPC_MMR6 + 0U, // AND + 0U, // AND16_MM + 0U, // AND16_MMR6 + 0U, // AND64 + 0U, // ANDI16_MM + 0U, // ANDI16_MMR6 + 6U, // ANDI_B + 8U, // ANDI_MMR6 + 0U, // AND_MM + 0U, // AND_MMR6 + 0U, // AND_V + 8U, // ANDi + 8U, // ANDi64 + 8U, // ANDi_MM + 4U, // APPEND + 4U, // APPEND_MMR2 + 0U, // ASUB_S_B + 0U, // ASUB_S_D + 0U, // ASUB_S_H + 0U, // ASUB_S_W + 0U, // ASUB_U_B + 0U, // ASUB_U_D + 0U, // ASUB_U_H + 0U, // ASUB_U_W + 8U, // AUI + 0U, // AUIPC + 0U, // AUIPC_MMR6 + 8U, // AUI_MMR6 + 0U, // AVER_S_B + 0U, // AVER_S_D + 0U, // AVER_S_H + 0U, // AVER_S_W + 0U, // AVER_U_B + 0U, // AVER_U_D + 0U, // AVER_U_H + 0U, // AVER_U_W + 0U, // AVE_S_B + 0U, // AVE_S_D + 0U, // AVE_S_H + 0U, // AVE_S_W + 0U, // AVE_U_B + 0U, // AVE_U_D + 0U, // AVE_U_H + 0U, // AVE_U_W + 0U, // AddiuRxImmX16 + 0U, // AddiuRxPcImmX16 + 0U, // AddiuRxRxImm16 + 0U, // AddiuRxRxImmX16 + 0U, // AddiuRxRyOffMemX16 + 0U, // AddiuSpImm16 + 0U, // AddiuSpImmX16 + 0U, // AdduRxRyRz16 + 0U, // AndRxRxRy16 + 0U, // B16_MM + 0U, // BADDu + 0U, // BAL + 0U, // BALC + 0U, // BALC_MMR6 + 10U, // BALIGN + 10U, // BALIGN_MMR2 + 0U, // BBIT0 + 0U, // BBIT032 + 0U, // BBIT1 + 0U, // BBIT132 + 0U, // BC + 0U, // BC0F + 0U, // BC0T + 0U, // BC16_MMR6 + 0U, // BC1EQZ + 0U, // BC1EQZC_MMR6 + 0U, // BC1F + 0U, // BC1FL + 0U, // BC1F_MM + 0U, // BC1NEZ + 0U, // BC1NEZC_MMR6 + 0U, // BC1T + 0U, // BC1TL + 0U, // BC1T_MM + 0U, // BC2EQZ + 0U, // BC2EQZC_MMR6 + 0U, // BC2F + 0U, // BC2FL + 0U, // BC2NEZ + 0U, // BC2NEZC_MMR6 + 0U, // BC2T + 0U, // BC2TL + 0U, // BC3F + 0U, // BC3FL + 0U, // BC3T + 0U, // BC3TL + 2U, // BCLRI_B + 12U, // BCLRI_D + 14U, // BCLRI_H + 4U, // BCLRI_W + 0U, // BCLR_B + 0U, // BCLR_D + 0U, // BCLR_H + 0U, // BCLR_W + 0U, // BC_MMR6 + 0U, // BEQ + 0U, // BEQ64 + 0U, // BEQC + 0U, // BEQC64 + 0U, // BEQC_MMR6 + 0U, // BEQL + 0U, // BEQZ16_MM + 0U, // BEQZALC + 0U, // BEQZALC_MMR6 + 0U, // BEQZC + 0U, // BEQZC16_MMR6 + 0U, // BEQZC64 + 0U, // BEQZC_MM + 0U, // BEQZC_MMR6 + 0U, // BEQ_MM + 0U, // BGEC + 0U, // BGEC64 + 0U, // BGEC_MMR6 + 0U, // BGEUC + 0U, // BGEUC64 + 0U, // BGEUC_MMR6 + 0U, // BGEZ + 0U, // BGEZ64 + 0U, // BGEZAL + 0U, // BGEZALC + 0U, // BGEZALC_MMR6 + 0U, // BGEZALL + 0U, // BGEZALS_MM + 0U, // BGEZAL_MM + 0U, // BGEZC + 0U, // BGEZC64 + 0U, // BGEZC_MMR6 + 0U, // BGEZL + 0U, // BGEZ_MM + 0U, // BGTZ + 0U, // BGTZ64 + 0U, // BGTZALC + 0U, // BGTZALC_MMR6 + 0U, // BGTZC + 0U, // BGTZC64 + 0U, // BGTZC_MMR6 + 0U, // BGTZL + 0U, // BGTZ_MM + 16U, // BINSLI_B + 18U, // BINSLI_D + 20U, // BINSLI_H + 22U, // BINSLI_W + 24U, // BINSL_B + 24U, // BINSL_D + 24U, // BINSL_H + 24U, // BINSL_W + 16U, // BINSRI_B + 18U, // BINSRI_D + 20U, // BINSRI_H + 22U, // BINSRI_W + 24U, // BINSR_B + 24U, // BINSR_D + 24U, // BINSR_H + 24U, // BINSR_W + 0U, // BITREV + 0U, // BITREV_MM + 0U, // BITSWAP + 0U, // BITSWAP_MMR6 + 0U, // BLEZ + 0U, // BLEZ64 + 0U, // BLEZALC + 0U, // BLEZALC_MMR6 + 0U, // BLEZC + 0U, // BLEZC64 + 0U, // BLEZC_MMR6 + 0U, // BLEZL + 0U, // BLEZ_MM + 0U, // BLTC + 0U, // BLTC64 + 0U, // BLTC_MMR6 + 0U, // BLTUC + 0U, // BLTUC64 + 0U, // BLTUC_MMR6 + 0U, // BLTZ + 0U, // BLTZ64 + 0U, // BLTZAL + 0U, // BLTZALC + 0U, // BLTZALC_MMR6 + 0U, // BLTZALL + 0U, // BLTZALS_MM + 0U, // BLTZAL_MM + 0U, // BLTZC + 0U, // BLTZC64 + 0U, // BLTZC_MMR6 + 0U, // BLTZL + 0U, // BLTZ_MM + 26U, // BMNZI_B + 24U, // BMNZ_V + 26U, // BMZI_B + 24U, // BMZ_V + 0U, // BNE + 0U, // BNE64 + 0U, // BNEC + 0U, // BNEC64 + 0U, // BNEC_MMR6 + 2U, // BNEGI_B + 12U, // BNEGI_D + 14U, // BNEGI_H + 4U, // BNEGI_W + 0U, // BNEG_B + 0U, // BNEG_D + 0U, // BNEG_H + 0U, // BNEG_W + 0U, // BNEL + 0U, // BNEZ16_MM + 0U, // BNEZALC + 0U, // BNEZALC_MMR6 + 0U, // BNEZC + 0U, // BNEZC16_MMR6 + 0U, // BNEZC64 + 0U, // BNEZC_MM + 0U, // BNEZC_MMR6 + 0U, // BNE_MM + 0U, // BNVC + 0U, // BNVC_MMR6 + 0U, // BNZ_B + 0U, // BNZ_D + 0U, // BNZ_H + 0U, // BNZ_V + 0U, // BNZ_W + 0U, // BOVC + 0U, // BOVC_MMR6 + 0U, // BPOSGE32 + 0U, // BPOSGE32C_MMR3 + 0U, // BPOSGE32_MM + 0U, // BREAK + 0U, // BREAK16_MM + 0U, // BREAK16_MMR6 + 0U, // BREAK_MM + 0U, // BREAK_MMR6 + 26U, // BSELI_B + 24U, // BSEL_V + 2U, // BSETI_B + 12U, // BSETI_D + 14U, // BSETI_H + 4U, // BSETI_W + 0U, // BSET_B + 0U, // BSET_D + 0U, // BSET_H + 0U, // BSET_W + 0U, // BZ_B + 0U, // BZ_D + 0U, // BZ_H + 0U, // BZ_V + 0U, // BZ_W + 0U, // BeqzRxImm16 + 0U, // BeqzRxImmX16 + 0U, // Bimm16 + 0U, // BimmX16 + 0U, // BnezRxImm16 + 0U, // BnezRxImmX16 + 0U, // Break16 + 0U, // Bteqz16 + 0U, // BteqzX16 + 0U, // Btnez16 + 0U, // BtnezX16 + 0U, // CACHE + 0U, // CACHEE + 0U, // CACHEE_MM + 0U, // CACHE_MM + 0U, // CACHE_MMR6 + 0U, // CACHE_R6 + 0U, // CEIL_L_D64 + 0U, // CEIL_L_D_MMR6 + 0U, // CEIL_L_S + 0U, // CEIL_L_S_MMR6 + 0U, // CEIL_W_D32 + 0U, // CEIL_W_D64 + 0U, // CEIL_W_D_MMR6 + 0U, // CEIL_W_MM + 0U, // CEIL_W_S + 0U, // CEIL_W_S_MM + 0U, // CEIL_W_S_MMR6 + 0U, // CEQI_B + 0U, // CEQI_D + 0U, // CEQI_H + 0U, // CEQI_W + 0U, // CEQ_B + 0U, // CEQ_D + 0U, // CEQ_H + 0U, // CEQ_W + 0U, // CFC1 + 0U, // CFC1_MM + 0U, // CFC2_MM + 0U, // CFCMSA + 580U, // CINS + 580U, // CINS32 + 580U, // CINS64_32 + 580U, // CINS_i32 + 0U, // CLASS_D + 0U, // CLASS_D_MMR6 + 0U, // CLASS_S + 0U, // CLASS_S_MMR6 + 0U, // CLEI_S_B + 0U, // CLEI_S_D + 0U, // CLEI_S_H + 0U, // CLEI_S_W + 4U, // CLEI_U_B + 4U, // CLEI_U_D + 4U, // CLEI_U_H + 4U, // CLEI_U_W + 0U, // CLE_S_B + 0U, // CLE_S_D + 0U, // CLE_S_H + 0U, // CLE_S_W + 0U, // CLE_U_B + 0U, // CLE_U_D + 0U, // CLE_U_H + 0U, // CLE_U_W + 0U, // CLO + 0U, // CLO_MM + 0U, // CLO_MMR6 + 0U, // CLO_R6 + 0U, // CLTI_S_B + 0U, // CLTI_S_D + 0U, // CLTI_S_H + 0U, // CLTI_S_W + 4U, // CLTI_U_B + 4U, // CLTI_U_D + 4U, // CLTI_U_H + 4U, // CLTI_U_W + 0U, // CLT_S_B + 0U, // CLT_S_D + 0U, // CLT_S_H + 0U, // CLT_S_W + 0U, // CLT_U_B + 0U, // CLT_U_D + 0U, // CLT_U_H + 0U, // CLT_U_W + 0U, // CLZ + 0U, // CLZ_MM + 0U, // CLZ_MMR6 + 0U, // CLZ_R6 + 0U, // CMPGDU_EQ_QB + 0U, // CMPGDU_EQ_QB_MMR2 + 0U, // CMPGDU_LE_QB + 0U, // CMPGDU_LE_QB_MMR2 + 0U, // CMPGDU_LT_QB + 0U, // CMPGDU_LT_QB_MMR2 + 0U, // CMPGU_EQ_QB + 0U, // CMPGU_EQ_QB_MM + 0U, // CMPGU_LE_QB + 0U, // CMPGU_LE_QB_MM + 0U, // CMPGU_LT_QB + 0U, // CMPGU_LT_QB_MM + 0U, // CMPU_EQ_QB + 0U, // CMPU_EQ_QB_MM + 0U, // CMPU_LE_QB + 0U, // CMPU_LE_QB_MM + 0U, // CMPU_LT_QB + 0U, // CMPU_LT_QB_MM + 0U, // CMP_AF_D_MMR6 + 0U, // CMP_AF_S_MMR6 + 0U, // CMP_EQ_D + 0U, // CMP_EQ_D_MMR6 + 0U, // CMP_EQ_PH + 0U, // CMP_EQ_PH_MM + 0U, // CMP_EQ_S + 0U, // CMP_EQ_S_MMR6 + 0U, // CMP_F_D + 0U, // CMP_F_S + 0U, // CMP_LE_D + 0U, // CMP_LE_D_MMR6 + 0U, // CMP_LE_PH + 0U, // CMP_LE_PH_MM + 0U, // CMP_LE_S + 0U, // CMP_LE_S_MMR6 + 0U, // CMP_LT_D + 0U, // CMP_LT_D_MMR6 + 0U, // CMP_LT_PH + 0U, // CMP_LT_PH_MM + 0U, // CMP_LT_S + 0U, // CMP_LT_S_MMR6 + 0U, // CMP_SAF_D + 0U, // CMP_SAF_D_MMR6 + 0U, // CMP_SAF_S + 0U, // CMP_SAF_S_MMR6 + 0U, // CMP_SEQ_D + 0U, // CMP_SEQ_D_MMR6 + 0U, // CMP_SEQ_S + 0U, // CMP_SEQ_S_MMR6 + 0U, // CMP_SLE_D + 0U, // CMP_SLE_D_MMR6 + 0U, // CMP_SLE_S + 0U, // CMP_SLE_S_MMR6 + 0U, // CMP_SLT_D + 0U, // CMP_SLT_D_MMR6 + 0U, // CMP_SLT_S + 0U, // CMP_SLT_S_MMR6 + 0U, // CMP_SUEQ_D + 0U, // CMP_SUEQ_D_MMR6 + 0U, // CMP_SUEQ_S + 0U, // CMP_SUEQ_S_MMR6 + 0U, // CMP_SULE_D + 0U, // CMP_SULE_D_MMR6 + 0U, // CMP_SULE_S + 0U, // CMP_SULE_S_MMR6 + 0U, // CMP_SULT_D + 0U, // CMP_SULT_D_MMR6 + 0U, // CMP_SULT_S + 0U, // CMP_SULT_S_MMR6 + 0U, // CMP_SUN_D + 0U, // CMP_SUN_D_MMR6 + 0U, // CMP_SUN_S + 0U, // CMP_SUN_S_MMR6 + 0U, // CMP_UEQ_D + 0U, // CMP_UEQ_D_MMR6 + 0U, // CMP_UEQ_S + 0U, // CMP_UEQ_S_MMR6 + 0U, // CMP_ULE_D + 0U, // CMP_ULE_D_MMR6 + 0U, // CMP_ULE_S + 0U, // CMP_ULE_S_MMR6 + 0U, // CMP_ULT_D + 0U, // CMP_ULT_D_MMR6 + 0U, // CMP_ULT_S + 0U, // CMP_ULT_S_MMR6 + 0U, // CMP_UN_D + 0U, // CMP_UN_D_MMR6 + 0U, // CMP_UN_S + 0U, // CMP_UN_S_MMR6 + 142U, // COPY_S_B + 156U, // COPY_S_D + 130U, // COPY_S_H + 138U, // COPY_S_W + 142U, // COPY_U_B + 130U, // COPY_U_H + 138U, // COPY_U_W + 0U, // CRC32B + 0U, // CRC32CB + 0U, // CRC32CD + 0U, // CRC32CH + 0U, // CRC32CW + 0U, // CRC32D + 0U, // CRC32H + 0U, // CRC32W + 0U, // CTC1 + 0U, // CTC1_MM + 0U, // CTC2_MM + 0U, // CTCMSA + 0U, // CVT_D32_S + 0U, // CVT_D32_S_MM + 0U, // CVT_D32_W + 0U, // CVT_D32_W_MM + 0U, // CVT_D64_L + 0U, // CVT_D64_S + 0U, // CVT_D64_S_MM + 0U, // CVT_D64_W + 0U, // CVT_D64_W_MM + 0U, // CVT_D_L_MMR6 + 0U, // CVT_L_D64 + 0U, // CVT_L_D64_MM + 0U, // CVT_L_D_MMR6 + 0U, // CVT_L_S + 0U, // CVT_L_S_MM + 0U, // CVT_L_S_MMR6 + 0U, // CVT_PS_PW64 + 0U, // CVT_PS_S64 + 0U, // CVT_PW_PS64 + 0U, // CVT_S_D32 + 0U, // CVT_S_D32_MM + 0U, // CVT_S_D64 + 0U, // CVT_S_D64_MM + 0U, // CVT_S_L + 0U, // CVT_S_L_MMR6 + 0U, // CVT_S_PL64 + 0U, // CVT_S_PU64 + 0U, // CVT_S_W + 0U, // CVT_S_W_MM + 0U, // CVT_S_W_MMR6 + 0U, // CVT_W_D32 + 0U, // CVT_W_D32_MM + 0U, // CVT_W_D64 + 0U, // CVT_W_D64_MM + 0U, // CVT_W_S + 0U, // CVT_W_S_MM + 0U, // CVT_W_S_MMR6 + 0U, // C_EQ_D32 + 0U, // C_EQ_D32_MM + 0U, // C_EQ_D64 + 0U, // C_EQ_D64_MM + 0U, // C_EQ_S + 0U, // C_EQ_S_MM + 0U, // C_F_D32 + 0U, // C_F_D32_MM + 0U, // C_F_D64 + 0U, // C_F_D64_MM + 0U, // C_F_S + 0U, // C_F_S_MM + 0U, // C_LE_D32 + 0U, // C_LE_D32_MM + 0U, // C_LE_D64 + 0U, // C_LE_D64_MM + 0U, // C_LE_S + 0U, // C_LE_S_MM + 0U, // C_LT_D32 + 0U, // C_LT_D32_MM + 0U, // C_LT_D64 + 0U, // C_LT_D64_MM + 0U, // C_LT_S + 0U, // C_LT_S_MM + 0U, // C_NGE_D32 + 0U, // C_NGE_D32_MM + 0U, // C_NGE_D64 + 0U, // C_NGE_D64_MM + 0U, // C_NGE_S + 0U, // C_NGE_S_MM + 0U, // C_NGLE_D32 + 0U, // C_NGLE_D32_MM + 0U, // C_NGLE_D64 + 0U, // C_NGLE_D64_MM + 0U, // C_NGLE_S + 0U, // C_NGLE_S_MM + 0U, // C_NGL_D32 + 0U, // C_NGL_D32_MM + 0U, // C_NGL_D64 + 0U, // C_NGL_D64_MM + 0U, // C_NGL_S + 0U, // C_NGL_S_MM + 0U, // C_NGT_D32 + 0U, // C_NGT_D32_MM + 0U, // C_NGT_D64 + 0U, // C_NGT_D64_MM + 0U, // C_NGT_S + 0U, // C_NGT_S_MM + 0U, // C_OLE_D32 + 0U, // C_OLE_D32_MM + 0U, // C_OLE_D64 + 0U, // C_OLE_D64_MM + 0U, // C_OLE_S + 0U, // C_OLE_S_MM + 0U, // C_OLT_D32 + 0U, // C_OLT_D32_MM + 0U, // C_OLT_D64 + 0U, // C_OLT_D64_MM + 0U, // C_OLT_S + 0U, // C_OLT_S_MM + 0U, // C_SEQ_D32 + 0U, // C_SEQ_D32_MM + 0U, // C_SEQ_D64 + 0U, // C_SEQ_D64_MM + 0U, // C_SEQ_S + 0U, // C_SEQ_S_MM + 0U, // C_SF_D32 + 0U, // C_SF_D32_MM + 0U, // C_SF_D64 + 0U, // C_SF_D64_MM + 0U, // C_SF_S + 0U, // C_SF_S_MM + 0U, // C_UEQ_D32 + 0U, // C_UEQ_D32_MM + 0U, // C_UEQ_D64 + 0U, // C_UEQ_D64_MM + 0U, // C_UEQ_S + 0U, // C_UEQ_S_MM + 0U, // C_ULE_D32 + 0U, // C_ULE_D32_MM + 0U, // C_ULE_D64 + 0U, // C_ULE_D64_MM + 0U, // C_ULE_S + 0U, // C_ULE_S_MM + 0U, // C_ULT_D32 + 0U, // C_ULT_D32_MM + 0U, // C_ULT_D64 + 0U, // C_ULT_D64_MM + 0U, // C_ULT_S + 0U, // C_ULT_S_MM + 0U, // C_UN_D32 + 0U, // C_UN_D32_MM + 0U, // C_UN_D64 + 0U, // C_UN_D64_MM + 0U, // C_UN_S + 0U, // C_UN_S_MM + 0U, // CmpRxRy16 + 0U, // CmpiRxImm16 + 0U, // CmpiRxImmX16 + 0U, // DADD + 0U, // DADDi + 0U, // DADDiu + 0U, // DADDu + 8U, // DAHI + 1088U, // DALIGN + 8U, // DATI + 8U, // DAUI + 0U, // DBITSWAP + 0U, // DCLO + 0U, // DCLO_R6 + 0U, // DCLZ + 0U, // DCLZ_R6 + 0U, // DDIV + 0U, // DDIVU + 0U, // DERET + 0U, // DERET_MM + 0U, // DERET_MMR6 + 1612U, // DEXT + 2124U, // DEXT64_32 + 2628U, // DEXTM + 222U, // DEXTU + 0U, // DI + 3148U, // DINS + 3652U, // DINSM + 286U, // DINSU + 0U, // DIV + 0U, // DIVU + 0U, // DIVU_MMR6 + 0U, // DIV_MMR6 + 0U, // DIV_S_B + 0U, // DIV_S_D + 0U, // DIV_S_H + 0U, // DIV_S_W + 0U, // DIV_U_B + 0U, // DIV_U_D + 0U, // DIV_U_H + 0U, // DIV_U_W + 0U, // DI_MM + 0U, // DI_MMR6 + 4160U, // DLSA + 4160U, // DLSA_R6 + 2U, // DMFC0 + 0U, // DMFC1 + 2U, // DMFC2 + 0U, // DMFC2_OCTEON + 2U, // DMFGC0 + 0U, // DMOD + 0U, // DMODU + 0U, // DMT + 0U, // DMTC0 + 0U, // DMTC1 + 0U, // DMTC2 + 0U, // DMTC2_OCTEON + 0U, // DMTGC0 + 0U, // DMUH + 0U, // DMUHU + 0U, // DMUL + 0U, // DMULT + 0U, // DMULTu + 0U, // DMULU + 0U, // DMUL_R6 + 0U, // DOTP_S_D + 0U, // DOTP_S_H + 0U, // DOTP_S_W + 0U, // DOTP_U_D + 0U, // DOTP_U_H + 0U, // DOTP_U_W + 24U, // DPADD_S_D + 24U, // DPADD_S_H + 24U, // DPADD_S_W + 24U, // DPADD_U_D + 24U, // DPADD_U_H + 24U, // DPADD_U_W + 0U, // DPAQX_SA_W_PH + 0U, // DPAQX_SA_W_PH_MMR2 + 0U, // DPAQX_S_W_PH + 0U, // DPAQX_S_W_PH_MMR2 + 0U, // DPAQ_SA_L_W + 0U, // DPAQ_SA_L_W_MM + 0U, // DPAQ_S_W_PH + 0U, // DPAQ_S_W_PH_MM + 0U, // DPAU_H_QBL + 0U, // DPAU_H_QBL_MM + 0U, // DPAU_H_QBR + 0U, // DPAU_H_QBR_MM + 0U, // DPAX_W_PH + 0U, // DPAX_W_PH_MMR2 + 0U, // DPA_W_PH + 0U, // DPA_W_PH_MMR2 + 0U, // DPOP + 0U, // DPSQX_SA_W_PH + 0U, // DPSQX_SA_W_PH_MMR2 + 0U, // DPSQX_S_W_PH + 0U, // DPSQX_S_W_PH_MMR2 + 0U, // DPSQ_SA_L_W + 0U, // DPSQ_SA_L_W_MM + 0U, // DPSQ_S_W_PH + 0U, // DPSQ_S_W_PH_MM + 24U, // DPSUB_S_D + 24U, // DPSUB_S_H + 24U, // DPSUB_S_W + 24U, // DPSUB_U_D + 24U, // DPSUB_U_H + 24U, // DPSUB_U_W + 0U, // DPSU_H_QBL + 0U, // DPSU_H_QBL_MM + 0U, // DPSU_H_QBR + 0U, // DPSU_H_QBR_MM + 0U, // DPSX_W_PH + 0U, // DPSX_W_PH_MMR2 + 0U, // DPS_W_PH + 0U, // DPS_W_PH_MMR2 + 12U, // DROTR + 4U, // DROTR32 + 0U, // DROTRV + 0U, // DSBH + 0U, // DSDIV + 0U, // DSHD + 12U, // DSLL + 4U, // DSLL32 + 0U, // DSLL64_32 + 0U, // DSLLV + 12U, // DSRA + 4U, // DSRA32 + 0U, // DSRAV + 12U, // DSRL + 4U, // DSRL32 + 0U, // DSRLV + 0U, // DSUB + 0U, // DSUBu + 0U, // DUDIV + 0U, // DVP + 0U, // DVPE + 0U, // DVP_MMR6 + 0U, // DivRxRy16 + 0U, // DivuRxRy16 + 0U, // EHB + 0U, // EHB_MM + 0U, // EHB_MMR6 + 0U, // EI + 0U, // EI_MM + 0U, // EI_MMR6 + 0U, // EMT + 0U, // ERET + 0U, // ERETNC + 0U, // ERETNC_MMR6 + 0U, // ERET_MM + 0U, // ERET_MMR6 + 0U, // EVP + 0U, // EVPE + 0U, // EVP_MMR6 + 2116U, // EXT + 4U, // EXTP + 4U, // EXTPDP + 0U, // EXTPDPV + 0U, // EXTPDPV_MM + 4U, // EXTPDP_MM + 0U, // EXTPV + 0U, // EXTPV_MM + 4U, // EXTP_MM + 0U, // EXTRV_RS_W + 0U, // EXTRV_RS_W_MM + 0U, // EXTRV_R_W + 0U, // EXTRV_R_W_MM + 0U, // EXTRV_S_H + 0U, // EXTRV_S_H_MM + 0U, // EXTRV_W + 0U, // EXTRV_W_MM + 4U, // EXTR_RS_W + 4U, // EXTR_RS_W_MM + 4U, // EXTR_R_W + 4U, // EXTR_R_W_MM + 4U, // EXTR_S_H + 4U, // EXTR_S_H_MM + 4U, // EXTR_W + 4U, // EXTR_W_MM + 580U, // EXTS + 580U, // EXTS32 + 2116U, // EXT_MM + 2116U, // EXT_MMR6 + 0U, // FABS_D32 + 0U, // FABS_D32_MM + 0U, // FABS_D64 + 0U, // FABS_D64_MM + 0U, // FABS_S + 0U, // FABS_S_MM + 0U, // FADD_D + 0U, // FADD_D32 + 0U, // FADD_D32_MM + 0U, // FADD_D64 + 0U, // FADD_D64_MM + 0U, // FADD_PS64 + 0U, // FADD_S + 0U, // FADD_S_MM + 32U, // FADD_S_MMR6 + 0U, // FADD_W + 0U, // FCAF_D + 0U, // FCAF_W + 0U, // FCEQ_D + 0U, // FCEQ_W + 0U, // FCLASS_D + 0U, // FCLASS_W + 0U, // FCLE_D + 0U, // FCLE_W + 0U, // FCLT_D + 0U, // FCLT_W + 0U, // FCMP_D32 + 0U, // FCMP_D32_MM + 0U, // FCMP_D64 + 0U, // FCMP_S32 + 0U, // FCMP_S32_MM + 0U, // FCNE_D + 0U, // FCNE_W + 0U, // FCOR_D + 0U, // FCOR_W + 0U, // FCUEQ_D + 0U, // FCUEQ_W + 0U, // FCULE_D + 0U, // FCULE_W + 0U, // FCULT_D + 0U, // FCULT_W + 0U, // FCUNE_D + 0U, // FCUNE_W + 0U, // FCUN_D + 0U, // FCUN_W + 0U, // FDIV_D + 0U, // FDIV_D32 + 0U, // FDIV_D32_MM + 0U, // FDIV_D64 + 0U, // FDIV_D64_MM + 0U, // FDIV_S + 0U, // FDIV_S_MM + 32U, // FDIV_S_MMR6 + 0U, // FDIV_W + 0U, // FEXDO_H + 0U, // FEXDO_W + 0U, // FEXP2_D + 0U, // FEXP2_W + 0U, // FEXUPL_D + 0U, // FEXUPL_W + 0U, // FEXUPR_D + 0U, // FEXUPR_W + 0U, // FFINT_S_D + 0U, // FFINT_S_W + 0U, // FFINT_U_D + 0U, // FFINT_U_W + 0U, // FFQL_D + 0U, // FFQL_W + 0U, // FFQR_D + 0U, // FFQR_W + 0U, // FILL_B + 0U, // FILL_D + 0U, // FILL_H + 0U, // FILL_W + 0U, // FLOG2_D + 0U, // FLOG2_W + 0U, // FLOOR_L_D64 + 0U, // FLOOR_L_D_MMR6 + 0U, // FLOOR_L_S + 0U, // FLOOR_L_S_MMR6 + 0U, // FLOOR_W_D32 + 0U, // FLOOR_W_D64 + 0U, // FLOOR_W_D_MMR6 + 0U, // FLOOR_W_MM + 0U, // FLOOR_W_S + 0U, // FLOOR_W_S_MM + 0U, // FLOOR_W_S_MMR6 + 24U, // FMADD_D + 24U, // FMADD_W + 0U, // FMAX_A_D + 0U, // FMAX_A_W + 0U, // FMAX_D + 0U, // FMAX_W + 0U, // FMIN_A_D + 0U, // FMIN_A_W + 0U, // FMIN_D + 0U, // FMIN_W + 0U, // FMOV_D32 + 0U, // FMOV_D32_MM + 0U, // FMOV_D64 + 0U, // FMOV_D64_MM + 0U, // FMOV_D_MMR6 + 0U, // FMOV_S + 0U, // FMOV_S_MM + 0U, // FMOV_S_MMR6 + 24U, // FMSUB_D + 24U, // FMSUB_W + 0U, // FMUL_D + 0U, // FMUL_D32 + 0U, // FMUL_D32_MM + 0U, // FMUL_D64 + 0U, // FMUL_D64_MM + 0U, // FMUL_PS64 + 0U, // FMUL_S + 0U, // FMUL_S_MM + 32U, // FMUL_S_MMR6 + 0U, // FMUL_W + 0U, // FNEG_D32 + 0U, // FNEG_D32_MM + 0U, // FNEG_D64 + 0U, // FNEG_D64_MM + 0U, // FNEG_S + 0U, // FNEG_S_MM + 0U, // FNEG_S_MMR6 + 0U, // FORK + 0U, // FRCP_D + 0U, // FRCP_W + 0U, // FRINT_D + 0U, // FRINT_W + 0U, // FRSQRT_D + 0U, // FRSQRT_W + 0U, // FSAF_D + 0U, // FSAF_W + 0U, // FSEQ_D + 0U, // FSEQ_W + 0U, // FSLE_D + 0U, // FSLE_W + 0U, // FSLT_D + 0U, // FSLT_W + 0U, // FSNE_D + 0U, // FSNE_W + 0U, // FSOR_D + 0U, // FSOR_W + 0U, // FSQRT_D + 0U, // FSQRT_D32 + 0U, // FSQRT_D32_MM + 0U, // FSQRT_D64 + 0U, // FSQRT_D64_MM + 0U, // FSQRT_S + 0U, // FSQRT_S_MM + 0U, // FSQRT_W + 0U, // FSUB_D + 0U, // FSUB_D32 + 0U, // FSUB_D32_MM + 0U, // FSUB_D64 + 0U, // FSUB_D64_MM + 0U, // FSUB_PS64 + 0U, // FSUB_S + 0U, // FSUB_S_MM + 32U, // FSUB_S_MMR6 + 0U, // FSUB_W + 0U, // FSUEQ_D + 0U, // FSUEQ_W + 0U, // FSULE_D + 0U, // FSULE_W + 0U, // FSULT_D + 0U, // FSULT_W + 0U, // FSUNE_D + 0U, // FSUNE_W + 0U, // FSUN_D + 0U, // FSUN_W + 0U, // FTINT_S_D + 0U, // FTINT_S_W + 0U, // FTINT_U_D + 0U, // FTINT_U_W + 0U, // FTQ_H + 0U, // FTQ_W + 0U, // FTRUNC_S_D + 0U, // FTRUNC_S_W + 0U, // FTRUNC_U_D + 0U, // FTRUNC_U_W + 0U, // GINVI + 0U, // GINVI_MMR6 + 0U, // GINVT + 0U, // GINVT_MMR6 + 0U, // HADD_S_D + 0U, // HADD_S_H + 0U, // HADD_S_W + 0U, // HADD_U_D + 0U, // HADD_U_H + 0U, // HADD_U_W + 0U, // HSUB_S_D + 0U, // HSUB_S_H + 0U, // HSUB_S_W + 0U, // HSUB_U_D + 0U, // HSUB_U_H + 0U, // HSUB_U_W + 0U, // HYPCALL + 0U, // HYPCALL_MM + 0U, // ILVEV_B + 0U, // ILVEV_D + 0U, // ILVEV_H + 0U, // ILVEV_W + 0U, // ILVL_B + 0U, // ILVL_D + 0U, // ILVL_H + 0U, // ILVL_W + 0U, // ILVOD_B + 0U, // ILVOD_D + 0U, // ILVOD_H + 0U, // ILVOD_W + 0U, // ILVR_B + 0U, // ILVR_D + 0U, // ILVR_H + 0U, // ILVR_W + 3140U, // INS + 0U, // INSERT_B + 0U, // INSERT_D + 0U, // INSERT_H + 0U, // INSERT_W + 0U, // INSV + 0U, // INSVE_B + 0U, // INSVE_D + 0U, // INSVE_H + 0U, // INSVE_W + 0U, // INSV_MM + 3140U, // INS_MM + 3140U, // INS_MMR6 + 0U, // J + 0U, // JAL + 0U, // JALR + 0U, // JALR16_MM + 0U, // JALR64 + 0U, // JALRC16_MMR6 + 0U, // JALRC_HB_MMR6 + 0U, // JALRC_MMR6 + 0U, // JALRS16_MM + 0U, // JALRS_MM + 0U, // JALR_HB + 0U, // JALR_HB64 + 0U, // JALR_MM + 0U, // JALS_MM + 0U, // JALX + 0U, // JALX_MM + 0U, // JAL_MM + 0U, // JIALC + 0U, // JIALC64 + 0U, // JIALC_MMR6 + 0U, // JIC + 0U, // JIC64 + 0U, // JIC_MMR6 + 0U, // JR + 0U, // JR16_MM + 0U, // JR64 + 0U, // JRADDIUSP + 0U, // JRC16_MM + 0U, // JRC16_MMR6 + 0U, // JRCADDIUSP_MMR6 + 0U, // JR_HB + 0U, // JR_HB64 + 0U, // JR_HB64_R6 + 0U, // JR_HB_R6 + 0U, // JR_MM + 0U, // J_MM + 0U, // Jal16 + 0U, // JalB16 + 0U, // JrRa16 + 0U, // JrcRa16 + 0U, // JrcRx16 + 0U, // JumpLinkReg16 + 0U, // LB + 0U, // LB64 + 0U, // LBE + 0U, // LBE_MM + 0U, // LBU16_MM + 0U, // LBUX + 0U, // LBUX_MM + 0U, // LBU_MMR6 + 0U, // LB_MM + 0U, // LB_MMR6 + 0U, // LBu + 0U, // LBu64 + 0U, // LBuE + 0U, // LBuE_MM + 0U, // LBu_MM + 0U, // LD + 0U, // LDC1 + 0U, // LDC164 + 0U, // LDC1_D64_MMR6 + 0U, // LDC1_MM + 0U, // LDC2 + 0U, // LDC2_MMR6 + 0U, // LDC2_R6 + 0U, // LDC3 + 0U, // LDI_B + 0U, // LDI_D + 0U, // LDI_H + 0U, // LDI_W + 0U, // LDL + 0U, // LDPC + 0U, // LDR + 0U, // LDXC1 + 0U, // LDXC164 + 0U, // LD_B + 0U, // LD_D + 0U, // LD_H + 0U, // LD_W + 0U, // LEA_ADDiu + 0U, // LEA_ADDiu64 + 0U, // LEA_ADDiu_MM + 0U, // LH + 0U, // LH64 + 0U, // LHE + 0U, // LHE_MM + 0U, // LHU16_MM + 0U, // LHX + 0U, // LHX_MM + 0U, // LH_MM + 0U, // LHu + 0U, // LHu64 + 0U, // LHuE + 0U, // LHuE_MM + 0U, // LHu_MM + 0U, // LI16_MM + 0U, // LI16_MMR6 + 0U, // LL + 0U, // LL64 + 0U, // LL64_R6 + 0U, // LLD + 0U, // LLD_R6 + 0U, // LLE + 0U, // LLE_MM + 0U, // LL_MM + 0U, // LL_MMR6 + 0U, // LL_R6 + 4160U, // LSA + 0U, // LSA_MMR6 + 4160U, // LSA_R6 + 0U, // LUI_MMR6 + 0U, // LUXC1 + 0U, // LUXC164 + 0U, // LUXC1_MM + 0U, // LUi + 0U, // LUi64 + 0U, // LUi_MM + 0U, // LW + 0U, // LW16_MM + 0U, // LW64 + 0U, // LWC1 + 0U, // LWC1_MM + 0U, // LWC2 + 0U, // LWC2_MMR6 + 0U, // LWC2_R6 + 0U, // LWC3 + 0U, // LWDSP + 0U, // LWDSP_MM + 0U, // LWE + 0U, // LWE_MM + 0U, // LWGP_MM + 0U, // LWL + 0U, // LWL64 + 0U, // LWLE + 0U, // LWLE_MM + 0U, // LWL_MM + 0U, // LWM16_MM + 0U, // LWM16_MMR6 + 0U, // LWM32_MM + 0U, // LWPC + 0U, // LWPC_MMR6 + 0U, // LWP_MM + 0U, // LWR + 0U, // LWR64 + 0U, // LWRE + 0U, // LWRE_MM + 0U, // LWR_MM + 0U, // LWSP_MM + 0U, // LWUPC + 0U, // LWU_MM + 0U, // LWX + 0U, // LWXC1 + 0U, // LWXC1_MM + 0U, // LWXS_MM + 0U, // LWX_MM + 0U, // LW_MM + 0U, // LW_MMR6 + 0U, // LWu + 0U, // LbRxRyOffMemX16 + 0U, // LbuRxRyOffMemX16 + 0U, // LhRxRyOffMemX16 + 0U, // LhuRxRyOffMemX16 + 0U, // LiRxImm16 + 0U, // LiRxImmAlignX16 + 0U, // LiRxImmX16 + 0U, // LwRxPcTcp16 + 0U, // LwRxPcTcpX16 + 0U, // LwRxRyOffMemX16 + 0U, // LwRxSpImmX16 + 0U, // MADD + 24U, // MADDF_D + 24U, // MADDF_D_MMR6 + 24U, // MADDF_S + 24U, // MADDF_S_MMR6 + 24U, // MADDR_Q_H + 24U, // MADDR_Q_W + 0U, // MADDU + 0U, // MADDU_DSP + 0U, // MADDU_DSP_MM + 0U, // MADDU_MM + 24U, // MADDV_B + 24U, // MADDV_D + 24U, // MADDV_H + 24U, // MADDV_W + 4672U, // MADD_D32 + 4672U, // MADD_D32_MM + 4672U, // MADD_D64 + 0U, // MADD_DSP + 0U, // MADD_DSP_MM + 0U, // MADD_MM + 24U, // MADD_Q_H + 24U, // MADD_Q_W + 4672U, // MADD_S + 4672U, // MADD_S_MM + 0U, // MAQ_SA_W_PHL + 0U, // MAQ_SA_W_PHL_MM + 0U, // MAQ_SA_W_PHR + 0U, // MAQ_SA_W_PHR_MM + 0U, // MAQ_S_W_PHL + 0U, // MAQ_S_W_PHL_MM + 0U, // MAQ_S_W_PHR + 0U, // MAQ_S_W_PHR_MM + 0U, // MAXA_D + 0U, // MAXA_D_MMR6 + 0U, // MAXA_S + 0U, // MAXA_S_MMR6 + 0U, // MAXI_S_B + 0U, // MAXI_S_D + 0U, // MAXI_S_H + 0U, // MAXI_S_W + 4U, // MAXI_U_B + 4U, // MAXI_U_D + 4U, // MAXI_U_H + 4U, // MAXI_U_W + 0U, // MAX_A_B + 0U, // MAX_A_D + 0U, // MAX_A_H + 0U, // MAX_A_W + 0U, // MAX_D + 0U, // MAX_D_MMR6 + 0U, // MAX_S + 0U, // MAX_S_B + 0U, // MAX_S_D + 0U, // MAX_S_H + 0U, // MAX_S_MMR6 + 0U, // MAX_S_W + 0U, // MAX_U_B + 0U, // MAX_U_D + 0U, // MAX_U_H + 0U, // MAX_U_W + 2U, // MFC0 + 2U, // MFC0_MMR6 + 0U, // MFC1 + 0U, // MFC1_D64 + 0U, // MFC1_MM + 0U, // MFC1_MMR6 + 2U, // MFC2 + 0U, // MFC2_MMR6 + 2U, // MFGC0 + 2U, // MFGC0_MM + 2U, // MFHC0_MMR6 + 0U, // MFHC1_D32 + 0U, // MFHC1_D32_MM + 0U, // MFHC1_D64 + 0U, // MFHC1_D64_MM + 0U, // MFHC2_MMR6 + 2U, // MFHGC0 + 2U, // MFHGC0_MM + 0U, // MFHI + 0U, // MFHI16_MM + 0U, // MFHI64 + 0U, // MFHI_DSP + 0U, // MFHI_DSP_MM + 0U, // MFHI_MM + 0U, // MFLO + 0U, // MFLO16_MM + 0U, // MFLO64 + 0U, // MFLO_DSP + 0U, // MFLO_DSP_MM + 0U, // MFLO_MM + 9308U, // MFTR + 0U, // MINA_D + 0U, // MINA_D_MMR6 + 0U, // MINA_S + 0U, // MINA_S_MMR6 + 0U, // MINI_S_B + 0U, // MINI_S_D + 0U, // MINI_S_H + 0U, // MINI_S_W + 4U, // MINI_U_B + 4U, // MINI_U_D + 4U, // MINI_U_H + 4U, // MINI_U_W + 0U, // MIN_A_B + 0U, // MIN_A_D + 0U, // MIN_A_H + 0U, // MIN_A_W + 0U, // MIN_D + 0U, // MIN_D_MMR6 + 0U, // MIN_S + 0U, // MIN_S_B + 0U, // MIN_S_D + 0U, // MIN_S_H + 0U, // MIN_S_MMR6 + 0U, // MIN_S_W + 0U, // MIN_U_B + 0U, // MIN_U_D + 0U, // MIN_U_H + 0U, // MIN_U_W + 0U, // MOD + 0U, // MODSUB + 0U, // MODSUB_MM + 0U, // MODU + 0U, // MODU_MMR6 + 0U, // MOD_MMR6 + 0U, // MOD_S_B + 0U, // MOD_S_D + 0U, // MOD_S_H + 0U, // MOD_S_W + 0U, // MOD_U_B + 0U, // MOD_U_D + 0U, // MOD_U_H + 0U, // MOD_U_W + 0U, // MOVE16_MM + 0U, // MOVE16_MMR6 + 4672U, // MOVEP_MM + 4672U, // MOVEP_MMR6 + 0U, // MOVE_V + 0U, // MOVF_D32 + 0U, // MOVF_D32_MM + 0U, // MOVF_D64 + 0U, // MOVF_I + 0U, // MOVF_I64 + 0U, // MOVF_I_MM + 0U, // MOVF_S + 0U, // MOVF_S_MM + 0U, // MOVN_I64_D64 + 0U, // MOVN_I64_I + 0U, // MOVN_I64_I64 + 0U, // MOVN_I64_S + 0U, // MOVN_I_D32 + 0U, // MOVN_I_D32_MM + 0U, // MOVN_I_D64 + 0U, // MOVN_I_I + 0U, // MOVN_I_I64 + 0U, // MOVN_I_MM + 0U, // MOVN_I_S + 0U, // MOVN_I_S_MM + 0U, // MOVT_D32 + 0U, // MOVT_D32_MM + 0U, // MOVT_D64 + 0U, // MOVT_I + 0U, // MOVT_I64 + 0U, // MOVT_I_MM + 0U, // MOVT_S + 0U, // MOVT_S_MM + 0U, // MOVZ_I64_D64 + 0U, // MOVZ_I64_I + 0U, // MOVZ_I64_I64 + 0U, // MOVZ_I64_S + 0U, // MOVZ_I_D32 + 0U, // MOVZ_I_D32_MM + 0U, // MOVZ_I_D64 + 0U, // MOVZ_I_I + 0U, // MOVZ_I_I64 + 0U, // MOVZ_I_MM + 0U, // MOVZ_I_S + 0U, // MOVZ_I_S_MM + 0U, // MSUB + 24U, // MSUBF_D + 24U, // MSUBF_D_MMR6 + 24U, // MSUBF_S + 24U, // MSUBF_S_MMR6 + 24U, // MSUBR_Q_H + 24U, // MSUBR_Q_W + 0U, // MSUBU + 0U, // MSUBU_DSP + 0U, // MSUBU_DSP_MM + 0U, // MSUBU_MM + 24U, // MSUBV_B + 24U, // MSUBV_D + 24U, // MSUBV_H + 24U, // MSUBV_W + 4672U, // MSUB_D32 + 4672U, // MSUB_D32_MM + 4672U, // MSUB_D64 + 0U, // MSUB_DSP + 0U, // MSUB_DSP_MM + 0U, // MSUB_MM + 24U, // MSUB_Q_H + 24U, // MSUB_Q_W + 4672U, // MSUB_S + 4672U, // MSUB_S_MM + 0U, // MTC0 + 0U, // MTC0_MMR6 + 0U, // MTC1 + 0U, // MTC1_D64 + 0U, // MTC1_D64_MM + 0U, // MTC1_MM + 0U, // MTC1_MMR6 + 0U, // MTC2 + 0U, // MTC2_MMR6 + 0U, // MTGC0 + 0U, // MTGC0_MM + 0U, // MTHC0_MMR6 + 0U, // MTHC1_D32 + 0U, // MTHC1_D32_MM + 0U, // MTHC1_D64 + 0U, // MTHC1_D64_MM + 0U, // MTHC2_MMR6 + 0U, // MTHGC0 + 0U, // MTHGC0_MM + 0U, // MTHI + 0U, // MTHI64 + 0U, // MTHI_DSP + 0U, // MTHI_DSP_MM + 0U, // MTHI_MM + 0U, // MTHLIP + 0U, // MTHLIP_MM + 0U, // MTLO + 0U, // MTLO64 + 0U, // MTLO_DSP + 0U, // MTLO_DSP_MM + 0U, // MTLO_MM + 0U, // MTM0 + 0U, // MTM1 + 0U, // MTM2 + 0U, // MTP0 + 0U, // MTP1 + 0U, // MTP2 + 1U, // MTTR + 0U, // MUH + 0U, // MUHU + 0U, // MUHU_MMR6 + 0U, // MUH_MMR6 + 0U, // MUL + 0U, // MULEQ_S_W_PHL + 0U, // MULEQ_S_W_PHL_MM + 0U, // MULEQ_S_W_PHR + 0U, // MULEQ_S_W_PHR_MM + 0U, // MULEU_S_PH_QBL + 0U, // MULEU_S_PH_QBL_MM + 0U, // MULEU_S_PH_QBR + 0U, // MULEU_S_PH_QBR_MM + 0U, // MULQ_RS_PH + 0U, // MULQ_RS_PH_MM + 0U, // MULQ_RS_W + 0U, // MULQ_RS_W_MMR2 + 0U, // MULQ_S_PH + 0U, // MULQ_S_PH_MMR2 + 0U, // MULQ_S_W + 0U, // MULQ_S_W_MMR2 + 0U, // MULR_PS64 + 0U, // MULR_Q_H + 0U, // MULR_Q_W + 0U, // MULSAQ_S_W_PH + 0U, // MULSAQ_S_W_PH_MM + 0U, // MULSA_W_PH + 0U, // MULSA_W_PH_MMR2 + 0U, // MULT + 0U, // MULTU_DSP + 0U, // MULTU_DSP_MM + 0U, // MULT_DSP + 0U, // MULT_DSP_MM + 0U, // MULT_MM + 0U, // MULTu + 0U, // MULTu_MM + 0U, // MULU + 0U, // MULU_MMR6 + 0U, // MULV_B + 0U, // MULV_D + 0U, // MULV_H + 0U, // MULV_W + 0U, // MUL_MM + 0U, // MUL_MMR6 + 0U, // MUL_PH + 0U, // MUL_PH_MMR2 + 0U, // MUL_Q_H + 0U, // MUL_Q_W + 0U, // MUL_R6 + 0U, // MUL_S_PH + 0U, // MUL_S_PH_MMR2 + 0U, // Mfhi16 + 0U, // Mflo16 + 0U, // Move32R16 + 0U, // MoveR3216 + 0U, // NLOC_B + 0U, // NLOC_D + 0U, // NLOC_H + 0U, // NLOC_W + 0U, // NLZC_B + 0U, // NLZC_D + 0U, // NLZC_H + 0U, // NLZC_W + 4672U, // NMADD_D32 + 4672U, // NMADD_D32_MM + 4672U, // NMADD_D64 + 4672U, // NMADD_S + 4672U, // NMADD_S_MM + 4672U, // NMSUB_D32 + 4672U, // NMSUB_D32_MM + 4672U, // NMSUB_D64 + 4672U, // NMSUB_S + 4672U, // NMSUB_S_MM + 0U, // NOR + 0U, // NOR64 + 6U, // NORI_B + 0U, // NOR_MM + 0U, // NOR_MMR6 + 0U, // NOR_V + 0U, // NOT16_MM + 0U, // NOT16_MMR6 + 0U, // NegRxRy16 + 0U, // NotRxRy16 + 0U, // OR + 0U, // OR16_MM + 0U, // OR16_MMR6 + 0U, // OR64 + 6U, // ORI_B + 8U, // ORI_MMR6 + 0U, // OR_MM + 0U, // OR_MMR6 + 0U, // OR_V + 8U, // ORi + 8U, // ORi64 + 8U, // ORi_MM + 0U, // OrRxRxRy16 + 0U, // PACKRL_PH + 0U, // PACKRL_PH_MM + 0U, // PAUSE + 0U, // PAUSE_MM + 0U, // PAUSE_MMR6 + 0U, // PCKEV_B + 0U, // PCKEV_D + 0U, // PCKEV_H + 0U, // PCKEV_W + 0U, // PCKOD_B + 0U, // PCKOD_D + 0U, // PCKOD_H + 0U, // PCKOD_W + 0U, // PCNT_B + 0U, // PCNT_D + 0U, // PCNT_H + 0U, // PCNT_W + 0U, // PICK_PH + 0U, // PICK_PH_MM + 0U, // PICK_QB + 0U, // PICK_QB_MM + 0U, // PLL_PS64 + 0U, // PLU_PS64 + 0U, // POP + 0U, // PRECEQU_PH_QBL + 0U, // PRECEQU_PH_QBLA + 0U, // PRECEQU_PH_QBLA_MM + 0U, // PRECEQU_PH_QBL_MM + 0U, // PRECEQU_PH_QBR + 0U, // PRECEQU_PH_QBRA + 0U, // PRECEQU_PH_QBRA_MM + 0U, // PRECEQU_PH_QBR_MM + 0U, // PRECEQ_W_PHL + 0U, // PRECEQ_W_PHL_MM + 0U, // PRECEQ_W_PHR + 0U, // PRECEQ_W_PHR_MM + 0U, // PRECEU_PH_QBL + 0U, // PRECEU_PH_QBLA + 0U, // PRECEU_PH_QBLA_MM + 0U, // PRECEU_PH_QBL_MM + 0U, // PRECEU_PH_QBR + 0U, // PRECEU_PH_QBRA + 0U, // PRECEU_PH_QBRA_MM + 0U, // PRECEU_PH_QBR_MM + 0U, // PRECRQU_S_QB_PH + 0U, // PRECRQU_S_QB_PH_MM + 0U, // PRECRQ_PH_W + 0U, // PRECRQ_PH_W_MM + 0U, // PRECRQ_QB_PH + 0U, // PRECRQ_QB_PH_MM + 0U, // PRECRQ_RS_PH_W + 0U, // PRECRQ_RS_PH_W_MM + 0U, // PRECR_QB_PH + 0U, // PRECR_QB_PH_MMR2 + 4U, // PRECR_SRA_PH_W + 4U, // PRECR_SRA_PH_W_MMR2 + 4U, // PRECR_SRA_R_PH_W + 4U, // PRECR_SRA_R_PH_W_MMR2 + 0U, // PREF + 0U, // PREFE + 0U, // PREFE_MM + 0U, // PREFX_MM + 0U, // PREF_MM + 0U, // PREF_MMR6 + 0U, // PREF_R6 + 4U, // PREPEND + 4U, // PREPEND_MMR2 + 0U, // PUL_PS64 + 0U, // PUU_PS64 + 0U, // RADDU_W_QB + 0U, // RADDU_W_QB_MM + 0U, // RDDSP + 0U, // RDDSP_MM + 6U, // RDHWR + 6U, // RDHWR64 + 6U, // RDHWR_MM + 2U, // RDHWR_MMR6 + 0U, // RDPGPR_MMR6 + 0U, // RECIP_D32 + 0U, // RECIP_D32_MM + 0U, // RECIP_D64 + 0U, // RECIP_D64_MM + 0U, // RECIP_S + 0U, // RECIP_S_MM + 0U, // REPLV_PH + 0U, // REPLV_PH_MM + 0U, // REPLV_QB + 0U, // REPLV_QB_MM + 0U, // REPL_PH + 0U, // REPL_PH_MM + 0U, // REPL_QB + 0U, // REPL_QB_MM + 0U, // RINT_D + 0U, // RINT_D_MMR6 + 0U, // RINT_S + 0U, // RINT_S_MMR6 + 4U, // ROTR + 0U, // ROTRV + 0U, // ROTRV_MM + 4U, // ROTR_MM + 0U, // ROUND_L_D64 + 0U, // ROUND_L_D_MMR6 + 0U, // ROUND_L_S + 0U, // ROUND_L_S_MMR6 + 0U, // ROUND_W_D32 + 0U, // ROUND_W_D64 + 0U, // ROUND_W_D_MMR6 + 0U, // ROUND_W_MM + 0U, // ROUND_W_S + 0U, // ROUND_W_S_MM + 0U, // ROUND_W_S_MMR6 + 0U, // RSQRT_D32 + 0U, // RSQRT_D32_MM + 0U, // RSQRT_D64 + 0U, // RSQRT_D64_MM + 0U, // RSQRT_S + 0U, // RSQRT_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 0U, // SAA + 0U, // SAAD + 2U, // SAT_S_B + 12U, // SAT_S_D + 14U, // SAT_S_H + 4U, // SAT_S_W + 2U, // SAT_U_B + 12U, // SAT_U_D + 14U, // SAT_U_H + 4U, // SAT_U_W + 0U, // SB + 0U, // SB16_MM + 0U, // SB16_MMR6 + 0U, // SB64 + 0U, // SBE + 0U, // SBE_MM + 0U, // SB_MM + 0U, // SB_MMR6 + 0U, // SC + 0U, // SC64 + 0U, // SC64_R6 + 0U, // SCD + 0U, // SCD_R6 + 0U, // SCE + 0U, // SCE_MM + 0U, // SC_MM + 0U, // SC_MMR6 + 0U, // SC_R6 + 0U, // SD + 0U, // SDBBP + 0U, // SDBBP16_MM + 0U, // SDBBP16_MMR6 + 0U, // SDBBP_MM + 0U, // SDBBP_MMR6 + 0U, // SDBBP_R6 + 0U, // SDC1 + 0U, // SDC164 + 0U, // SDC1_D64_MMR6 + 0U, // SDC1_MM + 0U, // SDC2 + 0U, // SDC2_MMR6 + 0U, // SDC2_R6 + 0U, // SDC3 + 0U, // SDIV + 0U, // SDIV_MM + 0U, // SDL + 0U, // SDR + 0U, // SDXC1 + 0U, // SDXC164 + 0U, // SEB + 0U, // SEB64 + 0U, // SEB_MM + 0U, // SEH + 0U, // SEH64 + 0U, // SEH_MM + 0U, // SELEQZ + 0U, // SELEQZ64 + 0U, // SELEQZ_D + 0U, // SELEQZ_D_MMR6 + 0U, // SELEQZ_MMR6 + 0U, // SELEQZ_S + 0U, // SELEQZ_S_MMR6 + 0U, // SELNEZ + 0U, // SELNEZ64 + 0U, // SELNEZ_D + 0U, // SELNEZ_D_MMR6 + 0U, // SELNEZ_MMR6 + 0U, // SELNEZ_S + 0U, // SELNEZ_S_MMR6 + 24U, // SEL_D + 24U, // SEL_D_MMR6 + 24U, // SEL_S + 24U, // SEL_S_MMR6 + 0U, // SEQ + 0U, // SEQi + 0U, // SH + 0U, // SH16_MM + 0U, // SH16_MMR6 + 0U, // SH64 + 0U, // SHE + 0U, // SHE_MM + 6U, // SHF_B + 6U, // SHF_H + 6U, // SHF_W + 0U, // SHILO + 0U, // SHILOV + 0U, // SHILOV_MM + 0U, // SHILO_MM + 0U, // SHLLV_PH + 0U, // SHLLV_PH_MM + 0U, // SHLLV_QB + 0U, // SHLLV_QB_MM + 0U, // SHLLV_S_PH + 0U, // SHLLV_S_PH_MM + 0U, // SHLLV_S_W + 0U, // SHLLV_S_W_MM + 14U, // SHLL_PH + 14U, // SHLL_PH_MM + 2U, // SHLL_QB + 2U, // SHLL_QB_MM + 14U, // SHLL_S_PH + 14U, // SHLL_S_PH_MM + 4U, // SHLL_S_W + 4U, // SHLL_S_W_MM + 0U, // SHRAV_PH + 0U, // SHRAV_PH_MM + 0U, // SHRAV_QB + 0U, // SHRAV_QB_MMR2 + 0U, // SHRAV_R_PH + 0U, // SHRAV_R_PH_MM + 0U, // SHRAV_R_QB + 0U, // SHRAV_R_QB_MMR2 + 0U, // SHRAV_R_W + 0U, // SHRAV_R_W_MM + 14U, // SHRA_PH + 14U, // SHRA_PH_MM + 2U, // SHRA_QB + 2U, // SHRA_QB_MMR2 + 14U, // SHRA_R_PH + 14U, // SHRA_R_PH_MM + 2U, // SHRA_R_QB + 2U, // SHRA_R_QB_MMR2 + 4U, // SHRA_R_W + 4U, // SHRA_R_W_MM + 0U, // SHRLV_PH + 0U, // SHRLV_PH_MMR2 + 0U, // SHRLV_QB + 0U, // SHRLV_QB_MM + 14U, // SHRL_PH + 14U, // SHRL_PH_MMR2 + 2U, // SHRL_QB + 2U, // SHRL_QB_MM + 0U, // SH_MM + 0U, // SH_MMR6 + 0U, // SIGRIE + 0U, // SIGRIE_MMR6 + 148U, // SLDI_B + 34U, // SLDI_D + 144U, // SLDI_H + 36U, // SLDI_W + 152U, // SLD_B + 152U, // SLD_D + 152U, // SLD_H + 152U, // SLD_W + 4U, // SLL + 0U, // SLL16_MM + 0U, // SLL16_MMR6 + 1U, // SLL64_32 + 1U, // SLL64_64 + 2U, // SLLI_B + 12U, // SLLI_D + 14U, // SLLI_H + 4U, // SLLI_W + 0U, // SLLV + 0U, // SLLV_MM + 0U, // SLL_B + 0U, // SLL_D + 0U, // SLL_H + 4U, // SLL_MM + 4U, // SLL_MMR6 + 0U, // SLL_W + 0U, // SLT + 0U, // SLT64 + 0U, // SLT_MM + 0U, // SLTi + 0U, // SLTi64 + 0U, // SLTi_MM + 0U, // SLTiu + 0U, // SLTiu64 + 0U, // SLTiu_MM + 0U, // SLTu + 0U, // SLTu64 + 0U, // SLTu_MM + 0U, // SNE + 0U, // SNEi + 142U, // SPLATI_B + 156U, // SPLATI_D + 130U, // SPLATI_H + 138U, // SPLATI_W + 128U, // SPLAT_B + 128U, // SPLAT_D + 128U, // SPLAT_H + 128U, // SPLAT_W + 4U, // SRA + 2U, // SRAI_B + 12U, // SRAI_D + 14U, // SRAI_H + 4U, // SRAI_W + 2U, // SRARI_B + 12U, // SRARI_D + 14U, // SRARI_H + 4U, // SRARI_W + 0U, // SRAR_B + 0U, // SRAR_D + 0U, // SRAR_H + 0U, // SRAR_W + 0U, // SRAV + 0U, // SRAV_MM + 0U, // SRA_B + 0U, // SRA_D + 0U, // SRA_H + 4U, // SRA_MM + 0U, // SRA_W + 4U, // SRL + 0U, // SRL16_MM + 0U, // SRL16_MMR6 + 2U, // SRLI_B + 12U, // SRLI_D + 14U, // SRLI_H + 4U, // SRLI_W + 2U, // SRLRI_B + 12U, // SRLRI_D + 14U, // SRLRI_H + 4U, // SRLRI_W + 0U, // SRLR_B + 0U, // SRLR_D + 0U, // SRLR_H + 0U, // SRLR_W + 0U, // SRLV + 0U, // SRLV_MM + 0U, // SRL_B + 0U, // SRL_D + 0U, // SRL_H + 4U, // SRL_MM + 0U, // SRL_W + 0U, // SSNOP + 0U, // SSNOP_MM + 0U, // SSNOP_MMR6 + 0U, // ST_B + 0U, // ST_D + 0U, // ST_H + 0U, // ST_W + 0U, // SUB + 0U, // SUBQH_PH + 0U, // SUBQH_PH_MMR2 + 0U, // SUBQH_R_PH + 0U, // SUBQH_R_PH_MMR2 + 0U, // SUBQH_R_W + 0U, // SUBQH_R_W_MMR2 + 0U, // SUBQH_W + 0U, // SUBQH_W_MMR2 + 0U, // SUBQ_PH + 0U, // SUBQ_PH_MM + 0U, // SUBQ_S_PH + 0U, // SUBQ_S_PH_MM + 0U, // SUBQ_S_W + 0U, // SUBQ_S_W_MM + 0U, // SUBSUS_U_B + 0U, // SUBSUS_U_D + 0U, // SUBSUS_U_H + 0U, // SUBSUS_U_W + 0U, // SUBSUU_S_B + 0U, // SUBSUU_S_D + 0U, // SUBSUU_S_H + 0U, // SUBSUU_S_W + 0U, // SUBS_S_B + 0U, // SUBS_S_D + 0U, // SUBS_S_H + 0U, // SUBS_S_W + 0U, // SUBS_U_B + 0U, // SUBS_U_D + 0U, // SUBS_U_H + 0U, // SUBS_U_W + 0U, // SUBU16_MM + 0U, // SUBU16_MMR6 + 0U, // SUBUH_QB + 0U, // SUBUH_QB_MMR2 + 0U, // SUBUH_R_QB + 0U, // SUBUH_R_QB_MMR2 + 0U, // SUBU_MMR6 + 0U, // SUBU_PH + 0U, // SUBU_PH_MMR2 + 0U, // SUBU_QB + 0U, // SUBU_QB_MM + 0U, // SUBU_S_PH + 0U, // SUBU_S_PH_MMR2 + 0U, // SUBU_S_QB + 0U, // SUBU_S_QB_MM + 4U, // SUBVI_B + 4U, // SUBVI_D + 4U, // SUBVI_H + 4U, // SUBVI_W + 0U, // SUBV_B + 0U, // SUBV_D + 0U, // SUBV_H + 0U, // SUBV_W + 0U, // SUB_MM + 0U, // SUB_MMR6 + 0U, // SUBu + 0U, // SUBu_MM + 0U, // SUXC1 + 0U, // SUXC164 + 0U, // SUXC1_MM + 0U, // SW + 0U, // SW16_MM + 0U, // SW16_MMR6 + 0U, // SW64 + 0U, // SWC1 + 0U, // SWC1_MM + 0U, // SWC2 + 0U, // SWC2_MMR6 + 0U, // SWC2_R6 + 0U, // SWC3 + 0U, // SWDSP + 0U, // SWDSP_MM + 0U, // SWE + 0U, // SWE_MM + 0U, // SWL + 0U, // SWL64 + 0U, // SWLE + 0U, // SWLE_MM + 0U, // SWL_MM + 0U, // SWM16_MM + 0U, // SWM16_MMR6 + 0U, // SWM32_MM + 0U, // SWP_MM + 0U, // SWR + 0U, // SWR64 + 0U, // SWRE + 0U, // SWRE_MM + 0U, // SWR_MM + 0U, // SWSP_MM + 0U, // SWSP_MMR6 + 0U, // SWXC1 + 0U, // SWXC1_MM + 0U, // SW_MM + 0U, // SW_MMR6 + 0U, // SYNC + 0U, // SYNCI + 0U, // SYNCI_MM + 0U, // SYNCI_MMR6 + 0U, // SYNC_MM + 0U, // SYNC_MMR6 + 0U, // SYSCALL + 0U, // SYSCALL_MM + 0U, // Save16 + 0U, // SaveX16 + 0U, // SbRxRyOffMemX16 + 0U, // SebRx16 + 0U, // SehRx16 + 0U, // ShRxRyOffMemX16 + 4U, // SllX16 + 0U, // SllvRxRy16 + 0U, // SltRxRy16 + 0U, // SltiRxImm16 + 0U, // SltiRxImmX16 + 0U, // SltiuRxImm16 + 0U, // SltiuRxImmX16 + 0U, // SltuRxRy16 + 4U, // SraX16 + 0U, // SravRxRy16 + 4U, // SrlX16 + 0U, // SrlvRxRy16 + 0U, // SubuRxRyRz16 + 0U, // SwRxRyOffMemX16 + 0U, // SwRxSpImmX16 + 38U, // TEQ + 0U, // TEQI + 0U, // TEQI_MM + 14U, // TEQ_MM + 38U, // TGE + 0U, // TGEI + 0U, // TGEIU + 0U, // TGEIU_MM + 0U, // TGEI_MM + 38U, // TGEU + 14U, // TGEU_MM + 14U, // TGE_MM + 0U, // TLBGINV + 0U, // TLBGINVF + 0U, // TLBGINVF_MM + 0U, // TLBGINV_MM + 0U, // TLBGP + 0U, // TLBGP_MM + 0U, // TLBGR + 0U, // TLBGR_MM + 0U, // TLBGWI + 0U, // TLBGWI_MM + 0U, // TLBGWR + 0U, // TLBGWR_MM + 0U, // TLBINV + 0U, // TLBINVF + 0U, // TLBINVF_MMR6 + 0U, // TLBINV_MMR6 + 0U, // TLBP + 0U, // TLBP_MM + 0U, // TLBR + 0U, // TLBR_MM + 0U, // TLBWI + 0U, // TLBWI_MM + 0U, // TLBWR + 0U, // TLBWR_MM + 38U, // TLT + 0U, // TLTI + 0U, // TLTIU_MM + 0U, // TLTI_MM + 38U, // TLTU + 14U, // TLTU_MM + 14U, // TLT_MM + 38U, // TNE + 0U, // TNEI + 0U, // TNEI_MM + 14U, // TNE_MM + 0U, // TRUNC_L_D64 + 0U, // TRUNC_L_D_MMR6 + 0U, // TRUNC_L_S + 0U, // TRUNC_L_S_MMR6 + 0U, // TRUNC_W_D32 + 0U, // TRUNC_W_D64 + 0U, // TRUNC_W_D_MMR6 + 0U, // TRUNC_W_MM + 0U, // TRUNC_W_S + 0U, // TRUNC_W_S_MM + 0U, // TRUNC_W_S_MMR6 + 0U, // TTLTIU + 0U, // UDIV + 0U, // UDIV_MM + 0U, // V3MULU + 0U, // VMM0 + 0U, // VMULU + 24U, // VSHF_B + 24U, // VSHF_D + 24U, // VSHF_H + 24U, // VSHF_W + 0U, // WAIT + 0U, // WAIT_MM + 0U, // WAIT_MMR6 + 0U, // WRDSP + 0U, // WRDSP_MM + 0U, // WRPGPR_MMR6 + 0U, // WSBH + 0U, // WSBH_MM + 0U, // WSBH_MMR6 + 0U, // XOR + 0U, // XOR16_MM + 0U, // XOR16_MMR6 + 0U, // XOR64 + 6U, // XORI_B + 8U, // XORI_MMR6 + 0U, // XOR_MM + 0U, // XOR_MMR6 + 0U, // XOR_V + 8U, // XORi + 8U, // XORi64 + 8U, // XORi_MM + 0U, // XorRxRxRy16 + 0U, // YIELD + }; + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + return createMnemonic(AsmStrs + (Bits & 16383) - 1, Bits); +} +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) { + MCMnemonic MnemonicInfo = Mips_getMnemonic(MI); + +#ifndef CAPSTONE_DIET + + SStream_concat0(O, MnemonicInfo.first); +#endif + + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 4 bits for 15 unique commands. + switch ((Bits >> 14) & 15) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 2: + // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, MultRxRyRz1... + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 3: + // LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, SWM16_MM, SWM16_MMR6, ... + printRegisterList /* printRegisterList (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printMemOperand /* printMemOperand (+ ) */ (MI, 1, O, ""); + return; + break; + case 4: + // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 5: + // AND16_MM, AND16_MMR6, LSA_MMR6, MTHC1_D32, MTHC1_D32_MM, MTHC1_D64, MT... + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + break; + case 6: + // BREAK, BREAK_MM, BREAK_MMR6, HYPCALL, HYPCALL_MM, SDBBP_MM, SYSCALL_MM... + printUImm /* printUImm<10> (+ ) */ (MI, 0, O, 10); + break; + case 7: + // BREAK16_MM, BREAK16_MMR6, SDBBP16_MM, SDBBP16_MMR6 + printUImm /* printUImm<4> (+ ) */ (MI, 0, O, 4); + return; + break; + case 8: + // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... + printUImm /* printUImm<5> (+ ) */ (MI, 2, O, 5); + SStream_concat0(O, ", "); + break; + case 9: + // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM + printFCCOperand /* printFCCOperand (+ ) */ (MI, 2, O); + break; + case 10: + // Jal16, JalB16 + printUImm /* printUImm<26> (+ ) */ (MI, 0, O, 26); + break; + case 11: + // SDBBP, SDBBP_MMR6, SDBBP_R6, SYSCALL + printUImm /* printUImm<20> (+ ) */ (MI, 0, O, 20); + return; + break; + case 12: + // SIGRIE, SIGRIE_MMR6 + printUImm /* printUImm<16> (+ ) */ (MI, 0, O, 16); + return; + break; + case 13: + // SYNC, SYNC_MM, SYNC_MMR6 + printUImm /* printUImm<5> (+ ) */ (MI, 0, O, 5); + return; + break; + case 14: + // SYNCI, SYNCI_MM, SYNCI_MMR6 + printMemOperand /* printMemOperand (+ ) */ (MI, 0, O, ""); + return; + break; + } + + // Fragment 1 encoded into 5 bits for 18 unique commands. + switch ((Bits >> 18) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... + SStream_concat0(O, ", "); + break; + case 1: + // B_MMR6_Pseudo, B_MM_Pseudo, Constant32, JalOneReg, MFTDSP, MTTDSP, ADD... + return; + break; + case 2: + // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, CTC1, CTC1_... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 3: + // LwConstant32 + SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "\n2:"); + return; + break; + case 4: + // MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImm... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 5: + // SelBeqZ, SelBneZ + SStream_concat0(O, ", .+4\n\t\n\tmove "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 6: + // AND16_MM, AND16_MMR6, LSA_MMR6, OR16_MM, OR16_MMR6, PREFX_MM, XOR16_MM... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 7: + // AddiuRxPcImmX16 + SStream_concat0(O, ", $pc, "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 8: + // AddiuSpImm16, Bimm16 + SStream_concat0(O, " # 16 bit inst"); + return; + break; + case 9: + // Bteqz16, Btnez16 + SStream_concat0(O, " # 16 bit inst"); + return; + break; + case 10: + // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... + printMemOperand /* printMemOperand (+ ) */ (MI, 0, O, ""); + return; + break; + case 11: + // FCMP_D32, FCMP_D32_MM, FCMP_D64 + SStream_concat0(O, ".d\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 12: + // FCMP_S32, FCMP_S32_MM + SStream_concat0(O, ".s\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 13: + // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... + SStream_concat0(O, "["); + break; + case 14: + // Jal16 + SStream_concat0(O, "\n\tnop"); + return; + break; + case 15: + // JalB16 + SStream_concat0(O, "\t# branch\n\tnop"); + return; + break; + case 16: + // SAA, SAAD + SStream_concat0(O, ", ("); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + case 17: + // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6 + printMemOperand /* printMemOperand (+ ) */ (MI, 2, O, ""); + return; + break; + } + + // Fragment 2 encoded into 5 bits for 25 unique commands. + switch ((Bits >> 23) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 1: + // CTTC1, MTTACX, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, ADDIUS5_MM, AND16_... + return; + break; + case 2: + // GotPrologue16, AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B,... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 3: + // LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC64DSP, LOAD_CCOND_DSP, LoadA... + printMemOperand /* printMemOperand (+ ) */ (MI, 1, O, ""); + return; + break; + case 4: + // MTTC0, DMTC0, DMTC2, DMTGC0, FORK, LSA_MMR6, MTC0, MTC0_MMR6, MTC2, MT... + SStream_concat0(O, ", "); + break; + case 5: + // MultRxRyRz16, MultuRxRyRz16 + SStream_concat0(O, "\n\tmflo\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 6: + // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... + printOperand /* printOperand (+ ) */ (MI, 4, O); + break; + case 7: + // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... + SStream_concat0(O, "\n\tmove\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", $t8"); + return; + break; + case 8: + // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM + printMemOperandEA /* printMemOperandEA (+ ) */ (MI, 1, O, ""); + return; + break; + case 9: + // BBIT0, BBIT032, BBIT1, BBIT132 + printUImm /* printUImm<5> (+ ) */ (MI, 1, O, 5); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 10: + // BREAK, BREAK_MM, BREAK_MMR6, RDDSP, WRDSP + printUImm /* printUImm<10> (+ ) */ (MI, 1, O, 10); + return; + break; + case 11: + // DMFC2_OCTEON, DMTC2_OCTEON, LUI_MMR6, LUi, LUi64, LUi_MM + printUImm /* printUImm<16> (+ ) */ (MI, 1, O, 16); + return; + break; + case 12: + // GINVT, GINVT_MMR6 + printUImm /* printUImm<2> (+ ) */ (MI, 1, O, 2); + return; + break; + case 13: + // INSERT_B + printUImm /* printUImm<4> (+ ) */ (MI, 3, O, 4); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 14: + // INSERT_D + printUImm /* printUImm<1> (+ ) */ (MI, 3, O, 1); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 15: + // INSERT_H + printUImm /* printUImm<3> (+ ) */ (MI, 3, O, 3); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 16: + // INSERT_W + printUImm /* printUImm<2> (+ ) */ (MI, 3, O, 2); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 17: + // INSVE_B + printUImm /* printUImm<4> (+ ) */ (MI, 2, O, 4); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "["); + printUImm /* printUImm<0> (+ ) */ (MI, 4, O, 0); + SStream_concat0(O, "]"); + return; + break; + case 18: + // INSVE_D + printUImm /* printUImm<1> (+ ) */ (MI, 2, O, 1); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "["); + printUImm /* printUImm<0> (+ ) */ (MI, 4, O, 0); + SStream_concat0(O, "]"); + return; + break; + case 19: + // INSVE_H + printUImm /* printUImm<3> (+ ) */ (MI, 2, O, 3); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "["); + printUImm /* printUImm<0> (+ ) */ (MI, 4, O, 0); + SStream_concat0(O, "]"); + return; + break; + case 20: + // INSVE_W + printUImm /* printUImm<2> (+ ) */ (MI, 2, O, 2); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "["); + printUImm /* printUImm<0> (+ ) */ (MI, 4, O, 0); + SStream_concat0(O, "]"); + return; + break; + case 21: + // LWP_MM, SWP_MM + printMemOperand /* printMemOperand (+ ) */ (MI, 2, O, ""); + return; + break; + case 22: + // PREFX_MM + SStream_concat0(O, "("); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ")"); + return; + break; + case 23: + // RDDSP_MM, WRDSP_MM + printUImm /* printUImm<7> (+ ) */ (MI, 1, O, 7); + return; + break; + case 24: + // REPL_QB, REPL_QB_MM + printUImm /* printUImm<8> (+ ) */ (MI, 1, O, 8); + return; + break; + } + + // Fragment 3 encoded into 5 bits for 18 unique commands. + switch ((Bits >> 28) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ABSMacro, CFTC1, JalTwoReg, LoadAddrImm32, LoadAddrImm64, LoadImm32, L... + return; + break; + case 1: + // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... + SStream_concat0(O, ", "); + break; + case 2: + // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... + SStream_concat0(O, "\n\tbteqz\t"); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 3: + // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... + SStream_concat0(O, "\n\tbtnez\t"); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 4: + // GotPrologue16 + SStream_concat0(O, "\n\taddiu\t"); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", $pc, "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "\n "); + return; + break; + case 5: + // MTTC0, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, MTGC0_MM, M... + printUImm /* printUImm<3> (+ ) */ (MI, 2, O, 3); + return; + break; + case 6: + // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... + SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 7: + // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... + SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 8: + // AddiuRxRxImm16, LwRxPcTcp16 + SStream_concat0(O, "\t# 16 bit inst"); + return; + break; + case 9: + // BeqzRxImm16, BnezRxImm16 + SStream_concat0(O, " # 16 bit inst"); + return; + break; + case 10: + // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... + SStream_concat0(O, "["); + break; + case 11: + // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 + SStream_concat0(O, " \t# 16 bit inst"); + return; + break; + case 12: + // DSLL64_32 + SStream_concat0(O, ", 32"); + return; + break; + case 13: + // FORK + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 14: + // LBUX, LBUX_MM, LDXC1, LDXC164, LHX, LHX_MM, LUXC1, LUXC164, LUXC1_MM, ... + SStream_concat0(O, "("); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + case 15: + // LSA_MMR6 + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printUImm /* printUImm<2, 1> (+ ) */ (MI, 3, O, 2, 1); + return; + break; + case 16: + // MTTR + printUImm /* printUImm<1> (+ ) */ (MI, 2, O, 1); + SStream_concat0(O, ", "); + printUImm /* printUImm<3> (+ ) */ (MI, 3, O, 3); + SStream_concat0(O, ", "); + printUImm /* printUImm<1> (+ ) */ (MI, 4, O, 1); + return; + break; + case 17: + // SLL64_32, SLL64_64 + SStream_concat0(O, ", 0"); + return; + break; + } + + // Fragment 4 encoded into 5 bits for 20 unique commands. + switch ((Bits >> 33) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 1: + // MFTC0, BCLRI_B, BNEGI_B, BSETI_B, COPY_S_H, COPY_U_H, DMFC0, DMFC2, DM... + printUImm /* printUImm<3> (+ ) */ (MI, 2, O, 3); + break; + case 2: + // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG... + printUImm /* printUImm<5> (+ ) */ (MI, 2, O, 5); + break; + case 3: + // ANDI_B, NORI_B, ORI_B, RDHWR, RDHWR64, RDHWR_MM, SHF_B, SHF_H, SHF_W, ... + printUImm /* printUImm<8> (+ ) */ (MI, 2, O, 8); + return; + break; + case 4: + // ANDI_MMR6, ANDi, ANDi64, ANDi_MM, AUI, AUI_MMR6, DAHI, DATI, DAUI, ORI... + printUImm /* printUImm<16> (+ ) */ (MI, 2, O, 16); + return; + break; + case 5: + // BALIGN, BALIGN_MMR2, COPY_S_W, COPY_U_W, SPLATI_W + printUImm /* printUImm<2> (+ ) */ (MI, 2, O, 2); + break; + case 6: + // BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D... + printUImm /* printUImm<6> (+ ) */ (MI, 2, O, 6); + break; + case 7: + // BCLRI_H, BNEGI_H, BSETI_H, COPY_S_B, COPY_U_B, SAT_S_H, SAT_U_H, SHLL_... + printUImm /* printUImm<4> (+ ) */ (MI, 2, O, 4); + break; + case 8: + // BINSLI_B, BINSRI_B, SLDI_H + printUImm /* printUImm<3> (+ ) */ (MI, 3, O, 3); + break; + case 9: + // BINSLI_D, BINSRI_D + printUImm /* printUImm<6> (+ ) */ (MI, 3, O, 6); + return; + break; + case 10: + // BINSLI_H, BINSRI_H, SLDI_B + printUImm /* printUImm<4> (+ ) */ (MI, 3, O, 4); + break; + case 11: + // BINSLI_W, BINSRI_W + printUImm /* printUImm<5> (+ ) */ (MI, 3, O, 5); + return; + break; + case 12: + // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 13: + // BMNZI_B, BMZI_B, BSELI_B + printUImm /* printUImm<8> (+ ) */ (MI, 3, O, 8); + return; + break; + case 14: + // COPY_S_D, MFTR, SPLATI_D + printUImm /* printUImm<1> (+ ) */ (MI, 2, O, 1); + break; + case 15: + // DEXTU, DINSU + printUImm /* printUImm<5, 32> (+ ) */ (MI, 2, O, 5, 32); + SStream_concat0(O, ", "); + break; + case 16: + // FADD_S_MMR6, FDIV_S_MMR6, FMUL_S_MMR6, FSUB_S_MMR6 + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 17: + // SLDI_D + printUImm /* printUImm<1> (+ ) */ (MI, 3, O, 1); + SStream_concat0(O, "]"); + return; + break; + case 18: + // SLDI_W + printUImm /* printUImm<2> (+ ) */ (MI, 3, O, 2); + SStream_concat0(O, "]"); + return; + break; + case 19: + // TEQ, TGE, TGEU, TLT, TLTU, TNE + printUImm /* printUImm<10> (+ ) */ (MI, 2, O, 10); + return; + break; + } + + // Fragment 5 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 38) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... + return; + break; + case 1: + // ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN, DEXT, DE... + SStream_concat0(O, ", "); + break; + case 2: + // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... + SStream_concat0(O, "]"); + return; + break; + case 3: + // DEXTU + printUImm /* printUImm<5, 1> (+ ) */ (MI, 3, O, 5, 1); + return; + break; + case 4: + // DINSU + printUImm /* printUImm<6> (+ ) */ (MI, 3, O, 6); + return; + break; + } + + // Fragment 6 encoded into 4 bits for 10 unique commands. + switch ((Bits >> 41) & 15) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ALIGN, ALIGN_MMR6 + printUImm /* printUImm<2> (+ ) */ (MI, 3, O, 2); + return; + break; + case 1: + // CINS, CINS32, CINS64_32, CINS_i32, EXTS, EXTS32 + printUImm /* printUImm<5> (+ ) */ (MI, 3, O, 5); + return; + break; + case 2: + // DALIGN, MFTR + printUImm /* printUImm<3> (+ ) */ (MI, 3, O, 3); + break; + case 3: + // DEXT + printUImm /* printUImm<6, 1> (+ ) */ (MI, 3, O, 6, 1); + return; + break; + case 4: + // DEXT64_32, EXT, EXT_MM, EXT_MMR6 + printUImm /* printUImm<5, 1> (+ ) */ (MI, 3, O, 5, 1); + return; + break; + case 5: + // DEXTM + printUImm /* printUImm<5, 33> (+ ) */ (MI, 3, O, 5, 33); + return; + break; + case 6: + // DINS, INS, INS_MM, INS_MMR6 + printUImm /* printUImm<6> (+ ) */ (MI, 3, O, 6); + return; + break; + case 7: + // DINSM + printUImm /* printUImm<6, 2> (+ ) */ (MI, 3, O, 6, 2); + return; + break; + case 8: + // DLSA, DLSA_R6, LSA, LSA_R6 + printUImm /* printUImm<2, 1> (+ ) */ (MI, 3, O, 2, 1); + return; + break; + case 9: + // MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MOVEP_MM, MOVEP_MM... + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + } + + // Fragment 7 encoded into 1 bits for 2 unique commands. + if ((Bits >> 45) & 1) { + // MFTR + SStream_concat0(O, ", "); + printUImm /* printUImm<1> (+ ) */ (MI, 4, O, 1); + return; + } else { + // DALIGN + return; + } +} + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +const char *getRegisterName(unsigned RegNo) { + assert(RegNo && RegNo < 442 && "Invalid register number!"); + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = {/* 0 */ "f10\0" + /* 4 */ "w10\0" + /* 8 */ "f20\0" + /* 12 */ "DSPOutFlag20\0" + /* 25 */ "w20\0" + /* 29 */ "f30\0" + /* 33 */ "w30\0" + /* 37 */ "ac0\0" + /* 41 */ "fcc0\0" + /* 46 */ "f0\0" + /* 49 */ "mpl0\0" + /* 54 */ "p0\0" + /* 57 */ "w0\0" + /* 60 */ "f11\0" + /* 64 */ "w11\0" + /* 68 */ "f21\0" + /* 72 */ "DSPOutFlag21\0" + /* 85 */ "w21\0" + /* 89 */ "f31\0" + /* 93 */ "w31\0" + /* 97 */ "ac1\0" + /* 101 */ "fcc1\0" + /* 106 */ "f1\0" + /* 109 */ "mpl1\0" + /* 114 */ "p1\0" + /* 117 */ "w1\0" + /* 120 */ "f12\0" + /* 124 */ "w12\0" + /* 128 */ "f22\0" + /* 132 */ "DSPOutFlag22\0" + /* 145 */ "w22\0" + /* 149 */ "ac2\0" + /* 153 */ "fcc2\0" + /* 158 */ "f2\0" + /* 161 */ "mpl2\0" + /* 166 */ "p2\0" + /* 169 */ "w2\0" + /* 172 */ "f13\0" + /* 176 */ "w13\0" + /* 180 */ "f23\0" + /* 184 */ "DSPOutFlag23\0" + /* 197 */ "w23\0" + /* 201 */ "ac3\0" + /* 205 */ "fcc3\0" + /* 210 */ "f3\0" + /* 213 */ "w3\0" + /* 216 */ "f14\0" + /* 220 */ "w14\0" + /* 224 */ "f24\0" + /* 228 */ "w24\0" + /* 232 */ "fcc4\0" + /* 237 */ "f4\0" + /* 240 */ "w4\0" + /* 243 */ "f15\0" + /* 247 */ "w15\0" + /* 251 */ "f25\0" + /* 255 */ "w25\0" + /* 259 */ "fcc5\0" + /* 264 */ "f5\0" + /* 267 */ "w5\0" + /* 270 */ "f16\0" + /* 274 */ "w16\0" + /* 278 */ "f26\0" + /* 282 */ "w26\0" + /* 286 */ "fcc6\0" + /* 291 */ "f6\0" + /* 294 */ "w6\0" + /* 297 */ "f17\0" + /* 301 */ "w17\0" + /* 305 */ "f27\0" + /* 309 */ "w27\0" + /* 313 */ "fcc7\0" + /* 318 */ "f7\0" + /* 321 */ "w7\0" + /* 324 */ "f18\0" + /* 328 */ "w18\0" + /* 332 */ "f28\0" + /* 336 */ "w28\0" + /* 340 */ "f8\0" + /* 343 */ "w8\0" + /* 346 */ "DSPOutFlag16_19\0" + /* 362 */ "f19\0" + /* 366 */ "w19\0" + /* 370 */ "f29\0" + /* 374 */ "w29\0" + /* 378 */ "f9\0" + /* 381 */ "w9\0" + /* 384 */ "DSPEFI\0" + /* 391 */ "ra\0" + /* 394 */ "hwr_cc\0" + /* 401 */ "pc\0" + /* 404 */ "DSPCCond\0" + /* 413 */ "DSPOutFlag\0" + /* 424 */ "hi\0" + /* 427 */ "hwr_cpunum\0" + /* 438 */ "lo\0" + /* 441 */ "zero\0" + /* 446 */ "hwr_synci_step\0" + /* 461 */ "fp\0" + /* 464 */ "gp\0" + /* 467 */ "sp\0" + /* 470 */ "hwr_ccres\0" + /* 480 */ "DSPPos\0" + /* 487 */ "DSPSCount\0" + /* 497 */ "DSPCarry\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint16_t RegAsmOffset[] = { + 62, 404, 497, 384, 413, 480, 487, 461, 464, 122, 62, 2, 272, 218, 245, + 174, 299, 401, 391, 467, 441, 218, 245, 272, 299, 37, 97, 149, 201, 62, + 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, 2, 62, 122, 174, 218, + 245, 272, 299, 326, 360, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, + 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, + 252, 279, 306, 333, 371, 30, 90, 1, 61, 121, 173, 217, 244, 271, 298, + 325, 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 1, + 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, + 279, 306, 333, 371, 30, 90, 46, 158, 237, 291, 340, 0, 120, 216, 270, + 324, 8, 128, 224, 278, 332, 29, 12, 72, 132, 184, 46, 106, 158, 210, + 237, 264, 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, + 362, 8, 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 41, 101, + 153, 205, 232, 259, 286, 313, 2, 62, 122, 174, 218, 245, 272, 299, 326, + 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, + 225, 252, 279, 306, 333, 371, 30, 90, 461, 46, 106, 158, 210, 237, 264, + 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, + 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 464, 37, 97, 149, + 201, 427, 446, 394, 470, 218, 245, 272, 299, 326, 360, 1, 61, 121, 173, + 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, + 371, 30, 90, 279, 306, 37, 97, 149, 201, 49, 109, 161, 326, 360, 1, + 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, + 279, 306, 333, 371, 30, 90, 54, 114, 166, 391, 271, 298, 325, 359, 9, + 69, 129, 181, 467, 326, 360, 1, 61, 121, 173, 217, 244, 225, 252, 122, + 174, 57, 117, 169, 213, 240, 267, 294, 321, 343, 381, 4, 64, 124, 176, + 220, 247, 274, 301, 328, 366, 25, 85, 145, 197, 228, 255, 282, 309, 336, + 374, 33, 93, 441, 218, 245, 272, 299, 37, 46, 106, 158, 210, 237, 264, + 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, + 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 346, 424, 279, 306, + 438, 271, 298, 325, 359, 9, 69, 129, 181, 326, 360, 1, 61, 121, 173, + 217, 244, 225, 252, 122, 174, + }; + + assert(*(AsmStrs + RegAsmOffset[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrs + RegAsmOffset[RegNo - 1]; +} +#endif +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + +static char *printAliasInstr(MCInst *MI, SStream *OS) { + static const PatternsForOpcode OpToPatterns[] = { + {Mips_MFTACX, 0, 1}, + {Mips_MFTC0, 1, 1}, + {Mips_MFTHI, 2, 1}, + {Mips_MFTLO, 3, 1}, + {Mips_MTTACX, 4, 1}, + {Mips_MTTC0, 5, 1}, + {Mips_MTTHI, 6, 1}, + {Mips_MTTLO, 7, 1}, + {Mips_NORImm, 8, 1}, + {Mips_NORImm64, 9, 1}, + {Mips_SLTImm64, 10, 1}, + {Mips_SLTUImm64, 11, 1}, + {Mips_ADDIUPC, 12, 1}, + {Mips_ADDIUPC_MMR6, 13, 1}, + {Mips_ADDu, 14, 1}, + {Mips_BC1F, 15, 1}, + {Mips_BC1FL, 16, 1}, + {Mips_BC1F_MM, 17, 1}, + {Mips_BC1T, 18, 1}, + {Mips_BC1TL, 19, 1}, + {Mips_BC1T_MM, 20, 1}, + {Mips_BC2F, 21, 1}, + {Mips_BC2FL, 22, 1}, + {Mips_BC2T, 23, 1}, + {Mips_BC2TL, 24, 1}, + {Mips_BC3F, 25, 1}, + {Mips_BC3FL, 26, 1}, + {Mips_BC3T, 27, 1}, + {Mips_BC3TL, 28, 1}, + {Mips_BEQL, 29, 1}, + {Mips_BGEZAL, 30, 1}, + {Mips_BGEZAL_MM, 31, 1}, + {Mips_BNEL, 32, 1}, + {Mips_BREAK, 33, 2}, + {Mips_BREAK_MM, 35, 2}, + {Mips_C_EQ_D32, 37, 1}, + {Mips_C_EQ_D32_MM, 38, 1}, + {Mips_C_EQ_D64, 39, 1}, + {Mips_C_EQ_D64_MM, 40, 1}, + {Mips_C_EQ_S, 41, 1}, + {Mips_C_EQ_S_MM, 42, 1}, + {Mips_C_F_D32, 43, 1}, + {Mips_C_F_D32_MM, 44, 1}, + {Mips_C_F_D64, 45, 1}, + {Mips_C_F_D64_MM, 46, 1}, + {Mips_C_F_S, 47, 1}, + {Mips_C_F_S_MM, 48, 1}, + {Mips_C_LE_D32, 49, 1}, + {Mips_C_LE_D32_MM, 50, 1}, + {Mips_C_LE_D64, 51, 1}, + {Mips_C_LE_D64_MM, 52, 1}, + {Mips_C_LE_S, 53, 1}, + {Mips_C_LE_S_MM, 54, 1}, + {Mips_C_LT_D32, 55, 1}, + {Mips_C_LT_D32_MM, 56, 1}, + {Mips_C_LT_D64, 57, 1}, + {Mips_C_LT_D64_MM, 58, 1}, + {Mips_C_LT_S, 59, 1}, + {Mips_C_LT_S_MM, 60, 1}, + {Mips_C_NGE_D32, 61, 1}, + {Mips_C_NGE_D32_MM, 62, 1}, + {Mips_C_NGE_D64, 63, 1}, + {Mips_C_NGE_D64_MM, 64, 1}, + {Mips_C_NGE_S, 65, 1}, + {Mips_C_NGE_S_MM, 66, 1}, + {Mips_C_NGLE_D32, 67, 1}, + {Mips_C_NGLE_D32_MM, 68, 1}, + {Mips_C_NGLE_D64, 69, 1}, + {Mips_C_NGLE_D64_MM, 70, 1}, + {Mips_C_NGLE_S, 71, 1}, + {Mips_C_NGLE_S_MM, 72, 1}, + {Mips_C_NGL_D32, 73, 1}, + {Mips_C_NGL_D32_MM, 74, 1}, + {Mips_C_NGL_D64, 75, 1}, + {Mips_C_NGL_D64_MM, 76, 1}, + {Mips_C_NGL_S, 77, 1}, + {Mips_C_NGL_S_MM, 78, 1}, + {Mips_C_NGT_D32, 79, 1}, + {Mips_C_NGT_D32_MM, 80, 1}, + {Mips_C_NGT_D64, 81, 1}, + {Mips_C_NGT_D64_MM, 82, 1}, + {Mips_C_NGT_S, 83, 1}, + {Mips_C_NGT_S_MM, 84, 1}, + {Mips_C_OLE_D32, 85, 1}, + {Mips_C_OLE_D32_MM, 86, 1}, + {Mips_C_OLE_D64, 87, 1}, + {Mips_C_OLE_D64_MM, 88, 1}, + {Mips_C_OLE_S, 89, 1}, + {Mips_C_OLE_S_MM, 90, 1}, + {Mips_C_OLT_D32, 91, 1}, + {Mips_C_OLT_D32_MM, 92, 1}, + {Mips_C_OLT_D64, 93, 1}, + {Mips_C_OLT_D64_MM, 94, 1}, + {Mips_C_OLT_S, 95, 1}, + {Mips_C_OLT_S_MM, 96, 1}, + {Mips_C_SEQ_D32, 97, 1}, + {Mips_C_SEQ_D32_MM, 98, 1}, + {Mips_C_SEQ_D64, 99, 1}, + {Mips_C_SEQ_D64_MM, 100, 1}, + {Mips_C_SEQ_S, 101, 1}, + {Mips_C_SEQ_S_MM, 102, 1}, + {Mips_C_SF_D32, 103, 1}, + {Mips_C_SF_D32_MM, 104, 1}, + {Mips_C_SF_D64, 105, 1}, + {Mips_C_SF_D64_MM, 106, 1}, + {Mips_C_SF_S, 107, 1}, + {Mips_C_SF_S_MM, 108, 1}, + {Mips_C_UEQ_D32, 109, 1}, + {Mips_C_UEQ_D32_MM, 110, 1}, + {Mips_C_UEQ_D64, 111, 1}, + {Mips_C_UEQ_D64_MM, 112, 1}, + {Mips_C_UEQ_S, 113, 1}, + {Mips_C_UEQ_S_MM, 114, 1}, + {Mips_C_ULE_D32, 115, 1}, + {Mips_C_ULE_D32_MM, 116, 1}, + {Mips_C_ULE_D64, 117, 1}, + {Mips_C_ULE_D64_MM, 118, 1}, + {Mips_C_ULE_S, 119, 1}, + {Mips_C_ULE_S_MM, 120, 1}, + {Mips_C_ULT_D32, 121, 1}, + {Mips_C_ULT_D32_MM, 122, 1}, + {Mips_C_ULT_D64, 123, 1}, + {Mips_C_ULT_D64_MM, 124, 1}, + {Mips_C_ULT_S, 125, 1}, + {Mips_C_ULT_S_MM, 126, 1}, + {Mips_C_UN_D32, 127, 1}, + {Mips_C_UN_D32_MM, 128, 1}, + {Mips_C_UN_D64, 129, 1}, + {Mips_C_UN_D64_MM, 130, 1}, + {Mips_C_UN_S, 131, 1}, + {Mips_C_UN_S_MM, 132, 1}, + {Mips_DADDu, 133, 1}, + {Mips_DI, 134, 1}, + {Mips_DIV, 135, 1}, + {Mips_DIVU, 136, 1}, + {Mips_DI_MM, 137, 1}, + {Mips_DI_MMR6, 138, 1}, + {Mips_DMT, 139, 1}, + {Mips_DSUB, 140, 2}, + {Mips_DSUBu, 142, 2}, + {Mips_DVPE, 144, 1}, + {Mips_EI, 145, 1}, + {Mips_EI_MM, 146, 1}, + {Mips_EI_MMR6, 147, 1}, + {Mips_EMT, 148, 1}, + {Mips_EVPE, 149, 1}, + {Mips_HYPCALL, 150, 1}, + {Mips_HYPCALL_MM, 151, 1}, + {Mips_JALR, 152, 1}, + {Mips_JALR64, 153, 1}, + {Mips_JALRC_HB_MMR6, 154, 1}, + {Mips_JALRC_MMR6, 155, 1}, + {Mips_JALR_HB, 156, 1}, + {Mips_JALR_HB64, 157, 1}, + {Mips_JIALC, 158, 1}, + {Mips_JIALC64, 159, 1}, + {Mips_JIC, 160, 1}, + {Mips_JIC64, 161, 1}, + {Mips_MOVE16_MM, 162, 1}, + {Mips_Move32R16, 163, 1}, + {Mips_OR, 164, 1}, + {Mips_OR64, 165, 1}, + {Mips_RDHWR, 166, 1}, + {Mips_RDHWR64, 167, 1}, + {Mips_RDHWR_MM, 168, 1}, + {Mips_RDHWR_MMR6, 169, 1}, + {Mips_SDBBP, 170, 1}, + {Mips_SDBBP_MMR6, 171, 1}, + {Mips_SDBBP_R6, 172, 1}, + {Mips_SIGRIE, 173, 1}, + {Mips_SIGRIE_MMR6, 174, 1}, + {Mips_SLL, 175, 1}, + {Mips_SLL_MM, 176, 1}, + {Mips_SLL_MMR6, 177, 1}, + {Mips_SUB, 178, 2}, + {Mips_SUBU_MMR6, 180, 2}, + {Mips_SUB_MM, 182, 2}, + {Mips_SUB_MMR6, 184, 2}, + {Mips_SUBu, 186, 2}, + {Mips_SUBu_MM, 188, 2}, + {Mips_SWSP_MM, 190, 1}, + {Mips_SYNC, 191, 1}, + {Mips_SYNC_MM, 192, 1}, + {Mips_SYNC_MMR6, 193, 1}, + {Mips_SYSCALL, 194, 1}, + {Mips_SYSCALL_MM, 195, 1}, + {Mips_TEQ, 196, 1}, + {Mips_TEQ_MM, 197, 1}, + {Mips_TGE, 198, 1}, + {Mips_TGEU, 199, 1}, + {Mips_TGEU_MM, 200, 1}, + {Mips_TGE_MM, 201, 1}, + {Mips_TLT, 202, 1}, + {Mips_TLTU, 203, 1}, + {Mips_TLTU_MM, 204, 1}, + {Mips_TLT_MM, 205, 1}, + {Mips_TNE, 206, 1}, + {Mips_TNE_MM, 207, 1}, + {Mips_WAIT_MM, 208, 1}, + {Mips_WRDSP, 209, 1}, + {Mips_WRDSP_MM, 210, 1}, + {Mips_YIELD, 211, 1}, + }; + + static const AliasPattern Patterns[] = { + // Mips::MFTACX - 0 + {0, 0, 2, 2}, + // Mips::MFTC0 - 1 + {10, 2, 3, 3}, + // Mips::MFTHI - 2 + {23, 5, 2, 2}, + // Mips::MFTLO - 3 + {32, 7, 2, 2}, + // Mips::MTTACX - 4 + {41, 9, 2, 2}, + // Mips::MTTC0 - 5 + {51, 11, 3, 3}, + // Mips::MTTHI - 6 + {64, 14, 2, 2}, + // Mips::MTTLO - 7 + {73, 16, 2, 2}, + // Mips::NORImm - 8 + {82, 18, 3, 2}, + // Mips::NORImm64 - 9 + {82, 20, 3, 2}, + // Mips::SLTImm64 - 10 + {93, 22, 3, 2}, + // Mips::SLTUImm64 - 11 + {104, 24, 3, 2}, + // Mips::ADDIUPC - 12 + {116, 26, 2, 1}, + // Mips::ADDIUPC_MMR6 - 13 + {116, 27, 2, 1}, + // Mips::ADDu - 14 + {128, 28, 3, 3}, + // Mips::BC1F - 15 + {140, 31, 2, 1}, + // Mips::BC1FL - 16 + {148, 32, 2, 1}, + // Mips::BC1F_MM - 17 + {140, 33, 2, 1}, + // Mips::BC1T - 18 + {157, 34, 2, 1}, + // Mips::BC1TL - 19 + {165, 35, 2, 1}, + // Mips::BC1T_MM - 20 + {157, 36, 2, 1}, + // Mips::BC2F - 21 + {174, 37, 2, 1}, + // Mips::BC2FL - 22 + {182, 38, 2, 1}, + // Mips::BC2T - 23 + {191, 39, 2, 1}, + // Mips::BC2TL - 24 + {199, 40, 2, 1}, + // Mips::BC3F - 25 + {208, 41, 2, 1}, + // Mips::BC3FL - 26 + {216, 42, 2, 1}, + // Mips::BC3T - 27 + {225, 43, 2, 1}, + // Mips::BC3TL - 28 + {233, 44, 2, 1}, + // Mips::BEQL - 29 + {242, 45, 3, 2}, + // Mips::BGEZAL - 30 + {255, 47, 2, 1}, + // Mips::BGEZAL_MM - 31 + {255, 48, 2, 1}, + // Mips::BNEL - 32 + {262, 49, 3, 2}, + // Mips::BREAK - 33 + {275, 51, 2, 2}, + {281, 53, 2, 2}, + // Mips::BREAK_MM - 35 + {275, 55, 2, 2}, + {281, 57, 2, 2}, + // Mips::C_EQ_D32 - 37 + {292, 59, 3, 3}, + // Mips::C_EQ_D32_MM - 38 + {292, 62, 3, 3}, + // Mips::C_EQ_D64 - 39 + {292, 65, 3, 3}, + // Mips::C_EQ_D64_MM - 40 + {292, 68, 3, 3}, + // Mips::C_EQ_S - 41 + {306, 71, 3, 3}, + // Mips::C_EQ_S_MM - 42 + {306, 74, 3, 3}, + // Mips::C_F_D32 - 43 + {320, 77, 3, 3}, + // Mips::C_F_D32_MM - 44 + {320, 80, 3, 3}, + // Mips::C_F_D64 - 45 + {320, 83, 3, 3}, + // Mips::C_F_D64_MM - 46 + {320, 86, 3, 3}, + // Mips::C_F_S - 47 + {333, 89, 3, 3}, + // Mips::C_F_S_MM - 48 + {333, 92, 3, 3}, + // Mips::C_LE_D32 - 49 + {346, 95, 3, 3}, + // Mips::C_LE_D32_MM - 50 + {346, 98, 3, 3}, + // Mips::C_LE_D64 - 51 + {346, 101, 3, 3}, + // Mips::C_LE_D64_MM - 52 + {346, 104, 3, 3}, + // Mips::C_LE_S - 53 + {360, 107, 3, 3}, + // Mips::C_LE_S_MM - 54 + {360, 110, 3, 3}, + // Mips::C_LT_D32 - 55 + {374, 113, 3, 3}, + // Mips::C_LT_D32_MM - 56 + {374, 116, 3, 3}, + // Mips::C_LT_D64 - 57 + {374, 119, 3, 3}, + // Mips::C_LT_D64_MM - 58 + {374, 122, 3, 3}, + // Mips::C_LT_S - 59 + {388, 125, 3, 3}, + // Mips::C_LT_S_MM - 60 + {388, 128, 3, 3}, + // Mips::C_NGE_D32 - 61 + {402, 131, 3, 3}, + // Mips::C_NGE_D32_MM - 62 + {402, 134, 3, 3}, + // Mips::C_NGE_D64 - 63 + {402, 137, 3, 3}, + // Mips::C_NGE_D64_MM - 64 + {402, 140, 3, 3}, + // Mips::C_NGE_S - 65 + {417, 143, 3, 3}, + // Mips::C_NGE_S_MM - 66 + {417, 146, 3, 3}, + // Mips::C_NGLE_D32 - 67 + {432, 149, 3, 3}, + // Mips::C_NGLE_D32_MM - 68 + {432, 152, 3, 3}, + // Mips::C_NGLE_D64 - 69 + {432, 155, 3, 3}, + // Mips::C_NGLE_D64_MM - 70 + {432, 158, 3, 3}, + // Mips::C_NGLE_S - 71 + {448, 161, 3, 3}, + // Mips::C_NGLE_S_MM - 72 + {448, 164, 3, 3}, + // Mips::C_NGL_D32 - 73 + {464, 167, 3, 3}, + // Mips::C_NGL_D32_MM - 74 + {464, 170, 3, 3}, + // Mips::C_NGL_D64 - 75 + {464, 173, 3, 3}, + // Mips::C_NGL_D64_MM - 76 + {464, 176, 3, 3}, + // Mips::C_NGL_S - 77 + {479, 179, 3, 3}, + // Mips::C_NGL_S_MM - 78 + {479, 182, 3, 3}, + // Mips::C_NGT_D32 - 79 + {494, 185, 3, 3}, + // Mips::C_NGT_D32_MM - 80 + {494, 188, 3, 3}, + // Mips::C_NGT_D64 - 81 + {494, 191, 3, 3}, + // Mips::C_NGT_D64_MM - 82 + {494, 194, 3, 3}, + // Mips::C_NGT_S - 83 + {509, 197, 3, 3}, + // Mips::C_NGT_S_MM - 84 + {509, 200, 3, 3}, + // Mips::C_OLE_D32 - 85 + {524, 203, 3, 3}, + // Mips::C_OLE_D32_MM - 86 + {524, 206, 3, 3}, + // Mips::C_OLE_D64 - 87 + {524, 209, 3, 3}, + // Mips::C_OLE_D64_MM - 88 + {524, 212, 3, 3}, + // Mips::C_OLE_S - 89 + {539, 215, 3, 3}, + // Mips::C_OLE_S_MM - 90 + {539, 218, 3, 3}, + // Mips::C_OLT_D32 - 91 + {554, 221, 3, 3}, + // Mips::C_OLT_D32_MM - 92 + {554, 224, 3, 3}, + // Mips::C_OLT_D64 - 93 + {554, 227, 3, 3}, + // Mips::C_OLT_D64_MM - 94 + {554, 230, 3, 3}, + // Mips::C_OLT_S - 95 + {569, 233, 3, 3}, + // Mips::C_OLT_S_MM - 96 + {569, 236, 3, 3}, + // Mips::C_SEQ_D32 - 97 + {584, 239, 3, 3}, + // Mips::C_SEQ_D32_MM - 98 + {584, 242, 3, 3}, + // Mips::C_SEQ_D64 - 99 + {584, 245, 3, 3}, + // Mips::C_SEQ_D64_MM - 100 + {584, 248, 3, 3}, + // Mips::C_SEQ_S - 101 + {599, 251, 3, 3}, + // Mips::C_SEQ_S_MM - 102 + {599, 254, 3, 3}, + // Mips::C_SF_D32 - 103 + {614, 257, 3, 3}, + // Mips::C_SF_D32_MM - 104 + {614, 260, 3, 3}, + // Mips::C_SF_D64 - 105 + {614, 263, 3, 3}, + // Mips::C_SF_D64_MM - 106 + {614, 266, 3, 3}, + // Mips::C_SF_S - 107 + {628, 269, 3, 3}, + // Mips::C_SF_S_MM - 108 + {628, 272, 3, 3}, + // Mips::C_UEQ_D32 - 109 + {642, 275, 3, 3}, + // Mips::C_UEQ_D32_MM - 110 + {642, 278, 3, 3}, + // Mips::C_UEQ_D64 - 111 + {642, 281, 3, 3}, + // Mips::C_UEQ_D64_MM - 112 + {642, 284, 3, 3}, + // Mips::C_UEQ_S - 113 + {657, 287, 3, 3}, + // Mips::C_UEQ_S_MM - 114 + {657, 290, 3, 3}, + // Mips::C_ULE_D32 - 115 + {672, 293, 3, 3}, + // Mips::C_ULE_D32_MM - 116 + {672, 296, 3, 3}, + // Mips::C_ULE_D64 - 117 + {672, 299, 3, 3}, + // Mips::C_ULE_D64_MM - 118 + {672, 302, 3, 3}, + // Mips::C_ULE_S - 119 + {687, 305, 3, 3}, + // Mips::C_ULE_S_MM - 120 + {687, 308, 3, 3}, + // Mips::C_ULT_D32 - 121 + {702, 311, 3, 3}, + // Mips::C_ULT_D32_MM - 122 + {702, 314, 3, 3}, + // Mips::C_ULT_D64 - 123 + {702, 317, 3, 3}, + // Mips::C_ULT_D64_MM - 124 + {702, 320, 3, 3}, + // Mips::C_ULT_S - 125 + {717, 323, 3, 3}, + // Mips::C_ULT_S_MM - 126 + {717, 326, 3, 3}, + // Mips::C_UN_D32 - 127 + {732, 329, 3, 3}, + // Mips::C_UN_D32_MM - 128 + {732, 332, 3, 3}, + // Mips::C_UN_D64 - 129 + {732, 335, 3, 3}, + // Mips::C_UN_D64_MM - 130 + {732, 338, 3, 3}, + // Mips::C_UN_S - 131 + {746, 341, 3, 3}, + // Mips::C_UN_S_MM - 132 + {746, 344, 3, 3}, + // Mips::DADDu - 133 + {128, 347, 3, 3}, + // Mips::DI - 134 + {760, 350, 1, 1}, + // Mips::DIV - 135 + {763, 351, 3, 3}, + // Mips::DIVU - 136 + {774, 354, 3, 3}, + // Mips::DI_MM - 137 + {760, 357, 1, 1}, + // Mips::DI_MMR6 - 138 + {760, 358, 1, 1}, + // Mips::DMT - 139 + {786, 359, 1, 1}, + // Mips::DSUB - 140 + {790, 360, 3, 3}, + {802, 363, 3, 3}, + // Mips::DSUBu - 142 + {810, 366, 3, 3}, + {823, 369, 3, 3}, + // Mips::DVPE - 144 + {832, 372, 1, 1}, + // Mips::EI - 145 + {837, 373, 1, 1}, + // Mips::EI_MM - 146 + {837, 374, 1, 1}, + // Mips::EI_MMR6 - 147 + {837, 375, 1, 1}, + // Mips::EMT - 148 + {840, 376, 1, 1}, + // Mips::EVPE - 149 + {844, 377, 1, 1}, + // Mips::HYPCALL - 150 + {849, 378, 1, 1}, + // Mips::HYPCALL_MM - 151 + {849, 379, 1, 1}, + // Mips::JALR - 152 + {857, 380, 2, 2}, + // Mips::JALR64 - 153 + {857, 382, 2, 2}, + // Mips::JALRC_HB_MMR6 - 154 + {863, 384, 2, 2}, + // Mips::JALRC_MMR6 - 155 + {875, 386, 2, 2}, + // Mips::JALR_HB - 156 + {884, 388, 2, 2}, + // Mips::JALR_HB64 - 157 + {884, 390, 2, 2}, + // Mips::JIALC - 158 + {895, 392, 2, 2}, + // Mips::JIALC64 - 159 + {895, 394, 2, 2}, + // Mips::JIC - 160 + {904, 396, 2, 2}, + // Mips::JIC64 - 161 + {904, 398, 2, 2}, + // Mips::MOVE16_MM - 162 + {911, 400, 2, 2}, + // Mips::Move32R16 - 163 + {911, 402, 2, 2}, + // Mips::OR - 164 + {128, 404, 3, 3}, + // Mips::OR64 - 165 + {128, 407, 3, 3}, + // Mips::RDHWR - 166 + {915, 410, 3, 3}, + // Mips::RDHWR64 - 167 + {915, 413, 3, 3}, + // Mips::RDHWR_MM - 168 + {915, 416, 3, 3}, + // Mips::RDHWR_MMR6 - 169 + {915, 419, 3, 3}, + // Mips::SDBBP - 170 + {928, 422, 1, 1}, + // Mips::SDBBP_MMR6 - 171 + {928, 423, 1, 1}, + // Mips::SDBBP_R6 - 172 + {928, 424, 1, 1}, + // Mips::SIGRIE - 173 + {934, 425, 1, 1}, + // Mips::SIGRIE_MMR6 - 174 + {934, 426, 1, 1}, + // Mips::SLL - 175 + {911, 427, 3, 3}, + // Mips::SLL_MM - 176 + {911, 430, 3, 3}, + // Mips::SLL_MMR6 - 177 + {911, 433, 3, 3}, + // Mips::SUB - 178 + {941, 436, 3, 3}, + {952, 439, 3, 3}, + // Mips::SUBU_MMR6 - 180 + {959, 442, 3, 3}, + {971, 445, 3, 3}, + // Mips::SUB_MM - 182 + {941, 448, 3, 3}, + {952, 451, 3, 3}, + // Mips::SUB_MMR6 - 184 + {941, 454, 3, 3}, + {952, 457, 3, 3}, + // Mips::SUBu - 186 + {959, 460, 3, 3}, + {971, 463, 3, 3}, + // Mips::SUBu_MM - 188 + {959, 466, 3, 3}, + {971, 469, 3, 3}, + // Mips::SWSP_MM - 190 + {979, 472, 3, 1}, + // Mips::SYNC - 191 + {991, 473, 1, 1}, + // Mips::SYNC_MM - 192 + {991, 474, 1, 1}, + // Mips::SYNC_MMR6 - 193 + {991, 475, 1, 1}, + // Mips::SYSCALL - 194 + {996, 476, 1, 1}, + // Mips::SYSCALL_MM - 195 + {996, 477, 1, 1}, + // Mips::TEQ - 196 + {1004, 478, 3, 3}, + // Mips::TEQ_MM - 197 + {1004, 481, 3, 3}, + // Mips::TGE - 198 + {1015, 484, 3, 3}, + // Mips::TGEU - 199 + {1026, 487, 3, 3}, + // Mips::TGEU_MM - 200 + {1026, 490, 3, 3}, + // Mips::TGE_MM - 201 + {1015, 493, 3, 3}, + // Mips::TLT - 202 + {1038, 496, 3, 3}, + // Mips::TLTU - 203 + {1049, 499, 3, 3}, + // Mips::TLTU_MM - 204 + {1049, 502, 3, 3}, + // Mips::TLT_MM - 205 + {1038, 505, 3, 3}, + // Mips::TNE - 206 + {1061, 508, 3, 3}, + // Mips::TNE_MM - 207 + {1061, 511, 3, 3}, + // Mips::WAIT_MM - 208 + {1072, 514, 1, 1}, + // Mips::WRDSP - 209 + {1077, 515, 2, 2}, + // Mips::WRDSP_MM - 210 + {1077, 517, 2, 2}, + // Mips::YIELD - 211 + {1086, 519, 2, 2}, + }; + + static const AliasPatternCond Conds[] = { + // (MFTACX GPR32Opnd:$rt, AC0) - 0 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + // (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0) - 2 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MFTHI GPR32Opnd:$rt, AC0) - 5 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + // (MFTLO GPR32Opnd:$rt, AC0) - 7 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + // (MTTACX AC0, GPR32Opnd:$rt) - 9 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0) - 11 + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MTTHI AC0, GPR32Opnd:$rt) - 14 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (MTTLO AC0, GPR32Opnd:$rt) - 16 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm) - 18 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + // (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 20 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + // (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 22 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + // (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 24 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + // (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm) - 26 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm) - 27 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 28 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (BC1F FCC0, brtarget:$offset) - 31 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC1FL FCC0, brtarget:$offset) - 32 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC1F_MM FCC0, brtarget:$offset) - 33 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC1T FCC0, brtarget:$offset) - 34 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC1TL FCC0, brtarget:$offset) - 35 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC1T_MM FCC0, brtarget:$offset) - 36 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC2F FCC0, brtarget:$offset) - 37 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC2FL FCC0, brtarget:$offset) - 38 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC2T FCC0, brtarget:$offset) - 39 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC2TL FCC0, brtarget:$offset) - 40 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC3F FCC0, brtarget:$offset) - 41 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC3FL FCC0, brtarget:$offset) - 42 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC3T FCC0, brtarget:$offset) - 43 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC3TL FCC0, brtarget:$offset) - 44 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 45 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (BGEZAL ZERO, brtarget:$offset) - 47 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (BGEZAL_MM ZERO, brtarget_mm:$offset) - 48 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 49 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (BREAK 0, 0) - 51 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BREAK uimm10:$imm, 0) - 53 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BREAK_MM 0, 0) - 55 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BREAK_MM uimm10:$imm, 0) - 57 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (C_EQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 59 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_EQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 62 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_EQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 65 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_EQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 68 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_EQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 71 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_EQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 74 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_F_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 77 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_F_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 80 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_F_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 83 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_F_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 86 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_F_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 89 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_F_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 92 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_LE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 95 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_LE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 98 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_LE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 101 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_LE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 104 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_LE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 107 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_LE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 110 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_LT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 113 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_LT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 116 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_LT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 119 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_LT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 122 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_LT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 125 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_LT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 128 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 131 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 134 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 137 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 140 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 143 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 146 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 149 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 152 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 155 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 158 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 161 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 164 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGL_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 167 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGL_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 170 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGL_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 173 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGL_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 176 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGL_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 179 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGL_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 182 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 185 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 188 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 191 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 194 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 197 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 200 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_OLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 203 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_OLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 206 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_OLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 209 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_OLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 212 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_OLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 215 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_OLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 218 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_OLT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 221 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_OLT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 224 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_OLT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 227 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_OLT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 230 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_OLT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 233 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_OLT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 236 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_SEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 239 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_SEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 242 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_SEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 245 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_SEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 248 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_SEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 251 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_SEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 254 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_SF_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 257 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_SF_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 260 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_SF_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 263 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_SF_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 266 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_SF_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 269 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_SF_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 272 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_UEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 275 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_UEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 278 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_UEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 281 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_UEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 284 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_UEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 287 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_UEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 290 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_ULE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 293 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_ULE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 296 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_ULE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 299 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_ULE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 302 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_ULE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 305 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_ULE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 308 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_ULT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 311 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_ULT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 314 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_ULT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 317 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_ULT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 320 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_ULT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 323 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_ULT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 326 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_UN_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 329 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_UN_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 332 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_UN_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 335 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_UN_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 338 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_UN_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 341 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_UN_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 344 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 347 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + // (DI ZERO) - 350 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 351 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 354 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (DI_MM ZERO) - 357 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (DI_MMR6 ZERO) - 358 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (DMT ZERO) - 359 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 360 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 363 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_TiedReg, 0}, + // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 366 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 369 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_TiedReg, 0}, + // (DVPE ZERO) - 372 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (EI ZERO) - 373 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (EI_MM ZERO) - 374 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (EI_MMR6 ZERO) - 375 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (EMT ZERO) - 376 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (EVPE ZERO) - 377 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (HYPCALL 0) - 378 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (HYPCALL_MM 0) - 379 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JALR ZERO, GPR32Opnd:$rs) - 380 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (JALR64 ZERO_64, GPR64Opnd:$rs) - 382 + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + // (JALRC_HB_MMR6 RA, GPR32Opnd:$rs) - 384 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (JALRC_MMR6 RA, GPR32Opnd:$rs) - 386 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (JALR_HB RA, GPR32Opnd:$rs) - 388 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (JALR_HB64 RA_64, GPR64Opnd:$rs) - 390 + {AliasPatternCond_K_Reg, Mips_RA_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + // (JIALC GPR32Opnd:$rs, 0) - 392 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JIALC64 GPR64Opnd:$rs, 0) - 394 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JIC GPR32Opnd:$rs, 0) - 396 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JIC64 GPR64Opnd:$rs, 0) - 398 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MOVE16_MM ZERO, ZERO) - 400 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (Move32R16 ZERO, S0) - 402 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_S0}, + // (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 404 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 407 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + // (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 410 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0) - 413 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 416 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 419 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SDBBP 0) - 422 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SDBBP_MMR6 0) - 423 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SDBBP_R6 0) - 424 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SIGRIE 0) - 425 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SIGRIE_MMR6 0) - 426 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SLL ZERO, ZERO, 0) - 427 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SLL_MM ZERO, ZERO, 0) - 430 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SLL_MMR6 ZERO, ZERO, 0) - 433 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 436 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 439 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 442 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 445 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 448 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 451 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 454 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 457 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 460 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 463 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 466 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 469 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset) - 472 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SYNC 0) - 473 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SYNC_MM 0) - 474 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SYNC_MMR6 0) - 475 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SYSCALL 0) - 476 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SYSCALL_MM 0) - 477 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 478 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 481 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 484 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 487 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 490 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 493 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 496 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 499 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 502 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 505 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 508 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 511 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (WAIT_MM 0) - 514 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (WRDSP GPR32Opnd:$rt, 31) - 515 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (WRDSP_MM GPR32Opnd:$rt, 31) - 517 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (YIELD ZERO, GPR32Opnd:$rs) - 519 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + }; + + static const char *AsmStrings[] = { + /* 0 */ "mftacx $\x01\0" + /* 10 */ "mftc0 $\x01, $\x02\0" + /* 23 */ "mfthi $\x01\0" + /* 32 */ "mftlo $\x01\0" + /* 41 */ "mttacx $\x02\0" + /* 51 */ "mttc0 $\x02, $\x01\0" + /* 64 */ "mtthi $\x02\0" + /* 73 */ "mttlo $\x02\0" + /* 82 */ "nor $\x01, $\x03\0" + /* 93 */ "slt $\x01, $\x03\0" + /* 104 */ "sltu $\x01, $\x03\0" + /* 116 */ "lapc $\x01, $\x02\0" + /* 128 */ "move $\x01, $\x02\0" + /* 140 */ "bc1f $\x02\0" + /* 148 */ "bc1fl $\x02\0" + /* 157 */ "bc1t $\x02\0" + /* 165 */ "bc1tl $\x02\0" + /* 174 */ "bc2f $\x02\0" + /* 182 */ "bc2fl $\x02\0" + /* 191 */ "bc2t $\x02\0" + /* 199 */ "bc2tl $\x02\0" + /* 208 */ "bc3f $\x02\0" + /* 216 */ "bc3fl $\x02\0" + /* 225 */ "bc3t $\x02\0" + /* 233 */ "bc3tl $\x02\0" + /* 242 */ "beqzl $\x01, $\x03\0" + /* 255 */ "bal $\x02\0" + /* 262 */ "bnezl $\x01, $\x03\0" + /* 275 */ "break\0" + /* 281 */ "break $\xFF\x01\x01\0" + /* 292 */ "c.eq.d $\x02, $\x03\0" + /* 306 */ "c.eq.s $\x02, $\x03\0" + /* 320 */ "c.f.d $\x02, $\x03\0" + /* 333 */ "c.f.s $\x02, $\x03\0" + /* 346 */ "c.le.d $\x02, $\x03\0" + /* 360 */ "c.le.s $\x02, $\x03\0" + /* 374 */ "c.lt.d $\x02, $\x03\0" + /* 388 */ "c.lt.s $\x02, $\x03\0" + /* 402 */ "c.nge.d $\x02, $\x03\0" + /* 417 */ "c.nge.s $\x02, $\x03\0" + /* 432 */ "c.ngle.d $\x02, $\x03\0" + /* 448 */ "c.ngle.s $\x02, $\x03\0" + /* 464 */ "c.ngl.d $\x02, $\x03\0" + /* 479 */ "c.ngl.s $\x02, $\x03\0" + /* 494 */ "c.ngt.d $\x02, $\x03\0" + /* 509 */ "c.ngt.s $\x02, $\x03\0" + /* 524 */ "c.ole.d $\x02, $\x03\0" + /* 539 */ "c.ole.s $\x02, $\x03\0" + /* 554 */ "c.olt.d $\x02, $\x03\0" + /* 569 */ "c.olt.s $\x02, $\x03\0" + /* 584 */ "c.seq.d $\x02, $\x03\0" + /* 599 */ "c.seq.s $\x02, $\x03\0" + /* 614 */ "c.sf.d $\x02, $\x03\0" + /* 628 */ "c.sf.s $\x02, $\x03\0" + /* 642 */ "c.ueq.d $\x02, $\x03\0" + /* 657 */ "c.ueq.s $\x02, $\x03\0" + /* 672 */ "c.ule.d $\x02, $\x03\0" + /* 687 */ "c.ule.s $\x02, $\x03\0" + /* 702 */ "c.ult.d $\x02, $\x03\0" + /* 717 */ "c.ult.s $\x02, $\x03\0" + /* 732 */ "c.un.d $\x02, $\x03\0" + /* 746 */ "c.un.s $\x02, $\x03\0" + /* 760 */ "di\0" + /* 763 */ "div $\x01, $\x03\0" + /* 774 */ "divu $\x01, $\x03\0" + /* 786 */ "dmt\0" + /* 790 */ "dneg $\x01, $\x03\0" + /* 802 */ "dneg $\x01\0" + /* 810 */ "dnegu $\x01, $\x03\0" + /* 823 */ "dnegu $\x01\0" + /* 832 */ "dvpe\0" + /* 837 */ "ei\0" + /* 840 */ "emt\0" + /* 844 */ "evpe\0" + /* 849 */ "hypcall\0" + /* 857 */ "jr $\x02\0" + /* 863 */ "jalrc.hb $\x02\0" + /* 875 */ "jalrc $\x02\0" + /* 884 */ "jalr.hb $\x02\0" + /* 895 */ "jalrc $\x01\0" + /* 904 */ "jrc $\x01\0" + /* 911 */ "nop\0" + /* 915 */ "rdhwr $\x01, $\x02\0" + /* 928 */ "sdbbp\0" + /* 934 */ "sigrie\0" + /* 941 */ "neg $\x01, $\x03\0" + /* 952 */ "neg $\x01\0" + /* 959 */ "negu $\x01, $\x03\0" + /* 971 */ "negu $\x01\0" + /* 979 */ "sw $\x01, $\xFF\x02\x02\0" + /* 991 */ "sync\0" + /* 996 */ "syscall\0" + /* 1004 */ "teq $\x01, $\x02\0" + /* 1015 */ "tge $\x01, $\x02\0" + /* 1026 */ "tgeu $\x01, $\x02\0" + /* 1038 */ "tlt $\x01, $\x02\0" + /* 1049 */ "tltu $\x01, $\x02\0" + /* 1061 */ "tne $\x01, $\x02\0" + /* 1072 */ "wait\0" + /* 1077 */ "wrdsp $\x01\0" + /* 1086 */ "yield $\x02\0"}; + + const char *AsmString = MCInstPrinter_matchAliasPatterns( + MI, OpToPatterns, Patterns, Conds, AsmStrings, 202); + if (!AsmString) + return false; + + char *tmpString = cs_strdup(AsmString); + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') + ++I; + + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, "\t"); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, *(tmpString + (I++))); + } + } while (AsmString[I] != '\0'); + } + + return tmpString; +} + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { + switch (PrintMethodIdx) { + default: + llvm_unreachable("Unknown PrintMethod kind"); + break; + // printUImm<10> + case 0: + printUImm(MI, OpIdx, OS, 10); + break; + // printMemOperand + case 1: + printMemOperand(MI, OpIdx, OS, ""); + break; + } +} + +#endif // PRINT_ALIAS_INSTR +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const MCOperandInfo OperandInfo2[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo3[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo4[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo5[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo6[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo7[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo8[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo9[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo10[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo11[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo12[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo13[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo14[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo15[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo16[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo17[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo18[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo19[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo20[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo21[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo22[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo23[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo24[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo25[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo26[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo27[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo28[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo29[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo30[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo31[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo32[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo33[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo34[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo35[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo36[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo37[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo38[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo39[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo40[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo41[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo42[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo43[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo44[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo45[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo46[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo47[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo48[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo49[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo50[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo51[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo52[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo53[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo54[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo55[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo56[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo57[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo58[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo59[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo60[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo61[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo62[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo63[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo64[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo65[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGRCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo66[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo67[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo68[] = { + {Mips_FGRCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo69[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo70[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo71[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo72[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo73[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo74[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo75[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo76[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo77[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo78[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo79[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo80[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo81[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo82[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo83[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo84[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo85[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo86[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo87[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo88[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo89[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo90[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo91[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo92[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo93[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo94[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo95[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo96[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo97[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo98[] = { + {Mips_MSA128F16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo99[] = { + {Mips_ACC128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo100[] = { + {Mips_ACC64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo101[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo102[] = { + {Mips_DSPCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo103[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo104[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo105[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo106[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo107[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo108[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo109[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo110[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo111[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo112[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo113[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo114[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo115[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo116[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo117[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo118[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo119[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_COP0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo120[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo121[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo122[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128F16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo123[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128F16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo124[] = { + {Mips_MSA128F16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo125[] = { + {Mips_MSA128F16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo126[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo127[] = { + {Mips_COP0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo128[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo129[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo130[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo131[] = { + {Mips_DSPCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo132[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo133[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo134[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo135[] = { + {Mips_ACC128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo136[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo137[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo138[] = { + {Mips_ACC64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo139[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo140[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo141[] = { + {Mips_ACC64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo142[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo143[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo144[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo145[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo146[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo147[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo148[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo149[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo150[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo151[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo152[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo153[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo154[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo155[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo156[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo157[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo158[] = { + {Mips_GPR32NONZERORegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo159[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo160[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo161[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo162[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo163[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo164[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo165[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo166[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo167[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo168[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo169[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo170[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo171[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo172[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo173[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo174[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo175[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo176[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo177[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo178[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo179[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo180[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo181[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo182[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo183[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo184[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsPlusSPRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo185[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo186[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo187[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo188[] = { + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo189[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo190[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo191[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo192[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo193[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo194[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo195[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo196[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo197[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo198[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo199[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo200[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo201[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo202[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo203[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo204[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo205[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo206[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo207[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo208[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo209[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSACtrlRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo210[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo211[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo212[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo213[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo214[] = { + {Mips_FGRCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo215[] = { + {Mips_FGRCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo216[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo217[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo218[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo219[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo220[] = { + {Mips_CCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo221[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo222[] = { + {Mips_MSACtrlRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo223[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo224[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo225[] = { + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo226[] = { + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo227[] = { + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo228[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo229[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo230[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo231[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_COP0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo232[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo233[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo234[] = { + {Mips_COP0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo235[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo236[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo237[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo238[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo239[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo240[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo241[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo242[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo243[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo244[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo245[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo246[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo247[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo248[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo249[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo250[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo251[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo252[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo253[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo254[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo255[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo256[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo257[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo258[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo259[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo260[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo261[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo262[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo263[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo264[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo265[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo266[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo267[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo268[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo269[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo270[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo271[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo272[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {1, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo273[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo274[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo275[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo276[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo277[] = { + {Mips_COP3RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo278[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo279[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo280[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo281[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo282[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo283[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo284[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo285[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo286[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo287[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo288[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo289[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo290[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo291[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo292[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo293[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {3, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo294[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo295[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {2, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo296[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo297[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {2, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo298[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo299[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo300[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo301[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo302[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo303[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo304[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo305[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo306[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo307[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo308[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo309[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo310[] = { + {Mips_GPRMM16MovePPairFirstRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16MovePPairSecondRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16MovePRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16MovePRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo311[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo312[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo313[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo314[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo315[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo316[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo317[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo318[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo319[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo320[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo321[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo322[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo323[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo324[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo325[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo326[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo327[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo328[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo329[] = { + {Mips_HI32DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo330[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo331[] = { + {Mips_LO32DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo332[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo333[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo334[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo335[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo336[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo337[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo338[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo339[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo340[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_HWRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo341[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_HWRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo342[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo343[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo344[] = { + {Mips_GPRMM16ZeroRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {1, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo345[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo346[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo347[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo348[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo349[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGRCCRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo350[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo351[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo352[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo353[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo354[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo355[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo356[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo357[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo358[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo359[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo360[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo361[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo362[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo363[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo364[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; + +extern const MCInstrDesc MipsInsts[] = { + {1, OperandInfo2}, // Inst #0 = PHI + {0, NULL}, // Inst #1 = INLINEASM + {0, NULL}, // Inst #2 = INLINEASM_BR + {1, OperandInfo3}, // Inst #3 = CFI_INSTRUCTION + {1, OperandInfo3}, // Inst #4 = EH_LABEL + {1, OperandInfo3}, // Inst #5 = GC_LABEL + {1, OperandInfo3}, // Inst #6 = ANNOTATION_LABEL + {0, NULL}, // Inst #7 = KILL + {3, OperandInfo4}, // Inst #8 = EXTRACT_SUBREG + {4, OperandInfo5}, // Inst #9 = INSERT_SUBREG + {1, OperandInfo2}, // Inst #10 = IMPLICIT_DEF + {4, OperandInfo6}, // Inst #11 = SUBREG_TO_REG + {3, OperandInfo4}, // Inst #12 = COPY_TO_REGCLASS + {0, NULL}, // Inst #13 = DBG_VALUE + {0, NULL}, // Inst #14 = DBG_VALUE_LIST + {0, NULL}, // Inst #15 = DBG_INSTR_REF + {0, NULL}, // Inst #16 = DBG_PHI + {1, OperandInfo2}, // Inst #17 = DBG_LABEL + {2, OperandInfo7}, // Inst #18 = REG_SEQUENCE + {2, OperandInfo7}, // Inst #19 = COPY + {0, NULL}, // Inst #20 = BUNDLE + {1, OperandInfo3}, // Inst #21 = LIFETIME_START + {1, OperandInfo3}, // Inst #22 = LIFETIME_END + {4, OperandInfo8}, // Inst #23 = PSEUDO_PROBE + {2, OperandInfo9}, // Inst #24 = ARITH_FENCE + {2, OperandInfo10}, // Inst #25 = STACKMAP + {0, NULL}, // Inst #26 = FENTRY_CALL + {6, OperandInfo11}, // Inst #27 = PATCHPOINT + {1, OperandInfo12}, // Inst #28 = LOAD_STACK_GUARD + {1, OperandInfo3}, // Inst #29 = PREALLOCATED_SETUP + {3, OperandInfo13}, // Inst #30 = PREALLOCATED_ARG + {0, NULL}, // Inst #31 = STATEPOINT + {2, OperandInfo14}, // Inst #32 = LOCAL_ESCAPE + {1, OperandInfo2}, // Inst #33 = FAULTING_OP + {0, NULL}, // Inst #34 = PATCHABLE_OP + {0, NULL}, // Inst #35 = PATCHABLE_FUNCTION_ENTER + {0, NULL}, // Inst #36 = PATCHABLE_RET + {0, NULL}, // Inst #37 = PATCHABLE_FUNCTION_EXIT + {0, NULL}, // Inst #38 = PATCHABLE_TAIL_CALL + {2, OperandInfo15}, // Inst #39 = PATCHABLE_EVENT_CALL + {3, OperandInfo16}, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + {0, NULL}, // Inst #41 = ICALL_BRANCH_FUNNEL + {3, OperandInfo17}, // Inst #42 = G_ASSERT_SEXT + {3, OperandInfo17}, // Inst #43 = G_ASSERT_ZEXT + {3, OperandInfo18}, // Inst #44 = G_ADD + {3, OperandInfo18}, // Inst #45 = G_SUB + {3, OperandInfo18}, // Inst #46 = G_MUL + {3, OperandInfo18}, // Inst #47 = G_SDIV + {3, OperandInfo18}, // Inst #48 = G_UDIV + {3, OperandInfo18}, // Inst #49 = G_SREM + {3, OperandInfo18}, // Inst #50 = G_UREM + {4, OperandInfo19}, // Inst #51 = G_SDIVREM + {4, OperandInfo19}, // Inst #52 = G_UDIVREM + {3, OperandInfo18}, // Inst #53 = G_AND + {3, OperandInfo18}, // Inst #54 = G_OR + {3, OperandInfo18}, // Inst #55 = G_XOR + {1, OperandInfo20}, // Inst #56 = G_IMPLICIT_DEF + {1, OperandInfo20}, // Inst #57 = G_PHI + {2, OperandInfo21}, // Inst #58 = G_FRAME_INDEX + {2, OperandInfo21}, // Inst #59 = G_GLOBAL_VALUE + {3, OperandInfo22}, // Inst #60 = G_EXTRACT + {2, OperandInfo23}, // Inst #61 = G_UNMERGE_VALUES + {4, OperandInfo24}, // Inst #62 = G_INSERT + {2, OperandInfo23}, // Inst #63 = G_MERGE_VALUES + {2, OperandInfo23}, // Inst #64 = G_BUILD_VECTOR + {2, OperandInfo23}, // Inst #65 = G_BUILD_VECTOR_TRUNC + {2, OperandInfo23}, // Inst #66 = G_CONCAT_VECTORS + {2, OperandInfo23}, // Inst #67 = G_PTRTOINT + {2, OperandInfo23}, // Inst #68 = G_INTTOPTR + {2, OperandInfo23}, // Inst #69 = G_BITCAST + {2, OperandInfo25}, // Inst #70 = G_FREEZE + {2, OperandInfo25}, // Inst #71 = G_INTRINSIC_TRUNC + {2, OperandInfo25}, // Inst #72 = G_INTRINSIC_ROUND + {2, OperandInfo23}, // Inst #73 = G_INTRINSIC_LRINT + {2, OperandInfo25}, // Inst #74 = G_INTRINSIC_ROUNDEVEN + {1, OperandInfo20}, // Inst #75 = G_READCYCLECOUNTER + {2, OperandInfo23}, // Inst #76 = G_LOAD + {2, OperandInfo23}, // Inst #77 = G_SEXTLOAD + {2, OperandInfo23}, // Inst #78 = G_ZEXTLOAD + {5, OperandInfo26}, // Inst #79 = G_INDEXED_LOAD + {5, OperandInfo26}, // Inst #80 = G_INDEXED_SEXTLOAD + {5, OperandInfo26}, // Inst #81 = G_INDEXED_ZEXTLOAD + {2, OperandInfo23}, // Inst #82 = G_STORE + {5, OperandInfo27}, // Inst #83 = G_INDEXED_STORE + {5, OperandInfo28}, // Inst #84 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + {4, OperandInfo29}, // Inst #85 = G_ATOMIC_CMPXCHG + {3, OperandInfo30}, // Inst #86 = G_ATOMICRMW_XCHG + {3, OperandInfo30}, // Inst #87 = G_ATOMICRMW_ADD + {3, OperandInfo30}, // Inst #88 = G_ATOMICRMW_SUB + {3, OperandInfo30}, // Inst #89 = G_ATOMICRMW_AND + {3, OperandInfo30}, // Inst #90 = G_ATOMICRMW_NAND + {3, OperandInfo30}, // Inst #91 = G_ATOMICRMW_OR + {3, OperandInfo30}, // Inst #92 = G_ATOMICRMW_XOR + {3, OperandInfo30}, // Inst #93 = G_ATOMICRMW_MAX + {3, OperandInfo30}, // Inst #94 = G_ATOMICRMW_MIN + {3, OperandInfo30}, // Inst #95 = G_ATOMICRMW_UMAX + {3, OperandInfo30}, // Inst #96 = G_ATOMICRMW_UMIN + {3, OperandInfo30}, // Inst #97 = G_ATOMICRMW_FADD + {3, OperandInfo30}, // Inst #98 = G_ATOMICRMW_FSUB + {2, OperandInfo10}, // Inst #99 = G_FENCE + {2, OperandInfo21}, // Inst #100 = G_BRCOND + {1, OperandInfo20}, // Inst #101 = G_BRINDIRECT + {1, OperandInfo2}, // Inst #102 = G_INTRINSIC + {1, OperandInfo2}, // Inst #103 = G_INTRINSIC_W_SIDE_EFFECTS + {2, OperandInfo23}, // Inst #104 = G_ANYEXT + {2, OperandInfo23}, // Inst #105 = G_TRUNC + {2, OperandInfo21}, // Inst #106 = G_CONSTANT + {2, OperandInfo21}, // Inst #107 = G_FCONSTANT + {1, OperandInfo20}, // Inst #108 = G_VASTART + {3, OperandInfo31}, // Inst #109 = G_VAARG + {2, OperandInfo23}, // Inst #110 = G_SEXT + {3, OperandInfo17}, // Inst #111 = G_SEXT_INREG + {2, OperandInfo23}, // Inst #112 = G_ZEXT + {3, OperandInfo32}, // Inst #113 = G_SHL + {3, OperandInfo32}, // Inst #114 = G_LSHR + {3, OperandInfo32}, // Inst #115 = G_ASHR + {4, OperandInfo33}, // Inst #116 = G_FSHL + {4, OperandInfo33}, // Inst #117 = G_FSHR + {3, OperandInfo32}, // Inst #118 = G_ROTR + {3, OperandInfo32}, // Inst #119 = G_ROTL + {4, OperandInfo34}, // Inst #120 = G_ICMP + {4, OperandInfo34}, // Inst #121 = G_FCMP + {4, OperandInfo29}, // Inst #122 = G_SELECT + {4, OperandInfo29}, // Inst #123 = G_UADDO + {5, OperandInfo35}, // Inst #124 = G_UADDE + {4, OperandInfo29}, // Inst #125 = G_USUBO + {5, OperandInfo35}, // Inst #126 = G_USUBE + {4, OperandInfo29}, // Inst #127 = G_SADDO + {5, OperandInfo35}, // Inst #128 = G_SADDE + {4, OperandInfo29}, // Inst #129 = G_SSUBO + {5, OperandInfo35}, // Inst #130 = G_SSUBE + {4, OperandInfo29}, // Inst #131 = G_UMULO + {4, OperandInfo29}, // Inst #132 = G_SMULO + {3, OperandInfo18}, // Inst #133 = G_UMULH + {3, OperandInfo18}, // Inst #134 = G_SMULH + {3, OperandInfo18}, // Inst #135 = G_UADDSAT + {3, OperandInfo18}, // Inst #136 = G_SADDSAT + {3, OperandInfo18}, // Inst #137 = G_USUBSAT + {3, OperandInfo18}, // Inst #138 = G_SSUBSAT + {3, OperandInfo32}, // Inst #139 = G_USHLSAT + {3, OperandInfo32}, // Inst #140 = G_SSHLSAT + {4, OperandInfo36}, // Inst #141 = G_SMULFIX + {4, OperandInfo36}, // Inst #142 = G_UMULFIX + {4, OperandInfo36}, // Inst #143 = G_SMULFIXSAT + {4, OperandInfo36}, // Inst #144 = G_UMULFIXSAT + {4, OperandInfo36}, // Inst #145 = G_SDIVFIX + {4, OperandInfo36}, // Inst #146 = G_UDIVFIX + {4, OperandInfo36}, // Inst #147 = G_SDIVFIXSAT + {4, OperandInfo36}, // Inst #148 = G_UDIVFIXSAT + {3, OperandInfo18}, // Inst #149 = G_FADD + {3, OperandInfo18}, // Inst #150 = G_FSUB + {3, OperandInfo18}, // Inst #151 = G_FMUL + {4, OperandInfo19}, // Inst #152 = G_FMA + {4, OperandInfo19}, // Inst #153 = G_FMAD + {3, OperandInfo18}, // Inst #154 = G_FDIV + {3, OperandInfo18}, // Inst #155 = G_FREM + {3, OperandInfo18}, // Inst #156 = G_FPOW + {3, OperandInfo32}, // Inst #157 = G_FPOWI + {2, OperandInfo25}, // Inst #158 = G_FEXP + {2, OperandInfo25}, // Inst #159 = G_FEXP2 + {2, OperandInfo25}, // Inst #160 = G_FLOG + {2, OperandInfo25}, // Inst #161 = G_FLOG2 + {2, OperandInfo25}, // Inst #162 = G_FLOG10 + {2, OperandInfo25}, // Inst #163 = G_FNEG + {2, OperandInfo23}, // Inst #164 = G_FPEXT + {2, OperandInfo23}, // Inst #165 = G_FPTRUNC + {2, OperandInfo23}, // Inst #166 = G_FPTOSI + {2, OperandInfo23}, // Inst #167 = G_FPTOUI + {2, OperandInfo23}, // Inst #168 = G_SITOFP + {2, OperandInfo23}, // Inst #169 = G_UITOFP + {2, OperandInfo25}, // Inst #170 = G_FABS + {3, OperandInfo32}, // Inst #171 = G_FCOPYSIGN + {2, OperandInfo25}, // Inst #172 = G_FCANONICALIZE + {3, OperandInfo18}, // Inst #173 = G_FMINNUM + {3, OperandInfo18}, // Inst #174 = G_FMAXNUM + {3, OperandInfo18}, // Inst #175 = G_FMINNUM_IEEE + {3, OperandInfo18}, // Inst #176 = G_FMAXNUM_IEEE + {3, OperandInfo18}, // Inst #177 = G_FMINIMUM + {3, OperandInfo18}, // Inst #178 = G_FMAXIMUM + {3, OperandInfo32}, // Inst #179 = G_PTR_ADD + {3, OperandInfo32}, // Inst #180 = G_PTRMASK + {3, OperandInfo18}, // Inst #181 = G_SMIN + {3, OperandInfo18}, // Inst #182 = G_SMAX + {3, OperandInfo18}, // Inst #183 = G_UMIN + {3, OperandInfo18}, // Inst #184 = G_UMAX + {2, OperandInfo25}, // Inst #185 = G_ABS + {2, OperandInfo23}, // Inst #186 = G_LROUND + {2, OperandInfo23}, // Inst #187 = G_LLROUND + {1, OperandInfo2}, // Inst #188 = G_BR + {3, OperandInfo37}, // Inst #189 = G_BRJT + {4, OperandInfo38}, // Inst #190 = G_INSERT_VECTOR_ELT + {3, OperandInfo39}, // Inst #191 = G_EXTRACT_VECTOR_ELT + {4, OperandInfo40}, // Inst #192 = G_SHUFFLE_VECTOR + {2, OperandInfo23}, // Inst #193 = G_CTTZ + {2, OperandInfo23}, // Inst #194 = G_CTTZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #195 = G_CTLZ + {2, OperandInfo23}, // Inst #196 = G_CTLZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #197 = G_CTPOP + {2, OperandInfo25}, // Inst #198 = G_BSWAP + {2, OperandInfo25}, // Inst #199 = G_BITREVERSE + {2, OperandInfo25}, // Inst #200 = G_FCEIL + {2, OperandInfo25}, // Inst #201 = G_FCOS + {2, OperandInfo25}, // Inst #202 = G_FSIN + {2, OperandInfo25}, // Inst #203 = G_FSQRT + {2, OperandInfo25}, // Inst #204 = G_FFLOOR + {2, OperandInfo25}, // Inst #205 = G_FRINT + {2, OperandInfo25}, // Inst #206 = G_FNEARBYINT + {2, OperandInfo23}, // Inst #207 = G_ADDRSPACE_CAST + {2, OperandInfo21}, // Inst #208 = G_BLOCK_ADDR + {2, OperandInfo21}, // Inst #209 = G_JUMP_TABLE + {3, OperandInfo22}, // Inst #210 = G_DYN_STACKALLOC + {3, OperandInfo18}, // Inst #211 = G_STRICT_FADD + {3, OperandInfo18}, // Inst #212 = G_STRICT_FSUB + {3, OperandInfo18}, // Inst #213 = G_STRICT_FMUL + {3, OperandInfo18}, // Inst #214 = G_STRICT_FDIV + {3, OperandInfo18}, // Inst #215 = G_STRICT_FREM + {4, OperandInfo19}, // Inst #216 = G_STRICT_FMA + {2, OperandInfo25}, // Inst #217 = G_STRICT_FSQRT + {2, OperandInfo21}, // Inst #218 = G_READ_REGISTER + {2, OperandInfo41}, // Inst #219 = G_WRITE_REGISTER + {4, OperandInfo42}, // Inst #220 = G_MEMCPY + {3, OperandInfo39}, // Inst #221 = G_MEMCPY_INLINE + {4, OperandInfo42}, // Inst #222 = G_MEMMOVE + {4, OperandInfo42}, // Inst #223 = G_MEMSET + {3, OperandInfo22}, // Inst #224 = G_BZERO + {3, OperandInfo39}, // Inst #225 = G_VECREDUCE_SEQ_FADD + {3, OperandInfo39}, // Inst #226 = G_VECREDUCE_SEQ_FMUL + {2, OperandInfo23}, // Inst #227 = G_VECREDUCE_FADD + {2, OperandInfo23}, // Inst #228 = G_VECREDUCE_FMUL + {2, OperandInfo23}, // Inst #229 = G_VECREDUCE_FMAX + {2, OperandInfo23}, // Inst #230 = G_VECREDUCE_FMIN + {2, OperandInfo23}, // Inst #231 = G_VECREDUCE_ADD + {2, OperandInfo23}, // Inst #232 = G_VECREDUCE_MUL + {2, OperandInfo23}, // Inst #233 = G_VECREDUCE_AND + {2, OperandInfo23}, // Inst #234 = G_VECREDUCE_OR + {2, OperandInfo23}, // Inst #235 = G_VECREDUCE_XOR + {2, OperandInfo23}, // Inst #236 = G_VECREDUCE_SMAX + {2, OperandInfo23}, // Inst #237 = G_VECREDUCE_SMIN + {2, OperandInfo23}, // Inst #238 = G_VECREDUCE_UMAX + {2, OperandInfo23}, // Inst #239 = G_VECREDUCE_UMIN + {4, OperandInfo43}, // Inst #240 = G_SBFX + {4, OperandInfo43}, // Inst #241 = G_UBFX + {2, OperandInfo44}, // Inst #242 = ABSMacro + {2, OperandInfo10}, // Inst #243 = ADJCALLSTACKDOWN + {2, OperandInfo10}, // Inst #244 = ADJCALLSTACKUP + {3, OperandInfo45}, // Inst #245 = AND_V_D_PSEUDO + {3, OperandInfo46}, // Inst #246 = AND_V_H_PSEUDO + {3, OperandInfo47}, // Inst #247 = AND_V_W_PSEUDO + {4, OperandInfo48}, // Inst #248 = ATOMIC_CMP_SWAP_I16 + {7, OperandInfo49}, // Inst #249 = ATOMIC_CMP_SWAP_I16_POSTRA + {4, OperandInfo48}, // Inst #250 = ATOMIC_CMP_SWAP_I32 + {4, OperandInfo48}, // Inst #251 = ATOMIC_CMP_SWAP_I32_POSTRA + {4, OperandInfo50}, // Inst #252 = ATOMIC_CMP_SWAP_I64 + {4, OperandInfo50}, // Inst #253 = ATOMIC_CMP_SWAP_I64_POSTRA + {4, OperandInfo48}, // Inst #254 = ATOMIC_CMP_SWAP_I8 + {7, OperandInfo49}, // Inst #255 = ATOMIC_CMP_SWAP_I8_POSTRA + {3, OperandInfo51}, // Inst #256 = ATOMIC_LOAD_ADD_I16 + {6, OperandInfo52}, // Inst #257 = ATOMIC_LOAD_ADD_I16_POSTRA + {3, OperandInfo51}, // Inst #258 = ATOMIC_LOAD_ADD_I32 + {3, OperandInfo51}, // Inst #259 = ATOMIC_LOAD_ADD_I32_POSTRA + {3, OperandInfo53}, // Inst #260 = ATOMIC_LOAD_ADD_I64 + {3, OperandInfo53}, // Inst #261 = ATOMIC_LOAD_ADD_I64_POSTRA + {3, OperandInfo51}, // Inst #262 = ATOMIC_LOAD_ADD_I8 + {6, OperandInfo52}, // Inst #263 = ATOMIC_LOAD_ADD_I8_POSTRA + {3, OperandInfo51}, // Inst #264 = ATOMIC_LOAD_AND_I16 + {6, OperandInfo52}, // Inst #265 = ATOMIC_LOAD_AND_I16_POSTRA + {3, OperandInfo51}, // Inst #266 = ATOMIC_LOAD_AND_I32 + {3, OperandInfo51}, // Inst #267 = ATOMIC_LOAD_AND_I32_POSTRA + {3, OperandInfo53}, // Inst #268 = ATOMIC_LOAD_AND_I64 + {3, OperandInfo53}, // Inst #269 = ATOMIC_LOAD_AND_I64_POSTRA + {3, OperandInfo51}, // Inst #270 = ATOMIC_LOAD_AND_I8 + {6, OperandInfo52}, // Inst #271 = ATOMIC_LOAD_AND_I8_POSTRA + {3, OperandInfo51}, // Inst #272 = ATOMIC_LOAD_MAX_I16 + {6, OperandInfo52}, // Inst #273 = ATOMIC_LOAD_MAX_I16_POSTRA + {3, OperandInfo51}, // Inst #274 = ATOMIC_LOAD_MAX_I32 + {3, OperandInfo51}, // Inst #275 = ATOMIC_LOAD_MAX_I32_POSTRA + {3, OperandInfo53}, // Inst #276 = ATOMIC_LOAD_MAX_I64 + {3, OperandInfo53}, // Inst #277 = ATOMIC_LOAD_MAX_I64_POSTRA + {3, OperandInfo51}, // Inst #278 = ATOMIC_LOAD_MAX_I8 + {6, OperandInfo52}, // Inst #279 = ATOMIC_LOAD_MAX_I8_POSTRA + {3, OperandInfo51}, // Inst #280 = ATOMIC_LOAD_MIN_I16 + {6, OperandInfo52}, // Inst #281 = ATOMIC_LOAD_MIN_I16_POSTRA + {3, OperandInfo51}, // Inst #282 = ATOMIC_LOAD_MIN_I32 + {3, OperandInfo51}, // Inst #283 = ATOMIC_LOAD_MIN_I32_POSTRA + {3, OperandInfo53}, // Inst #284 = ATOMIC_LOAD_MIN_I64 + {3, OperandInfo53}, // Inst #285 = ATOMIC_LOAD_MIN_I64_POSTRA + {3, OperandInfo51}, // Inst #286 = ATOMIC_LOAD_MIN_I8 + {6, OperandInfo52}, // Inst #287 = ATOMIC_LOAD_MIN_I8_POSTRA + {3, OperandInfo51}, // Inst #288 = ATOMIC_LOAD_NAND_I16 + {6, OperandInfo52}, // Inst #289 = ATOMIC_LOAD_NAND_I16_POSTRA + {3, OperandInfo51}, // Inst #290 = ATOMIC_LOAD_NAND_I32 + {3, OperandInfo51}, // Inst #291 = ATOMIC_LOAD_NAND_I32_POSTRA + {3, OperandInfo53}, // Inst #292 = ATOMIC_LOAD_NAND_I64 + {3, OperandInfo53}, // Inst #293 = ATOMIC_LOAD_NAND_I64_POSTRA + {3, OperandInfo51}, // Inst #294 = ATOMIC_LOAD_NAND_I8 + {6, OperandInfo52}, // Inst #295 = ATOMIC_LOAD_NAND_I8_POSTRA + {3, OperandInfo51}, // Inst #296 = ATOMIC_LOAD_OR_I16 + {6, OperandInfo52}, // Inst #297 = ATOMIC_LOAD_OR_I16_POSTRA + {3, OperandInfo51}, // Inst #298 = ATOMIC_LOAD_OR_I32 + {3, OperandInfo51}, // Inst #299 = ATOMIC_LOAD_OR_I32_POSTRA + {3, OperandInfo53}, // Inst #300 = ATOMIC_LOAD_OR_I64 + {3, OperandInfo53}, // Inst #301 = ATOMIC_LOAD_OR_I64_POSTRA + {3, OperandInfo51}, // Inst #302 = ATOMIC_LOAD_OR_I8 + {6, OperandInfo52}, // Inst #303 = ATOMIC_LOAD_OR_I8_POSTRA + {3, OperandInfo51}, // Inst #304 = ATOMIC_LOAD_SUB_I16 + {6, OperandInfo52}, // Inst #305 = ATOMIC_LOAD_SUB_I16_POSTRA + {3, OperandInfo51}, // Inst #306 = ATOMIC_LOAD_SUB_I32 + {3, OperandInfo51}, // Inst #307 = ATOMIC_LOAD_SUB_I32_POSTRA + {3, OperandInfo53}, // Inst #308 = ATOMIC_LOAD_SUB_I64 + {3, OperandInfo53}, // Inst #309 = ATOMIC_LOAD_SUB_I64_POSTRA + {3, OperandInfo51}, // Inst #310 = ATOMIC_LOAD_SUB_I8 + {6, OperandInfo52}, // Inst #311 = ATOMIC_LOAD_SUB_I8_POSTRA + {3, OperandInfo51}, // Inst #312 = ATOMIC_LOAD_UMAX_I16 + {6, OperandInfo52}, // Inst #313 = ATOMIC_LOAD_UMAX_I16_POSTRA + {3, OperandInfo51}, // Inst #314 = ATOMIC_LOAD_UMAX_I32 + {3, OperandInfo51}, // Inst #315 = ATOMIC_LOAD_UMAX_I32_POSTRA + {3, OperandInfo53}, // Inst #316 = ATOMIC_LOAD_UMAX_I64 + {3, OperandInfo53}, // Inst #317 = ATOMIC_LOAD_UMAX_I64_POSTRA + {3, OperandInfo51}, // Inst #318 = ATOMIC_LOAD_UMAX_I8 + {6, OperandInfo52}, // Inst #319 = ATOMIC_LOAD_UMAX_I8_POSTRA + {3, OperandInfo51}, // Inst #320 = ATOMIC_LOAD_UMIN_I16 + {6, OperandInfo52}, // Inst #321 = ATOMIC_LOAD_UMIN_I16_POSTRA + {3, OperandInfo51}, // Inst #322 = ATOMIC_LOAD_UMIN_I32 + {3, OperandInfo51}, // Inst #323 = ATOMIC_LOAD_UMIN_I32_POSTRA + {3, OperandInfo53}, // Inst #324 = ATOMIC_LOAD_UMIN_I64 + {3, OperandInfo53}, // Inst #325 = ATOMIC_LOAD_UMIN_I64_POSTRA + {3, OperandInfo51}, // Inst #326 = ATOMIC_LOAD_UMIN_I8 + {6, OperandInfo52}, // Inst #327 = ATOMIC_LOAD_UMIN_I8_POSTRA + {3, OperandInfo51}, // Inst #328 = ATOMIC_LOAD_XOR_I16 + {6, OperandInfo52}, // Inst #329 = ATOMIC_LOAD_XOR_I16_POSTRA + {3, OperandInfo51}, // Inst #330 = ATOMIC_LOAD_XOR_I32 + {3, OperandInfo51}, // Inst #331 = ATOMIC_LOAD_XOR_I32_POSTRA + {3, OperandInfo53}, // Inst #332 = ATOMIC_LOAD_XOR_I64 + {3, OperandInfo53}, // Inst #333 = ATOMIC_LOAD_XOR_I64_POSTRA + {3, OperandInfo51}, // Inst #334 = ATOMIC_LOAD_XOR_I8 + {6, OperandInfo52}, // Inst #335 = ATOMIC_LOAD_XOR_I8_POSTRA + {3, OperandInfo51}, // Inst #336 = ATOMIC_SWAP_I16 + {6, OperandInfo52}, // Inst #337 = ATOMIC_SWAP_I16_POSTRA + {3, OperandInfo51}, // Inst #338 = ATOMIC_SWAP_I32 + {3, OperandInfo51}, // Inst #339 = ATOMIC_SWAP_I32_POSTRA + {3, OperandInfo53}, // Inst #340 = ATOMIC_SWAP_I64 + {3, OperandInfo53}, // Inst #341 = ATOMIC_SWAP_I64_POSTRA + {3, OperandInfo51}, // Inst #342 = ATOMIC_SWAP_I8 + {6, OperandInfo52}, // Inst #343 = ATOMIC_SWAP_I8_POSTRA + {1, OperandInfo54}, // Inst #344 = B + {1, OperandInfo54}, // Inst #345 = BAL_BR + {1, OperandInfo54}, // Inst #346 = BAL_BR_MM + {3, OperandInfo55}, // Inst #347 = BEQLImmMacro + {3, OperandInfo56}, // Inst #348 = BGE + {3, OperandInfo55}, // Inst #349 = BGEImmMacro + {3, OperandInfo56}, // Inst #350 = BGEL + {3, OperandInfo55}, // Inst #351 = BGELImmMacro + {3, OperandInfo56}, // Inst #352 = BGEU + {3, OperandInfo55}, // Inst #353 = BGEUImmMacro + {3, OperandInfo56}, // Inst #354 = BGEUL + {3, OperandInfo55}, // Inst #355 = BGEULImmMacro + {3, OperandInfo56}, // Inst #356 = BGT + {3, OperandInfo55}, // Inst #357 = BGTImmMacro + {3, OperandInfo56}, // Inst #358 = BGTL + {3, OperandInfo55}, // Inst #359 = BGTLImmMacro + {3, OperandInfo56}, // Inst #360 = BGTU + {3, OperandInfo55}, // Inst #361 = BGTUImmMacro + {3, OperandInfo56}, // Inst #362 = BGTUL + {3, OperandInfo55}, // Inst #363 = BGTULImmMacro + {3, OperandInfo56}, // Inst #364 = BLE + {3, OperandInfo55}, // Inst #365 = BLEImmMacro + {3, OperandInfo56}, // Inst #366 = BLEL + {3, OperandInfo55}, // Inst #367 = BLELImmMacro + {3, OperandInfo56}, // Inst #368 = BLEU + {3, OperandInfo55}, // Inst #369 = BLEUImmMacro + {3, OperandInfo56}, // Inst #370 = BLEUL + {3, OperandInfo55}, // Inst #371 = BLEULImmMacro + {3, OperandInfo56}, // Inst #372 = BLT + {3, OperandInfo55}, // Inst #373 = BLTImmMacro + {3, OperandInfo56}, // Inst #374 = BLTL + {3, OperandInfo55}, // Inst #375 = BLTLImmMacro + {3, OperandInfo56}, // Inst #376 = BLTU + {3, OperandInfo55}, // Inst #377 = BLTUImmMacro + {3, OperandInfo56}, // Inst #378 = BLTUL + {3, OperandInfo55}, // Inst #379 = BLTULImmMacro + {3, OperandInfo55}, // Inst #380 = BNELImmMacro + {1, OperandInfo57}, // Inst #381 = BPOSGE32_PSEUDO + {4, OperandInfo58}, // Inst #382 = BSEL_D_PSEUDO + {4, OperandInfo58}, // Inst #383 = BSEL_FD_PSEUDO + {4, OperandInfo59}, // Inst #384 = BSEL_FW_PSEUDO + {4, OperandInfo60}, // Inst #385 = BSEL_H_PSEUDO + {4, OperandInfo59}, // Inst #386 = BSEL_W_PSEUDO + {1, OperandInfo54}, // Inst #387 = B_MM + {1, OperandInfo54}, // Inst #388 = B_MMR6_Pseudo + {1, OperandInfo54}, // Inst #389 = B_MM_Pseudo + {3, OperandInfo55}, // Inst #390 = BeqImm + {3, OperandInfo55}, // Inst #391 = BneImm + {3, OperandInfo61}, // Inst #392 = BteqzT8CmpX16 + {3, OperandInfo62}, // Inst #393 = BteqzT8CmpiX16 + {3, OperandInfo61}, // Inst #394 = BteqzT8SltX16 + {3, OperandInfo62}, // Inst #395 = BteqzT8SltiX16 + {3, OperandInfo62}, // Inst #396 = BteqzT8SltiuX16 + {3, OperandInfo61}, // Inst #397 = BteqzT8SltuX16 + {3, OperandInfo61}, // Inst #398 = BtnezT8CmpX16 + {3, OperandInfo62}, // Inst #399 = BtnezT8CmpiX16 + {3, OperandInfo61}, // Inst #400 = BtnezT8SltX16 + {3, OperandInfo62}, // Inst #401 = BtnezT8SltiX16 + {3, OperandInfo62}, // Inst #402 = BtnezT8SltiuX16 + {3, OperandInfo61}, // Inst #403 = BtnezT8SltuX16 + {3, OperandInfo63}, // Inst #404 = BuildPairF64 + {3, OperandInfo64}, // Inst #405 = BuildPairF64_64 + {2, OperandInfo65}, // Inst #406 = CFTC1 + {3, OperandInfo4}, // Inst #407 = CONSTPOOL_ENTRY + {3, OperandInfo66}, // Inst #408 = COPY_FD_PSEUDO + {3, OperandInfo67}, // Inst #409 = COPY_FW_PSEUDO + {2, OperandInfo68}, // Inst #410 = CTTC1 + {1, OperandInfo2}, // Inst #411 = Constant32 + {3, OperandInfo69}, // Inst #412 = DMULImmMacro + {3, OperandInfo70}, // Inst #413 = DMULMacro + {3, OperandInfo70}, // Inst #414 = DMULOMacro + {3, OperandInfo70}, // Inst #415 = DMULOUMacro + {3, OperandInfo71}, // Inst #416 = DROL + {3, OperandInfo72}, // Inst #417 = DROLImm + {3, OperandInfo71}, // Inst #418 = DROR + {3, OperandInfo72}, // Inst #419 = DRORImm + {3, OperandInfo69}, // Inst #420 = DSDivIMacro + {3, OperandInfo70}, // Inst #421 = DSDivMacro + {3, OperandInfo69}, // Inst #422 = DSRemIMacro + {3, OperandInfo70}, // Inst #423 = DSRemMacro + {3, OperandInfo69}, // Inst #424 = DUDivIMacro + {3, OperandInfo70}, // Inst #425 = DUDivMacro + {3, OperandInfo69}, // Inst #426 = DURemIMacro + {3, OperandInfo70}, // Inst #427 = DURemMacro + {0, NULL}, // Inst #428 = ERet + {3, OperandInfo73}, // Inst #429 = ExtractElementF64 + {3, OperandInfo74}, // Inst #430 = ExtractElementF64_64 + {2, OperandInfo75}, // Inst #431 = FABS_D + {2, OperandInfo76}, // Inst #432 = FABS_W + {2, OperandInfo75}, // Inst #433 = FEXP2_D_1_PSEUDO + {2, OperandInfo76}, // Inst #434 = FEXP2_W_1_PSEUDO + {2, OperandInfo77}, // Inst #435 = FILL_FD_PSEUDO + {2, OperandInfo78}, // Inst #436 = FILL_FW_PSEUDO + {4, OperandInfo79}, // Inst #437 = GotPrologue16 + {4, OperandInfo80}, // Inst #438 = INSERT_B_VIDX64_PSEUDO + {4, OperandInfo81}, // Inst #439 = INSERT_B_VIDX_PSEUDO + {4, OperandInfo82}, // Inst #440 = INSERT_D_VIDX64_PSEUDO + {4, OperandInfo83}, // Inst #441 = INSERT_D_VIDX_PSEUDO + {4, OperandInfo84}, // Inst #442 = INSERT_FD_PSEUDO + {4, OperandInfo85}, // Inst #443 = INSERT_FD_VIDX64_PSEUDO + {4, OperandInfo86}, // Inst #444 = INSERT_FD_VIDX_PSEUDO + {4, OperandInfo87}, // Inst #445 = INSERT_FW_PSEUDO + {4, OperandInfo88}, // Inst #446 = INSERT_FW_VIDX64_PSEUDO + {4, OperandInfo89}, // Inst #447 = INSERT_FW_VIDX_PSEUDO + {4, OperandInfo90}, // Inst #448 = INSERT_H_VIDX64_PSEUDO + {4, OperandInfo91}, // Inst #449 = INSERT_H_VIDX_PSEUDO + {4, OperandInfo92}, // Inst #450 = INSERT_W_VIDX64_PSEUDO + {4, OperandInfo93}, // Inst #451 = INSERT_W_VIDX_PSEUDO + {1, OperandInfo94}, // Inst #452 = JALR64Pseudo + {1, OperandInfo94}, // Inst #453 = JALRHB64Pseudo + {1, OperandInfo57}, // Inst #454 = JALRHBPseudo + {1, OperandInfo57}, // Inst #455 = JALRPseudo + {1, OperandInfo2}, // Inst #456 = JAL_MMR6 + {1, OperandInfo57}, // Inst #457 = JalOneReg + {2, OperandInfo44}, // Inst #458 = JalTwoReg + {3, OperandInfo95}, // Inst #459 = LDMacro + {3, OperandInfo96}, // Inst #460 = LDR_D + {3, OperandInfo97}, // Inst #461 = LDR_W + {3, OperandInfo98}, // Inst #462 = LD_F16 + {3, OperandInfo99}, // Inst #463 = LOAD_ACC128 + {3, OperandInfo100}, // Inst #464 = LOAD_ACC64 + {3, OperandInfo101}, // Inst #465 = LOAD_ACC64DSP + {3, OperandInfo102}, // Inst #466 = LOAD_CCOND_DSP + {4, OperandInfo103}, // Inst #467 = LONG_BRANCH_ADDiu + {3, OperandInfo56}, // Inst #468 = LONG_BRANCH_ADDiu2Op + {4, OperandInfo104}, // Inst #469 = LONG_BRANCH_DADDiu + {3, OperandInfo105}, // Inst #470 = LONG_BRANCH_DADDiu2Op + {3, OperandInfo106}, // Inst #471 = LONG_BRANCH_LUi + {2, OperandInfo107}, // Inst #472 = LONG_BRANCH_LUi2Op + {2, OperandInfo108}, // Inst #473 = LONG_BRANCH_LUi2Op_64 + {3, OperandInfo109}, // Inst #474 = LWM_MM + {2, OperandInfo110}, // Inst #475 = LoadAddrImm32 + {2, OperandInfo111}, // Inst #476 = LoadAddrImm64 + {3, OperandInfo95}, // Inst #477 = LoadAddrReg32 + {3, OperandInfo112}, // Inst #478 = LoadAddrReg64 + {2, OperandInfo113}, // Inst #479 = LoadImm32 + {2, OperandInfo111}, // Inst #480 = LoadImm64 + {2, OperandInfo114}, // Inst #481 = LoadImmDoubleFGR + {2, OperandInfo115}, // Inst #482 = LoadImmDoubleFGR_32 + {2, OperandInfo113}, // Inst #483 = LoadImmDoubleGPR + {2, OperandInfo116}, // Inst #484 = LoadImmSingleFGR + {2, OperandInfo113}, // Inst #485 = LoadImmSingleGPR + {3, OperandInfo117}, // Inst #486 = LwConstant32 + {2, OperandInfo118}, // Inst #487 = MFTACX + {3, OperandInfo119}, // Inst #488 = MFTC0 + {2, OperandInfo120}, // Inst #489 = MFTC1 + {1, OperandInfo57}, // Inst #490 = MFTDSP + {3, OperandInfo72}, // Inst #491 = MFTGPR + {2, OperandInfo120}, // Inst #492 = MFTHC1 + {2, OperandInfo118}, // Inst #493 = MFTHI + {2, OperandInfo118}, // Inst #494 = MFTLO + {2, OperandInfo44}, // Inst #495 = MIPSeh_return32 + {2, OperandInfo121}, // Inst #496 = MIPSeh_return64 + {2, OperandInfo122}, // Inst #497 = MSA_FP_EXTEND_D_PSEUDO + {2, OperandInfo123}, // Inst #498 = MSA_FP_EXTEND_W_PSEUDO + {2, OperandInfo124}, // Inst #499 = MSA_FP_ROUND_D_PSEUDO + {2, OperandInfo125}, // Inst #500 = MSA_FP_ROUND_W_PSEUDO + {2, OperandInfo126}, // Inst #501 = MTTACX + {3, OperandInfo127}, // Inst #502 = MTTC0 + {2, OperandInfo128}, // Inst #503 = MTTC1 + {1, OperandInfo57}, // Inst #504 = MTTDSP + {2, OperandInfo44}, // Inst #505 = MTTGPR + {2, OperandInfo128}, // Inst #506 = MTTHC1 + {2, OperandInfo126}, // Inst #507 = MTTHI + {2, OperandInfo126}, // Inst #508 = MTTLO + {3, OperandInfo72}, // Inst #509 = MULImmMacro + {3, OperandInfo71}, // Inst #510 = MULOMacro + {3, OperandInfo71}, // Inst #511 = MULOUMacro + {2, OperandInfo129}, // Inst #512 = MultRxRy16 + {3, OperandInfo130}, // Inst #513 = MultRxRyRz16 + {2, OperandInfo129}, // Inst #514 = MultuRxRy16 + {3, OperandInfo130}, // Inst #515 = MultuRxRyRz16 + {0, NULL}, // Inst #516 = NOP + {3, OperandInfo72}, // Inst #517 = NORImm + {3, OperandInfo69}, // Inst #518 = NORImm64 + {3, OperandInfo45}, // Inst #519 = NOR_V_D_PSEUDO + {3, OperandInfo46}, // Inst #520 = NOR_V_H_PSEUDO + {3, OperandInfo47}, // Inst #521 = NOR_V_W_PSEUDO + {3, OperandInfo45}, // Inst #522 = OR_V_D_PSEUDO + {3, OperandInfo46}, // Inst #523 = OR_V_H_PSEUDO + {3, OperandInfo47}, // Inst #524 = OR_V_W_PSEUDO + {3, OperandInfo131}, // Inst #525 = PseudoCMPU_EQ_QB + {3, OperandInfo131}, // Inst #526 = PseudoCMPU_LE_QB + {3, OperandInfo131}, // Inst #527 = PseudoCMPU_LT_QB + {3, OperandInfo131}, // Inst #528 = PseudoCMP_EQ_PH + {3, OperandInfo131}, // Inst #529 = PseudoCMP_LE_PH + {3, OperandInfo131}, // Inst #530 = PseudoCMP_LT_PH + {2, OperandInfo132}, // Inst #531 = PseudoCVT_D32_W + {2, OperandInfo133}, // Inst #532 = PseudoCVT_D64_L + {2, OperandInfo134}, // Inst #533 = PseudoCVT_D64_W + {2, OperandInfo133}, // Inst #534 = PseudoCVT_S_L + {2, OperandInfo128}, // Inst #535 = PseudoCVT_S_W + {3, OperandInfo135}, // Inst #536 = PseudoDMULT + {3, OperandInfo135}, // Inst #537 = PseudoDMULTu + {3, OperandInfo135}, // Inst #538 = PseudoDSDIV + {3, OperandInfo135}, // Inst #539 = PseudoDUDIV + {7, OperandInfo136}, // Inst #540 = PseudoD_SELECT_I + {7, OperandInfo137}, // Inst #541 = PseudoD_SELECT_I64 + {1, OperandInfo57}, // Inst #542 = PseudoIndirectBranch + {1, OperandInfo94}, // Inst #543 = PseudoIndirectBranch64 + {1, OperandInfo94}, // Inst #544 = PseudoIndirectBranch64R6 + {1, OperandInfo57}, // Inst #545 = PseudoIndirectBranchR6 + {1, OperandInfo57}, // Inst #546 = PseudoIndirectBranch_MM + {1, OperandInfo57}, // Inst #547 = PseudoIndirectBranch_MMR6 + {1, OperandInfo57}, // Inst #548 = PseudoIndirectHazardBranch + {1, OperandInfo94}, // Inst #549 = PseudoIndirectHazardBranch64 + {1, OperandInfo94}, // Inst #550 = PseudoIndrectHazardBranch64R6 + {1, OperandInfo57}, // Inst #551 = PseudoIndrectHazardBranchR6 + {4, OperandInfo138}, // Inst #552 = PseudoMADD + {4, OperandInfo138}, // Inst #553 = PseudoMADDU + {4, OperandInfo138}, // Inst #554 = PseudoMADDU_MM + {4, OperandInfo138}, // Inst #555 = PseudoMADD_MM + {2, OperandInfo139}, // Inst #556 = PseudoMFHI + {2, OperandInfo140}, // Inst #557 = PseudoMFHI64 + {2, OperandInfo139}, // Inst #558 = PseudoMFHI_MM + {2, OperandInfo139}, // Inst #559 = PseudoMFLO + {2, OperandInfo140}, // Inst #560 = PseudoMFLO64 + {2, OperandInfo139}, // Inst #561 = PseudoMFLO_MM + {4, OperandInfo138}, // Inst #562 = PseudoMSUB + {4, OperandInfo138}, // Inst #563 = PseudoMSUBU + {4, OperandInfo138}, // Inst #564 = PseudoMSUBU_MM + {4, OperandInfo138}, // Inst #565 = PseudoMSUB_MM + {3, OperandInfo141}, // Inst #566 = PseudoMTLOHI + {3, OperandInfo135}, // Inst #567 = PseudoMTLOHI64 + {3, OperandInfo142}, // Inst #568 = PseudoMTLOHI_DSP + {3, OperandInfo141}, // Inst #569 = PseudoMTLOHI_MM + {3, OperandInfo141}, // Inst #570 = PseudoMULT + {3, OperandInfo141}, // Inst #571 = PseudoMULT_MM + {3, OperandInfo141}, // Inst #572 = PseudoMULTu + {3, OperandInfo141}, // Inst #573 = PseudoMULTu_MM + {4, OperandInfo143}, // Inst #574 = PseudoPICK_PH + {4, OperandInfo143}, // Inst #575 = PseudoPICK_QB + {1, OperandInfo57}, // Inst #576 = PseudoReturn + {1, OperandInfo94}, // Inst #577 = PseudoReturn64 + {3, OperandInfo141}, // Inst #578 = PseudoSDIV + {4, OperandInfo144}, // Inst #579 = PseudoSELECTFP_F_D32 + {4, OperandInfo145}, // Inst #580 = PseudoSELECTFP_F_D64 + {4, OperandInfo146}, // Inst #581 = PseudoSELECTFP_F_I + {4, OperandInfo147}, // Inst #582 = PseudoSELECTFP_F_I64 + {4, OperandInfo148}, // Inst #583 = PseudoSELECTFP_F_S + {4, OperandInfo144}, // Inst #584 = PseudoSELECTFP_T_D32 + {4, OperandInfo145}, // Inst #585 = PseudoSELECTFP_T_D64 + {4, OperandInfo146}, // Inst #586 = PseudoSELECTFP_T_I + {4, OperandInfo147}, // Inst #587 = PseudoSELECTFP_T_I64 + {4, OperandInfo148}, // Inst #588 = PseudoSELECTFP_T_S + {4, OperandInfo149}, // Inst #589 = PseudoSELECT_D32 + {4, OperandInfo150}, // Inst #590 = PseudoSELECT_D64 + {4, OperandInfo151}, // Inst #591 = PseudoSELECT_I + {4, OperandInfo152}, // Inst #592 = PseudoSELECT_I64 + {4, OperandInfo153}, // Inst #593 = PseudoSELECT_S + {3, OperandInfo154}, // Inst #594 = PseudoTRUNC_W_D + {3, OperandInfo155}, // Inst #595 = PseudoTRUNC_W_D32 + {3, OperandInfo156}, // Inst #596 = PseudoTRUNC_W_S + {3, OperandInfo141}, // Inst #597 = PseudoUDIV + {3, OperandInfo71}, // Inst #598 = ROL + {3, OperandInfo72}, // Inst #599 = ROLImm + {3, OperandInfo71}, // Inst #600 = ROR + {3, OperandInfo72}, // Inst #601 = RORImm + {0, NULL}, // Inst #602 = RetRA + {0, NULL}, // Inst #603 = RetRA16 + {3, OperandInfo157}, // Inst #604 = SDC1_M1 + {3, OperandInfo141}, // Inst #605 = SDIV_MM_Pseudo + {3, OperandInfo95}, // Inst #606 = SDMacro + {3, OperandInfo72}, // Inst #607 = SDivIMacro + {3, OperandInfo158}, // Inst #608 = SDivMacro + {3, OperandInfo72}, // Inst #609 = SEQIMacro + {3, OperandInfo71}, // Inst #610 = SEQMacro + {3, OperandInfo71}, // Inst #611 = SGE + {3, OperandInfo72}, // Inst #612 = SGEImm + {3, OperandInfo69}, // Inst #613 = SGEImm64 + {3, OperandInfo71}, // Inst #614 = SGEU + {3, OperandInfo72}, // Inst #615 = SGEUImm + {3, OperandInfo69}, // Inst #616 = SGEUImm64 + {3, OperandInfo72}, // Inst #617 = SGTImm + {3, OperandInfo69}, // Inst #618 = SGTImm64 + {3, OperandInfo72}, // Inst #619 = SGTUImm + {3, OperandInfo69}, // Inst #620 = SGTUImm64 + {3, OperandInfo71}, // Inst #621 = SLE + {3, OperandInfo72}, // Inst #622 = SLEImm + {3, OperandInfo69}, // Inst #623 = SLEImm64 + {3, OperandInfo71}, // Inst #624 = SLEU + {3, OperandInfo72}, // Inst #625 = SLEUImm + {3, OperandInfo69}, // Inst #626 = SLEUImm64 + {3, OperandInfo69}, // Inst #627 = SLTImm64 + {3, OperandInfo69}, // Inst #628 = SLTUImm64 + {3, OperandInfo72}, // Inst #629 = SNEIMacro + {3, OperandInfo71}, // Inst #630 = SNEMacro + {2, OperandInfo159}, // Inst #631 = SNZ_B_PSEUDO + {2, OperandInfo160}, // Inst #632 = SNZ_D_PSEUDO + {2, OperandInfo161}, // Inst #633 = SNZ_H_PSEUDO + {2, OperandInfo159}, // Inst #634 = SNZ_V_PSEUDO + {2, OperandInfo162}, // Inst #635 = SNZ_W_PSEUDO + {3, OperandInfo72}, // Inst #636 = SRemIMacro + {3, OperandInfo71}, // Inst #637 = SRemMacro + {3, OperandInfo99}, // Inst #638 = STORE_ACC128 + {3, OperandInfo100}, // Inst #639 = STORE_ACC64 + {3, OperandInfo101}, // Inst #640 = STORE_ACC64DSP + {3, OperandInfo102}, // Inst #641 = STORE_CCOND_DSP + {3, OperandInfo96}, // Inst #642 = STR_D + {3, OperandInfo97}, // Inst #643 = STR_W + {3, OperandInfo98}, // Inst #644 = ST_F16 + {3, OperandInfo109}, // Inst #645 = SWM_MM + {2, OperandInfo159}, // Inst #646 = SZ_B_PSEUDO + {2, OperandInfo160}, // Inst #647 = SZ_D_PSEUDO + {2, OperandInfo161}, // Inst #648 = SZ_H_PSEUDO + {2, OperandInfo159}, // Inst #649 = SZ_V_PSEUDO + {2, OperandInfo162}, // Inst #650 = SZ_W_PSEUDO + {3, OperandInfo112}, // Inst #651 = SaaAddr + {3, OperandInfo112}, // Inst #652 = SaadAddr + {4, OperandInfo163}, // Inst #653 = SelBeqZ + {4, OperandInfo163}, // Inst #654 = SelBneZ + {5, OperandInfo164}, // Inst #655 = SelTBteqZCmp + {5, OperandInfo165}, // Inst #656 = SelTBteqZCmpi + {5, OperandInfo164}, // Inst #657 = SelTBteqZSlt + {5, OperandInfo165}, // Inst #658 = SelTBteqZSlti + {5, OperandInfo165}, // Inst #659 = SelTBteqZSltiu + {5, OperandInfo164}, // Inst #660 = SelTBteqZSltu + {5, OperandInfo164}, // Inst #661 = SelTBtneZCmp + {5, OperandInfo165}, // Inst #662 = SelTBtneZCmpi + {5, OperandInfo164}, // Inst #663 = SelTBtneZSlt + {5, OperandInfo165}, // Inst #664 = SelTBtneZSlti + {5, OperandInfo165}, // Inst #665 = SelTBtneZSltiu + {5, OperandInfo164}, // Inst #666 = SelTBtneZSltu + {3, OperandInfo130}, // Inst #667 = SltCCRxRy16 + {3, OperandInfo166}, // Inst #668 = SltiCCRxImmX16 + {3, OperandInfo166}, // Inst #669 = SltiuCCRxImmX16 + {3, OperandInfo130}, // Inst #670 = SltuCCRxRy16 + {3, OperandInfo130}, // Inst #671 = SltuRxRyRz16 + {1, OperandInfo2}, // Inst #672 = TAILCALL + {1, OperandInfo94}, // Inst #673 = TAILCALL64R6REG + {1, OperandInfo94}, // Inst #674 = TAILCALLHB64R6REG + {1, OperandInfo57}, // Inst #675 = TAILCALLHBR6REG + {1, OperandInfo57}, // Inst #676 = TAILCALLR6REG + {1, OperandInfo57}, // Inst #677 = TAILCALLREG + {1, OperandInfo94}, // Inst #678 = TAILCALLREG64 + {1, OperandInfo57}, // Inst #679 = TAILCALLREGHB + {1, OperandInfo94}, // Inst #680 = TAILCALLREGHB64 + {1, OperandInfo57}, // Inst #681 = TAILCALLREG_MM + {1, OperandInfo57}, // Inst #682 = TAILCALLREG_MMR6 + {1, OperandInfo2}, // Inst #683 = TAILCALL_MM + {1, OperandInfo2}, // Inst #684 = TAILCALL_MMR6 + {0, NULL}, // Inst #685 = TRAP + {0, NULL}, // Inst #686 = TRAP_MM + {3, OperandInfo141}, // Inst #687 = UDIV_MM_Pseudo + {3, OperandInfo72}, // Inst #688 = UDivIMacro + {3, OperandInfo71}, // Inst #689 = UDivMacro + {3, OperandInfo72}, // Inst #690 = URemIMacro + {3, OperandInfo71}, // Inst #691 = URemMacro + {3, OperandInfo95}, // Inst #692 = Ulh + {3, OperandInfo95}, // Inst #693 = Ulhu + {3, OperandInfo95}, // Inst #694 = Ulw + {3, OperandInfo95}, // Inst #695 = Ush + {3, OperandInfo95}, // Inst #696 = Usw + {3, OperandInfo45}, // Inst #697 = XOR_V_D_PSEUDO + {3, OperandInfo46}, // Inst #698 = XOR_V_H_PSEUDO + {3, OperandInfo47}, // Inst #699 = XOR_V_W_PSEUDO + {2, OperandInfo167}, // Inst #700 = ABSQ_S_PH + {2, OperandInfo167}, // Inst #701 = ABSQ_S_PH_MM + {2, OperandInfo167}, // Inst #702 = ABSQ_S_QB + {2, OperandInfo167}, // Inst #703 = ABSQ_S_QB_MMR2 + {2, OperandInfo44}, // Inst #704 = ABSQ_S_W + {2, OperandInfo44}, // Inst #705 = ABSQ_S_W_MM + {3, OperandInfo71}, // Inst #706 = ADD + {2, OperandInfo113}, // Inst #707 = ADDIUPC + {2, OperandInfo168}, // Inst #708 = ADDIUPC_MM + {2, OperandInfo113}, // Inst #709 = ADDIUPC_MMR6 + {2, OperandInfo168}, // Inst #710 = ADDIUR1SP_MM + {3, OperandInfo169}, // Inst #711 = ADDIUR2_MM + {3, OperandInfo170}, // Inst #712 = ADDIUS5_MM + {1, OperandInfo2}, // Inst #713 = ADDIUSP_MM + {3, OperandInfo72}, // Inst #714 = ADDIU_MMR6 + {3, OperandInfo171}, // Inst #715 = ADDQH_PH + {3, OperandInfo171}, // Inst #716 = ADDQH_PH_MMR2 + {3, OperandInfo171}, // Inst #717 = ADDQH_R_PH + {3, OperandInfo171}, // Inst #718 = ADDQH_R_PH_MMR2 + {3, OperandInfo71}, // Inst #719 = ADDQH_R_W + {3, OperandInfo71}, // Inst #720 = ADDQH_R_W_MMR2 + {3, OperandInfo71}, // Inst #721 = ADDQH_W + {3, OperandInfo71}, // Inst #722 = ADDQH_W_MMR2 + {3, OperandInfo171}, // Inst #723 = ADDQ_PH + {3, OperandInfo171}, // Inst #724 = ADDQ_PH_MM + {3, OperandInfo171}, // Inst #725 = ADDQ_S_PH + {3, OperandInfo171}, // Inst #726 = ADDQ_S_PH_MM + {3, OperandInfo71}, // Inst #727 = ADDQ_S_W + {3, OperandInfo71}, // Inst #728 = ADDQ_S_W_MM + {3, OperandInfo172}, // Inst #729 = ADDR_PS64 + {3, OperandInfo71}, // Inst #730 = ADDSC + {3, OperandInfo71}, // Inst #731 = ADDSC_MM + {3, OperandInfo173}, // Inst #732 = ADDS_A_B + {3, OperandInfo45}, // Inst #733 = ADDS_A_D + {3, OperandInfo46}, // Inst #734 = ADDS_A_H + {3, OperandInfo47}, // Inst #735 = ADDS_A_W + {3, OperandInfo173}, // Inst #736 = ADDS_S_B + {3, OperandInfo45}, // Inst #737 = ADDS_S_D + {3, OperandInfo46}, // Inst #738 = ADDS_S_H + {3, OperandInfo47}, // Inst #739 = ADDS_S_W + {3, OperandInfo173}, // Inst #740 = ADDS_U_B + {3, OperandInfo45}, // Inst #741 = ADDS_U_D + {3, OperandInfo46}, // Inst #742 = ADDS_U_H + {3, OperandInfo47}, // Inst #743 = ADDS_U_W + {3, OperandInfo174}, // Inst #744 = ADDU16_MM + {3, OperandInfo174}, // Inst #745 = ADDU16_MMR6 + {3, OperandInfo171}, // Inst #746 = ADDUH_QB + {3, OperandInfo171}, // Inst #747 = ADDUH_QB_MMR2 + {3, OperandInfo171}, // Inst #748 = ADDUH_R_QB + {3, OperandInfo171}, // Inst #749 = ADDUH_R_QB_MMR2 + {3, OperandInfo71}, // Inst #750 = ADDU_MMR6 + {3, OperandInfo171}, // Inst #751 = ADDU_PH + {3, OperandInfo171}, // Inst #752 = ADDU_PH_MMR2 + {3, OperandInfo171}, // Inst #753 = ADDU_QB + {3, OperandInfo171}, // Inst #754 = ADDU_QB_MM + {3, OperandInfo171}, // Inst #755 = ADDU_S_PH + {3, OperandInfo171}, // Inst #756 = ADDU_S_PH_MMR2 + {3, OperandInfo171}, // Inst #757 = ADDU_S_QB + {3, OperandInfo171}, // Inst #758 = ADDU_S_QB_MM + {3, OperandInfo175}, // Inst #759 = ADDVI_B + {3, OperandInfo176}, // Inst #760 = ADDVI_D + {3, OperandInfo177}, // Inst #761 = ADDVI_H + {3, OperandInfo178}, // Inst #762 = ADDVI_W + {3, OperandInfo173}, // Inst #763 = ADDV_B + {3, OperandInfo45}, // Inst #764 = ADDV_D + {3, OperandInfo46}, // Inst #765 = ADDV_H + {3, OperandInfo47}, // Inst #766 = ADDV_W + {3, OperandInfo71}, // Inst #767 = ADDWC + {3, OperandInfo71}, // Inst #768 = ADDWC_MM + {3, OperandInfo173}, // Inst #769 = ADD_A_B + {3, OperandInfo45}, // Inst #770 = ADD_A_D + {3, OperandInfo46}, // Inst #771 = ADD_A_H + {3, OperandInfo47}, // Inst #772 = ADD_A_W + {3, OperandInfo71}, // Inst #773 = ADD_MM + {3, OperandInfo71}, // Inst #774 = ADD_MMR6 + {3, OperandInfo72}, // Inst #775 = ADDi + {3, OperandInfo72}, // Inst #776 = ADDi_MM + {3, OperandInfo72}, // Inst #777 = ADDiu + {3, OperandInfo72}, // Inst #778 = ADDiu_MM + {3, OperandInfo71}, // Inst #779 = ADDu + {3, OperandInfo71}, // Inst #780 = ADDu_MM + {4, OperandInfo179}, // Inst #781 = ALIGN + {4, OperandInfo179}, // Inst #782 = ALIGN_MMR6 + {2, OperandInfo113}, // Inst #783 = ALUIPC + {2, OperandInfo113}, // Inst #784 = ALUIPC_MMR6 + {3, OperandInfo71}, // Inst #785 = AND + {3, OperandInfo180}, // Inst #786 = AND16_MM + {3, OperandInfo180}, // Inst #787 = AND16_MMR6 + {3, OperandInfo70}, // Inst #788 = AND64 + {3, OperandInfo169}, // Inst #789 = ANDI16_MM + {3, OperandInfo169}, // Inst #790 = ANDI16_MMR6 + {3, OperandInfo175}, // Inst #791 = ANDI_B + {3, OperandInfo72}, // Inst #792 = ANDI_MMR6 + {3, OperandInfo71}, // Inst #793 = AND_MM + {3, OperandInfo71}, // Inst #794 = AND_MMR6 + {3, OperandInfo173}, // Inst #795 = AND_V + {3, OperandInfo72}, // Inst #796 = ANDi + {3, OperandInfo69}, // Inst #797 = ANDi64 + {3, OperandInfo72}, // Inst #798 = ANDi_MM + {4, OperandInfo181}, // Inst #799 = APPEND + {4, OperandInfo181}, // Inst #800 = APPEND_MMR2 + {3, OperandInfo173}, // Inst #801 = ASUB_S_B + {3, OperandInfo45}, // Inst #802 = ASUB_S_D + {3, OperandInfo46}, // Inst #803 = ASUB_S_H + {3, OperandInfo47}, // Inst #804 = ASUB_S_W + {3, OperandInfo173}, // Inst #805 = ASUB_U_B + {3, OperandInfo45}, // Inst #806 = ASUB_U_D + {3, OperandInfo46}, // Inst #807 = ASUB_U_H + {3, OperandInfo47}, // Inst #808 = ASUB_U_W + {3, OperandInfo72}, // Inst #809 = AUI + {2, OperandInfo113}, // Inst #810 = AUIPC + {2, OperandInfo113}, // Inst #811 = AUIPC_MMR6 + {3, OperandInfo72}, // Inst #812 = AUI_MMR6 + {3, OperandInfo173}, // Inst #813 = AVER_S_B + {3, OperandInfo45}, // Inst #814 = AVER_S_D + {3, OperandInfo46}, // Inst #815 = AVER_S_H + {3, OperandInfo47}, // Inst #816 = AVER_S_W + {3, OperandInfo173}, // Inst #817 = AVER_U_B + {3, OperandInfo45}, // Inst #818 = AVER_U_D + {3, OperandInfo46}, // Inst #819 = AVER_U_H + {3, OperandInfo47}, // Inst #820 = AVER_U_W + {3, OperandInfo173}, // Inst #821 = AVE_S_B + {3, OperandInfo45}, // Inst #822 = AVE_S_D + {3, OperandInfo46}, // Inst #823 = AVE_S_H + {3, OperandInfo47}, // Inst #824 = AVE_S_W + {3, OperandInfo173}, // Inst #825 = AVE_U_B + {3, OperandInfo45}, // Inst #826 = AVE_U_D + {3, OperandInfo46}, // Inst #827 = AVE_U_H + {3, OperandInfo47}, // Inst #828 = AVE_U_W + {2, OperandInfo182}, // Inst #829 = AddiuRxImmX16 + {2, OperandInfo182}, // Inst #830 = AddiuRxPcImmX16 + {3, OperandInfo183}, // Inst #831 = AddiuRxRxImm16 + {3, OperandInfo183}, // Inst #832 = AddiuRxRxImmX16 + {3, OperandInfo184}, // Inst #833 = AddiuRxRyOffMemX16 + {1, OperandInfo2}, // Inst #834 = AddiuSpImm16 + {1, OperandInfo2}, // Inst #835 = AddiuSpImmX16 + {3, OperandInfo130}, // Inst #836 = AdduRxRyRz16 + {3, OperandInfo185}, // Inst #837 = AndRxRxRy16 + {1, OperandInfo54}, // Inst #838 = B16_MM + {3, OperandInfo70}, // Inst #839 = BADDu + {1, OperandInfo54}, // Inst #840 = BAL + {1, OperandInfo54}, // Inst #841 = BALC + {1, OperandInfo54}, // Inst #842 = BALC_MMR6 + {4, OperandInfo181}, // Inst #843 = BALIGN + {4, OperandInfo181}, // Inst #844 = BALIGN_MMR2 + {3, OperandInfo186}, // Inst #845 = BBIT0 + {3, OperandInfo186}, // Inst #846 = BBIT032 + {3, OperandInfo186}, // Inst #847 = BBIT1 + {3, OperandInfo186}, // Inst #848 = BBIT132 + {1, OperandInfo54}, // Inst #849 = BC + {1, OperandInfo54}, // Inst #850 = BC0F + {1, OperandInfo54}, // Inst #851 = BC0T + {1, OperandInfo54}, // Inst #852 = BC16_MMR6 + {2, OperandInfo187}, // Inst #853 = BC1EQZ + {2, OperandInfo187}, // Inst #854 = BC1EQZC_MMR6 + {2, OperandInfo188}, // Inst #855 = BC1F + {2, OperandInfo188}, // Inst #856 = BC1FL + {2, OperandInfo188}, // Inst #857 = BC1F_MM + {2, OperandInfo187}, // Inst #858 = BC1NEZ + {2, OperandInfo187}, // Inst #859 = BC1NEZC_MMR6 + {2, OperandInfo188}, // Inst #860 = BC1T + {2, OperandInfo188}, // Inst #861 = BC1TL + {2, OperandInfo188}, // Inst #862 = BC1T_MM + {2, OperandInfo189}, // Inst #863 = BC2EQZ + {2, OperandInfo189}, // Inst #864 = BC2EQZC_MMR6 + {2, OperandInfo188}, // Inst #865 = BC2F + {2, OperandInfo188}, // Inst #866 = BC2FL + {2, OperandInfo189}, // Inst #867 = BC2NEZ + {2, OperandInfo189}, // Inst #868 = BC2NEZC_MMR6 + {2, OperandInfo188}, // Inst #869 = BC2T + {2, OperandInfo188}, // Inst #870 = BC2TL + {2, OperandInfo188}, // Inst #871 = BC3F + {2, OperandInfo188}, // Inst #872 = BC3FL + {2, OperandInfo188}, // Inst #873 = BC3T + {2, OperandInfo188}, // Inst #874 = BC3TL + {3, OperandInfo175}, // Inst #875 = BCLRI_B + {3, OperandInfo176}, // Inst #876 = BCLRI_D + {3, OperandInfo177}, // Inst #877 = BCLRI_H + {3, OperandInfo178}, // Inst #878 = BCLRI_W + {3, OperandInfo173}, // Inst #879 = BCLR_B + {3, OperandInfo45}, // Inst #880 = BCLR_D + {3, OperandInfo46}, // Inst #881 = BCLR_H + {3, OperandInfo47}, // Inst #882 = BCLR_W + {1, OperandInfo54}, // Inst #883 = BC_MMR6 + {3, OperandInfo56}, // Inst #884 = BEQ + {3, OperandInfo105}, // Inst #885 = BEQ64 + {3, OperandInfo56}, // Inst #886 = BEQC + {3, OperandInfo105}, // Inst #887 = BEQC64 + {3, OperandInfo56}, // Inst #888 = BEQC_MMR6 + {3, OperandInfo56}, // Inst #889 = BEQL + {2, OperandInfo190}, // Inst #890 = BEQZ16_MM + {2, OperandInfo107}, // Inst #891 = BEQZALC + {2, OperandInfo107}, // Inst #892 = BEQZALC_MMR6 + {2, OperandInfo107}, // Inst #893 = BEQZC + {2, OperandInfo190}, // Inst #894 = BEQZC16_MMR6 + {2, OperandInfo108}, // Inst #895 = BEQZC64 + {2, OperandInfo107}, // Inst #896 = BEQZC_MM + {2, OperandInfo107}, // Inst #897 = BEQZC_MMR6 + {3, OperandInfo56}, // Inst #898 = BEQ_MM + {3, OperandInfo56}, // Inst #899 = BGEC + {3, OperandInfo105}, // Inst #900 = BGEC64 + {3, OperandInfo56}, // Inst #901 = BGEC_MMR6 + {3, OperandInfo56}, // Inst #902 = BGEUC + {3, OperandInfo105}, // Inst #903 = BGEUC64 + {3, OperandInfo56}, // Inst #904 = BGEUC_MMR6 + {2, OperandInfo107}, // Inst #905 = BGEZ + {2, OperandInfo108}, // Inst #906 = BGEZ64 + {2, OperandInfo107}, // Inst #907 = BGEZAL + {2, OperandInfo107}, // Inst #908 = BGEZALC + {2, OperandInfo107}, // Inst #909 = BGEZALC_MMR6 + {2, OperandInfo107}, // Inst #910 = BGEZALL + {2, OperandInfo107}, // Inst #911 = BGEZALS_MM + {2, OperandInfo107}, // Inst #912 = BGEZAL_MM + {2, OperandInfo107}, // Inst #913 = BGEZC + {2, OperandInfo108}, // Inst #914 = BGEZC64 + {2, OperandInfo107}, // Inst #915 = BGEZC_MMR6 + {2, OperandInfo107}, // Inst #916 = BGEZL + {2, OperandInfo107}, // Inst #917 = BGEZ_MM + {2, OperandInfo107}, // Inst #918 = BGTZ + {2, OperandInfo108}, // Inst #919 = BGTZ64 + {2, OperandInfo107}, // Inst #920 = BGTZALC + {2, OperandInfo107}, // Inst #921 = BGTZALC_MMR6 + {2, OperandInfo107}, // Inst #922 = BGTZC + {2, OperandInfo108}, // Inst #923 = BGTZC64 + {2, OperandInfo107}, // Inst #924 = BGTZC_MMR6 + {2, OperandInfo107}, // Inst #925 = BGTZL + {2, OperandInfo107}, // Inst #926 = BGTZ_MM + {4, OperandInfo191}, // Inst #927 = BINSLI_B + {4, OperandInfo192}, // Inst #928 = BINSLI_D + {4, OperandInfo193}, // Inst #929 = BINSLI_H + {4, OperandInfo194}, // Inst #930 = BINSLI_W + {4, OperandInfo195}, // Inst #931 = BINSL_B + {4, OperandInfo58}, // Inst #932 = BINSL_D + {4, OperandInfo60}, // Inst #933 = BINSL_H + {4, OperandInfo59}, // Inst #934 = BINSL_W + {4, OperandInfo191}, // Inst #935 = BINSRI_B + {4, OperandInfo192}, // Inst #936 = BINSRI_D + {4, OperandInfo193}, // Inst #937 = BINSRI_H + {4, OperandInfo194}, // Inst #938 = BINSRI_W + {4, OperandInfo195}, // Inst #939 = BINSR_B + {4, OperandInfo58}, // Inst #940 = BINSR_D + {4, OperandInfo60}, // Inst #941 = BINSR_H + {4, OperandInfo59}, // Inst #942 = BINSR_W + {2, OperandInfo44}, // Inst #943 = BITREV + {2, OperandInfo44}, // Inst #944 = BITREV_MM + {2, OperandInfo44}, // Inst #945 = BITSWAP + {2, OperandInfo44}, // Inst #946 = BITSWAP_MMR6 + {2, OperandInfo107}, // Inst #947 = BLEZ + {2, OperandInfo108}, // Inst #948 = BLEZ64 + {2, OperandInfo107}, // Inst #949 = BLEZALC + {2, OperandInfo107}, // Inst #950 = BLEZALC_MMR6 + {2, OperandInfo107}, // Inst #951 = BLEZC + {2, OperandInfo108}, // Inst #952 = BLEZC64 + {2, OperandInfo107}, // Inst #953 = BLEZC_MMR6 + {2, OperandInfo107}, // Inst #954 = BLEZL + {2, OperandInfo107}, // Inst #955 = BLEZ_MM + {3, OperandInfo56}, // Inst #956 = BLTC + {3, OperandInfo105}, // Inst #957 = BLTC64 + {3, OperandInfo56}, // Inst #958 = BLTC_MMR6 + {3, OperandInfo56}, // Inst #959 = BLTUC + {3, OperandInfo105}, // Inst #960 = BLTUC64 + {3, OperandInfo56}, // Inst #961 = BLTUC_MMR6 + {2, OperandInfo107}, // Inst #962 = BLTZ + {2, OperandInfo108}, // Inst #963 = BLTZ64 + {2, OperandInfo107}, // Inst #964 = BLTZAL + {2, OperandInfo107}, // Inst #965 = BLTZALC + {2, OperandInfo107}, // Inst #966 = BLTZALC_MMR6 + {2, OperandInfo107}, // Inst #967 = BLTZALL + {2, OperandInfo107}, // Inst #968 = BLTZALS_MM + {2, OperandInfo107}, // Inst #969 = BLTZAL_MM + {2, OperandInfo107}, // Inst #970 = BLTZC + {2, OperandInfo108}, // Inst #971 = BLTZC64 + {2, OperandInfo107}, // Inst #972 = BLTZC_MMR6 + {2, OperandInfo107}, // Inst #973 = BLTZL + {2, OperandInfo107}, // Inst #974 = BLTZ_MM + {4, OperandInfo191}, // Inst #975 = BMNZI_B + {4, OperandInfo195}, // Inst #976 = BMNZ_V + {4, OperandInfo191}, // Inst #977 = BMZI_B + {4, OperandInfo195}, // Inst #978 = BMZ_V + {3, OperandInfo56}, // Inst #979 = BNE + {3, OperandInfo105}, // Inst #980 = BNE64 + {3, OperandInfo56}, // Inst #981 = BNEC + {3, OperandInfo105}, // Inst #982 = BNEC64 + {3, OperandInfo56}, // Inst #983 = BNEC_MMR6 + {3, OperandInfo175}, // Inst #984 = BNEGI_B + {3, OperandInfo176}, // Inst #985 = BNEGI_D + {3, OperandInfo177}, // Inst #986 = BNEGI_H + {3, OperandInfo178}, // Inst #987 = BNEGI_W + {3, OperandInfo173}, // Inst #988 = BNEG_B + {3, OperandInfo45}, // Inst #989 = BNEG_D + {3, OperandInfo46}, // Inst #990 = BNEG_H + {3, OperandInfo47}, // Inst #991 = BNEG_W + {3, OperandInfo56}, // Inst #992 = BNEL + {2, OperandInfo190}, // Inst #993 = BNEZ16_MM + {2, OperandInfo107}, // Inst #994 = BNEZALC + {2, OperandInfo107}, // Inst #995 = BNEZALC_MMR6 + {2, OperandInfo107}, // Inst #996 = BNEZC + {2, OperandInfo190}, // Inst #997 = BNEZC16_MMR6 + {2, OperandInfo108}, // Inst #998 = BNEZC64 + {2, OperandInfo107}, // Inst #999 = BNEZC_MM + {2, OperandInfo107}, // Inst #1000 = BNEZC_MMR6 + {3, OperandInfo56}, // Inst #1001 = BNE_MM + {3, OperandInfo56}, // Inst #1002 = BNVC + {3, OperandInfo56}, // Inst #1003 = BNVC_MMR6 + {2, OperandInfo196}, // Inst #1004 = BNZ_B + {2, OperandInfo197}, // Inst #1005 = BNZ_D + {2, OperandInfo198}, // Inst #1006 = BNZ_H + {2, OperandInfo196}, // Inst #1007 = BNZ_V + {2, OperandInfo199}, // Inst #1008 = BNZ_W + {3, OperandInfo56}, // Inst #1009 = BOVC + {3, OperandInfo56}, // Inst #1010 = BOVC_MMR6 + {1, OperandInfo54}, // Inst #1011 = BPOSGE32 + {1, OperandInfo54}, // Inst #1012 = BPOSGE32C_MMR3 + {1, OperandInfo54}, // Inst #1013 = BPOSGE32_MM + {2, OperandInfo7}, // Inst #1014 = BREAK + {1, OperandInfo2}, // Inst #1015 = BREAK16_MM + {1, OperandInfo2}, // Inst #1016 = BREAK16_MMR6 + {2, OperandInfo7}, // Inst #1017 = BREAK_MM + {2, OperandInfo7}, // Inst #1018 = BREAK_MMR6 + {4, OperandInfo191}, // Inst #1019 = BSELI_B + {4, OperandInfo195}, // Inst #1020 = BSEL_V + {3, OperandInfo175}, // Inst #1021 = BSETI_B + {3, OperandInfo176}, // Inst #1022 = BSETI_D + {3, OperandInfo177}, // Inst #1023 = BSETI_H + {3, OperandInfo178}, // Inst #1024 = BSETI_W + {3, OperandInfo173}, // Inst #1025 = BSET_B + {3, OperandInfo45}, // Inst #1026 = BSET_D + {3, OperandInfo46}, // Inst #1027 = BSET_H + {3, OperandInfo47}, // Inst #1028 = BSET_W + {2, OperandInfo196}, // Inst #1029 = BZ_B + {2, OperandInfo197}, // Inst #1030 = BZ_D + {2, OperandInfo198}, // Inst #1031 = BZ_H + {2, OperandInfo196}, // Inst #1032 = BZ_V + {2, OperandInfo199}, // Inst #1033 = BZ_W + {2, OperandInfo200}, // Inst #1034 = BeqzRxImm16 + {2, OperandInfo200}, // Inst #1035 = BeqzRxImmX16 + {1, OperandInfo54}, // Inst #1036 = Bimm16 + {1, OperandInfo54}, // Inst #1037 = BimmX16 + {2, OperandInfo200}, // Inst #1038 = BnezRxImm16 + {2, OperandInfo200}, // Inst #1039 = BnezRxImmX16 + {0, NULL}, // Inst #1040 = Break16 + {1, OperandInfo2}, // Inst #1041 = Bteqz16 + {1, OperandInfo2}, // Inst #1042 = BteqzX16 + {1, OperandInfo2}, // Inst #1043 = Btnez16 + {1, OperandInfo2}, // Inst #1044 = BtnezX16 + {3, OperandInfo201}, // Inst #1045 = CACHE + {3, OperandInfo201}, // Inst #1046 = CACHEE + {3, OperandInfo201}, // Inst #1047 = CACHEE_MM + {3, OperandInfo201}, // Inst #1048 = CACHE_MM + {3, OperandInfo201}, // Inst #1049 = CACHE_MMR6 + {3, OperandInfo201}, // Inst #1050 = CACHE_R6 + {2, OperandInfo202}, // Inst #1051 = CEIL_L_D64 + {2, OperandInfo202}, // Inst #1052 = CEIL_L_D_MMR6 + {2, OperandInfo203}, // Inst #1053 = CEIL_L_S + {2, OperandInfo203}, // Inst #1054 = CEIL_L_S_MMR6 + {2, OperandInfo204}, // Inst #1055 = CEIL_W_D32 + {2, OperandInfo205}, // Inst #1056 = CEIL_W_D64 + {2, OperandInfo204}, // Inst #1057 = CEIL_W_D_MMR6 + {2, OperandInfo204}, // Inst #1058 = CEIL_W_MM + {2, OperandInfo206}, // Inst #1059 = CEIL_W_S + {2, OperandInfo206}, // Inst #1060 = CEIL_W_S_MM + {2, OperandInfo206}, // Inst #1061 = CEIL_W_S_MMR6 + {3, OperandInfo175}, // Inst #1062 = CEQI_B + {3, OperandInfo176}, // Inst #1063 = CEQI_D + {3, OperandInfo177}, // Inst #1064 = CEQI_H + {3, OperandInfo178}, // Inst #1065 = CEQI_W + {3, OperandInfo173}, // Inst #1066 = CEQ_B + {3, OperandInfo45}, // Inst #1067 = CEQ_D + {3, OperandInfo46}, // Inst #1068 = CEQ_H + {3, OperandInfo47}, // Inst #1069 = CEQ_W + {2, OperandInfo207}, // Inst #1070 = CFC1 + {2, OperandInfo207}, // Inst #1071 = CFC1_MM + {2, OperandInfo208}, // Inst #1072 = CFC2_MM + {2, OperandInfo209}, // Inst #1073 = CFCMSA + {4, OperandInfo210}, // Inst #1074 = CINS + {4, OperandInfo210}, // Inst #1075 = CINS32 + {4, OperandInfo211}, // Inst #1076 = CINS64_32 + {4, OperandInfo212}, // Inst #1077 = CINS_i32 + {2, OperandInfo202}, // Inst #1078 = CLASS_D + {2, OperandInfo202}, // Inst #1079 = CLASS_D_MMR6 + {2, OperandInfo206}, // Inst #1080 = CLASS_S + {2, OperandInfo206}, // Inst #1081 = CLASS_S_MMR6 + {3, OperandInfo175}, // Inst #1082 = CLEI_S_B + {3, OperandInfo176}, // Inst #1083 = CLEI_S_D + {3, OperandInfo177}, // Inst #1084 = CLEI_S_H + {3, OperandInfo178}, // Inst #1085 = CLEI_S_W + {3, OperandInfo175}, // Inst #1086 = CLEI_U_B + {3, OperandInfo176}, // Inst #1087 = CLEI_U_D + {3, OperandInfo177}, // Inst #1088 = CLEI_U_H + {3, OperandInfo178}, // Inst #1089 = CLEI_U_W + {3, OperandInfo173}, // Inst #1090 = CLE_S_B + {3, OperandInfo45}, // Inst #1091 = CLE_S_D + {3, OperandInfo46}, // Inst #1092 = CLE_S_H + {3, OperandInfo47}, // Inst #1093 = CLE_S_W + {3, OperandInfo173}, // Inst #1094 = CLE_U_B + {3, OperandInfo45}, // Inst #1095 = CLE_U_D + {3, OperandInfo46}, // Inst #1096 = CLE_U_H + {3, OperandInfo47}, // Inst #1097 = CLE_U_W + {2, OperandInfo44}, // Inst #1098 = CLO + {2, OperandInfo44}, // Inst #1099 = CLO_MM + {2, OperandInfo44}, // Inst #1100 = CLO_MMR6 + {2, OperandInfo44}, // Inst #1101 = CLO_R6 + {3, OperandInfo175}, // Inst #1102 = CLTI_S_B + {3, OperandInfo176}, // Inst #1103 = CLTI_S_D + {3, OperandInfo177}, // Inst #1104 = CLTI_S_H + {3, OperandInfo178}, // Inst #1105 = CLTI_S_W + {3, OperandInfo175}, // Inst #1106 = CLTI_U_B + {3, OperandInfo176}, // Inst #1107 = CLTI_U_D + {3, OperandInfo177}, // Inst #1108 = CLTI_U_H + {3, OperandInfo178}, // Inst #1109 = CLTI_U_W + {3, OperandInfo173}, // Inst #1110 = CLT_S_B + {3, OperandInfo45}, // Inst #1111 = CLT_S_D + {3, OperandInfo46}, // Inst #1112 = CLT_S_H + {3, OperandInfo47}, // Inst #1113 = CLT_S_W + {3, OperandInfo173}, // Inst #1114 = CLT_U_B + {3, OperandInfo45}, // Inst #1115 = CLT_U_D + {3, OperandInfo46}, // Inst #1116 = CLT_U_H + {3, OperandInfo47}, // Inst #1117 = CLT_U_W + {2, OperandInfo44}, // Inst #1118 = CLZ + {2, OperandInfo44}, // Inst #1119 = CLZ_MM + {2, OperandInfo44}, // Inst #1120 = CLZ_MMR6 + {2, OperandInfo44}, // Inst #1121 = CLZ_R6 + {3, OperandInfo213}, // Inst #1122 = CMPGDU_EQ_QB + {3, OperandInfo213}, // Inst #1123 = CMPGDU_EQ_QB_MMR2 + {3, OperandInfo213}, // Inst #1124 = CMPGDU_LE_QB + {3, OperandInfo213}, // Inst #1125 = CMPGDU_LE_QB_MMR2 + {3, OperandInfo213}, // Inst #1126 = CMPGDU_LT_QB + {3, OperandInfo213}, // Inst #1127 = CMPGDU_LT_QB_MMR2 + {3, OperandInfo213}, // Inst #1128 = CMPGU_EQ_QB + {3, OperandInfo213}, // Inst #1129 = CMPGU_EQ_QB_MM + {3, OperandInfo213}, // Inst #1130 = CMPGU_LE_QB + {3, OperandInfo213}, // Inst #1131 = CMPGU_LE_QB_MM + {3, OperandInfo213}, // Inst #1132 = CMPGU_LT_QB + {3, OperandInfo213}, // Inst #1133 = CMPGU_LT_QB_MM + {2, OperandInfo167}, // Inst #1134 = CMPU_EQ_QB + {2, OperandInfo167}, // Inst #1135 = CMPU_EQ_QB_MM + {2, OperandInfo167}, // Inst #1136 = CMPU_LE_QB + {2, OperandInfo167}, // Inst #1137 = CMPU_LE_QB_MM + {2, OperandInfo167}, // Inst #1138 = CMPU_LT_QB + {2, OperandInfo167}, // Inst #1139 = CMPU_LT_QB_MM + {3, OperandInfo214}, // Inst #1140 = CMP_AF_D_MMR6 + {3, OperandInfo215}, // Inst #1141 = CMP_AF_S_MMR6 + {3, OperandInfo214}, // Inst #1142 = CMP_EQ_D + {3, OperandInfo214}, // Inst #1143 = CMP_EQ_D_MMR6 + {2, OperandInfo167}, // Inst #1144 = CMP_EQ_PH + {2, OperandInfo167}, // Inst #1145 = CMP_EQ_PH_MM + {3, OperandInfo215}, // Inst #1146 = CMP_EQ_S + {3, OperandInfo215}, // Inst #1147 = CMP_EQ_S_MMR6 + {3, OperandInfo214}, // Inst #1148 = CMP_F_D + {3, OperandInfo215}, // Inst #1149 = CMP_F_S + {3, OperandInfo214}, // Inst #1150 = CMP_LE_D + {3, OperandInfo214}, // Inst #1151 = CMP_LE_D_MMR6 + {2, OperandInfo167}, // Inst #1152 = CMP_LE_PH + {2, OperandInfo167}, // Inst #1153 = CMP_LE_PH_MM + {3, OperandInfo215}, // Inst #1154 = CMP_LE_S + {3, OperandInfo215}, // Inst #1155 = CMP_LE_S_MMR6 + {3, OperandInfo214}, // Inst #1156 = CMP_LT_D + {3, OperandInfo214}, // Inst #1157 = CMP_LT_D_MMR6 + {2, OperandInfo167}, // Inst #1158 = CMP_LT_PH + {2, OperandInfo167}, // Inst #1159 = CMP_LT_PH_MM + {3, OperandInfo215}, // Inst #1160 = CMP_LT_S + {3, OperandInfo215}, // Inst #1161 = CMP_LT_S_MMR6 + {3, OperandInfo214}, // Inst #1162 = CMP_SAF_D + {3, OperandInfo214}, // Inst #1163 = CMP_SAF_D_MMR6 + {3, OperandInfo215}, // Inst #1164 = CMP_SAF_S + {3, OperandInfo215}, // Inst #1165 = CMP_SAF_S_MMR6 + {3, OperandInfo214}, // Inst #1166 = CMP_SEQ_D + {3, OperandInfo214}, // Inst #1167 = CMP_SEQ_D_MMR6 + {3, OperandInfo215}, // Inst #1168 = CMP_SEQ_S + {3, OperandInfo215}, // Inst #1169 = CMP_SEQ_S_MMR6 + {3, OperandInfo214}, // Inst #1170 = CMP_SLE_D + {3, OperandInfo214}, // Inst #1171 = CMP_SLE_D_MMR6 + {3, OperandInfo215}, // Inst #1172 = CMP_SLE_S + {3, OperandInfo215}, // Inst #1173 = CMP_SLE_S_MMR6 + {3, OperandInfo214}, // Inst #1174 = CMP_SLT_D + {3, OperandInfo214}, // Inst #1175 = CMP_SLT_D_MMR6 + {3, OperandInfo215}, // Inst #1176 = CMP_SLT_S + {3, OperandInfo215}, // Inst #1177 = CMP_SLT_S_MMR6 + {3, OperandInfo214}, // Inst #1178 = CMP_SUEQ_D + {3, OperandInfo214}, // Inst #1179 = CMP_SUEQ_D_MMR6 + {3, OperandInfo215}, // Inst #1180 = CMP_SUEQ_S + {3, OperandInfo215}, // Inst #1181 = CMP_SUEQ_S_MMR6 + {3, OperandInfo214}, // Inst #1182 = CMP_SULE_D + {3, OperandInfo214}, // Inst #1183 = CMP_SULE_D_MMR6 + {3, OperandInfo215}, // Inst #1184 = CMP_SULE_S + {3, OperandInfo215}, // Inst #1185 = CMP_SULE_S_MMR6 + {3, OperandInfo214}, // Inst #1186 = CMP_SULT_D + {3, OperandInfo214}, // Inst #1187 = CMP_SULT_D_MMR6 + {3, OperandInfo215}, // Inst #1188 = CMP_SULT_S + {3, OperandInfo215}, // Inst #1189 = CMP_SULT_S_MMR6 + {3, OperandInfo214}, // Inst #1190 = CMP_SUN_D + {3, OperandInfo214}, // Inst #1191 = CMP_SUN_D_MMR6 + {3, OperandInfo215}, // Inst #1192 = CMP_SUN_S + {3, OperandInfo215}, // Inst #1193 = CMP_SUN_S_MMR6 + {3, OperandInfo214}, // Inst #1194 = CMP_UEQ_D + {3, OperandInfo214}, // Inst #1195 = CMP_UEQ_D_MMR6 + {3, OperandInfo215}, // Inst #1196 = CMP_UEQ_S + {3, OperandInfo215}, // Inst #1197 = CMP_UEQ_S_MMR6 + {3, OperandInfo214}, // Inst #1198 = CMP_ULE_D + {3, OperandInfo214}, // Inst #1199 = CMP_ULE_D_MMR6 + {3, OperandInfo215}, // Inst #1200 = CMP_ULE_S + {3, OperandInfo215}, // Inst #1201 = CMP_ULE_S_MMR6 + {3, OperandInfo214}, // Inst #1202 = CMP_ULT_D + {3, OperandInfo214}, // Inst #1203 = CMP_ULT_D_MMR6 + {3, OperandInfo215}, // Inst #1204 = CMP_ULT_S + {3, OperandInfo215}, // Inst #1205 = CMP_ULT_S_MMR6 + {3, OperandInfo214}, // Inst #1206 = CMP_UN_D + {3, OperandInfo214}, // Inst #1207 = CMP_UN_D_MMR6 + {3, OperandInfo215}, // Inst #1208 = CMP_UN_S + {3, OperandInfo215}, // Inst #1209 = CMP_UN_S_MMR6 + {3, OperandInfo216}, // Inst #1210 = COPY_S_B + {3, OperandInfo217}, // Inst #1211 = COPY_S_D + {3, OperandInfo218}, // Inst #1212 = COPY_S_H + {3, OperandInfo219}, // Inst #1213 = COPY_S_W + {3, OperandInfo216}, // Inst #1214 = COPY_U_B + {3, OperandInfo218}, // Inst #1215 = COPY_U_H + {3, OperandInfo219}, // Inst #1216 = COPY_U_W + {3, OperandInfo71}, // Inst #1217 = CRC32B + {3, OperandInfo71}, // Inst #1218 = CRC32CB + {3, OperandInfo71}, // Inst #1219 = CRC32CD + {3, OperandInfo71}, // Inst #1220 = CRC32CH + {3, OperandInfo71}, // Inst #1221 = CRC32CW + {3, OperandInfo71}, // Inst #1222 = CRC32D + {3, OperandInfo71}, // Inst #1223 = CRC32H + {3, OperandInfo71}, // Inst #1224 = CRC32W + {2, OperandInfo220}, // Inst #1225 = CTC1 + {2, OperandInfo220}, // Inst #1226 = CTC1_MM + {2, OperandInfo221}, // Inst #1227 = CTC2_MM + {2, OperandInfo222}, // Inst #1228 = CTCMSA + {2, OperandInfo223}, // Inst #1229 = CVT_D32_S + {2, OperandInfo223}, // Inst #1230 = CVT_D32_S_MM + {2, OperandInfo223}, // Inst #1231 = CVT_D32_W + {2, OperandInfo223}, // Inst #1232 = CVT_D32_W_MM + {2, OperandInfo202}, // Inst #1233 = CVT_D64_L + {2, OperandInfo203}, // Inst #1234 = CVT_D64_S + {2, OperandInfo203}, // Inst #1235 = CVT_D64_S_MM + {2, OperandInfo203}, // Inst #1236 = CVT_D64_W + {2, OperandInfo203}, // Inst #1237 = CVT_D64_W_MM + {2, OperandInfo202}, // Inst #1238 = CVT_D_L_MMR6 + {2, OperandInfo202}, // Inst #1239 = CVT_L_D64 + {2, OperandInfo202}, // Inst #1240 = CVT_L_D64_MM + {2, OperandInfo202}, // Inst #1241 = CVT_L_D_MMR6 + {2, OperandInfo203}, // Inst #1242 = CVT_L_S + {2, OperandInfo203}, // Inst #1243 = CVT_L_S_MM + {2, OperandInfo203}, // Inst #1244 = CVT_L_S_MMR6 + {2, OperandInfo202}, // Inst #1245 = CVT_PS_PW64 + {3, OperandInfo224}, // Inst #1246 = CVT_PS_S64 + {2, OperandInfo202}, // Inst #1247 = CVT_PW_PS64 + {2, OperandInfo204}, // Inst #1248 = CVT_S_D32 + {2, OperandInfo204}, // Inst #1249 = CVT_S_D32_MM + {2, OperandInfo205}, // Inst #1250 = CVT_S_D64 + {2, OperandInfo205}, // Inst #1251 = CVT_S_D64_MM + {2, OperandInfo205}, // Inst #1252 = CVT_S_L + {2, OperandInfo203}, // Inst #1253 = CVT_S_L_MMR6 + {2, OperandInfo205}, // Inst #1254 = CVT_S_PL64 + {2, OperandInfo205}, // Inst #1255 = CVT_S_PU64 + {2, OperandInfo206}, // Inst #1256 = CVT_S_W + {2, OperandInfo206}, // Inst #1257 = CVT_S_W_MM + {2, OperandInfo206}, // Inst #1258 = CVT_S_W_MMR6 + {2, OperandInfo204}, // Inst #1259 = CVT_W_D32 + {2, OperandInfo204}, // Inst #1260 = CVT_W_D32_MM + {2, OperandInfo205}, // Inst #1261 = CVT_W_D64 + {2, OperandInfo205}, // Inst #1262 = CVT_W_D64_MM + {2, OperandInfo206}, // Inst #1263 = CVT_W_S + {2, OperandInfo206}, // Inst #1264 = CVT_W_S_MM + {2, OperandInfo206}, // Inst #1265 = CVT_W_S_MMR6 + {3, OperandInfo225}, // Inst #1266 = C_EQ_D32 + {3, OperandInfo225}, // Inst #1267 = C_EQ_D32_MM + {3, OperandInfo226}, // Inst #1268 = C_EQ_D64 + {3, OperandInfo226}, // Inst #1269 = C_EQ_D64_MM + {3, OperandInfo227}, // Inst #1270 = C_EQ_S + {3, OperandInfo227}, // Inst #1271 = C_EQ_S_MM + {3, OperandInfo225}, // Inst #1272 = C_F_D32 + {3, OperandInfo225}, // Inst #1273 = C_F_D32_MM + {3, OperandInfo226}, // Inst #1274 = C_F_D64 + {3, OperandInfo226}, // Inst #1275 = C_F_D64_MM + {3, OperandInfo227}, // Inst #1276 = C_F_S + {3, OperandInfo227}, // Inst #1277 = C_F_S_MM + {3, OperandInfo225}, // Inst #1278 = C_LE_D32 + {3, OperandInfo225}, // Inst #1279 = C_LE_D32_MM + {3, OperandInfo226}, // Inst #1280 = C_LE_D64 + {3, OperandInfo226}, // Inst #1281 = C_LE_D64_MM + {3, OperandInfo227}, // Inst #1282 = C_LE_S + {3, OperandInfo227}, // Inst #1283 = C_LE_S_MM + {3, OperandInfo225}, // Inst #1284 = C_LT_D32 + {3, OperandInfo225}, // Inst #1285 = C_LT_D32_MM + {3, OperandInfo226}, // Inst #1286 = C_LT_D64 + {3, OperandInfo226}, // Inst #1287 = C_LT_D64_MM + {3, OperandInfo227}, // Inst #1288 = C_LT_S + {3, OperandInfo227}, // Inst #1289 = C_LT_S_MM + {3, OperandInfo225}, // Inst #1290 = C_NGE_D32 + {3, OperandInfo225}, // Inst #1291 = C_NGE_D32_MM + {3, OperandInfo226}, // Inst #1292 = C_NGE_D64 + {3, OperandInfo226}, // Inst #1293 = C_NGE_D64_MM + {3, OperandInfo227}, // Inst #1294 = C_NGE_S + {3, OperandInfo227}, // Inst #1295 = C_NGE_S_MM + {3, OperandInfo225}, // Inst #1296 = C_NGLE_D32 + {3, OperandInfo225}, // Inst #1297 = C_NGLE_D32_MM + {3, OperandInfo226}, // Inst #1298 = C_NGLE_D64 + {3, OperandInfo226}, // Inst #1299 = C_NGLE_D64_MM + {3, OperandInfo227}, // Inst #1300 = C_NGLE_S + {3, OperandInfo227}, // Inst #1301 = C_NGLE_S_MM + {3, OperandInfo225}, // Inst #1302 = C_NGL_D32 + {3, OperandInfo225}, // Inst #1303 = C_NGL_D32_MM + {3, OperandInfo226}, // Inst #1304 = C_NGL_D64 + {3, OperandInfo226}, // Inst #1305 = C_NGL_D64_MM + {3, OperandInfo227}, // Inst #1306 = C_NGL_S + {3, OperandInfo227}, // Inst #1307 = C_NGL_S_MM + {3, OperandInfo225}, // Inst #1308 = C_NGT_D32 + {3, OperandInfo225}, // Inst #1309 = C_NGT_D32_MM + {3, OperandInfo226}, // Inst #1310 = C_NGT_D64 + {3, OperandInfo226}, // Inst #1311 = C_NGT_D64_MM + {3, OperandInfo227}, // Inst #1312 = C_NGT_S + {3, OperandInfo227}, // Inst #1313 = C_NGT_S_MM + {3, OperandInfo225}, // Inst #1314 = C_OLE_D32 + {3, OperandInfo225}, // Inst #1315 = C_OLE_D32_MM + {3, OperandInfo226}, // Inst #1316 = C_OLE_D64 + {3, OperandInfo226}, // Inst #1317 = C_OLE_D64_MM + {3, OperandInfo227}, // Inst #1318 = C_OLE_S + {3, OperandInfo227}, // Inst #1319 = C_OLE_S_MM + {3, OperandInfo225}, // Inst #1320 = C_OLT_D32 + {3, OperandInfo225}, // Inst #1321 = C_OLT_D32_MM + {3, OperandInfo226}, // Inst #1322 = C_OLT_D64 + {3, OperandInfo226}, // Inst #1323 = C_OLT_D64_MM + {3, OperandInfo227}, // Inst #1324 = C_OLT_S + {3, OperandInfo227}, // Inst #1325 = C_OLT_S_MM + {3, OperandInfo225}, // Inst #1326 = C_SEQ_D32 + {3, OperandInfo225}, // Inst #1327 = C_SEQ_D32_MM + {3, OperandInfo226}, // Inst #1328 = C_SEQ_D64 + {3, OperandInfo226}, // Inst #1329 = C_SEQ_D64_MM + {3, OperandInfo227}, // Inst #1330 = C_SEQ_S + {3, OperandInfo227}, // Inst #1331 = C_SEQ_S_MM + {3, OperandInfo225}, // Inst #1332 = C_SF_D32 + {3, OperandInfo225}, // Inst #1333 = C_SF_D32_MM + {3, OperandInfo226}, // Inst #1334 = C_SF_D64 + {3, OperandInfo226}, // Inst #1335 = C_SF_D64_MM + {3, OperandInfo227}, // Inst #1336 = C_SF_S + {3, OperandInfo227}, // Inst #1337 = C_SF_S_MM + {3, OperandInfo225}, // Inst #1338 = C_UEQ_D32 + {3, OperandInfo225}, // Inst #1339 = C_UEQ_D32_MM + {3, OperandInfo226}, // Inst #1340 = C_UEQ_D64 + {3, OperandInfo226}, // Inst #1341 = C_UEQ_D64_MM + {3, OperandInfo227}, // Inst #1342 = C_UEQ_S + {3, OperandInfo227}, // Inst #1343 = C_UEQ_S_MM + {3, OperandInfo225}, // Inst #1344 = C_ULE_D32 + {3, OperandInfo225}, // Inst #1345 = C_ULE_D32_MM + {3, OperandInfo226}, // Inst #1346 = C_ULE_D64 + {3, OperandInfo226}, // Inst #1347 = C_ULE_D64_MM + {3, OperandInfo227}, // Inst #1348 = C_ULE_S + {3, OperandInfo227}, // Inst #1349 = C_ULE_S_MM + {3, OperandInfo225}, // Inst #1350 = C_ULT_D32 + {3, OperandInfo225}, // Inst #1351 = C_ULT_D32_MM + {3, OperandInfo226}, // Inst #1352 = C_ULT_D64 + {3, OperandInfo226}, // Inst #1353 = C_ULT_D64_MM + {3, OperandInfo227}, // Inst #1354 = C_ULT_S + {3, OperandInfo227}, // Inst #1355 = C_ULT_S_MM + {3, OperandInfo225}, // Inst #1356 = C_UN_D32 + {3, OperandInfo225}, // Inst #1357 = C_UN_D32_MM + {3, OperandInfo226}, // Inst #1358 = C_UN_D64 + {3, OperandInfo226}, // Inst #1359 = C_UN_D64_MM + {3, OperandInfo227}, // Inst #1360 = C_UN_S + {3, OperandInfo227}, // Inst #1361 = C_UN_S_MM + {2, OperandInfo129}, // Inst #1362 = CmpRxRy16 + {2, OperandInfo182}, // Inst #1363 = CmpiRxImm16 + {2, OperandInfo182}, // Inst #1364 = CmpiRxImmX16 + {3, OperandInfo70}, // Inst #1365 = DADD + {3, OperandInfo69}, // Inst #1366 = DADDi + {3, OperandInfo69}, // Inst #1367 = DADDiu + {3, OperandInfo70}, // Inst #1368 = DADDu + {3, OperandInfo228}, // Inst #1369 = DAHI + {4, OperandInfo229}, // Inst #1370 = DALIGN + {3, OperandInfo228}, // Inst #1371 = DATI + {3, OperandInfo69}, // Inst #1372 = DAUI + {2, OperandInfo121}, // Inst #1373 = DBITSWAP + {2, OperandInfo121}, // Inst #1374 = DCLO + {2, OperandInfo121}, // Inst #1375 = DCLO_R6 + {2, OperandInfo121}, // Inst #1376 = DCLZ + {2, OperandInfo121}, // Inst #1377 = DCLZ_R6 + {3, OperandInfo70}, // Inst #1378 = DDIV + {3, OperandInfo70}, // Inst #1379 = DDIVU + {0, NULL}, // Inst #1380 = DERET + {0, NULL}, // Inst #1381 = DERET_MM + {0, NULL}, // Inst #1382 = DERET_MMR6 + {4, OperandInfo210}, // Inst #1383 = DEXT + {4, OperandInfo211}, // Inst #1384 = DEXT64_32 + {4, OperandInfo210}, // Inst #1385 = DEXTM + {4, OperandInfo210}, // Inst #1386 = DEXTU + {1, OperandInfo57}, // Inst #1387 = DI + {5, OperandInfo230}, // Inst #1388 = DINS + {5, OperandInfo230}, // Inst #1389 = DINSM + {5, OperandInfo230}, // Inst #1390 = DINSU + {3, OperandInfo71}, // Inst #1391 = DIV + {3, OperandInfo71}, // Inst #1392 = DIVU + {3, OperandInfo71}, // Inst #1393 = DIVU_MMR6 + {3, OperandInfo71}, // Inst #1394 = DIV_MMR6 + {3, OperandInfo173}, // Inst #1395 = DIV_S_B + {3, OperandInfo45}, // Inst #1396 = DIV_S_D + {3, OperandInfo46}, // Inst #1397 = DIV_S_H + {3, OperandInfo47}, // Inst #1398 = DIV_S_W + {3, OperandInfo173}, // Inst #1399 = DIV_U_B + {3, OperandInfo45}, // Inst #1400 = DIV_U_D + {3, OperandInfo46}, // Inst #1401 = DIV_U_H + {3, OperandInfo47}, // Inst #1402 = DIV_U_W + {1, OperandInfo57}, // Inst #1403 = DI_MM + {1, OperandInfo57}, // Inst #1404 = DI_MMR6 + {4, OperandInfo229}, // Inst #1405 = DLSA + {4, OperandInfo229}, // Inst #1406 = DLSA_R6 + {3, OperandInfo231}, // Inst #1407 = DMFC0 + {2, OperandInfo232}, // Inst #1408 = DMFC1 + {3, OperandInfo233}, // Inst #1409 = DMFC2 + {2, OperandInfo111}, // Inst #1410 = DMFC2_OCTEON + {3, OperandInfo231}, // Inst #1411 = DMFGC0 + {3, OperandInfo70}, // Inst #1412 = DMOD + {3, OperandInfo70}, // Inst #1413 = DMODU + {1, OperandInfo57}, // Inst #1414 = DMT + {3, OperandInfo234}, // Inst #1415 = DMTC0 + {2, OperandInfo133}, // Inst #1416 = DMTC1 + {3, OperandInfo235}, // Inst #1417 = DMTC2 + {2, OperandInfo111}, // Inst #1418 = DMTC2_OCTEON + {3, OperandInfo234}, // Inst #1419 = DMTGC0 + {3, OperandInfo70}, // Inst #1420 = DMUH + {3, OperandInfo70}, // Inst #1421 = DMUHU + {3, OperandInfo70}, // Inst #1422 = DMUL + {2, OperandInfo121}, // Inst #1423 = DMULT + {2, OperandInfo121}, // Inst #1424 = DMULTu + {3, OperandInfo70}, // Inst #1425 = DMULU + {3, OperandInfo70}, // Inst #1426 = DMUL_R6 + {3, OperandInfo236}, // Inst #1427 = DOTP_S_D + {3, OperandInfo237}, // Inst #1428 = DOTP_S_H + {3, OperandInfo238}, // Inst #1429 = DOTP_S_W + {3, OperandInfo236}, // Inst #1430 = DOTP_U_D + {3, OperandInfo237}, // Inst #1431 = DOTP_U_H + {3, OperandInfo238}, // Inst #1432 = DOTP_U_W + {4, OperandInfo239}, // Inst #1433 = DPADD_S_D + {4, OperandInfo240}, // Inst #1434 = DPADD_S_H + {4, OperandInfo241}, // Inst #1435 = DPADD_S_W + {4, OperandInfo239}, // Inst #1436 = DPADD_U_D + {4, OperandInfo240}, // Inst #1437 = DPADD_U_H + {4, OperandInfo241}, // Inst #1438 = DPADD_U_W + {4, OperandInfo242}, // Inst #1439 = DPAQX_SA_W_PH + {4, OperandInfo242}, // Inst #1440 = DPAQX_SA_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1441 = DPAQX_S_W_PH + {4, OperandInfo242}, // Inst #1442 = DPAQX_S_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1443 = DPAQ_SA_L_W + {4, OperandInfo242}, // Inst #1444 = DPAQ_SA_L_W_MM + {4, OperandInfo242}, // Inst #1445 = DPAQ_S_W_PH + {4, OperandInfo242}, // Inst #1446 = DPAQ_S_W_PH_MM + {4, OperandInfo242}, // Inst #1447 = DPAU_H_QBL + {4, OperandInfo242}, // Inst #1448 = DPAU_H_QBL_MM + {4, OperandInfo242}, // Inst #1449 = DPAU_H_QBR + {4, OperandInfo242}, // Inst #1450 = DPAU_H_QBR_MM + {4, OperandInfo242}, // Inst #1451 = DPAX_W_PH + {4, OperandInfo242}, // Inst #1452 = DPAX_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1453 = DPA_W_PH + {4, OperandInfo242}, // Inst #1454 = DPA_W_PH_MMR2 + {2, OperandInfo121}, // Inst #1455 = DPOP + {4, OperandInfo242}, // Inst #1456 = DPSQX_SA_W_PH + {4, OperandInfo242}, // Inst #1457 = DPSQX_SA_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1458 = DPSQX_S_W_PH + {4, OperandInfo242}, // Inst #1459 = DPSQX_S_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1460 = DPSQ_SA_L_W + {4, OperandInfo242}, // Inst #1461 = DPSQ_SA_L_W_MM + {4, OperandInfo242}, // Inst #1462 = DPSQ_S_W_PH + {4, OperandInfo242}, // Inst #1463 = DPSQ_S_W_PH_MM + {4, OperandInfo239}, // Inst #1464 = DPSUB_S_D + {4, OperandInfo240}, // Inst #1465 = DPSUB_S_H + {4, OperandInfo241}, // Inst #1466 = DPSUB_S_W + {4, OperandInfo239}, // Inst #1467 = DPSUB_U_D + {4, OperandInfo240}, // Inst #1468 = DPSUB_U_H + {4, OperandInfo241}, // Inst #1469 = DPSUB_U_W + {4, OperandInfo242}, // Inst #1470 = DPSU_H_QBL + {4, OperandInfo242}, // Inst #1471 = DPSU_H_QBL_MM + {4, OperandInfo242}, // Inst #1472 = DPSU_H_QBR + {4, OperandInfo242}, // Inst #1473 = DPSU_H_QBR_MM + {4, OperandInfo242}, // Inst #1474 = DPSX_W_PH + {4, OperandInfo242}, // Inst #1475 = DPSX_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1476 = DPS_W_PH + {4, OperandInfo242}, // Inst #1477 = DPS_W_PH_MMR2 + {3, OperandInfo69}, // Inst #1478 = DROTR + {3, OperandInfo69}, // Inst #1479 = DROTR32 + {3, OperandInfo243}, // Inst #1480 = DROTRV + {2, OperandInfo121}, // Inst #1481 = DSBH + {2, OperandInfo121}, // Inst #1482 = DSDIV + {2, OperandInfo121}, // Inst #1483 = DSHD + {3, OperandInfo69}, // Inst #1484 = DSLL + {3, OperandInfo69}, // Inst #1485 = DSLL32 + {2, OperandInfo244}, // Inst #1486 = DSLL64_32 + {3, OperandInfo243}, // Inst #1487 = DSLLV + {3, OperandInfo69}, // Inst #1488 = DSRA + {3, OperandInfo69}, // Inst #1489 = DSRA32 + {3, OperandInfo243}, // Inst #1490 = DSRAV + {3, OperandInfo69}, // Inst #1491 = DSRL + {3, OperandInfo69}, // Inst #1492 = DSRL32 + {3, OperandInfo243}, // Inst #1493 = DSRLV + {3, OperandInfo70}, // Inst #1494 = DSUB + {3, OperandInfo70}, // Inst #1495 = DSUBu + {2, OperandInfo121}, // Inst #1496 = DUDIV + {1, OperandInfo57}, // Inst #1497 = DVP + {1, OperandInfo57}, // Inst #1498 = DVPE + {1, OperandInfo57}, // Inst #1499 = DVP_MMR6 + {2, OperandInfo129}, // Inst #1500 = DivRxRy16 + {2, OperandInfo129}, // Inst #1501 = DivuRxRy16 + {0, NULL}, // Inst #1502 = EHB + {0, NULL}, // Inst #1503 = EHB_MM + {0, NULL}, // Inst #1504 = EHB_MMR6 + {1, OperandInfo57}, // Inst #1505 = EI + {1, OperandInfo57}, // Inst #1506 = EI_MM + {1, OperandInfo57}, // Inst #1507 = EI_MMR6 + {1, OperandInfo57}, // Inst #1508 = EMT + {0, NULL}, // Inst #1509 = ERET + {0, NULL}, // Inst #1510 = ERETNC + {0, NULL}, // Inst #1511 = ERETNC_MMR6 + {0, NULL}, // Inst #1512 = ERET_MM + {0, NULL}, // Inst #1513 = ERET_MMR6 + {1, OperandInfo57}, // Inst #1514 = EVP + {1, OperandInfo57}, // Inst #1515 = EVPE + {1, OperandInfo57}, // Inst #1516 = EVP_MMR6 + {4, OperandInfo212}, // Inst #1517 = EXT + {3, OperandInfo245}, // Inst #1518 = EXTP + {3, OperandInfo245}, // Inst #1519 = EXTPDP + {3, OperandInfo246}, // Inst #1520 = EXTPDPV + {3, OperandInfo246}, // Inst #1521 = EXTPDPV_MM + {3, OperandInfo245}, // Inst #1522 = EXTPDP_MM + {3, OperandInfo246}, // Inst #1523 = EXTPV + {3, OperandInfo246}, // Inst #1524 = EXTPV_MM + {3, OperandInfo245}, // Inst #1525 = EXTP_MM + {3, OperandInfo246}, // Inst #1526 = EXTRV_RS_W + {3, OperandInfo246}, // Inst #1527 = EXTRV_RS_W_MM + {3, OperandInfo246}, // Inst #1528 = EXTRV_R_W + {3, OperandInfo246}, // Inst #1529 = EXTRV_R_W_MM + {3, OperandInfo246}, // Inst #1530 = EXTRV_S_H + {3, OperandInfo246}, // Inst #1531 = EXTRV_S_H_MM + {3, OperandInfo246}, // Inst #1532 = EXTRV_W + {3, OperandInfo246}, // Inst #1533 = EXTRV_W_MM + {3, OperandInfo245}, // Inst #1534 = EXTR_RS_W + {3, OperandInfo245}, // Inst #1535 = EXTR_RS_W_MM + {3, OperandInfo245}, // Inst #1536 = EXTR_R_W + {3, OperandInfo245}, // Inst #1537 = EXTR_R_W_MM + {3, OperandInfo245}, // Inst #1538 = EXTR_S_H + {3, OperandInfo245}, // Inst #1539 = EXTR_S_H_MM + {3, OperandInfo245}, // Inst #1540 = EXTR_W + {3, OperandInfo245}, // Inst #1541 = EXTR_W_MM + {4, OperandInfo210}, // Inst #1542 = EXTS + {4, OperandInfo210}, // Inst #1543 = EXTS32 + {4, OperandInfo212}, // Inst #1544 = EXT_MM + {4, OperandInfo212}, // Inst #1545 = EXT_MMR6 + {2, OperandInfo247}, // Inst #1546 = FABS_D32 + {2, OperandInfo247}, // Inst #1547 = FABS_D32_MM + {2, OperandInfo202}, // Inst #1548 = FABS_D64 + {2, OperandInfo202}, // Inst #1549 = FABS_D64_MM + {2, OperandInfo206}, // Inst #1550 = FABS_S + {2, OperandInfo206}, // Inst #1551 = FABS_S_MM + {3, OperandInfo45}, // Inst #1552 = FADD_D + {3, OperandInfo248}, // Inst #1553 = FADD_D32 + {3, OperandInfo248}, // Inst #1554 = FADD_D32_MM + {3, OperandInfo172}, // Inst #1555 = FADD_D64 + {3, OperandInfo172}, // Inst #1556 = FADD_D64_MM + {3, OperandInfo172}, // Inst #1557 = FADD_PS64 + {3, OperandInfo249}, // Inst #1558 = FADD_S + {3, OperandInfo249}, // Inst #1559 = FADD_S_MM + {3, OperandInfo249}, // Inst #1560 = FADD_S_MMR6 + {3, OperandInfo47}, // Inst #1561 = FADD_W + {3, OperandInfo45}, // Inst #1562 = FCAF_D + {3, OperandInfo47}, // Inst #1563 = FCAF_W + {3, OperandInfo45}, // Inst #1564 = FCEQ_D + {3, OperandInfo47}, // Inst #1565 = FCEQ_W + {2, OperandInfo75}, // Inst #1566 = FCLASS_D + {2, OperandInfo76}, // Inst #1567 = FCLASS_W + {3, OperandInfo45}, // Inst #1568 = FCLE_D + {3, OperandInfo47}, // Inst #1569 = FCLE_W + {3, OperandInfo45}, // Inst #1570 = FCLT_D + {3, OperandInfo47}, // Inst #1571 = FCLT_W + {3, OperandInfo250}, // Inst #1572 = FCMP_D32 + {3, OperandInfo250}, // Inst #1573 = FCMP_D32_MM + {3, OperandInfo251}, // Inst #1574 = FCMP_D64 + {3, OperandInfo252}, // Inst #1575 = FCMP_S32 + {3, OperandInfo252}, // Inst #1576 = FCMP_S32_MM + {3, OperandInfo45}, // Inst #1577 = FCNE_D + {3, OperandInfo47}, // Inst #1578 = FCNE_W + {3, OperandInfo45}, // Inst #1579 = FCOR_D + {3, OperandInfo47}, // Inst #1580 = FCOR_W + {3, OperandInfo45}, // Inst #1581 = FCUEQ_D + {3, OperandInfo47}, // Inst #1582 = FCUEQ_W + {3, OperandInfo45}, // Inst #1583 = FCULE_D + {3, OperandInfo47}, // Inst #1584 = FCULE_W + {3, OperandInfo45}, // Inst #1585 = FCULT_D + {3, OperandInfo47}, // Inst #1586 = FCULT_W + {3, OperandInfo45}, // Inst #1587 = FCUNE_D + {3, OperandInfo47}, // Inst #1588 = FCUNE_W + {3, OperandInfo45}, // Inst #1589 = FCUN_D + {3, OperandInfo47}, // Inst #1590 = FCUN_W + {3, OperandInfo45}, // Inst #1591 = FDIV_D + {3, OperandInfo248}, // Inst #1592 = FDIV_D32 + {3, OperandInfo248}, // Inst #1593 = FDIV_D32_MM + {3, OperandInfo172}, // Inst #1594 = FDIV_D64 + {3, OperandInfo172}, // Inst #1595 = FDIV_D64_MM + {3, OperandInfo249}, // Inst #1596 = FDIV_S + {3, OperandInfo249}, // Inst #1597 = FDIV_S_MM + {3, OperandInfo249}, // Inst #1598 = FDIV_S_MMR6 + {3, OperandInfo47}, // Inst #1599 = FDIV_W + {3, OperandInfo253}, // Inst #1600 = FEXDO_H + {3, OperandInfo254}, // Inst #1601 = FEXDO_W + {3, OperandInfo45}, // Inst #1602 = FEXP2_D + {3, OperandInfo47}, // Inst #1603 = FEXP2_W + {2, OperandInfo255}, // Inst #1604 = FEXUPL_D + {2, OperandInfo256}, // Inst #1605 = FEXUPL_W + {2, OperandInfo255}, // Inst #1606 = FEXUPR_D + {2, OperandInfo256}, // Inst #1607 = FEXUPR_W + {2, OperandInfo75}, // Inst #1608 = FFINT_S_D + {2, OperandInfo76}, // Inst #1609 = FFINT_S_W + {2, OperandInfo75}, // Inst #1610 = FFINT_U_D + {2, OperandInfo76}, // Inst #1611 = FFINT_U_W + {2, OperandInfo255}, // Inst #1612 = FFQL_D + {2, OperandInfo256}, // Inst #1613 = FFQL_W + {2, OperandInfo255}, // Inst #1614 = FFQR_D + {2, OperandInfo256}, // Inst #1615 = FFQR_W + {2, OperandInfo257}, // Inst #1616 = FILL_B + {2, OperandInfo258}, // Inst #1617 = FILL_D + {2, OperandInfo259}, // Inst #1618 = FILL_H + {2, OperandInfo260}, // Inst #1619 = FILL_W + {2, OperandInfo75}, // Inst #1620 = FLOG2_D + {2, OperandInfo76}, // Inst #1621 = FLOG2_W + {2, OperandInfo202}, // Inst #1622 = FLOOR_L_D64 + {2, OperandInfo202}, // Inst #1623 = FLOOR_L_D_MMR6 + {2, OperandInfo203}, // Inst #1624 = FLOOR_L_S + {2, OperandInfo203}, // Inst #1625 = FLOOR_L_S_MMR6 + {2, OperandInfo204}, // Inst #1626 = FLOOR_W_D32 + {2, OperandInfo205}, // Inst #1627 = FLOOR_W_D64 + {2, OperandInfo204}, // Inst #1628 = FLOOR_W_D_MMR6 + {2, OperandInfo204}, // Inst #1629 = FLOOR_W_MM + {2, OperandInfo206}, // Inst #1630 = FLOOR_W_S + {2, OperandInfo206}, // Inst #1631 = FLOOR_W_S_MM + {2, OperandInfo206}, // Inst #1632 = FLOOR_W_S_MMR6 + {4, OperandInfo58}, // Inst #1633 = FMADD_D + {4, OperandInfo59}, // Inst #1634 = FMADD_W + {3, OperandInfo45}, // Inst #1635 = FMAX_A_D + {3, OperandInfo47}, // Inst #1636 = FMAX_A_W + {3, OperandInfo45}, // Inst #1637 = FMAX_D + {3, OperandInfo47}, // Inst #1638 = FMAX_W + {3, OperandInfo45}, // Inst #1639 = FMIN_A_D + {3, OperandInfo47}, // Inst #1640 = FMIN_A_W + {3, OperandInfo45}, // Inst #1641 = FMIN_D + {3, OperandInfo47}, // Inst #1642 = FMIN_W + {2, OperandInfo247}, // Inst #1643 = FMOV_D32 + {2, OperandInfo247}, // Inst #1644 = FMOV_D32_MM + {2, OperandInfo202}, // Inst #1645 = FMOV_D64 + {2, OperandInfo202}, // Inst #1646 = FMOV_D64_MM + {2, OperandInfo202}, // Inst #1647 = FMOV_D_MMR6 + {2, OperandInfo206}, // Inst #1648 = FMOV_S + {2, OperandInfo206}, // Inst #1649 = FMOV_S_MM + {2, OperandInfo206}, // Inst #1650 = FMOV_S_MMR6 + {4, OperandInfo58}, // Inst #1651 = FMSUB_D + {4, OperandInfo59}, // Inst #1652 = FMSUB_W + {3, OperandInfo45}, // Inst #1653 = FMUL_D + {3, OperandInfo248}, // Inst #1654 = FMUL_D32 + {3, OperandInfo248}, // Inst #1655 = FMUL_D32_MM + {3, OperandInfo172}, // Inst #1656 = FMUL_D64 + {3, OperandInfo172}, // Inst #1657 = FMUL_D64_MM + {3, OperandInfo172}, // Inst #1658 = FMUL_PS64 + {3, OperandInfo249}, // Inst #1659 = FMUL_S + {3, OperandInfo249}, // Inst #1660 = FMUL_S_MM + {3, OperandInfo249}, // Inst #1661 = FMUL_S_MMR6 + {3, OperandInfo47}, // Inst #1662 = FMUL_W + {2, OperandInfo247}, // Inst #1663 = FNEG_D32 + {2, OperandInfo247}, // Inst #1664 = FNEG_D32_MM + {2, OperandInfo202}, // Inst #1665 = FNEG_D64 + {2, OperandInfo202}, // Inst #1666 = FNEG_D64_MM + {2, OperandInfo206}, // Inst #1667 = FNEG_S + {2, OperandInfo206}, // Inst #1668 = FNEG_S_MM + {2, OperandInfo206}, // Inst #1669 = FNEG_S_MMR6 + {3, OperandInfo71}, // Inst #1670 = FORK + {2, OperandInfo75}, // Inst #1671 = FRCP_D + {2, OperandInfo76}, // Inst #1672 = FRCP_W + {2, OperandInfo75}, // Inst #1673 = FRINT_D + {2, OperandInfo76}, // Inst #1674 = FRINT_W + {2, OperandInfo75}, // Inst #1675 = FRSQRT_D + {2, OperandInfo76}, // Inst #1676 = FRSQRT_W + {3, OperandInfo45}, // Inst #1677 = FSAF_D + {3, OperandInfo47}, // Inst #1678 = FSAF_W + {3, OperandInfo45}, // Inst #1679 = FSEQ_D + {3, OperandInfo47}, // Inst #1680 = FSEQ_W + {3, OperandInfo45}, // Inst #1681 = FSLE_D + {3, OperandInfo47}, // Inst #1682 = FSLE_W + {3, OperandInfo45}, // Inst #1683 = FSLT_D + {3, OperandInfo47}, // Inst #1684 = FSLT_W + {3, OperandInfo45}, // Inst #1685 = FSNE_D + {3, OperandInfo47}, // Inst #1686 = FSNE_W + {3, OperandInfo45}, // Inst #1687 = FSOR_D + {3, OperandInfo47}, // Inst #1688 = FSOR_W + {2, OperandInfo75}, // Inst #1689 = FSQRT_D + {2, OperandInfo247}, // Inst #1690 = FSQRT_D32 + {2, OperandInfo247}, // Inst #1691 = FSQRT_D32_MM + {2, OperandInfo202}, // Inst #1692 = FSQRT_D64 + {2, OperandInfo202}, // Inst #1693 = FSQRT_D64_MM + {2, OperandInfo206}, // Inst #1694 = FSQRT_S + {2, OperandInfo206}, // Inst #1695 = FSQRT_S_MM + {2, OperandInfo76}, // Inst #1696 = FSQRT_W + {3, OperandInfo45}, // Inst #1697 = FSUB_D + {3, OperandInfo248}, // Inst #1698 = FSUB_D32 + {3, OperandInfo248}, // Inst #1699 = FSUB_D32_MM + {3, OperandInfo172}, // Inst #1700 = FSUB_D64 + {3, OperandInfo172}, // Inst #1701 = FSUB_D64_MM + {3, OperandInfo172}, // Inst #1702 = FSUB_PS64 + {3, OperandInfo249}, // Inst #1703 = FSUB_S + {3, OperandInfo249}, // Inst #1704 = FSUB_S_MM + {3, OperandInfo249}, // Inst #1705 = FSUB_S_MMR6 + {3, OperandInfo47}, // Inst #1706 = FSUB_W + {3, OperandInfo45}, // Inst #1707 = FSUEQ_D + {3, OperandInfo47}, // Inst #1708 = FSUEQ_W + {3, OperandInfo45}, // Inst #1709 = FSULE_D + {3, OperandInfo47}, // Inst #1710 = FSULE_W + {3, OperandInfo45}, // Inst #1711 = FSULT_D + {3, OperandInfo47}, // Inst #1712 = FSULT_W + {3, OperandInfo45}, // Inst #1713 = FSUNE_D + {3, OperandInfo47}, // Inst #1714 = FSUNE_W + {3, OperandInfo45}, // Inst #1715 = FSUN_D + {3, OperandInfo47}, // Inst #1716 = FSUN_W + {2, OperandInfo75}, // Inst #1717 = FTINT_S_D + {2, OperandInfo76}, // Inst #1718 = FTINT_S_W + {2, OperandInfo75}, // Inst #1719 = FTINT_U_D + {2, OperandInfo76}, // Inst #1720 = FTINT_U_W + {3, OperandInfo253}, // Inst #1721 = FTQ_H + {3, OperandInfo254}, // Inst #1722 = FTQ_W + {2, OperandInfo75}, // Inst #1723 = FTRUNC_S_D + {2, OperandInfo76}, // Inst #1724 = FTRUNC_S_W + {2, OperandInfo75}, // Inst #1725 = FTRUNC_U_D + {2, OperandInfo76}, // Inst #1726 = FTRUNC_U_W + {1, OperandInfo57}, // Inst #1727 = GINVI + {1, OperandInfo57}, // Inst #1728 = GINVI_MMR6 + {2, OperandInfo113}, // Inst #1729 = GINVT + {2, OperandInfo113}, // Inst #1730 = GINVT_MMR6 + {3, OperandInfo236}, // Inst #1731 = HADD_S_D + {3, OperandInfo237}, // Inst #1732 = HADD_S_H + {3, OperandInfo238}, // Inst #1733 = HADD_S_W + {3, OperandInfo236}, // Inst #1734 = HADD_U_D + {3, OperandInfo237}, // Inst #1735 = HADD_U_H + {3, OperandInfo238}, // Inst #1736 = HADD_U_W + {3, OperandInfo236}, // Inst #1737 = HSUB_S_D + {3, OperandInfo237}, // Inst #1738 = HSUB_S_H + {3, OperandInfo238}, // Inst #1739 = HSUB_S_W + {3, OperandInfo236}, // Inst #1740 = HSUB_U_D + {3, OperandInfo237}, // Inst #1741 = HSUB_U_H + {3, OperandInfo238}, // Inst #1742 = HSUB_U_W + {1, OperandInfo2}, // Inst #1743 = HYPCALL + {1, OperandInfo2}, // Inst #1744 = HYPCALL_MM + {3, OperandInfo173}, // Inst #1745 = ILVEV_B + {3, OperandInfo45}, // Inst #1746 = ILVEV_D + {3, OperandInfo46}, // Inst #1747 = ILVEV_H + {3, OperandInfo47}, // Inst #1748 = ILVEV_W + {3, OperandInfo173}, // Inst #1749 = ILVL_B + {3, OperandInfo45}, // Inst #1750 = ILVL_D + {3, OperandInfo46}, // Inst #1751 = ILVL_H + {3, OperandInfo47}, // Inst #1752 = ILVL_W + {3, OperandInfo173}, // Inst #1753 = ILVOD_B + {3, OperandInfo45}, // Inst #1754 = ILVOD_D + {3, OperandInfo46}, // Inst #1755 = ILVOD_H + {3, OperandInfo47}, // Inst #1756 = ILVOD_W + {3, OperandInfo173}, // Inst #1757 = ILVR_B + {3, OperandInfo45}, // Inst #1758 = ILVR_D + {3, OperandInfo46}, // Inst #1759 = ILVR_H + {3, OperandInfo47}, // Inst #1760 = ILVR_W + {5, OperandInfo261}, // Inst #1761 = INS + {4, OperandInfo262}, // Inst #1762 = INSERT_B + {4, OperandInfo263}, // Inst #1763 = INSERT_D + {4, OperandInfo264}, // Inst #1764 = INSERT_H + {4, OperandInfo265}, // Inst #1765 = INSERT_W + {3, OperandInfo266}, // Inst #1766 = INSV + {5, OperandInfo267}, // Inst #1767 = INSVE_B + {5, OperandInfo268}, // Inst #1768 = INSVE_D + {5, OperandInfo269}, // Inst #1769 = INSVE_H + {5, OperandInfo270}, // Inst #1770 = INSVE_W + {3, OperandInfo266}, // Inst #1771 = INSV_MM + {5, OperandInfo261}, // Inst #1772 = INS_MM + {5, OperandInfo261}, // Inst #1773 = INS_MMR6 + {1, OperandInfo2}, // Inst #1774 = J + {1, OperandInfo2}, // Inst #1775 = JAL + {2, OperandInfo44}, // Inst #1776 = JALR + {1, OperandInfo57}, // Inst #1777 = JALR16_MM + {2, OperandInfo121}, // Inst #1778 = JALR64 + {1, OperandInfo57}, // Inst #1779 = JALRC16_MMR6 + {2, OperandInfo44}, // Inst #1780 = JALRC_HB_MMR6 + {2, OperandInfo44}, // Inst #1781 = JALRC_MMR6 + {1, OperandInfo57}, // Inst #1782 = JALRS16_MM + {2, OperandInfo44}, // Inst #1783 = JALRS_MM + {2, OperandInfo44}, // Inst #1784 = JALR_HB + {2, OperandInfo121}, // Inst #1785 = JALR_HB64 + {2, OperandInfo44}, // Inst #1786 = JALR_MM + {1, OperandInfo2}, // Inst #1787 = JALS_MM + {1, OperandInfo2}, // Inst #1788 = JALX + {1, OperandInfo2}, // Inst #1789 = JALX_MM + {1, OperandInfo2}, // Inst #1790 = JAL_MM + {2, OperandInfo113}, // Inst #1791 = JIALC + {2, OperandInfo111}, // Inst #1792 = JIALC64 + {2, OperandInfo113}, // Inst #1793 = JIALC_MMR6 + {2, OperandInfo113}, // Inst #1794 = JIC + {2, OperandInfo111}, // Inst #1795 = JIC64 + {2, OperandInfo113}, // Inst #1796 = JIC_MMR6 + {1, OperandInfo57}, // Inst #1797 = JR + {1, OperandInfo57}, // Inst #1798 = JR16_MM + {1, OperandInfo94}, // Inst #1799 = JR64 + {1, OperandInfo2}, // Inst #1800 = JRADDIUSP + {1, OperandInfo57}, // Inst #1801 = JRC16_MM + {1, OperandInfo57}, // Inst #1802 = JRC16_MMR6 + {1, OperandInfo2}, // Inst #1803 = JRCADDIUSP_MMR6 + {1, OperandInfo57}, // Inst #1804 = JR_HB + {1, OperandInfo94}, // Inst #1805 = JR_HB64 + {1, OperandInfo94}, // Inst #1806 = JR_HB64_R6 + {1, OperandInfo57}, // Inst #1807 = JR_HB_R6 + {1, OperandInfo57}, // Inst #1808 = JR_MM + {1, OperandInfo2}, // Inst #1809 = J_MM + {1, OperandInfo2}, // Inst #1810 = Jal16 + {1, OperandInfo2}, // Inst #1811 = JalB16 + {0, NULL}, // Inst #1812 = JrRa16 + {0, NULL}, // Inst #1813 = JrcRa16 + {1, OperandInfo271}, // Inst #1814 = JrcRx16 + {1, OperandInfo271}, // Inst #1815 = JumpLinkReg16 + {3, OperandInfo95}, // Inst #1816 = LB + {3, OperandInfo112}, // Inst #1817 = LB64 + {3, OperandInfo95}, // Inst #1818 = LBE + {3, OperandInfo95}, // Inst #1819 = LBE_MM + {3, OperandInfo272}, // Inst #1820 = LBU16_MM + {3, OperandInfo273}, // Inst #1821 = LBUX + {3, OperandInfo273}, // Inst #1822 = LBUX_MM + {3, OperandInfo95}, // Inst #1823 = LBU_MMR6 + {3, OperandInfo95}, // Inst #1824 = LB_MM + {3, OperandInfo95}, // Inst #1825 = LB_MMR6 + {3, OperandInfo95}, // Inst #1826 = LBu + {3, OperandInfo112}, // Inst #1827 = LBu64 + {3, OperandInfo95}, // Inst #1828 = LBuE + {3, OperandInfo95}, // Inst #1829 = LBuE_MM + {3, OperandInfo95}, // Inst #1830 = LBu_MM + {3, OperandInfo112}, // Inst #1831 = LD + {3, OperandInfo157}, // Inst #1832 = LDC1 + {3, OperandInfo274}, // Inst #1833 = LDC164 + {3, OperandInfo274}, // Inst #1834 = LDC1_D64_MMR6 + {3, OperandInfo157}, // Inst #1835 = LDC1_MM + {3, OperandInfo275}, // Inst #1836 = LDC2 + {3, OperandInfo276}, // Inst #1837 = LDC2_MMR6 + {3, OperandInfo275}, // Inst #1838 = LDC2_R6 + {3, OperandInfo277}, // Inst #1839 = LDC3 + {2, OperandInfo278}, // Inst #1840 = LDI_B + {2, OperandInfo279}, // Inst #1841 = LDI_D + {2, OperandInfo280}, // Inst #1842 = LDI_H + {2, OperandInfo281}, // Inst #1843 = LDI_W + {4, OperandInfo282}, // Inst #1844 = LDL + {2, OperandInfo111}, // Inst #1845 = LDPC + {4, OperandInfo282}, // Inst #1846 = LDR + {3, OperandInfo283}, // Inst #1847 = LDXC1 + {3, OperandInfo284}, // Inst #1848 = LDXC164 + {3, OperandInfo285}, // Inst #1849 = LD_B + {3, OperandInfo286}, // Inst #1850 = LD_D + {3, OperandInfo287}, // Inst #1851 = LD_H + {3, OperandInfo288}, // Inst #1852 = LD_W + {3, OperandInfo95}, // Inst #1853 = LEA_ADDiu + {3, OperandInfo112}, // Inst #1854 = LEA_ADDiu64 + {3, OperandInfo95}, // Inst #1855 = LEA_ADDiu_MM + {3, OperandInfo95}, // Inst #1856 = LH + {3, OperandInfo112}, // Inst #1857 = LH64 + {3, OperandInfo95}, // Inst #1858 = LHE + {3, OperandInfo95}, // Inst #1859 = LHE_MM + {3, OperandInfo272}, // Inst #1860 = LHU16_MM + {3, OperandInfo273}, // Inst #1861 = LHX + {3, OperandInfo273}, // Inst #1862 = LHX_MM + {3, OperandInfo95}, // Inst #1863 = LH_MM + {3, OperandInfo95}, // Inst #1864 = LHu + {3, OperandInfo112}, // Inst #1865 = LHu64 + {3, OperandInfo95}, // Inst #1866 = LHuE + {3, OperandInfo95}, // Inst #1867 = LHuE_MM + {3, OperandInfo95}, // Inst #1868 = LHu_MM + {2, OperandInfo168}, // Inst #1869 = LI16_MM + {2, OperandInfo168}, // Inst #1870 = LI16_MMR6 + {3, OperandInfo95}, // Inst #1871 = LL + {3, OperandInfo95}, // Inst #1872 = LL64 + {3, OperandInfo289}, // Inst #1873 = LL64_R6 + {3, OperandInfo112}, // Inst #1874 = LLD + {3, OperandInfo290}, // Inst #1875 = LLD_R6 + {3, OperandInfo95}, // Inst #1876 = LLE + {3, OperandInfo95}, // Inst #1877 = LLE_MM + {3, OperandInfo95}, // Inst #1878 = LL_MM + {3, OperandInfo95}, // Inst #1879 = LL_MMR6 + {3, OperandInfo289}, // Inst #1880 = LL_R6 + {4, OperandInfo179}, // Inst #1881 = LSA + {4, OperandInfo179}, // Inst #1882 = LSA_MMR6 + {4, OperandInfo179}, // Inst #1883 = LSA_R6 + {2, OperandInfo113}, // Inst #1884 = LUI_MMR6 + {3, OperandInfo283}, // Inst #1885 = LUXC1 + {3, OperandInfo284}, // Inst #1886 = LUXC164 + {3, OperandInfo284}, // Inst #1887 = LUXC1_MM + {2, OperandInfo113}, // Inst #1888 = LUi + {2, OperandInfo111}, // Inst #1889 = LUi64 + {2, OperandInfo113}, // Inst #1890 = LUi_MM + {3, OperandInfo95}, // Inst #1891 = LW + {3, OperandInfo272}, // Inst #1892 = LW16_MM + {3, OperandInfo112}, // Inst #1893 = LW64 + {3, OperandInfo291}, // Inst #1894 = LWC1 + {3, OperandInfo291}, // Inst #1895 = LWC1_MM + {3, OperandInfo275}, // Inst #1896 = LWC2 + {3, OperandInfo276}, // Inst #1897 = LWC2_MMR6 + {3, OperandInfo275}, // Inst #1898 = LWC2_R6 + {3, OperandInfo277}, // Inst #1899 = LWC3 + {3, OperandInfo292}, // Inst #1900 = LWDSP + {3, OperandInfo292}, // Inst #1901 = LWDSP_MM + {3, OperandInfo95}, // Inst #1902 = LWE + {3, OperandInfo95}, // Inst #1903 = LWE_MM + {3, OperandInfo293}, // Inst #1904 = LWGP_MM + {4, OperandInfo294}, // Inst #1905 = LWL + {4, OperandInfo282}, // Inst #1906 = LWL64 + {4, OperandInfo294}, // Inst #1907 = LWLE + {4, OperandInfo294}, // Inst #1908 = LWLE_MM + {4, OperandInfo294}, // Inst #1909 = LWL_MM + {3, OperandInfo295}, // Inst #1910 = LWM16_MM + {3, OperandInfo295}, // Inst #1911 = LWM16_MMR6 + {3, OperandInfo109}, // Inst #1912 = LWM32_MM + {2, OperandInfo113}, // Inst #1913 = LWPC + {2, OperandInfo113}, // Inst #1914 = LWPC_MMR6 + {4, OperandInfo296}, // Inst #1915 = LWP_MM + {4, OperandInfo294}, // Inst #1916 = LWR + {4, OperandInfo282}, // Inst #1917 = LWR64 + {4, OperandInfo294}, // Inst #1918 = LWRE + {4, OperandInfo294}, // Inst #1919 = LWRE_MM + {4, OperandInfo294}, // Inst #1920 = LWR_MM + {3, OperandInfo297}, // Inst #1921 = LWSP_MM + {2, OperandInfo113}, // Inst #1922 = LWUPC + {3, OperandInfo95}, // Inst #1923 = LWU_MM + {3, OperandInfo273}, // Inst #1924 = LWX + {3, OperandInfo298}, // Inst #1925 = LWXC1 + {3, OperandInfo298}, // Inst #1926 = LWXC1_MM + {3, OperandInfo273}, // Inst #1927 = LWXS_MM + {3, OperandInfo273}, // Inst #1928 = LWX_MM + {3, OperandInfo95}, // Inst #1929 = LW_MM + {3, OperandInfo95}, // Inst #1930 = LW_MMR6 + {3, OperandInfo112}, // Inst #1931 = LWu + {3, OperandInfo299}, // Inst #1932 = LbRxRyOffMemX16 + {3, OperandInfo299}, // Inst #1933 = LbuRxRyOffMemX16 + {3, OperandInfo299}, // Inst #1934 = LhRxRyOffMemX16 + {3, OperandInfo299}, // Inst #1935 = LhuRxRyOffMemX16 + {2, OperandInfo182}, // Inst #1936 = LiRxImm16 + {2, OperandInfo182}, // Inst #1937 = LiRxImmAlignX16 + {2, OperandInfo182}, // Inst #1938 = LiRxImmX16 + {3, OperandInfo300}, // Inst #1939 = LwRxPcTcp16 + {3, OperandInfo300}, // Inst #1940 = LwRxPcTcpX16 + {3, OperandInfo299}, // Inst #1941 = LwRxRyOffMemX16 + {3, OperandInfo184}, // Inst #1942 = LwRxSpImmX16 + {2, OperandInfo44}, // Inst #1943 = MADD + {4, OperandInfo301}, // Inst #1944 = MADDF_D + {4, OperandInfo301}, // Inst #1945 = MADDF_D_MMR6 + {4, OperandInfo302}, // Inst #1946 = MADDF_S + {4, OperandInfo302}, // Inst #1947 = MADDF_S_MMR6 + {4, OperandInfo60}, // Inst #1948 = MADDR_Q_H + {4, OperandInfo59}, // Inst #1949 = MADDR_Q_W + {2, OperandInfo44}, // Inst #1950 = MADDU + {4, OperandInfo242}, // Inst #1951 = MADDU_DSP + {4, OperandInfo242}, // Inst #1952 = MADDU_DSP_MM + {2, OperandInfo44}, // Inst #1953 = MADDU_MM + {4, OperandInfo195}, // Inst #1954 = MADDV_B + {4, OperandInfo58}, // Inst #1955 = MADDV_D + {4, OperandInfo60}, // Inst #1956 = MADDV_H + {4, OperandInfo59}, // Inst #1957 = MADDV_W + {4, OperandInfo303}, // Inst #1958 = MADD_D32 + {4, OperandInfo303}, // Inst #1959 = MADD_D32_MM + {4, OperandInfo304}, // Inst #1960 = MADD_D64 + {4, OperandInfo242}, // Inst #1961 = MADD_DSP + {4, OperandInfo242}, // Inst #1962 = MADD_DSP_MM + {2, OperandInfo44}, // Inst #1963 = MADD_MM + {4, OperandInfo60}, // Inst #1964 = MADD_Q_H + {4, OperandInfo59}, // Inst #1965 = MADD_Q_W + {4, OperandInfo305}, // Inst #1966 = MADD_S + {4, OperandInfo305}, // Inst #1967 = MADD_S_MM + {4, OperandInfo242}, // Inst #1968 = MAQ_SA_W_PHL + {4, OperandInfo242}, // Inst #1969 = MAQ_SA_W_PHL_MM + {4, OperandInfo242}, // Inst #1970 = MAQ_SA_W_PHR + {4, OperandInfo242}, // Inst #1971 = MAQ_SA_W_PHR_MM + {4, OperandInfo242}, // Inst #1972 = MAQ_S_W_PHL + {4, OperandInfo242}, // Inst #1973 = MAQ_S_W_PHL_MM + {4, OperandInfo242}, // Inst #1974 = MAQ_S_W_PHR + {4, OperandInfo242}, // Inst #1975 = MAQ_S_W_PHR_MM + {3, OperandInfo172}, // Inst #1976 = MAXA_D + {3, OperandInfo172}, // Inst #1977 = MAXA_D_MMR6 + {3, OperandInfo249}, // Inst #1978 = MAXA_S + {3, OperandInfo249}, // Inst #1979 = MAXA_S_MMR6 + {3, OperandInfo175}, // Inst #1980 = MAXI_S_B + {3, OperandInfo176}, // Inst #1981 = MAXI_S_D + {3, OperandInfo177}, // Inst #1982 = MAXI_S_H + {3, OperandInfo178}, // Inst #1983 = MAXI_S_W + {3, OperandInfo175}, // Inst #1984 = MAXI_U_B + {3, OperandInfo176}, // Inst #1985 = MAXI_U_D + {3, OperandInfo177}, // Inst #1986 = MAXI_U_H + {3, OperandInfo178}, // Inst #1987 = MAXI_U_W + {3, OperandInfo173}, // Inst #1988 = MAX_A_B + {3, OperandInfo45}, // Inst #1989 = MAX_A_D + {3, OperandInfo46}, // Inst #1990 = MAX_A_H + {3, OperandInfo47}, // Inst #1991 = MAX_A_W + {3, OperandInfo172}, // Inst #1992 = MAX_D + {3, OperandInfo172}, // Inst #1993 = MAX_D_MMR6 + {3, OperandInfo249}, // Inst #1994 = MAX_S + {3, OperandInfo173}, // Inst #1995 = MAX_S_B + {3, OperandInfo45}, // Inst #1996 = MAX_S_D + {3, OperandInfo46}, // Inst #1997 = MAX_S_H + {3, OperandInfo249}, // Inst #1998 = MAX_S_MMR6 + {3, OperandInfo47}, // Inst #1999 = MAX_S_W + {3, OperandInfo173}, // Inst #2000 = MAX_U_B + {3, OperandInfo45}, // Inst #2001 = MAX_U_D + {3, OperandInfo46}, // Inst #2002 = MAX_U_H + {3, OperandInfo47}, // Inst #2003 = MAX_U_W + {3, OperandInfo119}, // Inst #2004 = MFC0 + {3, OperandInfo119}, // Inst #2005 = MFC0_MMR6 + {2, OperandInfo120}, // Inst #2006 = MFC1 + {2, OperandInfo306}, // Inst #2007 = MFC1_D64 + {2, OperandInfo120}, // Inst #2008 = MFC1_MM + {2, OperandInfo120}, // Inst #2009 = MFC1_MMR6 + {3, OperandInfo307}, // Inst #2010 = MFC2 + {2, OperandInfo208}, // Inst #2011 = MFC2_MMR6 + {3, OperandInfo119}, // Inst #2012 = MFGC0 + {3, OperandInfo119}, // Inst #2013 = MFGC0_MM + {3, OperandInfo119}, // Inst #2014 = MFHC0_MMR6 + {2, OperandInfo308}, // Inst #2015 = MFHC1_D32 + {2, OperandInfo308}, // Inst #2016 = MFHC1_D32_MM + {2, OperandInfo306}, // Inst #2017 = MFHC1_D64 + {2, OperandInfo306}, // Inst #2018 = MFHC1_D64_MM + {2, OperandInfo208}, // Inst #2019 = MFHC2_MMR6 + {3, OperandInfo119}, // Inst #2020 = MFHGC0 + {3, OperandInfo119}, // Inst #2021 = MFHGC0_MM + {1, OperandInfo57}, // Inst #2022 = MFHI + {1, OperandInfo57}, // Inst #2023 = MFHI16_MM + {1, OperandInfo94}, // Inst #2024 = MFHI64 + {2, OperandInfo118}, // Inst #2025 = MFHI_DSP + {2, OperandInfo118}, // Inst #2026 = MFHI_DSP_MM + {1, OperandInfo57}, // Inst #2027 = MFHI_MM + {1, OperandInfo57}, // Inst #2028 = MFLO + {1, OperandInfo57}, // Inst #2029 = MFLO16_MM + {1, OperandInfo94}, // Inst #2030 = MFLO64 + {2, OperandInfo118}, // Inst #2031 = MFLO_DSP + {2, OperandInfo118}, // Inst #2032 = MFLO_DSP_MM + {1, OperandInfo57}, // Inst #2033 = MFLO_MM + {5, OperandInfo309}, // Inst #2034 = MFTR + {3, OperandInfo172}, // Inst #2035 = MINA_D + {3, OperandInfo172}, // Inst #2036 = MINA_D_MMR6 + {3, OperandInfo249}, // Inst #2037 = MINA_S + {3, OperandInfo249}, // Inst #2038 = MINA_S_MMR6 + {3, OperandInfo175}, // Inst #2039 = MINI_S_B + {3, OperandInfo176}, // Inst #2040 = MINI_S_D + {3, OperandInfo177}, // Inst #2041 = MINI_S_H + {3, OperandInfo178}, // Inst #2042 = MINI_S_W + {3, OperandInfo175}, // Inst #2043 = MINI_U_B + {3, OperandInfo176}, // Inst #2044 = MINI_U_D + {3, OperandInfo177}, // Inst #2045 = MINI_U_H + {3, OperandInfo178}, // Inst #2046 = MINI_U_W + {3, OperandInfo173}, // Inst #2047 = MIN_A_B + {3, OperandInfo45}, // Inst #2048 = MIN_A_D + {3, OperandInfo46}, // Inst #2049 = MIN_A_H + {3, OperandInfo47}, // Inst #2050 = MIN_A_W + {3, OperandInfo172}, // Inst #2051 = MIN_D + {3, OperandInfo172}, // Inst #2052 = MIN_D_MMR6 + {3, OperandInfo249}, // Inst #2053 = MIN_S + {3, OperandInfo173}, // Inst #2054 = MIN_S_B + {3, OperandInfo45}, // Inst #2055 = MIN_S_D + {3, OperandInfo46}, // Inst #2056 = MIN_S_H + {3, OperandInfo249}, // Inst #2057 = MIN_S_MMR6 + {3, OperandInfo47}, // Inst #2058 = MIN_S_W + {3, OperandInfo173}, // Inst #2059 = MIN_U_B + {3, OperandInfo45}, // Inst #2060 = MIN_U_D + {3, OperandInfo46}, // Inst #2061 = MIN_U_H + {3, OperandInfo47}, // Inst #2062 = MIN_U_W + {3, OperandInfo71}, // Inst #2063 = MOD + {3, OperandInfo71}, // Inst #2064 = MODSUB + {3, OperandInfo71}, // Inst #2065 = MODSUB_MM + {3, OperandInfo71}, // Inst #2066 = MODU + {3, OperandInfo71}, // Inst #2067 = MODU_MMR6 + {3, OperandInfo71}, // Inst #2068 = MOD_MMR6 + {3, OperandInfo173}, // Inst #2069 = MOD_S_B + {3, OperandInfo45}, // Inst #2070 = MOD_S_D + {3, OperandInfo46}, // Inst #2071 = MOD_S_H + {3, OperandInfo47}, // Inst #2072 = MOD_S_W + {3, OperandInfo173}, // Inst #2073 = MOD_U_B + {3, OperandInfo45}, // Inst #2074 = MOD_U_D + {3, OperandInfo46}, // Inst #2075 = MOD_U_H + {3, OperandInfo47}, // Inst #2076 = MOD_U_W + {2, OperandInfo44}, // Inst #2077 = MOVE16_MM + {2, OperandInfo44}, // Inst #2078 = MOVE16_MMR6 + {4, OperandInfo310}, // Inst #2079 = MOVEP_MM + {4, OperandInfo310}, // Inst #2080 = MOVEP_MMR6 + {2, OperandInfo311}, // Inst #2081 = MOVE_V + {4, OperandInfo312}, // Inst #2082 = MOVF_D32 + {4, OperandInfo312}, // Inst #2083 = MOVF_D32_MM + {4, OperandInfo313}, // Inst #2084 = MOVF_D64 + {4, OperandInfo314}, // Inst #2085 = MOVF_I + {4, OperandInfo315}, // Inst #2086 = MOVF_I64 + {4, OperandInfo314}, // Inst #2087 = MOVF_I_MM + {4, OperandInfo316}, // Inst #2088 = MOVF_S + {4, OperandInfo316}, // Inst #2089 = MOVF_S_MM + {4, OperandInfo317}, // Inst #2090 = MOVN_I64_D64 + {4, OperandInfo318}, // Inst #2091 = MOVN_I64_I + {4, OperandInfo319}, // Inst #2092 = MOVN_I64_I64 + {4, OperandInfo320}, // Inst #2093 = MOVN_I64_S + {4, OperandInfo321}, // Inst #2094 = MOVN_I_D32 + {4, OperandInfo321}, // Inst #2095 = MOVN_I_D32_MM + {4, OperandInfo322}, // Inst #2096 = MOVN_I_D64 + {4, OperandInfo323}, // Inst #2097 = MOVN_I_I + {4, OperandInfo324}, // Inst #2098 = MOVN_I_I64 + {4, OperandInfo323}, // Inst #2099 = MOVN_I_MM + {4, OperandInfo325}, // Inst #2100 = MOVN_I_S + {4, OperandInfo325}, // Inst #2101 = MOVN_I_S_MM + {4, OperandInfo312}, // Inst #2102 = MOVT_D32 + {4, OperandInfo312}, // Inst #2103 = MOVT_D32_MM + {4, OperandInfo313}, // Inst #2104 = MOVT_D64 + {4, OperandInfo314}, // Inst #2105 = MOVT_I + {4, OperandInfo315}, // Inst #2106 = MOVT_I64 + {4, OperandInfo314}, // Inst #2107 = MOVT_I_MM + {4, OperandInfo316}, // Inst #2108 = MOVT_S + {4, OperandInfo316}, // Inst #2109 = MOVT_S_MM + {4, OperandInfo317}, // Inst #2110 = MOVZ_I64_D64 + {4, OperandInfo318}, // Inst #2111 = MOVZ_I64_I + {4, OperandInfo319}, // Inst #2112 = MOVZ_I64_I64 + {4, OperandInfo320}, // Inst #2113 = MOVZ_I64_S + {4, OperandInfo321}, // Inst #2114 = MOVZ_I_D32 + {4, OperandInfo321}, // Inst #2115 = MOVZ_I_D32_MM + {4, OperandInfo322}, // Inst #2116 = MOVZ_I_D64 + {4, OperandInfo323}, // Inst #2117 = MOVZ_I_I + {4, OperandInfo324}, // Inst #2118 = MOVZ_I_I64 + {4, OperandInfo323}, // Inst #2119 = MOVZ_I_MM + {4, OperandInfo325}, // Inst #2120 = MOVZ_I_S + {4, OperandInfo325}, // Inst #2121 = MOVZ_I_S_MM + {2, OperandInfo44}, // Inst #2122 = MSUB + {4, OperandInfo301}, // Inst #2123 = MSUBF_D + {4, OperandInfo301}, // Inst #2124 = MSUBF_D_MMR6 + {4, OperandInfo302}, // Inst #2125 = MSUBF_S + {4, OperandInfo302}, // Inst #2126 = MSUBF_S_MMR6 + {4, OperandInfo60}, // Inst #2127 = MSUBR_Q_H + {4, OperandInfo59}, // Inst #2128 = MSUBR_Q_W + {2, OperandInfo44}, // Inst #2129 = MSUBU + {4, OperandInfo242}, // Inst #2130 = MSUBU_DSP + {4, OperandInfo242}, // Inst #2131 = MSUBU_DSP_MM + {2, OperandInfo44}, // Inst #2132 = MSUBU_MM + {4, OperandInfo195}, // Inst #2133 = MSUBV_B + {4, OperandInfo58}, // Inst #2134 = MSUBV_D + {4, OperandInfo60}, // Inst #2135 = MSUBV_H + {4, OperandInfo59}, // Inst #2136 = MSUBV_W + {4, OperandInfo303}, // Inst #2137 = MSUB_D32 + {4, OperandInfo303}, // Inst #2138 = MSUB_D32_MM + {4, OperandInfo304}, // Inst #2139 = MSUB_D64 + {4, OperandInfo242}, // Inst #2140 = MSUB_DSP + {4, OperandInfo242}, // Inst #2141 = MSUB_DSP_MM + {2, OperandInfo44}, // Inst #2142 = MSUB_MM + {4, OperandInfo60}, // Inst #2143 = MSUB_Q_H + {4, OperandInfo59}, // Inst #2144 = MSUB_Q_W + {4, OperandInfo305}, // Inst #2145 = MSUB_S + {4, OperandInfo305}, // Inst #2146 = MSUB_S_MM + {3, OperandInfo127}, // Inst #2147 = MTC0 + {3, OperandInfo127}, // Inst #2148 = MTC0_MMR6 + {2, OperandInfo128}, // Inst #2149 = MTC1 + {2, OperandInfo134}, // Inst #2150 = MTC1_D64 + {2, OperandInfo134}, // Inst #2151 = MTC1_D64_MM + {2, OperandInfo128}, // Inst #2152 = MTC1_MM + {2, OperandInfo128}, // Inst #2153 = MTC1_MMR6 + {3, OperandInfo326}, // Inst #2154 = MTC2 + {2, OperandInfo221}, // Inst #2155 = MTC2_MMR6 + {3, OperandInfo127}, // Inst #2156 = MTGC0 + {3, OperandInfo127}, // Inst #2157 = MTGC0_MM + {3, OperandInfo127}, // Inst #2158 = MTHC0_MMR6 + {3, OperandInfo327}, // Inst #2159 = MTHC1_D32 + {3, OperandInfo327}, // Inst #2160 = MTHC1_D32_MM + {3, OperandInfo328}, // Inst #2161 = MTHC1_D64 + {3, OperandInfo328}, // Inst #2162 = MTHC1_D64_MM + {2, OperandInfo221}, // Inst #2163 = MTHC2_MMR6 + {3, OperandInfo127}, // Inst #2164 = MTHGC0 + {3, OperandInfo127}, // Inst #2165 = MTHGC0_MM + {1, OperandInfo57}, // Inst #2166 = MTHI + {1, OperandInfo94}, // Inst #2167 = MTHI64 + {2, OperandInfo329}, // Inst #2168 = MTHI_DSP + {2, OperandInfo329}, // Inst #2169 = MTHI_DSP_MM + {1, OperandInfo57}, // Inst #2170 = MTHI_MM + {3, OperandInfo330}, // Inst #2171 = MTHLIP + {3, OperandInfo330}, // Inst #2172 = MTHLIP_MM + {1, OperandInfo57}, // Inst #2173 = MTLO + {1, OperandInfo94}, // Inst #2174 = MTLO64 + {2, OperandInfo331}, // Inst #2175 = MTLO_DSP + {2, OperandInfo331}, // Inst #2176 = MTLO_DSP_MM + {1, OperandInfo57}, // Inst #2177 = MTLO_MM + {1, OperandInfo94}, // Inst #2178 = MTM0 + {1, OperandInfo94}, // Inst #2179 = MTM1 + {1, OperandInfo94}, // Inst #2180 = MTM2 + {1, OperandInfo94}, // Inst #2181 = MTP0 + {1, OperandInfo94}, // Inst #2182 = MTP1 + {1, OperandInfo94}, // Inst #2183 = MTP2 + {5, OperandInfo309}, // Inst #2184 = MTTR + {3, OperandInfo71}, // Inst #2185 = MUH + {3, OperandInfo71}, // Inst #2186 = MUHU + {3, OperandInfo71}, // Inst #2187 = MUHU_MMR6 + {3, OperandInfo71}, // Inst #2188 = MUH_MMR6 + {3, OperandInfo71}, // Inst #2189 = MUL + {3, OperandInfo213}, // Inst #2190 = MULEQ_S_W_PHL + {3, OperandInfo213}, // Inst #2191 = MULEQ_S_W_PHL_MM + {3, OperandInfo213}, // Inst #2192 = MULEQ_S_W_PHR + {3, OperandInfo213}, // Inst #2193 = MULEQ_S_W_PHR_MM + {3, OperandInfo171}, // Inst #2194 = MULEU_S_PH_QBL + {3, OperandInfo171}, // Inst #2195 = MULEU_S_PH_QBL_MM + {3, OperandInfo171}, // Inst #2196 = MULEU_S_PH_QBR + {3, OperandInfo171}, // Inst #2197 = MULEU_S_PH_QBR_MM + {3, OperandInfo171}, // Inst #2198 = MULQ_RS_PH + {3, OperandInfo171}, // Inst #2199 = MULQ_RS_PH_MM + {3, OperandInfo71}, // Inst #2200 = MULQ_RS_W + {3, OperandInfo71}, // Inst #2201 = MULQ_RS_W_MMR2 + {3, OperandInfo171}, // Inst #2202 = MULQ_S_PH + {3, OperandInfo171}, // Inst #2203 = MULQ_S_PH_MMR2 + {3, OperandInfo71}, // Inst #2204 = MULQ_S_W + {3, OperandInfo71}, // Inst #2205 = MULQ_S_W_MMR2 + {3, OperandInfo172}, // Inst #2206 = MULR_PS64 + {3, OperandInfo46}, // Inst #2207 = MULR_Q_H + {3, OperandInfo47}, // Inst #2208 = MULR_Q_W + {4, OperandInfo242}, // Inst #2209 = MULSAQ_S_W_PH + {4, OperandInfo242}, // Inst #2210 = MULSAQ_S_W_PH_MM + {4, OperandInfo242}, // Inst #2211 = MULSA_W_PH + {4, OperandInfo242}, // Inst #2212 = MULSA_W_PH_MMR2 + {2, OperandInfo44}, // Inst #2213 = MULT + {3, OperandInfo142}, // Inst #2214 = MULTU_DSP + {3, OperandInfo142}, // Inst #2215 = MULTU_DSP_MM + {3, OperandInfo142}, // Inst #2216 = MULT_DSP + {3, OperandInfo142}, // Inst #2217 = MULT_DSP_MM + {2, OperandInfo44}, // Inst #2218 = MULT_MM + {2, OperandInfo44}, // Inst #2219 = MULTu + {2, OperandInfo44}, // Inst #2220 = MULTu_MM + {3, OperandInfo71}, // Inst #2221 = MULU + {3, OperandInfo71}, // Inst #2222 = MULU_MMR6 + {3, OperandInfo173}, // Inst #2223 = MULV_B + {3, OperandInfo45}, // Inst #2224 = MULV_D + {3, OperandInfo46}, // Inst #2225 = MULV_H + {3, OperandInfo47}, // Inst #2226 = MULV_W + {3, OperandInfo71}, // Inst #2227 = MUL_MM + {3, OperandInfo71}, // Inst #2228 = MUL_MMR6 + {3, OperandInfo171}, // Inst #2229 = MUL_PH + {3, OperandInfo171}, // Inst #2230 = MUL_PH_MMR2 + {3, OperandInfo46}, // Inst #2231 = MUL_Q_H + {3, OperandInfo47}, // Inst #2232 = MUL_Q_W + {3, OperandInfo71}, // Inst #2233 = MUL_R6 + {3, OperandInfo171}, // Inst #2234 = MUL_S_PH + {3, OperandInfo171}, // Inst #2235 = MUL_S_PH_MMR2 + {1, OperandInfo271}, // Inst #2236 = Mfhi16 + {1, OperandInfo271}, // Inst #2237 = Mflo16 + {2, OperandInfo332}, // Inst #2238 = Move32R16 + {2, OperandInfo333}, // Inst #2239 = MoveR3216 + {2, OperandInfo311}, // Inst #2240 = NLOC_B + {2, OperandInfo75}, // Inst #2241 = NLOC_D + {2, OperandInfo334}, // Inst #2242 = NLOC_H + {2, OperandInfo76}, // Inst #2243 = NLOC_W + {2, OperandInfo311}, // Inst #2244 = NLZC_B + {2, OperandInfo75}, // Inst #2245 = NLZC_D + {2, OperandInfo334}, // Inst #2246 = NLZC_H + {2, OperandInfo76}, // Inst #2247 = NLZC_W + {4, OperandInfo303}, // Inst #2248 = NMADD_D32 + {4, OperandInfo303}, // Inst #2249 = NMADD_D32_MM + {4, OperandInfo304}, // Inst #2250 = NMADD_D64 + {4, OperandInfo305}, // Inst #2251 = NMADD_S + {4, OperandInfo305}, // Inst #2252 = NMADD_S_MM + {4, OperandInfo303}, // Inst #2253 = NMSUB_D32 + {4, OperandInfo303}, // Inst #2254 = NMSUB_D32_MM + {4, OperandInfo304}, // Inst #2255 = NMSUB_D64 + {4, OperandInfo305}, // Inst #2256 = NMSUB_S + {4, OperandInfo305}, // Inst #2257 = NMSUB_S_MM + {3, OperandInfo71}, // Inst #2258 = NOR + {3, OperandInfo70}, // Inst #2259 = NOR64 + {3, OperandInfo175}, // Inst #2260 = NORI_B + {3, OperandInfo71}, // Inst #2261 = NOR_MM + {3, OperandInfo71}, // Inst #2262 = NOR_MMR6 + {3, OperandInfo173}, // Inst #2263 = NOR_V + {2, OperandInfo335}, // Inst #2264 = NOT16_MM + {2, OperandInfo335}, // Inst #2265 = NOT16_MMR6 + {2, OperandInfo129}, // Inst #2266 = NegRxRy16 + {2, OperandInfo129}, // Inst #2267 = NotRxRy16 + {3, OperandInfo71}, // Inst #2268 = OR + {3, OperandInfo180}, // Inst #2269 = OR16_MM + {3, OperandInfo180}, // Inst #2270 = OR16_MMR6 + {3, OperandInfo70}, // Inst #2271 = OR64 + {3, OperandInfo175}, // Inst #2272 = ORI_B + {3, OperandInfo72}, // Inst #2273 = ORI_MMR6 + {3, OperandInfo71}, // Inst #2274 = OR_MM + {3, OperandInfo71}, // Inst #2275 = OR_MMR6 + {3, OperandInfo173}, // Inst #2276 = OR_V + {3, OperandInfo72}, // Inst #2277 = ORi + {3, OperandInfo69}, // Inst #2278 = ORi64 + {3, OperandInfo72}, // Inst #2279 = ORi_MM + {3, OperandInfo185}, // Inst #2280 = OrRxRxRy16 + {3, OperandInfo171}, // Inst #2281 = PACKRL_PH + {3, OperandInfo171}, // Inst #2282 = PACKRL_PH_MM + {0, NULL}, // Inst #2283 = PAUSE + {0, NULL}, // Inst #2284 = PAUSE_MM + {0, NULL}, // Inst #2285 = PAUSE_MMR6 + {3, OperandInfo173}, // Inst #2286 = PCKEV_B + {3, OperandInfo45}, // Inst #2287 = PCKEV_D + {3, OperandInfo46}, // Inst #2288 = PCKEV_H + {3, OperandInfo47}, // Inst #2289 = PCKEV_W + {3, OperandInfo173}, // Inst #2290 = PCKOD_B + {3, OperandInfo45}, // Inst #2291 = PCKOD_D + {3, OperandInfo46}, // Inst #2292 = PCKOD_H + {3, OperandInfo47}, // Inst #2293 = PCKOD_W + {2, OperandInfo311}, // Inst #2294 = PCNT_B + {2, OperandInfo75}, // Inst #2295 = PCNT_D + {2, OperandInfo334}, // Inst #2296 = PCNT_H + {2, OperandInfo76}, // Inst #2297 = PCNT_W + {3, OperandInfo171}, // Inst #2298 = PICK_PH + {3, OperandInfo171}, // Inst #2299 = PICK_PH_MM + {3, OperandInfo171}, // Inst #2300 = PICK_QB + {3, OperandInfo171}, // Inst #2301 = PICK_QB_MM + {3, OperandInfo172}, // Inst #2302 = PLL_PS64 + {3, OperandInfo172}, // Inst #2303 = PLU_PS64 + {2, OperandInfo44}, // Inst #2304 = POP + {2, OperandInfo167}, // Inst #2305 = PRECEQU_PH_QBL + {2, OperandInfo167}, // Inst #2306 = PRECEQU_PH_QBLA + {2, OperandInfo167}, // Inst #2307 = PRECEQU_PH_QBLA_MM + {2, OperandInfo167}, // Inst #2308 = PRECEQU_PH_QBL_MM + {2, OperandInfo167}, // Inst #2309 = PRECEQU_PH_QBR + {2, OperandInfo167}, // Inst #2310 = PRECEQU_PH_QBRA + {2, OperandInfo167}, // Inst #2311 = PRECEQU_PH_QBRA_MM + {2, OperandInfo167}, // Inst #2312 = PRECEQU_PH_QBR_MM + {2, OperandInfo336}, // Inst #2313 = PRECEQ_W_PHL + {2, OperandInfo336}, // Inst #2314 = PRECEQ_W_PHL_MM + {2, OperandInfo336}, // Inst #2315 = PRECEQ_W_PHR + {2, OperandInfo336}, // Inst #2316 = PRECEQ_W_PHR_MM + {2, OperandInfo167}, // Inst #2317 = PRECEU_PH_QBL + {2, OperandInfo167}, // Inst #2318 = PRECEU_PH_QBLA + {2, OperandInfo167}, // Inst #2319 = PRECEU_PH_QBLA_MM + {2, OperandInfo167}, // Inst #2320 = PRECEU_PH_QBL_MM + {2, OperandInfo167}, // Inst #2321 = PRECEU_PH_QBR + {2, OperandInfo167}, // Inst #2322 = PRECEU_PH_QBRA + {2, OperandInfo167}, // Inst #2323 = PRECEU_PH_QBRA_MM + {2, OperandInfo167}, // Inst #2324 = PRECEU_PH_QBR_MM + {3, OperandInfo171}, // Inst #2325 = PRECRQU_S_QB_PH + {3, OperandInfo171}, // Inst #2326 = PRECRQU_S_QB_PH_MM + {3, OperandInfo337}, // Inst #2327 = PRECRQ_PH_W + {3, OperandInfo337}, // Inst #2328 = PRECRQ_PH_W_MM + {3, OperandInfo171}, // Inst #2329 = PRECRQ_QB_PH + {3, OperandInfo171}, // Inst #2330 = PRECRQ_QB_PH_MM + {3, OperandInfo337}, // Inst #2331 = PRECRQ_RS_PH_W + {3, OperandInfo337}, // Inst #2332 = PRECRQ_RS_PH_W_MM + {3, OperandInfo171}, // Inst #2333 = PRECR_QB_PH + {3, OperandInfo171}, // Inst #2334 = PRECR_QB_PH_MMR2 + {4, OperandInfo338}, // Inst #2335 = PRECR_SRA_PH_W + {4, OperandInfo338}, // Inst #2336 = PRECR_SRA_PH_W_MMR2 + {4, OperandInfo338}, // Inst #2337 = PRECR_SRA_R_PH_W + {4, OperandInfo338}, // Inst #2338 = PRECR_SRA_R_PH_W_MMR2 + {3, OperandInfo201}, // Inst #2339 = PREF + {3, OperandInfo201}, // Inst #2340 = PREFE + {3, OperandInfo201}, // Inst #2341 = PREFE_MM + {3, OperandInfo339}, // Inst #2342 = PREFX_MM + {3, OperandInfo201}, // Inst #2343 = PREF_MM + {3, OperandInfo201}, // Inst #2344 = PREF_MMR6 + {3, OperandInfo201}, // Inst #2345 = PREF_R6 + {4, OperandInfo181}, // Inst #2346 = PREPEND + {4, OperandInfo181}, // Inst #2347 = PREPEND_MMR2 + {3, OperandInfo172}, // Inst #2348 = PUL_PS64 + {3, OperandInfo172}, // Inst #2349 = PUU_PS64 + {2, OperandInfo336}, // Inst #2350 = RADDU_W_QB + {2, OperandInfo336}, // Inst #2351 = RADDU_W_QB_MM + {2, OperandInfo113}, // Inst #2352 = RDDSP + {2, OperandInfo113}, // Inst #2353 = RDDSP_MM + {3, OperandInfo340}, // Inst #2354 = RDHWR + {3, OperandInfo341}, // Inst #2355 = RDHWR64 + {3, OperandInfo340}, // Inst #2356 = RDHWR_MM + {3, OperandInfo340}, // Inst #2357 = RDHWR_MMR6 + {2, OperandInfo44}, // Inst #2358 = RDPGPR_MMR6 + {2, OperandInfo247}, // Inst #2359 = RECIP_D32 + {2, OperandInfo247}, // Inst #2360 = RECIP_D32_MM + {2, OperandInfo202}, // Inst #2361 = RECIP_D64 + {2, OperandInfo202}, // Inst #2362 = RECIP_D64_MM + {2, OperandInfo206}, // Inst #2363 = RECIP_S + {2, OperandInfo206}, // Inst #2364 = RECIP_S_MM + {2, OperandInfo342}, // Inst #2365 = REPLV_PH + {2, OperandInfo342}, // Inst #2366 = REPLV_PH_MM + {2, OperandInfo342}, // Inst #2367 = REPLV_QB + {2, OperandInfo342}, // Inst #2368 = REPLV_QB_MM + {2, OperandInfo343}, // Inst #2369 = REPL_PH + {2, OperandInfo343}, // Inst #2370 = REPL_PH_MM + {2, OperandInfo343}, // Inst #2371 = REPL_QB + {2, OperandInfo343}, // Inst #2372 = REPL_QB_MM + {2, OperandInfo202}, // Inst #2373 = RINT_D + {2, OperandInfo202}, // Inst #2374 = RINT_D_MMR6 + {2, OperandInfo206}, // Inst #2375 = RINT_S + {2, OperandInfo206}, // Inst #2376 = RINT_S_MMR6 + {3, OperandInfo72}, // Inst #2377 = ROTR + {3, OperandInfo71}, // Inst #2378 = ROTRV + {3, OperandInfo71}, // Inst #2379 = ROTRV_MM + {3, OperandInfo72}, // Inst #2380 = ROTR_MM + {2, OperandInfo202}, // Inst #2381 = ROUND_L_D64 + {2, OperandInfo202}, // Inst #2382 = ROUND_L_D_MMR6 + {2, OperandInfo203}, // Inst #2383 = ROUND_L_S + {2, OperandInfo203}, // Inst #2384 = ROUND_L_S_MMR6 + {2, OperandInfo204}, // Inst #2385 = ROUND_W_D32 + {2, OperandInfo205}, // Inst #2386 = ROUND_W_D64 + {2, OperandInfo202}, // Inst #2387 = ROUND_W_D_MMR6 + {2, OperandInfo204}, // Inst #2388 = ROUND_W_MM + {2, OperandInfo206}, // Inst #2389 = ROUND_W_S + {2, OperandInfo206}, // Inst #2390 = ROUND_W_S_MM + {2, OperandInfo206}, // Inst #2391 = ROUND_W_S_MMR6 + {2, OperandInfo247}, // Inst #2392 = RSQRT_D32 + {2, OperandInfo247}, // Inst #2393 = RSQRT_D32_MM + {2, OperandInfo202}, // Inst #2394 = RSQRT_D64 + {2, OperandInfo202}, // Inst #2395 = RSQRT_D64_MM + {2, OperandInfo206}, // Inst #2396 = RSQRT_S + {2, OperandInfo206}, // Inst #2397 = RSQRT_S_MM + {0, NULL}, // Inst #2398 = Restore16 + {0, NULL}, // Inst #2399 = RestoreX16 + {2, OperandInfo121}, // Inst #2400 = SAA + {2, OperandInfo121}, // Inst #2401 = SAAD + {3, OperandInfo175}, // Inst #2402 = SAT_S_B + {3, OperandInfo176}, // Inst #2403 = SAT_S_D + {3, OperandInfo177}, // Inst #2404 = SAT_S_H + {3, OperandInfo178}, // Inst #2405 = SAT_S_W + {3, OperandInfo175}, // Inst #2406 = SAT_U_B + {3, OperandInfo176}, // Inst #2407 = SAT_U_D + {3, OperandInfo177}, // Inst #2408 = SAT_U_H + {3, OperandInfo178}, // Inst #2409 = SAT_U_W + {3, OperandInfo95}, // Inst #2410 = SB + {3, OperandInfo344}, // Inst #2411 = SB16_MM + {3, OperandInfo344}, // Inst #2412 = SB16_MMR6 + {3, OperandInfo112}, // Inst #2413 = SB64 + {3, OperandInfo95}, // Inst #2414 = SBE + {3, OperandInfo95}, // Inst #2415 = SBE_MM + {3, OperandInfo95}, // Inst #2416 = SB_MM + {3, OperandInfo95}, // Inst #2417 = SB_MMR6 + {4, OperandInfo345}, // Inst #2418 = SC + {4, OperandInfo345}, // Inst #2419 = SC64 + {4, OperandInfo346}, // Inst #2420 = SC64_R6 + {4, OperandInfo347}, // Inst #2421 = SCD + {4, OperandInfo348}, // Inst #2422 = SCD_R6 + {4, OperandInfo345}, // Inst #2423 = SCE + {4, OperandInfo345}, // Inst #2424 = SCE_MM + {4, OperandInfo345}, // Inst #2425 = SC_MM + {4, OperandInfo345}, // Inst #2426 = SC_MMR6 + {4, OperandInfo346}, // Inst #2427 = SC_R6 + {3, OperandInfo112}, // Inst #2428 = SD + {1, OperandInfo2}, // Inst #2429 = SDBBP + {1, OperandInfo2}, // Inst #2430 = SDBBP16_MM + {1, OperandInfo2}, // Inst #2431 = SDBBP16_MMR6 + {1, OperandInfo2}, // Inst #2432 = SDBBP_MM + {1, OperandInfo2}, // Inst #2433 = SDBBP_MMR6 + {1, OperandInfo2}, // Inst #2434 = SDBBP_R6 + {3, OperandInfo157}, // Inst #2435 = SDC1 + {3, OperandInfo274}, // Inst #2436 = SDC164 + {3, OperandInfo274}, // Inst #2437 = SDC1_D64_MMR6 + {3, OperandInfo157}, // Inst #2438 = SDC1_MM + {3, OperandInfo275}, // Inst #2439 = SDC2 + {3, OperandInfo276}, // Inst #2440 = SDC2_MMR6 + {3, OperandInfo275}, // Inst #2441 = SDC2_R6 + {3, OperandInfo277}, // Inst #2442 = SDC3 + {2, OperandInfo44}, // Inst #2443 = SDIV + {2, OperandInfo44}, // Inst #2444 = SDIV_MM + {3, OperandInfo112}, // Inst #2445 = SDL + {3, OperandInfo112}, // Inst #2446 = SDR + {3, OperandInfo283}, // Inst #2447 = SDXC1 + {3, OperandInfo284}, // Inst #2448 = SDXC164 + {2, OperandInfo44}, // Inst #2449 = SEB + {2, OperandInfo121}, // Inst #2450 = SEB64 + {2, OperandInfo44}, // Inst #2451 = SEB_MM + {2, OperandInfo44}, // Inst #2452 = SEH + {2, OperandInfo121}, // Inst #2453 = SEH64 + {2, OperandInfo44}, // Inst #2454 = SEH_MM + {3, OperandInfo71}, // Inst #2455 = SELEQZ + {3, OperandInfo70}, // Inst #2456 = SELEQZ64 + {3, OperandInfo172}, // Inst #2457 = SELEQZ_D + {3, OperandInfo172}, // Inst #2458 = SELEQZ_D_MMR6 + {3, OperandInfo71}, // Inst #2459 = SELEQZ_MMR6 + {3, OperandInfo249}, // Inst #2460 = SELEQZ_S + {3, OperandInfo249}, // Inst #2461 = SELEQZ_S_MMR6 + {3, OperandInfo71}, // Inst #2462 = SELNEZ + {3, OperandInfo70}, // Inst #2463 = SELNEZ64 + {3, OperandInfo172}, // Inst #2464 = SELNEZ_D + {3, OperandInfo172}, // Inst #2465 = SELNEZ_D_MMR6 + {3, OperandInfo71}, // Inst #2466 = SELNEZ_MMR6 + {3, OperandInfo249}, // Inst #2467 = SELNEZ_S + {3, OperandInfo249}, // Inst #2468 = SELNEZ_S_MMR6 + {4, OperandInfo301}, // Inst #2469 = SEL_D + {4, OperandInfo301}, // Inst #2470 = SEL_D_MMR6 + {4, OperandInfo349}, // Inst #2471 = SEL_S + {4, OperandInfo349}, // Inst #2472 = SEL_S_MMR6 + {3, OperandInfo70}, // Inst #2473 = SEQ + {3, OperandInfo69}, // Inst #2474 = SEQi + {3, OperandInfo95}, // Inst #2475 = SH + {3, OperandInfo344}, // Inst #2476 = SH16_MM + {3, OperandInfo344}, // Inst #2477 = SH16_MMR6 + {3, OperandInfo112}, // Inst #2478 = SH64 + {3, OperandInfo95}, // Inst #2479 = SHE + {3, OperandInfo95}, // Inst #2480 = SHE_MM + {3, OperandInfo175}, // Inst #2481 = SHF_B + {3, OperandInfo177}, // Inst #2482 = SHF_H + {3, OperandInfo178}, // Inst #2483 = SHF_W + {3, OperandInfo350}, // Inst #2484 = SHILO + {3, OperandInfo330}, // Inst #2485 = SHILOV + {3, OperandInfo330}, // Inst #2486 = SHILOV_MM + {3, OperandInfo350}, // Inst #2487 = SHILO_MM + {3, OperandInfo351}, // Inst #2488 = SHLLV_PH + {3, OperandInfo351}, // Inst #2489 = SHLLV_PH_MM + {3, OperandInfo351}, // Inst #2490 = SHLLV_QB + {3, OperandInfo351}, // Inst #2491 = SHLLV_QB_MM + {3, OperandInfo351}, // Inst #2492 = SHLLV_S_PH + {3, OperandInfo351}, // Inst #2493 = SHLLV_S_PH_MM + {3, OperandInfo71}, // Inst #2494 = SHLLV_S_W + {3, OperandInfo71}, // Inst #2495 = SHLLV_S_W_MM + {3, OperandInfo352}, // Inst #2496 = SHLL_PH + {3, OperandInfo352}, // Inst #2497 = SHLL_PH_MM + {3, OperandInfo352}, // Inst #2498 = SHLL_QB + {3, OperandInfo352}, // Inst #2499 = SHLL_QB_MM + {3, OperandInfo352}, // Inst #2500 = SHLL_S_PH + {3, OperandInfo352}, // Inst #2501 = SHLL_S_PH_MM + {3, OperandInfo72}, // Inst #2502 = SHLL_S_W + {3, OperandInfo72}, // Inst #2503 = SHLL_S_W_MM + {3, OperandInfo351}, // Inst #2504 = SHRAV_PH + {3, OperandInfo351}, // Inst #2505 = SHRAV_PH_MM + {3, OperandInfo351}, // Inst #2506 = SHRAV_QB + {3, OperandInfo351}, // Inst #2507 = SHRAV_QB_MMR2 + {3, OperandInfo351}, // Inst #2508 = SHRAV_R_PH + {3, OperandInfo351}, // Inst #2509 = SHRAV_R_PH_MM + {3, OperandInfo351}, // Inst #2510 = SHRAV_R_QB + {3, OperandInfo351}, // Inst #2511 = SHRAV_R_QB_MMR2 + {3, OperandInfo71}, // Inst #2512 = SHRAV_R_W + {3, OperandInfo71}, // Inst #2513 = SHRAV_R_W_MM + {3, OperandInfo352}, // Inst #2514 = SHRA_PH + {3, OperandInfo352}, // Inst #2515 = SHRA_PH_MM + {3, OperandInfo352}, // Inst #2516 = SHRA_QB + {3, OperandInfo352}, // Inst #2517 = SHRA_QB_MMR2 + {3, OperandInfo352}, // Inst #2518 = SHRA_R_PH + {3, OperandInfo352}, // Inst #2519 = SHRA_R_PH_MM + {3, OperandInfo352}, // Inst #2520 = SHRA_R_QB + {3, OperandInfo352}, // Inst #2521 = SHRA_R_QB_MMR2 + {3, OperandInfo72}, // Inst #2522 = SHRA_R_W + {3, OperandInfo72}, // Inst #2523 = SHRA_R_W_MM + {3, OperandInfo351}, // Inst #2524 = SHRLV_PH + {3, OperandInfo351}, // Inst #2525 = SHRLV_PH_MMR2 + {3, OperandInfo351}, // Inst #2526 = SHRLV_QB + {3, OperandInfo351}, // Inst #2527 = SHRLV_QB_MM + {3, OperandInfo352}, // Inst #2528 = SHRL_PH + {3, OperandInfo352}, // Inst #2529 = SHRL_PH_MMR2 + {3, OperandInfo352}, // Inst #2530 = SHRL_QB + {3, OperandInfo352}, // Inst #2531 = SHRL_QB_MM + {3, OperandInfo95}, // Inst #2532 = SH_MM + {3, OperandInfo95}, // Inst #2533 = SH_MMR6 + {1, OperandInfo2}, // Inst #2534 = SIGRIE + {1, OperandInfo2}, // Inst #2535 = SIGRIE_MMR6 + {4, OperandInfo191}, // Inst #2536 = SLDI_B + {4, OperandInfo192}, // Inst #2537 = SLDI_D + {4, OperandInfo193}, // Inst #2538 = SLDI_H + {4, OperandInfo194}, // Inst #2539 = SLDI_W + {4, OperandInfo353}, // Inst #2540 = SLD_B + {4, OperandInfo354}, // Inst #2541 = SLD_D + {4, OperandInfo355}, // Inst #2542 = SLD_H + {4, OperandInfo356}, // Inst #2543 = SLD_W + {3, OperandInfo72}, // Inst #2544 = SLL + {3, OperandInfo169}, // Inst #2545 = SLL16_MM + {3, OperandInfo169}, // Inst #2546 = SLL16_MMR6 + {2, OperandInfo244}, // Inst #2547 = SLL64_32 + {2, OperandInfo121}, // Inst #2548 = SLL64_64 + {3, OperandInfo175}, // Inst #2549 = SLLI_B + {3, OperandInfo176}, // Inst #2550 = SLLI_D + {3, OperandInfo177}, // Inst #2551 = SLLI_H + {3, OperandInfo178}, // Inst #2552 = SLLI_W + {3, OperandInfo71}, // Inst #2553 = SLLV + {3, OperandInfo71}, // Inst #2554 = SLLV_MM + {3, OperandInfo173}, // Inst #2555 = SLL_B + {3, OperandInfo45}, // Inst #2556 = SLL_D + {3, OperandInfo46}, // Inst #2557 = SLL_H + {3, OperandInfo72}, // Inst #2558 = SLL_MM + {3, OperandInfo72}, // Inst #2559 = SLL_MMR6 + {3, OperandInfo47}, // Inst #2560 = SLL_W + {3, OperandInfo71}, // Inst #2561 = SLT + {3, OperandInfo357}, // Inst #2562 = SLT64 + {3, OperandInfo71}, // Inst #2563 = SLT_MM + {3, OperandInfo72}, // Inst #2564 = SLTi + {3, OperandInfo358}, // Inst #2565 = SLTi64 + {3, OperandInfo72}, // Inst #2566 = SLTi_MM + {3, OperandInfo72}, // Inst #2567 = SLTiu + {3, OperandInfo358}, // Inst #2568 = SLTiu64 + {3, OperandInfo72}, // Inst #2569 = SLTiu_MM + {3, OperandInfo71}, // Inst #2570 = SLTu + {3, OperandInfo357}, // Inst #2571 = SLTu64 + {3, OperandInfo71}, // Inst #2572 = SLTu_MM + {3, OperandInfo70}, // Inst #2573 = SNE + {3, OperandInfo69}, // Inst #2574 = SNEi + {3, OperandInfo175}, // Inst #2575 = SPLATI_B + {3, OperandInfo176}, // Inst #2576 = SPLATI_D + {3, OperandInfo177}, // Inst #2577 = SPLATI_H + {3, OperandInfo178}, // Inst #2578 = SPLATI_W + {3, OperandInfo359}, // Inst #2579 = SPLAT_B + {3, OperandInfo360}, // Inst #2580 = SPLAT_D + {3, OperandInfo361}, // Inst #2581 = SPLAT_H + {3, OperandInfo362}, // Inst #2582 = SPLAT_W + {3, OperandInfo72}, // Inst #2583 = SRA + {3, OperandInfo175}, // Inst #2584 = SRAI_B + {3, OperandInfo176}, // Inst #2585 = SRAI_D + {3, OperandInfo177}, // Inst #2586 = SRAI_H + {3, OperandInfo178}, // Inst #2587 = SRAI_W + {3, OperandInfo175}, // Inst #2588 = SRARI_B + {3, OperandInfo176}, // Inst #2589 = SRARI_D + {3, OperandInfo177}, // Inst #2590 = SRARI_H + {3, OperandInfo178}, // Inst #2591 = SRARI_W + {3, OperandInfo173}, // Inst #2592 = SRAR_B + {3, OperandInfo45}, // Inst #2593 = SRAR_D + {3, OperandInfo46}, // Inst #2594 = SRAR_H + {3, OperandInfo47}, // Inst #2595 = SRAR_W + {3, OperandInfo71}, // Inst #2596 = SRAV + {3, OperandInfo71}, // Inst #2597 = SRAV_MM + {3, OperandInfo173}, // Inst #2598 = SRA_B + {3, OperandInfo45}, // Inst #2599 = SRA_D + {3, OperandInfo46}, // Inst #2600 = SRA_H + {3, OperandInfo72}, // Inst #2601 = SRA_MM + {3, OperandInfo47}, // Inst #2602 = SRA_W + {3, OperandInfo72}, // Inst #2603 = SRL + {3, OperandInfo169}, // Inst #2604 = SRL16_MM + {3, OperandInfo169}, // Inst #2605 = SRL16_MMR6 + {3, OperandInfo175}, // Inst #2606 = SRLI_B + {3, OperandInfo176}, // Inst #2607 = SRLI_D + {3, OperandInfo177}, // Inst #2608 = SRLI_H + {3, OperandInfo178}, // Inst #2609 = SRLI_W + {3, OperandInfo175}, // Inst #2610 = SRLRI_B + {3, OperandInfo176}, // Inst #2611 = SRLRI_D + {3, OperandInfo177}, // Inst #2612 = SRLRI_H + {3, OperandInfo178}, // Inst #2613 = SRLRI_W + {3, OperandInfo173}, // Inst #2614 = SRLR_B + {3, OperandInfo45}, // Inst #2615 = SRLR_D + {3, OperandInfo46}, // Inst #2616 = SRLR_H + {3, OperandInfo47}, // Inst #2617 = SRLR_W + {3, OperandInfo71}, // Inst #2618 = SRLV + {3, OperandInfo71}, // Inst #2619 = SRLV_MM + {3, OperandInfo173}, // Inst #2620 = SRL_B + {3, OperandInfo45}, // Inst #2621 = SRL_D + {3, OperandInfo46}, // Inst #2622 = SRL_H + {3, OperandInfo72}, // Inst #2623 = SRL_MM + {3, OperandInfo47}, // Inst #2624 = SRL_W + {0, NULL}, // Inst #2625 = SSNOP + {0, NULL}, // Inst #2626 = SSNOP_MM + {0, NULL}, // Inst #2627 = SSNOP_MMR6 + {3, OperandInfo285}, // Inst #2628 = ST_B + {3, OperandInfo286}, // Inst #2629 = ST_D + {3, OperandInfo287}, // Inst #2630 = ST_H + {3, OperandInfo288}, // Inst #2631 = ST_W + {3, OperandInfo71}, // Inst #2632 = SUB + {3, OperandInfo171}, // Inst #2633 = SUBQH_PH + {3, OperandInfo171}, // Inst #2634 = SUBQH_PH_MMR2 + {3, OperandInfo171}, // Inst #2635 = SUBQH_R_PH + {3, OperandInfo171}, // Inst #2636 = SUBQH_R_PH_MMR2 + {3, OperandInfo71}, // Inst #2637 = SUBQH_R_W + {3, OperandInfo71}, // Inst #2638 = SUBQH_R_W_MMR2 + {3, OperandInfo71}, // Inst #2639 = SUBQH_W + {3, OperandInfo71}, // Inst #2640 = SUBQH_W_MMR2 + {3, OperandInfo171}, // Inst #2641 = SUBQ_PH + {3, OperandInfo171}, // Inst #2642 = SUBQ_PH_MM + {3, OperandInfo171}, // Inst #2643 = SUBQ_S_PH + {3, OperandInfo171}, // Inst #2644 = SUBQ_S_PH_MM + {3, OperandInfo71}, // Inst #2645 = SUBQ_S_W + {3, OperandInfo71}, // Inst #2646 = SUBQ_S_W_MM + {3, OperandInfo173}, // Inst #2647 = SUBSUS_U_B + {3, OperandInfo45}, // Inst #2648 = SUBSUS_U_D + {3, OperandInfo46}, // Inst #2649 = SUBSUS_U_H + {3, OperandInfo47}, // Inst #2650 = SUBSUS_U_W + {3, OperandInfo173}, // Inst #2651 = SUBSUU_S_B + {3, OperandInfo45}, // Inst #2652 = SUBSUU_S_D + {3, OperandInfo46}, // Inst #2653 = SUBSUU_S_H + {3, OperandInfo47}, // Inst #2654 = SUBSUU_S_W + {3, OperandInfo173}, // Inst #2655 = SUBS_S_B + {3, OperandInfo45}, // Inst #2656 = SUBS_S_D + {3, OperandInfo46}, // Inst #2657 = SUBS_S_H + {3, OperandInfo47}, // Inst #2658 = SUBS_S_W + {3, OperandInfo173}, // Inst #2659 = SUBS_U_B + {3, OperandInfo45}, // Inst #2660 = SUBS_U_D + {3, OperandInfo46}, // Inst #2661 = SUBS_U_H + {3, OperandInfo47}, // Inst #2662 = SUBS_U_W + {3, OperandInfo174}, // Inst #2663 = SUBU16_MM + {3, OperandInfo174}, // Inst #2664 = SUBU16_MMR6 + {3, OperandInfo171}, // Inst #2665 = SUBUH_QB + {3, OperandInfo171}, // Inst #2666 = SUBUH_QB_MMR2 + {3, OperandInfo171}, // Inst #2667 = SUBUH_R_QB + {3, OperandInfo171}, // Inst #2668 = SUBUH_R_QB_MMR2 + {3, OperandInfo71}, // Inst #2669 = SUBU_MMR6 + {3, OperandInfo171}, // Inst #2670 = SUBU_PH + {3, OperandInfo171}, // Inst #2671 = SUBU_PH_MMR2 + {3, OperandInfo171}, // Inst #2672 = SUBU_QB + {3, OperandInfo171}, // Inst #2673 = SUBU_QB_MM + {3, OperandInfo171}, // Inst #2674 = SUBU_S_PH + {3, OperandInfo171}, // Inst #2675 = SUBU_S_PH_MMR2 + {3, OperandInfo171}, // Inst #2676 = SUBU_S_QB + {3, OperandInfo171}, // Inst #2677 = SUBU_S_QB_MM + {3, OperandInfo175}, // Inst #2678 = SUBVI_B + {3, OperandInfo176}, // Inst #2679 = SUBVI_D + {3, OperandInfo177}, // Inst #2680 = SUBVI_H + {3, OperandInfo178}, // Inst #2681 = SUBVI_W + {3, OperandInfo173}, // Inst #2682 = SUBV_B + {3, OperandInfo45}, // Inst #2683 = SUBV_D + {3, OperandInfo46}, // Inst #2684 = SUBV_H + {3, OperandInfo47}, // Inst #2685 = SUBV_W + {3, OperandInfo71}, // Inst #2686 = SUB_MM + {3, OperandInfo71}, // Inst #2687 = SUB_MMR6 + {3, OperandInfo71}, // Inst #2688 = SUBu + {3, OperandInfo71}, // Inst #2689 = SUBu_MM + {3, OperandInfo283}, // Inst #2690 = SUXC1 + {3, OperandInfo284}, // Inst #2691 = SUXC164 + {3, OperandInfo284}, // Inst #2692 = SUXC1_MM + {3, OperandInfo95}, // Inst #2693 = SW + {3, OperandInfo344}, // Inst #2694 = SW16_MM + {3, OperandInfo344}, // Inst #2695 = SW16_MMR6 + {3, OperandInfo112}, // Inst #2696 = SW64 + {3, OperandInfo291}, // Inst #2697 = SWC1 + {3, OperandInfo291}, // Inst #2698 = SWC1_MM + {3, OperandInfo275}, // Inst #2699 = SWC2 + {3, OperandInfo276}, // Inst #2700 = SWC2_MMR6 + {3, OperandInfo275}, // Inst #2701 = SWC2_R6 + {3, OperandInfo277}, // Inst #2702 = SWC3 + {3, OperandInfo292}, // Inst #2703 = SWDSP + {3, OperandInfo292}, // Inst #2704 = SWDSP_MM + {3, OperandInfo95}, // Inst #2705 = SWE + {3, OperandInfo95}, // Inst #2706 = SWE_MM + {3, OperandInfo95}, // Inst #2707 = SWL + {3, OperandInfo112}, // Inst #2708 = SWL64 + {3, OperandInfo95}, // Inst #2709 = SWLE + {3, OperandInfo95}, // Inst #2710 = SWLE_MM + {3, OperandInfo95}, // Inst #2711 = SWL_MM + {3, OperandInfo295}, // Inst #2712 = SWM16_MM + {3, OperandInfo295}, // Inst #2713 = SWM16_MMR6 + {3, OperandInfo109}, // Inst #2714 = SWM32_MM + {4, OperandInfo296}, // Inst #2715 = SWP_MM + {3, OperandInfo95}, // Inst #2716 = SWR + {3, OperandInfo112}, // Inst #2717 = SWR64 + {3, OperandInfo95}, // Inst #2718 = SWRE + {3, OperandInfo95}, // Inst #2719 = SWRE_MM + {3, OperandInfo95}, // Inst #2720 = SWR_MM + {3, OperandInfo297}, // Inst #2721 = SWSP_MM + {3, OperandInfo297}, // Inst #2722 = SWSP_MMR6 + {3, OperandInfo298}, // Inst #2723 = SWXC1 + {3, OperandInfo298}, // Inst #2724 = SWXC1_MM + {3, OperandInfo95}, // Inst #2725 = SW_MM + {3, OperandInfo95}, // Inst #2726 = SW_MMR6 + {1, OperandInfo2}, // Inst #2727 = SYNC + {2, OperandInfo363}, // Inst #2728 = SYNCI + {2, OperandInfo363}, // Inst #2729 = SYNCI_MM + {2, OperandInfo363}, // Inst #2730 = SYNCI_MMR6 + {1, OperandInfo2}, // Inst #2731 = SYNC_MM + {1, OperandInfo2}, // Inst #2732 = SYNC_MMR6 + {1, OperandInfo2}, // Inst #2733 = SYSCALL + {1, OperandInfo2}, // Inst #2734 = SYSCALL_MM + {0, NULL}, // Inst #2735 = Save16 + {0, NULL}, // Inst #2736 = SaveX16 + {3, OperandInfo299}, // Inst #2737 = SbRxRyOffMemX16 + {2, OperandInfo364}, // Inst #2738 = SebRx16 + {2, OperandInfo364}, // Inst #2739 = SehRx16 + {3, OperandInfo299}, // Inst #2740 = ShRxRyOffMemX16 + {3, OperandInfo166}, // Inst #2741 = SllX16 + {3, OperandInfo185}, // Inst #2742 = SllvRxRy16 + {2, OperandInfo129}, // Inst #2743 = SltRxRy16 + {2, OperandInfo182}, // Inst #2744 = SltiRxImm16 + {2, OperandInfo182}, // Inst #2745 = SltiRxImmX16 + {2, OperandInfo182}, // Inst #2746 = SltiuRxImm16 + {2, OperandInfo182}, // Inst #2747 = SltiuRxImmX16 + {2, OperandInfo129}, // Inst #2748 = SltuRxRy16 + {3, OperandInfo166}, // Inst #2749 = SraX16 + {3, OperandInfo185}, // Inst #2750 = SravRxRy16 + {3, OperandInfo166}, // Inst #2751 = SrlX16 + {3, OperandInfo185}, // Inst #2752 = SrlvRxRy16 + {3, OperandInfo130}, // Inst #2753 = SubuRxRyRz16 + {3, OperandInfo299}, // Inst #2754 = SwRxRyOffMemX16 + {3, OperandInfo184}, // Inst #2755 = SwRxSpImmX16 + {3, OperandInfo72}, // Inst #2756 = TEQ + {2, OperandInfo113}, // Inst #2757 = TEQI + {2, OperandInfo113}, // Inst #2758 = TEQI_MM + {3, OperandInfo72}, // Inst #2759 = TEQ_MM + {3, OperandInfo72}, // Inst #2760 = TGE + {2, OperandInfo113}, // Inst #2761 = TGEI + {2, OperandInfo113}, // Inst #2762 = TGEIU + {2, OperandInfo113}, // Inst #2763 = TGEIU_MM + {2, OperandInfo113}, // Inst #2764 = TGEI_MM + {3, OperandInfo72}, // Inst #2765 = TGEU + {3, OperandInfo72}, // Inst #2766 = TGEU_MM + {3, OperandInfo72}, // Inst #2767 = TGE_MM + {0, NULL}, // Inst #2768 = TLBGINV + {0, NULL}, // Inst #2769 = TLBGINVF + {0, NULL}, // Inst #2770 = TLBGINVF_MM + {0, NULL}, // Inst #2771 = TLBGINV_MM + {0, NULL}, // Inst #2772 = TLBGP + {0, NULL}, // Inst #2773 = TLBGP_MM + {0, NULL}, // Inst #2774 = TLBGR + {0, NULL}, // Inst #2775 = TLBGR_MM + {0, NULL}, // Inst #2776 = TLBGWI + {0, NULL}, // Inst #2777 = TLBGWI_MM + {0, NULL}, // Inst #2778 = TLBGWR + {0, NULL}, // Inst #2779 = TLBGWR_MM + {0, NULL}, // Inst #2780 = TLBINV + {0, NULL}, // Inst #2781 = TLBINVF + {0, NULL}, // Inst #2782 = TLBINVF_MMR6 + {0, NULL}, // Inst #2783 = TLBINV_MMR6 + {0, NULL}, // Inst #2784 = TLBP + {0, NULL}, // Inst #2785 = TLBP_MM + {0, NULL}, // Inst #2786 = TLBR + {0, NULL}, // Inst #2787 = TLBR_MM + {0, NULL}, // Inst #2788 = TLBWI + {0, NULL}, // Inst #2789 = TLBWI_MM + {0, NULL}, // Inst #2790 = TLBWR + {0, NULL}, // Inst #2791 = TLBWR_MM + {3, OperandInfo72}, // Inst #2792 = TLT + {2, OperandInfo113}, // Inst #2793 = TLTI + {2, OperandInfo113}, // Inst #2794 = TLTIU_MM + {2, OperandInfo113}, // Inst #2795 = TLTI_MM + {3, OperandInfo72}, // Inst #2796 = TLTU + {3, OperandInfo72}, // Inst #2797 = TLTU_MM + {3, OperandInfo72}, // Inst #2798 = TLT_MM + {3, OperandInfo72}, // Inst #2799 = TNE + {2, OperandInfo113}, // Inst #2800 = TNEI + {2, OperandInfo113}, // Inst #2801 = TNEI_MM + {3, OperandInfo72}, // Inst #2802 = TNE_MM + {2, OperandInfo202}, // Inst #2803 = TRUNC_L_D64 + {2, OperandInfo202}, // Inst #2804 = TRUNC_L_D_MMR6 + {2, OperandInfo203}, // Inst #2805 = TRUNC_L_S + {2, OperandInfo203}, // Inst #2806 = TRUNC_L_S_MMR6 + {2, OperandInfo204}, // Inst #2807 = TRUNC_W_D32 + {2, OperandInfo205}, // Inst #2808 = TRUNC_W_D64 + {2, OperandInfo205}, // Inst #2809 = TRUNC_W_D_MMR6 + {2, OperandInfo204}, // Inst #2810 = TRUNC_W_MM + {2, OperandInfo206}, // Inst #2811 = TRUNC_W_S + {2, OperandInfo206}, // Inst #2812 = TRUNC_W_S_MM + {2, OperandInfo206}, // Inst #2813 = TRUNC_W_S_MMR6 + {2, OperandInfo113}, // Inst #2814 = TTLTIU + {2, OperandInfo44}, // Inst #2815 = UDIV + {2, OperandInfo44}, // Inst #2816 = UDIV_MM + {3, OperandInfo70}, // Inst #2817 = V3MULU + {3, OperandInfo70}, // Inst #2818 = VMM0 + {3, OperandInfo70}, // Inst #2819 = VMULU + {4, OperandInfo195}, // Inst #2820 = VSHF_B + {4, OperandInfo58}, // Inst #2821 = VSHF_D + {4, OperandInfo60}, // Inst #2822 = VSHF_H + {4, OperandInfo59}, // Inst #2823 = VSHF_W + {0, NULL}, // Inst #2824 = WAIT + {1, OperandInfo2}, // Inst #2825 = WAIT_MM + {1, OperandInfo2}, // Inst #2826 = WAIT_MMR6 + {2, OperandInfo113}, // Inst #2827 = WRDSP + {2, OperandInfo113}, // Inst #2828 = WRDSP_MM + {2, OperandInfo44}, // Inst #2829 = WRPGPR_MMR6 + {2, OperandInfo44}, // Inst #2830 = WSBH + {2, OperandInfo44}, // Inst #2831 = WSBH_MM + {2, OperandInfo44}, // Inst #2832 = WSBH_MMR6 + {3, OperandInfo71}, // Inst #2833 = XOR + {3, OperandInfo180}, // Inst #2834 = XOR16_MM + {3, OperandInfo180}, // Inst #2835 = XOR16_MMR6 + {3, OperandInfo70}, // Inst #2836 = XOR64 + {3, OperandInfo175}, // Inst #2837 = XORI_B + {3, OperandInfo72}, // Inst #2838 = XORI_MMR6 + {3, OperandInfo71}, // Inst #2839 = XOR_MM + {3, OperandInfo71}, // Inst #2840 = XOR_MMR6 + {3, OperandInfo173}, // Inst #2841 = XOR_V + {3, OperandInfo72}, // Inst #2842 = XORi + {3, OperandInfo69}, // Inst #2843 = XORi64 + {3, OperandInfo72}, // Inst #2844 = XORi_MM + {3, OperandInfo185}, // Inst #2845 = XorRxRxRy16 + {2, OperandInfo44}, // Inst #2846 = YIELD +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +extern const char MipsInstrNameData[] = { + /* 0 */ "G_FLOG10\0" + /* 9 */ "DMFC0\0" + /* 15 */ "DMFGC0\0" + /* 22 */ "MFHGC0\0" + /* 29 */ "MTHGC0\0" + /* 36 */ "DMTGC0\0" + /* 43 */ "MFTC0\0" + /* 49 */ "DMTC0\0" + /* 55 */ "MTTC0\0" + /* 61 */ "VMM0\0" + /* 66 */ "MTM0\0" + /* 71 */ "MTP0\0" + /* 76 */ "BBIT0\0" + /* 82 */ "LDC1\0" + /* 87 */ "SDC1\0" + /* 92 */ "CFC1\0" + /* 97 */ "DMFC1\0" + /* 103 */ "MFTHC1\0" + /* 110 */ "MTTHC1\0" + /* 117 */ "CTC1\0" + /* 122 */ "CFTC1\0" + /* 128 */ "MFTC1\0" + /* 134 */ "DMTC1\0" + /* 140 */ "CTTC1\0" + /* 146 */ "MTTC1\0" + /* 152 */ "LWC1\0" + /* 157 */ "SWC1\0" + /* 162 */ "LDXC1\0" + /* 168 */ "SDXC1\0" + /* 174 */ "LUXC1\0" + /* 180 */ "SUXC1\0" + /* 186 */ "LWXC1\0" + /* 192 */ "SWXC1\0" + /* 198 */ "MTM1\0" + /* 203 */ "SDC1_M1\0" + /* 211 */ "MTP1\0" + /* 216 */ "BBIT1\0" + /* 222 */ "BBIT032\0" + /* 230 */ "BBIT132\0" + /* 238 */ "DSRA32\0" + /* 245 */ "MFHC1_D32\0" + /* 255 */ "MTHC1_D32\0" + /* 265 */ "FSUB_D32\0" + /* 274 */ "NMSUB_D32\0" + /* 284 */ "FADD_D32\0" + /* 293 */ "NMADD_D32\0" + /* 303 */ "C_NGE_D32\0" + /* 313 */ "C_NGLE_D32\0" + /* 324 */ "C_OLE_D32\0" + /* 334 */ "C_ULE_D32\0" + /* 344 */ "C_LE_D32\0" + /* 353 */ "C_SF_D32\0" + /* 362 */ "MOVF_D32\0" + /* 371 */ "C_F_D32\0" + /* 379 */ "PseudoSELECTFP_F_D32\0" + /* 400 */ "FNEG_D32\0" + /* 409 */ "MOVN_I_D32\0" + /* 420 */ "MOVZ_I_D32\0" + /* 431 */ "C_NGL_D32\0" + /* 441 */ "FMUL_D32\0" + /* 450 */ "C_UN_D32\0" + /* 459 */ "RECIP_D32\0" + /* 469 */ "FCMP_D32\0" + /* 478 */ "C_SEQ_D32\0" + /* 488 */ "C_UEQ_D32\0" + /* 498 */ "C_EQ_D32\0" + /* 507 */ "FABS_D32\0" + /* 516 */ "CVT_S_D32\0" + /* 526 */ "PseudoSELECT_D32\0" + /* 543 */ "C_NGT_D32\0" + /* 553 */ "C_OLT_D32\0" + /* 563 */ "C_ULT_D32\0" + /* 573 */ "C_LT_D32\0" + /* 582 */ "FSQRT_D32\0" + /* 592 */ "RSQRT_D32\0" + /* 602 */ "MOVT_D32\0" + /* 611 */ "PseudoSELECTFP_T_D32\0" + /* 632 */ "FDIV_D32\0" + /* 641 */ "FMOV_D32\0" + /* 650 */ "PseudoTRUNC_W_D32\0" + /* 668 */ "ROUND_W_D32\0" + /* 680 */ "CEIL_W_D32\0" + /* 691 */ "FLOOR_W_D32\0" + /* 703 */ "CVT_W_D32\0" + /* 713 */ "BPOSGE32\0" + /* 722 */ "ATOMIC_LOAD_SUB_I32\0" + /* 742 */ "ATOMIC_LOAD_ADD_I32\0" + /* 762 */ "ATOMIC_LOAD_NAND_I32\0" + /* 783 */ "ATOMIC_LOAD_AND_I32\0" + /* 803 */ "ATOMIC_LOAD_UMIN_I32\0" + /* 824 */ "ATOMIC_LOAD_MIN_I32\0" + /* 844 */ "ATOMIC_SWAP_I32\0" + /* 860 */ "ATOMIC_CMP_SWAP_I32\0" + /* 880 */ "ATOMIC_LOAD_XOR_I32\0" + /* 900 */ "ATOMIC_LOAD_OR_I32\0" + /* 919 */ "ATOMIC_LOAD_UMAX_I32\0" + /* 940 */ "ATOMIC_LOAD_MAX_I32\0" + /* 960 */ "DSLL32\0" + /* 967 */ "DSRL32\0" + /* 974 */ "DROTR32\0" + /* 982 */ "CINS32\0" + /* 989 */ "EXTS32\0" + /* 996 */ "FCMP_S32\0" + /* 1005 */ "DSLL64_32\0" + /* 1015 */ "CINS64_32\0" + /* 1025 */ "DEXT64_32\0" + /* 1035 */ "LoadImmDoubleFGR_32\0" + /* 1055 */ "LoadAddrReg32\0" + /* 1069 */ "CINS_i32\0" + /* 1078 */ "LoadImm32\0" + /* 1088 */ "LoadAddrImm32\0" + /* 1102 */ "MIPSeh_return32\0" + /* 1118 */ "LwConstant32\0" + /* 1131 */ "LDC2\0" + /* 1136 */ "SDC2\0" + /* 1141 */ "DMFC2\0" + /* 1147 */ "DMTC2\0" + /* 1153 */ "LWC2\0" + /* 1158 */ "SWC2\0" + /* 1163 */ "G_FLOG2\0" + /* 1171 */ "MTM2\0" + /* 1176 */ "MTP2\0" + /* 1181 */ "G_FEXP2\0" + /* 1189 */ "SHRA_QB_MMR2\0" + /* 1202 */ "CMPGDU_LE_QB_MMR2\0" + /* 1220 */ "SUBUH_QB_MMR2\0" + /* 1234 */ "ADDUH_QB_MMR2\0" + /* 1248 */ "CMPGDU_EQ_QB_MMR2\0" + /* 1266 */ "SHRA_R_QB_MMR2\0" + /* 1281 */ "SUBUH_R_QB_MMR2\0" + /* 1297 */ "ADDUH_R_QB_MMR2\0" + /* 1313 */ "SHRAV_R_QB_MMR2\0" + /* 1329 */ "ABSQ_S_QB_MMR2\0" + /* 1344 */ "CMPGDU_LT_QB_MMR2\0" + /* 1362 */ "SHRAV_QB_MMR2\0" + /* 1376 */ "PREPEND_MMR2\0" + /* 1389 */ "APPEND_MMR2\0" + /* 1401 */ "PRECR_QB_PH_MMR2\0" + /* 1418 */ "SUBQH_PH_MMR2\0" + /* 1432 */ "ADDQH_PH_MMR2\0" + /* 1446 */ "SHRL_PH_MMR2\0" + /* 1459 */ "MUL_PH_MMR2\0" + /* 1471 */ "SUBQH_R_PH_MMR2\0" + /* 1487 */ "ADDQH_R_PH_MMR2\0" + /* 1503 */ "MUL_S_PH_MMR2\0" + /* 1517 */ "MULQ_S_PH_MMR2\0" + /* 1532 */ "SUBU_S_PH_MMR2\0" + /* 1547 */ "ADDU_S_PH_MMR2\0" + /* 1562 */ "SUBU_PH_MMR2\0" + /* 1575 */ "ADDU_PH_MMR2\0" + /* 1588 */ "SHRLV_PH_MMR2\0" + /* 1602 */ "DPA_W_PH_MMR2\0" + /* 1616 */ "MULSA_W_PH_MMR2\0" + /* 1632 */ "DPAQX_SA_W_PH_MMR2\0" + /* 1651 */ "DPSQX_SA_W_PH_MMR2\0" + /* 1670 */ "DPS_W_PH_MMR2\0" + /* 1684 */ "DPAQX_S_W_PH_MMR2\0" + /* 1702 */ "DPSQX_S_W_PH_MMR2\0" + /* 1720 */ "DPAX_W_PH_MMR2\0" + /* 1735 */ "DPSX_W_PH_MMR2\0" + /* 1750 */ "BALIGN_MMR2\0" + /* 1762 */ "PRECR_SRA_PH_W_MMR2\0" + /* 1782 */ "PRECR_SRA_R_PH_W_MMR2\0" + /* 1804 */ "SUBQH_W_MMR2\0" + /* 1817 */ "ADDQH_W_MMR2\0" + /* 1830 */ "SUBQH_R_W_MMR2\0" + /* 1845 */ "ADDQH_R_W_MMR2\0" + /* 1860 */ "MULQ_RS_W_MMR2\0" + /* 1875 */ "MULQ_S_W_MMR2\0" + /* 1889 */ "LDC3\0" + /* 1894 */ "SDC3\0" + /* 1899 */ "LWC3\0" + /* 1904 */ "SWC3\0" + /* 1909 */ "BPOSGE32C_MMR3\0" + /* 1924 */ "LDC164\0" + /* 1931 */ "SDC164\0" + /* 1938 */ "LDXC164\0" + /* 1946 */ "SDXC164\0" + /* 1954 */ "LUXC164\0" + /* 1962 */ "SUXC164\0" + /* 1970 */ "SEB64\0" + /* 1976 */ "TAILCALLREGHB64\0" + /* 1992 */ "JR_HB64\0" + /* 2000 */ "JALR_HB64\0" + /* 2010 */ "LB64\0" + /* 2015 */ "SB64\0" + /* 2020 */ "LOAD_ACC64\0" + /* 2031 */ "STORE_ACC64\0" + /* 2043 */ "BGEC64\0" + /* 2050 */ "BNEC64\0" + /* 2057 */ "JIC64\0" + /* 2063 */ "JIALC64\0" + /* 2071 */ "BEQC64\0" + /* 2078 */ "SC64\0" + /* 2083 */ "BLTC64\0" + /* 2090 */ "BGEUC64\0" + /* 2098 */ "BLTUC64\0" + /* 2106 */ "BGEZC64\0" + /* 2114 */ "BLEZC64\0" + /* 2122 */ "BNEZC64\0" + /* 2130 */ "BEQZC64\0" + /* 2138 */ "BGTZC64\0" + /* 2146 */ "BLTZC64\0" + /* 2154 */ "AND64\0" + /* 2160 */ "MFC1_D64\0" + /* 2169 */ "MFHC1_D64\0" + /* 2179 */ "MTHC1_D64\0" + /* 2189 */ "MTC1_D64\0" + /* 2198 */ "MOVN_I64_D64\0" + /* 2211 */ "MOVZ_I64_D64\0" + /* 2224 */ "FSUB_D64\0" + /* 2233 */ "NMSUB_D64\0" + /* 2243 */ "FADD_D64\0" + /* 2252 */ "NMADD_D64\0" + /* 2262 */ "C_NGE_D64\0" + /* 2272 */ "C_NGLE_D64\0" + /* 2283 */ "C_OLE_D64\0" + /* 2293 */ "C_ULE_D64\0" + /* 2303 */ "C_LE_D64\0" + /* 2312 */ "C_SF_D64\0" + /* 2321 */ "MOVF_D64\0" + /* 2330 */ "C_F_D64\0" + /* 2338 */ "PseudoSELECTFP_F_D64\0" + /* 2359 */ "FNEG_D64\0" + /* 2368 */ "MOVN_I_D64\0" + /* 2379 */ "MOVZ_I_D64\0" + /* 2390 */ "C_NGL_D64\0" + /* 2400 */ "FMUL_D64\0" + /* 2409 */ "TRUNC_L_D64\0" + /* 2421 */ "ROUND_L_D64\0" + /* 2433 */ "CEIL_L_D64\0" + /* 2444 */ "FLOOR_L_D64\0" + /* 2456 */ "CVT_L_D64\0" + /* 2466 */ "C_UN_D64\0" + /* 2475 */ "RECIP_D64\0" + /* 2485 */ "FCMP_D64\0" + /* 2494 */ "C_SEQ_D64\0" + /* 2504 */ "C_UEQ_D64\0" + /* 2514 */ "C_EQ_D64\0" + /* 2523 */ "FABS_D64\0" + /* 2532 */ "CVT_S_D64\0" + /* 2542 */ "PseudoSELECT_D64\0" + /* 2559 */ "C_NGT_D64\0" + /* 2569 */ "C_OLT_D64\0" + /* 2579 */ "C_ULT_D64\0" + /* 2589 */ "C_LT_D64\0" + /* 2598 */ "FSQRT_D64\0" + /* 2608 */ "RSQRT_D64\0" + /* 2618 */ "MOVT_D64\0" + /* 2627 */ "PseudoSELECTFP_T_D64\0" + /* 2648 */ "FDIV_D64\0" + /* 2657 */ "FMOV_D64\0" + /* 2666 */ "TRUNC_W_D64\0" + /* 2678 */ "ROUND_W_D64\0" + /* 2690 */ "CEIL_W_D64\0" + /* 2701 */ "FLOOR_W_D64\0" + /* 2713 */ "CVT_W_D64\0" + /* 2723 */ "BNE64\0" + /* 2729 */ "BuildPairF64\0" + /* 2742 */ "ExtractElementF64\0" + /* 2760 */ "TAILCALLREG64\0" + /* 2774 */ "SEH64\0" + /* 2780 */ "LH64\0" + /* 2785 */ "SH64\0" + /* 2790 */ "PseudoMFHI64\0" + /* 2803 */ "PseudoMTLOHI64\0" + /* 2818 */ "MTHI64\0" + /* 2825 */ "MOVN_I64_I64\0" + /* 2838 */ "MOVZ_I64_I64\0" + /* 2851 */ "ATOMIC_LOAD_SUB_I64\0" + /* 2871 */ "ATOMIC_LOAD_ADD_I64\0" + /* 2891 */ "ATOMIC_LOAD_NAND_I64\0" + /* 2912 */ "ATOMIC_LOAD_AND_I64\0" + /* 2932 */ "MOVF_I64\0" + /* 2941 */ "PseudoSELECTFP_F_I64\0" + /* 2962 */ "MOVN_I_I64\0" + /* 2973 */ "MOVZ_I_I64\0" + /* 2984 */ "ATOMIC_LOAD_UMIN_I64\0" + /* 3005 */ "ATOMIC_LOAD_MIN_I64\0" + /* 3025 */ "ATOMIC_SWAP_I64\0" + /* 3041 */ "ATOMIC_CMP_SWAP_I64\0" + /* 3061 */ "ATOMIC_LOAD_XOR_I64\0" + /* 3081 */ "ATOMIC_LOAD_OR_I64\0" + /* 3100 */ "PseudoD_SELECT_I64\0" + /* 3119 */ "PseudoSELECT_I64\0" + /* 3136 */ "MOVT_I64\0" + /* 3145 */ "PseudoSELECTFP_T_I64\0" + /* 3166 */ "ATOMIC_LOAD_UMAX_I64\0" + /* 3187 */ "ATOMIC_LOAD_MAX_I64\0" + /* 3207 */ "LL64\0" + /* 3212 */ "CVT_S_PL64\0" + /* 3223 */ "LWL64\0" + /* 3229 */ "SWL64\0" + /* 3235 */ "PseudoMFLO64\0" + /* 3248 */ "MTLO64\0" + /* 3255 */ "BEQ64\0" + /* 3261 */ "JR64\0" + /* 3266 */ "JALR64\0" + /* 3273 */ "NOR64\0" + /* 3279 */ "XOR64\0" + /* 3285 */ "RDHWR64\0" + /* 3293 */ "LWR64\0" + /* 3299 */ "SWR64\0" + /* 3305 */ "FSUB_PS64\0" + /* 3315 */ "FADD_PS64\0" + /* 3325 */ "PLL_PS64\0" + /* 3334 */ "FMUL_PS64\0" + /* 3344 */ "PUL_PS64\0" + /* 3353 */ "ADDR_PS64\0" + /* 3363 */ "MULR_PS64\0" + /* 3373 */ "PLU_PS64\0" + /* 3382 */ "PUU_PS64\0" + /* 3391 */ "CVT_PW_PS64\0" + /* 3403 */ "CVT_PS_S64\0" + /* 3414 */ "SLT64\0" + /* 3420 */ "CVT_S_PU64\0" + /* 3431 */ "LW64\0" + /* 3436 */ "CVT_PS_PW64\0" + /* 3448 */ "SW64\0" + /* 3453 */ "BGEZ64\0" + /* 3460 */ "BLEZ64\0" + /* 3467 */ "SELNEZ64\0" + /* 3476 */ "SELEQZ64\0" + /* 3485 */ "BGTZ64\0" + /* 3492 */ "BLTZ64\0" + /* 3499 */ "BuildPairF64_64\0" + /* 3515 */ "ExtractElementF64_64\0" + /* 3536 */ "SLL64_64\0" + /* 3545 */ "LONG_BRANCH_LUi2Op_64\0" + /* 3567 */ "LoadAddrReg64\0" + /* 3581 */ "PseudoIndirectHazardBranch64\0" + /* 3610 */ "PseudoIndirectBranch64\0" + /* 3633 */ "ANDi64\0" + /* 3640 */ "XORi64\0" + /* 3647 */ "SLTi64\0" + /* 3654 */ "LUi64\0" + /* 3660 */ "SGEImm64\0" + /* 3669 */ "SLEImm64\0" + /* 3678 */ "NORImm64\0" + /* 3687 */ "SGTImm64\0" + /* 3696 */ "SLTImm64\0" + /* 3705 */ "SGEUImm64\0" + /* 3715 */ "SLEUImm64\0" + /* 3725 */ "SGTUImm64\0" + /* 3735 */ "SLTUImm64\0" + /* 3745 */ "LoadImm64\0" + /* 3755 */ "LoadAddrImm64\0" + /* 3769 */ "PseudoReturn64\0" + /* 3784 */ "MIPSeh_return64\0" + /* 3800 */ "LBu64\0" + /* 3806 */ "LHu64\0" + /* 3812 */ "SLTu64\0" + /* 3819 */ "LEA_ADDiu64\0" + /* 3831 */ "SLTiu64\0" + /* 3839 */ "MoveR3216\0" + /* 3849 */ "RetRA16\0" + /* 3857 */ "JalB16\0" + /* 3864 */ "LD_F16\0" + /* 3871 */ "ST_F16\0" + /* 3878 */ "ATOMIC_LOAD_SUB_I16\0" + /* 3898 */ "ATOMIC_LOAD_ADD_I16\0" + /* 3918 */ "ATOMIC_LOAD_NAND_I16\0" + /* 3939 */ "ATOMIC_LOAD_AND_I16\0" + /* 3959 */ "ATOMIC_LOAD_UMIN_I16\0" + /* 3980 */ "ATOMIC_LOAD_MIN_I16\0" + /* 4000 */ "ATOMIC_SWAP_I16\0" + /* 4016 */ "ATOMIC_CMP_SWAP_I16\0" + /* 4036 */ "ATOMIC_LOAD_XOR_I16\0" + /* 4056 */ "ATOMIC_LOAD_OR_I16\0" + /* 4075 */ "ATOMIC_LOAD_UMAX_I16\0" + /* 4096 */ "ATOMIC_LOAD_MAX_I16\0" + /* 4116 */ "Move32R16\0" + /* 4126 */ "SraX16\0" + /* 4133 */ "RestoreX16\0" + /* 4144 */ "SaveX16\0" + /* 4152 */ "BtnezT8CmpiX16\0" + /* 4167 */ "BteqzT8CmpiX16\0" + /* 4182 */ "BtnezT8SltiX16\0" + /* 4197 */ "BteqzT8SltiX16\0" + /* 4212 */ "SllX16\0" + /* 4219 */ "SrlX16\0" + /* 4226 */ "LbRxRyOffMemX16\0" + /* 4242 */ "SbRxRyOffMemX16\0" + /* 4258 */ "LhRxRyOffMemX16\0" + /* 4274 */ "ShRxRyOffMemX16\0" + /* 4290 */ "LbuRxRyOffMemX16\0" + /* 4307 */ "LhuRxRyOffMemX16\0" + /* 4324 */ "AddiuRxRyOffMemX16\0" + /* 4343 */ "LwRxRyOffMemX16\0" + /* 4359 */ "SwRxRyOffMemX16\0" + /* 4375 */ "AddiuRxPcImmX16\0" + /* 4391 */ "AddiuSpImmX16\0" + /* 4405 */ "LwRxSpImmX16\0" + /* 4418 */ "SwRxSpImmX16\0" + /* 4431 */ "SltiCCRxImmX16\0" + /* 4446 */ "SltiuCCRxImmX16\0" + /* 4462 */ "LiRxImmX16\0" + /* 4473 */ "CmpiRxImmX16\0" + /* 4486 */ "SltiRxImmX16\0" + /* 4499 */ "AddiuRxImmX16\0" + /* 4513 */ "SltiuRxImmX16\0" + /* 4527 */ "AddiuRxRxImmX16\0" + /* 4543 */ "BnezRxImmX16\0" + /* 4556 */ "BeqzRxImmX16\0" + /* 4569 */ "BimmX16\0" + /* 4577 */ "LiRxImmAlignX16\0" + /* 4593 */ "LwRxPcTcpX16\0" + /* 4606 */ "BtnezT8CmpX16\0" + /* 4620 */ "BteqzT8CmpX16\0" + /* 4634 */ "BtnezT8SltX16\0" + /* 4648 */ "BteqzT8SltX16\0" + /* 4662 */ "BtnezT8SltiuX16\0" + /* 4678 */ "BteqzT8SltiuX16\0" + /* 4694 */ "BtnezT8SltuX16\0" + /* 4709 */ "BteqzT8SltuX16\0" + /* 4724 */ "BtnezX16\0" + /* 4733 */ "BteqzX16\0" + /* 4742 */ "JrcRa16\0" + /* 4750 */ "JrRa16\0" + /* 4757 */ "Restore16\0" + /* 4767 */ "GotPrologue16\0" + /* 4781 */ "Save16\0" + /* 4788 */ "JumpLinkReg16\0" + /* 4802 */ "Mfhi16\0" + /* 4809 */ "Break16\0" + /* 4817 */ "Jal16\0" + /* 4823 */ "AddiuSpImm16\0" + /* 4836 */ "LiRxImm16\0" + /* 4846 */ "CmpiRxImm16\0" + /* 4858 */ "SltiRxImm16\0" + /* 4870 */ "SltiuRxImm16\0" + /* 4883 */ "AddiuRxRxImm16\0" + /* 4898 */ "BnezRxImm16\0" + /* 4910 */ "BeqzRxImm16\0" + /* 4922 */ "Bimm16\0" + /* 4929 */ "Mflo16\0" + /* 4936 */ "LwRxPcTcp16\0" + /* 4948 */ "SebRx16\0" + /* 4956 */ "JrcRx16\0" + /* 4964 */ "SehRx16\0" + /* 4972 */ "SltCCRxRy16\0" + /* 4984 */ "SltuCCRxRy16\0" + /* 4997 */ "NegRxRy16\0" + /* 5007 */ "CmpRxRy16\0" + /* 5017 */ "SltRxRy16\0" + /* 5027 */ "MultRxRy16\0" + /* 5038 */ "NotRxRy16\0" + /* 5048 */ "SltuRxRy16\0" + /* 5059 */ "MultuRxRy16\0" + /* 5071 */ "DivuRxRy16\0" + /* 5082 */ "SravRxRy16\0" + /* 5093 */ "DivRxRy16\0" + /* 5103 */ "SllvRxRy16\0" + /* 5114 */ "SrlvRxRy16\0" + /* 5125 */ "AndRxRxRy16\0" + /* 5137 */ "OrRxRxRy16\0" + /* 5148 */ "XorRxRxRy16\0" + /* 5160 */ "MultRxRyRz16\0" + /* 5173 */ "SubuRxRyRz16\0" + /* 5186 */ "AdduRxRyRz16\0" + /* 5199 */ "SltuRxRyRz16\0" + /* 5212 */ "MultuRxRyRz16\0" + /* 5226 */ "Btnez16\0" + /* 5234 */ "Bteqz16\0" + /* 5242 */ "PseudoIndrectHazardBranch64R6\0" + /* 5272 */ "PseudoIndirectBranch64R6\0" + /* 5297 */ "MFC0_MMR6\0" + /* 5307 */ "MFHC0_MMR6\0" + /* 5318 */ "MTHC0_MMR6\0" + /* 5329 */ "MTC0_MMR6\0" + /* 5339 */ "MFC1_MMR6\0" + /* 5349 */ "MTC1_MMR6\0" + /* 5359 */ "LDC2_MMR6\0" + /* 5369 */ "SDC2_MMR6\0" + /* 5379 */ "MFC2_MMR6\0" + /* 5389 */ "MFHC2_MMR6\0" + /* 5400 */ "MTHC2_MMR6\0" + /* 5411 */ "MTC2_MMR6\0" + /* 5421 */ "LWC2_MMR6\0" + /* 5431 */ "SWC2_MMR6\0" + /* 5441 */ "LDC1_D64_MMR6\0" + /* 5455 */ "SDC1_D64_MMR6\0" + /* 5469 */ "SB16_MMR6\0" + /* 5479 */ "BC16_MMR6\0" + /* 5489 */ "JRC16_MMR6\0" + /* 5500 */ "JALRC16_MMR6\0" + /* 5513 */ "BNEZC16_MMR6\0" + /* 5526 */ "BEQZC16_MMR6\0" + /* 5539 */ "AND16_MMR6\0" + /* 5550 */ "MOVE16_MMR6\0" + /* 5562 */ "SH16_MMR6\0" + /* 5572 */ "ANDI16_MMR6\0" + /* 5584 */ "LI16_MMR6\0" + /* 5594 */ "BREAK16_MMR6\0" + /* 5607 */ "SLL16_MMR6\0" + /* 5618 */ "SRL16_MMR6\0" + /* 5629 */ "LWM16_MMR6\0" + /* 5640 */ "SWM16_MMR6\0" + /* 5651 */ "SDBBP16_MMR6\0" + /* 5664 */ "XOR16_MMR6\0" + /* 5675 */ "NOT16_MMR6\0" + /* 5686 */ "SUBU16_MMR6\0" + /* 5698 */ "ADDU16_MMR6\0" + /* 5710 */ "SW16_MMR6\0" + /* 5720 */ "LSA_MMR6\0" + /* 5729 */ "EHB_MMR6\0" + /* 5738 */ "JALRC_HB_MMR6\0" + /* 5752 */ "LB_MMR6\0" + /* 5760 */ "SB_MMR6\0" + /* 5768 */ "SUB_MMR6\0" + /* 5777 */ "BC_MMR6\0" + /* 5785 */ "BGEC_MMR6\0" + /* 5795 */ "BNEC_MMR6\0" + /* 5805 */ "JIC_MMR6\0" + /* 5814 */ "BALC_MMR6\0" + /* 5824 */ "JIALC_MMR6\0" + /* 5835 */ "BGEZALC_MMR6\0" + /* 5848 */ "BLEZALC_MMR6\0" + /* 5861 */ "BNEZALC_MMR6\0" + /* 5874 */ "BEQZALC_MMR6\0" + /* 5887 */ "BGTZALC_MMR6\0" + /* 5900 */ "BLTZALC_MMR6\0" + /* 5913 */ "ERETNC_MMR6\0" + /* 5925 */ "SYNC_MMR6\0" + /* 5935 */ "AUIPC_MMR6\0" + /* 5946 */ "ALUIPC_MMR6\0" + /* 5958 */ "ADDIUPC_MMR6\0" + /* 5971 */ "LWPC_MMR6\0" + /* 5981 */ "BEQC_MMR6\0" + /* 5991 */ "JALRC_MMR6\0" + /* 6002 */ "SC_MMR6\0" + /* 6010 */ "BLTC_MMR6\0" + /* 6020 */ "BGEUC_MMR6\0" + /* 6031 */ "BLTUC_MMR6\0" + /* 6042 */ "BNVC_MMR6\0" + /* 6052 */ "BOVC_MMR6\0" + /* 6062 */ "BGEZC_MMR6\0" + /* 6073 */ "BLEZC_MMR6\0" + /* 6084 */ "BC1NEZC_MMR6\0" + /* 6097 */ "BC2NEZC_MMR6\0" + /* 6110 */ "BNEZC_MMR6\0" + /* 6121 */ "BC1EQZC_MMR6\0" + /* 6134 */ "BC2EQZC_MMR6\0" + /* 6147 */ "BEQZC_MMR6\0" + /* 6158 */ "BGTZC_MMR6\0" + /* 6169 */ "BLTZC_MMR6\0" + /* 6180 */ "ADD_MMR6\0" + /* 6189 */ "AND_MMR6\0" + /* 6198 */ "MOD_MMR6\0" + /* 6207 */ "MINA_D_MMR6\0" + /* 6219 */ "MAXA_D_MMR6\0" + /* 6231 */ "CMP_SLE_D_MMR6\0" + /* 6246 */ "CMP_SULE_D_MMR6\0" + /* 6262 */ "CMP_ULE_D_MMR6\0" + /* 6277 */ "CMP_LE_D_MMR6\0" + /* 6291 */ "CMP_SAF_D_MMR6\0" + /* 6306 */ "CMP_AF_D_MMR6\0" + /* 6320 */ "MSUBF_D_MMR6\0" + /* 6333 */ "MADDF_D_MMR6\0" + /* 6346 */ "SEL_D_MMR6\0" + /* 6357 */ "TRUNC_L_D_MMR6\0" + /* 6372 */ "ROUND_L_D_MMR6\0" + /* 6387 */ "CEIL_L_D_MMR6\0" + /* 6401 */ "FLOOR_L_D_MMR6\0" + /* 6416 */ "CVT_L_D_MMR6\0" + /* 6429 */ "MIN_D_MMR6\0" + /* 6440 */ "CMP_SUN_D_MMR6\0" + /* 6455 */ "CMP_UN_D_MMR6\0" + /* 6469 */ "CMP_SEQ_D_MMR6\0" + /* 6484 */ "CMP_SUEQ_D_MMR6\0" + /* 6500 */ "CMP_UEQ_D_MMR6\0" + /* 6515 */ "CMP_EQ_D_MMR6\0" + /* 6529 */ "CLASS_D_MMR6\0" + /* 6542 */ "CMP_SLT_D_MMR6\0" + /* 6557 */ "CMP_SULT_D_MMR6\0" + /* 6573 */ "CMP_ULT_D_MMR6\0" + /* 6588 */ "CMP_LT_D_MMR6\0" + /* 6602 */ "RINT_D_MMR6\0" + /* 6614 */ "FMOV_D_MMR6\0" + /* 6626 */ "TRUNC_W_D_MMR6\0" + /* 6641 */ "ROUND_W_D_MMR6\0" + /* 6656 */ "CEIL_W_D_MMR6\0" + /* 6670 */ "FLOOR_W_D_MMR6\0" + /* 6685 */ "MAX_D_MMR6\0" + /* 6696 */ "SELNEZ_D_MMR6\0" + /* 6710 */ "SELEQZ_D_MMR6\0" + /* 6724 */ "CACHE_MMR6\0" + /* 6735 */ "SIGRIE_MMR6\0" + /* 6747 */ "PAUSE_MMR6\0" + /* 6758 */ "PREF_MMR6\0" + /* 6768 */ "TLBINVF_MMR6\0" + /* 6781 */ "TAILCALLREG_MMR6\0" + /* 6798 */ "WSBH_MMR6\0" + /* 6808 */ "SH_MMR6\0" + /* 6816 */ "MUH_MMR6\0" + /* 6825 */ "SYNCI_MMR6\0" + /* 6836 */ "ANDI_MMR6\0" + /* 6846 */ "EI_MMR6\0" + /* 6854 */ "XORI_MMR6\0" + /* 6864 */ "AUI_MMR6\0" + /* 6873 */ "LUI_MMR6\0" + /* 6882 */ "GINVI_MMR6\0" + /* 6893 */ "BREAK_MMR6\0" + /* 6904 */ "JAL_MMR6\0" + /* 6913 */ "TAILCALL_MMR6\0" + /* 6927 */ "SLL_MMR6\0" + /* 6936 */ "MUL_MMR6\0" + /* 6945 */ "CVT_D_L_MMR6\0" + /* 6958 */ "CVT_S_L_MMR6\0" + /* 6971 */ "ALIGN_MMR6\0" + /* 6982 */ "CLO_MMR6\0" + /* 6991 */ "BITSWAP_MMR6\0" + /* 7004 */ "SDBBP_MMR6\0" + /* 7015 */ "MOVEP_MMR6\0" + /* 7026 */ "SSNOP_MMR6\0" + /* 7037 */ "JRCADDIUSP_MMR6\0" + /* 7053 */ "SWSP_MMR6\0" + /* 7063 */ "DVP_MMR6\0" + /* 7072 */ "EVP_MMR6\0" + /* 7081 */ "NOR_MMR6\0" + /* 7090 */ "XOR_MMR6\0" + /* 7099 */ "RDPGPR_MMR6\0" + /* 7111 */ "WRPGPR_MMR6\0" + /* 7123 */ "RDHWR_MMR6\0" + /* 7134 */ "INS_MMR6\0" + /* 7143 */ "MINA_S_MMR6\0" + /* 7155 */ "MAXA_S_MMR6\0" + /* 7167 */ "FSUB_S_MMR6\0" + /* 7179 */ "FADD_S_MMR6\0" + /* 7191 */ "CMP_SLE_S_MMR6\0" + /* 7206 */ "CMP_SULE_S_MMR6\0" + /* 7222 */ "CMP_ULE_S_MMR6\0" + /* 7237 */ "CMP_LE_S_MMR6\0" + /* 7251 */ "CMP_SAF_S_MMR6\0" + /* 7266 */ "CMP_AF_S_MMR6\0" + /* 7280 */ "MSUBF_S_MMR6\0" + /* 7293 */ "MADDF_S_MMR6\0" + /* 7306 */ "FNEG_S_MMR6\0" + /* 7318 */ "SEL_S_MMR6\0" + /* 7329 */ "FMUL_S_MMR6\0" + /* 7341 */ "TRUNC_L_S_MMR6\0" + /* 7356 */ "ROUND_L_S_MMR6\0" + /* 7371 */ "CEIL_L_S_MMR6\0" + /* 7385 */ "FLOOR_L_S_MMR6\0" + /* 7400 */ "CVT_L_S_MMR6\0" + /* 7413 */ "MIN_S_MMR6\0" + /* 7424 */ "CMP_SUN_S_MMR6\0" + /* 7439 */ "CMP_UN_S_MMR6\0" + /* 7453 */ "CMP_SEQ_S_MMR6\0" + /* 7468 */ "CMP_SUEQ_S_MMR6\0" + /* 7484 */ "CMP_UEQ_S_MMR6\0" + /* 7499 */ "CMP_EQ_S_MMR6\0" + /* 7513 */ "CLASS_S_MMR6\0" + /* 7526 */ "CMP_SLT_S_MMR6\0" + /* 7541 */ "CMP_SULT_S_MMR6\0" + /* 7557 */ "CMP_ULT_S_MMR6\0" + /* 7572 */ "CMP_LT_S_MMR6\0" + /* 7586 */ "RINT_S_MMR6\0" + /* 7598 */ "FDIV_S_MMR6\0" + /* 7610 */ "FMOV_S_MMR6\0" + /* 7622 */ "TRUNC_W_S_MMR6\0" + /* 7637 */ "ROUND_W_S_MMR6\0" + /* 7652 */ "CEIL_W_S_MMR6\0" + /* 7666 */ "FLOOR_W_S_MMR6\0" + /* 7681 */ "CVT_W_S_MMR6\0" + /* 7694 */ "MAX_S_MMR6\0" + /* 7705 */ "SELNEZ_S_MMR6\0" + /* 7719 */ "SELEQZ_S_MMR6\0" + /* 7733 */ "DERET_MMR6\0" + /* 7744 */ "WAIT_MMR6\0" + /* 7754 */ "GINVT_MMR6\0" + /* 7765 */ "EXT_MMR6\0" + /* 7774 */ "LBU_MMR6\0" + /* 7783 */ "SUBU_MMR6\0" + /* 7793 */ "ADDU_MMR6\0" + /* 7803 */ "MODU_MMR6\0" + /* 7813 */ "MUHU_MMR6\0" + /* 7823 */ "ADDIU_MMR6\0" + /* 7834 */ "MULU_MMR6\0" + /* 7844 */ "DIVU_MMR6\0" + /* 7854 */ "DIV_MMR6\0" + /* 7863 */ "TLBINV_MMR6\0" + /* 7875 */ "LW_MMR6\0" + /* 7883 */ "SW_MMR6\0" + /* 7891 */ "CVT_S_W_MMR6\0" + /* 7904 */ "SELNEZ_MMR6\0" + /* 7916 */ "CLZ_MMR6\0" + /* 7925 */ "SELEQZ_MMR6\0" + /* 7937 */ "PseudoIndirectBranch_MMR6\0" + /* 7963 */ "LDC2_R6\0" + /* 7971 */ "SDC2_R6\0" + /* 7979 */ "LWC2_R6\0" + /* 7987 */ "SWC2_R6\0" + /* 7995 */ "JR_HB64_R6\0" + /* 8006 */ "SC64_R6\0" + /* 8014 */ "LL64_R6\0" + /* 8022 */ "DLSA_R6\0" + /* 8030 */ "JR_HB_R6\0" + /* 8039 */ "SC_R6\0" + /* 8045 */ "SCD_R6\0" + /* 8052 */ "LLD_R6\0" + /* 8059 */ "CACHE_R6\0" + /* 8068 */ "PREF_R6\0" + /* 8076 */ "LL_R6\0" + /* 8082 */ "DMUL_R6\0" + /* 8090 */ "DCLO_R6\0" + /* 8098 */ "SDBBP_R6\0" + /* 8107 */ "DCLZ_R6\0" + /* 8115 */ "PseudoIndrectHazardBranchR6\0" + /* 8143 */ "PseudoIndirectBranchR6\0" + /* 8166 */ "LOAD_ACC128\0" + /* 8178 */ "STORE_ACC128\0" + /* 8191 */ "ATOMIC_LOAD_SUB_I8\0" + /* 8210 */ "ATOMIC_LOAD_ADD_I8\0" + /* 8229 */ "ATOMIC_LOAD_NAND_I8\0" + /* 8249 */ "ATOMIC_LOAD_AND_I8\0" + /* 8268 */ "ATOMIC_LOAD_UMIN_I8\0" + /* 8288 */ "ATOMIC_LOAD_MIN_I8\0" + /* 8307 */ "ATOMIC_SWAP_I8\0" + /* 8322 */ "ATOMIC_CMP_SWAP_I8\0" + /* 8341 */ "ATOMIC_LOAD_XOR_I8\0" + /* 8360 */ "ATOMIC_LOAD_OR_I8\0" + /* 8378 */ "ATOMIC_LOAD_UMAX_I8\0" + /* 8398 */ "ATOMIC_LOAD_MAX_I8\0" + /* 8417 */ "SAA\0" + /* 8421 */ "PRECEU_PH_QBLA\0" + /* 8436 */ "PRECEQU_PH_QBLA\0" + /* 8452 */ "G_FMA\0" + /* 8458 */ "G_STRICT_FMA\0" + /* 8471 */ "PRECEU_PH_QBRA\0" + /* 8486 */ "PRECEQU_PH_QBRA\0" + /* 8502 */ "DSRA\0" + /* 8507 */ "ATOMIC_LOAD_SUB_I32_POSTRA\0" + /* 8534 */ "ATOMIC_LOAD_ADD_I32_POSTRA\0" + /* 8561 */ "ATOMIC_LOAD_NAND_I32_POSTRA\0" + /* 8589 */ "ATOMIC_LOAD_AND_I32_POSTRA\0" + /* 8616 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\0" + /* 8644 */ "ATOMIC_LOAD_MIN_I32_POSTRA\0" + /* 8671 */ "ATOMIC_SWAP_I32_POSTRA\0" + /* 8694 */ "ATOMIC_CMP_SWAP_I32_POSTRA\0" + /* 8721 */ "ATOMIC_LOAD_XOR_I32_POSTRA\0" + /* 8748 */ "ATOMIC_LOAD_OR_I32_POSTRA\0" + /* 8774 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\0" + /* 8802 */ "ATOMIC_LOAD_MAX_I32_POSTRA\0" + /* 8829 */ "ATOMIC_LOAD_SUB_I64_POSTRA\0" + /* 8856 */ "ATOMIC_LOAD_ADD_I64_POSTRA\0" + /* 8883 */ "ATOMIC_LOAD_NAND_I64_POSTRA\0" + /* 8911 */ "ATOMIC_LOAD_AND_I64_POSTRA\0" + /* 8938 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\0" + /* 8966 */ "ATOMIC_LOAD_MIN_I64_POSTRA\0" + /* 8993 */ "ATOMIC_SWAP_I64_POSTRA\0" + /* 9016 */ "ATOMIC_CMP_SWAP_I64_POSTRA\0" + /* 9043 */ "ATOMIC_LOAD_XOR_I64_POSTRA\0" + /* 9070 */ "ATOMIC_LOAD_OR_I64_POSTRA\0" + /* 9096 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\0" + /* 9124 */ "ATOMIC_LOAD_MAX_I64_POSTRA\0" + /* 9151 */ "ATOMIC_LOAD_SUB_I16_POSTRA\0" + /* 9178 */ "ATOMIC_LOAD_ADD_I16_POSTRA\0" + /* 9205 */ "ATOMIC_LOAD_NAND_I16_POSTRA\0" + /* 9233 */ "ATOMIC_LOAD_AND_I16_POSTRA\0" + /* 9260 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\0" + /* 9288 */ "ATOMIC_LOAD_MIN_I16_POSTRA\0" + /* 9315 */ "ATOMIC_SWAP_I16_POSTRA\0" + /* 9338 */ "ATOMIC_CMP_SWAP_I16_POSTRA\0" + /* 9365 */ "ATOMIC_LOAD_XOR_I16_POSTRA\0" + /* 9392 */ "ATOMIC_LOAD_OR_I16_POSTRA\0" + /* 9418 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\0" + /* 9446 */ "ATOMIC_LOAD_MAX_I16_POSTRA\0" + /* 9473 */ "ATOMIC_LOAD_SUB_I8_POSTRA\0" + /* 9499 */ "ATOMIC_LOAD_ADD_I8_POSTRA\0" + /* 9525 */ "ATOMIC_LOAD_NAND_I8_POSTRA\0" + /* 9552 */ "ATOMIC_LOAD_AND_I8_POSTRA\0" + /* 9578 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\0" + /* 9605 */ "ATOMIC_LOAD_MIN_I8_POSTRA\0" + /* 9631 */ "ATOMIC_SWAP_I8_POSTRA\0" + /* 9653 */ "ATOMIC_CMP_SWAP_I8_POSTRA\0" + /* 9679 */ "ATOMIC_LOAD_XOR_I8_POSTRA\0" + /* 9705 */ "ATOMIC_LOAD_OR_I8_POSTRA\0" + /* 9730 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\0" + /* 9757 */ "ATOMIC_LOAD_MAX_I8_POSTRA\0" + /* 9783 */ "RetRA\0" + /* 9789 */ "DLSA\0" + /* 9794 */ "CFCMSA\0" + /* 9801 */ "CTCMSA\0" + /* 9808 */ "CRC32B\0" + /* 9815 */ "CRC32CB\0" + /* 9823 */ "SEB\0" + /* 9827 */ "EHB\0" + /* 9831 */ "TAILCALLREGHB\0" + /* 9845 */ "JR_HB\0" + /* 9851 */ "JALR_HB\0" + /* 9859 */ "LB\0" + /* 9862 */ "SHRA_QB\0" + /* 9870 */ "CMPGDU_LE_QB\0" + /* 9883 */ "CMPGU_LE_QB\0" + /* 9895 */ "PseudoCMPU_LE_QB\0" + /* 9912 */ "SUBUH_QB\0" + /* 9921 */ "ADDUH_QB\0" + /* 9930 */ "PseudoPICK_QB\0" + /* 9944 */ "SHLL_QB\0" + /* 9952 */ "REPL_QB\0" + /* 9960 */ "SHRL_QB\0" + /* 9968 */ "CMPGDU_EQ_QB\0" + /* 9981 */ "CMPGU_EQ_QB\0" + /* 9993 */ "PseudoCMPU_EQ_QB\0" + /* 10010 */ "SHRA_R_QB\0" + /* 10020 */ "SUBUH_R_QB\0" + /* 10031 */ "ADDUH_R_QB\0" + /* 10042 */ "SHRAV_R_QB\0" + /* 10053 */ "ABSQ_S_QB\0" + /* 10063 */ "SUBU_S_QB\0" + /* 10073 */ "ADDU_S_QB\0" + /* 10083 */ "CMPGDU_LT_QB\0" + /* 10096 */ "CMPGU_LT_QB\0" + /* 10108 */ "PseudoCMPU_LT_QB\0" + /* 10125 */ "SUBU_QB\0" + /* 10133 */ "ADDU_QB\0" + /* 10141 */ "SHRAV_QB\0" + /* 10150 */ "SHLLV_QB\0" + /* 10159 */ "REPLV_QB\0" + /* 10168 */ "SHRLV_QB\0" + /* 10177 */ "RADDU_W_QB\0" + /* 10188 */ "SB\0" + /* 10191 */ "MODSUB\0" + /* 10198 */ "G_FSUB\0" + /* 10205 */ "G_STRICT_FSUB\0" + /* 10219 */ "G_ATOMICRMW_FSUB\0" + /* 10236 */ "PseudoMSUB\0" + /* 10247 */ "G_SUB\0" + /* 10253 */ "G_ATOMICRMW_SUB\0" + /* 10269 */ "SRA_B\0" + /* 10275 */ "ADD_A_B\0" + /* 10283 */ "MIN_A_B\0" + /* 10291 */ "ADDS_A_B\0" + /* 10300 */ "MAX_A_B\0" + /* 10308 */ "NLOC_B\0" + /* 10315 */ "NLZC_B\0" + /* 10322 */ "SLD_B\0" + /* 10328 */ "PCKOD_B\0" + /* 10336 */ "ILVOD_B\0" + /* 10344 */ "INSVE_B\0" + /* 10352 */ "VSHF_B\0" + /* 10359 */ "BNEG_B\0" + /* 10366 */ "SRAI_B\0" + /* 10373 */ "SLDI_B\0" + /* 10380 */ "ANDI_B\0" + /* 10387 */ "BNEGI_B\0" + /* 10395 */ "BSELI_B\0" + /* 10403 */ "SLLI_B\0" + /* 10410 */ "SRLI_B\0" + /* 10417 */ "BINSLI_B\0" + /* 10426 */ "CEQI_B\0" + /* 10433 */ "SRARI_B\0" + /* 10441 */ "BCLRI_B\0" + /* 10449 */ "SRLRI_B\0" + /* 10457 */ "NORI_B\0" + /* 10464 */ "XORI_B\0" + /* 10471 */ "BINSRI_B\0" + /* 10480 */ "SPLATI_B\0" + /* 10489 */ "BSETI_B\0" + /* 10497 */ "SUBVI_B\0" + /* 10505 */ "ADDVI_B\0" + /* 10513 */ "BMZI_B\0" + /* 10520 */ "BMNZI_B\0" + /* 10528 */ "FILL_B\0" + /* 10535 */ "SLL_B\0" + /* 10541 */ "SRL_B\0" + /* 10547 */ "BINSL_B\0" + /* 10555 */ "ILVL_B\0" + /* 10562 */ "CEQ_B\0" + /* 10568 */ "SRAR_B\0" + /* 10575 */ "BCLR_B\0" + /* 10582 */ "SRLR_B\0" + /* 10589 */ "BINSR_B\0" + /* 10597 */ "ILVR_B\0" + /* 10604 */ "ASUB_S_B\0" + /* 10613 */ "MOD_S_B\0" + /* 10621 */ "CLE_S_B\0" + /* 10629 */ "AVE_S_B\0" + /* 10637 */ "CLEI_S_B\0" + /* 10646 */ "MINI_S_B\0" + /* 10655 */ "CLTI_S_B\0" + /* 10664 */ "MAXI_S_B\0" + /* 10673 */ "MIN_S_B\0" + /* 10681 */ "AVER_S_B\0" + /* 10690 */ "SUBS_S_B\0" + /* 10699 */ "ADDS_S_B\0" + /* 10708 */ "SAT_S_B\0" + /* 10716 */ "CLT_S_B\0" + /* 10724 */ "SUBSUU_S_B\0" + /* 10735 */ "DIV_S_B\0" + /* 10743 */ "MAX_S_B\0" + /* 10751 */ "COPY_S_B\0" + /* 10760 */ "SPLAT_B\0" + /* 10768 */ "BSET_B\0" + /* 10775 */ "PCNT_B\0" + /* 10782 */ "INSERT_B\0" + /* 10791 */ "ST_B\0" + /* 10796 */ "ASUB_U_B\0" + /* 10805 */ "MOD_U_B\0" + /* 10813 */ "CLE_U_B\0" + /* 10821 */ "AVE_U_B\0" + /* 10829 */ "CLEI_U_B\0" + /* 10838 */ "MINI_U_B\0" + /* 10847 */ "CLTI_U_B\0" + /* 10856 */ "MAXI_U_B\0" + /* 10865 */ "MIN_U_B\0" + /* 10873 */ "AVER_U_B\0" + /* 10882 */ "SUBS_U_B\0" + /* 10891 */ "ADDS_U_B\0" + /* 10900 */ "SUBSUS_U_B\0" + /* 10911 */ "SAT_U_B\0" + /* 10919 */ "CLT_U_B\0" + /* 10927 */ "DIV_U_B\0" + /* 10935 */ "MAX_U_B\0" + /* 10943 */ "COPY_U_B\0" + /* 10952 */ "MSUBV_B\0" + /* 10960 */ "MADDV_B\0" + /* 10968 */ "PCKEV_B\0" + /* 10976 */ "ILVEV_B\0" + /* 10984 */ "MULV_B\0" + /* 10991 */ "BZ_B\0" + /* 10996 */ "BNZ_B\0" + /* 11002 */ "BC\0" + /* 11005 */ "BGEC\0" + /* 11010 */ "BNEC\0" + /* 11015 */ "JIC\0" + /* 11019 */ "G_INTRINSIC\0" + /* 11031 */ "BALC\0" + /* 11036 */ "JIALC\0" + /* 11042 */ "BGEZALC\0" + /* 11050 */ "BLEZALC\0" + /* 11058 */ "BNEZALC\0" + /* 11066 */ "BEQZALC\0" + /* 11074 */ "BGTZALC\0" + /* 11082 */ "BLTZALC\0" + /* 11090 */ "ERETNC\0" + /* 11097 */ "G_FPTRUNC\0" + /* 11107 */ "G_INTRINSIC_TRUNC\0" + /* 11125 */ "G_TRUNC\0" + /* 11133 */ "G_BUILD_VECTOR_TRUNC\0" + /* 11154 */ "SYNC\0" + /* 11159 */ "G_DYN_STACKALLOC\0" + /* 11176 */ "LDPC\0" + /* 11181 */ "AUIPC\0" + /* 11187 */ "ALUIPC\0" + /* 11194 */ "ADDIUPC\0" + /* 11202 */ "LWUPC\0" + /* 11208 */ "LWPC\0" + /* 11213 */ "BEQC\0" + /* 11218 */ "ADDSC\0" + /* 11224 */ "BLTC\0" + /* 11229 */ "BGEUC\0" + /* 11235 */ "BLTUC\0" + /* 11241 */ "BNVC\0" + /* 11246 */ "BOVC\0" + /* 11251 */ "ADDWC\0" + /* 11257 */ "BGEZC\0" + /* 11263 */ "BLEZC\0" + /* 11269 */ "BNEZC\0" + /* 11275 */ "BEQZC\0" + /* 11281 */ "BGTZC\0" + /* 11287 */ "BLTZC\0" + /* 11293 */ "CRC32D\0" + /* 11300 */ "SAAD\0" + /* 11305 */ "G_FMAD\0" + /* 11312 */ "G_INDEXED_SEXTLOAD\0" + /* 11331 */ "G_SEXTLOAD\0" + /* 11342 */ "G_INDEXED_ZEXTLOAD\0" + /* 11361 */ "G_ZEXTLOAD\0" + /* 11372 */ "G_INDEXED_LOAD\0" + /* 11387 */ "G_LOAD\0" + /* 11394 */ "CRC32CD\0" + /* 11402 */ "SCD\0" + /* 11406 */ "DADD\0" + /* 11411 */ "G_VECREDUCE_FADD\0" + /* 11428 */ "G_FADD\0" + /* 11435 */ "G_VECREDUCE_SEQ_FADD\0" + /* 11456 */ "G_STRICT_FADD\0" + /* 11470 */ "G_ATOMICRMW_FADD\0" + /* 11487 */ "PseudoMADD\0" + /* 11498 */ "G_VECREDUCE_ADD\0" + /* 11514 */ "G_ADD\0" + /* 11520 */ "G_PTR_ADD\0" + /* 11530 */ "G_ATOMICRMW_ADD\0" + /* 11546 */ "DSHD\0" + /* 11551 */ "YIELD\0" + /* 11557 */ "LLD\0" + /* 11561 */ "G_ATOMICRMW_NAND\0" + /* 11578 */ "G_VECREDUCE_AND\0" + /* 11594 */ "G_AND\0" + /* 11600 */ "G_ATOMICRMW_AND\0" + /* 11616 */ "PREPEND\0" + /* 11624 */ "APPEND\0" + /* 11631 */ "LIFETIME_END\0" + /* 11644 */ "G_BRCOND\0" + /* 11653 */ "G_LLROUND\0" + /* 11663 */ "G_LROUND\0" + /* 11672 */ "G_INTRINSIC_ROUND\0" + /* 11690 */ "DMOD\0" + /* 11695 */ "LOAD_STACK_GUARD\0" + /* 11712 */ "SD\0" + /* 11715 */ "FLOG2_D\0" + /* 11723 */ "FEXP2_D\0" + /* 11731 */ "MINA_D\0" + /* 11738 */ "SRA_D\0" + /* 11744 */ "MAXA_D\0" + /* 11751 */ "ADD_A_D\0" + /* 11759 */ "FMIN_A_D\0" + /* 11768 */ "ADDS_A_D\0" + /* 11777 */ "FMAX_A_D\0" + /* 11786 */ "FSUB_D\0" + /* 11793 */ "FMSUB_D\0" + /* 11801 */ "NLOC_D\0" + /* 11808 */ "NLZC_D\0" + /* 11815 */ "FADD_D\0" + /* 11822 */ "FMADD_D\0" + /* 11830 */ "SLD_D\0" + /* 11836 */ "PCKOD_D\0" + /* 11844 */ "ILVOD_D\0" + /* 11852 */ "FCLE_D\0" + /* 11859 */ "FSLE_D\0" + /* 11866 */ "CMP_SLE_D\0" + /* 11876 */ "FCULE_D\0" + /* 11884 */ "FSULE_D\0" + /* 11892 */ "CMP_SULE_D\0" + /* 11903 */ "CMP_ULE_D\0" + /* 11913 */ "CMP_LE_D\0" + /* 11922 */ "FCNE_D\0" + /* 11929 */ "FSNE_D\0" + /* 11936 */ "FCUNE_D\0" + /* 11944 */ "FSUNE_D\0" + /* 11952 */ "INSVE_D\0" + /* 11960 */ "FCAF_D\0" + /* 11967 */ "FSAF_D\0" + /* 11974 */ "CMP_SAF_D\0" + /* 11984 */ "MSUBF_D\0" + /* 11992 */ "MADDF_D\0" + /* 12000 */ "VSHF_D\0" + /* 12007 */ "CMP_F_D\0" + /* 12015 */ "BNEG_D\0" + /* 12022 */ "SRAI_D\0" + /* 12029 */ "SLDI_D\0" + /* 12036 */ "BNEGI_D\0" + /* 12044 */ "SLLI_D\0" + /* 12051 */ "SRLI_D\0" + /* 12058 */ "BINSLI_D\0" + /* 12067 */ "CEQI_D\0" + /* 12074 */ "SRARI_D\0" + /* 12082 */ "BCLRI_D\0" + /* 12090 */ "SRLRI_D\0" + /* 12098 */ "BINSRI_D\0" + /* 12107 */ "SPLATI_D\0" + /* 12116 */ "BSETI_D\0" + /* 12124 */ "SUBVI_D\0" + /* 12132 */ "ADDVI_D\0" + /* 12140 */ "SEL_D\0" + /* 12146 */ "FILL_D\0" + /* 12153 */ "SLL_D\0" + /* 12159 */ "FEXUPL_D\0" + /* 12168 */ "FFQL_D\0" + /* 12175 */ "SRL_D\0" + /* 12181 */ "BINSL_D\0" + /* 12189 */ "FMUL_D\0" + /* 12196 */ "ILVL_D\0" + /* 12203 */ "FMIN_D\0" + /* 12210 */ "FCUN_D\0" + /* 12217 */ "FSUN_D\0" + /* 12224 */ "CMP_SUN_D\0" + /* 12234 */ "CMP_UN_D\0" + /* 12243 */ "FRCP_D\0" + /* 12250 */ "FCEQ_D\0" + /* 12257 */ "FSEQ_D\0" + /* 12264 */ "CMP_SEQ_D\0" + /* 12274 */ "FCUEQ_D\0" + /* 12282 */ "FSUEQ_D\0" + /* 12290 */ "CMP_SUEQ_D\0" + /* 12301 */ "CMP_UEQ_D\0" + /* 12311 */ "CMP_EQ_D\0" + /* 12320 */ "SRAR_D\0" + /* 12327 */ "LDR_D\0" + /* 12333 */ "BCLR_D\0" + /* 12340 */ "SRLR_D\0" + /* 12347 */ "FCOR_D\0" + /* 12354 */ "FSOR_D\0" + /* 12361 */ "FEXUPR_D\0" + /* 12370 */ "FFQR_D\0" + /* 12377 */ "BINSR_D\0" + /* 12385 */ "STR_D\0" + /* 12391 */ "ILVR_D\0" + /* 12398 */ "FABS_D\0" + /* 12405 */ "FCLASS_D\0" + /* 12414 */ "ASUB_S_D\0" + /* 12423 */ "HSUB_S_D\0" + /* 12432 */ "DPSUB_S_D\0" + /* 12442 */ "FTRUNC_S_D\0" + /* 12453 */ "HADD_S_D\0" + /* 12462 */ "DPADD_S_D\0" + /* 12472 */ "MOD_S_D\0" + /* 12480 */ "CLE_S_D\0" + /* 12488 */ "AVE_S_D\0" + /* 12496 */ "CLEI_S_D\0" + /* 12505 */ "MINI_S_D\0" + /* 12514 */ "CLTI_S_D\0" + /* 12523 */ "MAXI_S_D\0" + /* 12532 */ "MIN_S_D\0" + /* 12540 */ "DOTP_S_D\0" + /* 12549 */ "AVER_S_D\0" + /* 12558 */ "SUBS_S_D\0" + /* 12567 */ "ADDS_S_D\0" + /* 12576 */ "SAT_S_D\0" + /* 12584 */ "CLT_S_D\0" + /* 12592 */ "FFINT_S_D\0" + /* 12602 */ "FTINT_S_D\0" + /* 12612 */ "SUBSUU_S_D\0" + /* 12623 */ "DIV_S_D\0" + /* 12631 */ "MAX_S_D\0" + /* 12639 */ "COPY_S_D\0" + /* 12648 */ "SPLAT_D\0" + /* 12656 */ "BSET_D\0" + /* 12663 */ "FCLT_D\0" + /* 12670 */ "FSLT_D\0" + /* 12677 */ "CMP_SLT_D\0" + /* 12687 */ "FCULT_D\0" + /* 12695 */ "FSULT_D\0" + /* 12703 */ "CMP_SULT_D\0" + /* 12714 */ "CMP_ULT_D\0" + /* 12724 */ "CMP_LT_D\0" + /* 12733 */ "PCNT_D\0" + /* 12740 */ "FRINT_D\0" + /* 12748 */ "INSERT_D\0" + /* 12757 */ "FSQRT_D\0" + /* 12765 */ "FRSQRT_D\0" + /* 12774 */ "ST_D\0" + /* 12779 */ "ASUB_U_D\0" + /* 12788 */ "HSUB_U_D\0" + /* 12797 */ "DPSUB_U_D\0" + /* 12807 */ "FTRUNC_U_D\0" + /* 12818 */ "HADD_U_D\0" + /* 12827 */ "DPADD_U_D\0" + /* 12837 */ "MOD_U_D\0" + /* 12845 */ "CLE_U_D\0" + /* 12853 */ "AVE_U_D\0" + /* 12861 */ "CLEI_U_D\0" + /* 12870 */ "MINI_U_D\0" + /* 12879 */ "CLTI_U_D\0" + /* 12888 */ "MAXI_U_D\0" + /* 12897 */ "MIN_U_D\0" + /* 12905 */ "DOTP_U_D\0" + /* 12914 */ "AVER_U_D\0" + /* 12923 */ "SUBS_U_D\0" + /* 12932 */ "ADDS_U_D\0" + /* 12941 */ "SUBSUS_U_D\0" + /* 12952 */ "SAT_U_D\0" + /* 12960 */ "CLT_U_D\0" + /* 12968 */ "FFINT_U_D\0" + /* 12978 */ "FTINT_U_D\0" + /* 12988 */ "DIV_U_D\0" + /* 12996 */ "MAX_U_D\0" + /* 13004 */ "MSUBV_D\0" + /* 13012 */ "MADDV_D\0" + /* 13020 */ "PCKEV_D\0" + /* 13028 */ "ILVEV_D\0" + /* 13036 */ "FDIV_D\0" + /* 13043 */ "MULV_D\0" + /* 13050 */ "PseudoTRUNC_W_D\0" + /* 13066 */ "FMAX_D\0" + /* 13073 */ "BZ_D\0" + /* 13078 */ "SELNEZ_D\0" + /* 13087 */ "BNZ_D\0" + /* 13093 */ "SELEQZ_D\0" + /* 13102 */ "LBE\0" + /* 13106 */ "PSEUDO_PROBE\0" + /* 13119 */ "SBE\0" + /* 13123 */ "G_SSUBE\0" + /* 13131 */ "G_USUBE\0" + /* 13139 */ "G_FENCE\0" + /* 13147 */ "ARITH_FENCE\0" + /* 13159 */ "REG_SEQUENCE\0" + /* 13172 */ "SCE\0" + /* 13176 */ "G_SADDE\0" + /* 13184 */ "G_UADDE\0" + /* 13192 */ "G_FMINNUM_IEEE\0" + /* 13207 */ "G_FMAXNUM_IEEE\0" + /* 13222 */ "CACHEE\0" + /* 13229 */ "PREFE\0" + /* 13235 */ "BGE\0" + /* 13239 */ "SGE\0" + /* 13243 */ "TGE\0" + /* 13247 */ "CACHE\0" + /* 13253 */ "LHE\0" + /* 13257 */ "SHE\0" + /* 13261 */ "SIGRIE\0" + /* 13268 */ "G_JUMP_TABLE\0" + /* 13281 */ "BUNDLE\0" + /* 13288 */ "LLE\0" + /* 13292 */ "SLE\0" + /* 13296 */ "LWLE\0" + /* 13301 */ "SWLE\0" + /* 13306 */ "BNE\0" + /* 13310 */ "G_MEMCPY_INLINE\0" + /* 13326 */ "SNE\0" + /* 13330 */ "TNE\0" + /* 13334 */ "LOCAL_ESCAPE\0" + /* 13347 */ "DVPE\0" + /* 13352 */ "EVPE\0" + /* 13357 */ "G_INDEXED_STORE\0" + /* 13373 */ "G_STORE\0" + /* 13381 */ "LWRE\0" + /* 13386 */ "SWRE\0" + /* 13391 */ "G_BITREVERSE\0" + /* 13404 */ "PAUSE\0" + /* 13410 */ "DBG_VALUE\0" + /* 13420 */ "G_GLOBAL_VALUE\0" + /* 13435 */ "G_MEMMOVE\0" + /* 13445 */ "LWE\0" + /* 13449 */ "SWE\0" + /* 13453 */ "G_FREEZE\0" + /* 13462 */ "G_FCANONICALIZE\0" + /* 13478 */ "LBuE\0" + /* 13483 */ "LHuE\0" + /* 13488 */ "BC0F\0" + /* 13493 */ "BC1F\0" + /* 13498 */ "BC2F\0" + /* 13503 */ "BC3F\0" + /* 13508 */ "G_CTLZ_ZERO_UNDEF\0" + /* 13526 */ "G_CTTZ_ZERO_UNDEF\0" + /* 13544 */ "G_IMPLICIT_DEF\0" + /* 13559 */ "PREF\0" + /* 13564 */ "DBG_INSTR_REF\0" + /* 13578 */ "TLBINVF\0" + /* 13586 */ "TLBGINVF\0" + /* 13595 */ "G_FNEG\0" + /* 13602 */ "TAILCALLHB64R6REG\0" + /* 13620 */ "TAILCALL64R6REG\0" + /* 13636 */ "TAILCALLHBR6REG\0" + /* 13652 */ "TAILCALLR6REG\0" + /* 13666 */ "EXTRACT_SUBREG\0" + /* 13681 */ "INSERT_SUBREG\0" + /* 13695 */ "TAILCALLREG\0" + /* 13707 */ "G_SEXT_INREG\0" + /* 13720 */ "SUBREG_TO_REG\0" + /* 13734 */ "G_ATOMIC_CMPXCHG\0" + /* 13751 */ "G_ATOMICRMW_XCHG\0" + /* 13768 */ "G_FLOG\0" + /* 13775 */ "G_VAARG\0" + /* 13783 */ "PREALLOCATED_ARG\0" + /* 13800 */ "CRC32H\0" + /* 13807 */ "DSBH\0" + /* 13812 */ "WSBH\0" + /* 13817 */ "CRC32CH\0" + /* 13825 */ "SEH\0" + /* 13829 */ "G_SMULH\0" + /* 13837 */ "G_UMULH\0" + /* 13845 */ "SHRA_PH\0" + /* 13853 */ "PRECRQ_QB_PH\0" + /* 13866 */ "PRECR_QB_PH\0" + /* 13878 */ "PRECRQU_S_QB_PH\0" + /* 13894 */ "PseudoCMP_LE_PH\0" + /* 13910 */ "SUBQH_PH\0" + /* 13919 */ "ADDQH_PH\0" + /* 13928 */ "PseudoPICK_PH\0" + /* 13942 */ "SHLL_PH\0" + /* 13950 */ "REPL_PH\0" + /* 13958 */ "SHRL_PH\0" + /* 13966 */ "PACKRL_PH\0" + /* 13976 */ "MUL_PH\0" + /* 13983 */ "SUBQ_PH\0" + /* 13991 */ "ADDQ_PH\0" + /* 13999 */ "PseudoCMP_EQ_PH\0" + /* 14015 */ "SHRA_R_PH\0" + /* 14025 */ "SUBQH_R_PH\0" + /* 14036 */ "ADDQH_R_PH\0" + /* 14047 */ "SHRAV_R_PH\0" + /* 14058 */ "MULQ_RS_PH\0" + /* 14069 */ "SHLL_S_PH\0" + /* 14079 */ "MUL_S_PH\0" + /* 14088 */ "SUBQ_S_PH\0" + /* 14098 */ "ADDQ_S_PH\0" + /* 14108 */ "MULQ_S_PH\0" + /* 14118 */ "ABSQ_S_PH\0" + /* 14128 */ "SUBU_S_PH\0" + /* 14138 */ "ADDU_S_PH\0" + /* 14148 */ "SHLLV_S_PH\0" + /* 14159 */ "PseudoCMP_LT_PH\0" + /* 14175 */ "SUBU_PH\0" + /* 14183 */ "ADDU_PH\0" + /* 14191 */ "SHRAV_PH\0" + /* 14200 */ "SHLLV_PH\0" + /* 14209 */ "REPLV_PH\0" + /* 14218 */ "SHRLV_PH\0" + /* 14227 */ "DPA_W_PH\0" + /* 14236 */ "MULSA_W_PH\0" + /* 14247 */ "DPAQX_SA_W_PH\0" + /* 14261 */ "DPSQX_SA_W_PH\0" + /* 14275 */ "DPS_W_PH\0" + /* 14284 */ "DPAQ_S_W_PH\0" + /* 14296 */ "MULSAQ_S_W_PH\0" + /* 14310 */ "DPSQ_S_W_PH\0" + /* 14322 */ "DPAQX_S_W_PH\0" + /* 14335 */ "DPSQX_S_W_PH\0" + /* 14348 */ "DPAX_W_PH\0" + /* 14358 */ "DPSX_W_PH\0" + /* 14368 */ "SH\0" + /* 14371 */ "DMUH\0" + /* 14376 */ "SRA_H\0" + /* 14382 */ "ADD_A_H\0" + /* 14390 */ "MIN_A_H\0" + /* 14398 */ "ADDS_A_H\0" + /* 14407 */ "MAX_A_H\0" + /* 14415 */ "NLOC_H\0" + /* 14422 */ "NLZC_H\0" + /* 14429 */ "SLD_H\0" + /* 14435 */ "PCKOD_H\0" + /* 14443 */ "ILVOD_H\0" + /* 14451 */ "INSVE_H\0" + /* 14459 */ "VSHF_H\0" + /* 14466 */ "BNEG_H\0" + /* 14473 */ "SRAI_H\0" + /* 14480 */ "SLDI_H\0" + /* 14487 */ "BNEGI_H\0" + /* 14495 */ "SLLI_H\0" + /* 14502 */ "SRLI_H\0" + /* 14509 */ "BINSLI_H\0" + /* 14518 */ "CEQI_H\0" + /* 14525 */ "SRARI_H\0" + /* 14533 */ "BCLRI_H\0" + /* 14541 */ "SRLRI_H\0" + /* 14549 */ "BINSRI_H\0" + /* 14558 */ "SPLATI_H\0" + /* 14567 */ "BSETI_H\0" + /* 14575 */ "SUBVI_H\0" + /* 14583 */ "ADDVI_H\0" + /* 14591 */ "FILL_H\0" + /* 14598 */ "SLL_H\0" + /* 14604 */ "SRL_H\0" + /* 14610 */ "BINSL_H\0" + /* 14618 */ "ILVL_H\0" + /* 14625 */ "FEXDO_H\0" + /* 14633 */ "CEQ_H\0" + /* 14639 */ "FTQ_H\0" + /* 14645 */ "MSUB_Q_H\0" + /* 14654 */ "MADD_Q_H\0" + /* 14663 */ "MUL_Q_H\0" + /* 14671 */ "MSUBR_Q_H\0" + /* 14681 */ "MADDR_Q_H\0" + /* 14691 */ "MULR_Q_H\0" + /* 14700 */ "SRAR_H\0" + /* 14707 */ "BCLR_H\0" + /* 14714 */ "SRLR_H\0" + /* 14721 */ "BINSR_H\0" + /* 14729 */ "ILVR_H\0" + /* 14736 */ "ASUB_S_H\0" + /* 14745 */ "HSUB_S_H\0" + /* 14754 */ "DPSUB_S_H\0" + /* 14764 */ "HADD_S_H\0" + /* 14773 */ "DPADD_S_H\0" + /* 14783 */ "MOD_S_H\0" + /* 14791 */ "CLE_S_H\0" + /* 14799 */ "AVE_S_H\0" + /* 14807 */ "CLEI_S_H\0" + /* 14816 */ "MINI_S_H\0" + /* 14825 */ "CLTI_S_H\0" + /* 14834 */ "MAXI_S_H\0" + /* 14843 */ "MIN_S_H\0" + /* 14851 */ "DOTP_S_H\0" + /* 14860 */ "AVER_S_H\0" + /* 14869 */ "EXTR_S_H\0" + /* 14878 */ "SUBS_S_H\0" + /* 14887 */ "ADDS_S_H\0" + /* 14896 */ "SAT_S_H\0" + /* 14904 */ "CLT_S_H\0" + /* 14912 */ "SUBSUU_S_H\0" + /* 14923 */ "DIV_S_H\0" + /* 14931 */ "EXTRV_S_H\0" + /* 14941 */ "MAX_S_H\0" + /* 14949 */ "COPY_S_H\0" + /* 14958 */ "SPLAT_H\0" + /* 14966 */ "BSET_H\0" + /* 14973 */ "PCNT_H\0" + /* 14980 */ "INSERT_H\0" + /* 14989 */ "ST_H\0" + /* 14994 */ "ASUB_U_H\0" + /* 15003 */ "HSUB_U_H\0" + /* 15012 */ "DPSUB_U_H\0" + /* 15022 */ "HADD_U_H\0" + /* 15031 */ "DPADD_U_H\0" + /* 15041 */ "MOD_U_H\0" + /* 15049 */ "CLE_U_H\0" + /* 15057 */ "AVE_U_H\0" + /* 15065 */ "CLEI_U_H\0" + /* 15074 */ "MINI_U_H\0" + /* 15083 */ "CLTI_U_H\0" + /* 15092 */ "MAXI_U_H\0" + /* 15101 */ "MIN_U_H\0" + /* 15109 */ "DOTP_U_H\0" + /* 15118 */ "AVER_U_H\0" + /* 15127 */ "SUBS_U_H\0" + /* 15136 */ "ADDS_U_H\0" + /* 15145 */ "SUBSUS_U_H\0" + /* 15156 */ "SAT_U_H\0" + /* 15164 */ "CLT_U_H\0" + /* 15172 */ "DIV_U_H\0" + /* 15180 */ "MAX_U_H\0" + /* 15188 */ "COPY_U_H\0" + /* 15197 */ "MSUBV_H\0" + /* 15205 */ "MADDV_H\0" + /* 15213 */ "PCKEV_H\0" + /* 15221 */ "ILVEV_H\0" + /* 15229 */ "MULV_H\0" + /* 15236 */ "BZ_H\0" + /* 15241 */ "BNZ_H\0" + /* 15247 */ "SYNCI\0" + /* 15253 */ "DI\0" + /* 15256 */ "TGEI\0" + /* 15261 */ "TNEI\0" + /* 15266 */ "DAHI\0" + /* 15271 */ "PseudoMFHI\0" + /* 15282 */ "PseudoMTLOHI\0" + /* 15295 */ "DBG_PHI\0" + /* 15303 */ "MFTHI\0" + /* 15309 */ "MTHI\0" + /* 15314 */ "MTTHI\0" + /* 15320 */ "TEQI\0" + /* 15325 */ "G_FPTOSI\0" + /* 15334 */ "DATI\0" + /* 15339 */ "TLTI\0" + /* 15344 */ "DAUI\0" + /* 15349 */ "G_FPTOUI\0" + /* 15358 */ "GINVI\0" + /* 15364 */ "TLBWI\0" + /* 15370 */ "TLBGWI\0" + /* 15377 */ "G_FPOWI\0" + /* 15385 */ "MOVN_I64_I\0" + /* 15396 */ "MOVZ_I64_I\0" + /* 15407 */ "MOVF_I\0" + /* 15414 */ "PseudoSELECTFP_F_I\0" + /* 15433 */ "MOVN_I_I\0" + /* 15442 */ "MOVZ_I_I\0" + /* 15451 */ "PseudoD_SELECT_I\0" + /* 15468 */ "PseudoSELECT_I\0" + /* 15483 */ "MOVT_I\0" + /* 15490 */ "PseudoSELECTFP_T_I\0" + /* 15509 */ "J\0" + /* 15511 */ "BREAK\0" + /* 15517 */ "FORK\0" + /* 15522 */ "G_PTRMASK\0" + /* 15532 */ "BAL\0" + /* 15536 */ "JAL\0" + /* 15540 */ "BGEZAL\0" + /* 15547 */ "BLTZAL\0" + /* 15554 */ "MULEU_S_PH_QBL\0" + /* 15569 */ "PRECEU_PH_QBL\0" + /* 15583 */ "PRECEQU_PH_QBL\0" + /* 15598 */ "DPAU_H_QBL\0" + /* 15609 */ "DPSU_H_QBL\0" + /* 15620 */ "LDL\0" + /* 15624 */ "SDL\0" + /* 15628 */ "GC_LABEL\0" + /* 15637 */ "DBG_LABEL\0" + /* 15647 */ "EH_LABEL\0" + /* 15656 */ "ANNOTATION_LABEL\0" + /* 15673 */ "BGEL\0" + /* 15678 */ "BLEL\0" + /* 15683 */ "BNEL\0" + /* 15688 */ "ICALL_BRANCH_FUNNEL\0" + /* 15708 */ "BC1FL\0" + /* 15714 */ "BC2FL\0" + /* 15720 */ "BC3FL\0" + /* 15726 */ "MAQ_SA_W_PHL\0" + /* 15739 */ "PRECEQ_W_PHL\0" + /* 15752 */ "MAQ_S_W_PHL\0" + /* 15764 */ "MULEQ_S_W_PHL\0" + /* 15778 */ "G_FSHL\0" + /* 15785 */ "G_SHL\0" + /* 15791 */ "G_FCEIL\0" + /* 15799 */ "TAILCALL\0" + /* 15808 */ "HYPCALL\0" + /* 15816 */ "SYSCALL\0" + /* 15824 */ "PATCHABLE_TAIL_CALL\0" + /* 15844 */ "PATCHABLE_TYPED_EVENT_CALL\0" + /* 15871 */ "PATCHABLE_EVENT_CALL\0" + /* 15892 */ "FENTRY_CALL\0" + /* 15904 */ "BGEZALL\0" + /* 15912 */ "BLTZALL\0" + /* 15920 */ "KILL\0" + /* 15925 */ "DSLL\0" + /* 15930 */ "DROL\0" + /* 15935 */ "BEQL\0" + /* 15940 */ "DSRL\0" + /* 15945 */ "BC1TL\0" + /* 15951 */ "BC2TL\0" + /* 15957 */ "BC3TL\0" + /* 15963 */ "BGTL\0" + /* 15968 */ "BLTL\0" + /* 15973 */ "G_ROTL\0" + /* 15980 */ "BGEUL\0" + /* 15986 */ "BLEUL\0" + /* 15992 */ "DMUL\0" + /* 15997 */ "G_VECREDUCE_FMUL\0" + /* 16014 */ "G_FMUL\0" + /* 16021 */ "G_VECREDUCE_SEQ_FMUL\0" + /* 16042 */ "G_STRICT_FMUL\0" + /* 16056 */ "G_VECREDUCE_MUL\0" + /* 16072 */ "G_MUL\0" + /* 16078 */ "BGTUL\0" + /* 16084 */ "BLTUL\0" + /* 16090 */ "LWL\0" + /* 16094 */ "SWL\0" + /* 16098 */ "BGEZL\0" + /* 16104 */ "BLEZL\0" + /* 16110 */ "BGTZL\0" + /* 16116 */ "BLTZL\0" + /* 16122 */ "PseudoCVT_D64_L\0" + /* 16138 */ "PseudoCVT_S_L\0" + /* 16152 */ "G_FREM\0" + /* 16159 */ "G_STRICT_FREM\0" + /* 16173 */ "G_SREM\0" + /* 16180 */ "G_UREM\0" + /* 16187 */ "G_SDIVREM\0" + /* 16197 */ "G_UDIVREM\0" + /* 16207 */ "MFGC0_MM\0" + /* 16216 */ "MFHGC0_MM\0" + /* 16226 */ "MTHGC0_MM\0" + /* 16236 */ "MTGC0_MM\0" + /* 16245 */ "LDC1_MM\0" + /* 16253 */ "SDC1_MM\0" + /* 16261 */ "CFC1_MM\0" + /* 16269 */ "MFC1_MM\0" + /* 16277 */ "CTC1_MM\0" + /* 16285 */ "MTC1_MM\0" + /* 16293 */ "LWC1_MM\0" + /* 16301 */ "SWC1_MM\0" + /* 16309 */ "LUXC1_MM\0" + /* 16318 */ "SUXC1_MM\0" + /* 16327 */ "LWXC1_MM\0" + /* 16336 */ "SWXC1_MM\0" + /* 16345 */ "MFHC1_D32_MM\0" + /* 16358 */ "MTHC1_D32_MM\0" + /* 16371 */ "FSUB_D32_MM\0" + /* 16383 */ "NMSUB_D32_MM\0" + /* 16396 */ "FADD_D32_MM\0" + /* 16408 */ "NMADD_D32_MM\0" + /* 16421 */ "C_NGE_D32_MM\0" + /* 16434 */ "C_NGLE_D32_MM\0" + /* 16448 */ "C_OLE_D32_MM\0" + /* 16461 */ "C_ULE_D32_MM\0" + /* 16474 */ "C_LE_D32_MM\0" + /* 16486 */ "C_SF_D32_MM\0" + /* 16498 */ "MOVF_D32_MM\0" + /* 16510 */ "C_F_D32_MM\0" + /* 16521 */ "FNEG_D32_MM\0" + /* 16533 */ "MOVN_I_D32_MM\0" + /* 16547 */ "MOVZ_I_D32_MM\0" + /* 16561 */ "C_NGL_D32_MM\0" + /* 16574 */ "FMUL_D32_MM\0" + /* 16586 */ "C_UN_D32_MM\0" + /* 16598 */ "RECIP_D32_MM\0" + /* 16611 */ "FCMP_D32_MM\0" + /* 16623 */ "C_SEQ_D32_MM\0" + /* 16636 */ "C_UEQ_D32_MM\0" + /* 16649 */ "C_EQ_D32_MM\0" + /* 16661 */ "FABS_D32_MM\0" + /* 16673 */ "CVT_S_D32_MM\0" + /* 16686 */ "C_NGT_D32_MM\0" + /* 16699 */ "C_OLT_D32_MM\0" + /* 16712 */ "C_ULT_D32_MM\0" + /* 16725 */ "C_LT_D32_MM\0" + /* 16737 */ "FSQRT_D32_MM\0" + /* 16750 */ "RSQRT_D32_MM\0" + /* 16763 */ "MOVT_D32_MM\0" + /* 16775 */ "FDIV_D32_MM\0" + /* 16787 */ "FMOV_D32_MM\0" + /* 16799 */ "CVT_W_D32_MM\0" + /* 16812 */ "BPOSGE32_MM\0" + /* 16824 */ "LWM32_MM\0" + /* 16833 */ "SWM32_MM\0" + /* 16842 */ "FCMP_S32_MM\0" + /* 16854 */ "CFC2_MM\0" + /* 16862 */ "CTC2_MM\0" + /* 16870 */ "ADDIUR2_MM\0" + /* 16881 */ "MFHC1_D64_MM\0" + /* 16894 */ "MTHC1_D64_MM\0" + /* 16907 */ "MTC1_D64_MM\0" + /* 16919 */ "FSUB_D64_MM\0" + /* 16931 */ "FADD_D64_MM\0" + /* 16943 */ "C_NGE_D64_MM\0" + /* 16956 */ "C_NGLE_D64_MM\0" + /* 16970 */ "C_OLE_D64_MM\0" + /* 16983 */ "C_ULE_D64_MM\0" + /* 16996 */ "C_LE_D64_MM\0" + /* 17008 */ "C_SF_D64_MM\0" + /* 17020 */ "C_F_D64_MM\0" + /* 17031 */ "FNEG_D64_MM\0" + /* 17043 */ "C_NGL_D64_MM\0" + /* 17056 */ "FMUL_D64_MM\0" + /* 17068 */ "CVT_L_D64_MM\0" + /* 17081 */ "C_UN_D64_MM\0" + /* 17093 */ "RECIP_D64_MM\0" + /* 17106 */ "C_SEQ_D64_MM\0" + /* 17119 */ "C_UEQ_D64_MM\0" + /* 17132 */ "C_EQ_D64_MM\0" + /* 17144 */ "FABS_D64_MM\0" + /* 17156 */ "CVT_S_D64_MM\0" + /* 17169 */ "C_NGT_D64_MM\0" + /* 17182 */ "C_OLT_D64_MM\0" + /* 17195 */ "C_ULT_D64_MM\0" + /* 17208 */ "C_LT_D64_MM\0" + /* 17220 */ "FSQRT_D64_MM\0" + /* 17233 */ "RSQRT_D64_MM\0" + /* 17246 */ "FDIV_D64_MM\0" + /* 17258 */ "FMOV_D64_MM\0" + /* 17270 */ "CVT_W_D64_MM\0" + /* 17283 */ "ADDIUS5_MM\0" + /* 17294 */ "SB16_MM\0" + /* 17302 */ "JRC16_MM\0" + /* 17311 */ "AND16_MM\0" + /* 17320 */ "MOVE16_MM\0" + /* 17330 */ "SH16_MM\0" + /* 17338 */ "ANDI16_MM\0" + /* 17348 */ "MFHI16_MM\0" + /* 17358 */ "LI16_MM\0" + /* 17366 */ "BREAK16_MM\0" + /* 17377 */ "SLL16_MM\0" + /* 17386 */ "SRL16_MM\0" + /* 17395 */ "LWM16_MM\0" + /* 17404 */ "SWM16_MM\0" + /* 17413 */ "MFLO16_MM\0" + /* 17423 */ "SDBBP16_MM\0" + /* 17434 */ "JR16_MM\0" + /* 17442 */ "JALR16_MM\0" + /* 17452 */ "XOR16_MM\0" + /* 17461 */ "JALRS16_MM\0" + /* 17472 */ "NOT16_MM\0" + /* 17481 */ "LBU16_MM\0" + /* 17490 */ "SUBU16_MM\0" + /* 17500 */ "ADDU16_MM\0" + /* 17510 */ "LHU16_MM\0" + /* 17519 */ "LW16_MM\0" + /* 17527 */ "SW16_MM\0" + /* 17535 */ "BNEZ16_MM\0" + /* 17545 */ "BEQZ16_MM\0" + /* 17555 */ "PRECEU_PH_QBLA_MM\0" + /* 17573 */ "PRECEQU_PH_QBLA_MM\0" + /* 17592 */ "PRECEU_PH_QBRA_MM\0" + /* 17610 */ "PRECEQU_PH_QBRA_MM\0" + /* 17629 */ "SRA_MM\0" + /* 17636 */ "SEB_MM\0" + /* 17643 */ "EHB_MM\0" + /* 17650 */ "LB_MM\0" + /* 17656 */ "CMPGU_LE_QB_MM\0" + /* 17671 */ "CMPU_LE_QB_MM\0" + /* 17685 */ "PICK_QB_MM\0" + /* 17696 */ "SHLL_QB_MM\0" + /* 17707 */ "REPL_QB_MM\0" + /* 17718 */ "SHRL_QB_MM\0" + /* 17729 */ "CMPGU_EQ_QB_MM\0" + /* 17744 */ "CMPU_EQ_QB_MM\0" + /* 17758 */ "SUBU_S_QB_MM\0" + /* 17771 */ "ADDU_S_QB_MM\0" + /* 17784 */ "CMPGU_LT_QB_MM\0" + /* 17799 */ "CMPU_LT_QB_MM\0" + /* 17813 */ "SUBU_QB_MM\0" + /* 17824 */ "ADDU_QB_MM\0" + /* 17835 */ "SHLLV_QB_MM\0" + /* 17847 */ "REPLV_QB_MM\0" + /* 17859 */ "SHRLV_QB_MM\0" + /* 17871 */ "RADDU_W_QB_MM\0" + /* 17885 */ "SB_MM\0" + /* 17891 */ "MODSUB_MM\0" + /* 17901 */ "PseudoMSUB_MM\0" + /* 17915 */ "SYNC_MM\0" + /* 17923 */ "ADDIUPC_MM\0" + /* 17934 */ "ADDSC_MM\0" + /* 17943 */ "ADDWC_MM\0" + /* 17952 */ "BNEZC_MM\0" + /* 17961 */ "BEQZC_MM\0" + /* 17970 */ "PseudoMADD_MM\0" + /* 17984 */ "AND_MM\0" + /* 17991 */ "LBE_MM\0" + /* 17998 */ "SBE_MM\0" + /* 18005 */ "SCE_MM\0" + /* 18012 */ "CACHEE_MM\0" + /* 18022 */ "PREFE_MM\0" + /* 18031 */ "TGE_MM\0" + /* 18038 */ "CACHE_MM\0" + /* 18047 */ "LHE_MM\0" + /* 18054 */ "SHE_MM\0" + /* 18061 */ "LLE_MM\0" + /* 18068 */ "LWLE_MM\0" + /* 18076 */ "SWLE_MM\0" + /* 18084 */ "BNE_MM\0" + /* 18091 */ "TNE_MM\0" + /* 18098 */ "LWRE_MM\0" + /* 18106 */ "SWRE_MM\0" + /* 18114 */ "PAUSE_MM\0" + /* 18123 */ "LWE_MM\0" + /* 18130 */ "SWE_MM\0" + /* 18137 */ "LBuE_MM\0" + /* 18145 */ "LHuE_MM\0" + /* 18153 */ "BC1F_MM\0" + /* 18161 */ "PREF_MM\0" + /* 18169 */ "TLBGINVF_MM\0" + /* 18181 */ "TAILCALLREG_MM\0" + /* 18196 */ "WSBH_MM\0" + /* 18204 */ "SEH_MM\0" + /* 18211 */ "LH_MM\0" + /* 18217 */ "SHRA_PH_MM\0" + /* 18228 */ "PRECRQ_QB_PH_MM\0" + /* 18244 */ "PRECRQU_S_QB_PH_MM\0" + /* 18263 */ "CMP_LE_PH_MM\0" + /* 18276 */ "PICK_PH_MM\0" + /* 18287 */ "SHLL_PH_MM\0" + /* 18298 */ "REPL_PH_MM\0" + /* 18309 */ "PACKRL_PH_MM\0" + /* 18322 */ "SUBQ_PH_MM\0" + /* 18333 */ "ADDQ_PH_MM\0" + /* 18344 */ "CMP_EQ_PH_MM\0" + /* 18357 */ "SHRA_R_PH_MM\0" + /* 18370 */ "SHRAV_R_PH_MM\0" + /* 18384 */ "MULQ_RS_PH_MM\0" + /* 18398 */ "SHLL_S_PH_MM\0" + /* 18411 */ "SUBQ_S_PH_MM\0" + /* 18424 */ "ADDQ_S_PH_MM\0" + /* 18437 */ "ABSQ_S_PH_MM\0" + /* 18450 */ "SHLLV_S_PH_MM\0" + /* 18464 */ "CMP_LT_PH_MM\0" + /* 18477 */ "SHRAV_PH_MM\0" + /* 18489 */ "SHLLV_PH_MM\0" + /* 18501 */ "REPLV_PH_MM\0" + /* 18513 */ "DPAQ_S_W_PH_MM\0" + /* 18528 */ "MULSAQ_S_W_PH_MM\0" + /* 18545 */ "DPSQ_S_W_PH_MM\0" + /* 18560 */ "SH_MM\0" + /* 18566 */ "EXTR_S_H_MM\0" + /* 18578 */ "EXTRV_S_H_MM\0" + /* 18591 */ "SYNCI_MM\0" + /* 18600 */ "DI_MM\0" + /* 18606 */ "TGEI_MM\0" + /* 18614 */ "TNEI_MM\0" + /* 18622 */ "PseudoMFHI_MM\0" + /* 18636 */ "PseudoMTLOHI_MM\0" + /* 18652 */ "MTHI_MM\0" + /* 18660 */ "TEQI_MM\0" + /* 18668 */ "TLTI_MM\0" + /* 18676 */ "TLBWI_MM\0" + /* 18685 */ "TLBGWI_MM\0" + /* 18695 */ "MOVF_I_MM\0" + /* 18705 */ "MOVN_I_MM\0" + /* 18715 */ "MOVT_I_MM\0" + /* 18725 */ "MOVZ_I_MM\0" + /* 18735 */ "J_MM\0" + /* 18740 */ "BREAK_MM\0" + /* 18749 */ "JAL_MM\0" + /* 18756 */ "BGEZAL_MM\0" + /* 18766 */ "BLTZAL_MM\0" + /* 18776 */ "MULEU_S_PH_QBL_MM\0" + /* 18794 */ "PRECEU_PH_QBL_MM\0" + /* 18811 */ "PRECEQU_PH_QBL_MM\0" + /* 18829 */ "DPAU_H_QBL_MM\0" + /* 18843 */ "DPSU_H_QBL_MM\0" + /* 18857 */ "MAQ_SA_W_PHL_MM\0" + /* 18873 */ "PRECEQ_W_PHL_MM\0" + /* 18889 */ "MAQ_S_W_PHL_MM\0" + /* 18904 */ "MULEQ_S_W_PHL_MM\0" + /* 18921 */ "TAILCALL_MM\0" + /* 18933 */ "HYPCALL_MM\0" + /* 18944 */ "SYSCALL_MM\0" + /* 18955 */ "SLL_MM\0" + /* 18962 */ "SRL_MM\0" + /* 18969 */ "MUL_MM\0" + /* 18976 */ "LWL_MM\0" + /* 18983 */ "SWL_MM\0" + /* 18990 */ "LWM_MM\0" + /* 18997 */ "SWM_MM\0" + /* 19004 */ "CLO_MM\0" + /* 19011 */ "PseudoMFLO_MM\0" + /* 19025 */ "SHILO_MM\0" + /* 19034 */ "MTLO_MM\0" + /* 19042 */ "TRAP_MM\0" + /* 19050 */ "SDBBP_MM\0" + /* 19059 */ "TLBP_MM\0" + /* 19067 */ "EXTPDP_MM\0" + /* 19077 */ "MOVEP_MM\0" + /* 19086 */ "TLBGP_MM\0" + /* 19095 */ "LWGP_MM\0" + /* 19103 */ "MTHLIP_MM\0" + /* 19113 */ "SSNOP_MM\0" + /* 19122 */ "ADDIUR1SP_MM\0" + /* 19135 */ "RDDSP_MM\0" + /* 19144 */ "WRDSP_MM\0" + /* 19153 */ "LWDSP_MM\0" + /* 19162 */ "SWDSP_MM\0" + /* 19171 */ "MSUB_DSP_MM\0" + /* 19183 */ "MADD_DSP_MM\0" + /* 19195 */ "MFHI_DSP_MM\0" + /* 19207 */ "MTHI_DSP_MM\0" + /* 19219 */ "MFLO_DSP_MM\0" + /* 19231 */ "MTLO_DSP_MM\0" + /* 19243 */ "MULT_DSP_MM\0" + /* 19255 */ "MSUBU_DSP_MM\0" + /* 19268 */ "MADDU_DSP_MM\0" + /* 19281 */ "MULTU_DSP_MM\0" + /* 19294 */ "ADDIUSP_MM\0" + /* 19305 */ "LWSP_MM\0" + /* 19313 */ "SWSP_MM\0" + /* 19321 */ "EXTP_MM\0" + /* 19329 */ "LWP_MM\0" + /* 19336 */ "SWP_MM\0" + /* 19343 */ "BEQ_MM\0" + /* 19350 */ "TEQ_MM\0" + /* 19357 */ "TLBR_MM\0" + /* 19365 */ "MULEU_S_PH_QBR_MM\0" + /* 19383 */ "PRECEU_PH_QBR_MM\0" + /* 19400 */ "PRECEQU_PH_QBR_MM\0" + /* 19418 */ "DPAU_H_QBR_MM\0" + /* 19432 */ "DPSU_H_QBR_MM\0" + /* 19446 */ "BAL_BR_MM\0" + /* 19456 */ "TLBGR_MM\0" + /* 19465 */ "MAQ_SA_W_PHR_MM\0" + /* 19481 */ "PRECEQ_W_PHR_MM\0" + /* 19497 */ "MAQ_S_W_PHR_MM\0" + /* 19512 */ "MULEQ_S_W_PHR_MM\0" + /* 19529 */ "JR_MM\0" + /* 19535 */ "JALR_MM\0" + /* 19543 */ "NOR_MM\0" + /* 19550 */ "XOR_MM\0" + /* 19557 */ "ROTR_MM\0" + /* 19565 */ "TLBWR_MM\0" + /* 19574 */ "TLBGWR_MM\0" + /* 19584 */ "RDHWR_MM\0" + /* 19593 */ "LWR_MM\0" + /* 19600 */ "SWR_MM\0" + /* 19607 */ "JALS_MM\0" + /* 19615 */ "BGEZALS_MM\0" + /* 19626 */ "BLTZALS_MM\0" + /* 19637 */ "INS_MM\0" + /* 19644 */ "JALRS_MM\0" + /* 19653 */ "LWXS_MM\0" + /* 19661 */ "CVT_D32_S_MM\0" + /* 19674 */ "CVT_D64_S_MM\0" + /* 19687 */ "FSUB_S_MM\0" + /* 19697 */ "NMSUB_S_MM\0" + /* 19708 */ "FADD_S_MM\0" + /* 19718 */ "NMADD_S_MM\0" + /* 19729 */ "C_NGE_S_MM\0" + /* 19740 */ "C_NGLE_S_MM\0" + /* 19752 */ "C_OLE_S_MM\0" + /* 19763 */ "C_ULE_S_MM\0" + /* 19774 */ "C_LE_S_MM\0" + /* 19784 */ "C_SF_S_MM\0" + /* 19794 */ "MOVF_S_MM\0" + /* 19804 */ "C_F_S_MM\0" + /* 19813 */ "FNEG_S_MM\0" + /* 19823 */ "MOVN_I_S_MM\0" + /* 19835 */ "MOVZ_I_S_MM\0" + /* 19847 */ "C_NGL_S_MM\0" + /* 19858 */ "FMUL_S_MM\0" + /* 19868 */ "CVT_L_S_MM\0" + /* 19879 */ "C_UN_S_MM\0" + /* 19889 */ "RECIP_S_MM\0" + /* 19900 */ "C_SEQ_S_MM\0" + /* 19911 */ "C_UEQ_S_MM\0" + /* 19922 */ "C_EQ_S_MM\0" + /* 19932 */ "FABS_S_MM\0" + /* 19942 */ "C_NGT_S_MM\0" + /* 19953 */ "C_OLT_S_MM\0" + /* 19964 */ "C_ULT_S_MM\0" + /* 19975 */ "C_LT_S_MM\0" + /* 19985 */ "FSQRT_S_MM\0" + /* 19996 */ "RSQRT_S_MM\0" + /* 20007 */ "MOVT_S_MM\0" + /* 20017 */ "FDIV_S_MM\0" + /* 20027 */ "FMOV_S_MM\0" + /* 20037 */ "TRUNC_W_S_MM\0" + /* 20050 */ "ROUND_W_S_MM\0" + /* 20063 */ "CEIL_W_S_MM\0" + /* 20075 */ "FLOOR_W_S_MM\0" + /* 20088 */ "CVT_W_S_MM\0" + /* 20099 */ "BC1T_MM\0" + /* 20107 */ "DERET_MM\0" + /* 20116 */ "WAIT_MM\0" + /* 20124 */ "SLT_MM\0" + /* 20131 */ "TLT_MM\0" + /* 20138 */ "PseudoMULT_MM\0" + /* 20152 */ "EXT_MM\0" + /* 20159 */ "PseudoMSUBU_MM\0" + /* 20174 */ "PseudoMADDU_MM\0" + /* 20189 */ "TGEU_MM\0" + /* 20197 */ "TGEIU_MM\0" + /* 20206 */ "TLTIU_MM\0" + /* 20215 */ "TLTU_MM\0" + /* 20223 */ "LWU_MM\0" + /* 20230 */ "SRAV_MM\0" + /* 20238 */ "BITREV_MM\0" + /* 20248 */ "SDIV_MM\0" + /* 20256 */ "UDIV_MM\0" + /* 20264 */ "SLLV_MM\0" + /* 20272 */ "SRLV_MM\0" + /* 20280 */ "TLBGINV_MM\0" + /* 20291 */ "SHILOV_MM\0" + /* 20301 */ "EXTPDPV_MM\0" + /* 20312 */ "EXTPV_MM\0" + /* 20321 */ "ROTRV_MM\0" + /* 20330 */ "INSV_MM\0" + /* 20338 */ "LW_MM\0" + /* 20344 */ "SW_MM\0" + /* 20350 */ "CVT_D32_W_MM\0" + /* 20363 */ "CVT_D64_W_MM\0" + /* 20376 */ "TRUNC_W_MM\0" + /* 20387 */ "ROUND_W_MM\0" + /* 20398 */ "PRECRQ_PH_W_MM\0" + /* 20413 */ "PRECRQ_RS_PH_W_MM\0" + /* 20431 */ "CEIL_W_MM\0" + /* 20441 */ "DPAQ_SA_L_W_MM\0" + /* 20456 */ "DPSQ_SA_L_W_MM\0" + /* 20471 */ "FLOOR_W_MM\0" + /* 20482 */ "EXTR_W_MM\0" + /* 20492 */ "SHRA_R_W_MM\0" + /* 20504 */ "EXTR_R_W_MM\0" + /* 20516 */ "SHRAV_R_W_MM\0" + /* 20529 */ "EXTRV_R_W_MM\0" + /* 20542 */ "EXTR_RS_W_MM\0" + /* 20555 */ "EXTRV_RS_W_MM\0" + /* 20569 */ "SHLL_S_W_MM\0" + /* 20581 */ "SUBQ_S_W_MM\0" + /* 20593 */ "ADDQ_S_W_MM\0" + /* 20605 */ "ABSQ_S_W_MM\0" + /* 20617 */ "CVT_S_W_MM\0" + /* 20628 */ "SHLLV_S_W_MM\0" + /* 20641 */ "EXTRV_W_MM\0" + /* 20652 */ "PREFX_MM\0" + /* 20661 */ "LHX_MM\0" + /* 20668 */ "JALX_MM\0" + /* 20676 */ "LBUX_MM\0" + /* 20684 */ "LWX_MM\0" + /* 20691 */ "BGEZ_MM\0" + /* 20699 */ "BLEZ_MM\0" + /* 20707 */ "CLZ_MM\0" + /* 20714 */ "BGTZ_MM\0" + /* 20722 */ "BLTZ_MM\0" + /* 20730 */ "PseudoIndirectBranch_MM\0" + /* 20754 */ "ADDi_MM\0" + /* 20762 */ "ANDi_MM\0" + /* 20770 */ "XORi_MM\0" + /* 20778 */ "SLTi_MM\0" + /* 20786 */ "LUi_MM\0" + /* 20793 */ "LBu_MM\0" + /* 20800 */ "SUBu_MM\0" + /* 20808 */ "ADDu_MM\0" + /* 20816 */ "LHu_MM\0" + /* 20823 */ "SLTu_MM\0" + /* 20831 */ "PseudoMULTu_MM\0" + /* 20846 */ "LEA_ADDiu_MM\0" + /* 20859 */ "SLTiu_MM\0" + /* 20868 */ "INLINEASM\0" + /* 20878 */ "DINSM\0" + /* 20884 */ "DEXTM\0" + /* 20890 */ "G_FMINIMUM\0" + /* 20901 */ "G_FMAXIMUM\0" + /* 20912 */ "G_FMINNUM\0" + /* 20922 */ "G_FMAXNUM\0" + /* 20932 */ "G_INTRINSIC_ROUNDEVEN\0" + /* 20954 */ "BALIGN\0" + /* 20961 */ "DALIGN\0" + /* 20968 */ "G_FCOPYSIGN\0" + /* 20980 */ "G_VECREDUCE_FMIN\0" + /* 20997 */ "G_VECREDUCE_SMIN\0" + /* 21014 */ "G_SMIN\0" + /* 21021 */ "G_VECREDUCE_UMIN\0" + /* 21038 */ "G_UMIN\0" + /* 21045 */ "G_ATOMICRMW_UMIN\0" + /* 21062 */ "G_ATOMICRMW_MIN\0" + /* 21078 */ "G_FSIN\0" + /* 21085 */ "DMFC2_OCTEON\0" + /* 21098 */ "DMTC2_OCTEON\0" + /* 21111 */ "CFI_INSTRUCTION\0" + /* 21127 */ "ADJCALLSTACKDOWN\0" + /* 21144 */ "G_SSUBO\0" + /* 21152 */ "G_USUBO\0" + /* 21160 */ "G_SADDO\0" + /* 21168 */ "G_UADDO\0" + /* 21176 */ "FEXP2_D_1_PSEUDO\0" + /* 21193 */ "FEXP2_W_1_PSEUDO\0" + /* 21210 */ "BPOSGE32_PSEUDO\0" + /* 21226 */ "INSERT_B_VIDX64_PSEUDO\0" + /* 21249 */ "INSERT_FD_VIDX64_PSEUDO\0" + /* 21273 */ "INSERT_D_VIDX64_PSEUDO\0" + /* 21296 */ "INSERT_H_VIDX64_PSEUDO\0" + /* 21319 */ "INSERT_FW_VIDX64_PSEUDO\0" + /* 21343 */ "INSERT_W_VIDX64_PSEUDO\0" + /* 21366 */ "SNZ_B_PSEUDO\0" + /* 21379 */ "SZ_B_PSEUDO\0" + /* 21391 */ "BSEL_FD_PSEUDO\0" + /* 21406 */ "FILL_FD_PSEUDO\0" + /* 21421 */ "INSERT_FD_PSEUDO\0" + /* 21438 */ "COPY_FD_PSEUDO\0" + /* 21453 */ "MSA_FP_EXTEND_D_PSEUDO\0" + /* 21476 */ "MSA_FP_ROUND_D_PSEUDO\0" + /* 21498 */ "BSEL_D_PSEUDO\0" + /* 21512 */ "AND_V_D_PSEUDO\0" + /* 21527 */ "NOR_V_D_PSEUDO\0" + /* 21542 */ "XOR_V_D_PSEUDO\0" + /* 21557 */ "SNZ_D_PSEUDO\0" + /* 21570 */ "SZ_D_PSEUDO\0" + /* 21582 */ "BSEL_H_PSEUDO\0" + /* 21596 */ "AND_V_H_PSEUDO\0" + /* 21611 */ "NOR_V_H_PSEUDO\0" + /* 21626 */ "XOR_V_H_PSEUDO\0" + /* 21641 */ "SNZ_H_PSEUDO\0" + /* 21654 */ "SZ_H_PSEUDO\0" + /* 21666 */ "SNZ_V_PSEUDO\0" + /* 21679 */ "SZ_V_PSEUDO\0" + /* 21691 */ "BSEL_FW_PSEUDO\0" + /* 21706 */ "FILL_FW_PSEUDO\0" + /* 21721 */ "INSERT_FW_PSEUDO\0" + /* 21738 */ "COPY_FW_PSEUDO\0" + /* 21753 */ "MSA_FP_EXTEND_W_PSEUDO\0" + /* 21776 */ "MSA_FP_ROUND_W_PSEUDO\0" + /* 21798 */ "BSEL_W_PSEUDO\0" + /* 21812 */ "AND_V_W_PSEUDO\0" + /* 21827 */ "NOR_V_W_PSEUDO\0" + /* 21842 */ "XOR_V_W_PSEUDO\0" + /* 21857 */ "SNZ_W_PSEUDO\0" + /* 21870 */ "SZ_W_PSEUDO\0" + /* 21882 */ "INSERT_B_VIDX_PSEUDO\0" + /* 21903 */ "INSERT_FD_VIDX_PSEUDO\0" + /* 21925 */ "INSERT_D_VIDX_PSEUDO\0" + /* 21946 */ "INSERT_H_VIDX_PSEUDO\0" + /* 21967 */ "INSERT_FW_VIDX_PSEUDO\0" + /* 21989 */ "INSERT_W_VIDX_PSEUDO\0" + /* 22010 */ "DCLO\0" + /* 22015 */ "PseudoMFLO\0" + /* 22026 */ "SHILO\0" + /* 22032 */ "MFTLO\0" + /* 22038 */ "MTLO\0" + /* 22043 */ "MTTLO\0" + /* 22049 */ "G_SMULO\0" + /* 22057 */ "G_UMULO\0" + /* 22065 */ "G_BZERO\0" + /* 22073 */ "STACKMAP\0" + /* 22082 */ "TRAP\0" + /* 22087 */ "G_BSWAP\0" + /* 22095 */ "DBITSWAP\0" + /* 22104 */ "SDBBP\0" + /* 22110 */ "TLBP\0" + /* 22115 */ "EXTPDP\0" + /* 22122 */ "G_SITOFP\0" + /* 22131 */ "G_UITOFP\0" + /* 22140 */ "TLBGP\0" + /* 22146 */ "MTHLIP\0" + /* 22153 */ "G_FCMP\0" + /* 22160 */ "G_ICMP\0" + /* 22167 */ "SSNOP\0" + /* 22173 */ "DPOP\0" + /* 22178 */ "G_CTPOP\0" + /* 22186 */ "PATCHABLE_OP\0" + /* 22199 */ "FAULTING_OP\0" + /* 22211 */ "LOAD_ACC64DSP\0" + /* 22225 */ "STORE_ACC64DSP\0" + /* 22240 */ "RDDSP\0" + /* 22246 */ "WRDSP\0" + /* 22252 */ "MFTDSP\0" + /* 22259 */ "MTTDSP\0" + /* 22266 */ "LWDSP\0" + /* 22272 */ "SWDSP\0" + /* 22278 */ "MSUB_DSP\0" + /* 22287 */ "MADD_DSP\0" + /* 22296 */ "LOAD_CCOND_DSP\0" + /* 22311 */ "STORE_CCOND_DSP\0" + /* 22327 */ "MFHI_DSP\0" + /* 22336 */ "PseudoMTLOHI_DSP\0" + /* 22353 */ "MTHI_DSP\0" + /* 22362 */ "MFLO_DSP\0" + /* 22371 */ "MTLO_DSP\0" + /* 22380 */ "MULT_DSP\0" + /* 22389 */ "MSUBU_DSP\0" + /* 22399 */ "MADDU_DSP\0" + /* 22409 */ "MULTU_DSP\0" + /* 22419 */ "JRADDIUSP\0" + /* 22429 */ "EXTP\0" + /* 22434 */ "ADJCALLSTACKUP\0" + /* 22449 */ "PREALLOCATED_SETUP\0" + /* 22468 */ "DVP\0" + /* 22472 */ "EVP\0" + /* 22476 */ "G_FEXP\0" + /* 22483 */ "BEQ\0" + /* 22487 */ "SEQ\0" + /* 22491 */ "TEQ\0" + /* 22495 */ "TLBR\0" + /* 22500 */ "MULEU_S_PH_QBR\0" + /* 22515 */ "PRECEU_PH_QBR\0" + /* 22529 */ "PRECEQU_PH_QBR\0" + /* 22544 */ "DPAU_H_QBR\0" + /* 22555 */ "DPSU_H_QBR\0" + /* 22566 */ "G_BR\0" + /* 22571 */ "BAL_BR\0" + /* 22578 */ "INLINEASM_BR\0" + /* 22591 */ "G_BLOCK_ADDR\0" + /* 22604 */ "LDR\0" + /* 22608 */ "SDR\0" + /* 22612 */ "PATCHABLE_FUNCTION_ENTER\0" + /* 22637 */ "G_READCYCLECOUNTER\0" + /* 22656 */ "G_READ_REGISTER\0" + /* 22672 */ "G_WRITE_REGISTER\0" + /* 22689 */ "TLBGR\0" + /* 22695 */ "LoadImmDoubleFGR\0" + /* 22712 */ "LoadImmSingleFGR\0" + /* 22729 */ "MAQ_SA_W_PHR\0" + /* 22742 */ "PRECEQ_W_PHR\0" + /* 22755 */ "MAQ_S_W_PHR\0" + /* 22767 */ "MULEQ_S_W_PHR\0" + /* 22781 */ "G_ASHR\0" + /* 22788 */ "G_FSHR\0" + /* 22795 */ "G_LSHR\0" + /* 22802 */ "JR\0" + /* 22805 */ "JALR\0" + /* 22810 */ "NOR\0" + /* 22814 */ "G_FFLOOR\0" + /* 22823 */ "DROR\0" + /* 22828 */ "G_BUILD_VECTOR\0" + /* 22843 */ "G_SHUFFLE_VECTOR\0" + /* 22860 */ "G_VECREDUCE_XOR\0" + /* 22876 */ "G_XOR\0" + /* 22882 */ "G_ATOMICRMW_XOR\0" + /* 22898 */ "G_VECREDUCE_OR\0" + /* 22913 */ "G_OR\0" + /* 22918 */ "G_ATOMICRMW_OR\0" + /* 22933 */ "MFTGPR\0" + /* 22940 */ "MTTGPR\0" + /* 22947 */ "LoadImmDoubleGPR\0" + /* 22964 */ "LoadImmSingleGPR\0" + /* 22981 */ "MFTR\0" + /* 22986 */ "DROTR\0" + /* 22992 */ "G_ROTR\0" + /* 22999 */ "G_INTTOPTR\0" + /* 23010 */ "MTTR\0" + /* 23015 */ "TLBWR\0" + /* 23021 */ "TLBGWR\0" + /* 23028 */ "RDHWR\0" + /* 23034 */ "LWR\0" + /* 23038 */ "SWR\0" + /* 23042 */ "G_FABS\0" + /* 23049 */ "G_ABS\0" + /* 23055 */ "G_UNMERGE_VALUES\0" + /* 23072 */ "G_MERGE_VALUES\0" + /* 23087 */ "CINS\0" + /* 23092 */ "DINS\0" + /* 23097 */ "G_FCOS\0" + /* 23104 */ "G_CONCAT_VECTORS\0" + /* 23121 */ "COPY_TO_REGCLASS\0" + /* 23138 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" + /* 23168 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" + /* 23195 */ "EXTS\0" + /* 23200 */ "CVT_D32_S\0" + /* 23210 */ "CVT_D64_S\0" + /* 23220 */ "MOVN_I64_S\0" + /* 23231 */ "MOVZ_I64_S\0" + /* 23242 */ "MINA_S\0" + /* 23249 */ "MAXA_S\0" + /* 23256 */ "FSUB_S\0" + /* 23263 */ "NMSUB_S\0" + /* 23271 */ "FADD_S\0" + /* 23278 */ "NMADD_S\0" + /* 23286 */ "C_NGE_S\0" + /* 23294 */ "C_NGLE_S\0" + /* 23303 */ "C_OLE_S\0" + /* 23311 */ "CMP_SLE_S\0" + /* 23321 */ "CMP_SULE_S\0" + /* 23332 */ "C_ULE_S\0" + /* 23340 */ "CMP_ULE_S\0" + /* 23350 */ "C_LE_S\0" + /* 23357 */ "CMP_LE_S\0" + /* 23366 */ "CMP_SAF_S\0" + /* 23376 */ "MSUBF_S\0" + /* 23384 */ "MADDF_S\0" + /* 23392 */ "C_SF_S\0" + /* 23399 */ "MOVF_S\0" + /* 23406 */ "C_F_S\0" + /* 23412 */ "PseudoSELECTFP_F_S\0" + /* 23431 */ "CMP_F_S\0" + /* 23439 */ "FNEG_S\0" + /* 23446 */ "MOVN_I_S\0" + /* 23455 */ "MOVZ_I_S\0" + /* 23464 */ "SEL_S\0" + /* 23470 */ "C_NGL_S\0" + /* 23478 */ "FMUL_S\0" + /* 23485 */ "TRUNC_L_S\0" + /* 23495 */ "ROUND_L_S\0" + /* 23505 */ "CEIL_L_S\0" + /* 23514 */ "FLOOR_L_S\0" + /* 23524 */ "CVT_L_S\0" + /* 23532 */ "MIN_S\0" + /* 23538 */ "CMP_SUN_S\0" + /* 23548 */ "C_UN_S\0" + /* 23555 */ "CMP_UN_S\0" + /* 23564 */ "RECIP_S\0" + /* 23572 */ "C_SEQ_S\0" + /* 23580 */ "CMP_SEQ_S\0" + /* 23590 */ "CMP_SUEQ_S\0" + /* 23601 */ "C_UEQ_S\0" + /* 23609 */ "CMP_UEQ_S\0" + /* 23619 */ "C_EQ_S\0" + /* 23626 */ "CMP_EQ_S\0" + /* 23635 */ "FABS_S\0" + /* 23642 */ "CLASS_S\0" + /* 23650 */ "PseudoSELECT_S\0" + /* 23665 */ "C_NGT_S\0" + /* 23673 */ "C_OLT_S\0" + /* 23681 */ "CMP_SLT_S\0" + /* 23691 */ "CMP_SULT_S\0" + /* 23702 */ "C_ULT_S\0" + /* 23710 */ "CMP_ULT_S\0" + /* 23720 */ "C_LT_S\0" + /* 23727 */ "CMP_LT_S\0" + /* 23736 */ "RINT_S\0" + /* 23743 */ "FSQRT_S\0" + /* 23751 */ "RSQRT_S\0" + /* 23759 */ "MOVT_S\0" + /* 23766 */ "PseudoSELECTFP_T_S\0" + /* 23785 */ "FDIV_S\0" + /* 23792 */ "FMOV_S\0" + /* 23799 */ "PseudoTRUNC_W_S\0" + /* 23815 */ "ROUND_W_S\0" + /* 23825 */ "CEIL_W_S\0" + /* 23834 */ "FLOOR_W_S\0" + /* 23844 */ "CVT_W_S\0" + /* 23852 */ "MAX_S\0" + /* 23858 */ "SELNEZ_S\0" + /* 23867 */ "SELEQZ_S\0" + /* 23876 */ "BC0T\0" + /* 23881 */ "BC1T\0" + /* 23886 */ "BC2T\0" + /* 23891 */ "BC3T\0" + /* 23896 */ "G_SSUBSAT\0" + /* 23906 */ "G_USUBSAT\0" + /* 23916 */ "G_SADDSAT\0" + /* 23926 */ "G_UADDSAT\0" + /* 23936 */ "G_SSHLSAT\0" + /* 23946 */ "G_USHLSAT\0" + /* 23956 */ "G_SMULFIXSAT\0" + /* 23969 */ "G_UMULFIXSAT\0" + /* 23982 */ "G_SDIVFIXSAT\0" + /* 23995 */ "G_UDIVFIXSAT\0" + /* 24008 */ "G_EXTRACT\0" + /* 24018 */ "G_SELECT\0" + /* 24027 */ "G_BRINDIRECT\0" + /* 24040 */ "DERET\0" + /* 24046 */ "PATCHABLE_RET\0" + /* 24060 */ "G_MEMSET\0" + /* 24069 */ "BGT\0" + /* 24073 */ "WAIT\0" + /* 24078 */ "PATCHABLE_FUNCTION_EXIT\0" + /* 24102 */ "G_BRJT\0" + /* 24109 */ "BLT\0" + /* 24113 */ "G_EXTRACT_VECTOR_ELT\0" + /* 24134 */ "G_INSERT_VECTOR_ELT\0" + /* 24154 */ "SLT\0" + /* 24158 */ "TLT\0" + /* 24162 */ "PseudoDMULT\0" + /* 24174 */ "PseudoMULT\0" + /* 24185 */ "DMT\0" + /* 24189 */ "EMT\0" + /* 24193 */ "G_FCONSTANT\0" + /* 24205 */ "G_CONSTANT\0" + /* 24216 */ "STATEPOINT\0" + /* 24227 */ "PATCHPOINT\0" + /* 24238 */ "G_PTRTOINT\0" + /* 24249 */ "G_FRINT\0" + /* 24257 */ "G_INTRINSIC_LRINT\0" + /* 24275 */ "G_FNEARBYINT\0" + /* 24288 */ "G_VASTART\0" + /* 24298 */ "LIFETIME_START\0" + /* 24313 */ "G_INSERT\0" + /* 24322 */ "G_FSQRT\0" + /* 24330 */ "G_STRICT_FSQRT\0" + /* 24345 */ "G_BITCAST\0" + /* 24355 */ "G_ADDRSPACE_CAST\0" + /* 24372 */ "DBG_VALUE_LIST\0" + /* 24387 */ "GINVT\0" + /* 24393 */ "DEXT\0" + /* 24398 */ "G_FPEXT\0" + /* 24406 */ "G_SEXT\0" + /* 24413 */ "G_ASSERT_SEXT\0" + /* 24427 */ "G_ANYEXT\0" + /* 24436 */ "G_ZEXT\0" + /* 24443 */ "G_ASSERT_ZEXT\0" + /* 24457 */ "PseudoMSUBU\0" + /* 24469 */ "PseudoMADDU\0" + /* 24481 */ "DMODU\0" + /* 24487 */ "BGEU\0" + /* 24492 */ "SGEU\0" + /* 24497 */ "TGEU\0" + /* 24502 */ "BLEU\0" + /* 24507 */ "SLEU\0" + /* 24512 */ "DMUHU\0" + /* 24518 */ "TGEIU\0" + /* 24524 */ "TTLTIU\0" + /* 24531 */ "V3MULU\0" + /* 24538 */ "DMULU\0" + /* 24544 */ "VMULU\0" + /* 24550 */ "DINSU\0" + /* 24556 */ "BGTU\0" + /* 24561 */ "BLTU\0" + /* 24566 */ "TLTU\0" + /* 24571 */ "DEXTU\0" + /* 24577 */ "DDIVU\0" + /* 24583 */ "DSRAV\0" + /* 24589 */ "BITREV\0" + /* 24596 */ "DDIV\0" + /* 24601 */ "G_FDIV\0" + /* 24608 */ "G_STRICT_FDIV\0" + /* 24622 */ "PseudoDSDIV\0" + /* 24634 */ "G_SDIV\0" + /* 24641 */ "PseudoSDIV\0" + /* 24652 */ "PseudoDUDIV\0" + /* 24664 */ "G_UDIV\0" + /* 24671 */ "PseudoUDIV\0" + /* 24682 */ "DSLLV\0" + /* 24688 */ "DSRLV\0" + /* 24694 */ "TLBINV\0" + /* 24701 */ "TLBGINV\0" + /* 24709 */ "SHILOV\0" + /* 24716 */ "EXTPDPV\0" + /* 24724 */ "EXTPV\0" + /* 24730 */ "DROTRV\0" + /* 24737 */ "INSV\0" + /* 24742 */ "AND_V\0" + /* 24748 */ "MOVE_V\0" + /* 24755 */ "BSEL_V\0" + /* 24762 */ "NOR_V\0" + /* 24768 */ "XOR_V\0" + /* 24774 */ "BZ_V\0" + /* 24779 */ "BMZ_V\0" + /* 24785 */ "BNZ_V\0" + /* 24791 */ "BMNZ_V\0" + /* 24798 */ "CRC32W\0" + /* 24805 */ "CRC32CW\0" + /* 24813 */ "LW\0" + /* 24816 */ "G_FPOW\0" + /* 24823 */ "SW\0" + /* 24826 */ "PseudoCVT_D32_W\0" + /* 24842 */ "FLOG2_W\0" + /* 24850 */ "FEXP2_W\0" + /* 24858 */ "PseudoCVT_D64_W\0" + /* 24874 */ "SRA_W\0" + /* 24880 */ "ADD_A_W\0" + /* 24888 */ "FMIN_A_W\0" + /* 24897 */ "ADDS_A_W\0" + /* 24906 */ "FMAX_A_W\0" + /* 24915 */ "FSUB_W\0" + /* 24922 */ "FMSUB_W\0" + /* 24930 */ "NLOC_W\0" + /* 24937 */ "NLZC_W\0" + /* 24944 */ "FADD_W\0" + /* 24951 */ "FMADD_W\0" + /* 24959 */ "SLD_W\0" + /* 24965 */ "PCKOD_W\0" + /* 24973 */ "ILVOD_W\0" + /* 24981 */ "FCLE_W\0" + /* 24988 */ "FSLE_W\0" + /* 24995 */ "FCULE_W\0" + /* 25003 */ "FSULE_W\0" + /* 25011 */ "FCNE_W\0" + /* 25018 */ "FSNE_W\0" + /* 25025 */ "FCUNE_W\0" + /* 25033 */ "FSUNE_W\0" + /* 25041 */ "INSVE_W\0" + /* 25049 */ "FCAF_W\0" + /* 25056 */ "FSAF_W\0" + /* 25063 */ "VSHF_W\0" + /* 25070 */ "BNEG_W\0" + /* 25077 */ "PRECR_SRA_PH_W\0" + /* 25092 */ "PRECRQ_PH_W\0" + /* 25104 */ "PRECR_SRA_R_PH_W\0" + /* 25121 */ "PRECRQ_RS_PH_W\0" + /* 25136 */ "SUBQH_W\0" + /* 25144 */ "ADDQH_W\0" + /* 25152 */ "SRAI_W\0" + /* 25159 */ "SLDI_W\0" + /* 25166 */ "BNEGI_W\0" + /* 25174 */ "SLLI_W\0" + /* 25181 */ "SRLI_W\0" + /* 25188 */ "BINSLI_W\0" + /* 25197 */ "CEQI_W\0" + /* 25204 */ "SRARI_W\0" + /* 25212 */ "BCLRI_W\0" + /* 25220 */ "SRLRI_W\0" + /* 25228 */ "BINSRI_W\0" + /* 25237 */ "SPLATI_W\0" + /* 25246 */ "BSETI_W\0" + /* 25254 */ "SUBVI_W\0" + /* 25262 */ "ADDVI_W\0" + /* 25270 */ "FILL_W\0" + /* 25277 */ "SLL_W\0" + /* 25283 */ "FEXUPL_W\0" + /* 25292 */ "FFQL_W\0" + /* 25299 */ "SRL_W\0" + /* 25305 */ "BINSL_W\0" + /* 25313 */ "FMUL_W\0" + /* 25320 */ "ILVL_W\0" + /* 25327 */ "DPAQ_SA_L_W\0" + /* 25339 */ "DPSQ_SA_L_W\0" + /* 25351 */ "FMIN_W\0" + /* 25358 */ "FCUN_W\0" + /* 25365 */ "FSUN_W\0" + /* 25372 */ "FEXDO_W\0" + /* 25380 */ "FRCP_W\0" + /* 25387 */ "FCEQ_W\0" + /* 25394 */ "FSEQ_W\0" + /* 25401 */ "FCUEQ_W\0" + /* 25409 */ "FSUEQ_W\0" + /* 25417 */ "FTQ_W\0" + /* 25423 */ "MSUB_Q_W\0" + /* 25432 */ "MADD_Q_W\0" + /* 25441 */ "MUL_Q_W\0" + /* 25449 */ "MSUBR_Q_W\0" + /* 25459 */ "MADDR_Q_W\0" + /* 25469 */ "MULR_Q_W\0" + /* 25478 */ "SRAR_W\0" + /* 25485 */ "LDR_W\0" + /* 25491 */ "BCLR_W\0" + /* 25498 */ "SRLR_W\0" + /* 25505 */ "FCOR_W\0" + /* 25512 */ "FSOR_W\0" + /* 25519 */ "FEXUPR_W\0" + /* 25528 */ "FFQR_W\0" + /* 25535 */ "BINSR_W\0" + /* 25543 */ "STR_W\0" + /* 25549 */ "EXTR_W\0" + /* 25556 */ "ILVR_W\0" + /* 25563 */ "SHRA_R_W\0" + /* 25572 */ "SUBQH_R_W\0" + /* 25582 */ "ADDQH_R_W\0" + /* 25592 */ "EXTR_R_W\0" + /* 25601 */ "SHRAV_R_W\0" + /* 25611 */ "EXTRV_R_W\0" + /* 25621 */ "FABS_W\0" + /* 25628 */ "MULQ_RS_W\0" + /* 25638 */ "EXTR_RS_W\0" + /* 25648 */ "EXTRV_RS_W\0" + /* 25659 */ "FCLASS_W\0" + /* 25668 */ "ASUB_S_W\0" + /* 25677 */ "HSUB_S_W\0" + /* 25686 */ "DPSUB_S_W\0" + /* 25696 */ "FTRUNC_S_W\0" + /* 25707 */ "HADD_S_W\0" + /* 25716 */ "DPADD_S_W\0" + /* 25726 */ "MOD_S_W\0" + /* 25734 */ "CLE_S_W\0" + /* 25742 */ "AVE_S_W\0" + /* 25750 */ "CLEI_S_W\0" + /* 25759 */ "MINI_S_W\0" + /* 25768 */ "CLTI_S_W\0" + /* 25777 */ "MAXI_S_W\0" + /* 25786 */ "SHLL_S_W\0" + /* 25795 */ "MIN_S_W\0" + /* 25803 */ "DOTP_S_W\0" + /* 25812 */ "SUBQ_S_W\0" + /* 25821 */ "ADDQ_S_W\0" + /* 25830 */ "MULQ_S_W\0" + /* 25839 */ "ABSQ_S_W\0" + /* 25848 */ "AVER_S_W\0" + /* 25857 */ "SUBS_S_W\0" + /* 25866 */ "ADDS_S_W\0" + /* 25875 */ "SAT_S_W\0" + /* 25883 */ "CLT_S_W\0" + /* 25891 */ "FFINT_S_W\0" + /* 25901 */ "FTINT_S_W\0" + /* 25911 */ "PseudoCVT_S_W\0" + /* 25925 */ "SUBSUU_S_W\0" + /* 25936 */ "DIV_S_W\0" + /* 25944 */ "SHLLV_S_W\0" + /* 25954 */ "MAX_S_W\0" + /* 25962 */ "COPY_S_W\0" + /* 25971 */ "SPLAT_W\0" + /* 25979 */ "BSET_W\0" + /* 25986 */ "FCLT_W\0" + /* 25993 */ "FSLT_W\0" + /* 26000 */ "FCULT_W\0" + /* 26008 */ "FSULT_W\0" + /* 26016 */ "PCNT_W\0" + /* 26023 */ "FRINT_W\0" + /* 26031 */ "INSERT_W\0" + /* 26040 */ "FSQRT_W\0" + /* 26048 */ "FRSQRT_W\0" + /* 26057 */ "ST_W\0" + /* 26062 */ "ASUB_U_W\0" + /* 26071 */ "HSUB_U_W\0" + /* 26080 */ "DPSUB_U_W\0" + /* 26090 */ "FTRUNC_U_W\0" + /* 26101 */ "HADD_U_W\0" + /* 26110 */ "DPADD_U_W\0" + /* 26120 */ "MOD_U_W\0" + /* 26128 */ "CLE_U_W\0" + /* 26136 */ "AVE_U_W\0" + /* 26144 */ "CLEI_U_W\0" + /* 26153 */ "MINI_U_W\0" + /* 26162 */ "CLTI_U_W\0" + /* 26171 */ "MAXI_U_W\0" + /* 26180 */ "MIN_U_W\0" + /* 26188 */ "DOTP_U_W\0" + /* 26197 */ "AVER_U_W\0" + /* 26206 */ "SUBS_U_W\0" + /* 26215 */ "ADDS_U_W\0" + /* 26224 */ "SUBSUS_U_W\0" + /* 26235 */ "SAT_U_W\0" + /* 26243 */ "CLT_U_W\0" + /* 26251 */ "FFINT_U_W\0" + /* 26261 */ "FTINT_U_W\0" + /* 26271 */ "DIV_U_W\0" + /* 26279 */ "MAX_U_W\0" + /* 26287 */ "COPY_U_W\0" + /* 26296 */ "MSUBV_W\0" + /* 26304 */ "MADDV_W\0" + /* 26312 */ "PCKEV_W\0" + /* 26320 */ "ILVEV_W\0" + /* 26328 */ "FDIV_W\0" + /* 26335 */ "MULV_W\0" + /* 26342 */ "EXTRV_W\0" + /* 26350 */ "FMAX_W\0" + /* 26357 */ "BZ_W\0" + /* 26362 */ "BNZ_W\0" + /* 26368 */ "G_VECREDUCE_FMAX\0" + /* 26385 */ "G_VECREDUCE_SMAX\0" + /* 26402 */ "G_SMAX\0" + /* 26409 */ "G_VECREDUCE_UMAX\0" + /* 26426 */ "G_UMAX\0" + /* 26433 */ "G_ATOMICRMW_UMAX\0" + /* 26450 */ "G_ATOMICRMW_MAX\0" + /* 26466 */ "MFTACX\0" + /* 26473 */ "MTTACX\0" + /* 26480 */ "G_FRAME_INDEX\0" + /* 26494 */ "G_SBFX\0" + /* 26501 */ "G_UBFX\0" + /* 26508 */ "LHX\0" + /* 26512 */ "G_SMULFIX\0" + /* 26522 */ "G_UMULFIX\0" + /* 26532 */ "G_SDIVFIX\0" + /* 26542 */ "G_UDIVFIX\0" + /* 26552 */ "JALX\0" + /* 26557 */ "LBUX\0" + /* 26562 */ "LWX\0" + /* 26566 */ "G_MEMCPY\0" + /* 26575 */ "COPY\0" + /* 26580 */ "CONSTPOOL_ENTRY\0" + /* 26596 */ "BGEZ\0" + /* 26601 */ "BLEZ\0" + /* 26606 */ "BC1NEZ\0" + /* 26613 */ "BC2NEZ\0" + /* 26620 */ "SELNEZ\0" + /* 26627 */ "DCLZ\0" + /* 26632 */ "G_CTLZ\0" + /* 26639 */ "BC1EQZ\0" + /* 26646 */ "BC2EQZ\0" + /* 26653 */ "SELEQZ\0" + /* 26660 */ "BGTZ\0" + /* 26665 */ "BLTZ\0" + /* 26670 */ "G_CTTZ\0" + /* 26677 */ "SelBneZ\0" + /* 26685 */ "SelBeqZ\0" + /* 26693 */ "JalOneReg\0" + /* 26703 */ "JalTwoReg\0" + /* 26713 */ "PseudoIndirectHazardBranch\0" + /* 26740 */ "PseudoIndirectBranch\0" + /* 26761 */ "Ulh\0" + /* 26765 */ "Ush\0" + /* 26769 */ "DADDi\0" + /* 26775 */ "ANDi\0" + /* 26780 */ "SNEi\0" + /* 26785 */ "SEQi\0" + /* 26790 */ "XORi\0" + /* 26795 */ "SLTi\0" + /* 26800 */ "LONG_BRANCH_LUi\0" + /* 26816 */ "SelTBtneZCmpi\0" + /* 26830 */ "SelTBteqZCmpi\0" + /* 26844 */ "SelTBtneZSlti\0" + /* 26858 */ "SelTBteqZSlti\0" + /* 26872 */ "SGEImm\0" + /* 26879 */ "SLEImm\0" + /* 26886 */ "DROLImm\0" + /* 26894 */ "NORImm\0" + /* 26901 */ "DRORImm\0" + /* 26909 */ "SGTImm\0" + /* 26916 */ "SGEUImm\0" + /* 26924 */ "SLEUImm\0" + /* 26932 */ "SGTUImm\0" + /* 26940 */ "BneImm\0" + /* 26947 */ "BeqImm\0" + /* 26954 */ "PseudoReturn\0" + /* 26967 */ "JALRHB64Pseudo\0" + /* 26982 */ "JALR64Pseudo\0" + /* 26995 */ "JALRHBPseudo\0" + /* 27008 */ "JALRPseudo\0" + /* 27019 */ "B_MMR6_Pseudo\0" + /* 27033 */ "B_MM_Pseudo\0" + /* 27045 */ "SDIV_MM_Pseudo\0" + /* 27060 */ "UDIV_MM_Pseudo\0" + /* 27075 */ "LDMacro\0" + /* 27083 */ "SDMacro\0" + /* 27091 */ "SNEMacro\0" + /* 27100 */ "SNEIMacro\0" + /* 27110 */ "SEQIMacro\0" + /* 27120 */ "DSRemIMacro\0" + /* 27132 */ "DURemIMacro\0" + /* 27144 */ "DSDivIMacro\0" + /* 27156 */ "DUDivIMacro\0" + /* 27168 */ "DMULMacro\0" + /* 27178 */ "DMULOMacro\0" + /* 27189 */ "SEQMacro\0" + /* 27198 */ "ABSMacro\0" + /* 27207 */ "DMULOUMacro\0" + /* 27219 */ "DSRemMacro\0" + /* 27230 */ "DURemMacro\0" + /* 27241 */ "BGEImmMacro\0" + /* 27253 */ "BLEImmMacro\0" + /* 27265 */ "BGELImmMacro\0" + /* 27278 */ "BLELImmMacro\0" + /* 27291 */ "BNELImmMacro\0" + /* 27304 */ "BEQLImmMacro\0" + /* 27317 */ "BGTLImmMacro\0" + /* 27330 */ "BLTLImmMacro\0" + /* 27343 */ "BGEULImmMacro\0" + /* 27357 */ "BLEULImmMacro\0" + /* 27371 */ "DMULImmMacro\0" + /* 27384 */ "BGTULImmMacro\0" + /* 27398 */ "BLTULImmMacro\0" + /* 27412 */ "BGTImmMacro\0" + /* 27424 */ "BLTImmMacro\0" + /* 27436 */ "BGEUImmMacro\0" + /* 27449 */ "BLEUImmMacro\0" + /* 27462 */ "BGTUImmMacro\0" + /* 27475 */ "BLTUImmMacro\0" + /* 27488 */ "DSDivMacro\0" + /* 27499 */ "DUDivMacro\0" + /* 27510 */ "LONG_BRANCH_LUi2Op\0" + /* 27529 */ "LONG_BRANCH_DADDiu2Op\0" + /* 27551 */ "LONG_BRANCH_ADDiu2Op\0" + /* 27572 */ "SelTBtneZCmp\0" + /* 27585 */ "SelTBteqZCmp\0" + /* 27598 */ "SaaAddr\0" + /* 27606 */ "SaadAddr\0" + /* 27615 */ "ERet\0" + /* 27620 */ "SelTBtneZSlt\0" + /* 27633 */ "SelTBteqZSlt\0" + /* 27646 */ "LBu\0" + /* 27650 */ "DSUBu\0" + /* 27656 */ "BADDu\0" + /* 27662 */ "DADDu\0" + /* 27668 */ "LHu\0" + /* 27672 */ "SLTu\0" + /* 27677 */ "PseudoDMULTu\0" + /* 27690 */ "PseudoMULTu\0" + /* 27702 */ "LWu\0" + /* 27706 */ "Ulhu\0" + /* 27711 */ "LONG_BRANCH_DADDiu\0" + /* 27730 */ "LEA_ADDiu\0" + /* 27740 */ "LONG_BRANCH_ADDiu\0" + /* 27758 */ "SLTiu\0" + /* 27764 */ "SelTBtneZSltiu\0" + /* 27779 */ "SelTBteqZSltiu\0" + /* 27794 */ "SelTBtneZSltu\0" + /* 27808 */ "SelTBteqZSltu\0" + /* 27822 */ "Ulw\0" + /* 27826 */ "Usw\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +extern const unsigned MipsInstrNameIndices[] = { + 15299U, 20868U, 22578U, 21111U, 15647U, 15628U, 15656U, 15920U, 13666U, + 13681U, 13546U, 13720U, 23121U, 13410U, 24372U, 13564U, 15295U, 15637U, + 13159U, 26575U, 13281U, 24298U, 11631U, 13106U, 13147U, 22073U, 15892U, + 24227U, 11695U, 22449U, 13783U, 24216U, 13334U, 22199U, 22186U, 22612U, + 24046U, 24078U, 15824U, 15871U, 15844U, 15688U, 24413U, 24443U, 11514U, + 10247U, 16072U, 24634U, 24664U, 16173U, 16180U, 16187U, 16197U, 11594U, + 22913U, 22876U, 13544U, 15297U, 26480U, 13420U, 24008U, 23055U, 24313U, + 23072U, 22828U, 11133U, 23104U, 24238U, 22999U, 24345U, 13453U, 11107U, + 11672U, 24257U, 20932U, 22637U, 11387U, 11331U, 11361U, 11372U, 11312U, + 11342U, 13373U, 13357U, 23138U, 13734U, 13751U, 11530U, 10253U, 11600U, + 11561U, 22918U, 22882U, 26450U, 21062U, 26433U, 21045U, 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1418U, 14025U, 1471U, + 25572U, 1830U, 25136U, 1804U, 13983U, 18322U, 14088U, 18411U, 25812U, + 20581U, 10900U, 12941U, 15145U, 26224U, 10724U, 12612U, 14912U, 25925U, + 10690U, 12558U, 14878U, 25857U, 10882U, 12923U, 15127U, 26206U, 17490U, + 5686U, 9912U, 1220U, 10020U, 1281U, 7783U, 14175U, 1562U, 10125U, + 17813U, 14128U, 1532U, 10063U, 17758U, 10497U, 12124U, 14575U, 25254U, + 10953U, 13005U, 15198U, 26297U, 17894U, 5768U, 27651U, 20800U, 180U, + 1962U, 16318U, 24823U, 17527U, 5710U, 3448U, 157U, 16301U, 1158U, + 5431U, 7987U, 1904U, 22272U, 19162U, 13449U, 18130U, 16094U, 3229U, + 13301U, 18076U, 18983U, 17404U, 5640U, 16833U, 19336U, 23038U, 3299U, + 13386U, 18106U, 19600U, 19313U, 7053U, 192U, 16336U, 20344U, 7883U, + 11154U, 15247U, 18591U, 6825U, 17915U, 5925U, 15816U, 18944U, 4781U, + 4144U, 4242U, 4948U, 4964U, 4274U, 4212U, 5103U, 5017U, 4858U, + 4486U, 4870U, 4513U, 5048U, 4126U, 5082U, 4219U, 5114U, 5173U, + 4359U, 4418U, 22491U, 15320U, 18660U, 19350U, 13243U, 15256U, 24518U, + 20197U, 18606U, 24497U, 20189U, 18031U, 24701U, 13586U, 18169U, 20280U, + 22140U, 19086U, 22689U, 19456U, 15370U, 18685U, 23021U, 19574U, 24694U, + 13578U, 6768U, 7863U, 22110U, 19059U, 22495U, 19357U, 15364U, 18676U, + 23015U, 19565U, 24158U, 15339U, 20206U, 18668U, 24566U, 20215U, 20131U, + 13330U, 15261U, 18614U, 18091U, 2409U, 6357U, 23485U, 7341U, 656U, + 2666U, 6626U, 20376U, 23805U, 20037U, 7622U, 24524U, 24659U, 20256U, + 24531U, 61U, 24544U, 10352U, 12000U, 14459U, 25063U, 24073U, 20116U, + 7744U, 22246U, 19144U, 7111U, 13812U, 18196U, 6798U, 22872U, 17452U, + 5664U, 3279U, 10464U, 6854U, 19550U, 7090U, 24768U, 26790U, 3640U, + 20770U, 5148U, 11551U, +}; + +#endif // GET_INSTRINFO_MC_DESC diff --git a/arch/Mips/MipsGenInstrInfo.inc b/arch/Mips/MipsGenInstrInfo.inc deleted file mode 100644 index b6e8983edc..0000000000 --- a/arch/Mips/MipsGenInstrInfo.inc +++ /dev/null @@ -1,1805 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Target Instruction Enum Values *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ - - -#ifdef GET_INSTRINFO_ENUM -#undef GET_INSTRINFO_ENUM - -enum { - Mips_PHI = 0, - Mips_INLINEASM = 1, - Mips_CFI_INSTRUCTION = 2, - Mips_EH_LABEL = 3, - Mips_GC_LABEL = 4, - Mips_KILL = 5, - Mips_EXTRACT_SUBREG = 6, - Mips_INSERT_SUBREG = 7, - Mips_IMPLICIT_DEF = 8, - Mips_SUBREG_TO_REG = 9, - Mips_COPY_TO_REGCLASS = 10, - Mips_DBG_VALUE = 11, - Mips_REG_SEQUENCE = 12, - Mips_COPY = 13, - Mips_BUNDLE = 14, - Mips_LIFETIME_START = 15, - Mips_LIFETIME_END = 16, - Mips_STACKMAP = 17, - Mips_PATCHPOINT = 18, - Mips_LOAD_STACK_GUARD = 19, - Mips_STATEPOINT = 20, - Mips_FRAME_ALLOC = 21, - Mips_ABSQ_S_PH = 22, - Mips_ABSQ_S_QB = 23, - Mips_ABSQ_S_W = 24, - Mips_ADD = 25, - Mips_ADDIUPC = 26, - Mips_ADDIUPC_MM = 27, - Mips_ADDIUR1SP_MM = 28, - Mips_ADDIUR2_MM = 29, - Mips_ADDIUS5_MM = 30, - Mips_ADDIUSP_MM = 31, - Mips_ADDQH_PH = 32, - Mips_ADDQH_R_PH = 33, - Mips_ADDQH_R_W = 34, - Mips_ADDQH_W = 35, - Mips_ADDQ_PH = 36, - Mips_ADDQ_S_PH = 37, - Mips_ADDQ_S_W = 38, - Mips_ADDSC = 39, - Mips_ADDS_A_B = 40, - Mips_ADDS_A_D = 41, - Mips_ADDS_A_H = 42, - Mips_ADDS_A_W = 43, - Mips_ADDS_S_B = 44, - Mips_ADDS_S_D = 45, - Mips_ADDS_S_H = 46, - Mips_ADDS_S_W = 47, - Mips_ADDS_U_B = 48, - Mips_ADDS_U_D = 49, - Mips_ADDS_U_H = 50, - Mips_ADDS_U_W = 51, - Mips_ADDU16_MM = 52, - Mips_ADDUH_QB = 53, - Mips_ADDUH_R_QB = 54, - Mips_ADDU_PH = 55, - Mips_ADDU_QB = 56, - Mips_ADDU_S_PH = 57, - Mips_ADDU_S_QB = 58, - Mips_ADDVI_B = 59, - Mips_ADDVI_D = 60, - Mips_ADDVI_H = 61, - Mips_ADDVI_W = 62, - Mips_ADDV_B = 63, - Mips_ADDV_D = 64, - Mips_ADDV_H = 65, - Mips_ADDV_W = 66, - Mips_ADDWC = 67, - Mips_ADD_A_B = 68, - Mips_ADD_A_D = 69, - Mips_ADD_A_H = 70, - Mips_ADD_A_W = 71, - Mips_ADD_MM = 72, - Mips_ADDi = 73, - Mips_ADDi_MM = 74, - Mips_ADDiu = 75, - Mips_ADDiu_MM = 76, - Mips_ADDu = 77, - Mips_ADDu_MM = 78, - Mips_ADJCALLSTACKDOWN = 79, - Mips_ADJCALLSTACKUP = 80, - Mips_ALIGN = 81, - Mips_ALUIPC = 82, - Mips_AND = 83, - Mips_AND16_MM = 84, - Mips_AND64 = 85, - Mips_ANDI16_MM = 86, - Mips_ANDI_B = 87, - Mips_AND_MM = 88, - Mips_AND_V = 89, - Mips_AND_V_D_PSEUDO = 90, - Mips_AND_V_H_PSEUDO = 91, - Mips_AND_V_W_PSEUDO = 92, - Mips_ANDi = 93, - Mips_ANDi64 = 94, - Mips_ANDi_MM = 95, - Mips_APPEND = 96, - Mips_ASUB_S_B = 97, - Mips_ASUB_S_D = 98, - Mips_ASUB_S_H = 99, - Mips_ASUB_S_W = 100, - Mips_ASUB_U_B = 101, - Mips_ASUB_U_D = 102, - Mips_ASUB_U_H = 103, - Mips_ASUB_U_W = 104, - Mips_ATOMIC_CMP_SWAP_I16 = 105, - Mips_ATOMIC_CMP_SWAP_I32 = 106, - Mips_ATOMIC_CMP_SWAP_I64 = 107, - Mips_ATOMIC_CMP_SWAP_I8 = 108, - Mips_ATOMIC_LOAD_ADD_I16 = 109, - Mips_ATOMIC_LOAD_ADD_I32 = 110, - Mips_ATOMIC_LOAD_ADD_I64 = 111, - Mips_ATOMIC_LOAD_ADD_I8 = 112, - Mips_ATOMIC_LOAD_AND_I16 = 113, - Mips_ATOMIC_LOAD_AND_I32 = 114, - Mips_ATOMIC_LOAD_AND_I64 = 115, - Mips_ATOMIC_LOAD_AND_I8 = 116, - Mips_ATOMIC_LOAD_NAND_I16 = 117, - Mips_ATOMIC_LOAD_NAND_I32 = 118, - Mips_ATOMIC_LOAD_NAND_I64 = 119, - Mips_ATOMIC_LOAD_NAND_I8 = 120, - Mips_ATOMIC_LOAD_OR_I16 = 121, - Mips_ATOMIC_LOAD_OR_I32 = 122, - Mips_ATOMIC_LOAD_OR_I64 = 123, - Mips_ATOMIC_LOAD_OR_I8 = 124, - Mips_ATOMIC_LOAD_SUB_I16 = 125, - Mips_ATOMIC_LOAD_SUB_I32 = 126, - Mips_ATOMIC_LOAD_SUB_I64 = 127, - Mips_ATOMIC_LOAD_SUB_I8 = 128, - Mips_ATOMIC_LOAD_XOR_I16 = 129, - Mips_ATOMIC_LOAD_XOR_I32 = 130, - Mips_ATOMIC_LOAD_XOR_I64 = 131, - Mips_ATOMIC_LOAD_XOR_I8 = 132, - Mips_ATOMIC_SWAP_I16 = 133, - Mips_ATOMIC_SWAP_I32 = 134, - Mips_ATOMIC_SWAP_I64 = 135, - Mips_ATOMIC_SWAP_I8 = 136, - Mips_AUI = 137, - Mips_AUIPC = 138, - Mips_AVER_S_B = 139, - Mips_AVER_S_D = 140, - Mips_AVER_S_H = 141, - Mips_AVER_S_W = 142, - Mips_AVER_U_B = 143, - Mips_AVER_U_D = 144, - Mips_AVER_U_H = 145, - Mips_AVER_U_W = 146, - Mips_AVE_S_B = 147, - Mips_AVE_S_D = 148, - Mips_AVE_S_H = 149, - Mips_AVE_S_W = 150, - Mips_AVE_U_B = 151, - Mips_AVE_U_D = 152, - Mips_AVE_U_H = 153, - Mips_AVE_U_W = 154, - Mips_AddiuRxImmX16 = 155, - Mips_AddiuRxPcImmX16 = 156, - Mips_AddiuRxRxImm16 = 157, - Mips_AddiuRxRxImmX16 = 158, - Mips_AddiuRxRyOffMemX16 = 159, - Mips_AddiuSpImm16 = 160, - Mips_AddiuSpImmX16 = 161, - Mips_AdduRxRyRz16 = 162, - Mips_AndRxRxRy16 = 163, - Mips_B = 164, - Mips_B16_MM = 165, - Mips_BADDu = 166, - Mips_BAL = 167, - Mips_BALC = 168, - Mips_BALIGN = 169, - Mips_BAL_BR = 170, - Mips_BBIT0 = 171, - Mips_BBIT032 = 172, - Mips_BBIT1 = 173, - Mips_BBIT132 = 174, - Mips_BC = 175, - Mips_BC0F = 176, - Mips_BC0FL = 177, - Mips_BC0T = 178, - Mips_BC0TL = 179, - Mips_BC1EQZ = 180, - Mips_BC1F = 181, - Mips_BC1FL = 182, - Mips_BC1F_MM = 183, - Mips_BC1NEZ = 184, - Mips_BC1T = 185, - Mips_BC1TL = 186, - Mips_BC1T_MM = 187, - Mips_BC2EQZ = 188, - Mips_BC2F = 189, - Mips_BC2FL = 190, - Mips_BC2NEZ = 191, - Mips_BC2T = 192, - Mips_BC2TL = 193, - Mips_BC3F = 194, - Mips_BC3FL = 195, - Mips_BC3T = 196, - Mips_BC3TL = 197, - Mips_BCLRI_B = 198, - Mips_BCLRI_D = 199, - Mips_BCLRI_H = 200, - Mips_BCLRI_W = 201, - Mips_BCLR_B = 202, - Mips_BCLR_D = 203, - Mips_BCLR_H = 204, - Mips_BCLR_W = 205, - Mips_BEQ = 206, - Mips_BEQ64 = 207, - Mips_BEQC = 208, - Mips_BEQL = 209, - Mips_BEQZ16_MM = 210, - Mips_BEQZALC = 211, - Mips_BEQZC = 212, - Mips_BEQZC_MM = 213, - Mips_BEQ_MM = 214, - Mips_BGEC = 215, - Mips_BGEUC = 216, - Mips_BGEZ = 217, - Mips_BGEZ64 = 218, - Mips_BGEZAL = 219, - Mips_BGEZALC = 220, - Mips_BGEZALL = 221, - Mips_BGEZALS_MM = 222, - Mips_BGEZAL_MM = 223, - Mips_BGEZC = 224, - Mips_BGEZL = 225, - Mips_BGEZ_MM = 226, - Mips_BGTZ = 227, - Mips_BGTZ64 = 228, - Mips_BGTZALC = 229, - Mips_BGTZC = 230, - Mips_BGTZL = 231, - Mips_BGTZ_MM = 232, - Mips_BINSLI_B = 233, - Mips_BINSLI_D = 234, - Mips_BINSLI_H = 235, - Mips_BINSLI_W = 236, - Mips_BINSL_B = 237, - Mips_BINSL_D = 238, - Mips_BINSL_H = 239, - Mips_BINSL_W = 240, - Mips_BINSRI_B = 241, - Mips_BINSRI_D = 242, - Mips_BINSRI_H = 243, - Mips_BINSRI_W = 244, - Mips_BINSR_B = 245, - Mips_BINSR_D = 246, - Mips_BINSR_H = 247, - Mips_BINSR_W = 248, - Mips_BITREV = 249, - Mips_BITSWAP = 250, - Mips_BLEZ = 251, - Mips_BLEZ64 = 252, - Mips_BLEZALC = 253, - Mips_BLEZC = 254, - Mips_BLEZL = 255, - Mips_BLEZ_MM = 256, - Mips_BLTC = 257, - Mips_BLTUC = 258, - Mips_BLTZ = 259, - Mips_BLTZ64 = 260, - Mips_BLTZAL = 261, - Mips_BLTZALC = 262, - Mips_BLTZALL = 263, - Mips_BLTZALS_MM = 264, - Mips_BLTZAL_MM = 265, - Mips_BLTZC = 266, - Mips_BLTZL = 267, - Mips_BLTZ_MM = 268, - Mips_BMNZI_B = 269, - Mips_BMNZ_V = 270, - Mips_BMZI_B = 271, - Mips_BMZ_V = 272, - Mips_BNE = 273, - Mips_BNE64 = 274, - Mips_BNEC = 275, - Mips_BNEGI_B = 276, - Mips_BNEGI_D = 277, - Mips_BNEGI_H = 278, - Mips_BNEGI_W = 279, - Mips_BNEG_B = 280, - Mips_BNEG_D = 281, - Mips_BNEG_H = 282, - Mips_BNEG_W = 283, - Mips_BNEL = 284, - Mips_BNEZ16_MM = 285, - Mips_BNEZALC = 286, - Mips_BNEZC = 287, - Mips_BNEZC_MM = 288, - Mips_BNE_MM = 289, - Mips_BNVC = 290, - Mips_BNZ_B = 291, - Mips_BNZ_D = 292, - Mips_BNZ_H = 293, - Mips_BNZ_V = 294, - Mips_BNZ_W = 295, - Mips_BOVC = 296, - Mips_BPOSGE32 = 297, - Mips_BPOSGE32_PSEUDO = 298, - Mips_BREAK = 299, - Mips_BREAK16_MM = 300, - Mips_BREAK_MM = 301, - Mips_BSELI_B = 302, - Mips_BSEL_D_PSEUDO = 303, - Mips_BSEL_FD_PSEUDO = 304, - Mips_BSEL_FW_PSEUDO = 305, - Mips_BSEL_H_PSEUDO = 306, - Mips_BSEL_V = 307, - Mips_BSEL_W_PSEUDO = 308, - Mips_BSETI_B = 309, - Mips_BSETI_D = 310, - Mips_BSETI_H = 311, - Mips_BSETI_W = 312, - Mips_BSET_B = 313, - Mips_BSET_D = 314, - Mips_BSET_H = 315, - Mips_BSET_W = 316, - Mips_BZ_B = 317, - Mips_BZ_D = 318, - Mips_BZ_H = 319, - Mips_BZ_V = 320, - Mips_BZ_W = 321, - Mips_B_MM_Pseudo = 322, - Mips_BeqzRxImm16 = 323, - Mips_BeqzRxImmX16 = 324, - Mips_Bimm16 = 325, - Mips_BimmX16 = 326, - Mips_BnezRxImm16 = 327, - Mips_BnezRxImmX16 = 328, - Mips_Break16 = 329, - Mips_Bteqz16 = 330, - Mips_BteqzT8CmpX16 = 331, - Mips_BteqzT8CmpiX16 = 332, - Mips_BteqzT8SltX16 = 333, - Mips_BteqzT8SltiX16 = 334, - Mips_BteqzT8SltiuX16 = 335, - Mips_BteqzT8SltuX16 = 336, - Mips_BteqzX16 = 337, - Mips_Btnez16 = 338, - Mips_BtnezT8CmpX16 = 339, - Mips_BtnezT8CmpiX16 = 340, - Mips_BtnezT8SltX16 = 341, - Mips_BtnezT8SltiX16 = 342, - Mips_BtnezT8SltiuX16 = 343, - Mips_BtnezT8SltuX16 = 344, - Mips_BtnezX16 = 345, - Mips_BuildPairF64 = 346, - Mips_BuildPairF64_64 = 347, - Mips_CACHE = 348, - Mips_CACHE_MM = 349, - Mips_CACHE_R6 = 350, - Mips_CEIL_L_D64 = 351, - Mips_CEIL_L_S = 352, - Mips_CEIL_W_D32 = 353, - Mips_CEIL_W_D64 = 354, - Mips_CEIL_W_MM = 355, - Mips_CEIL_W_S = 356, - Mips_CEIL_W_S_MM = 357, - Mips_CEQI_B = 358, - Mips_CEQI_D = 359, - Mips_CEQI_H = 360, - Mips_CEQI_W = 361, - Mips_CEQ_B = 362, - Mips_CEQ_D = 363, - Mips_CEQ_H = 364, - Mips_CEQ_W = 365, - Mips_CFC1 = 366, - Mips_CFC1_MM = 367, - Mips_CFCMSA = 368, - Mips_CINS = 369, - Mips_CINS32 = 370, - Mips_CLASS_D = 371, - Mips_CLASS_S = 372, - Mips_CLEI_S_B = 373, - Mips_CLEI_S_D = 374, - Mips_CLEI_S_H = 375, - Mips_CLEI_S_W = 376, - Mips_CLEI_U_B = 377, - Mips_CLEI_U_D = 378, - Mips_CLEI_U_H = 379, - Mips_CLEI_U_W = 380, - Mips_CLE_S_B = 381, - Mips_CLE_S_D = 382, - Mips_CLE_S_H = 383, - Mips_CLE_S_W = 384, - Mips_CLE_U_B = 385, - Mips_CLE_U_D = 386, - Mips_CLE_U_H = 387, - Mips_CLE_U_W = 388, - Mips_CLO = 389, - Mips_CLO_MM = 390, - Mips_CLO_R6 = 391, - Mips_CLTI_S_B = 392, - Mips_CLTI_S_D = 393, - Mips_CLTI_S_H = 394, - Mips_CLTI_S_W = 395, - Mips_CLTI_U_B = 396, - Mips_CLTI_U_D = 397, - Mips_CLTI_U_H = 398, - Mips_CLTI_U_W = 399, - Mips_CLT_S_B = 400, - Mips_CLT_S_D = 401, - Mips_CLT_S_H = 402, - Mips_CLT_S_W = 403, - Mips_CLT_U_B = 404, - Mips_CLT_U_D = 405, - Mips_CLT_U_H = 406, - Mips_CLT_U_W = 407, - Mips_CLZ = 408, - Mips_CLZ_MM = 409, - Mips_CLZ_R6 = 410, - Mips_CMPGDU_EQ_QB = 411, - Mips_CMPGDU_LE_QB = 412, - Mips_CMPGDU_LT_QB = 413, - Mips_CMPGU_EQ_QB = 414, - Mips_CMPGU_LE_QB = 415, - Mips_CMPGU_LT_QB = 416, - Mips_CMPU_EQ_QB = 417, - Mips_CMPU_LE_QB = 418, - Mips_CMPU_LT_QB = 419, - Mips_CMP_EQ_D = 420, - Mips_CMP_EQ_PH = 421, - Mips_CMP_EQ_S = 422, - Mips_CMP_F_D = 423, - Mips_CMP_F_S = 424, - Mips_CMP_LE_D = 425, - Mips_CMP_LE_PH = 426, - Mips_CMP_LE_S = 427, - Mips_CMP_LT_D = 428, - Mips_CMP_LT_PH = 429, - Mips_CMP_LT_S = 430, - Mips_CMP_SAF_D = 431, - Mips_CMP_SAF_S = 432, - Mips_CMP_SEQ_D = 433, - Mips_CMP_SEQ_S = 434, - Mips_CMP_SLE_D = 435, - Mips_CMP_SLE_S = 436, - Mips_CMP_SLT_D = 437, - Mips_CMP_SLT_S = 438, - Mips_CMP_SUEQ_D = 439, - Mips_CMP_SUEQ_S = 440, - Mips_CMP_SULE_D = 441, - Mips_CMP_SULE_S = 442, - Mips_CMP_SULT_D = 443, - Mips_CMP_SULT_S = 444, - Mips_CMP_SUN_D = 445, - Mips_CMP_SUN_S = 446, - Mips_CMP_UEQ_D = 447, - Mips_CMP_UEQ_S = 448, - Mips_CMP_ULE_D = 449, - Mips_CMP_ULE_S = 450, - Mips_CMP_ULT_D = 451, - Mips_CMP_ULT_S = 452, - Mips_CMP_UN_D = 453, - Mips_CMP_UN_S = 454, - Mips_CONSTPOOL_ENTRY = 455, - Mips_COPY_FD_PSEUDO = 456, - Mips_COPY_FW_PSEUDO = 457, - Mips_COPY_S_B = 458, - Mips_COPY_S_D = 459, - Mips_COPY_S_H = 460, - Mips_COPY_S_W = 461, - Mips_COPY_U_B = 462, - Mips_COPY_U_D = 463, - Mips_COPY_U_H = 464, - Mips_COPY_U_W = 465, - Mips_CTC1 = 466, - Mips_CTC1_MM = 467, - Mips_CTCMSA = 468, - Mips_CVT_D32_S = 469, - Mips_CVT_D32_W = 470, - Mips_CVT_D32_W_MM = 471, - Mips_CVT_D64_L = 472, - Mips_CVT_D64_S = 473, - Mips_CVT_D64_W = 474, - Mips_CVT_D_S_MM = 475, - Mips_CVT_L_D64 = 476, - Mips_CVT_L_D64_MM = 477, - Mips_CVT_L_S = 478, - Mips_CVT_L_S_MM = 479, - Mips_CVT_S_D32 = 480, - Mips_CVT_S_D32_MM = 481, - Mips_CVT_S_D64 = 482, - Mips_CVT_S_L = 483, - Mips_CVT_S_W = 484, - Mips_CVT_S_W_MM = 485, - Mips_CVT_W_D32 = 486, - Mips_CVT_W_D64 = 487, - Mips_CVT_W_MM = 488, - Mips_CVT_W_S = 489, - Mips_CVT_W_S_MM = 490, - Mips_C_EQ_D32 = 491, - Mips_C_EQ_D64 = 492, - Mips_C_EQ_S = 493, - Mips_C_F_D32 = 494, - Mips_C_F_D64 = 495, - Mips_C_F_S = 496, - Mips_C_LE_D32 = 497, - Mips_C_LE_D64 = 498, - Mips_C_LE_S = 499, - Mips_C_LT_D32 = 500, - Mips_C_LT_D64 = 501, - Mips_C_LT_S = 502, - Mips_C_NGE_D32 = 503, - Mips_C_NGE_D64 = 504, - Mips_C_NGE_S = 505, - Mips_C_NGLE_D32 = 506, - Mips_C_NGLE_D64 = 507, - Mips_C_NGLE_S = 508, - Mips_C_NGL_D32 = 509, - Mips_C_NGL_D64 = 510, - Mips_C_NGL_S = 511, - Mips_C_NGT_D32 = 512, - Mips_C_NGT_D64 = 513, - Mips_C_NGT_S = 514, - Mips_C_OLE_D32 = 515, - Mips_C_OLE_D64 = 516, - Mips_C_OLE_S = 517, - Mips_C_OLT_D32 = 518, - Mips_C_OLT_D64 = 519, - Mips_C_OLT_S = 520, - Mips_C_SEQ_D32 = 521, - Mips_C_SEQ_D64 = 522, - Mips_C_SEQ_S = 523, - Mips_C_SF_D32 = 524, - Mips_C_SF_D64 = 525, - Mips_C_SF_S = 526, - Mips_C_UEQ_D32 = 527, - Mips_C_UEQ_D64 = 528, - Mips_C_UEQ_S = 529, - Mips_C_ULE_D32 = 530, - Mips_C_ULE_D64 = 531, - Mips_C_ULE_S = 532, - Mips_C_ULT_D32 = 533, - Mips_C_ULT_D64 = 534, - Mips_C_ULT_S = 535, - Mips_C_UN_D32 = 536, - Mips_C_UN_D64 = 537, - Mips_C_UN_S = 538, - Mips_CmpRxRy16 = 539, - Mips_CmpiRxImm16 = 540, - Mips_CmpiRxImmX16 = 541, - Mips_Constant32 = 542, - Mips_DADD = 543, - Mips_DADDi = 544, - Mips_DADDiu = 545, - Mips_DADDu = 546, - Mips_DAHI = 547, - Mips_DALIGN = 548, - Mips_DATI = 549, - Mips_DAUI = 550, - Mips_DBITSWAP = 551, - Mips_DCLO = 552, - Mips_DCLO_R6 = 553, - Mips_DCLZ = 554, - Mips_DCLZ_R6 = 555, - Mips_DDIV = 556, - Mips_DDIVU = 557, - Mips_DERET = 558, - Mips_DERET_MM = 559, - Mips_DEXT = 560, - Mips_DEXTM = 561, - Mips_DEXTU = 562, - Mips_DI = 563, - Mips_DINS = 564, - Mips_DINSM = 565, - Mips_DINSU = 566, - Mips_DIV = 567, - Mips_DIVU = 568, - Mips_DIV_S_B = 569, - Mips_DIV_S_D = 570, - Mips_DIV_S_H = 571, - Mips_DIV_S_W = 572, - Mips_DIV_U_B = 573, - Mips_DIV_U_D = 574, - Mips_DIV_U_H = 575, - Mips_DIV_U_W = 576, - Mips_DI_MM = 577, - Mips_DLSA = 578, - Mips_DLSA_R6 = 579, - Mips_DMFC0 = 580, - Mips_DMFC1 = 581, - Mips_DMFC2 = 582, - Mips_DMOD = 583, - Mips_DMODU = 584, - Mips_DMTC0 = 585, - Mips_DMTC1 = 586, - Mips_DMTC2 = 587, - Mips_DMUH = 588, - Mips_DMUHU = 589, - Mips_DMUL = 590, - Mips_DMULT = 591, - Mips_DMULTu = 592, - Mips_DMULU = 593, - Mips_DMUL_R6 = 594, - Mips_DOTP_S_D = 595, - Mips_DOTP_S_H = 596, - Mips_DOTP_S_W = 597, - Mips_DOTP_U_D = 598, - Mips_DOTP_U_H = 599, - Mips_DOTP_U_W = 600, - Mips_DPADD_S_D = 601, - Mips_DPADD_S_H = 602, - Mips_DPADD_S_W = 603, - Mips_DPADD_U_D = 604, - Mips_DPADD_U_H = 605, - Mips_DPADD_U_W = 606, - Mips_DPAQX_SA_W_PH = 607, - Mips_DPAQX_S_W_PH = 608, - Mips_DPAQ_SA_L_W = 609, - Mips_DPAQ_S_W_PH = 610, - Mips_DPAU_H_QBL = 611, - Mips_DPAU_H_QBR = 612, - Mips_DPAX_W_PH = 613, - Mips_DPA_W_PH = 614, - Mips_DPOP = 615, - Mips_DPSQX_SA_W_PH = 616, - Mips_DPSQX_S_W_PH = 617, - Mips_DPSQ_SA_L_W = 618, - Mips_DPSQ_S_W_PH = 619, - Mips_DPSUB_S_D = 620, - Mips_DPSUB_S_H = 621, - Mips_DPSUB_S_W = 622, - Mips_DPSUB_U_D = 623, - Mips_DPSUB_U_H = 624, - Mips_DPSUB_U_W = 625, - Mips_DPSU_H_QBL = 626, - Mips_DPSU_H_QBR = 627, - Mips_DPSX_W_PH = 628, - Mips_DPS_W_PH = 629, - Mips_DROTR = 630, - Mips_DROTR32 = 631, - Mips_DROTRV = 632, - Mips_DSBH = 633, - Mips_DSDIV = 634, - Mips_DSHD = 635, - Mips_DSLL = 636, - Mips_DSLL32 = 637, - Mips_DSLL64_32 = 638, - Mips_DSLLV = 639, - Mips_DSRA = 640, - Mips_DSRA32 = 641, - Mips_DSRAV = 642, - Mips_DSRL = 643, - Mips_DSRL32 = 644, - Mips_DSRLV = 645, - Mips_DSUB = 646, - Mips_DSUBu = 647, - Mips_DUDIV = 648, - Mips_DivRxRy16 = 649, - Mips_DivuRxRy16 = 650, - Mips_EHB = 651, - Mips_EHB_MM = 652, - Mips_EI = 653, - Mips_EI_MM = 654, - Mips_ERET = 655, - Mips_ERET_MM = 656, - Mips_EXT = 657, - Mips_EXTP = 658, - Mips_EXTPDP = 659, - Mips_EXTPDPV = 660, - Mips_EXTPV = 661, - Mips_EXTRV_RS_W = 662, - Mips_EXTRV_R_W = 663, - Mips_EXTRV_S_H = 664, - Mips_EXTRV_W = 665, - Mips_EXTR_RS_W = 666, - Mips_EXTR_R_W = 667, - Mips_EXTR_S_H = 668, - Mips_EXTR_W = 669, - Mips_EXTS = 670, - Mips_EXTS32 = 671, - Mips_EXT_MM = 672, - Mips_ExtractElementF64 = 673, - Mips_ExtractElementF64_64 = 674, - Mips_FABS_D = 675, - Mips_FABS_D32 = 676, - Mips_FABS_D64 = 677, - Mips_FABS_MM = 678, - Mips_FABS_S = 679, - Mips_FABS_S_MM = 680, - Mips_FABS_W = 681, - Mips_FADD_D = 682, - Mips_FADD_D32 = 683, - Mips_FADD_D64 = 684, - Mips_FADD_MM = 685, - Mips_FADD_S = 686, - Mips_FADD_S_MM = 687, - Mips_FADD_W = 688, - Mips_FCAF_D = 689, - Mips_FCAF_W = 690, - Mips_FCEQ_D = 691, - Mips_FCEQ_W = 692, - Mips_FCLASS_D = 693, - Mips_FCLASS_W = 694, - Mips_FCLE_D = 695, - Mips_FCLE_W = 696, - Mips_FCLT_D = 697, - Mips_FCLT_W = 698, - Mips_FCMP_D32 = 699, - Mips_FCMP_D32_MM = 700, - Mips_FCMP_D64 = 701, - Mips_FCMP_S32 = 702, - Mips_FCMP_S32_MM = 703, - Mips_FCNE_D = 704, - Mips_FCNE_W = 705, - Mips_FCOR_D = 706, - Mips_FCOR_W = 707, - Mips_FCUEQ_D = 708, - Mips_FCUEQ_W = 709, - Mips_FCULE_D = 710, - Mips_FCULE_W = 711, - Mips_FCULT_D = 712, - Mips_FCULT_W = 713, - Mips_FCUNE_D = 714, - Mips_FCUNE_W = 715, - Mips_FCUN_D = 716, - Mips_FCUN_W = 717, - Mips_FDIV_D = 718, - Mips_FDIV_D32 = 719, - Mips_FDIV_D64 = 720, - Mips_FDIV_MM = 721, - Mips_FDIV_S = 722, - Mips_FDIV_S_MM = 723, - Mips_FDIV_W = 724, - Mips_FEXDO_H = 725, - Mips_FEXDO_W = 726, - Mips_FEXP2_D = 727, - Mips_FEXP2_D_1_PSEUDO = 728, - Mips_FEXP2_W = 729, - Mips_FEXP2_W_1_PSEUDO = 730, - Mips_FEXUPL_D = 731, - Mips_FEXUPL_W = 732, - Mips_FEXUPR_D = 733, - Mips_FEXUPR_W = 734, - Mips_FFINT_S_D = 735, - Mips_FFINT_S_W = 736, - Mips_FFINT_U_D = 737, - Mips_FFINT_U_W = 738, - Mips_FFQL_D = 739, - Mips_FFQL_W = 740, - Mips_FFQR_D = 741, - Mips_FFQR_W = 742, - Mips_FILL_B = 743, - Mips_FILL_D = 744, - Mips_FILL_FD_PSEUDO = 745, - Mips_FILL_FW_PSEUDO = 746, - Mips_FILL_H = 747, - Mips_FILL_W = 748, - Mips_FLOG2_D = 749, - Mips_FLOG2_W = 750, - Mips_FLOOR_L_D64 = 751, - Mips_FLOOR_L_S = 752, - Mips_FLOOR_W_D32 = 753, - Mips_FLOOR_W_D64 = 754, - Mips_FLOOR_W_MM = 755, - Mips_FLOOR_W_S = 756, - Mips_FLOOR_W_S_MM = 757, - Mips_FMADD_D = 758, - Mips_FMADD_W = 759, - Mips_FMAX_A_D = 760, - Mips_FMAX_A_W = 761, - Mips_FMAX_D = 762, - Mips_FMAX_W = 763, - Mips_FMIN_A_D = 764, - Mips_FMIN_A_W = 765, - Mips_FMIN_D = 766, - Mips_FMIN_W = 767, - Mips_FMOV_D32 = 768, - Mips_FMOV_D32_MM = 769, - Mips_FMOV_D64 = 770, - Mips_FMOV_S = 771, - Mips_FMOV_S_MM = 772, - Mips_FMSUB_D = 773, - Mips_FMSUB_W = 774, - Mips_FMUL_D = 775, - Mips_FMUL_D32 = 776, - Mips_FMUL_D64 = 777, - Mips_FMUL_MM = 778, - Mips_FMUL_S = 779, - Mips_FMUL_S_MM = 780, - Mips_FMUL_W = 781, - Mips_FNEG_D32 = 782, - Mips_FNEG_D64 = 783, - Mips_FNEG_MM = 784, - Mips_FNEG_S = 785, - Mips_FNEG_S_MM = 786, - Mips_FRCP_D = 787, - Mips_FRCP_W = 788, - Mips_FRINT_D = 789, - Mips_FRINT_W = 790, - Mips_FRSQRT_D = 791, - Mips_FRSQRT_W = 792, - Mips_FSAF_D = 793, - Mips_FSAF_W = 794, - Mips_FSEQ_D = 795, - Mips_FSEQ_W = 796, - Mips_FSLE_D = 797, - Mips_FSLE_W = 798, - Mips_FSLT_D = 799, - Mips_FSLT_W = 800, - Mips_FSNE_D = 801, - Mips_FSNE_W = 802, - Mips_FSOR_D = 803, - Mips_FSOR_W = 804, - Mips_FSQRT_D = 805, - Mips_FSQRT_D32 = 806, - Mips_FSQRT_D64 = 807, - Mips_FSQRT_MM = 808, - Mips_FSQRT_S = 809, - Mips_FSQRT_S_MM = 810, - Mips_FSQRT_W = 811, - Mips_FSUB_D = 812, - Mips_FSUB_D32 = 813, - Mips_FSUB_D64 = 814, - Mips_FSUB_MM = 815, - Mips_FSUB_S = 816, - Mips_FSUB_S_MM = 817, - Mips_FSUB_W = 818, - Mips_FSUEQ_D = 819, - Mips_FSUEQ_W = 820, - Mips_FSULE_D = 821, - Mips_FSULE_W = 822, - Mips_FSULT_D = 823, - Mips_FSULT_W = 824, - Mips_FSUNE_D = 825, - Mips_FSUNE_W = 826, - Mips_FSUN_D = 827, - Mips_FSUN_W = 828, - Mips_FTINT_S_D = 829, - Mips_FTINT_S_W = 830, - Mips_FTINT_U_D = 831, - Mips_FTINT_U_W = 832, - Mips_FTQ_H = 833, - Mips_FTQ_W = 834, - Mips_FTRUNC_S_D = 835, - Mips_FTRUNC_S_W = 836, - Mips_FTRUNC_U_D = 837, - Mips_FTRUNC_U_W = 838, - Mips_GotPrologue16 = 839, - Mips_HADD_S_D = 840, - Mips_HADD_S_H = 841, - Mips_HADD_S_W = 842, - Mips_HADD_U_D = 843, - Mips_HADD_U_H = 844, - Mips_HADD_U_W = 845, - Mips_HSUB_S_D = 846, - Mips_HSUB_S_H = 847, - Mips_HSUB_S_W = 848, - Mips_HSUB_U_D = 849, - Mips_HSUB_U_H = 850, - Mips_HSUB_U_W = 851, - Mips_ILVEV_B = 852, - Mips_ILVEV_D = 853, - Mips_ILVEV_H = 854, - Mips_ILVEV_W = 855, - Mips_ILVL_B = 856, - Mips_ILVL_D = 857, - Mips_ILVL_H = 858, - Mips_ILVL_W = 859, - Mips_ILVOD_B = 860, - Mips_ILVOD_D = 861, - Mips_ILVOD_H = 862, - Mips_ILVOD_W = 863, - Mips_ILVR_B = 864, - Mips_ILVR_D = 865, - Mips_ILVR_H = 866, - Mips_ILVR_W = 867, - Mips_INS = 868, - Mips_INSERT_B = 869, - Mips_INSERT_B_VIDX_PSEUDO = 870, - Mips_INSERT_D = 871, - Mips_INSERT_D_VIDX_PSEUDO = 872, - Mips_INSERT_FD_PSEUDO = 873, - Mips_INSERT_FD_VIDX_PSEUDO = 874, - Mips_INSERT_FW_PSEUDO = 875, - Mips_INSERT_FW_VIDX_PSEUDO = 876, - Mips_INSERT_H = 877, - Mips_INSERT_H_VIDX_PSEUDO = 878, - Mips_INSERT_W = 879, - Mips_INSERT_W_VIDX_PSEUDO = 880, - Mips_INSV = 881, - Mips_INSVE_B = 882, - Mips_INSVE_D = 883, - Mips_INSVE_H = 884, - Mips_INSVE_W = 885, - Mips_INS_MM = 886, - Mips_J = 887, - Mips_JAL = 888, - Mips_JALR = 889, - Mips_JALR16_MM = 890, - Mips_JALR64 = 891, - Mips_JALR64Pseudo = 892, - Mips_JALRPseudo = 893, - Mips_JALRS16_MM = 894, - Mips_JALRS_MM = 895, - Mips_JALR_HB = 896, - Mips_JALR_MM = 897, - Mips_JALS_MM = 898, - Mips_JALX = 899, - Mips_JALX_MM = 900, - Mips_JAL_MM = 901, - Mips_JIALC = 902, - Mips_JIC = 903, - Mips_JR = 904, - Mips_JR16_MM = 905, - Mips_JR64 = 906, - Mips_JRADDIUSP = 907, - Mips_JRC16_MM = 908, - Mips_JR_HB = 909, - Mips_JR_HB_R6 = 910, - Mips_JR_MM = 911, - Mips_J_MM = 912, - Mips_Jal16 = 913, - Mips_JalB16 = 914, - Mips_JalOneReg = 915, - Mips_JalTwoReg = 916, - Mips_JrRa16 = 917, - Mips_JrcRa16 = 918, - Mips_JrcRx16 = 919, - Mips_JumpLinkReg16 = 920, - Mips_LB = 921, - Mips_LB64 = 922, - Mips_LBU16_MM = 923, - Mips_LBUX = 924, - Mips_LB_MM = 925, - Mips_LBu = 926, - Mips_LBu64 = 927, - Mips_LBu_MM = 928, - Mips_LD = 929, - Mips_LDC1 = 930, - Mips_LDC164 = 931, - Mips_LDC1_MM = 932, - Mips_LDC2 = 933, - Mips_LDC2_R6 = 934, - Mips_LDC3 = 935, - Mips_LDI_B = 936, - Mips_LDI_D = 937, - Mips_LDI_H = 938, - Mips_LDI_W = 939, - Mips_LDL = 940, - Mips_LDPC = 941, - Mips_LDR = 942, - Mips_LDXC1 = 943, - Mips_LDXC164 = 944, - Mips_LD_B = 945, - Mips_LD_D = 946, - Mips_LD_H = 947, - Mips_LD_W = 948, - Mips_LEA_ADDiu = 949, - Mips_LEA_ADDiu64 = 950, - Mips_LEA_ADDiu_MM = 951, - Mips_LH = 952, - Mips_LH64 = 953, - Mips_LHU16_MM = 954, - Mips_LHX = 955, - Mips_LH_MM = 956, - Mips_LHu = 957, - Mips_LHu64 = 958, - Mips_LHu_MM = 959, - Mips_LI16_MM = 960, - Mips_LL = 961, - Mips_LLD = 962, - Mips_LLD_R6 = 963, - Mips_LL_MM = 964, - Mips_LL_R6 = 965, - Mips_LOAD_ACC128 = 966, - Mips_LOAD_ACC64 = 967, - Mips_LOAD_ACC64DSP = 968, - Mips_LOAD_CCOND_DSP = 969, - Mips_LONG_BRANCH_ADDiu = 970, - Mips_LONG_BRANCH_DADDiu = 971, - Mips_LONG_BRANCH_LUi = 972, - Mips_LSA = 973, - Mips_LSA_R6 = 974, - Mips_LUXC1 = 975, - Mips_LUXC164 = 976, - Mips_LUXC1_MM = 977, - Mips_LUi = 978, - Mips_LUi64 = 979, - Mips_LUi_MM = 980, - Mips_LW = 981, - Mips_LW16_MM = 982, - Mips_LW64 = 983, - Mips_LWC1 = 984, - Mips_LWC1_MM = 985, - Mips_LWC2 = 986, - Mips_LWC2_R6 = 987, - Mips_LWC3 = 988, - Mips_LWGP_MM = 989, - Mips_LWL = 990, - Mips_LWL64 = 991, - Mips_LWL_MM = 992, - Mips_LWM16_MM = 993, - Mips_LWM32_MM = 994, - Mips_LWM_MM = 995, - Mips_LWPC = 996, - Mips_LWP_MM = 997, - Mips_LWR = 998, - Mips_LWR64 = 999, - Mips_LWR_MM = 1000, - Mips_LWSP_MM = 1001, - Mips_LWUPC = 1002, - Mips_LWU_MM = 1003, - Mips_LWX = 1004, - Mips_LWXC1 = 1005, - Mips_LWXC1_MM = 1006, - Mips_LWXS_MM = 1007, - Mips_LW_MM = 1008, - Mips_LWu = 1009, - Mips_LbRxRyOffMemX16 = 1010, - Mips_LbuRxRyOffMemX16 = 1011, - Mips_LhRxRyOffMemX16 = 1012, - Mips_LhuRxRyOffMemX16 = 1013, - Mips_LiRxImm16 = 1014, - Mips_LiRxImmAlignX16 = 1015, - Mips_LiRxImmX16 = 1016, - Mips_LoadAddr32Imm = 1017, - Mips_LoadAddr32Reg = 1018, - Mips_LoadImm32Reg = 1019, - Mips_LoadImm64Reg = 1020, - Mips_LwConstant32 = 1021, - Mips_LwRxPcTcp16 = 1022, - Mips_LwRxPcTcpX16 = 1023, - Mips_LwRxRyOffMemX16 = 1024, - Mips_LwRxSpImmX16 = 1025, - Mips_MADD = 1026, - Mips_MADDF_D = 1027, - Mips_MADDF_S = 1028, - Mips_MADDR_Q_H = 1029, - Mips_MADDR_Q_W = 1030, - Mips_MADDU = 1031, - Mips_MADDU_DSP = 1032, - Mips_MADDU_MM = 1033, - Mips_MADDV_B = 1034, - Mips_MADDV_D = 1035, - Mips_MADDV_H = 1036, - Mips_MADDV_W = 1037, - Mips_MADD_D32 = 1038, - Mips_MADD_D32_MM = 1039, - Mips_MADD_D64 = 1040, - Mips_MADD_DSP = 1041, - Mips_MADD_MM = 1042, - Mips_MADD_Q_H = 1043, - Mips_MADD_Q_W = 1044, - Mips_MADD_S = 1045, - Mips_MADD_S_MM = 1046, - Mips_MAQ_SA_W_PHL = 1047, - Mips_MAQ_SA_W_PHR = 1048, - Mips_MAQ_S_W_PHL = 1049, - Mips_MAQ_S_W_PHR = 1050, - Mips_MAXA_D = 1051, - Mips_MAXA_S = 1052, - Mips_MAXI_S_B = 1053, - Mips_MAXI_S_D = 1054, - Mips_MAXI_S_H = 1055, - Mips_MAXI_S_W = 1056, - Mips_MAXI_U_B = 1057, - Mips_MAXI_U_D = 1058, - Mips_MAXI_U_H = 1059, - Mips_MAXI_U_W = 1060, - Mips_MAX_A_B = 1061, - Mips_MAX_A_D = 1062, - Mips_MAX_A_H = 1063, - Mips_MAX_A_W = 1064, - Mips_MAX_D = 1065, - Mips_MAX_S = 1066, - Mips_MAX_S_B = 1067, - Mips_MAX_S_D = 1068, - Mips_MAX_S_H = 1069, - Mips_MAX_S_W = 1070, - Mips_MAX_U_B = 1071, - Mips_MAX_U_D = 1072, - Mips_MAX_U_H = 1073, - Mips_MAX_U_W = 1074, - Mips_MFC0 = 1075, - Mips_MFC1 = 1076, - Mips_MFC1_MM = 1077, - Mips_MFC2 = 1078, - Mips_MFHC1_D32 = 1079, - Mips_MFHC1_D64 = 1080, - Mips_MFHC1_MM = 1081, - Mips_MFHI = 1082, - Mips_MFHI16_MM = 1083, - Mips_MFHI64 = 1084, - Mips_MFHI_DSP = 1085, - Mips_MFHI_MM = 1086, - Mips_MFLO = 1087, - Mips_MFLO16_MM = 1088, - Mips_MFLO64 = 1089, - Mips_MFLO_DSP = 1090, - Mips_MFLO_MM = 1091, - Mips_MINA_D = 1092, - Mips_MINA_S = 1093, - Mips_MINI_S_B = 1094, - Mips_MINI_S_D = 1095, - Mips_MINI_S_H = 1096, - Mips_MINI_S_W = 1097, - Mips_MINI_U_B = 1098, - Mips_MINI_U_D = 1099, - Mips_MINI_U_H = 1100, - Mips_MINI_U_W = 1101, - Mips_MIN_A_B = 1102, - Mips_MIN_A_D = 1103, - Mips_MIN_A_H = 1104, - Mips_MIN_A_W = 1105, - Mips_MIN_D = 1106, - Mips_MIN_S = 1107, - Mips_MIN_S_B = 1108, - Mips_MIN_S_D = 1109, - Mips_MIN_S_H = 1110, - Mips_MIN_S_W = 1111, - Mips_MIN_U_B = 1112, - Mips_MIN_U_D = 1113, - Mips_MIN_U_H = 1114, - Mips_MIN_U_W = 1115, - Mips_MIPSeh_return32 = 1116, - Mips_MIPSeh_return64 = 1117, - Mips_MOD = 1118, - Mips_MODSUB = 1119, - Mips_MODU = 1120, - Mips_MOD_S_B = 1121, - Mips_MOD_S_D = 1122, - Mips_MOD_S_H = 1123, - Mips_MOD_S_W = 1124, - Mips_MOD_U_B = 1125, - Mips_MOD_U_D = 1126, - Mips_MOD_U_H = 1127, - Mips_MOD_U_W = 1128, - Mips_MOVE16_MM = 1129, - Mips_MOVEP_MM = 1130, - Mips_MOVE_V = 1131, - Mips_MOVF_D32 = 1132, - Mips_MOVF_D32_MM = 1133, - Mips_MOVF_D64 = 1134, - Mips_MOVF_I = 1135, - Mips_MOVF_I64 = 1136, - Mips_MOVF_I_MM = 1137, - Mips_MOVF_S = 1138, - Mips_MOVF_S_MM = 1139, - Mips_MOVN_I64_D64 = 1140, - Mips_MOVN_I64_I = 1141, - Mips_MOVN_I64_I64 = 1142, - Mips_MOVN_I64_S = 1143, - Mips_MOVN_I_D32 = 1144, - Mips_MOVN_I_D32_MM = 1145, - Mips_MOVN_I_D64 = 1146, - Mips_MOVN_I_I = 1147, - Mips_MOVN_I_I64 = 1148, - Mips_MOVN_I_MM = 1149, - Mips_MOVN_I_S = 1150, - Mips_MOVN_I_S_MM = 1151, - Mips_MOVT_D32 = 1152, - Mips_MOVT_D32_MM = 1153, - Mips_MOVT_D64 = 1154, - Mips_MOVT_I = 1155, - Mips_MOVT_I64 = 1156, - Mips_MOVT_I_MM = 1157, - Mips_MOVT_S = 1158, - Mips_MOVT_S_MM = 1159, - Mips_MOVZ_I64_D64 = 1160, - Mips_MOVZ_I64_I = 1161, - Mips_MOVZ_I64_I64 = 1162, - Mips_MOVZ_I64_S = 1163, - Mips_MOVZ_I_D32 = 1164, - Mips_MOVZ_I_D32_MM = 1165, - Mips_MOVZ_I_D64 = 1166, - Mips_MOVZ_I_I = 1167, - Mips_MOVZ_I_I64 = 1168, - Mips_MOVZ_I_MM = 1169, - Mips_MOVZ_I_S = 1170, - Mips_MOVZ_I_S_MM = 1171, - Mips_MSUB = 1172, - Mips_MSUBF_D = 1173, - Mips_MSUBF_S = 1174, - Mips_MSUBR_Q_H = 1175, - Mips_MSUBR_Q_W = 1176, - Mips_MSUBU = 1177, - Mips_MSUBU_DSP = 1178, - Mips_MSUBU_MM = 1179, - Mips_MSUBV_B = 1180, - Mips_MSUBV_D = 1181, - Mips_MSUBV_H = 1182, - Mips_MSUBV_W = 1183, - Mips_MSUB_D32 = 1184, - Mips_MSUB_D32_MM = 1185, - Mips_MSUB_D64 = 1186, - Mips_MSUB_DSP = 1187, - Mips_MSUB_MM = 1188, - Mips_MSUB_Q_H = 1189, - Mips_MSUB_Q_W = 1190, - Mips_MSUB_S = 1191, - Mips_MSUB_S_MM = 1192, - Mips_MTC0 = 1193, - Mips_MTC1 = 1194, - Mips_MTC1_MM = 1195, - Mips_MTC2 = 1196, - Mips_MTHC1_D32 = 1197, - Mips_MTHC1_D64 = 1198, - Mips_MTHC1_MM = 1199, - Mips_MTHI = 1200, - Mips_MTHI64 = 1201, - Mips_MTHI_DSP = 1202, - Mips_MTHI_MM = 1203, - Mips_MTHLIP = 1204, - Mips_MTLO = 1205, - Mips_MTLO64 = 1206, - Mips_MTLO_DSP = 1207, - Mips_MTLO_MM = 1208, - Mips_MTM0 = 1209, - Mips_MTM1 = 1210, - Mips_MTM2 = 1211, - Mips_MTP0 = 1212, - Mips_MTP1 = 1213, - Mips_MTP2 = 1214, - Mips_MUH = 1215, - Mips_MUHU = 1216, - Mips_MUL = 1217, - Mips_MULEQ_S_W_PHL = 1218, - Mips_MULEQ_S_W_PHR = 1219, - Mips_MULEU_S_PH_QBL = 1220, - Mips_MULEU_S_PH_QBR = 1221, - Mips_MULQ_RS_PH = 1222, - Mips_MULQ_RS_W = 1223, - Mips_MULQ_S_PH = 1224, - Mips_MULQ_S_W = 1225, - Mips_MULR_Q_H = 1226, - Mips_MULR_Q_W = 1227, - Mips_MULSAQ_S_W_PH = 1228, - Mips_MULSA_W_PH = 1229, - Mips_MULT = 1230, - Mips_MULTU_DSP = 1231, - Mips_MULT_DSP = 1232, - Mips_MULT_MM = 1233, - Mips_MULTu = 1234, - Mips_MULTu_MM = 1235, - Mips_MULU = 1236, - Mips_MULV_B = 1237, - Mips_MULV_D = 1238, - Mips_MULV_H = 1239, - Mips_MULV_W = 1240, - Mips_MUL_MM = 1241, - Mips_MUL_PH = 1242, - Mips_MUL_Q_H = 1243, - Mips_MUL_Q_W = 1244, - Mips_MUL_R6 = 1245, - Mips_MUL_S_PH = 1246, - Mips_Mfhi16 = 1247, - Mips_Mflo16 = 1248, - Mips_Move32R16 = 1249, - Mips_MoveR3216 = 1250, - Mips_MultRxRy16 = 1251, - Mips_MultRxRyRz16 = 1252, - Mips_MultuRxRy16 = 1253, - Mips_MultuRxRyRz16 = 1254, - Mips_NLOC_B = 1255, - Mips_NLOC_D = 1256, - Mips_NLOC_H = 1257, - Mips_NLOC_W = 1258, - Mips_NLZC_B = 1259, - Mips_NLZC_D = 1260, - Mips_NLZC_H = 1261, - Mips_NLZC_W = 1262, - Mips_NMADD_D32 = 1263, - Mips_NMADD_D32_MM = 1264, - Mips_NMADD_D64 = 1265, - Mips_NMADD_S = 1266, - Mips_NMADD_S_MM = 1267, - Mips_NMSUB_D32 = 1268, - Mips_NMSUB_D32_MM = 1269, - Mips_NMSUB_D64 = 1270, - Mips_NMSUB_S = 1271, - Mips_NMSUB_S_MM = 1272, - Mips_NOP = 1273, - Mips_NOR = 1274, - Mips_NOR64 = 1275, - Mips_NORI_B = 1276, - Mips_NOR_MM = 1277, - Mips_NOR_V = 1278, - Mips_NOR_V_D_PSEUDO = 1279, - Mips_NOR_V_H_PSEUDO = 1280, - Mips_NOR_V_W_PSEUDO = 1281, - Mips_NOT16_MM = 1282, - Mips_NegRxRy16 = 1283, - Mips_NotRxRy16 = 1284, - Mips_OR = 1285, - Mips_OR16_MM = 1286, - Mips_OR64 = 1287, - Mips_ORI_B = 1288, - Mips_OR_MM = 1289, - Mips_OR_V = 1290, - Mips_OR_V_D_PSEUDO = 1291, - Mips_OR_V_H_PSEUDO = 1292, - Mips_OR_V_W_PSEUDO = 1293, - Mips_ORi = 1294, - Mips_ORi64 = 1295, - Mips_ORi_MM = 1296, - Mips_OrRxRxRy16 = 1297, - Mips_PACKRL_PH = 1298, - Mips_PAUSE = 1299, - Mips_PAUSE_MM = 1300, - Mips_PCKEV_B = 1301, - Mips_PCKEV_D = 1302, - Mips_PCKEV_H = 1303, - Mips_PCKEV_W = 1304, - Mips_PCKOD_B = 1305, - Mips_PCKOD_D = 1306, - Mips_PCKOD_H = 1307, - Mips_PCKOD_W = 1308, - Mips_PCNT_B = 1309, - Mips_PCNT_D = 1310, - Mips_PCNT_H = 1311, - Mips_PCNT_W = 1312, - Mips_PICK_PH = 1313, - Mips_PICK_QB = 1314, - Mips_POP = 1315, - Mips_PRECEQU_PH_QBL = 1316, - Mips_PRECEQU_PH_QBLA = 1317, - Mips_PRECEQU_PH_QBR = 1318, - Mips_PRECEQU_PH_QBRA = 1319, - Mips_PRECEQ_W_PHL = 1320, - Mips_PRECEQ_W_PHR = 1321, - Mips_PRECEU_PH_QBL = 1322, - Mips_PRECEU_PH_QBLA = 1323, - Mips_PRECEU_PH_QBR = 1324, - Mips_PRECEU_PH_QBRA = 1325, - Mips_PRECRQU_S_QB_PH = 1326, - Mips_PRECRQ_PH_W = 1327, - Mips_PRECRQ_QB_PH = 1328, - Mips_PRECRQ_RS_PH_W = 1329, - Mips_PRECR_QB_PH = 1330, - Mips_PRECR_SRA_PH_W = 1331, - Mips_PRECR_SRA_R_PH_W = 1332, - Mips_PREF = 1333, - Mips_PREF_MM = 1334, - Mips_PREF_R6 = 1335, - Mips_PREPEND = 1336, - Mips_PseudoCMPU_EQ_QB = 1337, - Mips_PseudoCMPU_LE_QB = 1338, - Mips_PseudoCMPU_LT_QB = 1339, - Mips_PseudoCMP_EQ_PH = 1340, - Mips_PseudoCMP_LE_PH = 1341, - Mips_PseudoCMP_LT_PH = 1342, - Mips_PseudoCVT_D32_W = 1343, - Mips_PseudoCVT_D64_L = 1344, - Mips_PseudoCVT_D64_W = 1345, - Mips_PseudoCVT_S_L = 1346, - Mips_PseudoCVT_S_W = 1347, - Mips_PseudoDMULT = 1348, - Mips_PseudoDMULTu = 1349, - Mips_PseudoDSDIV = 1350, - Mips_PseudoDUDIV = 1351, - Mips_PseudoIndirectBranch = 1352, - Mips_PseudoIndirectBranch64 = 1353, - Mips_PseudoMADD = 1354, - Mips_PseudoMADDU = 1355, - Mips_PseudoMFHI = 1356, - Mips_PseudoMFHI64 = 1357, - Mips_PseudoMFLO = 1358, - Mips_PseudoMFLO64 = 1359, - Mips_PseudoMSUB = 1360, - Mips_PseudoMSUBU = 1361, - Mips_PseudoMTLOHI = 1362, - Mips_PseudoMTLOHI64 = 1363, - Mips_PseudoMTLOHI_DSP = 1364, - Mips_PseudoMULT = 1365, - Mips_PseudoMULTu = 1366, - Mips_PseudoPICK_PH = 1367, - Mips_PseudoPICK_QB = 1368, - Mips_PseudoReturn = 1369, - Mips_PseudoReturn64 = 1370, - Mips_PseudoSDIV = 1371, - Mips_PseudoSELECTFP_F_D32 = 1372, - Mips_PseudoSELECTFP_F_D64 = 1373, - Mips_PseudoSELECTFP_F_I = 1374, - Mips_PseudoSELECTFP_F_I64 = 1375, - Mips_PseudoSELECTFP_F_S = 1376, - Mips_PseudoSELECTFP_T_D32 = 1377, - Mips_PseudoSELECTFP_T_D64 = 1378, - Mips_PseudoSELECTFP_T_I = 1379, - Mips_PseudoSELECTFP_T_I64 = 1380, - Mips_PseudoSELECTFP_T_S = 1381, - Mips_PseudoSELECT_D32 = 1382, - Mips_PseudoSELECT_D64 = 1383, - Mips_PseudoSELECT_I = 1384, - Mips_PseudoSELECT_I64 = 1385, - Mips_PseudoSELECT_S = 1386, - Mips_PseudoUDIV = 1387, - Mips_RADDU_W_QB = 1388, - Mips_RDDSP = 1389, - Mips_RDHWR = 1390, - Mips_RDHWR64 = 1391, - Mips_RDHWR_MM = 1392, - Mips_REPLV_PH = 1393, - Mips_REPLV_QB = 1394, - Mips_REPL_PH = 1395, - Mips_REPL_QB = 1396, - Mips_RINT_D = 1397, - Mips_RINT_S = 1398, - Mips_ROTR = 1399, - Mips_ROTRV = 1400, - Mips_ROTRV_MM = 1401, - Mips_ROTR_MM = 1402, - Mips_ROUND_L_D64 = 1403, - Mips_ROUND_L_S = 1404, - Mips_ROUND_W_D32 = 1405, - Mips_ROUND_W_D64 = 1406, - Mips_ROUND_W_MM = 1407, - Mips_ROUND_W_S = 1408, - Mips_ROUND_W_S_MM = 1409, - Mips_Restore16 = 1410, - Mips_RestoreX16 = 1411, - Mips_RetRA = 1412, - Mips_RetRA16 = 1413, - Mips_SAT_S_B = 1414, - Mips_SAT_S_D = 1415, - Mips_SAT_S_H = 1416, - Mips_SAT_S_W = 1417, - Mips_SAT_U_B = 1418, - Mips_SAT_U_D = 1419, - Mips_SAT_U_H = 1420, - Mips_SAT_U_W = 1421, - Mips_SB = 1422, - Mips_SB16_MM = 1423, - Mips_SB64 = 1424, - Mips_SB_MM = 1425, - Mips_SC = 1426, - Mips_SCD = 1427, - Mips_SCD_R6 = 1428, - Mips_SC_MM = 1429, - Mips_SC_R6 = 1430, - Mips_SD = 1431, - Mips_SDBBP = 1432, - Mips_SDBBP16_MM = 1433, - Mips_SDBBP_MM = 1434, - Mips_SDBBP_R6 = 1435, - Mips_SDC1 = 1436, - Mips_SDC164 = 1437, - Mips_SDC1_MM = 1438, - Mips_SDC2 = 1439, - Mips_SDC2_R6 = 1440, - Mips_SDC3 = 1441, - Mips_SDIV = 1442, - Mips_SDIV_MM = 1443, - Mips_SDL = 1444, - Mips_SDR = 1445, - Mips_SDXC1 = 1446, - Mips_SDXC164 = 1447, - Mips_SEB = 1448, - Mips_SEB64 = 1449, - Mips_SEB_MM = 1450, - Mips_SEH = 1451, - Mips_SEH64 = 1452, - Mips_SEH_MM = 1453, - Mips_SELEQZ = 1454, - Mips_SELEQZ64 = 1455, - Mips_SELEQZ_D = 1456, - Mips_SELEQZ_S = 1457, - Mips_SELNEZ = 1458, - Mips_SELNEZ64 = 1459, - Mips_SELNEZ_D = 1460, - Mips_SELNEZ_S = 1461, - Mips_SEL_D = 1462, - Mips_SEL_S = 1463, - Mips_SEQ = 1464, - Mips_SEQi = 1465, - Mips_SH = 1466, - Mips_SH16_MM = 1467, - Mips_SH64 = 1468, - Mips_SHF_B = 1469, - Mips_SHF_H = 1470, - Mips_SHF_W = 1471, - Mips_SHILO = 1472, - Mips_SHILOV = 1473, - Mips_SHLLV_PH = 1474, - Mips_SHLLV_QB = 1475, - Mips_SHLLV_S_PH = 1476, - Mips_SHLLV_S_W = 1477, - Mips_SHLL_PH = 1478, - Mips_SHLL_QB = 1479, - Mips_SHLL_S_PH = 1480, - Mips_SHLL_S_W = 1481, - Mips_SHRAV_PH = 1482, - Mips_SHRAV_QB = 1483, - Mips_SHRAV_R_PH = 1484, - Mips_SHRAV_R_QB = 1485, - Mips_SHRAV_R_W = 1486, - Mips_SHRA_PH = 1487, - Mips_SHRA_QB = 1488, - Mips_SHRA_R_PH = 1489, - Mips_SHRA_R_QB = 1490, - Mips_SHRA_R_W = 1491, - Mips_SHRLV_PH = 1492, - Mips_SHRLV_QB = 1493, - Mips_SHRL_PH = 1494, - Mips_SHRL_QB = 1495, - Mips_SH_MM = 1496, - Mips_SLDI_B = 1497, - Mips_SLDI_D = 1498, - Mips_SLDI_H = 1499, - Mips_SLDI_W = 1500, - Mips_SLD_B = 1501, - Mips_SLD_D = 1502, - Mips_SLD_H = 1503, - Mips_SLD_W = 1504, - Mips_SLL = 1505, - Mips_SLL16_MM = 1506, - Mips_SLL64_32 = 1507, - Mips_SLL64_64 = 1508, - Mips_SLLI_B = 1509, - Mips_SLLI_D = 1510, - Mips_SLLI_H = 1511, - Mips_SLLI_W = 1512, - Mips_SLLV = 1513, - Mips_SLLV_MM = 1514, - Mips_SLL_B = 1515, - Mips_SLL_D = 1516, - Mips_SLL_H = 1517, - Mips_SLL_MM = 1518, - Mips_SLL_W = 1519, - Mips_SLT = 1520, - Mips_SLT64 = 1521, - Mips_SLT_MM = 1522, - Mips_SLTi = 1523, - Mips_SLTi64 = 1524, - Mips_SLTi_MM = 1525, - Mips_SLTiu = 1526, - Mips_SLTiu64 = 1527, - Mips_SLTiu_MM = 1528, - Mips_SLTu = 1529, - Mips_SLTu64 = 1530, - Mips_SLTu_MM = 1531, - Mips_SNE = 1532, - Mips_SNEi = 1533, - Mips_SNZ_B_PSEUDO = 1534, - Mips_SNZ_D_PSEUDO = 1535, - Mips_SNZ_H_PSEUDO = 1536, - Mips_SNZ_V_PSEUDO = 1537, - Mips_SNZ_W_PSEUDO = 1538, - Mips_SPLATI_B = 1539, - Mips_SPLATI_D = 1540, - Mips_SPLATI_H = 1541, - Mips_SPLATI_W = 1542, - Mips_SPLAT_B = 1543, - Mips_SPLAT_D = 1544, - Mips_SPLAT_H = 1545, - Mips_SPLAT_W = 1546, - Mips_SRA = 1547, - Mips_SRAI_B = 1548, - Mips_SRAI_D = 1549, - Mips_SRAI_H = 1550, - Mips_SRAI_W = 1551, - Mips_SRARI_B = 1552, - Mips_SRARI_D = 1553, - Mips_SRARI_H = 1554, - Mips_SRARI_W = 1555, - Mips_SRAR_B = 1556, - Mips_SRAR_D = 1557, - Mips_SRAR_H = 1558, - Mips_SRAR_W = 1559, - Mips_SRAV = 1560, - Mips_SRAV_MM = 1561, - Mips_SRA_B = 1562, - Mips_SRA_D = 1563, - Mips_SRA_H = 1564, - Mips_SRA_MM = 1565, - Mips_SRA_W = 1566, - Mips_SRL = 1567, - Mips_SRL16_MM = 1568, - Mips_SRLI_B = 1569, - Mips_SRLI_D = 1570, - Mips_SRLI_H = 1571, - Mips_SRLI_W = 1572, - Mips_SRLRI_B = 1573, - Mips_SRLRI_D = 1574, - Mips_SRLRI_H = 1575, - Mips_SRLRI_W = 1576, - Mips_SRLR_B = 1577, - Mips_SRLR_D = 1578, - Mips_SRLR_H = 1579, - Mips_SRLR_W = 1580, - Mips_SRLV = 1581, - Mips_SRLV_MM = 1582, - Mips_SRL_B = 1583, - Mips_SRL_D = 1584, - Mips_SRL_H = 1585, - Mips_SRL_MM = 1586, - Mips_SRL_W = 1587, - Mips_SSNOP = 1588, - Mips_SSNOP_MM = 1589, - Mips_STORE_ACC128 = 1590, - Mips_STORE_ACC64 = 1591, - Mips_STORE_ACC64DSP = 1592, - Mips_STORE_CCOND_DSP = 1593, - Mips_ST_B = 1594, - Mips_ST_D = 1595, - Mips_ST_H = 1596, - Mips_ST_W = 1597, - Mips_SUB = 1598, - Mips_SUBQH_PH = 1599, - Mips_SUBQH_R_PH = 1600, - Mips_SUBQH_R_W = 1601, - Mips_SUBQH_W = 1602, - Mips_SUBQ_PH = 1603, - Mips_SUBQ_S_PH = 1604, - Mips_SUBQ_S_W = 1605, - Mips_SUBSUS_U_B = 1606, - Mips_SUBSUS_U_D = 1607, - Mips_SUBSUS_U_H = 1608, - Mips_SUBSUS_U_W = 1609, - Mips_SUBSUU_S_B = 1610, - Mips_SUBSUU_S_D = 1611, - Mips_SUBSUU_S_H = 1612, - Mips_SUBSUU_S_W = 1613, - Mips_SUBS_S_B = 1614, - Mips_SUBS_S_D = 1615, - Mips_SUBS_S_H = 1616, - Mips_SUBS_S_W = 1617, - Mips_SUBS_U_B = 1618, - Mips_SUBS_U_D = 1619, - Mips_SUBS_U_H = 1620, - Mips_SUBS_U_W = 1621, - Mips_SUBU16_MM = 1622, - Mips_SUBUH_QB = 1623, - Mips_SUBUH_R_QB = 1624, - Mips_SUBU_PH = 1625, - Mips_SUBU_QB = 1626, - Mips_SUBU_S_PH = 1627, - Mips_SUBU_S_QB = 1628, - Mips_SUBVI_B = 1629, - Mips_SUBVI_D = 1630, - Mips_SUBVI_H = 1631, - Mips_SUBVI_W = 1632, - Mips_SUBV_B = 1633, - Mips_SUBV_D = 1634, - Mips_SUBV_H = 1635, - Mips_SUBV_W = 1636, - Mips_SUB_MM = 1637, - Mips_SUBu = 1638, - Mips_SUBu_MM = 1639, - Mips_SUXC1 = 1640, - Mips_SUXC164 = 1641, - Mips_SUXC1_MM = 1642, - Mips_SW = 1643, - Mips_SW16_MM = 1644, - Mips_SW64 = 1645, - Mips_SWC1 = 1646, - Mips_SWC1_MM = 1647, - Mips_SWC2 = 1648, - Mips_SWC2_R6 = 1649, - Mips_SWC3 = 1650, - Mips_SWL = 1651, - Mips_SWL64 = 1652, - Mips_SWL_MM = 1653, - Mips_SWM16_MM = 1654, - Mips_SWM32_MM = 1655, - Mips_SWM_MM = 1656, - Mips_SWP_MM = 1657, - Mips_SWR = 1658, - Mips_SWR64 = 1659, - Mips_SWR_MM = 1660, - Mips_SWSP_MM = 1661, - Mips_SWXC1 = 1662, - Mips_SWXC1_MM = 1663, - Mips_SW_MM = 1664, - Mips_SYNC = 1665, - Mips_SYNCI = 1666, - Mips_SYNC_MM = 1667, - Mips_SYSCALL = 1668, - Mips_SYSCALL_MM = 1669, - Mips_SZ_B_PSEUDO = 1670, - Mips_SZ_D_PSEUDO = 1671, - Mips_SZ_H_PSEUDO = 1672, - Mips_SZ_V_PSEUDO = 1673, - Mips_SZ_W_PSEUDO = 1674, - Mips_Save16 = 1675, - Mips_SaveX16 = 1676, - Mips_SbRxRyOffMemX16 = 1677, - Mips_SebRx16 = 1678, - Mips_SehRx16 = 1679, - Mips_SelBeqZ = 1680, - Mips_SelBneZ = 1681, - Mips_SelTBteqZCmp = 1682, - Mips_SelTBteqZCmpi = 1683, - Mips_SelTBteqZSlt = 1684, - Mips_SelTBteqZSlti = 1685, - Mips_SelTBteqZSltiu = 1686, - Mips_SelTBteqZSltu = 1687, - Mips_SelTBtneZCmp = 1688, - Mips_SelTBtneZCmpi = 1689, - Mips_SelTBtneZSlt = 1690, - Mips_SelTBtneZSlti = 1691, - Mips_SelTBtneZSltiu = 1692, - Mips_SelTBtneZSltu = 1693, - Mips_ShRxRyOffMemX16 = 1694, - Mips_SllX16 = 1695, - Mips_SllvRxRy16 = 1696, - Mips_SltCCRxRy16 = 1697, - Mips_SltRxRy16 = 1698, - Mips_SltiCCRxImmX16 = 1699, - Mips_SltiRxImm16 = 1700, - Mips_SltiRxImmX16 = 1701, - Mips_SltiuCCRxImmX16 = 1702, - Mips_SltiuRxImm16 = 1703, - Mips_SltiuRxImmX16 = 1704, - Mips_SltuCCRxRy16 = 1705, - Mips_SltuRxRy16 = 1706, - Mips_SltuRxRyRz16 = 1707, - Mips_SraX16 = 1708, - Mips_SravRxRy16 = 1709, - Mips_SrlX16 = 1710, - Mips_SrlvRxRy16 = 1711, - Mips_SubuRxRyRz16 = 1712, - Mips_SwRxRyOffMemX16 = 1713, - Mips_SwRxSpImmX16 = 1714, - Mips_TAILCALL = 1715, - Mips_TAILCALL64_R = 1716, - Mips_TAILCALL_R = 1717, - Mips_TEQ = 1718, - Mips_TEQI = 1719, - Mips_TEQI_MM = 1720, - Mips_TEQ_MM = 1721, - Mips_TGE = 1722, - Mips_TGEI = 1723, - Mips_TGEIU = 1724, - Mips_TGEIU_MM = 1725, - Mips_TGEI_MM = 1726, - Mips_TGEU = 1727, - Mips_TGEU_MM = 1728, - Mips_TGE_MM = 1729, - Mips_TLBP = 1730, - Mips_TLBP_MM = 1731, - Mips_TLBR = 1732, - Mips_TLBR_MM = 1733, - Mips_TLBWI = 1734, - Mips_TLBWI_MM = 1735, - Mips_TLBWR = 1736, - Mips_TLBWR_MM = 1737, - Mips_TLT = 1738, - Mips_TLTI = 1739, - Mips_TLTIU_MM = 1740, - Mips_TLTI_MM = 1741, - Mips_TLTU = 1742, - Mips_TLTU_MM = 1743, - Mips_TLT_MM = 1744, - Mips_TNE = 1745, - Mips_TNEI = 1746, - Mips_TNEI_MM = 1747, - Mips_TNE_MM = 1748, - Mips_TRAP = 1749, - Mips_TRUNC_L_D64 = 1750, - Mips_TRUNC_L_S = 1751, - Mips_TRUNC_W_D32 = 1752, - Mips_TRUNC_W_D64 = 1753, - Mips_TRUNC_W_MM = 1754, - Mips_TRUNC_W_S = 1755, - Mips_TRUNC_W_S_MM = 1756, - Mips_TTLTIU = 1757, - Mips_UDIV = 1758, - Mips_UDIV_MM = 1759, - Mips_V3MULU = 1760, - Mips_VMM0 = 1761, - Mips_VMULU = 1762, - Mips_VSHF_B = 1763, - Mips_VSHF_D = 1764, - Mips_VSHF_H = 1765, - Mips_VSHF_W = 1766, - Mips_WAIT = 1767, - Mips_WAIT_MM = 1768, - Mips_WRDSP = 1769, - Mips_WSBH = 1770, - Mips_WSBH_MM = 1771, - Mips_XOR = 1772, - Mips_XOR16_MM = 1773, - Mips_XOR64 = 1774, - Mips_XORI_B = 1775, - Mips_XOR_MM = 1776, - Mips_XOR_V = 1777, - Mips_XOR_V_D_PSEUDO = 1778, - Mips_XOR_V_H_PSEUDO = 1779, - Mips_XOR_V_W_PSEUDO = 1780, - Mips_XORi = 1781, - Mips_XORi64 = 1782, - Mips_XORi_MM = 1783, - Mips_XorRxRxRy16 = 1784, - Mips_INSTRUCTION_LIST_END = 1785 -}; - -#endif // GET_INSTRINFO_ENUM diff --git a/arch/Mips/MipsGenRegisterInfo.inc b/arch/Mips/MipsGenRegisterInfo.inc deleted file mode 100644 index 4501a407fd..0000000000 --- a/arch/Mips/MipsGenRegisterInfo.inc +++ /dev/null @@ -1,1679 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Target Register Enum Values *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2019 */ - - -#ifdef GET_REGINFO_ENUM -#undef GET_REGINFO_ENUM - -enum { - Mips_NoRegister, - Mips_AT = 1, - Mips_DSPCCond = 2, - Mips_DSPCarry = 3, - Mips_DSPEFI = 4, - Mips_DSPOutFlag = 5, - Mips_DSPPos = 6, - Mips_DSPSCount = 7, - Mips_FP = 8, - Mips_GP = 9, - Mips_MSAAccess = 10, - Mips_MSACSR = 11, - Mips_MSAIR = 12, - Mips_MSAMap = 13, - Mips_MSAModify = 14, - Mips_MSARequest = 15, - Mips_MSASave = 16, - Mips_MSAUnmap = 17, - Mips_PC = 18, - Mips_RA = 19, - Mips_SP = 20, - Mips_ZERO = 21, - Mips_A0 = 22, - Mips_A1 = 23, - Mips_A2 = 24, - Mips_A3 = 25, - Mips_AC0 = 26, - Mips_AC1 = 27, - Mips_AC2 = 28, - Mips_AC3 = 29, - Mips_AT_64 = 30, - Mips_CC0 = 31, - Mips_CC1 = 32, - Mips_CC2 = 33, - Mips_CC3 = 34, - Mips_CC4 = 35, - Mips_CC5 = 36, - Mips_CC6 = 37, - Mips_CC7 = 38, - Mips_COP20 = 39, - Mips_COP21 = 40, - Mips_COP22 = 41, - Mips_COP23 = 42, - Mips_COP24 = 43, - Mips_COP25 = 44, - Mips_COP26 = 45, - Mips_COP27 = 46, - Mips_COP28 = 47, - Mips_COP29 = 48, - Mips_COP30 = 49, - Mips_COP31 = 50, - Mips_COP32 = 51, - Mips_COP33 = 52, - Mips_COP34 = 53, - Mips_COP35 = 54, - Mips_COP36 = 55, - Mips_COP37 = 56, - Mips_COP38 = 57, - Mips_COP39 = 58, - Mips_COP210 = 59, - Mips_COP211 = 60, - Mips_COP212 = 61, - Mips_COP213 = 62, - Mips_COP214 = 63, - Mips_COP215 = 64, - Mips_COP216 = 65, - Mips_COP217 = 66, - Mips_COP218 = 67, - Mips_COP219 = 68, - Mips_COP220 = 69, - Mips_COP221 = 70, - Mips_COP222 = 71, - Mips_COP223 = 72, - Mips_COP224 = 73, - Mips_COP225 = 74, - Mips_COP226 = 75, - Mips_COP227 = 76, - Mips_COP228 = 77, - Mips_COP229 = 78, - Mips_COP230 = 79, - Mips_COP231 = 80, - Mips_COP310 = 81, - Mips_COP311 = 82, - Mips_COP312 = 83, - Mips_COP313 = 84, - Mips_COP314 = 85, - Mips_COP315 = 86, - Mips_COP316 = 87, - Mips_COP317 = 88, - Mips_COP318 = 89, - Mips_COP319 = 90, - Mips_COP320 = 91, - Mips_COP321 = 92, - Mips_COP322 = 93, - Mips_COP323 = 94, - Mips_COP324 = 95, - Mips_COP325 = 96, - Mips_COP326 = 97, - Mips_COP327 = 98, - Mips_COP328 = 99, - Mips_COP329 = 100, - Mips_COP330 = 101, - Mips_COP331 = 102, - Mips_D0 = 103, - Mips_D1 = 104, - Mips_D2 = 105, - Mips_D3 = 106, - Mips_D4 = 107, - Mips_D5 = 108, - Mips_D6 = 109, - Mips_D7 = 110, - Mips_D8 = 111, - Mips_D9 = 112, - Mips_D10 = 113, - Mips_D11 = 114, - Mips_D12 = 115, - Mips_D13 = 116, - Mips_D14 = 117, - Mips_D15 = 118, - Mips_DSPOutFlag20 = 119, - Mips_DSPOutFlag21 = 120, - Mips_DSPOutFlag22 = 121, - Mips_DSPOutFlag23 = 122, - Mips_F0 = 123, - Mips_F1 = 124, - Mips_F2 = 125, - Mips_F3 = 126, - Mips_F4 = 127, - Mips_F5 = 128, - Mips_F6 = 129, - Mips_F7 = 130, - Mips_F8 = 131, - Mips_F9 = 132, - Mips_F10 = 133, - Mips_F11 = 134, - Mips_F12 = 135, - Mips_F13 = 136, - Mips_F14 = 137, - Mips_F15 = 138, - Mips_F16 = 139, - Mips_F17 = 140, - Mips_F18 = 141, - Mips_F19 = 142, - Mips_F20 = 143, - Mips_F21 = 144, - Mips_F22 = 145, - Mips_F23 = 146, - Mips_F24 = 147, - Mips_F25 = 148, - Mips_F26 = 149, - Mips_F27 = 150, - Mips_F28 = 151, - Mips_F29 = 152, - Mips_F30 = 153, - Mips_F31 = 154, - Mips_FCC0 = 155, - Mips_FCC1 = 156, - Mips_FCC2 = 157, - Mips_FCC3 = 158, - Mips_FCC4 = 159, - Mips_FCC5 = 160, - Mips_FCC6 = 161, - Mips_FCC7 = 162, - Mips_FCR0 = 163, - Mips_FCR1 = 164, - Mips_FCR2 = 165, - Mips_FCR3 = 166, - Mips_FCR4 = 167, - Mips_FCR5 = 168, - Mips_FCR6 = 169, - Mips_FCR7 = 170, - Mips_FCR8 = 171, - Mips_FCR9 = 172, - Mips_FCR10 = 173, - Mips_FCR11 = 174, - Mips_FCR12 = 175, - Mips_FCR13 = 176, - Mips_FCR14 = 177, - Mips_FCR15 = 178, - Mips_FCR16 = 179, - Mips_FCR17 = 180, - Mips_FCR18 = 181, - Mips_FCR19 = 182, - Mips_FCR20 = 183, - Mips_FCR21 = 184, - Mips_FCR22 = 185, - Mips_FCR23 = 186, - Mips_FCR24 = 187, - Mips_FCR25 = 188, - Mips_FCR26 = 189, - Mips_FCR27 = 190, - Mips_FCR28 = 191, - Mips_FCR29 = 192, - Mips_FCR30 = 193, - Mips_FCR31 = 194, - Mips_FP_64 = 195, - Mips_F_HI0 = 196, - Mips_F_HI1 = 197, - Mips_F_HI2 = 198, - Mips_F_HI3 = 199, - Mips_F_HI4 = 200, - Mips_F_HI5 = 201, - Mips_F_HI6 = 202, - Mips_F_HI7 = 203, - Mips_F_HI8 = 204, - Mips_F_HI9 = 205, - Mips_F_HI10 = 206, - Mips_F_HI11 = 207, - Mips_F_HI12 = 208, - Mips_F_HI13 = 209, - Mips_F_HI14 = 210, - Mips_F_HI15 = 211, - Mips_F_HI16 = 212, - Mips_F_HI17 = 213, - Mips_F_HI18 = 214, - Mips_F_HI19 = 215, - Mips_F_HI20 = 216, - Mips_F_HI21 = 217, - Mips_F_HI22 = 218, - Mips_F_HI23 = 219, - Mips_F_HI24 = 220, - Mips_F_HI25 = 221, - Mips_F_HI26 = 222, - Mips_F_HI27 = 223, - Mips_F_HI28 = 224, - Mips_F_HI29 = 225, - Mips_F_HI30 = 226, - Mips_F_HI31 = 227, - Mips_GP_64 = 228, - Mips_HI0 = 229, - Mips_HI1 = 230, - Mips_HI2 = 231, - Mips_HI3 = 232, - Mips_HWR0 = 233, - Mips_HWR1 = 234, - Mips_HWR2 = 235, - Mips_HWR3 = 236, - Mips_HWR4 = 237, - Mips_HWR5 = 238, - Mips_HWR6 = 239, - Mips_HWR7 = 240, - Mips_HWR8 = 241, - Mips_HWR9 = 242, - Mips_HWR10 = 243, - Mips_HWR11 = 244, - Mips_HWR12 = 245, - Mips_HWR13 = 246, - Mips_HWR14 = 247, - Mips_HWR15 = 248, - Mips_HWR16 = 249, - Mips_HWR17 = 250, - Mips_HWR18 = 251, - Mips_HWR19 = 252, - Mips_HWR20 = 253, - Mips_HWR21 = 254, - Mips_HWR22 = 255, - Mips_HWR23 = 256, - Mips_HWR24 = 257, - Mips_HWR25 = 258, - Mips_HWR26 = 259, - Mips_HWR27 = 260, - Mips_HWR28 = 261, - Mips_HWR29 = 262, - Mips_HWR30 = 263, - Mips_HWR31 = 264, - Mips_K0 = 265, - Mips_K1 = 266, - Mips_LO0 = 267, - Mips_LO1 = 268, - Mips_LO2 = 269, - Mips_LO3 = 270, - Mips_MPL0 = 271, - Mips_MPL1 = 272, - Mips_MPL2 = 273, - Mips_P0 = 274, - Mips_P1 = 275, - Mips_P2 = 276, - Mips_RA_64 = 277, - Mips_S0 = 278, - Mips_S1 = 279, - Mips_S2 = 280, - Mips_S3 = 281, - Mips_S4 = 282, - Mips_S5 = 283, - Mips_S6 = 284, - Mips_S7 = 285, - Mips_SP_64 = 286, - Mips_T0 = 287, - Mips_T1 = 288, - Mips_T2 = 289, - Mips_T3 = 290, - Mips_T4 = 291, - Mips_T5 = 292, - Mips_T6 = 293, - Mips_T7 = 294, - Mips_T8 = 295, - Mips_T9 = 296, - Mips_V0 = 297, - Mips_V1 = 298, - Mips_W0 = 299, - Mips_W1 = 300, - Mips_W2 = 301, - Mips_W3 = 302, - Mips_W4 = 303, - Mips_W5 = 304, - Mips_W6 = 305, - Mips_W7 = 306, - Mips_W8 = 307, - Mips_W9 = 308, - Mips_W10 = 309, - Mips_W11 = 310, - Mips_W12 = 311, - Mips_W13 = 312, - Mips_W14 = 313, - Mips_W15 = 314, - Mips_W16 = 315, - Mips_W17 = 316, - Mips_W18 = 317, - Mips_W19 = 318, - Mips_W20 = 319, - Mips_W21 = 320, - Mips_W22 = 321, - Mips_W23 = 322, - Mips_W24 = 323, - Mips_W25 = 324, - Mips_W26 = 325, - Mips_W27 = 326, - Mips_W28 = 327, - Mips_W29 = 328, - Mips_W30 = 329, - Mips_W31 = 330, - Mips_ZERO_64 = 331, - Mips_A0_64 = 332, - Mips_A1_64 = 333, - Mips_A2_64 = 334, - Mips_A3_64 = 335, - Mips_AC0_64 = 336, - Mips_D0_64 = 337, - Mips_D1_64 = 338, - Mips_D2_64 = 339, - Mips_D3_64 = 340, - Mips_D4_64 = 341, - Mips_D5_64 = 342, - Mips_D6_64 = 343, - Mips_D7_64 = 344, - Mips_D8_64 = 345, - Mips_D9_64 = 346, - Mips_D10_64 = 347, - Mips_D11_64 = 348, - Mips_D12_64 = 349, - Mips_D13_64 = 350, - Mips_D14_64 = 351, - Mips_D15_64 = 352, - Mips_D16_64 = 353, - Mips_D17_64 = 354, - Mips_D18_64 = 355, - Mips_D19_64 = 356, - Mips_D20_64 = 357, - Mips_D21_64 = 358, - Mips_D22_64 = 359, - Mips_D23_64 = 360, - Mips_D24_64 = 361, - Mips_D25_64 = 362, - Mips_D26_64 = 363, - Mips_D27_64 = 364, - Mips_D28_64 = 365, - Mips_D29_64 = 366, - Mips_D30_64 = 367, - Mips_D31_64 = 368, - Mips_DSPOutFlag16_19 = 369, - Mips_HI0_64 = 370, - Mips_K0_64 = 371, - Mips_K1_64 = 372, - Mips_LO0_64 = 373, - Mips_S0_64 = 374, - Mips_S1_64 = 375, - Mips_S2_64 = 376, - Mips_S3_64 = 377, - Mips_S4_64 = 378, - Mips_S5_64 = 379, - Mips_S6_64 = 380, - Mips_S7_64 = 381, - Mips_T0_64 = 382, - Mips_T1_64 = 383, - Mips_T2_64 = 384, - Mips_T3_64 = 385, - Mips_T4_64 = 386, - Mips_T5_64 = 387, - Mips_T6_64 = 388, - Mips_T7_64 = 389, - Mips_T8_64 = 390, - Mips_T9_64 = 391, - Mips_V0_64 = 392, - Mips_V1_64 = 393, - Mips_NUM_TARGET_REGS // 394 -}; - -// Register classes -enum { - Mips_OddSPRegClassID = 0, - Mips_CCRRegClassID = 1, - Mips_COP2RegClassID = 2, - Mips_COP3RegClassID = 3, - Mips_DSPRRegClassID = 4, - Mips_FGR32RegClassID = 5, - Mips_FGRCCRegClassID = 6, - Mips_FGRH32RegClassID = 7, - Mips_GPR32RegClassID = 8, - Mips_HWRegsRegClassID = 9, - Mips_OddSP_with_sub_hiRegClassID = 10, - Mips_FGR32_and_OddSPRegClassID = 11, - Mips_FGRH32_and_OddSPRegClassID = 12, - Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13, - Mips_CPU16RegsPlusSPRegClassID = 14, - Mips_CCRegClassID = 15, - Mips_CPU16RegsRegClassID = 16, - Mips_FCCRegClassID = 17, - Mips_GPRMM16RegClassID = 18, - Mips_GPRMM16MovePRegClassID = 19, - Mips_GPRMM16ZeroRegClassID = 20, - Mips_MSACtrlRegClassID = 21, - Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22, - Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 23, - Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 24, - Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25, - Mips_HI32DSPRegClassID = 26, - Mips_LO32DSPRegClassID = 27, - Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28, - Mips_CPURARegRegClassID = 29, - Mips_CPUSPRegRegClassID = 30, - Mips_DSPCCRegClassID = 31, - Mips_HI32RegClassID = 32, - Mips_LO32RegClassID = 33, - Mips_FGR64RegClassID = 34, - Mips_GPR64RegClassID = 35, - Mips_AFGR64RegClassID = 36, - Mips_FGR64_and_OddSPRegClassID = 37, - Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38, - Mips_AFGR64_and_OddSPRegClassID = 39, - Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 40, - Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41, - Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42, - Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43, - Mips_ACC64DSPRegClassID = 44, - Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45, - Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46, - Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47, - Mips_OCTEON_MPLRegClassID = 48, - Mips_OCTEON_PRegClassID = 49, - Mips_ACC64RegClassID = 50, - Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 51, - Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 52, - Mips_HI64RegClassID = 53, - Mips_LO64RegClassID = 54, - Mips_MSA128BRegClassID = 55, - Mips_MSA128DRegClassID = 56, - Mips_MSA128HRegClassID = 57, - Mips_MSA128WRegClassID = 58, - Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 59, - Mips_MSA128WEvensRegClassID = 60, - Mips_ACC128RegClassID = 61, -}; - -#endif // GET_REGINFO_ENUM - -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*MC Register Information *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2019 */ - - -#ifdef GET_REGINFO_MC_DESC -#undef GET_REGINFO_MC_DESC - -static const MCPhysReg MipsRegDiffLists[] = { - /* 0 */ 0, 0, - /* 2 */ 4, 1, 1, 1, 1, 0, - /* 8 */ 364, 65286, 1, 1, 1, 0, - /* 14 */ 20, 1, 0, - /* 17 */ 21, 1, 0, - /* 20 */ 22, 1, 0, - /* 23 */ 23, 1, 0, - /* 26 */ 24, 1, 0, - /* 29 */ 25, 1, 0, - /* 32 */ 26, 1, 0, - /* 35 */ 27, 1, 0, - /* 38 */ 28, 1, 0, - /* 41 */ 29, 1, 0, - /* 44 */ 30, 1, 0, - /* 47 */ 31, 1, 0, - /* 50 */ 32, 1, 0, - /* 53 */ 33, 1, 0, - /* 56 */ 34, 1, 0, - /* 59 */ 35, 1, 0, - /* 62 */ 65439, 1, 0, - /* 65 */ 65513, 1, 0, - /* 68 */ 3, 0, - /* 70 */ 4, 0, - /* 72 */ 6, 0, - /* 74 */ 11, 0, - /* 76 */ 12, 0, - /* 78 */ 22, 0, - /* 80 */ 23, 0, - /* 82 */ 29, 0, - /* 84 */ 30, 0, - /* 86 */ 65308, 72, 0, - /* 89 */ 65346, 72, 0, - /* 92 */ 38, 65322, 73, 0, - /* 96 */ 95, 0, - /* 98 */ 96, 0, - /* 100 */ 106, 0, - /* 102 */ 187, 0, - /* 104 */ 219, 0, - /* 106 */ 258, 0, - /* 108 */ 266, 0, - /* 110 */ 310, 0, - /* 112 */ 65031, 0, - /* 114 */ 65108, 0, - /* 116 */ 65172, 0, - /* 118 */ 65226, 0, - /* 120 */ 65229, 0, - /* 122 */ 65270, 0, - /* 124 */ 65278, 0, - /* 126 */ 65295, 0, - /* 128 */ 65317, 0, - /* 130 */ 37, 65430, 103, 65395, 65333, 0, - /* 136 */ 65349, 0, - /* 138 */ 65395, 0, - /* 140 */ 65410, 0, - /* 142 */ 65415, 0, - /* 144 */ 65419, 0, - /* 146 */ 65420, 0, - /* 148 */ 65421, 0, - /* 150 */ 65422, 0, - /* 152 */ 65430, 0, - /* 154 */ 65440, 0, - /* 156 */ 65441, 0, - /* 158 */ 141, 65498, 0, - /* 161 */ 65516, 234, 65498, 0, - /* 165 */ 65515, 235, 65498, 0, - /* 169 */ 65514, 236, 65498, 0, - /* 173 */ 65513, 237, 65498, 0, - /* 177 */ 65512, 238, 65498, 0, - /* 181 */ 65511, 239, 65498, 0, - /* 185 */ 65510, 240, 65498, 0, - /* 189 */ 65509, 241, 65498, 0, - /* 193 */ 65508, 242, 65498, 0, - /* 197 */ 65507, 243, 65498, 0, - /* 201 */ 65506, 244, 65498, 0, - /* 205 */ 65505, 245, 65498, 0, - /* 209 */ 65504, 246, 65498, 0, - /* 213 */ 65503, 247, 65498, 0, - /* 217 */ 65502, 248, 65498, 0, - /* 221 */ 65501, 249, 65498, 0, - /* 225 */ 65500, 250, 65498, 0, - /* 229 */ 65295, 347, 65499, 0, - /* 233 */ 65333, 344, 65502, 0, - /* 237 */ 65507, 0, - /* 239 */ 65510, 0, - /* 241 */ 65511, 0, - /* 243 */ 65512, 0, - /* 245 */ 65516, 0, - /* 247 */ 65521, 0, - /* 249 */ 65522, 0, - /* 251 */ 65535, 0, -}; - -static const uint16_t MipsSubRegIdxLists[] = { - /* 0 */ 1, 0, - /* 2 */ 3, 4, 5, 6, 7, 0, - /* 8 */ 2, 9, 8, 0, - /* 12 */ 9, 1, 8, 10, 11, 0, -}; - -static const MCRegisterDesc MipsRegDesc[] = { // Descriptors - { 6, 0, 0, 0, 0, 0 }, - { 2007, 1, 82, 1, 4017, 0 }, - { 2010, 1, 1, 1, 4017, 0 }, - { 2102, 1, 1, 1, 4017, 0 }, - { 1973, 1, 1, 1, 4017, 0 }, - { 2027, 8, 1, 2, 32, 4 }, - { 2054, 1, 1, 1, 1089, 0 }, - { 2071, 1, 1, 1, 1089, 0 }, - { 1985, 1, 102, 1, 1089, 0 }, - { 1988, 1, 104, 1, 1089, 0 }, - { 2061, 1, 1, 1, 1089, 0 }, - { 2000, 1, 1, 1, 1089, 0 }, - { 1994, 1, 1, 1, 1089, 0 }, - { 2038, 1, 1, 1, 1089, 0 }, - { 2092, 1, 1, 1, 1089, 0 }, - { 2081, 1, 1, 1, 1089, 0 }, - { 2019, 1, 1, 1, 1089, 0 }, - { 2045, 1, 1, 1, 1089, 0 }, - { 1970, 1, 1, 1, 1089, 0 }, - { 1967, 1, 106, 1, 1089, 0 }, - { 1991, 1, 108, 1, 1089, 0 }, - { 1980, 1, 110, 1, 1089, 0 }, - { 152, 1, 110, 1, 1089, 0 }, - { 365, 1, 110, 1, 1089, 0 }, - { 537, 1, 110, 1, 1089, 0 }, - { 703, 1, 110, 1, 1089, 0 }, - { 155, 190, 110, 9, 1042, 10 }, - { 368, 190, 1, 9, 1042, 10 }, - { 540, 190, 1, 9, 1042, 10 }, - { 706, 190, 1, 9, 1042, 10 }, - { 1271, 237, 1, 0, 0, 2 }, - { 160, 1, 1, 1, 1153, 0 }, - { 373, 1, 1, 1, 1153, 0 }, - { 545, 1, 1, 1, 1153, 0 }, - { 711, 1, 1, 1, 1153, 0 }, - { 1278, 1, 1, 1, 1153, 0 }, - { 1412, 1, 1, 1, 1153, 0 }, - { 1542, 1, 1, 1, 1153, 0 }, - { 1672, 1, 1, 1, 1153, 0 }, - { 70, 1, 1, 1, 1153, 0 }, - { 283, 1, 1, 1, 1153, 0 }, - { 496, 1, 1, 1, 1153, 0 }, - { 662, 1, 1, 1, 1153, 0 }, - { 820, 1, 1, 1, 1153, 0 }, - { 1383, 1, 1, 1, 1153, 0 }, - { 1513, 1, 1, 1, 1153, 0 }, - { 1643, 1, 1, 1, 1153, 0 }, - { 1773, 1, 1, 1, 1153, 0 }, - { 1911, 1, 1, 1, 1153, 0 }, - { 130, 1, 1, 1, 1153, 0 }, - { 343, 1, 1, 1, 1153, 0 }, - { 531, 1, 1, 1, 1153, 0 }, - { 697, 1, 1, 1, 1153, 0 }, - { 842, 1, 1, 1, 1153, 0 }, - { 1405, 1, 1, 1, 1153, 0 }, - { 1535, 1, 1, 1, 1153, 0 }, - { 1665, 1, 1, 1, 1153, 0 }, - { 1795, 1, 1, 1, 1153, 0 }, - { 1933, 1, 1, 1, 1153, 0 }, - { 0, 1, 1, 1, 1153, 0 }, - { 213, 1, 1, 1, 1153, 0 }, - { 426, 1, 1, 1, 1153, 0 }, - { 592, 1, 1, 1, 1153, 0 }, - { 750, 1, 1, 1, 1153, 0 }, - { 1313, 1, 1, 1, 1153, 0 }, - { 1447, 1, 1, 1, 1153, 0 }, - { 1577, 1, 1, 1, 1153, 0 }, - { 1707, 1, 1, 1, 1153, 0 }, - { 1829, 1, 1, 1, 1153, 0 }, - { 45, 1, 1, 1, 1153, 0 }, - { 258, 1, 1, 1, 1153, 0 }, - { 471, 1, 1, 1, 1153, 0 }, - { 637, 1, 1, 1, 1153, 0 }, - { 795, 1, 1, 1, 1153, 0 }, - { 1358, 1, 1, 1, 1153, 0 }, - { 1488, 1, 1, 1, 1153, 0 }, - { 1618, 1, 1, 1, 1153, 0 }, - { 1748, 1, 1, 1, 1153, 0 }, - { 1886, 1, 1, 1, 1153, 0 }, - { 105, 1, 1, 1, 1153, 0 }, - { 318, 1, 1, 1, 1153, 0 }, - { 7, 1, 1, 1, 1153, 0 }, - { 220, 1, 1, 1, 1153, 0 }, - { 433, 1, 1, 1, 1153, 0 }, - { 599, 1, 1, 1, 1153, 0 }, - { 757, 1, 1, 1, 1153, 0 }, - { 1320, 1, 1, 1, 1153, 0 }, - { 1454, 1, 1, 1, 1153, 0 }, - { 1584, 1, 1, 1, 1153, 0 }, - { 1714, 1, 1, 1, 1153, 0 }, - { 1836, 1, 1, 1, 1153, 0 }, - { 52, 1, 1, 1, 1153, 0 }, - { 265, 1, 1, 1, 1153, 0 }, - { 478, 1, 1, 1, 1153, 0 }, - { 644, 1, 1, 1, 1153, 0 }, - { 802, 1, 1, 1, 1153, 0 }, - { 1365, 1, 1, 1, 1153, 0 }, - { 1495, 1, 1, 1, 1153, 0 }, - { 1625, 1, 1, 1, 1153, 0 }, - { 1755, 1, 1, 1, 1153, 0 }, - { 1893, 1, 1, 1, 1153, 0 }, - { 112, 1, 1, 1, 1153, 0 }, - { 325, 1, 1, 1, 1153, 0 }, - { 164, 14, 1, 9, 994, 10 }, - { 377, 17, 1, 9, 994, 10 }, - { 549, 20, 1, 9, 994, 10 }, - { 715, 23, 1, 9, 994, 10 }, - { 1282, 26, 1, 9, 994, 10 }, - { 1416, 29, 1, 9, 994, 10 }, - { 1546, 32, 1, 9, 994, 10 }, - { 1676, 35, 1, 9, 994, 10 }, - { 1801, 38, 1, 9, 994, 10 }, - { 1939, 41, 1, 9, 994, 10 }, - { 14, 44, 1, 9, 994, 10 }, - { 227, 47, 1, 9, 994, 10 }, - { 440, 50, 1, 9, 994, 10 }, - { 606, 53, 1, 9, 994, 10 }, - { 764, 56, 1, 9, 994, 10 }, - { 1327, 59, 1, 9, 994, 10 }, - { 92, 1, 150, 1, 2401, 0 }, - { 305, 1, 148, 1, 2401, 0 }, - { 518, 1, 146, 1, 2401, 0 }, - { 684, 1, 144, 1, 2401, 0 }, - { 167, 1, 161, 1, 3985, 0 }, - { 380, 1, 165, 1, 3985, 0 }, - { 552, 1, 165, 1, 3985, 0 }, - { 718, 1, 169, 1, 3985, 0 }, - { 1285, 1, 169, 1, 3985, 0 }, - { 1419, 1, 173, 1, 3985, 0 }, - { 1549, 1, 173, 1, 3985, 0 }, - { 1679, 1, 177, 1, 3985, 0 }, - { 1804, 1, 177, 1, 3985, 0 }, - { 1942, 1, 181, 1, 3985, 0 }, - { 18, 1, 181, 1, 3985, 0 }, - { 231, 1, 185, 1, 3985, 0 }, - { 444, 1, 185, 1, 3985, 0 }, - { 610, 1, 189, 1, 3985, 0 }, - { 768, 1, 189, 1, 3985, 0 }, - { 1331, 1, 193, 1, 3985, 0 }, - { 1461, 1, 193, 1, 3985, 0 }, - { 1591, 1, 197, 1, 3985, 0 }, - { 1721, 1, 197, 1, 3985, 0 }, - { 1843, 1, 201, 1, 3985, 0 }, - { 59, 1, 201, 1, 3985, 0 }, - { 272, 1, 205, 1, 3985, 0 }, - { 485, 1, 205, 1, 3985, 0 }, - { 651, 1, 209, 1, 3985, 0 }, - { 809, 1, 209, 1, 3985, 0 }, - { 1372, 1, 213, 1, 3985, 0 }, - { 1502, 1, 213, 1, 3985, 0 }, - { 1632, 1, 217, 1, 3985, 0 }, - { 1762, 1, 217, 1, 3985, 0 }, - { 1900, 1, 221, 1, 3985, 0 }, - { 119, 1, 221, 1, 3985, 0 }, - { 332, 1, 225, 1, 3985, 0 }, - { 159, 1, 1, 1, 3985, 0 }, - { 372, 1, 1, 1, 3985, 0 }, - { 544, 1, 1, 1, 3985, 0 }, - { 710, 1, 1, 1, 3985, 0 }, - { 1277, 1, 1, 1, 3985, 0 }, - { 1411, 1, 1, 1, 3985, 0 }, - { 1541, 1, 1, 1, 3985, 0 }, - { 1671, 1, 1, 1, 3985, 0 }, - { 191, 1, 1, 1, 3985, 0 }, - { 404, 1, 1, 1, 3985, 0 }, - { 573, 1, 1, 1, 3985, 0 }, - { 731, 1, 1, 1, 3985, 0 }, - { 1294, 1, 1, 1, 3985, 0 }, - { 1428, 1, 1, 1, 3985, 0 }, - { 1558, 1, 1, 1, 3985, 0 }, - { 1688, 1, 1, 1, 3985, 0 }, - { 1813, 1, 1, 1, 3985, 0 }, - { 1951, 1, 1, 1, 3985, 0 }, - { 29, 1, 1, 1, 3985, 0 }, - { 242, 1, 1, 1, 3985, 0 }, - { 455, 1, 1, 1, 3985, 0 }, - { 621, 1, 1, 1, 3985, 0 }, - { 779, 1, 1, 1, 3985, 0 }, - { 1342, 1, 1, 1, 3985, 0 }, - { 1472, 1, 1, 1, 3985, 0 }, - { 1602, 1, 1, 1, 3985, 0 }, - { 1732, 1, 1, 1, 3985, 0 }, - { 1854, 1, 1, 1, 3985, 0 }, - { 76, 1, 1, 1, 3985, 0 }, - { 289, 1, 1, 1, 3985, 0 }, - { 502, 1, 1, 1, 3985, 0 }, - { 668, 1, 1, 1, 3985, 0 }, - { 826, 1, 1, 1, 3985, 0 }, - { 1389, 1, 1, 1, 3985, 0 }, - { 1519, 1, 1, 1, 3985, 0 }, - { 1649, 1, 1, 1, 3985, 0 }, - { 1779, 1, 1, 1, 3985, 0 }, - { 1917, 1, 1, 1, 3985, 0 }, - { 136, 1, 1, 1, 3985, 0 }, - { 349, 1, 1, 1, 3985, 0 }, - { 1253, 136, 1, 0, 1184, 2 }, - { 170, 1, 158, 1, 3953, 0 }, - { 383, 1, 158, 1, 3953, 0 }, - { 555, 1, 158, 1, 3953, 0 }, - { 721, 1, 158, 1, 3953, 0 }, - { 1288, 1, 158, 1, 3953, 0 }, - { 1422, 1, 158, 1, 3953, 0 }, - { 1552, 1, 158, 1, 3953, 0 }, - { 1682, 1, 158, 1, 3953, 0 }, - { 1807, 1, 158, 1, 3953, 0 }, - { 1945, 1, 158, 1, 3953, 0 }, - { 22, 1, 158, 1, 3953, 0 }, - { 235, 1, 158, 1, 3953, 0 }, - { 448, 1, 158, 1, 3953, 0 }, - { 614, 1, 158, 1, 3953, 0 }, - { 772, 1, 158, 1, 3953, 0 }, - { 1335, 1, 158, 1, 3953, 0 }, - { 1465, 1, 158, 1, 3953, 0 }, - { 1595, 1, 158, 1, 3953, 0 }, - { 1725, 1, 158, 1, 3953, 0 }, - { 1847, 1, 158, 1, 3953, 0 }, - { 63, 1, 158, 1, 3953, 0 }, - { 276, 1, 158, 1, 3953, 0 }, - { 489, 1, 158, 1, 3953, 0 }, - { 655, 1, 158, 1, 3953, 0 }, - { 813, 1, 158, 1, 3953, 0 }, - { 1376, 1, 158, 1, 3953, 0 }, - { 1506, 1, 158, 1, 3953, 0 }, - { 1636, 1, 158, 1, 3953, 0 }, - { 1766, 1, 158, 1, 3953, 0 }, - { 1904, 1, 158, 1, 3953, 0 }, - { 123, 1, 158, 1, 3953, 0 }, - { 336, 1, 158, 1, 3953, 0 }, - { 1259, 128, 1, 0, 1216, 2 }, - { 172, 1, 233, 1, 1826, 0 }, - { 385, 1, 134, 1, 1826, 0 }, - { 557, 1, 134, 1, 1826, 0 }, - { 723, 1, 134, 1, 1826, 0 }, - { 196, 1, 1, 1, 3921, 0 }, - { 409, 1, 1, 1, 3921, 0 }, - { 578, 1, 1, 1, 3921, 0 }, - { 736, 1, 1, 1, 3921, 0 }, - { 1299, 1, 1, 1, 3921, 0 }, - { 1433, 1, 1, 1, 3921, 0 }, - { 1563, 1, 1, 1, 3921, 0 }, - { 1693, 1, 1, 1, 3921, 0 }, - { 1818, 1, 1, 1, 3921, 0 }, - { 1956, 1, 1, 1, 3921, 0 }, - { 35, 1, 1, 1, 3921, 0 }, - { 248, 1, 1, 1, 3921, 0 }, - { 461, 1, 1, 1, 3921, 0 }, - { 627, 1, 1, 1, 3921, 0 }, - { 785, 1, 1, 1, 3921, 0 }, - { 1348, 1, 1, 1, 3921, 0 }, - { 1478, 1, 1, 1, 3921, 0 }, - { 1608, 1, 1, 1, 3921, 0 }, - { 1738, 1, 1, 1, 3921, 0 }, - { 1860, 1, 1, 1, 3921, 0 }, - { 82, 1, 1, 1, 3921, 0 }, - { 295, 1, 1, 1, 3921, 0 }, - { 508, 1, 1, 1, 3921, 0 }, - { 674, 1, 1, 1, 3921, 0 }, - { 832, 1, 1, 1, 3921, 0 }, - { 1395, 1, 1, 1, 3921, 0 }, - { 1525, 1, 1, 1, 3921, 0 }, - { 1655, 1, 1, 1, 3921, 0 }, - { 1785, 1, 1, 1, 3921, 0 }, - { 1923, 1, 1, 1, 3921, 0 }, - { 142, 1, 1, 1, 3921, 0 }, - { 355, 1, 1, 1, 3921, 0 }, - { 176, 1, 100, 1, 3921, 0 }, - { 389, 1, 100, 1, 3921, 0 }, - { 184, 1, 229, 1, 1794, 0 }, - { 397, 1, 126, 1, 1794, 0 }, - { 566, 1, 126, 1, 1794, 0 }, - { 727, 1, 126, 1, 1794, 0 }, - { 179, 1, 1, 1, 3889, 0 }, - { 392, 1, 1, 1, 3889, 0 }, - { 561, 1, 1, 1, 3889, 0 }, - { 188, 1, 1, 1, 3889, 0 }, - { 401, 1, 1, 1, 3889, 0 }, - { 570, 1, 1, 1, 3889, 0 }, - { 1239, 124, 1, 0, 1248, 2 }, - { 201, 1, 98, 1, 3857, 0 }, - { 414, 1, 98, 1, 3857, 0 }, - { 583, 1, 98, 1, 3857, 0 }, - { 741, 1, 98, 1, 3857, 0 }, - { 1304, 1, 98, 1, 3857, 0 }, - { 1438, 1, 98, 1, 3857, 0 }, - { 1568, 1, 98, 1, 3857, 0 }, - { 1698, 1, 98, 1, 3857, 0 }, - { 1265, 122, 1, 0, 1280, 2 }, - { 204, 1, 96, 1, 3825, 0 }, - { 417, 1, 96, 1, 3825, 0 }, - { 586, 1, 96, 1, 3825, 0 }, - { 744, 1, 96, 1, 3825, 0 }, - { 1307, 1, 96, 1, 3825, 0 }, - { 1441, 1, 96, 1, 3825, 0 }, - { 1571, 1, 96, 1, 3825, 0 }, - { 1701, 1, 96, 1, 3825, 0 }, - { 1823, 1, 96, 1, 3825, 0 }, - { 1961, 1, 96, 1, 3825, 0 }, - { 207, 1, 96, 1, 3825, 0 }, - { 420, 1, 96, 1, 3825, 0 }, - { 210, 92, 1, 8, 1425, 10 }, - { 423, 92, 1, 8, 1425, 10 }, - { 589, 92, 1, 8, 1425, 10 }, - { 747, 92, 1, 8, 1425, 10 }, - { 1310, 92, 1, 8, 1425, 10 }, - { 1444, 92, 1, 8, 1425, 10 }, - { 1574, 92, 1, 8, 1425, 10 }, - { 1704, 92, 1, 8, 1425, 10 }, - { 1826, 92, 1, 8, 1425, 10 }, - { 1964, 92, 1, 8, 1425, 10 }, - { 41, 92, 1, 8, 1425, 10 }, - { 254, 92, 1, 8, 1425, 10 }, - { 467, 92, 1, 8, 1425, 10 }, - { 633, 92, 1, 8, 1425, 10 }, - { 791, 92, 1, 8, 1425, 10 }, - { 1354, 92, 1, 8, 1425, 10 }, - { 1484, 92, 1, 8, 1425, 10 }, - { 1614, 92, 1, 8, 1425, 10 }, - { 1744, 92, 1, 8, 1425, 10 }, - { 1866, 92, 1, 8, 1425, 10 }, - { 88, 92, 1, 8, 1425, 10 }, - { 301, 92, 1, 8, 1425, 10 }, - { 514, 92, 1, 8, 1425, 10 }, - { 680, 92, 1, 8, 1425, 10 }, - { 838, 92, 1, 8, 1425, 10 }, - { 1401, 92, 1, 8, 1425, 10 }, - { 1531, 92, 1, 8, 1425, 10 }, - { 1661, 92, 1, 8, 1425, 10 }, - { 1791, 92, 1, 8, 1425, 10 }, - { 1929, 92, 1, 8, 1425, 10 }, - { 148, 92, 1, 8, 1425, 10 }, - { 361, 92, 1, 8, 1425, 10 }, - { 1245, 118, 1, 0, 1921, 2 }, - { 869, 118, 1, 0, 1921, 2 }, - { 947, 118, 1, 0, 1921, 2 }, - { 997, 118, 1, 0, 1921, 2 }, - { 1035, 118, 1, 0, 1921, 2 }, - { 875, 130, 1, 12, 656, 10 }, - { 882, 93, 159, 9, 1377, 10 }, - { 953, 93, 159, 9, 1377, 10 }, - { 1003, 93, 159, 9, 1377, 10 }, - { 1041, 93, 159, 9, 1377, 10 }, - { 1073, 93, 159, 9, 1377, 10 }, - { 1105, 93, 159, 9, 1377, 10 }, - { 1137, 93, 159, 9, 1377, 10 }, - { 1169, 93, 159, 9, 1377, 10 }, - { 1201, 93, 159, 9, 1377, 10 }, - { 1227, 93, 159, 9, 1377, 10 }, - { 848, 93, 159, 9, 1377, 10 }, - { 926, 93, 159, 9, 1377, 10 }, - { 983, 93, 159, 9, 1377, 10 }, - { 1021, 93, 159, 9, 1377, 10 }, - { 1059, 93, 159, 9, 1377, 10 }, - { 1091, 93, 159, 9, 1377, 10 }, - { 1123, 93, 159, 9, 1377, 10 }, - { 1155, 93, 159, 9, 1377, 10 }, - { 1187, 93, 159, 9, 1377, 10 }, - { 1213, 93, 159, 9, 1377, 10 }, - { 855, 93, 159, 9, 1377, 10 }, - { 933, 93, 159, 9, 1377, 10 }, - { 990, 93, 159, 9, 1377, 10 }, - { 1028, 93, 159, 9, 1377, 10 }, - { 1066, 93, 159, 9, 1377, 10 }, - { 1098, 93, 159, 9, 1377, 10 }, - { 1130, 93, 159, 9, 1377, 10 }, - { 1162, 93, 159, 9, 1377, 10 }, - { 1194, 93, 159, 9, 1377, 10 }, - { 1220, 93, 159, 9, 1377, 10 }, - { 862, 93, 159, 9, 1377, 10 }, - { 940, 93, 159, 9, 1377, 10 }, - { 1870, 1, 116, 1, 1120, 0 }, - { 888, 138, 235, 0, 1344, 2 }, - { 895, 152, 1, 0, 2241, 2 }, - { 959, 152, 1, 0, 2241, 2 }, - { 901, 152, 231, 0, 1312, 2 }, - { 908, 154, 1, 0, 2273, 2 }, - { 965, 154, 1, 0, 2273, 2 }, - { 1009, 154, 1, 0, 2273, 2 }, - { 1047, 154, 1, 0, 2273, 2 }, - { 1079, 154, 1, 0, 2273, 2 }, - { 1111, 154, 1, 0, 2273, 2 }, - { 1143, 154, 1, 0, 2273, 2 }, - { 1175, 154, 1, 0, 2273, 2 }, - { 914, 156, 1, 0, 2273, 2 }, - { 971, 156, 1, 0, 2273, 2 }, - { 1015, 156, 1, 0, 2273, 2 }, - { 1053, 156, 1, 0, 2273, 2 }, - { 1085, 156, 1, 0, 2273, 2 }, - { 1117, 156, 1, 0, 2273, 2 }, - { 1149, 156, 1, 0, 2273, 2 }, - { 1181, 156, 1, 0, 2273, 2 }, - { 1207, 156, 1, 0, 2273, 2 }, - { 1233, 156, 1, 0, 2273, 2 }, - { 920, 156, 1, 0, 2273, 2 }, - { 977, 156, 1, 0, 2273, 2 }, -}; - - // OddSP Register Class... - static const MCPhysReg OddSP[] = { - Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // OddSP Bit set. - static const uint8_t OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, - }; - - // CCR Register Class... - static const MCPhysReg CCR[] = { - Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, - }; - - // CCR Bit set. - static const uint8_t CCRBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // COP2 Register Class... - static const MCPhysReg COP2[] = { - Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, - }; - - // COP2 Bit set. - static const uint8_t COP2Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01, - }; - - // COP3 Register Class... - static const MCPhysReg COP3[] = { - Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, - }; - - // COP3 Bit set. - static const uint8_t COP3Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f, - }; - - // DSPR Register Class... - static const MCPhysReg DSPR[] = { - Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, - }; - - // DSPR Bit set. - static const uint8_t DSPRBits[] = { - 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, - }; - - // FGR32 Register Class... - static const MCPhysReg FGR32[] = { - Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, - }; - - // FGR32 Bit set. - static const uint8_t FGR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // FGRCC Register Class... - static const MCPhysReg FGRCC[] = { - Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, - }; - - // FGRCC Bit set. - static const uint8_t FGRCCBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // FGRH32 Register Class... - static const MCPhysReg FGRH32[] = { - Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31, - }; - - // FGRH32 Bit set. - static const uint8_t FGRH32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, - }; - - // GPR32 Register Class... - static const MCPhysReg GPR32[] = { - Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, - }; - - // GPR32 Bit set. - static const uint8_t GPR32Bits[] = { - 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, - }; - - // HWRegs Register Class... - static const MCPhysReg HWRegs[] = { - Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, - }; - - // HWRegs Bit set. - static const uint8_t HWRegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, - }; - - // OddSP_with_sub_hi Register Class... - static const MCPhysReg OddSP_with_sub_hi[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // OddSP_with_sub_hi Bit set. - static const uint8_t OddSP_with_sub_hiBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, - }; - - // FGR32_and_OddSP Register Class... - static const MCPhysReg FGR32_and_OddSP[] = { - Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, - }; - - // FGR32_and_OddSP Bit set. - static const uint8_t FGR32_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, - }; - - // FGRH32_and_OddSP Register Class... - static const MCPhysReg FGRH32_and_OddSP[] = { - Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, - }; - - // FGRH32_and_OddSP Bit set. - static const uint8_t FGRH32_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, - }; - - // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... - static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { - Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. - static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, - }; - - // CPU16RegsPlusSP Register Class... - static const MCPhysReg CPU16RegsPlusSP[] = { - Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, - }; - - // CPU16RegsPlusSP Bit set. - static const uint8_t CPU16RegsPlusSPBits[] = { - 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // CC Register Class... - static const MCPhysReg CC[] = { - Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7, - }; - - // CC Bit set. - static const uint8_t CCBits[] = { - 0x00, 0x00, 0x00, 0x80, 0x7f, - }; - - // CPU16Regs Register Class... - static const MCPhysReg CPU16Regs[] = { - Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, - }; - - // CPU16Regs Bit set. - static const uint8_t CPU16RegsBits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // FCC Register Class... - static const MCPhysReg FCC[] = { - Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, - }; - - // FCC Bit set. - static const uint8_t FCCBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, - }; - - // GPRMM16 Register Class... - static const MCPhysReg GPRMM16[] = { - Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, - }; - - // GPRMM16 Bit set. - static const uint8_t GPRMM16Bits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // GPRMM16MoveP Register Class... - static const MCPhysReg GPRMM16MoveP[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, - }; - - // GPRMM16MoveP Bit set. - static const uint8_t GPRMM16MovePBits[] = { - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, - }; - - // GPRMM16Zero Register Class... - static const MCPhysReg GPRMM16Zero[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, - }; - - // GPRMM16Zero Bit set. - static const uint8_t GPRMM16ZeroBits[] = { - 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, - }; - - // MSACtrl Register Class... - static const MCPhysReg MSACtrl[] = { - Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, - }; - - // MSACtrl Bit set. - static const uint8_t MSACtrlBits[] = { - 0x00, 0xfc, 0x03, - }; - - // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... - static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, - }; - - // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. - static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, - }; - - // CPU16Regs_and_GPRMM16Zero Register Class... - static const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { - Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, - }; - - // CPU16Regs_and_GPRMM16Zero Bit set. - static const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, - }; - - // CPU16Regs_and_GPRMM16MoveP Register Class... - static const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { - Mips_S1, Mips_V0, Mips_V1, Mips_S0, - }; - - // CPU16Regs_and_GPRMM16MoveP Bit set. - static const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // GPRMM16MoveP_and_GPRMM16Zero Register Class... - static const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, - }; - - // GPRMM16MoveP_and_GPRMM16Zero Bit set. - static const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, - }; - - // HI32DSP Register Class... - static const MCPhysReg HI32DSP[] = { - Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, - }; - - // HI32DSP Bit set. - static const uint8_t HI32DSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, - }; - - // LO32DSP Register Class... - static const MCPhysReg LO32DSP[] = { - Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, - }; - - // LO32DSP Bit set. - static const uint8_t LO32DSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, - }; - - // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... - static const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { - Mips_S1, Mips_V0, Mips_V1, - }; - - // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. - static const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, - }; - - // CPURAReg Register Class... - static const MCPhysReg CPURAReg[] = { - Mips_RA, - }; - - // CPURAReg Bit set. - static const uint8_t CPURARegBits[] = { - 0x00, 0x00, 0x08, - }; - - // CPUSPReg Register Class... - static const MCPhysReg CPUSPReg[] = { - Mips_SP, - }; - - // CPUSPReg Bit set. - static const uint8_t CPUSPRegBits[] = { - 0x00, 0x00, 0x10, - }; - - // DSPCC Register Class... - static const MCPhysReg DSPCC[] = { - Mips_DSPCCond, - }; - - // DSPCC Bit set. - static const uint8_t DSPCCBits[] = { - 0x04, - }; - - // HI32 Register Class... - static const MCPhysReg HI32[] = { - Mips_HI0, - }; - - // HI32 Bit set. - static const uint8_t HI32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, - }; - - // LO32 Register Class... - static const MCPhysReg LO32[] = { - Mips_LO0, - }; - - // LO32 Bit set. - static const uint8_t LO32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, - }; - - // FGR64 Register Class... - static const MCPhysReg FGR64[] = { - Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, - }; - - // FGR64 Bit set. - static const uint8_t FGR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, - }; - - // GPR64 Register Class... - static const MCPhysReg GPR64[] = { - Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, - }; - - // GPR64 Bit set. - static const uint8_t GPR64Bits[] = { - 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, - }; - - // AFGR64 Register Class... - static const MCPhysReg AFGR64[] = { - Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, - }; - - // AFGR64 Bit set. - static const uint8_t AFGR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, - }; - - // FGR64_and_OddSP Register Class... - static const MCPhysReg FGR64_and_OddSP[] = { - Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // FGR64_and_OddSP Bit set. - static const uint8_t FGR64_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, - }; - - // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, - }; - - // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. - static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, - }; - - // AFGR64_and_OddSP Register Class... - static const MCPhysReg AFGR64_and_OddSP[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, - }; - - // AFGR64_and_OddSP Bit set. - static const uint8_t AFGR64_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, - }; - - // GPR64_with_sub_32_in_CPU16Regs Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_CPU16Regs Bit set. - static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... - static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. - static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, - }; - - // GPR64_with_sub_32_in_GPRMM16Zero Register Class... - static const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_GPRMM16Zero Bit set. - static const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, - }; - - // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. - static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, - }; - - // ACC64DSP Register Class... - static const MCPhysReg ACC64DSP[] = { - Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, - }; - - // ACC64DSP Bit set. - static const uint8_t ACC64DSPBits[] = { - 0x00, 0x00, 0x00, 0x3c, - }; - - // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { - Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. - static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... - static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. - static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... - static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { - Mips_V0_64, Mips_V1_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. - static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, - }; - - // OCTEON_MPL Register Class... - static const MCPhysReg OCTEON_MPL[] = { - Mips_MPL0, Mips_MPL1, Mips_MPL2, - }; - - // OCTEON_MPL Bit set. - static const uint8_t OCTEON_MPLBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, - }; - - // OCTEON_P Register Class... - static const MCPhysReg OCTEON_P[] = { - Mips_P0, Mips_P1, Mips_P2, - }; - - // OCTEON_P Bit set. - static const uint8_t OCTEON_PBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, - }; - - // ACC64 Register Class... - static const MCPhysReg ACC64[] = { - Mips_AC0, - }; - - // ACC64 Bit set. - static const uint8_t ACC64Bits[] = { - 0x00, 0x00, 0x00, 0x04, - }; - - // GPR64_with_sub_32_in_CPURAReg Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { - Mips_RA_64, - }; - - // GPR64_with_sub_32_in_CPURAReg Bit set. - static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, - }; - - // GPR64_with_sub_32_in_CPUSPReg Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { - Mips_SP_64, - }; - - // GPR64_with_sub_32_in_CPUSPReg Bit set. - static const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, - }; - - // HI64 Register Class... - static const MCPhysReg HI64[] = { - Mips_HI0_64, - }; - - // HI64 Bit set. - static const uint8_t HI64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, - }; - - // LO64 Register Class... - static const MCPhysReg LO64[] = { - Mips_LO0_64, - }; - - // LO64 Bit set. - static const uint8_t LO64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, - }; - - // MSA128B Register Class... - static const MCPhysReg MSA128B[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, - }; - - // MSA128B Bit set. - static const uint8_t MSA128BBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // MSA128D Register Class... - static const MCPhysReg MSA128D[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, - }; - - // MSA128D Bit set. - static const uint8_t MSA128DBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // MSA128H Register Class... - static const MCPhysReg MSA128H[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, - }; - - // MSA128H Bit set. - static const uint8_t MSA128HBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // MSA128W Register Class... - static const MCPhysReg MSA128W[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, - }; - - // MSA128W Bit set. - static const uint8_t MSA128WBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // MSA128B_with_sub_64_in_OddSP Register Class... - static const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { - Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31, - }; - - // MSA128B_with_sub_64_in_OddSP Bit set. - static const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, - }; - - // MSA128WEvens Register Class... - static const MCPhysReg MSA128WEvens[] = { - Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30, - }; - - // MSA128WEvens Bit set. - static const uint8_t MSA128WEvensBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, - }; - - // ACC128 Register Class... - static const MCPhysReg ACC128[] = { - Mips_AC0_64, - }; - - // ACC128 Bit set. - static const uint8_t ACC128Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - }; - -static const MCRegisterClass MipsMCRegisterClasses[] = { - { OddSP, OddSPBits, sizeof(OddSPBits) }, - { CCR, CCRBits, sizeof(CCRBits) }, - { COP2, COP2Bits, sizeof(COP2Bits) }, - { COP3, COP3Bits, sizeof(COP3Bits) }, - { DSPR, DSPRBits, sizeof(DSPRBits) }, - { FGR32, FGR32Bits, sizeof(FGR32Bits) }, - { FGRCC, FGRCCBits, sizeof(FGRCCBits) }, - { FGRH32, FGRH32Bits, sizeof(FGRH32Bits) }, - { GPR32, GPR32Bits, sizeof(GPR32Bits) }, - { HWRegs, HWRegsBits, sizeof(HWRegsBits) }, - { OddSP_with_sub_hi, OddSP_with_sub_hiBits, sizeof(OddSP_with_sub_hiBits) }, - { FGR32_and_OddSP, FGR32_and_OddSPBits, sizeof(FGR32_and_OddSPBits) }, - { FGRH32_and_OddSP, FGRH32_and_OddSPBits, sizeof(FGRH32_and_OddSPBits) }, - { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits) }, - { CPU16RegsPlusSP, CPU16RegsPlusSPBits, sizeof(CPU16RegsPlusSPBits) }, - { CC, CCBits, sizeof(CCBits) }, - { CPU16Regs, CPU16RegsBits, sizeof(CPU16RegsBits) }, - { FCC, FCCBits, sizeof(FCCBits) }, - { GPRMM16, GPRMM16Bits, sizeof(GPRMM16Bits) }, - { GPRMM16MoveP, GPRMM16MovePBits, sizeof(GPRMM16MovePBits) }, - { GPRMM16Zero, GPRMM16ZeroBits, sizeof(GPRMM16ZeroBits) }, - { MSACtrl, MSACtrlBits, sizeof(MSACtrlBits) }, - { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits) }, - { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, sizeof(CPU16Regs_and_GPRMM16ZeroBits) }, - { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, sizeof(CPU16Regs_and_GPRMM16MovePBits) }, - { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits) }, - { HI32DSP, HI32DSPBits, sizeof(HI32DSPBits) }, - { LO32DSP, LO32DSPBits, sizeof(LO32DSPBits) }, - { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) }, - { CPURAReg, CPURARegBits, sizeof(CPURARegBits) }, - { CPUSPReg, CPUSPRegBits, sizeof(CPUSPRegBits) }, - { DSPCC, DSPCCBits, sizeof(DSPCCBits) }, - { HI32, HI32Bits, sizeof(HI32Bits) }, - { LO32, LO32Bits, sizeof(LO32Bits) }, - { FGR64, FGR64Bits, sizeof(FGR64Bits) }, - { GPR64, GPR64Bits, sizeof(GPR64Bits) }, - { AFGR64, AFGR64Bits, sizeof(AFGR64Bits) }, - { FGR64_and_OddSP, FGR64_and_OddSPBits, sizeof(FGR64_and_OddSPBits) }, - { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits) }, - { AFGR64_and_OddSP, AFGR64_and_OddSPBits, sizeof(AFGR64_and_OddSPBits) }, - { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, sizeof(GPR64_with_sub_32_in_CPU16RegsBits) }, - { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits) }, - { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits) }, - { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits) }, - { ACC64DSP, ACC64DSPBits, sizeof(ACC64DSPBits) }, - { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits) }, - { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits) }, - { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) }, - { OCTEON_MPL, OCTEON_MPLBits, sizeof(OCTEON_MPLBits) }, - { OCTEON_P, OCTEON_PBits, sizeof(OCTEON_PBits) }, - { ACC64, ACC64Bits, sizeof(ACC64Bits) }, - { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, sizeof(GPR64_with_sub_32_in_CPURARegBits) }, - { GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, sizeof(GPR64_with_sub_32_in_CPUSPRegBits) }, - { HI64, HI64Bits, sizeof(HI64Bits) }, - { LO64, LO64Bits, sizeof(LO64Bits) }, - { MSA128B, MSA128BBits, sizeof(MSA128BBits) }, - { MSA128D, MSA128DBits, sizeof(MSA128DBits) }, - { MSA128H, MSA128HBits, sizeof(MSA128HBits) }, - { MSA128W, MSA128WBits, sizeof(MSA128WBits) }, - { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, sizeof(MSA128B_with_sub_64_in_OddSPBits) }, - { MSA128WEvens, MSA128WEvensBits, sizeof(MSA128WEvensBits) }, - { ACC128, ACC128Bits, sizeof(ACC128Bits) }, -}; - -#endif // GET_REGINFO_MC_DESC diff --git a/arch/Mips/MipsGenSubtargetInfo.inc b/arch/Mips/MipsGenSubtargetInfo.inc deleted file mode 100644 index 36e7a7f866..0000000000 --- a/arch/Mips/MipsGenSubtargetInfo.inc +++ /dev/null @@ -1,52 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Subtarget Enumeration Source Fragment *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ - - -#ifdef GET_SUBTARGETINFO_ENUM -#undef GET_SUBTARGETINFO_ENUM - -#define Mips_FeatureCnMips (1ULL << 0) -#define Mips_FeatureDSP (1ULL << 1) -#define Mips_FeatureDSPR2 (1ULL << 2) -#define Mips_FeatureFP64Bit (1ULL << 3) -#define Mips_FeatureFPXX (1ULL << 4) -#define Mips_FeatureGP64Bit (1ULL << 5) -#define Mips_FeatureMSA (1ULL << 6) -#define Mips_FeatureMicroMips (1ULL << 7) -#define Mips_FeatureMips1 (1ULL << 8) -#define Mips_FeatureMips2 (1ULL << 9) -#define Mips_FeatureMips3 (1ULL << 10) -#define Mips_FeatureMips3_32 (1ULL << 11) -#define Mips_FeatureMips3_32r2 (1ULL << 12) -#define Mips_FeatureMips4 (1ULL << 13) -#define Mips_FeatureMips4_32 (1ULL << 14) -#define Mips_FeatureMips4_32r2 (1ULL << 15) -#define Mips_FeatureMips5 (1ULL << 16) -#define Mips_FeatureMips5_32r2 (1ULL << 17) -#define Mips_FeatureMips16 (1ULL << 18) -#define Mips_FeatureMips32 (1ULL << 19) -#define Mips_FeatureMips32r2 (1ULL << 20) -#define Mips_FeatureMips32r3 (1ULL << 21) -#define Mips_FeatureMips32r5 (1ULL << 22) -#define Mips_FeatureMips32r6 (1ULL << 23) -#define Mips_FeatureMips64 (1ULL << 24) -#define Mips_FeatureMips64r2 (1ULL << 25) -#define Mips_FeatureMips64r3 (1ULL << 26) -#define Mips_FeatureMips64r5 (1ULL << 27) -#define Mips_FeatureMips64r6 (1ULL << 28) -#define Mips_FeatureNaN2008 (1ULL << 29) -#define Mips_FeatureNoABICalls (1ULL << 30) -#define Mips_FeatureNoOddSPReg (1ULL << 31) -#define Mips_FeatureSingleFloat (1ULL << 32) -#define Mips_FeatureVFPU (1ULL << 33) - -#endif // GET_SUBTARGETINFO_ENUM - diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c index 9bbf4bc2e5..247533d863 100644 --- a/arch/Mips/MipsInstPrinter.c +++ b/arch/Mips/MipsInstPrinter.c @@ -31,8 +31,11 @@ #include "MipsInstPrinter.h" static void printUnsignedImm(MCInst *MI, int opNum, SStream *O); -static char *printAliasInstr(MCInst *MI, SStream *O, void *info); +#define printUImm(MI, Op, O, ...) printUnsignedImm(MI, Op, O) +static char *printAliasInstr(MCInst *MI, SStream *O); static char *printAlias(MCInst *MI, SStream *OS); +static void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); // These enumeration declarations were originally in MipsInstrInfo.h but // had to be moved here to avoid circular dependencies between @@ -79,11 +82,24 @@ typedef enum Mips_CondCode { Mips_FCOND_GT } Mips_CondCode; -#define GET_INSTRINFO_ENUM -#include "MipsGenInstrInfo.inc" static const char *getRegisterName(unsigned RegNo); -static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); +static void printInstruction(MCInst *MI, SStream *O); +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printMemOperand(MCInst *MI, int opNum, SStream *O, char *); +static void printMemOperandEA(MCInst *MI, int opNum, SStream *O, char *); +static void printFCCOperand(MCInst *MI, int opNum, SStream *O); +static void printRegisterList(MCInst *MI, int opNum, SStream *O); + +#include "../MCInstPrinter.h" + + +#define GET_INSTRINFO_ENUM +#define GET_REGINFO_ENUM +#define GET_ASM_WRITER +#define PRINT_ALIAS_INSTR +#include "MipsGenDisassemblerTables.inc" + static void set_mem_access(MCInst *MI, bool status) { @@ -149,6 +165,11 @@ static const char* MipsFCCToString(Mips_CondCode CC) static void printRegName(SStream *OS, unsigned RegNo) { + const char *Name = Mips_reg_name(0, RegNo); + + if (Name) + SStream_concat(OS, "$%s", Name); + else SStream_concat(OS, "$%s", getRegisterName(RegNo)); } @@ -156,6 +177,8 @@ void Mips_printInst(MCInst *MI, SStream *O, void *info) { char *mnem; + MRI = info; + switch (MCInst_getOpcode(MI)) { default: break; case Mips_Save16: @@ -166,11 +189,11 @@ void Mips_printInst(MCInst *MI, SStream *O, void *info) } // Try to print any aliases first. - mnem = printAliasInstr(MI, O, info); + mnem = printAliasInstr(MI, O); if (!mnem) { mnem = printAlias(MI, O); if (!mnem) { - printInstruction(MI, O, NULL); + printInstruction(MI, O); } } @@ -192,7 +215,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) if (MCOperand_isReg(Op)) { unsigned int reg = MCOperand_getReg(Op); printRegName(O, reg); - reg = Mips_map_register(reg); +// reg = Mips_map_register(reg); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg; @@ -256,7 +279,7 @@ static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O) printOperand(MI, opNum, O); } -static void printMemOperand(MCInst *MI, int opNum, SStream *O) +static void printMemOperand(MCInst *MI, int opNum, SStream *O, char *unused) { // Load/Store memory operands -- imm($reg) // If PIC target the target is loaded as the @@ -284,7 +307,7 @@ static void printMemOperand(MCInst *MI, int opNum, SStream *O) } // TODO??? -static void printMemOperandEA(MCInst *MI, int opNum, SStream *O) +static void printMemOperandEA(MCInst *MI, int opNum, SStream *O, char *unused) { // when using stack locations for not load/store instructions // print the same way as all normal 3 operand instructions. @@ -324,9 +347,6 @@ static char *printAlias2(const char *Str, MCInst *MI, return tmp; } -#define GET_REGINFO_ENUM -#include "MipsGenRegisterInfo.inc" - static char *printAlias(MCInst *MI, SStream *OS) { switch (MCInst_getOpcode(MI)) { @@ -418,7 +438,4 @@ static void printRegisterList(MCInst *MI, int opNum, SStream *O) } } -#define PRINT_ALIAS_INSTR -#include "MipsGenAsmWriter.inc" - #endif diff --git a/arch/Mips/MipsMapperInfo.inc b/arch/Mips/MipsMapperInfo.inc new file mode 100644 index 0000000000..65f7342010 --- /dev/null +++ b/arch/Mips/MipsMapperInfo.inc @@ -0,0 +1,30121 @@ +static const insn_map insns[] = { + // dummy item + {0, + 0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + + {/* abs */ + Mips_ABSMacro, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* abs.d */ + Mips_FABS_D32, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* abs.d */ + Mips_FABS_D32_MM, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* abs.d */ + Mips_FABS_D64, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* abs.d */ + Mips_FABS_D64_MM, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* abs.s */ + Mips_FABS_S, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* abs.s */ + Mips_FABS_S_MM, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* absq_s.ph */ + Mips_ABSQ_S_PH_MM, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* absq_s.ph */ + Mips_ABSQ_S_PH, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* absq_s.qb */ + Mips_ABSQ_S_QB_MMR2, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* absq_s.qb */ + Mips_ABSQ_S_QB, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* absq_s.w */ + Mips_ABSQ_S_W_MM, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* absq_s.w */ + Mips_ABSQ_S_W, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD_MMR6, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADDi, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADDi_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD_MMR6, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADDi, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADDi_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add.d */ + Mips_FADD_D32, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add.d */ + Mips_FADD_D32_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* add.d */ + Mips_FADD_D64, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add.d */ + Mips_FADD_D64_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* add.ps */ + Mips_FADD_PS64, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add.s */ + Mips_FADD_S, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add.s */ + Mips_FADD_S_MMR6, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* add.s */ + Mips_FADD_S_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* add_a.b */ + Mips_ADD_A_B, + MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* add_a.d */ + Mips_ADD_A_D, + MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* add_a.h */ + Mips_ADD_A_H, + MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* add_a.w */ + Mips_ADD_A_W, + MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addi */ + Mips_ADDi_MM, + MIPS_INS_ADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addi */ + Mips_ADDi, + MIPS_INS_ADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addi */ + Mips_ADDi_MM, + MIPS_INS_ADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addi */ + Mips_ADDi, + MIPS_INS_ADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuSpImmX16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuRxImmX16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDIU_MMR6, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDiu_MM, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDiu, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuRxPcImmX16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuRxRyOffMemX16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDIU_MMR6, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDiu_MM, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDiu, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuSpImm16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuRxRxImm16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiupc */ + Mips_ADDIUPC, + MIPS_INS_ADDIUPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiupc */ + Mips_ADDIUPC_MMR6, + MIPS_INS_ADDIUPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiupc */ + Mips_ADDIUPC_MM, + MIPS_INS_ADDIUPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiur1sp */ + Mips_ADDIUR1SP_MM, + MIPS_INS_ADDIUR1SP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addiur2 */ + Mips_ADDIUR2_MM, + MIPS_INS_ADDIUR2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addius5 */ + Mips_ADDIUS5_MM, + MIPS_INS_ADDIUS5, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addiusp */ + Mips_ADDIUSP_MM, + MIPS_INS_ADDIUSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addq.ph */ + Mips_ADDQ_PH_MM, + MIPS_INS_ADDQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addq.ph */ + Mips_ADDQ_PH, + MIPS_INS_ADDQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addq_s.ph */ + Mips_ADDQ_S_PH_MM, + MIPS_INS_ADDQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addq_s.ph */ + Mips_ADDQ_S_PH, + MIPS_INS_ADDQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addq_s.w */ + Mips_ADDQ_S_W_MM, + MIPS_INS_ADDQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addq_s.w */ + Mips_ADDQ_S_W, + MIPS_INS_ADDQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addqh.ph */ + Mips_ADDQH_PH_MMR2, + MIPS_INS_ADDQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh.ph */ + Mips_ADDQH_PH, + MIPS_INS_ADDQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh.w */ + Mips_ADDQH_W_MMR2, + MIPS_INS_ADDQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh.w */ + Mips_ADDQH_W, + MIPS_INS_ADDQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh_r.ph */ + Mips_ADDQH_R_PH_MMR2, + MIPS_INS_ADDQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh_r.ph */ + Mips_ADDQH_R_PH, + MIPS_INS_ADDQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh_r.w */ + Mips_ADDQH_R_W_MMR2, + MIPS_INS_ADDQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh_r.w */ + Mips_ADDQH_R_W, + MIPS_INS_ADDQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addr.ps */ + Mips_ADDR_PS64, + MIPS_INS_ADDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MIPS3D, 0}, + 0, + 0 +#endif + }, + {/* adds_a.b */ + Mips_ADDS_A_B, + MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_a.d */ + Mips_ADDS_A_D, + MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_a.h */ + Mips_ADDS_A_H, + MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_a.w */ + Mips_ADDS_A_W, + MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_s.b */ + Mips_ADDS_S_B, + MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_s.d */ + Mips_ADDS_S_D, + MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_s.h */ + Mips_ADDS_S_H, + MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_s.w */ + Mips_ADDS_S_W, + MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_u.b */ + Mips_ADDS_U_B, + MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_u.d */ + Mips_ADDS_U_D, + MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_u.h */ + Mips_ADDS_U_H, + MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_u.w */ + Mips_ADDS_U_W, + MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addsc */ + Mips_ADDSC_MM, + MIPS_INS_ADDSC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addsc */ + Mips_ADDSC, + MIPS_INS_ADDSC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDU_MMR6, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDu, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDu_MM, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDiu, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDiu_MM, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_AdduRxRyRz16, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDU_MMR6, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDu, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDu_MM, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDiu, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDiu_MM, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu.ph */ + Mips_ADDU_PH_MMR2, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addu.ph */ + Mips_ADDU_PH, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addu.qb */ + Mips_ADDU_QB_MM, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addu.qb */ + Mips_ADDU_QB, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addu16 */ + Mips_ADDU16_MM, + MIPS_INS_ADDU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu16 */ + Mips_ADDU16_MMR6, + MIPS_INS_ADDU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu_s.ph */ + Mips_ADDU_S_PH_MMR2, + MIPS_INS_ADDU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addu_s.ph */ + Mips_ADDU_S_PH, + MIPS_INS_ADDU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addu_s.qb */ + Mips_ADDU_S_QB_MM, + MIPS_INS_ADDU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addu_s.qb */ + Mips_ADDU_S_QB, + MIPS_INS_ADDU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* adduh.qb */ + Mips_ADDUH_QB_MMR2, + MIPS_INS_ADDUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* adduh.qb */ + Mips_ADDUH_QB, + MIPS_INS_ADDUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* adduh_r.qb */ + Mips_ADDUH_R_QB_MMR2, + MIPS_INS_ADDUH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* adduh_r.qb */ + Mips_ADDUH_R_QB, + MIPS_INS_ADDUH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addv.b */ + Mips_ADDV_B, + MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addv.d */ + Mips_ADDV_D, + MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addv.h */ + Mips_ADDV_H, + MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addv.w */ + Mips_ADDV_W, + MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addvi.b */ + Mips_ADDVI_B, + MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addvi.d */ + Mips_ADDVI_D, + MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addvi.h */ + Mips_ADDVI_H, + MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addvi.w */ + Mips_ADDVI_W, + MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addwc */ + Mips_ADDWC_MM, + MIPS_INS_ADDWC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addwc */ + Mips_ADDWC, + MIPS_INS_ADDWC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* align */ + Mips_ALIGN, + MIPS_INS_ALIGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* align */ + Mips_ALIGN_MMR6, + MIPS_INS_ALIGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* aluipc */ + Mips_ALUIPC, + MIPS_INS_ALUIPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* aluipc */ + Mips_ALUIPC_MMR6, + MIPS_INS_ALUIPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AndRxRxRy16, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND_MM, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND_MMR6, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDI_MMR6, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi_MM, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi64, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND_MM, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND_MMR6, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDI_MMR6, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi_MM, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi64, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and.v */ + Mips_AND_V, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* and16 */ + Mips_AND16_MM, + MIPS_INS_AND16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and16 */ + Mips_AND16_MMR6, + MIPS_INS_AND16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDI_MMR6, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDi, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDi_MM, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDI_MMR6, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDi, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDi_MM, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi.b */ + Mips_ANDI_B, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* andi16 */ + Mips_ANDI16_MM, + MIPS_INS_ANDI16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi16 */ + Mips_ANDI16_MMR6, + MIPS_INS_ANDI16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* append */ + Mips_APPEND_MMR2, + MIPS_INS_APPEND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* append */ + Mips_APPEND, + MIPS_INS_APPEND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* asub_s.b */ + Mips_ASUB_S_B, + MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_s.d */ + Mips_ASUB_S_D, + MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_s.h */ + Mips_ASUB_S_H, + MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_s.w */ + Mips_ASUB_S_W, + MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_u.b */ + Mips_ASUB_U_B, + MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_u.d */ + Mips_ASUB_U_D, + MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_u.h */ + Mips_ASUB_U_H, + MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_u.w */ + Mips_ASUB_U_W, + MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aui */ + Mips_AUI, + MIPS_INS_AUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* aui */ + Mips_AUI_MMR6, + MIPS_INS_AUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* auipc */ + Mips_AUIPC, + MIPS_INS_AUIPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* auipc */ + Mips_AUIPC_MMR6, + MIPS_INS_AUIPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ave_s.b */ + Mips_AVE_S_B, + MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_s.d */ + Mips_AVE_S_D, + MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_s.h */ + Mips_AVE_S_H, + MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_s.w */ + Mips_AVE_S_W, + MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_u.b */ + Mips_AVE_U_B, + MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_u.d */ + Mips_AVE_U_D, + MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_u.h */ + Mips_AVE_U_H, + MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_u.w */ + Mips_AVE_U_W, + MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_s.b */ + Mips_AVER_S_B, + MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_s.d */ + Mips_AVER_S_D, + MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_s.h */ + Mips_AVER_S_H, + MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_s.w */ + Mips_AVER_S_W, + MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_u.b */ + Mips_AVER_U_B, + MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_u.d */ + Mips_AVER_U_D, + MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_u.h */ + Mips_AVER_U_H, + MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_u.w */ + Mips_AVER_U_W, + MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* b */ + Mips_BEQ, + MIPS_INS_B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* b */ + Mips_B_MM_Pseudo, + MIPS_INS_B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* b */ + Mips_BimmX16, + MIPS_INS_B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* b */ + Mips_B_MMR6_Pseudo, + MIPS_INS_B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* b */ + Mips_Bimm16, + MIPS_INS_B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* b16 */ + Mips_BC16_MMR6, + MIPS_INS_B16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* b16 */ + Mips_B16_MM, + MIPS_INS_B16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* baddu */ + Mips_BADDu, + MIPS_INS_BADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* baddu */ + Mips_BADDu, + MIPS_INS_BADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* bal */ + Mips_BGEZAL, + MIPS_INS_BAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* bal */ + Mips_BAL, + MIPS_INS_BAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bal */ + Mips_BGEZAL_MM, + MIPS_INS_BAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* balc */ + Mips_BALC, + MIPS_INS_BALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* balc */ + Mips_BALC_MMR6, + MIPS_INS_BALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* balign */ + Mips_BALIGN_MMR2, + MIPS_INS_BALIGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* balign */ + Mips_BALIGN, + MIPS_INS_BALIGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* bbit0 */ + Mips_BBIT032, + MIPS_INS_BBIT0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bbit0 */ + Mips_BBIT0, + MIPS_INS_BBIT0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bbit032 */ + Mips_BBIT032, + MIPS_INS_BBIT032, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bbit1 */ + Mips_BBIT132, + MIPS_INS_BBIT1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bbit1 */ + Mips_BBIT1, + MIPS_INS_BBIT1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bbit132 */ + Mips_BBIT132, + MIPS_INS_BBIT132, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc */ + Mips_BC, + MIPS_INS_BC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc */ + Mips_BC_MMR6, + MIPS_INS_BC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bc16 */ + Mips_BC16_MMR6, + MIPS_INS_BC16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bc1eqz */ + Mips_BC1EQZ, + MIPS_INS_BC1EQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1eqzc */ + Mips_BC1EQZC_MMR6, + MIPS_INS_BC1EQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1f */ + Mips_BC1F, + MIPS_INS_BC1F, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1f */ + Mips_BC1F_MM, + MIPS_INS_BC1F, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1f */ + Mips_BC1F, + MIPS_INS_BC1F, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1f */ + Mips_BC1F_MM, + MIPS_INS_BC1F, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1fl */ + Mips_BC1FL, + MIPS_INS_BC1FL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1fl */ + Mips_BC1FL, + MIPS_INS_BC1FL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1nez */ + Mips_BC1NEZ, + MIPS_INS_BC1NEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1nezc */ + Mips_BC1NEZC_MMR6, + MIPS_INS_BC1NEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1t */ + Mips_BC1T, + MIPS_INS_BC1T, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1t */ + Mips_BC1T_MM, + MIPS_INS_BC1T, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1t */ + Mips_BC1T, + MIPS_INS_BC1T, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1t */ + Mips_BC1T_MM, + MIPS_INS_BC1T, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1tl */ + Mips_BC1TL, + MIPS_INS_BC1TL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1tl */ + Mips_BC1TL, + MIPS_INS_BC1TL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc2eqz */ + Mips_BC2EQZ, + MIPS_INS_BC2EQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc2eqzc */ + Mips_BC2EQZC_MMR6, + MIPS_INS_BC2EQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bc2nez */ + Mips_BC2NEZ, + MIPS_INS_BC2NEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc2nezc */ + Mips_BC2NEZC_MMR6, + MIPS_INS_BC2NEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bclr.b */ + Mips_BCLR_B, + MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclr.d */ + Mips_BCLR_D, + MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclr.h */ + Mips_BCLR_H, + MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclr.w */ + Mips_BCLR_W, + MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclri.b */ + Mips_BCLRI_B, + MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclri.d */ + Mips_BCLRI_D, + MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclri.h */ + Mips_BCLRI_H, + MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclri.w */ + Mips_BCLRI_W, + MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* beq */ + Mips_BEQ, + MIPS_INS_BEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beq */ + Mips_BEQ_MM, + MIPS_INS_BEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beq */ + Mips_BeqImm, + MIPS_INS_BEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* beqc */ + Mips_BEQC, + MIPS_INS_BEQC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beqc */ + Mips_BEQC_MMR6, + MIPS_INS_BEQC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqc */ + Mips_BEQC64, + MIPS_INS_BEQC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* beql */ + Mips_BEQL, + MIPS_INS_BEQL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beql */ + Mips_BEQLImmMacro, + MIPS_INS_BEQL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* beqz */ + Mips_BeqzRxImmX16, + MIPS_INS_BEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* beqz */ + Mips_BEQ, + MIPS_INS_BEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beqz */ + Mips_BEQ_MM, + MIPS_INS_BEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beqz */ + Mips_BeqzRxImm16, + MIPS_INS_BEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* beqz16 */ + Mips_BEQZ16_MM, + MIPS_INS_BEQZ16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqz16 */ + Mips_BEQZC16_MMR6, + MIPS_INS_BEQZ16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqzalc */ + Mips_BEQZALC, + MIPS_INS_BEQZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beqzalc */ + Mips_BEQZALC_MMR6, + MIPS_INS_BEQZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqzc */ + Mips_BEQZC, + MIPS_INS_BEQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beqzc */ + Mips_BEQZC_MM, + MIPS_INS_BEQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqzc */ + Mips_BEQZC_MMR6, + MIPS_INS_BEQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqzc */ + Mips_BEQZC64, + MIPS_INS_BEQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* beqzc16 */ + Mips_BEQZC16_MMR6, + MIPS_INS_BEQZC16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqzl */ + Mips_BEQL, + MIPS_INS_BEQZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bge */ + Mips_BGE, + MIPS_INS_BGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bge */ + Mips_BGEImmMacro, + MIPS_INS_BGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgec */ + Mips_BGEC, + MIPS_INS_BGEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgec */ + Mips_BGEC_MMR6, + MIPS_INS_BGEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgec */ + Mips_BGEC64, + MIPS_INS_BGEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bgel */ + Mips_BGEL, + MIPS_INS_BGEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgel */ + Mips_BGELImmMacro, + MIPS_INS_BGEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgeu */ + Mips_BGEU, + MIPS_INS_BGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgeu */ + Mips_BGEUImmMacro, + MIPS_INS_BGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgeuc */ + Mips_BGEUC, + MIPS_INS_BGEUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgeuc */ + Mips_BGEUC_MMR6, + MIPS_INS_BGEUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgeuc */ + Mips_BGEUC64, + MIPS_INS_BGEUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bgeul */ + Mips_BGEUL, + MIPS_INS_BGEUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgeul */ + Mips_BGEULImmMacro, + MIPS_INS_BGEUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgez */ + Mips_BGEZ, + MIPS_INS_BGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgez */ + Mips_BGEZ_MM, + MIPS_INS_BGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgezal */ + Mips_BGEZAL, + MIPS_INS_BGEZAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* bgezal */ + Mips_BGEZAL_MM, + MIPS_INS_BGEZAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bgezalc */ + Mips_BGEZALC, + MIPS_INS_BGEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgezalc */ + Mips_BGEZALC_MMR6, + MIPS_INS_BGEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgezall */ + Mips_BGEZALL, + MIPS_INS_BGEZALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* bgezals */ + Mips_BGEZALS_MM, + MIPS_INS_BGEZALS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bgezc */ + Mips_BGEZC, + MIPS_INS_BGEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgezc */ + Mips_BGEZC_MMR6, + MIPS_INS_BGEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgezc */ + Mips_BGEZC64, + MIPS_INS_BGEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bgezl */ + Mips_BGEZL, + MIPS_INS_BGEZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgt */ + Mips_BGT, + MIPS_INS_BGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgt */ + Mips_BGTImmMacro, + MIPS_INS_BGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgtl */ + Mips_BGTL, + MIPS_INS_BGTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgtl */ + Mips_BGTLImmMacro, + MIPS_INS_BGTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgtu */ + Mips_BGTU, + MIPS_INS_BGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgtu */ + Mips_BGTUImmMacro, + MIPS_INS_BGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgtul */ + Mips_BGTUL, + MIPS_INS_BGTUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgtul */ + Mips_BGTULImmMacro, + MIPS_INS_BGTUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgtz */ + Mips_BGTZ, + MIPS_INS_BGTZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgtz */ + Mips_BGTZ_MM, + MIPS_INS_BGTZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgtzalc */ + Mips_BGTZALC, + MIPS_INS_BGTZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgtzalc */ + Mips_BGTZALC_MMR6, + MIPS_INS_BGTZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgtzc */ + Mips_BGTZC, + MIPS_INS_BGTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgtzc */ + Mips_BGTZC_MMR6, + MIPS_INS_BGTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgtzc */ + Mips_BGTZC64, + MIPS_INS_BGTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bgtzl */ + Mips_BGTZL, + MIPS_INS_BGTZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* binsl.b */ + Mips_BINSL_B, + MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsl.d */ + Mips_BINSL_D, + MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsl.h */ + Mips_BINSL_H, + MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsl.w */ + Mips_BINSL_W, + MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsli.b */ + Mips_BINSLI_B, + MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsli.d */ + Mips_BINSLI_D, + MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsli.h */ + Mips_BINSLI_H, + MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsli.w */ + Mips_BINSLI_W, + MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsr.b */ + Mips_BINSR_B, + MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsr.d */ + Mips_BINSR_D, + MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsr.h */ + Mips_BINSR_H, + MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsr.w */ + Mips_BINSR_W, + MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsri.b */ + Mips_BINSRI_B, + MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsri.d */ + Mips_BINSRI_D, + MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsri.h */ + Mips_BINSRI_H, + MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsri.w */ + Mips_BINSRI_W, + MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bitrev */ + Mips_BITREV_MM, + MIPS_INS_BITREV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* bitrev */ + Mips_BITREV, + MIPS_INS_BITREV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* bitswap */ + Mips_BITSWAP, + MIPS_INS_BITSWAP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bitswap */ + Mips_BITSWAP_MMR6, + MIPS_INS_BITSWAP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ble */ + Mips_BLE, + MIPS_INS_BLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ble */ + Mips_BLEImmMacro, + MIPS_INS_BLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* blel */ + Mips_BLEL, + MIPS_INS_BLEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* blel */ + Mips_BLELImmMacro, + MIPS_INS_BLEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bleu */ + Mips_BLEU, + MIPS_INS_BLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bleu */ + Mips_BLEUImmMacro, + MIPS_INS_BLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bleul */ + Mips_BLEUL, + MIPS_INS_BLEUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bleul */ + Mips_BLEULImmMacro, + MIPS_INS_BLEUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* blez */ + Mips_BLEZ, + MIPS_INS_BLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* blez */ + Mips_BLEZ_MM, + MIPS_INS_BLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* blezalc */ + Mips_BLEZALC, + MIPS_INS_BLEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* blezalc */ + Mips_BLEZALC_MMR6, + MIPS_INS_BLEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* blezc */ + Mips_BLEZC, + MIPS_INS_BLEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* blezc */ + Mips_BLEZC_MMR6, + MIPS_INS_BLEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* blezc */ + Mips_BLEZC64, + MIPS_INS_BLEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* blezl */ + Mips_BLEZL, + MIPS_INS_BLEZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* blt */ + Mips_BLT, + MIPS_INS_BLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* blt */ + Mips_BLTImmMacro, + MIPS_INS_BLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bltc */ + Mips_BLTC, + MIPS_INS_BLTC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bltc */ + Mips_BLTC_MMR6, + MIPS_INS_BLTC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bltc */ + Mips_BLTC64, + MIPS_INS_BLTC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bltl */ + Mips_BLTL, + MIPS_INS_BLTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bltl */ + Mips_BLTLImmMacro, + MIPS_INS_BLTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bltu */ + Mips_BLTU, + MIPS_INS_BLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bltu */ + Mips_BLTUImmMacro, + MIPS_INS_BLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bltuc */ + Mips_BLTUC, + MIPS_INS_BLTUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bltuc */ + Mips_BLTUC_MMR6, + MIPS_INS_BLTUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bltuc */ + Mips_BLTUC64, + MIPS_INS_BLTUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bltul */ + Mips_BLTUL, + MIPS_INS_BLTUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bltul */ + Mips_BLTULImmMacro, + MIPS_INS_BLTUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bltz */ + Mips_BLTZ, + MIPS_INS_BLTZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bltz */ + Mips_BLTZ_MM, + MIPS_INS_BLTZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bltzal */ + Mips_BLTZAL, + MIPS_INS_BLTZAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* bltzal */ + Mips_BLTZAL_MM, + MIPS_INS_BLTZAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bltzalc */ + Mips_BLTZALC, + MIPS_INS_BLTZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bltzalc */ + Mips_BLTZALC_MMR6, + MIPS_INS_BLTZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bltzall */ + Mips_BLTZALL, + MIPS_INS_BLTZALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* bltzals */ + Mips_BLTZALS_MM, + MIPS_INS_BLTZALS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bltzc */ + Mips_BLTZC, + MIPS_INS_BLTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bltzc */ + Mips_BLTZC_MMR6, + MIPS_INS_BLTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bltzc */ + Mips_BLTZC64, + MIPS_INS_BLTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bltzl */ + Mips_BLTZL, + MIPS_INS_BLTZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bmnz.v */ + Mips_BMNZ_V, + MIPS_INS_BMNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bmnzi.b */ + Mips_BMNZI_B, + MIPS_INS_BMNZI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bmz.v */ + Mips_BMZ_V, + MIPS_INS_BMZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bmzi.b */ + Mips_BMZI_B, + MIPS_INS_BMZI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bne */ + Mips_BNE, + MIPS_INS_BNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bne */ + Mips_BNE_MM, + MIPS_INS_BNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bne */ + Mips_BneImm, + MIPS_INS_BNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bnec */ + Mips_BNEC, + MIPS_INS_BNEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnec */ + Mips_BNEC_MMR6, + MIPS_INS_BNEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnec */ + Mips_BNEC64, + MIPS_INS_BNEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bneg.b */ + Mips_BNEG_B, + MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bneg.d */ + Mips_BNEG_D, + MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bneg.h */ + Mips_BNEG_H, + MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bneg.w */ + Mips_BNEG_W, + MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bnegi.b */ + Mips_BNEGI_B, + MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bnegi.d */ + Mips_BNEGI_D, + MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bnegi.h */ + Mips_BNEGI_H, + MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bnegi.w */ + Mips_BNEGI_W, + MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bnel */ + Mips_BNEL, + MIPS_INS_BNEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnel */ + Mips_BNELImmMacro, + MIPS_INS_BNEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bnez */ + Mips_BnezRxImmX16, + MIPS_INS_BNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* bnez */ + Mips_BNE, + MIPS_INS_BNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnez */ + Mips_BNE_MM, + MIPS_INS_BNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnez */ + Mips_BnezRxImm16, + MIPS_INS_BNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* bnez16 */ + Mips_BNEZ16_MM, + MIPS_INS_BNEZ16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnez16 */ + Mips_BNEZC16_MMR6, + MIPS_INS_BNEZ16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnezalc */ + Mips_BNEZALC, + MIPS_INS_BNEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnezalc */ + Mips_BNEZALC_MMR6, + MIPS_INS_BNEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnezc */ + Mips_BNEZC, + MIPS_INS_BNEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnezc */ + Mips_BNEZC_MM, + MIPS_INS_BNEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnezc */ + Mips_BNEZC_MMR6, + MIPS_INS_BNEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnezc */ + Mips_BNEZC64, + MIPS_INS_BNEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bnezc16 */ + Mips_BNEZC16_MMR6, + MIPS_INS_BNEZC16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnezl */ + Mips_BNEL, + MIPS_INS_BNEZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnvc */ + Mips_BNVC, + MIPS_INS_BNVC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnvc */ + Mips_BNVC_MMR6, + MIPS_INS_BNVC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnz.b */ + Mips_BNZ_B, + MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bnz.d */ + Mips_BNZ_D, + MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bnz.h */ + Mips_BNZ_H, + MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bnz.v */ + Mips_BNZ_V, + MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bnz.w */ + Mips_BNZ_W, + MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bovc */ + Mips_BOVC, + MIPS_INS_BOVC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bovc */ + Mips_BOVC_MMR6, + MIPS_INS_BOVC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bposge32 */ + Mips_BPOSGE32_MM, + MIPS_INS_BPOSGE32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_DSP, 0}, + 1, + 0 +#endif + }, + {/* bposge32 */ + Mips_BPOSGE32, + MIPS_INS_BPOSGE32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bposge32c */ + Mips_BPOSGE32C_MMR3, + MIPS_INS_BPOSGE32C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR3, 0}, + 1, + 0 +#endif + }, + {/* break */ + Mips_BREAK, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK_MM, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_Break16, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK_MM, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK_MMR6, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK_MM, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break16 */ + Mips_BREAK16_MM, + MIPS_INS_BREAK16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* break16 */ + Mips_BREAK16_MMR6, + MIPS_INS_BREAK16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bsel.v */ + Mips_BSEL_V, + MIPS_INS_BSEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bseli.b */ + Mips_BSELI_B, + MIPS_INS_BSELI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bset.b */ + Mips_BSET_B, + MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bset.d */ + Mips_BSET_D, + MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bset.h */ + Mips_BSET_H, + MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bset.w */ + Mips_BSET_W, + MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bseti.b */ + Mips_BSETI_B, + MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bseti.d */ + Mips_BSETI_D, + MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bseti.h */ + Mips_BSETI_H, + MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bseti.w */ + Mips_BSETI_W, + MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bteqz */ + Mips_BteqzX16, + MIPS_INS_BTEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* bteqz */ + Mips_Bteqz16, + MIPS_INS_BTEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* btnez */ + Mips_BtnezX16, + MIPS_INS_BTNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* btnez */ + Mips_Btnez16, + MIPS_INS_BTNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* bz.b */ + Mips_BZ_B, + MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bz.d */ + Mips_BZ_D, + MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bz.h */ + Mips_BZ_H, + MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bz.v */ + Mips_BZ_V, + MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bz.w */ + Mips_BZ_W, + MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.eq.s */ + Mips_C_EQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.s */ + Mips_C_EQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.eq.s */ + Mips_C_EQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.s */ + Mips_C_EQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.s */ + Mips_C_F_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.s */ + Mips_C_F_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.s */ + Mips_C_F_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.s */ + Mips_C_F_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.s */ + Mips_C_LE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.s */ + Mips_C_LE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.s */ + Mips_C_LE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.s */ + Mips_C_LE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.s */ + Mips_C_LT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.s */ + Mips_C_LT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.s */ + Mips_C_LT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.s */ + Mips_C_LT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.s */ + Mips_C_NGE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.s */ + Mips_C_NGE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.s */ + Mips_C_NGE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.s */ + Mips_C_NGE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.s */ + Mips_C_NGL_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.s */ + Mips_C_NGL_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.s */ + Mips_C_NGL_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.s */ + Mips_C_NGL_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.s */ + Mips_C_NGLE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.s */ + Mips_C_NGLE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.s */ + Mips_C_NGLE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.s */ + Mips_C_NGLE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.s */ + Mips_C_NGT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.s */ + Mips_C_NGT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.s */ + Mips_C_NGT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.s */ + Mips_C_NGT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.s */ + Mips_C_OLE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.s */ + Mips_C_OLE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.s */ + Mips_C_OLE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.s */ + Mips_C_OLE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.s */ + Mips_C_OLT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.s */ + Mips_C_OLT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.s */ + Mips_C_OLT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.s */ + Mips_C_OLT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.s */ + Mips_C_SEQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.s */ + Mips_C_SEQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.s */ + Mips_C_SEQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.s */ + Mips_C_SEQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.s */ + Mips_C_SF_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.s */ + Mips_C_SF_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.s */ + Mips_C_SF_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.s */ + Mips_C_SF_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.s */ + Mips_C_UEQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.s */ + Mips_C_UEQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.s */ + Mips_C_UEQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.s */ + Mips_C_UEQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.s */ + Mips_C_ULE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.s */ + Mips_C_ULE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.s */ + Mips_C_ULE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.s */ + Mips_C_ULE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.s */ + Mips_C_ULT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.s */ + Mips_C_ULT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.s */ + Mips_C_ULT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.s */ + Mips_C_ULT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.s */ + Mips_C_UN_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.s */ + Mips_C_UN_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.s */ + Mips_C_UN_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.s */ + Mips_C_UN_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cache */ + Mips_CACHE_R6, + MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cache */ + Mips_CACHE, + MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cache */ + Mips_CACHE_MM, + MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* cache */ + Mips_CACHE_MMR6, + MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* cachee */ + Mips_CACHEE, + MIPS_INS_CACHEE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* cachee */ + Mips_CACHEE_MM, + MIPS_INS_CACHEE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* ceil.l.d */ + Mips_CEIL_L_D64, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ceil.l.d */ + Mips_CEIL_L_D_MMR6, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceil.l.s */ + Mips_CEIL_L_S, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ceil.l.s */ + Mips_CEIL_L_S_MMR6, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.d */ + Mips_CEIL_W_D32, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.d */ + Mips_CEIL_W_D_MMR6, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.d */ + Mips_CEIL_W_MM, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.d */ + Mips_CEIL_W_D64, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.s */ + Mips_CEIL_W_S, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.s */ + Mips_CEIL_W_S_MMR6, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.s */ + Mips_CEIL_W_S_MM, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceq.b */ + Mips_CEQ_B, + MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceq.d */ + Mips_CEQ_D, + MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceq.h */ + Mips_CEQ_H, + MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceq.w */ + Mips_CEQ_W, + MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceqi.b */ + Mips_CEQI_B, + MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceqi.d */ + Mips_CEQI_D, + MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceqi.h */ + Mips_CEQI_H, + MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceqi.w */ + Mips_CEQI_W, + MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cfc1 */ + Mips_CFC1, + MIPS_INS_CFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cfc1 */ + Mips_CFC1_MM, + MIPS_INS_CFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cfc2 */ + Mips_CFC2_MM, + MIPS_INS_CFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cfcmsa */ + Mips_CFCMSA, + MIPS_INS_CFCMSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cftc1 */ + Mips_CFTC1, + MIPS_INS_CFTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* cins */ + Mips_CINS, + MIPS_INS_CINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cins */ + Mips_CINS32, + MIPS_INS_CINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* cins */ + Mips_CINS, + MIPS_INS_CINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cins */ + Mips_CINS32, + MIPS_INS_CINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* cins32 */ + Mips_CINS32, + MIPS_INS_CINS32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cins32 */ + Mips_CINS32, + MIPS_INS_CINS32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* class.d */ + Mips_CLASS_D, + MIPS_INS_CLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* class.d */ + Mips_CLASS_D_MMR6, + MIPS_INS_CLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* class.s */ + Mips_CLASS_S, + MIPS_INS_CLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* class.s */ + Mips_CLASS_S_MMR6, + MIPS_INS_CLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* cle_s.b */ + Mips_CLE_S_B, + MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_s.d */ + Mips_CLE_S_D, + MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_s.h */ + Mips_CLE_S_H, + MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_s.w */ + Mips_CLE_S_W, + MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_u.b */ + Mips_CLE_U_B, + MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_u.d */ + Mips_CLE_U_D, + MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_u.h */ + Mips_CLE_U_H, + MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_u.w */ + Mips_CLE_U_W, + MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_s.b */ + Mips_CLEI_S_B, + MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_s.d */ + Mips_CLEI_S_D, + MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_s.h */ + Mips_CLEI_S_H, + MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_s.w */ + Mips_CLEI_S_W, + MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_u.b */ + Mips_CLEI_U_B, + MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_u.d */ + Mips_CLEI_U_D, + MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_u.h */ + Mips_CLEI_U_H, + MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_u.w */ + Mips_CLEI_U_W, + MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clo */ + Mips_CLO, + MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* clo */ + Mips_CLO_MMR6, + MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* clo */ + Mips_CLO_R6, + MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* clo */ + Mips_CLO_MM, + MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* clt_s.b */ + Mips_CLT_S_B, + MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_s.d */ + Mips_CLT_S_D, + MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_s.h */ + Mips_CLT_S_H, + MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_s.w */ + Mips_CLT_S_W, + MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_u.b */ + Mips_CLT_U_B, + MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_u.d */ + Mips_CLT_U_D, + MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_u.h */ + Mips_CLT_U_H, + MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_u.w */ + Mips_CLT_U_W, + MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_s.b */ + Mips_CLTI_S_B, + MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_s.d */ + Mips_CLTI_S_D, + MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_s.h */ + Mips_CLTI_S_H, + MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_s.w */ + Mips_CLTI_S_W, + MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_u.b */ + Mips_CLTI_U_B, + MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_u.d */ + Mips_CLTI_U_D, + MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_u.h */ + Mips_CLTI_U_H, + MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_u.w */ + Mips_CLTI_U_W, + MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clz */ + Mips_CLZ, + MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* clz */ + Mips_CLZ_MMR6, + MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* clz */ + Mips_CLZ_R6, + MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* clz */ + Mips_CLZ_MM, + MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp */ + Mips_CmpRxRy16, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* cmp.af.d */ + Mips_CMP_F_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.af.d */ + Mips_CMP_AF_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.af.s */ + Mips_CMP_F_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.af.s */ + Mips_CMP_AF_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.d */ + Mips_CMP_EQ_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.d */ + Mips_CMP_EQ_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.ph */ + Mips_CMP_EQ_PH_MM, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.ph */ + Mips_CMP_EQ_PH, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.s */ + Mips_CMP_EQ_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.s */ + Mips_CMP_EQ_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.d */ + Mips_CMP_LE_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.d */ + Mips_CMP_LE_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.ph */ + Mips_CMP_LE_PH_MM, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.ph */ + Mips_CMP_LE_PH, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.s */ + Mips_CMP_LE_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.s */ + Mips_CMP_LE_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.d */ + Mips_CMP_LT_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.d */ + Mips_CMP_LT_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.ph */ + Mips_CMP_LT_PH_MM, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.ph */ + Mips_CMP_LT_PH, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.s */ + Mips_CMP_LT_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.s */ + Mips_CMP_LT_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.saf.d */ + Mips_CMP_SAF_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.saf.d */ + Mips_CMP_SAF_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.saf.s */ + Mips_CMP_SAF_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.saf.s */ + Mips_CMP_SAF_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.seq.d */ + Mips_CMP_SEQ_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.seq.d */ + Mips_CMP_SEQ_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.seq.s */ + Mips_CMP_SEQ_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.seq.s */ + Mips_CMP_SEQ_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sle.d */ + Mips_CMP_SLE_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sle.d */ + Mips_CMP_SLE_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sle.s */ + Mips_CMP_SLE_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sle.s */ + Mips_CMP_SLE_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.slt.d */ + Mips_CMP_SLT_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.slt.d */ + Mips_CMP_SLT_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.slt.s */ + Mips_CMP_SLT_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.slt.s */ + Mips_CMP_SLT_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sueq.d */ + Mips_CMP_SUEQ_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sueq.d */ + Mips_CMP_SUEQ_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sueq.s */ + Mips_CMP_SUEQ_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sueq.s */ + Mips_CMP_SUEQ_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sule.d */ + Mips_CMP_SULE_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sule.d */ + Mips_CMP_SULE_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sule.s */ + Mips_CMP_SULE_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sule.s */ + Mips_CMP_SULE_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sult.d */ + Mips_CMP_SULT_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sult.d */ + Mips_CMP_SULT_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sult.s */ + Mips_CMP_SULT_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sult.s */ + Mips_CMP_SULT_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sun.d */ + Mips_CMP_SUN_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sun.d */ + Mips_CMP_SUN_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sun.s */ + Mips_CMP_SUN_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sun.s */ + Mips_CMP_SUN_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ueq.d */ + Mips_CMP_UEQ_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ueq.d */ + Mips_CMP_UEQ_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ueq.s */ + Mips_CMP_UEQ_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ueq.s */ + Mips_CMP_UEQ_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ule.d */ + Mips_CMP_ULE_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ule.d */ + Mips_CMP_ULE_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ule.s */ + Mips_CMP_ULE_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ule.s */ + Mips_CMP_ULE_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ult.d */ + Mips_CMP_ULT_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ult.d */ + Mips_CMP_ULT_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ult.s */ + Mips_CMP_ULT_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ult.s */ + Mips_CMP_ULT_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.un.d */ + Mips_CMP_UN_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.un.d */ + Mips_CMP_UN_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.un.s */ + Mips_CMP_UN_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.un.s */ + Mips_CMP_UN_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.eq.qb */ + Mips_CMPGDU_EQ_QB_MMR2, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.eq.qb */ + Mips_CMPGDU_EQ_QB, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.le.qb */ + Mips_CMPGDU_LE_QB_MMR2, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.le.qb */ + Mips_CMPGDU_LE_QB, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.lt.qb */ + Mips_CMPGDU_LT_QB_MMR2, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.lt.qb */ + Mips_CMPGDU_LT_QB, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.eq.qb */ + Mips_CMPGU_EQ_QB_MM, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.eq.qb */ + Mips_CMPGU_EQ_QB, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.le.qb */ + Mips_CMPGU_LE_QB_MM, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.le.qb */ + Mips_CMPGU_LE_QB, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.lt.qb */ + Mips_CMPGU_LT_QB_MM, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.lt.qb */ + Mips_CMPGU_LT_QB, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpi */ + Mips_CmpiRxImmX16, + MIPS_INS_CMPI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* cmpi */ + Mips_CmpiRxImm16, + MIPS_INS_CMPI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* cmpu.eq.qb */ + Mips_CMPU_EQ_QB_MM, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpu.eq.qb */ + Mips_CMPU_EQ_QB, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpu.le.qb */ + Mips_CMPU_LE_QB_MM, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpu.le.qb */ + Mips_CMPU_LE_QB, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpu.lt.qb */ + Mips_CMPU_LT_QB_MM, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpu.lt.qb */ + Mips_CMPU_LT_QB, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* copy_s.b */ + Mips_COPY_S_B, + MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* copy_s.d */ + Mips_COPY_S_D, + MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* copy_s.h */ + Mips_COPY_S_H, + MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* copy_s.w */ + Mips_COPY_S_W, + MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* copy_u.b */ + Mips_COPY_U_B, + MIPS_INS_COPY_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* copy_u.h */ + Mips_COPY_U_H, + MIPS_INS_COPY_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* copy_u.w */ + Mips_COPY_U_W, + MIPS_INS_COPY_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* crc32b */ + Mips_CRC32B, + MIPS_INS_CRC32B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32cb */ + Mips_CRC32CB, + MIPS_INS_CRC32CB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32cd */ + Mips_CRC32CD, + MIPS_INS_CRC32CD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32ch */ + Mips_CRC32CH, + MIPS_INS_CRC32CH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32cw */ + Mips_CRC32CW, + MIPS_INS_CRC32CW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32d */ + Mips_CRC32D, + MIPS_INS_CRC32D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32h */ + Mips_CRC32H, + MIPS_INS_CRC32H, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32w */ + Mips_CRC32W, + MIPS_INS_CRC32W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* ctc1 */ + Mips_CTC1, + MIPS_INS_CTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ctc1 */ + Mips_CTC1_MM, + MIPS_INS_CTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ctc2 */ + Mips_CTC2_MM, + MIPS_INS_CTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ctcmsa */ + Mips_CTCMSA, + MIPS_INS_CTCMSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cttc1 */ + Mips_CTTC1, + MIPS_INS_CTTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.l */ + Mips_CVT_D64_L, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.l */ + Mips_CVT_D_L_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.s */ + Mips_CVT_D32_S, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.s */ + Mips_CVT_D32_S_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.s */ + Mips_CVT_D64_S, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.s */ + Mips_CVT_D64_S_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.w */ + Mips_CVT_D32_W, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.w */ + Mips_CVT_D32_W_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.w */ + Mips_CVT_D64_W, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.w */ + Mips_CVT_D64_W_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.d */ + Mips_CVT_L_D64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.d */ + Mips_CVT_L_D64_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.d */ + Mips_CVT_L_D_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.s */ + Mips_CVT_L_S, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.s */ + Mips_CVT_L_S_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.s */ + Mips_CVT_L_S_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.ps.pw */ + Mips_CVT_PS_PW64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MIPS3D, 0}, + 0, + 0 +#endif + }, + {/* cvt.ps.s */ + Mips_CVT_PS_S64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.pw.ps */ + Mips_CVT_PW_PS64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MIPS3D, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.d */ + Mips_CVT_S_D32, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.d */ + Mips_CVT_S_D32_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.d */ + Mips_CVT_S_D64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.d */ + Mips_CVT_S_D64_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.l */ + Mips_CVT_S_L, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.l */ + Mips_CVT_S_L_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.pl */ + Mips_CVT_S_PL64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.pu */ + Mips_CVT_S_PU64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.w */ + Mips_CVT_S_W, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.w */ + Mips_CVT_S_W_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.w */ + Mips_CVT_S_W_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.d */ + Mips_CVT_W_D32, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.d */ + Mips_CVT_W_D32_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.d */ + Mips_CVT_W_D64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.d */ + Mips_CVT_W_D64_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.s */ + Mips_CVT_W_S, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.s */ + Mips_CVT_W_S_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.s */ + Mips_CVT_W_S_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* dadd */ + Mips_DADD, + MIPS_INS_DADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dadd */ + Mips_DADDi, + MIPS_INS_DADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dadd */ + Mips_DADD, + MIPS_INS_DADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dadd */ + Mips_DADDi, + MIPS_INS_DADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddi */ + Mips_DADDi, + MIPS_INS_DADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* daddi */ + Mips_DADDi, + MIPS_INS_DADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* daddiu */ + Mips_DADDiu, + MIPS_INS_DADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddiu */ + Mips_DADDiu, + MIPS_INS_DADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddu */ + Mips_DADDu, + MIPS_INS_DADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddu */ + Mips_DADDiu, + MIPS_INS_DADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddu */ + Mips_DADDu, + MIPS_INS_DADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddu */ + Mips_DADDiu, + MIPS_INS_DADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dahi */ + Mips_DAHI, + MIPS_INS_DAHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dalign */ + Mips_DALIGN, + MIPS_INS_DALIGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dati */ + Mips_DATI, + MIPS_INS_DATI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daui */ + Mips_DAUI, + MIPS_INS_DAUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dbitswap */ + Mips_DBITSWAP, + MIPS_INS_DBITSWAP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dclo */ + Mips_DCLO, + MIPS_INS_DCLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dclo */ + Mips_DCLO_R6, + MIPS_INS_DCLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dclz */ + Mips_DCLZ, + MIPS_INS_DCLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dclz */ + Mips_DCLZ_R6, + MIPS_INS_DCLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DSDivMacro, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DSDivIMacro, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DSDIV, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DSDivMacro, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DDIV, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DSDivIMacro, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DUDivMacro, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DUDivIMacro, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DUDIV, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DUDivMacro, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DDIVU, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DUDivIMacro, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* deret */ + Mips_DERET, + MIPS_INS_DERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* deret */ + Mips_DERET_MMR6, + MIPS_INS_DERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* deret */ + Mips_DERET_MM, + MIPS_INS_DERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dext */ + Mips_DEXTM, + MIPS_INS_DEXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dext */ + Mips_DEXTU, + MIPS_INS_DEXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dext */ + Mips_DEXT, + MIPS_INS_DEXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dextm */ + Mips_DEXTM, + MIPS_INS_DEXTM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dextu */ + Mips_DEXTU, + MIPS_INS_DEXTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI_MMR6, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI_MM, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI_MMR6, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI_MM, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dins */ + Mips_DINSM, + MIPS_INS_DINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dins */ + Mips_DINSU, + MIPS_INS_DINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dins */ + Mips_DINS, + MIPS_INS_DINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dinsm */ + Mips_DINSM, + MIPS_INS_DINSM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dinsu */ + Mips_DINSU, + MIPS_INS_DINSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_DIV, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDivIMacro, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDivMacro, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDIV, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_DivRxRy16, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDIV, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDIV_MM, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_DIV, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_DIV_MMR6, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDivIMacro, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDivMacro, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* div.d */ + Mips_FDIV_D32, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div.d */ + Mips_FDIV_D32_MM, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* div.d */ + Mips_FDIV_D64, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div.d */ + Mips_FDIV_D64_MM, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* div.s */ + Mips_FDIV_S, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div.s */ + Mips_FDIV_S_MMR6, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* div.s */ + Mips_FDIV_S_MM, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* div_s.b */ + Mips_DIV_S_B, + MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_s.d */ + Mips_DIV_S_D, + MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_s.h */ + Mips_DIV_S_H, + MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_s.w */ + Mips_DIV_S_W, + MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_u.b */ + Mips_DIV_U_B, + MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_u.d */ + Mips_DIV_U_D, + MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_u.h */ + Mips_DIV_U_H, + MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_u.w */ + Mips_DIV_U_W, + MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_DIVU, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDivIMacro, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDivMacro, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDIV, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_DivuRxRy16, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDIV, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDIV_MM, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDivMacro, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_DIVU, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_DIVU_MMR6, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDivIMacro, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dla */ + Mips_LoadAddrImm64, + MIPS_INS_DLA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* dla */ + Mips_LoadAddrReg64, + MIPS_INS_DLA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* dli */ + Mips_LoadImm64, + MIPS_INS_DLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* dlsa */ + Mips_DLSA, + MIPS_INS_DLSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* dlsa */ + Mips_DLSA_R6, + MIPS_INS_DLSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmfc0 */ + Mips_DMFC0, + MIPS_INS_DMFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmfc0 */ + Mips_DMFC0, + MIPS_INS_DMFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, 0}, + 0, + 0 +#endif + }, + {/* dmfc1 */ + Mips_DMFC1, + MIPS_INS_DMFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmfc2 */ + Mips_DMFC2, + MIPS_INS_DMFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* dmfc2 */ + Mips_DMFC2_OCTEON, + MIPS_INS_DMFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmfc2 */ + Mips_DMFC2, + MIPS_INS_DMFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, 0}, + 0, + 0 +#endif + }, + {/* dmfgc0 */ + Mips_DMFGC0, + MIPS_INS_DMFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmfgc0 */ + Mips_DMFGC0, + MIPS_INS_DMFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* dmod */ + Mips_DMOD, + MIPS_INS_DMOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmodu */ + Mips_DMODU, + MIPS_INS_DMODU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmt */ + Mips_DMT, + MIPS_INS_DMT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmt */ + Mips_DMT, + MIPS_INS_DMT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmtc0 */ + Mips_DMTC0, + MIPS_INS_DMTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmtc0 */ + Mips_DMTC0, + MIPS_INS_DMTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, 0}, + 0, + 0 +#endif + }, + {/* dmtc1 */ + Mips_DMTC1, + MIPS_INS_DMTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmtc2 */ + Mips_DMTC2, + MIPS_INS_DMTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* dmtc2 */ + Mips_DMTC2_OCTEON, + MIPS_INS_DMTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmtc2 */ + Mips_DMTC2, + MIPS_INS_DMTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, 0}, + 0, + 0 +#endif + }, + {/* dmtgc0 */ + Mips_DMTGC0, + MIPS_INS_DMTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmtgc0 */ + Mips_DMTGC0, + MIPS_INS_DMTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* dmuh */ + Mips_DMUH, + MIPS_INS_DMUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmuhu */ + Mips_DMUHU, + MIPS_INS_DMUHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmul */ + Mips_DMUL, + MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmul */ + Mips_DMULMacro, + MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmul */ + Mips_DMUL_R6, + MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmul */ + Mips_DMUL, + MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmul */ + Mips_DMULImmMacro, + MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dmulo */ + Mips_DMULOMacro, + MIPS_INS_DMULO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dmulou */ + Mips_DMULOUMacro, + MIPS_INS_DMULOU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dmult */ + Mips_DMULT, + MIPS_INS_DMULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmultu */ + Mips_DMULTu, + MIPS_INS_DMULTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmulu */ + Mips_DMULU, + MIPS_INS_DMULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dneg */ + Mips_DSUB, + MIPS_INS_DNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dneg */ + Mips_DSUB, + MIPS_INS_DNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dnegu */ + Mips_DSUBu, + MIPS_INS_DNEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dnegu */ + Mips_DSUBu, + MIPS_INS_DNEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dotp_s.d */ + Mips_DOTP_S_D, + MIPS_INS_DOTP_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dotp_s.h */ + Mips_DOTP_S_H, + MIPS_INS_DOTP_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dotp_s.w */ + Mips_DOTP_S_W, + MIPS_INS_DOTP_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dotp_u.d */ + Mips_DOTP_U_D, + MIPS_INS_DOTP_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dotp_u.h */ + Mips_DOTP_U_H, + MIPS_INS_DOTP_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dotp_u.w */ + Mips_DOTP_U_W, + MIPS_INS_DOTP_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpa.w.ph */ + Mips_DPA_W_PH_MMR2, + MIPS_INS_DPA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpa.w.ph */ + Mips_DPA_W_PH, + MIPS_INS_DPA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpadd_s.d */ + Mips_DPADD_S_D, + MIPS_INS_DPADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpadd_s.h */ + Mips_DPADD_S_H, + MIPS_INS_DPADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpadd_s.w */ + Mips_DPADD_S_W, + MIPS_INS_DPADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpadd_u.d */ + Mips_DPADD_U_D, + MIPS_INS_DPADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpadd_u.h */ + Mips_DPADD_U_H, + MIPS_INS_DPADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpadd_u.w */ + Mips_DPADD_U_W, + MIPS_INS_DPADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpaq_s.w.ph */ + Mips_DPAQ_S_W_PH_MM, + MIPS_INS_DPAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpaq_s.w.ph */ + Mips_DPAQ_S_W_PH, + MIPS_INS_DPAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpaq_sa.l.w */ + Mips_DPAQ_SA_L_W_MM, + MIPS_INS_DPAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpaq_sa.l.w */ + Mips_DPAQ_SA_L_W, + MIPS_INS_DPAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpaqx_s.w.ph */ + Mips_DPAQX_S_W_PH_MMR2, + MIPS_INS_DPAQX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpaqx_s.w.ph */ + Mips_DPAQX_S_W_PH, + MIPS_INS_DPAQX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpaqx_sa.w.ph */ + Mips_DPAQX_SA_W_PH_MMR2, + MIPS_INS_DPAQX_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpaqx_sa.w.ph */ + Mips_DPAQX_SA_W_PH, + MIPS_INS_DPAQX_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpau.h.qbl */ + Mips_DPAU_H_QBL_MM, + MIPS_INS_DPAU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpau.h.qbl */ + Mips_DPAU_H_QBL, + MIPS_INS_DPAU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpau.h.qbr */ + Mips_DPAU_H_QBR_MM, + MIPS_INS_DPAU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpau.h.qbr */ + Mips_DPAU_H_QBR, + MIPS_INS_DPAU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpax.w.ph */ + Mips_DPAX_W_PH_MMR2, + MIPS_INS_DPAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpax.w.ph */ + Mips_DPAX_W_PH, + MIPS_INS_DPAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpop */ + Mips_DPOP, + MIPS_INS_DPOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dpop */ + Mips_DPOP, + MIPS_INS_DPOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dps.w.ph */ + Mips_DPS_W_PH_MMR2, + MIPS_INS_DPS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dps.w.ph */ + Mips_DPS_W_PH, + MIPS_INS_DPS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsq_s.w.ph */ + Mips_DPSQ_S_W_PH_MM, + MIPS_INS_DPSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsq_s.w.ph */ + Mips_DPSQ_S_W_PH, + MIPS_INS_DPSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsq_sa.l.w */ + Mips_DPSQ_SA_L_W_MM, + MIPS_INS_DPSQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsq_sa.l.w */ + Mips_DPSQ_SA_L_W, + MIPS_INS_DPSQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsqx_s.w.ph */ + Mips_DPSQX_S_W_PH_MMR2, + MIPS_INS_DPSQX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsqx_s.w.ph */ + Mips_DPSQX_S_W_PH, + MIPS_INS_DPSQX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsqx_sa.w.ph */ + Mips_DPSQX_SA_W_PH_MMR2, + MIPS_INS_DPSQX_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsqx_sa.w.ph */ + Mips_DPSQX_SA_W_PH, + MIPS_INS_DPSQX_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsu.h.qbl */ + Mips_DPSU_H_QBL_MM, + MIPS_INS_DPSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsu.h.qbl */ + Mips_DPSU_H_QBL, + MIPS_INS_DPSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsu.h.qbr */ + Mips_DPSU_H_QBR_MM, + MIPS_INS_DPSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsu.h.qbr */ + Mips_DPSU_H_QBR, + MIPS_INS_DPSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsub_s.d */ + Mips_DPSUB_S_D, + MIPS_INS_DPSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsub_s.h */ + Mips_DPSUB_S_H, + MIPS_INS_DPSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsub_s.w */ + Mips_DPSUB_S_W, + MIPS_INS_DPSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsub_u.d */ + Mips_DPSUB_U_D, + MIPS_INS_DPSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsub_u.h */ + Mips_DPSUB_U_H, + MIPS_INS_DPSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsub_u.w */ + Mips_DPSUB_U_W, + MIPS_INS_DPSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsx.w.ph */ + Mips_DPSX_W_PH_MMR2, + MIPS_INS_DPSX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsx.w.ph */ + Mips_DPSX_W_PH, + MIPS_INS_DPSX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* drem */ + Mips_DSRemMacro, + MIPS_INS_DREM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drem */ + Mips_DSRemIMacro, + MIPS_INS_DREM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drem */ + Mips_DSRemMacro, + MIPS_INS_DREM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drem */ + Mips_DSRemIMacro, + MIPS_INS_DREM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dremu */ + Mips_DURemMacro, + MIPS_INS_DREMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dremu */ + Mips_DURemIMacro, + MIPS_INS_DREMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dremu */ + Mips_DURemMacro, + MIPS_INS_DREMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dremu */ + Mips_DURemIMacro, + MIPS_INS_DREMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drol */ + Mips_DROL, + MIPS_INS_DROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* drol */ + Mips_DROLImm, + MIPS_INS_DROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* drol */ + Mips_DROL, + MIPS_INS_DROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* drol */ + Mips_DROLImm, + MIPS_INS_DROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* dror */ + Mips_DROR, + MIPS_INS_DROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* dror */ + Mips_DRORImm, + MIPS_INS_DROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* dror */ + Mips_DROR, + MIPS_INS_DROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* dror */ + Mips_DRORImm, + MIPS_INS_DROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* drotr */ + Mips_DROTR, + MIPS_INS_DROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drotr */ + Mips_DROTR, + MIPS_INS_DROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drotr32 */ + Mips_DROTR32, + MIPS_INS_DROTR32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drotr32 */ + Mips_DROTR32, + MIPS_INS_DROTR32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drotrv */ + Mips_DROTRV, + MIPS_INS_DROTRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsbh */ + Mips_DSBH, + MIPS_INS_DSBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dshd */ + Mips_DSHD, + MIPS_INS_DSHD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll */ + Mips_DSLLV, + MIPS_INS_DSLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll */ + Mips_DSLL, + MIPS_INS_DSLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll */ + Mips_DSLLV, + MIPS_INS_DSLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll */ + Mips_DSLL, + MIPS_INS_DSLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll32 */ + Mips_DSLL32, + MIPS_INS_DSLL32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll32 */ + Mips_DSLL32, + MIPS_INS_DSLL32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsllv */ + Mips_DSLLV, + MIPS_INS_DSLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsra */ + Mips_DSRA, + MIPS_INS_DSRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsra */ + Mips_DSRAV, + MIPS_INS_DSRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0}, + 0, + 0 +#endif + }, + {/* dsra */ + Mips_DSRA, + MIPS_INS_DSRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsra32 */ + Mips_DSRA32, + MIPS_INS_DSRA32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsra32 */ + Mips_DSRA32, + MIPS_INS_DSRA32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrav */ + Mips_DSRAV, + MIPS_INS_DSRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl */ + Mips_DSRLV, + MIPS_INS_DSRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl */ + Mips_DSRL, + MIPS_INS_DSRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl */ + Mips_DSRLV, + MIPS_INS_DSRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl */ + Mips_DSRL, + MIPS_INS_DSRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl32 */ + Mips_DSRL32, + MIPS_INS_DSRL32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl32 */ + Mips_DSRL32, + MIPS_INS_DSRL32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrlv */ + Mips_DSRLV, + MIPS_INS_DSRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsub */ + Mips_DSUB, + MIPS_INS_DSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsub */ + Mips_DADDi, + MIPS_INS_DSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dsub */ + Mips_DSUB, + MIPS_INS_DSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsub */ + Mips_DADDi, + MIPS_INS_DSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dsubi */ + Mips_DADDi, + MIPS_INS_DSUBI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dsubi */ + Mips_DADDi, + MIPS_INS_DSUBI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dsubu */ + Mips_DSUBu, + MIPS_INS_DSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsubu */ + Mips_DADDiu, + MIPS_INS_DSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsubu */ + Mips_DSUBu, + MIPS_INS_DSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsubu */ + Mips_DADDiu, + MIPS_INS_DSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dvp */ + Mips_DVP, + MIPS_INS_DVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* dvp */ + Mips_DVP_MMR6, + MIPS_INS_DVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* dvp */ + Mips_DVP, + MIPS_INS_DVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* dvp */ + Mips_DVP_MMR6, + MIPS_INS_DVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* dvpe */ + Mips_DVPE, + MIPS_INS_DVPE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dvpe */ + Mips_DVPE, + MIPS_INS_DVPE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ehb */ + Mips_EHB, + MIPS_INS_EHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ehb */ + Mips_EHB_MMR6, + MIPS_INS_EHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ehb */ + Mips_EHB_MM, + MIPS_INS_EHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI_MMR6, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI_MM, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI_MMR6, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI_MM, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* emt */ + Mips_EMT, + MIPS_INS_EMT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* emt */ + Mips_EMT, + MIPS_INS_EMT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* eret */ + Mips_ERET, + MIPS_INS_ERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* eret */ + Mips_ERET_MMR6, + MIPS_INS_ERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* eret */ + Mips_ERET_MM, + MIPS_INS_ERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* eretnc */ + Mips_ERETNC, + MIPS_INS_ERETNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* eretnc */ + Mips_ERETNC_MMR6, + MIPS_INS_ERETNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* evp */ + Mips_EVP, + MIPS_INS_EVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* evp */ + Mips_EVP_MMR6, + MIPS_INS_EVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* evp */ + Mips_EVP, + MIPS_INS_EVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* evp */ + Mips_EVP_MMR6, + MIPS_INS_EVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* evpe */ + Mips_EVPE, + MIPS_INS_EVPE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* evpe */ + Mips_EVPE, + MIPS_INS_EVPE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ext */ + Mips_EXT, + MIPS_INS_EXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ext */ + Mips_EXT_MM, + MIPS_INS_EXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ext */ + Mips_EXT_MMR6, + MIPS_INS_EXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* extp */ + Mips_EXTP_MM, + MIPS_INS_EXTP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extp */ + Mips_EXTP, + MIPS_INS_EXTP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpdp */ + Mips_EXTPDP_MM, + MIPS_INS_EXTPDP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpdp */ + Mips_EXTPDP, + MIPS_INS_EXTPDP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpdpv */ + Mips_EXTPDPV_MM, + MIPS_INS_EXTPDPV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpdpv */ + Mips_EXTPDPV, + MIPS_INS_EXTPDPV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpv */ + Mips_EXTPV_MM, + MIPS_INS_EXTPV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpv */ + Mips_EXTPV, + MIPS_INS_EXTPV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr.w */ + Mips_EXTR_W_MM, + MIPS_INS_EXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr.w */ + Mips_EXTR_W, + MIPS_INS_EXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_r.w */ + Mips_EXTR_R_W_MM, + MIPS_INS_EXTR_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_r.w */ + Mips_EXTR_R_W, + MIPS_INS_EXTR_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_rs.w */ + Mips_EXTR_RS_W_MM, + MIPS_INS_EXTR_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_rs.w */ + Mips_EXTR_RS_W, + MIPS_INS_EXTR_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_s.h */ + Mips_EXTR_S_H_MM, + MIPS_INS_EXTR_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_s.h */ + Mips_EXTR_S_H, + MIPS_INS_EXTR_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv.w */ + Mips_EXTRV_W_MM, + MIPS_INS_EXTRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv.w */ + Mips_EXTRV_W, + MIPS_INS_EXTRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_r.w */ + Mips_EXTRV_R_W_MM, + MIPS_INS_EXTRV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_r.w */ + Mips_EXTRV_R_W, + MIPS_INS_EXTRV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_rs.w */ + Mips_EXTRV_RS_W_MM, + MIPS_INS_EXTRV_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_rs.w */ + Mips_EXTRV_RS_W, + MIPS_INS_EXTRV_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_s.h */ + Mips_EXTRV_S_H_MM, + MIPS_INS_EXTRV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_s.h */ + Mips_EXTRV_S_H, + MIPS_INS_EXTRV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* exts */ + Mips_EXTS, + MIPS_INS_EXTS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* exts */ + Mips_EXTS32, + MIPS_INS_EXTS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* exts */ + Mips_EXTS, + MIPS_INS_EXTS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* exts */ + Mips_EXTS32, + MIPS_INS_EXTS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* exts32 */ + Mips_EXTS32, + MIPS_INS_EXTS32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* exts32 */ + Mips_EXTS32, + MIPS_INS_EXTS32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* fadd.d */ + Mips_FADD_D, + MIPS_INS_FADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fadd.w */ + Mips_FADD_W, + MIPS_INS_FADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcaf.d */ + Mips_FCAF_D, + MIPS_INS_FCAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcaf.w */ + Mips_FCAF_W, + MIPS_INS_FCAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fceq.d */ + Mips_FCEQ_D, + MIPS_INS_FCEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fceq.w */ + Mips_FCEQ_W, + MIPS_INS_FCEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fclass.d */ + Mips_FCLASS_D, + MIPS_INS_FCLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fclass.w */ + Mips_FCLASS_W, + MIPS_INS_FCLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcle.d */ + Mips_FCLE_D, + MIPS_INS_FCLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcle.w */ + Mips_FCLE_W, + MIPS_INS_FCLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fclt.d */ + Mips_FCLT_D, + MIPS_INS_FCLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fclt.w */ + Mips_FCLT_W, + MIPS_INS_FCLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcne.d */ + Mips_FCNE_D, + MIPS_INS_FCNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcne.w */ + Mips_FCNE_W, + MIPS_INS_FCNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcor.d */ + Mips_FCOR_D, + MIPS_INS_FCOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcor.w */ + Mips_FCOR_W, + MIPS_INS_FCOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcueq.d */ + Mips_FCUEQ_D, + MIPS_INS_FCUEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcueq.w */ + Mips_FCUEQ_W, + MIPS_INS_FCUEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcule.d */ + Mips_FCULE_D, + MIPS_INS_FCULE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcule.w */ + Mips_FCULE_W, + MIPS_INS_FCULE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcult.d */ + Mips_FCULT_D, + MIPS_INS_FCULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcult.w */ + Mips_FCULT_W, + MIPS_INS_FCULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcun.d */ + Mips_FCUN_D, + MIPS_INS_FCUN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcun.w */ + Mips_FCUN_W, + MIPS_INS_FCUN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcune.d */ + Mips_FCUNE_D, + MIPS_INS_FCUNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcune.w */ + Mips_FCUNE_W, + MIPS_INS_FCUNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fdiv.d */ + Mips_FDIV_D, + MIPS_INS_FDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fdiv.w */ + Mips_FDIV_W, + MIPS_INS_FDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexdo.h */ + Mips_FEXDO_H, + MIPS_INS_FEXDO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexdo.w */ + Mips_FEXDO_W, + MIPS_INS_FEXDO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexp2.d */ + Mips_FEXP2_D, + MIPS_INS_FEXP2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexp2.w */ + Mips_FEXP2_W, + MIPS_INS_FEXP2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexupl.d */ + Mips_FEXUPL_D, + MIPS_INS_FEXUPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexupl.w */ + Mips_FEXUPL_W, + MIPS_INS_FEXUPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexupr.d */ + Mips_FEXUPR_D, + MIPS_INS_FEXUPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexupr.w */ + Mips_FEXUPR_W, + MIPS_INS_FEXUPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffint_s.d */ + Mips_FFINT_S_D, + MIPS_INS_FFINT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffint_s.w */ + Mips_FFINT_S_W, + MIPS_INS_FFINT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffint_u.d */ + Mips_FFINT_U_D, + MIPS_INS_FFINT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffint_u.w */ + Mips_FFINT_U_W, + MIPS_INS_FFINT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffql.d */ + Mips_FFQL_D, + MIPS_INS_FFQL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffql.w */ + Mips_FFQL_W, + MIPS_INS_FFQL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffqr.d */ + Mips_FFQR_D, + MIPS_INS_FFQR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffqr.w */ + Mips_FFQR_W, + MIPS_INS_FFQR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fill.b */ + Mips_FILL_B, + MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fill.d */ + Mips_FILL_D, + MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* fill.h */ + Mips_FILL_H, + MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fill.w */ + Mips_FILL_W, + MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* flog2.d */ + Mips_FLOG2_D, + MIPS_INS_FLOG2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* flog2.w */ + Mips_FLOG2_W, + MIPS_INS_FLOG2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* floor.l.d */ + Mips_FLOOR_L_D64, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* floor.l.d */ + Mips_FLOOR_L_D_MMR6, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* floor.l.s */ + Mips_FLOOR_L_S, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* floor.l.s */ + Mips_FLOOR_L_S_MMR6, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* floor.w.d */ + Mips_FLOOR_W_D32, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* floor.w.d */ + Mips_FLOOR_W_D_MMR6, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* floor.w.d */ + Mips_FLOOR_W_MM, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* floor.w.d */ + Mips_FLOOR_W_D64, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* floor.w.s */ + Mips_FLOOR_W_S, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* floor.w.s */ + Mips_FLOOR_W_S_MMR6, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* floor.w.s */ + Mips_FLOOR_W_S_MM, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* fmadd.d */ + Mips_FMADD_D, + MIPS_INS_FMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmadd.w */ + Mips_FMADD_W, + MIPS_INS_FMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmax.d */ + Mips_FMAX_D, + MIPS_INS_FMAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmax.w */ + Mips_FMAX_W, + MIPS_INS_FMAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmax_a.d */ + Mips_FMAX_A_D, + MIPS_INS_FMAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmax_a.w */ + Mips_FMAX_A_W, + MIPS_INS_FMAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmin.d */ + Mips_FMIN_D, + MIPS_INS_FMIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmin.w */ + Mips_FMIN_W, + MIPS_INS_FMIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmin_a.d */ + Mips_FMIN_A_D, + MIPS_INS_FMIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmin_a.w */ + Mips_FMIN_A_W, + MIPS_INS_FMIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmsub.d */ + Mips_FMSUB_D, + MIPS_INS_FMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmsub.w */ + Mips_FMSUB_W, + MIPS_INS_FMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmul.d */ + Mips_FMUL_D, + MIPS_INS_FMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmul.w */ + Mips_FMUL_W, + MIPS_INS_FMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fork */ + Mips_FORK, + MIPS_INS_FORK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* frcp.d */ + Mips_FRCP_D, + MIPS_INS_FRCP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* frcp.w */ + Mips_FRCP_W, + MIPS_INS_FRCP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* frint.d */ + Mips_FRINT_D, + MIPS_INS_FRINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* frint.w */ + Mips_FRINT_W, + MIPS_INS_FRINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* frsqrt.d */ + Mips_FRSQRT_D, + MIPS_INS_FRSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* frsqrt.w */ + Mips_FRSQRT_W, + MIPS_INS_FRSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsaf.d */ + Mips_FSAF_D, + MIPS_INS_FSAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsaf.w */ + Mips_FSAF_W, + MIPS_INS_FSAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fseq.d */ + Mips_FSEQ_D, + MIPS_INS_FSEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fseq.w */ + Mips_FSEQ_W, + MIPS_INS_FSEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsle.d */ + Mips_FSLE_D, + MIPS_INS_FSLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsle.w */ + Mips_FSLE_W, + MIPS_INS_FSLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fslt.d */ + Mips_FSLT_D, + MIPS_INS_FSLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fslt.w */ + Mips_FSLT_W, + MIPS_INS_FSLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsne.d */ + Mips_FSNE_D, + MIPS_INS_FSNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsne.w */ + Mips_FSNE_W, + MIPS_INS_FSNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsor.d */ + Mips_FSOR_D, + MIPS_INS_FSOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsor.w */ + Mips_FSOR_W, + MIPS_INS_FSOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsqrt.d */ + Mips_FSQRT_D, + MIPS_INS_FSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsqrt.w */ + Mips_FSQRT_W, + MIPS_INS_FSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsub.d */ + Mips_FSUB_D, + MIPS_INS_FSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsub.w */ + Mips_FSUB_W, + MIPS_INS_FSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsueq.d */ + Mips_FSUEQ_D, + MIPS_INS_FSUEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsueq.w */ + Mips_FSUEQ_W, + MIPS_INS_FSUEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsule.d */ + Mips_FSULE_D, + MIPS_INS_FSULE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsule.w */ + Mips_FSULE_W, + MIPS_INS_FSULE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsult.d */ + Mips_FSULT_D, + MIPS_INS_FSULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsult.w */ + Mips_FSULT_W, + MIPS_INS_FSULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsun.d */ + Mips_FSUN_D, + MIPS_INS_FSUN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsun.w */ + Mips_FSUN_W, + MIPS_INS_FSUN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsune.d */ + Mips_FSUNE_D, + MIPS_INS_FSUNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsune.w */ + Mips_FSUNE_W, + MIPS_INS_FSUNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftint_s.d */ + Mips_FTINT_S_D, + MIPS_INS_FTINT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftint_s.w */ + Mips_FTINT_S_W, + MIPS_INS_FTINT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftint_u.d */ + Mips_FTINT_U_D, + MIPS_INS_FTINT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftint_u.w */ + Mips_FTINT_U_W, + MIPS_INS_FTINT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftq.h */ + Mips_FTQ_H, + MIPS_INS_FTQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftq.w */ + Mips_FTQ_W, + MIPS_INS_FTQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftrunc_s.d */ + Mips_FTRUNC_S_D, + MIPS_INS_FTRUNC_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftrunc_s.w */ + Mips_FTRUNC_S_W, + MIPS_INS_FTRUNC_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftrunc_u.d */ + Mips_FTRUNC_U_D, + MIPS_INS_FTRUNC_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftrunc_u.w */ + Mips_FTRUNC_U_W, + MIPS_INS_FTRUNC_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ginvi */ + Mips_GINVI, + MIPS_INS_GINVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_GINV, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ginvi */ + Mips_GINVI_MMR6, + MIPS_INS_GINVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_GINV, 0}, + 0, + 0 +#endif + }, + {/* ginvt */ + Mips_GINVT, + MIPS_INS_GINVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_GINV, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ginvt */ + Mips_GINVT_MMR6, + MIPS_INS_GINVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_GINV, 0}, + 0, + 0 +#endif + }, + {/* hadd_s.d */ + Mips_HADD_S_D, + MIPS_INS_HADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hadd_s.h */ + Mips_HADD_S_H, + MIPS_INS_HADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hadd_s.w */ + Mips_HADD_S_W, + MIPS_INS_HADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hadd_u.d */ + Mips_HADD_U_D, + MIPS_INS_HADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hadd_u.h */ + Mips_HADD_U_H, + MIPS_INS_HADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hadd_u.w */ + Mips_HADD_U_W, + MIPS_INS_HADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_s.d */ + Mips_HSUB_S_D, + MIPS_INS_HSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_s.h */ + Mips_HSUB_S_H, + MIPS_INS_HSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_s.w */ + Mips_HSUB_S_W, + MIPS_INS_HSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_u.d */ + Mips_HSUB_U_D, + MIPS_INS_HSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_u.h */ + Mips_HSUB_U_H, + MIPS_INS_HSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_u.w */ + Mips_HSUB_U_W, + MIPS_INS_HSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hypcall */ + Mips_HYPCALL, + MIPS_INS_HYPCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* hypcall */ + Mips_HYPCALL_MM, + MIPS_INS_HYPCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* hypcall */ + Mips_HYPCALL, + MIPS_INS_HYPCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* hypcall */ + Mips_HYPCALL_MM, + MIPS_INS_HYPCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* ilvev.b */ + Mips_ILVEV_B, + MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvev.d */ + Mips_ILVEV_D, + MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvev.h */ + Mips_ILVEV_H, + MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvev.w */ + Mips_ILVEV_W, + MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvl.b */ + Mips_ILVL_B, + MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvl.d */ + Mips_ILVL_D, + MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvl.h */ + Mips_ILVL_H, + MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvl.w */ + Mips_ILVL_W, + MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvod.b */ + Mips_ILVOD_B, + MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvod.d */ + Mips_ILVOD_D, + MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvod.h */ + Mips_ILVOD_H, + MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvod.w */ + Mips_ILVOD_W, + MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvr.b */ + Mips_ILVR_B, + MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvr.d */ + Mips_ILVR_D, + MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvr.h */ + Mips_ILVR_H, + MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvr.w */ + Mips_ILVR_W, + MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ins */ + Mips_INS, + MIPS_INS_INS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ins */ + Mips_INS_MM, + MIPS_INS_INS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ins */ + Mips_INS_MMR6, + MIPS_INS_INS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* insert.b */ + Mips_INSERT_B, + MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insert.d */ + Mips_INSERT_D, + MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* insert.h */ + Mips_INSERT_H, + MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insert.w */ + Mips_INSERT_W, + MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insv */ + Mips_INSV_MM, + MIPS_INS_INSV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* insv */ + Mips_INSV, + MIPS_INS_INSV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* insve.b */ + Mips_INSVE_B, + MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insve.d */ + Mips_INSVE_D, + MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insve.h */ + Mips_INSVE_H, + MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insve.w */ + Mips_INSVE_W, + MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* j */ + Mips_JR, + MIPS_INS_J, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 1 +#endif + }, + {/* j */ + Mips_JR_MM, + MIPS_INS_J, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* j */ + Mips_J_MM, + MIPS_INS_J, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* j */ + Mips_J, + MIPS_INS_J, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* jal */ + Mips_JalOneReg, + MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* jal */ + Mips_JAL_MM, + MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jal */ + Mips_JAL, + MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* jal */ + Mips_BALC_MMR6, + MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* jal */ + Mips_JalTwoReg, + MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALR16_MM, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALRC16_MMR6, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALR, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALR, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOINDIRECTJUMPGUARDS, + 0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALR_MM, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALR64, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMIPS16MODE, MIPS_GRP_PTR64BIT, 0}, + 0, + 0 +#endif + }, + {/* jalr.hb */ + Mips_JALR_HB, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 1 +#endif + }, + {/* jalr.hb */ + Mips_JALR_HB64, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 1 +#endif + }, + {/* jalr.hb */ + Mips_JALR_HB, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0}, + 0, + 1 +#endif + }, + {/* jalr.hb */ + Mips_JALR_HB64, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 1 +#endif + }, + {/* jalrc */ + Mips_JumpLinkReg16, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* jalrc */ + Mips_JIALC, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 1 +#endif + }, + {/* jalrc */ + Mips_JALRC_MMR6, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalrc */ + Mips_JIALC64, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0}, + 1, + 1 +#endif + }, + {/* jalrc */ + Mips_JALRC_MMR6, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalrc.hb */ + Mips_JALRC_HB_MMR6, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 1 +#endif + }, + {/* jalrc.hb */ + Mips_JALRC_HB_MMR6, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 1 +#endif + }, + {/* jalrs */ + Mips_JALRS_MM, + MIPS_INS_JALRS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalrs16 */ + Mips_JALRS16_MM, + MIPS_INS_JALRS16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jals */ + Mips_JALS_MM, + MIPS_INS_JALS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalx */ + Mips_JALX, + MIPS_INS_JALX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* jalx */ + Mips_JALX_MM, + MIPS_INS_JALX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jialc */ + Mips_JIALC, + MIPS_INS_JIALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jialc */ + Mips_JIALC_MMR6, + MIPS_INS_JIALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jialc */ + Mips_JIALC64, + MIPS_INS_JIALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 1 +#endif + }, + {/* jic */ + Mips_JIC, + MIPS_INS_JIC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jic */ + Mips_JIC_MMR6, + MIPS_INS_JIC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jic */ + Mips_JIC64, + MIPS_INS_JIC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 1 +#endif + }, + {/* jr */ + Mips_JrRa16, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 1 +#endif + }, + {/* jr */ + Mips_JR, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 1 +#endif + }, + {/* jr */ + Mips_JALR, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* jr */ + Mips_JR_MM, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jr */ + Mips_JR64, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMIPS16MODE, MIPS_GRP_PTR64BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 1 +#endif + }, + {/* jr */ + Mips_JALR64, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* jr.hb */ + Mips_JR_HB, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 1, + 1 +#endif + }, + {/* jr.hb */ + Mips_JR_HB_R6, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jr.hb */ + Mips_JR_HB64, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 1 +#endif + }, + {/* jr.hb */ + Mips_JR_HB64_R6, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jr16 */ + Mips_JR16_MM, + MIPS_INS_JR16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jraddiusp */ + Mips_JRADDIUSP, + MIPS_INS_JRADDIUSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jrc */ + Mips_JrcRa16, + MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 1 +#endif + }, + {/* jrc */ + Mips_JrcRx16, + MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 1 +#endif + }, + {/* jrc */ + Mips_JIC, + MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jrc */ + Mips_JRC16_MM, + MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jrc */ + Mips_JIC64, + MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0}, + 1, + 1 +#endif + }, + {/* jrc16 */ + Mips_JRC16_MMR6, + MIPS_INS_JRC16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jrcaddiusp */ + Mips_JRCADDIUSP_MMR6, + MIPS_INS_JRCADDIUSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* l.d */ + Mips_LDC1, + MIPS_INS_L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* l.d */ + Mips_LDC164, + MIPS_INS_L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + 0}, + 0, + 0 +#endif + }, + {/* l.s */ + Mips_LWC1, + MIPS_INS_L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* la */ + Mips_LoadAddrImm32, + MIPS_INS_LA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* la */ + Mips_LoadAddrReg32, + MIPS_INS_LA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* lapc */ + Mips_ADDIUPC, + MIPS_INS_LAPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lapc */ + Mips_ADDIUPC_MMR6, + MIPS_INS_LAPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lb */ + Mips_LB, + MIPS_INS_LB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lb */ + Mips_LB_MMR6, + MIPS_INS_LB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lb */ + Mips_LB_MM, + MIPS_INS_LB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lbe */ + Mips_LBE, + MIPS_INS_LBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lbe */ + Mips_LBE_MM, + MIPS_INS_LBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lbu */ + Mips_LBu, + MIPS_INS_LBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lbu */ + Mips_LBU_MMR6, + MIPS_INS_LBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lbu */ + Mips_LBu_MM, + MIPS_INS_LBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lbu16 */ + Mips_LBU16_MM, + MIPS_INS_LBU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lbue */ + Mips_LBuE, + MIPS_INS_LBUE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lbue */ + Mips_LBuE_MM, + MIPS_INS_LBUE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lbux */ + Mips_LBUX_MM, + MIPS_INS_LBUX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lbux */ + Mips_LBUX, + MIPS_INS_LBUX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* ld */ + Mips_LDMacro, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS3, 0}, + 0, + 0 +#endif + }, + {/* ld */ + Mips_LD, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ld.b */ + Mips_LD_B, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ld.d */ + Mips_LD_D, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ld.h */ + Mips_LD_H, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ld.w */ + Mips_LD_W, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ldc1 */ + Mips_LDC1, + MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldc1 */ + Mips_LDC1_MM, + MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ldc1 */ + Mips_LDC164, + MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldc1 */ + Mips_LDC1_D64_MMR6, + MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ldc2 */ + Mips_LDC2_R6, + MIPS_INS_LDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldc2 */ + Mips_LDC2_MMR6, + MIPS_INS_LDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ldc2 */ + Mips_LDC2, + MIPS_INS_LDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldc3 */ + Mips_LDC3, + MIPS_INS_LDC3, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTCNMIPS, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldi.b */ + Mips_LDI_B, + MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ldi.d */ + Mips_LDI_D, + MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ldi.h */ + Mips_LDI_H, + MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ldi.w */ + Mips_LDI_W, + MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ldl */ + Mips_LDL, + MIPS_INS_LDL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* ldpc */ + Mips_LDPC, + MIPS_INS_LDPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* ldr */ + Mips_LDR, + MIPS_INS_LDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* ldxc1 */ + Mips_LDXC1, + MIPS_INS_LDXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldxc1 */ + Mips_LDXC164, + MIPS_INS_LDXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* lh */ + Mips_LH, + MIPS_INS_LH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lh */ + Mips_LH_MM, + MIPS_INS_LH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lhe */ + Mips_LHE, + MIPS_INS_LHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lhe */ + Mips_LHE_MM, + MIPS_INS_LHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lhu */ + Mips_LHu, + MIPS_INS_LHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lhu */ + Mips_LHu_MM, + MIPS_INS_LHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lhu16 */ + Mips_LHU16_MM, + MIPS_INS_LHU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lhue */ + Mips_LHuE, + MIPS_INS_LHUE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lhue */ + Mips_LHuE_MM, + MIPS_INS_LHUE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lhx */ + Mips_LHX_MM, + MIPS_INS_LHX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lhx */ + Mips_LHX, + MIPS_INS_LHX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* li */ + Mips_LiRxImmX16, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* li */ + Mips_LoadImm32, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* li */ + Mips_LiRxImm16, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* li.d */ + Mips_LoadImmDoubleGPR, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* li.d */ + Mips_LoadImmDoubleFGR_32, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* li.d */ + Mips_LoadImmDoubleFGR, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* li.s */ + Mips_LoadImmSingleGPR, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* li.s */ + Mips_LoadImmSingleFGR, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* li16 */ + Mips_LI16_MM, + MIPS_INS_LI16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* li16 */ + Mips_LI16_MMR6, + MIPS_INS_LI16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL64_R6, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR64BIT, MIPS_GRP_MIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL_R6, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL_MMR6, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR32BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL64, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL_MM, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lld */ + Mips_LLD, + MIPS_INS_LLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lld */ + Mips_LLD_R6, + MIPS_INS_LLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lle */ + Mips_LLE, + MIPS_INS_LLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lle */ + Mips_LLE_MM, + MIPS_INS_LLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lsa */ + Mips_LSA, + MIPS_INS_LSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* lsa */ + Mips_LSA_MMR6, + MIPS_INS_LSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lsa */ + Mips_LSA_R6, + MIPS_INS_LSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lui */ + Mips_LUI_MMR6, + MIPS_INS_LUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lui */ + Mips_LUi, + MIPS_INS_LUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lui */ + Mips_LUi_MM, + MIPS_INS_LUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* luxc1 */ + Mips_LUXC1, + MIPS_INS_LUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* luxc1 */ + Mips_LUXC164, + MIPS_INS_LUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* luxc1 */ + Mips_LUXC1_MM, + MIPS_INS_LUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LwRxPcTcpX16, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LWSP_MM, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LW, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LWDSP, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMIPS16MODE, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LWDSP_MM, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LW_MMR6, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LW_MM, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LWGP_MM, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LwRxSpImmX16, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LwRxPcTcp16, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* lw16 */ + Mips_LW16_MM, + MIPS_INS_LW16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwc1 */ + Mips_LWC1, + MIPS_INS_LWC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwc1 */ + Mips_LWC1_MM, + MIPS_INS_LWC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* lwc2 */ + Mips_LWC2_R6, + MIPS_INS_LWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwc2 */ + Mips_LWC2_MMR6, + MIPS_INS_LWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwc2 */ + Mips_LWC2, + MIPS_INS_LWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwc3 */ + Mips_LWC3, + MIPS_INS_LWC3, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTCNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwe */ + Mips_LWE, + MIPS_INS_LWE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lwe */ + Mips_LWE_MM, + MIPS_INS_LWE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lwl */ + Mips_LWL, + MIPS_INS_LWL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwl */ + Mips_LWL_MM, + MIPS_INS_LWL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwle */ + Mips_LWLE, + MIPS_INS_LWLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwle */ + Mips_LWLE_MM, + MIPS_INS_LWLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lwm */ + Mips_LWM_MM, + MIPS_INS_LWM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwm16 */ + Mips_LWM16_MM, + MIPS_INS_LWM16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwm16 */ + Mips_LWM16_MMR6, + MIPS_INS_LWM16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwm32 */ + Mips_LWM32_MM, + MIPS_INS_LWM32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwp */ + Mips_LWP_MM, + MIPS_INS_LWP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwpc */ + Mips_LWPC, + MIPS_INS_LWPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwpc */ + Mips_LWPC_MMR6, + MIPS_INS_LWPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwr */ + Mips_LWR, + MIPS_INS_LWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwr */ + Mips_LWR_MM, + MIPS_INS_LWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwre */ + Mips_LWRE, + MIPS_INS_LWRE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwre */ + Mips_LWRE_MM, + MIPS_INS_LWRE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lwu */ + Mips_LWU_MM, + MIPS_INS_LWU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwu */ + Mips_LWu, + MIPS_INS_LWU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwupc */ + Mips_LWUPC, + MIPS_INS_LWUPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* lwx */ + Mips_LWX_MM, + MIPS_INS_LWX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lwx */ + Mips_LWX, + MIPS_INS_LWX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lwxc1 */ + Mips_LWXC1, + MIPS_INS_LWXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* lwxc1 */ + Mips_LWXC1_MM, + MIPS_INS_LWXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* lwxs */ + Mips_LWXS_MM, + MIPS_INS_LWXS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* madd */ + Mips_MADD, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* madd */ + Mips_MADD_MM, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* madd */ + Mips_MADD_DSP_MM, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* madd */ + Mips_MADD_DSP, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* madd.d */ + Mips_MADD_D32, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* madd.d */ + Mips_MADD_D32_MM, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* madd.d */ + Mips_MADD_D64, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* madd.s */ + Mips_MADD_S, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* madd.s */ + Mips_MADD_S_MM, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* madd_q.h */ + Mips_MADD_Q_H, + MIPS_INS_MADD_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* madd_q.w */ + Mips_MADD_Q_W, + MIPS_INS_MADD_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddf.d */ + Mips_MADDF_D, + MIPS_INS_MADDF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* maddf.d */ + Mips_MADDF_D_MMR6, + MIPS_INS_MADDF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* maddf.s */ + Mips_MADDF_S, + MIPS_INS_MADDF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* maddf.s */ + Mips_MADDF_S_MMR6, + MIPS_INS_MADDF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* maddr_q.h */ + Mips_MADDR_Q_H, + MIPS_INS_MADDR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddr_q.w */ + Mips_MADDR_Q_W, + MIPS_INS_MADDR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddu */ + Mips_MADDU, + MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* maddu */ + Mips_MADDU_MM, + MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* maddu */ + Mips_MADDU_DSP_MM, + MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maddu */ + Mips_MADDU_DSP, + MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maddv.b */ + Mips_MADDV_B, + MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddv.d */ + Mips_MADDV_D, + MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddv.h */ + Mips_MADDV_H, + MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddv.w */ + Mips_MADDV_W, + MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maq_s.w.phl */ + Mips_MAQ_S_W_PHL_MM, + MIPS_INS_MAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_s.w.phl */ + Mips_MAQ_S_W_PHL, + MIPS_INS_MAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_s.w.phr */ + Mips_MAQ_S_W_PHR_MM, + MIPS_INS_MAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_s.w.phr */ + Mips_MAQ_S_W_PHR, + MIPS_INS_MAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_sa.w.phl */ + Mips_MAQ_SA_W_PHL_MM, + MIPS_INS_MAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_sa.w.phl */ + Mips_MAQ_SA_W_PHL, + MIPS_INS_MAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_sa.w.phr */ + Mips_MAQ_SA_W_PHR_MM, + MIPS_INS_MAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_sa.w.phr */ + Mips_MAQ_SA_W_PHR, + MIPS_INS_MAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* max.d */ + Mips_MAX_D, + MIPS_INS_MAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* max.d */ + Mips_MAX_D_MMR6, + MIPS_INS_MAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* max.s */ + Mips_MAX_S, + MIPS_INS_MAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* max.s */ + Mips_MAX_S_MMR6, + MIPS_INS_MAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* max_a.b */ + Mips_MAX_A_B, + MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_a.d */ + Mips_MAX_A_D, + MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_a.h */ + Mips_MAX_A_H, + MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_a.w */ + Mips_MAX_A_W, + MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_s.b */ + Mips_MAX_S_B, + MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_s.d */ + Mips_MAX_S_D, + MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_s.h */ + Mips_MAX_S_H, + MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_s.w */ + Mips_MAX_S_W, + MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_u.b */ + Mips_MAX_U_B, + MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_u.d */ + Mips_MAX_U_D, + MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_u.h */ + Mips_MAX_U_H, + MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_u.w */ + Mips_MAX_U_W, + MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxa.d */ + Mips_MAXA_D, + MIPS_INS_MAXA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* maxa.d */ + Mips_MAXA_D_MMR6, + MIPS_INS_MAXA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* maxa.s */ + Mips_MAXA_S, + MIPS_INS_MAXA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* maxa.s */ + Mips_MAXA_S_MMR6, + MIPS_INS_MAXA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* maxi_s.b */ + Mips_MAXI_S_B, + MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_s.d */ + Mips_MAXI_S_D, + MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_s.h */ + Mips_MAXI_S_H, + MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_s.w */ + Mips_MAXI_S_W, + MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_u.b */ + Mips_MAXI_U_B, + MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_u.d */ + Mips_MAXI_U_D, + MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_u.h */ + Mips_MAXI_U_H, + MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_u.w */ + Mips_MAXI_U_W, + MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mfc0 */ + Mips_MFC0, + MIPS_INS_MFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfc0 */ + Mips_MFC0_MMR6, + MIPS_INS_MFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfc0 */ + Mips_MFC0, + MIPS_INS_MFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfc0 */ + Mips_MFC0_MMR6, + MIPS_INS_MFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfc1 */ + Mips_MFC1, + MIPS_INS_MFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfc1 */ + Mips_MFC1_MMR6, + MIPS_INS_MFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mfc1 */ + Mips_MFC1_MM, + MIPS_INS_MFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mfc1 */ + Mips_MFC1_D64, + MIPS_INS_MFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfc2 */ + Mips_MFC2_MMR6, + MIPS_INS_MFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfc2 */ + Mips_MFC2, + MIPS_INS_MFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfc2 */ + Mips_MFC2, + MIPS_INS_MFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfgc0 */ + Mips_MFGC0, + MIPS_INS_MFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfgc0 */ + Mips_MFGC0_MM, + MIPS_INS_MFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mfgc0 */ + Mips_MFGC0, + MIPS_INS_MFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfgc0 */ + Mips_MFGC0_MM, + MIPS_INS_MFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mfhc0 */ + Mips_MFHC0_MMR6, + MIPS_INS_MFHC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfhc0 */ + Mips_MFHC0_MMR6, + MIPS_INS_MFHC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfhc1 */ + Mips_MFHC1_D32, + MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfhc1 */ + Mips_MFHC1_D32_MM, + MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mfhc1 */ + Mips_MFHC1_D64, + MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfhc1 */ + Mips_MFHC1_D64_MM, + MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mfhc2 */ + Mips_MFHC2_MMR6, + MIPS_INS_MFHC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfhgc0 */ + Mips_MFHGC0, + MIPS_INS_MFHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfhgc0 */ + Mips_MFHGC0_MM, + MIPS_INS_MFHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mfhgc0 */ + Mips_MFHGC0, + MIPS_INS_MFHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfhgc0 */ + Mips_MFHGC0_MM, + MIPS_INS_MFHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mfhi */ + Mips_Mfhi16, + MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* mfhi */ + Mips_MFHI, + MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfhi */ + Mips_MFHI_MM, + MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfhi */ + Mips_MFHI_DSP_MM, + MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mfhi */ + Mips_MFHI_DSP, + MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mfhi16 */ + Mips_MFHI16_MM, + MIPS_INS_MFHI16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mflo */ + Mips_Mflo16, + MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* mflo */ + Mips_MFLO, + MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mflo */ + Mips_MFLO_MM, + MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mflo */ + Mips_MFLO_DSP_MM, + MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mflo */ + Mips_MFLO_DSP, + MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mflo16 */ + Mips_MFLO16_MM, + MIPS_INS_MFLO16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mftacx */ + Mips_MFTACX, + MIPS_INS_MFTACX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mftacx */ + Mips_MFTACX, + MIPS_INS_MFTACX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftc0 */ + Mips_MFTC0, + MIPS_INS_MFTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mftc0 */ + Mips_MFTC0, + MIPS_INS_MFTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftc1 */ + Mips_MFTC1, + MIPS_INS_MFTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftdsp */ + Mips_MFTDSP, + MIPS_INS_MFTDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftgpr */ + Mips_MFTGPR, + MIPS_INS_MFTGPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mfthc1 */ + Mips_MFTHC1, + MIPS_INS_MFTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mfthi */ + Mips_MFTHI, + MIPS_INS_MFTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfthi */ + Mips_MFTHI, + MIPS_INS_MFTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftlo */ + Mips_MFTLO, + MIPS_INS_MFTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mftlo */ + Mips_MFTLO, + MIPS_INS_MFTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftr */ + Mips_MFTR, + MIPS_INS_MFTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* min.d */ + Mips_MIN_D, + MIPS_INS_MIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* min.d */ + Mips_MIN_D_MMR6, + MIPS_INS_MIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* min.s */ + Mips_MIN_S, + MIPS_INS_MIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* min.s */ + Mips_MIN_S_MMR6, + MIPS_INS_MIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* min_a.b */ + Mips_MIN_A_B, + MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_a.d */ + Mips_MIN_A_D, + MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_a.h */ + Mips_MIN_A_H, + MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_a.w */ + Mips_MIN_A_W, + MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_s.b */ + Mips_MIN_S_B, + MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_s.d */ + Mips_MIN_S_D, + MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_s.h */ + Mips_MIN_S_H, + MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_s.w */ + Mips_MIN_S_W, + MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_u.b */ + Mips_MIN_U_B, + MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_u.d */ + Mips_MIN_U_D, + MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_u.h */ + Mips_MIN_U_H, + MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_u.w */ + Mips_MIN_U_W, + MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mina.d */ + Mips_MINA_D, + MIPS_INS_MINA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mina.d */ + Mips_MINA_D_MMR6, + MIPS_INS_MINA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mina.s */ + Mips_MINA_S, + MIPS_INS_MINA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mina.s */ + Mips_MINA_S_MMR6, + MIPS_INS_MINA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mini_s.b */ + Mips_MINI_S_B, + MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_s.d */ + Mips_MINI_S_D, + MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_s.h */ + Mips_MINI_S_H, + MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_s.w */ + Mips_MINI_S_W, + MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_u.b */ + Mips_MINI_U_B, + MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_u.d */ + Mips_MINI_U_D, + MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_u.h */ + Mips_MINI_U_H, + MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_u.w */ + Mips_MINI_U_W, + MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod */ + Mips_MOD, + MIPS_INS_MOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mod */ + Mips_MOD_MMR6, + MIPS_INS_MOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mod_s.b */ + Mips_MOD_S_B, + MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_s.d */ + Mips_MOD_S_D, + MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_s.h */ + Mips_MOD_S_H, + MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_s.w */ + Mips_MOD_S_W, + MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_u.b */ + Mips_MOD_U_B, + MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_u.d */ + Mips_MOD_U_D, + MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_u.h */ + Mips_MOD_U_H, + MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_u.w */ + Mips_MOD_U_W, + MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* modsub */ + Mips_MODSUB_MM, + MIPS_INS_MODSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* modsub */ + Mips_MODSUB, + MIPS_INS_MODSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* modu */ + Mips_MODU, + MIPS_INS_MODU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* modu */ + Mips_MODU_MMR6, + MIPS_INS_MODU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mov.d */ + Mips_FMOV_D32, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mov.d */ + Mips_FMOV_D32_MM, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mov.d */ + Mips_FMOV_D64, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mov.d */ + Mips_FMOV_D64_MM, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mov.d */ + Mips_FMOV_D_MMR6, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mov.s */ + Mips_FMOV_S, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mov.s */ + Mips_FMOV_S_MMR6, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mov.s */ + Mips_FMOV_S_MM, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_MoveR3216, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_Move32R16, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_OR, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_ADDu, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_MOVE16_MM, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_OR64, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_DADDu, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* move.v */ + Mips_MOVE_V, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* move16 */ + Mips_MOVE16_MMR6, + MIPS_INS_MOVE16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* movep */ + Mips_MOVEP_MM, + MIPS_INS_MOVEP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* movep */ + Mips_MOVEP_MMR6, + MIPS_INS_MOVEP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* movf */ + Mips_MOVF_I, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movf */ + Mips_MOVF_I_MM, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movf.d */ + Mips_MOVF_D32, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movf.d */ + Mips_MOVF_D32_MM, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movf.d */ + Mips_MOVF_D64, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movf.s */ + Mips_MOVF_S, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movf.s */ + Mips_MOVF_S_MM, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movn */ + Mips_MOVN_I_I, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movn */ + Mips_MOVN_I_MM, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* movn.d */ + Mips_MOVN_I_D32, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movn.d */ + Mips_MOVN_I_D32_MM, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movn.d */ + Mips_MOVN_I_D64, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movn.s */ + Mips_MOVN_I_S, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movn.s */ + Mips_MOVN_I_S_MM, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movt */ + Mips_MOVT_I, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movt */ + Mips_MOVT_I_MM, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movt.d */ + Mips_MOVT_D32, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movt.d */ + Mips_MOVT_D32_MM, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movt.d */ + Mips_MOVT_D64, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movt.s */ + Mips_MOVT_S, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movt.s */ + Mips_MOVT_S_MM, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movz */ + Mips_MOVZ_I_I, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movz */ + Mips_MOVZ_I_MM, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* movz.d */ + Mips_MOVZ_I_D32, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movz.d */ + Mips_MOVZ_I_D32_MM, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movz.d */ + Mips_MOVZ_I_D64, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movz.s */ + Mips_MOVZ_I_S, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movz.s */ + Mips_MOVZ_I_S_MM, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* msub */ + Mips_MSUB, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* msub */ + Mips_MSUB_MM, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* msub */ + Mips_MSUB_DSP_MM, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* msub */ + Mips_MSUB_DSP, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* msub.d */ + Mips_MSUB_D32, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* msub.d */ + Mips_MSUB_D32_MM, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* msub.d */ + Mips_MSUB_D64, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* msub.s */ + Mips_MSUB_S, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* msub.s */ + Mips_MSUB_S_MM, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* msub_q.h */ + Mips_MSUB_Q_H, + MIPS_INS_MSUB_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msub_q.w */ + Mips_MSUB_Q_W, + MIPS_INS_MSUB_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubf.d */ + Mips_MSUBF_D, + MIPS_INS_MSUBF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* msubf.d */ + Mips_MSUBF_D_MMR6, + MIPS_INS_MSUBF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* msubf.s */ + Mips_MSUBF_S, + MIPS_INS_MSUBF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* msubf.s */ + Mips_MSUBF_S_MMR6, + MIPS_INS_MSUBF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* msubr_q.h */ + Mips_MSUBR_Q_H, + MIPS_INS_MSUBR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubr_q.w */ + Mips_MSUBR_Q_W, + MIPS_INS_MSUBR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubu */ + Mips_MSUBU, + MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* msubu */ + Mips_MSUBU_MM, + MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* msubu */ + Mips_MSUBU_DSP_MM, + MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* msubu */ + Mips_MSUBU_DSP, + MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* msubv.b */ + Mips_MSUBV_B, + MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubv.d */ + Mips_MSUBV_D, + MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubv.h */ + Mips_MSUBV_H, + MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubv.w */ + Mips_MSUBV_W, + MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mtc0 */ + Mips_MTC0, + MIPS_INS_MTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtc0 */ + Mips_MTC0_MMR6, + MIPS_INS_MTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mtc0 */ + Mips_MTC0, + MIPS_INS_MTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtc0 */ + Mips_MTC0_MMR6, + MIPS_INS_MTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mtc1 */ + Mips_MTC1, + MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtc1 */ + Mips_MTC1_MMR6, + MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mtc1 */ + Mips_MTC1_MM, + MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mtc1 */ + Mips_MTC1_D64, + MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtc1 */ + Mips_MTC1_D64_MM, + MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mtc2 */ + Mips_MTC2_MMR6, + MIPS_INS_MTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mtc2 */ + Mips_MTC2, + MIPS_INS_MTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtc2 */ + Mips_MTC2, + MIPS_INS_MTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtgc0 */ + Mips_MTGC0, + MIPS_INS_MTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtgc0 */ + Mips_MTGC0_MM, + MIPS_INS_MTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mtgc0 */ + Mips_MTGC0, + MIPS_INS_MTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtgc0 */ + Mips_MTGC0_MM, + MIPS_INS_MTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mthc0 */ + Mips_MTHC0_MMR6, + MIPS_INS_MTHC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mthc0 */ + Mips_MTHC0_MMR6, + MIPS_INS_MTHC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mthc1 */ + Mips_MTHC1_D32, + MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mthc1 */ + Mips_MTHC1_D32_MM, + MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mthc1 */ + Mips_MTHC1_D64, + MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mthc1 */ + Mips_MTHC1_D64_MM, + MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mthc2 */ + Mips_MTHC2_MMR6, + MIPS_INS_MTHC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mthgc0 */ + Mips_MTHGC0, + MIPS_INS_MTHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mthgc0 */ + Mips_MTHGC0_MM, + MIPS_INS_MTHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mthgc0 */ + Mips_MTHGC0, + MIPS_INS_MTHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mthgc0 */ + Mips_MTHGC0_MM, + MIPS_INS_MTHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mthi */ + Mips_MTHI, + MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mthi */ + Mips_MTHI_MM, + MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mthi */ + Mips_MTHI_DSP_MM, + MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mthi */ + Mips_MTHI_DSP, + MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mthlip */ + Mips_MTHLIP_MM, + MIPS_INS_MTHLIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mthlip */ + Mips_MTHLIP, + MIPS_INS_MTHLIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mtlo */ + Mips_MTLO, + MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtlo */ + Mips_MTLO_MM, + MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mtlo */ + Mips_MTLO_DSP_MM, + MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mtlo */ + Mips_MTLO_DSP, + MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mtm0 */ + Mips_MTM0, + MIPS_INS_MTM0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtm1 */ + Mips_MTM1, + MIPS_INS_MTM1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtm2 */ + Mips_MTM2, + MIPS_INS_MTM2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtp0 */ + Mips_MTP0, + MIPS_INS_MTP0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtp1 */ + Mips_MTP1, + MIPS_INS_MTP1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtp2 */ + Mips_MTP2, + MIPS_INS_MTP2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mttacx */ + Mips_MTTACX, + MIPS_INS_MTTACX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mttacx */ + Mips_MTTACX, + MIPS_INS_MTTACX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttc0 */ + Mips_MTTC0, + MIPS_INS_MTTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mttc0 */ + Mips_MTTC0, + MIPS_INS_MTTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttc1 */ + Mips_MTTC1, + MIPS_INS_MTTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttdsp */ + Mips_MTTDSP, + MIPS_INS_MTTDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttgpr */ + Mips_MTTGPR, + MIPS_INS_MTTGPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mtthc1 */ + Mips_MTTHC1, + MIPS_INS_MTTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mtthi */ + Mips_MTTHI, + MIPS_INS_MTTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtthi */ + Mips_MTTHI, + MIPS_INS_MTTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttlo */ + Mips_MTTLO, + MIPS_INS_MTTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mttlo */ + Mips_MTTLO, + MIPS_INS_MTTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttr */ + Mips_MTTR, + MIPS_INS_MTTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* muh */ + Mips_MUH_MMR6, + MIPS_INS_MUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* muh */ + Mips_MUH, + MIPS_INS_MUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* muh */ + Mips_MUH_MMR6, + MIPS_INS_MUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* muhu */ + Mips_MUHU_MMR6, + MIPS_INS_MUHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* muhu */ + Mips_MUHU, + MIPS_INS_MUHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* muhu */ + Mips_MUHU_MMR6, + MIPS_INS_MUHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL_MM, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL_MMR6, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL_R6, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL_MM, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL_MMR6, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MULImmMacro, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* mul.d */ + Mips_FMUL_D32, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul.d */ + Mips_FMUL_D32_MM, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mul.d */ + Mips_FMUL_D64, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul.d */ + Mips_FMUL_D64_MM, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mul.ph */ + Mips_MUL_PH_MMR2, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mul.ph */ + Mips_MUL_PH, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mul.ps */ + Mips_FMUL_PS64, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul.s */ + Mips_FMUL_S, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul.s */ + Mips_FMUL_S_MMR6, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mul.s */ + Mips_FMUL_S_MM, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mul_q.h */ + Mips_MUL_Q_H, + MIPS_INS_MUL_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mul_q.w */ + Mips_MUL_Q_W, + MIPS_INS_MUL_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mul_s.ph */ + Mips_MUL_S_PH_MMR2, + MIPS_INS_MUL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mul_s.ph */ + Mips_MUL_S_PH, + MIPS_INS_MUL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* muleq_s.w.phl */ + Mips_MULEQ_S_W_PHL_MM, + MIPS_INS_MULEQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleq_s.w.phl */ + Mips_MULEQ_S_W_PHL, + MIPS_INS_MULEQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleq_s.w.phr */ + Mips_MULEQ_S_W_PHR_MM, + MIPS_INS_MULEQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleq_s.w.phr */ + Mips_MULEQ_S_W_PHR, + MIPS_INS_MULEQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleu_s.ph.qbl */ + Mips_MULEU_S_PH_QBL_MM, + MIPS_INS_MULEU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleu_s.ph.qbl */ + Mips_MULEU_S_PH_QBL, + MIPS_INS_MULEU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleu_s.ph.qbr */ + Mips_MULEU_S_PH_QBR_MM, + MIPS_INS_MULEU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleu_s.ph.qbr */ + Mips_MULEU_S_PH_QBR, + MIPS_INS_MULEU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mulo */ + Mips_MULOMacro, + MIPS_INS_MULO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* mulo */ + Mips_MULOMacro, + MIPS_INS_MULO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* mulou */ + Mips_MULOUMacro, + MIPS_INS_MULOU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* mulou */ + Mips_MULOUMacro, + MIPS_INS_MULOU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* mulq_rs.ph */ + Mips_MULQ_RS_PH_MM, + MIPS_INS_MULQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mulq_rs.ph */ + Mips_MULQ_RS_PH, + MIPS_INS_MULQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mulq_rs.w */ + Mips_MULQ_RS_W_MMR2, + MIPS_INS_MULQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulq_rs.w */ + Mips_MULQ_RS_W, + MIPS_INS_MULQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulq_s.ph */ + Mips_MULQ_S_PH_MMR2, + MIPS_INS_MULQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulq_s.ph */ + Mips_MULQ_S_PH, + MIPS_INS_MULQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulq_s.w */ + Mips_MULQ_S_W_MMR2, + MIPS_INS_MULQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulq_s.w */ + Mips_MULQ_S_W, + MIPS_INS_MULQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulr.ps */ + Mips_MULR_PS64, + MIPS_INS_MULR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MIPS3D, 0}, + 0, + 0 +#endif + }, + {/* mulr_q.h */ + Mips_MULR_Q_H, + MIPS_INS_MULR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mulr_q.w */ + Mips_MULR_Q_W, + MIPS_INS_MULR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mulsa.w.ph */ + Mips_MULSA_W_PH_MMR2, + MIPS_INS_MULSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulsa.w.ph */ + Mips_MULSA_W_PH, + MIPS_INS_MULSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulsaq_s.w.ph */ + Mips_MULSAQ_S_W_PH_MM, + MIPS_INS_MULSAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mulsaq_s.w.ph */ + Mips_MULSAQ_S_W_PH, + MIPS_INS_MULSAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mult */ + Mips_MULT, + MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mult */ + Mips_MULT_MM, + MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mult */ + Mips_MULT_DSP_MM, + MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mult */ + Mips_MULT_DSP, + MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* multu */ + Mips_MULTu, + MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* multu */ + Mips_MULTu_MM, + MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* multu */ + Mips_MULTU_DSP_MM, + MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* multu */ + Mips_MULTU_DSP, + MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mulu */ + Mips_MULU_MMR6, + MIPS_INS_MULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mulu */ + Mips_MULU, + MIPS_INS_MULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mulu */ + Mips_MULU_MMR6, + MIPS_INS_MULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mulv.b */ + Mips_MULV_B, + MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mulv.d */ + Mips_MULV_D, + MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mulv.h */ + Mips_MULV_H, + MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mulv.w */ + Mips_MULV_W, + MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB_MM, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB_MMR6, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_NegRxRy16, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB_MM, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB_MMR6, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* neg.d */ + Mips_FNEG_D32, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* neg.d */ + Mips_FNEG_D32_MM, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* neg.d */ + Mips_FNEG_D64, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* neg.d */ + Mips_FNEG_D64_MM, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* neg.s */ + Mips_FNEG_S_MMR6, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* neg.s */ + Mips_FNEG_S, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* neg.s */ + Mips_FNEG_S_MM, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBu, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBu_MM, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBU_MMR6, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBu, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBu_MM, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBU_MMR6, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* nloc.b */ + Mips_NLOC_B, + MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nloc.d */ + Mips_NLOC_D, + MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nloc.h */ + Mips_NLOC_H, + MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nloc.w */ + Mips_NLOC_W, + MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nlzc.b */ + Mips_NLZC_B, + MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nlzc.d */ + Mips_NLZC_D, + MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nlzc.h */ + Mips_NLZC_H, + MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nlzc.w */ + Mips_NLZC_W, + MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nmadd.d */ + Mips_NMADD_D32, + MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmadd.d */ + Mips_NMADD_D32_MM, + MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* nmadd.d */ + Mips_NMADD_D64, + MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmadd.s */ + Mips_NMADD_S, + MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmadd.s */ + Mips_NMADD_S_MM, + MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* nmsub.d */ + Mips_NMSUB_D32, + MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmsub.d */ + Mips_NMSUB_D32_MM, + MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* nmsub.d */ + Mips_NMSUB_D64, + MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmsub.s */ + Mips_NMSUB_S, + MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmsub.s */ + Mips_NMSUB_S_MM, + MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* nop */ + Mips_SLL, + MIPS_INS_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nop */ + Mips_SLL_MMR6, + MIPS_INS_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* nop */ + Mips_Move32R16, + MIPS_INS_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* nop */ + Mips_SLL_MM, + MIPS_INS_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nop */ + Mips_MOVE16_MM, + MIPS_INS_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NORImm, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NORImm64, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NOR, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NOR_MM, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NOR_MMR6, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NORImm, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NORImm64, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* nor.v */ + Mips_NOR_V, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nori.b */ + Mips_NORI_B, + MIPS_INS_NORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR_MM, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR_MMR6, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NotRxRy16, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR_MM, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR_MMR6, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* not16 */ + Mips_NOT16_MM, + MIPS_INS_NOT16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* not16 */ + Mips_NOT16_MMR6, + MIPS_INS_NOT16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OrRxRxRy16, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR_MM, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR_MMR6, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORI_MMR6, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi_MM, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi64, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR_MM, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR_MMR6, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORI_MMR6, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi_MM, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi64, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or.v */ + Mips_OR_V, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* or16 */ + Mips_OR16_MM, + MIPS_INS_OR16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or16 */ + Mips_OR16_MMR6, + MIPS_INS_OR16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORI_MMR6, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORi, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORi_MM, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORI_MMR6, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORi, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORi_MM, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ori.b */ + Mips_ORI_B, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* packrl.ph */ + Mips_PACKRL_PH_MM, + MIPS_INS_PACKRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* packrl.ph */ + Mips_PACKRL_PH, + MIPS_INS_PACKRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pause */ + Mips_PAUSE, + MIPS_INS_PAUSE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* pause */ + Mips_PAUSE_MMR6, + MIPS_INS_PAUSE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* pause */ + Mips_PAUSE_MM, + MIPS_INS_PAUSE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* pckev.b */ + Mips_PCKEV_B, + MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckev.d */ + Mips_PCKEV_D, + MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckev.h */ + Mips_PCKEV_H, + MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckev.w */ + Mips_PCKEV_W, + MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckod.b */ + Mips_PCKOD_B, + MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckod.d */ + Mips_PCKOD_D, + MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckod.h */ + Mips_PCKOD_H, + MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckod.w */ + Mips_PCKOD_W, + MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pcnt.b */ + Mips_PCNT_B, + MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pcnt.d */ + Mips_PCNT_D, + MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pcnt.h */ + Mips_PCNT_H, + MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pcnt.w */ + Mips_PCNT_W, + MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pick.ph */ + Mips_PICK_PH_MM, + MIPS_INS_PICK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pick.ph */ + Mips_PICK_PH, + MIPS_INS_PICK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pick.qb */ + Mips_PICK_QB_MM, + MIPS_INS_PICK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pick.qb */ + Mips_PICK_QB, + MIPS_INS_PICK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pll.ps */ + Mips_PLL_PS64, + MIPS_INS_PLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* plu.ps */ + Mips_PLU_PS64, + MIPS_INS_PLU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* pop */ + Mips_POP, + MIPS_INS_POP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* pop */ + Mips_POP, + MIPS_INS_POP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* preceq.w.phl */ + Mips_PRECEQ_W_PHL_MM, + MIPS_INS_PRECEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceq.w.phl */ + Mips_PRECEQ_W_PHL, + MIPS_INS_PRECEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceq.w.phr */ + Mips_PRECEQ_W_PHR_MM, + MIPS_INS_PRECEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceq.w.phr */ + Mips_PRECEQ_W_PHR, + MIPS_INS_PRECEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbl */ + Mips_PRECEQU_PH_QBL_MM, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbl */ + Mips_PRECEQU_PH_QBL, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbla */ + Mips_PRECEQU_PH_QBLA_MM, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbla */ + Mips_PRECEQU_PH_QBLA, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbr */ + Mips_PRECEQU_PH_QBR_MM, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbr */ + Mips_PRECEQU_PH_QBR, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbra */ + Mips_PRECEQU_PH_QBRA_MM, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbra */ + Mips_PRECEQU_PH_QBRA, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbl */ + Mips_PRECEU_PH_QBL_MM, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbl */ + Mips_PRECEU_PH_QBL, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbla */ + Mips_PRECEU_PH_QBLA_MM, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbla */ + Mips_PRECEU_PH_QBLA, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbr */ + Mips_PRECEU_PH_QBR_MM, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbr */ + Mips_PRECEU_PH_QBR, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbra */ + Mips_PRECEU_PH_QBRA_MM, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbra */ + Mips_PRECEU_PH_QBRA, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precr.qb.ph */ + Mips_PRECR_QB_PH_MMR2, + MIPS_INS_PRECR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precr.qb.ph */ + Mips_PRECR_QB_PH, + MIPS_INS_PRECR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precr_sra.ph.w */ + Mips_PRECR_SRA_PH_W_MMR2, + MIPS_INS_PRECR_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precr_sra.ph.w */ + Mips_PRECR_SRA_PH_W, + MIPS_INS_PRECR_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precr_sra_r.ph.w */ + Mips_PRECR_SRA_R_PH_W_MMR2, + MIPS_INS_PRECR_SRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precr_sra_r.ph.w */ + Mips_PRECR_SRA_R_PH_W, + MIPS_INS_PRECR_SRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precrq.ph.w */ + Mips_PRECRQ_PH_W_MM, + MIPS_INS_PRECRQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrq.ph.w */ + Mips_PRECRQ_PH_W, + MIPS_INS_PRECRQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrq.qb.ph */ + Mips_PRECRQ_QB_PH_MM, + MIPS_INS_PRECRQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrq.qb.ph */ + Mips_PRECRQ_QB_PH, + MIPS_INS_PRECRQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrq_rs.ph.w */ + Mips_PRECRQ_RS_PH_W_MM, + MIPS_INS_PRECRQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrq_rs.ph.w */ + Mips_PRECRQ_RS_PH_W, + MIPS_INS_PRECRQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrqu_s.qb.ph */ + Mips_PRECRQU_S_QB_PH_MM, + MIPS_INS_PRECRQU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrqu_s.qb.ph */ + Mips_PRECRQU_S_QB_PH, + MIPS_INS_PRECRQU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pref */ + Mips_PREF_R6, + MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* pref */ + Mips_PREF, + MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* pref */ + Mips_PREF_MM, + MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* pref */ + Mips_PREF_MMR6, + MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* prefe */ + Mips_PREFE, + MIPS_INS_PREFE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* prefe */ + Mips_PREFE_MM, + MIPS_INS_PREFE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* prefx */ + Mips_PREFX_MM, + MIPS_INS_PREFX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* prepend */ + Mips_PREPEND_MMR2, + MIPS_INS_PREPEND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* prepend */ + Mips_PREPEND, + MIPS_INS_PREPEND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* pul.ps */ + Mips_PUL_PS64, + MIPS_INS_PUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* puu.ps */ + Mips_PUU_PS64, + MIPS_INS_PUU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* raddu.w.qb */ + Mips_RADDU_W_QB_MM, + MIPS_INS_RADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* raddu.w.qb */ + Mips_RADDU_W_QB, + MIPS_INS_RADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* rddsp */ + Mips_RDDSP_MM, + MIPS_INS_RDDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* rddsp */ + Mips_RDDSP, + MIPS_INS_RDDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR_MM, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR_MMR6, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR64, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR_MMR6, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR_MM, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rdpgpr */ + Mips_RDPGPR_MMR6, + MIPS_INS_RDPGPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* recip.d */ + Mips_RECIP_D32, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* recip.d */ + Mips_RECIP_D32_MM, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* recip.d */ + Mips_RECIP_D64, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* recip.d */ + Mips_RECIP_D64_MM, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* recip.s */ + Mips_RECIP_S, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* recip.s */ + Mips_RECIP_S_MM, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* rem */ + Mips_SRemMacro, + MIPS_INS_REM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* rem */ + Mips_SRemIMacro, + MIPS_INS_REM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* rem */ + Mips_SRemMacro, + MIPS_INS_REM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* rem */ + Mips_SRemIMacro, + MIPS_INS_REM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* remu */ + Mips_URemMacro, + MIPS_INS_REMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* remu */ + Mips_URemIMacro, + MIPS_INS_REMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* remu */ + Mips_URemMacro, + MIPS_INS_REMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* remu */ + Mips_URemIMacro, + MIPS_INS_REMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* repl.ph */ + Mips_REPL_PH_MM, + MIPS_INS_REPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* repl.ph */ + Mips_REPL_PH, + MIPS_INS_REPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* repl.qb */ + Mips_REPL_QB_MM, + MIPS_INS_REPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* repl.qb */ + Mips_REPL_QB, + MIPS_INS_REPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* replv.ph */ + Mips_REPLV_PH_MM, + MIPS_INS_REPLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* replv.ph */ + Mips_REPLV_PH, + MIPS_INS_REPLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* replv.qb */ + Mips_REPLV_QB_MM, + MIPS_INS_REPLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* replv.qb */ + Mips_REPLV_QB, + MIPS_INS_REPLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* rint.d */ + Mips_RINT_D, + MIPS_INS_RINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rint.d */ + Mips_RINT_D_MMR6, + MIPS_INS_RINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rint.s */ + Mips_RINT_S, + MIPS_INS_RINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rint.s */ + Mips_RINT_S_MMR6, + MIPS_INS_RINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rol */ + Mips_ROL, + MIPS_INS_ROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* rol */ + Mips_ROLImm, + MIPS_INS_ROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* rol */ + Mips_ROL, + MIPS_INS_ROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* rol */ + Mips_ROLImm, + MIPS_INS_ROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ror */ + Mips_ROR, + MIPS_INS_ROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ror */ + Mips_RORImm, + MIPS_INS_ROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ror */ + Mips_ROR, + MIPS_INS_ROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ror */ + Mips_RORImm, + MIPS_INS_ROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* rotr */ + Mips_ROTR, + MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotr */ + Mips_ROTR_MM, + MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotr */ + Mips_ROTR_MM, + MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotr */ + Mips_ROTR, + MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotr */ + Mips_ROTR_MM, + MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotrv */ + Mips_ROTRV, + MIPS_INS_ROTRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotrv */ + Mips_ROTRV_MM, + MIPS_INS_ROTRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.l.d */ + Mips_ROUND_L_D64, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.l.d */ + Mips_ROUND_L_D_MMR6, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* round.l.s */ + Mips_ROUND_L_S, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.l.s */ + Mips_ROUND_L_S_MMR6, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* round.w.d */ + Mips_ROUND_W_D32, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.w.d */ + Mips_ROUND_W_MM, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* round.w.d */ + Mips_ROUND_W_D64, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.w.d */ + Mips_ROUND_W_D_MMR6, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* round.w.s */ + Mips_ROUND_W_S, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.w.s */ + Mips_ROUND_W_S_MMR6, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* round.w.s */ + Mips_ROUND_W_S_MM, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.d */ + Mips_RSQRT_D32, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.d */ + Mips_RSQRT_D32_MM, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.d */ + Mips_RSQRT_D64, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.d */ + Mips_RSQRT_D64_MM, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.s */ + Mips_RSQRT_S, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.s */ + Mips_RSQRT_S_MM, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* s.d */ + Mips_SDC1, + MIPS_INS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* s.d */ + Mips_SDC1_M1, + MIPS_INS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* s.d */ + Mips_SDC1_M1, + MIPS_INS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* s.d */ + Mips_SDC164, + MIPS_INS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + 0}, + 0, + 0 +#endif + }, + {/* s.s */ + Mips_SWC1, + MIPS_INS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* saa */ + Mips_SaaAddr, + MIPS_INS_SAA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPSP, 0}, + 0, + 0 +#endif + }, + {/* saa */ + Mips_SAA, + MIPS_INS_SAA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPSP, 0}, + 0, + 0 +#endif + }, + {/* saad */ + Mips_SaadAddr, + MIPS_INS_SAAD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPSP, 0}, + 0, + 0 +#endif + }, + {/* saad */ + Mips_SAAD, + MIPS_INS_SAAD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPSP, 0}, + 0, + 0 +#endif + }, + {/* sat_s.b */ + Mips_SAT_S_B, + MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_s.d */ + Mips_SAT_S_D, + MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_s.h */ + Mips_SAT_S_H, + MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_s.w */ + Mips_SAT_S_W, + MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_u.b */ + Mips_SAT_U_B, + MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_u.d */ + Mips_SAT_U_D, + MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_u.h */ + Mips_SAT_U_H, + MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_u.w */ + Mips_SAT_U_W, + MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sb */ + Mips_SB, + MIPS_INS_SB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sb */ + Mips_SB_MMR6, + MIPS_INS_SB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sb */ + Mips_SB_MM, + MIPS_INS_SB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sb */ + Mips_SbRxRyOffMemX16, + MIPS_INS_SB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sb16 */ + Mips_SB16_MM, + MIPS_INS_SB16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sb16 */ + Mips_SB16_MMR6, + MIPS_INS_SB16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sbe */ + Mips_SBE, + MIPS_INS_SBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* sbe */ + Mips_SBE_MM, + MIPS_INS_SBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC64_R6, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR64BIT, MIPS_GRP_MIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC_R6, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC_MMR6, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR32BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC64, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC_MM, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* scd */ + Mips_SCD_R6, + MIPS_INS_SCD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* scd */ + Mips_SCD, + MIPS_INS_SCD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sce */ + Mips_SCE, + MIPS_INS_SCE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* sce */ + Mips_SCE_MM, + MIPS_INS_SCE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* sd */ + Mips_SDMacro, + MIPS_INS_SD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS3, 0}, + 0, + 0 +#endif + }, + {/* sd */ + Mips_SD, + MIPS_INS_SD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP_R6, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP_MMR6, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP_MM, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP_R6, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP_MMR6, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sdbbp16 */ + Mips_SDBBP16_MM, + MIPS_INS_SDBBP16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sdbbp16 */ + Mips_SDBBP16_MMR6, + MIPS_INS_SDBBP16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sdc1 */ + Mips_SDC1, + MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdc1 */ + Mips_SDC1_MM, + MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sdc1 */ + Mips_SDC164, + MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdc1 */ + Mips_SDC1_D64_MMR6, + MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sdc2 */ + Mips_SDC2_R6, + MIPS_INS_SDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdc2 */ + Mips_SDC2_MMR6, + MIPS_INS_SDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sdc2 */ + Mips_SDC2, + MIPS_INS_SDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdc3 */ + Mips_SDC3, + MIPS_INS_SDC3, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTCNMIPS, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdl */ + Mips_SDL, + MIPS_INS_SDL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sdr */ + Mips_SDR, + MIPS_INS_SDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sdxc1 */ + Mips_SDXC1, + MIPS_INS_SDXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdxc1 */ + Mips_SDXC164, + MIPS_INS_SDXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* seb */ + Mips_SebRx16, + MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* seb */ + Mips_SEB, + MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seb */ + Mips_SEB_MM, + MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seb */ + Mips_SEB, + MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seb */ + Mips_SEB_MM, + MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seh */ + Mips_SehRx16, + MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* seh */ + Mips_SEH, + MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seh */ + Mips_SEH_MM, + MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seh */ + Mips_SEH, + MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seh */ + Mips_SEH_MM, + MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sel.d */ + Mips_SEL_D, + MIPS_INS_SEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sel.d */ + Mips_SEL_D_MMR6, + MIPS_INS_SEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sel.s */ + Mips_SEL_S, + MIPS_INS_SEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sel.s */ + Mips_SEL_S_MMR6, + MIPS_INS_SEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* seleqz */ + Mips_SELEQZ, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seleqz */ + Mips_SELEQZ_MMR6, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* seleqz */ + Mips_SELEQZ64, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* seleqz.d */ + Mips_SELEQZ_D, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seleqz.d */ + Mips_SELEQZ_D_MMR6, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* seleqz.s */ + Mips_SELEQZ_S, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seleqz.s */ + Mips_SELEQZ_S_MMR6, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* selnez */ + Mips_SELNEZ, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* selnez */ + Mips_SELNEZ_MMR6, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* selnez */ + Mips_SELNEZ64, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* selnez.d */ + Mips_SELNEZ_D, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* selnez.d */ + Mips_SELNEZ_D_MMR6, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* selnez.s */ + Mips_SELNEZ_S, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* selnez.s */ + Mips_SELNEZ_S_MMR6, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQMacro, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQIMacro, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQ, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQMacro, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQIMacro, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQ, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seqi */ + Mips_SEQi, + MIPS_INS_SEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seqi */ + Mips_SEQi, + MIPS_INS_SEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGE, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGEImm, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGEImm64, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGE, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGEImm, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGEImm64, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEU, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEUImm, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEUImm64, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEU, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEUImm, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEUImm64, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SLT, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SLT_MM, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SGTImm, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SGTImm64, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SLT, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SLT_MM, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SGTImm, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SGTImm64, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SLTu, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SLTu_MM, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SGTUImm, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SGTUImm64, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SLTu, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SLTu_MM, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SGTUImm, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SGTUImm64, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sh */ + Mips_SH, + MIPS_INS_SH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sh */ + Mips_SH_MMR6, + MIPS_INS_SH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sh */ + Mips_SH_MM, + MIPS_INS_SH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sh */ + Mips_ShRxRyOffMemX16, + MIPS_INS_SH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sh16 */ + Mips_SH16_MM, + MIPS_INS_SH16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sh16 */ + Mips_SH16_MMR6, + MIPS_INS_SH16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* she */ + Mips_SHE, + MIPS_INS_SHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* she */ + Mips_SHE_MM, + MIPS_INS_SHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* shf.b */ + Mips_SHF_B, + MIPS_INS_SHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* shf.h */ + Mips_SHF_H, + MIPS_INS_SHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* shf.w */ + Mips_SHF_W, + MIPS_INS_SHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* shilo */ + Mips_SHILO_MM, + MIPS_INS_SHILO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shilo */ + Mips_SHILO, + MIPS_INS_SHILO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shilov */ + Mips_SHILOV_MM, + MIPS_INS_SHILOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shilov */ + Mips_SHILOV, + MIPS_INS_SHILOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll.ph */ + Mips_SHLL_PH_MM, + MIPS_INS_SHLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll.ph */ + Mips_SHLL_PH, + MIPS_INS_SHLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll.qb */ + Mips_SHLL_QB_MM, + MIPS_INS_SHLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll.qb */ + Mips_SHLL_QB, + MIPS_INS_SHLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll_s.ph */ + Mips_SHLL_S_PH_MM, + MIPS_INS_SHLL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll_s.ph */ + Mips_SHLL_S_PH, + MIPS_INS_SHLL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll_s.w */ + Mips_SHLL_S_W_MM, + MIPS_INS_SHLL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll_s.w */ + Mips_SHLL_S_W, + MIPS_INS_SHLL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv.ph */ + Mips_SHLLV_PH_MM, + MIPS_INS_SHLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv.ph */ + Mips_SHLLV_PH, + MIPS_INS_SHLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv.qb */ + Mips_SHLLV_QB_MM, + MIPS_INS_SHLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv.qb */ + Mips_SHLLV_QB, + MIPS_INS_SHLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv_s.ph */ + Mips_SHLLV_S_PH_MM, + MIPS_INS_SHLLV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv_s.ph */ + Mips_SHLLV_S_PH, + MIPS_INS_SHLLV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv_s.w */ + Mips_SHLLV_S_W_MM, + MIPS_INS_SHLLV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv_s.w */ + Mips_SHLLV_S_W, + MIPS_INS_SHLLV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra.ph */ + Mips_SHRA_PH_MM, + MIPS_INS_SHRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra.ph */ + Mips_SHRA_PH, + MIPS_INS_SHRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra.qb */ + Mips_SHRA_QB_MMR2, + MIPS_INS_SHRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shra.qb */ + Mips_SHRA_QB, + MIPS_INS_SHRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shra_r.ph */ + Mips_SHRA_R_PH_MM, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra_r.ph */ + Mips_SHRA_R_PH, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra_r.qb */ + Mips_SHRA_R_QB_MMR2, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shra_r.qb */ + Mips_SHRA_R_QB, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shra_r.w */ + Mips_SHRA_R_W_MM, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra_r.w */ + Mips_SHRA_R_W, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav.ph */ + Mips_SHRAV_PH_MM, + MIPS_INS_SHRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav.ph */ + Mips_SHRAV_PH, + MIPS_INS_SHRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav.qb */ + Mips_SHRAV_QB_MMR2, + MIPS_INS_SHRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrav.qb */ + Mips_SHRAV_QB, + MIPS_INS_SHRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.ph */ + Mips_SHRAV_R_PH_MM, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.ph */ + Mips_SHRAV_R_PH, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.qb */ + Mips_SHRAV_R_QB_MMR2, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.qb */ + Mips_SHRAV_R_QB, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.w */ + Mips_SHRAV_R_W_MM, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.w */ + Mips_SHRAV_R_W, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrl.ph */ + Mips_SHRL_PH_MMR2, + MIPS_INS_SHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrl.ph */ + Mips_SHRL_PH, + MIPS_INS_SHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrl.qb */ + Mips_SHRL_QB_MM, + MIPS_INS_SHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrl.qb */ + Mips_SHRL_QB, + MIPS_INS_SHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrlv.ph */ + Mips_SHRLV_PH_MMR2, + MIPS_INS_SHRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrlv.ph */ + Mips_SHRLV_PH, + MIPS_INS_SHRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrlv.qb */ + Mips_SHRLV_QB_MM, + MIPS_INS_SHRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrlv.qb */ + Mips_SHRLV_QB, + MIPS_INS_SHRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* sigrie */ + Mips_SIGRIE, + MIPS_INS_SIGRIE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sigrie */ + Mips_SIGRIE_MMR6, + MIPS_INS_SIGRIE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sigrie */ + Mips_SIGRIE, + MIPS_INS_SIGRIE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sigrie */ + Mips_SIGRIE_MMR6, + MIPS_INS_SIGRIE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sld.b */ + Mips_SLD_B, + MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sld.d */ + Mips_SLD_D, + MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sld.h */ + Mips_SLD_H, + MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sld.w */ + Mips_SLD_W, + MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sldi.b */ + Mips_SLDI_B, + MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sldi.d */ + Mips_SLDI_D, + MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sldi.h */ + Mips_SLDI_H, + MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sldi.w */ + Mips_SLDI_W, + MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLE, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLEImm, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLEImm64, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLE, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLEImm, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLEImm64, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEU, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEUImm, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEUImm64, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEU, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEUImm, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEUImm64, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLLV, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLLV_MM, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL_MMR6, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL_MM, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL_MM, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SllX16, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLLV, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLLV_MM, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL_MMR6, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL_MM, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll.b */ + Mips_SLL_B, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sll.d */ + Mips_SLL_D, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sll.h */ + Mips_SLL_H, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sll.w */ + Mips_SLL_W, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sll16 */ + Mips_SLL16_MM, + MIPS_INS_SLL16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sll16 */ + Mips_SLL16_MMR6, + MIPS_INS_SLL16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* slli.b */ + Mips_SLLI_B, + MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* slli.d */ + Mips_SLLI_D, + MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* slli.h */ + Mips_SLLI_H, + MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* slli.w */ + Mips_SLLI_W, + MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sllv */ + Mips_SllvRxRy16, + MIPS_INS_SLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sllv */ + Mips_SLLV, + MIPS_INS_SLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sllv */ + Mips_SLLV_MM, + MIPS_INS_SLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SltRxRy16, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTi, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTi_MM, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTImm64, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLT, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLT_MM, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTi, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTi_MM, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTImm64, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* slti */ + Mips_SltiRxImmX16, + MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* slti */ + Mips_SLTi, + MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slti */ + Mips_SLTi_MM, + MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slti */ + Mips_SltiRxImm16, + MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sltiu */ + Mips_SltiuRxImmX16, + MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sltiu */ + Mips_SLTiu, + MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltiu */ + Mips_SLTiu_MM, + MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltiu */ + Mips_SltiuRxImm16, + MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SltuRxRy16, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTiu, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTiu_MM, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTUImm64, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTu, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTu_MM, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTiu, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTiu_MM, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTUImm64, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNEMacro, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNEIMacro, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNE, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNEMacro, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNEIMacro, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNE, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* snei */ + Mips_SNEi, + MIPS_INS_SNEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* snei */ + Mips_SNEi, + MIPS_INS_SNEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* splat.b */ + Mips_SPLAT_B, + MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splat.d */ + Mips_SPLAT_D, + MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splat.h */ + Mips_SPLAT_H, + MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splat.w */ + Mips_SPLAT_W, + MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splati.b */ + Mips_SPLATI_B, + MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splati.d */ + Mips_SPLATI_D, + MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splati.h */ + Mips_SPLATI_H, + MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splati.w */ + Mips_SPLATI_W, + MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sqrt.d */ + Mips_FSQRT_D32, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sqrt.d */ + Mips_FSQRT_D32_MM, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sqrt.d */ + Mips_FSQRT_D64, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sqrt.d */ + Mips_FSQRT_D64_MM, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sqrt.s */ + Mips_FSQRT_S, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sqrt.s */ + Mips_FSQRT_S_MM, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRAV, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRAV_MM, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRA, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRA_MM, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRA_MM, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SraX16, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRAV, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRAV_MM, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRA, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRA_MM, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra.b */ + Mips_SRA_B, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sra.d */ + Mips_SRA_D, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sra.h */ + Mips_SRA_H, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sra.w */ + Mips_SRA_W, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srai.b */ + Mips_SRAI_B, + MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srai.d */ + Mips_SRAI_D, + MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srai.h */ + Mips_SRAI_H, + MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srai.w */ + Mips_SRAI_W, + MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srar.b */ + Mips_SRAR_B, + MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srar.d */ + Mips_SRAR_D, + MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srar.h */ + Mips_SRAR_H, + MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srar.w */ + Mips_SRAR_W, + MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srari.b */ + Mips_SRARI_B, + MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srari.d */ + Mips_SRARI_D, + MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srari.h */ + Mips_SRARI_H, + MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srari.w */ + Mips_SRARI_W, + MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srav */ + Mips_SravRxRy16, + MIPS_INS_SRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* srav */ + Mips_SRAV, + MIPS_INS_SRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srav */ + Mips_SRAV_MM, + MIPS_INS_SRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRLV, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRLV_MM, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRL, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRL_MM, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRL_MM, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SrlX16, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRLV, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRLV_MM, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRL, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRL_MM, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl.b */ + Mips_SRL_B, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srl.d */ + Mips_SRL_D, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srl.h */ + Mips_SRL_H, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srl.w */ + Mips_SRL_W, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srl16 */ + Mips_SRL16_MM, + MIPS_INS_SRL16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* srl16 */ + Mips_SRL16_MMR6, + MIPS_INS_SRL16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* srli.b */ + Mips_SRLI_B, + MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srli.d */ + Mips_SRLI_D, + MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srli.h */ + Mips_SRLI_H, + MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srli.w */ + Mips_SRLI_W, + MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlr.b */ + Mips_SRLR_B, + MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlr.d */ + Mips_SRLR_D, + MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlr.h */ + Mips_SRLR_H, + MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlr.w */ + Mips_SRLR_W, + MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlri.b */ + Mips_SRLRI_B, + MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlri.d */ + Mips_SRLRI_D, + MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlri.h */ + Mips_SRLRI_H, + MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlri.w */ + Mips_SRLRI_W, + MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlv */ + Mips_SrlvRxRy16, + MIPS_INS_SRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* srlv */ + Mips_SRLV, + MIPS_INS_SRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srlv */ + Mips_SRLV_MM, + MIPS_INS_SRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ssnop */ + Mips_SSNOP, + MIPS_INS_SSNOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ssnop */ + Mips_SSNOP_MMR6, + MIPS_INS_SSNOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ssnop */ + Mips_SSNOP_MM, + MIPS_INS_SSNOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* st.b */ + Mips_ST_B, + MIPS_INS_ST, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* st.d */ + Mips_ST_D, + MIPS_INS_ST, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* st.h */ + Mips_ST_H, + MIPS_INS_ST, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* st.w */ + Mips_ST_W, + MIPS_INS_ST, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB_MM, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB_MMR6, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_ADDi, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB_MM, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB_MMR6, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_ADDi, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sub.d */ + Mips_FSUB_D32, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub.d */ + Mips_FSUB_D32_MM, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sub.d */ + Mips_FSUB_D64, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub.d */ + Mips_FSUB_D64_MM, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sub.ps */ + Mips_FSUB_PS64, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub.s */ + Mips_FSUB_S, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub.s */ + Mips_FSUB_S_MMR6, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sub.s */ + Mips_FSUB_S_MM, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* subq.ph */ + Mips_SUBQ_PH_MM, + MIPS_INS_SUBQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subq.ph */ + Mips_SUBQ_PH, + MIPS_INS_SUBQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subq_s.ph */ + Mips_SUBQ_S_PH_MM, + MIPS_INS_SUBQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subq_s.ph */ + Mips_SUBQ_S_PH, + MIPS_INS_SUBQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subq_s.w */ + Mips_SUBQ_S_W_MM, + MIPS_INS_SUBQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subq_s.w */ + Mips_SUBQ_S_W, + MIPS_INS_SUBQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subqh.ph */ + Mips_SUBQH_PH_MMR2, + MIPS_INS_SUBQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh.ph */ + Mips_SUBQH_PH, + MIPS_INS_SUBQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh.w */ + Mips_SUBQH_W_MMR2, + MIPS_INS_SUBQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh.w */ + Mips_SUBQH_W, + MIPS_INS_SUBQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh_r.ph */ + Mips_SUBQH_R_PH_MMR2, + MIPS_INS_SUBQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh_r.ph */ + Mips_SUBQH_R_PH, + MIPS_INS_SUBQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh_r.w */ + Mips_SUBQH_R_W_MMR2, + MIPS_INS_SUBQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh_r.w */ + Mips_SUBQH_R_W, + MIPS_INS_SUBQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subs_s.b */ + Mips_SUBS_S_B, + MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_s.d */ + Mips_SUBS_S_D, + MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_s.h */ + Mips_SUBS_S_H, + MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_s.w */ + Mips_SUBS_S_W, + MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_u.b */ + Mips_SUBS_U_B, + MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_u.d */ + Mips_SUBS_U_D, + MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_u.h */ + Mips_SUBS_U_H, + MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_u.w */ + Mips_SUBS_U_W, + MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsus_u.b */ + Mips_SUBSUS_U_B, + MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsus_u.d */ + Mips_SUBSUS_U_D, + MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsus_u.h */ + Mips_SUBSUS_U_H, + MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsus_u.w */ + Mips_SUBSUS_U_W, + MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsuu_s.b */ + Mips_SUBSUU_S_B, + MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsuu_s.d */ + Mips_SUBSUU_S_D, + MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsuu_s.h */ + Mips_SUBSUU_S_H, + MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsuu_s.w */ + Mips_SUBSUU_S_W, + MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBU_MMR6, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBu, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBu_MM, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_ADDiu, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SubuRxRyRz16, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBU_MMR6, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBu, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBu_MM, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_ADDiu, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* subu.ph */ + Mips_SUBU_PH_MMR2, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subu.ph */ + Mips_SUBU_PH, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subu.qb */ + Mips_SUBU_QB_MM, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subu.qb */ + Mips_SUBU_QB, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subu16 */ + Mips_SUBU16_MM, + MIPS_INS_SUBU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu16 */ + Mips_SUBU16_MMR6, + MIPS_INS_SUBU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu_s.ph */ + Mips_SUBU_S_PH_MMR2, + MIPS_INS_SUBU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subu_s.ph */ + Mips_SUBU_S_PH, + MIPS_INS_SUBU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subu_s.qb */ + Mips_SUBU_S_QB_MM, + MIPS_INS_SUBU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subu_s.qb */ + Mips_SUBU_S_QB, + MIPS_INS_SUBU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subuh.qb */ + Mips_SUBUH_QB_MMR2, + MIPS_INS_SUBUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subuh.qb */ + Mips_SUBUH_QB, + MIPS_INS_SUBUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subuh_r.qb */ + Mips_SUBUH_R_QB_MMR2, + MIPS_INS_SUBUH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subuh_r.qb */ + Mips_SUBUH_R_QB, + MIPS_INS_SUBUH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subv.b */ + Mips_SUBV_B, + MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subv.d */ + Mips_SUBV_D, + MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subv.h */ + Mips_SUBV_H, + MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subv.w */ + Mips_SUBV_W, + MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subvi.b */ + Mips_SUBVI_B, + MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subvi.d */ + Mips_SUBVI_D, + MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subvi.h */ + Mips_SUBVI_H, + MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subvi.w */ + Mips_SUBVI_W, + MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* suxc1 */ + Mips_SUXC1, + MIPS_INS_SUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* suxc1 */ + Mips_SUXC164, + MIPS_INS_SUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* suxc1 */ + Mips_SUXC1_MM, + MIPS_INS_SUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SWSP_MMR6, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SWSP_MM, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SW, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SWDSP, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMIPS16MODE, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SWDSP_MM, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SW_MMR6, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SW_MM, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SwRxRyOffMemX16, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SwRxSpImmX16, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sw16 */ + Mips_SW16_MM, + MIPS_INS_SW16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sw16 */ + Mips_SW16_MMR6, + MIPS_INS_SW16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swc1 */ + Mips_SWC1, + MIPS_INS_SWC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swc1 */ + Mips_SWC1_MM, + MIPS_INS_SWC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* swc2 */ + Mips_SWC2_R6, + MIPS_INS_SWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swc2 */ + Mips_SWC2_MMR6, + MIPS_INS_SWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swc2 */ + Mips_SWC2, + MIPS_INS_SWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swc3 */ + Mips_SWC3, + MIPS_INS_SWC3, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTCNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swe */ + Mips_SWE, + MIPS_INS_SWE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* swe */ + Mips_SWE_MM, + MIPS_INS_SWE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* swl */ + Mips_SWL, + MIPS_INS_SWL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swl */ + Mips_SWL_MM, + MIPS_INS_SWL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swle */ + Mips_SWLE, + MIPS_INS_SWLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swle */ + Mips_SWLE_MM, + MIPS_INS_SWLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* swm */ + Mips_SWM_MM, + MIPS_INS_SWM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swm16 */ + Mips_SWM16_MM, + MIPS_INS_SWM16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swm16 */ + Mips_SWM16_MMR6, + MIPS_INS_SWM16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swm32 */ + Mips_SWM32_MM, + MIPS_INS_SWM32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swp */ + Mips_SWP_MM, + MIPS_INS_SWP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swr */ + Mips_SWR, + MIPS_INS_SWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swr */ + Mips_SWR_MM, + MIPS_INS_SWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swre */ + Mips_SWRE, + MIPS_INS_SWRE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swre */ + Mips_SWRE_MM, + MIPS_INS_SWRE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* swsp */ + Mips_SWSP_MM, + MIPS_INS_SWSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swxc1 */ + Mips_SWXC1, + MIPS_INS_SWXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* swxc1 */ + Mips_SWXC1_MM, + MIPS_INS_SWXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC_MMR6, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC_MM, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC_MMR6, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC_MM, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* synci */ + Mips_SYNCI, + MIPS_INS_SYNCI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* synci */ + Mips_SYNCI_MM, + MIPS_INS_SYNCI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* synci */ + Mips_SYNCI_MMR6, + MIPS_INS_SYNCI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* synciobdma */ + Mips_SYNC, + MIPS_INS_SYNCIOBDMA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* syncs */ + Mips_SYNC, + MIPS_INS_SYNCS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* syncw */ + Mips_SYNC, + MIPS_INS_SYNCW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* syncws */ + Mips_SYNC, + MIPS_INS_SYNCWS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* syscall */ + Mips_SYSCALL, + MIPS_INS_SYSCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* syscall */ + Mips_SYSCALL_MM, + MIPS_INS_SYSCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* syscall */ + Mips_SYSCALL_MM, + MIPS_INS_SYSCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* syscall */ + Mips_SYSCALL, + MIPS_INS_SYSCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teq */ + Mips_TEQ, + MIPS_INS_TEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teq */ + Mips_TEQ_MM, + MIPS_INS_TEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teq */ + Mips_TEQ_MM, + MIPS_INS_TEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teq */ + Mips_TEQ, + MIPS_INS_TEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teqi */ + Mips_TEQI, + MIPS_INS_TEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teqi */ + Mips_TEQI_MM, + MIPS_INS_TEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tge */ + Mips_TGE, + MIPS_INS_TGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tge */ + Mips_TGE_MM, + MIPS_INS_TGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tge */ + Mips_TGE_MM, + MIPS_INS_TGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tge */ + Mips_TGE, + MIPS_INS_TGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgei */ + Mips_TGEI, + MIPS_INS_TGEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgei */ + Mips_TGEI_MM, + MIPS_INS_TGEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tgeiu */ + Mips_TGEIU, + MIPS_INS_TGEIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgeiu */ + Mips_TGEIU_MM, + MIPS_INS_TGEIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tgeu */ + Mips_TGEU, + MIPS_INS_TGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgeu */ + Mips_TGEU_MM, + MIPS_INS_TGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgeu */ + Mips_TGEU_MM, + MIPS_INS_TGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgeu */ + Mips_TGEU, + MIPS_INS_TGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbginv */ + Mips_TLBGINV, + MIPS_INS_TLBGINV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbginv */ + Mips_TLBGINV_MM, + MIPS_INS_TLBGINV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbginvf */ + Mips_TLBGINVF, + MIPS_INS_TLBGINVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbginvf */ + Mips_TLBGINVF_MM, + MIPS_INS_TLBGINVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbgp */ + Mips_TLBGP, + MIPS_INS_TLBGP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbgp */ + Mips_TLBGP_MM, + MIPS_INS_TLBGP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbgr */ + Mips_TLBGR, + MIPS_INS_TLBGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbgr */ + Mips_TLBGR_MM, + MIPS_INS_TLBGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbgwi */ + Mips_TLBGWI, + MIPS_INS_TLBGWI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbgwi */ + Mips_TLBGWI_MM, + MIPS_INS_TLBGWI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbgwr */ + Mips_TLBGWR, + MIPS_INS_TLBGWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbgwr */ + Mips_TLBGWR_MM, + MIPS_INS_TLBGWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbinv */ + Mips_TLBINV, + MIPS_INS_TLBINV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* tlbinv */ + Mips_TLBINV_MMR6, + MIPS_INS_TLBINV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tlbinvf */ + Mips_TLBINVF, + MIPS_INS_TLBINVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* tlbinvf */ + Mips_TLBINVF_MMR6, + MIPS_INS_TLBINVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tlbp */ + Mips_TLBP, + MIPS_INS_TLBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbp */ + Mips_TLBP_MM, + MIPS_INS_TLBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbr */ + Mips_TLBR, + MIPS_INS_TLBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbr */ + Mips_TLBR_MM, + MIPS_INS_TLBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbwi */ + Mips_TLBWI, + MIPS_INS_TLBWI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbwi */ + Mips_TLBWI_MM, + MIPS_INS_TLBWI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbwr */ + Mips_TLBWR, + MIPS_INS_TLBWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbwr */ + Mips_TLBWR_MM, + MIPS_INS_TLBWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlt */ + Mips_TLT, + MIPS_INS_TLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlt */ + Mips_TLT_MM, + MIPS_INS_TLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlt */ + Mips_TLT_MM, + MIPS_INS_TLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlt */ + Mips_TLT, + MIPS_INS_TLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlti */ + Mips_TLTI, + MIPS_INS_TLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlti */ + Mips_TLTI_MM, + MIPS_INS_TLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tltiu */ + Mips_TTLTIU, + MIPS_INS_TLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tltiu */ + Mips_TLTIU_MM, + MIPS_INS_TLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tltu */ + Mips_TLTU, + MIPS_INS_TLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tltu */ + Mips_TLTU_MM, + MIPS_INS_TLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tltu */ + Mips_TLTU_MM, + MIPS_INS_TLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tltu */ + Mips_TLTU, + MIPS_INS_TLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tne */ + Mips_TNE, + MIPS_INS_TNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tne */ + Mips_TNE_MM, + MIPS_INS_TNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tne */ + Mips_TNE_MM, + MIPS_INS_TNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tne */ + Mips_TNE, + MIPS_INS_TNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tnei */ + Mips_TNEI, + MIPS_INS_TNEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tnei */ + Mips_TNEI_MM, + MIPS_INS_TNEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* trunc.l.d */ + Mips_TRUNC_L_D64, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* trunc.l.d */ + Mips_TRUNC_L_D_MMR6, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.l.s */ + Mips_TRUNC_L_S, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* trunc.l.s */ + Mips_TRUNC_L_S_MMR6, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_TRUNC_W_D32, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_TRUNC_W_MM, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_TRUNC_W_D64, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_TRUNC_W_D_MMR6, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_PseudoTRUNC_W_D32, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_PseudoTRUNC_W_D, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.s */ + Mips_TRUNC_W_S, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.s */ + Mips_TRUNC_W_S_MMR6, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.s */ + Mips_TRUNC_W_S_MM, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.s */ + Mips_PseudoTRUNC_W_S, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ulh */ + Mips_Ulh, + MIPS_INS_ULH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ulhu */ + Mips_Ulhu, + MIPS_INS_ULHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ulw */ + Mips_Ulw, + MIPS_INS_ULW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ush */ + Mips_Ush, + MIPS_INS_USH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* usw */ + Mips_Usw, + MIPS_INS_USW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* v3mulu */ + Mips_V3MULU, + MIPS_INS_V3MULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* v3mulu */ + Mips_V3MULU, + MIPS_INS_V3MULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* vmm0 */ + Mips_VMM0, + MIPS_INS_VMM0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* vmm0 */ + Mips_VMM0, + MIPS_INS_VMM0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* vmulu */ + Mips_VMULU, + MIPS_INS_VMULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* vmulu */ + Mips_VMULU, + MIPS_INS_VMULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* vshf.b */ + Mips_VSHF_B, + MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* vshf.d */ + Mips_VSHF_D, + MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* vshf.h */ + Mips_VSHF_H, + MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* vshf.w */ + Mips_VSHF_W, + MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* wait */ + Mips_WAIT, + MIPS_INS_WAIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wait */ + Mips_WAIT_MM, + MIPS_INS_WAIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wait */ + Mips_WAIT_MMR6, + MIPS_INS_WAIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* wait */ + Mips_WAIT_MM, + MIPS_INS_WAIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wrdsp */ + Mips_WRDSP, + MIPS_INS_WRDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wrdsp */ + Mips_WRDSP_MM, + MIPS_INS_WRDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wrdsp */ + Mips_WRDSP_MM, + MIPS_INS_WRDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* wrdsp */ + Mips_WRDSP, + MIPS_INS_WRDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wrpgpr */ + Mips_WRPGPR_MMR6, + MIPS_INS_WRPGPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* wsbh */ + Mips_WSBH, + MIPS_INS_WSBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wsbh */ + Mips_WSBH_MMR6, + MIPS_INS_WSBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* wsbh */ + Mips_WSBH_MM, + MIPS_INS_WSBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XorRxRxRy16, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR_MM, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR_MMR6, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORI_MMR6, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi_MM, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi64, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR_MM, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR_MMR6, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORI_MMR6, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi_MM, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi64, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor.v */ + Mips_XOR_V, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* xor16 */ + Mips_XOR16_MM, + MIPS_INS_XOR16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor16 */ + Mips_XOR16_MMR6, + MIPS_INS_XOR16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORI_MMR6, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORi, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORi_MM, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORI_MMR6, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORi, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORi_MM, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xori.b */ + Mips_XORI_B, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* yield */ + Mips_YIELD, + MIPS_INS_YIELD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* yield */ + Mips_YIELD, + MIPS_INS_YIELD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, +}; diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c index c8a159d80e..5c35762b6c 100644 --- a/arch/Mips/MipsMapping.c +++ b/arch/Mips/MipsMapping.c @@ -11,7 +11,8 @@ #include "MipsMapping.h" #define GET_INSTRINFO_ENUM -#include "MipsGenInstrInfo.inc" +#define GET_REGINFO_ENUM +#include "MipsGenDisassemblerTables.inc" #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { @@ -198,29 +199,15 @@ static const name_map reg_name_maps[] = { }; #endif -const char *Mips_reg_name(csh handle, unsigned int reg) -{ +const char *Mips_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps)) - return NULL; - - return reg_name_maps[reg].name; + return reg_name_maps[Mips_map_register(reg)].name; #else - return NULL; + return NULL; #endif } -static const insn_map insns[] = { - // dummy item - { - 0, 0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - -#include "MipsMappingInsn.inc" -}; +#include "MipsMapperInfo.inc" // given internal insn id, return public instruction info void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) @@ -253,818 +240,1508 @@ void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) } static const name_map insn_name_maps[] = { - { MIPS_INS_INVALID, NULL }, - - { MIPS_INS_ABSQ_S, "absq_s" }, - { MIPS_INS_ADD, "add" }, - { MIPS_INS_ADDIUPC, "addiupc" }, - { MIPS_INS_ADDIUR1SP, "addiur1sp" }, - { MIPS_INS_ADDIUR2, "addiur2" }, - { MIPS_INS_ADDIUS5, "addius5" }, - { MIPS_INS_ADDIUSP, "addiusp" }, - { MIPS_INS_ADDQH, "addqh" }, - { MIPS_INS_ADDQH_R, "addqh_r" }, - { MIPS_INS_ADDQ, "addq" }, - { MIPS_INS_ADDQ_S, "addq_s" }, - { MIPS_INS_ADDSC, "addsc" }, - { MIPS_INS_ADDS_A, "adds_a" }, - { MIPS_INS_ADDS_S, "adds_s" }, - { MIPS_INS_ADDS_U, "adds_u" }, - { MIPS_INS_ADDU16, "addu16" }, - { MIPS_INS_ADDUH, "adduh" }, - { MIPS_INS_ADDUH_R, "adduh_r" }, - { MIPS_INS_ADDU, "addu" }, - { MIPS_INS_ADDU_S, "addu_s" }, - { MIPS_INS_ADDVI, "addvi" }, - { MIPS_INS_ADDV, "addv" }, - { MIPS_INS_ADDWC, "addwc" }, - { MIPS_INS_ADD_A, "add_a" }, - { MIPS_INS_ADDI, "addi" }, - { MIPS_INS_ADDIU, "addiu" }, - { MIPS_INS_ALIGN, "align" }, - { MIPS_INS_ALUIPC, "aluipc" }, - { MIPS_INS_AND, "and" }, - { MIPS_INS_AND16, "and16" }, - { MIPS_INS_ANDI16, "andi16" }, - { MIPS_INS_ANDI, "andi" }, - { MIPS_INS_APPEND, "append" }, - { MIPS_INS_ASUB_S, "asub_s" }, - { MIPS_INS_ASUB_U, "asub_u" }, - { MIPS_INS_AUI, "aui" }, - { MIPS_INS_AUIPC, "auipc" }, - { MIPS_INS_AVER_S, "aver_s" }, - { MIPS_INS_AVER_U, "aver_u" }, - { MIPS_INS_AVE_S, "ave_s" }, - { MIPS_INS_AVE_U, "ave_u" }, - { MIPS_INS_B16, "b16" }, - { MIPS_INS_BADDU, "baddu" }, - { MIPS_INS_BAL, "bal" }, - { MIPS_INS_BALC, "balc" }, - { MIPS_INS_BALIGN, "balign" }, - { MIPS_INS_BBIT0, "bbit0" }, - { MIPS_INS_BBIT032, "bbit032" }, - { MIPS_INS_BBIT1, "bbit1" }, - { MIPS_INS_BBIT132, "bbit132" }, - { MIPS_INS_BC, "bc" }, - { MIPS_INS_BC0F, "bc0f" }, - { MIPS_INS_BC0FL, "bc0fl" }, - { MIPS_INS_BC0T, "bc0t" }, - { MIPS_INS_BC0TL, "bc0tl" }, - { MIPS_INS_BC1EQZ, "bc1eqz" }, - { MIPS_INS_BC1F, "bc1f" }, - { MIPS_INS_BC1FL, "bc1fl" }, - { MIPS_INS_BC1NEZ, "bc1nez" }, - { MIPS_INS_BC1T, "bc1t" }, - { MIPS_INS_BC1TL, "bc1tl" }, - { MIPS_INS_BC2EQZ, "bc2eqz" }, - { MIPS_INS_BC2F, "bc2f" }, - { MIPS_INS_BC2FL, "bc2fl" }, - { MIPS_INS_BC2NEZ, "bc2nez" }, - { MIPS_INS_BC2T, "bc2t" }, - { MIPS_INS_BC2TL, "bc2tl" }, - { MIPS_INS_BC3F, "bc3f" }, - { MIPS_INS_BC3FL, "bc3fl" }, - { MIPS_INS_BC3T, "bc3t" }, - { MIPS_INS_BC3TL, "bc3tl" }, - { MIPS_INS_BCLRI, "bclri" }, - { MIPS_INS_BCLR, "bclr" }, - { MIPS_INS_BEQ, "beq" }, - { MIPS_INS_BEQC, "beqc" }, - { MIPS_INS_BEQL, "beql" }, - { MIPS_INS_BEQZ16, "beqz16" }, - { MIPS_INS_BEQZALC, "beqzalc" }, - { MIPS_INS_BEQZC, "beqzc" }, - { MIPS_INS_BGEC, "bgec" }, - { MIPS_INS_BGEUC, "bgeuc" }, - { MIPS_INS_BGEZ, "bgez" }, - { MIPS_INS_BGEZAL, "bgezal" }, - { MIPS_INS_BGEZALC, "bgezalc" }, - { MIPS_INS_BGEZALL, "bgezall" }, - { MIPS_INS_BGEZALS, "bgezals" }, - { MIPS_INS_BGEZC, "bgezc" }, - { MIPS_INS_BGEZL, "bgezl" }, - { MIPS_INS_BGTZ, "bgtz" }, - { MIPS_INS_BGTZALC, "bgtzalc" }, - { MIPS_INS_BGTZC, "bgtzc" }, - { MIPS_INS_BGTZL, "bgtzl" }, - { MIPS_INS_BINSLI, "binsli" }, - { MIPS_INS_BINSL, "binsl" }, - { MIPS_INS_BINSRI, "binsri" }, - { MIPS_INS_BINSR, "binsr" }, - { MIPS_INS_BITREV, "bitrev" }, - { MIPS_INS_BITSWAP, "bitswap" }, - { MIPS_INS_BLEZ, "blez" }, - { MIPS_INS_BLEZALC, "blezalc" }, - { MIPS_INS_BLEZC, "blezc" }, - { MIPS_INS_BLEZL, "blezl" }, - { MIPS_INS_BLTC, "bltc" }, - { MIPS_INS_BLTUC, "bltuc" }, - { MIPS_INS_BLTZ, "bltz" }, - { MIPS_INS_BLTZAL, "bltzal" }, - { MIPS_INS_BLTZALC, "bltzalc" }, - { MIPS_INS_BLTZALL, "bltzall" }, - { MIPS_INS_BLTZALS, "bltzals" }, - { MIPS_INS_BLTZC, "bltzc" }, - { MIPS_INS_BLTZL, "bltzl" }, - { MIPS_INS_BMNZI, "bmnzi" }, - { MIPS_INS_BMNZ, "bmnz" }, - { MIPS_INS_BMZI, "bmzi" }, - { MIPS_INS_BMZ, "bmz" }, - { MIPS_INS_BNE, "bne" }, - { MIPS_INS_BNEC, "bnec" }, - { MIPS_INS_BNEGI, "bnegi" }, - { MIPS_INS_BNEG, "bneg" }, - { MIPS_INS_BNEL, "bnel" }, - { MIPS_INS_BNEZ16, "bnez16" }, - { MIPS_INS_BNEZALC, "bnezalc" }, - { MIPS_INS_BNEZC, "bnezc" }, - { MIPS_INS_BNVC, "bnvc" }, - { MIPS_INS_BNZ, "bnz" }, - { MIPS_INS_BOVC, "bovc" }, - { MIPS_INS_BPOSGE32, "bposge32" }, - { MIPS_INS_BREAK, "break" }, - { MIPS_INS_BREAK16, "break16" }, - { MIPS_INS_BSELI, "bseli" }, - { MIPS_INS_BSEL, "bsel" }, - { MIPS_INS_BSETI, "bseti" }, - { MIPS_INS_BSET, "bset" }, - { MIPS_INS_BZ, "bz" }, - { MIPS_INS_BEQZ, "beqz" }, - { MIPS_INS_B, "b" }, - { MIPS_INS_BNEZ, "bnez" }, - { MIPS_INS_BTEQZ, "bteqz" }, - { MIPS_INS_BTNEZ, "btnez" }, - { MIPS_INS_CACHE, "cache" }, - { MIPS_INS_CEIL, "ceil" }, - { MIPS_INS_CEQI, "ceqi" }, - { MIPS_INS_CEQ, "ceq" }, - { MIPS_INS_CFC1, "cfc1" }, - { MIPS_INS_CFCMSA, "cfcmsa" }, - { MIPS_INS_CINS, "cins" }, - { MIPS_INS_CINS32, "cins32" }, - { MIPS_INS_CLASS, "class" }, - { MIPS_INS_CLEI_S, "clei_s" }, - { MIPS_INS_CLEI_U, "clei_u" }, - { MIPS_INS_CLE_S, "cle_s" }, - { MIPS_INS_CLE_U, "cle_u" }, - { MIPS_INS_CLO, "clo" }, - { MIPS_INS_CLTI_S, "clti_s" }, - { MIPS_INS_CLTI_U, "clti_u" }, - { MIPS_INS_CLT_S, "clt_s" }, - { MIPS_INS_CLT_U, "clt_u" }, - { MIPS_INS_CLZ, "clz" }, - { MIPS_INS_CMPGDU, "cmpgdu" }, - { MIPS_INS_CMPGU, "cmpgu" }, - { MIPS_INS_CMPU, "cmpu" }, - { MIPS_INS_CMP, "cmp" }, - { MIPS_INS_COPY_S, "copy_s" }, - { MIPS_INS_COPY_U, "copy_u" }, - { MIPS_INS_CTC1, "ctc1" }, - { MIPS_INS_CTCMSA, "ctcmsa" }, - { MIPS_INS_CVT, "cvt" }, - { MIPS_INS_C, "c" }, - { MIPS_INS_CMPI, "cmpi" }, - { MIPS_INS_DADD, "dadd" }, - { MIPS_INS_DADDI, "daddi" }, - { MIPS_INS_DADDIU, "daddiu" }, - { MIPS_INS_DADDU, "daddu" }, - { MIPS_INS_DAHI, "dahi" }, - { MIPS_INS_DALIGN, "dalign" }, - { MIPS_INS_DATI, "dati" }, - { MIPS_INS_DAUI, "daui" }, - { MIPS_INS_DBITSWAP, "dbitswap" }, - { MIPS_INS_DCLO, "dclo" }, - { MIPS_INS_DCLZ, "dclz" }, - { MIPS_INS_DDIV, "ddiv" }, - { MIPS_INS_DDIVU, "ddivu" }, - { MIPS_INS_DERET, "deret" }, - { MIPS_INS_DEXT, "dext" }, - { MIPS_INS_DEXTM, "dextm" }, - { MIPS_INS_DEXTU, "dextu" }, - { MIPS_INS_DI, "di" }, - { MIPS_INS_DINS, "dins" }, - { MIPS_INS_DINSM, "dinsm" }, - { MIPS_INS_DINSU, "dinsu" }, - { MIPS_INS_DIV, "div" }, - { MIPS_INS_DIVU, "divu" }, - { MIPS_INS_DIV_S, "div_s" }, - { MIPS_INS_DIV_U, "div_u" }, - { MIPS_INS_DLSA, "dlsa" }, - { MIPS_INS_DMFC0, "dmfc0" }, - { MIPS_INS_DMFC1, "dmfc1" }, - { MIPS_INS_DMFC2, "dmfc2" }, - { MIPS_INS_DMOD, "dmod" }, - { MIPS_INS_DMODU, "dmodu" }, - { MIPS_INS_DMTC0, "dmtc0" }, - { MIPS_INS_DMTC1, "dmtc1" }, - { MIPS_INS_DMTC2, "dmtc2" }, - { MIPS_INS_DMUH, "dmuh" }, - { MIPS_INS_DMUHU, "dmuhu" }, - { MIPS_INS_DMUL, "dmul" }, - { MIPS_INS_DMULT, "dmult" }, - { MIPS_INS_DMULTU, "dmultu" }, - { MIPS_INS_DMULU, "dmulu" }, - { MIPS_INS_DOTP_S, "dotp_s" }, - { MIPS_INS_DOTP_U, "dotp_u" }, - { MIPS_INS_DPADD_S, "dpadd_s" }, - { MIPS_INS_DPADD_U, "dpadd_u" }, - { MIPS_INS_DPAQX_SA, "dpaqx_sa" }, - { MIPS_INS_DPAQX_S, "dpaqx_s" }, - { MIPS_INS_DPAQ_SA, "dpaq_sa" }, - { MIPS_INS_DPAQ_S, "dpaq_s" }, - { MIPS_INS_DPAU, "dpau" }, - { MIPS_INS_DPAX, "dpax" }, - { MIPS_INS_DPA, "dpa" }, - { MIPS_INS_DPOP, "dpop" }, - { MIPS_INS_DPSQX_SA, "dpsqx_sa" }, - { MIPS_INS_DPSQX_S, "dpsqx_s" }, - { MIPS_INS_DPSQ_SA, "dpsq_sa" }, - { MIPS_INS_DPSQ_S, "dpsq_s" }, - { MIPS_INS_DPSUB_S, "dpsub_s" }, - { MIPS_INS_DPSUB_U, "dpsub_u" }, - { MIPS_INS_DPSU, "dpsu" }, - { MIPS_INS_DPSX, "dpsx" }, - { MIPS_INS_DPS, "dps" }, - { MIPS_INS_DROTR, "drotr" }, - { MIPS_INS_DROTR32, "drotr32" }, - { MIPS_INS_DROTRV, "drotrv" }, - { MIPS_INS_DSBH, "dsbh" }, - { MIPS_INS_DSHD, "dshd" }, - { MIPS_INS_DSLL, "dsll" }, - { MIPS_INS_DSLL32, "dsll32" }, - { MIPS_INS_DSLLV, "dsllv" }, - { MIPS_INS_DSRA, "dsra" }, - { MIPS_INS_DSRA32, "dsra32" }, - { MIPS_INS_DSRAV, "dsrav" }, - { MIPS_INS_DSRL, "dsrl" }, - { MIPS_INS_DSRL32, "dsrl32" }, - { MIPS_INS_DSRLV, "dsrlv" }, - { MIPS_INS_DSUB, "dsub" }, - { MIPS_INS_DSUBU, "dsubu" }, - { MIPS_INS_EHB, "ehb" }, - { MIPS_INS_EI, "ei" }, - { MIPS_INS_ERET, "eret" }, - { MIPS_INS_EXT, "ext" }, - { MIPS_INS_EXTP, "extp" }, - { MIPS_INS_EXTPDP, "extpdp" }, - { MIPS_INS_EXTPDPV, "extpdpv" }, - { MIPS_INS_EXTPV, "extpv" }, - { MIPS_INS_EXTRV_RS, "extrv_rs" }, - { MIPS_INS_EXTRV_R, "extrv_r" }, - { MIPS_INS_EXTRV_S, "extrv_s" }, - { MIPS_INS_EXTRV, "extrv" }, - { MIPS_INS_EXTR_RS, "extr_rs" }, - { MIPS_INS_EXTR_R, "extr_r" }, - { MIPS_INS_EXTR_S, "extr_s" }, - { MIPS_INS_EXTR, "extr" }, - { MIPS_INS_EXTS, "exts" }, - { MIPS_INS_EXTS32, "exts32" }, - { MIPS_INS_ABS, "abs" }, - { MIPS_INS_FADD, "fadd" }, - { MIPS_INS_FCAF, "fcaf" }, - { MIPS_INS_FCEQ, "fceq" }, - { MIPS_INS_FCLASS, "fclass" }, - { MIPS_INS_FCLE, "fcle" }, - { MIPS_INS_FCLT, "fclt" }, - { MIPS_INS_FCNE, "fcne" }, - { MIPS_INS_FCOR, "fcor" }, - { MIPS_INS_FCUEQ, "fcueq" }, - { MIPS_INS_FCULE, "fcule" }, - { MIPS_INS_FCULT, "fcult" }, - { MIPS_INS_FCUNE, "fcune" }, - { MIPS_INS_FCUN, "fcun" }, - { MIPS_INS_FDIV, "fdiv" }, - { MIPS_INS_FEXDO, "fexdo" }, - { MIPS_INS_FEXP2, "fexp2" }, - { MIPS_INS_FEXUPL, "fexupl" }, - { MIPS_INS_FEXUPR, "fexupr" }, - { MIPS_INS_FFINT_S, "ffint_s" }, - { MIPS_INS_FFINT_U, "ffint_u" }, - { MIPS_INS_FFQL, "ffql" }, - { MIPS_INS_FFQR, "ffqr" }, - { MIPS_INS_FILL, "fill" }, - { MIPS_INS_FLOG2, "flog2" }, - { MIPS_INS_FLOOR, "floor" }, - { MIPS_INS_FMADD, "fmadd" }, - { MIPS_INS_FMAX_A, "fmax_a" }, - { MIPS_INS_FMAX, "fmax" }, - { MIPS_INS_FMIN_A, "fmin_a" }, - { MIPS_INS_FMIN, "fmin" }, - { MIPS_INS_MOV, "mov" }, - { MIPS_INS_FMSUB, "fmsub" }, - { MIPS_INS_FMUL, "fmul" }, - { MIPS_INS_MUL, "mul" }, - { MIPS_INS_NEG, "neg" }, - { MIPS_INS_FRCP, "frcp" }, - { MIPS_INS_FRINT, "frint" }, - { MIPS_INS_FRSQRT, "frsqrt" }, - { MIPS_INS_FSAF, "fsaf" }, - { MIPS_INS_FSEQ, "fseq" }, - { MIPS_INS_FSLE, "fsle" }, - { MIPS_INS_FSLT, "fslt" }, - { MIPS_INS_FSNE, "fsne" }, - { MIPS_INS_FSOR, "fsor" }, - { MIPS_INS_FSQRT, "fsqrt" }, - { MIPS_INS_SQRT, "sqrt" }, - { MIPS_INS_FSUB, "fsub" }, - { MIPS_INS_SUB, "sub" }, - { MIPS_INS_FSUEQ, "fsueq" }, - { MIPS_INS_FSULE, "fsule" }, - { MIPS_INS_FSULT, "fsult" }, - { MIPS_INS_FSUNE, "fsune" }, - { MIPS_INS_FSUN, "fsun" }, - { MIPS_INS_FTINT_S, "ftint_s" }, - { MIPS_INS_FTINT_U, "ftint_u" }, - { MIPS_INS_FTQ, "ftq" }, - { MIPS_INS_FTRUNC_S, "ftrunc_s" }, - { MIPS_INS_FTRUNC_U, "ftrunc_u" }, - { MIPS_INS_HADD_S, "hadd_s" }, - { MIPS_INS_HADD_U, "hadd_u" }, - { MIPS_INS_HSUB_S, "hsub_s" }, - { MIPS_INS_HSUB_U, "hsub_u" }, - { MIPS_INS_ILVEV, "ilvev" }, - { MIPS_INS_ILVL, "ilvl" }, - { MIPS_INS_ILVOD, "ilvod" }, - { MIPS_INS_ILVR, "ilvr" }, - { MIPS_INS_INS, "ins" }, - { MIPS_INS_INSERT, "insert" }, - { MIPS_INS_INSV, "insv" }, - { MIPS_INS_INSVE, "insve" }, - { MIPS_INS_J, "j" }, - { MIPS_INS_JAL, "jal" }, - { MIPS_INS_JALR, "jalr" }, - { MIPS_INS_JALRS16, "jalrs16" }, - { MIPS_INS_JALRS, "jalrs" }, - { MIPS_INS_JALS, "jals" }, - { MIPS_INS_JALX, "jalx" }, - { MIPS_INS_JIALC, "jialc" }, - { MIPS_INS_JIC, "jic" }, - { MIPS_INS_JR, "jr" }, - { MIPS_INS_JR16, "jr16" }, - { MIPS_INS_JRADDIUSP, "jraddiusp" }, - { MIPS_INS_JRC, "jrc" }, - { MIPS_INS_JALRC, "jalrc" }, - { MIPS_INS_LB, "lb" }, - { MIPS_INS_LBU16, "lbu16" }, - { MIPS_INS_LBUX, "lbux" }, - { MIPS_INS_LBU, "lbu" }, - { MIPS_INS_LD, "ld" }, - { MIPS_INS_LDC1, "ldc1" }, - { MIPS_INS_LDC2, "ldc2" }, - { MIPS_INS_LDC3, "ldc3" }, - { MIPS_INS_LDI, "ldi" }, - { MIPS_INS_LDL, "ldl" }, - { MIPS_INS_LDPC, "ldpc" }, - { MIPS_INS_LDR, "ldr" }, - { MIPS_INS_LDXC1, "ldxc1" }, - { MIPS_INS_LH, "lh" }, - { MIPS_INS_LHU16, "lhu16" }, - { MIPS_INS_LHX, "lhx" }, - { MIPS_INS_LHU, "lhu" }, - { MIPS_INS_LI16, "li16" }, - { MIPS_INS_LL, "ll" }, - { MIPS_INS_LLD, "lld" }, - { MIPS_INS_LSA, "lsa" }, - { MIPS_INS_LUXC1, "luxc1" }, - { MIPS_INS_LUI, "lui" }, - { MIPS_INS_LW, "lw" }, - { MIPS_INS_LW16, "lw16" }, - { MIPS_INS_LWC1, "lwc1" }, - { MIPS_INS_LWC2, "lwc2" }, - { MIPS_INS_LWC3, "lwc3" }, - { MIPS_INS_LWL, "lwl" }, - { MIPS_INS_LWM16, "lwm16" }, - { MIPS_INS_LWM32, "lwm32" }, - { MIPS_INS_LWPC, "lwpc" }, - { MIPS_INS_LWP, "lwp" }, - { MIPS_INS_LWR, "lwr" }, - { MIPS_INS_LWUPC, "lwupc" }, - { MIPS_INS_LWU, "lwu" }, - { MIPS_INS_LWX, "lwx" }, - { MIPS_INS_LWXC1, "lwxc1" }, - { MIPS_INS_LWXS, "lwxs" }, - { MIPS_INS_LI, "li" }, - { MIPS_INS_MADD, "madd" }, - { MIPS_INS_MADDF, "maddf" }, - { MIPS_INS_MADDR_Q, "maddr_q" }, - { MIPS_INS_MADDU, "maddu" }, - { MIPS_INS_MADDV, "maddv" }, - { MIPS_INS_MADD_Q, "madd_q" }, - { MIPS_INS_MAQ_SA, "maq_sa" }, - { MIPS_INS_MAQ_S, "maq_s" }, - { MIPS_INS_MAXA, "maxa" }, - { MIPS_INS_MAXI_S, "maxi_s" }, - { MIPS_INS_MAXI_U, "maxi_u" }, - { MIPS_INS_MAX_A, "max_a" }, - { MIPS_INS_MAX, "max" }, - { MIPS_INS_MAX_S, "max_s" }, - { MIPS_INS_MAX_U, "max_u" }, - { MIPS_INS_MFC0, "mfc0" }, - { MIPS_INS_MFC1, "mfc1" }, - { MIPS_INS_MFC2, "mfc2" }, - { MIPS_INS_MFHC1, "mfhc1" }, - { MIPS_INS_MFHI, "mfhi" }, - { MIPS_INS_MFLO, "mflo" }, - { MIPS_INS_MINA, "mina" }, - { MIPS_INS_MINI_S, "mini_s" }, - { MIPS_INS_MINI_U, "mini_u" }, - { MIPS_INS_MIN_A, "min_a" }, - { MIPS_INS_MIN, "min" }, - { MIPS_INS_MIN_S, "min_s" }, - { MIPS_INS_MIN_U, "min_u" }, - { MIPS_INS_MOD, "mod" }, - { MIPS_INS_MODSUB, "modsub" }, - { MIPS_INS_MODU, "modu" }, - { MIPS_INS_MOD_S, "mod_s" }, - { MIPS_INS_MOD_U, "mod_u" }, - { MIPS_INS_MOVE, "move" }, - { MIPS_INS_MOVEP, "movep" }, - { MIPS_INS_MOVF, "movf" }, - { MIPS_INS_MOVN, "movn" }, - { MIPS_INS_MOVT, "movt" }, - { MIPS_INS_MOVZ, "movz" }, - { MIPS_INS_MSUB, "msub" }, - { MIPS_INS_MSUBF, "msubf" }, - { MIPS_INS_MSUBR_Q, "msubr_q" }, - { MIPS_INS_MSUBU, "msubu" }, - { MIPS_INS_MSUBV, "msubv" }, - { MIPS_INS_MSUB_Q, "msub_q" }, - { MIPS_INS_MTC0, "mtc0" }, - { MIPS_INS_MTC1, "mtc1" }, - { MIPS_INS_MTC2, "mtc2" }, - { MIPS_INS_MTHC1, "mthc1" }, - { MIPS_INS_MTHI, "mthi" }, - { MIPS_INS_MTHLIP, "mthlip" }, - { MIPS_INS_MTLO, "mtlo" }, - { MIPS_INS_MTM0, "mtm0" }, - { MIPS_INS_MTM1, "mtm1" }, - { MIPS_INS_MTM2, "mtm2" }, - { MIPS_INS_MTP0, "mtp0" }, - { MIPS_INS_MTP1, "mtp1" }, - { MIPS_INS_MTP2, "mtp2" }, - { MIPS_INS_MUH, "muh" }, - { MIPS_INS_MUHU, "muhu" }, - { MIPS_INS_MULEQ_S, "muleq_s" }, - { MIPS_INS_MULEU_S, "muleu_s" }, - { MIPS_INS_MULQ_RS, "mulq_rs" }, - { MIPS_INS_MULQ_S, "mulq_s" }, - { MIPS_INS_MULR_Q, "mulr_q" }, - { MIPS_INS_MULSAQ_S, "mulsaq_s" }, - { MIPS_INS_MULSA, "mulsa" }, - { MIPS_INS_MULT, "mult" }, - { MIPS_INS_MULTU, "multu" }, - { MIPS_INS_MULU, "mulu" }, - { MIPS_INS_MULV, "mulv" }, - { MIPS_INS_MUL_Q, "mul_q" }, - { MIPS_INS_MUL_S, "mul_s" }, - { MIPS_INS_NLOC, "nloc" }, - { MIPS_INS_NLZC, "nlzc" }, - { MIPS_INS_NMADD, "nmadd" }, - { MIPS_INS_NMSUB, "nmsub" }, - { MIPS_INS_NOR, "nor" }, - { MIPS_INS_NORI, "nori" }, - { MIPS_INS_NOT16, "not16" }, - { MIPS_INS_NOT, "not" }, - { MIPS_INS_OR, "or" }, - { MIPS_INS_OR16, "or16" }, - { MIPS_INS_ORI, "ori" }, - { MIPS_INS_PACKRL, "packrl" }, - { MIPS_INS_PAUSE, "pause" }, - { MIPS_INS_PCKEV, "pckev" }, - { MIPS_INS_PCKOD, "pckod" }, - { MIPS_INS_PCNT, "pcnt" }, - { MIPS_INS_PICK, "pick" }, - { MIPS_INS_POP, "pop" }, - { MIPS_INS_PRECEQU, "precequ" }, - { MIPS_INS_PRECEQ, "preceq" }, - { MIPS_INS_PRECEU, "preceu" }, - { MIPS_INS_PRECRQU_S, "precrqu_s" }, - { MIPS_INS_PRECRQ, "precrq" }, - { MIPS_INS_PRECRQ_RS, "precrq_rs" }, - { MIPS_INS_PRECR, "precr" }, - { MIPS_INS_PRECR_SRA, "precr_sra" }, - { MIPS_INS_PRECR_SRA_R, "precr_sra_r" }, - { MIPS_INS_PREF, "pref" }, - { MIPS_INS_PREPEND, "prepend" }, - { MIPS_INS_RADDU, "raddu" }, - { MIPS_INS_RDDSP, "rddsp" }, - { MIPS_INS_RDHWR, "rdhwr" }, - { MIPS_INS_REPLV, "replv" }, - { MIPS_INS_REPL, "repl" }, - { MIPS_INS_RINT, "rint" }, - { MIPS_INS_ROTR, "rotr" }, - { MIPS_INS_ROTRV, "rotrv" }, - { MIPS_INS_ROUND, "round" }, - { MIPS_INS_SAT_S, "sat_s" }, - { MIPS_INS_SAT_U, "sat_u" }, - { MIPS_INS_SB, "sb" }, - { MIPS_INS_SB16, "sb16" }, - { MIPS_INS_SC, "sc" }, - { MIPS_INS_SCD, "scd" }, - { MIPS_INS_SD, "sd" }, - { MIPS_INS_SDBBP, "sdbbp" }, - { MIPS_INS_SDBBP16, "sdbbp16" }, - { MIPS_INS_SDC1, "sdc1" }, - { MIPS_INS_SDC2, "sdc2" }, - { MIPS_INS_SDC3, "sdc3" }, - { MIPS_INS_SDL, "sdl" }, - { MIPS_INS_SDR, "sdr" }, - { MIPS_INS_SDXC1, "sdxc1" }, - { MIPS_INS_SEB, "seb" }, - { MIPS_INS_SEH, "seh" }, - { MIPS_INS_SELEQZ, "seleqz" }, - { MIPS_INS_SELNEZ, "selnez" }, - { MIPS_INS_SEL, "sel" }, - { MIPS_INS_SEQ, "seq" }, - { MIPS_INS_SEQI, "seqi" }, - { MIPS_INS_SH, "sh" }, - { MIPS_INS_SH16, "sh16" }, - { MIPS_INS_SHF, "shf" }, - { MIPS_INS_SHILO, "shilo" }, - { MIPS_INS_SHILOV, "shilov" }, - { MIPS_INS_SHLLV, "shllv" }, - { MIPS_INS_SHLLV_S, "shllv_s" }, - { MIPS_INS_SHLL, "shll" }, - { MIPS_INS_SHLL_S, "shll_s" }, - { MIPS_INS_SHRAV, "shrav" }, - { MIPS_INS_SHRAV_R, "shrav_r" }, - { MIPS_INS_SHRA, "shra" }, - { MIPS_INS_SHRA_R, "shra_r" }, - { MIPS_INS_SHRLV, "shrlv" }, - { MIPS_INS_SHRL, "shrl" }, - { MIPS_INS_SLDI, "sldi" }, - { MIPS_INS_SLD, "sld" }, - { MIPS_INS_SLL, "sll" }, - { MIPS_INS_SLL16, "sll16" }, - { MIPS_INS_SLLI, "slli" }, - { MIPS_INS_SLLV, "sllv" }, - { MIPS_INS_SLT, "slt" }, - { MIPS_INS_SLTI, "slti" }, - { MIPS_INS_SLTIU, "sltiu" }, - { MIPS_INS_SLTU, "sltu" }, - { MIPS_INS_SNE, "sne" }, - { MIPS_INS_SNEI, "snei" }, - { MIPS_INS_SPLATI, "splati" }, - { MIPS_INS_SPLAT, "splat" }, - { MIPS_INS_SRA, "sra" }, - { MIPS_INS_SRAI, "srai" }, - { MIPS_INS_SRARI, "srari" }, - { MIPS_INS_SRAR, "srar" }, - { MIPS_INS_SRAV, "srav" }, - { MIPS_INS_SRL, "srl" }, - { MIPS_INS_SRL16, "srl16" }, - { MIPS_INS_SRLI, "srli" }, - { MIPS_INS_SRLRI, "srlri" }, - { MIPS_INS_SRLR, "srlr" }, - { MIPS_INS_SRLV, "srlv" }, - { MIPS_INS_SSNOP, "ssnop" }, - { MIPS_INS_ST, "st" }, - { MIPS_INS_SUBQH, "subqh" }, - { MIPS_INS_SUBQH_R, "subqh_r" }, - { MIPS_INS_SUBQ, "subq" }, - { MIPS_INS_SUBQ_S, "subq_s" }, - { MIPS_INS_SUBSUS_U, "subsus_u" }, - { MIPS_INS_SUBSUU_S, "subsuu_s" }, - { MIPS_INS_SUBS_S, "subs_s" }, - { MIPS_INS_SUBS_U, "subs_u" }, - { MIPS_INS_SUBU16, "subu16" }, - { MIPS_INS_SUBUH, "subuh" }, - { MIPS_INS_SUBUH_R, "subuh_r" }, - { MIPS_INS_SUBU, "subu" }, - { MIPS_INS_SUBU_S, "subu_s" }, - { MIPS_INS_SUBVI, "subvi" }, - { MIPS_INS_SUBV, "subv" }, - { MIPS_INS_SUXC1, "suxc1" }, - { MIPS_INS_SW, "sw" }, - { MIPS_INS_SW16, "sw16" }, - { MIPS_INS_SWC1, "swc1" }, - { MIPS_INS_SWC2, "swc2" }, - { MIPS_INS_SWC3, "swc3" }, - { MIPS_INS_SWL, "swl" }, - { MIPS_INS_SWM16, "swm16" }, - { MIPS_INS_SWM32, "swm32" }, - { MIPS_INS_SWP, "swp" }, - { MIPS_INS_SWR, "swr" }, - { MIPS_INS_SWXC1, "swxc1" }, - { MIPS_INS_SYNC, "sync" }, - { MIPS_INS_SYNCI, "synci" }, - { MIPS_INS_SYSCALL, "syscall" }, - { MIPS_INS_TEQ, "teq" }, - { MIPS_INS_TEQI, "teqi" }, - { MIPS_INS_TGE, "tge" }, - { MIPS_INS_TGEI, "tgei" }, - { MIPS_INS_TGEIU, "tgeiu" }, - { MIPS_INS_TGEU, "tgeu" }, - { MIPS_INS_TLBP, "tlbp" }, - { MIPS_INS_TLBR, "tlbr" }, - { MIPS_INS_TLBWI, "tlbwi" }, - { MIPS_INS_TLBWR, "tlbwr" }, - { MIPS_INS_TLT, "tlt" }, - { MIPS_INS_TLTI, "tlti" }, - { MIPS_INS_TLTIU, "tltiu" }, - { MIPS_INS_TLTU, "tltu" }, - { MIPS_INS_TNE, "tne" }, - { MIPS_INS_TNEI, "tnei" }, - { MIPS_INS_TRUNC, "trunc" }, - { MIPS_INS_V3MULU, "v3mulu" }, - { MIPS_INS_VMM0, "vmm0" }, - { MIPS_INS_VMULU, "vmulu" }, - { MIPS_INS_VSHF, "vshf" }, - { MIPS_INS_WAIT, "wait" }, - { MIPS_INS_WRDSP, "wrdsp" }, - { MIPS_INS_WSBH, "wsbh" }, - { MIPS_INS_XOR, "xor" }, - { MIPS_INS_XOR16, "xor16" }, - { MIPS_INS_XORI, "xori" }, + {MIPS_INS_INVALID, NULL}, - // alias instructions - { MIPS_INS_NOP, "nop" }, - { MIPS_INS_NEGU, "negu" }, + {MIPS_INS_ABSQ_S, "absq_s"}, + {MIPS_INS_ADD, "add"}, + {MIPS_INS_ADDIUPC, "addiupc"}, + {MIPS_INS_ADDIUR1SP, "addiur1sp"}, + {MIPS_INS_ADDIUR2, "addiur2"}, + {MIPS_INS_ADDIUS5, "addius5"}, + {MIPS_INS_ADDIUSP, "addiusp"}, + {MIPS_INS_ADDQH, "addqh"}, + {MIPS_INS_ADDQH_R, "addqh_r"}, + {MIPS_INS_ADDQ, "addq"}, + {MIPS_INS_ADDQ_S, "addq_s"}, + {MIPS_INS_ADDSC, "addsc"}, + {MIPS_INS_ADDS_A, "adds_a"}, + {MIPS_INS_ADDS_S, "adds_s"}, + {MIPS_INS_ADDS_U, "adds_u"}, + {MIPS_INS_ADDU16, "addu16"}, + {MIPS_INS_ADDUH, "adduh"}, + {MIPS_INS_ADDUH_R, "adduh_r"}, + {MIPS_INS_ADDU, "addu"}, + {MIPS_INS_ADDU_S, "addu_s"}, + {MIPS_INS_ADDVI, "addvi"}, + {MIPS_INS_ADDV, "addv"}, + {MIPS_INS_ADDWC, "addwc"}, + {MIPS_INS_ADD_A, "add_a"}, + {MIPS_INS_ADDI, "addi"}, + {MIPS_INS_ADDIU, "addiu"}, + {MIPS_INS_ALIGN, "align"}, + {MIPS_INS_ALUIPC, "aluipc"}, + {MIPS_INS_AND, "and"}, + {MIPS_INS_AND16, "and16"}, + {MIPS_INS_ANDI16, "andi16"}, + {MIPS_INS_ANDI, "andi"}, + {MIPS_INS_APPEND, "append"}, + {MIPS_INS_ASUB_S, "asub_s"}, + {MIPS_INS_ASUB_U, "asub_u"}, + {MIPS_INS_AUI, "aui"}, + {MIPS_INS_AUIPC, "auipc"}, + {MIPS_INS_AVER_S, "aver_s"}, + {MIPS_INS_AVER_U, "aver_u"}, + {MIPS_INS_AVE_S, "ave_s"}, + {MIPS_INS_AVE_U, "ave_u"}, + {MIPS_INS_B16, "b16"}, + {MIPS_INS_BADDU, "baddu"}, + {MIPS_INS_BAL, "bal"}, + {MIPS_INS_BALC, "balc"}, + {MIPS_INS_BALIGN, "balign"}, + {MIPS_INS_BBIT0, "bbit0"}, + {MIPS_INS_BBIT032, "bbit032"}, + {MIPS_INS_BBIT1, "bbit1"}, + {MIPS_INS_BBIT132, "bbit132"}, + {MIPS_INS_BC, "bc"}, + {MIPS_INS_BC1EQZ, "bc1eqz"}, + {MIPS_INS_BC1F, "bc1f"}, + {MIPS_INS_BC1FL, "bc1fl"}, + {MIPS_INS_BC1NEZ, "bc1nez"}, + {MIPS_INS_BC1T, "bc1t"}, + {MIPS_INS_BC1TL, "bc1tl"}, + {MIPS_INS_BC2EQZ, "bc2eqz"}, + {MIPS_INS_BC2NEZ, "bc2nez"}, + {MIPS_INS_BCLRI, "bclri"}, + {MIPS_INS_BCLR, "bclr"}, + {MIPS_INS_BEQ, "beq"}, + {MIPS_INS_BEQC, "beqc"}, + {MIPS_INS_BEQL, "beql"}, + {MIPS_INS_BEQZ16, "beqz16"}, + {MIPS_INS_BEQZALC, "beqzalc"}, + {MIPS_INS_BEQZC, "beqzc"}, + {MIPS_INS_BGEC, "bgec"}, + {MIPS_INS_BGEUC, "bgeuc"}, + {MIPS_INS_BGEZ, "bgez"}, + {MIPS_INS_BGEZAL, "bgezal"}, + {MIPS_INS_BGEZALC, "bgezalc"}, + {MIPS_INS_BGEZALL, "bgezall"}, + {MIPS_INS_BGEZALS, "bgezals"}, + {MIPS_INS_BGEZC, "bgezc"}, + {MIPS_INS_BGEZL, "bgezl"}, + {MIPS_INS_BGTZ, "bgtz"}, + {MIPS_INS_BGTZALC, "bgtzalc"}, + {MIPS_INS_BGTZC, "bgtzc"}, + {MIPS_INS_BGTZL, "bgtzl"}, + {MIPS_INS_BINSLI, "binsli"}, + {MIPS_INS_BINSL, "binsl"}, + {MIPS_INS_BINSRI, "binsri"}, + {MIPS_INS_BINSR, "binsr"}, + {MIPS_INS_BITREV, "bitrev"}, + {MIPS_INS_BITSWAP, "bitswap"}, + {MIPS_INS_BLEZ, "blez"}, + {MIPS_INS_BLEZALC, "blezalc"}, + {MIPS_INS_BLEZC, "blezc"}, + {MIPS_INS_BLEZL, "blezl"}, + {MIPS_INS_BLTC, "bltc"}, + {MIPS_INS_BLTUC, "bltuc"}, + {MIPS_INS_BLTZ, "bltz"}, + {MIPS_INS_BLTZAL, "bltzal"}, + {MIPS_INS_BLTZALC, "bltzalc"}, + {MIPS_INS_BLTZALL, "bltzall"}, + {MIPS_INS_BLTZALS, "bltzals"}, + {MIPS_INS_BLTZC, "bltzc"}, + {MIPS_INS_BLTZL, "bltzl"}, + {MIPS_INS_BMNZI, "bmnzi"}, + {MIPS_INS_BMNZ, "bmnz"}, + {MIPS_INS_BMZI, "bmzi"}, + {MIPS_INS_BMZ, "bmz"}, + {MIPS_INS_BNE, "bne"}, + {MIPS_INS_BNEC, "bnec"}, + {MIPS_INS_BNEGI, "bnegi"}, + {MIPS_INS_BNEG, "bneg"}, + {MIPS_INS_BNEL, "bnel"}, + {MIPS_INS_BNEZ16, "bnez16"}, + {MIPS_INS_BNEZALC, "bnezalc"}, + {MIPS_INS_BNEZC, "bnezc"}, + {MIPS_INS_BNVC, "bnvc"}, + {MIPS_INS_BNZ, "bnz"}, + {MIPS_INS_BOVC, "bovc"}, + {MIPS_INS_BPOSGE32, "bposge32"}, + {MIPS_INS_BREAK, "break"}, + {MIPS_INS_BREAK16, "break16"}, + {MIPS_INS_BSELI, "bseli"}, + {MIPS_INS_BSEL, "bsel"}, + {MIPS_INS_BSETI, "bseti"}, + {MIPS_INS_BSET, "bset"}, + {MIPS_INS_BZ, "bz"}, + {MIPS_INS_BEQZ, "beqz"}, + {MIPS_INS_B, "b"}, + {MIPS_INS_BNEZ, "bnez"}, + {MIPS_INS_BTEQZ, "bteqz"}, + {MIPS_INS_BTNEZ, "btnez"}, + {MIPS_INS_CACHE, "cache"}, + {MIPS_INS_CEIL, "ceil"}, + {MIPS_INS_CEQI, "ceqi"}, + {MIPS_INS_CEQ, "ceq"}, + {MIPS_INS_CFC1, "cfc1"}, + {MIPS_INS_CFCMSA, "cfcmsa"}, + {MIPS_INS_CINS, "cins"}, + {MIPS_INS_CINS32, "cins32"}, + {MIPS_INS_CLASS, "class"}, + {MIPS_INS_CLEI_S, "clei_s"}, + {MIPS_INS_CLEI_U, "clei_u"}, + {MIPS_INS_CLE_S, "cle_s"}, + {MIPS_INS_CLE_U, "cle_u"}, + {MIPS_INS_CLO, "clo"}, + {MIPS_INS_CLTI_S, "clti_s"}, + {MIPS_INS_CLTI_U, "clti_u"}, + {MIPS_INS_CLT_S, "clt_s"}, + {MIPS_INS_CLT_U, "clt_u"}, + {MIPS_INS_CLZ, "clz"}, + {MIPS_INS_CMPGDU, "cmpgdu"}, + {MIPS_INS_CMPGU, "cmpgu"}, + {MIPS_INS_CMPU, "cmpu"}, + {MIPS_INS_CMP, "cmp"}, + {MIPS_INS_COPY_S, "copy_s"}, + {MIPS_INS_COPY_U, "copy_u"}, + {MIPS_INS_CTC1, "ctc1"}, + {MIPS_INS_CTCMSA, "ctcmsa"}, + {MIPS_INS_CVT, "cvt"}, + {MIPS_INS_C, "c"}, + {MIPS_INS_CMPI, "cmpi"}, + {MIPS_INS_DADD, "dadd"}, + {MIPS_INS_DADDI, "daddi"}, + {MIPS_INS_DADDIU, "daddiu"}, + {MIPS_INS_DADDU, "daddu"}, + {MIPS_INS_DAHI, "dahi"}, + {MIPS_INS_DALIGN, "dalign"}, + {MIPS_INS_DATI, "dati"}, + {MIPS_INS_DAUI, "daui"}, + {MIPS_INS_DBITSWAP, "dbitswap"}, + {MIPS_INS_DCLO, "dclo"}, + {MIPS_INS_DCLZ, "dclz"}, + {MIPS_INS_DDIV, "ddiv"}, + {MIPS_INS_DDIVU, "ddivu"}, + {MIPS_INS_DERET, "deret"}, + {MIPS_INS_DEXT, "dext"}, + {MIPS_INS_DEXTM, "dextm"}, + {MIPS_INS_DEXTU, "dextu"}, + {MIPS_INS_DI, "di"}, + {MIPS_INS_DINS, "dins"}, + {MIPS_INS_DINSM, "dinsm"}, + {MIPS_INS_DINSU, "dinsu"}, + {MIPS_INS_DIV, "div"}, + {MIPS_INS_DIVU, "divu"}, + {MIPS_INS_DIV_S, "div_s"}, + {MIPS_INS_DIV_U, "div_u"}, + {MIPS_INS_DLSA, "dlsa"}, + {MIPS_INS_DMFC0, "dmfc0"}, + {MIPS_INS_DMFC1, "dmfc1"}, + {MIPS_INS_DMFC2, "dmfc2"}, + {MIPS_INS_DMOD, "dmod"}, + {MIPS_INS_DMODU, "dmodu"}, + {MIPS_INS_DMTC0, "dmtc0"}, + {MIPS_INS_DMTC1, "dmtc1"}, + {MIPS_INS_DMTC2, "dmtc2"}, + {MIPS_INS_DMUH, "dmuh"}, + {MIPS_INS_DMUHU, "dmuhu"}, + {MIPS_INS_DMUL, "dmul"}, + {MIPS_INS_DMULT, "dmult"}, + {MIPS_INS_DMULTU, "dmultu"}, + {MIPS_INS_DMULU, "dmulu"}, + {MIPS_INS_DOTP_S, "dotp_s"}, + {MIPS_INS_DOTP_U, "dotp_u"}, + {MIPS_INS_DPADD_S, "dpadd_s"}, + {MIPS_INS_DPADD_U, "dpadd_u"}, + {MIPS_INS_DPAQX_SA, "dpaqx_sa"}, + {MIPS_INS_DPAQX_S, "dpaqx_s"}, + {MIPS_INS_DPAQ_SA, "dpaq_sa"}, + {MIPS_INS_DPAQ_S, "dpaq_s"}, + {MIPS_INS_DPAU, "dpau"}, + {MIPS_INS_DPAX, "dpax"}, + {MIPS_INS_DPA, "dpa"}, + {MIPS_INS_DPOP, "dpop"}, + {MIPS_INS_DPSQX_SA, "dpsqx_sa"}, + {MIPS_INS_DPSQX_S, "dpsqx_s"}, + {MIPS_INS_DPSQ_SA, "dpsq_sa"}, + {MIPS_INS_DPSQ_S, "dpsq_s"}, + {MIPS_INS_DPSUB_S, "dpsub_s"}, + {MIPS_INS_DPSUB_U, "dpsub_u"}, + {MIPS_INS_DPSU, "dpsu"}, + {MIPS_INS_DPSX, "dpsx"}, + {MIPS_INS_DPS, "dps"}, + {MIPS_INS_DROTR, "drotr"}, + {MIPS_INS_DROTR32, "drotr32"}, + {MIPS_INS_DROTRV, "drotrv"}, + {MIPS_INS_DSBH, "dsbh"}, + {MIPS_INS_DSHD, "dshd"}, + {MIPS_INS_DSLL, "dsll"}, + {MIPS_INS_DSLL32, "dsll32"}, + {MIPS_INS_DSLLV, "dsllv"}, + {MIPS_INS_DSRA, "dsra"}, + {MIPS_INS_DSRA32, "dsra32"}, + {MIPS_INS_DSRAV, "dsrav"}, + {MIPS_INS_DSRL, "dsrl"}, + {MIPS_INS_DSRL32, "dsrl32"}, + {MIPS_INS_DSRLV, "dsrlv"}, + {MIPS_INS_DSUB, "dsub"}, + {MIPS_INS_DSUBU, "dsubu"}, + {MIPS_INS_EHB, "ehb"}, + {MIPS_INS_EI, "ei"}, + {MIPS_INS_ERET, "eret"}, + {MIPS_INS_EXT, "ext"}, + {MIPS_INS_EXTP, "extp"}, + {MIPS_INS_EXTPDP, "extpdp"}, + {MIPS_INS_EXTPDPV, "extpdpv"}, + {MIPS_INS_EXTPV, "extpv"}, + {MIPS_INS_EXTRV_RS, "extrv_rs"}, + {MIPS_INS_EXTRV_R, "extrv_r"}, + {MIPS_INS_EXTRV_S, "extrv_s"}, + {MIPS_INS_EXTRV, "extrv"}, + {MIPS_INS_EXTR_RS, "extr_rs"}, + {MIPS_INS_EXTR_R, "extr_r"}, + {MIPS_INS_EXTR_S, "extr_s"}, + {MIPS_INS_EXTR, "extr"}, + {MIPS_INS_EXTS, "exts"}, + {MIPS_INS_EXTS32, "exts32"}, + {MIPS_INS_ABS, "abs"}, + {MIPS_INS_FADD, "fadd"}, + {MIPS_INS_FCAF, "fcaf"}, + {MIPS_INS_FCEQ, "fceq"}, + {MIPS_INS_FCLASS, "fclass"}, + {MIPS_INS_FCLE, "fcle"}, + {MIPS_INS_FCLT, "fclt"}, + {MIPS_INS_FCNE, "fcne"}, + {MIPS_INS_FCOR, "fcor"}, + {MIPS_INS_FCUEQ, "fcueq"}, + {MIPS_INS_FCULE, "fcule"}, + {MIPS_INS_FCULT, "fcult"}, + {MIPS_INS_FCUNE, "fcune"}, + {MIPS_INS_FCUN, "fcun"}, + {MIPS_INS_FDIV, "fdiv"}, + {MIPS_INS_FEXDO, "fexdo"}, + {MIPS_INS_FEXP2, "fexp2"}, + {MIPS_INS_FEXUPL, "fexupl"}, + {MIPS_INS_FEXUPR, "fexupr"}, + {MIPS_INS_FFINT_S, "ffint_s"}, + {MIPS_INS_FFINT_U, "ffint_u"}, + {MIPS_INS_FFQL, "ffql"}, + {MIPS_INS_FFQR, "ffqr"}, + {MIPS_INS_FILL, "fill"}, + {MIPS_INS_FLOG2, "flog2"}, + {MIPS_INS_FLOOR, "floor"}, + {MIPS_INS_FMADD, "fmadd"}, + {MIPS_INS_FMAX_A, "fmax_a"}, + {MIPS_INS_FMAX, "fmax"}, + {MIPS_INS_FMIN_A, "fmin_a"}, + {MIPS_INS_FMIN, "fmin"}, + {MIPS_INS_MOV, "mov"}, + {MIPS_INS_FMSUB, "fmsub"}, + {MIPS_INS_FMUL, "fmul"}, + {MIPS_INS_MUL, "mul"}, + {MIPS_INS_NEG, "neg"}, + {MIPS_INS_FRCP, "frcp"}, + {MIPS_INS_FRINT, "frint"}, + {MIPS_INS_FRSQRT, "frsqrt"}, + {MIPS_INS_FSAF, "fsaf"}, + {MIPS_INS_FSEQ, "fseq"}, + {MIPS_INS_FSLE, "fsle"}, + {MIPS_INS_FSLT, "fslt"}, + {MIPS_INS_FSNE, "fsne"}, + {MIPS_INS_FSOR, "fsor"}, + {MIPS_INS_FSQRT, "fsqrt"}, + {MIPS_INS_SQRT, "sqrt"}, + {MIPS_INS_FSUB, "fsub"}, + {MIPS_INS_SUB, "sub"}, + {MIPS_INS_FSUEQ, "fsueq"}, + {MIPS_INS_FSULE, "fsule"}, + {MIPS_INS_FSULT, "fsult"}, + {MIPS_INS_FSUNE, "fsune"}, + {MIPS_INS_FSUN, "fsun"}, + {MIPS_INS_FTINT_S, "ftint_s"}, + {MIPS_INS_FTINT_U, "ftint_u"}, + {MIPS_INS_FTQ, "ftq"}, + {MIPS_INS_FTRUNC_S, "ftrunc_s"}, + {MIPS_INS_FTRUNC_U, "ftrunc_u"}, + {MIPS_INS_HADD_S, "hadd_s"}, + {MIPS_INS_HADD_U, "hadd_u"}, + {MIPS_INS_HSUB_S, "hsub_s"}, + {MIPS_INS_HSUB_U, "hsub_u"}, + {MIPS_INS_ILVEV, "ilvev"}, + {MIPS_INS_ILVL, "ilvl"}, + {MIPS_INS_ILVOD, "ilvod"}, + {MIPS_INS_ILVR, "ilvr"}, + {MIPS_INS_INS, "ins"}, + {MIPS_INS_INSERT, "insert"}, + {MIPS_INS_INSV, "insv"}, + {MIPS_INS_INSVE, "insve"}, + {MIPS_INS_J, "j"}, + {MIPS_INS_JAL, "jal"}, + {MIPS_INS_JALR, "jalr"}, + {MIPS_INS_JALRS16, "jalrs16"}, + {MIPS_INS_JALRS, "jalrs"}, + {MIPS_INS_JALS, "jals"}, + {MIPS_INS_JALX, "jalx"}, + {MIPS_INS_JIALC, "jialc"}, + {MIPS_INS_JIC, "jic"}, + {MIPS_INS_JR, "jr"}, + {MIPS_INS_JR16, "jr16"}, + {MIPS_INS_JRADDIUSP, "jraddiusp"}, + {MIPS_INS_JRC, "jrc"}, + {MIPS_INS_JALRC, "jalrc"}, + {MIPS_INS_LB, "lb"}, + {MIPS_INS_LBU16, "lbu16"}, + {MIPS_INS_LBUX, "lbux"}, + {MIPS_INS_LBU, "lbu"}, + {MIPS_INS_LD, "ld"}, + {MIPS_INS_LDC1, "ldc1"}, + {MIPS_INS_LDC2, "ldc2"}, + {MIPS_INS_LDC3, "ldc3"}, + {MIPS_INS_LDI, "ldi"}, + {MIPS_INS_LDL, "ldl"}, + {MIPS_INS_LDPC, "ldpc"}, + {MIPS_INS_LDR, "ldr"}, + {MIPS_INS_LDXC1, "ldxc1"}, + {MIPS_INS_LH, "lh"}, + {MIPS_INS_LHU16, "lhu16"}, + {MIPS_INS_LHX, "lhx"}, + {MIPS_INS_LHU, "lhu"}, + {MIPS_INS_LI16, "li16"}, + {MIPS_INS_LL, "ll"}, + {MIPS_INS_LLD, "lld"}, + {MIPS_INS_LSA, "lsa"}, + {MIPS_INS_LUXC1, "luxc1"}, + {MIPS_INS_LUI, "lui"}, + {MIPS_INS_LW, "lw"}, + {MIPS_INS_LW16, "lw16"}, + {MIPS_INS_LWC1, "lwc1"}, + {MIPS_INS_LWC2, "lwc2"}, + {MIPS_INS_LWC3, "lwc3"}, + {MIPS_INS_LWL, "lwl"}, + {MIPS_INS_LWM16, "lwm16"}, + {MIPS_INS_LWM32, "lwm32"}, + {MIPS_INS_LWPC, "lwpc"}, + {MIPS_INS_LWP, "lwp"}, + {MIPS_INS_LWR, "lwr"}, + {MIPS_INS_LWUPC, "lwupc"}, + {MIPS_INS_LWU, "lwu"}, + {MIPS_INS_LWX, "lwx"}, + {MIPS_INS_LWXC1, "lwxc1"}, + {MIPS_INS_LWXS, "lwxs"}, + {MIPS_INS_LI, "li"}, + {MIPS_INS_MADD, "madd"}, + {MIPS_INS_MADDF, "maddf"}, + {MIPS_INS_MADDR_Q, "maddr_q"}, + {MIPS_INS_MADDU, "maddu"}, + {MIPS_INS_MADDV, "maddv"}, + {MIPS_INS_MADD_Q, "madd_q"}, + {MIPS_INS_MAQ_SA, "maq_sa"}, + {MIPS_INS_MAQ_S, "maq_s"}, + {MIPS_INS_MAXA, "maxa"}, + {MIPS_INS_MAXI_S, "maxi_s"}, + {MIPS_INS_MAXI_U, "maxi_u"}, + {MIPS_INS_MAX_A, "max_a"}, + {MIPS_INS_MAX, "max"}, + {MIPS_INS_MAX_S, "max_s"}, + {MIPS_INS_MAX_U, "max_u"}, + {MIPS_INS_MFC0, "mfc0"}, + {MIPS_INS_MFC1, "mfc1"}, + {MIPS_INS_MFC2, "mfc2"}, + {MIPS_INS_MFHC1, "mfhc1"}, + {MIPS_INS_MFHI, "mfhi"}, + {MIPS_INS_MFLO, "mflo"}, + {MIPS_INS_MINA, "mina"}, + {MIPS_INS_MINI_S, "mini_s"}, + {MIPS_INS_MINI_U, "mini_u"}, + {MIPS_INS_MIN_A, "min_a"}, + {MIPS_INS_MIN, "min"}, + {MIPS_INS_MIN_S, "min_s"}, + {MIPS_INS_MIN_U, "min_u"}, + {MIPS_INS_MOD, "mod"}, + {MIPS_INS_MODSUB, "modsub"}, + {MIPS_INS_MODU, "modu"}, + {MIPS_INS_MOD_S, "mod_s"}, + {MIPS_INS_MOD_U, "mod_u"}, + {MIPS_INS_MOVE, "move"}, + {MIPS_INS_MOVEP, "movep"}, + {MIPS_INS_MOVF, "movf"}, + {MIPS_INS_MOVN, "movn"}, + {MIPS_INS_MOVT, "movt"}, + {MIPS_INS_MOVZ, "movz"}, + {MIPS_INS_MSUB, "msub"}, + {MIPS_INS_MSUBF, "msubf"}, + {MIPS_INS_MSUBR_Q, "msubr_q"}, + {MIPS_INS_MSUBU, "msubu"}, + {MIPS_INS_MSUBV, "msubv"}, + {MIPS_INS_MSUB_Q, "msub_q"}, + {MIPS_INS_MTC0, "mtc0"}, + {MIPS_INS_MTC1, "mtc1"}, + {MIPS_INS_MTC2, "mtc2"}, + {MIPS_INS_MTHC1, "mthc1"}, + {MIPS_INS_MTHI, "mthi"}, + {MIPS_INS_MTHLIP, "mthlip"}, + {MIPS_INS_MTLO, "mtlo"}, + {MIPS_INS_MTM0, "mtm0"}, + {MIPS_INS_MTM1, "mtm1"}, + {MIPS_INS_MTM2, "mtm2"}, + {MIPS_INS_MTP0, "mtp0"}, + {MIPS_INS_MTP1, "mtp1"}, + {MIPS_INS_MTP2, "mtp2"}, + {MIPS_INS_MUH, "muh"}, + {MIPS_INS_MUHU, "muhu"}, + {MIPS_INS_MULEQ_S, "muleq_s"}, + {MIPS_INS_MULEU_S, "muleu_s"}, + {MIPS_INS_MULQ_RS, "mulq_rs"}, + {MIPS_INS_MULQ_S, "mulq_s"}, + {MIPS_INS_MULR_Q, "mulr_q"}, + {MIPS_INS_MULSAQ_S, "mulsaq_s"}, + {MIPS_INS_MULSA, "mulsa"}, + {MIPS_INS_MULT, "mult"}, + {MIPS_INS_MULTU, "multu"}, + {MIPS_INS_MULU, "mulu"}, + {MIPS_INS_MULV, "mulv"}, + {MIPS_INS_MUL_Q, "mul_q"}, + {MIPS_INS_MUL_S, "mul_s"}, + {MIPS_INS_NLOC, "nloc"}, + {MIPS_INS_NLZC, "nlzc"}, + {MIPS_INS_NMADD, "nmadd"}, + {MIPS_INS_NMSUB, "nmsub"}, + {MIPS_INS_NOR, "nor"}, + {MIPS_INS_NORI, "nori"}, + {MIPS_INS_NOT16, "not16"}, + {MIPS_INS_NOT, "not"}, + {MIPS_INS_OR, "or"}, + {MIPS_INS_OR16, "or16"}, + {MIPS_INS_ORI, "ori"}, + {MIPS_INS_PACKRL, "packrl"}, + {MIPS_INS_PAUSE, "pause"}, + {MIPS_INS_PCKEV, "pckev"}, + {MIPS_INS_PCKOD, "pckod"}, + {MIPS_INS_PCNT, "pcnt"}, + {MIPS_INS_PICK, "pick"}, + {MIPS_INS_POP, "pop"}, + {MIPS_INS_PRECEQU, "precequ"}, + {MIPS_INS_PRECEQ, "preceq"}, + {MIPS_INS_PRECEU, "preceu"}, + {MIPS_INS_PRECRQU_S, "precrqu_s"}, + {MIPS_INS_PRECRQ, "precrq"}, + {MIPS_INS_PRECRQ_RS, "precrq_rs"}, + {MIPS_INS_PRECR, "precr"}, + {MIPS_INS_PRECR_SRA, "precr_sra"}, + {MIPS_INS_PRECR_SRA_R, "precr_sra_r"}, + {MIPS_INS_PREF, "pref"}, + {MIPS_INS_PREPEND, "prepend"}, + {MIPS_INS_RADDU, "raddu"}, + {MIPS_INS_RDDSP, "rddsp"}, + {MIPS_INS_RDHWR, "rdhwr"}, + {MIPS_INS_REPLV, "replv"}, + {MIPS_INS_REPL, "repl"}, + {MIPS_INS_RINT, "rint"}, + {MIPS_INS_ROTR, "rotr"}, + {MIPS_INS_ROTRV, "rotrv"}, + {MIPS_INS_ROUND, "round"}, + {MIPS_INS_SAT_S, "sat_s"}, + {MIPS_INS_SAT_U, "sat_u"}, + {MIPS_INS_SB, "sb"}, + {MIPS_INS_SB16, "sb16"}, + {MIPS_INS_SC, "sc"}, + {MIPS_INS_SCD, "scd"}, + {MIPS_INS_SD, "sd"}, + {MIPS_INS_SDBBP, "sdbbp"}, + {MIPS_INS_SDBBP16, "sdbbp16"}, + {MIPS_INS_SDC1, "sdc1"}, + {MIPS_INS_SDC2, "sdc2"}, + {MIPS_INS_SDC3, "sdc3"}, + {MIPS_INS_SDL, "sdl"}, + {MIPS_INS_SDR, "sdr"}, + {MIPS_INS_SDXC1, "sdxc1"}, + {MIPS_INS_SEB, "seb"}, + {MIPS_INS_SEH, "seh"}, + {MIPS_INS_SELEQZ, "seleqz"}, + {MIPS_INS_SELNEZ, "selnez"}, + {MIPS_INS_SEL, "sel"}, + {MIPS_INS_SEQ, "seq"}, + {MIPS_INS_SEQI, "seqi"}, + {MIPS_INS_SH, "sh"}, + {MIPS_INS_SH16, "sh16"}, + {MIPS_INS_SHF, "shf"}, + {MIPS_INS_SHILO, "shilo"}, + {MIPS_INS_SHILOV, "shilov"}, + {MIPS_INS_SHLLV, "shllv"}, + {MIPS_INS_SHLLV_S, "shllv_s"}, + {MIPS_INS_SHLL, "shll"}, + {MIPS_INS_SHLL_S, "shll_s"}, + {MIPS_INS_SHRAV, "shrav"}, + {MIPS_INS_SHRAV_R, "shrav_r"}, + {MIPS_INS_SHRA, "shra"}, + {MIPS_INS_SHRA_R, "shra_r"}, + {MIPS_INS_SHRLV, "shrlv"}, + {MIPS_INS_SHRL, "shrl"}, + {MIPS_INS_SLDI, "sldi"}, + {MIPS_INS_SLD, "sld"}, + {MIPS_INS_SLL, "sll"}, + {MIPS_INS_SLL16, "sll16"}, + {MIPS_INS_SLLI, "slli"}, + {MIPS_INS_SLLV, "sllv"}, + {MIPS_INS_SLT, "slt"}, + {MIPS_INS_SLTI, "slti"}, + {MIPS_INS_SLTIU, "sltiu"}, + {MIPS_INS_SLTU, "sltu"}, + {MIPS_INS_SNE, "sne"}, + {MIPS_INS_SNEI, "snei"}, + {MIPS_INS_SPLATI, "splati"}, + {MIPS_INS_SPLAT, "splat"}, + {MIPS_INS_SRA, "sra"}, + {MIPS_INS_SRAI, "srai"}, + {MIPS_INS_SRARI, "srari"}, + {MIPS_INS_SRAR, "srar"}, + {MIPS_INS_SRAV, "srav"}, + {MIPS_INS_SRL, "srl"}, + {MIPS_INS_SRL16, "srl16"}, + {MIPS_INS_SRLI, "srli"}, + {MIPS_INS_SRLRI, "srlri"}, + {MIPS_INS_SRLR, "srlr"}, + {MIPS_INS_SRLV, "srlv"}, + {MIPS_INS_SSNOP, "ssnop"}, + {MIPS_INS_ST, "st"}, + {MIPS_INS_SUBQH, "subqh"}, + {MIPS_INS_SUBQH_R, "subqh_r"}, + {MIPS_INS_SUBQ, "subq"}, + {MIPS_INS_SUBQ_S, "subq_s"}, + {MIPS_INS_SUBSUS_U, "subsus_u"}, + {MIPS_INS_SUBSUU_S, "subsuu_s"}, + {MIPS_INS_SUBS_S, "subs_s"}, + {MIPS_INS_SUBS_U, "subs_u"}, + {MIPS_INS_SUBU16, "subu16"}, + {MIPS_INS_SUBUH, "subuh"}, + {MIPS_INS_SUBUH_R, "subuh_r"}, + {MIPS_INS_SUBU, "subu"}, + {MIPS_INS_SUBU_S, "subu_s"}, + {MIPS_INS_SUBVI, "subvi"}, + {MIPS_INS_SUBV, "subv"}, + {MIPS_INS_SUXC1, "suxc1"}, + {MIPS_INS_SW, "sw"}, + {MIPS_INS_SW16, "sw16"}, + {MIPS_INS_SWC1, "swc1"}, + {MIPS_INS_SWC2, "swc2"}, + {MIPS_INS_SWC3, "swc3"}, + {MIPS_INS_SWL, "swl"}, + {MIPS_INS_SWM16, "swm16"}, + {MIPS_INS_SWM32, "swm32"}, + {MIPS_INS_SWP, "swp"}, + {MIPS_INS_SWR, "swr"}, + {MIPS_INS_SWXC1, "swxc1"}, + {MIPS_INS_SYNC, "sync"}, + {MIPS_INS_SYNCI, "synci"}, + {MIPS_INS_SYSCALL, "syscall"}, + {MIPS_INS_TEQ, "teq"}, + {MIPS_INS_TEQI, "teqi"}, + {MIPS_INS_TGE, "tge"}, + {MIPS_INS_TGEI, "tgei"}, + {MIPS_INS_TGEIU, "tgeiu"}, + {MIPS_INS_TGEU, "tgeu"}, + {MIPS_INS_TLBP, "tlbp"}, + {MIPS_INS_TLBR, "tlbr"}, + {MIPS_INS_TLBWI, "tlbwi"}, + {MIPS_INS_TLBWR, "tlbwr"}, + {MIPS_INS_TLT, "tlt"}, + {MIPS_INS_TLTI, "tlti"}, + {MIPS_INS_TLTIU, "tltiu"}, + {MIPS_INS_TLTU, "tltu"}, + {MIPS_INS_TNE, "tne"}, + {MIPS_INS_TNEI, "tnei"}, + {MIPS_INS_TRUNC, "trunc"}, + {MIPS_INS_V3MULU, "v3mulu"}, + {MIPS_INS_VMM0, "vmm0"}, + {MIPS_INS_VMULU, "vmulu"}, + {MIPS_INS_VSHF, "vshf"}, + {MIPS_INS_WAIT, "wait"}, + {MIPS_INS_WRDSP, "wrdsp"}, + {MIPS_INS_WSBH, "wsbh"}, + {MIPS_INS_XOR, "xor"}, + {MIPS_INS_XOR16, "xor16"}, + {MIPS_INS_XORI, "xori"}, - { MIPS_INS_JALR_HB, "jalr.hb" }, - { MIPS_INS_JR_HB, "jr.hb" }, + // alias instructions + {MIPS_INS_NOP, "nop"}, + {MIPS_INS_NEGU, "negu"}, }; -const char *Mips_insn_name(csh handle, unsigned int id) -{ +const char *Mips_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - if (id >= MIPS_INS_ENDING) - return NULL; + if (id >= MIPS_INS_ENDING) + return NULL; - return insn_name_maps[id].name; + return insn_name_maps[id].name; #else - return NULL; + return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { - // generic groups - { MIPS_GRP_INVALID, NULL }, - { MIPS_GRP_JUMP, "jump" }, - { MIPS_GRP_CALL, "call" }, - { MIPS_GRP_RET, "ret" }, - { MIPS_GRP_INT, "int" }, - { MIPS_GRP_IRET, "iret" }, - { MIPS_GRP_PRIVILEGE, "privileged" }, - { MIPS_GRP_BRANCH_RELATIVE, "branch_relative" }, + // generic groups + {MIPS_GRP_INVALID, NULL}, + {MIPS_GRP_JUMP, "jump"}, + {MIPS_GRP_CALL, "call"}, + {MIPS_GRP_RET, "ret"}, + {MIPS_GRP_INT, "int"}, + {MIPS_GRP_IRET, "iret"}, + {MIPS_GRP_PRIVILEGE, "privileged"}, + {MIPS_GRP_BRANCH_RELATIVE, "branch_relative"}, - // architecture-specific groups - { MIPS_GRP_BITCOUNT, "bitcount" }, - { MIPS_GRP_DSP, "dsp" }, - { MIPS_GRP_DSPR2, "dspr2" }, - { MIPS_GRP_FPIDX, "fpidx" }, - { MIPS_GRP_MSA, "msa" }, - { MIPS_GRP_MIPS32R2, "mips32r2" }, - { MIPS_GRP_MIPS64, "mips64" }, - { MIPS_GRP_MIPS64R2, "mips64r2" }, - { MIPS_GRP_SEINREG, "seinreg" }, - { MIPS_GRP_STDENC, "stdenc" }, - { MIPS_GRP_SWAP, "swap" }, - { MIPS_GRP_MICROMIPS, "micromips" }, - { MIPS_GRP_MIPS16MODE, "mips16mode" }, - { MIPS_GRP_FP64BIT, "fp64bit" }, - { MIPS_GRP_NONANSFPMATH, "nonansfpmath" }, - { MIPS_GRP_NOTFP64BIT, "notfp64bit" }, - { MIPS_GRP_NOTINMICROMIPS, "notinmicromips" }, - { MIPS_GRP_NOTNACL, "notnacl" }, + // architecture-specific groups + {MIPS_GRP_BITCOUNT, "bitcount"}, + {MIPS_GRP_DSP, "dsp"}, + {MIPS_GRP_DSPR2, "dspr2"}, + {MIPS_GRP_FPIDX, "fpidx"}, + {MIPS_GRP_MSA, "msa"}, + {MIPS_GRP_MIPS32R2, "mips32r2"}, + {MIPS_GRP_MIPS64, "mips64"}, + {MIPS_GRP_MIPS64R2, "mips64r2"}, + {MIPS_GRP_SEINREG, "seinreg"}, + {MIPS_GRP_STDENC, "stdenc"}, + {MIPS_GRP_SWAP, "swap"}, + {MIPS_GRP_MICROMIPS, "micromips"}, + {MIPS_GRP_MIPS16MODE, "mips16mode"}, + {MIPS_GRP_FP64BIT, "fp64bit"}, + {MIPS_GRP_NONANSFPMATH, "nonansfpmath"}, + {MIPS_GRP_NOTFP64BIT, "notfp64bit"}, + {MIPS_GRP_NOTINMICROMIPS, "notinmicromips"}, + {MIPS_GRP_NOTNACL, "notnacl"}, - { MIPS_GRP_NOTMIPS32R6, "notmips32r6" }, - { MIPS_GRP_NOTMIPS64R6, "notmips64r6" }, - { MIPS_GRP_CNMIPS, "cnmips" }, + {MIPS_GRP_NOTMIPS32R6, "notmips32r6"}, + {MIPS_GRP_NOTMIPS64R6, "notmips64r6"}, + {MIPS_GRP_CNMIPS, "cnmips"}, - { MIPS_GRP_MIPS32, "mips32" }, - { MIPS_GRP_MIPS32R6, "mips32r6" }, - { MIPS_GRP_MIPS64R6, "mips64r6" }, + {MIPS_GRP_MIPS32, "mips32"}, + {MIPS_GRP_MIPS32R6, "mips32r6"}, + {MIPS_GRP_MIPS64R6, "mips64r6"}, - { MIPS_GRP_MIPS2, "mips2" }, - { MIPS_GRP_MIPS3, "mips3" }, - { MIPS_GRP_MIPS3_32, "mips3_32"}, - { MIPS_GRP_MIPS3_32R2, "mips3_32r2" }, + {MIPS_GRP_MIPS2, "mips2"}, + {MIPS_GRP_MIPS3, "mips3"}, + {MIPS_GRP_MIPS3_32, "mips3_32"}, + {MIPS_GRP_MIPS3_32R2, "mips3_32r2"}, - { MIPS_GRP_MIPS4_32, "mips4_32" }, - { MIPS_GRP_MIPS4_32R2, "mips4_32r2" }, - { MIPS_GRP_MIPS5_32R2, "mips5_32r2" }, + {MIPS_GRP_MIPS4_32, "mips4_32"}, + {MIPS_GRP_MIPS4_32R2, "mips4_32r2"}, + {MIPS_GRP_MIPS5_32R2, "mips5_32r2"}, - { MIPS_GRP_GP32BIT, "gp32bit" }, - { MIPS_GRP_GP64BIT, "gp64bit" }, + {MIPS_GRP_GP32BIT, "gp32bit"}, + {MIPS_GRP_GP64BIT, "gp64bit"}, }; #endif -const char *Mips_group_name(csh handle, unsigned int id) -{ +const char *Mips_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else - return NULL; + return NULL; #endif } // map instruction name to public instruction ID -mips_reg Mips_map_insn(const char *name) -{ - // handle special alias first - unsigned int i; +mips_reg Mips_map_insn(const char *name) { + // handle special alias first + unsigned int i; - // NOTE: skip first NULL name in insn_name_maps - i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); + // NOTE: skip first NULL name in insn_name_maps + i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); - return (i != -1)? i : MIPS_REG_INVALID; + return (i != -1) ? i : MIPS_REG_INVALID; } // map internal raw register to 'public' register -mips_reg Mips_map_register(unsigned int r) -{ - // for some reasons different Mips modes can map different register number to - // the same Mips register. this function handles the issue for exposing Mips - // operands by mapping internal registers to 'public' register. - static const unsigned int map[] = { 0, - MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG, - MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2, - MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5, - MIPS_REG_3, MIPS_REG_7, MIPS_REG_PC, MIPS_REG_RA, MIPS_REG_SP, - MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, - MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT, - MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4, - MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1, - MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, - MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1, - MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, - MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, - MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, - MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, - MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, - MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, - MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, - MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, - MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, - MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, - MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4, - MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14, - MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24, - MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21, - MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, - MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, - MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, - MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, - MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, - MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, - MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0, - MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5, - MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, - MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, - MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, - MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, - MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, - MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, - MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP, - MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, - MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, - MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, - MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, - MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, - MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, - MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1, - MIPS_REG_AC2, MIPS_REG_AC3, 0, 0, 0, - 0, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, - MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, - MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, - MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, - MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, - MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0, - MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, - MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, - MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, - MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7, - MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, - MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, - MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1, - MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6, - MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11, - MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16, - MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21, - MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26, - MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31, - MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, - MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, - MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, - MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, - MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, - MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, - MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, - MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI, - MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1, - MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, - MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, - MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, - MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1 - }; +mips_reg Mips_map_register(unsigned int r) { + // for some reasons different Mips modes can map different register number to + // the same Mips register. this function handles the issue for exposing Mips + // operands by mapping internal registers to 'public' register. + static const unsigned int map_outer[] = { + 0, + Mips_AT, + Mips_DSPCCond, + Mips_DSPCarry, + Mips_DSPEFI, + Mips_DSPOutFlag, + Mips_DSPPos, + Mips_DSPSCount, + Mips_FP, + Mips_GP, + Mips_MSAAccess, + Mips_MSACSR, + Mips_MSAIR, + Mips_MSAMap, + Mips_MSAModify, + Mips_MSARequest, + Mips_MSASave, + Mips_MSAUnmap, + Mips_PC, + Mips_RA, + Mips_SP, + Mips_ZERO, + Mips_A0, + Mips_A1, + Mips_A2, + Mips_A3, + Mips_AC0, + Mips_AC1, + Mips_AC2, + Mips_AC3, + Mips_AT_64, + Mips_FCC0, + Mips_FCC1, + Mips_FCC2, + Mips_FCC3, + Mips_FCC4, + Mips_FCC5, + Mips_FCC6, + Mips_FCC7, + Mips_COP20, + Mips_COP21, + Mips_COP22, + Mips_COP23, + Mips_COP24, + Mips_COP25, + Mips_COP26, + Mips_COP27, + Mips_COP28, + Mips_COP29, + Mips_COP30, + Mips_COP31, + Mips_COP32, + Mips_COP33, + Mips_COP34, + Mips_COP35, + Mips_COP36, + Mips_COP37, + Mips_COP38, + Mips_COP39, + Mips_COP210, + Mips_COP211, + Mips_COP212, + Mips_COP213, + Mips_COP214, + Mips_COP215, + Mips_COP216, + Mips_COP217, + Mips_COP218, + Mips_COP219, + Mips_COP220, + Mips_COP221, + Mips_COP222, + Mips_COP223, + Mips_COP224, + Mips_COP225, + Mips_COP226, + Mips_COP227, + Mips_COP228, + Mips_COP229, + Mips_COP230, + Mips_COP231, + Mips_COP310, + Mips_COP311, + Mips_COP312, + Mips_COP313, + Mips_COP314, + Mips_COP315, + Mips_COP316, + Mips_COP317, + Mips_COP318, + Mips_COP319, + Mips_COP320, + Mips_COP321, + Mips_COP322, + Mips_COP323, + Mips_COP324, + Mips_COP325, + Mips_COP326, + Mips_COP327, + Mips_COP328, + Mips_COP329, + Mips_COP330, + Mips_COP331, + Mips_D0, + Mips_D1, + Mips_D2, + Mips_D3, + Mips_D4, + Mips_D5, + Mips_D6, + Mips_D7, + Mips_D8, + Mips_D9, + Mips_D10, + Mips_D11, + Mips_D12, + Mips_D13, + Mips_D14, + Mips_D15, + Mips_DSPOutFlag20, + Mips_DSPOutFlag21, + Mips_DSPOutFlag22, + Mips_DSPOutFlag23, + Mips_F0, + Mips_F1, + Mips_F2, + Mips_F3, + Mips_F4, + Mips_F5, + Mips_F6, + Mips_F7, + Mips_F8, + Mips_F9, + Mips_F10, + Mips_F11, + Mips_F12, + Mips_F13, + Mips_F14, + Mips_F15, + Mips_F16, + Mips_F17, + Mips_F18, + Mips_F19, + Mips_F20, + Mips_F21, + Mips_F22, + Mips_F23, + Mips_F24, + Mips_F25, + Mips_F26, + Mips_F27, + Mips_F28, + Mips_F29, + Mips_F30, + Mips_F31, + Mips_FCC0, + Mips_FCC1, + Mips_FCC2, + Mips_FCC3, + Mips_FCC4, + Mips_FCC5, + Mips_FCC6, + Mips_FCC7, + Mips_FCR0, + Mips_FCR1, + Mips_FCR2, + Mips_FCR3, + Mips_FCR4, + Mips_FCR5, + Mips_FCR6, + Mips_FCR7, + Mips_FCR8, + Mips_FCR9, + Mips_FCR10, + Mips_FCR11, + Mips_FCR12, + Mips_FCR13, + Mips_FCR14, + Mips_FCR15, + Mips_FCR16, + Mips_FCR17, + Mips_FCR18, + Mips_FCR19, + Mips_FCR20, + Mips_FCR21, + Mips_FCR22, + Mips_FCR23, + Mips_FCR24, + Mips_FCR25, + Mips_FCR26, + Mips_FCR27, + Mips_FCR28, + Mips_FCR29, + Mips_FCR30, + Mips_FCR31, + Mips_FP_64, + Mips_F_HI0, + Mips_F_HI1, + Mips_F_HI2, + Mips_F_HI3, + Mips_F_HI4, + Mips_F_HI5, + Mips_F_HI6, + Mips_F_HI7, + Mips_F_HI8, + Mips_F_HI9, + Mips_F_HI10, + Mips_F_HI11, + Mips_F_HI12, + Mips_F_HI13, + Mips_F_HI14, + Mips_F_HI15, + Mips_F_HI16, + Mips_F_HI17, + Mips_F_HI18, + Mips_F_HI19, + Mips_F_HI20, + Mips_F_HI21, + Mips_F_HI22, + Mips_F_HI23, + Mips_F_HI24, + Mips_F_HI25, + Mips_F_HI26, + Mips_F_HI27, + Mips_F_HI28, + Mips_F_HI29, + Mips_F_HI30, + Mips_F_HI31, + Mips_GP_64, + Mips_HI0, + Mips_HI1, + Mips_HI2, + Mips_HI3, + Mips_HWR0, + Mips_HWR1, + Mips_HWR2, + Mips_HWR3, + Mips_HWR4, + Mips_HWR5, + Mips_HWR6, + Mips_HWR7, + Mips_HWR8, + Mips_HWR9, + Mips_HWR10, + Mips_HWR11, + Mips_HWR12, + Mips_HWR13, + Mips_HWR14, + Mips_HWR15, + Mips_HWR16, + Mips_HWR17, + Mips_HWR18, + Mips_HWR19, + Mips_HWR20, + Mips_HWR21, + Mips_HWR22, + Mips_HWR23, + Mips_HWR24, + Mips_HWR25, + Mips_HWR26, + Mips_HWR27, + Mips_HWR28, + Mips_HWR29, + Mips_HWR30, + Mips_HWR31, + Mips_K0, + Mips_K1, + Mips_LO0, + Mips_LO1, + Mips_LO2, + Mips_LO3, + Mips_MPL0, + Mips_MPL1, + Mips_MPL2, + Mips_P0, + Mips_P1, + Mips_P2, + Mips_RA_64, + Mips_S0, + Mips_S1, + Mips_S2, + Mips_S3, + Mips_S4, + Mips_S5, + Mips_S6, + Mips_S7, + Mips_SP_64, + Mips_T0, + Mips_T1, + Mips_T2, + Mips_T3, + Mips_T4, + Mips_T5, + Mips_T6, + Mips_T7, + Mips_T8, + Mips_T9, + Mips_V0, + Mips_V1, + Mips_W0, + Mips_W1, + Mips_W2, + Mips_W3, + Mips_W4, + Mips_W5, + Mips_W6, + Mips_W7, + Mips_W8, + Mips_W9, + Mips_W10, + Mips_W11, + Mips_W12, + Mips_W13, + Mips_W14, + Mips_W15, + Mips_W16, + Mips_W17, + Mips_W18, + Mips_W19, + Mips_W20, + Mips_W21, + Mips_W22, + Mips_W23, + Mips_W24, + Mips_W25, + Mips_W26, + Mips_W27, + Mips_W28, + Mips_W29, + Mips_W30, + Mips_W31, + Mips_ZERO_64, + Mips_A0_64, + Mips_A1_64, + Mips_A2_64, + Mips_A3_64, + Mips_AC0_64, + Mips_D0_64, + Mips_D1_64, + Mips_D2_64, + Mips_D3_64, + Mips_D4_64, + Mips_D5_64, + Mips_D6_64, + Mips_D7_64, + Mips_D8_64, + Mips_D9_64, + Mips_D10_64, + Mips_D11_64, + Mips_D12_64, + Mips_D13_64, + Mips_D14_64, + Mips_D15_64, + Mips_D16_64, + Mips_D17_64, + Mips_D18_64, + Mips_D19_64, + Mips_D20_64, + Mips_D21_64, + Mips_D22_64, + Mips_D23_64, + Mips_D24_64, + Mips_D25_64, + Mips_D26_64, + Mips_D27_64, + Mips_D28_64, + Mips_D29_64, + Mips_D30_64, + Mips_D31_64, + Mips_DSPOutFlag16_19, + Mips_HI0_64, + Mips_K0_64, + Mips_K1_64, + Mips_LO0_64, + Mips_S0_64, + Mips_S1_64, + Mips_S2_64, + Mips_S3_64, + Mips_S4_64, + Mips_S5_64, + Mips_S6_64, + Mips_S7_64, + Mips_T0_64, + Mips_T1_64, + Mips_T2_64, + Mips_T3_64, + Mips_T4_64, + Mips_T5_64, + Mips_T6_64, + Mips_T7_64, + Mips_T8_64, + Mips_T9_64, + }; + + static const unsigned int map[] = {0, + MIPS_REG_AT, + MIPS_REG_DSPCCOND, + MIPS_REG_DSPCARRY, + MIPS_REG_DSPEFI, + MIPS_REG_DSPOUTFLAG, + MIPS_REG_DSPPOS, + MIPS_REG_DSPSCOUNT, + MIPS_REG_FP, + MIPS_REG_GP, + MIPS_REG_2, + MIPS_REG_1, + MIPS_REG_0, + MIPS_REG_6, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_3, + MIPS_REG_7, + MIPS_REG_PC, + MIPS_REG_RA, + MIPS_REG_SP, + MIPS_REG_ZERO, + MIPS_REG_A0, + MIPS_REG_A1, + MIPS_REG_A2, + MIPS_REG_A3, + MIPS_REG_AC0, + MIPS_REG_AC1, + MIPS_REG_AC2, + MIPS_REG_AC3, + MIPS_REG_AT, + MIPS_REG_CC0, + MIPS_REG_CC1, + MIPS_REG_CC2, + MIPS_REG_CC3, + MIPS_REG_CC4, + MIPS_REG_CC5, + MIPS_REG_CC6, + MIPS_REG_CC7, + MIPS_REG_0, + MIPS_REG_1, + MIPS_REG_2, + MIPS_REG_3, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_6, + MIPS_REG_7, + MIPS_REG_8, + MIPS_REG_9, + MIPS_REG_0, + MIPS_REG_1, + MIPS_REG_2, + MIPS_REG_3, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_6, + MIPS_REG_7, + MIPS_REG_8, + MIPS_REG_9, + MIPS_REG_10, + MIPS_REG_11, + MIPS_REG_12, + MIPS_REG_13, + MIPS_REG_14, + MIPS_REG_15, + MIPS_REG_16, + MIPS_REG_17, + MIPS_REG_18, + MIPS_REG_19, + MIPS_REG_20, + MIPS_REG_21, + MIPS_REG_22, + MIPS_REG_23, + MIPS_REG_24, + MIPS_REG_25, + MIPS_REG_26, + MIPS_REG_27, + MIPS_REG_28, + MIPS_REG_29, + MIPS_REG_30, + MIPS_REG_31, + MIPS_REG_10, + MIPS_REG_11, + MIPS_REG_12, + MIPS_REG_13, + MIPS_REG_14, + MIPS_REG_15, + MIPS_REG_16, + MIPS_REG_17, + MIPS_REG_18, + MIPS_REG_19, + MIPS_REG_20, + MIPS_REG_21, + MIPS_REG_22, + MIPS_REG_23, + MIPS_REG_24, + MIPS_REG_25, + MIPS_REG_26, + MIPS_REG_27, + MIPS_REG_28, + MIPS_REG_29, + MIPS_REG_30, + MIPS_REG_31, + MIPS_REG_F0, + MIPS_REG_F2, + MIPS_REG_F4, + MIPS_REG_F6, + MIPS_REG_F8, + MIPS_REG_F10, + MIPS_REG_F12, + MIPS_REG_F14, + MIPS_REG_F16, + MIPS_REG_F18, + MIPS_REG_F20, + MIPS_REG_F22, + MIPS_REG_F24, + MIPS_REG_F26, + MIPS_REG_F28, + MIPS_REG_F30, + MIPS_REG_DSPOUTFLAG20, + MIPS_REG_DSPOUTFLAG21, + MIPS_REG_DSPOUTFLAG22, + MIPS_REG_DSPOUTFLAG23, + MIPS_REG_F0, + MIPS_REG_F1, + MIPS_REG_F2, + MIPS_REG_F3, + MIPS_REG_F4, + MIPS_REG_F5, + MIPS_REG_F6, + MIPS_REG_F7, + MIPS_REG_F8, + MIPS_REG_F9, + MIPS_REG_F10, + MIPS_REG_F11, + MIPS_REG_F12, + MIPS_REG_F13, + MIPS_REG_F14, + MIPS_REG_F15, + MIPS_REG_F16, + MIPS_REG_F17, + MIPS_REG_F18, + MIPS_REG_F19, + MIPS_REG_F20, + MIPS_REG_F21, + MIPS_REG_F22, + MIPS_REG_F23, + MIPS_REG_F24, + MIPS_REG_F25, + MIPS_REG_F26, + MIPS_REG_F27, + MIPS_REG_F28, + MIPS_REG_F29, + MIPS_REG_F30, + MIPS_REG_F31, + MIPS_REG_FCC0, + MIPS_REG_FCC1, + MIPS_REG_FCC2, + MIPS_REG_FCC3, + MIPS_REG_FCC4, + MIPS_REG_FCC5, + MIPS_REG_FCC6, + MIPS_REG_FCC7, + MIPS_REG_0, + MIPS_REG_1, + MIPS_REG_2, + MIPS_REG_3, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_6, + MIPS_REG_7, + MIPS_REG_8, + MIPS_REG_9, + MIPS_REG_10, + MIPS_REG_11, + MIPS_REG_12, + MIPS_REG_13, + MIPS_REG_14, + MIPS_REG_15, + MIPS_REG_16, + MIPS_REG_17, + MIPS_REG_18, + MIPS_REG_19, + MIPS_REG_20, + MIPS_REG_21, + MIPS_REG_22, + MIPS_REG_23, + MIPS_REG_24, + MIPS_REG_25, + MIPS_REG_26, + MIPS_REG_27, + MIPS_REG_28, + MIPS_REG_29, + MIPS_REG_30, + MIPS_REG_31, + MIPS_REG_FP, + MIPS_REG_F0, + MIPS_REG_F1, + MIPS_REG_F2, + MIPS_REG_F3, + MIPS_REG_F4, + MIPS_REG_F5, + MIPS_REG_F6, + MIPS_REG_F7, + MIPS_REG_F8, + MIPS_REG_F9, + MIPS_REG_F10, + MIPS_REG_F11, + MIPS_REG_F12, + MIPS_REG_F13, + MIPS_REG_F14, + MIPS_REG_F15, + MIPS_REG_F16, + MIPS_REG_F17, + MIPS_REG_F18, + MIPS_REG_F19, + MIPS_REG_F20, + MIPS_REG_F21, + MIPS_REG_F22, + MIPS_REG_F23, + MIPS_REG_F24, + MIPS_REG_F25, + MIPS_REG_F26, + MIPS_REG_F27, + MIPS_REG_F28, + MIPS_REG_F29, + MIPS_REG_F30, + MIPS_REG_F31, + MIPS_REG_GP, + MIPS_REG_AC0, + MIPS_REG_AC1, + MIPS_REG_AC2, + MIPS_REG_AC3, + 0, + 0, + 0, + 0, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_6, + MIPS_REG_7, + MIPS_REG_8, + MIPS_REG_9, + MIPS_REG_10, + MIPS_REG_11, + MIPS_REG_12, + MIPS_REG_13, + MIPS_REG_14, + MIPS_REG_15, + MIPS_REG_16, + MIPS_REG_17, + MIPS_REG_18, + MIPS_REG_19, + MIPS_REG_20, + MIPS_REG_21, + MIPS_REG_22, + MIPS_REG_23, + MIPS_REG_24, + MIPS_REG_25, + MIPS_REG_26, + MIPS_REG_27, + MIPS_REG_28, + MIPS_REG_29, + MIPS_REG_30, + MIPS_REG_31, + MIPS_REG_K0, + MIPS_REG_K1, + MIPS_REG_AC0, + MIPS_REG_AC1, + MIPS_REG_AC2, + MIPS_REG_AC3, + MIPS_REG_MPL0, + MIPS_REG_MPL1, + MIPS_REG_MPL2, + MIPS_REG_P0, + MIPS_REG_P1, + MIPS_REG_P2, + MIPS_REG_RA, + MIPS_REG_S0, + MIPS_REG_S1, + MIPS_REG_S2, + MIPS_REG_S3, + MIPS_REG_S4, + MIPS_REG_S5, + MIPS_REG_S6, + MIPS_REG_S7, + MIPS_REG_SP, + MIPS_REG_T0, + MIPS_REG_T1, + MIPS_REG_T2, + MIPS_REG_T3, + MIPS_REG_T4, + MIPS_REG_T5, + MIPS_REG_T6, + MIPS_REG_T7, + MIPS_REG_T8, + MIPS_REG_T9, + MIPS_REG_V0, + MIPS_REG_V1, + MIPS_REG_W0, + MIPS_REG_W1, + MIPS_REG_W2, + MIPS_REG_W3, + MIPS_REG_W4, + MIPS_REG_W5, + MIPS_REG_W6, + MIPS_REG_W7, + MIPS_REG_W8, + MIPS_REG_W9, + MIPS_REG_W10, + MIPS_REG_W11, + MIPS_REG_W12, + MIPS_REG_W13, + MIPS_REG_W14, + MIPS_REG_W15, + MIPS_REG_W16, + MIPS_REG_W17, + MIPS_REG_W18, + MIPS_REG_W19, + MIPS_REG_W20, + MIPS_REG_W21, + MIPS_REG_W22, + MIPS_REG_W23, + MIPS_REG_W24, + MIPS_REG_W25, + MIPS_REG_W26, + MIPS_REG_W27, + MIPS_REG_W28, + MIPS_REG_W29, + MIPS_REG_W30, + MIPS_REG_W31, + MIPS_REG_ZERO, + MIPS_REG_A0, + MIPS_REG_A1, + MIPS_REG_A2, + MIPS_REG_A3, + MIPS_REG_AC0, + MIPS_REG_F0, + MIPS_REG_F1, + MIPS_REG_F2, + MIPS_REG_F3, + MIPS_REG_F4, + MIPS_REG_F5, + MIPS_REG_F6, + MIPS_REG_F7, + MIPS_REG_F8, + MIPS_REG_F9, + MIPS_REG_F10, + MIPS_REG_F11, + MIPS_REG_F12, + MIPS_REG_F13, + MIPS_REG_F14, + MIPS_REG_F15, + MIPS_REG_F16, + MIPS_REG_F17, + MIPS_REG_F18, + MIPS_REG_F19, + MIPS_REG_F20, + MIPS_REG_F21, + MIPS_REG_F22, + MIPS_REG_F23, + MIPS_REG_F24, + MIPS_REG_F25, + MIPS_REG_F26, + MIPS_REG_F27, + MIPS_REG_F28, + MIPS_REG_F29, + MIPS_REG_F30, + MIPS_REG_F31, + MIPS_REG_DSPOUTFLAG16_19, + MIPS_REG_HI, + MIPS_REG_K0, + MIPS_REG_K1, + MIPS_REG_LO, + MIPS_REG_S0, + MIPS_REG_S1, + MIPS_REG_S2, + MIPS_REG_S3, + MIPS_REG_S4, + MIPS_REG_S5, + MIPS_REG_S6, + MIPS_REG_S7, + MIPS_REG_T0, + MIPS_REG_T1, + MIPS_REG_T2, + MIPS_REG_T3, + MIPS_REG_T4, + MIPS_REG_T5, + MIPS_REG_T6, + MIPS_REG_T7, + MIPS_REG_T8, + MIPS_REG_T9, + MIPS_REG_V0, + MIPS_REG_V1}; - if (r < ARR_SIZE(map)) - return map[r]; + for (int i = 0; i < ARR_SIZE(map_outer); i++) + if (map_outer[i] == r) + return map[i]; - // cannot find this register - return 0; + // cannot find this register + return 0; } #endif diff --git a/arch/Mips/MipsMappingInsn.inc b/arch/Mips/MipsMappingInsn.inc deleted file mode 100644 index beb026c71e..0000000000 --- a/arch/Mips/MipsMappingInsn.inc +++ /dev/null @@ -1,9315 +0,0 @@ -// This is auto-gen data for Capstone engine (www.capstone-engine.org) -// By Nguyen Anh Quynh - -{ - Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ABSQ_S_W, MIPS_INS_ABSQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUPC, MIPS_INS_ADDIUPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUPC_MM, MIPS_INS_ADDIUPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUR1SP_MM, MIPS_INS_ADDIUR1SP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUR2_MM, MIPS_INS_ADDIUR2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUS5_MM, MIPS_INS_ADDIUS5, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUSP_MM, MIPS_INS_ADDIUSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQH_PH, MIPS_INS_ADDQH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQH_R_W, MIPS_INS_ADDQH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQH_W, MIPS_INS_ADDQH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQ_PH, MIPS_INS_ADDQ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQ_S_W, MIPS_INS_ADDQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDSC, MIPS_INS_ADDSC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_A_B, MIPS_INS_ADDS_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_A_D, MIPS_INS_ADDS_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_A_H, MIPS_INS_ADDS_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_A_W, MIPS_INS_ADDS_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_S_B, MIPS_INS_ADDS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_S_D, MIPS_INS_ADDS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_S_H, MIPS_INS_ADDS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_S_W, MIPS_INS_ADDS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_U_B, MIPS_INS_ADDS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_U_D, MIPS_INS_ADDS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_U_H, MIPS_INS_ADDS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_U_W, MIPS_INS_ADDS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDU16_MM, MIPS_INS_ADDU16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDUH_QB, MIPS_INS_ADDUH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDU_PH, MIPS_INS_ADDU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDU_QB, MIPS_INS_ADDU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDU_S_PH, MIPS_INS_ADDU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDU_S_QB, MIPS_INS_ADDU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDVI_B, MIPS_INS_ADDVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDVI_D, MIPS_INS_ADDVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDVI_H, MIPS_INS_ADDVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDVI_W, MIPS_INS_ADDVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDV_B, MIPS_INS_ADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDV_D, MIPS_INS_ADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDV_H, MIPS_INS_ADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDV_W, MIPS_INS_ADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDWC, MIPS_INS_ADDWC, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD_A_B, MIPS_INS_ADD_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD_A_D, MIPS_INS_ADD_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD_A_H, MIPS_INS_ADD_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD_A_W, MIPS_INS_ADD_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD_MM, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDi, MIPS_INS_ADDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDi_MM, MIPS_INS_ADDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDiu, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDiu_MM, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDu, MIPS_INS_ADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDu_MM, MIPS_INS_ADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ALIGN, MIPS_INS_ALIGN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_ALUIPC, MIPS_INS_ALUIPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_AND, MIPS_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_AND16_MM, MIPS_INS_AND16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_AND64, MIPS_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ANDI16_MM, MIPS_INS_ANDI16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ANDI_B, MIPS_INS_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AND_MM, MIPS_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_AND_V, MIPS_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ANDi, MIPS_INS_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ANDi64, MIPS_INS_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ANDi_MM, MIPS_INS_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_APPEND, MIPS_INS_APPEND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_S_B, MIPS_INS_ASUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_S_D, MIPS_INS_ASUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_S_H, MIPS_INS_ASUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_S_W, MIPS_INS_ASUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_U_B, MIPS_INS_ASUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_U_D, MIPS_INS_ASUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_U_H, MIPS_INS_ASUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_U_W, MIPS_INS_ASUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AUI, MIPS_INS_AUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_AUIPC, MIPS_INS_AUIPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_S_B, MIPS_INS_AVER_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_S_D, MIPS_INS_AVER_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_S_H, MIPS_INS_AVER_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_S_W, MIPS_INS_AVER_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_U_B, MIPS_INS_AVER_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_U_D, MIPS_INS_AVER_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_U_H, MIPS_INS_AVER_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_U_W, MIPS_INS_AVER_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_S_B, MIPS_INS_AVE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_S_D, MIPS_INS_AVE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_S_H, MIPS_INS_AVE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_S_W, MIPS_INS_AVE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_U_B, MIPS_INS_AVE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_U_D, MIPS_INS_AVE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_U_H, MIPS_INS_AVE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_U_W, MIPS_INS_AVE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuRxImmX16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuRxRxImm16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuSpImm16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuSpImmX16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AdduRxRyRz16, MIPS_INS_ADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AndRxRxRy16, MIPS_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_B16_MM, MIPS_INS_B16, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BADDu, MIPS_INS_BADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BAL, MIPS_INS_BAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BALC, MIPS_INS_BALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BALIGN, MIPS_INS_BALIGN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_BBIT0, MIPS_INS_BBIT0, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BBIT032, MIPS_INS_BBIT032, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BBIT1, MIPS_INS_BBIT1, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BBIT132, MIPS_INS_BBIT132, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BC, MIPS_INS_BC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC0F, MIPS_INS_BC0F, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC0FL, MIPS_INS_BC0FL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC0T, MIPS_INS_BC0T, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC0TL, MIPS_INS_BC0TL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1EQZ, MIPS_INS_BC1EQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1F, MIPS_INS_BC1F, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1FL, MIPS_INS_BC1FL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1F_MM, MIPS_INS_BC1F, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1NEZ, MIPS_INS_BC1NEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1T, MIPS_INS_BC1T, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1TL, MIPS_INS_BC1TL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1T_MM, MIPS_INS_BC1T, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2EQZ, MIPS_INS_BC2EQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2F, MIPS_INS_BC2F, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2FL, MIPS_INS_BC2FL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2NEZ, MIPS_INS_BC2NEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2T, MIPS_INS_BC2T, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2TL, MIPS_INS_BC2TL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC3F, MIPS_INS_BC3F, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC3FL, MIPS_INS_BC3FL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC3T, MIPS_INS_BC3T, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC3TL, MIPS_INS_BC3TL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BCLRI_B, MIPS_INS_BCLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLRI_D, MIPS_INS_BCLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLRI_H, MIPS_INS_BCLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLRI_W, MIPS_INS_BCLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLR_B, MIPS_INS_BCLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLR_D, MIPS_INS_BCLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLR_H, MIPS_INS_BCLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLR_W, MIPS_INS_BCLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BEQ, MIPS_INS_BEQ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQ64, MIPS_INS_BEQ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQC, MIPS_INS_BEQC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQL, MIPS_INS_BEQL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQZ16_MM, MIPS_INS_BEQZ16, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQZALC, MIPS_INS_BEQZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQZC, MIPS_INS_BEQZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQZC_MM, MIPS_INS_BEQZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQ_MM, MIPS_INS_BEQ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEC, MIPS_INS_BGEC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEUC, MIPS_INS_BGEUC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZ, MIPS_INS_BGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZ64, MIPS_INS_BGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZAL, MIPS_INS_BGEZAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_BGEZALC, MIPS_INS_BGEZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZALL, MIPS_INS_BGEZALL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_BGEZALS_MM, MIPS_INS_BGEZALS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BGEZAL_MM, MIPS_INS_BGEZAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BGEZC, MIPS_INS_BGEZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZL, MIPS_INS_BGEZL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZ_MM, MIPS_INS_BGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZ, MIPS_INS_BGTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZ64, MIPS_INS_BGTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZALC, MIPS_INS_BGTZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZC, MIPS_INS_BGTZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZL, MIPS_INS_BGTZL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZ_MM, MIPS_INS_BGTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BINSLI_B, MIPS_INS_BINSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSLI_D, MIPS_INS_BINSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSLI_H, MIPS_INS_BINSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSLI_W, MIPS_INS_BINSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSL_B, MIPS_INS_BINSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSL_D, MIPS_INS_BINSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSL_H, MIPS_INS_BINSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSL_W, MIPS_INS_BINSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSRI_B, MIPS_INS_BINSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSRI_D, MIPS_INS_BINSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSRI_H, MIPS_INS_BINSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSRI_W, MIPS_INS_BINSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSR_B, MIPS_INS_BINSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSR_D, MIPS_INS_BINSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSR_H, MIPS_INS_BINSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSR_W, MIPS_INS_BINSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BITREV, MIPS_INS_BITREV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_BITSWAP, MIPS_INS_BITSWAP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_BLEZ, MIPS_INS_BLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BLEZ64, MIPS_INS_BLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BLEZALC, MIPS_INS_BLEZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLEZC, MIPS_INS_BLEZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLEZL, MIPS_INS_BLEZL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLEZ_MM, MIPS_INS_BLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTC, MIPS_INS_BLTC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTUC, MIPS_INS_BLTUC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZ, MIPS_INS_BLTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZ64, MIPS_INS_BLTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZAL, MIPS_INS_BLTZAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_BLTZALC, MIPS_INS_BLTZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZALL, MIPS_INS_BLTZALL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_BLTZALS_MM, MIPS_INS_BLTZALS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BLTZAL_MM, MIPS_INS_BLTZAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BLTZC, MIPS_INS_BLTZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZL, MIPS_INS_BLTZL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZ_MM, MIPS_INS_BLTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BMNZI_B, MIPS_INS_BMNZI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BMNZ_V, MIPS_INS_BMNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BMZI_B, MIPS_INS_BMZI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BMZ_V, MIPS_INS_BMZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNE, MIPS_INS_BNE, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BNE64, MIPS_INS_BNE, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEC, MIPS_INS_BNEC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEGI_B, MIPS_INS_BNEGI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEGI_D, MIPS_INS_BNEGI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEGI_H, MIPS_INS_BNEGI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEGI_W, MIPS_INS_BNEGI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEG_B, MIPS_INS_BNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEG_D, MIPS_INS_BNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEG_H, MIPS_INS_BNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEG_W, MIPS_INS_BNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEL, MIPS_INS_BNEL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEZ16_MM, MIPS_INS_BNEZ16, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEZALC, MIPS_INS_BNEZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEZC, MIPS_INS_BNEZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEZC_MM, MIPS_INS_BNEZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BNE_MM, MIPS_INS_BNE, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BNVC, MIPS_INS_BNVC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BNZ_B, MIPS_INS_BNZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BNZ_D, MIPS_INS_BNZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BNZ_H, MIPS_INS_BNZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BNZ_V, MIPS_INS_BNZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BNZ_W, MIPS_INS_BNZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BOVC, MIPS_INS_BOVC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BPOSGE32, MIPS_INS_BPOSGE32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_DSP, 0 }, 1, 0 -#endif -}, -{ - Mips_BREAK, MIPS_INS_BREAK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_BREAK16_MM, MIPS_INS_BREAK16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BREAK_MM, MIPS_INS_BREAK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BSELI_B, MIPS_INS_BSELI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSEL_V, MIPS_INS_BSEL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSETI_B, MIPS_INS_BSETI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSETI_D, MIPS_INS_BSETI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSETI_H, MIPS_INS_BSETI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSETI_W, MIPS_INS_BSETI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSET_B, MIPS_INS_BSET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSET_D, MIPS_INS_BSET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSET_H, MIPS_INS_BSET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSET_W, MIPS_INS_BSET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BZ_B, MIPS_INS_BZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BZ_D, MIPS_INS_BZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BZ_H, MIPS_INS_BZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BZ_V, MIPS_INS_BZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BZ_W, MIPS_INS_BZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BeqzRxImm16, MIPS_INS_BEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BeqzRxImmX16, MIPS_INS_BEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_Bimm16, MIPS_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BimmX16, MIPS_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BnezRxImm16, MIPS_INS_BNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BnezRxImmX16, MIPS_INS_BNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_Break16, MIPS_INS_BREAK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_Bteqz16, MIPS_INS_BTEQZ, -#ifndef CAPSTONE_DIET - { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BteqzX16, MIPS_INS_BTEQZ, -#ifndef CAPSTONE_DIET - { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_Btnez16, MIPS_INS_BTNEZ, -#ifndef CAPSTONE_DIET - { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BtnezX16, MIPS_INS_BTNEZ, -#ifndef CAPSTONE_DIET - { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_CACHE, MIPS_INS_CACHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CACHE_MM, MIPS_INS_CACHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CACHE_R6, MIPS_INS_CACHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_L_D64, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_L_S, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_W_D32, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_W_D64, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_W_MM, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_W_S, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_W_S_MM, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQI_B, MIPS_INS_CEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQI_D, MIPS_INS_CEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQI_H, MIPS_INS_CEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQI_W, MIPS_INS_CEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQ_B, MIPS_INS_CEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQ_D, MIPS_INS_CEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQ_H, MIPS_INS_CEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQ_W, MIPS_INS_CEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CFC1, MIPS_INS_CFC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_CFC1_MM, MIPS_INS_CFC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CFCMSA, MIPS_INS_CFCMSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CINS, MIPS_INS_CINS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CINS32, MIPS_INS_CINS32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CLASS_D, MIPS_INS_CLASS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CLASS_S, MIPS_INS_CLASS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_S_B, MIPS_INS_CLEI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_S_D, MIPS_INS_CLEI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_S_H, MIPS_INS_CLEI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_S_W, MIPS_INS_CLEI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_U_B, MIPS_INS_CLEI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_U_D, MIPS_INS_CLEI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_U_H, MIPS_INS_CLEI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_U_W, MIPS_INS_CLEI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_S_B, MIPS_INS_CLE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_S_D, MIPS_INS_CLE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_S_H, MIPS_INS_CLE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_S_W, MIPS_INS_CLE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_U_B, MIPS_INS_CLE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_U_D, MIPS_INS_CLE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_U_H, MIPS_INS_CLE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_U_W, MIPS_INS_CLE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLO, MIPS_INS_CLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CLO_MM, MIPS_INS_CLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CLO_R6, MIPS_INS_CLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_S_B, MIPS_INS_CLTI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_S_D, MIPS_INS_CLTI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_S_H, MIPS_INS_CLTI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_S_W, MIPS_INS_CLTI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_U_B, MIPS_INS_CLTI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_U_D, MIPS_INS_CLTI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_U_H, MIPS_INS_CLTI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_U_W, MIPS_INS_CLTI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_S_B, MIPS_INS_CLT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_S_D, MIPS_INS_CLT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_S_H, MIPS_INS_CLT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_S_W, MIPS_INS_CLT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_U_B, MIPS_INS_CLT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_U_D, MIPS_INS_CLT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_U_H, MIPS_INS_CLT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_U_W, MIPS_INS_CLT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLZ, MIPS_INS_CLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CLZ_MM, MIPS_INS_CLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CLZ_R6, MIPS_INS_CLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGU_LE_QB, MIPS_INS_CMPGU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGU_LT_QB, MIPS_INS_CMPGU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPU_EQ_QB, MIPS_INS_CMPU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPU_LE_QB, MIPS_INS_CMPU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPU_LT_QB, MIPS_INS_CMPU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_EQ_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_EQ_PH, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_EQ_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_F_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_F_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LE_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LE_PH, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LE_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LT_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LT_PH, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LT_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SAF_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SAF_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SEQ_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SEQ_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SLE_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SLE_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SLT_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SLT_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SUEQ_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SUEQ_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SULE_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SULE_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SULT_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SULT_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SUN_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SUN_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_UEQ_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_UEQ_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_ULE_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_ULE_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_ULT_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_ULT_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_UN_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_UN_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_S_B, MIPS_INS_COPY_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_S_D, MIPS_INS_COPY_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_S_H, MIPS_INS_COPY_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_S_W, MIPS_INS_COPY_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_U_B, MIPS_INS_COPY_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_U_D, MIPS_INS_COPY_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_U_H, MIPS_INS_COPY_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_U_W, MIPS_INS_COPY_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CTC1, MIPS_INS_CTC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_CTC1_MM, MIPS_INS_CTC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CTCMSA, MIPS_INS_CTCMSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D32_S, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D32_W, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D32_W_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D64_L, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D64_S, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D64_W, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D_S_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_L_D64, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_L_D64_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_L_S, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_L_S_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_D32, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_D32_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_D64, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_L, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_W, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_W_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_W_D32, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_W_D64, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_W_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_W_S, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_W_S_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_C_EQ_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_EQ_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_EQ_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_F_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_F_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_F_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LE_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LE_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LE_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LT_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LT_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LT_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGE_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGE_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGE_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGLE_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGLE_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGLE_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGL_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGL_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGL_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGT_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGT_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGT_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLE_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLE_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLE_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLT_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLT_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLT_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SEQ_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SEQ_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SEQ_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SF_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SF_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SF_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UEQ_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UEQ_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UEQ_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULE_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULE_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULE_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULT_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULT_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULT_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UN_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UN_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UN_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CmpRxRy16, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_CmpiRxImm16, MIPS_INS_CMPI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_CmpiRxImmX16, MIPS_INS_CMPI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_DADD, MIPS_INS_DADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DADDi, MIPS_INS_DADDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DADDiu, MIPS_INS_DADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DADDu, MIPS_INS_DADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DAHI, MIPS_INS_DAHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DALIGN, MIPS_INS_DALIGN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DATI, MIPS_INS_DATI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DAUI, MIPS_INS_DAUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DBITSWAP, MIPS_INS_DBITSWAP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DCLO, MIPS_INS_DCLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DCLO_R6, MIPS_INS_DCLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DCLZ, MIPS_INS_DCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DCLZ_R6, MIPS_INS_DCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DDIV, MIPS_INS_DDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DDIVU, MIPS_INS_DDIVU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DERET, MIPS_INS_DERET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 -#endif -}, -{ - Mips_DERET_MM, MIPS_INS_DERET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_DEXT, MIPS_INS_DEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DEXTM, MIPS_INS_DEXTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DEXTU, MIPS_INS_DEXTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DI, MIPS_INS_DI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DINS, MIPS_INS_DINS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DINSM, MIPS_INS_DINSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DINSU, MIPS_INS_DINSU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DIVU, MIPS_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_S_B, MIPS_INS_DIV_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_S_D, MIPS_INS_DIV_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_S_H, MIPS_INS_DIV_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_S_W, MIPS_INS_DIV_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_U_B, MIPS_INS_DIV_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_U_D, MIPS_INS_DIV_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_U_H, MIPS_INS_DIV_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_U_W, MIPS_INS_DIV_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DI_MM, MIPS_INS_DI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_DLSA, MIPS_INS_DLSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_DLSA_R6, MIPS_INS_DLSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMFC0, MIPS_INS_DMFC0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_DMFC1, MIPS_INS_DMFC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DMFC2, MIPS_INS_DMFC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_DMOD, MIPS_INS_DMOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMODU, MIPS_INS_DMODU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMTC0, MIPS_INS_DMTC0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_DMTC1, MIPS_INS_DMTC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DMTC2, MIPS_INS_DMTC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_DMUH, MIPS_INS_DMUH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMUHU, MIPS_INS_DMUHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMUL, MIPS_INS_DMUL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_DMULT, MIPS_INS_DMULT, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMULTu, MIPS_INS_DMULTU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMULU, MIPS_INS_DMULU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMUL_R6, MIPS_INS_DMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_S_D, MIPS_INS_DOTP_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_S_H, MIPS_INS_DOTP_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_S_W, MIPS_INS_DOTP_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_U_D, MIPS_INS_DOTP_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_U_H, MIPS_INS_DOTP_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_U_W, MIPS_INS_DOTP_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_S_D, MIPS_INS_DPADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_S_H, MIPS_INS_DPADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_S_W, MIPS_INS_DPADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_U_D, MIPS_INS_DPADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_U_H, MIPS_INS_DPADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_U_W, MIPS_INS_DPADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAU_H_QBL, MIPS_INS_DPAU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAU_H_QBR, MIPS_INS_DPAU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAX_W_PH, MIPS_INS_DPAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPA_W_PH, MIPS_INS_DPA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPOP, MIPS_INS_DPOP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_S_D, MIPS_INS_DPSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_S_H, MIPS_INS_DPSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_S_W, MIPS_INS_DPSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_U_D, MIPS_INS_DPSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_U_H, MIPS_INS_DPSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_U_W, MIPS_INS_DPSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSU_H_QBL, MIPS_INS_DPSU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSU_H_QBR, MIPS_INS_DPSU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSX_W_PH, MIPS_INS_DPSX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPS_W_PH, MIPS_INS_DPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DROTR, MIPS_INS_DROTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DROTR32, MIPS_INS_DROTR32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DROTRV, MIPS_INS_DROTRV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DSBH, MIPS_INS_DSBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DSDIV, MIPS_INS_DDIV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DSHD, MIPS_INS_DSHD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DSLL, MIPS_INS_DSLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSLL32, MIPS_INS_DSLL32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSLL64_32, MIPS_INS_DSLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_DSLLV, MIPS_INS_DSLLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRA, MIPS_INS_DSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRA32, MIPS_INS_DSRA32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRAV, MIPS_INS_DSRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRL, MIPS_INS_DSRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRL32, MIPS_INS_DSRL32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRLV, MIPS_INS_DSRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSUB, MIPS_INS_DSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSUBu, MIPS_INS_DSUBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DUDIV, MIPS_INS_DDIVU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DivRxRy16, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_DivuRxRy16, MIPS_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_EHB, MIPS_INS_EHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_EHB_MM, MIPS_INS_EHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_EI, MIPS_INS_EI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_EI_MM, MIPS_INS_EI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ERET, MIPS_INS_ERET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, 0 }, 0, 0 -#endif -}, -{ - Mips_ERET_MM, MIPS_INS_ERET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_EXT, MIPS_INS_EXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTP, MIPS_INS_EXTP, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTPDP, MIPS_INS_EXTPDP, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTPDPV, MIPS_INS_EXTPDPV, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTPV, MIPS_INS_EXTPV, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTRV_R_W, MIPS_INS_EXTRV_R, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTRV_S_H, MIPS_INS_EXTRV_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTRV_W, MIPS_INS_EXTRV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTR_RS_W, MIPS_INS_EXTR_RS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTR_R_W, MIPS_INS_EXTR_R, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTR_S_H, MIPS_INS_EXTR_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTR_W, MIPS_INS_EXTR, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTS, MIPS_INS_EXTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTS32, MIPS_INS_EXTS32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_EXT_MM, MIPS_INS_EXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FABS_D32, MIPS_INS_ABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FABS_D64, MIPS_INS_ABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FABS_MM, MIPS_INS_ABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FABS_S, MIPS_INS_ABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FABS_S_MM, MIPS_INS_ABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_D, MIPS_INS_FADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_D32, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_D64, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_MM, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_S, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_S_MM, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_W, MIPS_INS_FADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCAF_D, MIPS_INS_FCAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCAF_W, MIPS_INS_FCAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCEQ_D, MIPS_INS_FCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCEQ_W, MIPS_INS_FCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLASS_D, MIPS_INS_FCLASS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLASS_W, MIPS_INS_FCLASS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLE_D, MIPS_INS_FCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLE_W, MIPS_INS_FCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLT_D, MIPS_INS_FCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLT_W, MIPS_INS_FCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCMP_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FCMP_D32_MM, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FCMP_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FCMP_S32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_FCMP_S32_MM, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FCNE_D, MIPS_INS_FCNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCNE_W, MIPS_INS_FCNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCOR_D, MIPS_INS_FCOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCOR_W, MIPS_INS_FCOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUEQ_D, MIPS_INS_FCUEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUEQ_W, MIPS_INS_FCUEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCULE_D, MIPS_INS_FCULE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCULE_W, MIPS_INS_FCULE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCULT_D, MIPS_INS_FCULT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCULT_W, MIPS_INS_FCULT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUNE_D, MIPS_INS_FCUNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUNE_W, MIPS_INS_FCUNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUN_D, MIPS_INS_FCUN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUN_W, MIPS_INS_FCUN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_D, MIPS_INS_FDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_D32, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_D64, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_MM, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_S, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_S_MM, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_W, MIPS_INS_FDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXDO_H, MIPS_INS_FEXDO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXDO_W, MIPS_INS_FEXDO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXP2_D, MIPS_INS_FEXP2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXP2_W, MIPS_INS_FEXP2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXUPL_D, MIPS_INS_FEXUPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXUPL_W, MIPS_INS_FEXUPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXUPR_D, MIPS_INS_FEXUPR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXUPR_W, MIPS_INS_FEXUPR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFINT_S_D, MIPS_INS_FFINT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFINT_S_W, MIPS_INS_FFINT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFINT_U_D, MIPS_INS_FFINT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFINT_U_W, MIPS_INS_FFINT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFQL_D, MIPS_INS_FFQL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFQL_W, MIPS_INS_FFQL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFQR_D, MIPS_INS_FFQR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFQR_W, MIPS_INS_FFQR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FILL_B, MIPS_INS_FILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FILL_D, MIPS_INS_FILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_FILL_H, MIPS_INS_FILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FILL_W, MIPS_INS_FILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOG2_D, MIPS_INS_FLOG2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOG2_W, MIPS_INS_FLOG2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_L_D64, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_L_S, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_W_D32, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_W_D64, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_W_MM, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_W_S, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FMADD_D, MIPS_INS_FMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMADD_W, MIPS_INS_FMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMAX_A_D, MIPS_INS_FMAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMAX_A_W, MIPS_INS_FMAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMAX_D, MIPS_INS_FMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMAX_W, MIPS_INS_FMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMIN_A_D, MIPS_INS_FMIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMIN_A_W, MIPS_INS_FMIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMIN_D, MIPS_INS_FMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMIN_W, MIPS_INS_FMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMOV_D32, MIPS_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FMOV_D32_MM, MIPS_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FMOV_D64, MIPS_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FMOV_S, MIPS_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FMOV_S_MM, MIPS_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FMSUB_D, MIPS_INS_FMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMSUB_W, MIPS_INS_FMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_D, MIPS_INS_FMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_D32, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_D64, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_MM, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_S, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_S_MM, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_W, MIPS_INS_FMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FNEG_D32, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FNEG_D64, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FNEG_MM, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FNEG_S, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FNEG_S_MM, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FRCP_D, MIPS_INS_FRCP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FRCP_W, MIPS_INS_FRCP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FRINT_D, MIPS_INS_FRINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FRINT_W, MIPS_INS_FRINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FRSQRT_D, MIPS_INS_FRSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FRSQRT_W, MIPS_INS_FRSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSAF_D, MIPS_INS_FSAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSAF_W, MIPS_INS_FSAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSEQ_D, MIPS_INS_FSEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSEQ_W, MIPS_INS_FSEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSLE_D, MIPS_INS_FSLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSLE_W, MIPS_INS_FSLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSLT_D, MIPS_INS_FSLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSLT_W, MIPS_INS_FSLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSNE_D, MIPS_INS_FSNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSNE_W, MIPS_INS_FSNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSOR_D, MIPS_INS_FSOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSOR_W, MIPS_INS_FSOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_D, MIPS_INS_FSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_D32, MIPS_INS_SQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_D64, MIPS_INS_SQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_MM, MIPS_INS_SQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_S, MIPS_INS_SQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_S_MM, MIPS_INS_SQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_W, MIPS_INS_FSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_D, MIPS_INS_FSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_D32, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_D64, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_MM, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_S, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_S_MM, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_W, MIPS_INS_FSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUEQ_D, MIPS_INS_FSUEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUEQ_W, MIPS_INS_FSUEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSULE_D, MIPS_INS_FSULE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSULE_W, MIPS_INS_FSULE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSULT_D, MIPS_INS_FSULT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSULT_W, MIPS_INS_FSULT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUNE_D, MIPS_INS_FSUNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUNE_W, MIPS_INS_FSUNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUN_D, MIPS_INS_FSUN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUN_W, MIPS_INS_FSUN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTINT_S_D, MIPS_INS_FTINT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTINT_S_W, MIPS_INS_FTINT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTINT_U_D, MIPS_INS_FTINT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTINT_U_W, MIPS_INS_FTINT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTQ_H, MIPS_INS_FTQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTQ_W, MIPS_INS_FTQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_S_D, MIPS_INS_HADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_S_H, MIPS_INS_HADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_S_W, MIPS_INS_HADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_U_D, MIPS_INS_HADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_U_H, MIPS_INS_HADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_U_W, MIPS_INS_HADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_S_D, MIPS_INS_HSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_S_H, MIPS_INS_HSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_S_W, MIPS_INS_HSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_U_D, MIPS_INS_HSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_U_H, MIPS_INS_HSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_U_W, MIPS_INS_HSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVEV_B, MIPS_INS_ILVEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVEV_D, MIPS_INS_ILVEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVEV_H, MIPS_INS_ILVEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVEV_W, MIPS_INS_ILVEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVL_B, MIPS_INS_ILVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVL_D, MIPS_INS_ILVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVL_H, MIPS_INS_ILVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVL_W, MIPS_INS_ILVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVOD_B, MIPS_INS_ILVOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVOD_D, MIPS_INS_ILVOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVOD_H, MIPS_INS_ILVOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVOD_W, MIPS_INS_ILVOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVR_B, MIPS_INS_ILVR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVR_D, MIPS_INS_ILVR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVR_H, MIPS_INS_ILVR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVR_W, MIPS_INS_ILVR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INS, MIPS_INS_INS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_INSERT_B, MIPS_INS_INSERT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSERT_D, MIPS_INS_INSERT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_INSERT_H, MIPS_INS_INSERT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSERT_W, MIPS_INS_INSERT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSV, MIPS_INS_INSV, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_INSVE_B, MIPS_INS_INSVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSVE_D, MIPS_INS_INSVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSVE_H, MIPS_INS_INSVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSVE_W, MIPS_INS_INSVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INS_MM, MIPS_INS_INS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_J, MIPS_INS_J, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_JAL, MIPS_INS_JAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_JALR, MIPS_INS_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALR16_MM, MIPS_INS_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALR64, MIPS_INS_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALRS16_MM, MIPS_INS_JALRS16, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALRS_MM, MIPS_INS_JALRS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALR_HB, MIPS_INS_JALR_HB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_CALL, 0 }, 0, 1 -#endif -}, -{ - Mips_JALR_MM, MIPS_INS_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALS_MM, MIPS_INS_JALS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_JALX, MIPS_INS_JALX, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_JALX_MM, MIPS_INS_JALX, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_JAL_MM, MIPS_INS_JAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_JIALC, MIPS_INS_JIALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_JIC, MIPS_INS_JIC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_JR, MIPS_INS_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 -#endif -}, -{ - Mips_JR16_MM, MIPS_INS_JR16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 -#endif -}, -{ - Mips_JR64, MIPS_INS_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 -#endif -}, -{ - Mips_JRADDIUSP, MIPS_INS_JRADDIUSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 -#endif -}, -{ - Mips_JRC16_MM, MIPS_INS_JRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 -#endif -}, -{ - Mips_JR_HB, MIPS_INS_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 1 -#endif -}, -{ - Mips_JR_HB_R6, MIPS_INS_JR_HB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 1 -#endif -}, -{ - Mips_JR_MM, MIPS_INS_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 -#endif -}, -{ - Mips_J_MM, MIPS_INS_J, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_Jal16, MIPS_INS_JAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_JrRa16, MIPS_INS_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 -#endif -}, -{ - Mips_JrcRa16, MIPS_INS_JRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 -#endif -}, -{ - Mips_JrcRx16, MIPS_INS_JRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 -#endif -}, -{ - Mips_JumpLinkReg16, MIPS_INS_JALRC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_LB, MIPS_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LB64, MIPS_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LBU16_MM, MIPS_INS_LBU16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LBUX, MIPS_INS_LBUX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_LB_MM, MIPS_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LBu, MIPS_INS_LBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LBu64, MIPS_INS_LBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LBu_MM, MIPS_INS_LBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LD, MIPS_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC1, MIPS_INS_LDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC164, MIPS_INS_LDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC1_MM, MIPS_INS_LDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC2, MIPS_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC2_R6, MIPS_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC3, MIPS_INS_LDC3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LDI_B, MIPS_INS_LDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LDI_D, MIPS_INS_LDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LDI_H, MIPS_INS_LDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LDI_W, MIPS_INS_LDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LDL, MIPS_INS_LDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LDPC, MIPS_INS_LDPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LDR, MIPS_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LDXC1, MIPS_INS_LDXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_LDXC164, MIPS_INS_LDXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LD_B, MIPS_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LD_D, MIPS_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LD_H, MIPS_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LD_W, MIPS_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LEA_ADDiu, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LEA_ADDiu64, MIPS_INS_DADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LH, MIPS_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LH64, MIPS_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LHU16_MM, MIPS_INS_LHU16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LHX, MIPS_INS_LHX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_LH_MM, MIPS_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LHu, MIPS_INS_LHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LHu64, MIPS_INS_LHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LHu_MM, MIPS_INS_LHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LI16_MM, MIPS_INS_LI16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LL, MIPS_INS_LL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LLD, MIPS_INS_LLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LLD_R6, MIPS_INS_LLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LL_MM, MIPS_INS_LL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LL_R6, MIPS_INS_LL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LSA, MIPS_INS_LSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LSA_R6, MIPS_INS_LSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LUXC1, MIPS_INS_LUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_LUXC164, MIPS_INS_LUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LUXC1_MM, MIPS_INS_LUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LUi, MIPS_INS_LUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LUi64, MIPS_INS_LUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LUi_MM, MIPS_INS_LUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LW, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LW16_MM, MIPS_INS_LW16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LW64, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LWC1, MIPS_INS_LWC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LWC1_MM, MIPS_INS_LWC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWC2, MIPS_INS_LWC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWC2_R6, MIPS_INS_LWC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LWC3, MIPS_INS_LWC3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWGP_MM, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWL, MIPS_INS_LWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWL64, MIPS_INS_LWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LWL_MM, MIPS_INS_LWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWM16_MM, MIPS_INS_LWM16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWM32_MM, MIPS_INS_LWM32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWPC, MIPS_INS_LWPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LWP_MM, MIPS_INS_LWP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWR, MIPS_INS_LWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWR64, MIPS_INS_LWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LWR_MM, MIPS_INS_LWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWSP_MM, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWUPC, MIPS_INS_LWUPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LWU_MM, MIPS_INS_LWU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWX, MIPS_INS_LWX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_LWXC1, MIPS_INS_LWXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_LWXC1_MM, MIPS_INS_LWXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWXS_MM, MIPS_INS_LWXS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LW_MM, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWu, MIPS_INS_LWU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_LbRxRyOffMemX16, MIPS_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LbuRxRyOffMemX16, MIPS_INS_LBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LhRxRyOffMemX16, MIPS_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LhuRxRyOffMemX16, MIPS_INS_LHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LiRxImm16, MIPS_INS_LI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LiRxImmX16, MIPS_INS_LI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LwRxPcTcp16, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LwRxPcTcpX16, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LwRxRyOffMemX16, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LwRxSpImmX16, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDF_D, MIPS_INS_MADDF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDF_S, MIPS_INS_MADDF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDR_Q_H, MIPS_INS_MADDR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDR_Q_W, MIPS_INS_MADDR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDU, MIPS_INS_MADDU, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDU_DSP, MIPS_INS_MADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDU_MM, MIPS_INS_MADDU, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDV_B, MIPS_INS_MADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDV_D, MIPS_INS_MADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDV_H, MIPS_INS_MADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDV_W, MIPS_INS_MADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_D32, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_D32_MM, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_D64, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_DSP, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_MM, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_Q_H, MIPS_INS_MADD_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_Q_W, MIPS_INS_MADD_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_S, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_S_MM, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXA_D, MIPS_INS_MAXA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXA_S, MIPS_INS_MAXA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_S_B, MIPS_INS_MAXI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_S_D, MIPS_INS_MAXI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_S_H, MIPS_INS_MAXI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_S_W, MIPS_INS_MAXI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_U_B, MIPS_INS_MAXI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_U_D, MIPS_INS_MAXI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_U_H, MIPS_INS_MAXI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_U_W, MIPS_INS_MAXI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_A_B, MIPS_INS_MAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_A_D, MIPS_INS_MAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_A_H, MIPS_INS_MAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_A_W, MIPS_INS_MAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_D, MIPS_INS_MAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_S, MIPS_INS_MAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_S_B, MIPS_INS_MAX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_S_D, MIPS_INS_MAX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_S_H, MIPS_INS_MAX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_S_W, MIPS_INS_MAX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_U_B, MIPS_INS_MAX_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_U_D, MIPS_INS_MAX_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_U_H, MIPS_INS_MAX_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_U_W, MIPS_INS_MAX_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MFC0, MIPS_INS_MFC0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 -#endif -}, -{ - Mips_MFC1, MIPS_INS_MFC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_MFC1_MM, MIPS_INS_MFC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFC2, MIPS_INS_MFC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHC1_D32, MIPS_INS_MFHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHC1_D64, MIPS_INS_MFHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHC1_MM, MIPS_INS_MFHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHI, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHI16_MM, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHI64, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHI_DSP, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHI_MM, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFLO, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFLO16_MM, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFLO64, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MFLO_DSP, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MFLO_MM, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MINA_D, MIPS_INS_MINA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MINA_S, MIPS_INS_MINA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_S_B, MIPS_INS_MINI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_S_D, MIPS_INS_MINI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_S_H, MIPS_INS_MINI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_S_W, MIPS_INS_MINI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_U_B, MIPS_INS_MINI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_U_D, MIPS_INS_MINI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_U_H, MIPS_INS_MINI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_U_W, MIPS_INS_MINI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_A_B, MIPS_INS_MIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_A_D, MIPS_INS_MIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_A_H, MIPS_INS_MIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_A_W, MIPS_INS_MIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_D, MIPS_INS_MIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_S, MIPS_INS_MIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_S_B, MIPS_INS_MIN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_S_D, MIPS_INS_MIN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_S_H, MIPS_INS_MIN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_S_W, MIPS_INS_MIN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_U_B, MIPS_INS_MIN_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_U_D, MIPS_INS_MIN_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_U_H, MIPS_INS_MIN_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_U_W, MIPS_INS_MIN_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD, MIPS_INS_MOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MODSUB, MIPS_INS_MODSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MODU, MIPS_INS_MODU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_S_B, MIPS_INS_MOD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_S_D, MIPS_INS_MOD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_S_H, MIPS_INS_MOD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_S_W, MIPS_INS_MOD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_U_B, MIPS_INS_MOD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_U_D, MIPS_INS_MOD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_U_H, MIPS_INS_MOD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_U_W, MIPS_INS_MOD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVE16_MM, MIPS_INS_MOVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVEP_MM, MIPS_INS_MOVEP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVE_V, MIPS_INS_MOVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_D32, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_D32_MM, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_D64, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_I, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_I64, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_I_MM, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_S, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_S_MM, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I64_D64, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I64_I, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I64_I64, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I64_S, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_D32, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_D32_MM, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_D64, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_I, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_I64, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_MM, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_S, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_S_MM, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_D32, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_D32_MM, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_D64, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_I, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_I64, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_I_MM, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_S, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_S_MM, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I64_D64, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I64_I, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I64_I64, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I64_S, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_D32, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_D64, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_I, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_I64, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_MM, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_S, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBF_D, MIPS_INS_MSUBF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBF_S, MIPS_INS_MSUBF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBU, MIPS_INS_MSUBU, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBU_DSP, MIPS_INS_MSUBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBU_MM, MIPS_INS_MSUBU, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBV_B, MIPS_INS_MSUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBV_D, MIPS_INS_MSUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBV_H, MIPS_INS_MSUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBV_W, MIPS_INS_MSUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_D32, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_D32_MM, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_D64, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_DSP, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_MM, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_Q_H, MIPS_INS_MSUB_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_Q_W, MIPS_INS_MSUB_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_S, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_S_MM, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTC0, MIPS_INS_MTC0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 -#endif -}, -{ - Mips_MTC1, MIPS_INS_MTC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_MTC1_MM, MIPS_INS_MTC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTC2, MIPS_INS_MTC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHC1_D32, MIPS_INS_MTHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHC1_D64, MIPS_INS_MTHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHC1_MM, MIPS_INS_MTHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHI, MIPS_INS_MTHI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHI64, MIPS_INS_MTHI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHI_DSP, MIPS_INS_MTHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHI_MM, MIPS_INS_MTHI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHLIP, MIPS_INS_MTHLIP, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MTLO, MIPS_INS_MTLO, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MTLO64, MIPS_INS_MTLO, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MTLO_DSP, MIPS_INS_MTLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MTLO_MM, MIPS_INS_MTLO, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTM0, MIPS_INS_MTM0, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTM1, MIPS_INS_MTM1, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTM2, MIPS_INS_MTM2, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTP0, MIPS_INS_MTP0, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_P0, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTP1, MIPS_INS_MTP1, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_P1, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTP2, MIPS_INS_MTP2, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MUH, MIPS_INS_MUH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MUHU, MIPS_INS_MUHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULQ_RS_W, MIPS_INS_MULQ_RS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_MULQ_S_PH, MIPS_INS_MULQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_MULQ_S_W, MIPS_INS_MULQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_MULR_Q_H, MIPS_INS_MULR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MULR_Q_W, MIPS_INS_MULR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULSA_W_PH, MIPS_INS_MULSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_MULT, MIPS_INS_MULT, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MULTU_DSP, MIPS_INS_MULTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULT_DSP, MIPS_INS_MULT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULT_MM, MIPS_INS_MULT, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MULTu, MIPS_INS_MULTU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MULTu_MM, MIPS_INS_MULTU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MULU, MIPS_INS_MULU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MULV_B, MIPS_INS_MULV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MULV_D, MIPS_INS_MULV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MULV_H, MIPS_INS_MULV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MULV_W, MIPS_INS_MULV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_MM, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_PH, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_Q_H, MIPS_INS_MUL_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_Q_W, MIPS_INS_MUL_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_R6, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_S_PH, MIPS_INS_MUL_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_Mfhi16, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_Mflo16, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_Move32R16, MIPS_INS_MOVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_MoveR3216, MIPS_INS_MOVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_NLOC_B, MIPS_INS_NLOC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLOC_D, MIPS_INS_NLOC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLOC_H, MIPS_INS_NLOC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLOC_W, MIPS_INS_NLOC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLZC_B, MIPS_INS_NLZC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLZC_D, MIPS_INS_NLZC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLZC_H, MIPS_INS_NLZC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLZC_W, MIPS_INS_NLZC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NMADD_D32, MIPS_INS_NMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMADD_D32_MM, MIPS_INS_NMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NMADD_D64, MIPS_INS_NMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMADD_S, MIPS_INS_NMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMADD_S_MM, MIPS_INS_NMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NMSUB_D32, MIPS_INS_NMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMSUB_D32_MM, MIPS_INS_NMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NMSUB_D64, MIPS_INS_NMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMSUB_S, MIPS_INS_NMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMSUB_S_MM, MIPS_INS_NMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NOR, MIPS_INS_NOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_NOR64, MIPS_INS_NOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_NORI_B, MIPS_INS_NORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NOR_MM, MIPS_INS_NOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NOR_V, MIPS_INS_NOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NOT16_MM, MIPS_INS_NOT16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NegRxRy16, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_NotRxRy16, MIPS_INS_NOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_OR, MIPS_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_OR16_MM, MIPS_INS_OR16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_OR64, MIPS_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ORI_B, MIPS_INS_ORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_OR_MM, MIPS_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_OR_V, MIPS_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ORi, MIPS_INS_ORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ORi64, MIPS_INS_ORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ORi_MM, MIPS_INS_ORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_OrRxRxRy16, MIPS_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_PACKRL_PH, MIPS_INS_PACKRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PAUSE, MIPS_INS_PAUSE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_PAUSE_MM, MIPS_INS_PAUSE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKEV_B, MIPS_INS_PCKEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKEV_D, MIPS_INS_PCKEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKEV_H, MIPS_INS_PCKEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKEV_W, MIPS_INS_PCKEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKOD_B, MIPS_INS_PCKOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKOD_D, MIPS_INS_PCKOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKOD_H, MIPS_INS_PCKOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKOD_W, MIPS_INS_PCKOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCNT_B, MIPS_INS_PCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCNT_D, MIPS_INS_PCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCNT_H, MIPS_INS_PCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCNT_W, MIPS_INS_PCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PICK_PH, MIPS_INS_PICK, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PICK_QB, MIPS_INS_PICK, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_POP, MIPS_INS_POP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECR_QB_PH, MIPS_INS_PRECR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_PREF, MIPS_INS_PREF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_PREF_MM, MIPS_INS_PREF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_PREF_R6, MIPS_INS_PREF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_PREPEND, MIPS_INS_PREPEND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_RADDU_W_QB, MIPS_INS_RADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_RDDSP, MIPS_INS_RDDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_RDHWR, MIPS_INS_RDHWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_RDHWR64, MIPS_INS_RDHWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_RDHWR_MM, MIPS_INS_RDHWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_REPLV_PH, MIPS_INS_REPLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_REPLV_QB, MIPS_INS_REPLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_REPL_PH, MIPS_INS_REPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_REPL_QB, MIPS_INS_REPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_RINT_D, MIPS_INS_RINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_RINT_S, MIPS_INS_RINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_ROTR, MIPS_INS_ROTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_ROTRV, MIPS_INS_ROTRV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_ROTRV_MM, MIPS_INS_ROTRV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ROTR_MM, MIPS_INS_ROTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_L_D64, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_L_S, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_W_D32, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_W_D64, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_W_MM, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_W_S, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_W_S_MM, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_S_B, MIPS_INS_SAT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_S_D, MIPS_INS_SAT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_S_H, MIPS_INS_SAT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_S_W, MIPS_INS_SAT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_U_B, MIPS_INS_SAT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_U_D, MIPS_INS_SAT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_U_H, MIPS_INS_SAT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_U_W, MIPS_INS_SAT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SB, MIPS_INS_SB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SB16_MM, MIPS_INS_SB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SB64, MIPS_INS_SB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SB_MM, MIPS_INS_SB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SC, MIPS_INS_SC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SCD, MIPS_INS_SCD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SCD_R6, MIPS_INS_SCD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SC_MM, MIPS_INS_SC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SC_R6, MIPS_INS_SC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SD, MIPS_INS_SD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_SDBBP, MIPS_INS_SDBBP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDBBP16_MM, MIPS_INS_SDBBP16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDBBP_MM, MIPS_INS_SDBBP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDBBP_R6, MIPS_INS_SDBBP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC1, MIPS_INS_SDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC164, MIPS_INS_SDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC1_MM, MIPS_INS_SDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC2, MIPS_INS_SDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC2_R6, MIPS_INS_SDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC3, MIPS_INS_SDC3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDIV, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDIV_MM, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDL, MIPS_INS_SDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDR, MIPS_INS_SDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDXC1, MIPS_INS_SDXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_SDXC164, MIPS_INS_SDXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SEB, MIPS_INS_SEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_SEB64, MIPS_INS_SEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_SEB_MM, MIPS_INS_SEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SEH, MIPS_INS_SEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_SEH64, MIPS_INS_SEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_SEH_MM, MIPS_INS_SEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SELEQZ, MIPS_INS_SELEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELEQZ64, MIPS_INS_SELEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELEQZ_D, MIPS_INS_SELEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELEQZ_S, MIPS_INS_SELEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELNEZ, MIPS_INS_SELNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELNEZ64, MIPS_INS_SELNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELNEZ_D, MIPS_INS_SELNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELNEZ_S, MIPS_INS_SELNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SEL_D, MIPS_INS_SEL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SEL_S, MIPS_INS_SEL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SEQ, MIPS_INS_SEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SEQi, MIPS_INS_SEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SH, MIPS_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SH16_MM, MIPS_INS_SH16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SH64, MIPS_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SHF_B, MIPS_INS_SHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SHF_H, MIPS_INS_SHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SHF_W, MIPS_INS_SHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SHILO, MIPS_INS_SHILO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHILOV, MIPS_INS_SHILOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLLV_PH, MIPS_INS_SHLLV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLLV_QB, MIPS_INS_SHLLV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLLV_S_W, MIPS_INS_SHLLV_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLL_PH, MIPS_INS_SHLL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLL_QB, MIPS_INS_SHLL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLL_S_PH, MIPS_INS_SHLL_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLL_S_W, MIPS_INS_SHLL_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRAV_PH, MIPS_INS_SHRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRAV_QB, MIPS_INS_SHRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRAV_R_W, MIPS_INS_SHRAV_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRA_PH, MIPS_INS_SHRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRA_QB, MIPS_INS_SHRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRA_R_PH, MIPS_INS_SHRA_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRA_R_QB, MIPS_INS_SHRA_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRA_R_W, MIPS_INS_SHRA_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRLV_PH, MIPS_INS_SHRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRLV_QB, MIPS_INS_SHRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRL_PH, MIPS_INS_SHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRL_QB, MIPS_INS_SHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SH_MM, MIPS_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLDI_B, MIPS_INS_SLDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLDI_D, MIPS_INS_SLDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLDI_H, MIPS_INS_SLDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLDI_W, MIPS_INS_SLDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLD_B, MIPS_INS_SLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLD_D, MIPS_INS_SLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLD_H, MIPS_INS_SLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLD_W, MIPS_INS_SLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL16_MM, MIPS_INS_SLL16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL64_32, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL64_64, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLI_B, MIPS_INS_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLI_D, MIPS_INS_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLI_H, MIPS_INS_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLI_W, MIPS_INS_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLV, MIPS_INS_SLLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLV_MM, MIPS_INS_SLLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL_B, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL_D, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL_H, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL_MM, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL_W, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLT, MIPS_INS_SLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLT64, MIPS_INS_SLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLT_MM, MIPS_INS_SLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTi, MIPS_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTi64, MIPS_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTi_MM, MIPS_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTiu, MIPS_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTiu64, MIPS_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTiu_MM, MIPS_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTu, MIPS_INS_SLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTu64, MIPS_INS_SLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTu_MM, MIPS_INS_SLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SNE, MIPS_INS_SNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SNEi, MIPS_INS_SNEI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLATI_B, MIPS_INS_SPLATI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLATI_D, MIPS_INS_SPLATI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLATI_H, MIPS_INS_SPLATI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLATI_W, MIPS_INS_SPLATI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLAT_B, MIPS_INS_SPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLAT_D, MIPS_INS_SPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLAT_H, MIPS_INS_SPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLAT_W, MIPS_INS_SPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAI_B, MIPS_INS_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAI_D, MIPS_INS_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAI_H, MIPS_INS_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAI_W, MIPS_INS_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRARI_B, MIPS_INS_SRARI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRARI_D, MIPS_INS_SRARI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRARI_H, MIPS_INS_SRARI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRARI_W, MIPS_INS_SRARI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAR_B, MIPS_INS_SRAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAR_D, MIPS_INS_SRAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAR_H, MIPS_INS_SRAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAR_W, MIPS_INS_SRAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAV, MIPS_INS_SRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAV_MM, MIPS_INS_SRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA_B, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA_D, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA_H, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA_MM, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA_W, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL16_MM, MIPS_INS_SRL16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLI_B, MIPS_INS_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLI_D, MIPS_INS_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLI_H, MIPS_INS_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLI_W, MIPS_INS_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLRI_B, MIPS_INS_SRLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLRI_D, MIPS_INS_SRLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLRI_H, MIPS_INS_SRLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLRI_W, MIPS_INS_SRLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLR_B, MIPS_INS_SRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLR_D, MIPS_INS_SRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLR_H, MIPS_INS_SRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLR_W, MIPS_INS_SRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLV, MIPS_INS_SRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLV_MM, MIPS_INS_SRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL_B, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL_D, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL_H, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL_MM, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL_W, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SSNOP, MIPS_INS_SSNOP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SSNOP_MM, MIPS_INS_SSNOP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ST_B, MIPS_INS_ST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ST_D, MIPS_INS_ST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ST_H, MIPS_INS_ST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ST_W, MIPS_INS_ST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUB, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQH_PH, MIPS_INS_SUBQH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQH_R_W, MIPS_INS_SUBQH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQH_W, MIPS_INS_SUBQH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQ_PH, MIPS_INS_SUBQ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQ_S_W, MIPS_INS_SUBQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_S_B, MIPS_INS_SUBS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_S_D, MIPS_INS_SUBS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_S_H, MIPS_INS_SUBS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_S_W, MIPS_INS_SUBS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_U_B, MIPS_INS_SUBS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_U_D, MIPS_INS_SUBS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_U_H, MIPS_INS_SUBS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_U_W, MIPS_INS_SUBS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBU16_MM, MIPS_INS_SUBU16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBUH_QB, MIPS_INS_SUBUH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBU_PH, MIPS_INS_SUBU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBU_QB, MIPS_INS_SUBU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBU_S_PH, MIPS_INS_SUBU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBU_S_QB, MIPS_INS_SUBU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBVI_B, MIPS_INS_SUBVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBVI_D, MIPS_INS_SUBVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBVI_H, MIPS_INS_SUBVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBVI_W, MIPS_INS_SUBVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBV_B, MIPS_INS_SUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBV_D, MIPS_INS_SUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBV_H, MIPS_INS_SUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBV_W, MIPS_INS_SUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUB_MM, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBu, MIPS_INS_SUBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBu_MM, MIPS_INS_SUBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SUXC1, MIPS_INS_SUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_SUXC164, MIPS_INS_SUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SUXC1_MM, MIPS_INS_SUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SW, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SW16_MM, MIPS_INS_SW16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SW64, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SWC1, MIPS_INS_SWC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SWC1_MM, MIPS_INS_SWC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWC2, MIPS_INS_SWC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWC2_R6, MIPS_INS_SWC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SWC3, MIPS_INS_SWC3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWL, MIPS_INS_SWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWL64, MIPS_INS_SWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SWL_MM, MIPS_INS_SWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWM16_MM, MIPS_INS_SWM16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWM32_MM, MIPS_INS_SWM32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWP_MM, MIPS_INS_SWP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWR, MIPS_INS_SWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWR64, MIPS_INS_SWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SWR_MM, MIPS_INS_SWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWSP_MM, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWXC1, MIPS_INS_SWXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_SWXC1_MM, MIPS_INS_SWXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SW_MM, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SYNC, MIPS_INS_SYNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 -#endif -}, -{ - Mips_SYNCI, MIPS_INS_SYNCI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_SYNC_MM, MIPS_INS_SYNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SYSCALL, MIPS_INS_SYSCALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_INT, 0 }, 0, 0 -#endif -}, -{ - Mips_SYSCALL_MM, MIPS_INS_SYSCALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_INT, 0 }, 0, 0 -#endif -}, -{ - Mips_SbRxRyOffMemX16, MIPS_INS_SB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SebRx16, MIPS_INS_SEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SehRx16, MIPS_INS_SEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_ShRxRyOffMemX16, MIPS_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SllX16, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SllvRxRy16, MIPS_INS_SLLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltRxRy16, MIPS_INS_SLT, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltiRxImm16, MIPS_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltiRxImmX16, MIPS_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltiuRxImm16, MIPS_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltiuRxImmX16, MIPS_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltuRxRy16, MIPS_INS_SLTU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SraX16, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SravRxRy16, MIPS_INS_SRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SrlX16, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SrlvRxRy16, MIPS_INS_SRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SubuRxRyRz16, MIPS_INS_SUBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SwRxRyOffMemX16, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SwRxSpImmX16, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_TEQ, MIPS_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TEQI, MIPS_INS_TEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_TEQI_MM, MIPS_INS_TEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TEQ_MM, MIPS_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TGE, MIPS_INS_TGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEI, MIPS_INS_TGEI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEIU, MIPS_INS_TGEIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEIU_MM, MIPS_INS_TGEIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEI_MM, MIPS_INS_TGEI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEU, MIPS_INS_TGEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEU_MM, MIPS_INS_TGEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TGE_MM, MIPS_INS_TGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBP, MIPS_INS_TLBP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBP_MM, MIPS_INS_TLBP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBR, MIPS_INS_TLBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBR_MM, MIPS_INS_TLBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBWI, MIPS_INS_TLBWI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBWI_MM, MIPS_INS_TLBWI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBWR, MIPS_INS_TLBWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBWR_MM, MIPS_INS_TLBWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLT, MIPS_INS_TLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TLTI, MIPS_INS_TLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_TLTIU_MM, MIPS_INS_TLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLTI_MM, MIPS_INS_TLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLTU, MIPS_INS_TLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TLTU_MM, MIPS_INS_TLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLT_MM, MIPS_INS_TLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TNE, MIPS_INS_TNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TNEI, MIPS_INS_TNEI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_TNEI_MM, MIPS_INS_TNEI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TNE_MM, MIPS_INS_TNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_L_D64, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_L_S, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_W_D32, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_W_D64, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_W_MM, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_W_S, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TTLTIU, MIPS_INS_TLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_UDIV, MIPS_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_UDIV_MM, MIPS_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_V3MULU, MIPS_INS_V3MULU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_VMM0, MIPS_INS_VMM0, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_VMULU, MIPS_INS_VMULU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_VSHF_B, MIPS_INS_VSHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_VSHF_D, MIPS_INS_VSHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_VSHF_H, MIPS_INS_VSHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_VSHF_W, MIPS_INS_VSHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_WAIT, MIPS_INS_WAIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_WAIT_MM, MIPS_INS_WAIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_WRDSP, MIPS_INS_WRDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_WSBH, MIPS_INS_WSBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_WSBH_MM, MIPS_INS_WSBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_XOR, MIPS_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_XOR16_MM, MIPS_INS_XOR16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_XOR64, MIPS_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_XORI_B, MIPS_INS_XORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_XOR_MM, MIPS_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_XOR_V, MIPS_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_XORi, MIPS_INS_XORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_XORi64, MIPS_INS_XORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_XORi_MM, MIPS_INS_XORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_XorRxRxRy16, MIPS_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, diff --git a/include/capstone/mips.h b/include/capstone/mips.h index 339445611c..07b9aba402 100644 --- a/include/capstone/mips.h +++ b/include/capstone/mips.h @@ -256,697 +256,857 @@ typedef struct cs_mips { /// MIPS instruction typedef enum mips_insn { - MIPS_INS_INVALID = 0, - - MIPS_INS_ABSQ_S, - MIPS_INS_ADD, - MIPS_INS_ADDIUPC, - MIPS_INS_ADDIUR1SP, - MIPS_INS_ADDIUR2, - MIPS_INS_ADDIUS5, - MIPS_INS_ADDIUSP, - MIPS_INS_ADDQH, - MIPS_INS_ADDQH_R, - MIPS_INS_ADDQ, - MIPS_INS_ADDQ_S, - MIPS_INS_ADDSC, - MIPS_INS_ADDS_A, - MIPS_INS_ADDS_S, - MIPS_INS_ADDS_U, - MIPS_INS_ADDU16, - MIPS_INS_ADDUH, - MIPS_INS_ADDUH_R, - MIPS_INS_ADDU, - MIPS_INS_ADDU_S, - MIPS_INS_ADDVI, - MIPS_INS_ADDV, - MIPS_INS_ADDWC, - MIPS_INS_ADD_A, - MIPS_INS_ADDI, - MIPS_INS_ADDIU, - MIPS_INS_ALIGN, - MIPS_INS_ALUIPC, - MIPS_INS_AND, - MIPS_INS_AND16, - MIPS_INS_ANDI16, - MIPS_INS_ANDI, - MIPS_INS_APPEND, - MIPS_INS_ASUB_S, - MIPS_INS_ASUB_U, - MIPS_INS_AUI, - MIPS_INS_AUIPC, - MIPS_INS_AVER_S, - MIPS_INS_AVER_U, - MIPS_INS_AVE_S, - MIPS_INS_AVE_U, - MIPS_INS_B16, - MIPS_INS_BADDU, - MIPS_INS_BAL, - MIPS_INS_BALC, - MIPS_INS_BALIGN, - MIPS_INS_BBIT0, - MIPS_INS_BBIT032, - MIPS_INS_BBIT1, - MIPS_INS_BBIT132, - MIPS_INS_BC, - MIPS_INS_BC0F, - MIPS_INS_BC0FL, - MIPS_INS_BC0T, - MIPS_INS_BC0TL, - MIPS_INS_BC1EQZ, - MIPS_INS_BC1F, - MIPS_INS_BC1FL, - MIPS_INS_BC1NEZ, - MIPS_INS_BC1T, - MIPS_INS_BC1TL, - MIPS_INS_BC2EQZ, - MIPS_INS_BC2F, - MIPS_INS_BC2FL, - MIPS_INS_BC2NEZ, - MIPS_INS_BC2T, - MIPS_INS_BC2TL, - MIPS_INS_BC3F, - MIPS_INS_BC3FL, - MIPS_INS_BC3T, - MIPS_INS_BC3TL, - MIPS_INS_BCLRI, - MIPS_INS_BCLR, - MIPS_INS_BEQ, - MIPS_INS_BEQC, - MIPS_INS_BEQL, - MIPS_INS_BEQZ16, - MIPS_INS_BEQZALC, - MIPS_INS_BEQZC, - MIPS_INS_BGEC, - MIPS_INS_BGEUC, - MIPS_INS_BGEZ, - MIPS_INS_BGEZAL, - MIPS_INS_BGEZALC, - MIPS_INS_BGEZALL, - MIPS_INS_BGEZALS, - MIPS_INS_BGEZC, - MIPS_INS_BGEZL, - MIPS_INS_BGTZ, - MIPS_INS_BGTZALC, - MIPS_INS_BGTZC, - MIPS_INS_BGTZL, - MIPS_INS_BINSLI, - MIPS_INS_BINSL, - MIPS_INS_BINSRI, - MIPS_INS_BINSR, - MIPS_INS_BITREV, - MIPS_INS_BITSWAP, - MIPS_INS_BLEZ, - MIPS_INS_BLEZALC, - MIPS_INS_BLEZC, - MIPS_INS_BLEZL, - MIPS_INS_BLTC, - MIPS_INS_BLTUC, - MIPS_INS_BLTZ, - MIPS_INS_BLTZAL, - MIPS_INS_BLTZALC, - MIPS_INS_BLTZALL, - MIPS_INS_BLTZALS, - MIPS_INS_BLTZC, - MIPS_INS_BLTZL, - MIPS_INS_BMNZI, - MIPS_INS_BMNZ, - MIPS_INS_BMZI, - MIPS_INS_BMZ, - MIPS_INS_BNE, - MIPS_INS_BNEC, - MIPS_INS_BNEGI, - MIPS_INS_BNEG, - MIPS_INS_BNEL, - MIPS_INS_BNEZ16, - MIPS_INS_BNEZALC, - MIPS_INS_BNEZC, - MIPS_INS_BNVC, - MIPS_INS_BNZ, - MIPS_INS_BOVC, - MIPS_INS_BPOSGE32, - MIPS_INS_BREAK, - MIPS_INS_BREAK16, - MIPS_INS_BSELI, - MIPS_INS_BSEL, - MIPS_INS_BSETI, - MIPS_INS_BSET, - MIPS_INS_BZ, - MIPS_INS_BEQZ, - MIPS_INS_B, - MIPS_INS_BNEZ, - MIPS_INS_BTEQZ, - MIPS_INS_BTNEZ, - MIPS_INS_CACHE, - MIPS_INS_CEIL, - MIPS_INS_CEQI, - MIPS_INS_CEQ, - MIPS_INS_CFC1, - MIPS_INS_CFCMSA, - MIPS_INS_CINS, - MIPS_INS_CINS32, - MIPS_INS_CLASS, - MIPS_INS_CLEI_S, - MIPS_INS_CLEI_U, - MIPS_INS_CLE_S, - MIPS_INS_CLE_U, - MIPS_INS_CLO, - MIPS_INS_CLTI_S, - MIPS_INS_CLTI_U, - MIPS_INS_CLT_S, - MIPS_INS_CLT_U, - MIPS_INS_CLZ, - MIPS_INS_CMPGDU, - MIPS_INS_CMPGU, - MIPS_INS_CMPU, - MIPS_INS_CMP, - MIPS_INS_COPY_S, - MIPS_INS_COPY_U, - MIPS_INS_CTC1, - MIPS_INS_CTCMSA, - MIPS_INS_CVT, - MIPS_INS_C, - MIPS_INS_CMPI, - MIPS_INS_DADD, - MIPS_INS_DADDI, - MIPS_INS_DADDIU, - MIPS_INS_DADDU, - MIPS_INS_DAHI, - MIPS_INS_DALIGN, - MIPS_INS_DATI, - MIPS_INS_DAUI, - MIPS_INS_DBITSWAP, - MIPS_INS_DCLO, - MIPS_INS_DCLZ, - MIPS_INS_DDIV, - MIPS_INS_DDIVU, - MIPS_INS_DERET, - MIPS_INS_DEXT, - MIPS_INS_DEXTM, - MIPS_INS_DEXTU, - MIPS_INS_DI, - MIPS_INS_DINS, - MIPS_INS_DINSM, - MIPS_INS_DINSU, - MIPS_INS_DIV, - MIPS_INS_DIVU, - MIPS_INS_DIV_S, - MIPS_INS_DIV_U, - MIPS_INS_DLSA, - MIPS_INS_DMFC0, - MIPS_INS_DMFC1, - MIPS_INS_DMFC2, - MIPS_INS_DMOD, - MIPS_INS_DMODU, - MIPS_INS_DMTC0, - MIPS_INS_DMTC1, - MIPS_INS_DMTC2, - MIPS_INS_DMUH, - MIPS_INS_DMUHU, - MIPS_INS_DMUL, - MIPS_INS_DMULT, - MIPS_INS_DMULTU, - MIPS_INS_DMULU, - MIPS_INS_DOTP_S, - MIPS_INS_DOTP_U, - MIPS_INS_DPADD_S, - MIPS_INS_DPADD_U, - MIPS_INS_DPAQX_SA, - MIPS_INS_DPAQX_S, - MIPS_INS_DPAQ_SA, - MIPS_INS_DPAQ_S, - MIPS_INS_DPAU, - MIPS_INS_DPAX, - MIPS_INS_DPA, - MIPS_INS_DPOP, - MIPS_INS_DPSQX_SA, - MIPS_INS_DPSQX_S, - MIPS_INS_DPSQ_SA, - MIPS_INS_DPSQ_S, - MIPS_INS_DPSUB_S, - MIPS_INS_DPSUB_U, - MIPS_INS_DPSU, - MIPS_INS_DPSX, - MIPS_INS_DPS, - MIPS_INS_DROTR, - MIPS_INS_DROTR32, - MIPS_INS_DROTRV, - MIPS_INS_DSBH, - MIPS_INS_DSHD, - MIPS_INS_DSLL, - MIPS_INS_DSLL32, - MIPS_INS_DSLLV, - MIPS_INS_DSRA, - MIPS_INS_DSRA32, - MIPS_INS_DSRAV, - MIPS_INS_DSRL, - MIPS_INS_DSRL32, - MIPS_INS_DSRLV, - MIPS_INS_DSUB, - MIPS_INS_DSUBU, - MIPS_INS_EHB, - MIPS_INS_EI, - MIPS_INS_ERET, - MIPS_INS_EXT, - MIPS_INS_EXTP, - MIPS_INS_EXTPDP, - MIPS_INS_EXTPDPV, - MIPS_INS_EXTPV, - MIPS_INS_EXTRV_RS, - MIPS_INS_EXTRV_R, - MIPS_INS_EXTRV_S, - MIPS_INS_EXTRV, - MIPS_INS_EXTR_RS, - MIPS_INS_EXTR_R, - MIPS_INS_EXTR_S, - MIPS_INS_EXTR, - MIPS_INS_EXTS, - MIPS_INS_EXTS32, - MIPS_INS_ABS, - MIPS_INS_FADD, - MIPS_INS_FCAF, - MIPS_INS_FCEQ, - MIPS_INS_FCLASS, - MIPS_INS_FCLE, - MIPS_INS_FCLT, - MIPS_INS_FCNE, - MIPS_INS_FCOR, - MIPS_INS_FCUEQ, - MIPS_INS_FCULE, - MIPS_INS_FCULT, - MIPS_INS_FCUNE, - MIPS_INS_FCUN, - MIPS_INS_FDIV, - MIPS_INS_FEXDO, - MIPS_INS_FEXP2, - MIPS_INS_FEXUPL, - MIPS_INS_FEXUPR, - MIPS_INS_FFINT_S, - MIPS_INS_FFINT_U, - MIPS_INS_FFQL, - MIPS_INS_FFQR, - MIPS_INS_FILL, - MIPS_INS_FLOG2, - MIPS_INS_FLOOR, - MIPS_INS_FMADD, - MIPS_INS_FMAX_A, - MIPS_INS_FMAX, - MIPS_INS_FMIN_A, - MIPS_INS_FMIN, - MIPS_INS_MOV, - MIPS_INS_FMSUB, - MIPS_INS_FMUL, - MIPS_INS_MUL, - MIPS_INS_NEG, - MIPS_INS_FRCP, - MIPS_INS_FRINT, - MIPS_INS_FRSQRT, - MIPS_INS_FSAF, - MIPS_INS_FSEQ, - MIPS_INS_FSLE, - MIPS_INS_FSLT, - MIPS_INS_FSNE, - MIPS_INS_FSOR, - MIPS_INS_FSQRT, - MIPS_INS_SQRT, - MIPS_INS_FSUB, - MIPS_INS_SUB, - MIPS_INS_FSUEQ, - MIPS_INS_FSULE, - MIPS_INS_FSULT, - MIPS_INS_FSUNE, - MIPS_INS_FSUN, - MIPS_INS_FTINT_S, - MIPS_INS_FTINT_U, - MIPS_INS_FTQ, - MIPS_INS_FTRUNC_S, - MIPS_INS_FTRUNC_U, - MIPS_INS_HADD_S, - MIPS_INS_HADD_U, - MIPS_INS_HSUB_S, - MIPS_INS_HSUB_U, - MIPS_INS_ILVEV, - MIPS_INS_ILVL, - MIPS_INS_ILVOD, - MIPS_INS_ILVR, - MIPS_INS_INS, - MIPS_INS_INSERT, - MIPS_INS_INSV, - MIPS_INS_INSVE, - MIPS_INS_J, - MIPS_INS_JAL, - MIPS_INS_JALR, - MIPS_INS_JALRS16, - MIPS_INS_JALRS, - MIPS_INS_JALS, - MIPS_INS_JALX, - MIPS_INS_JIALC, - MIPS_INS_JIC, - MIPS_INS_JR, - MIPS_INS_JR16, - MIPS_INS_JRADDIUSP, - MIPS_INS_JRC, - MIPS_INS_JALRC, - MIPS_INS_LB, - MIPS_INS_LBU16, - MIPS_INS_LBUX, - MIPS_INS_LBU, - MIPS_INS_LD, - MIPS_INS_LDC1, - MIPS_INS_LDC2, - MIPS_INS_LDC3, - MIPS_INS_LDI, - MIPS_INS_LDL, - MIPS_INS_LDPC, - MIPS_INS_LDR, - MIPS_INS_LDXC1, - MIPS_INS_LH, - MIPS_INS_LHU16, - MIPS_INS_LHX, - MIPS_INS_LHU, - MIPS_INS_LI16, - MIPS_INS_LL, - MIPS_INS_LLD, - MIPS_INS_LSA, - MIPS_INS_LUXC1, - MIPS_INS_LUI, - MIPS_INS_LW, - MIPS_INS_LW16, - MIPS_INS_LWC1, - MIPS_INS_LWC2, - MIPS_INS_LWC3, - MIPS_INS_LWL, - MIPS_INS_LWM16, - MIPS_INS_LWM32, - MIPS_INS_LWPC, - MIPS_INS_LWP, - MIPS_INS_LWR, - MIPS_INS_LWUPC, - MIPS_INS_LWU, - MIPS_INS_LWX, - MIPS_INS_LWXC1, - MIPS_INS_LWXS, - MIPS_INS_LI, - MIPS_INS_MADD, - MIPS_INS_MADDF, - MIPS_INS_MADDR_Q, - MIPS_INS_MADDU, - MIPS_INS_MADDV, - MIPS_INS_MADD_Q, - MIPS_INS_MAQ_SA, - MIPS_INS_MAQ_S, - MIPS_INS_MAXA, - MIPS_INS_MAXI_S, - MIPS_INS_MAXI_U, - MIPS_INS_MAX_A, - MIPS_INS_MAX, - MIPS_INS_MAX_S, - MIPS_INS_MAX_U, - MIPS_INS_MFC0, - MIPS_INS_MFC1, - MIPS_INS_MFC2, - MIPS_INS_MFHC1, - MIPS_INS_MFHI, - MIPS_INS_MFLO, - MIPS_INS_MINA, - MIPS_INS_MINI_S, - MIPS_INS_MINI_U, - MIPS_INS_MIN_A, - MIPS_INS_MIN, - MIPS_INS_MIN_S, - MIPS_INS_MIN_U, - MIPS_INS_MOD, - MIPS_INS_MODSUB, - MIPS_INS_MODU, - MIPS_INS_MOD_S, - MIPS_INS_MOD_U, - MIPS_INS_MOVE, - MIPS_INS_MOVEP, - MIPS_INS_MOVF, - MIPS_INS_MOVN, - MIPS_INS_MOVT, - MIPS_INS_MOVZ, - MIPS_INS_MSUB, - MIPS_INS_MSUBF, - MIPS_INS_MSUBR_Q, - MIPS_INS_MSUBU, - MIPS_INS_MSUBV, - MIPS_INS_MSUB_Q, - MIPS_INS_MTC0, - MIPS_INS_MTC1, - MIPS_INS_MTC2, - MIPS_INS_MTHC1, - MIPS_INS_MTHI, - MIPS_INS_MTHLIP, - MIPS_INS_MTLO, - MIPS_INS_MTM0, - MIPS_INS_MTM1, - MIPS_INS_MTM2, - MIPS_INS_MTP0, - MIPS_INS_MTP1, - MIPS_INS_MTP2, - MIPS_INS_MUH, - MIPS_INS_MUHU, - MIPS_INS_MULEQ_S, - MIPS_INS_MULEU_S, - MIPS_INS_MULQ_RS, - MIPS_INS_MULQ_S, - MIPS_INS_MULR_Q, - MIPS_INS_MULSAQ_S, - MIPS_INS_MULSA, - MIPS_INS_MULT, - MIPS_INS_MULTU, - MIPS_INS_MULU, - MIPS_INS_MULV, - MIPS_INS_MUL_Q, - MIPS_INS_MUL_S, - MIPS_INS_NLOC, - MIPS_INS_NLZC, - MIPS_INS_NMADD, - MIPS_INS_NMSUB, - MIPS_INS_NOR, - MIPS_INS_NORI, - MIPS_INS_NOT16, - MIPS_INS_NOT, - MIPS_INS_OR, - MIPS_INS_OR16, - MIPS_INS_ORI, - MIPS_INS_PACKRL, - MIPS_INS_PAUSE, - MIPS_INS_PCKEV, - MIPS_INS_PCKOD, - MIPS_INS_PCNT, - MIPS_INS_PICK, - MIPS_INS_POP, - MIPS_INS_PRECEQU, - MIPS_INS_PRECEQ, - MIPS_INS_PRECEU, - MIPS_INS_PRECRQU_S, - MIPS_INS_PRECRQ, - MIPS_INS_PRECRQ_RS, - MIPS_INS_PRECR, - MIPS_INS_PRECR_SRA, - MIPS_INS_PRECR_SRA_R, - MIPS_INS_PREF, - MIPS_INS_PREPEND, - MIPS_INS_RADDU, - MIPS_INS_RDDSP, - MIPS_INS_RDHWR, - MIPS_INS_REPLV, - MIPS_INS_REPL, - MIPS_INS_RINT, - MIPS_INS_ROTR, - MIPS_INS_ROTRV, - MIPS_INS_ROUND, - MIPS_INS_SAT_S, - MIPS_INS_SAT_U, - MIPS_INS_SB, - MIPS_INS_SB16, - MIPS_INS_SC, - MIPS_INS_SCD, - MIPS_INS_SD, - MIPS_INS_SDBBP, - MIPS_INS_SDBBP16, - MIPS_INS_SDC1, - MIPS_INS_SDC2, - MIPS_INS_SDC3, - MIPS_INS_SDL, - MIPS_INS_SDR, - MIPS_INS_SDXC1, - MIPS_INS_SEB, - MIPS_INS_SEH, - MIPS_INS_SELEQZ, - MIPS_INS_SELNEZ, - MIPS_INS_SEL, - MIPS_INS_SEQ, - MIPS_INS_SEQI, - MIPS_INS_SH, - MIPS_INS_SH16, - MIPS_INS_SHF, - MIPS_INS_SHILO, - MIPS_INS_SHILOV, - MIPS_INS_SHLLV, - MIPS_INS_SHLLV_S, - MIPS_INS_SHLL, - MIPS_INS_SHLL_S, - MIPS_INS_SHRAV, - MIPS_INS_SHRAV_R, - MIPS_INS_SHRA, - MIPS_INS_SHRA_R, - MIPS_INS_SHRLV, - MIPS_INS_SHRL, - MIPS_INS_SLDI, - MIPS_INS_SLD, - MIPS_INS_SLL, - MIPS_INS_SLL16, - MIPS_INS_SLLI, - MIPS_INS_SLLV, - MIPS_INS_SLT, - MIPS_INS_SLTI, - MIPS_INS_SLTIU, - MIPS_INS_SLTU, - MIPS_INS_SNE, - MIPS_INS_SNEI, - MIPS_INS_SPLATI, - MIPS_INS_SPLAT, - MIPS_INS_SRA, - MIPS_INS_SRAI, - MIPS_INS_SRARI, - MIPS_INS_SRAR, - MIPS_INS_SRAV, - MIPS_INS_SRL, - MIPS_INS_SRL16, - MIPS_INS_SRLI, - MIPS_INS_SRLRI, - MIPS_INS_SRLR, - MIPS_INS_SRLV, - MIPS_INS_SSNOP, - MIPS_INS_ST, - MIPS_INS_SUBQH, - MIPS_INS_SUBQH_R, - MIPS_INS_SUBQ, - MIPS_INS_SUBQ_S, - MIPS_INS_SUBSUS_U, - MIPS_INS_SUBSUU_S, - MIPS_INS_SUBS_S, - MIPS_INS_SUBS_U, - MIPS_INS_SUBU16, - MIPS_INS_SUBUH, - MIPS_INS_SUBUH_R, - MIPS_INS_SUBU, - MIPS_INS_SUBU_S, - MIPS_INS_SUBVI, - MIPS_INS_SUBV, - MIPS_INS_SUXC1, - MIPS_INS_SW, - MIPS_INS_SW16, - MIPS_INS_SWC1, - MIPS_INS_SWC2, - MIPS_INS_SWC3, - MIPS_INS_SWL, - MIPS_INS_SWM16, - MIPS_INS_SWM32, - MIPS_INS_SWP, - MIPS_INS_SWR, - MIPS_INS_SWXC1, - MIPS_INS_SYNC, - MIPS_INS_SYNCI, - MIPS_INS_SYSCALL, - MIPS_INS_TEQ, - MIPS_INS_TEQI, - MIPS_INS_TGE, - MIPS_INS_TGEI, - MIPS_INS_TGEIU, - MIPS_INS_TGEU, - MIPS_INS_TLBP, - MIPS_INS_TLBR, - MIPS_INS_TLBWI, - MIPS_INS_TLBWR, - MIPS_INS_TLT, - MIPS_INS_TLTI, - MIPS_INS_TLTIU, - MIPS_INS_TLTU, - MIPS_INS_TNE, - MIPS_INS_TNEI, - MIPS_INS_TRUNC, - MIPS_INS_V3MULU, - MIPS_INS_VMM0, - MIPS_INS_VMULU, - MIPS_INS_VSHF, - MIPS_INS_WAIT, - MIPS_INS_WRDSP, - MIPS_INS_WSBH, - MIPS_INS_XOR, - MIPS_INS_XOR16, - MIPS_INS_XORI, - - //> some alias instructions - MIPS_INS_NOP, - MIPS_INS_NEGU, - - //> special instructions - MIPS_INS_JALR_HB, // jump and link with Hazard Barrier - MIPS_INS_JR_HB, // jump register with Hazard Barrier - - MIPS_INS_ENDING, + MIPS_INS_INVALID = 0, + MIPS_INS_ABS, + MIPS_INS_ABSQ_S, + MIPS_INS_ADD, + MIPS_INS_ADDI, + MIPS_INS_ADDIU, + MIPS_INS_ADDIUPC, + MIPS_INS_ADDIUR1SP, + MIPS_INS_ADDIUR2, + MIPS_INS_ADDIUS5, + MIPS_INS_ADDIUSP, + MIPS_INS_ADDQ, + MIPS_INS_ADDQH, + MIPS_INS_ADDQH_R, + MIPS_INS_ADDQ_S, + MIPS_INS_ADDR, + MIPS_INS_ADDSC, + MIPS_INS_ADDS_A, + MIPS_INS_ADDS_S, + MIPS_INS_ADDS_U, + MIPS_INS_ADDU, + MIPS_INS_ADDU16, + MIPS_INS_ADDUH, + MIPS_INS_ADDUH_R, + MIPS_INS_ADDU_S, + MIPS_INS_ADDV, + MIPS_INS_ADDVI, + MIPS_INS_ADDWC, + MIPS_INS_ADD_A, + MIPS_INS_ALIGN, + MIPS_INS_ALUIPC, + MIPS_INS_AND, + MIPS_INS_AND16, + MIPS_INS_ANDI, + MIPS_INS_ANDI16, + MIPS_INS_APPEND, + MIPS_INS_ASUB_S, + MIPS_INS_ASUB_U, + MIPS_INS_AUI, + MIPS_INS_AUIPC, + MIPS_INS_AVER_S, + MIPS_INS_AVER_U, + MIPS_INS_AVE_S, + MIPS_INS_AVE_U, + MIPS_INS_B, + MIPS_INS_B16, + MIPS_INS_BADDU, + MIPS_INS_BAL, + MIPS_INS_BALC, + MIPS_INS_BALIGN, + MIPS_INS_BBIT0, + MIPS_INS_BBIT032, + MIPS_INS_BBIT1, + MIPS_INS_BBIT132, + MIPS_INS_BC, + MIPS_INS_BC16, + MIPS_INS_BC1EQZ, + MIPS_INS_BC1EQZC, + MIPS_INS_BC1F, + MIPS_INS_BC1FL, + MIPS_INS_BC1NEZ, + MIPS_INS_BC1NEZC, + MIPS_INS_BC1T, + MIPS_INS_BC1TL, + MIPS_INS_BC2EQZ, + MIPS_INS_BC2EQZC, + MIPS_INS_BC2NEZ, + MIPS_INS_BC2NEZC, + MIPS_INS_BCLR, + MIPS_INS_BCLRI, + MIPS_INS_BEQ, + MIPS_INS_BEQC, + MIPS_INS_BEQL, + MIPS_INS_BEQZ, + MIPS_INS_BEQZ16, + MIPS_INS_BEQZALC, + MIPS_INS_BEQZC, + MIPS_INS_BEQZC16, + MIPS_INS_BEQZL, + MIPS_INS_BGE, + MIPS_INS_BGEC, + MIPS_INS_BGEL, + MIPS_INS_BGEU, + MIPS_INS_BGEUC, + MIPS_INS_BGEUL, + MIPS_INS_BGEZ, + MIPS_INS_BGEZAL, + MIPS_INS_BGEZALC, + MIPS_INS_BGEZALL, + MIPS_INS_BGEZALS, + MIPS_INS_BGEZC, + MIPS_INS_BGEZL, + MIPS_INS_BGT, + MIPS_INS_BGTL, + MIPS_INS_BGTU, + MIPS_INS_BGTUL, + MIPS_INS_BGTZ, + MIPS_INS_BGTZALC, + MIPS_INS_BGTZC, + MIPS_INS_BGTZL, + MIPS_INS_BINSL, + MIPS_INS_BINSLI, + MIPS_INS_BINSR, + MIPS_INS_BINSRI, + MIPS_INS_BITREV, + MIPS_INS_BITSWAP, + MIPS_INS_BLE, + MIPS_INS_BLEL, + MIPS_INS_BLEU, + MIPS_INS_BLEUL, + MIPS_INS_BLEZ, + MIPS_INS_BLEZALC, + MIPS_INS_BLEZC, + MIPS_INS_BLEZL, + MIPS_INS_BLT, + MIPS_INS_BLTC, + MIPS_INS_BLTL, + MIPS_INS_BLTU, + MIPS_INS_BLTUC, + MIPS_INS_BLTUL, + MIPS_INS_BLTZ, + MIPS_INS_BLTZAL, + MIPS_INS_BLTZALC, + MIPS_INS_BLTZALL, + MIPS_INS_BLTZALS, + MIPS_INS_BLTZC, + MIPS_INS_BLTZL, + MIPS_INS_BMNZ, + MIPS_INS_BMNZI, + MIPS_INS_BMZ, + MIPS_INS_BMZI, + MIPS_INS_BNE, + MIPS_INS_BNEC, + MIPS_INS_BNEG, + MIPS_INS_BNEGI, + MIPS_INS_BNEL, + MIPS_INS_BNEZ, + MIPS_INS_BNEZ16, + MIPS_INS_BNEZALC, + MIPS_INS_BNEZC, + MIPS_INS_BNEZC16, + MIPS_INS_BNEZL, + MIPS_INS_BNVC, + MIPS_INS_BNZ, + MIPS_INS_BOVC, + MIPS_INS_BPOSGE32, + MIPS_INS_BPOSGE32C, + MIPS_INS_BREAK, + MIPS_INS_BREAK16, + MIPS_INS_BSEL, + MIPS_INS_BSELI, + MIPS_INS_BSET, + MIPS_INS_BSETI, + MIPS_INS_BTEQZ, + MIPS_INS_BTNEZ, + MIPS_INS_BZ, + MIPS_INS_C, + MIPS_INS_CACHE, + MIPS_INS_CACHEE, + MIPS_INS_CEIL, + MIPS_INS_CEQ, + MIPS_INS_CEQI, + MIPS_INS_CFC1, + MIPS_INS_CFC2, + MIPS_INS_CFCMSA, + MIPS_INS_CFTC1, + MIPS_INS_CINS, + MIPS_INS_CINS32, + MIPS_INS_CLASS, + MIPS_INS_CLEI_S, + MIPS_INS_CLEI_U, + MIPS_INS_CLE_S, + MIPS_INS_CLE_U, + MIPS_INS_CLO, + MIPS_INS_CLTI_S, + MIPS_INS_CLTI_U, + MIPS_INS_CLT_S, + MIPS_INS_CLT_U, + MIPS_INS_CLZ, + MIPS_INS_CMP, + MIPS_INS_CMPGDU, + MIPS_INS_CMPGU, + MIPS_INS_CMPI, + MIPS_INS_CMPU, + MIPS_INS_COPY_S, + MIPS_INS_COPY_U, + MIPS_INS_CRC32B, + MIPS_INS_CRC32CB, + MIPS_INS_CRC32CD, + MIPS_INS_CRC32CH, + MIPS_INS_CRC32CW, + MIPS_INS_CRC32D, + MIPS_INS_CRC32H, + MIPS_INS_CRC32W, + MIPS_INS_CTC1, + MIPS_INS_CTC2, + MIPS_INS_CTCMSA, + MIPS_INS_CTTC1, + MIPS_INS_CVT, + MIPS_INS_DADD, + MIPS_INS_DADDI, + MIPS_INS_DADDIU, + MIPS_INS_DADDU, + MIPS_INS_DAHI, + MIPS_INS_DALIGN, + MIPS_INS_DATI, + MIPS_INS_DAUI, + MIPS_INS_DBITSWAP, + MIPS_INS_DCLO, + MIPS_INS_DCLZ, + MIPS_INS_DDIV, + MIPS_INS_DDIVU, + MIPS_INS_DERET, + MIPS_INS_DEXT, + MIPS_INS_DEXTM, + MIPS_INS_DEXTU, + MIPS_INS_DI, + MIPS_INS_DINS, + MIPS_INS_DINSM, + MIPS_INS_DINSU, + MIPS_INS_DIV, + MIPS_INS_DIVU, + MIPS_INS_DIV_S, + MIPS_INS_DIV_U, + MIPS_INS_DLA, + MIPS_INS_DLI, + MIPS_INS_DLSA, + MIPS_INS_DMFC0, + MIPS_INS_DMFC1, + MIPS_INS_DMFC2, + MIPS_INS_DMFGC0, + MIPS_INS_DMOD, + MIPS_INS_DMODU, + MIPS_INS_DMT, + MIPS_INS_DMTC0, + MIPS_INS_DMTC1, + MIPS_INS_DMTC2, + MIPS_INS_DMTGC0, + MIPS_INS_DMUH, + MIPS_INS_DMUHU, + MIPS_INS_DMUL, + MIPS_INS_DMULO, + MIPS_INS_DMULOU, + MIPS_INS_DMULT, + MIPS_INS_DMULTU, + MIPS_INS_DMULU, + MIPS_INS_DNEG, + MIPS_INS_DNEGU, + MIPS_INS_DOTP_S, + MIPS_INS_DOTP_U, + MIPS_INS_DPA, + MIPS_INS_DPADD_S, + MIPS_INS_DPADD_U, + MIPS_INS_DPAQX_S, + MIPS_INS_DPAQX_SA, + MIPS_INS_DPAQ_S, + MIPS_INS_DPAQ_SA, + MIPS_INS_DPAU, + MIPS_INS_DPAX, + MIPS_INS_DPOP, + MIPS_INS_DPS, + MIPS_INS_DPSQX_S, + MIPS_INS_DPSQX_SA, + MIPS_INS_DPSQ_S, + MIPS_INS_DPSQ_SA, + MIPS_INS_DPSU, + MIPS_INS_DPSUB_S, + MIPS_INS_DPSUB_U, + MIPS_INS_DPSX, + MIPS_INS_DREM, + MIPS_INS_DREMU, + MIPS_INS_DROL, + MIPS_INS_DROR, + MIPS_INS_DROTR, + MIPS_INS_DROTR32, + MIPS_INS_DROTRV, + MIPS_INS_DSBH, + MIPS_INS_DSHD, + MIPS_INS_DSLL, + MIPS_INS_DSLL32, + MIPS_INS_DSLLV, + MIPS_INS_DSRA, + MIPS_INS_DSRA32, + MIPS_INS_DSRAV, + MIPS_INS_DSRL, + MIPS_INS_DSRL32, + MIPS_INS_DSRLV, + MIPS_INS_DSUB, + MIPS_INS_DSUBI, + MIPS_INS_DSUBU, + MIPS_INS_DVP, + MIPS_INS_DVPE, + MIPS_INS_EHB, + MIPS_INS_EI, + MIPS_INS_EMT, + MIPS_INS_ERET, + MIPS_INS_ERETNC, + MIPS_INS_EVP, + MIPS_INS_EVPE, + MIPS_INS_EXT, + MIPS_INS_EXTP, + MIPS_INS_EXTPDP, + MIPS_INS_EXTPDPV, + MIPS_INS_EXTPV, + MIPS_INS_EXTR, + MIPS_INS_EXTRV, + MIPS_INS_EXTRV_R, + MIPS_INS_EXTRV_RS, + MIPS_INS_EXTRV_S, + MIPS_INS_EXTR_R, + MIPS_INS_EXTR_RS, + MIPS_INS_EXTR_S, + MIPS_INS_EXTS, + MIPS_INS_EXTS32, + MIPS_INS_FADD, + MIPS_INS_FCAF, + MIPS_INS_FCEQ, + MIPS_INS_FCLASS, + MIPS_INS_FCLE, + MIPS_INS_FCLT, + MIPS_INS_FCNE, + MIPS_INS_FCOR, + MIPS_INS_FCUEQ, + MIPS_INS_FCULE, + MIPS_INS_FCULT, + MIPS_INS_FCUN, + MIPS_INS_FCUNE, + MIPS_INS_FDIV, + MIPS_INS_FEXDO, + MIPS_INS_FEXP2, + MIPS_INS_FEXUPL, + MIPS_INS_FEXUPR, + MIPS_INS_FFINT_S, + MIPS_INS_FFINT_U, + MIPS_INS_FFQL, + MIPS_INS_FFQR, + MIPS_INS_FILL, + MIPS_INS_FLOG2, + MIPS_INS_FLOOR, + MIPS_INS_FMADD, + MIPS_INS_FMAX, + MIPS_INS_FMAX_A, + MIPS_INS_FMIN, + MIPS_INS_FMIN_A, + MIPS_INS_FMSUB, + MIPS_INS_FMUL, + MIPS_INS_FORK, + MIPS_INS_FRCP, + MIPS_INS_FRINT, + MIPS_INS_FRSQRT, + MIPS_INS_FSAF, + MIPS_INS_FSEQ, + MIPS_INS_FSLE, + MIPS_INS_FSLT, + MIPS_INS_FSNE, + MIPS_INS_FSOR, + MIPS_INS_FSQRT, + MIPS_INS_FSUB, + MIPS_INS_FSUEQ, + MIPS_INS_FSULE, + MIPS_INS_FSULT, + MIPS_INS_FSUN, + MIPS_INS_FSUNE, + MIPS_INS_FTINT_S, + MIPS_INS_FTINT_U, + MIPS_INS_FTQ, + MIPS_INS_FTRUNC_S, + MIPS_INS_FTRUNC_U, + MIPS_INS_GINVI, + MIPS_INS_GINVT, + MIPS_INS_HADD_S, + MIPS_INS_HADD_U, + MIPS_INS_HSUB_S, + MIPS_INS_HSUB_U, + MIPS_INS_HYPCALL, + MIPS_INS_ILVEV, + MIPS_INS_ILVL, + MIPS_INS_ILVOD, + MIPS_INS_ILVR, + MIPS_INS_INS, + MIPS_INS_INSERT, + MIPS_INS_INSV, + MIPS_INS_INSVE, + MIPS_INS_J, + MIPS_INS_JAL, + MIPS_INS_JALR, + MIPS_INS_JALRC, + MIPS_INS_JALRS, + MIPS_INS_JALRS16, + MIPS_INS_JALS, + MIPS_INS_JALX, + MIPS_INS_JIALC, + MIPS_INS_JIC, + MIPS_INS_JR, + MIPS_INS_JR16, + MIPS_INS_JRADDIUSP, + MIPS_INS_JRC, + MIPS_INS_JRC16, + MIPS_INS_JRCADDIUSP, + MIPS_INS_L, + MIPS_INS_LA, + MIPS_INS_LAPC, + MIPS_INS_LB, + MIPS_INS_LBE, + MIPS_INS_LBU, + MIPS_INS_LBU16, + MIPS_INS_LBUE, + MIPS_INS_LBUX, + MIPS_INS_LD, + MIPS_INS_LDC1, + MIPS_INS_LDC2, + MIPS_INS_LDC3, + MIPS_INS_LDI, + MIPS_INS_LDL, + MIPS_INS_LDPC, + MIPS_INS_LDR, + MIPS_INS_LDXC1, + MIPS_INS_LH, + MIPS_INS_LHE, + MIPS_INS_LHU, + MIPS_INS_LHU16, + MIPS_INS_LHUE, + MIPS_INS_LHX, + MIPS_INS_LI, + MIPS_INS_LI16, + MIPS_INS_LL, + MIPS_INS_LLD, + MIPS_INS_LLE, + MIPS_INS_LSA, + MIPS_INS_LUI, + MIPS_INS_LUXC1, + MIPS_INS_LW, + MIPS_INS_LW16, + MIPS_INS_LWC1, + MIPS_INS_LWC2, + MIPS_INS_LWC3, + MIPS_INS_LWE, + MIPS_INS_LWL, + MIPS_INS_LWLE, + MIPS_INS_LWM, + MIPS_INS_LWM16, + MIPS_INS_LWM32, + MIPS_INS_LWP, + MIPS_INS_LWPC, + MIPS_INS_LWR, + MIPS_INS_LWRE, + MIPS_INS_LWU, + MIPS_INS_LWUPC, + MIPS_INS_LWX, + MIPS_INS_LWXC1, + MIPS_INS_LWXS, + MIPS_INS_MADD, + MIPS_INS_MADDF, + MIPS_INS_MADDR_Q, + MIPS_INS_MADDU, + MIPS_INS_MADDV, + MIPS_INS_MADD_Q, + MIPS_INS_MAQ_S, + MIPS_INS_MAQ_SA, + MIPS_INS_MAX, + MIPS_INS_MAXA, + MIPS_INS_MAXI_S, + MIPS_INS_MAXI_U, + MIPS_INS_MAX_A, + MIPS_INS_MAX_S, + MIPS_INS_MAX_U, + MIPS_INS_MFC0, + MIPS_INS_MFC1, + MIPS_INS_MFC2, + MIPS_INS_MFGC0, + MIPS_INS_MFHC0, + MIPS_INS_MFHC1, + MIPS_INS_MFHC2, + MIPS_INS_MFHGC0, + MIPS_INS_MFHI, + MIPS_INS_MFHI16, + MIPS_INS_MFLO, + MIPS_INS_MFLO16, + MIPS_INS_MFTACX, + MIPS_INS_MFTC0, + MIPS_INS_MFTC1, + MIPS_INS_MFTDSP, + MIPS_INS_MFTGPR, + MIPS_INS_MFTHC1, + MIPS_INS_MFTHI, + MIPS_INS_MFTLO, + MIPS_INS_MFTR, + MIPS_INS_MIN, + MIPS_INS_MINA, + MIPS_INS_MINI_S, + MIPS_INS_MINI_U, + MIPS_INS_MIN_A, + MIPS_INS_MIN_S, + MIPS_INS_MIN_U, + MIPS_INS_MOD, + MIPS_INS_MODSUB, + MIPS_INS_MODU, + MIPS_INS_MOD_S, + MIPS_INS_MOD_U, + MIPS_INS_MOV, + MIPS_INS_MOVE, + MIPS_INS_MOVE16, + MIPS_INS_MOVEP, + MIPS_INS_MOVF, + MIPS_INS_MOVN, + MIPS_INS_MOVT, + MIPS_INS_MOVZ, + MIPS_INS_MSUB, + MIPS_INS_MSUBF, + MIPS_INS_MSUBR_Q, + MIPS_INS_MSUBU, + MIPS_INS_MSUBV, + MIPS_INS_MSUB_Q, + MIPS_INS_MTC0, + MIPS_INS_MTC1, + MIPS_INS_MTC2, + MIPS_INS_MTGC0, + MIPS_INS_MTHC0, + MIPS_INS_MTHC1, + MIPS_INS_MTHC2, + MIPS_INS_MTHGC0, + MIPS_INS_MTHI, + MIPS_INS_MTHLIP, + MIPS_INS_MTLO, + MIPS_INS_MTM0, + MIPS_INS_MTM1, + MIPS_INS_MTM2, + MIPS_INS_MTP0, + MIPS_INS_MTP1, + MIPS_INS_MTP2, + MIPS_INS_MTTACX, + MIPS_INS_MTTC0, + MIPS_INS_MTTC1, + MIPS_INS_MTTDSP, + MIPS_INS_MTTGPR, + MIPS_INS_MTTHC1, + MIPS_INS_MTTHI, + MIPS_INS_MTTLO, + MIPS_INS_MTTR, + MIPS_INS_MUH, + MIPS_INS_MUHU, + MIPS_INS_MUL, + MIPS_INS_MULEQ_S, + MIPS_INS_MULEU_S, + MIPS_INS_MULO, + MIPS_INS_MULOU, + MIPS_INS_MULQ_RS, + MIPS_INS_MULQ_S, + MIPS_INS_MULR, + MIPS_INS_MULR_Q, + MIPS_INS_MULSA, + MIPS_INS_MULSAQ_S, + MIPS_INS_MULT, + MIPS_INS_MULTU, + MIPS_INS_MULU, + MIPS_INS_MULV, + MIPS_INS_MUL_Q, + MIPS_INS_MUL_S, + MIPS_INS_NEG, + MIPS_INS_NEGU, + MIPS_INS_NLOC, + MIPS_INS_NLZC, + MIPS_INS_NMADD, + MIPS_INS_NMSUB, + MIPS_INS_NOP, + MIPS_INS_NOR, + MIPS_INS_NORI, + MIPS_INS_NOT, + MIPS_INS_NOT16, + MIPS_INS_OR, + MIPS_INS_OR16, + MIPS_INS_ORI, + MIPS_INS_PACKRL, + MIPS_INS_PAUSE, + MIPS_INS_PCKEV, + MIPS_INS_PCKOD, + MIPS_INS_PCNT, + MIPS_INS_PICK, + MIPS_INS_PLL, + MIPS_INS_PLU, + MIPS_INS_POP, + MIPS_INS_PRECEQ, + MIPS_INS_PRECEQU, + MIPS_INS_PRECEU, + MIPS_INS_PRECR, + MIPS_INS_PRECRQ, + MIPS_INS_PRECRQU_S, + MIPS_INS_PRECRQ_RS, + MIPS_INS_PRECR_SRA, + MIPS_INS_PRECR_SRA_R, + MIPS_INS_PREF, + MIPS_INS_PREFE, + MIPS_INS_PREFX, + MIPS_INS_PREPEND, + MIPS_INS_PUL, + MIPS_INS_PUU, + MIPS_INS_RADDU, + MIPS_INS_RDDSP, + MIPS_INS_RDHWR, + MIPS_INS_RDPGPR, + MIPS_INS_RECIP, + MIPS_INS_REM, + MIPS_INS_REMU, + MIPS_INS_REPL, + MIPS_INS_REPLV, + MIPS_INS_RINT, + MIPS_INS_ROL, + MIPS_INS_ROR, + MIPS_INS_ROTR, + MIPS_INS_ROTRV, + MIPS_INS_ROUND, + MIPS_INS_RSQRT, + MIPS_INS_S, + MIPS_INS_SAA, + MIPS_INS_SAAD, + MIPS_INS_SAT_S, + MIPS_INS_SAT_U, + MIPS_INS_SB, + MIPS_INS_SB16, + MIPS_INS_SBE, + MIPS_INS_SC, + MIPS_INS_SCD, + MIPS_INS_SCE, + MIPS_INS_SD, + MIPS_INS_SDBBP, + MIPS_INS_SDBBP16, + MIPS_INS_SDC1, + MIPS_INS_SDC2, + MIPS_INS_SDC3, + MIPS_INS_SDL, + MIPS_INS_SDR, + MIPS_INS_SDXC1, + MIPS_INS_SEB, + MIPS_INS_SEH, + MIPS_INS_SEL, + MIPS_INS_SELEQZ, + MIPS_INS_SELNEZ, + MIPS_INS_SEQ, + MIPS_INS_SEQI, + MIPS_INS_SGE, + MIPS_INS_SGEU, + MIPS_INS_SGT, + MIPS_INS_SGTU, + MIPS_INS_SH, + MIPS_INS_SH16, + MIPS_INS_SHE, + MIPS_INS_SHF, + MIPS_INS_SHILO, + MIPS_INS_SHILOV, + MIPS_INS_SHLL, + MIPS_INS_SHLLV, + MIPS_INS_SHLLV_S, + MIPS_INS_SHLL_S, + MIPS_INS_SHRA, + MIPS_INS_SHRAV, + MIPS_INS_SHRAV_R, + MIPS_INS_SHRA_R, + MIPS_INS_SHRL, + MIPS_INS_SHRLV, + MIPS_INS_SIGRIE, + MIPS_INS_SLD, + MIPS_INS_SLDI, + MIPS_INS_SLE, + MIPS_INS_SLEU, + MIPS_INS_SLL, + MIPS_INS_SLL16, + MIPS_INS_SLLI, + MIPS_INS_SLLV, + MIPS_INS_SLT, + MIPS_INS_SLTI, + MIPS_INS_SLTIU, + MIPS_INS_SLTU, + MIPS_INS_SNE, + MIPS_INS_SNEI, + MIPS_INS_SPLAT, + MIPS_INS_SPLATI, + MIPS_INS_SQRT, + MIPS_INS_SRA, + MIPS_INS_SRAI, + MIPS_INS_SRAR, + MIPS_INS_SRARI, + MIPS_INS_SRAV, + MIPS_INS_SRL, + MIPS_INS_SRL16, + MIPS_INS_SRLI, + MIPS_INS_SRLR, + MIPS_INS_SRLRI, + MIPS_INS_SRLV, + MIPS_INS_SSNOP, + MIPS_INS_ST, + MIPS_INS_SUB, + MIPS_INS_SUBQ, + MIPS_INS_SUBQH, + MIPS_INS_SUBQH_R, + MIPS_INS_SUBQ_S, + MIPS_INS_SUBSUS_U, + MIPS_INS_SUBSUU_S, + MIPS_INS_SUBS_S, + MIPS_INS_SUBS_U, + MIPS_INS_SUBU, + MIPS_INS_SUBU16, + MIPS_INS_SUBUH, + MIPS_INS_SUBUH_R, + MIPS_INS_SUBU_S, + MIPS_INS_SUBV, + MIPS_INS_SUBVI, + MIPS_INS_SUXC1, + MIPS_INS_SW, + MIPS_INS_SW16, + MIPS_INS_SWC1, + MIPS_INS_SWC2, + MIPS_INS_SWC3, + MIPS_INS_SWE, + MIPS_INS_SWL, + MIPS_INS_SWLE, + MIPS_INS_SWM, + MIPS_INS_SWM16, + MIPS_INS_SWM32, + MIPS_INS_SWP, + MIPS_INS_SWR, + MIPS_INS_SWRE, + MIPS_INS_SWSP, + MIPS_INS_SWXC1, + MIPS_INS_SYNC, + MIPS_INS_SYNCI, + MIPS_INS_SYNCIOBDMA, + MIPS_INS_SYNCS, + MIPS_INS_SYNCW, + MIPS_INS_SYNCWS, + MIPS_INS_SYSCALL, + MIPS_INS_TEQ, + MIPS_INS_TEQI, + MIPS_INS_TGE, + MIPS_INS_TGEI, + MIPS_INS_TGEIU, + MIPS_INS_TGEU, + MIPS_INS_TLBGINV, + MIPS_INS_TLBGINVF, + MIPS_INS_TLBGP, + MIPS_INS_TLBGR, + MIPS_INS_TLBGWI, + MIPS_INS_TLBGWR, + MIPS_INS_TLBINV, + MIPS_INS_TLBINVF, + MIPS_INS_TLBP, + MIPS_INS_TLBR, + MIPS_INS_TLBWI, + MIPS_INS_TLBWR, + MIPS_INS_TLT, + MIPS_INS_TLTI, + MIPS_INS_TLTIU, + MIPS_INS_TLTU, + MIPS_INS_TNE, + MIPS_INS_TNEI, + MIPS_INS_TRUNC, + MIPS_INS_ULH, + MIPS_INS_ULHU, + MIPS_INS_ULW, + MIPS_INS_USH, + MIPS_INS_USW, + MIPS_INS_V3MULU, + MIPS_INS_VMM0, + MIPS_INS_VMULU, + MIPS_INS_VSHF, + MIPS_INS_WAIT, + MIPS_INS_WRDSP, + MIPS_INS_WRPGPR, + MIPS_INS_WSBH, + MIPS_INS_XOR, + MIPS_INS_XOR16, + MIPS_INS_XORI, + MIPS_INS_YIELD, + + MIPS_INS_ENDING, } mips_insn; /// Group of MIPS instructions typedef enum mips_insn_group { - MIPS_GRP_INVALID = 0, ///< = CS_GRP_INVALID - - // Generic groups - // all jump instructions (conditional+direct+indirect jumps) - MIPS_GRP_JUMP, ///< = CS_GRP_JUMP - // all call instructions - MIPS_GRP_CALL, ///< = CS_GRP_CALL - // all return instructions - MIPS_GRP_RET, ///< = CS_GRP_RET - // all interrupt instructions (int+syscall) - MIPS_GRP_INT, ///< = CS_GRP_INT - // all interrupt return instructions - MIPS_GRP_IRET, ///< = CS_GRP_IRET - // all privileged instructions - MIPS_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE - // all relative branching instructions - MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE - - // Architecture-specific groups - MIPS_GRP_BITCOUNT = 128, - MIPS_GRP_DSP, - MIPS_GRP_DSPR2, - MIPS_GRP_FPIDX, - MIPS_GRP_MSA, - MIPS_GRP_MIPS32R2, - MIPS_GRP_MIPS64, - MIPS_GRP_MIPS64R2, - MIPS_GRP_SEINREG, - MIPS_GRP_STDENC, - MIPS_GRP_SWAP, - MIPS_GRP_MICROMIPS, - MIPS_GRP_MIPS16MODE, - MIPS_GRP_FP64BIT, - MIPS_GRP_NONANSFPMATH, - MIPS_GRP_NOTFP64BIT, - MIPS_GRP_NOTINMICROMIPS, - MIPS_GRP_NOTNACL, - MIPS_GRP_NOTMIPS32R6, - MIPS_GRP_NOTMIPS64R6, - MIPS_GRP_CNMIPS, - MIPS_GRP_MIPS32, - MIPS_GRP_MIPS32R6, - MIPS_GRP_MIPS64R6, - MIPS_GRP_MIPS2, - MIPS_GRP_MIPS3, - MIPS_GRP_MIPS3_32, - MIPS_GRP_MIPS3_32R2, - MIPS_GRP_MIPS4_32, - MIPS_GRP_MIPS4_32R2, - MIPS_GRP_MIPS5_32R2, - MIPS_GRP_GP32BIT, - MIPS_GRP_GP64BIT, - - MIPS_GRP_ENDING, + MIPS_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + MIPS_GRP_JUMP, ///< = CS_GRP_JUMP + // all call instructions + MIPS_GRP_CALL, ///< = CS_GRP_CALL + // all return instructions + MIPS_GRP_RET, ///< = CS_GRP_RET + // all interrupt instructions (int+syscall) + MIPS_GRP_INT, ///< = CS_GRP_INT + // all interrupt return instructions + MIPS_GRP_IRET, ///< = CS_GRP_IRET + // all privileged instructions + MIPS_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE + // all relative branching instructions + MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE + + // Architecture-specific groups + MIPS_GRP_BITCOUNT = 128, + MIPS_GRP_DSP, + MIPS_GRP_DSPR2, + MIPS_GRP_FPIDX, + MIPS_GRP_MSA, + MIPS_GRP_MIPS32R2, + MIPS_GRP_MIPS64, + MIPS_GRP_MIPS64R2, + MIPS_GRP_SEINREG, + MIPS_GRP_STDENC, + MIPS_GRP_SWAP, + MIPS_GRP_MICROMIPS, + MIPS_GRP_MIPS16MODE, + MIPS_GRP_FP64BIT, + MIPS_GRP_NONANSFPMATH, + MIPS_GRP_NOTFP64BIT, + MIPS_GRP_NOTINMICROMIPS, + MIPS_GRP_NOTNACL, + MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_CNMIPS, + MIPS_GRP_MIPS32, + MIPS_GRP_MIPS32R6, + MIPS_GRP_MIPS64R6, + MIPS_GRP_MIPS2, + MIPS_GRP_MIPS3, + MIPS_GRP_MIPS3_32, + MIPS_GRP_MIPS3_32R2, + MIPS_GRP_MIPS4_32, + MIPS_GRP_MIPS4_32R2, + MIPS_GRP_MIPS5_32R2, + MIPS_GRP_GP32BIT, + MIPS_GRP_GP64BIT, + + MIPS_GRP_MIPS3D, + MIPS_GRP_DSPR3, + MIPS_GRP_EVA, + MIPS_GRP_CRC, + MIPS_GRP_MT, + MIPS_GRP_MIPS64R5, + MIPS_GRP_VIRT, + MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTCNMIPS, + MIPS_GRP_MIPS32R5, + MIPS_GRP_GINV, + MIPS_GRP_NOINDIRECTJUMPGUARDS, + MIPS_GRP_NOTINMIPS16MODE, + MIPS_GRP_MADD4, + MIPS_GRP_PTR32BIT, + MIPS_GRP_PTR64BIT, + MIPS_GRP_NOTMIPS3, + MIPS_GRP_CNMIPSP, + + MIPS_GRP_ENDING, } mips_insn_group; #ifdef __cplusplus diff --git a/sync/README.md b/sync/README.md new file mode 100644 index 0000000000..78f640f5d7 --- /dev/null +++ b/sync/README.md @@ -0,0 +1,93 @@ +Capstone Syncing +=============== + +This document describes the use of syncing tools and +used as a tracking file for sync progress. + +## How to adapt an architecture with auto-sync + +0. Get a copy of llvm-project source (or all it's architecture files) + +1. Pull the [modified llvm-tblgen backend](https://github.com/rizinorg/llvm-capstone) from +It is recommend that the llvm-project commit matches with the latest mainstream commit from llvm-capstone. + +2. Build the modified backend with target `llvm-tblgen` +```shell +cmake --build ./llvm-project/build --target llvm-tblgen --config Release +``` + +3. Select the architecture from llvm as ARCH +```shell +export $ARCH=Mips +``` + +4. Use `llvm-tblgen` binary to generate the disassembler +```shell +python ./sync/gen-table.py -i ./llvm-project/ -b ./llvm-project/llvm/build/llvm-tblgen ${ARCH} -o ~/Capstone/${ARCH}/${ARCH}GenDisassemblerTables.inc +``` + +Note that the last path varies depending on the location of your Capstone sources. +More information on the TableGen backend see at the [SYNCING](SYNCING.md) document. + +5. Use the `sync/main.py` script from this repo. to generate a disassembler callback file +```shell +python ./sync/main.py ./llvm-project/llvm/lib/Target/$ARCH/Disassembler/${ARCH}Disassembler.cpp \ + > ./Capstone${ARCH}Module.h +``` + +6. Integrate the `Capstone${Arch}Module.h` with corresponding backends in capstone + +for more notes on integration see the `Note on Capstone{Arch}Module.h` chapter below + +7. Truncate the arch's disassembler and instruction printers to make it fit + +This is a rather complicated step and highly depends on the original design of arch, the main idea +is to make it best fit the table-gened file + +## How to sync with LLVM's update once the adaptation is done + +Simple, just repeat the step `4` on the previous chapter and replace the `.inc` file with newly generated one + +## Note on Capstone{Arch}Module.h + +0. ARM & AArch64 from llvm uses feature bits on operand decoding, but capstone ignores them, e.g. +```c++ +const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + +bool hasMP = featureBits[ARM_FeatureMP]; +bool hasV7Ops = featureBits[ARM_HasV7Ops]; +``` +in capstone scene it would simply be +```c +bool hasMP = true; +bool hasV7Ops = true; +``` + +1. The auto-sync python script does not performs well on template functions, so some manual override might be needed + +## Current adaptation progress: + +- [ ] All architectures + - [x] Mips + - [x] ARM + - [x] AArch64 + - [x] Riscv + - [x] PowerPC + - [x] Sparc + - [x] SystemZ + - [ ] ~~TMS320C64x~~ (not supported by LLVM) + - [x] XCore + - [ ] ~~BPF~~ (structurally independent) +- [x] Disassembler +- [x] Instruction Printer +- [ ] Tests +- [ ] Mapping Supports + - [x] Mips +- [ ] Binding Supports + +## Some points that might have to be fixed later + +- [ ] Feature bits +- [ ] Suspicious namespace conflicts +- [ ] PPC QPX ? PPC 64 diff --git a/sync/SYNCING.md b/sync/SYNCING.md new file mode 100644 index 0000000000..34ecd5d741 --- /dev/null +++ b/sync/SYNCING.md @@ -0,0 +1,109 @@ +Capstone Auto-Sync +=============== + +Capstone Auto-Sync is an initiative to partly automate the synchronization of certain architectures to the latest. + +Most of the Capstone's `.inc` files a generated from LLVM's TableGen backend and processed by python scrips +in `suite/synctools` into C-compatible files, which leads to the problem that with LLVM's update, it's not always +(hardly, in fact) +possible to use the synctools without patch in regard to LLVM's upstream change. + +This syncing tools, however, using a custom-made LLVM TableGen +backend ([here](https://github.com/rizinorg/llvm-capstone)) +to generate `.inc` files natively usable by Capstone. With certain adaptations in Capstone's structure, it is possible +to consistently automate large parts of the work on keeping up with LLVM's latest Target (i.e. `.td` files) update, and +optimally, there could be zero-overhead in the process of updating +( +see [this patch on missing bcxf instructions](https://github.com/rizinorg/llvm-capstone/commit/d594f4f6b0755ab11580e1e87d610b560e71b5ef)) + +## Components + +There are three primary components on this syncing tools, listed below: + +1. llvm-capstone (as shown above), this is where the custom `.inc` file generator lies, it's based on the latest HEAD of + llvm-project and is prepared for rebase onto future versions. +2. CapstoneXXX(Arch)Modules.h, this is added for each supported architectures, and contains the necessary specialized + decoder functions for TableGen-ed disassemblers, it also means that it is used to import the disassembler and expose + it to Capstone. +3. XXX(Arch)GenDisassemblerTables.inc, this is the TableGen-ed file contains various information & codes generated from + LLVM's Target Description (*.td) + files, it is fully auto-generated and is recommended not to be modified manually, the following of this document will + introduce various important parts of this file. + +## TableGen-ed file + +The tablegen-ed file has the following parts, respectively: + +### Disassembler & Feature Enums + +This disassembler part contains **tables** and codes of this architecture's instructions, and is expected to be +C-Compatible, the `DecodeInstruction` here can be used to define an instruction decoder function like that we could see +in `AArch64GenDisassemblerTables.inc`: + +```c +// define the insn file extractor +FieldFromInstruction(fieldFromInstruction, uint32_t) +// define the `to MCInst` decoder +DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) +// define the instruction decoder `i.e. disassembler` +DecodeInstruction(decodeInstruction, fieldFromInstruction, + decodeToMCInst, uint32_t) +``` + +and thus this `decodeInstruction` can be called as a C function with the disassemble **table** given, like such: + +```c +// Calling the auto-generated decoder function. + result = + decodeInstruction_4(DecoderTableARM32, MI, insn, Address, 0, ud->mode); +``` + +This part of file is enabled with macro `#{ARCH}_GET_DISASSEMBLER` + +### Registers Info & Instruction Info Enums + +Each disassembled MCInst contains OpCode ID and Operand ID (if they're not immediate) that might not be known to +Capstone. The Register & Instruction Info Enums exhibit there correspondence to the "magic numbers" within MCInst. And +can be used by Capstone to map each OpCode & Operand into the identifiable ones. + +This also contains miscellaneous like Register Class IDs, which shall be vital to certain instructions. + +This part of file is enabled with macro `#GET_INSTRINFO_ENUM` and `#GET_REGINFO_ENUM` + +### Extra Register Info + +Sometimes Capstone needs more information Certain information on registers, e.g., architectures have special registers +that possesses `Sub Register` or `Super Register` (like `D` and `Q` +registers in ARM64), and also, Capstone is using their names (in LLVM), like for instruction printing. This part +contains all the info. that might be needed to find a registers' name, their sub-regs or super-regs, and also it +contains register class definitions, making it possible to index into certain register class, or to find which class a +register belongs to. + +This part of file is enabled with macro `#GET_REGINFO_EXTRA` and `#GET_REGINFO_MC_DESC` + +### Instruction Printer (Asm Writer) + +Printing an instruction, like that of disassembler, is provided with certain functions to perform, this includes: + +1. `$ARCH_getMnemonic`, this function returns a pair of instruction mnemonic and its printer-specific operand info, + given a valid `MCInst`. +2. `printInstruction`, this function prints instruction according to the given `MCInst`, and make it's output to a + Capstone `SStream`, note that this method make callbacks to architecture-specific operand printers defined + in `${ARCH}InstPrinter.c`, and the specialized operand printer should be manually tweaked to meet up with custom + needs. +3. `getRegisterName`, this function maps register ID (LLVM internal) into their names, note that the name provided could + be different from convention to convention, that's why we have `$ARCH_reg_name` in `${ARCH}Mapping.c` file. In this + patched version this is used as a fallback for register that has not been named by Capstone. +4. `printAliasInstr`, some instructions might have aliases in that the performs the same under certain architecture, + that's when this function is used, commonly, this function is called before `printInstruction` to make sure that the + aliases is checked before printing the raw one. + +The first two is accessed by `#GET_ASM_WRITER`, and the alias printing function is accessed by `#PRINT_ALIAS_INSTR`. + +### Instruction Operand Info + +Capstone partly rely on operand usages provided by LLVM, that has its cons and pros, this part of the file is for providing it. +It contains an instruction-to-info. mappings, giving Capstone information on the properties of an instructions' operand one-by-one. + +This part also contains the LLVM internal name table for each instruction, which is not commonly used by capstone (but can be referenced if needed) +To enable this, use `#GET_INSTRINFO_MC_DESC` diff --git a/sync/gen-table.py b/sync/gen-table.py new file mode 100755 index 0000000000..cad9be119d --- /dev/null +++ b/sync/gen-table.py @@ -0,0 +1,88 @@ +#! /usr/bin/env python3 + +import optparse +import os +import platform +import sys + +parse = optparse.OptionParser(usage='"usage:%prog [options] "', version="%prog 1.0") +parse.add_option('-i', '--include', dest='include_dir', action='store', type=str + , help='path to LLVM source location, which should generally be path to a dir named `llvm-project` (' + 'or `llvm-capstone`)') + +# It's the best that you configure llvm-tblgen into PATH variable, however we support manual approach +parse.add_option('-b', '--bin', type=str, help='specify location of llvm-tblgen.exe/llvm-tblgen binary') + +parse.add_option('-o', '--output', type=str, help='specify output file location, this is NOT mandatory') + +parse.add_option('--mapper', dest='mapper', action='store_true' + , default=False, help='generate mapper instead of disassembler') + +parse.add_option('-d', '--build-dir', type=str, help='custom cmake build dir (for seeking tablegen includes) relative ' + 'to include dir') + +(options, args) = parse.parse_args() + +if options.include_dir is None: + print("Error: Please specify the LLVM source location with `-i`") + exit() + +if len(args) == 0: + parse.print_usage() + print("Error: Please specify the architecture") + exit() + +supported_arch = ["Mips", "ARM", "AArch64", "RISCV", "PowerPC", "Sparc", "SystemZ", "XCore"] + + +# In case of architecture names' ambiguity +def fix_arch_mapping(name): + for arch in supported_arch: + if name.lower() == arch.lower(): + return arch + if name.lower() == "arm64": + return "AArch64" + if name.lower() == "ppc": + return "PowerPC" + return name + + +arch = fix_arch_mapping(args[0]) + +if arch not in supported_arch: + parse.print_usage() + print("Unrecognized architecture: " + arch) + print("Those supported are:") + print(supported_arch) + +print(options) + +is_win = platform.system().lower() == "windows" + +bin_to_use = ("llvm-tblgen.exe" if is_win else "llvm-tblgen") if options.bin is None else options.bin + +use_mapper = "-mapper" if options.mapper else "" + +build_dir = "build" if options.build_dir is None else options.build_dir + +command = "{0} --gen-capstone{1} -I{2}/llvm/lib/Target/{3} " \ + "-I{2}/{4}/include " \ + "-I{2}/llvm/include " \ + "-I{2}/llvm/lib/Target " \ + "{2}/llvm/lib/Target/{3}/{5}.td".format(bin_to_use, use_mapper, options.include_dir, arch, + build_dir, arch if arch != "PowerPC" else "PPC") + +result = os.popen(command, "r") +lines = result.readlines() + +if not lines: + print("TableGen execution exited with error, command executed is:") + print(command) + exit() + +if options.output is None: + sys.stdout.writelines(lines) +else: + file_out = file(options.output, "wb") + file_out.writelines(lines) + diff --git a/sync/main.py b/sync/main.py new file mode 100644 index 0000000000..e7d9a52eec --- /dev/null +++ b/sync/main.py @@ -0,0 +1,231 @@ +#! /usr/bin/env python3 + +import functools +import sys +import re +import os + +# NOTE : unfortunately not all of the disassembler details are recorded in llvm *.td file +# this script is for dumping those codes into our project + +try: + arch = os.environ["ARCH"] +except KeyError: + print "Please set the environment variable FOO" + sys.exit(1) + +f = open(sys.argv[1]) +lines = f.readlines() +f.close() + +buffer = [] +read_depth = 0 + +thumb_mode = False + + +def is_arm(): + return arch == "ARM" or arch == "AArch64" + + +def join(x, y): + return x + y + + +def create_reg_decode_def(func): + output = functools.reduce(join, func) + + # parameters type replacement + output = output.replace("MCInst &", "MCInst *", 1) + output = output.replace("InsnType", "unsigned") # replace all for InsnType is fine + output = output.replace("const void", "MCRegisterInfo", 1) + + print(output) + + +def create_reg_const(func): + output = functools.reduce(join, func) + output = output.replace("::", "_") + print(output) + + +def create_reg_decode(func): + output = functools.reduce(join, func) + + # parameters type replacement + output = output.replace("MCInst &", "MCInst *", 1) + output = output.replace("InsnType", "unsigned") # replace all for InsnType is fine + output = output.replace("const void", "MCRegisterInfo", 1) + + # standard c-fy + output = output.replace("nullptr", "0x0") + output = output.replace("LLVM_FALLTHROUGH", "0x0") + + # FIXME bunch of patches incoming + # quick patch to the MIPS function pointers + output = output.replace( + "using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);", + "DecodeStatus (* RegDecoder)(MCInst *, unsigned, uint64_t, MCRegisterInfo *);", + ) + output = output.replace("DecodeFN RegDecoder = 0x0;", "RegDecoder = 0x0;") + + # a unfortunate patch to MIPS + + output = output.replace( + "Inst.getOperand(2).getImm()", "MCOperand_getImm(MCInst_getOperand(Inst, 2))" + ) + + # unfortunate patch to ARM & AArch64 + + if is_arm(): + output = output.replace( + "fieldFromInstruction", + "fieldFromInstruction_" + ("2" if thumb_mode else "4"), + ) + output = output.replace("Check(S", "Check(&S") + output = output.replace("Check(DS", "Check(&DS") + output = re.sub( + r"const FeatureBitset &[fF]eatureBits =.+?;", + "/* Ignored bit flags */", + output, + flags=re.S, + ) + output = re.sub(r"[fF]eatureBits\[.+?]", "true", output) + + # here goes the common procedure (not patch) + # namespace replacement + output = output.replace("MCDisassembler::", "MCDisassembler_") + output = output.replace(arch + "::", arch + "_") + + # method call replacement + def re_opcode(x): + return "MCInst_setOpcode(" + x.group(1) + ", " + x.group(2) + ");" + + def re_with(op_name): + def re_with_inner(x): + return ( + "MCOperand_Create" + + op_name + + "(" + + x.group(1) + + ", " + + x.group(2) + + ");" + ) + + return re_with_inner + + def re_operand(x): + newline = x.group(0) + if "createReg" in newline: + return re.sub( + r"([A-Za-z]+)\.addOperand\(\s*MCOperand::createReg\((.+?)\)\);", + re_with("Reg0"), + newline, + flags=re.DOTALL, + ) + else: + return re.sub( + r"([A-Za-z]+)\.addOperand\(\s*MCOperand::createImm\((.+?)\)\);", + re_with("Imm0"), + newline, + flags=re.DOTALL, + ) + + output = re.sub( + r"([A-Za-z]+)\.setOpcode\(\s*(.+?)\);", re_opcode, output, flags=re.DOTALL + ) + output = re.sub( + r"([A-Za-z]+)\.addOperand\(\s*(.+?)\);", re_operand, output, flags=re.DOTALL + ) + output = re.sub( + r"([A-Za-z]+)\.getOpcode\(\)", + lambda x: "MCInst_getOpcode(" + x.group(1) + ")", + output, + ) + + # for template functions constraint by value, we integrate those template param + # template void func(); ----> void func(int x); + # note that this change is on call site, so we've got to change the decls. manually + while re.findall(r"<.+>\(", output, flags=re.DOTALL): + location = re.findall(r"<.+?>\(", output) + for line_str in location: + pos = output.find(line_str) + end = pos + len(line_str) # scan parameters within brackets + depth = 0 + while depth >= 0: + end += 1 + if output[end] == ")": + depth -= 1 + if output[end] == "(": + depth += 1 + params = output[pos + len(line_str) : end] + template = re.findall(r"<(.+?)>", output) + output = output[0:pos] + "(" + params + ", " + template[0] + output[end:] + + # `::` are never valid in C, we'd remove it whenever possible + output = output.replace("::", "_") + + print(output) + + +# dump the constants +print("static void llvm_unreachable(const char * info) {}") +print("static void assert(int val) {}") + +const_table = False + + +for line in lines: + if re.match(r"static DecodeStatus", line): + if "readInstruction" in line or "checkDecodedInstruction" in line: + continue + if "Thumb" in line and is_arm(): + thumb_mode = True + buffer.append(line) + if ";" in line: # let go of the function declaration + create_reg_decode_def(buffer) + buffer.clear() + continue + if "{" in line: + read_depth = 2 + else: + read_depth = 1 + continue + if "static const uint16_t" in line or "static const unsigned" in line: + if read_depth < 1: + buffer.append(line) + const_table = 0 + if "{" in line: + read_depth = 2 + else: + read_depth = 1 + continue + if ( + ";" in line and read_depth <= 1 and len(buffer) > 0 + ): # lazy detection of function definitions + buffer.append(line) + create_reg_decode_def(buffer) + buffer.clear() + read_depth = 0 + continue + if is_arm() and read_depth == 1: + if "Thumb" in line: + thumb_mode = True + if "{" in line and read_depth >= 1: + buffer.append(line) + if "}" not in line: + read_depth += 1 + continue + if read_depth >= 1: + buffer.append(line) + if "}" in line: + read_depth -= 1 + if read_depth <= 1: + if const_table: + create_reg_const(buffer) + else: + create_reg_decode(buffer) + read_depth = 0 + thumb_mode = False + buffer.clear() diff --git a/utils.h b/utils.h index 520e0b4197..94fcc1cb22 100644 --- a/utils.h +++ b/utils.h @@ -22,7 +22,7 @@ typedef struct insn_map { #ifndef CAPSTONE_DIET uint16_t regs_use[12]; // list of implicit registers used by this instruction uint16_t regs_mod[20]; // list of implicit registers modified by this instruction - unsigned char groups[8]; // list of group this instruction belong to + unsigned char groups[16]; // list of group this instruction belong to bool branch; // branch instruction? bool indirect_branch; // indirect branch instruction? #endif