diff --git a/.gitignore b/.gitignore
index 734d4ecb7c..aa1c8b6457 100644
--- a/.gitignore
+++ b/.gitignore
@@ -62,6 +62,7 @@ tests/test_skipdata
 tests/test_sparc
 tests/test_systemz
 tests/test_xcore
+tests/test_tricore
 tests/*.static
 tests/test_customized_mnem
 tests/test_m68k
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 395e1937f8..6d9002a4b8 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -39,13 +39,14 @@ option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ${BUILD_SHARED_LIBS}
 option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
 option(CAPSTONE_BUILD_TESTS "Build tests" ${PROJECT_IS_TOP_LEVEL})
 option(CAPSTONE_BUILD_CSTOOL "Build cstool" ${PROJECT_IS_TOP_LEVEL})
+option(CAPSTONE_BUILD_CSTEST "Build cstest" OFF)
 option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
 option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON)
 option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF)
 option(CAPSTONE_INSTALL "Generate install target" ${PROJECT_IS_TOP_LEVEL})
 
-set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH)
-set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH)
+set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE)
+set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore)
 
 list(LENGTH SUPPORTED_ARCHITECTURES count)
 math(EXPR count "${count}-1")
@@ -135,6 +136,7 @@ set(HEADERS_COMMON
     include/capstone/bpf.h
     include/capstone/riscv.h
     include/capstone/sh.h
+    include/capstone/tricore.h
     include/capstone/platform.h
 )
 
@@ -533,7 +535,28 @@ if(CAPSTONE_SH_SUPPORT)
     set(TEST_SOURCES ${TEST_SOURCES} test_sh.c)
 endif()
 
-if(CAPSTONE_OSXKERNEL_SUPPORT)
+if (CAPSTONE_TRICORE_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_TRICORE)
+    set(SOURCES_TRICORE
+            arch/TriCore/TriCoreDisassembler.c
+            arch/TriCore/TriCoreInstPrinter.c
+            arch/TriCore/TriCoreMapping.c
+            arch/TriCore/TriCoreModule.c
+            )
+    set(HEADERS_TRICORE
+            arch/TriCore/TriCoreDisassembler.h
+            arch/TriCore/TriCoreGenAsmWriter.inc
+            arch/TriCore/TriCoreGenDisassemblerTables.inc
+            arch/TriCore/TriCoreGenInstrInfo.inc
+            arch/TriCore/TriCoreGenRegisterInfo.inc
+            arch/TriCore/TriCoreInstPrinter.h
+            arch/TriCore/TriCoreMapping.h
+            arch/TriCore/TriCoreModule.h
+            )
+    set(TEST_SOURCES ${TEST_SOURCES} test_tricore.c)
+endif ()
+
+if (CAPSTONE_OSXKERNEL_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
 endif()
 
@@ -556,6 +579,7 @@ set(ALL_SOURCES
     ${SOURCES_BPF}
     ${SOURCES_RISCV}
     ${SOURCES_SH}
+    ${SOURCES_TRICORE}
 )
 
 set(ALL_HEADERS
@@ -578,6 +602,7 @@ set(ALL_HEADERS
     ${HEADERS_BPF}
     ${HEADERS_RISCV}
     ${HEADERS_SH}
+    ${HEADERS_TRICORE}
 )
 
 ## properties
@@ -640,6 +665,7 @@ source_group("Source\\MOS65XX" FILES ${SOURCES_MOS65XX})
 source_group("Source\\BPF" FILES ${SOURCES_BPF})
 source_group("Source\\RISCV" FILES ${SOURCES_RISCV})
 source_group("Source\\SH" FILES ${SOURCES_SH})
+source_group("Source\\TriCore" FILES ${SOURCES_TRICORE})
 
 source_group("Include\\Common" FILES ${HEADERS_COMMON})
 source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
@@ -660,6 +686,7 @@ source_group("Include\\MOS65XX" FILES ${HEADERS_MOS65XX})
 source_group("Include\\BPF" FILES ${HEADERS_BPF})
 source_group("Include\\RISCV" FILES ${HEADERS_RISCV})
 source_group("Include\\SH" FILES ${HEADERS_SH})
+source_group("Include\\TriCore" FILES ${HEADERS_TRICORE})
 
 ## installation
 if(CAPSTONE_INSTALL)
@@ -726,3 +753,20 @@ if(CAPSTONE_BUILD_CSTOOL)
         install(TARGETS cstool EXPORT capstone-targets DESTINATION ${CMAKE_INSTALL_BINDIR})
     endif()
 endif()
+
+if(CAPSTONE_BUILD_CSTEST)
+    find_package(CMOCKA)
+
+    file(GLOB CSTEST_SRC suite/cstest/src/*.c)
+    add_executable(cstest ${CSTEST_SRC})
+    target_link_libraries(cstest PUBLIC capstone ${CMOCKA_LIBRARIES})
+    target_include_directories(cstest PRIVATE
+            $<BUILD_INTERFACE:${PROJECT_SOURCE_DIR}/include>
+            ${PROJECT_SOURCE_DIR}/suite/cstest/include
+            ${CMOCKA_INCLUDE_DIR}
+            )
+
+    if(CAPSTONE_INSTALL)
+        install(TARGETS cstest EXPORT capstone-targets DESTINATION ${CMAKE_INSTALL_BINDIR})
+    endif()
+endif()
diff --git a/COMPILE.TXT b/COMPILE.TXT
index 81dc4b6314..87b07bd52c 100644
--- a/COMPILE.TXT
+++ b/COMPILE.TXT
@@ -100,6 +100,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 	/usr/include/capstone/wasm.h
 	/usr/include/capstone/x86.h
 	/usr/include/capstone/xcore.h
+	/usr/include/capstone/tricore.h
 	/usr/lib/libcapstone.a
 	/usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
 
diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT
index 7834097078..6181cbb084 100644
--- a/COMPILE_CMAKE.TXT
+++ b/COMPILE_CMAKE.TXT
@@ -29,6 +29,7 @@ Get CMake for free from http://www.cmake.org.
   - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc.
   - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ.
   - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore.
+  - CAPSTONE_TRICORE_SUPPORT: support TriCore. Run cmake with -DCAPSTONE_TRICORE_SUPPORT=0 to remove TriCore.
   - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86.
   - CAPSTONE_X86_TMS320C64X: support TMS320C64X. Run cmake with -DCAPSTONE_TMS320C64X_SUPPORT=0 to remove TMS320C64X.
   - CAPSTONE_X86_M680X: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT
index b2d9bdd26c..e478c831f1 100644
--- a/COMPILE_MSVC.TXT
+++ b/COMPILE_MSVC.TXT
@@ -39,6 +39,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
   - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support.
   - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support.
   - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support.
+  - CAPSTONE_HAS_TRICORE: support TriCore. Delete this to remove TriCore support.
 
   By default, all 9 architectures are compiled in.
 
diff --git a/CREDITS.TXT b/CREDITS.TXT
index 32205ef670..0f7265a6f3 100644
--- a/CREDITS.TXT
+++ b/CREDITS.TXT
@@ -87,3 +87,4 @@ david942j: BPF (both classic and extended) architecture.
 fanfuqiang & citypw & porto703 : RISCV architecture.
 Josh "blacktop" Maine: Arm64 architecture improvements.
 Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support)
+Billow & Sidneyp : TriCore architecture.
diff --git a/HACK.TXT b/HACK.TXT
index 228ec5fb3f..76c56551fc 100644
--- a/HACK.TXT
+++ b/HACK.TXT
@@ -14,11 +14,13 @@ Capstone source is organized as followings.
 │   ├── Mips        <- Mips engine
 │   ├── MOS65XX     <- MOS65XX engine
 │   ├── PowerPC     <- PowerPC engine
+│   ├── RISCV       <- RISCV engine
+│   ├── SH          <- SH engine
 │   ├── Sparc       <- Sparc engine
 │   ├── SystemZ     <- SystemZ engine
 │   ├── TMS320C64x  <- TMS320C64x engine
-│   ├── X86         <- X86 engine
-│   └── XCore       <- XCore engine
+│   ├── TriCore     <- TriCore engine
+│   └── WASM        <- WASM engine
 ├── bindings        <- all bindings are under this dir
 │   ├── java        <- Java bindings + test code
 │   ├── ocaml       <- Ocaml bindings + test code
@@ -85,7 +87,7 @@ Tests:
 - tests/test_detail.c
 - tests/test_iter.c
 - tests/test_newarch.c
-- suite/fuzz/fuzz_disasm.c: add the architecture and its modes to the list of fuzzed platforms
+- suite/fuzz/platform.c: add the architecture and its modes to the list of fuzzed platforms
 - suite/capstone_get_setup.c
 - suite/MC/newarch/mode.mc: samples
 - suite/test_corpus.py: correspondence between architecture and mode as text and architecture number for fuzzing
diff --git a/MCInstrDesc.h b/MCInstrDesc.h
index 084da9b7d0..0bdbb6b084 100644
--- a/MCInstrDesc.h
+++ b/MCInstrDesc.h
@@ -57,7 +57,11 @@ enum MCOI_OperandType {
 	MCOI_OPERAND_GENERIC_5 = 11,
 	MCOI_OPERAND_LAST_GENERIC = 11,
 
-	MCOI_OPERAND_FIRST_TARGET = 12,
+	MCOI_OPERAND_FIRST_GENERIC_IMM = 12,
+	MCOI_OPERAND_GENERIC_IMM_0 = 12,
+	MCOI_OPERAND_LAST_GENERIC_IMM = 12,
+
+	MCOI_OPERAND_FIRST_TARGET = 13,
 };
 
 
diff --git a/Makefile b/Makefile
index 892c983c7c..a971f55244 100644
--- a/Makefile
+++ b/Makefile
@@ -314,11 +314,22 @@ ifneq (,$(findstring bpf,$(CAPSTONE_ARCHS)))
 	LIBOBJ_BPF += $(LIBSRC_BPF:%.c=$(OBJDIR)/%.o)
 endif
 
+DEP_TRICORE =
+DEP_TRICORE +=$(wildcard arch/TriCore/TriCore*.inc)
+
+LIBOBJ_TRICORE =
+ifneq (,$(findstring tricore,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_TRICORE
+	LIBSRC_TRICORE += $(wildcard arch/TriCore/TriCore*.c)
+	LIBOBJ_TRICORE += $(LIBSRC_TRICORE:%.c=$(OBJDIR)/%.o)
+endif
+
 
 LIBOBJ =
 LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o
 LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
 LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
+LIBOBJ += $(LIBOBJ_TRICORE)
 LIBOBJ += $(OBJDIR)/MCInst.o
 
 
@@ -454,6 +465,7 @@ $(LIBOBJ_RISCV): $(DEP_RISCV)
 $(LIBOBJ_WASM): $(DEP_WASM)
 $(LIBOBJ_MOS65XX): $(DEP_MOS65XX)
 $(LIBOBJ_BPF): $(DEP_BPF)
+$(LIBOBJ_TRICORE): $(DEP_TRICORE)
 
 ifeq ($(CAPSTONE_STATIC),yes)
 $(ARCHIVE): $(LIBOBJ)
@@ -539,7 +551,7 @@ dist:
 	git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
 	git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
 
-TESTS  = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc	
+TESTS  = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc test_tricore
 TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf
 TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
 TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
diff --git a/README.md b/README.md
index c6e3095a53..b362bd410c 100644
--- a/README.md
+++ b/README.md
@@ -16,7 +16,7 @@ Capstone offers some unparalleled features:
 
 - Support multiple hardware architectures: ARM, ARM64 (ARMv8), BPF, Ethereum VM,
   M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ,
-  TMS320C64X, Webassembly, XCore and X86 (16, 32, 64).
+  TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64).
 
 - Having clean/simple/lightweight/intuitive architecture-neutral API.
 
diff --git a/arch/TriCore/TriCore.td b/arch/TriCore/TriCore.td
new file mode 100644
index 0000000000..5ba97414c1
--- /dev/null
+++ b/arch/TriCore/TriCore.td
@@ -0,0 +1,134 @@
+//===-- TriCore.td - Describe the TriCore Target Machine ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This is the top level entry point for the TriCore target.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Target-independent interfaces which we are implementing
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+//===----------------------------------------------------------------------===//
+// Descriptions
+//===----------------------------------------------------------------------===//
+
+// Specify whether target support specific TRICORE ISA variants.
+
+def HasV110Ops   : SubtargetFeature<"v1.1", "HasV110Ops", "true",
+								   "Support TriCore v1.1 instructions",
+								   []>;
+def HasV120Ops   : SubtargetFeature<"v1.2", "HasV120Ops", "true",
+								   "Support TriCore v1.2 instructions",
+								   []>;
+def HasV130Ops   : SubtargetFeature<"v1.3", "HasV130Ops", "true",
+								   "Support TriCore v1.3 instructions",
+								   []>;
+def HasV131Ops   : SubtargetFeature<"v1.3.1", "HasV131Ops", "true",
+								   "Support TriCore v1.3.1 instructions",
+								   []>;
+def HasV160Ops   : SubtargetFeature<"v1.6", "HasV160Ops", "true",
+								   "Support TriCore v1.6 instructions",
+								   []>;
+def HasV161Ops   : SubtargetFeature<"v1.6.1", "HasV161Ops", "true",
+								   "Support TriCore v1.6.1 instructions",
+								   []>;
+def HasV162Ops   : SubtargetFeature<"v1.6.2", "HasV162Ops", "true",
+								   "Support TriCore v1.6.2 instructions",
+								   []>;
+
+def HasV110     : Predicate<"HasV120Ops()">, AssemblerPredicate<(all_of HasV110Ops), "v1.1">;
+def HasV120     : Predicate<"HasV120Ops()">, AssemblerPredicate<(all_of HasV120Ops), "v1.2">;
+def HasV130     : Predicate<"HasV130Ops()">, AssemblerPredicate<(all_of HasV130Ops), "v1.3">;
+def HasV131     : Predicate<"HasV131Ops()">, AssemblerPredicate<(all_of HasV131Ops), "v1.3.1">;
+def HasV160     : Predicate<"HasV160Ops()">, AssemblerPredicate<(all_of HasV160Ops), "v1.6">;
+def HasV161     : Predicate<"HasV161Ops()">, AssemblerPredicate<(all_of HasV161Ops), "v1.6.1">;
+def HasV162     : Predicate<"HasV162Ops()">, AssemblerPredicate<(all_of HasV162Ops), "v1.6.2">;
+
+def HasV120_UP  : Predicate<"HasV120Ops() || HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV120Ops, HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v120up">;
+def HasV130_UP  : Predicate<"HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v130up">;
+def HasV131_UP  : Predicate<"HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v131up">;
+def HasV160_UP  : Predicate<"HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV160Ops, HasV161Ops, HasV162Ops), "v160up">;
+def HasV161_UP  : Predicate<"HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV161Ops, HasV162Ops), "v161up">;
+def HasV162_UP  : Predicate<"HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV162Ops), "v162up">;
+
+def HasV120_DN : Predicate<"HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV120Ops, HasV110Ops), "v120dn">;
+def HasV130_DN : Predicate<"HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV130Ops, HasV120Ops, HasV110Ops), "v130dn">;
+def HasV131_DN : Predicate<"HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v131dn">;
+def HasV160_DN : Predicate<"HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v160dn">;
+def HasV161_DN : Predicate<"HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v161dn">;
+def HasV162_DN : Predicate<"HasV162Ops() || HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV162Ops, HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v162dn">;
+
+
+class Architecture<string fname, string aname, list<SubtargetFeature> features = []>
+  : SubtargetFeature<fname, "TriCoreArch", aname,
+					 !strconcat(aname, " architecture"), features>;
+
+class ProcNoItin<string Name, list<SubtargetFeature> Features>
+  : Processor<Name, NoItineraries, Features>;
+
+
+def TRICORE_V1_1    : Architecture<"tricore-v1.1",    "TRICOREv110", [HasV110Ops]>;
+def TRICORE_V1_2    : Architecture<"tricore-V1.2",    "TRICOREv120", [HasV120Ops]>;
+def TRICORE_V1_3    : Architecture<"tricore-V1.3",    "TRICOREv130", [HasV130Ops]>;
+def TRICORE_V1_3_1  : Architecture<"tricore-V1.3.1",  "TRICOREv131", [HasV131Ops]>;
+def TRICORE_V1_6    : Architecture<"tricore-V1.6",    "TRICOREv160", [HasV160Ops]>;
+def TRICORE_V1_6_1  : Architecture<"tricore-V1.6.1",  "TRICOREv161", [HasV161Ops]>;
+def TRICORE_V1_6_2  : Architecture<"tricore-V1.6.2",  "TRICOREv162", [HasV162Ops]>;
+def TRICORE_PCP     : Architecture<"tricore-PCP",     "TRICOREpcp">;
+def TRICORE_PCP2    : Architecture<"tricore-PCP2",    "TRICOREpcp2">;
+
+def TRICORE_RIDER_A : Architecture<"tricore-rider-a", "TRICOREv110", [TRICORE_V1_1]>;
+
+
+include "TriCoreRegisterInfo.td"
+include "TriCoreInstrInfo.td"
+include "TriCoreCallingConv.td"
+
+//===----------------------------------------------------------------------===//
+// TriCore processors supported.
+//===----------------------------------------------------------------------===//
+
+def : ProcNoItin<"tc1796",  [TRICORE_V1_3]>;
+def : ProcNoItin<"tc1797",  [TRICORE_V1_3_1]>;
+def : ProcNoItin<"tc27x",   [TRICORE_V1_6_1]>;
+def : ProcNoItin<"tc161",   [TRICORE_V1_6_1]>;
+def : ProcNoItin<"tc162",   [TRICORE_V1_6_2]>;
+def : ProcNoItin<"tc16",    [TRICORE_V1_6]>;
+def : ProcNoItin<"tc131",   [TRICORE_V1_3_1]>;
+def : ProcNoItin<"tc13",    [TRICORE_V1_3]>;
+
+def TriCoreAsmWriter : AsmWriter {
+  int PassSubtarget = 1;
+}
+
+def TriCoreInstrInfo : InstrInfo;
+
+//===----------------------------------------------------------------------===//
+// Declare the target which we are implementing
+//===----------------------------------------------------------------------===//
+
+def TriCore : Target {
+  let InstructionSet = TriCoreInstrInfo;
+  let AssemblyWriters = [TriCoreAsmWriter];
+}
diff --git a/arch/TriCore/TriCoreCallingConv.td b/arch/TriCore/TriCoreCallingConv.td
new file mode 100644
index 0000000000..0a43914802
--- /dev/null
+++ b/arch/TriCore/TriCoreCallingConv.td
@@ -0,0 +1,61 @@
+//=- TriCoreCallingConv.td - Calling Conventions for TriCore -*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// This describes the calling conventions for TriCore architecture.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// CCDelegate implemented form TriCore LLVM Thesis
+//===----------------------------------------------------------------------===//
+//def CC_TriCore_StackModel : CallingConv<[
+//CCAssignToStack<4, 4>
+//]>;
+
+//===----------------------------------------------------------------------===//
+// TriCore Return Value Calling Convention
+//===----------------------------------------------------------------------===//
+def RetCC_TriCore : CallingConv<[
+  // Promote i8/i16 arguments to i32.
+  CCIfType<[i8, i16], CCPromoteToType<i32>>,
+  
+  // i32 are returned in registers D2
+  CCIfType<[i32], CCAssignToReg<[D2]>>,
+
+  // Integer values get stored in stack slots that are 4 bytes in
+  // size and 4-byte aligned.
+  CCIfType<[i32], CCAssignToStack<4, 4>>
+]>;
+
+//===----------------------------------------------------------------------===//
+// TriCore Argument Calling Conventions
+//===----------------------------------------------------------------------===//
+def CC_TriCore : CallingConv<[
+  // Promote i8/i16 arguments to i32.
+  CCIfType<[i8, i16], CCPromoteToType<i32>>,
+
+	
+	// The first 4 integer arguments are passed in integer registers.
+	//	CCIfType<[i32], CCAssignToReg<[D4, D5, D6, D7]>>,
+	
+	//CCIfType<[i32], CCAssignToReg<[A4, A5, A6, A7]>>,
+	
+	// Pointer arguments are handled inside TriCoreIselLowering, because
+	// LLVM lowers i32** type into i32, hence there is no way to distingusish
+	// beetwen a pointer type and an integer type.
+	
+
+	
+	
+  //CCDelegateTo<CC_TriCore_StackModel>
+  
+  // Integer values get stored in stack slots that are 4 bytes in
+  // size and 4-byte aligned.
+  CCIfType<[i32], CCAssignToStack<4, 4>>
+]>;
+
+//def CC_Save : CalleeSavedRegs<(add R4, R5, R6, R7, R8, R9)>;
diff --git a/arch/TriCore/TriCoreDisassembler.c b/arch/TriCore/TriCoreDisassembler.c
new file mode 100644
index 0000000000..b94b1fc928
--- /dev/null
+++ b/arch/TriCore/TriCoreDisassembler.c
@@ -0,0 +1,1591 @@
+//===------ TriCoreDisassembler.cpp - Disassembler for TriCore --*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_TRICORE
+
+#include <stdio.h> // DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+#include "../../MathExtras.h"
+
+static bool readInstruction16(const uint8_t *code, size_t code_len,
+			      uint16_t *insn)
+{
+	if (code_len < 2)
+		// insufficient data
+		return false;
+
+	// Encoded as a little-endian 16-bit word in the stream.
+	*insn = (code[0] << 0) | (code[1] << 8);
+	return true;
+}
+
+static bool readInstruction32(const uint8_t *code, size_t code_len,
+			      uint32_t *insn)
+{
+	if (code_len < 4)
+		// insufficient data
+		return false;
+
+	// Encoded as a little-endian 32-bit word in the stream.
+	*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) |
+		(code[3] << 24);
+	return true;
+}
+
+static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
+{
+	const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
+	return rc->RegsBegin[RegNo];
+}
+
+#define tryDecodeReg(i, x)                                                    \
+	status = DecodeRegisterClass(Inst, (x), &desc->OpInfo[(i)], Decoder); \
+	if (status != MCDisassembler_Success)                                 \
+		return status;
+
+#define decodeImm(x) MCOperand_CreateImm0(Inst, (x));
+
+static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn,
+				       uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder);
+
+#define GET_SUBTARGETINFO_ENUM
+
+#include "TriCoreGenSubtargetInfo.inc"
+
+bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+	switch (mode) {
+	case CS_MODE_TRICORE_110: {
+		return feature == TRICORE_HasV110Ops;
+	}
+	case CS_MODE_TRICORE_120: {
+		return feature == TRICORE_HasV120Ops;
+	}
+	case CS_MODE_TRICORE_130: {
+		return feature == TRICORE_HasV130Ops;
+	}
+	case CS_MODE_TRICORE_131: {
+		return feature == TRICORE_HasV131Ops;
+	}
+	case CS_MODE_TRICORE_160: {
+		return feature == TRICORE_HasV160Ops;
+	}
+	case CS_MODE_TRICORE_161: {
+		return feature == TRICORE_HasV161Ops;
+	}
+	case CS_MODE_TRICORE_162: {
+		return feature == TRICORE_HasV162Ops;
+	}
+	default:
+		return false;
+	}
+}
+
+#include "TriCoreGenDisassemblerTables.inc"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+
+#include "TriCoreGenRegisterInfo.inc"
+
+static DecodeStatus DecodeRegisterClass(MCInst *Inst, unsigned RegNo,
+					const MCOperandInfo *MCOI,
+					void *Decoder)
+{
+	unsigned Reg;
+	unsigned RegHalfNo = RegNo / 2;
+
+	if (!MCOI || MCOI->OperandType != MCOI_OPERAND_REGISTER) {
+		return MCDisassembler_Fail;
+	}
+
+	if (RegHalfNo > 15)
+		return MCDisassembler_Fail;
+
+	if (MCOI->RegClass < 3) {
+		Reg = getReg(Decoder, MCOI->RegClass, RegNo);
+	} else {
+		Reg = getReg(Decoder, MCOI->RegClass, RegHalfNo);
+	}
+
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+#define GET_INSTRINFO_ENUM
+#define GET_INSTRINFO_MC_DESC
+
+#include "TriCoreGenInstrInfo.inc"
+
+static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder)
+{
+	unsigned disp8 = fieldFromInstruction_2(Insn, 8, 8);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	// Decode disp8.
+	MCOperand_CreateImm0(Inst, disp8);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode disp4.
+	MCOperand_CreateImm0(Inst, disp4);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder)
+{
+	unsigned const8 = fieldFromInstruction_2(Insn, 8, 8);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	// Decode const8.
+	MCOperand_CreateImm0(Inst, const8);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	if (desc->NumOperands > 0) {
+		status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	if (desc->NumOperands > 1) {
+		status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned const4 = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+
+	// Decode s1/d.
+	status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode const4.
+	MCOperand_CreateImm0(Inst, const4);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	// Decode s1/d.
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned off18_0 = fieldFromInstruction_4(Insn, 16, 6);
+	unsigned off18_1 = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned off18_2 = fieldFromInstruction_4(Insn, 22, 4);
+	unsigned off18_3 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned off18 = (off18_0 << 0) | (off18_1 << 6) | (off18_2 << 10) |
+			 (off18_3 << 14);
+
+	unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+
+	if (desc->NumOperands > 1) {
+		if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
+			status = DecodeRegisterClass(Inst, s1_d,
+						     &desc->OpInfo[0], Decoder);
+			if (status != MCDisassembler_Success)
+				return status;
+
+			MCOperand_CreateImm0(Inst, off18);
+		} else {
+			MCOperand_CreateImm0(Inst, off18);
+			status = DecodeRegisterClass(Inst, s1_d,
+						     &desc->OpInfo[0], Decoder);
+			if (status != MCDisassembler_Success)
+				return status;
+		}
+	} else {
+		MCOperand_CreateImm0(Inst, off18);
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn,
+				       uint64_t Address, void *Decoder)
+{
+	unsigned disp24_0 = fieldFromInstruction_4(Insn, 16, 16);
+	unsigned disp24_1 = fieldFromInstruction_4(Insn, 8, 8);
+	unsigned disp24 = (disp24_0 << 0) | (disp24_1 << 16);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	// Decode disp24.
+	MCOperand_CreateImm0(Inst, disp24);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned off10_0 = fieldFromInstruction_4(Insn, 16, 6);
+	unsigned off10_1 = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned off10 = (off10_0 << 0) | (off10_1 << 6);
+
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+
+	if (desc->NumOperands == 1) {
+		return DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder);
+	}
+
+	if (desc->NumOperands == 2) {
+		status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		if (desc->OpInfo[1].OperandType == MCOI_OPERAND_REGISTER) {
+			return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
+						   Decoder);
+		} else {
+			MCOperand_CreateImm0(Inst, off10);
+		}
+		return MCDisassembler_Success;
+	}
+
+	if (desc->NumOperands > 2) {
+		status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		MCOperand_CreateImm0(Inst, off10);
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned off16_0 = fieldFromInstruction_4(Insn, 16, 6);
+	unsigned off16_1 = fieldFromInstruction_4(Insn, 22, 6);
+	unsigned off16_2 = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned off16 = (off16_0 << 0) | (off16_1 << 10) | (off16_2 << 6);
+
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+
+	switch (MCInst_getOpcode(Inst)) {
+	case TRICORE_LD_A_bol:
+	case TRICORE_LD_B_bol:
+	case TRICORE_LD_BU_bol:
+	case TRICORE_LD_H_bol:
+	case TRICORE_LD_HU_bol:
+	case TRICORE_LD_W_bol:
+	case TRICORE_LEA_bol: {
+		// Decode s1_d.
+		status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		// Decode s2.
+		status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+		break;
+	}
+	case TRICORE_ST_A_bol:
+	case TRICORE_ST_B_bol:
+	case TRICORE_ST_H_bol:
+	case TRICORE_ST_W_bol: {
+		// Decode s2.
+		status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		// Decode s1_d.
+		status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+		break;
+	}
+	default:
+		return MCDisassembler_Fail;
+	}
+
+	// Decode off16.
+	MCOperand_CreateImm0(Inst, off16);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned const9 = fieldFromInstruction_4(Insn, 12, 9);
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	if (desc->NumOperands > 1) {
+		// Decode d.
+		status =
+			DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		// Decode s1.
+		status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	// Decode const9.
+	MCOperand_CreateImm0(Inst, const9);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned pos = fieldFromInstruction_4(Insn, 23, 5);
+	unsigned width = fieldFromInstruction_4(Insn, 16, 5);
+	unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	// Decode d.
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode const4.
+	MCOperand_CreateImm0(Inst, const4);
+
+	// Decode pos.
+	MCOperand_CreateImm0(Inst, pos);
+
+	// Decode width.
+	MCOperand_CreateImm0(Inst, width);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned const16 = fieldFromInstruction_4(Insn, 12, 16);
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	if (desc->NumOperands == 3) {
+		status =
+			DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		MCOperand_CreateImm0(Inst, const16);
+
+		return MCDisassembler_Success;
+	}
+
+	if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
+		status =
+			DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		MCOperand_CreateImm0(Inst, const16);
+	} else {
+		MCOperand_CreateImm0(Inst, const16);
+		status =
+			DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
+					uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned n = fieldFromInstruction_4(Insn, 16, 2);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	/// But even if the instruction is in RR format and has only one operand,
+	/// we cannot be sure whether the operand is s1 or s2
+	if (desc->NumOperands == 1) {
+		if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
+			switch (MCInst_getOpcode(Inst)) {
+			case TRICORE_CALLI_rr_v110: {
+				return DecodeRegisterClass(
+					Inst, s2, &desc->OpInfo[0], Decoder);
+			}
+			default: {
+				return DecodeRegisterClass(
+					Inst, s1, &desc->OpInfo[0], Decoder);
+			}
+			}
+		}
+		return MCDisassembler_Fail;
+	}
+
+	if (desc->NumOperands > 0) {
+		// Decode d.
+		status =
+			DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	if (desc->NumOperands > 1) {
+		status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	if (desc->NumOperands > 2) {
+		status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	if (desc->NumOperands > 3) {
+		MCOperand_CreateImm0(Inst, n);
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	// Decode d.
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status;
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned pos = fieldFromInstruction_4(Insn, 23, 5);
+	unsigned width = fieldFromInstruction_4(Insn, 16, 5);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	tryDecodeReg(0, d) tryDecodeReg(1, s1) tryDecodeReg(2, s2)
+		decodeImm(pos) decodeImm(width)
+
+			return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned d = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	// Decode d.
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned d = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned off4 = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	// Decode d.
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode off4.
+	MCOperand_CreateImm0(Inst, off4);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned off4 = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	// Decode s2.
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode off4.
+	MCOperand_CreateImm0(Inst, off4);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned n = fieldFromInstruction_2(Insn, 6, 2);
+	unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+
+	// Decode s1_d.
+	status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode n.
+	MCOperand_CreateImm0(Inst, n);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned const4 = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	if (desc->NumOperands != 2) {
+		return MCDisassembler_Fail;
+	}
+
+	// Decode disp4.
+	MCOperand_CreateImm0(Inst, disp4);
+
+	// Decode const4.
+	MCOperand_CreateImm0(Inst, const4);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned n = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	// Decode n.
+	MCOperand_CreateImm0(Inst, n);
+	// Decode disp4.
+	MCOperand_CreateImm0(Inst, disp4);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_2(Insn, 8, 4);
+	unsigned off4 = fieldFromInstruction_2(Insn, 12, 4);
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (is32Bit) // This instruction is 16-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode off4.
+	MCOperand_CreateImm0(Inst, off4);
+
+	return MCDisassembler_Success;
+}
+
+/// 32-bit Opcode Format
+
+static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	if (desc->NumOperands > 0) {
+		status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s3.
+	status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned n = fieldFromInstruction_4(Insn, 16, 2);
+	unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s3.
+	status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode n.
+	MCOperand_CreateImm0(Inst, n);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned pos1 = fieldFromInstruction_4(Insn, 16, 5);
+	unsigned pos2 = fieldFromInstruction_4(Insn, 23, 5);
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode pos1.
+	MCOperand_CreateImm0(Inst, pos1);
+
+	// Decode pos2.
+	MCOperand_CreateImm0(Inst, pos2);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned n = fieldFromInstruction_4(Insn, 16, 2);
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode n.
+	MCOperand_CreateImm0(Inst, n);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned const9 = fieldFromInstruction_4(Insn, 12, 9);
+	unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s3.
+	status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[2], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode const9.
+	MCOperand_CreateImm0(Inst, const9);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned width = fieldFromInstruction_4(Insn, 16, 5);
+	unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s3.
+	status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode width.
+	MCOperand_CreateImm0(Inst, width);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode const4.
+	MCOperand_CreateImm0(Inst, const4);
+
+	// Decode s3.
+	status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	if (desc->NumOperands == 3) {
+		return DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
+	}
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+	// Decode s3.
+	status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned disp15 = fieldFromInstruction_4(Insn, 16, 15);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	if (MCInst_getOpcode(Inst) == TRICORE_LOOP_brr) {
+		status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		MCOperand_CreateImm0(Inst, disp15);
+		return MCDisassembler_Success;
+	}
+
+	if (desc->NumOperands >= 2) {
+		status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0],
+					     Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+
+		if (desc->NumOperands >= 3) {
+			status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
+						     Decoder);
+			if (status != MCDisassembler_Success)
+				return status;
+		}
+	}
+
+	// Decode disp15.
+	MCOperand_CreateImm0(Inst, disp15);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned disp15 = fieldFromInstruction_4(Insn, 16, 15);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode const4.
+	MCOperand_CreateImm0(Inst, const4);
+
+	// Decode disp15.
+	MCOperand_CreateImm0(Inst, disp15);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
+	//	unsigned n = fieldFromInstruction_4(Insn, 16, 2);
+	unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s1.
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s2.
+	status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode s3.
+	status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	unsigned bpos3 = fieldFromInstruction_4(Insn, 8, 3);
+	unsigned b = fieldFromInstruction_4(Insn, 12, 1);
+
+	unsigned off18_0_5 = fieldFromInstruction_4(Insn, 16, 6);
+	unsigned off18_6_9 = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned off18_10_13 = fieldFromInstruction_4(Insn, 22, 4);
+	unsigned off18_14_17 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned off18 = (off18_0_5 << 0) | (off18_6_9 << 6) |
+			 (off18_10_13 << 10) | (off18_14_17 << 14);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	decodeImm(off18) decodeImm(bpos3) decodeImm(b)
+
+		return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn,
+					  uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned width = fieldFromInstruction_4(Insn, 16, 5);
+	unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
+	unsigned d = fieldFromInstruction_4(Insn, 28, 4);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	tryDecodeReg(0, d) tryDecodeReg(1, s1) tryDecodeReg(2, s3)
+		decodeImm(const4) decodeImm(width)
+
+			return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn,
+					 uint64_t Address, void *Decoder)
+{
+	DecodeStatus status = MCDisassembler_Fail;
+	unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
+
+	unsigned n_0_3 = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned n_4 = fieldFromInstruction_4(Insn, 7, 1);
+	unsigned n = (n_0_3 << 0) | (n_4 << 4);
+
+	unsigned disp15 = fieldFromInstruction_4(Insn, 16, 15);
+
+	unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
+	if (!is32Bit) // This instruction is 32-bit
+		return MCDisassembler_Fail;
+
+	const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)];
+	status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0], Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode n.
+	MCOperand_CreateImm0(Inst, n);
+
+	// Decode disp15.
+	MCOperand_CreateImm0(Inst, disp15);
+
+	return MCDisassembler_Success;
+}
+
+#define GET_SUBTARGETINFO_ENUM
+
+#include "TriCoreGenInstrInfo.inc"
+
+static inline bool tryGetInstruction16(const uint8_t *code, size_t code_len,
+				       MCInst *MI, uint16_t *size,
+				       uint64_t address, void *info,
+				       const uint8_t *decoderTable16)
+{
+	uint16_t insn16;
+	DecodeStatus Result;
+	if (!readInstruction16(code, code_len, &insn16)) {
+		return false;
+	}
+	// Calling the auto-generated decoder function.
+	Result = decodeInstruction_2(decoderTable16, MI, insn16, address, info,
+				     0);
+	if (Result != MCDisassembler_Fail) {
+		*size = 2;
+		return true;
+	}
+	return false;
+}
+
+static inline bool tryGetInstruction32(const uint8_t *code, size_t code_len,
+				       MCInst *MI, uint16_t *size,
+				       uint64_t address, void *info,
+				       const uint8_t *decoderTable32)
+{
+	uint32_t insn32;
+	DecodeStatus Result;
+	if (!readInstruction32(code, code_len, &insn32)) {
+		return false;
+	}
+	// Calling the auto-generated decoder function.
+	Result = decodeInstruction_4(decoderTable32, MI, insn32, address, info,
+				     0);
+	if (Result != MCDisassembler_Fail) {
+		*size = 4;
+		return true;
+	}
+	return false;
+}
+
+bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+			    MCInst *MI, uint16_t *size, uint64_t address,
+			    void *info)
+{
+	if (!ud) {
+		return false;
+	}
+
+	struct cs_struct *cs = (struct cs_struct *)ud;
+	if (MI->flat_insn->detail) {
+		memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
+	}
+
+	switch (cs->mode) {
+	case CS_MODE_TRICORE_110: {
+		if (tryGetInstruction16(code, code_len, MI, size, address, info,
+					DecoderTablev11016) ||
+		    tryGetInstruction32(code, code_len, MI, size, address, info,
+					DecoderTablev11032)) {
+			return true;
+		}
+		break;
+	}
+	case CS_MODE_TRICORE_161: {
+		if (tryGetInstruction32(code, code_len, MI, size, address, info,
+					DecoderTablev16132)) {
+			return true;
+		}
+		break;
+	}
+	case CS_MODE_TRICORE_162: {
+		if (tryGetInstruction16(code, code_len, MI, size, address, info,
+					DecoderTablev16216) ||
+		    tryGetInstruction32(code, code_len, MI, size, address, info,
+					DecoderTablev16232)) {
+			return true;
+		}
+		break;
+	}
+	default:
+		break;
+	}
+
+	return tryGetInstruction16(code, code_len, MI, size, address, info,
+				   DecoderTable16) ||
+	       tryGetInstruction32(code, code_len, MI, size, address, info,
+				   DecoderTable32);
+}
+
+void TriCore_init(MCRegisterInfo *MRI)
+{
+	/*
+	InitMCRegisterInfo(TriCoreRegDesc, 45, RA, PC,
+			TriCoreMCRegisterClasses, 4,
+			TriCoreRegUnitRoots,
+			16,
+			TriCoreRegDiffLists,
+			TriCoreRegStrings,
+			TriCoreSubRegIdxLists,
+			1,
+			TriCoreSubRegIdxRanges,
+			TriCoreRegEncodingTable);
+	*/
+
+	MCRegisterInfo_InitMCRegisterInfo(
+		MRI, TriCoreRegDesc, ARR_SIZE(TriCoreRegDesc), 0, 0,
+		TriCoreMCRegisterClasses, ARR_SIZE(TriCoreMCRegisterClasses), 0,
+		0, TriCoreRegDiffLists, 0, TriCoreSubRegIdxLists, 1, 0);
+}
+
+#endif
diff --git a/arch/TriCore/TriCoreDisassembler.h b/arch/TriCore/TriCoreDisassembler.h
new file mode 100644
index 0000000000..30bb4d12af
--- /dev/null
+++ b/arch/TriCore/TriCoreDisassembler.h
@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_TRICOREDISASSEMBLER_H
+#define CS_TRICOREDISASSEMBLER_H
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include <capstone/capstone.h>
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void TriCore_init(MCRegisterInfo *MRI);
+
+bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+			    MCInst *instr, uint16_t *size, uint64_t address,
+			    void *info);
+
+#endif
diff --git a/arch/TriCore/TriCoreGenAsmWriter.inc b/arch/TriCore/TriCoreGenAsmWriter.inc
new file mode 100644
index 0000000000..c21aad5499
--- /dev/null
+++ b/arch/TriCore/TriCoreGenAsmWriter.inc
@@ -0,0 +1,3691 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#include <capstone/platform.h>
+#include <assert.h>
+
+/// getMnemonic - This method is automatically generated by tablegen
+/// from the instruction set description.
+MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
+#ifndef CAPSTONE_DIET
+  static const char AsmStrs[] = {
+  /* 0 */ "sub %d15, \0"
+  /* 11 */ "add %d15, \0"
+  /* 22 */ "and %d15, \0"
+  /* 33 */ "jne %d15, \0"
+  /* 44 */ "jeq %d15, \0"
+  /* 55 */ "or %d15, \0"
+  /* 65 */ "jz.t %d15, \0"
+  /* 77 */ "jnz.t %d15, \0"
+  /* 90 */ "lt %d15, \0"
+  /* 100 */ "lt.u %d15, \0"
+  /* 112 */ "mov %d15, \0"
+  /* 123 */ "jz %d15, \0"
+  /* 133 */ "jnz %d15, \0"
+  /* 144 */ "sub.a %sp, \0"
+  /* 156 */ "ftoq31 \0"
+  /* 164 */ "csub.a \0"
+  /* 172 */ "subsc.a \0"
+  /* 181 */ "addsc.a \0"
+  /* 190 */ "difsc.a \0"
+  /* 199 */ "cadd.a \0"
+  /* 207 */ "ld.a \0"
+  /* 213 */ "tlbprobe.a \0"
+  /* 225 */ "ge.a \0"
+  /* 231 */ "jne.a \0"
+  /* 238 */ "addih.a \0"
+  /* 247 */ "movh.a \0"
+  /* 255 */ "sel.a \0"
+  /* 262 */ "csubn.a \0"
+  /* 271 */ "caddn.a \0"
+  /* 280 */ "seln.a \0"
+  /* 288 */ "swap.a \0"
+  /* 296 */ "jeq.a \0"
+  /* 303 */ "lt.a \0"
+  /* 309 */ "st.a \0"
+  /* 315 */ "mov.a \0"
+  /* 322 */ "nez.a \0"
+  /* 329 */ "jz.a \0"
+  /* 335 */ "jnz.a \0"
+  /* 342 */ "eqz.a \0"
+  /* 349 */ "movz.a \0"
+  /* 357 */ "mov.aa \0"
+  /* 365 */ "ld.da \0"
+  /* 372 */ "st.da \0"
+  /* 379 */ "lea \0"
+  /* 384 */ "lha \0"
+  /* 389 */ "sha \0"
+  /* 394 */ "ja \0"
+  /* 398 */ "jla \0"
+  /* 403 */ "fcalla \0"
+  /* 411 */ "crc32.b \0"
+  /* 420 */ "sha.b \0"
+  /* 427 */ "sub.b \0"
+  /* 434 */ "add.b \0"
+  /* 441 */ "ld.b \0"
+  /* 447 */ "absdif.b \0"
+  /* 457 */ "sh.b \0"
+  /* 463 */ "min.b \0"
+  /* 470 */ "clo.b \0"
+  /* 477 */ "eq.b \0"
+  /* 483 */ "abs.b \0"
+  /* 490 */ "subs.b \0"
+  /* 498 */ "adds.b \0"
+  /* 506 */ "absdifs.b \0"
+  /* 517 */ "cls.b \0"
+  /* 524 */ "abss.b \0"
+  /* 532 */ "sat.b \0"
+  /* 539 */ "dvinit.b \0"
+  /* 549 */ "lt.b \0"
+  /* 555 */ "st.b \0"
+  /* 561 */ "max.b \0"
+  /* 568 */ "eqany.b \0"
+  /* 577 */ "clz.b \0"
+  /* 584 */ "csub \0"
+  /* 590 */ "msub \0"
+  /* 596 */ "rsub \0"
+  /* 602 */ "subc \0"
+  /* 608 */ "addc \0"
+  /* 614 */ "ld.d \0"
+  /* 620 */ "st.d \0"
+  /* 626 */ "mov.d \0"
+  /* 633 */ "cadd \0"
+  /* 639 */ "madd \0"
+  /* 645 */ "jned \0"
+  /* 651 */ "nand \0"
+  /* 657 */ "and.ge \0"
+  /* 665 */ "sh.ge \0"
+  /* 672 */ "xor.ge \0"
+  /* 680 */ "jge \0"
+  /* 685 */ "bmerge \0"
+  /* 693 */ "disable \0"
+  /* 702 */ "shuffle \0"
+  /* 711 */ "and.ne \0"
+  /* 719 */ "sh.ne \0"
+  /* 726 */ "xor.ne \0"
+  /* 734 */ "jne \0"
+  /* 739 */ "restore \0"
+  /* 748 */ "msub.f \0"
+  /* 756 */ "madd.f \0"
+  /* 764 */ "qseed.f \0"
+  /* 773 */ "mul.f \0"
+  /* 780 */ "cmp.f \0"
+  /* 787 */ "div.f \0"
+  /* 794 */ "absdif \0"
+  /* 802 */ "q31tof \0"
+  /* 810 */ "itof \0"
+  /* 816 */ "hptof \0"
+  /* 823 */ "utof \0"
+  /* 829 */ "sha.h \0"
+  /* 836 */ "msub.h \0"
+  /* 844 */ "msubad.h \0"
+  /* 854 */ "madd.h \0"
+  /* 862 */ "ld.h \0"
+  /* 868 */ "absdif.h \0"
+  /* 878 */ "sh.h \0"
+  /* 884 */ "mul.h \0"
+  /* 891 */ "msubm.h \0"
+  /* 900 */ "msubadm.h \0"
+  /* 911 */ "maddm.h \0"
+  /* 920 */ "mulm.h \0"
+  /* 928 */ "maddsum.h \0"
+  /* 939 */ "min.h \0"
+  /* 946 */ "clo.h \0"
+  /* 953 */ "eq.h \0"
+  /* 959 */ "msubr.h \0"
+  /* 968 */ "msubadr.h \0"
+  /* 979 */ "maddr.h \0"
+  /* 988 */ "mulr.h \0"
+  /* 996 */ "maddsur.h \0"
+  /* 1007 */ "abs.h \0"
+  /* 1014 */ "msubs.h \0"
+  /* 1023 */ "msubads.h \0"
+  /* 1034 */ "madds.h \0"
+  /* 1043 */ "absdifs.h \0"
+  /* 1054 */ "cls.h \0"
+  /* 1061 */ "msubms.h \0"
+  /* 1071 */ "msubadms.h \0"
+  /* 1083 */ "maddms.h \0"
+  /* 1093 */ "mulms.h \0"
+  /* 1102 */ "maddsums.h \0"
+  /* 1114 */ "msubrs.h \0"
+  /* 1124 */ "msubadrs.h \0"
+  /* 1136 */ "maddrs.h \0"
+  /* 1146 */ "maddsurs.h \0"
+  /* 1158 */ "abss.h \0"
+  /* 1166 */ "maddsus.h \0"
+  /* 1177 */ "sat.h \0"
+  /* 1184 */ "dvinit.h \0"
+  /* 1194 */ "lt.h \0"
+  /* 1200 */ "st.h \0"
+  /* 1206 */ "maddsu.h \0"
+  /* 1216 */ "max.h \0"
+  /* 1223 */ "eqany.h \0"
+  /* 1232 */ "clz.h \0"
+  /* 1239 */ "addih \0"
+  /* 1246 */ "sh \0"
+  /* 1250 */ "movh \0"
+  /* 1256 */ "tlbprobe.i \0"
+  /* 1268 */ "addi \0"
+  /* 1274 */ "jnei \0"
+  /* 1280 */ "ji \0"
+  /* 1284 */ "jli \0"
+  /* 1289 */ "fcalli \0"
+  /* 1297 */ "ftoi \0"
+  /* 1303 */ "dvadj \0"
+  /* 1310 */ "unpack \0"
+  /* 1318 */ "imask \0"
+  /* 1325 */ "sel \0"
+  /* 1330 */ "updfl \0"
+  /* 1337 */ "jl \0"
+  /* 1341 */ "fcall \0"
+  /* 1348 */ "syscall \0"
+  /* 1357 */ "mul \0"
+  /* 1362 */ "msubm \0"
+  /* 1369 */ "maddm \0"
+  /* 1376 */ "mulm \0"
+  /* 1382 */ "csubn \0"
+  /* 1389 */ "crcn \0"
+  /* 1395 */ "caddn \0"
+  /* 1402 */ "andn \0"
+  /* 1408 */ "ixmin \0"
+  /* 1415 */ "seln \0"
+  /* 1421 */ "orn \0"
+  /* 1426 */ "cmovn \0"
+  /* 1433 */ "clo \0"
+  /* 1438 */ "tlbmap \0"
+  /* 1446 */ "tlbdemap \0"
+  /* 1456 */ "dvstep \0"
+  /* 1464 */ "ftohp \0"
+  /* 1471 */ "loop \0"
+  /* 1477 */ "msub.q \0"
+  /* 1485 */ "madd.q \0"
+  /* 1493 */ "ld.q \0"
+  /* 1499 */ "mul.q \0"
+  /* 1506 */ "msubm.q \0"
+  /* 1515 */ "maddm.q \0"
+  /* 1524 */ "msubr.q \0"
+  /* 1533 */ "maddr.q \0"
+  /* 1542 */ "mulr.q \0"
+  /* 1550 */ "msubs.q \0"
+  /* 1559 */ "madds.q \0"
+  /* 1568 */ "msubrs.q \0"
+  /* 1578 */ "maddrs.q \0"
+  /* 1588 */ "st.q \0"
+  /* 1594 */ "and.eq \0"
+  /* 1602 */ "sh.eq \0"
+  /* 1609 */ "xor.eq \0"
+  /* 1617 */ "jeq \0"
+  /* 1622 */ "mfcr \0"
+  /* 1628 */ "mtcr \0"
+  /* 1634 */ "xnor \0"
+  /* 1640 */ "xor \0"
+  /* 1645 */ "bisr \0"
+  /* 1651 */ "dextr \0"
+  /* 1658 */ "shas \0"
+  /* 1664 */ "abs \0"
+  /* 1669 */ "msubs \0"
+  /* 1676 */ "rsubs \0"
+  /* 1683 */ "madds \0"
+  /* 1690 */ "absdifs \0"
+  /* 1699 */ "cls \0"
+  /* 1704 */ "muls \0"
+  /* 1710 */ "msubms \0"
+  /* 1718 */ "maddms \0"
+  /* 1726 */ "abss \0"
+  /* 1732 */ "and.and.t \0"
+  /* 1743 */ "sh.and.t \0"
+  /* 1753 */ "or.and.t \0"
+  /* 1763 */ "sh.nand.t \0"
+  /* 1774 */ "and.andn.t \0"
+  /* 1786 */ "sh.andn.t \0"
+  /* 1797 */ "or.andn.t \0"
+  /* 1808 */ "sh.orn.t \0"
+  /* 1818 */ "insn.t \0"
+  /* 1826 */ "and.or.t \0"
+  /* 1836 */ "sh.or.t \0"
+  /* 1845 */ "or.or.t \0"
+  /* 1854 */ "and.nor.t \0"
+  /* 1865 */ "sh.nor.t \0"
+  /* 1875 */ "or.nor.t \0"
+  /* 1885 */ "sh.xnor.t \0"
+  /* 1896 */ "sh.xor.t \0"
+  /* 1906 */ "ins.t \0"
+  /* 1913 */ "st.t \0"
+  /* 1919 */ "jz.t \0"
+  /* 1925 */ "jnz.t \0"
+  /* 1932 */ "addsc.at \0"
+  /* 1942 */ "bsplit \0"
+  /* 1950 */ "dvinit \0"
+  /* 1958 */ "and.lt \0"
+  /* 1966 */ "sh.lt \0"
+  /* 1973 */ "xor.lt \0"
+  /* 1981 */ "jlt \0"
+  /* 1986 */ "not \0"
+  /* 1991 */ "insert \0"
+  /* 1999 */ "ldmst \0"
+  /* 2006 */ "msub.u \0"
+  /* 2014 */ "madd.u \0"
+  /* 2022 */ "and.ge.u \0"
+  /* 2032 */ "sh.ge.u \0"
+  /* 2041 */ "xor.ge.u \0"
+  /* 2051 */ "jge.u \0"
+  /* 2058 */ "mul.u \0"
+  /* 2065 */ "msubm.u \0"
+  /* 2074 */ "maddm.u \0"
+  /* 2083 */ "mulm.u \0"
+  /* 2091 */ "ixmin.u \0"
+  /* 2100 */ "dvstep.u \0"
+  /* 2110 */ "extr.u \0"
+  /* 2118 */ "msubs.u \0"
+  /* 2127 */ "rsubs.u \0"
+  /* 2136 */ "madds.u \0"
+  /* 2145 */ "muls.u \0"
+  /* 2153 */ "msubms.u \0"
+  /* 2163 */ "maddms.u \0"
+  /* 2173 */ "dvinit.u \0"
+  /* 2183 */ "and.lt.u \0"
+  /* 2193 */ "sh.lt.u \0"
+  /* 2202 */ "xor.lt.u \0"
+  /* 2212 */ "jlt.u \0"
+  /* 2219 */ "div.u \0"
+  /* 2226 */ "mov.u \0"
+  /* 2233 */ "ixmax.u \0"
+  /* 2242 */ "ld.bu \0"
+  /* 2249 */ "min.bu \0"
+  /* 2257 */ "subs.bu \0"
+  /* 2266 */ "adds.bu \0"
+  /* 2275 */ "sat.bu \0"
+  /* 2283 */ "dvinit.bu \0"
+  /* 2294 */ "lt.bu \0"
+  /* 2301 */ "max.bu \0"
+  /* 2309 */ "ld.hu \0"
+  /* 2316 */ "min.hu \0"
+  /* 2324 */ "subs.hu \0"
+  /* 2333 */ "adds.hu \0"
+  /* 2342 */ "sat.hu \0"
+  /* 2350 */ "dvinit.hu \0"
+  /* 2361 */ "lt.hu \0"
+  /* 2368 */ "max.hu \0"
+  /* 2376 */ "ftou \0"
+  /* 2382 */ "loopu \0"
+  /* 2389 */ "lt.wu \0"
+  /* 2396 */ "div \0"
+  /* 2401 */ "cmov \0"
+  /* 2407 */ "crc32b.w \0"
+  /* 2417 */ "ld.w \0"
+  /* 2423 */ "crc32l.w \0"
+  /* 2433 */ "swap.w \0"
+  /* 2441 */ "eq.w \0"
+  /* 2447 */ "lt.w \0"
+  /* 2453 */ "popcnt.w \0"
+  /* 2463 */ "st.w \0"
+  /* 2469 */ "ixmax \0"
+  /* 2476 */ "subx \0"
+  /* 2482 */ "ldlcx \0"
+  /* 2489 */ "stlcx \0"
+  /* 2496 */ "lducx \0"
+  /* 2503 */ "stucx \0"
+  /* 2510 */ "addx \0"
+  /* 2516 */ "parity \0"
+  /* 2524 */ "ftoq31z \0"
+  /* 2533 */ "jgez \0"
+  /* 2539 */ "jlez \0"
+  /* 2545 */ "ftoiz \0"
+  /* 2552 */ "jz \0"
+  /* 2556 */ "clz \0"
+  /* 2561 */ "jnz \0"
+  /* 2566 */ "jgtz \0"
+  /* 2572 */ "jltz \0"
+  /* 2578 */ "ftouz \0"
+  /* 2585 */ "swap.a [+\0"
+  /* 2595 */ "st.a [+\0"
+  /* 2603 */ "st.da [+\0"
+  /* 2612 */ "st.b [+\0"
+  /* 2620 */ "st.d [+\0"
+  /* 2628 */ "st.h [+\0"
+  /* 2636 */ "cachea.i [+\0"
+  /* 2648 */ "cachei.i [+\0"
+  /* 2660 */ "cachea.wi [+\0"
+  /* 2673 */ "cachei.wi [+\0"
+  /* 2686 */ "st.q [+\0"
+  /* 2694 */ "ldmst [+\0"
+  /* 2703 */ "cachea.w [+\0"
+  /* 2715 */ "cachei.w [+\0"
+  /* 2727 */ "swapmsk.w [+\0"
+  /* 2740 */ "cmpswap.w [+\0"
+  /* 2753 */ "st.w [+\0"
+  /* 2761 */ "# XRay Function Patchable RET.\0"
+  /* 2792 */ "# XRay Typed Event Log.\0"
+  /* 2816 */ "# XRay Custom Event Log.\0"
+  /* 2841 */ "# XRay Function Enter.\0"
+  /* 2864 */ "# XRay Tail Call Exit.\0"
+  /* 2887 */ "# XRay Function Exit.\0"
+  /* 2909 */ "LIFETIME_END\0"
+  /* 2922 */ "PSEUDO_PROBE\0"
+  /* 2935 */ "BUNDLE\0"
+  /* 2942 */ "DBG_VALUE\0"
+  /* 2952 */ "DBG_INSTR_REF\0"
+  /* 2966 */ "DBG_PHI\0"
+  /* 2974 */ "DBG_LABEL\0"
+  /* 2984 */ "LIFETIME_START\0"
+  /* 2999 */ "DBG_VALUE_LIST\0"
+  /* 3014 */ "ld.a %a15, [\0"
+  /* 3027 */ "ld.b %d15, [\0"
+  /* 3040 */ "ld.h %d15, [\0"
+  /* 3053 */ "ld.bu %d15, [\0"
+  /* 3067 */ "ld.w %d15, [\0"
+  /* 3080 */ "swap.a [\0"
+  /* 3089 */ "st.a [\0"
+  /* 3096 */ "st.da [\0"
+  /* 3104 */ "st.b [\0"
+  /* 3111 */ "st.d [\0"
+  /* 3118 */ "st.h [\0"
+  /* 3125 */ "cachea.i [\0"
+  /* 3136 */ "cachei.i [\0"
+  /* 3147 */ "cachea.wi [\0"
+  /* 3159 */ "cachei.wi [\0"
+  /* 3171 */ "st.q [\0"
+  /* 3178 */ "ldmst [\0"
+  /* 3186 */ "cachea.w [\0"
+  /* 3197 */ "cachei.w [\0"
+  /* 3208 */ "swapmsk.w [\0"
+  /* 3220 */ "cmpswap.w [\0"
+  /* 3232 */ "st.w [\0"
+  /* 3239 */ "ldlcx [\0"
+  /* 3247 */ "stlcx [\0"
+  /* 3255 */ "lducx [\0"
+  /* 3263 */ "stucx [\0"
+  /* 3271 */ "st.a [%a15]\0"
+  /* 3283 */ "st.b [%a15]\0"
+  /* 3295 */ "st.h [%a15]\0"
+  /* 3307 */ "st.w [%a15]\0"
+  /* 3319 */ "ld.a %a15, [%sp]\0"
+  /* 3336 */ "ld.w %d15, [%sp]\0"
+  /* 3353 */ "st.a [%sp]\0"
+  /* 3364 */ "st.w [%sp]\0"
+  /* 3375 */ "tlbflush.a\0"
+  /* 3386 */ "tlbflush.b\0"
+  /* 3397 */ "dsync\0"
+  /* 3403 */ "isync\0"
+  /* 3409 */ "rfe\0"
+  /* 3413 */ "enable\0"
+  /* 3420 */ "disable\0"
+  /* 3428 */ "debug\0"
+  /* 3434 */ "# FEntry call\0"
+  /* 3448 */ "rfm\0"
+  /* 3452 */ "nop\0"
+  /* 3456 */ "fret\0"
+  /* 3461 */ "wait\0"
+  /* 3466 */ "trapv\0"
+  /* 3472 */ "trapsv\0"
+  /* 3479 */ "rstv\0"
+  /* 3484 */ "rslcx\0"
+  /* 3490 */ "svlcx\0"
+};
+#endif // CAPSTONE_DIET
+
+  static const uint32_t OpInfo0[] = {
+    0U,	// PHI
+    0U,	// INLINEASM
+    0U,	// INLINEASM_BR
+    0U,	// CFI_INSTRUCTION
+    0U,	// EH_LABEL
+    0U,	// GC_LABEL
+    0U,	// ANNOTATION_LABEL
+    0U,	// KILL
+    0U,	// EXTRACT_SUBREG
+    0U,	// INSERT_SUBREG
+    0U,	// IMPLICIT_DEF
+    0U,	// SUBREG_TO_REG
+    0U,	// COPY_TO_REGCLASS
+    2943U,	// DBG_VALUE
+    3000U,	// DBG_VALUE_LIST
+    2953U,	// DBG_INSTR_REF
+    2967U,	// DBG_PHI
+    2975U,	// DBG_LABEL
+    0U,	// REG_SEQUENCE
+    0U,	// COPY
+    2936U,	// BUNDLE
+    2985U,	// LIFETIME_START
+    2910U,	// LIFETIME_END
+    2923U,	// PSEUDO_PROBE
+    0U,	// ARITH_FENCE
+    0U,	// STACKMAP
+    3435U,	// FENTRY_CALL
+    0U,	// PATCHPOINT
+    0U,	// LOAD_STACK_GUARD
+    0U,	// PREALLOCATED_SETUP
+    0U,	// PREALLOCATED_ARG
+    0U,	// STATEPOINT
+    0U,	// LOCAL_ESCAPE
+    0U,	// FAULTING_OP
+    0U,	// PATCHABLE_OP
+    2842U,	// PATCHABLE_FUNCTION_ENTER
+    2762U,	// PATCHABLE_RET
+    2888U,	// PATCHABLE_FUNCTION_EXIT
+    2865U,	// PATCHABLE_TAIL_CALL
+    2817U,	// PATCHABLE_EVENT_CALL
+    2793U,	// PATCHABLE_TYPED_EVENT_CALL
+    0U,	// ICALL_BRANCH_FUNNEL
+    0U,	// MEMBARRIER
+    0U,	// G_ASSERT_SEXT
+    0U,	// G_ASSERT_ZEXT
+    0U,	// G_ASSERT_ALIGN
+    0U,	// G_ADD
+    0U,	// G_SUB
+    0U,	// G_MUL
+    0U,	// G_SDIV
+    0U,	// G_UDIV
+    0U,	// G_SREM
+    0U,	// G_UREM
+    0U,	// G_SDIVREM
+    0U,	// G_UDIVREM
+    0U,	// G_AND
+    0U,	// G_OR
+    0U,	// G_XOR
+    0U,	// G_IMPLICIT_DEF
+    0U,	// G_PHI
+    0U,	// G_FRAME_INDEX
+    0U,	// G_GLOBAL_VALUE
+    0U,	// G_EXTRACT
+    0U,	// G_UNMERGE_VALUES
+    0U,	// G_INSERT
+    0U,	// G_MERGE_VALUES
+    0U,	// G_BUILD_VECTOR
+    0U,	// G_BUILD_VECTOR_TRUNC
+    0U,	// G_CONCAT_VECTORS
+    0U,	// G_PTRTOINT
+    0U,	// G_INTTOPTR
+    0U,	// G_BITCAST
+    0U,	// G_FREEZE
+    0U,	// G_INTRINSIC_FPTRUNC_ROUND
+    0U,	// G_INTRINSIC_TRUNC
+    0U,	// G_INTRINSIC_ROUND
+    0U,	// G_INTRINSIC_LRINT
+    0U,	// G_INTRINSIC_ROUNDEVEN
+    0U,	// G_READCYCLECOUNTER
+    0U,	// G_LOAD
+    0U,	// G_SEXTLOAD
+    0U,	// G_ZEXTLOAD
+    0U,	// G_INDEXED_LOAD
+    0U,	// G_INDEXED_SEXTLOAD
+    0U,	// G_INDEXED_ZEXTLOAD
+    0U,	// G_STORE
+    0U,	// G_INDEXED_STORE
+    0U,	// G_ATOMIC_CMPXCHG_WITH_SUCCESS
+    0U,	// G_ATOMIC_CMPXCHG
+    0U,	// G_ATOMICRMW_XCHG
+    0U,	// G_ATOMICRMW_ADD
+    0U,	// G_ATOMICRMW_SUB
+    0U,	// G_ATOMICRMW_AND
+    0U,	// G_ATOMICRMW_NAND
+    0U,	// G_ATOMICRMW_OR
+    0U,	// G_ATOMICRMW_XOR
+    0U,	// G_ATOMICRMW_MAX
+    0U,	// G_ATOMICRMW_MIN
+    0U,	// G_ATOMICRMW_UMAX
+    0U,	// G_ATOMICRMW_UMIN
+    0U,	// G_ATOMICRMW_FADD
+    0U,	// G_ATOMICRMW_FSUB
+    0U,	// G_ATOMICRMW_FMAX
+    0U,	// G_ATOMICRMW_FMIN
+    0U,	// G_ATOMICRMW_UINC_WRAP
+    0U,	// G_ATOMICRMW_UDEC_WRAP
+    0U,	// G_FENCE
+    0U,	// G_BRCOND
+    0U,	// G_BRINDIRECT
+    0U,	// G_INVOKE_REGION_START
+    0U,	// G_INTRINSIC
+    0U,	// G_INTRINSIC_W_SIDE_EFFECTS
+    0U,	// G_ANYEXT
+    0U,	// G_TRUNC
+    0U,	// G_CONSTANT
+    0U,	// G_FCONSTANT
+    0U,	// G_VASTART
+    0U,	// G_VAARG
+    0U,	// G_SEXT
+    0U,	// G_SEXT_INREG
+    0U,	// G_ZEXT
+    0U,	// G_SHL
+    0U,	// G_LSHR
+    0U,	// G_ASHR
+    0U,	// G_FSHL
+    0U,	// G_FSHR
+    0U,	// G_ROTR
+    0U,	// G_ROTL
+    0U,	// G_ICMP
+    0U,	// G_FCMP
+    0U,	// G_SELECT
+    0U,	// G_UADDO
+    0U,	// G_UADDE
+    0U,	// G_USUBO
+    0U,	// G_USUBE
+    0U,	// G_SADDO
+    0U,	// G_SADDE
+    0U,	// G_SSUBO
+    0U,	// G_SSUBE
+    0U,	// G_UMULO
+    0U,	// G_SMULO
+    0U,	// G_UMULH
+    0U,	// G_SMULH
+    0U,	// G_UADDSAT
+    0U,	// G_SADDSAT
+    0U,	// G_USUBSAT
+    0U,	// G_SSUBSAT
+    0U,	// G_USHLSAT
+    0U,	// G_SSHLSAT
+    0U,	// G_SMULFIX
+    0U,	// G_UMULFIX
+    0U,	// G_SMULFIXSAT
+    0U,	// G_UMULFIXSAT
+    0U,	// G_SDIVFIX
+    0U,	// G_UDIVFIX
+    0U,	// G_SDIVFIXSAT
+    0U,	// G_UDIVFIXSAT
+    0U,	// G_FADD
+    0U,	// G_FSUB
+    0U,	// G_FMUL
+    0U,	// G_FMA
+    0U,	// G_FMAD
+    0U,	// G_FDIV
+    0U,	// G_FREM
+    0U,	// G_FPOW
+    0U,	// G_FPOWI
+    0U,	// G_FEXP
+    0U,	// G_FEXP2
+    0U,	// G_FLOG
+    0U,	// G_FLOG2
+    0U,	// G_FLOG10
+    0U,	// G_FNEG
+    0U,	// G_FPEXT
+    0U,	// G_FPTRUNC
+    0U,	// G_FPTOSI
+    0U,	// G_FPTOUI
+    0U,	// G_SITOFP
+    0U,	// G_UITOFP
+    0U,	// G_FABS
+    0U,	// G_FCOPYSIGN
+    0U,	// G_IS_FPCLASS
+    0U,	// G_FCANONICALIZE
+    0U,	// G_FMINNUM
+    0U,	// G_FMAXNUM
+    0U,	// G_FMINNUM_IEEE
+    0U,	// G_FMAXNUM_IEEE
+    0U,	// G_FMINIMUM
+    0U,	// G_FMAXIMUM
+    0U,	// G_PTR_ADD
+    0U,	// G_PTRMASK
+    0U,	// G_SMIN
+    0U,	// G_SMAX
+    0U,	// G_UMIN
+    0U,	// G_UMAX
+    0U,	// G_ABS
+    0U,	// G_LROUND
+    0U,	// G_LLROUND
+    0U,	// G_BR
+    0U,	// G_BRJT
+    0U,	// G_INSERT_VECTOR_ELT
+    0U,	// G_EXTRACT_VECTOR_ELT
+    0U,	// G_SHUFFLE_VECTOR
+    0U,	// G_CTTZ
+    0U,	// G_CTTZ_ZERO_UNDEF
+    0U,	// G_CTLZ
+    0U,	// G_CTLZ_ZERO_UNDEF
+    0U,	// G_CTPOP
+    0U,	// G_BSWAP
+    0U,	// G_BITREVERSE
+    0U,	// G_FCEIL
+    0U,	// G_FCOS
+    0U,	// G_FSIN
+    0U,	// G_FSQRT
+    0U,	// G_FFLOOR
+    0U,	// G_FRINT
+    0U,	// G_FNEARBYINT
+    0U,	// G_ADDRSPACE_CAST
+    0U,	// G_BLOCK_ADDR
+    0U,	// G_JUMP_TABLE
+    0U,	// G_DYN_STACKALLOC
+    0U,	// G_STRICT_FADD
+    0U,	// G_STRICT_FSUB
+    0U,	// G_STRICT_FMUL
+    0U,	// G_STRICT_FDIV
+    0U,	// G_STRICT_FREM
+    0U,	// G_STRICT_FMA
+    0U,	// G_STRICT_FSQRT
+    0U,	// G_READ_REGISTER
+    0U,	// G_WRITE_REGISTER
+    0U,	// G_MEMCPY
+    0U,	// G_MEMCPY_INLINE
+    0U,	// G_MEMMOVE
+    0U,	// G_MEMSET
+    0U,	// G_BZERO
+    0U,	// G_VECREDUCE_SEQ_FADD
+    0U,	// G_VECREDUCE_SEQ_FMUL
+    0U,	// G_VECREDUCE_FADD
+    0U,	// G_VECREDUCE_FMUL
+    0U,	// G_VECREDUCE_FMAX
+    0U,	// G_VECREDUCE_FMIN
+    0U,	// G_VECREDUCE_ADD
+    0U,	// G_VECREDUCE_MUL
+    0U,	// G_VECREDUCE_AND
+    0U,	// G_VECREDUCE_OR
+    0U,	// G_VECREDUCE_XOR
+    0U,	// G_VECREDUCE_SMAX
+    0U,	// G_VECREDUCE_SMIN
+    0U,	// G_VECREDUCE_UMAX
+    0U,	// G_VECREDUCE_UMIN
+    0U,	// G_SBFX
+    0U,	// G_UBFX
+    4603U,	// ABSDIFS_B_rr_v110
+    5140U,	// ABSDIFS_H_rr
+    5787U,	// ABSDIFS_rc
+    5787U,	// ABSDIFS_rr
+    4544U,	// ABSDIF_B_rr
+    4965U,	// ABSDIF_H_rr
+    536875803U,	// ABSDIF_rc
+    4891U,	// ABSDIF_rr
+    34607629U,	// ABSS_B_rr_v110
+    34608263U,	// ABSS_H_rr
+    34608831U,	// ABSS_rr
+    33559012U,	// ABS_B_rr
+    33559536U,	// ABS_H_rr
+    33560193U,	// ABS_rr
+    536875617U,	// ADDC_rc
+    4705U,	// ADDC_rr
+    1073746159U,	// ADDIH_A_rlc
+    1073747160U,	// ADDIH_rlc
+    1610618101U,	// ADDI_rlc
+    2148538253U,	// ADDSC_AT_rr
+    6029U,	// ADDSC_AT_rr_v110
+    2148536502U,	// ADDSC_A_rr
+    4278U,	// ADDSC_A_rr_v110
+    67113142U,	// ADDSC_A_srrs
+    2684358838U,	// ADDSC_A_srrs_v110
+    6363U,	// ADDS_BU_rr_v110
+    4595U,	// ADDS_B_rr
+    5132U,	// ADDS_H
+    6430U,	// ADDS_HU
+    6234U,	// ADDS_U
+    536877146U,	// ADDS_U_rc
+    536876693U,	// ADDS_rc
+    5781U,	// ADDS_rr
+    33560213U,	// ADDS_srr
+    536877519U,	// ADDX_rc
+    6607U,	// ADDX_rr
+    4297U,	// ADD_A_rr
+    35655881U,	// ADD_A_src
+    33558729U,	// ADD_A_srr
+    4531U,	// ADD_B_rr
+    3325039350U,	// ADD_F_rrr
+    4952U,	// ADD_H_rr
+    536875643U,	// ADD_rc
+    4731U,	// ADD_rr
+    35656315U,	// ADD_src
+    35655692U,	// ADD_src_15a
+    35721851U,	// ADD_src_a15
+    33559163U,	// ADD_srr
+    33558540U,	// ADD_srr_15a
+    33624699U,	// ADD_srr_a15
+    3758102259U,	// ANDN_T
+    536876411U,	// ANDN_rc
+    5499U,	// ANDN_rr
+    3758102255U,	// AND_ANDN_T
+    3758102213U,	// AND_AND_T
+    536876603U,	// AND_EQ_rc
+    5691U,	// AND_EQ_rr
+    536877031U,	// AND_GE_U_rc
+    6119U,	// AND_GE_U_rr
+    536875666U,	// AND_GE_rc
+    4754U,	// AND_GE_rr
+    536877192U,	// AND_LT_U_rc
+    6280U,	// AND_LT_U_rr
+    536876967U,	// AND_LT_rc
+    6055U,	// AND_LT_rr
+    536875720U,	// AND_NE_rc
+    4808U,	// AND_NE_rr
+    3758102335U,	// AND_NOR_T
+    3758102307U,	// AND_OR_T
+    3758102217U,	// AND_T
+    536875661U,	// AND_rc
+    4749U,	// AND_rr
+    139287U,	// AND_sc
+    139287U,	// AND_sc_v110
+    33559181U,	// AND_srr
+    33559181U,	// AND_srr_v110
+    13934U,	// BISR_rc
+    13934U,	// BISR_rc_v161
+    140910U,	// BISR_sc
+    140910U,	// BISR_sc_v110
+    4782U,	// BMERGAE_rr_v110
+    4782U,	// BMERGE_rr
+    33560471U,	// BSPLIT_rr
+    33560471U,	// BSPLIT_rr_v110
+    4398134U,	// CACHEA_I_bo_bso
+    4463670U,	// CACHEA_I_bo_c
+    4529206U,	// CACHEA_I_bo_pos
+    4397645U,	// CACHEA_I_bo_pre
+    400438U,	// CACHEA_I_bo_r
+    4398156U,	// CACHEA_WI_bo_bso
+    4463692U,	// CACHEA_WI_bo_c
+    4529228U,	// CACHEA_WI_bo_pos
+    4397669U,	// CACHEA_WI_bo_pre
+    400460U,	// CACHEA_WI_bo_r
+    4398195U,	// CACHEA_W_bo_bso
+    4463731U,	// CACHEA_W_bo_c
+    4529267U,	// CACHEA_W_bo_pos
+    4397712U,	// CACHEA_W_bo_pre
+    400499U,	// CACHEA_W_bo_r
+    4398145U,	// CACHEI_I_bo_bso
+    4529217U,	// CACHEI_I_bo_pos
+    4397657U,	// CACHEI_I_bo_pre
+    4398168U,	// CACHEI_WI_bo_bso
+    4529240U,	// CACHEI_WI_bo_pos
+    4397682U,	// CACHEI_WI_bo_pre
+    4398206U,	// CACHEI_W_bo_bso
+    4529278U,	// CACHEI_W_bo_pos
+    4397724U,	// CACHEI_W_bo_pre
+    2148536592U,	// CADDN_A_rcr_v110
+    103813392U,	// CADDN_A_rrr_v110
+    2148537716U,	// CADDN_rcr
+    103814516U,	// CADDN_rrr
+    35722612U,	// CADDN_src
+    33625460U,	// CADDN_srr_v110
+    2148536520U,	// CADD_A_rcr_v110
+    103813320U,	// CADD_A_rrr_v110
+    2148536954U,	// CADD_rcr
+    103813754U,	// CADD_rrr
+    35721850U,	// CADD_src
+    33624698U,	// CADD_srr_v110
+    16789U,	// CALLA_b
+    136459U,	// CALLI_rr
+    136459U,	// CALLI_rr_v110
+    17727U,	// CALL_b
+    21823U,	// CALL_sb
+    33558999U,	// CLO_B_rr_v110
+    33559475U,	// CLO_H_rr
+    33559962U,	// CLO_rr
+    33559046U,	// CLS_B_rr_v110
+    33559583U,	// CLS_H_rr
+    33560228U,	// CLS_rr
+    33559106U,	// CLZ_B_rr_v110
+    33559761U,	// CLZ_H_rr
+    33561085U,	// CLZ_rr
+    35722643U,	// CMOVN_src
+    33625491U,	// CMOVN_srr
+    35723618U,	// CMOV_src
+    33626466U,	// CMOV_srr
+    139685013U,	// CMPSWAP_W_bo_bso
+    139750549U,	// CMPSWAP_W_bo_c
+    139816085U,	// CMPSWAP_W_bo_pos
+    139684533U,	// CMPSWAP_W_bo_pre
+    6778005U,	// CMPSWAP_W_bo_r
+    4877U,	// CMP_F_rr
+    2148538728U,	// CRC32B_W_rr
+    2148538744U,	// CRC32L_W_rr
+    2148536732U,	// CRC32_B_rr
+    103814510U,	// CRCN_rrr
+    103813383U,	// CSUBN_A__rrr_v110
+    103814503U,	// CSUBN_rrr
+    103813285U,	// CSUB_A__rrr_v110
+    103813705U,	// CSUB_rrr
+    3429U,	// DEBUG_sr
+    3429U,	// DEBUG_sys
+    5748U,	// DEXTR_rrpw
+    5748U,	// DEXTR_rrrr
+    4287U,	// DIFSC_A_rr_v110
+    3421U,	// DISABLE_sys
+    135862U,	// DISABLE_sys_1
+    4884U,	// DIV_F_rr
+    6316U,	// DIV_U_rr
+    6493U,	// DIV_rr
+    3398U,	// DSYNC_sys
+    3392148760U,	// DVADJ_rrr
+    3392148760U,	// DVADJ_rrr_v110
+    33559832U,	// DVADJ_srr_v110
+    6380U,	// DVINIT_BU_rr
+    6380U,	// DVINIT_BU_rr_v110
+    4636U,	// DVINIT_B_rr
+    4636U,	// DVINIT_B_rr_v110
+    6447U,	// DVINIT_HU_rr
+    6447U,	// DVINIT_HU_rr_v110
+    5281U,	// DVINIT_H_rr
+    5281U,	// DVINIT_H_rr_v110
+    6270U,	// DVINIT_U_rr
+    6270U,	// DVINIT_U_rr_v110
+    6047U,	// DVINIT_rr
+    6047U,	// DVINIT_rr_v110
+    3392149557U,	// DVSTEP_U_rrr
+    3392149557U,	// DVSTEP_U_rrrv110
+    33560629U,	// DVSTEP_Uv110
+    3392148913U,	// DVSTEP_rrr
+    3392148913U,	// DVSTEP_rrrv110
+    33559985U,	// DVSTEPv110
+    3414U,	// ENABLE_sys
+    536875577U,	// EQANY_B_rc
+    4665U,	// EQANY_B_rr
+    536876232U,	// EQANY_H_rc
+    5320U,	// EQANY_H_rr
+    33558871U,	// EQZ_A_rr
+    4394U,	// EQ_A_rr
+    4574U,	// EQ_B_rr
+    5050U,	// EQ_H_rr
+    6538U,	// EQ_W_rr
+    536876607U,	// EQ_rc
+    5695U,	// EQ_rr
+    35655726U,	// EQ_src
+    33558574U,	// EQ_srr
+    536877119U,	// EXTR_U_rrpw
+    6207U,	// EXTR_U_rrrr
+    536877119U,	// EXTR_U_rrrw
+    536876661U,	// EXTR_rrpw
+    5749U,	// EXTR_rrrr
+    536876661U,	// EXTR_rrrw
+    16788U,	// FCALLA_b
+    136458U,	// FCALLA_i
+    17726U,	// FCALL_b
+    3457U,	// FRET_sr
+    3457U,	// FRET_sys
+    33559993U,	// FTOHP_rr
+    33561074U,	// FTOIZ_rr
+    33559826U,	// FTOI_rr
+    6621U,	// FTOQ31Z_rr
+    4253U,	// FTOQ31_rr
+    33561107U,	// FTOUZ_rr
+    33560905U,	// FTOU_rr
+    4322U,	// GE_A_rr
+    536877035U,	// GE_U_rc
+    6123U,	// GE_U_rr
+    536875670U,	// GE_rc
+    4758U,	// GE_rr
+    33559345U,	// HPTOF_rr
+    537924903U,	// IMASK_rcpw
+    170923303U,	// IMASK_rcrw
+    537924903U,	// IMASK_rrpw
+    537924903U,	// IMASK_rrrw
+    6088U,	// INSERT_rcpw
+    6088U,	// INSERT_rcrr
+    536877000U,	// INSERT_rcrw
+    6088U,	// INSERT_rrpw
+    6088U,	// INSERT_rrrr
+    6088U,	// INSERT_rrrw
+    3758102299U,	// INSN_T
+    3758102387U,	// INS_T
+    3404U,	// ISYNC_sys
+    33559339U,	// ITOF_rr
+    3392149690U,	// IXMAX_U_rrr
+    3392149926U,	// IXMAX_rrr
+    3392149548U,	// IXMIN_U_rrr
+    3392148865U,	// IXMIN_rrr
+    16779U,	// JA_b
+    1073746217U,	// JEQ_A_brr
+    1075844690U,	// JEQ_brc
+    1073747538U,	// JEQ_brr
+    28717U,	// JEQ_sbc1
+    28717U,	// JEQ_sbc2
+    28717U,	// JEQ_sbc_v110
+    7344173U,	// JEQ_sbr1
+    7344173U,	// JEQ_sbr2
+    7344173U,	// JEQ_sbr_v110
+    7346662U,	// JGEZ_sbr
+    7346662U,	// JGEZ_sbr_v110
+    1082136580U,	// JGE_U_brc
+    1073747972U,	// JGE_U_brr
+    1075843753U,	// JGE_brc
+    1073746601U,	// JGE_brr
+    7346695U,	// JGTZ_sbr
+    7346695U,	// JGTZ_sbr_v110
+    136449U,	// JI_rr
+    136449U,	// JI_rr_v110
+    136449U,	// JI_sbr_v110
+    136449U,	// JI_sr
+    16783U,	// JLA_b
+    7346668U,	// JLEZ_sbr
+    7346668U,	// JLEZ_sbr_v110
+    136453U,	// JLI_rr
+    136453U,	// JLI_rr_v110
+    7346701U,	// JLTZ_sbr
+    7346701U,	// JLTZ_sbr_v110
+    1082136741U,	// JLT_U_brc
+    1073748133U,	// JLT_U_brr
+    1082136510U,	// JLT_brc
+    1073747902U,	// JLT_brr
+    17722U,	// JL_b
+    1082135174U,	// JNED_brc
+    1073746566U,	// JNED_brr
+    1082135803U,	// JNEI_brc
+    1073747195U,	// JNEI_brr
+    1073746152U,	// JNE_A_brr
+    1075843807U,	// JNE_brc
+    1073746655U,	// JNE_brr
+    28706U,	// JNE_sbc1
+    28706U,	// JNE_sbc2
+    28706U,	// JNE_sbc_v110
+    7344162U,	// JNE_sbr1
+    7344162U,	// JNE_sbr2
+    7344162U,	// JNE_sbr_v110
+    9441616U,	// JNZ_A_brr
+    7344464U,	// JNZ_A_sbr
+    1073747846U,	// JNZ_T_brn
+    7344206U,	// JNZ_T_sbrn
+    7344206U,	// JNZ_T_sbrn_v110
+    20614U,	// JNZ_sb
+    20614U,	// JNZ_sb_v110
+    7346690U,	// JNZ_sbr
+    7346690U,	// JNZ_sbr_v110
+    9441610U,	// JZ_A_brr
+    7344458U,	// JZ_A_sbr
+    1073747840U,	// JZ_T_brn
+    7344194U,	// JZ_T_sbrn
+    7344194U,	// JZ_T_sbrn_v110
+    20604U,	// JZ_sb
+    20604U,	// JZ_sb_v110
+    7346681U,	// JZ_sbr
+    7346681U,	// JZ_sbr_v110
+    17692U,	// J_b
+    21788U,	// J_sb
+    21788U,	// J_sb_v110
+    166323U,	// LDLCX_abs
+    4398248U,	// LDLCX_bo_bso
+    38864U,	// LDMST_abs
+    139684971U,	// LDMST_bo_bso
+    139750507U,	// LDMST_bo_c
+    139816043U,	// LDMST_bo_pos
+    139684487U,	// LDMST_bo_pre
+    6777963U,	// LDMST_bo_r
+    166337U,	// LDUCX_abs
+    4398264U,	// LDUCX_bo_bso
+    10490064U,	// LD_A_abs
+    213389520U,	// LD_A_bo_bso
+    13111504U,	// LD_A_bo_c
+    215486672U,	// LD_A_bo_pos
+    594128U,	// LD_A_bo_pre
+    15208656U,	// LD_A_bo_r
+    246943952U,	// LD_A_bol
+    142584U,	// LD_A_sc
+    45617360U,	// LD_A_slr
+    47714512U,	// LD_A_slr_post
+    47714512U,	// LD_A_slr_post_v110
+    45617360U,	// LD_A_slr_v110
+    659664U,	// LD_A_slro
+    659664U,	// LD_A_slro_v110
+    42146759U,	// LD_A_sro
+    42146759U,	// LD_A_sro_v110
+    10492099U,	// LD_BU_abs
+    213391555U,	// LD_BU_bo_bso
+    13113539U,	// LD_BU_bo_c
+    215488707U,	// LD_BU_bo_pos
+    596163U,	// LD_BU_bo_pre
+    15210691U,	// LD_BU_bo_r
+    246945987U,	// LD_BU_bol
+    45619395U,	// LD_BU_slr
+    47716547U,	// LD_BU_slr_post
+    47716547U,	// LD_BU_slr_post_v110
+    45619395U,	// LD_BU_slr_v110
+    661699U,	// LD_BU_slro
+    661699U,	// LD_BU_slro_v110
+    42146798U,	// LD_BU_sro
+    42146798U,	// LD_BU_sro_v110
+    10490298U,	// LD_B_abs
+    213389754U,	// LD_B_bo_bso
+    13111738U,	// LD_B_bo_c
+    215486906U,	// LD_B_bo_pos
+    594362U,	// LD_B_bo_pre
+    15208890U,	// LD_B_bo_r
+    246944186U,	// LD_B_bol
+    47714746U,	// LD_B_slr_post_v110
+    45617594U,	// LD_B_slr_v110
+    659898U,	// LD_B_slro_v110
+    42146772U,	// LD_B_sro_v110
+    10490222U,	// LD_DA_abs
+    213389678U,	// LD_DA_bo_bso
+    13111662U,	// LD_DA_bo_c
+    215486830U,	// LD_DA_bo_pos
+    594286U,	// LD_DA_bo_pre
+    15208814U,	// LD_DA_bo_r
+    10490471U,	// LD_D_abs
+    213389927U,	// LD_D_bo_bso
+    13111911U,	// LD_D_bo_c
+    215487079U,	// LD_D_bo_pos
+    594535U,	// LD_D_bo_pre
+    15209063U,	// LD_D_bo_r
+    10492166U,	// LD_HU_abs
+    213391622U,	// LD_HU_bo_bso
+    13113606U,	// LD_HU_bo_c
+    215488774U,	// LD_HU_bo_pos
+    596230U,	// LD_HU_bo_pre
+    15210758U,	// LD_HU_bo_r
+    246946054U,	// LD_HU_bol
+    10490719U,	// LD_H_abs
+    213390175U,	// LD_H_bo_bso
+    13112159U,	// LD_H_bo_c
+    215487327U,	// LD_H_bo_pos
+    594783U,	// LD_H_bo_pre
+    15209311U,	// LD_H_bo_r
+    246944607U,	// LD_H_bol
+    45618015U,	// LD_H_slr
+    47715167U,	// LD_H_slr_post
+    47715167U,	// LD_H_slr_post_v110
+    45618015U,	// LD_H_slr_v110
+    660319U,	// LD_H_slro
+    660319U,	// LD_H_slro_v110
+    42146785U,	// LD_H_sro
+    42146785U,	// LD_H_sro_v110
+    10491350U,	// LD_Q_abs
+    213390806U,	// LD_Q_bo_bso
+    13112790U,	// LD_Q_bo_c
+    215487958U,	// LD_Q_bo_pos
+    595414U,	// LD_Q_bo_pre
+    15209942U,	// LD_Q_bo_r
+    10492274U,	// LD_W_abs
+    213391730U,	// LD_W_bo_bso
+    13113714U,	// LD_W_bo_c
+    215488882U,	// LD_W_bo_pos
+    596338U,	// LD_W_bo_pre
+    15210866U,	// LD_W_bo_r
+    246946162U,	// LD_W_bol
+    142601U,	// LD_W_sc
+    45619570U,	// LD_W_slr
+    47716722U,	// LD_W_slr_post
+    47716722U,	// LD_W_slr_post_v110
+    45619570U,	// LD_W_slr_v110
+    661874U,	// LD_W_slro
+    661874U,	// LD_W_slro_v110
+    42146812U,	// LD_W_sro
+    42146812U,	// LD_W_sro_v110
+    10490236U,	// LEA_abs
+    213389692U,	// LEA_bo_bso
+    246944124U,	// LEA_bol
+    10490241U,	// LHA_abs
+    43343U,	// LOOPU_brr
+    9442752U,	// LOOP_brr
+    15734208U,	// LOOP_sbr
+    4400U,	// LT_A_rr
+    4646U,	// LT_B
+    6391U,	// LT_BU
+    5291U,	// LT_H
+    6458U,	// LT_HU
+    536877196U,	// LT_U_rc
+    6284U,	// LT_U_rr
+    41947237U,	// LT_U_srcv110
+    33558629U,	// LT_U_srrv110
+    6544U,	// LT_W
+    6486U,	// LT_WU
+    536876971U,	// LT_rc
+    6059U,	// LT_rr
+    35655771U,	// LT_src
+    33558619U,	// LT_srr
+    103814204U,	// MADDMS_H_rrr1_LL
+    103814204U,	// MADDMS_H_rrr1_LU
+    103814204U,	// MADDMS_H_rrr1_UL
+    103814204U,	// MADDMS_H_rrr1_UU
+    2148538484U,	// MADDMS_U_rcr_v110
+    103815284U,	// MADDMS_U_rrr2_v110
+    2148538039U,	// MADDMS_rcr_v110
+    103814839U,	// MADDMS_rrr2_v110
+    103814032U,	// MADDM_H_rrr1_LL
+    103814032U,	// MADDM_H_rrr1_LU
+    103814032U,	// MADDM_H_rrr1_UL
+    103814032U,	// MADDM_H_rrr1_UU
+    103814032U,	// MADDM_H_rrr1_v110
+    103814636U,	// MADDM_Q_rrr1_v110
+    2148538395U,	// MADDM_U_rcr_v110
+    103815195U,	// MADDM_U_rrr2_v110
+    2148537690U,	// MADDM_rcr_v110
+    103814490U,	// MADDM_rrr2_v110
+    103814257U,	// MADDRS_H_rrr1_LL
+    103814257U,	// MADDRS_H_rrr1_LU
+    103814257U,	// MADDRS_H_rrr1_UL
+    103814257U,	// MADDRS_H_rrr1_UL_2
+    103814257U,	// MADDRS_H_rrr1_UU
+    103814257U,	// MADDRS_H_rrr1_v110
+    1714427435U,	// MADDRS_Q_rrr1_L_L
+    2251298347U,	// MADDRS_Q_rrr1_U_U
+    103814699U,	// MADDRS_Q_rrr1_v110
+    103814100U,	// MADDR_H_rrr1_LL
+    103814100U,	// MADDR_H_rrr1_LU
+    103814100U,	// MADDR_H_rrr1_UL
+    103814100U,	// MADDR_H_rrr1_UL_2
+    103814100U,	// MADDR_H_rrr1_UU
+    103814100U,	// MADDR_H_rrr1_v110
+    1714427390U,	// MADDR_Q_rrr1_L_L
+    2251298302U,	// MADDR_Q_rrr1_U_U
+    103814654U,	// MADDR_Q_rrr1_v110
+    103814223U,	// MADDSUMS_H_rrr1_LL
+    103814223U,	// MADDSUMS_H_rrr1_LU
+    103814223U,	// MADDSUMS_H_rrr1_UL
+    103814223U,	// MADDSUMS_H_rrr1_UU
+    103814049U,	// MADDSUM_H_rrr1_LL
+    103814049U,	// MADDSUM_H_rrr1_LU
+    103814049U,	// MADDSUM_H_rrr1_UL
+    103814049U,	// MADDSUM_H_rrr1_UU
+    103814267U,	// MADDSURS_H_rrr1_LL
+    103814267U,	// MADDSURS_H_rrr1_LU
+    103814267U,	// MADDSURS_H_rrr1_UL
+    103814267U,	// MADDSURS_H_rrr1_UU
+    103814117U,	// MADDSUR_H_rrr1_LL
+    103814117U,	// MADDSUR_H_rrr1_LU
+    103814117U,	// MADDSUR_H_rrr1_UL
+    103814117U,	// MADDSUR_H_rrr1_UU
+    103814287U,	// MADDSUS_H_rrr1_LL
+    103814287U,	// MADDSUS_H_rrr1_LU
+    103814287U,	// MADDSUS_H_rrr1_UL
+    103814287U,	// MADDSUS_H_rrr1_UU
+    103814327U,	// MADDSU_H_rrr1_LL
+    103814327U,	// MADDSU_H_rrr1_LU
+    103814327U,	// MADDSU_H_rrr1_UL
+    103814327U,	// MADDSU_H_rrr1_UU
+    103814155U,	// MADDS_H_rrr1_LL
+    103814155U,	// MADDS_H_rrr1_LU
+    103814155U,	// MADDS_H_rrr1_UL
+    103814155U,	// MADDS_H_rrr1_UU
+    103814155U,	// MADDS_H_rrr1_v110
+    103814680U,	// MADDS_Q_rrr1
+    103814680U,	// MADDS_Q_rrr1_L
+    1714427416U,	// MADDS_Q_rrr1_L_L
+    103814680U,	// MADDS_Q_rrr1_U
+    103814680U,	// MADDS_Q_rrr1_UU2_v110
+    2251298328U,	// MADDS_Q_rrr1_U_U
+    103814680U,	// MADDS_Q_rrr1_e
+    103814680U,	// MADDS_Q_rrr1_e_L
+    1714427416U,	// MADDS_Q_rrr1_e_L_L
+    103814680U,	// MADDS_Q_rrr1_e_U
+    2251298328U,	// MADDS_Q_rrr1_e_U_U
+    2148538457U,	// MADDS_U_rcr
+    2148538457U,	// MADDS_U_rcr_e
+    103815257U,	// MADDS_U_rrr2
+    103815257U,	// MADDS_U_rrr2_e
+    2148538004U,	// MADDS_rcr
+    2148538004U,	// MADDS_rcr_e
+    103814804U,	// MADDS_rrr2
+    103814804U,	// MADDS_rrr2_e
+    103813877U,	// MADD_F_rrr
+    103813975U,	// MADD_H_rrr1_LL
+    103813975U,	// MADD_H_rrr1_LU
+    103813975U,	// MADD_H_rrr1_UL
+    103813975U,	// MADD_H_rrr1_UU
+    103813975U,	// MADD_H_rrr1_v110
+    103814606U,	// MADD_Q_rrr1
+    103814606U,	// MADD_Q_rrr1_L
+    1714427342U,	// MADD_Q_rrr1_L_L
+    103814606U,	// MADD_Q_rrr1_U
+    103814606U,	// MADD_Q_rrr1_UU2_v110
+    2251298254U,	// MADD_Q_rrr1_U_U
+    103814606U,	// MADD_Q_rrr1_e
+    103814606U,	// MADD_Q_rrr1_e_L
+    1714427342U,	// MADD_Q_rrr1_e_L_L
+    103814606U,	// MADD_Q_rrr1_e_U
+    2251298254U,	// MADD_Q_rrr1_e_U_U
+    2148538335U,	// MADD_U_rcr
+    103815135U,	// MADD_U_rrr2
+    2148536960U,	// MADD_rcr
+    2148536960U,	// MADD_rcr_e
+    103813760U,	// MADD_rrr2
+    103813760U,	// MADD_rrr2_e
+    4658U,	// MAX_B
+    6398U,	// MAX_BU
+    5313U,	// MAX_H
+    6465U,	// MAX_HU
+    536877244U,	// MAX_U_rc
+    6332U,	// MAX_U_rr
+    536877480U,	// MAX_rc
+    6568U,	// MAX_rr
+    16782935U,	// MFCR_rlc
+    4560U,	// MIN_B
+    6346U,	// MIN_BU
+    5036U,	// MIN_H
+    6413U,	// MIN_HU
+    536877102U,	// MIN_U_rc
+    6190U,	// MIN_U_rr
+    536876419U,	// MIN_rc
+    5507U,	// MIN_rr
+    16781560U,	// MOVH_A_rlc
+    16782563U,	// MOVH_rlc
+    135518U,	// MOVZ_A_sr
+    34607462U,	// MOV_AA_rr
+    33558886U,	// MOV_AA_srr_srr
+    33558886U,	// MOV_AA_srr_srr_v110
+    34607420U,	// MOV_A_rr
+    41947452U,	// MOV_A_src
+    33558844U,	// MOV_A_srr
+    33558844U,	// MOV_A_srr_v110
+    34607731U,	// MOV_D_rr
+    33559155U,	// MOV_D_srr_srr
+    33559155U,	// MOV_D_srr_srr_v110
+    16783539U,	// MOV_U_rlc
+    17832291U,	// MOV_rlc
+    16783715U,	// MOV_rlc_e
+    34609507U,	// MOV_rr
+    34609507U,	// MOV_rr_e
+    6499U,	// MOV_rr_eab
+    139377U,	// MOV_sc
+    139377U,	// MOV_sc_v110
+    35658083U,	// MOV_src
+    35658083U,	// MOV_src_e
+    33560931U,	// MOV_srr
+    103814192U,	// MSUBADMS_H_rrr1_LL
+    103814192U,	// MSUBADMS_H_rrr1_LU
+    103814192U,	// MSUBADMS_H_rrr1_UL
+    103814192U,	// MSUBADMS_H_rrr1_UU
+    103814021U,	// MSUBADM_H_rrr1_LL
+    103814021U,	// MSUBADM_H_rrr1_LU
+    103814021U,	// MSUBADM_H_rrr1_UL
+    103814021U,	// MSUBADM_H_rrr1_UU
+    103814245U,	// MSUBADRS_H_rrr1_LL
+    103814245U,	// MSUBADRS_H_rrr1_LU
+    103814245U,	// MSUBADRS_H_rrr1_UL
+    103814245U,	// MSUBADRS_H_rrr1_UU
+    103814245U,	// MSUBADRS_H_rrr1_v110
+    103814089U,	// MSUBADR_H_rrr1_LL
+    103814089U,	// MSUBADR_H_rrr1_LU
+    103814089U,	// MSUBADR_H_rrr1_UL
+    103814089U,	// MSUBADR_H_rrr1_UU
+    103814089U,	// MSUBADR_H_rrr1_v110
+    103814144U,	// MSUBADS_H_rrr1_LL
+    103814144U,	// MSUBADS_H_rrr1_LU
+    103814144U,	// MSUBADS_H_rrr1_UL
+    103814144U,	// MSUBADS_H_rrr1_UU
+    103813965U,	// MSUBAD_H_rrr1_LL
+    103813965U,	// MSUBAD_H_rrr1_LU
+    103813965U,	// MSUBAD_H_rrr1_UL
+    103813965U,	// MSUBAD_H_rrr1_UU
+    103814182U,	// MSUBMS_H_rrr1_LL
+    103814182U,	// MSUBMS_H_rrr1_LU
+    103814182U,	// MSUBMS_H_rrr1_UL
+    103814182U,	// MSUBMS_H_rrr1_UU
+    2148538474U,	// MSUBMS_U_rcrv110
+    103815274U,	// MSUBMS_U_rrr2v110
+    2148538031U,	// MSUBMS_rcrv110
+    103814831U,	// MSUBMS_rrr2v110
+    103814012U,	// MSUBM_H_rrr1_LL
+    103814012U,	// MSUBM_H_rrr1_LU
+    103814012U,	// MSUBM_H_rrr1_UL
+    103814012U,	// MSUBM_H_rrr1_UU
+    103814012U,	// MSUBM_H_rrr1_v110
+    103814627U,	// MSUBM_Q_rrr1_v110
+    2148538386U,	// MSUBM_U_rcrv110
+    103815186U,	// MSUBM_U_rrr2v110
+    2148537683U,	// MSUBM_rcrv110
+    103814483U,	// MSUBM_rrr2v110
+    103814235U,	// MSUBRS_H_rrr1_LL
+    103814235U,	// MSUBRS_H_rrr1_LU
+    103814235U,	// MSUBRS_H_rrr1_UL
+    103814235U,	// MSUBRS_H_rrr1_UL_2
+    103814235U,	// MSUBRS_H_rrr1_UU
+    103814235U,	// MSUBRS_H_rrr1_v110
+    1714427425U,	// MSUBRS_Q_rrr1_L_L
+    2251298337U,	// MSUBRS_Q_rrr1_U_U
+    103814689U,	// MSUBRS_Q_rrr1_v110
+    103814080U,	// MSUBR_H_rrr1_LL
+    103814080U,	// MSUBR_H_rrr1_LU
+    103814080U,	// MSUBR_H_rrr1_UL
+    103814080U,	// MSUBR_H_rrr1_UL_2
+    103814080U,	// MSUBR_H_rrr1_UU
+    103814080U,	// MSUBR_H_rrr1_v110
+    1714427381U,	// MSUBR_Q_rrr1_L_L
+    2251298293U,	// MSUBR_Q_rrr1_U_U
+    103814645U,	// MSUBR_Q_rrr1_v110
+    103814135U,	// MSUBS_H_rrr1_LL
+    103814135U,	// MSUBS_H_rrr1_LU
+    103814135U,	// MSUBS_H_rrr1_UL
+    103814135U,	// MSUBS_H_rrr1_UU
+    103814135U,	// MSUBS_H_rrr1_v110
+    103814671U,	// MSUBS_Q_rrr1
+    103814671U,	// MSUBS_Q_rrr1_L
+    1714427407U,	// MSUBS_Q_rrr1_L_L
+    103814671U,	// MSUBS_Q_rrr1_U
+    103814671U,	// MSUBS_Q_rrr1_UU2_v110
+    2251298319U,	// MSUBS_Q_rrr1_U_U
+    103814671U,	// MSUBS_Q_rrr1_e
+    103814671U,	// MSUBS_Q_rrr1_e_L
+    1714427407U,	// MSUBS_Q_rrr1_e_L_L
+    103814671U,	// MSUBS_Q_rrr1_e_U
+    2251298319U,	// MSUBS_Q_rrr1_e_U_U
+    2148538439U,	// MSUBS_U_rcr
+    2148538439U,	// MSUBS_U_rcr_e
+    103815239U,	// MSUBS_U_rrr2
+    103815239U,	// MSUBS_U_rrr2_e
+    2148537990U,	// MSUBS_rcr
+    2148537990U,	// MSUBS_rcr_e
+    103814790U,	// MSUBS_rrr2
+    103814790U,	// MSUBS_rrr2_e
+    103813869U,	// MSUB_F_rrr
+    103813957U,	// MSUB_H_rrr1_LL
+    103813957U,	// MSUB_H_rrr1_LU
+    103813957U,	// MSUB_H_rrr1_UL
+    103813957U,	// MSUB_H_rrr1_UU
+    103813957U,	// MSUB_H_rrr1_v110
+    103814598U,	// MSUB_Q_rrr1
+    103814598U,	// MSUB_Q_rrr1_L
+    1714427334U,	// MSUB_Q_rrr1_L_L
+    103814598U,	// MSUB_Q_rrr1_U
+    103814598U,	// MSUB_Q_rrr1_UU2_v110
+    2251298246U,	// MSUB_Q_rrr1_U_U
+    103814598U,	// MSUB_Q_rrr1_e
+    103814598U,	// MSUB_Q_rrr1_e_L
+    1714427334U,	// MSUB_Q_rrr1_e_L_L
+    103814598U,	// MSUB_Q_rrr1_e_U
+    2251298246U,	// MSUB_Q_rrr1_e_U_U
+    2148538327U,	// MSUB_U_rcr
+    103815127U,	// MSUB_U_rrr2
+    2148536911U,	// MSUB_rcr
+    2148536911U,	// MSUB_rcr_e
+    103813711U,	// MSUB_rrr2
+    103813711U,	// MSUB_rrr2_e
+    46685U,	// MTCR_rlc
+    5190U,	// MULMS_H_rr1_LL2e
+    5190U,	// MULMS_H_rr1_LU2e
+    5190U,	// MULMS_H_rr1_UL2e
+    5190U,	// MULMS_H_rr1_UU2e
+    5017U,	// MULM_H_rr1_LL2e
+    5017U,	// MULM_H_rr1_LU2e
+    5017U,	// MULM_H_rr1_UL2e
+    5017U,	// MULM_H_rr1_UU2e
+    536877092U,	// MULM_U_rc
+    6180U,	// MULM_U_rr
+    536876385U,	// MULM_rc
+    5473U,	// MULM_rr
+    5085U,	// MULR_H_rr1_LL2e
+    5085U,	// MULR_H_rr1_LU2e
+    5085U,	// MULR_H_rr1_UL2e
+    5085U,	// MULR_H_rr1_UU2e
+    5085U,	// MULR_H_rr_v110
+    268441095U,	// MULR_Q_rr1_2LL
+    301995527U,	// MULR_Q_rr1_2UU
+    5639U,	// MULR_Q_rr_v110
+    536877154U,	// MULS_U_rc
+    6242U,	// MULS_U_rr2
+    6242U,	// MULS_U_rr_v110
+    536876713U,	// MULS_rc
+    5801U,	// MULS_rr2
+    5801U,	// MULS_rr_v110
+    4870U,	// MUL_F_rrr
+    4981U,	// MUL_H_rr1_LL2e
+    4981U,	// MUL_H_rr1_LU2e
+    4981U,	// MUL_H_rr1_UL2e
+    4981U,	// MUL_H_rr1_UU2e
+    4981U,	// MUL_H_rr_v110
+    5596U,	// MUL_Q_rr1_2
+    268441052U,	// MUL_Q_rr1_2LL
+    301995484U,	// MUL_Q_rr1_2UU
+    5596U,	// MUL_Q_rr1_2_L
+    5596U,	// MUL_Q_rr1_2_Le
+    5596U,	// MUL_Q_rr1_2_U
+    5596U,	// MUL_Q_rr1_2_Ue
+    5596U,	// MUL_Q_rr1_2__e
+    5596U,	// MUL_Q_rr_v110
+    536877067U,	// MUL_U_rc
+    6155U,	// MUL_U_rr2
+    536876366U,	// MUL_rc
+    536876366U,	// MUL_rc_e
+    5454U,	// MUL_rr2
+    5454U,	// MUL_rr2_e
+    5454U,	// MUL_rr_v110
+    33559886U,	// MUL_srr
+    3758102247U,	// NAND_T
+    536875660U,	// NAND_rc
+    4748U,	// NAND_rr
+    33558851U,	// NEZ_A
+    4329U,	// NE_A
+    536875724U,	// NE_rc
+    4812U,	// NE_rr
+    3453U,	// NOP_sr
+    3453U,	// NOP_sys
+    3758102339U,	// NOR_T
+    536876644U,	// NOR_rc
+    5732U,	// NOR_rr
+    136804U,	// NOR_sr
+    136804U,	// NOR_sr_v110
+    137155U,	// NOT_sr_v162
+    3758102292U,	// ORN_T
+    536876430U,	// ORN_rc
+    5518U,	// ORN_rr
+    3758102278U,	// OR_ANDN_T
+    3758102234U,	// OR_AND_T
+    536876619U,	// OR_EQ_rc
+    5707U,	// OR_EQ_rr
+    536877051U,	// OR_GE_U_rc
+    6139U,	// OR_GE_U_rr
+    536875682U,	// OR_GE_rc
+    4770U,	// OR_GE_rr
+    536877212U,	// OR_LT_U_rc
+    6300U,	// OR_LT_U_rr
+    536876983U,	// OR_LT_rc
+    6071U,	// OR_LT_rr
+    536875736U,	// OR_NE_rc
+    4824U,	// OR_NE_rr
+    3758102356U,	// OR_NOR_T
+    3758102326U,	// OR_OR_T
+    3758102311U,	// OR_T
+    2684360293U,	// OR_rc
+    5733U,	// OR_rr
+    139320U,	// OR_sc
+    139320U,	// OR_sc_v110
+    33560165U,	// OR_srr
+    33560165U,	// OR_srr_v110
+    3325039905U,	// PACK_rrr
+    33561045U,	// PARITY_rr
+    33561045U,	// PARITY_rr_v110
+    33560982U,	// POPCNT_W_rr
+    4899U,	// Q31TOF_rr
+    33559293U,	// QSEED_F_rr
+    135908U,	// RESTORE_sys
+    3458U,	// RET_sr
+    3458U,	// RET_sys
+    3458U,	// RET_sys_v110
+    3410U,	// RFE_sr
+    3410U,	// RFE_sys_sys
+    3410U,	// RFE_sys_sys_v110
+    3449U,	// RFM_sys
+    3485U,	// RSLCX_sys
+    3480U,	// RSTV_sys
+    536877136U,	// RSUBS_U_rc
+    536876685U,	// RSUBS_rc
+    536875605U,	// RSUB_rc
+    135765U,	// RSUB_sr_sr
+    135765U,	// RSUB_sr_sr_v110
+    33560804U,	// SAT_BU_rr
+    137444U,	// SAT_BU_sr
+    137444U,	// SAT_BU_sr_v110
+    33559061U,	// SAT_B_rr
+    135701U,	// SAT_B_sr
+    135701U,	// SAT_B_sr_v110
+    33560871U,	// SAT_HU_rr
+    137511U,	// SAT_HU_sr
+    137511U,	// SAT_HU_sr_v110
+    33559706U,	// SAT_H_rr
+    136346U,	// SAT_H_sr
+    136346U,	// SAT_H_sr_v110
+    2148536601U,	// SELN_A_rcr_v110
+    103813401U,	// SELN_A_rrr_v110
+    2148537736U,	// SELN_rcr
+    103814536U,	// SELN_rrr
+    2148536576U,	// SEL_A_rcr_v110
+    103813376U,	// SEL_A_rrr_v110
+    2148537646U,	// SEL_rcr
+    103814446U,	// SEL_rrr
+    536876667U,	// SHAS_rc
+    5755U,	// SHAS_rr
+    536875429U,	// SHA_B_rc
+    4517U,	// SHA_B_rr
+    536875838U,	// SHA_H_rc
+    4926U,	// SHA_H_rr
+    536875398U,	// SHA_rc
+    4486U,	// SHA_rr
+    35656070U,	// SHA_src
+    35656070U,	// SHA_src_v110
+    536875711U,	// SHUFFLE_rc
+    3758102267U,	// SH_ANDN_T
+    3758102224U,	// SH_AND_T
+    536875466U,	// SH_B_rc
+    4554U,	// SH_B_rr
+    536876611U,	// SH_EQ_rc
+    5699U,	// SH_EQ_rr
+    536877041U,	// SH_GE_U_rc
+    6129U,	// SH_GE_U_rr
+    536875674U,	// SH_GE_rc
+    4762U,	// SH_GE_rr
+    536875887U,	// SH_H_rc
+    4975U,	// SH_H_rr
+    536877202U,	// SH_LT_U_rc
+    6290U,	// SH_LT_U_rr
+    536876975U,	// SH_LT_rc
+    6063U,	// SH_LT_rr
+    3758102244U,	// SH_NAND_T
+    536875728U,	// SH_NE_rc
+    4816U,	// SH_NE_rr
+    3758102346U,	// SH_NOR_T
+    3758102289U,	// SH_ORN_T
+    3758102317U,	// SH_OR_T
+    3758102366U,	// SH_XNOR_T
+    3758102377U,	// SH_XOR_T
+    536876255U,	// SH_rc
+    5343U,	// SH_rr
+    35656927U,	// SH_src
+    35656927U,	// SH_src_v110
+    166330U,	// STLCX_abs
+    4398256U,	// STLCX_bo_bso
+    166344U,	// STUCX_abs
+    4398272U,	// STUCX_bo_bso
+    37174U,	// ST_A_abs
+    139684882U,	// ST_A_bo_bso
+    3327400978U,	// ST_A_bo_c
+    139815954U,	// ST_A_bo_pos
+    139684388U,	// ST_A_bo_pre
+    34020370U,	// ST_A_bo_r
+    19078162U,	// ST_A_bol
+    732442U,	// ST_A_sc
+    344136722U,	// ST_A_sro
+    344136722U,	// ST_A_sro_v110
+    793618U,	// ST_A_ssr
+    859154U,	// ST_A_ssr_pos
+    859154U,	// ST_A_ssr_pos_v110
+    793618U,	// ST_A_ssr_v110
+    52424U,	// ST_A_ssro
+    52424U,	// ST_A_ssro_v110
+    37420U,	// ST_B_abs
+    139684897U,	// ST_B_bo_bso
+    3327400993U,	// ST_B_bo_c
+    139815969U,	// ST_B_bo_pos
+    139684405U,	// ST_B_bo_pre
+    34020385U,	// ST_B_bo_r
+    19078177U,	// ST_B_bol
+    377691169U,	// ST_B_sro
+    377691169U,	// ST_B_sro_v110
+    793633U,	// ST_B_ssr
+    859169U,	// ST_B_ssr_pos
+    859169U,	// ST_B_ssr_pos_v110
+    793633U,	// ST_B_ssr_v110
+    52436U,	// ST_B_ssro
+    52436U,	// ST_B_ssro_v110
+    37237U,	// ST_DA_abs
+    139684889U,	// ST_DA_bo_bso
+    3327400985U,	// ST_DA_bo_c
+    139815961U,	// ST_DA_bo_pos
+    139684396U,	// ST_DA_bo_pre
+    34020377U,	// ST_DA_bo_r
+    37485U,	// ST_D_abs
+    139684904U,	// ST_D_bo_bso
+    3327401000U,	// ST_D_bo_c
+    139815976U,	// ST_D_bo_pos
+    139684413U,	// ST_D_bo_pre
+    34020392U,	// ST_D_bo_r
+    38065U,	// ST_H_abs
+    139684911U,	// ST_H_bo_bso
+    3327401007U,	// ST_H_bo_c
+    139815983U,	// ST_H_bo_pos
+    139684421U,	// ST_H_bo_pre
+    34020399U,	// ST_H_bo_r
+    19078191U,	// ST_H_bol
+    377691183U,	// ST_H_sro
+    377691183U,	// ST_H_sro_v110
+    793647U,	// ST_H_ssr
+    859183U,	// ST_H_ssr_pos
+    859183U,	// ST_H_ssr_pos_v110
+    793647U,	// ST_H_ssr_v110
+    52448U,	// ST_H_ssro
+    52448U,	// ST_H_ssro_v110
+    38453U,	// ST_Q_abs
+    139684964U,	// ST_Q_bo_bso
+    3327401060U,	// ST_Q_bo_c
+    139816036U,	// ST_Q_bo_pos
+    139684479U,	// ST_Q_bo_pre
+    34020452U,	// ST_Q_bo_r
+    34682U,	// ST_T
+    39328U,	// ST_W_abs
+    139685025U,	// ST_W_bo_bso
+    3327401121U,	// ST_W_bo_c
+    139816097U,	// ST_W_bo_pos
+    139684546U,	// ST_W_bo_pre
+    34020513U,	// ST_W_bo_r
+    19078305U,	// ST_W_bol
+    929061U,	// ST_W_sc
+    377691297U,	// ST_W_sro
+    377691297U,	// ST_W_sro_v110
+    793761U,	// ST_W_ssr
+    859297U,	// ST_W_ssr_pos
+    859297U,	// ST_W_ssr_pos_v110
+    793761U,	// ST_W_ssr_v110
+    52460U,	// ST_W_ssro
+    52460U,	// ST_W_ssro_v110
+    4699U,	// SUBC_rr
+    4269U,	// SUBSC_A_rr
+    6354U,	// SUBS_BU_rr
+    4587U,	// SUBS_B_rr
+    6421U,	// SUBS_HU_rr
+    5112U,	// SUBS_H_rr
+    6216U,	// SUBS_U_rr
+    5767U,	// SUBS_rr
+    33560199U,	// SUBS_srr
+    6573U,	// SUBX_rr
+    4262U,	// SUB_A_rr
+    139409U,	// SUB_A_sc
+    139409U,	// SUB_A_sc_v110
+    4524U,	// SUB_B_rr
+    3325039342U,	// SUB_F_rrr
+    4934U,	// SUB_H_rr
+    4682U,	// SUB_rr
+    33559114U,	// SUB_srr
+    33558529U,	// SUB_srr_15a
+    33624650U,	// SUB_srr_a15
+    3491U,	// SVLCX_sys
+    139685001U,	// SWAPMSK_W_bo_bso
+    3327401097U,	// SWAPMSK_W_bo_c
+    1010825U,	// SWAPMSK_W_bo_i
+    139816073U,	// SWAPMSK_W_bo_pos
+    139684520U,	// SWAPMSK_W_bo_pre
+    34020489U,	// SWAPMSK_W_bo_r
+    37153U,	// SWAP_A_abs
+    139684873U,	// SWAP_A_bo_bso
+    3327400969U,	// SWAP_A_bo_c
+    139815945U,	// SWAP_A_bo_pos
+    139684378U,	// SWAP_A_bo_pre
+    34020361U,	// SWAP_A_bo_r
+    39298U,	// SWAP_W_abs
+    139685016U,	// SWAP_W_bo_bso
+    3327401112U,	// SWAP_W_bo_c
+    1010840U,	// SWAP_W_bo_i
+    139816088U,	// SWAP_W_bo_pos
+    139684536U,	// SWAP_W_bo_pre
+    34020504U,	// SWAP_W_bo_r
+    13637U,	// SYSCALL_rc
+    136615U,	// TLBDEMAP_rr
+    3376U,	// TLBFLUSH_A_rr
+    3387U,	// TLBFLUSH_B_rr
+    136607U,	// TLBMAP_rr
+    135382U,	// TLBPROBE_A_rr
+    136425U,	// TLBPROBE_I_rr
+    3473U,	// TRAPSV_sys
+    3467U,	// TRAPV_sys
+    33559839U,	// UNPACK_rr_rr
+    33559839U,	// UNPACK_rr_rr_v110
+    136499U,	// UPDFL_rr
+    33559352U,	// UTOF_rr
+    3462U,	// WAIT_sys
+    3758102369U,	// XNOR_T
+    536876643U,	// XNOR_rc
+    5731U,	// XNOR_rr
+    536876618U,	// XOR_EQ_rc
+    5706U,	// XOR_EQ_rr
+    536877050U,	// XOR_GE_U_rc
+    6138U,	// XOR_GE_U_rr
+    536875681U,	// XOR_GE_rc
+    4769U,	// XOR_GE_rr
+    536877211U,	// XOR_LT_U_rc
+    6299U,	// XOR_LT_U_rr
+    536876982U,	// XOR_LT_rc
+    6070U,	// XOR_LT_rr
+    536875735U,	// XOR_NE_rc
+    4823U,	// XOR_NE_rr
+    3758102380U,	// XOR_T
+    536876649U,	// XOR_rc
+    5737U,	// XOR_rr
+    33560169U,	// XOR_srr
+  };
+
+  static const uint16_t OpInfo1[] = {
+    0U,	// PHI
+    0U,	// INLINEASM
+    0U,	// INLINEASM_BR
+    0U,	// CFI_INSTRUCTION
+    0U,	// EH_LABEL
+    0U,	// GC_LABEL
+    0U,	// ANNOTATION_LABEL
+    0U,	// KILL
+    0U,	// EXTRACT_SUBREG
+    0U,	// INSERT_SUBREG
+    0U,	// IMPLICIT_DEF
+    0U,	// SUBREG_TO_REG
+    0U,	// COPY_TO_REGCLASS
+    0U,	// DBG_VALUE
+    0U,	// DBG_VALUE_LIST
+    0U,	// DBG_INSTR_REF
+    0U,	// DBG_PHI
+    0U,	// DBG_LABEL
+    0U,	// REG_SEQUENCE
+    0U,	// COPY
+    0U,	// BUNDLE
+    0U,	// LIFETIME_START
+    0U,	// LIFETIME_END
+    0U,	// PSEUDO_PROBE
+    0U,	// ARITH_FENCE
+    0U,	// STACKMAP
+    0U,	// FENTRY_CALL
+    0U,	// PATCHPOINT
+    0U,	// LOAD_STACK_GUARD
+    0U,	// PREALLOCATED_SETUP
+    0U,	// PREALLOCATED_ARG
+    0U,	// STATEPOINT
+    0U,	// LOCAL_ESCAPE
+    0U,	// FAULTING_OP
+    0U,	// PATCHABLE_OP
+    0U,	// PATCHABLE_FUNCTION_ENTER
+    0U,	// PATCHABLE_RET
+    0U,	// PATCHABLE_FUNCTION_EXIT
+    0U,	// PATCHABLE_TAIL_CALL
+    0U,	// PATCHABLE_EVENT_CALL
+    0U,	// PATCHABLE_TYPED_EVENT_CALL
+    0U,	// ICALL_BRANCH_FUNNEL
+    0U,	// MEMBARRIER
+    0U,	// G_ASSERT_SEXT
+    0U,	// G_ASSERT_ZEXT
+    0U,	// G_ASSERT_ALIGN
+    0U,	// G_ADD
+    0U,	// G_SUB
+    0U,	// G_MUL
+    0U,	// G_SDIV
+    0U,	// G_UDIV
+    0U,	// G_SREM
+    0U,	// G_UREM
+    0U,	// G_SDIVREM
+    0U,	// G_UDIVREM
+    0U,	// G_AND
+    0U,	// G_OR
+    0U,	// G_XOR
+    0U,	// G_IMPLICIT_DEF
+    0U,	// G_PHI
+    0U,	// G_FRAME_INDEX
+    0U,	// G_GLOBAL_VALUE
+    0U,	// G_EXTRACT
+    0U,	// G_UNMERGE_VALUES
+    0U,	// G_INSERT
+    0U,	// G_MERGE_VALUES
+    0U,	// G_BUILD_VECTOR
+    0U,	// G_BUILD_VECTOR_TRUNC
+    0U,	// G_CONCAT_VECTORS
+    0U,	// G_PTRTOINT
+    0U,	// G_INTTOPTR
+    0U,	// G_BITCAST
+    0U,	// G_FREEZE
+    0U,	// G_INTRINSIC_FPTRUNC_ROUND
+    0U,	// G_INTRINSIC_TRUNC
+    0U,	// G_INTRINSIC_ROUND
+    0U,	// G_INTRINSIC_LRINT
+    0U,	// G_INTRINSIC_ROUNDEVEN
+    0U,	// G_READCYCLECOUNTER
+    0U,	// G_LOAD
+    0U,	// G_SEXTLOAD
+    0U,	// G_ZEXTLOAD
+    0U,	// G_INDEXED_LOAD
+    0U,	// G_INDEXED_SEXTLOAD
+    0U,	// G_INDEXED_ZEXTLOAD
+    0U,	// G_STORE
+    0U,	// G_INDEXED_STORE
+    0U,	// G_ATOMIC_CMPXCHG_WITH_SUCCESS
+    0U,	// G_ATOMIC_CMPXCHG
+    0U,	// G_ATOMICRMW_XCHG
+    0U,	// G_ATOMICRMW_ADD
+    0U,	// G_ATOMICRMW_SUB
+    0U,	// G_ATOMICRMW_AND
+    0U,	// G_ATOMICRMW_NAND
+    0U,	// G_ATOMICRMW_OR
+    0U,	// G_ATOMICRMW_XOR
+    0U,	// G_ATOMICRMW_MAX
+    0U,	// G_ATOMICRMW_MIN
+    0U,	// G_ATOMICRMW_UMAX
+    0U,	// G_ATOMICRMW_UMIN
+    0U,	// G_ATOMICRMW_FADD
+    0U,	// G_ATOMICRMW_FSUB
+    0U,	// G_ATOMICRMW_FMAX
+    0U,	// G_ATOMICRMW_FMIN
+    0U,	// G_ATOMICRMW_UINC_WRAP
+    0U,	// G_ATOMICRMW_UDEC_WRAP
+    0U,	// G_FENCE
+    0U,	// G_BRCOND
+    0U,	// G_BRINDIRECT
+    0U,	// G_INVOKE_REGION_START
+    0U,	// G_INTRINSIC
+    0U,	// G_INTRINSIC_W_SIDE_EFFECTS
+    0U,	// G_ANYEXT
+    0U,	// G_TRUNC
+    0U,	// G_CONSTANT
+    0U,	// G_FCONSTANT
+    0U,	// G_VASTART
+    0U,	// G_VAARG
+    0U,	// G_SEXT
+    0U,	// G_SEXT_INREG
+    0U,	// G_ZEXT
+    0U,	// G_SHL
+    0U,	// G_LSHR
+    0U,	// G_ASHR
+    0U,	// G_FSHL
+    0U,	// G_FSHR
+    0U,	// G_ROTR
+    0U,	// G_ROTL
+    0U,	// G_ICMP
+    0U,	// G_FCMP
+    0U,	// G_SELECT
+    0U,	// G_UADDO
+    0U,	// G_UADDE
+    0U,	// G_USUBO
+    0U,	// G_USUBE
+    0U,	// G_SADDO
+    0U,	// G_SADDE
+    0U,	// G_SSUBO
+    0U,	// G_SSUBE
+    0U,	// G_UMULO
+    0U,	// G_SMULO
+    0U,	// G_UMULH
+    0U,	// G_SMULH
+    0U,	// G_UADDSAT
+    0U,	// G_SADDSAT
+    0U,	// G_USUBSAT
+    0U,	// G_SSUBSAT
+    0U,	// G_USHLSAT
+    0U,	// G_SSHLSAT
+    0U,	// G_SMULFIX
+    0U,	// G_UMULFIX
+    0U,	// G_SMULFIXSAT
+    0U,	// G_UMULFIXSAT
+    0U,	// G_SDIVFIX
+    0U,	// G_UDIVFIX
+    0U,	// G_SDIVFIXSAT
+    0U,	// G_UDIVFIXSAT
+    0U,	// G_FADD
+    0U,	// G_FSUB
+    0U,	// G_FMUL
+    0U,	// G_FMA
+    0U,	// G_FMAD
+    0U,	// G_FDIV
+    0U,	// G_FREM
+    0U,	// G_FPOW
+    0U,	// G_FPOWI
+    0U,	// G_FEXP
+    0U,	// G_FEXP2
+    0U,	// G_FLOG
+    0U,	// G_FLOG2
+    0U,	// G_FLOG10
+    0U,	// G_FNEG
+    0U,	// G_FPEXT
+    0U,	// G_FPTRUNC
+    0U,	// G_FPTOSI
+    0U,	// G_FPTOUI
+    0U,	// G_SITOFP
+    0U,	// G_UITOFP
+    0U,	// G_FABS
+    0U,	// G_FCOPYSIGN
+    0U,	// G_IS_FPCLASS
+    0U,	// G_FCANONICALIZE
+    0U,	// G_FMINNUM
+    0U,	// G_FMAXNUM
+    0U,	// G_FMINNUM_IEEE
+    0U,	// G_FMAXNUM_IEEE
+    0U,	// G_FMINIMUM
+    0U,	// G_FMAXIMUM
+    0U,	// G_PTR_ADD
+    0U,	// G_PTRMASK
+    0U,	// G_SMIN
+    0U,	// G_SMAX
+    0U,	// G_UMIN
+    0U,	// G_UMAX
+    0U,	// G_ABS
+    0U,	// G_LROUND
+    0U,	// G_LLROUND
+    0U,	// G_BR
+    0U,	// G_BRJT
+    0U,	// G_INSERT_VECTOR_ELT
+    0U,	// G_EXTRACT_VECTOR_ELT
+    0U,	// G_SHUFFLE_VECTOR
+    0U,	// G_CTTZ
+    0U,	// G_CTTZ_ZERO_UNDEF
+    0U,	// G_CTLZ
+    0U,	// G_CTLZ_ZERO_UNDEF
+    0U,	// G_CTPOP
+    0U,	// G_BSWAP
+    0U,	// G_BITREVERSE
+    0U,	// G_FCEIL
+    0U,	// G_FCOS
+    0U,	// G_FSIN
+    0U,	// G_FSQRT
+    0U,	// G_FFLOOR
+    0U,	// G_FRINT
+    0U,	// G_FNEARBYINT
+    0U,	// G_ADDRSPACE_CAST
+    0U,	// G_BLOCK_ADDR
+    0U,	// G_JUMP_TABLE
+    0U,	// G_DYN_STACKALLOC
+    0U,	// G_STRICT_FADD
+    0U,	// G_STRICT_FSUB
+    0U,	// G_STRICT_FMUL
+    0U,	// G_STRICT_FDIV
+    0U,	// G_STRICT_FREM
+    0U,	// G_STRICT_FMA
+    0U,	// G_STRICT_FSQRT
+    0U,	// G_READ_REGISTER
+    0U,	// G_WRITE_REGISTER
+    0U,	// G_MEMCPY
+    0U,	// G_MEMCPY_INLINE
+    0U,	// G_MEMMOVE
+    0U,	// G_MEMSET
+    0U,	// G_BZERO
+    0U,	// G_VECREDUCE_SEQ_FADD
+    0U,	// G_VECREDUCE_SEQ_FMUL
+    0U,	// G_VECREDUCE_FADD
+    0U,	// G_VECREDUCE_FMUL
+    0U,	// G_VECREDUCE_FMAX
+    0U,	// G_VECREDUCE_FMIN
+    0U,	// G_VECREDUCE_ADD
+    0U,	// G_VECREDUCE_MUL
+    0U,	// G_VECREDUCE_AND
+    0U,	// G_VECREDUCE_OR
+    0U,	// G_VECREDUCE_XOR
+    0U,	// G_VECREDUCE_SMAX
+    0U,	// G_VECREDUCE_SMIN
+    0U,	// G_VECREDUCE_UMAX
+    0U,	// G_VECREDUCE_UMIN
+    0U,	// G_SBFX
+    0U,	// G_UBFX
+    0U,	// ABSDIFS_B_rr_v110
+    0U,	// ABSDIFS_H_rr
+    0U,	// ABSDIFS_rc
+    0U,	// ABSDIFS_rr
+    0U,	// ABSDIF_B_rr
+    0U,	// ABSDIF_H_rr
+    0U,	// ABSDIF_rc
+    0U,	// ABSDIF_rr
+    0U,	// ABSS_B_rr_v110
+    0U,	// ABSS_H_rr
+    0U,	// ABSS_rr
+    0U,	// ABS_B_rr
+    0U,	// ABS_H_rr
+    0U,	// ABS_rr
+    0U,	// ADDC_rc
+    0U,	// ADDC_rr
+    0U,	// ADDIH_A_rlc
+    0U,	// ADDIH_rlc
+    0U,	// ADDI_rlc
+    0U,	// ADDSC_AT_rr
+    0U,	// ADDSC_AT_rr_v110
+    2U,	// ADDSC_A_rr
+    2U,	// ADDSC_A_rr_v110
+    0U,	// ADDSC_A_srrs
+    0U,	// ADDSC_A_srrs_v110
+    0U,	// ADDS_BU_rr_v110
+    0U,	// ADDS_B_rr
+    0U,	// ADDS_H
+    0U,	// ADDS_HU
+    0U,	// ADDS_U
+    0U,	// ADDS_U_rc
+    0U,	// ADDS_rc
+    0U,	// ADDS_rr
+    0U,	// ADDS_srr
+    0U,	// ADDX_rc
+    0U,	// ADDX_rr
+    0U,	// ADD_A_rr
+    0U,	// ADD_A_src
+    0U,	// ADD_A_srr
+    0U,	// ADD_B_rr
+    0U,	// ADD_F_rrr
+    0U,	// ADD_H_rr
+    0U,	// ADD_rc
+    0U,	// ADD_rr
+    0U,	// ADD_src
+    0U,	// ADD_src_15a
+    0U,	// ADD_src_a15
+    0U,	// ADD_srr
+    0U,	// ADD_srr_15a
+    0U,	// ADD_srr_a15
+    0U,	// ANDN_T
+    0U,	// ANDN_rc
+    0U,	// ANDN_rr
+    0U,	// AND_ANDN_T
+    0U,	// AND_AND_T
+    0U,	// AND_EQ_rc
+    0U,	// AND_EQ_rr
+    0U,	// AND_GE_U_rc
+    0U,	// AND_GE_U_rr
+    0U,	// AND_GE_rc
+    0U,	// AND_GE_rr
+    0U,	// AND_LT_U_rc
+    0U,	// AND_LT_U_rr
+    0U,	// AND_LT_rc
+    0U,	// AND_LT_rr
+    0U,	// AND_NE_rc
+    0U,	// AND_NE_rr
+    0U,	// AND_NOR_T
+    0U,	// AND_OR_T
+    0U,	// AND_T
+    0U,	// AND_rc
+    0U,	// AND_rr
+    0U,	// AND_sc
+    0U,	// AND_sc_v110
+    0U,	// AND_srr
+    0U,	// AND_srr_v110
+    0U,	// BISR_rc
+    0U,	// BISR_rc_v161
+    0U,	// BISR_sc
+    0U,	// BISR_sc_v110
+    0U,	// BMERGAE_rr_v110
+    0U,	// BMERGE_rr
+    0U,	// BSPLIT_rr
+    0U,	// BSPLIT_rr_v110
+    0U,	// CACHEA_I_bo_bso
+    0U,	// CACHEA_I_bo_c
+    0U,	// CACHEA_I_bo_pos
+    0U,	// CACHEA_I_bo_pre
+    0U,	// CACHEA_I_bo_r
+    0U,	// CACHEA_WI_bo_bso
+    0U,	// CACHEA_WI_bo_c
+    0U,	// CACHEA_WI_bo_pos
+    0U,	// CACHEA_WI_bo_pre
+    0U,	// CACHEA_WI_bo_r
+    0U,	// CACHEA_W_bo_bso
+    0U,	// CACHEA_W_bo_c
+    0U,	// CACHEA_W_bo_pos
+    0U,	// CACHEA_W_bo_pre
+    0U,	// CACHEA_W_bo_r
+    0U,	// CACHEI_I_bo_bso
+    0U,	// CACHEI_I_bo_pos
+    0U,	// CACHEI_I_bo_pre
+    0U,	// CACHEI_WI_bo_bso
+    0U,	// CACHEI_WI_bo_pos
+    0U,	// CACHEI_WI_bo_pre
+    0U,	// CACHEI_W_bo_bso
+    0U,	// CACHEI_W_bo_pos
+    0U,	// CACHEI_W_bo_pre
+    34U,	// CADDN_A_rcr_v110
+    69U,	// CADDN_A_rrr_v110
+    34U,	// CADDN_rcr
+    69U,	// CADDN_rrr
+    0U,	// CADDN_src
+    0U,	// CADDN_srr_v110
+    34U,	// CADD_A_rcr_v110
+    69U,	// CADD_A_rrr_v110
+    34U,	// CADD_rcr
+    69U,	// CADD_rrr
+    0U,	// CADD_src
+    0U,	// CADD_srr_v110
+    0U,	// CALLA_b
+    0U,	// CALLI_rr
+    0U,	// CALLI_rr_v110
+    0U,	// CALL_b
+    0U,	// CALL_sb
+    0U,	// CLO_B_rr_v110
+    0U,	// CLO_H_rr
+    0U,	// CLO_rr
+    0U,	// CLS_B_rr_v110
+    0U,	// CLS_H_rr
+    0U,	// CLS_rr
+    0U,	// CLZ_B_rr_v110
+    0U,	// CLZ_H_rr
+    0U,	// CLZ_rr
+    0U,	// CMOVN_src
+    0U,	// CMOVN_srr
+    0U,	// CMOV_src
+    0U,	// CMOV_srr
+    0U,	// CMPSWAP_W_bo_bso
+    0U,	// CMPSWAP_W_bo_c
+    0U,	// CMPSWAP_W_bo_pos
+    0U,	// CMPSWAP_W_bo_pre
+    0U,	// CMPSWAP_W_bo_r
+    0U,	// CMP_F_rr
+    0U,	// CRC32B_W_rr
+    0U,	// CRC32L_W_rr
+    0U,	// CRC32_B_rr
+    69U,	// CRCN_rrr
+    69U,	// CSUBN_A__rrr_v110
+    69U,	// CSUBN_rrr
+    69U,	// CSUB_A__rrr_v110
+    69U,	// CSUB_rrr
+    0U,	// DEBUG_sr
+    0U,	// DEBUG_sys
+    98U,	// DEXTR_rrpw
+    98U,	// DEXTR_rrrr
+    2U,	// DIFSC_A_rr_v110
+    0U,	// DISABLE_sys
+    0U,	// DISABLE_sys_1
+    0U,	// DIV_F_rr
+    0U,	// DIV_U_rr
+    0U,	// DIV_rr
+    0U,	// DSYNC_sys
+    0U,	// DVADJ_rrr
+    0U,	// DVADJ_rrr_v110
+    0U,	// DVADJ_srr_v110
+    0U,	// DVINIT_BU_rr
+    0U,	// DVINIT_BU_rr_v110
+    0U,	// DVINIT_B_rr
+    0U,	// DVINIT_B_rr_v110
+    0U,	// DVINIT_HU_rr
+    0U,	// DVINIT_HU_rr_v110
+    0U,	// DVINIT_H_rr
+    0U,	// DVINIT_H_rr_v110
+    0U,	// DVINIT_U_rr
+    0U,	// DVINIT_U_rr_v110
+    0U,	// DVINIT_rr
+    0U,	// DVINIT_rr_v110
+    0U,	// DVSTEP_U_rrr
+    0U,	// DVSTEP_U_rrrv110
+    0U,	// DVSTEP_Uv110
+    0U,	// DVSTEP_rrr
+    0U,	// DVSTEP_rrrv110
+    0U,	// DVSTEPv110
+    0U,	// ENABLE_sys
+    0U,	// EQANY_B_rc
+    0U,	// EQANY_B_rr
+    0U,	// EQANY_H_rc
+    0U,	// EQANY_H_rr
+    0U,	// EQZ_A_rr
+    0U,	// EQ_A_rr
+    0U,	// EQ_B_rr
+    0U,	// EQ_H_rr
+    0U,	// EQ_W_rr
+    0U,	// EQ_rc
+    0U,	// EQ_rr
+    0U,	// EQ_src
+    0U,	// EQ_srr
+    7U,	// EXTR_U_rrpw
+    0U,	// EXTR_U_rrrr
+    7U,	// EXTR_U_rrrw
+    7U,	// EXTR_rrpw
+    0U,	// EXTR_rrrr
+    7U,	// EXTR_rrrw
+    0U,	// FCALLA_b
+    0U,	// FCALLA_i
+    0U,	// FCALL_b
+    0U,	// FRET_sr
+    0U,	// FRET_sys
+    0U,	// FTOHP_rr
+    0U,	// FTOIZ_rr
+    0U,	// FTOI_rr
+    0U,	// FTOQ31Z_rr
+    0U,	// FTOQ31_rr
+    0U,	// FTOUZ_rr
+    0U,	// FTOU_rr
+    0U,	// GE_A_rr
+    0U,	// GE_U_rc
+    0U,	// GE_U_rr
+    0U,	// GE_rc
+    0U,	// GE_rr
+    0U,	// HPTOF_rr
+    7U,	// IMASK_rcpw
+    7U,	// IMASK_rcrw
+    7U,	// IMASK_rrpw
+    7U,	// IMASK_rrrw
+    610U,	// INSERT_rcpw
+    98U,	// INSERT_rcrr
+    1157U,	// INSERT_rcrw
+    610U,	// INSERT_rrpw
+    98U,	// INSERT_rrrr
+    610U,	// INSERT_rrrw
+    0U,	// INSN_T
+    0U,	// INS_T
+    0U,	// ISYNC_sys
+    0U,	// ITOF_rr
+    0U,	// IXMAX_U_rrr
+    0U,	// IXMAX_rrr
+    0U,	// IXMIN_U_rrr
+    0U,	// IXMIN_rrr
+    0U,	// JA_b
+    1U,	// JEQ_A_brr
+    1U,	// JEQ_brc
+    1U,	// JEQ_brr
+    0U,	// JEQ_sbc1
+    0U,	// JEQ_sbc2
+    0U,	// JEQ_sbc_v110
+    0U,	// JEQ_sbr1
+    0U,	// JEQ_sbr2
+    0U,	// JEQ_sbr_v110
+    0U,	// JGEZ_sbr
+    0U,	// JGEZ_sbr_v110
+    1U,	// JGE_U_brc
+    1U,	// JGE_U_brr
+    1U,	// JGE_brc
+    1U,	// JGE_brr
+    0U,	// JGTZ_sbr
+    0U,	// JGTZ_sbr_v110
+    0U,	// JI_rr
+    0U,	// JI_rr_v110
+    0U,	// JI_sbr_v110
+    0U,	// JI_sr
+    0U,	// JLA_b
+    0U,	// JLEZ_sbr
+    0U,	// JLEZ_sbr_v110
+    0U,	// JLI_rr
+    0U,	// JLI_rr_v110
+    0U,	// JLTZ_sbr
+    0U,	// JLTZ_sbr_v110
+    1U,	// JLT_U_brc
+    1U,	// JLT_U_brr
+    1U,	// JLT_brc
+    1U,	// JLT_brr
+    0U,	// JL_b
+    1U,	// JNED_brc
+    1U,	// JNED_brr
+    1U,	// JNEI_brc
+    1U,	// JNEI_brr
+    1U,	// JNE_A_brr
+    1U,	// JNE_brc
+    1U,	// JNE_brr
+    0U,	// JNE_sbc1
+    0U,	// JNE_sbc2
+    0U,	// JNE_sbc_v110
+    0U,	// JNE_sbr1
+    0U,	// JNE_sbr2
+    0U,	// JNE_sbr_v110
+    0U,	// JNZ_A_brr
+    0U,	// JNZ_A_sbr
+    1U,	// JNZ_T_brn
+    0U,	// JNZ_T_sbrn
+    0U,	// JNZ_T_sbrn_v110
+    0U,	// JNZ_sb
+    0U,	// JNZ_sb_v110
+    0U,	// JNZ_sbr
+    0U,	// JNZ_sbr_v110
+    0U,	// JZ_A_brr
+    0U,	// JZ_A_sbr
+    1U,	// JZ_T_brn
+    0U,	// JZ_T_sbrn
+    0U,	// JZ_T_sbrn_v110
+    0U,	// JZ_sb
+    0U,	// JZ_sb_v110
+    0U,	// JZ_sbr
+    0U,	// JZ_sbr_v110
+    0U,	// J_b
+    0U,	// J_sb
+    0U,	// J_sb_v110
+    0U,	// LDLCX_abs
+    0U,	// LDLCX_bo_bso
+    0U,	// LDMST_abs
+    0U,	// LDMST_bo_bso
+    0U,	// LDMST_bo_c
+    0U,	// LDMST_bo_pos
+    0U,	// LDMST_bo_pre
+    0U,	// LDMST_bo_r
+    0U,	// LDUCX_abs
+    0U,	// LDUCX_bo_bso
+    0U,	// LD_A_abs
+    0U,	// LD_A_bo_bso
+    0U,	// LD_A_bo_c
+    0U,	// LD_A_bo_pos
+    0U,	// LD_A_bo_pre
+    0U,	// LD_A_bo_r
+    0U,	// LD_A_bol
+    0U,	// LD_A_sc
+    0U,	// LD_A_slr
+    0U,	// LD_A_slr_post
+    0U,	// LD_A_slr_post_v110
+    0U,	// LD_A_slr_v110
+    0U,	// LD_A_slro
+    0U,	// LD_A_slro_v110
+    0U,	// LD_A_sro
+    0U,	// LD_A_sro_v110
+    0U,	// LD_BU_abs
+    0U,	// LD_BU_bo_bso
+    0U,	// LD_BU_bo_c
+    0U,	// LD_BU_bo_pos
+    0U,	// LD_BU_bo_pre
+    0U,	// LD_BU_bo_r
+    0U,	// LD_BU_bol
+    0U,	// LD_BU_slr
+    0U,	// LD_BU_slr_post
+    0U,	// LD_BU_slr_post_v110
+    0U,	// LD_BU_slr_v110
+    0U,	// LD_BU_slro
+    0U,	// LD_BU_slro_v110
+    0U,	// LD_BU_sro
+    0U,	// LD_BU_sro_v110
+    0U,	// LD_B_abs
+    0U,	// LD_B_bo_bso
+    0U,	// LD_B_bo_c
+    0U,	// LD_B_bo_pos
+    0U,	// LD_B_bo_pre
+    0U,	// LD_B_bo_r
+    0U,	// LD_B_bol
+    0U,	// LD_B_slr_post_v110
+    0U,	// LD_B_slr_v110
+    0U,	// LD_B_slro_v110
+    0U,	// LD_B_sro_v110
+    0U,	// LD_DA_abs
+    0U,	// LD_DA_bo_bso
+    0U,	// LD_DA_bo_c
+    0U,	// LD_DA_bo_pos
+    0U,	// LD_DA_bo_pre
+    0U,	// LD_DA_bo_r
+    0U,	// LD_D_abs
+    0U,	// LD_D_bo_bso
+    0U,	// LD_D_bo_c
+    0U,	// LD_D_bo_pos
+    0U,	// LD_D_bo_pre
+    0U,	// LD_D_bo_r
+    0U,	// LD_HU_abs
+    0U,	// LD_HU_bo_bso
+    0U,	// LD_HU_bo_c
+    0U,	// LD_HU_bo_pos
+    0U,	// LD_HU_bo_pre
+    0U,	// LD_HU_bo_r
+    0U,	// LD_HU_bol
+    0U,	// LD_H_abs
+    0U,	// LD_H_bo_bso
+    0U,	// LD_H_bo_c
+    0U,	// LD_H_bo_pos
+    0U,	// LD_H_bo_pre
+    0U,	// LD_H_bo_r
+    0U,	// LD_H_bol
+    0U,	// LD_H_slr
+    0U,	// LD_H_slr_post
+    0U,	// LD_H_slr_post_v110
+    0U,	// LD_H_slr_v110
+    0U,	// LD_H_slro
+    0U,	// LD_H_slro_v110
+    0U,	// LD_H_sro
+    0U,	// LD_H_sro_v110
+    0U,	// LD_Q_abs
+    0U,	// LD_Q_bo_bso
+    0U,	// LD_Q_bo_c
+    0U,	// LD_Q_bo_pos
+    0U,	// LD_Q_bo_pre
+    0U,	// LD_Q_bo_r
+    0U,	// LD_W_abs
+    0U,	// LD_W_bo_bso
+    0U,	// LD_W_bo_c
+    0U,	// LD_W_bo_pos
+    0U,	// LD_W_bo_pre
+    0U,	// LD_W_bo_r
+    0U,	// LD_W_bol
+    0U,	// LD_W_sc
+    0U,	// LD_W_slr
+    0U,	// LD_W_slr_post
+    0U,	// LD_W_slr_post_v110
+    0U,	// LD_W_slr_v110
+    0U,	// LD_W_slro
+    0U,	// LD_W_slro_v110
+    0U,	// LD_W_sro
+    0U,	// LD_W_sro_v110
+    0U,	// LEA_abs
+    0U,	// LEA_bo_bso
+    0U,	// LEA_bol
+    0U,	// LHA_abs
+    0U,	// LOOPU_brr
+    0U,	// LOOP_brr
+    0U,	// LOOP_sbr
+    0U,	// LT_A_rr
+    0U,	// LT_B
+    0U,	// LT_BU
+    0U,	// LT_H
+    0U,	// LT_HU
+    0U,	// LT_U_rc
+    0U,	// LT_U_rr
+    0U,	// LT_U_srcv110
+    0U,	// LT_U_srrv110
+    0U,	// LT_W
+    0U,	// LT_WU
+    0U,	// LT_rc
+    0U,	// LT_rr
+    0U,	// LT_src
+    0U,	// LT_srr
+    165U,	// MADDMS_H_rrr1_LL
+    197U,	// MADDMS_H_rrr1_LU
+    229U,	// MADDMS_H_rrr1_UL
+    261U,	// MADDMS_H_rrr1_UU
+    290U,	// MADDMS_U_rcr_v110
+    69U,	// MADDMS_U_rrr2_v110
+    34U,	// MADDMS_rcr_v110
+    69U,	// MADDMS_rrr2_v110
+    165U,	// MADDM_H_rrr1_LL
+    197U,	// MADDM_H_rrr1_LU
+    229U,	// MADDM_H_rrr1_UL
+    261U,	// MADDM_H_rrr1_UU
+    69U,	// MADDM_H_rrr1_v110
+    69U,	// MADDM_Q_rrr1_v110
+    290U,	// MADDM_U_rcr_v110
+    69U,	// MADDM_U_rrr2_v110
+    34U,	// MADDM_rcr_v110
+    69U,	// MADDM_rrr2_v110
+    165U,	// MADDRS_H_rrr1_LL
+    197U,	// MADDRS_H_rrr1_LU
+    229U,	// MADDRS_H_rrr1_UL
+    229U,	// MADDRS_H_rrr1_UL_2
+    261U,	// MADDRS_H_rrr1_UU
+    1669U,	// MADDRS_H_rrr1_v110
+    1U,	// MADDRS_Q_rrr1_L_L
+    1U,	// MADDRS_Q_rrr1_U_U
+    1669U,	// MADDRS_Q_rrr1_v110
+    165U,	// MADDR_H_rrr1_LL
+    197U,	// MADDR_H_rrr1_LU
+    229U,	// MADDR_H_rrr1_UL
+    229U,	// MADDR_H_rrr1_UL_2
+    261U,	// MADDR_H_rrr1_UU
+    1669U,	// MADDR_H_rrr1_v110
+    1U,	// MADDR_Q_rrr1_L_L
+    1U,	// MADDR_Q_rrr1_U_U
+    1669U,	// MADDR_Q_rrr1_v110
+    165U,	// MADDSUMS_H_rrr1_LL
+    197U,	// MADDSUMS_H_rrr1_LU
+    229U,	// MADDSUMS_H_rrr1_UL
+    261U,	// MADDSUMS_H_rrr1_UU
+    165U,	// MADDSUM_H_rrr1_LL
+    197U,	// MADDSUM_H_rrr1_LU
+    229U,	// MADDSUM_H_rrr1_UL
+    261U,	// MADDSUM_H_rrr1_UU
+    165U,	// MADDSURS_H_rrr1_LL
+    197U,	// MADDSURS_H_rrr1_LU
+    229U,	// MADDSURS_H_rrr1_UL
+    261U,	// MADDSURS_H_rrr1_UU
+    165U,	// MADDSUR_H_rrr1_LL
+    197U,	// MADDSUR_H_rrr1_LU
+    229U,	// MADDSUR_H_rrr1_UL
+    261U,	// MADDSUR_H_rrr1_UU
+    165U,	// MADDSUS_H_rrr1_LL
+    197U,	// MADDSUS_H_rrr1_LU
+    229U,	// MADDSUS_H_rrr1_UL
+    261U,	// MADDSUS_H_rrr1_UU
+    165U,	// MADDSU_H_rrr1_LL
+    197U,	// MADDSU_H_rrr1_LU
+    229U,	// MADDSU_H_rrr1_UL
+    261U,	// MADDSU_H_rrr1_UU
+    165U,	// MADDS_H_rrr1_LL
+    197U,	// MADDS_H_rrr1_LU
+    229U,	// MADDS_H_rrr1_UL
+    261U,	// MADDS_H_rrr1_UU
+    1669U,	// MADDS_H_rrr1_v110
+    1669U,	// MADDS_Q_rrr1
+    325U,	// MADDS_Q_rrr1_L
+    1U,	// MADDS_Q_rrr1_L_L
+    357U,	// MADDS_Q_rrr1_U
+    1669U,	// MADDS_Q_rrr1_UU2_v110
+    1U,	// MADDS_Q_rrr1_U_U
+    1669U,	// MADDS_Q_rrr1_e
+    325U,	// MADDS_Q_rrr1_e_L
+    1U,	// MADDS_Q_rrr1_e_L_L
+    357U,	// MADDS_Q_rrr1_e_U
+    1U,	// MADDS_Q_rrr1_e_U_U
+    34U,	// MADDS_U_rcr
+    34U,	// MADDS_U_rcr_e
+    69U,	// MADDS_U_rrr2
+    69U,	// MADDS_U_rrr2_e
+    34U,	// MADDS_rcr
+    34U,	// MADDS_rcr_e
+    69U,	// MADDS_rrr2
+    69U,	// MADDS_rrr2_e
+    69U,	// MADD_F_rrr
+    165U,	// MADD_H_rrr1_LL
+    197U,	// MADD_H_rrr1_LU
+    229U,	// MADD_H_rrr1_UL
+    261U,	// MADD_H_rrr1_UU
+    1669U,	// MADD_H_rrr1_v110
+    1669U,	// MADD_Q_rrr1
+    325U,	// MADD_Q_rrr1_L
+    1U,	// MADD_Q_rrr1_L_L
+    357U,	// MADD_Q_rrr1_U
+    1669U,	// MADD_Q_rrr1_UU2_v110
+    1U,	// MADD_Q_rrr1_U_U
+    1669U,	// MADD_Q_rrr1_e
+    325U,	// MADD_Q_rrr1_e_L
+    1U,	// MADD_Q_rrr1_e_L_L
+    357U,	// MADD_Q_rrr1_e_U
+    1U,	// MADD_Q_rrr1_e_U_U
+    290U,	// MADD_U_rcr
+    69U,	// MADD_U_rrr2
+    34U,	// MADD_rcr
+    34U,	// MADD_rcr_e
+    69U,	// MADD_rrr2
+    69U,	// MADD_rrr2_e
+    0U,	// MAX_B
+    0U,	// MAX_BU
+    0U,	// MAX_H
+    0U,	// MAX_HU
+    0U,	// MAX_U_rc
+    0U,	// MAX_U_rr
+    0U,	// MAX_rc
+    0U,	// MAX_rr
+    0U,	// MFCR_rlc
+    0U,	// MIN_B
+    0U,	// MIN_BU
+    0U,	// MIN_H
+    0U,	// MIN_HU
+    0U,	// MIN_U_rc
+    0U,	// MIN_U_rr
+    0U,	// MIN_rc
+    0U,	// MIN_rr
+    0U,	// MOVH_A_rlc
+    0U,	// MOVH_rlc
+    0U,	// MOVZ_A_sr
+    0U,	// MOV_AA_rr
+    0U,	// MOV_AA_srr_srr
+    0U,	// MOV_AA_srr_srr_v110
+    0U,	// MOV_A_rr
+    0U,	// MOV_A_src
+    0U,	// MOV_A_srr
+    0U,	// MOV_A_srr_v110
+    0U,	// MOV_D_rr
+    0U,	// MOV_D_srr_srr
+    0U,	// MOV_D_srr_srr_v110
+    0U,	// MOV_U_rlc
+    0U,	// MOV_rlc
+    0U,	// MOV_rlc_e
+    0U,	// MOV_rr
+    0U,	// MOV_rr_e
+    0U,	// MOV_rr_eab
+    0U,	// MOV_sc
+    0U,	// MOV_sc_v110
+    0U,	// MOV_src
+    0U,	// MOV_src_e
+    0U,	// MOV_srr
+    165U,	// MSUBADMS_H_rrr1_LL
+    197U,	// MSUBADMS_H_rrr1_LU
+    229U,	// MSUBADMS_H_rrr1_UL
+    261U,	// MSUBADMS_H_rrr1_UU
+    165U,	// MSUBADM_H_rrr1_LL
+    197U,	// MSUBADM_H_rrr1_LU
+    229U,	// MSUBADM_H_rrr1_UL
+    261U,	// MSUBADM_H_rrr1_UU
+    165U,	// MSUBADRS_H_rrr1_LL
+    197U,	// MSUBADRS_H_rrr1_LU
+    229U,	// MSUBADRS_H_rrr1_UL
+    261U,	// MSUBADRS_H_rrr1_UU
+    1669U,	// MSUBADRS_H_rrr1_v110
+    165U,	// MSUBADR_H_rrr1_LL
+    197U,	// MSUBADR_H_rrr1_LU
+    229U,	// MSUBADR_H_rrr1_UL
+    261U,	// MSUBADR_H_rrr1_UU
+    1669U,	// MSUBADR_H_rrr1_v110
+    165U,	// MSUBADS_H_rrr1_LL
+    197U,	// MSUBADS_H_rrr1_LU
+    229U,	// MSUBADS_H_rrr1_UL
+    261U,	// MSUBADS_H_rrr1_UU
+    165U,	// MSUBAD_H_rrr1_LL
+    197U,	// MSUBAD_H_rrr1_LU
+    229U,	// MSUBAD_H_rrr1_UL
+    261U,	// MSUBAD_H_rrr1_UU
+    165U,	// MSUBMS_H_rrr1_LL
+    197U,	// MSUBMS_H_rrr1_LU
+    229U,	// MSUBMS_H_rrr1_UL
+    261U,	// MSUBMS_H_rrr1_UU
+    34U,	// MSUBMS_U_rcrv110
+    69U,	// MSUBMS_U_rrr2v110
+    34U,	// MSUBMS_rcrv110
+    69U,	// MSUBMS_rrr2v110
+    165U,	// MSUBM_H_rrr1_LL
+    197U,	// MSUBM_H_rrr1_LU
+    229U,	// MSUBM_H_rrr1_UL
+    261U,	// MSUBM_H_rrr1_UU
+    69U,	// MSUBM_H_rrr1_v110
+    69U,	// MSUBM_Q_rrr1_v110
+    34U,	// MSUBM_U_rcrv110
+    69U,	// MSUBM_U_rrr2v110
+    34U,	// MSUBM_rcrv110
+    69U,	// MSUBM_rrr2v110
+    165U,	// MSUBRS_H_rrr1_LL
+    197U,	// MSUBRS_H_rrr1_LU
+    229U,	// MSUBRS_H_rrr1_UL
+    229U,	// MSUBRS_H_rrr1_UL_2
+    261U,	// MSUBRS_H_rrr1_UU
+    1669U,	// MSUBRS_H_rrr1_v110
+    1U,	// MSUBRS_Q_rrr1_L_L
+    1U,	// MSUBRS_Q_rrr1_U_U
+    1669U,	// MSUBRS_Q_rrr1_v110
+    165U,	// MSUBR_H_rrr1_LL
+    197U,	// MSUBR_H_rrr1_LU
+    229U,	// MSUBR_H_rrr1_UL
+    229U,	// MSUBR_H_rrr1_UL_2
+    261U,	// MSUBR_H_rrr1_UU
+    1669U,	// MSUBR_H_rrr1_v110
+    1U,	// MSUBR_Q_rrr1_L_L
+    1U,	// MSUBR_Q_rrr1_U_U
+    1669U,	// MSUBR_Q_rrr1_v110
+    165U,	// MSUBS_H_rrr1_LL
+    197U,	// MSUBS_H_rrr1_LU
+    229U,	// MSUBS_H_rrr1_UL
+    261U,	// MSUBS_H_rrr1_UU
+    1669U,	// MSUBS_H_rrr1_v110
+    1669U,	// MSUBS_Q_rrr1
+    325U,	// MSUBS_Q_rrr1_L
+    1U,	// MSUBS_Q_rrr1_L_L
+    357U,	// MSUBS_Q_rrr1_U
+    1669U,	// MSUBS_Q_rrr1_UU2_v110
+    1U,	// MSUBS_Q_rrr1_U_U
+    1669U,	// MSUBS_Q_rrr1_e
+    325U,	// MSUBS_Q_rrr1_e_L
+    1U,	// MSUBS_Q_rrr1_e_L_L
+    357U,	// MSUBS_Q_rrr1_e_U
+    1U,	// MSUBS_Q_rrr1_e_U_U
+    34U,	// MSUBS_U_rcr
+    34U,	// MSUBS_U_rcr_e
+    69U,	// MSUBS_U_rrr2
+    69U,	// MSUBS_U_rrr2_e
+    34U,	// MSUBS_rcr
+    34U,	// MSUBS_rcr_e
+    69U,	// MSUBS_rrr2
+    69U,	// MSUBS_rrr2_e
+    69U,	// MSUB_F_rrr
+    165U,	// MSUB_H_rrr1_LL
+    197U,	// MSUB_H_rrr1_LU
+    229U,	// MSUB_H_rrr1_UL
+    261U,	// MSUB_H_rrr1_UU
+    1669U,	// MSUB_H_rrr1_v110
+    1669U,	// MSUB_Q_rrr1
+    325U,	// MSUB_Q_rrr1_L
+    1U,	// MSUB_Q_rrr1_L_L
+    357U,	// MSUB_Q_rrr1_U
+    1669U,	// MSUB_Q_rrr1_UU2_v110
+    1U,	// MSUB_Q_rrr1_U_U
+    1669U,	// MSUB_Q_rrr1_e
+    325U,	// MSUB_Q_rrr1_e_L
+    1U,	// MSUB_Q_rrr1_e_L_L
+    357U,	// MSUB_Q_rrr1_e_U
+    1U,	// MSUB_Q_rrr1_e_U_U
+    290U,	// MSUB_U_rcr
+    69U,	// MSUB_U_rrr2
+    34U,	// MSUB_rcr
+    34U,	// MSUB_rcr_e
+    69U,	// MSUB_rrr2
+    69U,	// MSUB_rrr2_e
+    0U,	// MTCR_rlc
+    8U,	// MULMS_H_rr1_LL2e
+    10U,	// MULMS_H_rr1_LU2e
+    12U,	// MULMS_H_rr1_UL2e
+    14U,	// MULMS_H_rr1_UU2e
+    8U,	// MULM_H_rr1_LL2e
+    10U,	// MULM_H_rr1_LU2e
+    12U,	// MULM_H_rr1_UL2e
+    14U,	// MULM_H_rr1_UU2e
+    0U,	// MULM_U_rc
+    0U,	// MULM_U_rr
+    0U,	// MULM_rc
+    0U,	// MULM_rr
+    8U,	// MULR_H_rr1_LL2e
+    10U,	// MULR_H_rr1_LU2e
+    12U,	// MULR_H_rr1_UL2e
+    14U,	// MULR_H_rr1_UU2e
+    2U,	// MULR_H_rr_v110
+    0U,	// MULR_Q_rr1_2LL
+    0U,	// MULR_Q_rr1_2UU
+    2U,	// MULR_Q_rr_v110
+    0U,	// MULS_U_rc
+    0U,	// MULS_U_rr2
+    0U,	// MULS_U_rr_v110
+    0U,	// MULS_rc
+    0U,	// MULS_rr2
+    0U,	// MULS_rr_v110
+    0U,	// MUL_F_rrr
+    8U,	// MUL_H_rr1_LL2e
+    10U,	// MUL_H_rr1_LU2e
+    12U,	// MUL_H_rr1_UL2e
+    14U,	// MUL_H_rr1_UU2e
+    2U,	// MUL_H_rr_v110
+    2U,	// MUL_Q_rr1_2
+    0U,	// MUL_Q_rr1_2LL
+    0U,	// MUL_Q_rr1_2UU
+    16U,	// MUL_Q_rr1_2_L
+    16U,	// MUL_Q_rr1_2_Le
+    18U,	// MUL_Q_rr1_2_U
+    18U,	// MUL_Q_rr1_2_Ue
+    2U,	// MUL_Q_rr1_2__e
+    2U,	// MUL_Q_rr_v110
+    0U,	// MUL_U_rc
+    0U,	// MUL_U_rr2
+    0U,	// MUL_rc
+    0U,	// MUL_rc_e
+    0U,	// MUL_rr2
+    0U,	// MUL_rr2_e
+    0U,	// MUL_rr_v110
+    0U,	// MUL_srr
+    0U,	// NAND_T
+    0U,	// NAND_rc
+    0U,	// NAND_rr
+    0U,	// NEZ_A
+    0U,	// NE_A
+    0U,	// NE_rc
+    0U,	// NE_rr
+    0U,	// NOP_sr
+    0U,	// NOP_sys
+    0U,	// NOR_T
+    0U,	// NOR_rc
+    0U,	// NOR_rr
+    0U,	// NOR_sr
+    0U,	// NOR_sr_v110
+    0U,	// NOT_sr_v162
+    0U,	// ORN_T
+    0U,	// ORN_rc
+    0U,	// ORN_rr
+    0U,	// OR_ANDN_T
+    0U,	// OR_AND_T
+    0U,	// OR_EQ_rc
+    0U,	// OR_EQ_rr
+    0U,	// OR_GE_U_rc
+    0U,	// OR_GE_U_rr
+    0U,	// OR_GE_rc
+    0U,	// OR_GE_rr
+    0U,	// OR_LT_U_rc
+    0U,	// OR_LT_U_rr
+    0U,	// OR_LT_rc
+    0U,	// OR_LT_rr
+    0U,	// OR_NE_rc
+    0U,	// OR_NE_rr
+    0U,	// OR_NOR_T
+    0U,	// OR_OR_T
+    0U,	// OR_T
+    1U,	// OR_rc
+    0U,	// OR_rr
+    0U,	// OR_sc
+    0U,	// OR_sc_v110
+    0U,	// OR_srr
+    0U,	// OR_srr_v110
+    0U,	// PACK_rrr
+    0U,	// PARITY_rr
+    0U,	// PARITY_rr_v110
+    0U,	// POPCNT_W_rr
+    0U,	// Q31TOF_rr
+    0U,	// QSEED_F_rr
+    0U,	// RESTORE_sys
+    0U,	// RET_sr
+    0U,	// RET_sys
+    0U,	// RET_sys_v110
+    0U,	// RFE_sr
+    0U,	// RFE_sys_sys
+    0U,	// RFE_sys_sys_v110
+    0U,	// RFM_sys
+    0U,	// RSLCX_sys
+    0U,	// RSTV_sys
+    0U,	// RSUBS_U_rc
+    0U,	// RSUBS_rc
+    0U,	// RSUB_rc
+    0U,	// RSUB_sr_sr
+    0U,	// RSUB_sr_sr_v110
+    0U,	// SAT_BU_rr
+    0U,	// SAT_BU_sr
+    0U,	// SAT_BU_sr_v110
+    0U,	// SAT_B_rr
+    0U,	// SAT_B_sr
+    0U,	// SAT_B_sr_v110
+    0U,	// SAT_HU_rr
+    0U,	// SAT_HU_sr
+    0U,	// SAT_HU_sr_v110
+    0U,	// SAT_H_rr
+    0U,	// SAT_H_sr
+    0U,	// SAT_H_sr_v110
+    34U,	// SELN_A_rcr_v110
+    69U,	// SELN_A_rrr_v110
+    34U,	// SELN_rcr
+    69U,	// SELN_rrr
+    34U,	// SEL_A_rcr_v110
+    69U,	// SEL_A_rrr_v110
+    34U,	// SEL_rcr
+    69U,	// SEL_rrr
+    0U,	// SHAS_rc
+    0U,	// SHAS_rr
+    0U,	// SHA_B_rc
+    0U,	// SHA_B_rr
+    0U,	// SHA_H_rc
+    0U,	// SHA_H_rr
+    0U,	// SHA_rc
+    0U,	// SHA_rr
+    0U,	// SHA_src
+    0U,	// SHA_src_v110
+    0U,	// SHUFFLE_rc
+    0U,	// SH_ANDN_T
+    0U,	// SH_AND_T
+    0U,	// SH_B_rc
+    0U,	// SH_B_rr
+    0U,	// SH_EQ_rc
+    0U,	// SH_EQ_rr
+    0U,	// SH_GE_U_rc
+    0U,	// SH_GE_U_rr
+    0U,	// SH_GE_rc
+    0U,	// SH_GE_rr
+    0U,	// SH_H_rc
+    0U,	// SH_H_rr
+    0U,	// SH_LT_U_rc
+    0U,	// SH_LT_U_rr
+    0U,	// SH_LT_rc
+    0U,	// SH_LT_rr
+    0U,	// SH_NAND_T
+    0U,	// SH_NE_rc
+    0U,	// SH_NE_rr
+    0U,	// SH_NOR_T
+    0U,	// SH_ORN_T
+    0U,	// SH_OR_T
+    0U,	// SH_XNOR_T
+    0U,	// SH_XOR_T
+    0U,	// SH_rc
+    0U,	// SH_rr
+    0U,	// SH_src
+    0U,	// SH_src_v110
+    0U,	// STLCX_abs
+    0U,	// STLCX_bo_bso
+    0U,	// STUCX_abs
+    0U,	// STUCX_bo_bso
+    0U,	// ST_A_abs
+    0U,	// ST_A_bo_bso
+    0U,	// ST_A_bo_c
+    0U,	// ST_A_bo_pos
+    0U,	// ST_A_bo_pre
+    0U,	// ST_A_bo_r
+    0U,	// ST_A_bol
+    0U,	// ST_A_sc
+    0U,	// ST_A_sro
+    0U,	// ST_A_sro_v110
+    0U,	// ST_A_ssr
+    0U,	// ST_A_ssr_pos
+    0U,	// ST_A_ssr_pos_v110
+    0U,	// ST_A_ssr_v110
+    0U,	// ST_A_ssro
+    0U,	// ST_A_ssro_v110
+    0U,	// ST_B_abs
+    0U,	// ST_B_bo_bso
+    0U,	// ST_B_bo_c
+    0U,	// ST_B_bo_pos
+    0U,	// ST_B_bo_pre
+    0U,	// ST_B_bo_r
+    0U,	// ST_B_bol
+    0U,	// ST_B_sro
+    0U,	// ST_B_sro_v110
+    0U,	// ST_B_ssr
+    0U,	// ST_B_ssr_pos
+    0U,	// ST_B_ssr_pos_v110
+    0U,	// ST_B_ssr_v110
+    0U,	// ST_B_ssro
+    0U,	// ST_B_ssro_v110
+    0U,	// ST_DA_abs
+    0U,	// ST_DA_bo_bso
+    0U,	// ST_DA_bo_c
+    0U,	// ST_DA_bo_pos
+    0U,	// ST_DA_bo_pre
+    0U,	// ST_DA_bo_r
+    0U,	// ST_D_abs
+    0U,	// ST_D_bo_bso
+    0U,	// ST_D_bo_c
+    0U,	// ST_D_bo_pos
+    0U,	// ST_D_bo_pre
+    0U,	// ST_D_bo_r
+    0U,	// ST_H_abs
+    0U,	// ST_H_bo_bso
+    0U,	// ST_H_bo_c
+    0U,	// ST_H_bo_pos
+    0U,	// ST_H_bo_pre
+    0U,	// ST_H_bo_r
+    0U,	// ST_H_bol
+    0U,	// ST_H_sro
+    0U,	// ST_H_sro_v110
+    0U,	// ST_H_ssr
+    0U,	// ST_H_ssr_pos
+    0U,	// ST_H_ssr_pos_v110
+    0U,	// ST_H_ssr_v110
+    0U,	// ST_H_ssro
+    0U,	// ST_H_ssro_v110
+    0U,	// ST_Q_abs
+    0U,	// ST_Q_bo_bso
+    0U,	// ST_Q_bo_c
+    0U,	// ST_Q_bo_pos
+    0U,	// ST_Q_bo_pre
+    0U,	// ST_Q_bo_r
+    0U,	// ST_T
+    0U,	// ST_W_abs
+    0U,	// ST_W_bo_bso
+    0U,	// ST_W_bo_c
+    0U,	// ST_W_bo_pos
+    0U,	// ST_W_bo_pre
+    0U,	// ST_W_bo_r
+    0U,	// ST_W_bol
+    0U,	// ST_W_sc
+    0U,	// ST_W_sro
+    0U,	// ST_W_sro_v110
+    0U,	// ST_W_ssr
+    0U,	// ST_W_ssr_pos
+    0U,	// ST_W_ssr_pos_v110
+    0U,	// ST_W_ssr_v110
+    0U,	// ST_W_ssro
+    0U,	// ST_W_ssro_v110
+    0U,	// SUBC_rr
+    2U,	// SUBSC_A_rr
+    0U,	// SUBS_BU_rr
+    0U,	// SUBS_B_rr
+    0U,	// SUBS_HU_rr
+    0U,	// SUBS_H_rr
+    0U,	// SUBS_U_rr
+    0U,	// SUBS_rr
+    0U,	// SUBS_srr
+    0U,	// SUBX_rr
+    0U,	// SUB_A_rr
+    0U,	// SUB_A_sc
+    0U,	// SUB_A_sc_v110
+    0U,	// SUB_B_rr
+    0U,	// SUB_F_rrr
+    0U,	// SUB_H_rr
+    0U,	// SUB_rr
+    0U,	// SUB_srr
+    0U,	// SUB_srr_15a
+    0U,	// SUB_srr_a15
+    0U,	// SVLCX_sys
+    0U,	// SWAPMSK_W_bo_bso
+    0U,	// SWAPMSK_W_bo_c
+    0U,	// SWAPMSK_W_bo_i
+    0U,	// SWAPMSK_W_bo_pos
+    0U,	// SWAPMSK_W_bo_pre
+    0U,	// SWAPMSK_W_bo_r
+    0U,	// SWAP_A_abs
+    0U,	// SWAP_A_bo_bso
+    0U,	// SWAP_A_bo_c
+    0U,	// SWAP_A_bo_pos
+    0U,	// SWAP_A_bo_pre
+    0U,	// SWAP_A_bo_r
+    0U,	// SWAP_W_abs
+    0U,	// SWAP_W_bo_bso
+    0U,	// SWAP_W_bo_c
+    0U,	// SWAP_W_bo_i
+    0U,	// SWAP_W_bo_pos
+    0U,	// SWAP_W_bo_pre
+    0U,	// SWAP_W_bo_r
+    0U,	// SYSCALL_rc
+    0U,	// TLBDEMAP_rr
+    0U,	// TLBFLUSH_A_rr
+    0U,	// TLBFLUSH_B_rr
+    0U,	// TLBMAP_rr
+    0U,	// TLBPROBE_A_rr
+    0U,	// TLBPROBE_I_rr
+    0U,	// TRAPSV_sys
+    0U,	// TRAPV_sys
+    0U,	// UNPACK_rr_rr
+    0U,	// UNPACK_rr_rr_v110
+    0U,	// UPDFL_rr
+    0U,	// UTOF_rr
+    0U,	// WAIT_sys
+    0U,	// XNOR_T
+    0U,	// XNOR_rc
+    0U,	// XNOR_rr
+    0U,	// XOR_EQ_rc
+    0U,	// XOR_EQ_rr
+    0U,	// XOR_GE_U_rc
+    0U,	// XOR_GE_U_rr
+    0U,	// XOR_GE_rc
+    0U,	// XOR_GE_rr
+    0U,	// XOR_LT_U_rc
+    0U,	// XOR_LT_U_rr
+    0U,	// XOR_LT_rc
+    0U,	// XOR_LT_rr
+    0U,	// XOR_NE_rc
+    0U,	// XOR_NE_rr
+    0U,	// XOR_T
+    0U,	// XOR_rc
+    0U,	// XOR_rr
+    0U,	// XOR_srr
+  };
+
+  // Emit the opcode for the instruction.
+  uint64_t Bits = 0;
+  Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0;
+  Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32;
+  MnemonicBitsInfo MBI = {
+#ifndef CAPSTONE_DIET
+    AsmStrs+(Bits & 4095)-1,
+#else
+    NULL,
+#endif // CAPSTONE_DIET
+    Bits
+  };
+  return MBI;
+}
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+  SStream_concat0(O, "");
+  MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);
+
+  SStream_concat0(O, MnemonicInfo.first);
+
+  uint64_t Bits = MnemonicInfo.second;
+  assert(Bits != 0 && "Cannot print this instruction.");
+
+  // Fragment 0 encoded into 4 bits for 13 unique commands.
+  switch ((Bits >> 12) & 15) {
+  default: assert(0 && "Invalid command number.");
+  case 0:
+    // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
+    return;
+    break;
+  case 1:
+    // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
+    printOperand(MI, 0, O);
+    break;
+  case 2:
+    // AND_sc, AND_sc_v110, BISR_sc, BISR_sc_v110, LD_A_sc, LD_W_sc, MOV_sc, ...
+    printZExtImm_8(MI, 0, O);
+    break;
+  case 3:
+    // BISR_rc, BISR_rc_v161, SYSCALL_rc
+    printSExtImm_9(MI, 0, O);
+    return;
+    break;
+  case 4:
+    // CALLA_b, CALL_b, FCALLA_b, FCALL_b, JA_b, JLA_b, JL_b, J_b
+    printDisp24Imm(MI, 0, O);
+    return;
+    break;
+  case 5:
+    // CALL_sb, JNZ_sb, JNZ_sb_v110, JZ_sb, JZ_sb_v110, J_sb, J_sb_v110
+    printDisp8Imm(MI, 0, O);
+    return;
+    break;
+  case 6:
+    // CMPSWAP_W_bo_bso, CMPSWAP_W_bo_c, CMPSWAP_W_bo_pos, CMPSWAP_W_bo_pre, ...
+    printOperand(MI, 1, O);
+    break;
+  case 7:
+    // JEQ_sbc1, JEQ_sbc2, JEQ_sbc_v110, JNE_sbc1, JNE_sbc2, JNE_sbc_v110
+    printSExtImm_4(MI, 1, O);
+    SStream_concat0(O, ", ");
+    printDisp4Imm(MI, 0, O);
+    return;
+    break;
+  case 8:
+    // LDLCX_abs, LDUCX_abs, STLCX_abs, STUCX_abs, ST_T
+    printOff18Imm(MI, 0, O);
+    break;
+  case 9:
+    // LDMST_abs, ST_A_abs, ST_B_abs, ST_DA_abs, ST_D_abs, ST_H_abs, ST_Q_abs...
+    printOff18Imm(MI, 1, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 0, O);
+    return;
+    break;
+  case 10:
+    // LOOPU_brr
+    printDisp15Imm(MI, 0, O);
+    return;
+    break;
+  case 11:
+    // MTCR_rlc
+    printSExtImm_16(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    return;
+    break;
+  case 12:
+    // ST_A_ssro, ST_A_ssro_v110, ST_B_ssro, ST_B_ssro_v110, ST_H_ssro, ST_H_...
+    printZExtImm_4(MI, 1, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 0, O);
+    return;
+    break;
+  }
+
+
+  // Fragment 1 encoded into 4 bits for 16 unique commands.
+  switch ((Bits >> 16) & 15) {
+  default: assert(0 && "Invalid command number.");
+  case 0:
+    // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
+    SStream_concat0(O, ", ");
+    break;
+  case 1:
+    // ADD_src_a15, ADD_srr_a15, CADDN_src, CADDN_srr_v110, CADD_src, CADD_sr...
+    SStream_concat0(O, ", %d15, ");
+    break;
+  case 2:
+    // AND_sc, AND_sc_v110, BISR_sc, BISR_sc_v110, CALLI_rr, CALLI_rr_v110, D...
+    return;
+    break;
+  case 3:
+    // CACHEA_I_bo_bso, CACHEA_I_bo_pre, CACHEA_WI_bo_bso, CACHEA_WI_bo_pre, ...
+    SStream_concat1(O, ']');
+    break;
+  case 4:
+    // CACHEA_I_bo_c, CACHEA_WI_bo_c, CACHEA_W_bo_c, CMPSWAP_W_bo_c, LDMST_bo...
+    SStream_concat0(O, "+c]");
+    set_mem_access(MI, false);
+    break;
+  case 5:
+    // CACHEA_I_bo_pos, CACHEA_WI_bo_pos, CACHEA_W_bo_pos, CACHEI_I_bo_pos, C...
+    SStream_concat0(O, "+]");
+    set_mem_access(MI, false);
+    break;
+  case 6:
+    // CACHEA_I_bo_r, CACHEA_WI_bo_r, CACHEA_W_bo_r
+    SStream_concat0(O, "+r]");
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 7:
+    // CMPSWAP_W_bo_r, LDMST_bo_r, ST_A_bo_r, ST_B_bo_r, ST_DA_bo_r, ST_D_bo_...
+    SStream_concat0(O, "+r], ");
+    set_mem_access(MI, false);
+    break;
+  case 8:
+    // LD_A_bo_bso, LD_A_bo_c, LD_A_bo_pos, LD_A_bo_r, LD_A_bol, LD_A_slr, LD...
+    SStream_concat0(O, ", [");
+    set_mem_access(MI, true);
+    printOperand(MI, 1, O);
+    break;
+  case 9:
+    // LD_A_bo_pre, LD_BU_bo_pre, LD_B_bo_pre, LD_DA_bo_pre, LD_D_bo_pre, LD_...
+    SStream_concat0(O, ", [+");
+    set_mem_access(MI, true);
+    printOperand(MI, 1, O);
+    SStream_concat1(O, ']');
+    printSExtImm_10(MI, 2, O);
+    return;
+    break;
+  case 10:
+    // LD_A_slro, LD_A_slro_v110, LD_BU_slro, LD_BU_slro_v110, LD_B_slro_v110...
+    SStream_concat0(O, ", [%a15]");
+    set_mem_access(MI, true);
+    printZExtImm_4(MI, 1, O);
+    return;
+    break;
+  case 11:
+    // ST_A_sc
+    SStream_concat0(O, ", %a15");
+    return;
+    break;
+  case 12:
+    // ST_A_ssr, ST_A_ssr_v110, ST_B_ssr, ST_B_ssr_v110, ST_H_ssr, ST_H_ssr_v...
+    SStream_concat0(O, "], ");
+    set_mem_access(MI, false);
+    printOperand(MI, 1, O);
+    return;
+    break;
+  case 13:
+    // ST_A_ssr_pos, ST_A_ssr_pos_v110, ST_B_ssr_pos, ST_B_ssr_pos_v110, ST_H...
+    SStream_concat0(O, "+], ");
+    set_mem_access(MI, false);
+    printOperand(MI, 1, O);
+    return;
+    break;
+  case 14:
+    // ST_W_sc
+    SStream_concat0(O, ", %d15");
+    return;
+    break;
+  case 15:
+    // SWAPMSK_W_bo_i, SWAP_W_bo_i
+    SStream_concat0(O, "+i], ");
+    set_mem_access(MI, false);
+    printOperand(MI, 0, O);
+    return;
+    break;
+  }
+
+
+  // Fragment 2 encoded into 5 bits for 19 unique commands.
+  switch ((Bits >> 20) & 31) {
+  default: assert(0 && "Invalid command number.");
+  case 0:
+    // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
+    printOperand(MI, 1, O);
+    break;
+  case 1:
+    // ABSS_B_rr_v110, ABSS_H_rr, ABSS_rr, ADDSC_AT_rr, ADDSC_A_rr, CADDN_A_r...
+    printOperand(MI, 2, O);
+    break;
+  case 2:
+    // ADD_A_src, ADD_src, ADD_src_15a, ADD_src_a15, CADDN_src, CADD_src, CMO...
+    printSExtImm_4(MI, 1, O);
+    break;
+  case 3:
+    // ADD_F_rrr, CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRC...
+    printOperand(MI, 3, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 4:
+    // CACHEA_I_bo_bso, CACHEA_I_bo_c, CACHEA_I_bo_pos, CACHEA_I_bo_pre, CACH...
+    printSExtImm_10(MI, 1, O);
+    return;
+    break;
+  case 5:
+    // CMPSWAP_W_bo_bso, CMPSWAP_W_bo_c, CMPSWAP_W_bo_pos, CMPSWAP_W_bo_pre, ...
+    printSExtImm_10(MI, 2, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 6:
+    // CMPSWAP_W_bo_r, LDMST_bo_r
+    printOperand(MI, 0, O);
+    return;
+    break;
+  case 7:
+    // JEQ_sbr1, JEQ_sbr2, JEQ_sbr_v110, JGEZ_sbr, JGEZ_sbr_v110, JGTZ_sbr, J...
+    printDisp4Imm(MI, 1, O);
+    return;
+    break;
+  case 8:
+    // JGE_U_brc, JLT_U_brc, JLT_brc, JNED_brc, JNEI_brc, LD_A_sro, LD_A_sro_...
+    printZExtImm_4(MI, 1, O);
+    break;
+  case 9:
+    // JNZ_A_brr, JZ_A_brr, LOOP_brr
+    printDisp15Imm(MI, 1, O);
+    return;
+    break;
+  case 10:
+    // LD_A_abs, LD_BU_abs, LD_B_abs, LD_DA_abs, LD_D_abs, LD_HU_abs, LD_H_ab...
+    printOff18Imm(MI, 1, O);
+    return;
+    break;
+  case 11:
+    // LD_A_bo_bso, LD_A_bol, LD_A_slr, LD_A_slr_v110, LD_BU_bo_bso, LD_BU_bo...
+    SStream_concat1(O, ']');
+    break;
+  case 12:
+    // LD_A_bo_c, LD_BU_bo_c, LD_B_bo_c, LD_DA_bo_c, LD_D_bo_c, LD_HU_bo_c, L...
+    SStream_concat0(O, "+c]");
+    set_mem_access(MI, false);
+    printSExtImm_10(MI, 2, O);
+    return;
+    break;
+  case 13:
+    // LD_A_bo_pos, LD_A_slr_post, LD_A_slr_post_v110, LD_BU_bo_pos, LD_BU_sl...
+    SStream_concat0(O, "+]");
+    set_mem_access(MI, false);
+    break;
+  case 14:
+    // LD_A_bo_r, LD_BU_bo_r, LD_B_bo_r, LD_DA_bo_r, LD_D_bo_r, LD_HU_bo_r, L...
+    SStream_concat0(O, "+r]");
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 15:
+    // LOOP_sbr
+    printOExtImm_4(MI, 1, O);
+    return;
+    break;
+  case 16:
+    // MFCR_rlc, MOVH_A_rlc, MOVH_rlc, MOV_U_rlc, MOV_rlc_e
+    printZExtImm_16(MI, 1, O);
+    return;
+    break;
+  case 17:
+    // MOV_rlc
+    printSExtImm_16(MI, 1, O);
+    return;
+    break;
+  case 18:
+    // ST_A_bol, ST_B_bol, ST_H_bol, ST_W_bol
+    printSExtImm_16(MI, 2, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    return;
+    break;
+  }
+
+
+  // Fragment 3 encoded into 4 bits for 12 unique commands.
+  switch ((Bits >> 25) & 15) {
+  default: assert(0 && "Invalid command number.");
+  case 0:
+    // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
+    SStream_concat0(O, ", ");
+    break;
+  case 1:
+    // ABSS_B_rr_v110, ABSS_H_rr, ABSS_rr, ABS_B_rr, ABS_H_rr, ABS_rr, ADDS_s...
+    return;
+    break;
+  case 2:
+    // ADDSC_A_srrs
+    SStream_concat0(O, ", %d15, ");
+    printZExtImm_2(MI, 2, O);
+    return;
+    break;
+  case 3:
+    // ADD_F_rrr, CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRC...
+    printOperand(MI, 1, O);
+    break;
+  case 4:
+    // CMPSWAP_W_bo_bso, CMPSWAP_W_bo_c, CMPSWAP_W_bo_pos, CMPSWAP_W_bo_pre, ...
+    printOperand(MI, 0, O);
+    return;
+    break;
+  case 5:
+    // DVADJ_rrr, DVADJ_rrr_v110, DVSTEP_U_rrr, DVSTEP_U_rrrv110, DVSTEP_rrr,...
+    printOperand(MI, 2, O);
+    break;
+  case 6:
+    // LD_A_bo_bso, LD_A_bo_pos, LD_BU_bo_bso, LD_BU_bo_pos, LD_B_bo_bso, LD_...
+    printSExtImm_10(MI, 2, O);
+    return;
+    break;
+  case 7:
+    // LD_A_bol, LD_BU_bol, LD_B_bol, LD_HU_bol, LD_H_bol, LD_W_bol, LEA_bol
+    printSExtImm_16(MI, 2, O);
+    return;
+    break;
+  case 8:
+    // MULR_Q_rr1_2LL, MUL_Q_rr1_2LL
+    SStream_concat0(O, "l, ");
+    printOperand(MI, 2, O);
+    SStream_concat0(O, "l, ");
+    printZExtImm_2(MI, 3, O);
+    return;
+    break;
+  case 9:
+    // MULR_Q_rr1_2UU, MUL_Q_rr1_2UU
+    SStream_concat0(O, "u, ");
+    printOperand(MI, 2, O);
+    SStream_concat0(O, "u, ");
+    printZExtImm_2(MI, 3, O);
+    return;
+    break;
+  case 10:
+    // ST_A_sro, ST_A_sro_v110
+    SStream_concat0(O, ", %a15");
+    return;
+    break;
+  case 11:
+    // ST_B_sro, ST_B_sro_v110, ST_H_sro, ST_H_sro_v110, ST_W_sro, ST_W_sro_v...
+    SStream_concat0(O, ", %d15");
+    return;
+    break;
+  }
+
+
+  // Fragment 4 encoded into 4 bits for 14 unique commands.
+  switch ((Bits >> 29) & 15) {
+  default: assert(0 && "Invalid command number.");
+  case 0:
+    // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
+    printOperand(MI, 2, O);
+    break;
+  case 1:
+    // ABSDIF_rc, ADDC_rc, ADDS_U_rc, ADDS_rc, ADDX_rc, ADD_rc, ANDN_rc, AND_...
+    printSExtImm_9(MI, 2, O);
+    return;
+    break;
+  case 2:
+    // ADDIH_A_rlc, ADDIH_rlc
+    printZExtImm_16(MI, 2, O);
+    return;
+    break;
+  case 3:
+    // ADDI_rlc
+    printSExtImm_16(MI, 2, O);
+    return;
+    break;
+  case 4:
+    // ADDSC_AT_rr, ADDSC_A_rr, CADDN_A_rcr_v110, CADDN_rcr, CADD_A_rcr_v110,...
+    printOperand(MI, 1, O);
+    break;
+  case 5:
+    // ADDSC_A_srrs_v110
+    printZExtImm_2(MI, 2, O);
+    return;
+    break;
+  case 6:
+    // ADD_F_rrr, DVADJ_rrr, DVADJ_rrr_v110, DVSTEP_U_rrr, DVSTEP_U_rrrv110, ...
+    return;
+    break;
+  case 7:
+    // ANDN_T, AND_ANDN_T, AND_AND_T, AND_NOR_T, AND_OR_T, AND_T, INSN_T, INS...
+    printZExtImm_4(MI, 3, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O);
+    SStream_concat0(O, ", ");
+    printZExtImm_4(MI, 4, O);
+    return;
+    break;
+  case 8:
+    // CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRCN_rrr, CSUB...
+    SStream_concat0(O, ", ");
+    break;
+  case 9:
+    // EXTR_U_rrpw, EXTR_U_rrrw, EXTR_rrpw, EXTR_rrrw, IMASK_rcpw, IMASK_rrpw...
+    printOperand(MI, 3, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 10:
+    // JEQ_A_brr, JEQ_brc, JEQ_brr, JGE_U_brc, JGE_U_brr, JGE_brc, JGE_brr, J...
+    printDisp15Imm(MI, 2, O);
+    return;
+    break;
+  case 11:
+    // MADDRS_Q_rrr1_L_L, MADDR_Q_rrr1_L_L, MADDS_Q_rrr1_L_L, MADDS_Q_rrr1_e_...
+    SStream_concat0(O, "l, ");
+    printOperand(MI, 2, O);
+    SStream_concat0(O, "l, ");
+    printZExtImm_2(MI, 4, O);
+    return;
+    break;
+  case 12:
+    // MADDRS_Q_rrr1_U_U, MADDR_Q_rrr1_U_U, MADDS_Q_rrr1_U_U, MADDS_Q_rrr1_e_...
+    SStream_concat0(O, "u, ");
+    printOperand(MI, 2, O);
+    SStream_concat0(O, "u, ");
+    printZExtImm_2(MI, 4, O);
+    return;
+    break;
+  case 13:
+    // OR_rc
+    printZExtImm_9(MI, 2, O);
+    return;
+    break;
+  }
+
+
+  // Fragment 5 encoded into 4 bits for 10 unique commands.
+  switch ((Bits >> 33) & 15) {
+  default: assert(0 && "Invalid command number.");
+  case 0:
+    // ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
+    return;
+    break;
+  case 1:
+    // ADDSC_A_rr, ADDSC_A_rr_v110, CADDN_A_rcr_v110, CADDN_rcr, CADD_A_rcr_v...
+    SStream_concat0(O, ", ");
+    break;
+  case 2:
+    // CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRCN_rrr, CSUB...
+    printOperand(MI, 2, O);
+    break;
+  case 3:
+    // EXTR_U_rrpw, EXTR_U_rrrw, EXTR_rrpw, EXTR_rrrw, IMASK_rcpw, IMASK_rcrw...
+    printOperand(MI, 4, O);
+    return;
+    break;
+  case 4:
+    // MULMS_H_rr1_LL2e, MULM_H_rr1_LL2e, MULR_H_rr1_LL2e, MUL_H_rr1_LL2e
+    SStream_concat0(O, "ll, ");
+    printZExtImm_2(MI, 3, O);
+    return;
+    break;
+  case 5:
+    // MULMS_H_rr1_LU2e, MULM_H_rr1_LU2e, MULR_H_rr1_LU2e, MUL_H_rr1_LU2e
+    SStream_concat0(O, "lu, ");
+    printZExtImm_2(MI, 3, O);
+    return;
+    break;
+  case 6:
+    // MULMS_H_rr1_UL2e, MULM_H_rr1_UL2e, MULR_H_rr1_UL2e, MUL_H_rr1_UL2e
+    SStream_concat0(O, "ul, ");
+    printZExtImm_2(MI, 3, O);
+    return;
+    break;
+  case 7:
+    // MULMS_H_rr1_UU2e, MULM_H_rr1_UU2e, MULR_H_rr1_UU2e, MUL_H_rr1_UU2e
+    SStream_concat0(O, "uu, ");
+    printZExtImm_2(MI, 3, O);
+    return;
+    break;
+  case 8:
+    // MUL_Q_rr1_2_L, MUL_Q_rr1_2_Le
+    SStream_concat0(O, "l, ");
+    printZExtImm_2(MI, 3, O);
+    return;
+    break;
+  case 9:
+    // MUL_Q_rr1_2_U, MUL_Q_rr1_2_Ue
+    SStream_concat0(O, "u, ");
+    printZExtImm_2(MI, 3, O);
+    return;
+    break;
+  }
+
+
+  // Fragment 6 encoded into 4 bits for 12 unique commands.
+  switch ((Bits >> 37) & 15) {
+  default: assert(0 && "Invalid command number.");
+  case 0:
+    // ADDSC_A_rr, ADDSC_A_rr_v110, DIFSC_A_rr_v110, MULR_H_rr_v110, MULR_Q_r...
+    printZExtImm_2(MI, 3, O);
+    return;
+    break;
+  case 1:
+    // CADDN_A_rcr_v110, CADDN_rcr, CADD_A_rcr_v110, CADD_rcr, MADDMS_rcr_v11...
+    printSExtImm_9(MI, 3, O);
+    return;
+    break;
+  case 2:
+    // CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRCN_rrr, CSUB...
+    return;
+    break;
+  case 3:
+    // DEXTR_rrpw, DEXTR_rrrr, INSERT_rcpw, INSERT_rcrr, INSERT_rrpw, INSERT_...
+    printOperand(MI, 3, O);
+    break;
+  case 4:
+    // INSERT_rcrw, MADDRS_H_rrr1_v110, MADDRS_Q_rrr1_v110, MADDR_H_rrr1_v110...
+    SStream_concat0(O, ", ");
+    break;
+  case 5:
+    // MADDMS_H_rrr1_LL, MADDM_H_rrr1_LL, MADDRS_H_rrr1_LL, MADDR_H_rrr1_LL, ...
+    SStream_concat0(O, "ll, ");
+    printZExtImm_2(MI, 4, O);
+    return;
+    break;
+  case 6:
+    // MADDMS_H_rrr1_LU, MADDM_H_rrr1_LU, MADDRS_H_rrr1_LU, MADDR_H_rrr1_LU, ...
+    SStream_concat0(O, "lu, ");
+    printZExtImm_2(MI, 4, O);
+    return;
+    break;
+  case 7:
+    // MADDMS_H_rrr1_UL, MADDM_H_rrr1_UL, MADDRS_H_rrr1_UL, MADDRS_H_rrr1_UL_...
+    SStream_concat0(O, "ul, ");
+    printZExtImm_2(MI, 4, O);
+    return;
+    break;
+  case 8:
+    // MADDMS_H_rrr1_UU, MADDM_H_rrr1_UU, MADDRS_H_rrr1_UU, MADDR_H_rrr1_UU, ...
+    SStream_concat0(O, "uu, ");
+    printZExtImm_2(MI, 4, O);
+    return;
+    break;
+  case 9:
+    // MADDMS_U_rcr_v110, MADDM_U_rcr_v110, MADD_U_rcr, MSUB_U_rcr
+    printZExtImm_9(MI, 3, O);
+    return;
+    break;
+  case 10:
+    // MADDS_Q_rrr1_L, MADDS_Q_rrr1_e_L, MADD_Q_rrr1_L, MADD_Q_rrr1_e_L, MSUB...
+    SStream_concat0(O, "l, ");
+    printZExtImm_2(MI, 4, O);
+    return;
+    break;
+  case 11:
+    // MADDS_Q_rrr1_U, MADDS_Q_rrr1_e_U, MADD_Q_rrr1_U, MADD_Q_rrr1_e_U, MSUB...
+    SStream_concat0(O, "u, ");
+    printZExtImm_2(MI, 4, O);
+    return;
+    break;
+  }
+
+
+  // Fragment 7 encoded into 2 bits for 4 unique commands.
+  switch ((Bits >> 41) & 3) {
+  default: assert(0 && "Invalid command number.");
+  case 0:
+    // DEXTR_rrpw, DEXTR_rrrr, INSERT_rcrr, INSERT_rrrr
+    return;
+    break;
+  case 1:
+    // INSERT_rcpw, INSERT_rrpw, INSERT_rrrw
+    SStream_concat0(O, ", ");
+    printOperand(MI, 4, O);
+    return;
+    break;
+  case 2:
+    // INSERT_rcrw
+    printOperand(MI, 4, O);
+    return;
+    break;
+  case 3:
+    // MADDRS_H_rrr1_v110, MADDRS_Q_rrr1_v110, MADDR_H_rrr1_v110, MADDR_Q_rrr...
+    printZExtImm_2(MI, 4, O);
+    return;
+    break;
+  }
+
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description.  This returns the assembler name
+/// for the specified register.
+const char *getRegisterName(unsigned RegNo) {
+#ifndef CAPSTONE_DIET
+  assert(RegNo && RegNo < 61 && "Invalid register number!");
+
+  static const char AsmStrs[] = {
+  /* 0 */ "d10\0"
+  /* 4 */ "e10\0"
+  /* 8 */ "p10\0"
+  /* 12 */ "a0\0"
+  /* 15 */ "d0\0"
+  /* 18 */ "e0\0"
+  /* 21 */ "p0\0"
+  /* 24 */ "A10_A11\0"
+  /* 32 */ "a11\0"
+  /* 36 */ "d11\0"
+  /* 40 */ "A0_A1\0"
+  /* 46 */ "a1\0"
+  /* 49 */ "d1\0"
+  /* 52 */ "a12\0"
+  /* 56 */ "d12\0"
+  /* 60 */ "e12\0"
+  /* 64 */ "p12\0"
+  /* 68 */ "a2\0"
+  /* 71 */ "d2\0"
+  /* 74 */ "e2\0"
+  /* 77 */ "p2\0"
+  /* 80 */ "A12_A13\0"
+  /* 88 */ "a13\0"
+  /* 92 */ "d13\0"
+  /* 96 */ "A2_A3\0"
+  /* 102 */ "a3\0"
+  /* 105 */ "d3\0"
+  /* 108 */ "a14\0"
+  /* 112 */ "d14\0"
+  /* 116 */ "e14\0"
+  /* 120 */ "p14\0"
+  /* 124 */ "a4\0"
+  /* 127 */ "d4\0"
+  /* 130 */ "e4\0"
+  /* 133 */ "p4\0"
+  /* 136 */ "A14_A15\0"
+  /* 144 */ "a15\0"
+  /* 148 */ "d15\0"
+  /* 152 */ "A4_A5\0"
+  /* 158 */ "a5\0"
+  /* 161 */ "d5\0"
+  /* 164 */ "a6\0"
+  /* 167 */ "d6\0"
+  /* 170 */ "e6\0"
+  /* 173 */ "p6\0"
+  /* 176 */ "A6_A7\0"
+  /* 182 */ "a7\0"
+  /* 185 */ "d7\0"
+  /* 188 */ "a8\0"
+  /* 191 */ "d8\0"
+  /* 194 */ "e8\0"
+  /* 197 */ "p8\0"
+  /* 200 */ "A8_A9\0"
+  /* 206 */ "a9\0"
+  /* 209 */ "d9\0"
+  /* 212 */ "pc\0"
+  /* 215 */ "pcxi\0"
+  /* 220 */ "sp\0"
+  /* 223 */ "psw\0"
+  /* 227 */ "fcx\0"
+};
+  static const uint8_t RegAsmOffset[] = {
+    227, 212, 215, 223, 12, 46, 68, 102, 124, 158, 164, 182, 188, 206, 
+    220, 32, 52, 88, 108, 144, 15, 49, 71, 105, 127, 161, 167, 185, 
+    191, 209, 0, 36, 56, 92, 112, 148, 18, 74, 130, 170, 194, 4, 
+    60, 116, 21, 77, 133, 173, 197, 8, 64, 120, 40, 96, 152, 176, 
+    200, 24, 80, 136, 
+  };
+
+  assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
+          "Invalid alt name index for register!");
+  return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+  return NULL;
+#endif // CAPSTONE_DIET
+}
+#ifdef PRINT_ALIAS_INSTR
+#undef PRINT_ALIAS_INSTR
+
+bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
+#ifndef CAPSTONE_DIET
+  return false;
+#endif // CAPSTONE_DIET
+}
+
+#endif // PRINT_ALIAS_INSTR
diff --git a/arch/TriCore/TriCoreGenCSFeatureName.inc b/arch/TriCore/TriCoreGenCSFeatureName.inc
new file mode 100644
index 0000000000..01e1297ae2
--- /dev/null
+++ b/arch/TriCore/TriCoreGenCSFeatureName.inc
@@ -0,0 +1,22 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ TRICORE_FEATURE_HasV110, "HasV110" },
+{ TRICORE_FEATURE_HasV120_UP, "HasV120_UP" },
+{ TRICORE_FEATURE_HasV130_UP, "HasV130_UP" },
+{ TRICORE_FEATURE_HasV161, "HasV161" },
+{ TRICORE_FEATURE_HasV160_UP, "HasV160_UP" },
+{ TRICORE_FEATURE_HasV131_UP, "HasV131_UP" },
+{ TRICORE_FEATURE_HasV161_UP, "HasV161_UP" },
+{ TRICORE_FEATURE_HasV162, "HasV162" },
+{ TRICORE_FEATURE_HasV162_UP, "HasV162_UP" },
diff --git a/arch/TriCore/TriCoreGenCSMappingInsn.inc b/arch/TriCore/TriCoreGenCSMappingInsn.inc
new file mode 100644
index 0000000000..d0815aa0f2
--- /dev/null
+++ b/arch/TriCore/TriCoreGenCSMappingInsn.inc
@@ -0,0 +1,7663 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{
+  TRICORE_PHI /* 0 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INLINEASM /* 1 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INLINEASM_BR /* 2 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CFI_INSTRUCTION /* 3 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EH_LABEL /* 4 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_GC_LABEL /* 5 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ANNOTATION_LABEL /* 6 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_KILL /* 7 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EXTRACT_SUBREG /* 8 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INSERT_SUBREG /* 9 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_IMPLICIT_DEF /* 10 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBREG_TO_REG /* 11 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_COPY_TO_REGCLASS /* 12 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DBG_VALUE /* 13 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DBG_VALUE_LIST /* 14 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DBG_INSTR_REF /* 15 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DBG_PHI /* 16 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DBG_LABEL /* 17 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_REG_SEQUENCE /* 18 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_COPY /* 19 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_BUNDLE /* 20 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LIFETIME_START /* 21 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LIFETIME_END /* 22 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PSEUDO_PROBE /* 23 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ARITH_FENCE /* 24 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_STACKMAP /* 25 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FENTRY_CALL /* 26 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PATCHPOINT /* 27 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LOAD_STACK_GUARD /* 28 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PREALLOCATED_SETUP /* 29 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PREALLOCATED_ARG /* 30 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_STATEPOINT /* 31 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LOCAL_ESCAPE /* 32 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FAULTING_OP /* 33 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PATCHABLE_OP /* 34 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PATCHABLE_FUNCTION_ENTER /* 35 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PATCHABLE_RET /* 36 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PATCHABLE_FUNCTION_EXIT /* 37 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PATCHABLE_TAIL_CALL /* 38 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PATCHABLE_EVENT_CALL /* 39 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PATCHABLE_TYPED_EVENT_CALL /* 40 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ICALL_BRANCH_FUNNEL /* 41 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MEMBARRIER /* 42 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ASSERT_SEXT /* 43 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ASSERT_ZEXT /* 44 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ASSERT_ALIGN /* 45 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ADD /* 46 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SUB /* 47 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_MUL /* 48 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SDIV /* 49 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UDIV /* 50 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SREM /* 51 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UREM /* 52 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SDIVREM /* 53 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UDIVREM /* 54 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_AND /* 55 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_OR /* 56 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_XOR /* 57 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_IMPLICIT_DEF /* 58 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_PHI /* 59 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FRAME_INDEX /* 60 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_GLOBAL_VALUE /* 61 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_EXTRACT /* 62 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UNMERGE_VALUES /* 63 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INSERT /* 64 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_MERGE_VALUES /* 65 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BUILD_VECTOR /* 66 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BUILD_VECTOR_TRUNC /* 67 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_CONCAT_VECTORS /* 68 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_PTRTOINT /* 69 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INTTOPTR /* 70 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BITCAST /* 71 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FREEZE /* 72 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INTRINSIC_FPTRUNC_ROUND /* 73 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INTRINSIC_TRUNC /* 74 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INTRINSIC_ROUND /* 75 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INTRINSIC_LRINT /* 76 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INTRINSIC_ROUNDEVEN /* 77 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_READCYCLECOUNTER /* 78 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_LOAD /* 79 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SEXTLOAD /* 80 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ZEXTLOAD /* 81 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INDEXED_LOAD /* 82 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INDEXED_SEXTLOAD /* 83 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INDEXED_ZEXTLOAD /* 84 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_STORE /* 85 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INDEXED_STORE /* 86 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMIC_CMPXCHG_WITH_SUCCESS /* 87 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMIC_CMPXCHG /* 88 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_XCHG /* 89 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_ADD /* 90 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_SUB /* 91 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_AND /* 92 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_NAND /* 93 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_OR /* 94 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_XOR /* 95 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_MAX /* 96 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_MIN /* 97 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_UMAX /* 98 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_UMIN /* 99 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_FADD /* 100 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_FSUB /* 101 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_FMAX /* 102 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_FMIN /* 103 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_UINC_WRAP /* 104 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ATOMICRMW_UDEC_WRAP /* 105 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FENCE /* 106 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BRCOND /* 107 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BRINDIRECT /* 108 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INVOKE_REGION_START /* 109 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INTRINSIC /* 110 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INTRINSIC_W_SIDE_EFFECTS /* 111 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ANYEXT /* 112 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_TRUNC /* 113 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_CONSTANT /* 114 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FCONSTANT /* 115 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VASTART /* 116 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VAARG /* 117 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SEXT /* 118 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SEXT_INREG /* 119 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ZEXT /* 120 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SHL /* 121 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_LSHR /* 122 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ASHR /* 123 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FSHL /* 124 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FSHR /* 125 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ROTR /* 126 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ROTL /* 127 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ICMP /* 128 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FCMP /* 129 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SELECT /* 130 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UADDO /* 131 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UADDE /* 132 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_USUBO /* 133 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_USUBE /* 134 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SADDO /* 135 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SADDE /* 136 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SSUBO /* 137 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SSUBE /* 138 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UMULO /* 139 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SMULO /* 140 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UMULH /* 141 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SMULH /* 142 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UADDSAT /* 143 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SADDSAT /* 144 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_USUBSAT /* 145 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SSUBSAT /* 146 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_USHLSAT /* 147 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SSHLSAT /* 148 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SMULFIX /* 149 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UMULFIX /* 150 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SMULFIXSAT /* 151 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UMULFIXSAT /* 152 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SDIVFIX /* 153 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UDIVFIX /* 154 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SDIVFIXSAT /* 155 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UDIVFIXSAT /* 156 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FADD /* 157 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FSUB /* 158 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FMUL /* 159 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FMA /* 160 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FMAD /* 161 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FDIV /* 162 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FREM /* 163 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FPOW /* 164 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FPOWI /* 165 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FEXP /* 166 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FEXP2 /* 167 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FLOG /* 168 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FLOG2 /* 169 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FLOG10 /* 170 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FNEG /* 171 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FPEXT /* 172 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FPTRUNC /* 173 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FPTOSI /* 174 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FPTOUI /* 175 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SITOFP /* 176 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UITOFP /* 177 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FABS /* 178 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FCOPYSIGN /* 179 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_IS_FPCLASS /* 180 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FCANONICALIZE /* 181 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FMINNUM /* 182 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FMAXNUM /* 183 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FMINNUM_IEEE /* 184 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FMAXNUM_IEEE /* 185 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FMINIMUM /* 186 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FMAXIMUM /* 187 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_PTR_ADD /* 188 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_PTRMASK /* 189 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SMIN /* 190 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SMAX /* 191 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UMIN /* 192 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UMAX /* 193 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ABS /* 194 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_LROUND /* 195 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_LLROUND /* 196 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BR /* 197 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BRJT /* 198 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_INSERT_VECTOR_ELT /* 199 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_EXTRACT_VECTOR_ELT /* 200 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SHUFFLE_VECTOR /* 201 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_CTTZ /* 202 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_CTTZ_ZERO_UNDEF /* 203 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_CTLZ /* 204 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_CTLZ_ZERO_UNDEF /* 205 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_CTPOP /* 206 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BSWAP /* 207 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BITREVERSE /* 208 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FCEIL /* 209 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FCOS /* 210 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FSIN /* 211 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FSQRT /* 212 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FFLOOR /* 213 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FRINT /* 214 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_FNEARBYINT /* 215 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_ADDRSPACE_CAST /* 216 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BLOCK_ADDR /* 217 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_JUMP_TABLE /* 218 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_DYN_STACKALLOC /* 219 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_STRICT_FADD /* 220 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_STRICT_FSUB /* 221 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_STRICT_FMUL /* 222 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_STRICT_FDIV /* 223 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_STRICT_FREM /* 224 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_STRICT_FMA /* 225 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_STRICT_FSQRT /* 226 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_READ_REGISTER /* 227 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_WRITE_REGISTER /* 228 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_MEMCPY /* 229 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_MEMCPY_INLINE /* 230 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_MEMMOVE /* 231 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_MEMSET /* 232 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_BZERO /* 233 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_SEQ_FADD /* 234 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_SEQ_FMUL /* 235 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_FADD /* 236 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_FMUL /* 237 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_FMAX /* 238 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_FMIN /* 239 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_ADD /* 240 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_MUL /* 241 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_AND /* 242 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_OR /* 243 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_XOR /* 244 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_SMAX /* 245 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_SMIN /* 246 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_UMAX /* 247 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_VECREDUCE_UMIN /* 248 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_SBFX /* 249 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_G_UBFX /* 250 */, TRICORE_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSDIFS_B_rr_v110 /* 251 */, TRICORE_INS_ABSDIFS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSDIFS_H_rr /* 252 */, TRICORE_INS_ABSDIFS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSDIFS_rc /* 253 */, TRICORE_INS_ABSDIFS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSDIFS_rr /* 254 */, TRICORE_INS_ABSDIFS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSDIF_B_rr /* 255 */, TRICORE_INS_ABSDIF_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSDIF_H_rr /* 256 */, TRICORE_INS_ABSDIF_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSDIF_rc /* 257 */, TRICORE_INS_ABSDIF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSDIF_rr /* 258 */, TRICORE_INS_ABSDIF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSS_B_rr_v110 /* 259 */, TRICORE_INS_ABSS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSS_H_rr /* 260 */, TRICORE_INS_ABSS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABSS_rr /* 261 */, TRICORE_INS_ABSS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABS_B_rr /* 262 */, TRICORE_INS_ABS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABS_H_rr /* 263 */, TRICORE_INS_ABS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ABS_rr /* 264 */, TRICORE_INS_ABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { TRICORE_REG_PSW, 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDC_rc /* 265 */, TRICORE_INS_ADDC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDC_rr /* 266 */, TRICORE_INS_ADDC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDIH_A_rlc /* 267 */, TRICORE_INS_ADDIH_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDIH_rlc /* 268 */, TRICORE_INS_ADDIH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDI_rlc /* 269 */, TRICORE_INS_ADDI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDSC_AT_rr /* 270 */, TRICORE_INS_ADDSC_AT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDSC_AT_rr_v110 /* 271 */, TRICORE_INS_ADDSC_AT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDSC_A_rr /* 272 */, TRICORE_INS_ADDSC_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDSC_A_rr_v110 /* 273 */, TRICORE_INS_ADDSC_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDSC_A_srrs /* 274 */, TRICORE_INS_ADDSC_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDSC_A_srrs_v110 /* 275 */, TRICORE_INS_ADDSC_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDS_BU_rr_v110 /* 276 */, TRICORE_INS_ADDS_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDS_B_rr /* 277 */, TRICORE_INS_ADDS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDS_H /* 278 */, TRICORE_INS_ADDS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDS_HU /* 279 */, TRICORE_INS_ADDS_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDS_U /* 280 */, TRICORE_INS_ADDS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDS_U_rc /* 281 */, TRICORE_INS_ADDS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDS_rc /* 282 */, TRICORE_INS_ADDS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDS_rr /* 283 */, TRICORE_INS_ADDS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDS_srr /* 284 */, TRICORE_INS_ADDS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDX_rc /* 285 */, TRICORE_INS_ADDX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADDX_rr /* 286 */, TRICORE_INS_ADDX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_A_rr /* 287 */, TRICORE_INS_ADD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_A_src /* 288 */, TRICORE_INS_ADD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_A_srr /* 289 */, TRICORE_INS_ADD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_B_rr /* 290 */, TRICORE_INS_ADD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_F_rrr /* 291 */, TRICORE_INS_ADD_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_H_rr /* 292 */, TRICORE_INS_ADD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_rc /* 293 */, TRICORE_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_rr /* 294 */, TRICORE_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_src /* 295 */, TRICORE_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_src_15a /* 296 */, TRICORE_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_src_a15 /* 297 */, TRICORE_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_srr /* 298 */, TRICORE_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_srr_15a /* 299 */, TRICORE_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ADD_srr_a15 /* 300 */, TRICORE_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ANDN_T /* 301 */, TRICORE_INS_ANDN_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ANDN_rc /* 302 */, TRICORE_INS_ANDN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ANDN_rr /* 303 */, TRICORE_INS_ANDN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_ANDN_T /* 304 */, TRICORE_INS_AND_ANDN_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_AND_T /* 305 */, TRICORE_INS_AND_AND_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_EQ_rc /* 306 */, TRICORE_INS_AND_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_EQ_rr /* 307 */, TRICORE_INS_AND_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_GE_U_rc /* 308 */, TRICORE_INS_AND_GE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_GE_U_rr /* 309 */, TRICORE_INS_AND_GE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_GE_rc /* 310 */, TRICORE_INS_AND_GE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_GE_rr /* 311 */, TRICORE_INS_AND_GE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_LT_U_rc /* 312 */, TRICORE_INS_AND_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_LT_U_rr /* 313 */, TRICORE_INS_AND_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_LT_rc /* 314 */, TRICORE_INS_AND_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_LT_rr /* 315 */, TRICORE_INS_AND_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_NE_rc /* 316 */, TRICORE_INS_AND_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_NE_rr /* 317 */, TRICORE_INS_AND_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_NOR_T /* 318 */, TRICORE_INS_AND_NOR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_OR_T /* 319 */, TRICORE_INS_AND_OR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_T /* 320 */, TRICORE_INS_AND_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_rc /* 321 */, TRICORE_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_rr /* 322 */, TRICORE_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_sc /* 323 */, TRICORE_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_sc_v110 /* 324 */, TRICORE_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_srr /* 325 */, TRICORE_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_AND_srr_v110 /* 326 */, TRICORE_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_BISR_rc /* 327 */, TRICORE_INS_BISR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_BISR_rc_v161 /* 328 */, TRICORE_INS_BISR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_BISR_sc /* 329 */, TRICORE_INS_BISR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_BISR_sc_v110 /* 330 */, TRICORE_INS_BISR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_BMERGAE_rr_v110 /* 331 */, TRICORE_INS_BMERGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_BMERGE_rr /* 332 */, TRICORE_INS_BMERGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_BSPLIT_rr /* 333 */, TRICORE_INS_BSPLIT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_BSPLIT_rr_v110 /* 334 */, TRICORE_INS_BSPLIT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_I_bo_bso /* 335 */, TRICORE_INS_CACHEA_I,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_I_bo_c /* 336 */, TRICORE_INS_CACHEA_I,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_I_bo_pos /* 337 */, TRICORE_INS_CACHEA_I,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_I_bo_pre /* 338 */, TRICORE_INS_CACHEA_I,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_I_bo_r /* 339 */, TRICORE_INS_CACHEA_I,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_WI_bo_bso /* 340 */, TRICORE_INS_CACHEA_WI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_WI_bo_c /* 341 */, TRICORE_INS_CACHEA_WI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_WI_bo_pos /* 342 */, TRICORE_INS_CACHEA_WI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_WI_bo_pre /* 343 */, TRICORE_INS_CACHEA_WI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_WI_bo_r /* 344 */, TRICORE_INS_CACHEA_WI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_W_bo_bso /* 345 */, TRICORE_INS_CACHEA_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_W_bo_c /* 346 */, TRICORE_INS_CACHEA_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_W_bo_pos /* 347 */, TRICORE_INS_CACHEA_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_W_bo_pre /* 348 */, TRICORE_INS_CACHEA_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEA_W_bo_r /* 349 */, TRICORE_INS_CACHEA_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEI_I_bo_bso /* 350 */, TRICORE_INS_CACHEI_I,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEI_I_bo_pos /* 351 */, TRICORE_INS_CACHEI_I,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEI_I_bo_pre /* 352 */, TRICORE_INS_CACHEI_I,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEI_WI_bo_bso /* 353 */, TRICORE_INS_CACHEI_WI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV131_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEI_WI_bo_pos /* 354 */, TRICORE_INS_CACHEI_WI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV131_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEI_WI_bo_pre /* 355 */, TRICORE_INS_CACHEI_WI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV131_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEI_W_bo_bso /* 356 */, TRICORE_INS_CACHEI_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV131_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEI_W_bo_pos /* 357 */, TRICORE_INS_CACHEI_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV131_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CACHEI_W_bo_pre /* 358 */, TRICORE_INS_CACHEI_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV131_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADDN_A_rcr_v110 /* 359 */, TRICORE_INS_CADDN_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADDN_A_rrr_v110 /* 360 */, TRICORE_INS_CADDN_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADDN_rcr /* 361 */, TRICORE_INS_CADDN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADDN_rrr /* 362 */, TRICORE_INS_CADDN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADDN_src /* 363 */, TRICORE_INS_CADDN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADDN_srr_v110 /* 364 */, TRICORE_INS_CADDN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADD_A_rcr_v110 /* 365 */, TRICORE_INS_CADD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADD_A_rrr_v110 /* 366 */, TRICORE_INS_CADD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADD_rcr /* 367 */, TRICORE_INS_CADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADD_rrr /* 368 */, TRICORE_INS_CADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADD_src /* 369 */, TRICORE_INS_CADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CADD_srr_v110 /* 370 */, TRICORE_INS_CADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CALLA_b /* 371 */, TRICORE_INS_CALLA,
+  #ifndef CAPSTONE_DIET
+    { TRICORE_REG_A10, 0 }, { TRICORE_REG_A11, 0 }, { TRICORE_GRP_CALL, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CALLI_rr /* 372 */, TRICORE_INS_CALLI,
+  #ifndef CAPSTONE_DIET
+    { TRICORE_REG_A10, 0 }, { TRICORE_REG_A11, 0 }, { TRICORE_GRP_CALL, TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CALLI_rr_v110 /* 373 */, TRICORE_INS_CALLI,
+  #ifndef CAPSTONE_DIET
+    { TRICORE_REG_A10, 0 }, { TRICORE_REG_A11, 0 }, { TRICORE_GRP_CALL, TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CALL_b /* 374 */, TRICORE_INS_CALL,
+  #ifndef CAPSTONE_DIET
+    { TRICORE_REG_A10, 0 }, { TRICORE_REG_A11, 0 }, { TRICORE_GRP_CALL, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CALL_sb /* 375 */, TRICORE_INS_CALL,
+  #ifndef CAPSTONE_DIET
+    { TRICORE_REG_A10, 0 }, { TRICORE_REG_A11, 0 }, { TRICORE_GRP_CALL, TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CLO_B_rr_v110 /* 376 */, TRICORE_INS_CLO_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CLO_H_rr /* 377 */, TRICORE_INS_CLO_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CLO_rr /* 378 */, TRICORE_INS_CLO,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CLS_B_rr_v110 /* 379 */, TRICORE_INS_CLS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CLS_H_rr /* 380 */, TRICORE_INS_CLS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CLS_rr /* 381 */, TRICORE_INS_CLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CLZ_B_rr_v110 /* 382 */, TRICORE_INS_CLZ_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CLZ_H_rr /* 383 */, TRICORE_INS_CLZ_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CLZ_rr /* 384 */, TRICORE_INS_CLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CMOVN_src /* 385 */, TRICORE_INS_CMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CMOVN_srr /* 386 */, TRICORE_INS_CMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CMOV_src /* 387 */, TRICORE_INS_CMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CMOV_srr /* 388 */, TRICORE_INS_CMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CMPSWAP_W_bo_bso /* 389 */, TRICORE_INS_CMPSWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CMPSWAP_W_bo_c /* 390 */, TRICORE_INS_CMPSWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CMPSWAP_W_bo_pos /* 391 */, TRICORE_INS_CMPSWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CMPSWAP_W_bo_pre /* 392 */, TRICORE_INS_CMPSWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CMPSWAP_W_bo_r /* 393 */, TRICORE_INS_CMPSWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CMP_F_rr /* 394 */, TRICORE_INS_CMP_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CRC32B_W_rr /* 395 */, TRICORE_INS_CRC32B_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV162, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CRC32L_W_rr /* 396 */, TRICORE_INS_CRC32L_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV162, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CRC32_B_rr /* 397 */, TRICORE_INS_CRC32_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV162, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CRCN_rrr /* 398 */, TRICORE_INS_CRCN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV162, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CSUBN_A__rrr_v110 /* 399 */, TRICORE_INS_CSUBN_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CSUBN_rrr /* 400 */, TRICORE_INS_CSUBN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CSUB_A__rrr_v110 /* 401 */, TRICORE_INS_CSUB_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_CSUB_rrr /* 402 */, TRICORE_INS_CSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DEBUG_sr /* 403 */, TRICORE_INS_DEBUG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DEBUG_sys /* 404 */, TRICORE_INS_DEBUG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DEXTR_rrpw /* 405 */, TRICORE_INS_DEXTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DEXTR_rrrr /* 406 */, TRICORE_INS_DEXTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DIFSC_A_rr_v110 /* 407 */, TRICORE_INS_DIFSC_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DISABLE_sys /* 408 */, TRICORE_INS_DISABLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DISABLE_sys_1 /* 409 */, TRICORE_INS_DISABLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DIV_F_rr /* 410 */, TRICORE_INS_DIV_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DIV_U_rr /* 411 */, TRICORE_INS_DIV_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DIV_rr /* 412 */, TRICORE_INS_DIV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DSYNC_sys /* 413 */, TRICORE_INS_DSYNC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVADJ_rrr /* 414 */, TRICORE_INS_DVADJ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVADJ_rrr_v110 /* 415 */, TRICORE_INS_DVADJ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVADJ_srr_v110 /* 416 */, TRICORE_INS_DVADJ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_BU_rr /* 417 */, TRICORE_INS_DVINIT_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_BU_rr_v110 /* 418 */, TRICORE_INS_DVINIT_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_B_rr /* 419 */, TRICORE_INS_DVINIT_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_B_rr_v110 /* 420 */, TRICORE_INS_DVINIT_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_HU_rr /* 421 */, TRICORE_INS_DVINIT_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_HU_rr_v110 /* 422 */, TRICORE_INS_DVINIT_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_H_rr /* 423 */, TRICORE_INS_DVINIT_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_H_rr_v110 /* 424 */, TRICORE_INS_DVINIT_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_U_rr /* 425 */, TRICORE_INS_DVINIT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_U_rr_v110 /* 426 */, TRICORE_INS_DVINIT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_rr /* 427 */, TRICORE_INS_DVINIT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVINIT_rr_v110 /* 428 */, TRICORE_INS_DVINIT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVSTEP_U_rrr /* 429 */, TRICORE_INS_DVSTEP_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVSTEP_U_rrrv110 /* 430 */, TRICORE_INS_DVSTEP_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVSTEP_Uv110 /* 431 */, TRICORE_INS_DVSTEP_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVSTEP_rrr /* 432 */, TRICORE_INS_DVSTEP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVSTEP_rrrv110 /* 433 */, TRICORE_INS_DVSTEP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_DVSTEPv110 /* 434 */, TRICORE_INS_DVSTEP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ENABLE_sys /* 435 */, TRICORE_INS_ENABLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQANY_B_rc /* 436 */, TRICORE_INS_EQANY_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQANY_B_rr /* 437 */, TRICORE_INS_EQANY_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQANY_H_rc /* 438 */, TRICORE_INS_EQANY_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQANY_H_rr /* 439 */, TRICORE_INS_EQANY_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQZ_A_rr /* 440 */, TRICORE_INS_EQZ_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQ_A_rr /* 441 */, TRICORE_INS_EQ_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQ_B_rr /* 442 */, TRICORE_INS_EQ_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQ_H_rr /* 443 */, TRICORE_INS_EQ_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQ_W_rr /* 444 */, TRICORE_INS_EQ_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQ_rc /* 445 */, TRICORE_INS_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQ_rr /* 446 */, TRICORE_INS_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQ_src /* 447 */, TRICORE_INS_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EQ_srr /* 448 */, TRICORE_INS_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EXTR_U_rrpw /* 449 */, TRICORE_INS_EXTR_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EXTR_U_rrrr /* 450 */, TRICORE_INS_EXTR_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EXTR_U_rrrw /* 451 */, TRICORE_INS_EXTR_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EXTR_rrpw /* 452 */, TRICORE_INS_EXTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EXTR_rrrr /* 453 */, TRICORE_INS_EXTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_EXTR_rrrw /* 454 */, TRICORE_INS_EXTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FCALLA_b /* 455 */, TRICORE_INS_FCALLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FCALLA_i /* 456 */, TRICORE_INS_FCALLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FCALL_b /* 457 */, TRICORE_INS_FCALL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FRET_sr /* 458 */, TRICORE_INS_FRET,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FRET_sys /* 459 */, TRICORE_INS_FRET,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FTOHP_rr /* 460 */, TRICORE_INS_FTOHP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV162_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FTOIZ_rr /* 461 */, TRICORE_INS_FTOIZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV131_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FTOI_rr /* 462 */, TRICORE_INS_FTOI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FTOQ31Z_rr /* 463 */, TRICORE_INS_FTOQ31Z,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV131_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FTOQ31_rr /* 464 */, TRICORE_INS_FTOQ31,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FTOUZ_rr /* 465 */, TRICORE_INS_FTOUZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV131_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_FTOU_rr /* 466 */, TRICORE_INS_FTOU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_GE_A_rr /* 467 */, TRICORE_INS_GE_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_GE_U_rc /* 468 */, TRICORE_INS_GE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_GE_U_rr /* 469 */, TRICORE_INS_GE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_GE_rc /* 470 */, TRICORE_INS_GE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_GE_rr /* 471 */, TRICORE_INS_GE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_HPTOF_rr /* 472 */, TRICORE_INS_HPTOF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV162_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_IMASK_rcpw /* 473 */, TRICORE_INS_IMASK,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_IMASK_rcrw /* 474 */, TRICORE_INS_IMASK,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_IMASK_rrpw /* 475 */, TRICORE_INS_IMASK,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_IMASK_rrrw /* 476 */, TRICORE_INS_IMASK,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INSERT_rcpw /* 477 */, TRICORE_INS_INSERT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INSERT_rcrr /* 478 */, TRICORE_INS_INSERT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INSERT_rcrw /* 479 */, TRICORE_INS_INSERT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INSERT_rrpw /* 480 */, TRICORE_INS_INSERT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INSERT_rrrr /* 481 */, TRICORE_INS_INSERT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INSERT_rrrw /* 482 */, TRICORE_INS_INSERT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INSN_T /* 483 */, TRICORE_INS_INSN_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_INS_T /* 484 */, TRICORE_INS_INS_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ISYNC_sys /* 485 */, TRICORE_INS_ISYNC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ITOF_rr /* 486 */, TRICORE_INS_ITOF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_IXMAX_U_rrr /* 487 */, TRICORE_INS_IXMAX_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_IXMAX_rrr /* 488 */, TRICORE_INS_IXMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_IXMIN_U_rrr /* 489 */, TRICORE_INS_IXMIN_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_IXMIN_rrr /* 490 */, TRICORE_INS_IXMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JA_b /* 491 */, TRICORE_INS_JA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JEQ_A_brr /* 492 */, TRICORE_INS_JEQ_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JEQ_brc /* 493 */, TRICORE_INS_JEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JEQ_brr /* 494 */, TRICORE_INS_JEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JEQ_sbc1 /* 495 */, TRICORE_INS_JEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JEQ_sbc2 /* 496 */, TRICORE_INS_JEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JEQ_sbc_v110 /* 497 */, TRICORE_INS_JEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JEQ_sbr1 /* 498 */, TRICORE_INS_JEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JEQ_sbr2 /* 499 */, TRICORE_INS_JEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JEQ_sbr_v110 /* 500 */, TRICORE_INS_JEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JGEZ_sbr /* 501 */, TRICORE_INS_JGEZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JGEZ_sbr_v110 /* 502 */, TRICORE_INS_JGEZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JGE_U_brc /* 503 */, TRICORE_INS_JGE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JGE_U_brr /* 504 */, TRICORE_INS_JGE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JGE_brc /* 505 */, TRICORE_INS_JGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JGE_brr /* 506 */, TRICORE_INS_JGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JGTZ_sbr /* 507 */, TRICORE_INS_JGTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JGTZ_sbr_v110 /* 508 */, TRICORE_INS_JGTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JI_rr /* 509 */, TRICORE_INS_JI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JI_rr_v110 /* 510 */, TRICORE_INS_JI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JI_sbr_v110 /* 511 */, TRICORE_INS_JI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JI_sr /* 512 */, TRICORE_INS_JI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLA_b /* 513 */, TRICORE_INS_JLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLEZ_sbr /* 514 */, TRICORE_INS_JLEZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLEZ_sbr_v110 /* 515 */, TRICORE_INS_JLEZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLI_rr /* 516 */, TRICORE_INS_JLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLI_rr_v110 /* 517 */, TRICORE_INS_JLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLTZ_sbr /* 518 */, TRICORE_INS_JLTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLTZ_sbr_v110 /* 519 */, TRICORE_INS_JLTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLT_U_brc /* 520 */, TRICORE_INS_JLT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLT_U_brr /* 521 */, TRICORE_INS_JLT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLT_brc /* 522 */, TRICORE_INS_JLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JLT_brr /* 523 */, TRICORE_INS_JLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JL_b /* 524 */, TRICORE_INS_JL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNED_brc /* 525 */, TRICORE_INS_JNED,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNED_brr /* 526 */, TRICORE_INS_JNED,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNEI_brc /* 527 */, TRICORE_INS_JNEI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNEI_brr /* 528 */, TRICORE_INS_JNEI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNE_A_brr /* 529 */, TRICORE_INS_JNE_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNE_brc /* 530 */, TRICORE_INS_JNE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNE_brr /* 531 */, TRICORE_INS_JNE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNE_sbc1 /* 532 */, TRICORE_INS_JNE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNE_sbc2 /* 533 */, TRICORE_INS_JNE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNE_sbc_v110 /* 534 */, TRICORE_INS_JNE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNE_sbr1 /* 535 */, TRICORE_INS_JNE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNE_sbr2 /* 536 */, TRICORE_INS_JNE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNE_sbr_v110 /* 537 */, TRICORE_INS_JNE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNZ_A_brr /* 538 */, TRICORE_INS_JNZ_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNZ_A_sbr /* 539 */, TRICORE_INS_JNZ_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNZ_T_brn /* 540 */, TRICORE_INS_JNZ_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNZ_T_sbrn /* 541 */, TRICORE_INS_JNZ_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNZ_T_sbrn_v110 /* 542 */, TRICORE_INS_JNZ_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNZ_sb /* 543 */, TRICORE_INS_JNZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNZ_sb_v110 /* 544 */, TRICORE_INS_JNZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNZ_sbr /* 545 */, TRICORE_INS_JNZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JNZ_sbr_v110 /* 546 */, TRICORE_INS_JNZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JZ_A_brr /* 547 */, TRICORE_INS_JZ_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JZ_A_sbr /* 548 */, TRICORE_INS_JZ_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JZ_T_brn /* 549 */, TRICORE_INS_JZ_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JZ_T_sbrn /* 550 */, TRICORE_INS_JZ_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JZ_T_sbrn_v110 /* 551 */, TRICORE_INS_JZ_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JZ_sb /* 552 */, TRICORE_INS_JZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JZ_sb_v110 /* 553 */, TRICORE_INS_JZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JZ_sbr /* 554 */, TRICORE_INS_JZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_JZ_sbr_v110 /* 555 */, TRICORE_INS_JZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_J_b /* 556 */, TRICORE_INS_J,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_J_sb /* 557 */, TRICORE_INS_J,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_J_sb_v110 /* 558 */, TRICORE_INS_J,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LDLCX_abs /* 559 */, TRICORE_INS_LDLCX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LDLCX_bo_bso /* 560 */, TRICORE_INS_LDLCX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LDMST_abs /* 561 */, TRICORE_INS_LDMST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LDMST_bo_bso /* 562 */, TRICORE_INS_LDMST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LDMST_bo_c /* 563 */, TRICORE_INS_LDMST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LDMST_bo_pos /* 564 */, TRICORE_INS_LDMST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LDMST_bo_pre /* 565 */, TRICORE_INS_LDMST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LDMST_bo_r /* 566 */, TRICORE_INS_LDMST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LDUCX_abs /* 567 */, TRICORE_INS_LDUCX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LDUCX_bo_bso /* 568 */, TRICORE_INS_LDUCX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_abs /* 569 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_bo_bso /* 570 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_bo_c /* 571 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_bo_pos /* 572 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_bo_pre /* 573 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_bo_r /* 574 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_bol /* 575 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_sc /* 576 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_slr /* 577 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_slr_post /* 578 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_slr_post_v110 /* 579 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_slr_v110 /* 580 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_slro /* 581 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_slro_v110 /* 582 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_sro /* 583 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_A_sro_v110 /* 584 */, TRICORE_INS_LD_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_abs /* 585 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_bo_bso /* 586 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_bo_c /* 587 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_bo_pos /* 588 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_bo_pre /* 589 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_bo_r /* 590 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_bol /* 591 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_slr /* 592 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_slr_post /* 593 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_slr_post_v110 /* 594 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_slr_v110 /* 595 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_slro /* 596 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_slro_v110 /* 597 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_sro /* 598 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_BU_sro_v110 /* 599 */, TRICORE_INS_LD_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_abs /* 600 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_bo_bso /* 601 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_bo_c /* 602 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_bo_pos /* 603 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_bo_pre /* 604 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_bo_r /* 605 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_bol /* 606 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_slr_post_v110 /* 607 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_slr_v110 /* 608 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_slro_v110 /* 609 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_B_sro_v110 /* 610 */, TRICORE_INS_LD_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_DA_abs /* 611 */, TRICORE_INS_LD_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_DA_bo_bso /* 612 */, TRICORE_INS_LD_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_DA_bo_c /* 613 */, TRICORE_INS_LD_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_DA_bo_pos /* 614 */, TRICORE_INS_LD_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_DA_bo_pre /* 615 */, TRICORE_INS_LD_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_DA_bo_r /* 616 */, TRICORE_INS_LD_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_D_abs /* 617 */, TRICORE_INS_LD_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_D_bo_bso /* 618 */, TRICORE_INS_LD_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_D_bo_c /* 619 */, TRICORE_INS_LD_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_D_bo_pos /* 620 */, TRICORE_INS_LD_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_D_bo_pre /* 621 */, TRICORE_INS_LD_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_D_bo_r /* 622 */, TRICORE_INS_LD_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_HU_abs /* 623 */, TRICORE_INS_LD_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_HU_bo_bso /* 624 */, TRICORE_INS_LD_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_HU_bo_c /* 625 */, TRICORE_INS_LD_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_HU_bo_pos /* 626 */, TRICORE_INS_LD_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_HU_bo_pre /* 627 */, TRICORE_INS_LD_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_HU_bo_r /* 628 */, TRICORE_INS_LD_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_HU_bol /* 629 */, TRICORE_INS_LD_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_abs /* 630 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_bo_bso /* 631 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_bo_c /* 632 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_bo_pos /* 633 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_bo_pre /* 634 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_bo_r /* 635 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_bol /* 636 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_slr /* 637 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_slr_post /* 638 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_slr_post_v110 /* 639 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_slr_v110 /* 640 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_slro /* 641 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_slro_v110 /* 642 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_sro /* 643 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_H_sro_v110 /* 644 */, TRICORE_INS_LD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_Q_abs /* 645 */, TRICORE_INS_LD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_Q_bo_bso /* 646 */, TRICORE_INS_LD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_Q_bo_c /* 647 */, TRICORE_INS_LD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_Q_bo_pos /* 648 */, TRICORE_INS_LD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_Q_bo_pre /* 649 */, TRICORE_INS_LD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_Q_bo_r /* 650 */, TRICORE_INS_LD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_abs /* 651 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_bo_bso /* 652 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_bo_c /* 653 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_bo_pos /* 654 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_bo_pre /* 655 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_bo_r /* 656 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_bol /* 657 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_sc /* 658 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_slr /* 659 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_slr_post /* 660 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_slr_post_v110 /* 661 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_slr_v110 /* 662 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_slro /* 663 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_slro_v110 /* 664 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_sro /* 665 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LD_W_sro_v110 /* 666 */, TRICORE_INS_LD_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LEA_abs /* 667 */, TRICORE_INS_LEA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LEA_bo_bso /* 668 */, TRICORE_INS_LEA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LEA_bol /* 669 */, TRICORE_INS_LEA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LHA_abs /* 670 */, TRICORE_INS_LHA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV162_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LOOPU_brr /* 671 */, TRICORE_INS_LOOPU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LOOP_brr /* 672 */, TRICORE_INS_LOOP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LOOP_sbr /* 673 */, TRICORE_INS_LOOP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_A_rr /* 674 */, TRICORE_INS_LT_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_B /* 675 */, TRICORE_INS_LT_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_BU /* 676 */, TRICORE_INS_LT_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_H /* 677 */, TRICORE_INS_LT_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_HU /* 678 */, TRICORE_INS_LT_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_U_rc /* 679 */, TRICORE_INS_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_U_rr /* 680 */, TRICORE_INS_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_U_srcv110 /* 681 */, TRICORE_INS_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_U_srrv110 /* 682 */, TRICORE_INS_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_W /* 683 */, TRICORE_INS_LT_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_WU /* 684 */, TRICORE_INS_LT_WU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_rc /* 685 */, TRICORE_INS_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_rr /* 686 */, TRICORE_INS_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_src /* 687 */, TRICORE_INS_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_LT_srr /* 688 */, TRICORE_INS_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDMS_H_rrr1_LL /* 689 */, TRICORE_INS_MADDMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDMS_H_rrr1_LU /* 690 */, TRICORE_INS_MADDMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDMS_H_rrr1_UL /* 691 */, TRICORE_INS_MADDMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDMS_H_rrr1_UU /* 692 */, TRICORE_INS_MADDMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDMS_U_rcr_v110 /* 693 */, TRICORE_INS_MADDMS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDMS_U_rrr2_v110 /* 694 */, TRICORE_INS_MADDMS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDMS_rcr_v110 /* 695 */, TRICORE_INS_MADDMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDMS_rrr2_v110 /* 696 */, TRICORE_INS_MADDMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDM_H_rrr1_LL /* 697 */, TRICORE_INS_MADDM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDM_H_rrr1_LU /* 698 */, TRICORE_INS_MADDM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDM_H_rrr1_UL /* 699 */, TRICORE_INS_MADDM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDM_H_rrr1_UU /* 700 */, TRICORE_INS_MADDM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDM_H_rrr1_v110 /* 701 */, TRICORE_INS_MADDM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDM_Q_rrr1_v110 /* 702 */, TRICORE_INS_MADDM_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDM_U_rcr_v110 /* 703 */, TRICORE_INS_MADDM_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDM_U_rrr2_v110 /* 704 */, TRICORE_INS_MADDM_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDM_rcr_v110 /* 705 */, TRICORE_INS_MADDM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDM_rrr2_v110 /* 706 */, TRICORE_INS_MADDM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDRS_H_rrr1_LL /* 707 */, TRICORE_INS_MADDRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDRS_H_rrr1_LU /* 708 */, TRICORE_INS_MADDRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDRS_H_rrr1_UL /* 709 */, TRICORE_INS_MADDRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDRS_H_rrr1_UL_2 /* 710 */, TRICORE_INS_MADDRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDRS_H_rrr1_UU /* 711 */, TRICORE_INS_MADDRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDRS_H_rrr1_v110 /* 712 */, TRICORE_INS_MADDRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDRS_Q_rrr1_L_L /* 713 */, TRICORE_INS_MADDRS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDRS_Q_rrr1_U_U /* 714 */, TRICORE_INS_MADDRS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDRS_Q_rrr1_v110 /* 715 */, TRICORE_INS_MADDRS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDR_H_rrr1_LL /* 716 */, TRICORE_INS_MADDR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDR_H_rrr1_LU /* 717 */, TRICORE_INS_MADDR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDR_H_rrr1_UL /* 718 */, TRICORE_INS_MADDR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDR_H_rrr1_UL_2 /* 719 */, TRICORE_INS_MADDR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDR_H_rrr1_UU /* 720 */, TRICORE_INS_MADDR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDR_H_rrr1_v110 /* 721 */, TRICORE_INS_MADDR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDR_Q_rrr1_L_L /* 722 */, TRICORE_INS_MADDR_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDR_Q_rrr1_U_U /* 723 */, TRICORE_INS_MADDR_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDR_Q_rrr1_v110 /* 724 */, TRICORE_INS_MADDR_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUMS_H_rrr1_LL /* 725 */, TRICORE_INS_MADDSUMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUMS_H_rrr1_LU /* 726 */, TRICORE_INS_MADDSUMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUMS_H_rrr1_UL /* 727 */, TRICORE_INS_MADDSUMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUMS_H_rrr1_UU /* 728 */, TRICORE_INS_MADDSUMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUM_H_rrr1_LL /* 729 */, TRICORE_INS_MADDSUM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUM_H_rrr1_LU /* 730 */, TRICORE_INS_MADDSUM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUM_H_rrr1_UL /* 731 */, TRICORE_INS_MADDSUM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUM_H_rrr1_UU /* 732 */, TRICORE_INS_MADDSUM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSURS_H_rrr1_LL /* 733 */, TRICORE_INS_MADDSURS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSURS_H_rrr1_LU /* 734 */, TRICORE_INS_MADDSURS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSURS_H_rrr1_UL /* 735 */, TRICORE_INS_MADDSURS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSURS_H_rrr1_UU /* 736 */, TRICORE_INS_MADDSURS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUR_H_rrr1_LL /* 737 */, TRICORE_INS_MADDSUR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUR_H_rrr1_LU /* 738 */, TRICORE_INS_MADDSUR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUR_H_rrr1_UL /* 739 */, TRICORE_INS_MADDSUR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUR_H_rrr1_UU /* 740 */, TRICORE_INS_MADDSUR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUS_H_rrr1_LL /* 741 */, TRICORE_INS_MADDSUS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUS_H_rrr1_LU /* 742 */, TRICORE_INS_MADDSUS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUS_H_rrr1_UL /* 743 */, TRICORE_INS_MADDSUS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSUS_H_rrr1_UU /* 744 */, TRICORE_INS_MADDSUS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSU_H_rrr1_LL /* 745 */, TRICORE_INS_MADDSU_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSU_H_rrr1_LU /* 746 */, TRICORE_INS_MADDSU_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSU_H_rrr1_UL /* 747 */, TRICORE_INS_MADDSU_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDSU_H_rrr1_UU /* 748 */, TRICORE_INS_MADDSU_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_H_rrr1_LL /* 749 */, TRICORE_INS_MADDS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_H_rrr1_LU /* 750 */, TRICORE_INS_MADDS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_H_rrr1_UL /* 751 */, TRICORE_INS_MADDS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_H_rrr1_UU /* 752 */, TRICORE_INS_MADDS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_H_rrr1_v110 /* 753 */, TRICORE_INS_MADDS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1 /* 754 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1_L /* 755 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1_L_L /* 756 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1_U /* 757 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1_UU2_v110 /* 758 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1_U_U /* 759 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1_e /* 760 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1_e_L /* 761 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1_e_L_L /* 762 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1_e_U /* 763 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_Q_rrr1_e_U_U /* 764 */, TRICORE_INS_MADDS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_U_rcr /* 765 */, TRICORE_INS_MADDS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_U_rcr_e /* 766 */, TRICORE_INS_MADDS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_U_rrr2 /* 767 */, TRICORE_INS_MADDS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_U_rrr2_e /* 768 */, TRICORE_INS_MADDS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_rcr /* 769 */, TRICORE_INS_MADDS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_rcr_e /* 770 */, TRICORE_INS_MADDS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_rrr2 /* 771 */, TRICORE_INS_MADDS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADDS_rrr2_e /* 772 */, TRICORE_INS_MADDS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_F_rrr /* 773 */, TRICORE_INS_MADD_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_H_rrr1_LL /* 774 */, TRICORE_INS_MADD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_H_rrr1_LU /* 775 */, TRICORE_INS_MADD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_H_rrr1_UL /* 776 */, TRICORE_INS_MADD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_H_rrr1_UU /* 777 */, TRICORE_INS_MADD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_H_rrr1_v110 /* 778 */, TRICORE_INS_MADD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1 /* 779 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1_L /* 780 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1_L_L /* 781 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1_U /* 782 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1_UU2_v110 /* 783 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1_U_U /* 784 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1_e /* 785 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1_e_L /* 786 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1_e_L_L /* 787 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1_e_U /* 788 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_Q_rrr1_e_U_U /* 789 */, TRICORE_INS_MADD_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_U_rcr /* 790 */, TRICORE_INS_MADD_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_U_rrr2 /* 791 */, TRICORE_INS_MADD_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_rcr /* 792 */, TRICORE_INS_MADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_rcr_e /* 793 */, TRICORE_INS_MADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_rrr2 /* 794 */, TRICORE_INS_MADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MADD_rrr2_e /* 795 */, TRICORE_INS_MADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MAX_B /* 796 */, TRICORE_INS_MAX_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MAX_BU /* 797 */, TRICORE_INS_MAX_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MAX_H /* 798 */, TRICORE_INS_MAX_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MAX_HU /* 799 */, TRICORE_INS_MAX_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MAX_U_rc /* 800 */, TRICORE_INS_MAX_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MAX_U_rr /* 801 */, TRICORE_INS_MAX_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MAX_rc /* 802 */, TRICORE_INS_MAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MAX_rr /* 803 */, TRICORE_INS_MAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MFCR_rlc /* 804 */, TRICORE_INS_MFCR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MIN_B /* 805 */, TRICORE_INS_MIN_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MIN_BU /* 806 */, TRICORE_INS_MIN_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MIN_H /* 807 */, TRICORE_INS_MIN_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MIN_HU /* 808 */, TRICORE_INS_MIN_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MIN_U_rc /* 809 */, TRICORE_INS_MIN_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MIN_U_rr /* 810 */, TRICORE_INS_MIN_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MIN_rc /* 811 */, TRICORE_INS_MIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MIN_rr /* 812 */, TRICORE_INS_MIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOVH_A_rlc /* 813 */, TRICORE_INS_MOVH_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOVH_rlc /* 814 */, TRICORE_INS_MOVH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOVZ_A_sr /* 815 */, TRICORE_INS_MOVZ_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_AA_rr /* 816 */, TRICORE_INS_MOV_AA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_AA_srr_srr /* 817 */, TRICORE_INS_MOV_AA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_AA_srr_srr_v110 /* 818 */, TRICORE_INS_MOV_AA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_A_rr /* 819 */, TRICORE_INS_MOV_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_A_src /* 820 */, TRICORE_INS_MOV_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_A_srr /* 821 */, TRICORE_INS_MOV_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_A_srr_v110 /* 822 */, TRICORE_INS_MOV_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_D_rr /* 823 */, TRICORE_INS_MOV_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_D_srr_srr /* 824 */, TRICORE_INS_MOV_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_D_srr_srr_v110 /* 825 */, TRICORE_INS_MOV_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_U_rlc /* 826 */, TRICORE_INS_MOV_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_rlc /* 827 */, TRICORE_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_rlc_e /* 828 */, TRICORE_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_rr /* 829 */, TRICORE_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_rr_e /* 830 */, TRICORE_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_rr_eab /* 831 */, TRICORE_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_sc /* 832 */, TRICORE_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_sc_v110 /* 833 */, TRICORE_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_src /* 834 */, TRICORE_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_src_e /* 835 */, TRICORE_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MOV_srr /* 836 */, TRICORE_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADMS_H_rrr1_LL /* 837 */, TRICORE_INS_MSUBADMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADMS_H_rrr1_LU /* 838 */, TRICORE_INS_MSUBADMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADMS_H_rrr1_UL /* 839 */, TRICORE_INS_MSUBADMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADMS_H_rrr1_UU /* 840 */, TRICORE_INS_MSUBADMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADM_H_rrr1_LL /* 841 */, TRICORE_INS_MSUBADM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADM_H_rrr1_LU /* 842 */, TRICORE_INS_MSUBADM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADM_H_rrr1_UL /* 843 */, TRICORE_INS_MSUBADM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADM_H_rrr1_UU /* 844 */, TRICORE_INS_MSUBADM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADRS_H_rrr1_LL /* 845 */, TRICORE_INS_MSUBADRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADRS_H_rrr1_LU /* 846 */, TRICORE_INS_MSUBADRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADRS_H_rrr1_UL /* 847 */, TRICORE_INS_MSUBADRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADRS_H_rrr1_UU /* 848 */, TRICORE_INS_MSUBADRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADRS_H_rrr1_v110 /* 849 */, TRICORE_INS_MSUBADRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADR_H_rrr1_LL /* 850 */, TRICORE_INS_MSUBADR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADR_H_rrr1_LU /* 851 */, TRICORE_INS_MSUBADR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADR_H_rrr1_UL /* 852 */, TRICORE_INS_MSUBADR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADR_H_rrr1_UU /* 853 */, TRICORE_INS_MSUBADR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADR_H_rrr1_v110 /* 854 */, TRICORE_INS_MSUBADR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADS_H_rrr1_LL /* 855 */, TRICORE_INS_MSUBADS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADS_H_rrr1_LU /* 856 */, TRICORE_INS_MSUBADS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADS_H_rrr1_UL /* 857 */, TRICORE_INS_MSUBADS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBADS_H_rrr1_UU /* 858 */, TRICORE_INS_MSUBADS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBAD_H_rrr1_LL /* 859 */, TRICORE_INS_MSUBAD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBAD_H_rrr1_LU /* 860 */, TRICORE_INS_MSUBAD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBAD_H_rrr1_UL /* 861 */, TRICORE_INS_MSUBAD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBAD_H_rrr1_UU /* 862 */, TRICORE_INS_MSUBAD_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBMS_H_rrr1_LL /* 863 */, TRICORE_INS_MSUBMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBMS_H_rrr1_LU /* 864 */, TRICORE_INS_MSUBMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBMS_H_rrr1_UL /* 865 */, TRICORE_INS_MSUBMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBMS_H_rrr1_UU /* 866 */, TRICORE_INS_MSUBMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBMS_U_rcrv110 /* 867 */, TRICORE_INS_MSUBMS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBMS_U_rrr2v110 /* 868 */, TRICORE_INS_MSUBMS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBMS_rcrv110 /* 869 */, TRICORE_INS_MSUBMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBMS_rrr2v110 /* 870 */, TRICORE_INS_MSUBMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBM_H_rrr1_LL /* 871 */, TRICORE_INS_MSUBM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBM_H_rrr1_LU /* 872 */, TRICORE_INS_MSUBM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBM_H_rrr1_UL /* 873 */, TRICORE_INS_MSUBM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBM_H_rrr1_UU /* 874 */, TRICORE_INS_MSUBM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBM_H_rrr1_v110 /* 875 */, TRICORE_INS_MSUBM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBM_Q_rrr1_v110 /* 876 */, TRICORE_INS_MSUBM_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBM_U_rcrv110 /* 877 */, TRICORE_INS_MSUBM_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBM_U_rrr2v110 /* 878 */, TRICORE_INS_MSUBM_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBM_rcrv110 /* 879 */, TRICORE_INS_MSUBM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBM_rrr2v110 /* 880 */, TRICORE_INS_MSUBM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBRS_H_rrr1_LL /* 881 */, TRICORE_INS_MSUBRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBRS_H_rrr1_LU /* 882 */, TRICORE_INS_MSUBRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBRS_H_rrr1_UL /* 883 */, TRICORE_INS_MSUBRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBRS_H_rrr1_UL_2 /* 884 */, TRICORE_INS_MSUBRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBRS_H_rrr1_UU /* 885 */, TRICORE_INS_MSUBRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBRS_H_rrr1_v110 /* 886 */, TRICORE_INS_MSUBRS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBRS_Q_rrr1_L_L /* 887 */, TRICORE_INS_MSUBRS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBRS_Q_rrr1_U_U /* 888 */, TRICORE_INS_MSUBRS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBRS_Q_rrr1_v110 /* 889 */, TRICORE_INS_MSUBRS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBR_H_rrr1_LL /* 890 */, TRICORE_INS_MSUBR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBR_H_rrr1_LU /* 891 */, TRICORE_INS_MSUBR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBR_H_rrr1_UL /* 892 */, TRICORE_INS_MSUBR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBR_H_rrr1_UL_2 /* 893 */, TRICORE_INS_MSUBR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBR_H_rrr1_UU /* 894 */, TRICORE_INS_MSUBR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBR_H_rrr1_v110 /* 895 */, TRICORE_INS_MSUBR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBR_Q_rrr1_L_L /* 896 */, TRICORE_INS_MSUBR_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBR_Q_rrr1_U_U /* 897 */, TRICORE_INS_MSUBR_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBR_Q_rrr1_v110 /* 898 */, TRICORE_INS_MSUBR_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_H_rrr1_LL /* 899 */, TRICORE_INS_MSUBS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_H_rrr1_LU /* 900 */, TRICORE_INS_MSUBS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_H_rrr1_UL /* 901 */, TRICORE_INS_MSUBS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_H_rrr1_UU /* 902 */, TRICORE_INS_MSUBS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_H_rrr1_v110 /* 903 */, TRICORE_INS_MSUBS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1 /* 904 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1_L /* 905 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1_L_L /* 906 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1_U /* 907 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1_UU2_v110 /* 908 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1_U_U /* 909 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1_e /* 910 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1_e_L /* 911 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1_e_L_L /* 912 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1_e_U /* 913 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_Q_rrr1_e_U_U /* 914 */, TRICORE_INS_MSUBS_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_U_rcr /* 915 */, TRICORE_INS_MSUBS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_U_rcr_e /* 916 */, TRICORE_INS_MSUBS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_U_rrr2 /* 917 */, TRICORE_INS_MSUBS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_U_rrr2_e /* 918 */, TRICORE_INS_MSUBS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_rcr /* 919 */, TRICORE_INS_MSUBS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_rcr_e /* 920 */, TRICORE_INS_MSUBS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_rrr2 /* 921 */, TRICORE_INS_MSUBS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUBS_rrr2_e /* 922 */, TRICORE_INS_MSUBS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_F_rrr /* 923 */, TRICORE_INS_MSUB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_H_rrr1_LL /* 924 */, TRICORE_INS_MSUB_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_H_rrr1_LU /* 925 */, TRICORE_INS_MSUB_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_H_rrr1_UL /* 926 */, TRICORE_INS_MSUB_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_H_rrr1_UU /* 927 */, TRICORE_INS_MSUB_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_H_rrr1_v110 /* 928 */, TRICORE_INS_MSUB_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1 /* 929 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1_L /* 930 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1_L_L /* 931 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1_U /* 932 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1_UU2_v110 /* 933 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1_U_U /* 934 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1_e /* 935 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1_e_L /* 936 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1_e_L_L /* 937 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1_e_U /* 938 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_Q_rrr1_e_U_U /* 939 */, TRICORE_INS_MSUB_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_U_rcr /* 940 */, TRICORE_INS_MSUB_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_U_rrr2 /* 941 */, TRICORE_INS_MSUB_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_rcr /* 942 */, TRICORE_INS_MSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_rcr_e /* 943 */, TRICORE_INS_MSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_rrr2 /* 944 */, TRICORE_INS_MSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MSUB_rrr2_e /* 945 */, TRICORE_INS_MSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MTCR_rlc /* 946 */, TRICORE_INS_MTCR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULMS_H_rr1_LL2e /* 947 */, TRICORE_INS_MULMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULMS_H_rr1_LU2e /* 948 */, TRICORE_INS_MULMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULMS_H_rr1_UL2e /* 949 */, TRICORE_INS_MULMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULMS_H_rr1_UU2e /* 950 */, TRICORE_INS_MULMS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULM_H_rr1_LL2e /* 951 */, TRICORE_INS_MULM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULM_H_rr1_LU2e /* 952 */, TRICORE_INS_MULM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULM_H_rr1_UL2e /* 953 */, TRICORE_INS_MULM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULM_H_rr1_UU2e /* 954 */, TRICORE_INS_MULM_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULM_U_rc /* 955 */, TRICORE_INS_MULM_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULM_U_rr /* 956 */, TRICORE_INS_MULM_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULM_rc /* 957 */, TRICORE_INS_MULM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULM_rr /* 958 */, TRICORE_INS_MULM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULR_H_rr1_LL2e /* 959 */, TRICORE_INS_MULR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULR_H_rr1_LU2e /* 960 */, TRICORE_INS_MULR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULR_H_rr1_UL2e /* 961 */, TRICORE_INS_MULR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULR_H_rr1_UU2e /* 962 */, TRICORE_INS_MULR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULR_H_rr_v110 /* 963 */, TRICORE_INS_MULR_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULR_Q_rr1_2LL /* 964 */, TRICORE_INS_MULR_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULR_Q_rr1_2UU /* 965 */, TRICORE_INS_MULR_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULR_Q_rr_v110 /* 966 */, TRICORE_INS_MULR_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULS_U_rc /* 967 */, TRICORE_INS_MULS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULS_U_rr2 /* 968 */, TRICORE_INS_MULS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULS_U_rr_v110 /* 969 */, TRICORE_INS_MULS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULS_rc /* 970 */, TRICORE_INS_MULS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULS_rr2 /* 971 */, TRICORE_INS_MULS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MULS_rr_v110 /* 972 */, TRICORE_INS_MULS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_F_rrr /* 973 */, TRICORE_INS_MUL_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_H_rr1_LL2e /* 974 */, TRICORE_INS_MUL_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_H_rr1_LU2e /* 975 */, TRICORE_INS_MUL_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_H_rr1_UL2e /* 976 */, TRICORE_INS_MUL_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_H_rr1_UU2e /* 977 */, TRICORE_INS_MUL_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_H_rr_v110 /* 978 */, TRICORE_INS_MUL_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_Q_rr1_2 /* 979 */, TRICORE_INS_MUL_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_Q_rr1_2LL /* 980 */, TRICORE_INS_MUL_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_Q_rr1_2UU /* 981 */, TRICORE_INS_MUL_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_Q_rr1_2_L /* 982 */, TRICORE_INS_MUL_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_Q_rr1_2_Le /* 983 */, TRICORE_INS_MUL_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_Q_rr1_2_U /* 984 */, TRICORE_INS_MUL_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_Q_rr1_2_Ue /* 985 */, TRICORE_INS_MUL_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_Q_rr1_2__e /* 986 */, TRICORE_INS_MUL_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_Q_rr_v110 /* 987 */, TRICORE_INS_MUL_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_U_rc /* 988 */, TRICORE_INS_MUL_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_U_rr2 /* 989 */, TRICORE_INS_MUL_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_rc /* 990 */, TRICORE_INS_MUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_rc_e /* 991 */, TRICORE_INS_MUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_rr2 /* 992 */, TRICORE_INS_MUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_rr2_e /* 993 */, TRICORE_INS_MUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_rr_v110 /* 994 */, TRICORE_INS_MUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_MUL_srr /* 995 */, TRICORE_INS_MUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NAND_T /* 996 */, TRICORE_INS_NAND_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NAND_rc /* 997 */, TRICORE_INS_NAND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NAND_rr /* 998 */, TRICORE_INS_NAND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NEZ_A /* 999 */, TRICORE_INS_NEZ_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NE_A /* 1000 */, TRICORE_INS_NE_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NE_rc /* 1001 */, TRICORE_INS_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NE_rr /* 1002 */, TRICORE_INS_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NOP_sr /* 1003 */, TRICORE_INS_NOP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NOP_sys /* 1004 */, TRICORE_INS_NOP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NOR_T /* 1005 */, TRICORE_INS_NOR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NOR_rc /* 1006 */, TRICORE_INS_NOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NOR_rr /* 1007 */, TRICORE_INS_NOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NOR_sr /* 1008 */, TRICORE_INS_NOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NOR_sr_v110 /* 1009 */, TRICORE_INS_NOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_NOT_sr_v162 /* 1010 */, TRICORE_INS_NOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV162, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ORN_T /* 1011 */, TRICORE_INS_ORN_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ORN_rc /* 1012 */, TRICORE_INS_ORN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ORN_rr /* 1013 */, TRICORE_INS_ORN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_ANDN_T /* 1014 */, TRICORE_INS_OR_ANDN_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_AND_T /* 1015 */, TRICORE_INS_OR_AND_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_EQ_rc /* 1016 */, TRICORE_INS_OR_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_EQ_rr /* 1017 */, TRICORE_INS_OR_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_GE_U_rc /* 1018 */, TRICORE_INS_OR_GE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_GE_U_rr /* 1019 */, TRICORE_INS_OR_GE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_GE_rc /* 1020 */, TRICORE_INS_OR_GE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_GE_rr /* 1021 */, TRICORE_INS_OR_GE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_LT_U_rc /* 1022 */, TRICORE_INS_OR_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_LT_U_rr /* 1023 */, TRICORE_INS_OR_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_LT_rc /* 1024 */, TRICORE_INS_OR_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_LT_rr /* 1025 */, TRICORE_INS_OR_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_NE_rc /* 1026 */, TRICORE_INS_OR_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_NE_rr /* 1027 */, TRICORE_INS_OR_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_NOR_T /* 1028 */, TRICORE_INS_OR_NOR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_OR_T /* 1029 */, TRICORE_INS_OR_OR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_T /* 1030 */, TRICORE_INS_OR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_rc /* 1031 */, TRICORE_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_rr /* 1032 */, TRICORE_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_sc /* 1033 */, TRICORE_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_sc_v110 /* 1034 */, TRICORE_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_srr /* 1035 */, TRICORE_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_OR_srr_v110 /* 1036 */, TRICORE_INS_OR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PACK_rrr /* 1037 */, TRICORE_INS_PACK,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PARITY_rr /* 1038 */, TRICORE_INS_PARITY,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_PARITY_rr_v110 /* 1039 */, TRICORE_INS_PARITY,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_POPCNT_W_rr /* 1040 */, TRICORE_INS_POPCNT_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV162, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_Q31TOF_rr /* 1041 */, TRICORE_INS_Q31TOF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_QSEED_F_rr /* 1042 */, TRICORE_INS_QSEED_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RESTORE_sys /* 1043 */, TRICORE_INS_RESTORE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RET_sr /* 1044 */, TRICORE_INS_RET,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RET_sys /* 1045 */, TRICORE_INS_RET,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RET_sys_v110 /* 1046 */, TRICORE_INS_RET,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RFE_sr /* 1047 */, TRICORE_INS_RFE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RFE_sys_sys /* 1048 */, TRICORE_INS_RFE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RFE_sys_sys_v110 /* 1049 */, TRICORE_INS_RFE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RFM_sys /* 1050 */, TRICORE_INS_RFM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RSLCX_sys /* 1051 */, TRICORE_INS_RSLCX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RSTV_sys /* 1052 */, TRICORE_INS_RSTV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RSUBS_U_rc /* 1053 */, TRICORE_INS_RSUBS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RSUBS_rc /* 1054 */, TRICORE_INS_RSUBS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RSUB_rc /* 1055 */, TRICORE_INS_RSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RSUB_sr_sr /* 1056 */, TRICORE_INS_RSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_RSUB_sr_sr_v110 /* 1057 */, TRICORE_INS_RSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_BU_rr /* 1058 */, TRICORE_INS_SAT_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_BU_sr /* 1059 */, TRICORE_INS_SAT_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_BU_sr_v110 /* 1060 */, TRICORE_INS_SAT_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_B_rr /* 1061 */, TRICORE_INS_SAT_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_B_sr /* 1062 */, TRICORE_INS_SAT_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_B_sr_v110 /* 1063 */, TRICORE_INS_SAT_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_HU_rr /* 1064 */, TRICORE_INS_SAT_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_HU_sr /* 1065 */, TRICORE_INS_SAT_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_HU_sr_v110 /* 1066 */, TRICORE_INS_SAT_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_H_rr /* 1067 */, TRICORE_INS_SAT_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_H_sr /* 1068 */, TRICORE_INS_SAT_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SAT_H_sr_v110 /* 1069 */, TRICORE_INS_SAT_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SELN_A_rcr_v110 /* 1070 */, TRICORE_INS_SELN_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SELN_A_rrr_v110 /* 1071 */, TRICORE_INS_SELN_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SELN_rcr /* 1072 */, TRICORE_INS_SELN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SELN_rrr /* 1073 */, TRICORE_INS_SELN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SEL_A_rcr_v110 /* 1074 */, TRICORE_INS_SEL_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SEL_A_rrr_v110 /* 1075 */, TRICORE_INS_SEL_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SEL_rcr /* 1076 */, TRICORE_INS_SEL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SEL_rrr /* 1077 */, TRICORE_INS_SEL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHAS_rc /* 1078 */, TRICORE_INS_SHAS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHAS_rr /* 1079 */, TRICORE_INS_SHAS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHA_B_rc /* 1080 */, TRICORE_INS_SHA_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHA_B_rr /* 1081 */, TRICORE_INS_SHA_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHA_H_rc /* 1082 */, TRICORE_INS_SHA_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHA_H_rr /* 1083 */, TRICORE_INS_SHA_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHA_rc /* 1084 */, TRICORE_INS_SHA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHA_rr /* 1085 */, TRICORE_INS_SHA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHA_src /* 1086 */, TRICORE_INS_SHA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHA_src_v110 /* 1087 */, TRICORE_INS_SHA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SHUFFLE_rc /* 1088 */, TRICORE_INS_SHUFFLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV162, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_ANDN_T /* 1089 */, TRICORE_INS_SH_ANDN_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_AND_T /* 1090 */, TRICORE_INS_SH_AND_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_B_rc /* 1091 */, TRICORE_INS_SH_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_B_rr /* 1092 */, TRICORE_INS_SH_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_EQ_rc /* 1093 */, TRICORE_INS_SH_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_EQ_rr /* 1094 */, TRICORE_INS_SH_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_GE_U_rc /* 1095 */, TRICORE_INS_SH_GE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_GE_U_rr /* 1096 */, TRICORE_INS_SH_GE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_GE_rc /* 1097 */, TRICORE_INS_SH_GE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_GE_rr /* 1098 */, TRICORE_INS_SH_GE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_H_rc /* 1099 */, TRICORE_INS_SH_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_H_rr /* 1100 */, TRICORE_INS_SH_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_LT_U_rc /* 1101 */, TRICORE_INS_SH_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_LT_U_rr /* 1102 */, TRICORE_INS_SH_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_LT_rc /* 1103 */, TRICORE_INS_SH_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_LT_rr /* 1104 */, TRICORE_INS_SH_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_NAND_T /* 1105 */, TRICORE_INS_SH_NAND_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_NE_rc /* 1106 */, TRICORE_INS_SH_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_NE_rr /* 1107 */, TRICORE_INS_SH_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_NOR_T /* 1108 */, TRICORE_INS_SH_NOR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_ORN_T /* 1109 */, TRICORE_INS_SH_ORN_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_OR_T /* 1110 */, TRICORE_INS_SH_OR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_XNOR_T /* 1111 */, TRICORE_INS_SH_XNOR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_XOR_T /* 1112 */, TRICORE_INS_SH_XOR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_rc /* 1113 */, TRICORE_INS_SH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_rr /* 1114 */, TRICORE_INS_SH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_src /* 1115 */, TRICORE_INS_SH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SH_src_v110 /* 1116 */, TRICORE_INS_SH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_STLCX_abs /* 1117 */, TRICORE_INS_STLCX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_STLCX_bo_bso /* 1118 */, TRICORE_INS_STLCX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_STUCX_abs /* 1119 */, TRICORE_INS_STUCX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_STUCX_bo_bso /* 1120 */, TRICORE_INS_STUCX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_abs /* 1121 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_bo_bso /* 1122 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_bo_c /* 1123 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_bo_pos /* 1124 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_bo_pre /* 1125 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_bo_r /* 1126 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_bol /* 1127 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_sc /* 1128 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_sro /* 1129 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_sro_v110 /* 1130 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_ssr /* 1131 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_ssr_pos /* 1132 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_ssr_pos_v110 /* 1133 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_ssr_v110 /* 1134 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_ssro /* 1135 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_A_ssro_v110 /* 1136 */, TRICORE_INS_ST_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_abs /* 1137 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_bo_bso /* 1138 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_bo_c /* 1139 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_bo_pos /* 1140 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_bo_pre /* 1141 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_bo_r /* 1142 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_bol /* 1143 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_sro /* 1144 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_sro_v110 /* 1145 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_ssr /* 1146 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_ssr_pos /* 1147 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_ssr_pos_v110 /* 1148 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_ssr_v110 /* 1149 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_ssro /* 1150 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_B_ssro_v110 /* 1151 */, TRICORE_INS_ST_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_DA_abs /* 1152 */, TRICORE_INS_ST_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_DA_bo_bso /* 1153 */, TRICORE_INS_ST_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_DA_bo_c /* 1154 */, TRICORE_INS_ST_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_DA_bo_pos /* 1155 */, TRICORE_INS_ST_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_DA_bo_pre /* 1156 */, TRICORE_INS_ST_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_DA_bo_r /* 1157 */, TRICORE_INS_ST_DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_D_abs /* 1158 */, TRICORE_INS_ST_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_D_bo_bso /* 1159 */, TRICORE_INS_ST_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_D_bo_c /* 1160 */, TRICORE_INS_ST_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_D_bo_pos /* 1161 */, TRICORE_INS_ST_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_D_bo_pre /* 1162 */, TRICORE_INS_ST_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_D_bo_r /* 1163 */, TRICORE_INS_ST_D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_abs /* 1164 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_bo_bso /* 1165 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_bo_c /* 1166 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_bo_pos /* 1167 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_bo_pre /* 1168 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_bo_r /* 1169 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_bol /* 1170 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_sro /* 1171 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_sro_v110 /* 1172 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_ssr /* 1173 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_ssr_pos /* 1174 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_ssr_pos_v110 /* 1175 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_ssr_v110 /* 1176 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_ssro /* 1177 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_H_ssro_v110 /* 1178 */, TRICORE_INS_ST_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_Q_abs /* 1179 */, TRICORE_INS_ST_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_Q_bo_bso /* 1180 */, TRICORE_INS_ST_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_Q_bo_c /* 1181 */, TRICORE_INS_ST_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_Q_bo_pos /* 1182 */, TRICORE_INS_ST_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_Q_bo_pre /* 1183 */, TRICORE_INS_ST_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_Q_bo_r /* 1184 */, TRICORE_INS_ST_Q,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_T /* 1185 */, TRICORE_INS_ST_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_abs /* 1186 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_bo_bso /* 1187 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_bo_c /* 1188 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_bo_pos /* 1189 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_bo_pre /* 1190 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_bo_r /* 1191 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_bol /* 1192 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_sc /* 1193 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_sro /* 1194 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_sro_v110 /* 1195 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_ssr /* 1196 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_ssr_pos /* 1197 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_ssr_pos_v110 /* 1198 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_ssr_v110 /* 1199 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_ssro /* 1200 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_ST_W_ssro_v110 /* 1201 */, TRICORE_INS_ST_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBC_rr /* 1202 */, TRICORE_INS_SUBC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBSC_A_rr /* 1203 */, TRICORE_INS_SUBSC_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBS_BU_rr /* 1204 */, TRICORE_INS_SUBS_BU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBS_B_rr /* 1205 */, TRICORE_INS_SUBS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBS_HU_rr /* 1206 */, TRICORE_INS_SUBS_HU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBS_H_rr /* 1207 */, TRICORE_INS_SUBS_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBS_U_rr /* 1208 */, TRICORE_INS_SUBS_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBS_rr /* 1209 */, TRICORE_INS_SUBS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBS_srr /* 1210 */, TRICORE_INS_SUBS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUBX_rr /* 1211 */, TRICORE_INS_SUBX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUB_A_rr /* 1212 */, TRICORE_INS_SUB_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUB_A_sc /* 1213 */, TRICORE_INS_SUB_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUB_A_sc_v110 /* 1214 */, TRICORE_INS_SUB_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUB_B_rr /* 1215 */, TRICORE_INS_SUB_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUB_F_rrr /* 1216 */, TRICORE_INS_SUB_F,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUB_H_rr /* 1217 */, TRICORE_INS_SUB_H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUB_rr /* 1218 */, TRICORE_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUB_srr /* 1219 */, TRICORE_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUB_srr_15a /* 1220 */, TRICORE_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SUB_srr_a15 /* 1221 */, TRICORE_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SVLCX_sys /* 1222 */, TRICORE_INS_SVLCX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAPMSK_W_bo_bso /* 1223 */, TRICORE_INS_SWAPMSK_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAPMSK_W_bo_c /* 1224 */, TRICORE_INS_SWAPMSK_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAPMSK_W_bo_i /* 1225 */, TRICORE_INS_SWAPMSK_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAPMSK_W_bo_pos /* 1226 */, TRICORE_INS_SWAPMSK_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAPMSK_W_bo_pre /* 1227 */, TRICORE_INS_SWAPMSK_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAPMSK_W_bo_r /* 1228 */, TRICORE_INS_SWAPMSK_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_A_abs /* 1229 */, TRICORE_INS_SWAP_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_A_bo_bso /* 1230 */, TRICORE_INS_SWAP_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_A_bo_c /* 1231 */, TRICORE_INS_SWAP_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_A_bo_pos /* 1232 */, TRICORE_INS_SWAP_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_A_bo_pre /* 1233 */, TRICORE_INS_SWAP_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_A_bo_r /* 1234 */, TRICORE_INS_SWAP_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_W_abs /* 1235 */, TRICORE_INS_SWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_W_bo_bso /* 1236 */, TRICORE_INS_SWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_W_bo_c /* 1237 */, TRICORE_INS_SWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_W_bo_i /* 1238 */, TRICORE_INS_SWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV160_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_W_bo_pos /* 1239 */, TRICORE_INS_SWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_W_bo_pre /* 1240 */, TRICORE_INS_SWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SWAP_W_bo_r /* 1241 */, TRICORE_INS_SWAP_W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_SYSCALL_rc /* 1242 */, TRICORE_INS_SYSCALL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_TLBDEMAP_rr /* 1243 */, TRICORE_INS_TLBDEMAP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_TLBFLUSH_A_rr /* 1244 */, TRICORE_INS_TLBFLUSH_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_TLBFLUSH_B_rr /* 1245 */, TRICORE_INS_TLBFLUSH_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_TLBMAP_rr /* 1246 */, TRICORE_INS_TLBMAP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_TLBPROBE_A_rr /* 1247 */, TRICORE_INS_TLBPROBE_A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_TLBPROBE_I_rr /* 1248 */, TRICORE_INS_TLBPROBE_I,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_TRAPSV_sys /* 1249 */, TRICORE_INS_TRAPSV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_TRAPV_sys /* 1250 */, TRICORE_INS_TRAPV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_UNPACK_rr_rr /* 1251 */, TRICORE_INS_UNPACK,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_UNPACK_rr_rr_v110 /* 1252 */, TRICORE_INS_UNPACK,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV110, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_UPDFL_rr /* 1253 */, TRICORE_INS_UPDFL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_UTOF_rr /* 1254 */, TRICORE_INS_UTOF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV130_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_WAIT_sys /* 1255 */, TRICORE_INS_WAIT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV161_UP, 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XNOR_T /* 1256 */, TRICORE_INS_XNOR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XNOR_rc /* 1257 */, TRICORE_INS_XNOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XNOR_rr /* 1258 */, TRICORE_INS_XNOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_EQ_rc /* 1259 */, TRICORE_INS_XOR_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_EQ_rr /* 1260 */, TRICORE_INS_XOR_EQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_GE_U_rc /* 1261 */, TRICORE_INS_XOR_GE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_GE_U_rr /* 1262 */, TRICORE_INS_XOR_GE_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_GE_rc /* 1263 */, TRICORE_INS_XOR_GE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_GE_rr /* 1264 */, TRICORE_INS_XOR_GE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_LT_U_rc /* 1265 */, TRICORE_INS_XOR_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_LT_U_rr /* 1266 */, TRICORE_INS_XOR_LT_U,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_LT_rc /* 1267 */, TRICORE_INS_XOR_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_LT_rr /* 1268 */, TRICORE_INS_XOR_LT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_NE_rc /* 1269 */, TRICORE_INS_XOR_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_NE_rr /* 1270 */, TRICORE_INS_XOR_NE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_T /* 1271 */, TRICORE_INS_XOR_T,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_rc /* 1272 */, TRICORE_INS_XOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_rr /* 1273 */, TRICORE_INS_XOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  TRICORE_XOR_srr /* 1274 */, TRICORE_INS_XOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { TRICORE_FEATURE_HasV120_UP, 0 }, 0, 0
+  #endif
+},
diff --git a/arch/TriCore/TriCoreGenCSMappingInsnName.inc b/arch/TriCore/TriCoreGenCSMappingInsnName.inc
new file mode 100644
index 0000000000..3a97b857d8
--- /dev/null
+++ b/arch/TriCore/TriCoreGenCSMappingInsnName.inc
@@ -0,0 +1,403 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  "xor.t", // TRICORE_INS_XOR_T
+  "absdifs.b", // TRICORE_INS_ABSDIFS_B
+  "absdifs.h", // TRICORE_INS_ABSDIFS_H
+  "absdifs", // TRICORE_INS_ABSDIFS
+  "absdif.b", // TRICORE_INS_ABSDIF_B
+  "absdif.h", // TRICORE_INS_ABSDIF_H
+  "absdif", // TRICORE_INS_ABSDIF
+  "abss.b", // TRICORE_INS_ABSS_B
+  "abss.h", // TRICORE_INS_ABSS_H
+  "abss", // TRICORE_INS_ABSS
+  "abs.b", // TRICORE_INS_ABS_B
+  "abs.h", // TRICORE_INS_ABS_H
+  "abs", // TRICORE_INS_ABS
+  "addc", // TRICORE_INS_ADDC
+  "addih.a", // TRICORE_INS_ADDIH_A
+  "addih", // TRICORE_INS_ADDIH
+  "addi", // TRICORE_INS_ADDI
+  "addsc.at", // TRICORE_INS_ADDSC_AT
+  "addsc.a", // TRICORE_INS_ADDSC_A
+  "adds.bu", // TRICORE_INS_ADDS_BU
+  "adds.b", // TRICORE_INS_ADDS_B
+  "adds.h", // TRICORE_INS_ADDS_H
+  "adds.hu", // TRICORE_INS_ADDS_HU
+  "adds.u", // TRICORE_INS_ADDS_U
+  "adds", // TRICORE_INS_ADDS
+  "addx", // TRICORE_INS_ADDX
+  "add.a", // TRICORE_INS_ADD_A
+  "add.b", // TRICORE_INS_ADD_B
+  "add.f", // TRICORE_INS_ADD_F
+  "add.h", // TRICORE_INS_ADD_H
+  "add", // TRICORE_INS_ADD
+  "andn.t", // TRICORE_INS_ANDN_T
+  "andn", // TRICORE_INS_ANDN
+  "and.andn.t", // TRICORE_INS_AND_ANDN_T
+  "and.and.t", // TRICORE_INS_AND_AND_T
+  "and.eq", // TRICORE_INS_AND_EQ
+  "and.ge.u", // TRICORE_INS_AND_GE_U
+  "and.ge", // TRICORE_INS_AND_GE
+  "and.lt.u", // TRICORE_INS_AND_LT_U
+  "and.lt", // TRICORE_INS_AND_LT
+  "and.ne", // TRICORE_INS_AND_NE
+  "and.nor.t", // TRICORE_INS_AND_NOR_T
+  "and.or.t", // TRICORE_INS_AND_OR_T
+  "and.t", // TRICORE_INS_AND_T
+  "and", // TRICORE_INS_AND
+  "bisr", // TRICORE_INS_BISR
+  "bmerge", // TRICORE_INS_BMERGE
+  "bsplit", // TRICORE_INS_BSPLIT
+  "cachea.i", // TRICORE_INS_CACHEA_I
+  "cachea.wi", // TRICORE_INS_CACHEA_WI
+  "cachea.w", // TRICORE_INS_CACHEA_W
+  "cachei.i", // TRICORE_INS_CACHEI_I
+  "cachei.wi", // TRICORE_INS_CACHEI_WI
+  "cachei.w", // TRICORE_INS_CACHEI_W
+  "caddn.a", // TRICORE_INS_CADDN_A
+  "caddn", // TRICORE_INS_CADDN
+  "cadd.a", // TRICORE_INS_CADD_A
+  "cadd", // TRICORE_INS_CADD
+  "calla", // TRICORE_INS_CALLA
+  "calli", // TRICORE_INS_CALLI
+  "call", // TRICORE_INS_CALL
+  "clo.b", // TRICORE_INS_CLO_B
+  "clo.h", // TRICORE_INS_CLO_H
+  "clo", // TRICORE_INS_CLO
+  "cls.b", // TRICORE_INS_CLS_B
+  "cls.h", // TRICORE_INS_CLS_H
+  "cls", // TRICORE_INS_CLS
+  "clz.b", // TRICORE_INS_CLZ_B
+  "clz.h", // TRICORE_INS_CLZ_H
+  "clz", // TRICORE_INS_CLZ
+  "cmovn", // TRICORE_INS_CMOVN
+  "cmov", // TRICORE_INS_CMOV
+  "cmpswap.w", // TRICORE_INS_CMPSWAP_W
+  "cmp.f", // TRICORE_INS_CMP_F
+  "crc32b.w", // TRICORE_INS_CRC32B_W
+  "crc32l.w", // TRICORE_INS_CRC32L_W
+  "crc32.b", // TRICORE_INS_CRC32_B
+  "crcn", // TRICORE_INS_CRCN
+  "csubn.a", // TRICORE_INS_CSUBN_A
+  "csubn", // TRICORE_INS_CSUBN
+  "csub.a", // TRICORE_INS_CSUB_A
+  "csub", // TRICORE_INS_CSUB
+  "debug", // TRICORE_INS_DEBUG
+  "dextr", // TRICORE_INS_DEXTR
+  "difsc.a", // TRICORE_INS_DIFSC_A
+  "disable", // TRICORE_INS_DISABLE
+  "div.f", // TRICORE_INS_DIV_F
+  "div.u", // TRICORE_INS_DIV_U
+  "div", // TRICORE_INS_DIV
+  "dsync", // TRICORE_INS_DSYNC
+  "dvadj", // TRICORE_INS_DVADJ
+  "dvinit.bu", // TRICORE_INS_DVINIT_BU
+  "dvinit.b", // TRICORE_INS_DVINIT_B
+  "dvinit.hu", // TRICORE_INS_DVINIT_HU
+  "dvinit.h", // TRICORE_INS_DVINIT_H
+  "dvinit.u", // TRICORE_INS_DVINIT_U
+  "dvinit", // TRICORE_INS_DVINIT
+  "dvstep.u", // TRICORE_INS_DVSTEP_U
+  "dvstep", // TRICORE_INS_DVSTEP
+  "enable", // TRICORE_INS_ENABLE
+  "eqany.b", // TRICORE_INS_EQANY_B
+  "eqany.h", // TRICORE_INS_EQANY_H
+  "eqz.a", // TRICORE_INS_EQZ_A
+  "eq.a", // TRICORE_INS_EQ_A
+  "eq.b", // TRICORE_INS_EQ_B
+  "eq.h", // TRICORE_INS_EQ_H
+  "eq.w", // TRICORE_INS_EQ_W
+  "eq", // TRICORE_INS_EQ
+  "extr.u", // TRICORE_INS_EXTR_U
+  "extr", // TRICORE_INS_EXTR
+  "fcalla", // TRICORE_INS_FCALLA
+  "fcalli", // TRICORE_INS_FCALLI
+  "fcall", // TRICORE_INS_FCALL
+  "fret", // TRICORE_INS_FRET
+  "ftohp", // TRICORE_INS_FTOHP
+  "ftoiz", // TRICORE_INS_FTOIZ
+  "ftoi", // TRICORE_INS_FTOI
+  "ftoq31z", // TRICORE_INS_FTOQ31Z
+  "ftoq31", // TRICORE_INS_FTOQ31
+  "ftouz", // TRICORE_INS_FTOUZ
+  "ftou", // TRICORE_INS_FTOU
+  "ge.a", // TRICORE_INS_GE_A
+  "ge.u", // TRICORE_INS_GE_U
+  "ge", // TRICORE_INS_GE
+  "hptof", // TRICORE_INS_HPTOF
+  "imask", // TRICORE_INS_IMASK
+  "insert", // TRICORE_INS_INSERT
+  "insn.t", // TRICORE_INS_INSN_T
+  "ins.t", // TRICORE_INS_INS_T
+  "isync", // TRICORE_INS_ISYNC
+  "itof", // TRICORE_INS_ITOF
+  "ixmax.u", // TRICORE_INS_IXMAX_U
+  "ixmax", // TRICORE_INS_IXMAX
+  "ixmin.u", // TRICORE_INS_IXMIN_U
+  "ixmin", // TRICORE_INS_IXMIN
+  "ja", // TRICORE_INS_JA
+  "jeq.a", // TRICORE_INS_JEQ_A
+  "jeq", // TRICORE_INS_JEQ
+  "jgez", // TRICORE_INS_JGEZ
+  "jge.u", // TRICORE_INS_JGE_U
+  "jge", // TRICORE_INS_JGE
+  "jgtz", // TRICORE_INS_JGTZ
+  "ji", // TRICORE_INS_JI
+  "jla", // TRICORE_INS_JLA
+  "jlez", // TRICORE_INS_JLEZ
+  "jli", // TRICORE_INS_JLI
+  "jltz", // TRICORE_INS_JLTZ
+  "jlt.u", // TRICORE_INS_JLT_U
+  "jlt", // TRICORE_INS_JLT
+  "jl", // TRICORE_INS_JL
+  "jned", // TRICORE_INS_JNED
+  "jnei", // TRICORE_INS_JNEI
+  "jne.a", // TRICORE_INS_JNE_A
+  "jne", // TRICORE_INS_JNE
+  "jnz.a", // TRICORE_INS_JNZ_A
+  "jnz.t", // TRICORE_INS_JNZ_T
+  "jnz", // TRICORE_INS_JNZ
+  "jz.a", // TRICORE_INS_JZ_A
+  "jz.t", // TRICORE_INS_JZ_T
+  "jz", // TRICORE_INS_JZ
+  "j", // TRICORE_INS_J
+  "ldlcx", // TRICORE_INS_LDLCX
+  "ldmst", // TRICORE_INS_LDMST
+  "lducx", // TRICORE_INS_LDUCX
+  "ld.a", // TRICORE_INS_LD_A
+  "ld.bu", // TRICORE_INS_LD_BU
+  "ld.b", // TRICORE_INS_LD_B
+  "ld.da", // TRICORE_INS_LD_DA
+  "ld.d", // TRICORE_INS_LD_D
+  "ld.hu", // TRICORE_INS_LD_HU
+  "ld.h", // TRICORE_INS_LD_H
+  "ld.q", // TRICORE_INS_LD_Q
+  "ld.w", // TRICORE_INS_LD_W
+  "lea", // TRICORE_INS_LEA
+  "lha", // TRICORE_INS_LHA
+  "loopu", // TRICORE_INS_LOOPU
+  "loop", // TRICORE_INS_LOOP
+  "lt.a", // TRICORE_INS_LT_A
+  "lt.b", // TRICORE_INS_LT_B
+  "lt.bu", // TRICORE_INS_LT_BU
+  "lt.h", // TRICORE_INS_LT_H
+  "lt.hu", // TRICORE_INS_LT_HU
+  "lt.u", // TRICORE_INS_LT_U
+  "lt.w", // TRICORE_INS_LT_W
+  "lt.wu", // TRICORE_INS_LT_WU
+  "lt", // TRICORE_INS_LT
+  "maddms.h", // TRICORE_INS_MADDMS_H
+  "maddms.u", // TRICORE_INS_MADDMS_U
+  "maddms", // TRICORE_INS_MADDMS
+  "maddm.h", // TRICORE_INS_MADDM_H
+  "maddm.q", // TRICORE_INS_MADDM_Q
+  "maddm.u", // TRICORE_INS_MADDM_U
+  "maddm", // TRICORE_INS_MADDM
+  "maddrs.h", // TRICORE_INS_MADDRS_H
+  "maddrs.q", // TRICORE_INS_MADDRS_Q
+  "maddr.h", // TRICORE_INS_MADDR_H
+  "maddr.q", // TRICORE_INS_MADDR_Q
+  "maddsums.h", // TRICORE_INS_MADDSUMS_H
+  "maddsum.h", // TRICORE_INS_MADDSUM_H
+  "maddsurs.h", // TRICORE_INS_MADDSURS_H
+  "maddsur.h", // TRICORE_INS_MADDSUR_H
+  "maddsus.h", // TRICORE_INS_MADDSUS_H
+  "maddsu.h", // TRICORE_INS_MADDSU_H
+  "madds.h", // TRICORE_INS_MADDS_H
+  "madds.q", // TRICORE_INS_MADDS_Q
+  "madds.u", // TRICORE_INS_MADDS_U
+  "madds", // TRICORE_INS_MADDS
+  "madd.f", // TRICORE_INS_MADD_F
+  "madd.h", // TRICORE_INS_MADD_H
+  "madd.q", // TRICORE_INS_MADD_Q
+  "madd.u", // TRICORE_INS_MADD_U
+  "madd", // TRICORE_INS_MADD
+  "max.b", // TRICORE_INS_MAX_B
+  "max.bu", // TRICORE_INS_MAX_BU
+  "max.h", // TRICORE_INS_MAX_H
+  "max.hu", // TRICORE_INS_MAX_HU
+  "max.u", // TRICORE_INS_MAX_U
+  "max", // TRICORE_INS_MAX
+  "mfcr", // TRICORE_INS_MFCR
+  "min.b", // TRICORE_INS_MIN_B
+  "min.bu", // TRICORE_INS_MIN_BU
+  "min.h", // TRICORE_INS_MIN_H
+  "min.hu", // TRICORE_INS_MIN_HU
+  "min.u", // TRICORE_INS_MIN_U
+  "min", // TRICORE_INS_MIN
+  "movh.a", // TRICORE_INS_MOVH_A
+  "movh", // TRICORE_INS_MOVH
+  "movz.a", // TRICORE_INS_MOVZ_A
+  "mov.aa", // TRICORE_INS_MOV_AA
+  "mov.a", // TRICORE_INS_MOV_A
+  "mov.d", // TRICORE_INS_MOV_D
+  "mov.u", // TRICORE_INS_MOV_U
+  "mov", // TRICORE_INS_MOV
+  "msubadms.h", // TRICORE_INS_MSUBADMS_H
+  "msubadm.h", // TRICORE_INS_MSUBADM_H
+  "msubadrs.h", // TRICORE_INS_MSUBADRS_H
+  "msubadr.h", // TRICORE_INS_MSUBADR_H
+  "msubads.h", // TRICORE_INS_MSUBADS_H
+  "msubad.h", // TRICORE_INS_MSUBAD_H
+  "msubms.h", // TRICORE_INS_MSUBMS_H
+  "msubms.u", // TRICORE_INS_MSUBMS_U
+  "msubms", // TRICORE_INS_MSUBMS
+  "msubm.h", // TRICORE_INS_MSUBM_H
+  "msubm.q", // TRICORE_INS_MSUBM_Q
+  "msubm.u", // TRICORE_INS_MSUBM_U
+  "msubm", // TRICORE_INS_MSUBM
+  "msubrs.h", // TRICORE_INS_MSUBRS_H
+  "msubrs.q", // TRICORE_INS_MSUBRS_Q
+  "msubr.h", // TRICORE_INS_MSUBR_H
+  "msubr.q", // TRICORE_INS_MSUBR_Q
+  "msubs.h", // TRICORE_INS_MSUBS_H
+  "msubs.q", // TRICORE_INS_MSUBS_Q
+  "msubs.u", // TRICORE_INS_MSUBS_U
+  "msubs", // TRICORE_INS_MSUBS
+  "msub.f", // TRICORE_INS_MSUB_F
+  "msub.h", // TRICORE_INS_MSUB_H
+  "msub.q", // TRICORE_INS_MSUB_Q
+  "msub.u", // TRICORE_INS_MSUB_U
+  "msub", // TRICORE_INS_MSUB
+  "mtcr", // TRICORE_INS_MTCR
+  "mulms.h", // TRICORE_INS_MULMS_H
+  "mulm.h", // TRICORE_INS_MULM_H
+  "mulm.u", // TRICORE_INS_MULM_U
+  "mulm", // TRICORE_INS_MULM
+  "mulr.h", // TRICORE_INS_MULR_H
+  "mulr.q", // TRICORE_INS_MULR_Q
+  "muls.u", // TRICORE_INS_MULS_U
+  "muls", // TRICORE_INS_MULS
+  "mul.f", // TRICORE_INS_MUL_F
+  "mul.h", // TRICORE_INS_MUL_H
+  "mul.q", // TRICORE_INS_MUL_Q
+  "mul.u", // TRICORE_INS_MUL_U
+  "mul", // TRICORE_INS_MUL
+  "nand.t", // TRICORE_INS_NAND_T
+  "nand", // TRICORE_INS_NAND
+  "nez.a", // TRICORE_INS_NEZ_A
+  "ne.a", // TRICORE_INS_NE_A
+  "ne", // TRICORE_INS_NE
+  "nop", // TRICORE_INS_NOP
+  "nor.t", // TRICORE_INS_NOR_T
+  "nor", // TRICORE_INS_NOR
+  "not", // TRICORE_INS_NOT
+  "orn.t", // TRICORE_INS_ORN_T
+  "orn", // TRICORE_INS_ORN
+  "or.andn.t", // TRICORE_INS_OR_ANDN_T
+  "or.and.t", // TRICORE_INS_OR_AND_T
+  "or.eq", // TRICORE_INS_OR_EQ
+  "or.ge.u", // TRICORE_INS_OR_GE_U
+  "or.ge", // TRICORE_INS_OR_GE
+  "or.lt.u", // TRICORE_INS_OR_LT_U
+  "or.lt", // TRICORE_INS_OR_LT
+  "or.ne", // TRICORE_INS_OR_NE
+  "or.nor.t", // TRICORE_INS_OR_NOR_T
+  "or.or.t", // TRICORE_INS_OR_OR_T
+  "or.t", // TRICORE_INS_OR_T
+  "or", // TRICORE_INS_OR
+  "pack", // TRICORE_INS_PACK
+  "parity", // TRICORE_INS_PARITY
+  "popcnt.w", // TRICORE_INS_POPCNT_W
+  "q31tof", // TRICORE_INS_Q31TOF
+  "qseed.f", // TRICORE_INS_QSEED_F
+  "restore", // TRICORE_INS_RESTORE
+  "ret", // TRICORE_INS_RET
+  "rfe", // TRICORE_INS_RFE
+  "rfm", // TRICORE_INS_RFM
+  "rslcx", // TRICORE_INS_RSLCX
+  "rstv", // TRICORE_INS_RSTV
+  "rsubs.u", // TRICORE_INS_RSUBS_U
+  "rsubs", // TRICORE_INS_RSUBS
+  "rsub", // TRICORE_INS_RSUB
+  "sat.bu", // TRICORE_INS_SAT_BU
+  "sat.b", // TRICORE_INS_SAT_B
+  "sat.hu", // TRICORE_INS_SAT_HU
+  "sat.h", // TRICORE_INS_SAT_H
+  "seln.a", // TRICORE_INS_SELN_A
+  "seln", // TRICORE_INS_SELN
+  "sel.a", // TRICORE_INS_SEL_A
+  "sel", // TRICORE_INS_SEL
+  "shas", // TRICORE_INS_SHAS
+  "sha.b", // TRICORE_INS_SHA_B
+  "sha.h", // TRICORE_INS_SHA_H
+  "sha", // TRICORE_INS_SHA
+  "shuffle", // TRICORE_INS_SHUFFLE
+  "sh.andn.t", // TRICORE_INS_SH_ANDN_T
+  "sh.and.t", // TRICORE_INS_SH_AND_T
+  "sh.b", // TRICORE_INS_SH_B
+  "sh.eq", // TRICORE_INS_SH_EQ
+  "sh.ge.u", // TRICORE_INS_SH_GE_U
+  "sh.ge", // TRICORE_INS_SH_GE
+  "sh.h", // TRICORE_INS_SH_H
+  "sh.lt.u", // TRICORE_INS_SH_LT_U
+  "sh.lt", // TRICORE_INS_SH_LT
+  "sh.nand.t", // TRICORE_INS_SH_NAND_T
+  "sh.ne", // TRICORE_INS_SH_NE
+  "sh.nor.t", // TRICORE_INS_SH_NOR_T
+  "sh.orn.t", // TRICORE_INS_SH_ORN_T
+  "sh.or.t", // TRICORE_INS_SH_OR_T
+  "sh.xnor.t", // TRICORE_INS_SH_XNOR_T
+  "sh.xor.t", // TRICORE_INS_SH_XOR_T
+  "sh", // TRICORE_INS_SH
+  "stlcx", // TRICORE_INS_STLCX
+  "stucx", // TRICORE_INS_STUCX
+  "st.a", // TRICORE_INS_ST_A
+  "st.b", // TRICORE_INS_ST_B
+  "st.da", // TRICORE_INS_ST_DA
+  "st.d", // TRICORE_INS_ST_D
+  "st.h", // TRICORE_INS_ST_H
+  "st.q", // TRICORE_INS_ST_Q
+  "st.t", // TRICORE_INS_ST_T
+  "st.w", // TRICORE_INS_ST_W
+  "subc", // TRICORE_INS_SUBC
+  "subsc.a", // TRICORE_INS_SUBSC_A
+  "subs.bu", // TRICORE_INS_SUBS_BU
+  "subs.b", // TRICORE_INS_SUBS_B
+  "subs.hu", // TRICORE_INS_SUBS_HU
+  "subs.h", // TRICORE_INS_SUBS_H
+  "subs.u", // TRICORE_INS_SUBS_U
+  "subs", // TRICORE_INS_SUBS
+  "subx", // TRICORE_INS_SUBX
+  "sub.a", // TRICORE_INS_SUB_A
+  "sub.b", // TRICORE_INS_SUB_B
+  "sub.f", // TRICORE_INS_SUB_F
+  "sub.h", // TRICORE_INS_SUB_H
+  "sub", // TRICORE_INS_SUB
+  "svlcx", // TRICORE_INS_SVLCX
+  "swapmsk.w", // TRICORE_INS_SWAPMSK_W
+  "swap.a", // TRICORE_INS_SWAP_A
+  "swap.w", // TRICORE_INS_SWAP_W
+  "syscall", // TRICORE_INS_SYSCALL
+  "tlbdemap", // TRICORE_INS_TLBDEMAP
+  "tlbflush.a", // TRICORE_INS_TLBFLUSH_A
+  "tlbflush.b", // TRICORE_INS_TLBFLUSH_B
+  "tlbmap", // TRICORE_INS_TLBMAP
+  "tlbprobe.a", // TRICORE_INS_TLBPROBE_A
+  "tlbprobe.i", // TRICORE_INS_TLBPROBE_I
+  "trapsv", // TRICORE_INS_TRAPSV
+  "trapv", // TRICORE_INS_TRAPV
+  "unpack", // TRICORE_INS_UNPACK
+  "updfl", // TRICORE_INS_UPDFL
+  "utof", // TRICORE_INS_UTOF
+  "wait", // TRICORE_INS_WAIT
+  "xnor.t", // TRICORE_INS_XNOR_T
+  "xnor", // TRICORE_INS_XNOR
+  "xor.eq", // TRICORE_INS_XOR_EQ
+  "xor.ge.u", // TRICORE_INS_XOR_GE_U
+  "xor.ge", // TRICORE_INS_XOR_GE
+  "xor.lt.u", // TRICORE_INS_XOR_LT_U
+  "xor.lt", // TRICORE_INS_XOR_LT
+  "xor.ne", // TRICORE_INS_XOR_NE
+  "xor", // TRICORE_INS_XOR
diff --git a/arch/TriCore/TriCoreGenCSMappingInsnOp.inc b/arch/TriCore/TriCoreGenCSMappingInsnOp.inc
new file mode 100644
index 0000000000..435c53265d
--- /dev/null
+++ b/arch/TriCore/TriCoreGenCSMappingInsnOp.inc
@@ -0,0 +1,7994 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{{{ /* TRICORE_PHI (0) - TRICORE_INS_INVALID - PHINODE */
+ 0 
+}}},
+{{{ /* TRICORE_INLINEASM (1) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_INLINEASM_BR (2) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_CFI_INSTRUCTION (3) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_EH_LABEL (4) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_GC_LABEL (5) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_ANNOTATION_LABEL (6) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_KILL (7) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_EXTRACT_SUBREG (8) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_INSERT_SUBREG (9) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_IMPLICIT_DEF (10) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_SUBREG_TO_REG (11) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_COPY_TO_REGCLASS (12) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_DBG_VALUE (13) - TRICORE_INS_INVALID - DBG_VALUE */
+ 0 
+}}},
+{{{ /* TRICORE_DBG_VALUE_LIST (14) - TRICORE_INS_INVALID - DBG_VALUE_LIST */
+ 0 
+}}},
+{{{ /* TRICORE_DBG_INSTR_REF (15) - TRICORE_INS_INVALID - DBG_INSTR_REF */
+ 0 
+}}},
+{{{ /* TRICORE_DBG_PHI (16) - TRICORE_INS_INVALID - DBG_PHI */
+ 0 
+}}},
+{{{ /* TRICORE_DBG_LABEL (17) - TRICORE_INS_INVALID - DBG_LABEL */
+ 0 
+}}},
+{{{ /* TRICORE_REG_SEQUENCE (18) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_COPY (19) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_BUNDLE (20) - TRICORE_INS_INVALID - BUNDLE */
+ 0 
+}}},
+{{{ /* TRICORE_LIFETIME_START (21) - TRICORE_INS_INVALID - LIFETIME_START */
+ 0 
+}}},
+{{{ /* TRICORE_LIFETIME_END (22) - TRICORE_INS_INVALID - LIFETIME_END */
+ 0 
+}}},
+{{{ /* TRICORE_PSEUDO_PROBE (23) - TRICORE_INS_INVALID - PSEUDO_PROBE */
+ 0 
+}}},
+{{{ /* TRICORE_ARITH_FENCE (24) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_STACKMAP (25) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_FENTRY_CALL (26) - TRICORE_INS_INVALID - # FEntry call */
+ 0 
+}}},
+{{{ /* TRICORE_PATCHPOINT (27) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_LOAD_STACK_GUARD (28) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_PREALLOCATED_SETUP (29) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_PREALLOCATED_ARG (30) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_STATEPOINT (31) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_LOCAL_ESCAPE (32) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_FAULTING_OP (33) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_PATCHABLE_OP (34) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_PATCHABLE_FUNCTION_ENTER (35) - TRICORE_INS_INVALID - # XRay Function Enter. */
+ 0 
+}}},
+{{{ /* TRICORE_PATCHABLE_RET (36) - TRICORE_INS_INVALID - # XRay Function Patchable RET. */
+ 0 
+}}},
+{{{ /* TRICORE_PATCHABLE_FUNCTION_EXIT (37) - TRICORE_INS_INVALID - # XRay Function Exit. */
+ 0 
+}}},
+{{{ /* TRICORE_PATCHABLE_TAIL_CALL (38) - TRICORE_INS_INVALID - # XRay Tail Call Exit. */
+ 0 
+}}},
+{{{ /* TRICORE_PATCHABLE_EVENT_CALL (39) - TRICORE_INS_INVALID - # XRay Custom Event Log. */
+ 0 
+}}},
+{{{ /* TRICORE_PATCHABLE_TYPED_EVENT_CALL (40) - TRICORE_INS_INVALID - # XRay Typed Event Log. */
+ 0 
+}}},
+{{{ /* TRICORE_ICALL_BRANCH_FUNNEL (41) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_MEMBARRIER (42) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ASSERT_SEXT (43) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ASSERT_ZEXT (44) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ASSERT_ALIGN (45) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ADD (46) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SUB (47) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_MUL (48) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SDIV (49) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UDIV (50) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SREM (51) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UREM (52) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SDIVREM (53) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UDIVREM (54) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_AND (55) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_OR (56) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_XOR (57) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_IMPLICIT_DEF (58) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_PHI (59) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FRAME_INDEX (60) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_GLOBAL_VALUE (61) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_EXTRACT (62) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UNMERGE_VALUES (63) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INSERT (64) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_MERGE_VALUES (65) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BUILD_VECTOR (66) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BUILD_VECTOR_TRUNC (67) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_CONCAT_VECTORS (68) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_PTRTOINT (69) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INTTOPTR (70) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BITCAST (71) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FREEZE (72) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INTRINSIC_FPTRUNC_ROUND (73) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INTRINSIC_TRUNC (74) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INTRINSIC_ROUND (75) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INTRINSIC_LRINT (76) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INTRINSIC_ROUNDEVEN (77) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_READCYCLECOUNTER (78) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_LOAD (79) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SEXTLOAD (80) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ZEXTLOAD (81) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INDEXED_LOAD (82) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INDEXED_SEXTLOAD (83) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INDEXED_ZEXTLOAD (84) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_STORE (85) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INDEXED_STORE (86) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMIC_CMPXCHG_WITH_SUCCESS (87) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMIC_CMPXCHG (88) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_XCHG (89) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_ADD (90) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_SUB (91) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_AND (92) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_NAND (93) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_OR (94) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_XOR (95) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_MAX (96) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_MIN (97) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_UMAX (98) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_UMIN (99) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_FADD (100) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_FSUB (101) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_FMAX (102) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_FMIN (103) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_UINC_WRAP (104) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ATOMICRMW_UDEC_WRAP (105) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FENCE (106) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BRCOND (107) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BRINDIRECT (108) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INVOKE_REGION_START (109) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INTRINSIC (110) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INTRINSIC_W_SIDE_EFFECTS (111) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ANYEXT (112) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_TRUNC (113) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_CONSTANT (114) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FCONSTANT (115) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VASTART (116) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VAARG (117) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SEXT (118) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SEXT_INREG (119) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ZEXT (120) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SHL (121) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_LSHR (122) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ASHR (123) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FSHL (124) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FSHR (125) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ROTR (126) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ROTL (127) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ICMP (128) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FCMP (129) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SELECT (130) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UADDO (131) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UADDE (132) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_USUBO (133) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_USUBE (134) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SADDO (135) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SADDE (136) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SSUBO (137) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SSUBE (138) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UMULO (139) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SMULO (140) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UMULH (141) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SMULH (142) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UADDSAT (143) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SADDSAT (144) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_USUBSAT (145) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SSUBSAT (146) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_USHLSAT (147) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SSHLSAT (148) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SMULFIX (149) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UMULFIX (150) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SMULFIXSAT (151) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UMULFIXSAT (152) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SDIVFIX (153) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UDIVFIX (154) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SDIVFIXSAT (155) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UDIVFIXSAT (156) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FADD (157) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FSUB (158) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FMUL (159) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FMA (160) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FMAD (161) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FDIV (162) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FREM (163) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FPOW (164) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FPOWI (165) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FEXP (166) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FEXP2 (167) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FLOG (168) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FLOG2 (169) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FLOG10 (170) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FNEG (171) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FPEXT (172) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FPTRUNC (173) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FPTOSI (174) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FPTOUI (175) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SITOFP (176) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UITOFP (177) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FABS (178) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FCOPYSIGN (179) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_IS_FPCLASS (180) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FCANONICALIZE (181) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FMINNUM (182) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FMAXNUM (183) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FMINNUM_IEEE (184) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FMAXNUM_IEEE (185) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FMINIMUM (186) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FMAXIMUM (187) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_PTR_ADD (188) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_PTRMASK (189) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SMIN (190) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SMAX (191) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UMIN (192) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UMAX (193) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ABS (194) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_LROUND (195) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_LLROUND (196) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BR (197) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BRJT (198) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_INSERT_VECTOR_ELT (199) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_EXTRACT_VECTOR_ELT (200) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SHUFFLE_VECTOR (201) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_CTTZ (202) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_CTTZ_ZERO_UNDEF (203) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_CTLZ (204) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_CTLZ_ZERO_UNDEF (205) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_CTPOP (206) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BSWAP (207) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BITREVERSE (208) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FCEIL (209) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FCOS (210) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FSIN (211) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FSQRT (212) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FFLOOR (213) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FRINT (214) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_FNEARBYINT (215) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_ADDRSPACE_CAST (216) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BLOCK_ADDR (217) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_JUMP_TABLE (218) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_DYN_STACKALLOC (219) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_STRICT_FADD (220) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_STRICT_FSUB (221) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_STRICT_FMUL (222) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_STRICT_FDIV (223) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_STRICT_FREM (224) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_STRICT_FMA (225) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_STRICT_FSQRT (226) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_READ_REGISTER (227) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_WRITE_REGISTER (228) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_MEMCPY (229) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_MEMCPY_INLINE (230) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_MEMMOVE (231) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_MEMSET (232) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_BZERO (233) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_SEQ_FADD (234) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_SEQ_FMUL (235) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_FADD (236) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_FMUL (237) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_FMAX (238) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_FMIN (239) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_ADD (240) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_MUL (241) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_AND (242) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_OR (243) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_XOR (244) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_SMAX (245) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_SMIN (246) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_UMAX (247) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_VECREDUCE_UMIN (248) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_SBFX (249) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{{{ /* TRICORE_G_UBFX (250) - TRICORE_INS_INVALID -  */
+ 0 
+}}},
+{ /* TRICORE_ABSDIFS_B_rr_v110 (251) - TriCore_INS_ABSDIFS_B - absdifs.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABSDIFS_H_rr (252) - TriCore_INS_ABSDIFS_H - absdifs.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABSDIFS_rc (253) - TriCore_INS_ABSDIFS - absdifs $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABSDIFS_rr (254) - TriCore_INS_ABSDIFS - absdifs $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABSDIF_B_rr (255) - TriCore_INS_ABSDIF_B - absdif.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABSDIF_H_rr (256) - TriCore_INS_ABSDIF_H - absdif.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABSDIF_rc (257) - TriCore_INS_ABSDIF - absdif $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_ABSDIF_rr (258) - TriCore_INS_ABSDIF - absdif $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABSS_B_rr_v110 (259) - TriCore_INS_ABSS_B - abss.b $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABSS_H_rr (260) - TriCore_INS_ABSS_H - abss.h $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABSS_rr (261) - TriCore_INS_ABSS - abss $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABS_B_rr (262) - TriCore_INS_ABS_B - abs.b $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABS_H_rr (263) - TriCore_INS_ABS_H - abs.h $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ABS_rr (264) - TriCore_INS_ABS - abs $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDC_rc (265) - TriCore_INS_ADDC - addc $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_ADDC_rr (266) - TriCore_INS_ADDC - addc $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDIH_A_rlc (267) - TriCore_INS_ADDIH_A - addih.a $d, $s1, $const16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const16 */
+  { 0 }
+}},
+{ /* TRICORE_ADDIH_rlc (268) - TriCore_INS_ADDIH - addih $d, $s1, $const16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const16 */
+  { 0 }
+}},
+{ /* TRICORE_ADDI_rlc (269) - TriCore_INS_ADDI - addi $d, $s1, $const16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const16 */
+  { 0 }
+}},
+{ /* TRICORE_ADDSC_AT_rr (270) - TriCore_INS_ADDSC_AT - addsc.at $d, $s2, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDSC_AT_rr_v110 (271) - TriCore_INS_ADDSC_AT - addsc.at $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDSC_A_rr (272) - TriCore_INS_ADDSC_A - addsc.a $d, $s2, $s1, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_ADDSC_A_rr_v110 (273) - TriCore_INS_ADDSC_A - addsc.a $d, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_ADDSC_A_srrs (274) - TriCore_INS_ADDSC_A - addsc.a $d, $s2, %d15, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_ADDSC_A_srrs_v110 (275) - TriCore_INS_ADDSC_A - addsc.a $d, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_ADDS_BU_rr_v110 (276) - TriCore_INS_ADDS_BU - adds.bu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDS_B_rr (277) - TriCore_INS_ADDS_B - adds.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDS_H (278) - TriCore_INS_ADDS_H - adds.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDS_HU (279) - TriCore_INS_ADDS_HU - adds.hu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDS_U (280) - TriCore_INS_ADDS_U - adds.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDS_U_rc (281) - TriCore_INS_ADDS_U - adds.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_ADDS_rc (282) - TriCore_INS_ADDS - adds $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_ADDS_rr (283) - TriCore_INS_ADDS - adds $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDS_srr (284) - TriCore_INS_ADDS - adds $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADDX_rc (285) - TriCore_INS_ADDX - addx $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_ADDX_rr (286) - TriCore_INS_ADDX - addx $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_A_rr (287) - TriCore_INS_ADD_A - add.a $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_A_src (288) - TriCore_INS_ADD_A - add.a $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_A_srr (289) - TriCore_INS_ADD_A - add.a $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_B_rr (290) - TriCore_INS_ADD_B - add.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_F_rrr (291) - TriCore_INS_ADD_F - add.f $d, $s3, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_H_rr (292) - TriCore_INS_ADD_H - add.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_rc (293) - TriCore_INS_ADD - add $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_rr (294) - TriCore_INS_ADD - add $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_src (295) - TriCore_INS_ADD - add $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_src_15a (296) - TriCore_INS_ADD - add %d15, $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_src_a15 (297) - TriCore_INS_ADD - add $d, %d15, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_srr (298) - TriCore_INS_ADD - add $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_srr_15a (299) - TriCore_INS_ADD - add %d15, $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ADD_srr_a15 (300) - TriCore_INS_ADD - add $d, %d15, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ANDN_T (301) - TriCore_INS_ANDN_T - andn.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_ANDN_rc (302) - TriCore_INS_ANDN - andn $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_ANDN_rr (303) - TriCore_INS_ANDN - andn $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_AND_ANDN_T (304) - TriCore_INS_AND_ANDN_T - and.andn.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_AND_AND_T (305) - TriCore_INS_AND_AND_T - and.and.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_AND_EQ_rc (306) - TriCore_INS_AND_EQ - and.eq $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_AND_EQ_rr (307) - TriCore_INS_AND_EQ - and.eq $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_AND_GE_U_rc (308) - TriCore_INS_AND_GE_U - and.ge.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_AND_GE_U_rr (309) - TriCore_INS_AND_GE_U - and.ge.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_AND_GE_rc (310) - TriCore_INS_AND_GE - and.ge $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_AND_GE_rr (311) - TriCore_INS_AND_GE - and.ge $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_AND_LT_U_rc (312) - TriCore_INS_AND_LT_U - and.lt.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_AND_LT_U_rr (313) - TriCore_INS_AND_LT_U - and.lt.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_AND_LT_rc (314) - TriCore_INS_AND_LT - and.lt $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_AND_LT_rr (315) - TriCore_INS_AND_LT - and.lt $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_AND_NE_rc (316) - TriCore_INS_AND_NE - and.ne $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_AND_NE_rr (317) - TriCore_INS_AND_NE - and.ne $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_AND_NOR_T (318) - TriCore_INS_AND_NOR_T - and.nor.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_AND_OR_T (319) - TriCore_INS_AND_OR_T - and.or.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_AND_T (320) - TriCore_INS_AND_T - and.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_AND_rc (321) - TriCore_INS_AND - and $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_AND_rr (322) - TriCore_INS_AND - and $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_AND_sc (323) - TriCore_INS_AND - and %d15, $const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_AND_sc_v110 (324) - TriCore_INS_AND - and %d15, $const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_AND_srr (325) - TriCore_INS_AND - and $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_AND_srr_v110 (326) - TriCore_INS_AND - and $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_BISR_rc (327) - TriCore_INS_BISR - bisr $const9 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_BISR_rc_v161 (328) - TriCore_INS_BISR - bisr $const9 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_BISR_sc (329) - TriCore_INS_BISR - bisr $const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_BISR_sc_v110 (330) - TriCore_INS_BISR - bisr $const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_BMERGAE_rr_v110 (331) - TriCore_INS_BMERGE - bmerge $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_BMERGE_rr (332) - TriCore_INS_BMERGE - bmerge $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_BSPLIT_rr (333) - TriCore_INS_BSPLIT - bsplit $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_BSPLIT_rr_v110 (334) - TriCore_INS_BSPLIT - bsplit $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_I_bo_bso (335) - TriCore_INS_CACHEA_I - cachea.i [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_I_bo_c (336) - TriCore_INS_CACHEA_I - cachea.i [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_I_bo_pos (337) - TriCore_INS_CACHEA_I - cachea.i [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_I_bo_pre (338) - TriCore_INS_CACHEA_I - cachea.i [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_I_bo_r (339) - TriCore_INS_CACHEA_I - cachea.i [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_WI_bo_bso (340) - TriCore_INS_CACHEA_WI - cachea.wi [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_WI_bo_c (341) - TriCore_INS_CACHEA_WI - cachea.wi [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_WI_bo_pos (342) - TriCore_INS_CACHEA_WI - cachea.wi [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_WI_bo_pre (343) - TriCore_INS_CACHEA_WI - cachea.wi [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_WI_bo_r (344) - TriCore_INS_CACHEA_WI - cachea.wi [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_W_bo_bso (345) - TriCore_INS_CACHEA_W - cachea.w [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_W_bo_c (346) - TriCore_INS_CACHEA_W - cachea.w [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_W_bo_pos (347) - TriCore_INS_CACHEA_W - cachea.w [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_W_bo_pre (348) - TriCore_INS_CACHEA_W - cachea.w [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEA_W_bo_r (349) - TriCore_INS_CACHEA_W - cachea.w [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEI_I_bo_bso (350) - TriCore_INS_CACHEI_I - cachei.i [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEI_I_bo_pos (351) - TriCore_INS_CACHEI_I - cachei.i [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEI_I_bo_pre (352) - TriCore_INS_CACHEI_I - cachei.i [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEI_WI_bo_bso (353) - TriCore_INS_CACHEI_WI - cachei.wi [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEI_WI_bo_pos (354) - TriCore_INS_CACHEI_WI - cachei.wi [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEI_WI_bo_pre (355) - TriCore_INS_CACHEI_WI - cachei.wi [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEI_W_bo_bso (356) - TriCore_INS_CACHEI_W - cachei.w [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEI_W_bo_pos (357) - TriCore_INS_CACHEI_W - cachei.w [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CACHEI_W_bo_pre (358) - TriCore_INS_CACHEI_W - cachei.w [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CADDN_A_rcr_v110 (359) - TriCore_INS_CADDN_A - caddn.a $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_CADDN_A_rrr_v110 (360) - TriCore_INS_CADDN_A - caddn.a $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_CADDN_rcr (361) - TriCore_INS_CADDN - caddn $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_CADDN_rrr (362) - TriCore_INS_CADDN - caddn $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_CADDN_src (363) - TriCore_INS_CADDN - caddn $d, %d15, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_CADDN_srr_v110 (364) - TriCore_INS_CADDN - caddn $d, %d15, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CADD_A_rcr_v110 (365) - TriCore_INS_CADD_A - cadd.a $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_CADD_A_rrr_v110 (366) - TriCore_INS_CADD_A - cadd.a $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_CADD_rcr (367) - TriCore_INS_CADD - cadd $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_CADD_rrr (368) - TriCore_INS_CADD - cadd $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_CADD_src (369) - TriCore_INS_CADD - cadd $d, %d15, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_CADD_srr_v110 (370) - TriCore_INS_CADD - cadd $d, %d15, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CALLA_b (371) - TriCore_INS_CALLA - calla $disp24 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp24 */
+  { 0 }
+}},
+{ /* TRICORE_CALLI_rr (372) - TriCore_INS_CALLI - calli $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CALLI_rr_v110 (373) - TriCore_INS_CALLI - calli $s2 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CALL_b (374) - TriCore_INS_CALL - call $disp24 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp24 */
+  { 0 }
+}},
+{ /* TRICORE_CALL_sb (375) - TriCore_INS_CALL - call $disp8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp8 */
+  { 0 }
+}},
+{ /* TRICORE_CLO_B_rr_v110 (376) - TriCore_INS_CLO_B - clo.b $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CLO_H_rr (377) - TriCore_INS_CLO_H - clo.h $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CLO_rr (378) - TriCore_INS_CLO - clo $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CLS_B_rr_v110 (379) - TriCore_INS_CLS_B - cls.b $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CLS_H_rr (380) - TriCore_INS_CLS_H - cls.h $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CLS_rr (381) - TriCore_INS_CLS - cls $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CLZ_B_rr_v110 (382) - TriCore_INS_CLZ_B - clz.b $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CLZ_H_rr (383) - TriCore_INS_CLZ_H - clz.h $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CLZ_rr (384) - TriCore_INS_CLZ - clz $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_CMOVN_src (385) - TriCore_INS_CMOVN - cmovn $d, %d15, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_CMOVN_srr (386) - TriCore_INS_CMOVN - cmovn $d, %d15, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CMOV_src (387) - TriCore_INS_CMOV - cmov $d, %d15, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_CMOV_srr (388) - TriCore_INS_CMOV - cmov $d, %d15, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CMPSWAP_W_bo_bso (389) - TriCore_INS_CMPSWAP_W - cmpswap.w [$s2]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CMPSWAP_W_bo_c (390) - TriCore_INS_CMPSWAP_W - cmpswap.w [${s2}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CMPSWAP_W_bo_pos (391) - TriCore_INS_CMPSWAP_W - cmpswap.w [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CMPSWAP_W_bo_pre (392) - TriCore_INS_CMPSWAP_W - cmpswap.w [+$s2]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_CMPSWAP_W_bo_r (393) - TriCore_INS_CMPSWAP_W - cmpswap.w [${s2}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CMP_F_rr (394) - TriCore_INS_CMP_F - cmp.f $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CRC32B_W_rr (395) - TriCore_INS_CRC32B_W - crc32b.w $d, $s2, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CRC32L_W_rr (396) - TriCore_INS_CRC32L_W - crc32l.w $d, $s2, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CRC32_B_rr (397) - TriCore_INS_CRC32_B - crc32.b $d, $s2, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_CRCN_rrr (398) - TriCore_INS_CRCN - crcn $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_CSUBN_A__rrr_v110 (399) - TriCore_INS_CSUBN_A - csubn.a $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_CSUBN_rrr (400) - TriCore_INS_CSUBN - csubn $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_CSUB_A__rrr_v110 (401) - TriCore_INS_CSUB_A - csub.a $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_CSUB_rrr (402) - TriCore_INS_CSUB - csub $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_DEBUG_sr (403) - TriCore_INS_DEBUG - debug */
+{
+  { 0 }
+}},
+{ /* TRICORE_DEBUG_sys (404) - TriCore_INS_DEBUG - debug */
+{
+  { 0 }
+}},
+{ /* TRICORE_DEXTR_rrpw (405) - TriCore_INS_DEXTR - dextr $d, $s1, $s2, $pos */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_DEXTR_rrrr (406) - TriCore_INS_DEXTR - dextr $d, $s1, $s2, $s3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_DIFSC_A_rr_v110 (407) - TriCore_INS_DIFSC_A - difsc.a $d, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_DISABLE_sys (408) - TriCore_INS_DISABLE - disable */
+{
+  { 0 }
+}},
+{ /* TRICORE_DISABLE_sys_1 (409) - TriCore_INS_DISABLE - disable $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_DIV_F_rr (410) - TriCore_INS_DIV_F - div.f $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DIV_U_rr (411) - TriCore_INS_DIV_U - div.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DIV_rr (412) - TriCore_INS_DIV - div $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DSYNC_sys (413) - TriCore_INS_DSYNC - dsync */
+{
+  { 0 }
+}},
+{ /* TRICORE_DVADJ_rrr (414) - TriCore_INS_DVADJ - dvadj $d, $s3, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_DVADJ_rrr_v110 (415) - TriCore_INS_DVADJ - dvadj $d, $s3, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_DVADJ_srr_v110 (416) - TriCore_INS_DVADJ - dvadj $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_BU_rr (417) - TriCore_INS_DVINIT_BU - dvinit.bu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_BU_rr_v110 (418) - TriCore_INS_DVINIT_BU - dvinit.bu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_B_rr (419) - TriCore_INS_DVINIT_B - dvinit.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_B_rr_v110 (420) - TriCore_INS_DVINIT_B - dvinit.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_HU_rr (421) - TriCore_INS_DVINIT_HU - dvinit.hu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_HU_rr_v110 (422) - TriCore_INS_DVINIT_HU - dvinit.hu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_H_rr (423) - TriCore_INS_DVINIT_H - dvinit.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_H_rr_v110 (424) - TriCore_INS_DVINIT_H - dvinit.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_U_rr (425) - TriCore_INS_DVINIT_U - dvinit.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_U_rr_v110 (426) - TriCore_INS_DVINIT_U - dvinit.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_rr (427) - TriCore_INS_DVINIT - dvinit $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVINIT_rr_v110 (428) - TriCore_INS_DVINIT - dvinit $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVSTEP_U_rrr (429) - TriCore_INS_DVSTEP_U - dvstep.u $d, $s3, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_DVSTEP_U_rrrv110 (430) - TriCore_INS_DVSTEP_U - dvstep.u $d, $s3, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_DVSTEP_Uv110 (431) - TriCore_INS_DVSTEP_U - dvstep.u $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_DVSTEP_rrr (432) - TriCore_INS_DVSTEP - dvstep $d, $s3, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_DVSTEP_rrrv110 (433) - TriCore_INS_DVSTEP - dvstep $d, $s3, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_DVSTEPv110 (434) - TriCore_INS_DVSTEP - dvstep $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_ENABLE_sys (435) - TriCore_INS_ENABLE - enable */
+{
+  { 0 }
+}},
+{ /* TRICORE_EQANY_B_rc (436) - TriCore_INS_EQANY_B - eqany.b $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_EQANY_B_rr (437) - TriCore_INS_EQANY_B - eqany.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_EQANY_H_rc (438) - TriCore_INS_EQANY_H - eqany.h $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_EQANY_H_rr (439) - TriCore_INS_EQANY_H - eqany.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_EQZ_A_rr (440) - TriCore_INS_EQZ_A - eqz.a $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_EQ_A_rr (441) - TriCore_INS_EQ_A - eq.a $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_EQ_B_rr (442) - TriCore_INS_EQ_B - eq.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_EQ_H_rr (443) - TriCore_INS_EQ_H - eq.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_EQ_W_rr (444) - TriCore_INS_EQ_W - eq.w $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_EQ_rc (445) - TriCore_INS_EQ - eq $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_EQ_rr (446) - TriCore_INS_EQ - eq $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_EQ_src (447) - TriCore_INS_EQ - eq %d15, $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_EQ_srr (448) - TriCore_INS_EQ - eq %d15, $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_EXTR_U_rrpw (449) - TriCore_INS_EXTR_U - extr.u $d, $s1, $pos, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_EXTR_U_rrrr (450) - TriCore_INS_EXTR_U - extr.u $d, $s1, $s3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_EXTR_U_rrrw (451) - TriCore_INS_EXTR_U - extr.u $d, $s1, $s3, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_EXTR_rrpw (452) - TriCore_INS_EXTR - extr $d, $s1, $pos, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_EXTR_rrrr (453) - TriCore_INS_EXTR - extr $d, $s1, $s3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_EXTR_rrrw (454) - TriCore_INS_EXTR - extr $d, $s1, $s3, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_FCALLA_b (455) - TriCore_INS_FCALLA - fcalla $disp24 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp24 */
+  { 0 }
+}},
+{ /* TRICORE_FCALLA_i (456) - TriCore_INS_FCALLI - fcalli $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_FCALL_b (457) - TriCore_INS_FCALL - fcall $disp24 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp24 */
+  { 0 }
+}},
+{ /* TRICORE_FRET_sr (458) - TriCore_INS_FRET - fret */
+{
+  { 0 }
+}},
+{ /* TRICORE_FRET_sys (459) - TriCore_INS_FRET - fret */
+{
+  { 0 }
+}},
+{ /* TRICORE_FTOHP_rr (460) - TriCore_INS_FTOHP - ftohp $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_FTOIZ_rr (461) - TriCore_INS_FTOIZ - ftoiz $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_FTOI_rr (462) - TriCore_INS_FTOI - ftoi $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_FTOQ31Z_rr (463) - TriCore_INS_FTOQ31Z - ftoq31z $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_FTOQ31_rr (464) - TriCore_INS_FTOQ31 - ftoq31 $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_FTOUZ_rr (465) - TriCore_INS_FTOUZ - ftouz $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_FTOU_rr (466) - TriCore_INS_FTOU - ftou $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_GE_A_rr (467) - TriCore_INS_GE_A - ge.a $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_GE_U_rc (468) - TriCore_INS_GE_U - ge.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_GE_U_rr (469) - TriCore_INS_GE_U - ge.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_GE_rc (470) - TriCore_INS_GE - ge $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_GE_rr (471) - TriCore_INS_GE - ge $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_HPTOF_rr (472) - TriCore_INS_HPTOF - hptof $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_IMASK_rcpw (473) - TriCore_INS_IMASK - imask $d, $const4, $pos, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_IMASK_rcrw (474) - TriCore_INS_IMASK - imask $d, $const4, $s3, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_IMASK_rrpw (475) - TriCore_INS_IMASK - imask $d, $s2, $pos, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_IMASK_rrrw (476) - TriCore_INS_IMASK - imask $d, $s2, $s3, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_INSERT_rcpw (477) - TriCore_INS_INSERT - insert $d, $s1, $const4, $pos, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_INSERT_rcrr (478) - TriCore_INS_INSERT - insert $d, $s1, $const4, $s3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_INSERT_rcrw (479) - TriCore_INS_INSERT - insert $d, $s1, $const4, $s3, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_INSERT_rrpw (480) - TriCore_INS_INSERT - insert $d, $s1, $s2, $pos, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_INSERT_rrrr (481) - TriCore_INS_INSERT - insert $d, $s1, $s2, $s3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_INSERT_rrrw (482) - TriCore_INS_INSERT - insert $d, $s1, $s2, $s3, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { 0 }
+}},
+{ /* TRICORE_INSN_T (483) - TriCore_INS_INSN_T - insn.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_INS_T (484) - TriCore_INS_INS_T - ins.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_ISYNC_sys (485) - TriCore_INS_ISYNC - isync */
+{
+  { 0 }
+}},
+{ /* TRICORE_ITOF_rr (486) - TriCore_INS_ITOF - itof $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_IXMAX_U_rrr (487) - TriCore_INS_IXMAX_U - ixmax.u $d, $s3, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_IXMAX_rrr (488) - TriCore_INS_IXMAX - ixmax $d, $s3, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_IXMIN_U_rrr (489) - TriCore_INS_IXMIN_U - ixmin.u $d, $s3, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_IXMIN_rrr (490) - TriCore_INS_IXMIN - ixmin $d, $s3, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_JA_b (491) - TriCore_INS_JA - ja $disp24 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp24 */
+  { 0 }
+}},
+{ /* TRICORE_JEQ_A_brr (492) - TriCore_INS_JEQ_A - jeq.a $s1, $s2, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JEQ_brc (493) - TriCore_INS_JEQ - jeq $s1, $const4, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JEQ_brr (494) - TriCore_INS_JEQ - jeq $s1, $s2, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JEQ_sbc1 (495) - TriCore_INS_JEQ - jeq %d15, $const4, $disp4 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_JEQ_sbc2 (496) - TriCore_INS_JEQ - jeq %d15, $const4, $disp4 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_JEQ_sbc_v110 (497) - TriCore_INS_JEQ - jeq %d15, $const4, $disp4 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_JEQ_sbr1 (498) - TriCore_INS_JEQ - jeq %d15, $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JEQ_sbr2 (499) - TriCore_INS_JEQ - jeq %d15, $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JEQ_sbr_v110 (500) - TriCore_INS_JEQ - jeq %d15, $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JGEZ_sbr (501) - TriCore_INS_JGEZ - jgez $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JGEZ_sbr_v110 (502) - TriCore_INS_JGEZ - jgez $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JGE_U_brc (503) - TriCore_INS_JGE_U - jge.u $s1, $const4, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JGE_U_brr (504) - TriCore_INS_JGE_U - jge.u $s1, $s2, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JGE_brc (505) - TriCore_INS_JGE - jge $s1, $const4, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JGE_brr (506) - TriCore_INS_JGE - jge $s1, $s2, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JGTZ_sbr (507) - TriCore_INS_JGTZ - jgtz $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JGTZ_sbr_v110 (508) - TriCore_INS_JGTZ - jgtz $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JI_rr (509) - TriCore_INS_JI - ji $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_JI_rr_v110 (510) - TriCore_INS_JI - ji $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_JI_sbr_v110 (511) - TriCore_INS_JI - ji $s2 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_JI_sr (512) - TriCore_INS_JI - ji $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_JLA_b (513) - TriCore_INS_JLA - jla $disp24 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp24 */
+  { 0 }
+}},
+{ /* TRICORE_JLEZ_sbr (514) - TriCore_INS_JLEZ - jlez $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JLEZ_sbr_v110 (515) - TriCore_INS_JLEZ - jlez $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JLI_rr (516) - TriCore_INS_JLI - jli $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_JLI_rr_v110 (517) - TriCore_INS_JLI - jli $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_JLTZ_sbr (518) - TriCore_INS_JLTZ - jltz $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JLTZ_sbr_v110 (519) - TriCore_INS_JLTZ - jltz $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JLT_U_brc (520) - TriCore_INS_JLT_U - jlt.u $s1, $const4, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JLT_U_brr (521) - TriCore_INS_JLT_U - jlt.u $s1, $s2, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JLT_brc (522) - TriCore_INS_JLT - jlt $s1, $const4, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JLT_brr (523) - TriCore_INS_JLT - jlt $s1, $s2, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JL_b (524) - TriCore_INS_JL - jl $disp24 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp24 */
+  { 0 }
+}},
+{ /* TRICORE_JNED_brc (525) - TriCore_INS_JNED - jned $s1, $const4, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JNED_brr (526) - TriCore_INS_JNED - jned $s1, $s2, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JNEI_brc (527) - TriCore_INS_JNEI - jnei $s1, $const4, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JNEI_brr (528) - TriCore_INS_JNEI - jnei $s1, $s2, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JNE_A_brr (529) - TriCore_INS_JNE_A - jne.a $s1, $s2, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JNE_brc (530) - TriCore_INS_JNE - jne $s1, $const4, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JNE_brr (531) - TriCore_INS_JNE - jne $s1, $s2, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JNE_sbc1 (532) - TriCore_INS_JNE - jne %d15, $const4, $disp4 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_JNE_sbc2 (533) - TriCore_INS_JNE - jne %d15, $const4, $disp4 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_JNE_sbc_v110 (534) - TriCore_INS_JNE - jne %d15, $const4, $disp4 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_JNE_sbr1 (535) - TriCore_INS_JNE - jne %d15, $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JNE_sbr2 (536) - TriCore_INS_JNE - jne %d15, $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JNE_sbr_v110 (537) - TriCore_INS_JNE - jne %d15, $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JNZ_A_brr (538) - TriCore_INS_JNZ_A - jnz.a $s1, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JNZ_A_sbr (539) - TriCore_INS_JNZ_A - jnz.a $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JNZ_T_brn (540) - TriCore_INS_JNZ_T - jnz.t $s1, $n, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JNZ_T_sbrn (541) - TriCore_INS_JNZ_T - jnz.t %d15, $n, $disp4 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JNZ_T_sbrn_v110 (542) - TriCore_INS_JNZ_T - jnz.t %d15, $n, $disp4 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JNZ_sb (543) - TriCore_INS_JNZ - jnz %d15, $disp8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp8 */
+  { 0 }
+}},
+{ /* TRICORE_JNZ_sb_v110 (544) - TriCore_INS_JNZ - jnz %d15, $disp8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp8 */
+  { 0 }
+}},
+{ /* TRICORE_JNZ_sbr (545) - TriCore_INS_JNZ - jnz $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JNZ_sbr_v110 (546) - TriCore_INS_JNZ - jnz $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JZ_A_brr (547) - TriCore_INS_JZ_A - jz.a $s1, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JZ_A_sbr (548) - TriCore_INS_JZ_A - jz.a $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JZ_T_brn (549) - TriCore_INS_JZ_T - jz.t $s1, $n, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_JZ_T_sbrn (550) - TriCore_INS_JZ_T - jz.t %d15, $n, $disp4 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JZ_T_sbrn_v110 (551) - TriCore_INS_JZ_T - jz.t %d15, $n, $disp4 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JZ_sb (552) - TriCore_INS_JZ - jz %d15, $disp8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp8 */
+  { 0 }
+}},
+{ /* TRICORE_JZ_sb_v110 (553) - TriCore_INS_JZ - jz %d15, $disp8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp8 */
+  { 0 }
+}},
+{ /* TRICORE_JZ_sbr (554) - TriCore_INS_JZ - jz $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_JZ_sbr_v110 (555) - TriCore_INS_JZ - jz $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_J_b (556) - TriCore_INS_J - j $disp24 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp24 */
+  { 0 }
+}},
+{ /* TRICORE_J_sb (557) - TriCore_INS_J - j $disp8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp8 */
+  { 0 }
+}},
+{ /* TRICORE_J_sb_v110 (558) - TriCore_INS_J - j $disp8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp8 */
+  { 0 }
+}},
+{ /* TRICORE_LDLCX_abs (559) - TriCore_INS_LDLCX - ldlcx $off18 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LDLCX_bo_bso (560) - TriCore_INS_LDLCX - ldlcx [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LDMST_abs (561) - TriCore_INS_LDMST - ldmst $off18, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LDMST_bo_bso (562) - TriCore_INS_LDMST - ldmst [$s2]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LDMST_bo_c (563) - TriCore_INS_LDMST - ldmst [${s2}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LDMST_bo_pos (564) - TriCore_INS_LDMST - ldmst [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LDMST_bo_pre (565) - TriCore_INS_LDMST - ldmst [+$s2]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LDMST_bo_r (566) - TriCore_INS_LDMST - ldmst [${s2}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LDUCX_abs (567) - TriCore_INS_LDUCX - lducx $off18 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LDUCX_bo_bso (568) - TriCore_INS_LDUCX - lducx [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_abs (569) - TriCore_INS_LD_A - ld.a $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_bo_bso (570) - TriCore_INS_LD_A - ld.a $d, [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_bo_c (571) - TriCore_INS_LD_A - ld.a $d, [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_bo_pos (572) - TriCore_INS_LD_A - ld.a $s1, [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_bo_pre (573) - TriCore_INS_LD_A - ld.a $s1, [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_bo_r (574) - TriCore_INS_LD_A - ld.a $d, [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_bol (575) - TriCore_INS_LD_A - ld.a $s1, [$s2]$off16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_sc (576) - TriCore_INS_LD_A - ld.a %a15, [%sp]$const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_slr (577) - TriCore_INS_LD_A - ld.a $d, [$s2] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_slr_post (578) - TriCore_INS_LD_A - ld.a $d, [${s2}+] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_slr_post_v110 (579) - TriCore_INS_LD_A - ld.a $d, [${s2}+] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_slr_v110 (580) - TriCore_INS_LD_A - ld.a $d, [$s2] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_slro (581) - TriCore_INS_LD_A - ld.a $d, [%a15]$off4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_slro_v110 (582) - TriCore_INS_LD_A - ld.a $d, [%a15]$off4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_sro (583) - TriCore_INS_LD_A - ld.a %a15, [$s2]$off4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_A_sro_v110 (584) - TriCore_INS_LD_A - ld.a %a15, [$s2]$off4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_abs (585) - TriCore_INS_LD_BU - ld.bu $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_bo_bso (586) - TriCore_INS_LD_BU - ld.bu $d, [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_bo_c (587) - TriCore_INS_LD_BU - ld.bu $d, [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_bo_pos (588) - TriCore_INS_LD_BU - ld.bu $s1, [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_bo_pre (589) - TriCore_INS_LD_BU - ld.bu $s1, [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_bo_r (590) - TriCore_INS_LD_BU - ld.bu $d, [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_bol (591) - TriCore_INS_LD_BU - ld.bu $s1, [$s2]$off16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_slr (592) - TriCore_INS_LD_BU - ld.bu $d, [$s2] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_slr_post (593) - TriCore_INS_LD_BU - ld.bu $d, [${s2}+] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_slr_post_v110 (594) - TriCore_INS_LD_BU - ld.bu $d, [${s2}+] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_slr_v110 (595) - TriCore_INS_LD_BU - ld.bu $d, [$s2] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_slro (596) - TriCore_INS_LD_BU - ld.bu $d, [%a15]$off4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_slro_v110 (597) - TriCore_INS_LD_BU - ld.bu $d, [%a15]$off4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_sro (598) - TriCore_INS_LD_BU - ld.bu %d15, [$s2]$off4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_BU_sro_v110 (599) - TriCore_INS_LD_BU - ld.bu %d15, [$s2]$off4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_abs (600) - TriCore_INS_LD_B - ld.b $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_bo_bso (601) - TriCore_INS_LD_B - ld.b $d, [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_bo_c (602) - TriCore_INS_LD_B - ld.b $d, [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_bo_pos (603) - TriCore_INS_LD_B - ld.b $s1, [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_bo_pre (604) - TriCore_INS_LD_B - ld.b $s1, [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_bo_r (605) - TriCore_INS_LD_B - ld.b $d, [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_bol (606) - TriCore_INS_LD_B - ld.b $s1, [$s2]$off16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_slr_post_v110 (607) - TriCore_INS_LD_B - ld.b $d, [${s2}+] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_slr_v110 (608) - TriCore_INS_LD_B - ld.b $d, [$s2] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_slro_v110 (609) - TriCore_INS_LD_B - ld.b $d, [%a15]$off4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_B_sro_v110 (610) - TriCore_INS_LD_B - ld.b %d15, [$s2]$off4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_DA_abs (611) - TriCore_INS_LD_DA - ld.da $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LD_DA_bo_bso (612) - TriCore_INS_LD_DA - ld.da $d, [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_DA_bo_c (613) - TriCore_INS_LD_DA - ld.da $d, [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_DA_bo_pos (614) - TriCore_INS_LD_DA - ld.da $s1, [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_DA_bo_pre (615) - TriCore_INS_LD_DA - ld.da $s1, [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_DA_bo_r (616) - TriCore_INS_LD_DA - ld.da $d, [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_D_abs (617) - TriCore_INS_LD_D - ld.d $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LD_D_bo_bso (618) - TriCore_INS_LD_D - ld.d $d, [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_D_bo_c (619) - TriCore_INS_LD_D - ld.d $d, [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_D_bo_pos (620) - TriCore_INS_LD_D - ld.d $s1, [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_D_bo_pre (621) - TriCore_INS_LD_D - ld.d $s1, [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_D_bo_r (622) - TriCore_INS_LD_D - ld.d $d, [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_HU_abs (623) - TriCore_INS_LD_HU - ld.hu $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LD_HU_bo_bso (624) - TriCore_INS_LD_HU - ld.hu $d, [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_HU_bo_c (625) - TriCore_INS_LD_HU - ld.hu $d, [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_HU_bo_pos (626) - TriCore_INS_LD_HU - ld.hu $s1, [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_HU_bo_pre (627) - TriCore_INS_LD_HU - ld.hu $s1, [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_HU_bo_r (628) - TriCore_INS_LD_HU - ld.hu $d, [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_HU_bol (629) - TriCore_INS_LD_HU - ld.hu $s1, [$s2]$off16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_abs (630) - TriCore_INS_LD_H - ld.h $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_bo_bso (631) - TriCore_INS_LD_H - ld.h $d, [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_bo_c (632) - TriCore_INS_LD_H - ld.h $d, [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_bo_pos (633) - TriCore_INS_LD_H - ld.h $s1, [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_bo_pre (634) - TriCore_INS_LD_H - ld.h $s1, [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_bo_r (635) - TriCore_INS_LD_H - ld.h $d, [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_bol (636) - TriCore_INS_LD_H - ld.h $s1, [$s2]$off16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_slr (637) - TriCore_INS_LD_H - ld.h $d, [$s2] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_slr_post (638) - TriCore_INS_LD_H - ld.h $d, [${s2}+] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_slr_post_v110 (639) - TriCore_INS_LD_H - ld.h $d, [${s2}+] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_slr_v110 (640) - TriCore_INS_LD_H - ld.h $d, [$s2] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_slro (641) - TriCore_INS_LD_H - ld.h $d, [%a15]$off4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_slro_v110 (642) - TriCore_INS_LD_H - ld.h $d, [%a15]$off4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_sro (643) - TriCore_INS_LD_H - ld.h %d15, [$s2]$off4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_H_sro_v110 (644) - TriCore_INS_LD_H - ld.h %d15, [$s2]$off4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_Q_abs (645) - TriCore_INS_LD_Q - ld.q $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LD_Q_bo_bso (646) - TriCore_INS_LD_Q - ld.q $d, [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_Q_bo_c (647) - TriCore_INS_LD_Q - ld.q $d, [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_Q_bo_pos (648) - TriCore_INS_LD_Q - ld.q $s1, [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_Q_bo_pre (649) - TriCore_INS_LD_Q - ld.q $s1, [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_Q_bo_r (650) - TriCore_INS_LD_Q - ld.q $d, [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_abs (651) - TriCore_INS_LD_W - ld.w $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_bo_bso (652) - TriCore_INS_LD_W - ld.w $d, [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_bo_c (653) - TriCore_INS_LD_W - ld.w $d, [${s2}+c]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_bo_pos (654) - TriCore_INS_LD_W - ld.w $s1, [${s2}+]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_bo_pre (655) - TriCore_INS_LD_W - ld.w $s1, [+${s2}]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_bo_r (656) - TriCore_INS_LD_W - ld.w $d, [${s2}+r] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_bol (657) - TriCore_INS_LD_W - ld.w $s1, [$s2]$off16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_sc (658) - TriCore_INS_LD_W - ld.w %d15, [%sp]$const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_slr (659) - TriCore_INS_LD_W - ld.w $d, [$s2] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_slr_post (660) - TriCore_INS_LD_W - ld.w $d, [${s2}+] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_slr_post_v110 (661) - TriCore_INS_LD_W - ld.w $d, [${s2}+] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_slr_v110 (662) - TriCore_INS_LD_W - ld.w $d, [$s2] */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_slro (663) - TriCore_INS_LD_W - ld.w $d, [%a15]$off4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_slro_v110 (664) - TriCore_INS_LD_W - ld.w $d, [%a15]$off4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_sro (665) - TriCore_INS_LD_W - ld.w %d15, [$s2]$off4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LD_W_sro_v110 (666) - TriCore_INS_LD_W - ld.w %d15, [$s2]$off4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_LEA_abs (667) - TriCore_INS_LEA - lea $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LEA_bo_bso (668) - TriCore_INS_LEA - lea $d, [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_LEA_bol (669) - TriCore_INS_LEA - lea $s1, [$s2]$off16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_LHA_abs (670) - TriCore_INS_LHA - lha $d, $off18 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_LOOPU_brr (671) - TriCore_INS_LOOPU - loopu $disp15 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_LOOP_brr (672) - TriCore_INS_LOOP - loop $s1, $disp15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp15 */
+  { 0 }
+}},
+{ /* TRICORE_LOOP_sbr (673) - TriCore_INS_LOOP - loop $s2, $disp4 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* disp4 */
+  { 0 }
+}},
+{ /* TRICORE_LT_A_rr (674) - TriCore_INS_LT_A - lt.a $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LT_B (675) - TriCore_INS_LT_B - lt.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LT_BU (676) - TriCore_INS_LT_BU - lt.bu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LT_H (677) - TriCore_INS_LT_H - lt.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LT_HU (678) - TriCore_INS_LT_HU - lt.hu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LT_U_rc (679) - TriCore_INS_LT_U - lt.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_LT_U_rr (680) - TriCore_INS_LT_U - lt.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LT_U_srcv110 (681) - TriCore_INS_LT_U - lt.u %d15, $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_LT_U_srrv110 (682) - TriCore_INS_LT_U - lt.u %d15, $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LT_W (683) - TriCore_INS_LT_W - lt.w $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LT_WU (684) - TriCore_INS_LT_WU - lt.wu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LT_rc (685) - TriCore_INS_LT - lt $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_LT_rr (686) - TriCore_INS_LT - lt $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_LT_src (687) - TriCore_INS_LT - lt %d15, $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_LT_srr (688) - TriCore_INS_LT - lt %d15, $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MADDMS_H_rrr1_LL (689) - TriCore_INS_MADDMS_H - maddms.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDMS_H_rrr1_LU (690) - TriCore_INS_MADDMS_H - maddms.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDMS_H_rrr1_UL (691) - TriCore_INS_MADDMS_H - maddms.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDMS_H_rrr1_UU (692) - TriCore_INS_MADDMS_H - maddms.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDMS_U_rcr_v110 (693) - TriCore_INS_MADDMS_U - maddms.u $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADDMS_U_rrr2_v110 (694) - TriCore_INS_MADDMS_U - maddms.u $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADDMS_rcr_v110 (695) - TriCore_INS_MADDMS - maddms $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADDMS_rrr2_v110 (696) - TriCore_INS_MADDMS - maddms $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADDM_H_rrr1_LL (697) - TriCore_INS_MADDM_H - maddm.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDM_H_rrr1_LU (698) - TriCore_INS_MADDM_H - maddm.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDM_H_rrr1_UL (699) - TriCore_INS_MADDM_H - maddm.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDM_H_rrr1_UU (700) - TriCore_INS_MADDM_H - maddm.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDM_H_rrr1_v110 (701) - TriCore_INS_MADDM_H - maddm.h $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDM_Q_rrr1_v110 (702) - TriCore_INS_MADDM_Q - maddm.q $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDM_U_rcr_v110 (703) - TriCore_INS_MADDM_U - maddm.u $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADDM_U_rrr2_v110 (704) - TriCore_INS_MADDM_U - maddm.u $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADDM_rcr_v110 (705) - TriCore_INS_MADDM - maddm $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADDM_rrr2_v110 (706) - TriCore_INS_MADDM - maddm $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADDRS_H_rrr1_LL (707) - TriCore_INS_MADDRS_H - maddrs.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDRS_H_rrr1_LU (708) - TriCore_INS_MADDRS_H - maddrs.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDRS_H_rrr1_UL (709) - TriCore_INS_MADDRS_H - maddrs.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDRS_H_rrr1_UL_2 (710) - TriCore_INS_MADDRS_H - maddrs.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDRS_H_rrr1_UU (711) - TriCore_INS_MADDRS_H - maddrs.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDRS_H_rrr1_v110 (712) - TriCore_INS_MADDRS_H - maddrs.h $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDRS_Q_rrr1_L_L (713) - TriCore_INS_MADDRS_Q - maddrs.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDRS_Q_rrr1_U_U (714) - TriCore_INS_MADDRS_Q - maddrs.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDRS_Q_rrr1_v110 (715) - TriCore_INS_MADDRS_Q - maddrs.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDR_H_rrr1_LL (716) - TriCore_INS_MADDR_H - maddr.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDR_H_rrr1_LU (717) - TriCore_INS_MADDR_H - maddr.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDR_H_rrr1_UL (718) - TriCore_INS_MADDR_H - maddr.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDR_H_rrr1_UL_2 (719) - TriCore_INS_MADDR_H - maddr.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDR_H_rrr1_UU (720) - TriCore_INS_MADDR_H - maddr.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDR_H_rrr1_v110 (721) - TriCore_INS_MADDR_H - maddr.h $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDR_Q_rrr1_L_L (722) - TriCore_INS_MADDR_Q - maddr.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDR_Q_rrr1_U_U (723) - TriCore_INS_MADDR_Q - maddr.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDR_Q_rrr1_v110 (724) - TriCore_INS_MADDR_Q - maddr.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUMS_H_rrr1_LL (725) - TriCore_INS_MADDSUMS_H - maddsums.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUMS_H_rrr1_LU (726) - TriCore_INS_MADDSUMS_H - maddsums.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUMS_H_rrr1_UL (727) - TriCore_INS_MADDSUMS_H - maddsums.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUMS_H_rrr1_UU (728) - TriCore_INS_MADDSUMS_H - maddsums.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUM_H_rrr1_LL (729) - TriCore_INS_MADDSUM_H - maddsum.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUM_H_rrr1_LU (730) - TriCore_INS_MADDSUM_H - maddsum.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUM_H_rrr1_UL (731) - TriCore_INS_MADDSUM_H - maddsum.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUM_H_rrr1_UU (732) - TriCore_INS_MADDSUM_H - maddsum.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSURS_H_rrr1_LL (733) - TriCore_INS_MADDSURS_H - maddsurs.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSURS_H_rrr1_LU (734) - TriCore_INS_MADDSURS_H - maddsurs.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSURS_H_rrr1_UL (735) - TriCore_INS_MADDSURS_H - maddsurs.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSURS_H_rrr1_UU (736) - TriCore_INS_MADDSURS_H - maddsurs.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUR_H_rrr1_LL (737) - TriCore_INS_MADDSUR_H - maddsur.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUR_H_rrr1_LU (738) - TriCore_INS_MADDSUR_H - maddsur.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUR_H_rrr1_UL (739) - TriCore_INS_MADDSUR_H - maddsur.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUR_H_rrr1_UU (740) - TriCore_INS_MADDSUR_H - maddsur.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUS_H_rrr1_LL (741) - TriCore_INS_MADDSUS_H - maddsus.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUS_H_rrr1_LU (742) - TriCore_INS_MADDSUS_H - maddsus.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUS_H_rrr1_UL (743) - TriCore_INS_MADDSUS_H - maddsus.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSUS_H_rrr1_UU (744) - TriCore_INS_MADDSUS_H - maddsus.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSU_H_rrr1_LL (745) - TriCore_INS_MADDSU_H - maddsu.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSU_H_rrr1_LU (746) - TriCore_INS_MADDSU_H - maddsu.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSU_H_rrr1_UL (747) - TriCore_INS_MADDSU_H - maddsu.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDSU_H_rrr1_UU (748) - TriCore_INS_MADDSU_H - maddsu.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_H_rrr1_LL (749) - TriCore_INS_MADDS_H - madds.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_H_rrr1_LU (750) - TriCore_INS_MADDS_H - madds.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_H_rrr1_UL (751) - TriCore_INS_MADDS_H - madds.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_H_rrr1_UU (752) - TriCore_INS_MADDS_H - madds.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_H_rrr1_v110 (753) - TriCore_INS_MADDS_H - madds.h $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1 (754) - TriCore_INS_MADDS_Q - madds.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1_L (755) - TriCore_INS_MADDS_Q - madds.q $d, $s3, $s1, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1_L_L (756) - TriCore_INS_MADDS_Q - madds.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1_U (757) - TriCore_INS_MADDS_Q - madds.q $d, $s3, $s1, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1_UU2_v110 (758) - TriCore_INS_MADDS_Q - madds.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1_U_U (759) - TriCore_INS_MADDS_Q - madds.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1_e (760) - TriCore_INS_MADDS_Q - madds.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1_e_L (761) - TriCore_INS_MADDS_Q - madds.q $d, $s3, $s1, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1_e_L_L (762) - TriCore_INS_MADDS_Q - madds.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1_e_U (763) - TriCore_INS_MADDS_Q - madds.q $d, $s3, $s1, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_Q_rrr1_e_U_U (764) - TriCore_INS_MADDS_Q - madds.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_U_rcr (765) - TriCore_INS_MADDS_U - madds.u $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_U_rcr_e (766) - TriCore_INS_MADDS_U - madds.u $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_U_rrr2 (767) - TriCore_INS_MADDS_U - madds.u $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_U_rrr2_e (768) - TriCore_INS_MADDS_U - madds.u $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_rcr (769) - TriCore_INS_MADDS - madds $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_rcr_e (770) - TriCore_INS_MADDS - madds $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_rrr2 (771) - TriCore_INS_MADDS - madds $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADDS_rrr2_e (772) - TriCore_INS_MADDS - madds $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADD_F_rrr (773) - TriCore_INS_MADD_F - madd.f $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADD_H_rrr1_LL (774) - TriCore_INS_MADD_H - madd.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_H_rrr1_LU (775) - TriCore_INS_MADD_H - madd.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_H_rrr1_UL (776) - TriCore_INS_MADD_H - madd.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_H_rrr1_UU (777) - TriCore_INS_MADD_H - madd.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_H_rrr1_v110 (778) - TriCore_INS_MADD_H - madd.h $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1 (779) - TriCore_INS_MADD_Q - madd.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1_L (780) - TriCore_INS_MADD_Q - madd.q $d, $s3, $s1, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1_L_L (781) - TriCore_INS_MADD_Q - madd.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1_U (782) - TriCore_INS_MADD_Q - madd.q $d, $s3, $s1, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1_UU2_v110 (783) - TriCore_INS_MADD_Q - madd.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1_U_U (784) - TriCore_INS_MADD_Q - madd.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1_e (785) - TriCore_INS_MADD_Q - madd.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1_e_L (786) - TriCore_INS_MADD_Q - madd.q $d, $s3, $s1, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1_e_L_L (787) - TriCore_INS_MADD_Q - madd.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1_e_U (788) - TriCore_INS_MADD_Q - madd.q $d, $s3, $s1, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_Q_rrr1_e_U_U (789) - TriCore_INS_MADD_Q - madd.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MADD_U_rcr (790) - TriCore_INS_MADD_U - madd.u $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADD_U_rrr2 (791) - TriCore_INS_MADD_U - madd.u $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADD_rcr (792) - TriCore_INS_MADD - madd $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADD_rcr_e (793) - TriCore_INS_MADD - madd $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MADD_rrr2 (794) - TriCore_INS_MADD - madd $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MADD_rrr2_e (795) - TriCore_INS_MADD - madd $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MAX_B (796) - TriCore_INS_MAX_B - max.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MAX_BU (797) - TriCore_INS_MAX_BU - max.bu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MAX_H (798) - TriCore_INS_MAX_H - max.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MAX_HU (799) - TriCore_INS_MAX_HU - max.hu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MAX_U_rc (800) - TriCore_INS_MAX_U - max.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MAX_U_rr (801) - TriCore_INS_MAX_U - max.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MAX_rc (802) - TriCore_INS_MAX - max $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MAX_rr (803) - TriCore_INS_MAX - max $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MFCR_rlc (804) - TriCore_INS_MFCR - mfcr $d, $const16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const16 */
+  { 0 }
+}},
+{ /* TRICORE_MIN_B (805) - TriCore_INS_MIN_B - min.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MIN_BU (806) - TriCore_INS_MIN_BU - min.bu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MIN_H (807) - TriCore_INS_MIN_H - min.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MIN_HU (808) - TriCore_INS_MIN_HU - min.hu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MIN_U_rc (809) - TriCore_INS_MIN_U - min.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MIN_U_rr (810) - TriCore_INS_MIN_U - min.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MIN_rc (811) - TriCore_INS_MIN - min $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MIN_rr (812) - TriCore_INS_MIN - min $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOVH_A_rlc (813) - TriCore_INS_MOVH_A - movh.a $d, $const16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const16 */
+  { 0 }
+}},
+{ /* TRICORE_MOVH_rlc (814) - TriCore_INS_MOVH - movh $d, $const16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const16 */
+  { 0 }
+}},
+{ /* TRICORE_MOVZ_A_sr (815) - TriCore_INS_MOVZ_A - movz.a $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_AA_rr (816) - TriCore_INS_MOV_AA - mov.aa $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_AA_srr_srr (817) - TriCore_INS_MOV_AA - mov.aa $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_AA_srr_srr_v110 (818) - TriCore_INS_MOV_AA - mov.aa $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_A_rr (819) - TriCore_INS_MOV_A - mov.a $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_A_src (820) - TriCore_INS_MOV_A - mov.a $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_A_srr (821) - TriCore_INS_MOV_A - mov.a $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_A_srr_v110 (822) - TriCore_INS_MOV_A - mov.a $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_D_rr (823) - TriCore_INS_MOV_D - mov.d $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_D_srr_srr (824) - TriCore_INS_MOV_D - mov.d $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_D_srr_srr_v110 (825) - TriCore_INS_MOV_D - mov.d $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_U_rlc (826) - TriCore_INS_MOV_U - mov.u $d, $const16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const16 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_rlc (827) - TriCore_INS_MOV - mov $d, $const16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const16 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_rlc_e (828) - TriCore_INS_MOV - mov $d, $const16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const16 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_rr (829) - TriCore_INS_MOV - mov $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_rr_e (830) - TriCore_INS_MOV - mov $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_rr_eab (831) - TriCore_INS_MOV - mov $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_sc (832) - TriCore_INS_MOV - mov %d15, $const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_sc_v110 (833) - TriCore_INS_MOV - mov %d15, $const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_src (834) - TriCore_INS_MOV - mov $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_src_e (835) - TriCore_INS_MOV - mov $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_MOV_srr (836) - TriCore_INS_MOV - mov $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADMS_H_rrr1_LL (837) - TriCore_INS_MSUBADMS_H - msubadms.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADMS_H_rrr1_LU (838) - TriCore_INS_MSUBADMS_H - msubadms.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADMS_H_rrr1_UL (839) - TriCore_INS_MSUBADMS_H - msubadms.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADMS_H_rrr1_UU (840) - TriCore_INS_MSUBADMS_H - msubadms.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADM_H_rrr1_LL (841) - TriCore_INS_MSUBADM_H - msubadm.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADM_H_rrr1_LU (842) - TriCore_INS_MSUBADM_H - msubadm.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADM_H_rrr1_UL (843) - TriCore_INS_MSUBADM_H - msubadm.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADM_H_rrr1_UU (844) - TriCore_INS_MSUBADM_H - msubadm.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADRS_H_rrr1_LL (845) - TriCore_INS_MSUBADRS_H - msubadrs.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADRS_H_rrr1_LU (846) - TriCore_INS_MSUBADRS_H - msubadrs.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADRS_H_rrr1_UL (847) - TriCore_INS_MSUBADRS_H - msubadrs.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADRS_H_rrr1_UU (848) - TriCore_INS_MSUBADRS_H - msubadrs.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADRS_H_rrr1_v110 (849) - TriCore_INS_MSUBADRS_H - msubadrs.h $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADR_H_rrr1_LL (850) - TriCore_INS_MSUBADR_H - msubadr.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADR_H_rrr1_LU (851) - TriCore_INS_MSUBADR_H - msubadr.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADR_H_rrr1_UL (852) - TriCore_INS_MSUBADR_H - msubadr.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADR_H_rrr1_UU (853) - TriCore_INS_MSUBADR_H - msubadr.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADR_H_rrr1_v110 (854) - TriCore_INS_MSUBADR_H - msubadr.h $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADS_H_rrr1_LL (855) - TriCore_INS_MSUBADS_H - msubads.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADS_H_rrr1_LU (856) - TriCore_INS_MSUBADS_H - msubads.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADS_H_rrr1_UL (857) - TriCore_INS_MSUBADS_H - msubads.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBADS_H_rrr1_UU (858) - TriCore_INS_MSUBADS_H - msubads.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBAD_H_rrr1_LL (859) - TriCore_INS_MSUBAD_H - msubad.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBAD_H_rrr1_LU (860) - TriCore_INS_MSUBAD_H - msubad.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBAD_H_rrr1_UL (861) - TriCore_INS_MSUBAD_H - msubad.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBAD_H_rrr1_UU (862) - TriCore_INS_MSUBAD_H - msubad.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBMS_H_rrr1_LL (863) - TriCore_INS_MSUBMS_H - msubms.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBMS_H_rrr1_LU (864) - TriCore_INS_MSUBMS_H - msubms.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBMS_H_rrr1_UL (865) - TriCore_INS_MSUBMS_H - msubms.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBMS_H_rrr1_UU (866) - TriCore_INS_MSUBMS_H - msubms.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBMS_U_rcrv110 (867) - TriCore_INS_MSUBMS_U - msubms.u $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBMS_U_rrr2v110 (868) - TriCore_INS_MSUBMS_U - msubms.u $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBMS_rcrv110 (869) - TriCore_INS_MSUBMS - msubms $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBMS_rrr2v110 (870) - TriCore_INS_MSUBMS - msubms $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBM_H_rrr1_LL (871) - TriCore_INS_MSUBM_H - msubm.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBM_H_rrr1_LU (872) - TriCore_INS_MSUBM_H - msubm.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBM_H_rrr1_UL (873) - TriCore_INS_MSUBM_H - msubm.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBM_H_rrr1_UU (874) - TriCore_INS_MSUBM_H - msubm.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBM_H_rrr1_v110 (875) - TriCore_INS_MSUBM_H - msubm.h $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBM_Q_rrr1_v110 (876) - TriCore_INS_MSUBM_Q - msubm.q $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBM_U_rcrv110 (877) - TriCore_INS_MSUBM_U - msubm.u $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBM_U_rrr2v110 (878) - TriCore_INS_MSUBM_U - msubm.u $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBM_rcrv110 (879) - TriCore_INS_MSUBM - msubm $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBM_rrr2v110 (880) - TriCore_INS_MSUBM - msubm $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBRS_H_rrr1_LL (881) - TriCore_INS_MSUBRS_H - msubrs.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBRS_H_rrr1_LU (882) - TriCore_INS_MSUBRS_H - msubrs.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBRS_H_rrr1_UL (883) - TriCore_INS_MSUBRS_H - msubrs.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBRS_H_rrr1_UL_2 (884) - TriCore_INS_MSUBRS_H - msubrs.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBRS_H_rrr1_UU (885) - TriCore_INS_MSUBRS_H - msubrs.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBRS_H_rrr1_v110 (886) - TriCore_INS_MSUBRS_H - msubrs.h $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBRS_Q_rrr1_L_L (887) - TriCore_INS_MSUBRS_Q - msubrs.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBRS_Q_rrr1_U_U (888) - TriCore_INS_MSUBRS_Q - msubrs.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBRS_Q_rrr1_v110 (889) - TriCore_INS_MSUBRS_Q - msubrs.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBR_H_rrr1_LL (890) - TriCore_INS_MSUBR_H - msubr.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBR_H_rrr1_LU (891) - TriCore_INS_MSUBR_H - msubr.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBR_H_rrr1_UL (892) - TriCore_INS_MSUBR_H - msubr.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBR_H_rrr1_UL_2 (893) - TriCore_INS_MSUBR_H - msubr.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBR_H_rrr1_UU (894) - TriCore_INS_MSUBR_H - msubr.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBR_H_rrr1_v110 (895) - TriCore_INS_MSUBR_H - msubr.h $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBR_Q_rrr1_L_L (896) - TriCore_INS_MSUBR_Q - msubr.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBR_Q_rrr1_U_U (897) - TriCore_INS_MSUBR_Q - msubr.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBR_Q_rrr1_v110 (898) - TriCore_INS_MSUBR_Q - msubr.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_H_rrr1_LL (899) - TriCore_INS_MSUBS_H - msubs.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_H_rrr1_LU (900) - TriCore_INS_MSUBS_H - msubs.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_H_rrr1_UL (901) - TriCore_INS_MSUBS_H - msubs.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_H_rrr1_UU (902) - TriCore_INS_MSUBS_H - msubs.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_H_rrr1_v110 (903) - TriCore_INS_MSUBS_H - msubs.h $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1 (904) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1_L (905) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, $s1, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1_L_L (906) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1_U (907) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, $s1, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1_UU2_v110 (908) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1_U_U (909) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1_e (910) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1_e_L (911) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, $s1, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1_e_L_L (912) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1_e_U (913) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, $s1, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_Q_rrr1_e_U_U (914) - TriCore_INS_MSUBS_Q - msubs.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_U_rcr (915) - TriCore_INS_MSUBS_U - msubs.u $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_U_rcr_e (916) - TriCore_INS_MSUBS_U - msubs.u $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_U_rrr2 (917) - TriCore_INS_MSUBS_U - msubs.u $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_U_rrr2_e (918) - TriCore_INS_MSUBS_U - msubs.u $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_rcr (919) - TriCore_INS_MSUBS - msubs $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_rcr_e (920) - TriCore_INS_MSUBS - msubs $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_rrr2 (921) - TriCore_INS_MSUBS - msubs $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUBS_rrr2_e (922) - TriCore_INS_MSUBS - msubs $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_F_rrr (923) - TriCore_INS_MSUB_F - msub.f $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_H_rrr1_LL (924) - TriCore_INS_MSUB_H - msub.h $d, $s3, $s1, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_H_rrr1_LU (925) - TriCore_INS_MSUB_H - msub.h $d, $s3, $s1, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_H_rrr1_UL (926) - TriCore_INS_MSUB_H - msub.h $d, $s3, $s1, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_H_rrr1_UU (927) - TriCore_INS_MSUB_H - msub.h $d, $s3, $s1, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_H_rrr1_v110 (928) - TriCore_INS_MSUB_H - msub.h $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1 (929) - TriCore_INS_MSUB_Q - msub.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1_L (930) - TriCore_INS_MSUB_Q - msub.q $d, $s3, $s1, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1_L_L (931) - TriCore_INS_MSUB_Q - msub.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1_U (932) - TriCore_INS_MSUB_Q - msub.q $d, $s3, $s1, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1_UU2_v110 (933) - TriCore_INS_MSUB_Q - msub.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1_U_U (934) - TriCore_INS_MSUB_Q - msub.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1_e (935) - TriCore_INS_MSUB_Q - msub.q $d, $s3, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1_e_L (936) - TriCore_INS_MSUB_Q - msub.q $d, $s3, $s1, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1_e_L_L (937) - TriCore_INS_MSUB_Q - msub.q $d, $s3, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1_e_U (938) - TriCore_INS_MSUB_Q - msub.q $d, $s3, $s1, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_Q_rrr1_e_U_U (939) - TriCore_INS_MSUB_Q - msub.q $d, $s3, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_U_rcr (940) - TriCore_INS_MSUB_U - msub.u $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_U_rrr2 (941) - TriCore_INS_MSUB_U - msub.u $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_rcr (942) - TriCore_INS_MSUB - msub $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_rcr_e (943) - TriCore_INS_MSUB - msub $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_rrr2 (944) - TriCore_INS_MSUB - msub $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MSUB_rrr2_e (945) - TriCore_INS_MSUB - msub $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_MTCR_rlc (946) - TriCore_INS_MTCR - mtcr $const16, $d */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const16 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { 0 }
+}},
+{ /* TRICORE_MULMS_H_rr1_LL2e (947) - TriCore_INS_MULMS_H - mulms.h $d, ${s1}, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULMS_H_rr1_LU2e (948) - TriCore_INS_MULMS_H - mulms.h $d, ${s1}, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULMS_H_rr1_UL2e (949) - TriCore_INS_MULMS_H - mulms.h $d, ${s1}, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULMS_H_rr1_UU2e (950) - TriCore_INS_MULMS_H - mulms.h $d, ${s1}, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULM_H_rr1_LL2e (951) - TriCore_INS_MULM_H - mulm.h $d, ${s1}, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULM_H_rr1_LU2e (952) - TriCore_INS_MULM_H - mulm.h $d, ${s1}, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULM_H_rr1_UL2e (953) - TriCore_INS_MULM_H - mulm.h $d, ${s1}, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULM_H_rr1_UU2e (954) - TriCore_INS_MULM_H - mulm.h $d, ${s1}, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULM_U_rc (955) - TriCore_INS_MULM_U - mulm.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MULM_U_rr (956) - TriCore_INS_MULM_U - mulm.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MULM_rc (957) - TriCore_INS_MULM - mulm $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MULM_rr (958) - TriCore_INS_MULM - mulm $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MULR_H_rr1_LL2e (959) - TriCore_INS_MULR_H - mulr.h $d, ${s1}, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULR_H_rr1_LU2e (960) - TriCore_INS_MULR_H - mulr.h $d, ${s1}, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULR_H_rr1_UL2e (961) - TriCore_INS_MULR_H - mulr.h $d, ${s1}, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULR_H_rr1_UU2e (962) - TriCore_INS_MULR_H - mulr.h $d, ${s1}, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULR_H_rr_v110 (963) - TriCore_INS_MULR_H - mulr.h $d, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULR_Q_rr1_2LL (964) - TriCore_INS_MULR_Q - mulr.q $d, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULR_Q_rr1_2UU (965) - TriCore_INS_MULR_Q - mulr.q $d, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULR_Q_rr_v110 (966) - TriCore_INS_MULR_Q - mulr.q $d, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MULS_U_rc (967) - TriCore_INS_MULS_U - muls.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MULS_U_rr2 (968) - TriCore_INS_MULS_U - muls.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MULS_U_rr_v110 (969) - TriCore_INS_MULS_U - muls.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MULS_rc (970) - TriCore_INS_MULS - muls $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MULS_rr2 (971) - TriCore_INS_MULS - muls $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MULS_rr_v110 (972) - TriCore_INS_MULS - muls $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MUL_F_rrr (973) - TriCore_INS_MUL_F - mul.f $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MUL_H_rr1_LL2e (974) - TriCore_INS_MUL_H - mul.h $d, ${s1}, ${s2}ll, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_H_rr1_LU2e (975) - TriCore_INS_MUL_H - mul.h $d, ${s1}, ${s2}lu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_H_rr1_UL2e (976) - TriCore_INS_MUL_H - mul.h $d, ${s1}, ${s2}ul, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_H_rr1_UU2e (977) - TriCore_INS_MUL_H - mul.h $d, ${s1}, ${s2}uu, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_H_rr_v110 (978) - TriCore_INS_MUL_H - mul.h $d, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_Q_rr1_2 (979) - TriCore_INS_MUL_Q - mul.q $d, ${s1}, ${s2}, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_Q_rr1_2LL (980) - TriCore_INS_MUL_Q - mul.q $d, ${s1}l, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_Q_rr1_2UU (981) - TriCore_INS_MUL_Q - mul.q $d, ${s1}u, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_Q_rr1_2_L (982) - TriCore_INS_MUL_Q - mul.q $d, ${s1}, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_Q_rr1_2_Le (983) - TriCore_INS_MUL_Q - mul.q $d, ${s1}, ${s2}l, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_Q_rr1_2_U (984) - TriCore_INS_MUL_Q - mul.q $d, ${s1}, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_Q_rr1_2_Ue (985) - TriCore_INS_MUL_Q - mul.q $d, ${s1}, ${s2}u, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_Q_rr1_2__e (986) - TriCore_INS_MUL_Q - mul.q $d, ${s1}, ${s2}, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_Q_rr_v110 (987) - TriCore_INS_MUL_Q - mul.q $d, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_MUL_U_rc (988) - TriCore_INS_MUL_U - mul.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MUL_U_rr2 (989) - TriCore_INS_MUL_U - mul.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MUL_rc (990) - TriCore_INS_MUL - mul $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MUL_rc_e (991) - TriCore_INS_MUL - mul $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_MUL_rr2 (992) - TriCore_INS_MUL - mul $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MUL_rr2_e (993) - TriCore_INS_MUL - mul $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MUL_rr_v110 (994) - TriCore_INS_MUL - mul $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_MUL_srr (995) - TriCore_INS_MUL - mul $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_NAND_T (996) - TriCore_INS_NAND_T - nand.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_NAND_rc (997) - TriCore_INS_NAND - nand $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_NAND_rr (998) - TriCore_INS_NAND - nand $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_NEZ_A (999) - TriCore_INS_NEZ_A - nez.a $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_NE_A (1000) - TriCore_INS_NE_A - ne.a $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_NE_rc (1001) - TriCore_INS_NE - ne $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_NE_rr (1002) - TriCore_INS_NE - ne $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_NOP_sr (1003) - TriCore_INS_NOP - nop */
+{
+  { 0 }
+}},
+{ /* TRICORE_NOP_sys (1004) - TriCore_INS_NOP - nop */
+{
+  { 0 }
+}},
+{ /* TRICORE_NOR_T (1005) - TriCore_INS_NOR_T - nor.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_NOR_rc (1006) - TriCore_INS_NOR - nor $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_NOR_rr (1007) - TriCore_INS_NOR - nor $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_NOR_sr (1008) - TriCore_INS_NOR - nor $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_NOR_sr_v110 (1009) - TriCore_INS_NOR - nor $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_NOT_sr_v162 (1010) - TriCore_INS_NOT - not $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ORN_T (1011) - TriCore_INS_ORN_T - orn.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_ORN_rc (1012) - TriCore_INS_ORN - orn $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_ORN_rr (1013) - TriCore_INS_ORN - orn $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_OR_ANDN_T (1014) - TriCore_INS_OR_ANDN_T - or.andn.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_OR_AND_T (1015) - TriCore_INS_OR_AND_T - or.and.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_OR_EQ_rc (1016) - TriCore_INS_OR_EQ - or.eq $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_OR_EQ_rr (1017) - TriCore_INS_OR_EQ - or.eq $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_OR_GE_U_rc (1018) - TriCore_INS_OR_GE_U - or.ge.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_OR_GE_U_rr (1019) - TriCore_INS_OR_GE_U - or.ge.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_OR_GE_rc (1020) - TriCore_INS_OR_GE - or.ge $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_OR_GE_rr (1021) - TriCore_INS_OR_GE - or.ge $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_OR_LT_U_rc (1022) - TriCore_INS_OR_LT_U - or.lt.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_OR_LT_U_rr (1023) - TriCore_INS_OR_LT_U - or.lt.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_OR_LT_rc (1024) - TriCore_INS_OR_LT - or.lt $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_OR_LT_rr (1025) - TriCore_INS_OR_LT - or.lt $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_OR_NE_rc (1026) - TriCore_INS_OR_NE - or.ne $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_OR_NE_rr (1027) - TriCore_INS_OR_NE - or.ne $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_OR_NOR_T (1028) - TriCore_INS_OR_NOR_T - or.nor.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_OR_OR_T (1029) - TriCore_INS_OR_OR_T - or.or.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_OR_T (1030) - TriCore_INS_OR_T - or.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_OR_rc (1031) - TriCore_INS_OR - or $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_OR_rr (1032) - TriCore_INS_OR - or $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_OR_sc (1033) - TriCore_INS_OR - or %d15, $const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_OR_sc_v110 (1034) - TriCore_INS_OR - or %d15, $const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_OR_srr (1035) - TriCore_INS_OR - or $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_OR_srr_v110 (1036) - TriCore_INS_OR - or $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_PACK_rrr (1037) - TriCore_INS_PACK - pack $d, $s3, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_PARITY_rr (1038) - TriCore_INS_PARITY - parity $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_PARITY_rr_v110 (1039) - TriCore_INS_PARITY - parity $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_POPCNT_W_rr (1040) - TriCore_INS_POPCNT_W - popcnt.w $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_Q31TOF_rr (1041) - TriCore_INS_Q31TOF - q31tof $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_QSEED_F_rr (1042) - TriCore_INS_QSEED_F - qseed.f $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_RESTORE_sys (1043) - TriCore_INS_RESTORE - restore $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_RET_sr (1044) - TriCore_INS_RET - ret */
+{
+  { 0 }
+}},
+{ /* TRICORE_RET_sys (1045) - TriCore_INS_RET - ret */
+{
+  { 0 }
+}},
+{ /* TRICORE_RET_sys_v110 (1046) - TriCore_INS_RET - ret */
+{
+  { 0 }
+}},
+{ /* TRICORE_RFE_sr (1047) - TriCore_INS_RFE - rfe */
+{
+  { 0 }
+}},
+{ /* TRICORE_RFE_sys_sys (1048) - TriCore_INS_RFE - rfe */
+{
+  { 0 }
+}},
+{ /* TRICORE_RFE_sys_sys_v110 (1049) - TriCore_INS_RFE - rfe */
+{
+  { 0 }
+}},
+{ /* TRICORE_RFM_sys (1050) - TriCore_INS_RFM - rfm */
+{
+  { 0 }
+}},
+{ /* TRICORE_RSLCX_sys (1051) - TriCore_INS_RSLCX - rslcx */
+{
+  { 0 }
+}},
+{ /* TRICORE_RSTV_sys (1052) - TriCore_INS_RSTV - rstv */
+{
+  { 0 }
+}},
+{ /* TRICORE_RSUBS_U_rc (1053) - TriCore_INS_RSUBS_U - rsubs.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_RSUBS_rc (1054) - TriCore_INS_RSUBS - rsubs $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_RSUB_rc (1055) - TriCore_INS_RSUB - rsub $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_RSUB_sr_sr (1056) - TriCore_INS_RSUB - rsub $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_RSUB_sr_sr_v110 (1057) - TriCore_INS_RSUB - rsub $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_BU_rr (1058) - TriCore_INS_SAT_BU - sat.bu $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_BU_sr (1059) - TriCore_INS_SAT_BU - sat.bu $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_BU_sr_v110 (1060) - TriCore_INS_SAT_BU - sat.bu $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_B_rr (1061) - TriCore_INS_SAT_B - sat.b $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_B_sr (1062) - TriCore_INS_SAT_B - sat.b $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_B_sr_v110 (1063) - TriCore_INS_SAT_B - sat.b $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_HU_rr (1064) - TriCore_INS_SAT_HU - sat.hu $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_HU_sr (1065) - TriCore_INS_SAT_HU - sat.hu $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_HU_sr_v110 (1066) - TriCore_INS_SAT_HU - sat.hu $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_H_rr (1067) - TriCore_INS_SAT_H - sat.h $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_H_sr (1068) - TriCore_INS_SAT_H - sat.h $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SAT_H_sr_v110 (1069) - TriCore_INS_SAT_H - sat.h $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SELN_A_rcr_v110 (1070) - TriCore_INS_SELN_A - seln.a $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SELN_A_rrr_v110 (1071) - TriCore_INS_SELN_A - seln.a $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_SELN_rcr (1072) - TriCore_INS_SELN - seln $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SELN_rrr (1073) - TriCore_INS_SELN - seln $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_SEL_A_rcr_v110 (1074) - TriCore_INS_SEL_A - sel.a $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SEL_A_rrr_v110 (1075) - TriCore_INS_SEL_A - sel.a $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_SEL_rcr (1076) - TriCore_INS_SEL - sel $d, $s3, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SEL_rrr (1077) - TriCore_INS_SEL - sel $d, $s3, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_SHAS_rc (1078) - TriCore_INS_SHAS - shas $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SHAS_rr (1079) - TriCore_INS_SHAS - shas $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SHA_B_rc (1080) - TriCore_INS_SHA_B - sha.b $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SHA_B_rr (1081) - TriCore_INS_SHA_B - sha.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SHA_H_rc (1082) - TriCore_INS_SHA_H - sha.h $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SHA_H_rr (1083) - TriCore_INS_SHA_H - sha.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SHA_rc (1084) - TriCore_INS_SHA - sha $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SHA_rr (1085) - TriCore_INS_SHA - sha $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SHA_src (1086) - TriCore_INS_SHA - sha $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_SHA_src_v110 (1087) - TriCore_INS_SHA - sha $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_SHUFFLE_rc (1088) - TriCore_INS_SHUFFLE - shuffle $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SH_ANDN_T (1089) - TriCore_INS_SH_ANDN_T - sh.andn.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_SH_AND_T (1090) - TriCore_INS_SH_AND_T - sh.and.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_SH_B_rc (1091) - TriCore_INS_SH_B - sh.b $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SH_B_rr (1092) - TriCore_INS_SH_B - sh.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SH_EQ_rc (1093) - TriCore_INS_SH_EQ - sh.eq $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SH_EQ_rr (1094) - TriCore_INS_SH_EQ - sh.eq $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SH_GE_U_rc (1095) - TriCore_INS_SH_GE_U - sh.ge.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SH_GE_U_rr (1096) - TriCore_INS_SH_GE_U - sh.ge.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SH_GE_rc (1097) - TriCore_INS_SH_GE - sh.ge $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SH_GE_rr (1098) - TriCore_INS_SH_GE - sh.ge $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SH_H_rc (1099) - TriCore_INS_SH_H - sh.h $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SH_H_rr (1100) - TriCore_INS_SH_H - sh.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SH_LT_U_rc (1101) - TriCore_INS_SH_LT_U - sh.lt.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SH_LT_U_rr (1102) - TriCore_INS_SH_LT_U - sh.lt.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SH_LT_rc (1103) - TriCore_INS_SH_LT - sh.lt $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SH_LT_rr (1104) - TriCore_INS_SH_LT - sh.lt $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SH_NAND_T (1105) - TriCore_INS_SH_NAND_T - sh.nand.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_SH_NE_rc (1106) - TriCore_INS_SH_NE - sh.ne $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SH_NE_rr (1107) - TriCore_INS_SH_NE - sh.ne $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SH_NOR_T (1108) - TriCore_INS_SH_NOR_T - sh.nor.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_SH_ORN_T (1109) - TriCore_INS_SH_ORN_T - sh.orn.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_SH_OR_T (1110) - TriCore_INS_SH_OR_T - sh.or.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_SH_XNOR_T (1111) - TriCore_INS_SH_XNOR_T - sh.xnor.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_SH_XOR_T (1112) - TriCore_INS_SH_XOR_T - sh.xor.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_SH_rc (1113) - TriCore_INS_SH - sh $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_SH_rr (1114) - TriCore_INS_SH - sh $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SH_src (1115) - TriCore_INS_SH - sh $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_SH_src_v110 (1116) - TriCore_INS_SH - sh $d, $const4 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const4 */
+  { 0 }
+}},
+{ /* TRICORE_STLCX_abs (1117) - TriCore_INS_STLCX - stlcx $off18 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_STLCX_bo_bso (1118) - TriCore_INS_STLCX - stlcx [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_STUCX_abs (1119) - TriCore_INS_STUCX - stucx $off18 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_STUCX_bo_bso (1120) - TriCore_INS_STUCX - stucx [$s2]$off10 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_abs (1121) - TriCore_INS_ST_A - st.a $off18, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_bo_bso (1122) - TriCore_INS_ST_A - st.a [$s1]$off10, $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_bo_c (1123) - TriCore_INS_ST_A - st.a [${d}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_bo_pos (1124) - TriCore_INS_ST_A - st.a [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_bo_pre (1125) - TriCore_INS_ST_A - st.a [+${s2}]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_bo_r (1126) - TriCore_INS_ST_A - st.a [${d}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_bol (1127) - TriCore_INS_ST_A - st.a [$s2]$off16, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_sc (1128) - TriCore_INS_ST_A - st.a [%sp]$const8, %a15 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_sro (1129) - TriCore_INS_ST_A - st.a [$s2]$off4, %a15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_sro_v110 (1130) - TriCore_INS_ST_A - st.a [$s2]$off4, %a15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_ssr (1131) - TriCore_INS_ST_A - st.a [$d], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_ssr_pos (1132) - TriCore_INS_ST_A - st.a [${d}+], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_ssr_pos_v110 (1133) - TriCore_INS_ST_A - st.a [${d}+], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_ssr_v110 (1134) - TriCore_INS_ST_A - st.a [$d], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_ssro (1135) - TriCore_INS_ST_A - st.a [%a15]$off4, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_A_ssro_v110 (1136) - TriCore_INS_ST_A - st.a [%a15]$off4, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_abs (1137) - TriCore_INS_ST_B - st.b $off18, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_bo_bso (1138) - TriCore_INS_ST_B - st.b [$s1]$off10, $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_bo_c (1139) - TriCore_INS_ST_B - st.b [${d}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_bo_pos (1140) - TriCore_INS_ST_B - st.b [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_bo_pre (1141) - TriCore_INS_ST_B - st.b [+${s2}]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_bo_r (1142) - TriCore_INS_ST_B - st.b [${d}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_bol (1143) - TriCore_INS_ST_B - st.b [$s2]$off16, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_sro (1144) - TriCore_INS_ST_B - st.b [$s2]$off4, %d15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_sro_v110 (1145) - TriCore_INS_ST_B - st.b [$s2]$off4, %d15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_ssr (1146) - TriCore_INS_ST_B - st.b [$d], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_ssr_pos (1147) - TriCore_INS_ST_B - st.b [${d}+], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_ssr_pos_v110 (1148) - TriCore_INS_ST_B - st.b [${d}+], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_ssr_v110 (1149) - TriCore_INS_ST_B - st.b [$d], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_ssro (1150) - TriCore_INS_ST_B - st.b [%a15]$off4, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_B_ssro_v110 (1151) - TriCore_INS_ST_B - st.b [%a15]$off4, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_DA_abs (1152) - TriCore_INS_ST_DA - st.da $off18, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_ST_DA_bo_bso (1153) - TriCore_INS_ST_DA - st.da [$s1]$off10, $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_DA_bo_c (1154) - TriCore_INS_ST_DA - st.da [${d}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_DA_bo_pos (1155) - TriCore_INS_ST_DA - st.da [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_DA_bo_pre (1156) - TriCore_INS_ST_DA - st.da [+${s2}]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_DA_bo_r (1157) - TriCore_INS_ST_DA - st.da [${d}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_D_abs (1158) - TriCore_INS_ST_D - st.d $off18, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_ST_D_bo_bso (1159) - TriCore_INS_ST_D - st.d [$s1]$off10, $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_D_bo_c (1160) - TriCore_INS_ST_D - st.d [${d}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_D_bo_pos (1161) - TriCore_INS_ST_D - st.d [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_D_bo_pre (1162) - TriCore_INS_ST_D - st.d [+${s2}]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_D_bo_r (1163) - TriCore_INS_ST_D - st.d [${d}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_abs (1164) - TriCore_INS_ST_H - st.h $off18, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_bo_bso (1165) - TriCore_INS_ST_H - st.h [$s1]$off10, $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_bo_c (1166) - TriCore_INS_ST_H - st.h [${d}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_bo_pos (1167) - TriCore_INS_ST_H - st.h [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_bo_pre (1168) - TriCore_INS_ST_H - st.h [+${s2}]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_bo_r (1169) - TriCore_INS_ST_H - st.h [${d}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_bol (1170) - TriCore_INS_ST_H - st.h [$s2]$off16, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_sro (1171) - TriCore_INS_ST_H - st.h [$s2]$off4, %d15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_sro_v110 (1172) - TriCore_INS_ST_H - st.h [$s2]$off4, %d15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_ssr (1173) - TriCore_INS_ST_H - st.h [$d], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_ssr_pos (1174) - TriCore_INS_ST_H - st.h [${d}+], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_ssr_pos_v110 (1175) - TriCore_INS_ST_H - st.h [${d}+], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_ssr_v110 (1176) - TriCore_INS_ST_H - st.h [$d], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_ssro (1177) - TriCore_INS_ST_H - st.h [%a15]$off4, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_H_ssro_v110 (1178) - TriCore_INS_ST_H - st.h [%a15]$off4, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_Q_abs (1179) - TriCore_INS_ST_Q - st.q $off18, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_ST_Q_bo_bso (1180) - TriCore_INS_ST_Q - st.q [$s1]$off10, $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_Q_bo_c (1181) - TriCore_INS_ST_Q - st.q [${d}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_Q_bo_pos (1182) - TriCore_INS_ST_Q - st.q [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_Q_bo_pre (1183) - TriCore_INS_ST_Q - st.q [+${s2}]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_Q_bo_r (1184) - TriCore_INS_ST_Q - st.q [${d}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_T (1185) - TriCore_INS_ST_T - st.t $off18, $bpos3, $b */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bpos3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* b */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_abs (1186) - TriCore_INS_ST_W - st.w $off18, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_bo_bso (1187) - TriCore_INS_ST_W - st.w [$s1]$off10, $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_bo_c (1188) - TriCore_INS_ST_W - st.w [${d}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_bo_pos (1189) - TriCore_INS_ST_W - st.w [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_bo_pre (1190) - TriCore_INS_ST_W - st.w [+${s2}]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_bo_r (1191) - TriCore_INS_ST_W - st.w [${d}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_bol (1192) - TriCore_INS_ST_W - st.w [$s2]$off16, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off16 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_sc (1193) - TriCore_INS_ST_W - st.w [%sp]$const8, %d15 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_sro (1194) - TriCore_INS_ST_W - st.w [$s2]$off4, %d15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_sro_v110 (1195) - TriCore_INS_ST_W - st.w [$s2]$off4, %d15 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_ssr (1196) - TriCore_INS_ST_W - st.w [$d], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_ssr_pos (1197) - TriCore_INS_ST_W - st.w [${d}+], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_ssr_pos_v110 (1198) - TriCore_INS_ST_W - st.w [${d}+], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_ssr_v110 (1199) - TriCore_INS_ST_W - st.w [$d], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_ssro (1200) - TriCore_INS_ST_W - st.w [%a15]$off4, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_ST_W_ssro_v110 (1201) - TriCore_INS_ST_W - st.w [%a15]$off4, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off4 */
+  { 0 }
+}},
+{ /* TRICORE_SUBC_rr (1202) - TriCore_INS_SUBC - subc $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUBSC_A_rr (1203) - TriCore_INS_SUBSC_A - subsc.a $d, $s1, $s2, $n */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */
+  { 0 }
+}},
+{ /* TRICORE_SUBS_BU_rr (1204) - TriCore_INS_SUBS_BU - subs.bu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUBS_B_rr (1205) - TriCore_INS_SUBS_B - subs.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUBS_HU_rr (1206) - TriCore_INS_SUBS_HU - subs.hu $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUBS_H_rr (1207) - TriCore_INS_SUBS_H - subs.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUBS_U_rr (1208) - TriCore_INS_SUBS_U - subs.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUBS_rr (1209) - TriCore_INS_SUBS - subs $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUBS_srr (1210) - TriCore_INS_SUBS - subs $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUBX_rr (1211) - TriCore_INS_SUBX - subx $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUB_A_rr (1212) - TriCore_INS_SUB_A - sub.a $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUB_A_sc (1213) - TriCore_INS_SUB_A - sub.a %sp, $const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_SUB_A_sc_v110 (1214) - TriCore_INS_SUB_A - sub.a %sp, $const8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const8 */
+  { 0 }
+}},
+{ /* TRICORE_SUB_B_rr (1215) - TriCore_INS_SUB_B - sub.b $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUB_F_rrr (1216) - TriCore_INS_SUB_F - sub.f $d, $s3, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s3 */
+  { 0 }
+}},
+{ /* TRICORE_SUB_H_rr (1217) - TriCore_INS_SUB_H - sub.h $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUB_rr (1218) - TriCore_INS_SUB - sub $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUB_srr (1219) - TriCore_INS_SUB - sub $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUB_srr_15a (1220) - TriCore_INS_SUB - sub %d15, $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SUB_srr_a15 (1221) - TriCore_INS_SUB - sub $d, %d15, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_SVLCX_sys (1222) - TriCore_INS_SVLCX - svlcx */
+{
+  { 0 }
+}},
+{ /* TRICORE_SWAPMSK_W_bo_bso (1223) - TriCore_INS_SWAPMSK_W - swapmsk.w [$s1]$off10, $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAPMSK_W_bo_c (1224) - TriCore_INS_SWAPMSK_W - swapmsk.w [${d}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAPMSK_W_bo_i (1225) - TriCore_INS_SWAPMSK_W - swapmsk.w [${s1}+i], $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAPMSK_W_bo_pos (1226) - TriCore_INS_SWAPMSK_W - swapmsk.w [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAPMSK_W_bo_pre (1227) - TriCore_INS_SWAPMSK_W - swapmsk.w [+${s2}]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAPMSK_W_bo_r (1228) - TriCore_INS_SWAPMSK_W - swapmsk.w [${d}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_A_abs (1229) - TriCore_INS_SWAP_A - swap.a $off18, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_A_bo_bso (1230) - TriCore_INS_SWAP_A - swap.a [$s1]$off10, $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_A_bo_c (1231) - TriCore_INS_SWAP_A - swap.a [${d}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_A_bo_pos (1232) - TriCore_INS_SWAP_A - swap.a [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_A_bo_pre (1233) - TriCore_INS_SWAP_A - swap.a [+${s2}]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_A_bo_r (1234) - TriCore_INS_SWAP_A - swap.a [${d}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_W_abs (1235) - TriCore_INS_SWAP_W - swap.w $off18, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off18 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_W_bo_bso (1236) - TriCore_INS_SWAP_W - swap.w [$s1]$off10, $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_W_bo_c (1237) - TriCore_INS_SWAP_W - swap.w [${d}+c]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_W_bo_i (1238) - TriCore_INS_SWAP_W - swap.w [${s1}+i], $d */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_W_bo_pos (1239) - TriCore_INS_SWAP_W - swap.w [${s2}+]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_W_bo_pre (1240) - TriCore_INS_SWAP_W - swap.w [+${s2}]$off10, $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* off10 */
+  { 0 }
+}},
+{ /* TRICORE_SWAP_W_bo_r (1241) - TriCore_INS_SWAP_W - swap.w [${d}+r], $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_SYSCALL_rc (1242) - TriCore_INS_SYSCALL - syscall $const9 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_TLBDEMAP_rr (1243) - TriCore_INS_TLBDEMAP - tlbdemap $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_TLBFLUSH_A_rr (1244) - TriCore_INS_TLBFLUSH_A - tlbflush.a */
+{
+  { 0 }
+}},
+{ /* TRICORE_TLBFLUSH_B_rr (1245) - TriCore_INS_TLBFLUSH_B - tlbflush.b */
+{
+  { 0 }
+}},
+{ /* TRICORE_TLBMAP_rr (1246) - TriCore_INS_TLBMAP - tlbmap $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_TLBPROBE_A_rr (1247) - TriCore_INS_TLBPROBE_A - tlbprobe.a $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_TLBPROBE_I_rr (1248) - TriCore_INS_TLBPROBE_I - tlbprobe.i $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_TRAPSV_sys (1249) - TriCore_INS_TRAPSV - trapsv */
+{
+  { 0 }
+}},
+{ /* TRICORE_TRAPV_sys (1250) - TriCore_INS_TRAPV - trapv */
+{
+  { 0 }
+}},
+{ /* TRICORE_UNPACK_rr_rr (1251) - TriCore_INS_UNPACK - unpack $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_UNPACK_rr_rr_v110 (1252) - TriCore_INS_UNPACK - unpack $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_UPDFL_rr (1253) - TriCore_INS_UPDFL - updfl $s1 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_UTOF_rr (1254) - TriCore_INS_UTOF - utof $d, $s1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { 0 }
+}},
+{ /* TRICORE_WAIT_sys (1255) - TriCore_INS_WAIT - wait */
+{
+  { 0 }
+}},
+{ /* TRICORE_XNOR_T (1256) - TriCore_INS_XNOR_T - xnor.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_XNOR_rc (1257) - TriCore_INS_XNOR - xnor $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_XNOR_rr (1258) - TriCore_INS_XNOR - xnor $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_EQ_rc (1259) - TriCore_INS_XOR_EQ - xor.eq $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_EQ_rr (1260) - TriCore_INS_XOR_EQ - xor.eq $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_GE_U_rc (1261) - TriCore_INS_XOR_GE_U - xor.ge.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_GE_U_rr (1262) - TriCore_INS_XOR_GE_U - xor.ge.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_GE_rc (1263) - TriCore_INS_XOR_GE - xor.ge $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_GE_rr (1264) - TriCore_INS_XOR_GE - xor.ge $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_LT_U_rc (1265) - TriCore_INS_XOR_LT_U - xor.lt.u $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_LT_U_rr (1266) - TriCore_INS_XOR_LT_U - xor.lt.u $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_LT_rc (1267) - TriCore_INS_XOR_LT - xor.lt $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_LT_rr (1268) - TriCore_INS_XOR_LT - xor.lt $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_NE_rc (1269) - TriCore_INS_XOR_NE - xor.ne $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_NE_rr (1270) - TriCore_INS_XOR_NE - xor.ne $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_T (1271) - TriCore_INS_XOR_T - xor.t $d, $s1, $pos1, $s2, $pos_r */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos_r */
+  { 0 }
+}},
+{ /* TRICORE_XOR_rc (1272) - TriCore_INS_XOR - xor $d, $s1, $const9 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* const9 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_rr (1273) - TriCore_INS_XOR - xor $d, $s1, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
+{ /* TRICORE_XOR_srr (1274) - TriCore_INS_XOR - xor $d, $s2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* d */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s2 */
+  { 0 }
+}},
diff --git a/arch/TriCore/TriCoreGenCSOpGroup.inc b/arch/TriCore/TriCoreGenCSOpGroup.inc
new file mode 100644
index 0000000000..a41a695320
--- /dev/null
+++ b/arch/TriCore/TriCoreGenCSOpGroup.inc
@@ -0,0 +1,32 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  TRICORE_OP_GROUP_RegImmShift = 0,
+  TRICORE_OP_GROUP_LdStmModeOperand = 1,
+  TRICORE_OP_GROUP_MandatoryInvertedPredicateOperand = 2,
+  TRICORE_OP_GROUP_Operand = 3,
+  TRICORE_OP_GROUP_SExtImm_9 = 4,
+  TRICORE_OP_GROUP_ZExtImm_16 = 5,
+  TRICORE_OP_GROUP_SExtImm_16 = 6,
+  TRICORE_OP_GROUP_ZExtImm_2 = 7,
+  TRICORE_OP_GROUP_SExtImm_4 = 8,
+  TRICORE_OP_GROUP_ZExtImm_4 = 9,
+  TRICORE_OP_GROUP_ZExtImm_8 = 10,
+  TRICORE_OP_GROUP_SExtImm_10 = 11,
+  TRICORE_OP_GROUP_Disp24Imm = 12,
+  TRICORE_OP_GROUP_Disp8Imm = 13,
+  TRICORE_OP_GROUP_Disp15Imm = 14,
+  TRICORE_OP_GROUP_Disp4Imm = 15,
+  TRICORE_OP_GROUP_Off18Imm = 16,
+  TRICORE_OP_GROUP_OExtImm_4 = 17,
+  TRICORE_OP_GROUP_ZExtImm_9 = 18,
diff --git a/arch/TriCore/TriCoreGenDisassemblerTables.inc b/arch/TriCore/TriCoreGenDisassemblerTables.inc
new file mode 100644
index 0000000000..2594ce2bee
--- /dev/null
+++ b/arch/TriCore/TriCoreGenDisassemblerTables.inc
@@ -0,0 +1,4044 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#include "../../MCInst.h"
+#include "../../LEB128.h"
+
+// Helper function for extracting fields from encoded instructions.
+#define FieldFromInstruction(fname, InsnType) \
+static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
+{ \
+  InsnType fieldMask; \
+  if (numBits == sizeof(InsnType) * 8) \
+    fieldMask = (InsnType)(-1LL); \
+  else \
+    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
+  return (insn & fieldMask) >> startBit; \
+}
+
+static const uint8_t DecoderTable16[] = {
+/* 0 */       MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 3 */       MCD_OPC_FilterValue, 0, 89, 0, 0, // Skip to: 97
+/* 8 */       MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 11 */      MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 69
+/* 16 */      MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 19 */      MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 28
+/* 24 */      MCD_OPC_Decode, 235, 7, 0, // Opcode: NOP_sr
+/* 28 */      MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 42
+/* 33 */      MCD_OPC_CheckPredicate, 0, 176, 6, 0, // Skip to: 1750
+/* 38 */      MCD_OPC_Decode, 202, 3, 0, // Opcode: FRET_sr
+/* 42 */      MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 51
+/* 47 */      MCD_OPC_Decode, 151, 8, 0, // Opcode: RFE_sr
+/* 51 */      MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 60
+/* 56 */      MCD_OPC_Decode, 148, 8, 0, // Opcode: RET_sr
+/* 60 */      MCD_OPC_FilterValue, 10, 149, 6, 0, // Skip to: 1750
+/* 65 */      MCD_OPC_Decode, 147, 3, 0, // Opcode: DEBUG_sr
+/* 69 */      MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 83
+/* 74 */      MCD_OPC_CheckPredicate, 1, 135, 6, 0, // Skip to: 1750
+/* 79 */      MCD_OPC_Decode, 177, 6, 1, // Opcode: MOV_AA_srr_srr
+/* 83 */      MCD_OPC_FilterValue, 2, 126, 6, 0, // Skip to: 1750
+/* 88 */      MCD_OPC_CheckPredicate, 1, 121, 6, 0, // Skip to: 1750
+/* 93 */      MCD_OPC_Decode, 184, 6, 1, // Opcode: MOV_D_srr_srr
+/* 97 */      MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 141
+/* 102 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 105 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 114
+/* 110 */     MCD_OPC_Decode, 196, 6, 1, // Opcode: MOV_srr
+/* 114 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 123
+/* 119 */     MCD_OPC_Decode, 170, 2, 1, // Opcode: ADD_srr
+/* 123 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 132
+/* 128 */     MCD_OPC_Decode, 194, 6, 2, // Opcode: MOV_src
+/* 132 */     MCD_OPC_FilterValue, 3, 77, 6, 0, // Skip to: 1750
+/* 137 */     MCD_OPC_Decode, 167, 2, 2, // Opcode: ADD_src
+/* 141 */     MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 205
+/* 146 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 149 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 163
+/* 154 */     MCD_OPC_CheckPredicate, 1, 55, 6, 0, // Skip to: 1750
+/* 159 */     MCD_OPC_Decode, 209, 4, 3, // Opcode: LD_BU_slr_post
+/* 163 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 177
+/* 168 */     MCD_OPC_CheckPredicate, 1, 41, 6, 0, // Skip to: 1750
+/* 173 */     MCD_OPC_Decode, 148, 5, 3, // Opcode: LD_W_slr_post
+/* 177 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 191
+/* 182 */     MCD_OPC_CheckPredicate, 1, 27, 6, 0, // Skip to: 1750
+/* 187 */     MCD_OPC_Decode, 254, 4, 3, // Opcode: LD_H_slr_post
+/* 191 */     MCD_OPC_FilterValue, 3, 18, 6, 0, // Skip to: 1750
+/* 196 */     MCD_OPC_CheckPredicate, 1, 13, 6, 0, // Skip to: 1750
+/* 201 */     MCD_OPC_Decode, 194, 4, 3, // Opcode: LD_A_slr_post
+/* 205 */     MCD_OPC_FilterValue, 6, 66, 0, 0, // Skip to: 276
+/* 210 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 213 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 227
+/* 218 */     MCD_OPC_CheckPredicate, 1, 247, 5, 0, // Skip to: 1750
+/* 223 */     MCD_OPC_Decode, 219, 8, 2, // Opcode: SH_src
+/* 227 */     MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 248
+/* 232 */     MCD_OPC_CheckPredicate, 1, 233, 5, 0, // Skip to: 1750
+/* 237 */     MCD_OPC_CheckField, 12, 4, 0, 226, 5, 0, // Skip to: 1750
+/* 244 */     MCD_OPC_Decode, 240, 7, 0, // Opcode: NOR_sr
+/* 248 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 262
+/* 253 */     MCD_OPC_CheckPredicate, 1, 212, 5, 0, // Skip to: 1750
+/* 258 */     MCD_OPC_Decode, 190, 8, 2, // Opcode: SHA_src
+/* 262 */     MCD_OPC_FilterValue, 3, 203, 5, 0, // Skip to: 1750
+/* 267 */     MCD_OPC_CheckPredicate, 1, 198, 5, 0, // Skip to: 1750
+/* 272 */     MCD_OPC_Decode, 250, 9, 1, // Opcode: XOR_srr
+/* 276 */     MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 340
+/* 281 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 284 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 298
+/* 289 */     MCD_OPC_CheckPredicate, 1, 176, 5, 0, // Skip to: 1750
+/* 294 */     MCD_OPC_Decode, 212, 4, 4, // Opcode: LD_BU_slro
+/* 298 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 312
+/* 303 */     MCD_OPC_CheckPredicate, 1, 162, 5, 0, // Skip to: 1750
+/* 308 */     MCD_OPC_Decode, 151, 5, 4, // Opcode: LD_W_slro
+/* 312 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 326
+/* 317 */     MCD_OPC_CheckPredicate, 1, 148, 5, 0, // Skip to: 1750
+/* 322 */     MCD_OPC_Decode, 129, 5, 4, // Opcode: LD_H_slro
+/* 326 */     MCD_OPC_FilterValue, 3, 139, 5, 0, // Skip to: 1750
+/* 331 */     MCD_OPC_CheckPredicate, 1, 134, 5, 0, // Skip to: 1750
+/* 336 */     MCD_OPC_Decode, 197, 4, 4, // Opcode: LD_A_slro
+/* 340 */     MCD_OPC_FilterValue, 10, 21, 0, 0, // Skip to: 366
+/* 345 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 348 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 357
+/* 353 */     MCD_OPC_Decode, 241, 2, 2, // Opcode: CADD_src
+/* 357 */     MCD_OPC_FilterValue, 3, 108, 5, 0, // Skip to: 1750
+/* 362 */     MCD_OPC_Decode, 235, 2, 2, // Opcode: CADDN_src
+/* 366 */     MCD_OPC_FilterValue, 12, 59, 0, 0, // Skip to: 430
+/* 371 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 374 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 388
+/* 379 */     MCD_OPC_CheckPredicate, 1, 86, 5, 0, // Skip to: 1750
+/* 384 */     MCD_OPC_Decode, 214, 4, 5, // Opcode: LD_BU_sro
+/* 388 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 402
+/* 393 */     MCD_OPC_CheckPredicate, 1, 72, 5, 0, // Skip to: 1750
+/* 398 */     MCD_OPC_Decode, 153, 5, 5, // Opcode: LD_W_sro
+/* 402 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 416
+/* 407 */     MCD_OPC_CheckPredicate, 1, 58, 5, 0, // Skip to: 1750
+/* 412 */     MCD_OPC_Decode, 131, 5, 5, // Opcode: LD_H_sro
+/* 416 */     MCD_OPC_FilterValue, 3, 49, 5, 0, // Skip to: 1750
+/* 421 */     MCD_OPC_CheckPredicate, 1, 44, 5, 0, // Skip to: 1750
+/* 426 */     MCD_OPC_Decode, 199, 4, 5, // Opcode: LD_A_sro
+/* 430 */     MCD_OPC_FilterValue, 14, 59, 0, 0, // Skip to: 494
+/* 435 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 438 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 452
+/* 443 */     MCD_OPC_CheckPredicate, 1, 22, 5, 0, // Skip to: 1750
+/* 448 */     MCD_OPC_Decode, 134, 4, 6, // Opcode: JLTZ_sbr
+/* 452 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 466
+/* 457 */     MCD_OPC_CheckPredicate, 1, 8, 5, 0, // Skip to: 1750
+/* 462 */     MCD_OPC_Decode, 251, 3, 6, // Opcode: JGTZ_sbr
+/* 466 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 480
+/* 471 */     MCD_OPC_CheckPredicate, 1, 250, 4, 0, // Skip to: 1750
+/* 476 */     MCD_OPC_Decode, 130, 4, 6, // Opcode: JLEZ_sbr
+/* 480 */     MCD_OPC_FilterValue, 3, 241, 4, 0, // Skip to: 1750
+/* 485 */     MCD_OPC_CheckPredicate, 1, 236, 4, 0, // Skip to: 1750
+/* 490 */     MCD_OPC_Decode, 245, 3, 6, // Opcode: JGEZ_sbr
+/* 494 */     MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 508
+/* 499 */     MCD_OPC_CheckPredicate, 1, 222, 4, 0, // Skip to: 1750
+/* 504 */     MCD_OPC_Decode, 146, 2, 7, // Opcode: ADDSC_A_srrs
+/* 508 */     MCD_OPC_FilterValue, 18, 59, 0, 0, // Skip to: 572
+/* 513 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 516 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 530
+/* 521 */     MCD_OPC_CheckPredicate, 1, 200, 4, 0, // Skip to: 1750
+/* 526 */     MCD_OPC_Decode, 172, 2, 1, // Opcode: ADD_srr_a15
+/* 530 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 544
+/* 535 */     MCD_OPC_CheckPredicate, 1, 186, 4, 0, // Skip to: 1750
+/* 540 */     MCD_OPC_Decode, 197, 9, 1, // Opcode: SUB_srr_a15
+/* 544 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 558
+/* 549 */     MCD_OPC_CheckPredicate, 1, 172, 4, 0, // Skip to: 1750
+/* 554 */     MCD_OPC_Decode, 169, 2, 2, // Opcode: ADD_src_a15
+/* 558 */     MCD_OPC_FilterValue, 3, 163, 4, 0, // Skip to: 1750
+/* 563 */     MCD_OPC_CheckPredicate, 0, 158, 4, 0, // Skip to: 1750
+/* 568 */     MCD_OPC_Decode, 195, 6, 2, // Opcode: MOV_src_e
+/* 572 */     MCD_OPC_FilterValue, 20, 59, 0, 0, // Skip to: 636
+/* 577 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 580 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 594
+/* 585 */     MCD_OPC_CheckPredicate, 1, 136, 4, 0, // Skip to: 1750
+/* 590 */     MCD_OPC_Decode, 208, 4, 3, // Opcode: LD_BU_slr
+/* 594 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 608
+/* 599 */     MCD_OPC_CheckPredicate, 1, 122, 4, 0, // Skip to: 1750
+/* 604 */     MCD_OPC_Decode, 147, 5, 3, // Opcode: LD_W_slr
+/* 608 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 622
+/* 613 */     MCD_OPC_CheckPredicate, 1, 108, 4, 0, // Skip to: 1750
+/* 618 */     MCD_OPC_Decode, 253, 4, 3, // Opcode: LD_H_slr
+/* 622 */     MCD_OPC_FilterValue, 3, 99, 4, 0, // Skip to: 1750
+/* 627 */     MCD_OPC_CheckPredicate, 1, 94, 4, 0, // Skip to: 1750
+/* 632 */     MCD_OPC_Decode, 193, 4, 3, // Opcode: LD_A_slr
+/* 636 */     MCD_OPC_FilterValue, 22, 31, 0, 0, // Skip to: 672
+/* 641 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 644 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 658
+/* 649 */     MCD_OPC_CheckPredicate, 1, 72, 4, 0, // Skip to: 1750
+/* 654 */     MCD_OPC_Decode, 195, 2, 8, // Opcode: AND_sc
+/* 658 */     MCD_OPC_FilterValue, 2, 63, 4, 0, // Skip to: 1750
+/* 663 */     MCD_OPC_CheckPredicate, 1, 58, 4, 0, // Skip to: 1750
+/* 668 */     MCD_OPC_Decode, 137, 8, 8, // Opcode: OR_sc
+/* 672 */     MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 708
+/* 677 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 680 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 694
+/* 685 */     MCD_OPC_CheckPredicate, 1, 36, 4, 0, // Skip to: 1750
+/* 690 */     MCD_OPC_Decode, 146, 5, 8, // Opcode: LD_W_sc
+/* 694 */     MCD_OPC_FilterValue, 3, 27, 4, 0, // Skip to: 1750
+/* 699 */     MCD_OPC_CheckPredicate, 1, 22, 4, 0, // Skip to: 1750
+/* 704 */     MCD_OPC_Decode, 192, 4, 8, // Opcode: LD_A_sc
+/* 708 */     MCD_OPC_FilterValue, 26, 44, 0, 0, // Skip to: 757
+/* 713 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 716 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 725
+/* 721 */     MCD_OPC_Decode, 171, 2, 1, // Opcode: ADD_srr_15a
+/* 725 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 734
+/* 730 */     MCD_OPC_Decode, 196, 9, 1, // Opcode: SUB_srr_15a
+/* 734 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 743
+/* 739 */     MCD_OPC_Decode, 168, 2, 2, // Opcode: ADD_src_15a
+/* 743 */     MCD_OPC_FilterValue, 3, 234, 3, 0, // Skip to: 1750
+/* 748 */     MCD_OPC_CheckPredicate, 1, 229, 3, 0, // Skip to: 1750
+/* 753 */     MCD_OPC_Decode, 192, 6, 8, // Opcode: MOV_sc
+/* 757 */     MCD_OPC_FilterValue, 28, 38, 0, 0, // Skip to: 800
+/* 762 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 765 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 779
+/* 770 */     MCD_OPC_CheckPredicate, 1, 207, 3, 0, // Skip to: 1750
+/* 775 */     MCD_OPC_Decode, 247, 2, 9, // Opcode: CALL_sb
+/* 779 */     MCD_OPC_FilterValue, 3, 198, 3, 0, // Skip to: 1750
+/* 784 */     MCD_OPC_CheckPredicate, 1, 193, 3, 0, // Skip to: 1750
+/* 789 */     MCD_OPC_CheckField, 12, 4, 0, 186, 3, 0, // Skip to: 1750
+/* 796 */     MCD_OPC_Decode, 128, 4, 0, // Opcode: JI_sr
+/* 800 */     MCD_OPC_FilterValue, 30, 59, 0, 0, // Skip to: 864
+/* 805 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 808 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 822
+/* 813 */     MCD_OPC_CheckPredicate, 1, 164, 3, 0, // Skip to: 1750
+/* 818 */     MCD_OPC_Decode, 239, 3, 10, // Opcode: JEQ_sbc1
+/* 822 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 836
+/* 827 */     MCD_OPC_CheckPredicate, 1, 150, 3, 0, // Skip to: 1750
+/* 832 */     MCD_OPC_Decode, 148, 4, 10, // Opcode: JNE_sbc1
+/* 836 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 850
+/* 841 */     MCD_OPC_CheckPredicate, 0, 136, 3, 0, // Skip to: 1750
+/* 846 */     MCD_OPC_Decode, 240, 3, 10, // Opcode: JEQ_sbc2
+/* 850 */     MCD_OPC_FilterValue, 3, 127, 3, 0, // Skip to: 1750
+/* 855 */     MCD_OPC_CheckPredicate, 0, 122, 3, 0, // Skip to: 1750
+/* 860 */     MCD_OPC_Decode, 149, 4, 10, // Opcode: JNE_sbc2
+/* 864 */     MCD_OPC_FilterValue, 32, 59, 0, 0, // Skip to: 928
+/* 869 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 872 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 886
+/* 877 */     MCD_OPC_CheckPredicate, 1, 100, 3, 0, // Skip to: 1750
+/* 882 */     MCD_OPC_Decode, 189, 9, 8, // Opcode: SUB_A_sc
+/* 886 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 900
+/* 891 */     MCD_OPC_CheckPredicate, 1, 86, 3, 0, // Skip to: 1750
+/* 896 */     MCD_OPC_Decode, 181, 6, 1, // Opcode: MOV_A_srr
+/* 900 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 914
+/* 905 */     MCD_OPC_CheckPredicate, 1, 72, 3, 0, // Skip to: 1750
+/* 910 */     MCD_OPC_Decode, 180, 6, 2, // Opcode: MOV_A_src
+/* 914 */     MCD_OPC_FilterValue, 3, 63, 3, 0, // Skip to: 1750
+/* 919 */     MCD_OPC_CheckPredicate, 1, 58, 3, 0, // Skip to: 1750
+/* 924 */     MCD_OPC_Decode, 201, 2, 8, // Opcode: BISR_sc
+/* 928 */     MCD_OPC_FilterValue, 34, 39, 0, 0, // Skip to: 972
+/* 933 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 936 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 945
+/* 941 */     MCD_OPC_Decode, 156, 2, 1, // Opcode: ADDS_srr
+/* 945 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 954
+/* 950 */     MCD_OPC_Decode, 186, 9, 1, // Opcode: SUBS_srr
+/* 954 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 963
+/* 959 */     MCD_OPC_Decode, 195, 9, 1, // Opcode: SUB_srr
+/* 963 */     MCD_OPC_FilterValue, 3, 14, 3, 0, // Skip to: 1750
+/* 968 */     MCD_OPC_Decode, 227, 7, 1, // Opcode: MUL_srr
+/* 972 */     MCD_OPC_FilterValue, 36, 59, 0, 0, // Skip to: 1036
+/* 977 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 980 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 994
+/* 985 */     MCD_OPC_CheckPredicate, 1, 248, 2, 0, // Skip to: 1750
+/* 990 */     MCD_OPC_Decode, 251, 8, 11, // Opcode: ST_B_ssr_pos
+/* 994 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1008
+/* 999 */     MCD_OPC_CheckPredicate, 1, 234, 2, 0, // Skip to: 1750
+/* 1004 */    MCD_OPC_Decode, 173, 9, 11, // Opcode: ST_W_ssr_pos
+/* 1008 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1022
+/* 1013 */    MCD_OPC_CheckPredicate, 1, 220, 2, 0, // Skip to: 1750
+/* 1018 */    MCD_OPC_Decode, 150, 9, 11, // Opcode: ST_H_ssr_pos
+/* 1022 */    MCD_OPC_FilterValue, 3, 211, 2, 0, // Skip to: 1750
+/* 1027 */    MCD_OPC_CheckPredicate, 1, 206, 2, 0, // Skip to: 1750
+/* 1032 */    MCD_OPC_Decode, 236, 8, 11, // Opcode: ST_A_ssr_pos
+/* 1036 */    MCD_OPC_FilterValue, 38, 31, 0, 0, // Skip to: 1072
+/* 1041 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1044 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1058
+/* 1049 */    MCD_OPC_CheckPredicate, 1, 184, 2, 0, // Skip to: 1750
+/* 1054 */    MCD_OPC_Decode, 197, 2, 1, // Opcode: AND_srr
+/* 1058 */    MCD_OPC_FilterValue, 2, 175, 2, 0, // Skip to: 1750
+/* 1063 */    MCD_OPC_CheckPredicate, 1, 170, 2, 0, // Skip to: 1750
+/* 1068 */    MCD_OPC_Decode, 139, 8, 1, // Opcode: OR_srr
+/* 1072 */    MCD_OPC_FilterValue, 40, 59, 0, 0, // Skip to: 1136
+/* 1077 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1080 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1094
+/* 1085 */    MCD_OPC_CheckPredicate, 1, 148, 2, 0, // Skip to: 1750
+/* 1090 */    MCD_OPC_Decode, 254, 8, 12, // Opcode: ST_B_ssro
+/* 1094 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1108
+/* 1099 */    MCD_OPC_CheckPredicate, 1, 134, 2, 0, // Skip to: 1750
+/* 1104 */    MCD_OPC_Decode, 176, 9, 12, // Opcode: ST_W_ssro
+/* 1108 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1122
+/* 1113 */    MCD_OPC_CheckPredicate, 1, 120, 2, 0, // Skip to: 1750
+/* 1118 */    MCD_OPC_Decode, 153, 9, 12, // Opcode: ST_H_ssro
+/* 1122 */    MCD_OPC_FilterValue, 3, 111, 2, 0, // Skip to: 1750
+/* 1127 */    MCD_OPC_CheckPredicate, 1, 106, 2, 0, // Skip to: 1750
+/* 1132 */    MCD_OPC_Decode, 239, 8, 12, // Opcode: ST_A_ssro
+/* 1136 */    MCD_OPC_FilterValue, 42, 39, 0, 0, // Skip to: 1180
+/* 1141 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1144 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1153
+/* 1149 */    MCD_OPC_Decode, 132, 3, 1, // Opcode: CMOV_srr
+/* 1153 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1162
+/* 1158 */    MCD_OPC_Decode, 130, 3, 1, // Opcode: CMOVN_srr
+/* 1162 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1171
+/* 1167 */    MCD_OPC_Decode, 131, 3, 2, // Opcode: CMOV_src
+/* 1171 */    MCD_OPC_FilterValue, 3, 62, 2, 0, // Skip to: 1750
+/* 1176 */    MCD_OPC_Decode, 129, 3, 2, // Opcode: CMOVN_src
+/* 1180 */    MCD_OPC_FilterValue, 44, 59, 0, 0, // Skip to: 1244
+/* 1185 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1188 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1202
+/* 1193 */    MCD_OPC_CheckPredicate, 1, 40, 2, 0, // Skip to: 1750
+/* 1198 */    MCD_OPC_Decode, 248, 8, 5, // Opcode: ST_B_sro
+/* 1202 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1216
+/* 1207 */    MCD_OPC_CheckPredicate, 1, 26, 2, 0, // Skip to: 1750
+/* 1212 */    MCD_OPC_Decode, 170, 9, 5, // Opcode: ST_W_sro
+/* 1216 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1230
+/* 1221 */    MCD_OPC_CheckPredicate, 1, 12, 2, 0, // Skip to: 1750
+/* 1226 */    MCD_OPC_Decode, 147, 9, 5, // Opcode: ST_H_sro
+/* 1230 */    MCD_OPC_FilterValue, 3, 3, 2, 0, // Skip to: 1750
+/* 1235 */    MCD_OPC_CheckPredicate, 1, 254, 1, 0, // Skip to: 1750
+/* 1240 */    MCD_OPC_Decode, 233, 8, 5, // Opcode: ST_A_sro
+/* 1244 */    MCD_OPC_FilterValue, 46, 59, 0, 0, // Skip to: 1308
+/* 1249 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1252 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1266
+/* 1257 */    MCD_OPC_CheckPredicate, 1, 232, 1, 0, // Skip to: 1750
+/* 1262 */    MCD_OPC_Decode, 166, 4, 13, // Opcode: JZ_T_sbrn
+/* 1266 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1280
+/* 1271 */    MCD_OPC_CheckPredicate, 1, 218, 1, 0, // Skip to: 1750
+/* 1276 */    MCD_OPC_Decode, 168, 4, 9, // Opcode: JZ_sb
+/* 1280 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1294
+/* 1285 */    MCD_OPC_CheckPredicate, 1, 204, 1, 0, // Skip to: 1750
+/* 1290 */    MCD_OPC_Decode, 157, 4, 13, // Opcode: JNZ_T_sbrn
+/* 1294 */    MCD_OPC_FilterValue, 3, 195, 1, 0, // Skip to: 1750
+/* 1299 */    MCD_OPC_CheckPredicate, 1, 190, 1, 0, // Skip to: 1750
+/* 1304 */    MCD_OPC_Decode, 159, 4, 9, // Opcode: JNZ_sb
+/* 1308 */    MCD_OPC_FilterValue, 48, 31, 0, 0, // Skip to: 1344
+/* 1313 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1316 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1330
+/* 1321 */    MCD_OPC_CheckPredicate, 1, 168, 1, 0, // Skip to: 1750
+/* 1326 */    MCD_OPC_Decode, 161, 2, 1, // Opcode: ADD_A_srr
+/* 1330 */    MCD_OPC_FilterValue, 2, 159, 1, 0, // Skip to: 1750
+/* 1335 */    MCD_OPC_CheckPredicate, 1, 154, 1, 0, // Skip to: 1750
+/* 1340 */    MCD_OPC_Decode, 160, 2, 2, // Opcode: ADD_A_src
+/* 1344 */    MCD_OPC_FilterValue, 50, 108, 0, 0, // Skip to: 1457
+/* 1349 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 1352 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1373
+/* 1357 */    MCD_OPC_CheckPredicate, 1, 132, 1, 0, // Skip to: 1750
+/* 1362 */    MCD_OPC_CheckField, 6, 2, 0, 125, 1, 0, // Skip to: 1750
+/* 1369 */    MCD_OPC_Decode, 166, 8, 0, // Opcode: SAT_B_sr
+/* 1373 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 1394
+/* 1378 */    MCD_OPC_CheckPredicate, 1, 111, 1, 0, // Skip to: 1750
+/* 1383 */    MCD_OPC_CheckField, 6, 2, 0, 104, 1, 0, // Skip to: 1750
+/* 1390 */    MCD_OPC_Decode, 163, 8, 0, // Opcode: SAT_BU_sr
+/* 1394 */    MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 1415
+/* 1399 */    MCD_OPC_CheckPredicate, 1, 90, 1, 0, // Skip to: 1750
+/* 1404 */    MCD_OPC_CheckField, 6, 2, 0, 83, 1, 0, // Skip to: 1750
+/* 1411 */    MCD_OPC_Decode, 172, 8, 0, // Opcode: SAT_H_sr
+/* 1415 */    MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 1436
+/* 1420 */    MCD_OPC_CheckPredicate, 1, 69, 1, 0, // Skip to: 1750
+/* 1425 */    MCD_OPC_CheckField, 6, 2, 0, 62, 1, 0, // Skip to: 1750
+/* 1432 */    MCD_OPC_Decode, 169, 8, 0, // Opcode: SAT_HU_sr
+/* 1436 */    MCD_OPC_FilterValue, 5, 53, 1, 0, // Skip to: 1750
+/* 1441 */    MCD_OPC_CheckPredicate, 1, 48, 1, 0, // Skip to: 1750
+/* 1446 */    MCD_OPC_CheckField, 6, 2, 0, 41, 1, 0, // Skip to: 1750
+/* 1453 */    MCD_OPC_Decode, 160, 8, 0, // Opcode: RSUB_sr_sr
+/* 1457 */    MCD_OPC_FilterValue, 52, 59, 0, 0, // Skip to: 1521
+/* 1462 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1465 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1479
+/* 1470 */    MCD_OPC_CheckPredicate, 1, 19, 1, 0, // Skip to: 1750
+/* 1475 */    MCD_OPC_Decode, 250, 8, 11, // Opcode: ST_B_ssr
+/* 1479 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1493
+/* 1484 */    MCD_OPC_CheckPredicate, 1, 5, 1, 0, // Skip to: 1750
+/* 1489 */    MCD_OPC_Decode, 172, 9, 11, // Opcode: ST_W_ssr
+/* 1493 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1507
+/* 1498 */    MCD_OPC_CheckPredicate, 1, 247, 0, 0, // Skip to: 1750
+/* 1503 */    MCD_OPC_Decode, 149, 9, 11, // Opcode: ST_H_ssr
+/* 1507 */    MCD_OPC_FilterValue, 3, 238, 0, 0, // Skip to: 1750
+/* 1512 */    MCD_OPC_CheckPredicate, 1, 233, 0, 0, // Skip to: 1750
+/* 1517 */    MCD_OPC_Decode, 235, 8, 11, // Opcode: ST_A_ssr
+/* 1521 */    MCD_OPC_FilterValue, 54, 31, 0, 0, // Skip to: 1557
+/* 1526 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1529 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1543
+/* 1534 */    MCD_OPC_CheckPredicate, 1, 211, 0, 0, // Skip to: 1750
+/* 1539 */    MCD_OPC_Decode, 170, 4, 6, // Opcode: JZ_sbr
+/* 1543 */    MCD_OPC_FilterValue, 3, 202, 0, 0, // Skip to: 1750
+/* 1548 */    MCD_OPC_CheckPredicate, 1, 197, 0, 0, // Skip to: 1750
+/* 1553 */    MCD_OPC_Decode, 161, 4, 6, // Opcode: JNZ_sbr
+/* 1557 */    MCD_OPC_FilterValue, 56, 31, 0, 0, // Skip to: 1593
+/* 1562 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1565 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1579
+/* 1570 */    MCD_OPC_CheckPredicate, 1, 175, 0, 0, // Skip to: 1750
+/* 1575 */    MCD_OPC_Decode, 169, 9, 8, // Opcode: ST_W_sc
+/* 1579 */    MCD_OPC_FilterValue, 3, 166, 0, 0, // Skip to: 1750
+/* 1584 */    MCD_OPC_CheckPredicate, 1, 161, 0, 0, // Skip to: 1750
+/* 1589 */    MCD_OPC_Decode, 232, 8, 8, // Opcode: ST_A_sc
+/* 1593 */    MCD_OPC_FilterValue, 58, 39, 0, 0, // Skip to: 1637
+/* 1598 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1601 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1610
+/* 1606 */    MCD_OPC_Decode, 192, 3, 1, // Opcode: EQ_srr
+/* 1610 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1619
+/* 1615 */    MCD_OPC_Decode, 176, 5, 1, // Opcode: LT_srr
+/* 1619 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1628
+/* 1624 */    MCD_OPC_Decode, 191, 3, 2, // Opcode: EQ_src
+/* 1628 */    MCD_OPC_FilterValue, 3, 117, 0, 0, // Skip to: 1750
+/* 1633 */    MCD_OPC_Decode, 175, 5, 2, // Opcode: LT_src
+/* 1637 */    MCD_OPC_FilterValue, 60, 44, 0, 0, // Skip to: 1686
+/* 1642 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1645 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1659
+/* 1650 */    MCD_OPC_CheckPredicate, 1, 95, 0, 0, // Skip to: 1750
+/* 1655 */    MCD_OPC_Decode, 173, 4, 9, // Opcode: J_sb
+/* 1659 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1668
+/* 1664 */    MCD_OPC_Decode, 155, 4, 6, // Opcode: JNZ_A_sbr
+/* 1668 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1677
+/* 1673 */    MCD_OPC_Decode, 164, 4, 6, // Opcode: JZ_A_sbr
+/* 1677 */    MCD_OPC_FilterValue, 3, 68, 0, 0, // Skip to: 1750
+/* 1682 */    MCD_OPC_Decode, 161, 5, 6, // Opcode: LOOP_sbr
+/* 1686 */    MCD_OPC_FilterValue, 62, 59, 0, 0, // Skip to: 1750
+/* 1691 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1694 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1708
+/* 1699 */    MCD_OPC_CheckPredicate, 2, 46, 0, 0, // Skip to: 1750
+/* 1704 */    MCD_OPC_Decode, 242, 3, 6, // Opcode: JEQ_sbr1
+/* 1708 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1722
+/* 1713 */    MCD_OPC_CheckPredicate, 1, 32, 0, 0, // Skip to: 1750
+/* 1718 */    MCD_OPC_Decode, 151, 4, 6, // Opcode: JNE_sbr1
+/* 1722 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1736
+/* 1727 */    MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 1750
+/* 1732 */    MCD_OPC_Decode, 243, 3, 6, // Opcode: JEQ_sbr2
+/* 1736 */    MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 1750
+/* 1741 */    MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 1750
+/* 1746 */    MCD_OPC_Decode, 152, 4, 6, // Opcode: JNE_sbr2
+/* 1750 */    MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTable32[] = {
+/* 0 */       MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
+/* 3 */       MCD_OPC_FilterValue, 1, 231, 0, 0, // Skip to: 239
+/* 8 */       MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 11 */      MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 27
+/* 16 */      MCD_OPC_CheckField, 7, 1, 0, 192, 50, 0, // Skip to: 13015
+/* 23 */      MCD_OPC_Decode, 176, 6, 14, // Opcode: MOV_AA_rr
+/* 27 */      MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 43
+/* 32 */      MCD_OPC_CheckField, 7, 1, 0, 176, 50, 0, // Skip to: 13015
+/* 39 */      MCD_OPC_Decode, 159, 2, 14, // Opcode: ADD_A_rr
+/* 43 */      MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 59
+/* 48 */      MCD_OPC_CheckField, 7, 1, 0, 160, 50, 0, // Skip to: 13015
+/* 55 */      MCD_OPC_Decode, 188, 9, 14, // Opcode: SUB_A_rr
+/* 59 */      MCD_OPC_FilterValue, 128, 2, 11, 0, 0, // Skip to: 76
+/* 65 */      MCD_OPC_CheckField, 7, 1, 0, 143, 50, 0, // Skip to: 13015
+/* 72 */      MCD_OPC_Decode, 185, 3, 14, // Opcode: EQ_A_rr
+/* 76 */      MCD_OPC_FilterValue, 132, 2, 11, 0, 0, // Skip to: 93
+/* 82 */      MCD_OPC_CheckField, 7, 1, 0, 126, 50, 0, // Skip to: 13015
+/* 89 */      MCD_OPC_Decode, 232, 7, 14, // Opcode: NE_A
+/* 93 */      MCD_OPC_FilterValue, 136, 2, 11, 0, 0, // Skip to: 110
+/* 99 */      MCD_OPC_CheckField, 7, 1, 0, 109, 50, 0, // Skip to: 13015
+/* 106 */     MCD_OPC_Decode, 162, 5, 14, // Opcode: LT_A_rr
+/* 110 */     MCD_OPC_FilterValue, 140, 2, 11, 0, 0, // Skip to: 127
+/* 116 */     MCD_OPC_CheckField, 7, 1, 0, 92, 50, 0, // Skip to: 13015
+/* 123 */     MCD_OPC_Decode, 211, 3, 14, // Opcode: GE_A_rr
+/* 127 */     MCD_OPC_FilterValue, 160, 2, 11, 0, 0, // Skip to: 144
+/* 133 */     MCD_OPC_CheckField, 7, 1, 0, 75, 50, 0, // Skip to: 13015
+/* 140 */     MCD_OPC_Decode, 184, 3, 14, // Opcode: EQZ_A_rr
+/* 144 */     MCD_OPC_FilterValue, 164, 2, 11, 0, 0, // Skip to: 161
+/* 150 */     MCD_OPC_CheckField, 7, 1, 0, 58, 50, 0, // Skip to: 13015
+/* 157 */     MCD_OPC_Decode, 231, 7, 14, // Opcode: NEZ_A
+/* 161 */     MCD_OPC_FilterValue, 176, 2, 11, 0, 0, // Skip to: 178
+/* 167 */     MCD_OPC_CheckField, 7, 1, 0, 41, 50, 0, // Skip to: 13015
+/* 174 */     MCD_OPC_Decode, 183, 6, 14, // Opcode: MOV_D_rr
+/* 178 */     MCD_OPC_FilterValue, 128, 3, 16, 0, 0, // Skip to: 200
+/* 184 */     MCD_OPC_CheckPredicate, 1, 26, 50, 0, // Skip to: 13015
+/* 189 */     MCD_OPC_CheckField, 7, 1, 0, 19, 50, 0, // Skip to: 13015
+/* 196 */     MCD_OPC_Decode, 144, 2, 14, // Opcode: ADDSC_A_rr
+/* 200 */     MCD_OPC_FilterValue, 136, 3, 16, 0, 0, // Skip to: 222
+/* 206 */     MCD_OPC_CheckPredicate, 1, 4, 50, 0, // Skip to: 13015
+/* 211 */     MCD_OPC_CheckField, 7, 1, 0, 253, 49, 0, // Skip to: 13015
+/* 218 */     MCD_OPC_Decode, 142, 2, 14, // Opcode: ADDSC_AT_rr
+/* 222 */     MCD_OPC_FilterValue, 140, 3, 243, 49, 0, // Skip to: 13015
+/* 228 */     MCD_OPC_CheckField, 7, 1, 0, 236, 49, 0, // Skip to: 13015
+/* 235 */     MCD_OPC_Decode, 179, 6, 14, // Opcode: MOV_A_rr
+/* 239 */     MCD_OPC_FilterValue, 3, 132, 2, 0, // Skip to: 888
+/* 244 */     MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 247 */     MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 270
+/* 252 */     MCD_OPC_CheckField, 16, 2, 2, 212, 49, 0, // Skip to: 13015
+/* 259 */     MCD_OPC_CheckField, 7, 1, 0, 205, 49, 0, // Skip to: 13015
+/* 266 */     MCD_OPC_Decode, 154, 6, 15, // Opcode: MADD_rrr2
+/* 270 */     MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 291
+/* 275 */     MCD_OPC_CheckPredicate, 1, 191, 49, 0, // Skip to: 13015
+/* 280 */     MCD_OPC_CheckField, 7, 1, 1, 184, 49, 0, // Skip to: 13015
+/* 287 */     MCD_OPC_Decode, 206, 5, 16, // Opcode: MADDR_H_rrr1_UL
+/* 291 */     MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 312
+/* 296 */     MCD_OPC_CheckPredicate, 1, 170, 49, 0, // Skip to: 13015
+/* 301 */     MCD_OPC_CheckField, 7, 1, 1, 163, 49, 0, // Skip to: 13015
+/* 308 */     MCD_OPC_Decode, 205, 5, 16, // Opcode: MADDR_H_rrr1_LU
+/* 312 */     MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 333
+/* 317 */     MCD_OPC_CheckPredicate, 1, 149, 49, 0, // Skip to: 13015
+/* 322 */     MCD_OPC_CheckField, 7, 1, 1, 142, 49, 0, // Skip to: 13015
+/* 329 */     MCD_OPC_Decode, 204, 5, 16, // Opcode: MADDR_H_rrr1_LL
+/* 333 */     MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 354
+/* 338 */     MCD_OPC_CheckPredicate, 1, 128, 49, 0, // Skip to: 13015
+/* 343 */     MCD_OPC_CheckField, 7, 1, 1, 121, 49, 0, // Skip to: 13015
+/* 350 */     MCD_OPC_Decode, 208, 5, 16, // Opcode: MADDR_H_rrr1_UU
+/* 354 */     MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 375
+/* 359 */     MCD_OPC_CheckPredicate, 1, 107, 49, 0, // Skip to: 13015
+/* 364 */     MCD_OPC_CheckField, 7, 1, 1, 100, 49, 0, // Skip to: 13015
+/* 371 */     MCD_OPC_Decode, 136, 6, 16, // Opcode: MADD_H_rrr1_UL
+/* 375 */     MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 396
+/* 380 */     MCD_OPC_CheckPredicate, 1, 86, 49, 0, // Skip to: 13015
+/* 385 */     MCD_OPC_CheckField, 7, 1, 1, 79, 49, 0, // Skip to: 13015
+/* 392 */     MCD_OPC_Decode, 135, 6, 16, // Opcode: MADD_H_rrr1_LU
+/* 396 */     MCD_OPC_FilterValue, 26, 53, 0, 0, // Skip to: 454
+/* 401 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 404 */     MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 440
+/* 409 */     MCD_OPC_ExtractField, 16, 2,  // Inst{17-16} ...
+/* 412 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 426
+/* 417 */     MCD_OPC_CheckPredicate, 1, 49, 49, 0, // Skip to: 13015
+/* 422 */     MCD_OPC_Decode, 151, 6, 15, // Opcode: MADD_U_rrr2
+/* 426 */     MCD_OPC_FilterValue, 2, 40, 49, 0, // Skip to: 13015
+/* 431 */     MCD_OPC_CheckPredicate, 1, 35, 49, 0, // Skip to: 13015
+/* 436 */     MCD_OPC_Decode, 155, 6, 15, // Opcode: MADD_rrr2_e
+/* 440 */     MCD_OPC_FilterValue, 1, 26, 49, 0, // Skip to: 13015
+/* 445 */     MCD_OPC_CheckPredicate, 1, 21, 49, 0, // Skip to: 13015
+/* 450 */     MCD_OPC_Decode, 134, 6, 16, // Opcode: MADD_H_rrr1_LL
+/* 454 */     MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 475
+/* 459 */     MCD_OPC_CheckPredicate, 1, 7, 49, 0, // Skip to: 13015
+/* 464 */     MCD_OPC_CheckField, 7, 1, 1, 0, 49, 0, // Skip to: 13015
+/* 471 */     MCD_OPC_Decode, 137, 6, 16, // Opcode: MADD_H_rrr1_UU
+/* 475 */     MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 496
+/* 480 */     MCD_OPC_CheckPredicate, 1, 242, 48, 0, // Skip to: 13015
+/* 485 */     MCD_OPC_CheckField, 7, 1, 1, 235, 48, 0, // Skip to: 13015
+/* 492 */     MCD_OPC_Decode, 187, 5, 16, // Opcode: MADDM_H_rrr1_UL
+/* 496 */     MCD_OPC_FilterValue, 29, 16, 0, 0, // Skip to: 517
+/* 501 */     MCD_OPC_CheckPredicate, 1, 221, 48, 0, // Skip to: 13015
+/* 506 */     MCD_OPC_CheckField, 7, 1, 1, 214, 48, 0, // Skip to: 13015
+/* 513 */     MCD_OPC_Decode, 186, 5, 16, // Opcode: MADDM_H_rrr1_LU
+/* 517 */     MCD_OPC_FilterValue, 30, 16, 0, 0, // Skip to: 538
+/* 522 */     MCD_OPC_CheckPredicate, 1, 200, 48, 0, // Skip to: 13015
+/* 527 */     MCD_OPC_CheckField, 7, 1, 1, 193, 48, 0, // Skip to: 13015
+/* 534 */     MCD_OPC_Decode, 185, 5, 16, // Opcode: MADDM_H_rrr1_LL
+/* 538 */     MCD_OPC_FilterValue, 31, 16, 0, 0, // Skip to: 559
+/* 543 */     MCD_OPC_CheckPredicate, 1, 179, 48, 0, // Skip to: 13015
+/* 548 */     MCD_OPC_CheckField, 7, 1, 1, 172, 48, 0, // Skip to: 13015
+/* 555 */     MCD_OPC_Decode, 188, 5, 16, // Opcode: MADDM_H_rrr1_UU
+/* 559 */     MCD_OPC_FilterValue, 34, 35, 0, 0, // Skip to: 599
+/* 564 */     MCD_OPC_ExtractField, 16, 2,  // Inst{17-16} ...
+/* 567 */     MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 583
+/* 572 */     MCD_OPC_CheckField, 7, 1, 0, 148, 48, 0, // Skip to: 13015
+/* 579 */     MCD_OPC_Decode, 255, 5, 15, // Opcode: MADDS_U_rrr2
+/* 583 */     MCD_OPC_FilterValue, 2, 139, 48, 0, // Skip to: 13015
+/* 588 */     MCD_OPC_CheckField, 7, 1, 0, 132, 48, 0, // Skip to: 13015
+/* 595 */     MCD_OPC_Decode, 131, 6, 15, // Opcode: MADDS_rrr2
+/* 599 */     MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 620
+/* 604 */     MCD_OPC_CheckPredicate, 1, 118, 48, 0, // Skip to: 13015
+/* 609 */     MCD_OPC_CheckField, 7, 1, 1, 111, 48, 0, // Skip to: 13015
+/* 616 */     MCD_OPC_Decode, 197, 5, 16, // Opcode: MADDRS_H_rrr1_UL
+/* 620 */     MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 641
+/* 625 */     MCD_OPC_CheckPredicate, 1, 97, 48, 0, // Skip to: 13015
+/* 630 */     MCD_OPC_CheckField, 7, 1, 1, 90, 48, 0, // Skip to: 13015
+/* 637 */     MCD_OPC_Decode, 196, 5, 16, // Opcode: MADDRS_H_rrr1_LU
+/* 641 */     MCD_OPC_FilterValue, 46, 16, 0, 0, // Skip to: 662
+/* 646 */     MCD_OPC_CheckPredicate, 1, 76, 48, 0, // Skip to: 13015
+/* 651 */     MCD_OPC_CheckField, 7, 1, 1, 69, 48, 0, // Skip to: 13015
+/* 658 */     MCD_OPC_Decode, 195, 5, 16, // Opcode: MADDRS_H_rrr1_LL
+/* 662 */     MCD_OPC_FilterValue, 47, 16, 0, 0, // Skip to: 683
+/* 667 */     MCD_OPC_CheckPredicate, 1, 55, 48, 0, // Skip to: 13015
+/* 672 */     MCD_OPC_CheckField, 7, 1, 1, 48, 48, 0, // Skip to: 13015
+/* 679 */     MCD_OPC_Decode, 199, 5, 16, // Opcode: MADDRS_H_rrr1_UU
+/* 683 */     MCD_OPC_FilterValue, 56, 16, 0, 0, // Skip to: 704
+/* 688 */     MCD_OPC_CheckPredicate, 1, 34, 48, 0, // Skip to: 13015
+/* 693 */     MCD_OPC_CheckField, 7, 1, 1, 27, 48, 0, // Skip to: 13015
+/* 700 */     MCD_OPC_Decode, 239, 5, 16, // Opcode: MADDS_H_rrr1_UL
+/* 704 */     MCD_OPC_FilterValue, 57, 16, 0, 0, // Skip to: 725
+/* 709 */     MCD_OPC_CheckPredicate, 1, 13, 48, 0, // Skip to: 13015
+/* 714 */     MCD_OPC_CheckField, 7, 1, 1, 6, 48, 0, // Skip to: 13015
+/* 721 */     MCD_OPC_Decode, 238, 5, 16, // Opcode: MADDS_H_rrr1_LU
+/* 725 */     MCD_OPC_FilterValue, 58, 53, 0, 0, // Skip to: 783
+/* 730 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 733 */     MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 769
+/* 738 */     MCD_OPC_ExtractField, 16, 2,  // Inst{17-16} ...
+/* 741 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 755
+/* 746 */     MCD_OPC_CheckPredicate, 1, 232, 47, 0, // Skip to: 13015
+/* 751 */     MCD_OPC_Decode, 128, 6, 15, // Opcode: MADDS_U_rrr2_e
+/* 755 */     MCD_OPC_FilterValue, 2, 223, 47, 0, // Skip to: 13015
+/* 760 */     MCD_OPC_CheckPredicate, 1, 218, 47, 0, // Skip to: 13015
+/* 765 */     MCD_OPC_Decode, 132, 6, 15, // Opcode: MADDS_rrr2_e
+/* 769 */     MCD_OPC_FilterValue, 1, 209, 47, 0, // Skip to: 13015
+/* 774 */     MCD_OPC_CheckPredicate, 1, 204, 47, 0, // Skip to: 13015
+/* 779 */     MCD_OPC_Decode, 237, 5, 16, // Opcode: MADDS_H_rrr1_LL
+/* 783 */     MCD_OPC_FilterValue, 59, 16, 0, 0, // Skip to: 804
+/* 788 */     MCD_OPC_CheckPredicate, 1, 190, 47, 0, // Skip to: 13015
+/* 793 */     MCD_OPC_CheckField, 7, 1, 1, 183, 47, 0, // Skip to: 13015
+/* 800 */     MCD_OPC_Decode, 240, 5, 16, // Opcode: MADDS_H_rrr1_UU
+/* 804 */     MCD_OPC_FilterValue, 60, 16, 0, 0, // Skip to: 825
+/* 809 */     MCD_OPC_CheckPredicate, 1, 169, 47, 0, // Skip to: 13015
+/* 814 */     MCD_OPC_CheckField, 7, 1, 1, 162, 47, 0, // Skip to: 13015
+/* 821 */     MCD_OPC_Decode, 179, 5, 16, // Opcode: MADDMS_H_rrr1_UL
+/* 825 */     MCD_OPC_FilterValue, 61, 16, 0, 0, // Skip to: 846
+/* 830 */     MCD_OPC_CheckPredicate, 1, 148, 47, 0, // Skip to: 13015
+/* 835 */     MCD_OPC_CheckField, 7, 1, 1, 141, 47, 0, // Skip to: 13015
+/* 842 */     MCD_OPC_Decode, 178, 5, 16, // Opcode: MADDMS_H_rrr1_LU
+/* 846 */     MCD_OPC_FilterValue, 62, 16, 0, 0, // Skip to: 867
+/* 851 */     MCD_OPC_CheckPredicate, 1, 127, 47, 0, // Skip to: 13015
+/* 856 */     MCD_OPC_CheckField, 7, 1, 1, 120, 47, 0, // Skip to: 13015
+/* 863 */     MCD_OPC_Decode, 177, 5, 16, // Opcode: MADDMS_H_rrr1_LL
+/* 867 */     MCD_OPC_FilterValue, 63, 111, 47, 0, // Skip to: 13015
+/* 872 */     MCD_OPC_CheckPredicate, 1, 106, 47, 0, // Skip to: 13015
+/* 877 */     MCD_OPC_CheckField, 7, 1, 1, 99, 47, 0, // Skip to: 13015
+/* 884 */     MCD_OPC_Decode, 180, 5, 16, // Opcode: MADDMS_H_rrr1_UU
+/* 888 */     MCD_OPC_FilterValue, 5, 107, 0, 0, // Skip to: 1000
+/* 893 */     MCD_OPC_ExtractField, 26, 2,  // Inst{27-26} ...
+/* 896 */     MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 922
+/* 901 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 904 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 913
+/* 909 */     MCD_OPC_Decode, 216, 4, 17, // Opcode: LD_B_abs
+/* 913 */     MCD_OPC_FilterValue, 1, 65, 47, 0, // Skip to: 13015
+/* 918 */     MCD_OPC_Decode, 139, 5, 17, // Opcode: LD_W_abs
+/* 922 */     MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 948
+/* 927 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 930 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 939
+/* 935 */     MCD_OPC_Decode, 201, 4, 17, // Opcode: LD_BU_abs
+/* 939 */     MCD_OPC_FilterValue, 1, 39, 47, 0, // Skip to: 13015
+/* 944 */     MCD_OPC_Decode, 233, 4, 17, // Opcode: LD_D_abs
+/* 948 */     MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 974
+/* 953 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 956 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 965
+/* 961 */     MCD_OPC_Decode, 246, 4, 17, // Opcode: LD_H_abs
+/* 965 */     MCD_OPC_FilterValue, 1, 13, 47, 0, // Skip to: 13015
+/* 970 */     MCD_OPC_Decode, 185, 4, 17, // Opcode: LD_A_abs
+/* 974 */     MCD_OPC_FilterValue, 3, 4, 47, 0, // Skip to: 13015
+/* 979 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 982 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 991
+/* 987 */     MCD_OPC_Decode, 239, 4, 17, // Opcode: LD_HU_abs
+/* 991 */     MCD_OPC_FilterValue, 1, 243, 46, 0, // Skip to: 13015
+/* 996 */     MCD_OPC_Decode, 227, 4, 17, // Opcode: LD_DA_abs
+/* 1000 */    MCD_OPC_FilterValue, 7, 107, 0, 0, // Skip to: 1112
+/* 1005 */    MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
+/* 1008 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 1034
+/* 1013 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1016 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1025
+/* 1021 */    MCD_OPC_Decode, 228, 7, 18, // Opcode: NAND_T
+/* 1025 */    MCD_OPC_FilterValue, 1, 209, 46, 0, // Skip to: 13015
+/* 1030 */    MCD_OPC_Decode, 192, 2, 18, // Opcode: AND_T
+/* 1034 */    MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 1060
+/* 1039 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1042 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1051
+/* 1047 */    MCD_OPC_Decode, 243, 7, 18, // Opcode: ORN_T
+/* 1051 */    MCD_OPC_FilterValue, 1, 183, 46, 0, // Skip to: 13015
+/* 1056 */    MCD_OPC_Decode, 134, 8, 18, // Opcode: OR_T
+/* 1060 */    MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 1086
+/* 1065 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1068 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1077
+/* 1073 */    MCD_OPC_Decode, 232, 9, 18, // Opcode: XNOR_T
+/* 1077 */    MCD_OPC_FilterValue, 1, 157, 46, 0, // Skip to: 13015
+/* 1082 */    MCD_OPC_Decode, 237, 7, 18, // Opcode: NOR_T
+/* 1086 */    MCD_OPC_FilterValue, 3, 148, 46, 0, // Skip to: 13015
+/* 1091 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1094 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1103
+/* 1099 */    MCD_OPC_Decode, 247, 9, 18, // Opcode: XOR_T
+/* 1103 */    MCD_OPC_FilterValue, 1, 131, 46, 0, // Skip to: 13015
+/* 1108 */    MCD_OPC_Decode, 173, 2, 18, // Opcode: ANDN_T
+/* 1112 */    MCD_OPC_FilterValue, 9, 255, 3, 0, // Skip to: 2140
+/* 1117 */    MCD_OPC_ExtractField, 22, 6,  // Inst{27-22} ...
+/* 1120 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 1146
+/* 1125 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1128 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1137
+/* 1133 */    MCD_OPC_Decode, 219, 4, 19, // Opcode: LD_B_bo_pos
+/* 1137 */    MCD_OPC_FilterValue, 1, 97, 46, 0, // Skip to: 13015
+/* 1142 */    MCD_OPC_Decode, 244, 8, 19, // Opcode: ST_B_bo_pos
+/* 1146 */    MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 1162
+/* 1151 */    MCD_OPC_CheckField, 7, 1, 0, 81, 46, 0, // Skip to: 13015
+/* 1158 */    MCD_OPC_Decode, 204, 4, 19, // Opcode: LD_BU_bo_pos
+/* 1162 */    MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 1188
+/* 1167 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1170 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1179
+/* 1175 */    MCD_OPC_Decode, 249, 4, 19, // Opcode: LD_H_bo_pos
+/* 1179 */    MCD_OPC_FilterValue, 1, 55, 46, 0, // Skip to: 13015
+/* 1184 */    MCD_OPC_Decode, 143, 9, 19, // Opcode: ST_H_bo_pos
+/* 1188 */    MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 1204
+/* 1193 */    MCD_OPC_CheckField, 7, 1, 0, 39, 46, 0, // Skip to: 13015
+/* 1200 */    MCD_OPC_Decode, 242, 4, 19, // Opcode: LD_HU_bo_pos
+/* 1204 */    MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 1230
+/* 1209 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1212 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1221
+/* 1217 */    MCD_OPC_Decode, 142, 5, 19, // Opcode: LD_W_bo_pos
+/* 1221 */    MCD_OPC_FilterValue, 1, 13, 46, 0, // Skip to: 13015
+/* 1226 */    MCD_OPC_Decode, 165, 9, 19, // Opcode: ST_W_bo_pos
+/* 1230 */    MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 1256
+/* 1235 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1238 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1247
+/* 1243 */    MCD_OPC_Decode, 236, 4, 19, // Opcode: LD_D_bo_pos
+/* 1247 */    MCD_OPC_FilterValue, 1, 243, 45, 0, // Skip to: 13015
+/* 1252 */    MCD_OPC_Decode, 137, 9, 19, // Opcode: ST_D_bo_pos
+/* 1256 */    MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 1282
+/* 1261 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1264 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1273
+/* 1269 */    MCD_OPC_Decode, 188, 4, 19, // Opcode: LD_A_bo_pos
+/* 1273 */    MCD_OPC_FilterValue, 1, 217, 45, 0, // Skip to: 13015
+/* 1278 */    MCD_OPC_Decode, 228, 8, 19, // Opcode: ST_A_bo_pos
+/* 1282 */    MCD_OPC_FilterValue, 7, 21, 0, 0, // Skip to: 1308
+/* 1287 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1290 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1299
+/* 1295 */    MCD_OPC_Decode, 230, 4, 19, // Opcode: LD_DA_bo_pos
+/* 1299 */    MCD_OPC_FilterValue, 1, 191, 45, 0, // Skip to: 13015
+/* 1304 */    MCD_OPC_Decode, 131, 9, 19, // Opcode: ST_DA_bo_pos
+/* 1308 */    MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 1334
+/* 1313 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1316 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1325
+/* 1321 */    MCD_OPC_Decode, 136, 5, 19, // Opcode: LD_Q_bo_pos
+/* 1325 */    MCD_OPC_FilterValue, 1, 165, 45, 0, // Skip to: 13015
+/* 1330 */    MCD_OPC_Decode, 158, 9, 19, // Opcode: ST_Q_bo_pos
+/* 1334 */    MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 1355
+/* 1339 */    MCD_OPC_CheckPredicate, 0, 151, 45, 0, // Skip to: 13015
+/* 1344 */    MCD_OPC_CheckField, 7, 1, 1, 144, 45, 0, // Skip to: 13015
+/* 1351 */    MCD_OPC_Decode, 223, 2, 19, // Opcode: CACHEI_I_bo_pos
+/* 1355 */    MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 1376
+/* 1360 */    MCD_OPC_CheckPredicate, 3, 130, 45, 0, // Skip to: 13015
+/* 1365 */    MCD_OPC_CheckField, 7, 1, 1, 123, 45, 0, // Skip to: 13015
+/* 1372 */    MCD_OPC_Decode, 229, 2, 19, // Opcode: CACHEI_W_bo_pos
+/* 1376 */    MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 1397
+/* 1381 */    MCD_OPC_CheckPredicate, 1, 109, 45, 0, // Skip to: 13015
+/* 1386 */    MCD_OPC_CheckField, 7, 1, 1, 102, 45, 0, // Skip to: 13015
+/* 1393 */    MCD_OPC_Decode, 219, 2, 19, // Opcode: CACHEA_W_bo_pos
+/* 1397 */    MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 1418
+/* 1402 */    MCD_OPC_CheckPredicate, 1, 88, 45, 0, // Skip to: 13015
+/* 1407 */    MCD_OPC_CheckField, 7, 1, 1, 81, 45, 0, // Skip to: 13015
+/* 1414 */    MCD_OPC_Decode, 214, 2, 19, // Opcode: CACHEA_WI_bo_pos
+/* 1418 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 1439
+/* 1423 */    MCD_OPC_CheckPredicate, 1, 67, 45, 0, // Skip to: 13015
+/* 1428 */    MCD_OPC_CheckField, 7, 1, 1, 60, 45, 0, // Skip to: 13015
+/* 1435 */    MCD_OPC_Decode, 209, 2, 19, // Opcode: CACHEA_I_bo_pos
+/* 1439 */    MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 1460
+/* 1444 */    MCD_OPC_CheckPredicate, 3, 46, 45, 0, // Skip to: 13015
+/* 1449 */    MCD_OPC_CheckField, 7, 1, 1, 39, 45, 0, // Skip to: 13015
+/* 1456 */    MCD_OPC_Decode, 226, 2, 19, // Opcode: CACHEI_WI_bo_pos
+/* 1460 */    MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 1486
+/* 1465 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1468 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1477
+/* 1473 */    MCD_OPC_Decode, 220, 4, 19, // Opcode: LD_B_bo_pre
+/* 1477 */    MCD_OPC_FilterValue, 1, 13, 45, 0, // Skip to: 13015
+/* 1482 */    MCD_OPC_Decode, 245, 8, 19, // Opcode: ST_B_bo_pre
+/* 1486 */    MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 1502
+/* 1491 */    MCD_OPC_CheckField, 7, 1, 0, 253, 44, 0, // Skip to: 13015
+/* 1498 */    MCD_OPC_Decode, 205, 4, 19, // Opcode: LD_BU_bo_pre
+/* 1502 */    MCD_OPC_FilterValue, 18, 21, 0, 0, // Skip to: 1528
+/* 1507 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1510 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1519
+/* 1515 */    MCD_OPC_Decode, 250, 4, 19, // Opcode: LD_H_bo_pre
+/* 1519 */    MCD_OPC_FilterValue, 1, 227, 44, 0, // Skip to: 13015
+/* 1524 */    MCD_OPC_Decode, 144, 9, 19, // Opcode: ST_H_bo_pre
+/* 1528 */    MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 1544
+/* 1533 */    MCD_OPC_CheckField, 7, 1, 0, 211, 44, 0, // Skip to: 13015
+/* 1540 */    MCD_OPC_Decode, 243, 4, 19, // Opcode: LD_HU_bo_pre
+/* 1544 */    MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 1570
+/* 1549 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1552 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1561
+/* 1557 */    MCD_OPC_Decode, 143, 5, 19, // Opcode: LD_W_bo_pre
+/* 1561 */    MCD_OPC_FilterValue, 1, 185, 44, 0, // Skip to: 13015
+/* 1566 */    MCD_OPC_Decode, 166, 9, 19, // Opcode: ST_W_bo_pre
+/* 1570 */    MCD_OPC_FilterValue, 21, 21, 0, 0, // Skip to: 1596
+/* 1575 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1578 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1587
+/* 1583 */    MCD_OPC_Decode, 237, 4, 19, // Opcode: LD_D_bo_pre
+/* 1587 */    MCD_OPC_FilterValue, 1, 159, 44, 0, // Skip to: 13015
+/* 1592 */    MCD_OPC_Decode, 138, 9, 19, // Opcode: ST_D_bo_pre
+/* 1596 */    MCD_OPC_FilterValue, 22, 21, 0, 0, // Skip to: 1622
+/* 1601 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1604 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1613
+/* 1609 */    MCD_OPC_Decode, 189, 4, 19, // Opcode: LD_A_bo_pre
+/* 1613 */    MCD_OPC_FilterValue, 1, 133, 44, 0, // Skip to: 13015
+/* 1618 */    MCD_OPC_Decode, 229, 8, 19, // Opcode: ST_A_bo_pre
+/* 1622 */    MCD_OPC_FilterValue, 23, 21, 0, 0, // Skip to: 1648
+/* 1627 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1630 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1639
+/* 1635 */    MCD_OPC_Decode, 231, 4, 19, // Opcode: LD_DA_bo_pre
+/* 1639 */    MCD_OPC_FilterValue, 1, 107, 44, 0, // Skip to: 13015
+/* 1644 */    MCD_OPC_Decode, 132, 9, 19, // Opcode: ST_DA_bo_pre
+/* 1648 */    MCD_OPC_FilterValue, 24, 21, 0, 0, // Skip to: 1674
+/* 1653 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1656 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1665
+/* 1661 */    MCD_OPC_Decode, 137, 5, 19, // Opcode: LD_Q_bo_pre
+/* 1665 */    MCD_OPC_FilterValue, 1, 81, 44, 0, // Skip to: 13015
+/* 1670 */    MCD_OPC_Decode, 159, 9, 19, // Opcode: ST_Q_bo_pre
+/* 1674 */    MCD_OPC_FilterValue, 26, 16, 0, 0, // Skip to: 1695
+/* 1679 */    MCD_OPC_CheckPredicate, 0, 67, 44, 0, // Skip to: 13015
+/* 1684 */    MCD_OPC_CheckField, 7, 1, 1, 60, 44, 0, // Skip to: 13015
+/* 1691 */    MCD_OPC_Decode, 224, 2, 19, // Opcode: CACHEI_I_bo_pre
+/* 1695 */    MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 1716
+/* 1700 */    MCD_OPC_CheckPredicate, 3, 46, 44, 0, // Skip to: 13015
+/* 1705 */    MCD_OPC_CheckField, 7, 1, 1, 39, 44, 0, // Skip to: 13015
+/* 1712 */    MCD_OPC_Decode, 230, 2, 19, // Opcode: CACHEI_W_bo_pre
+/* 1716 */    MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 1737
+/* 1721 */    MCD_OPC_CheckPredicate, 1, 25, 44, 0, // Skip to: 13015
+/* 1726 */    MCD_OPC_CheckField, 7, 1, 1, 18, 44, 0, // Skip to: 13015
+/* 1733 */    MCD_OPC_Decode, 220, 2, 19, // Opcode: CACHEA_W_bo_pre
+/* 1737 */    MCD_OPC_FilterValue, 29, 16, 0, 0, // Skip to: 1758
+/* 1742 */    MCD_OPC_CheckPredicate, 1, 4, 44, 0, // Skip to: 13015
+/* 1747 */    MCD_OPC_CheckField, 7, 1, 1, 253, 43, 0, // Skip to: 13015
+/* 1754 */    MCD_OPC_Decode, 215, 2, 19, // Opcode: CACHEA_WI_bo_pre
+/* 1758 */    MCD_OPC_FilterValue, 30, 16, 0, 0, // Skip to: 1779
+/* 1763 */    MCD_OPC_CheckPredicate, 1, 239, 43, 0, // Skip to: 13015
+/* 1768 */    MCD_OPC_CheckField, 7, 1, 1, 232, 43, 0, // Skip to: 13015
+/* 1775 */    MCD_OPC_Decode, 210, 2, 19, // Opcode: CACHEA_I_bo_pre
+/* 1779 */    MCD_OPC_FilterValue, 31, 16, 0, 0, // Skip to: 1800
+/* 1784 */    MCD_OPC_CheckPredicate, 3, 218, 43, 0, // Skip to: 13015
+/* 1789 */    MCD_OPC_CheckField, 7, 1, 1, 211, 43, 0, // Skip to: 13015
+/* 1796 */    MCD_OPC_Decode, 227, 2, 19, // Opcode: CACHEI_WI_bo_pre
+/* 1800 */    MCD_OPC_FilterValue, 32, 21, 0, 0, // Skip to: 1826
+/* 1805 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1808 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1817
+/* 1813 */    MCD_OPC_Decode, 217, 4, 19, // Opcode: LD_B_bo_bso
+/* 1817 */    MCD_OPC_FilterValue, 1, 185, 43, 0, // Skip to: 13015
+/* 1822 */    MCD_OPC_Decode, 242, 8, 19, // Opcode: ST_B_bo_bso
+/* 1826 */    MCD_OPC_FilterValue, 33, 11, 0, 0, // Skip to: 1842
+/* 1831 */    MCD_OPC_CheckField, 7, 1, 0, 169, 43, 0, // Skip to: 13015
+/* 1838 */    MCD_OPC_Decode, 202, 4, 19, // Opcode: LD_BU_bo_bso
+/* 1842 */    MCD_OPC_FilterValue, 34, 21, 0, 0, // Skip to: 1868
+/* 1847 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1850 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1859
+/* 1855 */    MCD_OPC_Decode, 247, 4, 19, // Opcode: LD_H_bo_bso
+/* 1859 */    MCD_OPC_FilterValue, 1, 143, 43, 0, // Skip to: 13015
+/* 1864 */    MCD_OPC_Decode, 141, 9, 19, // Opcode: ST_H_bo_bso
+/* 1868 */    MCD_OPC_FilterValue, 35, 11, 0, 0, // Skip to: 1884
+/* 1873 */    MCD_OPC_CheckField, 7, 1, 0, 127, 43, 0, // Skip to: 13015
+/* 1880 */    MCD_OPC_Decode, 240, 4, 19, // Opcode: LD_HU_bo_bso
+/* 1884 */    MCD_OPC_FilterValue, 36, 21, 0, 0, // Skip to: 1910
+/* 1889 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1892 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1901
+/* 1897 */    MCD_OPC_Decode, 140, 5, 19, // Opcode: LD_W_bo_bso
+/* 1901 */    MCD_OPC_FilterValue, 1, 101, 43, 0, // Skip to: 13015
+/* 1906 */    MCD_OPC_Decode, 163, 9, 19, // Opcode: ST_W_bo_bso
+/* 1910 */    MCD_OPC_FilterValue, 37, 21, 0, 0, // Skip to: 1936
+/* 1915 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1918 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1927
+/* 1923 */    MCD_OPC_Decode, 234, 4, 19, // Opcode: LD_D_bo_bso
+/* 1927 */    MCD_OPC_FilterValue, 1, 75, 43, 0, // Skip to: 13015
+/* 1932 */    MCD_OPC_Decode, 135, 9, 19, // Opcode: ST_D_bo_bso
+/* 1936 */    MCD_OPC_FilterValue, 38, 21, 0, 0, // Skip to: 1962
+/* 1941 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1944 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1953
+/* 1949 */    MCD_OPC_Decode, 186, 4, 19, // Opcode: LD_A_bo_bso
+/* 1953 */    MCD_OPC_FilterValue, 1, 49, 43, 0, // Skip to: 13015
+/* 1958 */    MCD_OPC_Decode, 226, 8, 19, // Opcode: ST_A_bo_bso
+/* 1962 */    MCD_OPC_FilterValue, 39, 21, 0, 0, // Skip to: 1988
+/* 1967 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1970 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1979
+/* 1975 */    MCD_OPC_Decode, 228, 4, 19, // Opcode: LD_DA_bo_bso
+/* 1979 */    MCD_OPC_FilterValue, 1, 23, 43, 0, // Skip to: 13015
+/* 1984 */    MCD_OPC_Decode, 129, 9, 19, // Opcode: ST_DA_bo_bso
+/* 1988 */    MCD_OPC_FilterValue, 40, 21, 0, 0, // Skip to: 2014
+/* 1993 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1996 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2005
+/* 2001 */    MCD_OPC_Decode, 134, 5, 19, // Opcode: LD_Q_bo_bso
+/* 2005 */    MCD_OPC_FilterValue, 1, 253, 42, 0, // Skip to: 13015
+/* 2010 */    MCD_OPC_Decode, 156, 9, 19, // Opcode: ST_Q_bo_bso
+/* 2014 */    MCD_OPC_FilterValue, 42, 16, 0, 0, // Skip to: 2035
+/* 2019 */    MCD_OPC_CheckPredicate, 0, 239, 42, 0, // Skip to: 13015
+/* 2024 */    MCD_OPC_CheckField, 7, 1, 1, 232, 42, 0, // Skip to: 13015
+/* 2031 */    MCD_OPC_Decode, 222, 2, 19, // Opcode: CACHEI_I_bo_bso
+/* 2035 */    MCD_OPC_FilterValue, 43, 16, 0, 0, // Skip to: 2056
+/* 2040 */    MCD_OPC_CheckPredicate, 3, 218, 42, 0, // Skip to: 13015
+/* 2045 */    MCD_OPC_CheckField, 7, 1, 1, 211, 42, 0, // Skip to: 13015
+/* 2052 */    MCD_OPC_Decode, 228, 2, 19, // Opcode: CACHEI_W_bo_bso
+/* 2056 */    MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 2077
+/* 2061 */    MCD_OPC_CheckPredicate, 1, 197, 42, 0, // Skip to: 13015
+/* 2066 */    MCD_OPC_CheckField, 7, 1, 1, 190, 42, 0, // Skip to: 13015
+/* 2073 */    MCD_OPC_Decode, 217, 2, 19, // Opcode: CACHEA_W_bo_bso
+/* 2077 */    MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 2098
+/* 2082 */    MCD_OPC_CheckPredicate, 1, 176, 42, 0, // Skip to: 13015
+/* 2087 */    MCD_OPC_CheckField, 7, 1, 1, 169, 42, 0, // Skip to: 13015
+/* 2094 */    MCD_OPC_Decode, 212, 2, 19, // Opcode: CACHEA_WI_bo_bso
+/* 2098 */    MCD_OPC_FilterValue, 46, 16, 0, 0, // Skip to: 2119
+/* 2103 */    MCD_OPC_CheckPredicate, 1, 155, 42, 0, // Skip to: 13015
+/* 2108 */    MCD_OPC_CheckField, 7, 1, 1, 148, 42, 0, // Skip to: 13015
+/* 2115 */    MCD_OPC_Decode, 207, 2, 19, // Opcode: CACHEA_I_bo_bso
+/* 2119 */    MCD_OPC_FilterValue, 47, 139, 42, 0, // Skip to: 13015
+/* 2124 */    MCD_OPC_CheckPredicate, 3, 134, 42, 0, // Skip to: 13015
+/* 2129 */    MCD_OPC_CheckField, 7, 1, 1, 127, 42, 0, // Skip to: 13015
+/* 2136 */    MCD_OPC_Decode, 225, 2, 19, // Opcode: CACHEI_WI_bo_bso
+/* 2140 */    MCD_OPC_FilterValue, 11, 206, 8, 0, // Skip to: 4399
+/* 2145 */    MCD_OPC_ExtractField, 21, 7,  // Inst{27-21} ...
+/* 2148 */    MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 2181
+/* 2153 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2156 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2172
+/* 2161 */    MCD_OPC_CheckField, 18, 3, 0, 95, 42, 0, // Skip to: 13015
+/* 2168 */    MCD_OPC_Decode, 166, 2, 14, // Opcode: ADD_rr
+/* 2172 */    MCD_OPC_FilterValue, 1, 86, 42, 0, // Skip to: 13015
+/* 2177 */    MCD_OPC_Decode, 165, 2, 20, // Opcode: ADD_rc
+/* 2181 */    MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 2221
+/* 2186 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2189 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2205
+/* 2194 */    MCD_OPC_CheckField, 7, 1, 0, 62, 42, 0, // Skip to: 13015
+/* 2201 */    MCD_OPC_Decode, 155, 2, 14, // Opcode: ADDS_rr
+/* 2205 */    MCD_OPC_FilterValue, 4, 53, 42, 0, // Skip to: 13015
+/* 2210 */    MCD_OPC_CheckField, 7, 1, 0, 46, 42, 0, // Skip to: 13015
+/* 2217 */    MCD_OPC_Decode, 152, 2, 14, // Opcode: ADDS_U
+/* 2221 */    MCD_OPC_FilterValue, 2, 38, 0, 0, // Skip to: 2264
+/* 2226 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2229 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2255
+/* 2234 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2237 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2246
+/* 2242 */    MCD_OPC_Decode, 158, 2, 14, // Opcode: ADDX_rr
+/* 2246 */    MCD_OPC_FilterValue, 4, 12, 42, 0, // Skip to: 13015
+/* 2251 */    MCD_OPC_Decode, 138, 2, 14, // Opcode: ADDC_rr
+/* 2255 */    MCD_OPC_FilterValue, 1, 3, 42, 0, // Skip to: 13015
+/* 2260 */    MCD_OPC_Decode, 154, 2, 20, // Opcode: ADDS_rc
+/* 2264 */    MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 2280
+/* 2269 */    MCD_OPC_CheckField, 7, 1, 1, 243, 41, 0, // Skip to: 13015
+/* 2276 */    MCD_OPC_Decode, 153, 2, 20, // Opcode: ADDS_U_rc
+/* 2280 */    MCD_OPC_FilterValue, 4, 28, 0, 0, // Skip to: 2313
+/* 2285 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2288 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2304
+/* 2293 */    MCD_OPC_CheckField, 18, 3, 0, 219, 41, 0, // Skip to: 13015
+/* 2300 */    MCD_OPC_Decode, 194, 9, 14, // Opcode: SUB_rr
+/* 2304 */    MCD_OPC_FilterValue, 1, 210, 41, 0, // Skip to: 13015
+/* 2309 */    MCD_OPC_Decode, 157, 2, 20, // Opcode: ADDX_rc
+/* 2313 */    MCD_OPC_FilterValue, 5, 38, 0, 0, // Skip to: 2356
+/* 2318 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2321 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2347
+/* 2326 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2329 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2338
+/* 2334 */    MCD_OPC_Decode, 185, 9, 14, // Opcode: SUBS_rr
+/* 2338 */    MCD_OPC_FilterValue, 4, 176, 41, 0, // Skip to: 13015
+/* 2343 */    MCD_OPC_Decode, 184, 9, 14, // Opcode: SUBS_U_rr
+/* 2347 */    MCD_OPC_FilterValue, 1, 167, 41, 0, // Skip to: 13015
+/* 2352 */    MCD_OPC_Decode, 137, 2, 20, // Opcode: ADDC_rc
+/* 2356 */    MCD_OPC_FilterValue, 6, 35, 0, 0, // Skip to: 2396
+/* 2361 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2364 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2380
+/* 2369 */    MCD_OPC_CheckField, 7, 1, 0, 143, 41, 0, // Skip to: 13015
+/* 2376 */    MCD_OPC_Decode, 187, 9, 14, // Opcode: SUBX_rr
+/* 2380 */    MCD_OPC_FilterValue, 4, 134, 41, 0, // Skip to: 13015
+/* 2385 */    MCD_OPC_CheckField, 7, 1, 0, 127, 41, 0, // Skip to: 13015
+/* 2392 */    MCD_OPC_Decode, 178, 9, 14, // Opcode: SUBC_rr
+/* 2396 */    MCD_OPC_FilterValue, 7, 35, 0, 0, // Skip to: 2436
+/* 2401 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2404 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2420
+/* 2409 */    MCD_OPC_CheckField, 7, 1, 0, 103, 41, 0, // Skip to: 13015
+/* 2416 */    MCD_OPC_Decode, 130, 2, 14, // Opcode: ABSDIF_rr
+/* 2420 */    MCD_OPC_FilterValue, 4, 94, 41, 0, // Skip to: 13015
+/* 2425 */    MCD_OPC_CheckField, 7, 1, 0, 87, 41, 0, // Skip to: 13015
+/* 2432 */    MCD_OPC_Decode, 254, 1, 14, // Opcode: ABSDIFS_rr
+/* 2436 */    MCD_OPC_FilterValue, 8, 38, 0, 0, // Skip to: 2479
+/* 2441 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2444 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2470
+/* 2449 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2452 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2461
+/* 2457 */    MCD_OPC_Decode, 190, 3, 14, // Opcode: EQ_rr
+/* 2461 */    MCD_OPC_FilterValue, 4, 53, 41, 0, // Skip to: 13015
+/* 2466 */    MCD_OPC_Decode, 234, 7, 14, // Opcode: NE_rr
+/* 2470 */    MCD_OPC_FilterValue, 1, 44, 41, 0, // Skip to: 13015
+/* 2475 */    MCD_OPC_Decode, 159, 8, 20, // Opcode: RSUB_rc
+/* 2479 */    MCD_OPC_FilterValue, 9, 35, 0, 0, // Skip to: 2519
+/* 2484 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2487 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2503
+/* 2492 */    MCD_OPC_CheckField, 7, 1, 0, 20, 41, 0, // Skip to: 13015
+/* 2499 */    MCD_OPC_Decode, 174, 5, 14, // Opcode: LT_rr
+/* 2503 */    MCD_OPC_FilterValue, 4, 11, 41, 0, // Skip to: 13015
+/* 2508 */    MCD_OPC_CheckField, 7, 1, 0, 4, 41, 0, // Skip to: 13015
+/* 2515 */    MCD_OPC_Decode, 168, 5, 14, // Opcode: LT_U_rr
+/* 2519 */    MCD_OPC_FilterValue, 10, 38, 0, 0, // Skip to: 2562
+/* 2524 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2527 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2553
+/* 2532 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2535 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2544
+/* 2540 */    MCD_OPC_Decode, 215, 3, 14, // Opcode: GE_rr
+/* 2544 */    MCD_OPC_FilterValue, 4, 226, 40, 0, // Skip to: 13015
+/* 2549 */    MCD_OPC_Decode, 213, 3, 14, // Opcode: GE_U_rr
+/* 2553 */    MCD_OPC_FilterValue, 1, 217, 40, 0, // Skip to: 13015
+/* 2558 */    MCD_OPC_Decode, 158, 8, 20, // Opcode: RSUBS_rc
+/* 2562 */    MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 2578
+/* 2567 */    MCD_OPC_CheckField, 7, 1, 1, 201, 40, 0, // Skip to: 13015
+/* 2574 */    MCD_OPC_Decode, 157, 8, 20, // Opcode: RSUBS_U_rc
+/* 2578 */    MCD_OPC_FilterValue, 12, 35, 0, 0, // Skip to: 2618
+/* 2583 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2586 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2602
+/* 2591 */    MCD_OPC_CheckField, 7, 1, 0, 177, 40, 0, // Skip to: 13015
+/* 2598 */    MCD_OPC_Decode, 172, 6, 14, // Opcode: MIN_rr
+/* 2602 */    MCD_OPC_FilterValue, 4, 168, 40, 0, // Skip to: 13015
+/* 2607 */    MCD_OPC_CheckField, 7, 1, 0, 161, 40, 0, // Skip to: 13015
+/* 2614 */    MCD_OPC_Decode, 170, 6, 14, // Opcode: MIN_U_rr
+/* 2618 */    MCD_OPC_FilterValue, 13, 35, 0, 0, // Skip to: 2658
+/* 2623 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2626 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2642
+/* 2631 */    MCD_OPC_CheckField, 7, 1, 0, 137, 40, 0, // Skip to: 13015
+/* 2638 */    MCD_OPC_Decode, 163, 6, 14, // Opcode: MAX_rr
+/* 2642 */    MCD_OPC_FilterValue, 4, 128, 40, 0, // Skip to: 13015
+/* 2647 */    MCD_OPC_CheckField, 7, 1, 0, 121, 40, 0, // Skip to: 13015
+/* 2654 */    MCD_OPC_Decode, 161, 6, 14, // Opcode: MAX_U_rr
+/* 2658 */    MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 2701
+/* 2663 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2666 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2692
+/* 2671 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2674 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2683
+/* 2679 */    MCD_OPC_Decode, 136, 2, 14, // Opcode: ABS_rr
+/* 2683 */    MCD_OPC_FilterValue, 4, 87, 40, 0, // Skip to: 13015
+/* 2688 */    MCD_OPC_Decode, 133, 2, 14, // Opcode: ABSS_rr
+/* 2692 */    MCD_OPC_FilterValue, 1, 78, 40, 0, // Skip to: 13015
+/* 2697 */    MCD_OPC_Decode, 129, 2, 20, // Opcode: ABSDIF_rc
+/* 2701 */    MCD_OPC_FilterValue, 15, 28, 0, 0, // Skip to: 2734
+/* 2706 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2709 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2725
+/* 2714 */    MCD_OPC_CheckField, 18, 3, 4, 54, 40, 0, // Skip to: 13015
+/* 2721 */    MCD_OPC_Decode, 189, 6, 14, // Opcode: MOV_rr
+/* 2725 */    MCD_OPC_FilterValue, 1, 45, 40, 0, // Skip to: 13015
+/* 2730 */    MCD_OPC_Decode, 253, 1, 20, // Opcode: ABSDIFS_rc
+/* 2734 */    MCD_OPC_FilterValue, 16, 38, 0, 0, // Skip to: 2777
+/* 2739 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2742 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2768
+/* 2747 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2750 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2759
+/* 2755 */    MCD_OPC_Decode, 179, 2, 14, // Opcode: AND_EQ_rr
+/* 2759 */    MCD_OPC_FilterValue, 4, 11, 40, 0, // Skip to: 13015
+/* 2764 */    MCD_OPC_Decode, 189, 2, 14, // Opcode: AND_NE_rr
+/* 2768 */    MCD_OPC_FilterValue, 1, 2, 40, 0, // Skip to: 13015
+/* 2773 */    MCD_OPC_Decode, 189, 3, 20, // Opcode: EQ_rc
+/* 2777 */    MCD_OPC_FilterValue, 17, 38, 0, 0, // Skip to: 2820
+/* 2782 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2785 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2811
+/* 2790 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2793 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2802
+/* 2798 */    MCD_OPC_Decode, 187, 2, 14, // Opcode: AND_LT_rr
+/* 2802 */    MCD_OPC_FilterValue, 4, 224, 39, 0, // Skip to: 13015
+/* 2807 */    MCD_OPC_Decode, 185, 2, 14, // Opcode: AND_LT_U_rr
+/* 2811 */    MCD_OPC_FilterValue, 1, 215, 39, 0, // Skip to: 13015
+/* 2816 */    MCD_OPC_Decode, 233, 7, 20, // Opcode: NE_rc
+/* 2820 */    MCD_OPC_FilterValue, 18, 38, 0, 0, // Skip to: 2863
+/* 2825 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2828 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2854
+/* 2833 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2836 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2845
+/* 2841 */    MCD_OPC_Decode, 183, 2, 14, // Opcode: AND_GE_rr
+/* 2845 */    MCD_OPC_FilterValue, 4, 181, 39, 0, // Skip to: 13015
+/* 2850 */    MCD_OPC_Decode, 181, 2, 14, // Opcode: AND_GE_U_rr
+/* 2854 */    MCD_OPC_FilterValue, 1, 172, 39, 0, // Skip to: 13015
+/* 2859 */    MCD_OPC_Decode, 173, 5, 20, // Opcode: LT_rc
+/* 2863 */    MCD_OPC_FilterValue, 19, 28, 0, 0, // Skip to: 2896
+/* 2868 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2871 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2887
+/* 2876 */    MCD_OPC_CheckField, 18, 3, 4, 148, 39, 0, // Skip to: 13015
+/* 2883 */    MCD_OPC_Decode, 249, 7, 14, // Opcode: OR_EQ_rr
+/* 2887 */    MCD_OPC_FilterValue, 1, 139, 39, 0, // Skip to: 13015
+/* 2892 */    MCD_OPC_Decode, 167, 5, 20, // Opcode: LT_U_rc
+/* 2896 */    MCD_OPC_FilterValue, 20, 38, 0, 0, // Skip to: 2939
+/* 2901 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2904 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2930
+/* 2909 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2912 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2921
+/* 2917 */    MCD_OPC_Decode, 131, 8, 14, // Opcode: OR_NE_rr
+/* 2921 */    MCD_OPC_FilterValue, 4, 105, 39, 0, // Skip to: 13015
+/* 2926 */    MCD_OPC_Decode, 129, 8, 14, // Opcode: OR_LT_rr
+/* 2930 */    MCD_OPC_FilterValue, 1, 96, 39, 0, // Skip to: 13015
+/* 2935 */    MCD_OPC_Decode, 214, 3, 20, // Opcode: GE_rc
+/* 2939 */    MCD_OPC_FilterValue, 21, 38, 0, 0, // Skip to: 2982
+/* 2944 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2947 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2973
+/* 2952 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 2955 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2964
+/* 2960 */    MCD_OPC_Decode, 255, 7, 14, // Opcode: OR_LT_U_rr
+/* 2964 */    MCD_OPC_FilterValue, 4, 62, 39, 0, // Skip to: 13015
+/* 2969 */    MCD_OPC_Decode, 253, 7, 14, // Opcode: OR_GE_rr
+/* 2973 */    MCD_OPC_FilterValue, 1, 53, 39, 0, // Skip to: 13015
+/* 2978 */    MCD_OPC_Decode, 212, 3, 20, // Opcode: GE_U_rc
+/* 2982 */    MCD_OPC_FilterValue, 22, 18, 0, 0, // Skip to: 3005
+/* 2987 */    MCD_OPC_CheckField, 18, 3, 0, 37, 39, 0, // Skip to: 13015
+/* 2994 */    MCD_OPC_CheckField, 7, 1, 0, 30, 39, 0, // Skip to: 13015
+/* 3001 */    MCD_OPC_Decode, 251, 7, 14, // Opcode: OR_GE_U_rr
+/* 3005 */    MCD_OPC_FilterValue, 23, 18, 0, 0, // Skip to: 3028
+/* 3010 */    MCD_OPC_CheckField, 18, 3, 4, 14, 39, 0, // Skip to: 13015
+/* 3017 */    MCD_OPC_CheckField, 7, 1, 0, 7, 39, 0, // Skip to: 13015
+/* 3024 */    MCD_OPC_Decode, 236, 9, 14, // Opcode: XOR_EQ_rr
+/* 3028 */    MCD_OPC_FilterValue, 24, 38, 0, 0, // Skip to: 3071
+/* 3033 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3036 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 3062
+/* 3041 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3044 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3053
+/* 3049 */    MCD_OPC_Decode, 246, 9, 14, // Opcode: XOR_NE_rr
+/* 3053 */    MCD_OPC_FilterValue, 4, 229, 38, 0, // Skip to: 13015
+/* 3058 */    MCD_OPC_Decode, 244, 9, 14, // Opcode: XOR_LT_rr
+/* 3062 */    MCD_OPC_FilterValue, 1, 220, 38, 0, // Skip to: 13015
+/* 3067 */    MCD_OPC_Decode, 171, 6, 20, // Opcode: MIN_rc
+/* 3071 */    MCD_OPC_FilterValue, 25, 38, 0, 0, // Skip to: 3114
+/* 3076 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3079 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 3105
+/* 3084 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3087 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3096
+/* 3092 */    MCD_OPC_Decode, 242, 9, 14, // Opcode: XOR_LT_U_rr
+/* 3096 */    MCD_OPC_FilterValue, 4, 186, 38, 0, // Skip to: 13015
+/* 3101 */    MCD_OPC_Decode, 240, 9, 14, // Opcode: XOR_GE_rr
+/* 3105 */    MCD_OPC_FilterValue, 1, 177, 38, 0, // Skip to: 13015
+/* 3110 */    MCD_OPC_Decode, 169, 6, 20, // Opcode: MIN_U_rc
+/* 3114 */    MCD_OPC_FilterValue, 26, 28, 0, 0, // Skip to: 3147
+/* 3119 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3122 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3138
+/* 3127 */    MCD_OPC_CheckField, 18, 3, 0, 153, 38, 0, // Skip to: 13015
+/* 3134 */    MCD_OPC_Decode, 238, 9, 14, // Opcode: XOR_GE_U_rr
+/* 3138 */    MCD_OPC_FilterValue, 1, 144, 38, 0, // Skip to: 13015
+/* 3143 */    MCD_OPC_Decode, 162, 6, 20, // Opcode: MAX_rc
+/* 3147 */    MCD_OPC_FilterValue, 27, 28, 0, 0, // Skip to: 3180
+/* 3152 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3155 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3171
+/* 3160 */    MCD_OPC_CheckField, 18, 3, 4, 120, 38, 0, // Skip to: 13015
+/* 3167 */    MCD_OPC_Decode, 198, 8, 14, // Opcode: SH_EQ_rr
+/* 3171 */    MCD_OPC_FilterValue, 1, 111, 38, 0, // Skip to: 13015
+/* 3176 */    MCD_OPC_Decode, 160, 6, 20, // Opcode: MAX_U_rc
+/* 3180 */    MCD_OPC_FilterValue, 28, 35, 0, 0, // Skip to: 3220
+/* 3185 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3188 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3204
+/* 3193 */    MCD_OPC_CheckField, 7, 1, 0, 87, 38, 0, // Skip to: 13015
+/* 3200 */    MCD_OPC_Decode, 211, 8, 14, // Opcode: SH_NE_rr
+/* 3204 */    MCD_OPC_FilterValue, 4, 78, 38, 0, // Skip to: 13015
+/* 3209 */    MCD_OPC_CheckField, 7, 1, 0, 71, 38, 0, // Skip to: 13015
+/* 3216 */    MCD_OPC_Decode, 208, 8, 14, // Opcode: SH_LT_rr
+/* 3220 */    MCD_OPC_FilterValue, 29, 35, 0, 0, // Skip to: 3260
+/* 3225 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3228 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3244
+/* 3233 */    MCD_OPC_CheckField, 7, 1, 0, 47, 38, 0, // Skip to: 13015
+/* 3240 */    MCD_OPC_Decode, 206, 8, 14, // Opcode: SH_LT_U_rr
+/* 3244 */    MCD_OPC_FilterValue, 4, 38, 38, 0, // Skip to: 13015
+/* 3249 */    MCD_OPC_CheckField, 7, 1, 0, 31, 38, 0, // Skip to: 13015
+/* 3256 */    MCD_OPC_Decode, 202, 8, 14, // Opcode: SH_GE_rr
+/* 3260 */    MCD_OPC_FilterValue, 30, 18, 0, 0, // Skip to: 3283
+/* 3265 */    MCD_OPC_CheckField, 18, 3, 0, 15, 38, 0, // Skip to: 13015
+/* 3272 */    MCD_OPC_CheckField, 7, 1, 0, 8, 38, 0, // Skip to: 13015
+/* 3279 */    MCD_OPC_Decode, 200, 8, 14, // Opcode: SH_GE_U_rr
+/* 3283 */    MCD_OPC_FilterValue, 32, 28, 0, 0, // Skip to: 3316
+/* 3288 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3291 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3307
+/* 3296 */    MCD_OPC_CheckField, 18, 3, 0, 240, 37, 0, // Skip to: 13015
+/* 3303 */    MCD_OPC_Decode, 162, 2, 14, // Opcode: ADD_B_rr
+/* 3307 */    MCD_OPC_FilterValue, 1, 231, 37, 0, // Skip to: 13015
+/* 3312 */    MCD_OPC_Decode, 178, 2, 20, // Opcode: AND_EQ_rc
+/* 3316 */    MCD_OPC_FilterValue, 33, 33, 0, 0, // Skip to: 3354
+/* 3321 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3324 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3345
+/* 3329 */    MCD_OPC_CheckPredicate, 4, 209, 37, 0, // Skip to: 13015
+/* 3334 */    MCD_OPC_CheckField, 18, 3, 4, 202, 37, 0, // Skip to: 13015
+/* 3341 */    MCD_OPC_Decode, 148, 2, 14, // Opcode: ADDS_BU_rr_v110
+/* 3345 */    MCD_OPC_FilterValue, 1, 193, 37, 0, // Skip to: 13015
+/* 3350 */    MCD_OPC_Decode, 188, 2, 20, // Opcode: AND_NE_rc
+/* 3354 */    MCD_OPC_FilterValue, 34, 11, 0, 0, // Skip to: 3370
+/* 3359 */    MCD_OPC_CheckField, 7, 1, 1, 177, 37, 0, // Skip to: 13015
+/* 3366 */    MCD_OPC_Decode, 186, 2, 20, // Opcode: AND_LT_rc
+/* 3370 */    MCD_OPC_FilterValue, 35, 11, 0, 0, // Skip to: 3386
+/* 3375 */    MCD_OPC_CheckField, 7, 1, 1, 161, 37, 0, // Skip to: 13015
+/* 3382 */    MCD_OPC_Decode, 184, 2, 20, // Opcode: AND_LT_U_rc
+/* 3386 */    MCD_OPC_FilterValue, 36, 28, 0, 0, // Skip to: 3419
+/* 3391 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3394 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3410
+/* 3399 */    MCD_OPC_CheckField, 18, 3, 0, 137, 37, 0, // Skip to: 13015
+/* 3406 */    MCD_OPC_Decode, 191, 9, 14, // Opcode: SUB_B_rr
+/* 3410 */    MCD_OPC_FilterValue, 1, 128, 37, 0, // Skip to: 13015
+/* 3415 */    MCD_OPC_Decode, 182, 2, 20, // Opcode: AND_GE_rc
+/* 3419 */    MCD_OPC_FilterValue, 37, 11, 0, 0, // Skip to: 3435
+/* 3424 */    MCD_OPC_CheckField, 7, 1, 1, 112, 37, 0, // Skip to: 13015
+/* 3431 */    MCD_OPC_Decode, 180, 2, 20, // Opcode: AND_GE_U_rc
+/* 3435 */    MCD_OPC_FilterValue, 39, 28, 0, 0, // Skip to: 3468
+/* 3440 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3443 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3459
+/* 3448 */    MCD_OPC_CheckField, 18, 3, 0, 88, 37, 0, // Skip to: 13015
+/* 3455 */    MCD_OPC_Decode, 255, 1, 14, // Opcode: ABSDIF_B_rr
+/* 3459 */    MCD_OPC_FilterValue, 1, 79, 37, 0, // Skip to: 13015
+/* 3464 */    MCD_OPC_Decode, 248, 7, 20, // Opcode: OR_EQ_rc
+/* 3468 */    MCD_OPC_FilterValue, 40, 28, 0, 0, // Skip to: 3501
+/* 3473 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3476 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3492
+/* 3481 */    MCD_OPC_CheckField, 18, 3, 0, 55, 37, 0, // Skip to: 13015
+/* 3488 */    MCD_OPC_Decode, 186, 3, 14, // Opcode: EQ_B_rr
+/* 3492 */    MCD_OPC_FilterValue, 1, 46, 37, 0, // Skip to: 13015
+/* 3497 */    MCD_OPC_Decode, 130, 8, 20, // Opcode: OR_NE_rc
+/* 3501 */    MCD_OPC_FilterValue, 41, 38, 0, 0, // Skip to: 3544
+/* 3506 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3509 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 3535
+/* 3514 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3517 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3526
+/* 3522 */    MCD_OPC_Decode, 163, 5, 14, // Opcode: LT_B
+/* 3526 */    MCD_OPC_FilterValue, 4, 12, 37, 0, // Skip to: 13015
+/* 3531 */    MCD_OPC_Decode, 164, 5, 14, // Opcode: LT_BU
+/* 3535 */    MCD_OPC_FilterValue, 1, 3, 37, 0, // Skip to: 13015
+/* 3540 */    MCD_OPC_Decode, 128, 8, 20, // Opcode: OR_LT_rc
+/* 3544 */    MCD_OPC_FilterValue, 42, 11, 0, 0, // Skip to: 3560
+/* 3549 */    MCD_OPC_CheckField, 7, 1, 1, 243, 36, 0, // Skip to: 13015
+/* 3556 */    MCD_OPC_Decode, 254, 7, 20, // Opcode: OR_LT_U_rc
+/* 3560 */    MCD_OPC_FilterValue, 43, 28, 0, 0, // Skip to: 3593
+/* 3565 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3568 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3584
+/* 3573 */    MCD_OPC_CheckField, 18, 3, 0, 219, 36, 0, // Skip to: 13015
+/* 3580 */    MCD_OPC_Decode, 181, 3, 14, // Opcode: EQANY_B_rr
+/* 3584 */    MCD_OPC_FilterValue, 1, 210, 36, 0, // Skip to: 13015
+/* 3589 */    MCD_OPC_Decode, 252, 7, 20, // Opcode: OR_GE_rc
+/* 3593 */    MCD_OPC_FilterValue, 44, 38, 0, 0, // Skip to: 3636
+/* 3598 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3601 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 3627
+/* 3606 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3609 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3618
+/* 3614 */    MCD_OPC_Decode, 165, 6, 14, // Opcode: MIN_B
+/* 3618 */    MCD_OPC_FilterValue, 4, 176, 36, 0, // Skip to: 13015
+/* 3623 */    MCD_OPC_Decode, 166, 6, 14, // Opcode: MIN_BU
+/* 3627 */    MCD_OPC_FilterValue, 1, 167, 36, 0, // Skip to: 13015
+/* 3632 */    MCD_OPC_Decode, 250, 7, 20, // Opcode: OR_GE_U_rc
+/* 3636 */    MCD_OPC_FilterValue, 45, 35, 0, 0, // Skip to: 3676
+/* 3641 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3644 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3660
+/* 3649 */    MCD_OPC_CheckField, 7, 1, 0, 143, 36, 0, // Skip to: 13015
+/* 3656 */    MCD_OPC_Decode, 156, 6, 14, // Opcode: MAX_B
+/* 3660 */    MCD_OPC_FilterValue, 4, 134, 36, 0, // Skip to: 13015
+/* 3665 */    MCD_OPC_CheckField, 7, 1, 0, 127, 36, 0, // Skip to: 13015
+/* 3672 */    MCD_OPC_Decode, 157, 6, 14, // Opcode: MAX_BU
+/* 3676 */    MCD_OPC_FilterValue, 46, 18, 0, 0, // Skip to: 3699
+/* 3681 */    MCD_OPC_CheckField, 18, 3, 0, 111, 36, 0, // Skip to: 13015
+/* 3688 */    MCD_OPC_CheckField, 7, 1, 0, 104, 36, 0, // Skip to: 13015
+/* 3695 */    MCD_OPC_Decode, 134, 2, 14, // Opcode: ABS_B_rr
+/* 3699 */    MCD_OPC_FilterValue, 47, 38, 0, 0, // Skip to: 3742
+/* 3704 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3707 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 3733
+/* 3712 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3715 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3724
+/* 3720 */    MCD_OPC_Decode, 165, 8, 14, // Opcode: SAT_B_rr
+/* 3724 */    MCD_OPC_FilterValue, 4, 70, 36, 0, // Skip to: 13015
+/* 3729 */    MCD_OPC_Decode, 162, 8, 14, // Opcode: SAT_BU_rr
+/* 3733 */    MCD_OPC_FilterValue, 1, 61, 36, 0, // Skip to: 13015
+/* 3738 */    MCD_OPC_Decode, 235, 9, 20, // Opcode: XOR_EQ_rc
+/* 3742 */    MCD_OPC_FilterValue, 48, 28, 0, 0, // Skip to: 3775
+/* 3747 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3750 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3766
+/* 3755 */    MCD_OPC_CheckField, 18, 3, 0, 37, 36, 0, // Skip to: 13015
+/* 3762 */    MCD_OPC_Decode, 164, 2, 14, // Opcode: ADD_H_rr
+/* 3766 */    MCD_OPC_FilterValue, 1, 28, 36, 0, // Skip to: 13015
+/* 3771 */    MCD_OPC_Decode, 245, 9, 20, // Opcode: XOR_NE_rc
+/* 3775 */    MCD_OPC_FilterValue, 49, 38, 0, 0, // Skip to: 3818
+/* 3780 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3783 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 3809
+/* 3788 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3791 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3800
+/* 3796 */    MCD_OPC_Decode, 150, 2, 14, // Opcode: ADDS_H
+/* 3800 */    MCD_OPC_FilterValue, 4, 250, 35, 0, // Skip to: 13015
+/* 3805 */    MCD_OPC_Decode, 151, 2, 14, // Opcode: ADDS_HU
+/* 3809 */    MCD_OPC_FilterValue, 1, 241, 35, 0, // Skip to: 13015
+/* 3814 */    MCD_OPC_Decode, 243, 9, 20, // Opcode: XOR_LT_rc
+/* 3818 */    MCD_OPC_FilterValue, 50, 11, 0, 0, // Skip to: 3834
+/* 3823 */    MCD_OPC_CheckField, 7, 1, 1, 225, 35, 0, // Skip to: 13015
+/* 3830 */    MCD_OPC_Decode, 241, 9, 20, // Opcode: XOR_LT_U_rc
+/* 3834 */    MCD_OPC_FilterValue, 51, 11, 0, 0, // Skip to: 3850
+/* 3839 */    MCD_OPC_CheckField, 7, 1, 1, 209, 35, 0, // Skip to: 13015
+/* 3846 */    MCD_OPC_Decode, 239, 9, 20, // Opcode: XOR_GE_rc
+/* 3850 */    MCD_OPC_FilterValue, 52, 28, 0, 0, // Skip to: 3883
+/* 3855 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3858 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3874
+/* 3863 */    MCD_OPC_CheckField, 18, 3, 0, 185, 35, 0, // Skip to: 13015
+/* 3870 */    MCD_OPC_Decode, 193, 9, 14, // Opcode: SUB_H_rr
+/* 3874 */    MCD_OPC_FilterValue, 1, 176, 35, 0, // Skip to: 13015
+/* 3879 */    MCD_OPC_Decode, 237, 9, 20, // Opcode: XOR_GE_U_rc
+/* 3883 */    MCD_OPC_FilterValue, 53, 35, 0, 0, // Skip to: 3923
+/* 3888 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3891 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3907
+/* 3896 */    MCD_OPC_CheckField, 7, 1, 0, 152, 35, 0, // Skip to: 13015
+/* 3903 */    MCD_OPC_Decode, 183, 9, 14, // Opcode: SUBS_H_rr
+/* 3907 */    MCD_OPC_FilterValue, 4, 143, 35, 0, // Skip to: 13015
+/* 3912 */    MCD_OPC_CheckField, 7, 1, 0, 136, 35, 0, // Skip to: 13015
+/* 3919 */    MCD_OPC_Decode, 182, 9, 14, // Opcode: SUBS_HU_rr
+/* 3923 */    MCD_OPC_FilterValue, 55, 38, 0, 0, // Skip to: 3966
+/* 3928 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3931 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 3957
+/* 3936 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 3939 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3948
+/* 3944 */    MCD_OPC_Decode, 128, 2, 14, // Opcode: ABSDIF_H_rr
+/* 3948 */    MCD_OPC_FilterValue, 4, 102, 35, 0, // Skip to: 13015
+/* 3953 */    MCD_OPC_Decode, 252, 1, 14, // Opcode: ABSDIFS_H_rr
+/* 3957 */    MCD_OPC_FilterValue, 1, 93, 35, 0, // Skip to: 13015
+/* 3962 */    MCD_OPC_Decode, 197, 8, 20, // Opcode: SH_EQ_rc
+/* 3966 */    MCD_OPC_FilterValue, 56, 28, 0, 0, // Skip to: 3999
+/* 3971 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3974 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3990
+/* 3979 */    MCD_OPC_CheckField, 18, 3, 0, 69, 35, 0, // Skip to: 13015
+/* 3986 */    MCD_OPC_Decode, 187, 3, 14, // Opcode: EQ_H_rr
+/* 3990 */    MCD_OPC_FilterValue, 1, 60, 35, 0, // Skip to: 13015
+/* 3995 */    MCD_OPC_Decode, 210, 8, 20, // Opcode: SH_NE_rc
+/* 3999 */    MCD_OPC_FilterValue, 57, 38, 0, 0, // Skip to: 4042
+/* 4004 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 4007 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 4033
+/* 4012 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4015 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4024
+/* 4020 */    MCD_OPC_Decode, 165, 5, 14, // Opcode: LT_H
+/* 4024 */    MCD_OPC_FilterValue, 4, 26, 35, 0, // Skip to: 13015
+/* 4029 */    MCD_OPC_Decode, 166, 5, 14, // Opcode: LT_HU
+/* 4033 */    MCD_OPC_FilterValue, 1, 17, 35, 0, // Skip to: 13015
+/* 4038 */    MCD_OPC_Decode, 207, 8, 20, // Opcode: SH_LT_rc
+/* 4042 */    MCD_OPC_FilterValue, 58, 11, 0, 0, // Skip to: 4058
+/* 4047 */    MCD_OPC_CheckField, 7, 1, 1, 1, 35, 0, // Skip to: 13015
+/* 4054 */    MCD_OPC_Decode, 205, 8, 20, // Opcode: SH_LT_U_rc
+/* 4058 */    MCD_OPC_FilterValue, 59, 28, 0, 0, // Skip to: 4091
+/* 4063 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 4066 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4082
+/* 4071 */    MCD_OPC_CheckField, 18, 3, 0, 233, 34, 0, // Skip to: 13015
+/* 4078 */    MCD_OPC_Decode, 183, 3, 14, // Opcode: EQANY_H_rr
+/* 4082 */    MCD_OPC_FilterValue, 1, 224, 34, 0, // Skip to: 13015
+/* 4087 */    MCD_OPC_Decode, 201, 8, 20, // Opcode: SH_GE_rc
+/* 4091 */    MCD_OPC_FilterValue, 60, 38, 0, 0, // Skip to: 4134
+/* 4096 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 4099 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 4125
+/* 4104 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4107 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4116
+/* 4112 */    MCD_OPC_Decode, 167, 6, 14, // Opcode: MIN_H
+/* 4116 */    MCD_OPC_FilterValue, 4, 190, 34, 0, // Skip to: 13015
+/* 4121 */    MCD_OPC_Decode, 168, 6, 14, // Opcode: MIN_HU
+/* 4125 */    MCD_OPC_FilterValue, 1, 181, 34, 0, // Skip to: 13015
+/* 4130 */    MCD_OPC_Decode, 199, 8, 20, // Opcode: SH_GE_U_rc
+/* 4134 */    MCD_OPC_FilterValue, 61, 35, 0, 0, // Skip to: 4174
+/* 4139 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4142 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4158
+/* 4147 */    MCD_OPC_CheckField, 7, 1, 0, 157, 34, 0, // Skip to: 13015
+/* 4154 */    MCD_OPC_Decode, 158, 6, 14, // Opcode: MAX_H
+/* 4158 */    MCD_OPC_FilterValue, 4, 148, 34, 0, // Skip to: 13015
+/* 4163 */    MCD_OPC_CheckField, 7, 1, 0, 141, 34, 0, // Skip to: 13015
+/* 4170 */    MCD_OPC_Decode, 159, 6, 14, // Opcode: MAX_HU
+/* 4174 */    MCD_OPC_FilterValue, 62, 35, 0, 0, // Skip to: 4214
+/* 4179 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4182 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4198
+/* 4187 */    MCD_OPC_CheckField, 7, 1, 0, 117, 34, 0, // Skip to: 13015
+/* 4194 */    MCD_OPC_Decode, 135, 2, 14, // Opcode: ABS_H_rr
+/* 4198 */    MCD_OPC_FilterValue, 4, 108, 34, 0, // Skip to: 13015
+/* 4203 */    MCD_OPC_CheckField, 7, 1, 0, 101, 34, 0, // Skip to: 13015
+/* 4210 */    MCD_OPC_Decode, 132, 2, 14, // Opcode: ABSS_H_rr
+/* 4214 */    MCD_OPC_FilterValue, 63, 35, 0, 0, // Skip to: 4254
+/* 4219 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4222 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4238
+/* 4227 */    MCD_OPC_CheckField, 7, 1, 0, 77, 34, 0, // Skip to: 13015
+/* 4234 */    MCD_OPC_Decode, 171, 8, 14, // Opcode: SAT_H_rr
+/* 4238 */    MCD_OPC_FilterValue, 4, 68, 34, 0, // Skip to: 13015
+/* 4243 */    MCD_OPC_CheckField, 7, 1, 0, 61, 34, 0, // Skip to: 13015
+/* 4250 */    MCD_OPC_Decode, 168, 8, 14, // Opcode: SAT_HU_rr
+/* 4254 */    MCD_OPC_FilterValue, 64, 45, 0, 0, // Skip to: 4304
+/* 4259 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4262 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4283
+/* 4267 */    MCD_OPC_CheckPredicate, 0, 39, 34, 0, // Skip to: 13015
+/* 4272 */    MCD_OPC_CheckField, 7, 1, 0, 32, 34, 0, // Skip to: 13015
+/* 4279 */    MCD_OPC_Decode, 190, 6, 14, // Opcode: MOV_rr_e
+/* 4283 */    MCD_OPC_FilterValue, 4, 23, 34, 0, // Skip to: 13015
+/* 4288 */    MCD_OPC_CheckPredicate, 0, 18, 34, 0, // Skip to: 13015
+/* 4293 */    MCD_OPC_CheckField, 7, 1, 0, 11, 34, 0, // Skip to: 13015
+/* 4300 */    MCD_OPC_Decode, 191, 6, 14, // Opcode: MOV_rr_eab
+/* 4304 */    MCD_OPC_FilterValue, 72, 18, 0, 0, // Skip to: 4327
+/* 4309 */    MCD_OPC_CheckField, 18, 3, 0, 251, 33, 0, // Skip to: 13015
+/* 4316 */    MCD_OPC_CheckField, 7, 1, 0, 244, 33, 0, // Skip to: 13015
+/* 4323 */    MCD_OPC_Decode, 188, 3, 14, // Opcode: EQ_W_rr
+/* 4327 */    MCD_OPC_FilterValue, 73, 35, 0, 0, // Skip to: 4367
+/* 4332 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4335 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4351
+/* 4340 */    MCD_OPC_CheckField, 7, 1, 0, 220, 33, 0, // Skip to: 13015
+/* 4347 */    MCD_OPC_Decode, 171, 5, 14, // Opcode: LT_W
+/* 4351 */    MCD_OPC_FilterValue, 4, 211, 33, 0, // Skip to: 13015
+/* 4356 */    MCD_OPC_CheckField, 7, 1, 0, 204, 33, 0, // Skip to: 13015
+/* 4363 */    MCD_OPC_Decode, 172, 5, 14, // Opcode: LT_WU
+/* 4367 */    MCD_OPC_FilterValue, 86, 11, 0, 0, // Skip to: 4383
+/* 4372 */    MCD_OPC_CheckField, 7, 1, 1, 188, 33, 0, // Skip to: 13015
+/* 4379 */    MCD_OPC_Decode, 180, 3, 20, // Opcode: EQANY_B_rc
+/* 4383 */    MCD_OPC_FilterValue, 118, 179, 33, 0, // Skip to: 13015
+/* 4388 */    MCD_OPC_CheckField, 7, 1, 1, 172, 33, 0, // Skip to: 13015
+/* 4395 */    MCD_OPC_Decode, 182, 3, 20, // Opcode: EQANY_H_rc
+/* 4399 */    MCD_OPC_FilterValue, 13, 70, 1, 0, // Skip to: 4730
+/* 4404 */    MCD_OPC_ExtractField, 12, 20,  // Inst{31-12} ...
+/* 4407 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4423
+/* 4412 */    MCD_OPC_CheckField, 7, 1, 0, 148, 33, 0, // Skip to: 13015
+/* 4419 */    MCD_OPC_Decode, 236, 7, 21, // Opcode: NOP_sys
+/* 4423 */    MCD_OPC_FilterValue, 128, 24, 16, 0, 0, // Skip to: 4445
+/* 4429 */    MCD_OPC_CheckPredicate, 0, 133, 33, 0, // Skip to: 13015
+/* 4434 */    MCD_OPC_CheckField, 7, 1, 0, 126, 33, 0, // Skip to: 13015
+/* 4441 */    MCD_OPC_Decode, 203, 3, 21, // Opcode: FRET_sys
+/* 4445 */    MCD_OPC_FilterValue, 128, 32, 11, 0, 0, // Skip to: 4462
+/* 4451 */    MCD_OPC_CheckField, 7, 1, 0, 109, 33, 0, // Skip to: 13015
+/* 4458 */    MCD_OPC_Decode, 148, 3, 21, // Opcode: DEBUG_sys
+/* 4462 */    MCD_OPC_FilterValue, 128, 40, 11, 0, 0, // Skip to: 4479
+/* 4468 */    MCD_OPC_CheckField, 7, 1, 0, 92, 33, 0, // Skip to: 13015
+/* 4475 */    MCD_OPC_Decode, 154, 8, 21, // Opcode: RFM_sys
+/* 4479 */    MCD_OPC_FilterValue, 128, 48, 16, 0, 0, // Skip to: 4501
+/* 4485 */    MCD_OPC_CheckPredicate, 1, 77, 33, 0, // Skip to: 13015
+/* 4490 */    MCD_OPC_CheckField, 7, 1, 0, 70, 33, 0, // Skip to: 13015
+/* 4497 */    MCD_OPC_Decode, 149, 8, 21, // Opcode: RET_sys
+/* 4501 */    MCD_OPC_FilterValue, 128, 56, 16, 0, 0, // Skip to: 4523
+/* 4507 */    MCD_OPC_CheckPredicate, 1, 55, 33, 0, // Skip to: 13015
+/* 4512 */    MCD_OPC_CheckField, 7, 1, 0, 48, 33, 0, // Skip to: 13015
+/* 4519 */    MCD_OPC_Decode, 152, 8, 21, // Opcode: RFE_sys_sys
+/* 4523 */    MCD_OPC_FilterValue, 128, 64, 11, 0, 0, // Skip to: 4540
+/* 4529 */    MCD_OPC_CheckField, 7, 1, 0, 31, 33, 0, // Skip to: 13015
+/* 4536 */    MCD_OPC_Decode, 198, 9, 21, // Opcode: SVLCX_sys
+/* 4540 */    MCD_OPC_FilterValue, 128, 72, 11, 0, 0, // Skip to: 4557
+/* 4546 */    MCD_OPC_CheckField, 7, 1, 0, 14, 33, 0, // Skip to: 13015
+/* 4553 */    MCD_OPC_Decode, 155, 8, 21, // Opcode: RSLCX_sys
+/* 4557 */    MCD_OPC_FilterValue, 128, 96, 11, 0, 0, // Skip to: 4574
+/* 4563 */    MCD_OPC_CheckField, 7, 1, 0, 253, 32, 0, // Skip to: 13015
+/* 4570 */    MCD_OPC_Decode, 179, 3, 21, // Opcode: ENABLE_sys
+/* 4574 */    MCD_OPC_FilterValue, 128, 104, 11, 0, 0, // Skip to: 4591
+/* 4580 */    MCD_OPC_CheckField, 7, 1, 0, 236, 32, 0, // Skip to: 13015
+/* 4587 */    MCD_OPC_Decode, 152, 3, 21, // Opcode: DISABLE_sys
+/* 4591 */    MCD_OPC_FilterValue, 128, 112, 16, 0, 0, // Skip to: 4613
+/* 4597 */    MCD_OPC_CheckPredicate, 0, 221, 32, 0, // Skip to: 13015
+/* 4602 */    MCD_OPC_CheckField, 7, 1, 0, 214, 32, 0, // Skip to: 13015
+/* 4609 */    MCD_OPC_Decode, 147, 8, 21, // Opcode: RESTORE_sys
+/* 4613 */    MCD_OPC_FilterValue, 128, 120, 16, 0, 0, // Skip to: 4635
+/* 4619 */    MCD_OPC_CheckPredicate, 0, 199, 32, 0, // Skip to: 13015
+/* 4624 */    MCD_OPC_CheckField, 7, 1, 0, 192, 32, 0, // Skip to: 13015
+/* 4631 */    MCD_OPC_Decode, 153, 3, 21, // Opcode: DISABLE_sys_1
+/* 4635 */    MCD_OPC_FilterValue, 128, 144, 1, 11, 0, 0, // Skip to: 4653
+/* 4642 */    MCD_OPC_CheckField, 7, 1, 0, 174, 32, 0, // Skip to: 13015
+/* 4649 */    MCD_OPC_Decode, 157, 3, 21, // Opcode: DSYNC_sys
+/* 4653 */    MCD_OPC_FilterValue, 128, 152, 1, 11, 0, 0, // Skip to: 4671
+/* 4660 */    MCD_OPC_CheckField, 7, 1, 0, 156, 32, 0, // Skip to: 13015
+/* 4667 */    MCD_OPC_Decode, 229, 3, 21, // Opcode: ISYNC_sys
+/* 4671 */    MCD_OPC_FilterValue, 128, 160, 1, 11, 0, 0, // Skip to: 4689
+/* 4678 */    MCD_OPC_CheckField, 7, 1, 0, 138, 32, 0, // Skip to: 13015
+/* 4685 */    MCD_OPC_Decode, 226, 9, 21, // Opcode: TRAPV_sys
+/* 4689 */    MCD_OPC_FilterValue, 128, 168, 1, 11, 0, 0, // Skip to: 4707
+/* 4696 */    MCD_OPC_CheckField, 7, 1, 0, 120, 32, 0, // Skip to: 13015
+/* 4703 */    MCD_OPC_Decode, 225, 9, 21, // Opcode: TRAPSV_sys
+/* 4707 */    MCD_OPC_FilterValue, 128, 176, 1, 109, 32, 0, // Skip to: 13015
+/* 4714 */    MCD_OPC_CheckPredicate, 5, 104, 32, 0, // Skip to: 13015
+/* 4719 */    MCD_OPC_CheckField, 7, 1, 0, 97, 32, 0, // Skip to: 13015
+/* 4726 */    MCD_OPC_Decode, 231, 9, 21, // Opcode: WAIT_sys
+/* 4730 */    MCD_OPC_FilterValue, 15, 58, 2, 0, // Skip to: 5305
+/* 4735 */    MCD_OPC_ExtractField, 21, 7,  // Inst{27-21} ...
+/* 4738 */    MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 4781
+/* 4743 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 4746 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 4772
+/* 4751 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4754 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4763
+/* 4759 */    MCD_OPC_Decode, 218, 8, 14, // Opcode: SH_rr
+/* 4763 */    MCD_OPC_FilterValue, 4, 55, 32, 0, // Skip to: 13015
+/* 4768 */    MCD_OPC_Decode, 189, 8, 14, // Opcode: SHA_rr
+/* 4772 */    MCD_OPC_FilterValue, 1, 46, 32, 0, // Skip to: 13015
+/* 4777 */    MCD_OPC_Decode, 217, 8, 20, // Opcode: SH_rc
+/* 4781 */    MCD_OPC_FilterValue, 1, 28, 0, 0, // Skip to: 4814
+/* 4786 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 4789 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4805
+/* 4794 */    MCD_OPC_CheckField, 18, 3, 0, 22, 32, 0, // Skip to: 13015
+/* 4801 */    MCD_OPC_Decode, 183, 8, 14, // Opcode: SHAS_rr
+/* 4805 */    MCD_OPC_FilterValue, 1, 13, 32, 0, // Skip to: 13015
+/* 4810 */    MCD_OPC_Decode, 188, 8, 20, // Opcode: SHA_rc
+/* 4814 */    MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 4830
+/* 4819 */    MCD_OPC_CheckField, 7, 1, 1, 253, 31, 0, // Skip to: 13015
+/* 4826 */    MCD_OPC_Decode, 182, 8, 20, // Opcode: SHAS_rc
+/* 4830 */    MCD_OPC_FilterValue, 4, 35, 0, 0, // Skip to: 4870
+/* 4835 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4838 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4854
+/* 4843 */    MCD_OPC_CheckField, 7, 1, 0, 229, 31, 0, // Skip to: 13015
+/* 4850 */    MCD_OPC_Decode, 194, 2, 14, // Opcode: AND_rr
+/* 4854 */    MCD_OPC_FilterValue, 4, 220, 31, 0, // Skip to: 13015
+/* 4859 */    MCD_OPC_CheckField, 7, 1, 0, 213, 31, 0, // Skip to: 13015
+/* 4866 */    MCD_OPC_Decode, 230, 7, 14, // Opcode: NAND_rr
+/* 4870 */    MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 4910
+/* 4875 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4878 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4894
+/* 4883 */    MCD_OPC_CheckField, 7, 1, 0, 189, 31, 0, // Skip to: 13015
+/* 4890 */    MCD_OPC_Decode, 136, 8, 14, // Opcode: OR_rr
+/* 4894 */    MCD_OPC_FilterValue, 4, 180, 31, 0, // Skip to: 13015
+/* 4899 */    MCD_OPC_CheckField, 7, 1, 0, 173, 31, 0, // Skip to: 13015
+/* 4906 */    MCD_OPC_Decode, 239, 7, 14, // Opcode: NOR_rr
+/* 4910 */    MCD_OPC_FilterValue, 6, 35, 0, 0, // Skip to: 4950
+/* 4915 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4918 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4934
+/* 4923 */    MCD_OPC_CheckField, 7, 1, 0, 149, 31, 0, // Skip to: 13015
+/* 4930 */    MCD_OPC_Decode, 249, 9, 14, // Opcode: XOR_rr
+/* 4934 */    MCD_OPC_FilterValue, 4, 140, 31, 0, // Skip to: 13015
+/* 4939 */    MCD_OPC_CheckField, 7, 1, 0, 133, 31, 0, // Skip to: 13015
+/* 4946 */    MCD_OPC_Decode, 234, 9, 14, // Opcode: XNOR_rr
+/* 4950 */    MCD_OPC_FilterValue, 7, 43, 0, 0, // Skip to: 4998
+/* 4955 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 4958 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 4984
+/* 4963 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 4966 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4975
+/* 4971 */    MCD_OPC_Decode, 175, 2, 14, // Opcode: ANDN_rr
+/* 4975 */    MCD_OPC_FilterValue, 4, 99, 31, 0, // Skip to: 13015
+/* 4980 */    MCD_OPC_Decode, 245, 7, 14, // Opcode: ORN_rr
+/* 4984 */    MCD_OPC_FilterValue, 1, 90, 31, 0, // Skip to: 13015
+/* 4989 */    MCD_OPC_CheckPredicate, 6, 85, 31, 0, // Skip to: 13015
+/* 4994 */    MCD_OPC_Decode, 192, 8, 20, // Opcode: SHUFFLE_rc
+/* 4998 */    MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 5014
+/* 5003 */    MCD_OPC_CheckField, 7, 1, 1, 69, 31, 0, // Skip to: 13015
+/* 5010 */    MCD_OPC_Decode, 193, 2, 20, // Opcode: AND_rc
+/* 5014 */    MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 5030
+/* 5019 */    MCD_OPC_CheckField, 7, 1, 1, 53, 31, 0, // Skip to: 13015
+/* 5026 */    MCD_OPC_Decode, 229, 7, 20, // Opcode: NAND_rc
+/* 5030 */    MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 5046
+/* 5035 */    MCD_OPC_CheckField, 7, 1, 1, 37, 31, 0, // Skip to: 13015
+/* 5042 */    MCD_OPC_Decode, 135, 8, 20, // Opcode: OR_rc
+/* 5046 */    MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 5062
+/* 5051 */    MCD_OPC_CheckField, 7, 1, 1, 21, 31, 0, // Skip to: 13015
+/* 5058 */    MCD_OPC_Decode, 238, 7, 20, // Opcode: NOR_rc
+/* 5062 */    MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 5078
+/* 5067 */    MCD_OPC_CheckField, 7, 1, 1, 5, 31, 0, // Skip to: 13015
+/* 5074 */    MCD_OPC_Decode, 248, 9, 20, // Opcode: XOR_rc
+/* 5078 */    MCD_OPC_FilterValue, 13, 28, 0, 0, // Skip to: 5111
+/* 5083 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5086 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5102
+/* 5091 */    MCD_OPC_CheckField, 18, 3, 4, 237, 30, 0, // Skip to: 13015
+/* 5098 */    MCD_OPC_Decode, 128, 3, 14, // Opcode: CLZ_rr
+/* 5102 */    MCD_OPC_FilterValue, 1, 228, 30, 0, // Skip to: 13015
+/* 5107 */    MCD_OPC_Decode, 233, 9, 20, // Opcode: XNOR_rc
+/* 5111 */    MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 5154
+/* 5116 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5119 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 5145
+/* 5124 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 5127 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5136
+/* 5132 */    MCD_OPC_Decode, 250, 2, 14, // Opcode: CLO_rr
+/* 5136 */    MCD_OPC_FilterValue, 4, 194, 30, 0, // Skip to: 13015
+/* 5141 */    MCD_OPC_Decode, 253, 2, 14, // Opcode: CLS_rr
+/* 5145 */    MCD_OPC_FilterValue, 1, 185, 30, 0, // Skip to: 13015
+/* 5150 */    MCD_OPC_Decode, 174, 2, 20, // Opcode: ANDN_rc
+/* 5154 */    MCD_OPC_FilterValue, 15, 11, 0, 0, // Skip to: 5170
+/* 5159 */    MCD_OPC_CheckField, 7, 1, 1, 169, 30, 0, // Skip to: 13015
+/* 5166 */    MCD_OPC_Decode, 244, 7, 20, // Opcode: ORN_rc
+/* 5170 */    MCD_OPC_FilterValue, 32, 35, 0, 0, // Skip to: 5210
+/* 5175 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 5178 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5194
+/* 5183 */    MCD_OPC_CheckField, 7, 1, 0, 145, 30, 0, // Skip to: 13015
+/* 5190 */    MCD_OPC_Decode, 204, 8, 14, // Opcode: SH_H_rr
+/* 5194 */    MCD_OPC_FilterValue, 4, 136, 30, 0, // Skip to: 13015
+/* 5199 */    MCD_OPC_CheckField, 7, 1, 0, 129, 30, 0, // Skip to: 13015
+/* 5206 */    MCD_OPC_Decode, 187, 8, 14, // Opcode: SHA_H_rr
+/* 5210 */    MCD_OPC_FilterValue, 62, 35, 0, 0, // Skip to: 5250
+/* 5215 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 5218 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5234
+/* 5223 */    MCD_OPC_CheckField, 7, 1, 0, 105, 30, 0, // Skip to: 13015
+/* 5230 */    MCD_OPC_Decode, 255, 2, 14, // Opcode: CLZ_H_rr
+/* 5234 */    MCD_OPC_FilterValue, 4, 96, 30, 0, // Skip to: 13015
+/* 5239 */    MCD_OPC_CheckField, 7, 1, 0, 89, 30, 0, // Skip to: 13015
+/* 5246 */    MCD_OPC_Decode, 249, 2, 14, // Opcode: CLO_H_rr
+/* 5250 */    MCD_OPC_FilterValue, 63, 18, 0, 0, // Skip to: 5273
+/* 5255 */    MCD_OPC_CheckField, 18, 3, 0, 73, 30, 0, // Skip to: 13015
+/* 5262 */    MCD_OPC_CheckField, 7, 1, 0, 66, 30, 0, // Skip to: 13015
+/* 5269 */    MCD_OPC_Decode, 252, 2, 14, // Opcode: CLS_H_rr
+/* 5273 */    MCD_OPC_FilterValue, 64, 11, 0, 0, // Skip to: 5289
+/* 5278 */    MCD_OPC_CheckField, 7, 1, 1, 50, 30, 0, // Skip to: 13015
+/* 5285 */    MCD_OPC_Decode, 203, 8, 20, // Opcode: SH_H_rc
+/* 5289 */    MCD_OPC_FilterValue, 65, 41, 30, 0, // Skip to: 13015
+/* 5294 */    MCD_OPC_CheckField, 7, 1, 1, 34, 30, 0, // Skip to: 13015
+/* 5301 */    MCD_OPC_Decode, 186, 8, 20, // Opcode: SHA_H_rc
+/* 5305 */    MCD_OPC_FilterValue, 17, 21, 0, 0, // Skip to: 5331
+/* 5310 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5313 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5322
+/* 5318 */    MCD_OPC_Decode, 139, 2, 22, // Opcode: ADDIH_A_rlc
+/* 5322 */    MCD_OPC_FilterValue, 1, 8, 30, 0, // Skip to: 13015
+/* 5327 */    MCD_OPC_Decode, 173, 6, 22, // Opcode: MOVH_A_rlc
+/* 5331 */    MCD_OPC_FilterValue, 19, 155, 1, 0, // Skip to: 5747
+/* 5336 */    MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
+/* 5339 */    MCD_OPC_FilterValue, 0, 199, 0, 0, // Skip to: 5543
+/* 5344 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 5347 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 5375
+/* 5352 */    MCD_OPC_CheckPredicate, 1, 234, 29, 0, // Skip to: 13015
+/* 5357 */    MCD_OPC_CheckField, 24, 4, 0, 227, 29, 0, // Skip to: 13015
+/* 5364 */    MCD_OPC_CheckField, 7, 1, 1, 220, 29, 0, // Skip to: 13015
+/* 5371 */    MCD_OPC_Decode, 216, 7, 23, // Opcode: MUL_Q_rr1_2_U
+/* 5375 */    MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 5403
+/* 5380 */    MCD_OPC_CheckPredicate, 1, 206, 29, 0, // Skip to: 13015
+/* 5385 */    MCD_OPC_CheckField, 24, 4, 0, 199, 29, 0, // Skip to: 13015
+/* 5392 */    MCD_OPC_CheckField, 7, 1, 1, 192, 29, 0, // Skip to: 13015
+/* 5399 */    MCD_OPC_Decode, 214, 7, 23, // Opcode: MUL_Q_rr1_2_L
+/* 5403 */    MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 5431
+/* 5408 */    MCD_OPC_CheckPredicate, 1, 178, 29, 0, // Skip to: 13015
+/* 5413 */    MCD_OPC_CheckField, 24, 4, 0, 171, 29, 0, // Skip to: 13015
+/* 5420 */    MCD_OPC_CheckField, 7, 1, 1, 164, 29, 0, // Skip to: 13015
+/* 5427 */    MCD_OPC_Decode, 211, 7, 23, // Opcode: MUL_Q_rr1_2
+/* 5431 */    MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 5459
+/* 5436 */    MCD_OPC_CheckPredicate, 1, 150, 29, 0, // Skip to: 13015
+/* 5441 */    MCD_OPC_CheckField, 24, 4, 0, 143, 29, 0, // Skip to: 13015
+/* 5448 */    MCD_OPC_CheckField, 7, 1, 1, 136, 29, 0, // Skip to: 13015
+/* 5455 */    MCD_OPC_Decode, 213, 7, 23, // Opcode: MUL_Q_rr1_2UU
+/* 5459 */    MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 5487
+/* 5464 */    MCD_OPC_CheckPredicate, 1, 122, 29, 0, // Skip to: 13015
+/* 5469 */    MCD_OPC_CheckField, 24, 4, 0, 115, 29, 0, // Skip to: 13015
+/* 5476 */    MCD_OPC_CheckField, 7, 1, 1, 108, 29, 0, // Skip to: 13015
+/* 5483 */    MCD_OPC_Decode, 212, 7, 23, // Opcode: MUL_Q_rr1_2LL
+/* 5487 */    MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 5515
+/* 5492 */    MCD_OPC_CheckPredicate, 1, 94, 29, 0, // Skip to: 13015
+/* 5497 */    MCD_OPC_CheckField, 24, 4, 0, 87, 29, 0, // Skip to: 13015
+/* 5504 */    MCD_OPC_CheckField, 7, 1, 1, 80, 29, 0, // Skip to: 13015
+/* 5511 */    MCD_OPC_Decode, 197, 7, 23, // Opcode: MULR_Q_rr1_2UU
+/* 5515 */    MCD_OPC_FilterValue, 7, 71, 29, 0, // Skip to: 13015
+/* 5520 */    MCD_OPC_CheckPredicate, 1, 66, 29, 0, // Skip to: 13015
+/* 5525 */    MCD_OPC_CheckField, 24, 4, 0, 59, 29, 0, // Skip to: 13015
+/* 5532 */    MCD_OPC_CheckField, 7, 1, 1, 52, 29, 0, // Skip to: 13015
+/* 5539 */    MCD_OPC_Decode, 196, 7, 23, // Opcode: MULR_Q_rr1_2LL
+/* 5543 */    MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 5559
+/* 5548 */    MCD_OPC_CheckField, 7, 1, 0, 36, 29, 0, // Skip to: 13015
+/* 5555 */    MCD_OPC_Decode, 152, 6, 24, // Opcode: MADD_rcr
+/* 5559 */    MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 5580
+/* 5564 */    MCD_OPC_CheckPredicate, 1, 22, 29, 0, // Skip to: 13015
+/* 5569 */    MCD_OPC_CheckField, 7, 1, 0, 15, 29, 0, // Skip to: 13015
+/* 5576 */    MCD_OPC_Decode, 150, 6, 24, // Opcode: MADD_U_rcr
+/* 5580 */    MCD_OPC_FilterValue, 3, 88, 0, 0, // Skip to: 5673
+/* 5585 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5588 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5602
+/* 5593 */    MCD_OPC_CheckPredicate, 1, 249, 28, 0, // Skip to: 13015
+/* 5598 */    MCD_OPC_Decode, 153, 6, 24, // Opcode: MADD_rcr_e
+/* 5602 */    MCD_OPC_FilterValue, 1, 240, 28, 0, // Skip to: 13015
+/* 5607 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 5610 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 5631
+/* 5615 */    MCD_OPC_CheckPredicate, 1, 227, 28, 0, // Skip to: 13015
+/* 5620 */    MCD_OPC_CheckField, 24, 4, 0, 220, 28, 0, // Skip to: 13015
+/* 5627 */    MCD_OPC_Decode, 217, 7, 23, // Opcode: MUL_Q_rr1_2_Ue
+/* 5631 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 5652
+/* 5636 */    MCD_OPC_CheckPredicate, 1, 206, 28, 0, // Skip to: 13015
+/* 5641 */    MCD_OPC_CheckField, 24, 4, 0, 199, 28, 0, // Skip to: 13015
+/* 5648 */    MCD_OPC_Decode, 215, 7, 23, // Opcode: MUL_Q_rr1_2_Le
+/* 5652 */    MCD_OPC_FilterValue, 3, 190, 28, 0, // Skip to: 13015
+/* 5657 */    MCD_OPC_CheckPredicate, 1, 185, 28, 0, // Skip to: 13015
+/* 5662 */    MCD_OPC_CheckField, 24, 4, 0, 178, 28, 0, // Skip to: 13015
+/* 5669 */    MCD_OPC_Decode, 218, 7, 23, // Opcode: MUL_Q_rr1_2__e
+/* 5673 */    MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 5689
+/* 5678 */    MCD_OPC_CheckField, 7, 1, 0, 162, 28, 0, // Skip to: 13015
+/* 5685 */    MCD_OPC_Decode, 253, 5, 24, // Opcode: MADDS_U_rcr
+/* 5689 */    MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 5705
+/* 5694 */    MCD_OPC_CheckField, 7, 1, 0, 146, 28, 0, // Skip to: 13015
+/* 5701 */    MCD_OPC_Decode, 129, 6, 24, // Opcode: MADDS_rcr
+/* 5705 */    MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 5726
+/* 5710 */    MCD_OPC_CheckPredicate, 1, 132, 28, 0, // Skip to: 13015
+/* 5715 */    MCD_OPC_CheckField, 7, 1, 0, 125, 28, 0, // Skip to: 13015
+/* 5722 */    MCD_OPC_Decode, 254, 5, 24, // Opcode: MADDS_U_rcr_e
+/* 5726 */    MCD_OPC_FilterValue, 7, 116, 28, 0, // Skip to: 13015
+/* 5731 */    MCD_OPC_CheckPredicate, 1, 111, 28, 0, // Skip to: 13015
+/* 5736 */    MCD_OPC_CheckField, 7, 1, 0, 104, 28, 0, // Skip to: 13015
+/* 5743 */    MCD_OPC_Decode, 130, 6, 24, // Opcode: MADDS_rcr_e
+/* 5747 */    MCD_OPC_FilterValue, 21, 67, 0, 0, // Skip to: 5819
+/* 5752 */    MCD_OPC_ExtractField, 26, 2,  // Inst{27-26} ...
+/* 5755 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5771
+/* 5760 */    MCD_OPC_CheckField, 7, 1, 0, 80, 28, 0, // Skip to: 13015
+/* 5767 */    MCD_OPC_Decode, 221, 8, 17, // Opcode: STLCX_abs
+/* 5771 */    MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 5787
+/* 5776 */    MCD_OPC_CheckField, 7, 1, 0, 64, 28, 0, // Skip to: 13015
+/* 5783 */    MCD_OPC_Decode, 223, 8, 17, // Opcode: STUCX_abs
+/* 5787 */    MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 5803
+/* 5792 */    MCD_OPC_CheckField, 7, 1, 0, 48, 28, 0, // Skip to: 13015
+/* 5799 */    MCD_OPC_Decode, 175, 4, 17, // Opcode: LDLCX_abs
+/* 5803 */    MCD_OPC_FilterValue, 3, 39, 28, 0, // Skip to: 13015
+/* 5808 */    MCD_OPC_CheckField, 7, 1, 0, 32, 28, 0, // Skip to: 13015
+/* 5815 */    MCD_OPC_Decode, 183, 4, 17, // Opcode: LDUCX_abs
+/* 5819 */    MCD_OPC_FilterValue, 23, 105, 0, 0, // Skip to: 5929
+/* 5824 */    MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
+/* 5827 */    MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 5860
+/* 5832 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5835 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5844
+/* 5840 */    MCD_OPC_Decode, 225, 3, 25, // Opcode: INSERT_rrrr
+/* 5844 */    MCD_OPC_FilterValue, 1, 254, 27, 0, // Skip to: 13015
+/* 5849 */    MCD_OPC_CheckField, 16, 5, 0, 247, 27, 0, // Skip to: 13015
+/* 5856 */    MCD_OPC_Decode, 222, 3, 26, // Opcode: INSERT_rcrr
+/* 5860 */    MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 5883
+/* 5865 */    MCD_OPC_CheckField, 16, 5, 0, 231, 27, 0, // Skip to: 13015
+/* 5872 */    MCD_OPC_CheckField, 7, 1, 0, 224, 27, 0, // Skip to: 13015
+/* 5879 */    MCD_OPC_Decode, 197, 3, 27, // Opcode: EXTR_rrrr
+/* 5883 */    MCD_OPC_FilterValue, 3, 18, 0, 0, // Skip to: 5906
+/* 5888 */    MCD_OPC_CheckField, 16, 5, 0, 208, 27, 0, // Skip to: 13015
+/* 5895 */    MCD_OPC_CheckField, 7, 1, 0, 201, 27, 0, // Skip to: 13015
+/* 5902 */    MCD_OPC_Decode, 194, 3, 27, // Opcode: EXTR_U_rrrr
+/* 5906 */    MCD_OPC_FilterValue, 4, 192, 27, 0, // Skip to: 13015
+/* 5911 */    MCD_OPC_CheckField, 16, 5, 0, 185, 27, 0, // Skip to: 13015
+/* 5918 */    MCD_OPC_CheckField, 7, 1, 0, 178, 27, 0, // Skip to: 13015
+/* 5925 */    MCD_OPC_Decode, 150, 3, 27, // Opcode: DEXTR_rrrr
+/* 5929 */    MCD_OPC_FilterValue, 25, 21, 0, 0, // Skip to: 5955
+/* 5934 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5937 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5946
+/* 5942 */    MCD_OPC_Decode, 145, 5, 28, // Opcode: LD_W_bol
+/* 5946 */    MCD_OPC_FilterValue, 1, 152, 27, 0, // Skip to: 13015
+/* 5951 */    MCD_OPC_Decode, 191, 4, 28, // Opcode: LD_A_bol
+/* 5955 */    MCD_OPC_FilterValue, 27, 21, 0, 0, // Skip to: 5981
+/* 5960 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5963 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5972
+/* 5968 */    MCD_OPC_Decode, 141, 2, 22, // Opcode: ADDI_rlc
+/* 5972 */    MCD_OPC_FilterValue, 1, 126, 27, 0, // Skip to: 13015
+/* 5977 */    MCD_OPC_Decode, 140, 2, 22, // Opcode: ADDIH_rlc
+/* 5981 */    MCD_OPC_FilterValue, 29, 21, 0, 0, // Skip to: 6007
+/* 5986 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5989 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5998
+/* 5994 */    MCD_OPC_Decode, 172, 4, 29, // Opcode: J_b
+/* 5998 */    MCD_OPC_FilterValue, 1, 100, 27, 0, // Skip to: 13015
+/* 6003 */    MCD_OPC_Decode, 235, 3, 29, // Opcode: JA_b
+/* 6007 */    MCD_OPC_FilterValue, 31, 55, 0, 0, // Skip to: 6067
+/* 6012 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6015 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 6041
+/* 6020 */    MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 6023 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6032
+/* 6028 */    MCD_OPC_Decode, 144, 4, 30, // Opcode: JNEI_brr
+/* 6032 */    MCD_OPC_FilterValue, 1, 66, 27, 0, // Skip to: 13015
+/* 6037 */    MCD_OPC_Decode, 142, 4, 30, // Opcode: JNED_brr
+/* 6041 */    MCD_OPC_FilterValue, 1, 57, 27, 0, // Skip to: 13015
+/* 6046 */    MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 6049 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6058
+/* 6054 */    MCD_OPC_Decode, 143, 4, 31, // Opcode: JNEI_brc
+/* 6058 */    MCD_OPC_FilterValue, 1, 40, 27, 0, // Skip to: 13015
+/* 6063 */    MCD_OPC_Decode, 141, 4, 31, // Opcode: JNED_brc
+/* 6067 */    MCD_OPC_FilterValue, 35, 132, 2, 0, // Skip to: 6716
+/* 6072 */    MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 6075 */    MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 6098
+/* 6080 */    MCD_OPC_CheckField, 16, 2, 2, 16, 27, 0, // Skip to: 13015
+/* 6087 */    MCD_OPC_CheckField, 7, 1, 0, 9, 27, 0, // Skip to: 13015
+/* 6094 */    MCD_OPC_Decode, 176, 7, 15, // Opcode: MSUB_rrr2
+/* 6098 */    MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 6119
+/* 6103 */    MCD_OPC_CheckPredicate, 1, 251, 26, 0, // Skip to: 13015
+/* 6108 */    MCD_OPC_CheckField, 7, 1, 1, 244, 26, 0, // Skip to: 13015
+/* 6115 */    MCD_OPC_Decode, 252, 6, 16, // Opcode: MSUBR_H_rrr1_UL
+/* 6119 */    MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 6140
+/* 6124 */    MCD_OPC_CheckPredicate, 1, 230, 26, 0, // Skip to: 13015
+/* 6129 */    MCD_OPC_CheckField, 7, 1, 1, 223, 26, 0, // Skip to: 13015
+/* 6136 */    MCD_OPC_Decode, 251, 6, 16, // Opcode: MSUBR_H_rrr1_LU
+/* 6140 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 6161
+/* 6145 */    MCD_OPC_CheckPredicate, 1, 209, 26, 0, // Skip to: 13015
+/* 6150 */    MCD_OPC_CheckField, 7, 1, 1, 202, 26, 0, // Skip to: 13015
+/* 6157 */    MCD_OPC_Decode, 250, 6, 16, // Opcode: MSUBR_H_rrr1_LL
+/* 6161 */    MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 6182
+/* 6166 */    MCD_OPC_CheckPredicate, 1, 188, 26, 0, // Skip to: 13015
+/* 6171 */    MCD_OPC_CheckField, 7, 1, 1, 181, 26, 0, // Skip to: 13015
+/* 6178 */    MCD_OPC_Decode, 254, 6, 16, // Opcode: MSUBR_H_rrr1_UU
+/* 6182 */    MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 6203
+/* 6187 */    MCD_OPC_CheckPredicate, 1, 167, 26, 0, // Skip to: 13015
+/* 6192 */    MCD_OPC_CheckField, 7, 1, 1, 160, 26, 0, // Skip to: 13015
+/* 6199 */    MCD_OPC_Decode, 158, 7, 16, // Opcode: MSUB_H_rrr1_UL
+/* 6203 */    MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 6224
+/* 6208 */    MCD_OPC_CheckPredicate, 1, 146, 26, 0, // Skip to: 13015
+/* 6213 */    MCD_OPC_CheckField, 7, 1, 1, 139, 26, 0, // Skip to: 13015
+/* 6220 */    MCD_OPC_Decode, 157, 7, 16, // Opcode: MSUB_H_rrr1_LU
+/* 6224 */    MCD_OPC_FilterValue, 26, 53, 0, 0, // Skip to: 6282
+/* 6229 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6232 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6268
+/* 6237 */    MCD_OPC_ExtractField, 16, 2,  // Inst{17-16} ...
+/* 6240 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6254
+/* 6245 */    MCD_OPC_CheckPredicate, 1, 109, 26, 0, // Skip to: 13015
+/* 6250 */    MCD_OPC_Decode, 173, 7, 15, // Opcode: MSUB_U_rrr2
+/* 6254 */    MCD_OPC_FilterValue, 2, 100, 26, 0, // Skip to: 13015
+/* 6259 */    MCD_OPC_CheckPredicate, 1, 95, 26, 0, // Skip to: 13015
+/* 6264 */    MCD_OPC_Decode, 177, 7, 15, // Opcode: MSUB_rrr2_e
+/* 6268 */    MCD_OPC_FilterValue, 1, 86, 26, 0, // Skip to: 13015
+/* 6273 */    MCD_OPC_CheckPredicate, 1, 81, 26, 0, // Skip to: 13015
+/* 6278 */    MCD_OPC_Decode, 156, 7, 16, // Opcode: MSUB_H_rrr1_LL
+/* 6282 */    MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 6303
+/* 6287 */    MCD_OPC_CheckPredicate, 1, 67, 26, 0, // Skip to: 13015
+/* 6292 */    MCD_OPC_CheckField, 7, 1, 1, 60, 26, 0, // Skip to: 13015
+/* 6299 */    MCD_OPC_Decode, 159, 7, 16, // Opcode: MSUB_H_rrr1_UU
+/* 6303 */    MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 6324
+/* 6308 */    MCD_OPC_CheckPredicate, 1, 46, 26, 0, // Skip to: 13015
+/* 6313 */    MCD_OPC_CheckField, 7, 1, 1, 39, 26, 0, // Skip to: 13015
+/* 6320 */    MCD_OPC_Decode, 233, 6, 16, // Opcode: MSUBM_H_rrr1_UL
+/* 6324 */    MCD_OPC_FilterValue, 29, 16, 0, 0, // Skip to: 6345
+/* 6329 */    MCD_OPC_CheckPredicate, 1, 25, 26, 0, // Skip to: 13015
+/* 6334 */    MCD_OPC_CheckField, 7, 1, 1, 18, 26, 0, // Skip to: 13015
+/* 6341 */    MCD_OPC_Decode, 232, 6, 16, // Opcode: MSUBM_H_rrr1_LU
+/* 6345 */    MCD_OPC_FilterValue, 30, 16, 0, 0, // Skip to: 6366
+/* 6350 */    MCD_OPC_CheckPredicate, 1, 4, 26, 0, // Skip to: 13015
+/* 6355 */    MCD_OPC_CheckField, 7, 1, 1, 253, 25, 0, // Skip to: 13015
+/* 6362 */    MCD_OPC_Decode, 231, 6, 16, // Opcode: MSUBM_H_rrr1_LL
+/* 6366 */    MCD_OPC_FilterValue, 31, 16, 0, 0, // Skip to: 6387
+/* 6371 */    MCD_OPC_CheckPredicate, 1, 239, 25, 0, // Skip to: 13015
+/* 6376 */    MCD_OPC_CheckField, 7, 1, 1, 232, 25, 0, // Skip to: 13015
+/* 6383 */    MCD_OPC_Decode, 234, 6, 16, // Opcode: MSUBM_H_rrr1_UU
+/* 6387 */    MCD_OPC_FilterValue, 34, 35, 0, 0, // Skip to: 6427
+/* 6392 */    MCD_OPC_ExtractField, 16, 2,  // Inst{17-16} ...
+/* 6395 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 6411
+/* 6400 */    MCD_OPC_CheckField, 7, 1, 0, 208, 25, 0, // Skip to: 13015
+/* 6407 */    MCD_OPC_Decode, 149, 7, 15, // Opcode: MSUBS_U_rrr2
+/* 6411 */    MCD_OPC_FilterValue, 2, 199, 25, 0, // Skip to: 13015
+/* 6416 */    MCD_OPC_CheckField, 7, 1, 0, 192, 25, 0, // Skip to: 13015
+/* 6423 */    MCD_OPC_Decode, 153, 7, 15, // Opcode: MSUBS_rrr2
+/* 6427 */    MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 6448
+/* 6432 */    MCD_OPC_CheckPredicate, 1, 178, 25, 0, // Skip to: 13015
+/* 6437 */    MCD_OPC_CheckField, 7, 1, 1, 171, 25, 0, // Skip to: 13015
+/* 6444 */    MCD_OPC_Decode, 243, 6, 16, // Opcode: MSUBRS_H_rrr1_UL
+/* 6448 */    MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 6469
+/* 6453 */    MCD_OPC_CheckPredicate, 1, 157, 25, 0, // Skip to: 13015
+/* 6458 */    MCD_OPC_CheckField, 7, 1, 1, 150, 25, 0, // Skip to: 13015
+/* 6465 */    MCD_OPC_Decode, 242, 6, 16, // Opcode: MSUBRS_H_rrr1_LU
+/* 6469 */    MCD_OPC_FilterValue, 46, 16, 0, 0, // Skip to: 6490
+/* 6474 */    MCD_OPC_CheckPredicate, 1, 136, 25, 0, // Skip to: 13015
+/* 6479 */    MCD_OPC_CheckField, 7, 1, 1, 129, 25, 0, // Skip to: 13015
+/* 6486 */    MCD_OPC_Decode, 241, 6, 16, // Opcode: MSUBRS_H_rrr1_LL
+/* 6490 */    MCD_OPC_FilterValue, 47, 16, 0, 0, // Skip to: 6511
+/* 6495 */    MCD_OPC_CheckPredicate, 1, 115, 25, 0, // Skip to: 13015
+/* 6500 */    MCD_OPC_CheckField, 7, 1, 1, 108, 25, 0, // Skip to: 13015
+/* 6507 */    MCD_OPC_Decode, 245, 6, 16, // Opcode: MSUBRS_H_rrr1_UU
+/* 6511 */    MCD_OPC_FilterValue, 56, 16, 0, 0, // Skip to: 6532
+/* 6516 */    MCD_OPC_CheckPredicate, 1, 94, 25, 0, // Skip to: 13015
+/* 6521 */    MCD_OPC_CheckField, 7, 1, 1, 87, 25, 0, // Skip to: 13015
+/* 6528 */    MCD_OPC_Decode, 133, 7, 16, // Opcode: MSUBS_H_rrr1_UL
+/* 6532 */    MCD_OPC_FilterValue, 57, 16, 0, 0, // Skip to: 6553
+/* 6537 */    MCD_OPC_CheckPredicate, 1, 73, 25, 0, // Skip to: 13015
+/* 6542 */    MCD_OPC_CheckField, 7, 1, 1, 66, 25, 0, // Skip to: 13015
+/* 6549 */    MCD_OPC_Decode, 132, 7, 16, // Opcode: MSUBS_H_rrr1_LU
+/* 6553 */    MCD_OPC_FilterValue, 58, 53, 0, 0, // Skip to: 6611
+/* 6558 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6561 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6597
+/* 6566 */    MCD_OPC_ExtractField, 16, 2,  // Inst{17-16} ...
+/* 6569 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6583
+/* 6574 */    MCD_OPC_CheckPredicate, 1, 36, 25, 0, // Skip to: 13015
+/* 6579 */    MCD_OPC_Decode, 150, 7, 15, // Opcode: MSUBS_U_rrr2_e
+/* 6583 */    MCD_OPC_FilterValue, 2, 27, 25, 0, // Skip to: 13015
+/* 6588 */    MCD_OPC_CheckPredicate, 1, 22, 25, 0, // Skip to: 13015
+/* 6593 */    MCD_OPC_Decode, 154, 7, 15, // Opcode: MSUBS_rrr2_e
+/* 6597 */    MCD_OPC_FilterValue, 1, 13, 25, 0, // Skip to: 13015
+/* 6602 */    MCD_OPC_CheckPredicate, 1, 8, 25, 0, // Skip to: 13015
+/* 6607 */    MCD_OPC_Decode, 131, 7, 16, // Opcode: MSUBS_H_rrr1_LL
+/* 6611 */    MCD_OPC_FilterValue, 59, 16, 0, 0, // Skip to: 6632
+/* 6616 */    MCD_OPC_CheckPredicate, 1, 250, 24, 0, // Skip to: 13015
+/* 6621 */    MCD_OPC_CheckField, 7, 1, 1, 243, 24, 0, // Skip to: 13015
+/* 6628 */    MCD_OPC_Decode, 134, 7, 16, // Opcode: MSUBS_H_rrr1_UU
+/* 6632 */    MCD_OPC_FilterValue, 60, 16, 0, 0, // Skip to: 6653
+/* 6637 */    MCD_OPC_CheckPredicate, 1, 229, 24, 0, // Skip to: 13015
+/* 6642 */    MCD_OPC_CheckField, 7, 1, 1, 222, 24, 0, // Skip to: 13015
+/* 6649 */    MCD_OPC_Decode, 225, 6, 16, // Opcode: MSUBMS_H_rrr1_UL
+/* 6653 */    MCD_OPC_FilterValue, 61, 16, 0, 0, // Skip to: 6674
+/* 6658 */    MCD_OPC_CheckPredicate, 1, 208, 24, 0, // Skip to: 13015
+/* 6663 */    MCD_OPC_CheckField, 7, 1, 1, 201, 24, 0, // Skip to: 13015
+/* 6670 */    MCD_OPC_Decode, 224, 6, 16, // Opcode: MSUBMS_H_rrr1_LU
+/* 6674 */    MCD_OPC_FilterValue, 62, 16, 0, 0, // Skip to: 6695
+/* 6679 */    MCD_OPC_CheckPredicate, 1, 187, 24, 0, // Skip to: 13015
+/* 6684 */    MCD_OPC_CheckField, 7, 1, 1, 180, 24, 0, // Skip to: 13015
+/* 6691 */    MCD_OPC_Decode, 223, 6, 16, // Opcode: MSUBMS_H_rrr1_LL
+/* 6695 */    MCD_OPC_FilterValue, 63, 171, 24, 0, // Skip to: 13015
+/* 6700 */    MCD_OPC_CheckPredicate, 1, 166, 24, 0, // Skip to: 13015
+/* 6705 */    MCD_OPC_CheckField, 7, 1, 1, 159, 24, 0, // Skip to: 13015
+/* 6712 */    MCD_OPC_Decode, 226, 6, 16, // Opcode: MSUBMS_H_rrr1_UU
+/* 6716 */    MCD_OPC_FilterValue, 37, 87, 0, 0, // Skip to: 6808
+/* 6721 */    MCD_OPC_ExtractField, 26, 2,  // Inst{27-26} ...
+/* 6724 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 6750
+/* 6729 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6732 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6741
+/* 6737 */    MCD_OPC_Decode, 241, 8, 17, // Opcode: ST_B_abs
+/* 6741 */    MCD_OPC_FilterValue, 1, 125, 24, 0, // Skip to: 13015
+/* 6746 */    MCD_OPC_Decode, 162, 9, 17, // Opcode: ST_W_abs
+/* 6750 */    MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 6766
+/* 6755 */    MCD_OPC_CheckField, 7, 1, 1, 109, 24, 0, // Skip to: 13015
+/* 6762 */    MCD_OPC_Decode, 134, 9, 17, // Opcode: ST_D_abs
+/* 6766 */    MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 6792
+/* 6771 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6774 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6783
+/* 6779 */    MCD_OPC_Decode, 140, 9, 17, // Opcode: ST_H_abs
+/* 6783 */    MCD_OPC_FilterValue, 1, 83, 24, 0, // Skip to: 13015
+/* 6788 */    MCD_OPC_Decode, 225, 8, 17, // Opcode: ST_A_abs
+/* 6792 */    MCD_OPC_FilterValue, 3, 74, 24, 0, // Skip to: 13015
+/* 6797 */    MCD_OPC_CheckField, 7, 1, 1, 67, 24, 0, // Skip to: 13015
+/* 6804 */    MCD_OPC_Decode, 128, 9, 17, // Opcode: ST_DA_abs
+/* 6808 */    MCD_OPC_FilterValue, 39, 107, 0, 0, // Skip to: 6920
+/* 6813 */    MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
+/* 6816 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 6842
+/* 6821 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6824 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6833
+/* 6829 */    MCD_OPC_Decode, 194, 8, 18, // Opcode: SH_AND_T
+/* 6833 */    MCD_OPC_FilterValue, 1, 33, 24, 0, // Skip to: 13015
+/* 6838 */    MCD_OPC_Decode, 209, 8, 18, // Opcode: SH_NAND_T
+/* 6842 */    MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 6868
+/* 6847 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6850 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6859
+/* 6855 */    MCD_OPC_Decode, 214, 8, 18, // Opcode: SH_OR_T
+/* 6859 */    MCD_OPC_FilterValue, 1, 7, 24, 0, // Skip to: 13015
+/* 6864 */    MCD_OPC_Decode, 213, 8, 18, // Opcode: SH_ORN_T
+/* 6868 */    MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 6894
+/* 6873 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6876 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6885
+/* 6881 */    MCD_OPC_Decode, 212, 8, 18, // Opcode: SH_NOR_T
+/* 6885 */    MCD_OPC_FilterValue, 1, 237, 23, 0, // Skip to: 13015
+/* 6890 */    MCD_OPC_Decode, 215, 8, 18, // Opcode: SH_XNOR_T
+/* 6894 */    MCD_OPC_FilterValue, 3, 228, 23, 0, // Skip to: 13015
+/* 6899 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6902 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6911
+/* 6907 */    MCD_OPC_Decode, 193, 8, 18, // Opcode: SH_ANDN_T
+/* 6911 */    MCD_OPC_FilterValue, 1, 211, 23, 0, // Skip to: 13015
+/* 6916 */    MCD_OPC_Decode, 216, 8, 18, // Opcode: SH_XOR_T
+/* 6920 */    MCD_OPC_FilterValue, 41, 45, 2, 0, // Skip to: 7482
+/* 6925 */    MCD_OPC_ExtractField, 22, 6,  // Inst{27-22} ...
+/* 6928 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 6954
+/* 6933 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6936 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6945
+/* 6941 */    MCD_OPC_Decode, 221, 4, 19, // Opcode: LD_B_bo_r
+/* 6945 */    MCD_OPC_FilterValue, 1, 177, 23, 0, // Skip to: 13015
+/* 6950 */    MCD_OPC_Decode, 246, 8, 19, // Opcode: ST_B_bo_r
+/* 6954 */    MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 6970
+/* 6959 */    MCD_OPC_CheckField, 7, 1, 0, 161, 23, 0, // Skip to: 13015
+/* 6966 */    MCD_OPC_Decode, 206, 4, 19, // Opcode: LD_BU_bo_r
+/* 6970 */    MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 6996
+/* 6975 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6978 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6987
+/* 6983 */    MCD_OPC_Decode, 251, 4, 19, // Opcode: LD_H_bo_r
+/* 6987 */    MCD_OPC_FilterValue, 1, 135, 23, 0, // Skip to: 13015
+/* 6992 */    MCD_OPC_Decode, 145, 9, 19, // Opcode: ST_H_bo_r
+/* 6996 */    MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 7012
+/* 7001 */    MCD_OPC_CheckField, 7, 1, 0, 119, 23, 0, // Skip to: 13015
+/* 7008 */    MCD_OPC_Decode, 244, 4, 19, // Opcode: LD_HU_bo_r
+/* 7012 */    MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 7038
+/* 7017 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7020 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7029
+/* 7025 */    MCD_OPC_Decode, 144, 5, 19, // Opcode: LD_W_bo_r
+/* 7029 */    MCD_OPC_FilterValue, 1, 93, 23, 0, // Skip to: 13015
+/* 7034 */    MCD_OPC_Decode, 167, 9, 19, // Opcode: ST_W_bo_r
+/* 7038 */    MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 7064
+/* 7043 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7046 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7055
+/* 7051 */    MCD_OPC_Decode, 238, 4, 19, // Opcode: LD_D_bo_r
+/* 7055 */    MCD_OPC_FilterValue, 1, 67, 23, 0, // Skip to: 13015
+/* 7060 */    MCD_OPC_Decode, 139, 9, 19, // Opcode: ST_D_bo_r
+/* 7064 */    MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 7090
+/* 7069 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7072 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7081
+/* 7077 */    MCD_OPC_Decode, 190, 4, 19, // Opcode: LD_A_bo_r
+/* 7081 */    MCD_OPC_FilterValue, 1, 41, 23, 0, // Skip to: 13015
+/* 7086 */    MCD_OPC_Decode, 230, 8, 19, // Opcode: ST_A_bo_r
+/* 7090 */    MCD_OPC_FilterValue, 7, 21, 0, 0, // Skip to: 7116
+/* 7095 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7098 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7107
+/* 7103 */    MCD_OPC_Decode, 232, 4, 19, // Opcode: LD_DA_bo_r
+/* 7107 */    MCD_OPC_FilterValue, 1, 15, 23, 0, // Skip to: 13015
+/* 7112 */    MCD_OPC_Decode, 133, 9, 19, // Opcode: ST_DA_bo_r
+/* 7116 */    MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 7142
+/* 7121 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7124 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7133
+/* 7129 */    MCD_OPC_Decode, 138, 5, 19, // Opcode: LD_Q_bo_r
+/* 7133 */    MCD_OPC_FilterValue, 1, 245, 22, 0, // Skip to: 13015
+/* 7138 */    MCD_OPC_Decode, 160, 9, 19, // Opcode: ST_Q_bo_r
+/* 7142 */    MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 7163
+/* 7147 */    MCD_OPC_CheckPredicate, 1, 231, 22, 0, // Skip to: 13015
+/* 7152 */    MCD_OPC_CheckField, 7, 1, 1, 224, 22, 0, // Skip to: 13015
+/* 7159 */    MCD_OPC_Decode, 221, 2, 19, // Opcode: CACHEA_W_bo_r
+/* 7163 */    MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 7184
+/* 7168 */    MCD_OPC_CheckPredicate, 1, 210, 22, 0, // Skip to: 13015
+/* 7173 */    MCD_OPC_CheckField, 7, 1, 1, 203, 22, 0, // Skip to: 13015
+/* 7180 */    MCD_OPC_Decode, 216, 2, 19, // Opcode: CACHEA_WI_bo_r
+/* 7184 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 7205
+/* 7189 */    MCD_OPC_CheckPredicate, 1, 189, 22, 0, // Skip to: 13015
+/* 7194 */    MCD_OPC_CheckField, 7, 1, 1, 182, 22, 0, // Skip to: 13015
+/* 7201 */    MCD_OPC_Decode, 211, 2, 19, // Opcode: CACHEA_I_bo_r
+/* 7205 */    MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 7231
+/* 7210 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7213 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7222
+/* 7218 */    MCD_OPC_Decode, 218, 4, 19, // Opcode: LD_B_bo_c
+/* 7222 */    MCD_OPC_FilterValue, 1, 156, 22, 0, // Skip to: 13015
+/* 7227 */    MCD_OPC_Decode, 243, 8, 19, // Opcode: ST_B_bo_c
+/* 7231 */    MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 7247
+/* 7236 */    MCD_OPC_CheckField, 7, 1, 0, 140, 22, 0, // Skip to: 13015
+/* 7243 */    MCD_OPC_Decode, 203, 4, 19, // Opcode: LD_BU_bo_c
+/* 7247 */    MCD_OPC_FilterValue, 18, 21, 0, 0, // Skip to: 7273
+/* 7252 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7255 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7264
+/* 7260 */    MCD_OPC_Decode, 248, 4, 19, // Opcode: LD_H_bo_c
+/* 7264 */    MCD_OPC_FilterValue, 1, 114, 22, 0, // Skip to: 13015
+/* 7269 */    MCD_OPC_Decode, 142, 9, 19, // Opcode: ST_H_bo_c
+/* 7273 */    MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 7289
+/* 7278 */    MCD_OPC_CheckField, 7, 1, 0, 98, 22, 0, // Skip to: 13015
+/* 7285 */    MCD_OPC_Decode, 241, 4, 19, // Opcode: LD_HU_bo_c
+/* 7289 */    MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 7315
+/* 7294 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7297 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7306
+/* 7302 */    MCD_OPC_Decode, 141, 5, 19, // Opcode: LD_W_bo_c
+/* 7306 */    MCD_OPC_FilterValue, 1, 72, 22, 0, // Skip to: 13015
+/* 7311 */    MCD_OPC_Decode, 164, 9, 19, // Opcode: ST_W_bo_c
+/* 7315 */    MCD_OPC_FilterValue, 21, 21, 0, 0, // Skip to: 7341
+/* 7320 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7323 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7332
+/* 7328 */    MCD_OPC_Decode, 235, 4, 19, // Opcode: LD_D_bo_c
+/* 7332 */    MCD_OPC_FilterValue, 1, 46, 22, 0, // Skip to: 13015
+/* 7337 */    MCD_OPC_Decode, 136, 9, 19, // Opcode: ST_D_bo_c
+/* 7341 */    MCD_OPC_FilterValue, 22, 21, 0, 0, // Skip to: 7367
+/* 7346 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7349 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7358
+/* 7354 */    MCD_OPC_Decode, 187, 4, 19, // Opcode: LD_A_bo_c
+/* 7358 */    MCD_OPC_FilterValue, 1, 20, 22, 0, // Skip to: 13015
+/* 7363 */    MCD_OPC_Decode, 227, 8, 19, // Opcode: ST_A_bo_c
+/* 7367 */    MCD_OPC_FilterValue, 23, 21, 0, 0, // Skip to: 7393
+/* 7372 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7375 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7384
+/* 7380 */    MCD_OPC_Decode, 229, 4, 19, // Opcode: LD_DA_bo_c
+/* 7384 */    MCD_OPC_FilterValue, 1, 250, 21, 0, // Skip to: 13015
+/* 7389 */    MCD_OPC_Decode, 130, 9, 19, // Opcode: ST_DA_bo_c
+/* 7393 */    MCD_OPC_FilterValue, 24, 21, 0, 0, // Skip to: 7419
+/* 7398 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7401 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7410
+/* 7406 */    MCD_OPC_Decode, 135, 5, 19, // Opcode: LD_Q_bo_c
+/* 7410 */    MCD_OPC_FilterValue, 1, 224, 21, 0, // Skip to: 13015
+/* 7415 */    MCD_OPC_Decode, 157, 9, 19, // Opcode: ST_Q_bo_c
+/* 7419 */    MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 7440
+/* 7424 */    MCD_OPC_CheckPredicate, 1, 210, 21, 0, // Skip to: 13015
+/* 7429 */    MCD_OPC_CheckField, 7, 1, 1, 203, 21, 0, // Skip to: 13015
+/* 7436 */    MCD_OPC_Decode, 218, 2, 19, // Opcode: CACHEA_W_bo_c
+/* 7440 */    MCD_OPC_FilterValue, 29, 16, 0, 0, // Skip to: 7461
+/* 7445 */    MCD_OPC_CheckPredicate, 1, 189, 21, 0, // Skip to: 13015
+/* 7450 */    MCD_OPC_CheckField, 7, 1, 1, 182, 21, 0, // Skip to: 13015
+/* 7457 */    MCD_OPC_Decode, 213, 2, 19, // Opcode: CACHEA_WI_bo_c
+/* 7461 */    MCD_OPC_FilterValue, 30, 173, 21, 0, // Skip to: 13015
+/* 7466 */    MCD_OPC_CheckPredicate, 1, 168, 21, 0, // Skip to: 13015
+/* 7471 */    MCD_OPC_CheckField, 7, 1, 1, 161, 21, 0, // Skip to: 13015
+/* 7478 */    MCD_OPC_Decode, 208, 2, 19, // Opcode: CACHEA_I_bo_c
+/* 7482 */    MCD_OPC_FilterValue, 43, 161, 0, 0, // Skip to: 7648
+/* 7487 */    MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
+/* 7490 */    MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 7533
+/* 7495 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7498 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 7524
+/* 7503 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 7506 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7515
+/* 7511 */    MCD_OPC_Decode, 240, 2, 32, // Opcode: CADD_rrr
+/* 7515 */    MCD_OPC_FilterValue, 4, 119, 21, 0, // Skip to: 13015
+/* 7520 */    MCD_OPC_Decode, 234, 2, 32, // Opcode: CADDN_rrr
+/* 7524 */    MCD_OPC_FilterValue, 1, 110, 21, 0, // Skip to: 13015
+/* 7529 */    MCD_OPC_Decode, 239, 2, 24, // Opcode: CADD_rcr
+/* 7533 */    MCD_OPC_FilterValue, 1, 38, 0, 0, // Skip to: 7576
+/* 7538 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7541 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 7567
+/* 7546 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 7549 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7558
+/* 7554 */    MCD_OPC_Decode, 146, 3, 32, // Opcode: CSUB_rrr
+/* 7558 */    MCD_OPC_FilterValue, 4, 76, 21, 0, // Skip to: 13015
+/* 7563 */    MCD_OPC_Decode, 144, 3, 32, // Opcode: CSUBN_rrr
+/* 7567 */    MCD_OPC_FilterValue, 1, 67, 21, 0, // Skip to: 13015
+/* 7572 */    MCD_OPC_Decode, 233, 2, 24, // Opcode: CADDN_rcr
+/* 7576 */    MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 7616
+/* 7581 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 7584 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 7600
+/* 7589 */    MCD_OPC_CheckField, 7, 1, 0, 43, 21, 0, // Skip to: 13015
+/* 7596 */    MCD_OPC_Decode, 181, 8, 32, // Opcode: SEL_rrr
+/* 7600 */    MCD_OPC_FilterValue, 4, 34, 21, 0, // Skip to: 13015
+/* 7605 */    MCD_OPC_CheckField, 7, 1, 0, 27, 21, 0, // Skip to: 13015
+/* 7612 */    MCD_OPC_Decode, 177, 8, 32, // Opcode: SELN_rrr
+/* 7616 */    MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 7632
+/* 7621 */    MCD_OPC_CheckField, 7, 1, 1, 11, 21, 0, // Skip to: 13015
+/* 7628 */    MCD_OPC_Decode, 180, 8, 24, // Opcode: SEL_rcr
+/* 7632 */    MCD_OPC_FilterValue, 5, 2, 21, 0, // Skip to: 13015
+/* 7637 */    MCD_OPC_CheckField, 7, 1, 1, 251, 20, 0, // Skip to: 13015
+/* 7644 */    MCD_OPC_Decode, 176, 8, 24, // Opcode: SELN_rcr
+/* 7648 */    MCD_OPC_FilterValue, 45, 122, 0, 0, // Skip to: 7775
+/* 7653 */    MCD_OPC_ExtractField, 21, 7,  // Inst{27-21} ...
+/* 7656 */    MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 7709
+/* 7661 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7664 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7700
+/* 7669 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 7672 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7686
+/* 7677 */    MCD_OPC_CheckPredicate, 1, 213, 20, 0, // Skip to: 13015
+/* 7682 */    MCD_OPC_Decode, 244, 2, 14, // Opcode: CALLI_rr
+/* 7686 */    MCD_OPC_FilterValue, 4, 204, 20, 0, // Skip to: 13015
+/* 7691 */    MCD_OPC_CheckPredicate, 0, 199, 20, 0, // Skip to: 13015
+/* 7696 */    MCD_OPC_Decode, 200, 3, 14, // Opcode: FCALLA_i
+/* 7700 */    MCD_OPC_FilterValue, 1, 190, 20, 0, // Skip to: 13015
+/* 7705 */    MCD_OPC_Decode, 199, 2, 20, // Opcode: BISR_rc
+/* 7709 */    MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 7759
+/* 7714 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 7717 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7738
+/* 7722 */    MCD_OPC_CheckPredicate, 1, 168, 20, 0, // Skip to: 13015
+/* 7727 */    MCD_OPC_CheckField, 7, 1, 0, 161, 20, 0, // Skip to: 13015
+/* 7734 */    MCD_OPC_Decode, 132, 4, 14, // Opcode: JLI_rr
+/* 7738 */    MCD_OPC_FilterValue, 4, 152, 20, 0, // Skip to: 13015
+/* 7743 */    MCD_OPC_CheckPredicate, 1, 147, 20, 0, // Skip to: 13015
+/* 7748 */    MCD_OPC_CheckField, 7, 1, 0, 140, 20, 0, // Skip to: 13015
+/* 7755 */    MCD_OPC_Decode, 253, 3, 14, // Opcode: JI_rr
+/* 7759 */    MCD_OPC_FilterValue, 4, 131, 20, 0, // Skip to: 13015
+/* 7764 */    MCD_OPC_CheckField, 7, 1, 1, 124, 20, 0, // Skip to: 13015
+/* 7771 */    MCD_OPC_Decode, 218, 9, 20, // Opcode: SYSCALL_rc
+/* 7775 */    MCD_OPC_FilterValue, 47, 18, 0, 0, // Skip to: 7798
+/* 7780 */    MCD_OPC_CheckField, 12, 20, 0, 108, 20, 0, // Skip to: 13015
+/* 7787 */    MCD_OPC_CheckField, 7, 1, 0, 101, 20, 0, // Skip to: 13015
+/* 7794 */    MCD_OPC_Decode, 156, 8, 21, // Opcode: RSTV_sys
+/* 7798 */    MCD_OPC_FilterValue, 51, 242, 1, 0, // Skip to: 8301
+/* 7803 */    MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
+/* 7806 */    MCD_OPC_FilterValue, 1, 104, 0, 0, // Skip to: 7915
+/* 7811 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7814 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7823
+/* 7819 */    MCD_OPC_Decode, 174, 7, 24, // Opcode: MSUB_rcr
+/* 7823 */    MCD_OPC_FilterValue, 1, 67, 20, 0, // Skip to: 13015
+/* 7828 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 7831 */    MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 7852
+/* 7836 */    MCD_OPC_CheckPredicate, 1, 54, 20, 0, // Skip to: 13015
+/* 7841 */    MCD_OPC_CheckField, 24, 4, 0, 47, 20, 0, // Skip to: 13015
+/* 7848 */    MCD_OPC_Decode, 193, 7, 23, // Opcode: MULR_H_rr1_UL2e
+/* 7852 */    MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 7873
+/* 7857 */    MCD_OPC_CheckPredicate, 1, 33, 20, 0, // Skip to: 13015
+/* 7862 */    MCD_OPC_CheckField, 24, 4, 0, 26, 20, 0, // Skip to: 13015
+/* 7869 */    MCD_OPC_Decode, 192, 7, 23, // Opcode: MULR_H_rr1_LU2e
+/* 7873 */    MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 7894
+/* 7878 */    MCD_OPC_CheckPredicate, 1, 12, 20, 0, // Skip to: 13015
+/* 7883 */    MCD_OPC_CheckField, 24, 4, 0, 5, 20, 0, // Skip to: 13015
+/* 7890 */    MCD_OPC_Decode, 191, 7, 23, // Opcode: MULR_H_rr1_LL2e
+/* 7894 */    MCD_OPC_FilterValue, 7, 252, 19, 0, // Skip to: 13015
+/* 7899 */    MCD_OPC_CheckPredicate, 1, 247, 19, 0, // Skip to: 13015
+/* 7904 */    MCD_OPC_CheckField, 24, 4, 0, 240, 19, 0, // Skip to: 13015
+/* 7911 */    MCD_OPC_Decode, 194, 7, 23, // Opcode: MULR_H_rr1_UU2e
+/* 7915 */    MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 7936
+/* 7920 */    MCD_OPC_CheckPredicate, 1, 226, 19, 0, // Skip to: 13015
+/* 7925 */    MCD_OPC_CheckField, 7, 1, 0, 219, 19, 0, // Skip to: 13015
+/* 7932 */    MCD_OPC_Decode, 172, 7, 24, // Opcode: MSUB_U_rcr
+/* 7936 */    MCD_OPC_FilterValue, 3, 193, 0, 0, // Skip to: 8134
+/* 7941 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7944 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7958
+/* 7949 */    MCD_OPC_CheckPredicate, 1, 197, 19, 0, // Skip to: 13015
+/* 7954 */    MCD_OPC_Decode, 175, 7, 24, // Opcode: MSUB_rcr_e
+/* 7958 */    MCD_OPC_FilterValue, 1, 188, 19, 0, // Skip to: 13015
+/* 7963 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 7966 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7987
+/* 7971 */    MCD_OPC_CheckPredicate, 1, 175, 19, 0, // Skip to: 13015
+/* 7976 */    MCD_OPC_CheckField, 24, 4, 0, 168, 19, 0, // Skip to: 13015
+/* 7983 */    MCD_OPC_Decode, 208, 7, 23, // Opcode: MUL_H_rr1_UL2e
+/* 7987 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 8008
+/* 7992 */    MCD_OPC_CheckPredicate, 1, 154, 19, 0, // Skip to: 13015
+/* 7997 */    MCD_OPC_CheckField, 24, 4, 0, 147, 19, 0, // Skip to: 13015
+/* 8004 */    MCD_OPC_Decode, 207, 7, 23, // Opcode: MUL_H_rr1_LU2e
+/* 8008 */    MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 8029
+/* 8013 */    MCD_OPC_CheckPredicate, 1, 133, 19, 0, // Skip to: 13015
+/* 8018 */    MCD_OPC_CheckField, 24, 4, 0, 126, 19, 0, // Skip to: 13015
+/* 8025 */    MCD_OPC_Decode, 206, 7, 23, // Opcode: MUL_H_rr1_LL2e
+/* 8029 */    MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 8050
+/* 8034 */    MCD_OPC_CheckPredicate, 1, 112, 19, 0, // Skip to: 13015
+/* 8039 */    MCD_OPC_CheckField, 24, 4, 0, 105, 19, 0, // Skip to: 13015
+/* 8046 */    MCD_OPC_Decode, 209, 7, 23, // Opcode: MUL_H_rr1_UU2e
+/* 8050 */    MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 8071
+/* 8055 */    MCD_OPC_CheckPredicate, 1, 91, 19, 0, // Skip to: 13015
+/* 8060 */    MCD_OPC_CheckField, 24, 4, 0, 84, 19, 0, // Skip to: 13015
+/* 8067 */    MCD_OPC_Decode, 185, 7, 23, // Opcode: MULM_H_rr1_UL2e
+/* 8071 */    MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 8092
+/* 8076 */    MCD_OPC_CheckPredicate, 1, 70, 19, 0, // Skip to: 13015
+/* 8081 */    MCD_OPC_CheckField, 24, 4, 0, 63, 19, 0, // Skip to: 13015
+/* 8088 */    MCD_OPC_Decode, 184, 7, 23, // Opcode: MULM_H_rr1_LU2e
+/* 8092 */    MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 8113
+/* 8097 */    MCD_OPC_CheckPredicate, 1, 49, 19, 0, // Skip to: 13015
+/* 8102 */    MCD_OPC_CheckField, 24, 4, 0, 42, 19, 0, // Skip to: 13015
+/* 8109 */    MCD_OPC_Decode, 183, 7, 23, // Opcode: MULM_H_rr1_LL2e
+/* 8113 */    MCD_OPC_FilterValue, 7, 33, 19, 0, // Skip to: 13015
+/* 8118 */    MCD_OPC_CheckPredicate, 1, 28, 19, 0, // Skip to: 13015
+/* 8123 */    MCD_OPC_CheckField, 24, 4, 0, 21, 19, 0, // Skip to: 13015
+/* 8130 */    MCD_OPC_Decode, 186, 7, 23, // Opcode: MULM_H_rr1_UU2e
+/* 8134 */    MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 8150
+/* 8139 */    MCD_OPC_CheckField, 7, 1, 0, 5, 19, 0, // Skip to: 13015
+/* 8146 */    MCD_OPC_Decode, 147, 7, 24, // Opcode: MSUBS_U_rcr
+/* 8150 */    MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 8166
+/* 8155 */    MCD_OPC_CheckField, 7, 1, 0, 245, 18, 0, // Skip to: 13015
+/* 8162 */    MCD_OPC_Decode, 151, 7, 24, // Opcode: MSUBS_rcr
+/* 8166 */    MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 8187
+/* 8171 */    MCD_OPC_CheckPredicate, 1, 231, 18, 0, // Skip to: 13015
+/* 8176 */    MCD_OPC_CheckField, 7, 1, 0, 224, 18, 0, // Skip to: 13015
+/* 8183 */    MCD_OPC_Decode, 148, 7, 24, // Opcode: MSUBS_U_rcr_e
+/* 8187 */    MCD_OPC_FilterValue, 7, 215, 18, 0, // Skip to: 13015
+/* 8192 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8195 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8209
+/* 8200 */    MCD_OPC_CheckPredicate, 1, 202, 18, 0, // Skip to: 13015
+/* 8205 */    MCD_OPC_Decode, 152, 7, 24, // Opcode: MSUBS_rcr_e
+/* 8209 */    MCD_OPC_FilterValue, 1, 193, 18, 0, // Skip to: 13015
+/* 8214 */    MCD_OPC_ExtractField, 18, 3,  // Inst{20-18} ...
+/* 8217 */    MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 8238
+/* 8222 */    MCD_OPC_CheckPredicate, 1, 180, 18, 0, // Skip to: 13015
+/* 8227 */    MCD_OPC_CheckField, 24, 4, 0, 173, 18, 0, // Skip to: 13015
+/* 8234 */    MCD_OPC_Decode, 181, 7, 23, // Opcode: MULMS_H_rr1_UL2e
+/* 8238 */    MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 8259
+/* 8243 */    MCD_OPC_CheckPredicate, 1, 159, 18, 0, // Skip to: 13015
+/* 8248 */    MCD_OPC_CheckField, 24, 4, 0, 152, 18, 0, // Skip to: 13015
+/* 8255 */    MCD_OPC_Decode, 180, 7, 23, // Opcode: MULMS_H_rr1_LU2e
+/* 8259 */    MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 8280
+/* 8264 */    MCD_OPC_CheckPredicate, 1, 138, 18, 0, // Skip to: 13015
+/* 8269 */    MCD_OPC_CheckField, 24, 4, 0, 131, 18, 0, // Skip to: 13015
+/* 8276 */    MCD_OPC_Decode, 179, 7, 23, // Opcode: MULMS_H_rr1_LL2e
+/* 8280 */    MCD_OPC_FilterValue, 7, 122, 18, 0, // Skip to: 13015
+/* 8285 */    MCD_OPC_CheckPredicate, 1, 117, 18, 0, // Skip to: 13015
+/* 8290 */    MCD_OPC_CheckField, 24, 4, 0, 110, 18, 0, // Skip to: 13015
+/* 8297 */    MCD_OPC_Decode, 182, 7, 23, // Opcode: MULMS_H_rr1_UU2e
+/* 8301 */    MCD_OPC_FilterValue, 53, 16, 0, 0, // Skip to: 8322
+/* 8306 */    MCD_OPC_CheckPredicate, 0, 96, 18, 0, // Skip to: 13015
+/* 8311 */    MCD_OPC_CheckField, 7, 1, 1, 89, 18, 0, // Skip to: 13015
+/* 8318 */    MCD_OPC_Decode, 231, 8, 28, // Opcode: ST_A_bol
+/* 8322 */    MCD_OPC_FilterValue, 55, 87, 0, 0, // Skip to: 8414
+/* 8327 */    MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
+/* 8330 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 8356
+/* 8335 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8338 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8347
+/* 8343 */    MCD_OPC_Decode, 224, 3, 33, // Opcode: INSERT_rrpw
+/* 8347 */    MCD_OPC_FilterValue, 1, 55, 18, 0, // Skip to: 13015
+/* 8352 */    MCD_OPC_Decode, 221, 3, 34, // Opcode: INSERT_rcpw
+/* 8356 */    MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 8382
+/* 8361 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8364 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8373
+/* 8369 */    MCD_OPC_Decode, 219, 3, 33, // Opcode: IMASK_rrpw
+/* 8373 */    MCD_OPC_FilterValue, 1, 29, 18, 0, // Skip to: 13015
+/* 8378 */    MCD_OPC_Decode, 217, 3, 34, // Opcode: IMASK_rcpw
+/* 8382 */    MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 8398
+/* 8387 */    MCD_OPC_CheckField, 7, 1, 0, 13, 18, 0, // Skip to: 13015
+/* 8394 */    MCD_OPC_Decode, 196, 3, 33, // Opcode: EXTR_rrpw
+/* 8398 */    MCD_OPC_FilterValue, 3, 4, 18, 0, // Skip to: 13015
+/* 8403 */    MCD_OPC_CheckField, 7, 1, 0, 253, 17, 0, // Skip to: 13015
+/* 8410 */    MCD_OPC_Decode, 193, 3, 33, // Opcode: EXTR_U_rrpw
+/* 8414 */    MCD_OPC_FilterValue, 57, 31, 0, 0, // Skip to: 8450
+/* 8419 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8422 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8436
+/* 8427 */    MCD_OPC_CheckPredicate, 0, 231, 17, 0, // Skip to: 13015
+/* 8432 */    MCD_OPC_Decode, 207, 4, 28, // Opcode: LD_BU_bol
+/* 8436 */    MCD_OPC_FilterValue, 1, 222, 17, 0, // Skip to: 13015
+/* 8441 */    MCD_OPC_CheckPredicate, 0, 217, 17, 0, // Skip to: 13015
+/* 8446 */    MCD_OPC_Decode, 245, 4, 28, // Opcode: LD_HU_bol
+/* 8450 */    MCD_OPC_FilterValue, 59, 21, 0, 0, // Skip to: 8476
+/* 8455 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8458 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8467
+/* 8463 */    MCD_OPC_Decode, 187, 6, 22, // Opcode: MOV_rlc
+/* 8467 */    MCD_OPC_FilterValue, 1, 191, 17, 0, // Skip to: 13015
+/* 8472 */    MCD_OPC_Decode, 186, 6, 22, // Opcode: MOV_U_rlc
+/* 8476 */    MCD_OPC_FilterValue, 61, 35, 0, 0, // Skip to: 8516
+/* 8481 */    MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 8484 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8500
+/* 8489 */    MCD_OPC_CheckField, 7, 1, 1, 167, 17, 0, // Skip to: 13015
+/* 8496 */    MCD_OPC_Decode, 163, 4, 30, // Opcode: JZ_A_brr
+/* 8500 */    MCD_OPC_FilterValue, 1, 158, 17, 0, // Skip to: 13015
+/* 8505 */    MCD_OPC_CheckField, 7, 1, 1, 151, 17, 0, // Skip to: 13015
+/* 8512 */    MCD_OPC_Decode, 154, 4, 30, // Opcode: JNZ_A_brr
+/* 8516 */    MCD_OPC_FilterValue, 63, 55, 0, 0, // Skip to: 8576
+/* 8521 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8524 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 8550
+/* 8529 */    MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 8532 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8541
+/* 8537 */    MCD_OPC_Decode, 139, 4, 30, // Opcode: JLT_brr
+/* 8541 */    MCD_OPC_FilterValue, 1, 117, 17, 0, // Skip to: 13015
+/* 8546 */    MCD_OPC_Decode, 137, 4, 30, // Opcode: JLT_U_brr
+/* 8550 */    MCD_OPC_FilterValue, 1, 108, 17, 0, // Skip to: 13015
+/* 8555 */    MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 8558 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8567
+/* 8563 */    MCD_OPC_Decode, 138, 4, 31, // Opcode: JLT_brc
+/* 8567 */    MCD_OPC_FilterValue, 1, 91, 17, 0, // Skip to: 13015
+/* 8572 */    MCD_OPC_Decode, 136, 4, 31, // Opcode: JLT_U_brc
+/* 8576 */    MCD_OPC_FilterValue, 67, 213, 3, 0, // Skip to: 9562
+/* 8581 */    MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 8584 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8605
+/* 8589 */    MCD_OPC_CheckPredicate, 1, 69, 17, 0, // Skip to: 13015
+/* 8594 */    MCD_OPC_CheckField, 7, 1, 0, 62, 17, 0, // Skip to: 13015
+/* 8601 */    MCD_OPC_Decode, 142, 6, 16, // Opcode: MADD_Q_rrr1_U
+/* 8605 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 8626
+/* 8610 */    MCD_OPC_CheckPredicate, 1, 48, 17, 0, // Skip to: 13015
+/* 8615 */    MCD_OPC_CheckField, 7, 1, 0, 41, 17, 0, // Skip to: 13015
+/* 8622 */    MCD_OPC_Decode, 140, 6, 16, // Opcode: MADD_Q_rrr1_L
+/* 8626 */    MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 8647
+/* 8631 */    MCD_OPC_CheckPredicate, 1, 27, 17, 0, // Skip to: 13015
+/* 8636 */    MCD_OPC_CheckField, 7, 1, 0, 20, 17, 0, // Skip to: 13015
+/* 8643 */    MCD_OPC_Decode, 139, 6, 16, // Opcode: MADD_Q_rrr1
+/* 8647 */    MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 8668
+/* 8652 */    MCD_OPC_CheckPredicate, 1, 6, 17, 0, // Skip to: 13015
+/* 8657 */    MCD_OPC_CheckField, 7, 1, 0, 255, 16, 0, // Skip to: 13015
+/* 8664 */    MCD_OPC_Decode, 144, 6, 16, // Opcode: MADD_Q_rrr1_U_U
+/* 8668 */    MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 8689
+/* 8673 */    MCD_OPC_CheckPredicate, 1, 241, 16, 0, // Skip to: 13015
+/* 8678 */    MCD_OPC_CheckField, 7, 1, 0, 234, 16, 0, // Skip to: 13015
+/* 8685 */    MCD_OPC_Decode, 141, 6, 16, // Opcode: MADD_Q_rrr1_L_L
+/* 8689 */    MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 8710
+/* 8694 */    MCD_OPC_CheckPredicate, 1, 220, 16, 0, // Skip to: 13015
+/* 8699 */    MCD_OPC_CheckField, 7, 1, 0, 213, 16, 0, // Skip to: 13015
+/* 8706 */    MCD_OPC_Decode, 211, 5, 16, // Opcode: MADDR_Q_rrr1_U_U
+/* 8710 */    MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 8731
+/* 8715 */    MCD_OPC_CheckPredicate, 1, 199, 16, 0, // Skip to: 13015
+/* 8720 */    MCD_OPC_CheckField, 7, 1, 0, 192, 16, 0, // Skip to: 13015
+/* 8727 */    MCD_OPC_Decode, 210, 5, 16, // Opcode: MADDR_Q_rrr1_L_L
+/* 8731 */    MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 8752
+/* 8736 */    MCD_OPC_CheckPredicate, 1, 178, 16, 0, // Skip to: 13015
+/* 8741 */    MCD_OPC_CheckField, 7, 1, 1, 171, 16, 0, // Skip to: 13015
+/* 8748 */    MCD_OPC_Decode, 227, 5, 16, // Opcode: MADDSUR_H_rrr1_UL
+/* 8752 */    MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 8773
+/* 8757 */    MCD_OPC_CheckPredicate, 1, 157, 16, 0, // Skip to: 13015
+/* 8762 */    MCD_OPC_CheckField, 7, 1, 1, 150, 16, 0, // Skip to: 13015
+/* 8769 */    MCD_OPC_Decode, 226, 5, 16, // Opcode: MADDSUR_H_rrr1_LU
+/* 8773 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 8794
+/* 8778 */    MCD_OPC_CheckPredicate, 1, 136, 16, 0, // Skip to: 13015
+/* 8783 */    MCD_OPC_CheckField, 7, 1, 1, 129, 16, 0, // Skip to: 13015
+/* 8790 */    MCD_OPC_Decode, 225, 5, 16, // Opcode: MADDSUR_H_rrr1_LL
+/* 8794 */    MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 8815
+/* 8799 */    MCD_OPC_CheckPredicate, 1, 115, 16, 0, // Skip to: 13015
+/* 8804 */    MCD_OPC_CheckField, 7, 1, 1, 108, 16, 0, // Skip to: 13015
+/* 8811 */    MCD_OPC_Decode, 228, 5, 16, // Opcode: MADDSUR_H_rrr1_UU
+/* 8815 */    MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 8851
+/* 8820 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8823 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8837
+/* 8828 */    MCD_OPC_CheckPredicate, 1, 86, 16, 0, // Skip to: 13015
+/* 8833 */    MCD_OPC_Decode, 148, 6, 16, // Opcode: MADD_Q_rrr1_e_U
+/* 8837 */    MCD_OPC_FilterValue, 1, 77, 16, 0, // Skip to: 13015
+/* 8842 */    MCD_OPC_CheckPredicate, 1, 72, 16, 0, // Skip to: 13015
+/* 8847 */    MCD_OPC_Decode, 235, 5, 16, // Opcode: MADDSU_H_rrr1_UL
+/* 8851 */    MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 8887
+/* 8856 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8859 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8873
+/* 8864 */    MCD_OPC_CheckPredicate, 1, 50, 16, 0, // Skip to: 13015
+/* 8869 */    MCD_OPC_Decode, 146, 6, 16, // Opcode: MADD_Q_rrr1_e_L
+/* 8873 */    MCD_OPC_FilterValue, 1, 41, 16, 0, // Skip to: 13015
+/* 8878 */    MCD_OPC_CheckPredicate, 1, 36, 16, 0, // Skip to: 13015
+/* 8883 */    MCD_OPC_Decode, 234, 5, 16, // Opcode: MADDSU_H_rrr1_LU
+/* 8887 */    MCD_OPC_FilterValue, 26, 16, 0, 0, // Skip to: 8908
+/* 8892 */    MCD_OPC_CheckPredicate, 1, 22, 16, 0, // Skip to: 13015
+/* 8897 */    MCD_OPC_CheckField, 7, 1, 1, 15, 16, 0, // Skip to: 13015
+/* 8904 */    MCD_OPC_Decode, 233, 5, 16, // Opcode: MADDSU_H_rrr1_LL
+/* 8908 */    MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 8944
+/* 8913 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8916 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8930
+/* 8921 */    MCD_OPC_CheckPredicate, 1, 249, 15, 0, // Skip to: 13015
+/* 8926 */    MCD_OPC_Decode, 145, 6, 16, // Opcode: MADD_Q_rrr1_e
+/* 8930 */    MCD_OPC_FilterValue, 1, 240, 15, 0, // Skip to: 13015
+/* 8935 */    MCD_OPC_CheckPredicate, 1, 235, 15, 0, // Skip to: 13015
+/* 8940 */    MCD_OPC_Decode, 236, 5, 16, // Opcode: MADDSU_H_rrr1_UU
+/* 8944 */    MCD_OPC_FilterValue, 28, 31, 0, 0, // Skip to: 8980
+/* 8949 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8952 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8966
+/* 8957 */    MCD_OPC_CheckPredicate, 1, 213, 15, 0, // Skip to: 13015
+/* 8962 */    MCD_OPC_Decode, 149, 6, 16, // Opcode: MADD_Q_rrr1_e_U_U
+/* 8966 */    MCD_OPC_FilterValue, 1, 204, 15, 0, // Skip to: 13015
+/* 8971 */    MCD_OPC_CheckPredicate, 1, 199, 15, 0, // Skip to: 13015
+/* 8976 */    MCD_OPC_Decode, 219, 5, 16, // Opcode: MADDSUM_H_rrr1_UL
+/* 8980 */    MCD_OPC_FilterValue, 29, 31, 0, 0, // Skip to: 9016
+/* 8985 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8988 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9002
+/* 8993 */    MCD_OPC_CheckPredicate, 1, 177, 15, 0, // Skip to: 13015
+/* 8998 */    MCD_OPC_Decode, 147, 6, 16, // Opcode: MADD_Q_rrr1_e_L_L
+/* 9002 */    MCD_OPC_FilterValue, 1, 168, 15, 0, // Skip to: 13015
+/* 9007 */    MCD_OPC_CheckPredicate, 1, 163, 15, 0, // Skip to: 13015
+/* 9012 */    MCD_OPC_Decode, 218, 5, 16, // Opcode: MADDSUM_H_rrr1_LU
+/* 9016 */    MCD_OPC_FilterValue, 30, 31, 0, 0, // Skip to: 9052
+/* 9021 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9024 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9038
+/* 9029 */    MCD_OPC_CheckPredicate, 1, 141, 15, 0, // Skip to: 13015
+/* 9034 */    MCD_OPC_Decode, 207, 5, 16, // Opcode: MADDR_H_rrr1_UL_2
+/* 9038 */    MCD_OPC_FilterValue, 1, 132, 15, 0, // Skip to: 13015
+/* 9043 */    MCD_OPC_CheckPredicate, 1, 127, 15, 0, // Skip to: 13015
+/* 9048 */    MCD_OPC_Decode, 217, 5, 16, // Opcode: MADDSUM_H_rrr1_LL
+/* 9052 */    MCD_OPC_FilterValue, 31, 16, 0, 0, // Skip to: 9073
+/* 9057 */    MCD_OPC_CheckPredicate, 1, 113, 15, 0, // Skip to: 13015
+/* 9062 */    MCD_OPC_CheckField, 7, 1, 1, 106, 15, 0, // Skip to: 13015
+/* 9069 */    MCD_OPC_Decode, 220, 5, 16, // Opcode: MADDSUM_H_rrr1_UU
+/* 9073 */    MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 9094
+/* 9078 */    MCD_OPC_CheckPredicate, 1, 92, 15, 0, // Skip to: 13015
+/* 9083 */    MCD_OPC_CheckField, 7, 1, 0, 85, 15, 0, // Skip to: 13015
+/* 9090 */    MCD_OPC_Decode, 245, 5, 16, // Opcode: MADDS_Q_rrr1_U
+/* 9094 */    MCD_OPC_FilterValue, 33, 16, 0, 0, // Skip to: 9115
+/* 9099 */    MCD_OPC_CheckPredicate, 1, 71, 15, 0, // Skip to: 13015
+/* 9104 */    MCD_OPC_CheckField, 7, 1, 0, 64, 15, 0, // Skip to: 13015
+/* 9111 */    MCD_OPC_Decode, 243, 5, 16, // Opcode: MADDS_Q_rrr1_L
+/* 9115 */    MCD_OPC_FilterValue, 34, 16, 0, 0, // Skip to: 9136
+/* 9120 */    MCD_OPC_CheckPredicate, 1, 50, 15, 0, // Skip to: 13015
+/* 9125 */    MCD_OPC_CheckField, 7, 1, 0, 43, 15, 0, // Skip to: 13015
+/* 9132 */    MCD_OPC_Decode, 242, 5, 16, // Opcode: MADDS_Q_rrr1
+/* 9136 */    MCD_OPC_FilterValue, 36, 16, 0, 0, // Skip to: 9157
+/* 9141 */    MCD_OPC_CheckPredicate, 1, 29, 15, 0, // Skip to: 13015
+/* 9146 */    MCD_OPC_CheckField, 7, 1, 0, 22, 15, 0, // Skip to: 13015
+/* 9153 */    MCD_OPC_Decode, 247, 5, 16, // Opcode: MADDS_Q_rrr1_U_U
+/* 9157 */    MCD_OPC_FilterValue, 37, 16, 0, 0, // Skip to: 9178
+/* 9162 */    MCD_OPC_CheckPredicate, 1, 8, 15, 0, // Skip to: 13015
+/* 9167 */    MCD_OPC_CheckField, 7, 1, 0, 1, 15, 0, // Skip to: 13015
+/* 9174 */    MCD_OPC_Decode, 244, 5, 16, // Opcode: MADDS_Q_rrr1_L_L
+/* 9178 */    MCD_OPC_FilterValue, 38, 16, 0, 0, // Skip to: 9199
+/* 9183 */    MCD_OPC_CheckPredicate, 1, 243, 14, 0, // Skip to: 13015
+/* 9188 */    MCD_OPC_CheckField, 7, 1, 0, 236, 14, 0, // Skip to: 13015
+/* 9195 */    MCD_OPC_Decode, 202, 5, 16, // Opcode: MADDRS_Q_rrr1_U_U
+/* 9199 */    MCD_OPC_FilterValue, 39, 16, 0, 0, // Skip to: 9220
+/* 9204 */    MCD_OPC_CheckPredicate, 1, 222, 14, 0, // Skip to: 13015
+/* 9209 */    MCD_OPC_CheckField, 7, 1, 0, 215, 14, 0, // Skip to: 13015
+/* 9216 */    MCD_OPC_Decode, 201, 5, 16, // Opcode: MADDRS_Q_rrr1_L_L
+/* 9220 */    MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 9241
+/* 9225 */    MCD_OPC_CheckPredicate, 1, 201, 14, 0, // Skip to: 13015
+/* 9230 */    MCD_OPC_CheckField, 7, 1, 1, 194, 14, 0, // Skip to: 13015
+/* 9237 */    MCD_OPC_Decode, 223, 5, 16, // Opcode: MADDSURS_H_rrr1_UL
+/* 9241 */    MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 9262
+/* 9246 */    MCD_OPC_CheckPredicate, 1, 180, 14, 0, // Skip to: 13015
+/* 9251 */    MCD_OPC_CheckField, 7, 1, 1, 173, 14, 0, // Skip to: 13015
+/* 9258 */    MCD_OPC_Decode, 222, 5, 16, // Opcode: MADDSURS_H_rrr1_LU
+/* 9262 */    MCD_OPC_FilterValue, 46, 16, 0, 0, // Skip to: 9283
+/* 9267 */    MCD_OPC_CheckPredicate, 1, 159, 14, 0, // Skip to: 13015
+/* 9272 */    MCD_OPC_CheckField, 7, 1, 1, 152, 14, 0, // Skip to: 13015
+/* 9279 */    MCD_OPC_Decode, 221, 5, 16, // Opcode: MADDSURS_H_rrr1_LL
+/* 9283 */    MCD_OPC_FilterValue, 47, 16, 0, 0, // Skip to: 9304
+/* 9288 */    MCD_OPC_CheckPredicate, 1, 138, 14, 0, // Skip to: 13015
+/* 9293 */    MCD_OPC_CheckField, 7, 1, 1, 131, 14, 0, // Skip to: 13015
+/* 9300 */    MCD_OPC_Decode, 224, 5, 16, // Opcode: MADDSURS_H_rrr1_UU
+/* 9304 */    MCD_OPC_FilterValue, 56, 31, 0, 0, // Skip to: 9340
+/* 9309 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9312 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9326
+/* 9317 */    MCD_OPC_CheckPredicate, 1, 109, 14, 0, // Skip to: 13015
+/* 9322 */    MCD_OPC_Decode, 251, 5, 16, // Opcode: MADDS_Q_rrr1_e_U
+/* 9326 */    MCD_OPC_FilterValue, 1, 100, 14, 0, // Skip to: 13015
+/* 9331 */    MCD_OPC_CheckPredicate, 1, 95, 14, 0, // Skip to: 13015
+/* 9336 */    MCD_OPC_Decode, 231, 5, 16, // Opcode: MADDSUS_H_rrr1_UL
+/* 9340 */    MCD_OPC_FilterValue, 57, 31, 0, 0, // Skip to: 9376
+/* 9345 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9348 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9362
+/* 9353 */    MCD_OPC_CheckPredicate, 1, 73, 14, 0, // Skip to: 13015
+/* 9358 */    MCD_OPC_Decode, 249, 5, 16, // Opcode: MADDS_Q_rrr1_e_L
+/* 9362 */    MCD_OPC_FilterValue, 1, 64, 14, 0, // Skip to: 13015
+/* 9367 */    MCD_OPC_CheckPredicate, 1, 59, 14, 0, // Skip to: 13015
+/* 9372 */    MCD_OPC_Decode, 230, 5, 16, // Opcode: MADDSUS_H_rrr1_LU
+/* 9376 */    MCD_OPC_FilterValue, 58, 16, 0, 0, // Skip to: 9397
+/* 9381 */    MCD_OPC_CheckPredicate, 1, 45, 14, 0, // Skip to: 13015
+/* 9386 */    MCD_OPC_CheckField, 7, 1, 1, 38, 14, 0, // Skip to: 13015
+/* 9393 */    MCD_OPC_Decode, 229, 5, 16, // Opcode: MADDSUS_H_rrr1_LL
+/* 9397 */    MCD_OPC_FilterValue, 59, 31, 0, 0, // Skip to: 9433
+/* 9402 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9405 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9419
+/* 9410 */    MCD_OPC_CheckPredicate, 1, 16, 14, 0, // Skip to: 13015
+/* 9415 */    MCD_OPC_Decode, 248, 5, 16, // Opcode: MADDS_Q_rrr1_e
+/* 9419 */    MCD_OPC_FilterValue, 1, 7, 14, 0, // Skip to: 13015
+/* 9424 */    MCD_OPC_CheckPredicate, 1, 2, 14, 0, // Skip to: 13015
+/* 9429 */    MCD_OPC_Decode, 232, 5, 16, // Opcode: MADDSUS_H_rrr1_UU
+/* 9433 */    MCD_OPC_FilterValue, 60, 31, 0, 0, // Skip to: 9469
+/* 9438 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9441 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9455
+/* 9446 */    MCD_OPC_CheckPredicate, 1, 236, 13, 0, // Skip to: 13015
+/* 9451 */    MCD_OPC_Decode, 252, 5, 16, // Opcode: MADDS_Q_rrr1_e_U_U
+/* 9455 */    MCD_OPC_FilterValue, 1, 227, 13, 0, // Skip to: 13015
+/* 9460 */    MCD_OPC_CheckPredicate, 1, 222, 13, 0, // Skip to: 13015
+/* 9465 */    MCD_OPC_Decode, 215, 5, 16, // Opcode: MADDSUMS_H_rrr1_UL
+/* 9469 */    MCD_OPC_FilterValue, 61, 31, 0, 0, // Skip to: 9505
+/* 9474 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9477 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9491
+/* 9482 */    MCD_OPC_CheckPredicate, 1, 200, 13, 0, // Skip to: 13015
+/* 9487 */    MCD_OPC_Decode, 250, 5, 16, // Opcode: MADDS_Q_rrr1_e_L_L
+/* 9491 */    MCD_OPC_FilterValue, 1, 191, 13, 0, // Skip to: 13015
+/* 9496 */    MCD_OPC_CheckPredicate, 1, 186, 13, 0, // Skip to: 13015
+/* 9501 */    MCD_OPC_Decode, 214, 5, 16, // Opcode: MADDSUMS_H_rrr1_LU
+/* 9505 */    MCD_OPC_FilterValue, 62, 31, 0, 0, // Skip to: 9541
+/* 9510 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9513 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9527
+/* 9518 */    MCD_OPC_CheckPredicate, 1, 164, 13, 0, // Skip to: 13015
+/* 9523 */    MCD_OPC_Decode, 198, 5, 16, // Opcode: MADDRS_H_rrr1_UL_2
+/* 9527 */    MCD_OPC_FilterValue, 1, 155, 13, 0, // Skip to: 13015
+/* 9532 */    MCD_OPC_CheckPredicate, 1, 150, 13, 0, // Skip to: 13015
+/* 9537 */    MCD_OPC_Decode, 213, 5, 16, // Opcode: MADDSUMS_H_rrr1_LL
+/* 9541 */    MCD_OPC_FilterValue, 63, 141, 13, 0, // Skip to: 13015
+/* 9546 */    MCD_OPC_CheckPredicate, 1, 136, 13, 0, // Skip to: 13015
+/* 9551 */    MCD_OPC_CheckField, 7, 1, 1, 129, 13, 0, // Skip to: 13015
+/* 9558 */    MCD_OPC_Decode, 216, 5, 16, // Opcode: MADDSUMS_H_rrr1_UU
+/* 9562 */    MCD_OPC_FilterValue, 69, 50, 0, 0, // Skip to: 9617
+/* 9567 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9570 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9586
+/* 9575 */    MCD_OPC_CheckField, 26, 2, 0, 105, 13, 0, // Skip to: 13015
+/* 9582 */    MCD_OPC_Decode, 133, 5, 17, // Opcode: LD_Q_abs
+/* 9586 */    MCD_OPC_FilterValue, 1, 96, 13, 0, // Skip to: 13015
+/* 9591 */    MCD_OPC_ExtractField, 26, 2,  // Inst{27-26} ...
+/* 9594 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9603
+/* 9599 */    MCD_OPC_Decode, 155, 5, 17, // Opcode: LEA_abs
+/* 9603 */    MCD_OPC_FilterValue, 1, 79, 13, 0, // Skip to: 13015
+/* 9608 */    MCD_OPC_CheckPredicate, 6, 74, 13, 0, // Skip to: 13015
+/* 9613 */    MCD_OPC_Decode, 158, 5, 17, // Opcode: LHA_abs
+/* 9617 */    MCD_OPC_FilterValue, 71, 107, 0, 0, // Skip to: 9729
+/* 9622 */    MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
+/* 9625 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 9651
+/* 9630 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9633 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9642
+/* 9638 */    MCD_OPC_Decode, 177, 2, 18, // Opcode: AND_AND_T
+/* 9642 */    MCD_OPC_FilterValue, 1, 40, 13, 0, // Skip to: 13015
+/* 9647 */    MCD_OPC_Decode, 247, 7, 18, // Opcode: OR_AND_T
+/* 9651 */    MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 9677
+/* 9656 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9659 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9668
+/* 9664 */    MCD_OPC_Decode, 191, 2, 18, // Opcode: AND_OR_T
+/* 9668 */    MCD_OPC_FilterValue, 1, 14, 13, 0, // Skip to: 13015
+/* 9673 */    MCD_OPC_Decode, 133, 8, 18, // Opcode: OR_OR_T
+/* 9677 */    MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 9703
+/* 9682 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9685 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9694
+/* 9690 */    MCD_OPC_Decode, 190, 2, 18, // Opcode: AND_NOR_T
+/* 9694 */    MCD_OPC_FilterValue, 1, 244, 12, 0, // Skip to: 13015
+/* 9699 */    MCD_OPC_Decode, 132, 8, 18, // Opcode: OR_NOR_T
+/* 9703 */    MCD_OPC_FilterValue, 3, 235, 12, 0, // Skip to: 13015
+/* 9708 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9711 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9720
+/* 9716 */    MCD_OPC_Decode, 176, 2, 18, // Opcode: AND_ANDN_T
+/* 9720 */    MCD_OPC_FilterValue, 1, 218, 12, 0, // Skip to: 13015
+/* 9725 */    MCD_OPC_Decode, 246, 7, 18, // Opcode: OR_ANDN_T
+/* 9729 */    MCD_OPC_FilterValue, 73, 208, 0, 0, // Skip to: 9942
+/* 9734 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9737 */    MCD_OPC_FilterValue, 0, 186, 0, 0, // Skip to: 9928
+/* 9742 */    MCD_OPC_ExtractField, 22, 6,  // Inst{27-22} ...
+/* 9745 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9754
+/* 9750 */    MCD_OPC_Decode, 215, 9, 19, // Opcode: SWAP_W_bo_pos
+/* 9754 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9763
+/* 9759 */    MCD_OPC_Decode, 180, 4, 19, // Opcode: LDMST_bo_pos
+/* 9763 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9777
+/* 9768 */    MCD_OPC_CheckPredicate, 5, 170, 12, 0, // Skip to: 13015
+/* 9773 */    MCD_OPC_Decode, 202, 9, 19, // Opcode: SWAPMSK_W_bo_pos
+/* 9777 */    MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 9791
+/* 9782 */    MCD_OPC_CheckPredicate, 5, 156, 12, 0, // Skip to: 13015
+/* 9787 */    MCD_OPC_Decode, 135, 3, 19, // Opcode: CMPSWAP_W_bo_pos
+/* 9791 */    MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 9800
+/* 9796 */    MCD_OPC_Decode, 216, 9, 19, // Opcode: SWAP_W_bo_pre
+/* 9800 */    MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 9809
+/* 9805 */    MCD_OPC_Decode, 181, 4, 19, // Opcode: LDMST_bo_pre
+/* 9809 */    MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 9823
+/* 9814 */    MCD_OPC_CheckPredicate, 5, 124, 12, 0, // Skip to: 13015
+/* 9819 */    MCD_OPC_Decode, 203, 9, 19, // Opcode: SWAPMSK_W_bo_pre
+/* 9823 */    MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 9837
+/* 9828 */    MCD_OPC_CheckPredicate, 5, 110, 12, 0, // Skip to: 13015
+/* 9833 */    MCD_OPC_Decode, 136, 3, 19, // Opcode: CMPSWAP_W_bo_pre
+/* 9837 */    MCD_OPC_FilterValue, 32, 4, 0, 0, // Skip to: 9846
+/* 9842 */    MCD_OPC_Decode, 212, 9, 19, // Opcode: SWAP_W_bo_bso
+/* 9846 */    MCD_OPC_FilterValue, 33, 4, 0, 0, // Skip to: 9855
+/* 9851 */    MCD_OPC_Decode, 178, 4, 19, // Opcode: LDMST_bo_bso
+/* 9855 */    MCD_OPC_FilterValue, 34, 9, 0, 0, // Skip to: 9869
+/* 9860 */    MCD_OPC_CheckPredicate, 5, 78, 12, 0, // Skip to: 13015
+/* 9865 */    MCD_OPC_Decode, 199, 9, 19, // Opcode: SWAPMSK_W_bo_bso
+/* 9869 */    MCD_OPC_FilterValue, 35, 9, 0, 0, // Skip to: 9883
+/* 9874 */    MCD_OPC_CheckPredicate, 5, 64, 12, 0, // Skip to: 13015
+/* 9879 */    MCD_OPC_Decode, 133, 3, 19, // Opcode: CMPSWAP_W_bo_bso
+/* 9883 */    MCD_OPC_FilterValue, 36, 4, 0, 0, // Skip to: 9892
+/* 9888 */    MCD_OPC_Decode, 176, 4, 19, // Opcode: LDLCX_bo_bso
+/* 9892 */    MCD_OPC_FilterValue, 37, 4, 0, 0, // Skip to: 9901
+/* 9897 */    MCD_OPC_Decode, 184, 4, 19, // Opcode: LDUCX_bo_bso
+/* 9901 */    MCD_OPC_FilterValue, 38, 4, 0, 0, // Skip to: 9910
+/* 9906 */    MCD_OPC_Decode, 222, 8, 19, // Opcode: STLCX_bo_bso
+/* 9910 */    MCD_OPC_FilterValue, 39, 4, 0, 0, // Skip to: 9919
+/* 9915 */    MCD_OPC_Decode, 224, 8, 19, // Opcode: STUCX_bo_bso
+/* 9919 */    MCD_OPC_FilterValue, 40, 19, 12, 0, // Skip to: 13015
+/* 9924 */    MCD_OPC_Decode, 156, 5, 19, // Opcode: LEA_bo_bso
+/* 9928 */    MCD_OPC_FilterValue, 1, 10, 12, 0, // Skip to: 13015
+/* 9933 */    MCD_OPC_CheckPredicate, 0, 5, 12, 0, // Skip to: 13015
+/* 9938 */    MCD_OPC_Decode, 252, 4, 28, // Opcode: LD_H_bol
+/* 9942 */    MCD_OPC_FilterValue, 75, 150, 2, 0, // Skip to: 10609
+/* 9947 */    MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 9950 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9971
+/* 9955 */    MCD_OPC_CheckPredicate, 2, 239, 11, 0, // Skip to: 13015
+/* 9960 */    MCD_OPC_CheckField, 7, 1, 0, 232, 11, 0, // Skip to: 13015
+/* 9967 */    MCD_OPC_Decode, 138, 3, 14, // Opcode: CMP_F_rr
+/* 9971 */    MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 9992
+/* 9976 */    MCD_OPC_CheckPredicate, 1, 218, 11, 0, // Skip to: 13015
+/* 9981 */    MCD_OPC_CheckField, 7, 1, 0, 211, 11, 0, // Skip to: 13015
+/* 9988 */    MCD_OPC_Decode, 204, 2, 14, // Opcode: BMERGE_rr
+/* 9992 */    MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 10013
+/* 9997 */    MCD_OPC_CheckPredicate, 1, 197, 11, 0, // Skip to: 13015
+/* 10002 */   MCD_OPC_CheckField, 7, 1, 0, 190, 11, 0, // Skip to: 13015
+/* 10009 */   MCD_OPC_Decode, 142, 8, 14, // Opcode: PARITY_rr
+/* 10013 */   MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 10034
+/* 10018 */   MCD_OPC_CheckPredicate, 6, 176, 11, 0, // Skip to: 13015
+/* 10023 */   MCD_OPC_CheckField, 7, 1, 0, 169, 11, 0, // Skip to: 13015
+/* 10030 */   MCD_OPC_Decode, 139, 3, 14, // Opcode: CRC32B_W_rr
+/* 10034 */   MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 10055
+/* 10039 */   MCD_OPC_CheckPredicate, 2, 155, 11, 0, // Skip to: 13015
+/* 10044 */   MCD_OPC_CheckField, 7, 1, 0, 148, 11, 0, // Skip to: 13015
+/* 10051 */   MCD_OPC_Decode, 205, 7, 14, // Opcode: MUL_F_rrr
+/* 10055 */   MCD_OPC_FilterValue, 20, 16, 0, 0, // Skip to: 10076
+/* 10060 */   MCD_OPC_CheckPredicate, 2, 134, 11, 0, // Skip to: 13015
+/* 10065 */   MCD_OPC_CheckField, 7, 1, 0, 127, 11, 0, // Skip to: 13015
+/* 10072 */   MCD_OPC_Decode, 154, 3, 14, // Opcode: DIV_F_rr
+/* 10076 */   MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 10097
+/* 10081 */   MCD_OPC_CheckPredicate, 6, 113, 11, 0, // Skip to: 13015
+/* 10086 */   MCD_OPC_CheckField, 7, 1, 0, 106, 11, 0, // Skip to: 13015
+/* 10093 */   MCD_OPC_Decode, 141, 3, 14, // Opcode: CRC32_B_rr
+/* 10097 */   MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 10118
+/* 10102 */   MCD_OPC_CheckPredicate, 6, 92, 11, 0, // Skip to: 13015
+/* 10107 */   MCD_OPC_CheckField, 7, 1, 0, 85, 11, 0, // Skip to: 13015
+/* 10114 */   MCD_OPC_Decode, 140, 3, 14, // Opcode: CRC32L_W_rr
+/* 10118 */   MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 10139
+/* 10123 */   MCD_OPC_CheckPredicate, 1, 71, 11, 0, // Skip to: 13015
+/* 10128 */   MCD_OPC_CheckField, 7, 1, 0, 64, 11, 0, // Skip to: 13015
+/* 10135 */   MCD_OPC_Decode, 227, 9, 14, // Opcode: UNPACK_rr_rr
+/* 10139 */   MCD_OPC_FilterValue, 36, 16, 0, 0, // Skip to: 10160
+/* 10144 */   MCD_OPC_CheckPredicate, 1, 50, 11, 0, // Skip to: 13015
+/* 10149 */   MCD_OPC_CheckField, 7, 1, 0, 43, 11, 0, // Skip to: 13015
+/* 10156 */   MCD_OPC_Decode, 205, 2, 14, // Opcode: BSPLIT_rr
+/* 10160 */   MCD_OPC_FilterValue, 40, 16, 0, 0, // Skip to: 10181
+/* 10165 */   MCD_OPC_CheckPredicate, 1, 29, 11, 0, // Skip to: 13015
+/* 10170 */   MCD_OPC_CheckField, 7, 1, 0, 22, 11, 0, // Skip to: 13015
+/* 10177 */   MCD_OPC_Decode, 169, 3, 14, // Opcode: DVINIT_U_rr
+/* 10181 */   MCD_OPC_FilterValue, 48, 16, 0, 0, // Skip to: 10202
+/* 10186 */   MCD_OPC_CheckPredicate, 2, 8, 11, 0, // Skip to: 13015
+/* 10191 */   MCD_OPC_CheckField, 7, 1, 0, 1, 11, 0, // Skip to: 13015
+/* 10198 */   MCD_OPC_Decode, 229, 9, 14, // Opcode: UPDFL_rr
+/* 10202 */   MCD_OPC_FilterValue, 64, 16, 0, 0, // Skip to: 10223
+/* 10207 */   MCD_OPC_CheckPredicate, 2, 243, 10, 0, // Skip to: 13015
+/* 10212 */   MCD_OPC_CheckField, 7, 1, 0, 236, 10, 0, // Skip to: 13015
+/* 10219 */   MCD_OPC_Decode, 206, 3, 14, // Opcode: FTOI_rr
+/* 10223 */   MCD_OPC_FilterValue, 68, 16, 0, 0, // Skip to: 10244
+/* 10228 */   MCD_OPC_CheckPredicate, 2, 222, 10, 0, // Skip to: 13015
+/* 10233 */   MCD_OPC_CheckField, 7, 1, 0, 215, 10, 0, // Skip to: 13015
+/* 10240 */   MCD_OPC_Decode, 208, 3, 14, // Opcode: FTOQ31_rr
+/* 10244 */   MCD_OPC_FilterValue, 72, 16, 0, 0, // Skip to: 10265
+/* 10249 */   MCD_OPC_CheckPredicate, 2, 201, 10, 0, // Skip to: 13015
+/* 10254 */   MCD_OPC_CheckField, 7, 1, 0, 194, 10, 0, // Skip to: 13015
+/* 10261 */   MCD_OPC_Decode, 210, 3, 14, // Opcode: FTOU_rr
+/* 10265 */   MCD_OPC_FilterValue, 76, 16, 0, 0, // Skip to: 10286
+/* 10270 */   MCD_OPC_CheckPredicate, 3, 180, 10, 0, // Skip to: 13015
+/* 10275 */   MCD_OPC_CheckField, 7, 1, 0, 173, 10, 0, // Skip to: 13015
+/* 10282 */   MCD_OPC_Decode, 205, 3, 14, // Opcode: FTOIZ_rr
+/* 10286 */   MCD_OPC_FilterValue, 80, 16, 0, 0, // Skip to: 10307
+/* 10291 */   MCD_OPC_CheckPredicate, 2, 159, 10, 0, // Skip to: 13015
+/* 10296 */   MCD_OPC_CheckField, 7, 1, 0, 152, 10, 0, // Skip to: 13015
+/* 10303 */   MCD_OPC_Decode, 230, 3, 14, // Opcode: ITOF_rr
+/* 10307 */   MCD_OPC_FilterValue, 84, 16, 0, 0, // Skip to: 10328
+/* 10312 */   MCD_OPC_CheckPredicate, 2, 138, 10, 0, // Skip to: 13015
+/* 10317 */   MCD_OPC_CheckField, 7, 1, 0, 131, 10, 0, // Skip to: 13015
+/* 10324 */   MCD_OPC_Decode, 145, 8, 14, // Opcode: Q31TOF_rr
+/* 10328 */   MCD_OPC_FilterValue, 88, 16, 0, 0, // Skip to: 10349
+/* 10333 */   MCD_OPC_CheckPredicate, 2, 117, 10, 0, // Skip to: 13015
+/* 10338 */   MCD_OPC_CheckField, 7, 1, 0, 110, 10, 0, // Skip to: 13015
+/* 10345 */   MCD_OPC_Decode, 230, 9, 14, // Opcode: UTOF_rr
+/* 10349 */   MCD_OPC_FilterValue, 92, 16, 0, 0, // Skip to: 10370
+/* 10354 */   MCD_OPC_CheckPredicate, 3, 96, 10, 0, // Skip to: 13015
+/* 10359 */   MCD_OPC_CheckField, 7, 1, 0, 89, 10, 0, // Skip to: 13015
+/* 10366 */   MCD_OPC_Decode, 209, 3, 14, // Opcode: FTOUZ_rr
+/* 10370 */   MCD_OPC_FilterValue, 96, 16, 0, 0, // Skip to: 10391
+/* 10375 */   MCD_OPC_CheckPredicate, 3, 75, 10, 0, // Skip to: 13015
+/* 10380 */   MCD_OPC_CheckField, 7, 1, 0, 68, 10, 0, // Skip to: 13015
+/* 10387 */   MCD_OPC_Decode, 207, 3, 14, // Opcode: FTOQ31Z_rr
+/* 10391 */   MCD_OPC_FilterValue, 100, 16, 0, 0, // Skip to: 10412
+/* 10396 */   MCD_OPC_CheckPredicate, 2, 54, 10, 0, // Skip to: 13015
+/* 10401 */   MCD_OPC_CheckField, 7, 1, 0, 47, 10, 0, // Skip to: 13015
+/* 10408 */   MCD_OPC_Decode, 146, 8, 14, // Opcode: QSEED_F_rr
+/* 10412 */   MCD_OPC_FilterValue, 104, 16, 0, 0, // Skip to: 10433
+/* 10417 */   MCD_OPC_CheckPredicate, 1, 33, 10, 0, // Skip to: 13015
+/* 10422 */   MCD_OPC_CheckField, 7, 1, 0, 26, 10, 0, // Skip to: 13015
+/* 10429 */   MCD_OPC_Decode, 171, 3, 14, // Opcode: DVINIT_rr
+/* 10433 */   MCD_OPC_FilterValue, 128, 1, 16, 0, 0, // Skip to: 10455
+/* 10439 */   MCD_OPC_CheckPredicate, 0, 11, 10, 0, // Skip to: 13015
+/* 10444 */   MCD_OPC_CheckField, 7, 1, 0, 4, 10, 0, // Skip to: 13015
+/* 10451 */   MCD_OPC_Decode, 156, 3, 14, // Opcode: DIV_rr
+/* 10455 */   MCD_OPC_FilterValue, 132, 1, 16, 0, 0, // Skip to: 10477
+/* 10461 */   MCD_OPC_CheckPredicate, 0, 245, 9, 0, // Skip to: 13015
+/* 10466 */   MCD_OPC_CheckField, 7, 1, 0, 238, 9, 0, // Skip to: 13015
+/* 10473 */   MCD_OPC_Decode, 155, 3, 14, // Opcode: DIV_U_rr
+/* 10477 */   MCD_OPC_FilterValue, 144, 1, 16, 0, 0, // Skip to: 10499
+/* 10483 */   MCD_OPC_CheckPredicate, 6, 223, 9, 0, // Skip to: 13015
+/* 10488 */   MCD_OPC_CheckField, 7, 1, 0, 216, 9, 0, // Skip to: 13015
+/* 10495 */   MCD_OPC_Decode, 216, 3, 14, // Opcode: HPTOF_rr
+/* 10499 */   MCD_OPC_FilterValue, 148, 1, 16, 0, 0, // Skip to: 10521
+/* 10505 */   MCD_OPC_CheckPredicate, 6, 201, 9, 0, // Skip to: 13015
+/* 10510 */   MCD_OPC_CheckField, 7, 1, 0, 194, 9, 0, // Skip to: 13015
+/* 10517 */   MCD_OPC_Decode, 204, 3, 14, // Opcode: FTOHP_rr
+/* 10521 */   MCD_OPC_FilterValue, 168, 1, 16, 0, 0, // Skip to: 10543
+/* 10527 */   MCD_OPC_CheckPredicate, 1, 179, 9, 0, // Skip to: 13015
+/* 10532 */   MCD_OPC_CheckField, 7, 1, 0, 172, 9, 0, // Skip to: 13015
+/* 10539 */   MCD_OPC_Decode, 165, 3, 14, // Opcode: DVINIT_HU_rr
+/* 10543 */   MCD_OPC_FilterValue, 232, 1, 16, 0, 0, // Skip to: 10565
+/* 10549 */   MCD_OPC_CheckPredicate, 1, 157, 9, 0, // Skip to: 13015
+/* 10554 */   MCD_OPC_CheckField, 7, 1, 0, 150, 9, 0, // Skip to: 13015
+/* 10561 */   MCD_OPC_Decode, 167, 3, 14, // Opcode: DVINIT_H_rr
+/* 10565 */   MCD_OPC_FilterValue, 168, 2, 16, 0, 0, // Skip to: 10587
+/* 10571 */   MCD_OPC_CheckPredicate, 1, 135, 9, 0, // Skip to: 13015
+/* 10576 */   MCD_OPC_CheckField, 7, 1, 0, 128, 9, 0, // Skip to: 13015
+/* 10583 */   MCD_OPC_Decode, 161, 3, 14, // Opcode: DVINIT_BU_rr
+/* 10587 */   MCD_OPC_FilterValue, 232, 2, 118, 9, 0, // Skip to: 13015
+/* 10593 */   MCD_OPC_CheckPredicate, 1, 113, 9, 0, // Skip to: 13015
+/* 10598 */   MCD_OPC_CheckField, 7, 1, 0, 106, 9, 0, // Skip to: 13015
+/* 10605 */   MCD_OPC_Decode, 163, 3, 14, // Opcode: DVINIT_B_rr
+/* 10609 */   MCD_OPC_FilterValue, 77, 21, 0, 0, // Skip to: 10635
+/* 10614 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 10617 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10626
+/* 10622 */   MCD_OPC_Decode, 164, 6, 22, // Opcode: MFCR_rlc
+/* 10626 */   MCD_OPC_FilterValue, 1, 80, 9, 0, // Skip to: 13015
+/* 10631 */   MCD_OPC_Decode, 178, 7, 22, // Opcode: MTCR_rlc
+/* 10635 */   MCD_OPC_FilterValue, 83, 93, 0, 0, // Skip to: 10733
+/* 10640 */   MCD_OPC_ExtractField, 21, 7,  // Inst{27-21} ...
+/* 10643 */   MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 10659
+/* 10648 */   MCD_OPC_CheckField, 7, 1, 0, 56, 9, 0, // Skip to: 13015
+/* 10655 */   MCD_OPC_Decode, 222, 7, 20, // Opcode: MUL_rc
+/* 10659 */   MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 10680
+/* 10664 */   MCD_OPC_CheckPredicate, 1, 42, 9, 0, // Skip to: 13015
+/* 10669 */   MCD_OPC_CheckField, 7, 1, 0, 35, 9, 0, // Skip to: 13015
+/* 10676 */   MCD_OPC_Decode, 220, 7, 20, // Opcode: MUL_U_rc
+/* 10680 */   MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 10701
+/* 10685 */   MCD_OPC_CheckPredicate, 1, 21, 9, 0, // Skip to: 13015
+/* 10690 */   MCD_OPC_CheckField, 7, 1, 0, 14, 9, 0, // Skip to: 13015
+/* 10697 */   MCD_OPC_Decode, 223, 7, 20, // Opcode: MUL_rc_e
+/* 10701 */   MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 10717
+/* 10706 */   MCD_OPC_CheckField, 7, 1, 0, 254, 8, 0, // Skip to: 13015
+/* 10713 */   MCD_OPC_Decode, 199, 7, 20, // Opcode: MULS_U_rc
+/* 10717 */   MCD_OPC_FilterValue, 5, 245, 8, 0, // Skip to: 13015
+/* 10722 */   MCD_OPC_CheckField, 7, 1, 0, 238, 8, 0, // Skip to: 13015
+/* 10729 */   MCD_OPC_Decode, 202, 7, 20, // Opcode: MULS_rc
+/* 10733 */   MCD_OPC_FilterValue, 85, 18, 0, 0, // Skip to: 10756
+/* 10738 */   MCD_OPC_CheckField, 26, 2, 0, 222, 8, 0, // Skip to: 13015
+/* 10745 */   MCD_OPC_CheckField, 7, 1, 1, 215, 8, 0, // Skip to: 13015
+/* 10752 */   MCD_OPC_Decode, 161, 9, 35, // Opcode: ST_T
+/* 10756 */   MCD_OPC_FilterValue, 87, 87, 0, 0, // Skip to: 10848
+/* 10761 */   MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
+/* 10764 */   MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 10790
+/* 10769 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 10772 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10781
+/* 10777 */   MCD_OPC_Decode, 226, 3, 25, // Opcode: INSERT_rrrw
+/* 10781 */   MCD_OPC_FilterValue, 1, 181, 8, 0, // Skip to: 13015
+/* 10786 */   MCD_OPC_Decode, 223, 3, 36, // Opcode: INSERT_rcrw
+/* 10790 */   MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 10816
+/* 10795 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 10798 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10807
+/* 10803 */   MCD_OPC_Decode, 220, 3, 25, // Opcode: IMASK_rrrw
+/* 10807 */   MCD_OPC_FilterValue, 1, 155, 8, 0, // Skip to: 13015
+/* 10812 */   MCD_OPC_Decode, 218, 3, 36, // Opcode: IMASK_rcrw
+/* 10816 */   MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 10832
+/* 10821 */   MCD_OPC_CheckField, 7, 1, 0, 139, 8, 0, // Skip to: 13015
+/* 10828 */   MCD_OPC_Decode, 198, 3, 25, // Opcode: EXTR_rrrw
+/* 10832 */   MCD_OPC_FilterValue, 3, 130, 8, 0, // Skip to: 13015
+/* 10837 */   MCD_OPC_CheckField, 7, 1, 0, 123, 8, 0, // Skip to: 13015
+/* 10844 */   MCD_OPC_Decode, 195, 3, 25, // Opcode: EXTR_U_rrrw
+/* 10848 */   MCD_OPC_FilterValue, 89, 21, 0, 0, // Skip to: 10874
+/* 10853 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 10856 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10865
+/* 10861 */   MCD_OPC_Decode, 168, 9, 28, // Opcode: ST_W_bol
+/* 10865 */   MCD_OPC_FilterValue, 1, 97, 8, 0, // Skip to: 13015
+/* 10870 */   MCD_OPC_Decode, 157, 5, 28, // Opcode: LEA_bol
+/* 10874 */   MCD_OPC_FilterValue, 93, 21, 0, 0, // Skip to: 10900
+/* 10879 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 10882 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10891
+/* 10887 */   MCD_OPC_Decode, 140, 4, 29, // Opcode: JL_b
+/* 10891 */   MCD_OPC_FilterValue, 1, 71, 8, 0, // Skip to: 13015
+/* 10896 */   MCD_OPC_Decode, 129, 4, 29, // Opcode: JLA_b
+/* 10900 */   MCD_OPC_FilterValue, 95, 55, 0, 0, // Skip to: 10960
+/* 10905 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 10908 */   MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 10934
+/* 10913 */   MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 10916 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10925
+/* 10921 */   MCD_OPC_Decode, 238, 3, 30, // Opcode: JEQ_brr
+/* 10925 */   MCD_OPC_FilterValue, 1, 37, 8, 0, // Skip to: 13015
+/* 10930 */   MCD_OPC_Decode, 147, 4, 30, // Opcode: JNE_brr
+/* 10934 */   MCD_OPC_FilterValue, 1, 28, 8, 0, // Skip to: 13015
+/* 10939 */   MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 10942 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10951
+/* 10947 */   MCD_OPC_Decode, 237, 3, 31, // Opcode: JEQ_brc
+/* 10951 */   MCD_OPC_FilterValue, 1, 11, 8, 0, // Skip to: 13015
+/* 10956 */   MCD_OPC_Decode, 146, 4, 31, // Opcode: JNE_brc
+/* 10960 */   MCD_OPC_FilterValue, 97, 31, 0, 0, // Skip to: 10996
+/* 10965 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 10968 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10982
+/* 10973 */   MCD_OPC_CheckPredicate, 0, 245, 7, 0, // Skip to: 13015
+/* 10978 */   MCD_OPC_Decode, 201, 3, 29, // Opcode: FCALL_b
+/* 10982 */   MCD_OPC_FilterValue, 1, 236, 7, 0, // Skip to: 13015
+/* 10987 */   MCD_OPC_CheckPredicate, 0, 231, 7, 0, // Skip to: 13015
+/* 10992 */   MCD_OPC_Decode, 199, 3, 29, // Opcode: FCALLA_b
+/* 10996 */   MCD_OPC_FilterValue, 99, 213, 3, 0, // Skip to: 11982
+/* 11001 */   MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 11004 */   MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 11025
+/* 11009 */   MCD_OPC_CheckPredicate, 1, 209, 7, 0, // Skip to: 13015
+/* 11014 */   MCD_OPC_CheckField, 7, 1, 0, 202, 7, 0, // Skip to: 13015
+/* 11021 */   MCD_OPC_Decode, 164, 7, 16, // Opcode: MSUB_Q_rrr1_U
+/* 11025 */   MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 11046
+/* 11030 */   MCD_OPC_CheckPredicate, 1, 188, 7, 0, // Skip to: 13015
+/* 11035 */   MCD_OPC_CheckField, 7, 1, 0, 181, 7, 0, // Skip to: 13015
+/* 11042 */   MCD_OPC_Decode, 162, 7, 16, // Opcode: MSUB_Q_rrr1_L
+/* 11046 */   MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 11067
+/* 11051 */   MCD_OPC_CheckPredicate, 1, 167, 7, 0, // Skip to: 13015
+/* 11056 */   MCD_OPC_CheckField, 7, 1, 0, 160, 7, 0, // Skip to: 13015
+/* 11063 */   MCD_OPC_Decode, 161, 7, 16, // Opcode: MSUB_Q_rrr1
+/* 11067 */   MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 11088
+/* 11072 */   MCD_OPC_CheckPredicate, 1, 146, 7, 0, // Skip to: 13015
+/* 11077 */   MCD_OPC_CheckField, 7, 1, 0, 139, 7, 0, // Skip to: 13015
+/* 11084 */   MCD_OPC_Decode, 166, 7, 16, // Opcode: MSUB_Q_rrr1_U_U
+/* 11088 */   MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 11109
+/* 11093 */   MCD_OPC_CheckPredicate, 1, 125, 7, 0, // Skip to: 13015
+/* 11098 */   MCD_OPC_CheckField, 7, 1, 0, 118, 7, 0, // Skip to: 13015
+/* 11105 */   MCD_OPC_Decode, 163, 7, 16, // Opcode: MSUB_Q_rrr1_L_L
+/* 11109 */   MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 11130
+/* 11114 */   MCD_OPC_CheckPredicate, 1, 104, 7, 0, // Skip to: 13015
+/* 11119 */   MCD_OPC_CheckField, 7, 1, 0, 97, 7, 0, // Skip to: 13015
+/* 11126 */   MCD_OPC_Decode, 129, 7, 16, // Opcode: MSUBR_Q_rrr1_U_U
+/* 11130 */   MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 11151
+/* 11135 */   MCD_OPC_CheckPredicate, 1, 83, 7, 0, // Skip to: 13015
+/* 11140 */   MCD_OPC_CheckField, 7, 1, 0, 76, 7, 0, // Skip to: 13015
+/* 11147 */   MCD_OPC_Decode, 128, 7, 16, // Opcode: MSUBR_Q_rrr1_L_L
+/* 11151 */   MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 11172
+/* 11156 */   MCD_OPC_CheckPredicate, 1, 62, 7, 0, // Skip to: 13015
+/* 11161 */   MCD_OPC_CheckField, 7, 1, 1, 55, 7, 0, // Skip to: 13015
+/* 11168 */   MCD_OPC_Decode, 212, 6, 16, // Opcode: MSUBADR_H_rrr1_UL
+/* 11172 */   MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 11193
+/* 11177 */   MCD_OPC_CheckPredicate, 1, 41, 7, 0, // Skip to: 13015
+/* 11182 */   MCD_OPC_CheckField, 7, 1, 1, 34, 7, 0, // Skip to: 13015
+/* 11189 */   MCD_OPC_Decode, 211, 6, 16, // Opcode: MSUBADR_H_rrr1_LU
+/* 11193 */   MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 11214
+/* 11198 */   MCD_OPC_CheckPredicate, 1, 20, 7, 0, // Skip to: 13015
+/* 11203 */   MCD_OPC_CheckField, 7, 1, 1, 13, 7, 0, // Skip to: 13015
+/* 11210 */   MCD_OPC_Decode, 210, 6, 16, // Opcode: MSUBADR_H_rrr1_LL
+/* 11214 */   MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 11235
+/* 11219 */   MCD_OPC_CheckPredicate, 1, 255, 6, 0, // Skip to: 13015
+/* 11224 */   MCD_OPC_CheckField, 7, 1, 1, 248, 6, 0, // Skip to: 13015
+/* 11231 */   MCD_OPC_Decode, 213, 6, 16, // Opcode: MSUBADR_H_rrr1_UU
+/* 11235 */   MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 11271
+/* 11240 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11243 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11257
+/* 11248 */   MCD_OPC_CheckPredicate, 1, 226, 6, 0, // Skip to: 13015
+/* 11253 */   MCD_OPC_Decode, 170, 7, 16, // Opcode: MSUB_Q_rrr1_e_U
+/* 11257 */   MCD_OPC_FilterValue, 1, 217, 6, 0, // Skip to: 13015
+/* 11262 */   MCD_OPC_CheckPredicate, 1, 212, 6, 0, // Skip to: 13015
+/* 11267 */   MCD_OPC_Decode, 221, 6, 16, // Opcode: MSUBAD_H_rrr1_UL
+/* 11271 */   MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 11307
+/* 11276 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11279 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11293
+/* 11284 */   MCD_OPC_CheckPredicate, 1, 190, 6, 0, // Skip to: 13015
+/* 11289 */   MCD_OPC_Decode, 168, 7, 16, // Opcode: MSUB_Q_rrr1_e_L
+/* 11293 */   MCD_OPC_FilterValue, 1, 181, 6, 0, // Skip to: 13015
+/* 11298 */   MCD_OPC_CheckPredicate, 1, 176, 6, 0, // Skip to: 13015
+/* 11303 */   MCD_OPC_Decode, 220, 6, 16, // Opcode: MSUBAD_H_rrr1_LU
+/* 11307 */   MCD_OPC_FilterValue, 26, 16, 0, 0, // Skip to: 11328
+/* 11312 */   MCD_OPC_CheckPredicate, 1, 162, 6, 0, // Skip to: 13015
+/* 11317 */   MCD_OPC_CheckField, 7, 1, 1, 155, 6, 0, // Skip to: 13015
+/* 11324 */   MCD_OPC_Decode, 219, 6, 16, // Opcode: MSUBAD_H_rrr1_LL
+/* 11328 */   MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 11364
+/* 11333 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11336 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11350
+/* 11341 */   MCD_OPC_CheckPredicate, 1, 133, 6, 0, // Skip to: 13015
+/* 11346 */   MCD_OPC_Decode, 167, 7, 16, // Opcode: MSUB_Q_rrr1_e
+/* 11350 */   MCD_OPC_FilterValue, 1, 124, 6, 0, // Skip to: 13015
+/* 11355 */   MCD_OPC_CheckPredicate, 1, 119, 6, 0, // Skip to: 13015
+/* 11360 */   MCD_OPC_Decode, 222, 6, 16, // Opcode: MSUBAD_H_rrr1_UU
+/* 11364 */   MCD_OPC_FilterValue, 28, 31, 0, 0, // Skip to: 11400
+/* 11369 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11372 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11386
+/* 11377 */   MCD_OPC_CheckPredicate, 1, 97, 6, 0, // Skip to: 13015
+/* 11382 */   MCD_OPC_Decode, 171, 7, 16, // Opcode: MSUB_Q_rrr1_e_U_U
+/* 11386 */   MCD_OPC_FilterValue, 1, 88, 6, 0, // Skip to: 13015
+/* 11391 */   MCD_OPC_CheckPredicate, 1, 83, 6, 0, // Skip to: 13015
+/* 11396 */   MCD_OPC_Decode, 203, 6, 16, // Opcode: MSUBADM_H_rrr1_UL
+/* 11400 */   MCD_OPC_FilterValue, 29, 31, 0, 0, // Skip to: 11436
+/* 11405 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11408 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11422
+/* 11413 */   MCD_OPC_CheckPredicate, 1, 61, 6, 0, // Skip to: 13015
+/* 11418 */   MCD_OPC_Decode, 169, 7, 16, // Opcode: MSUB_Q_rrr1_e_L_L
+/* 11422 */   MCD_OPC_FilterValue, 1, 52, 6, 0, // Skip to: 13015
+/* 11427 */   MCD_OPC_CheckPredicate, 1, 47, 6, 0, // Skip to: 13015
+/* 11432 */   MCD_OPC_Decode, 202, 6, 16, // Opcode: MSUBADM_H_rrr1_LU
+/* 11436 */   MCD_OPC_FilterValue, 30, 31, 0, 0, // Skip to: 11472
+/* 11441 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11444 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11458
+/* 11449 */   MCD_OPC_CheckPredicate, 1, 25, 6, 0, // Skip to: 13015
+/* 11454 */   MCD_OPC_Decode, 253, 6, 16, // Opcode: MSUBR_H_rrr1_UL_2
+/* 11458 */   MCD_OPC_FilterValue, 1, 16, 6, 0, // Skip to: 13015
+/* 11463 */   MCD_OPC_CheckPredicate, 1, 11, 6, 0, // Skip to: 13015
+/* 11468 */   MCD_OPC_Decode, 201, 6, 16, // Opcode: MSUBADM_H_rrr1_LL
+/* 11472 */   MCD_OPC_FilterValue, 31, 16, 0, 0, // Skip to: 11493
+/* 11477 */   MCD_OPC_CheckPredicate, 1, 253, 5, 0, // Skip to: 13015
+/* 11482 */   MCD_OPC_CheckField, 7, 1, 1, 246, 5, 0, // Skip to: 13015
+/* 11489 */   MCD_OPC_Decode, 204, 6, 16, // Opcode: MSUBADM_H_rrr1_UU
+/* 11493 */   MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 11514
+/* 11498 */   MCD_OPC_CheckPredicate, 1, 232, 5, 0, // Skip to: 13015
+/* 11503 */   MCD_OPC_CheckField, 7, 1, 0, 225, 5, 0, // Skip to: 13015
+/* 11510 */   MCD_OPC_Decode, 139, 7, 16, // Opcode: MSUBS_Q_rrr1_U
+/* 11514 */   MCD_OPC_FilterValue, 33, 16, 0, 0, // Skip to: 11535
+/* 11519 */   MCD_OPC_CheckPredicate, 1, 211, 5, 0, // Skip to: 13015
+/* 11524 */   MCD_OPC_CheckField, 7, 1, 0, 204, 5, 0, // Skip to: 13015
+/* 11531 */   MCD_OPC_Decode, 137, 7, 16, // Opcode: MSUBS_Q_rrr1_L
+/* 11535 */   MCD_OPC_FilterValue, 34, 16, 0, 0, // Skip to: 11556
+/* 11540 */   MCD_OPC_CheckPredicate, 1, 190, 5, 0, // Skip to: 13015
+/* 11545 */   MCD_OPC_CheckField, 7, 1, 0, 183, 5, 0, // Skip to: 13015
+/* 11552 */   MCD_OPC_Decode, 136, 7, 16, // Opcode: MSUBS_Q_rrr1
+/* 11556 */   MCD_OPC_FilterValue, 36, 16, 0, 0, // Skip to: 11577
+/* 11561 */   MCD_OPC_CheckPredicate, 1, 169, 5, 0, // Skip to: 13015
+/* 11566 */   MCD_OPC_CheckField, 7, 1, 0, 162, 5, 0, // Skip to: 13015
+/* 11573 */   MCD_OPC_Decode, 141, 7, 16, // Opcode: MSUBS_Q_rrr1_U_U
+/* 11577 */   MCD_OPC_FilterValue, 37, 16, 0, 0, // Skip to: 11598
+/* 11582 */   MCD_OPC_CheckPredicate, 1, 148, 5, 0, // Skip to: 13015
+/* 11587 */   MCD_OPC_CheckField, 7, 1, 0, 141, 5, 0, // Skip to: 13015
+/* 11594 */   MCD_OPC_Decode, 138, 7, 16, // Opcode: MSUBS_Q_rrr1_L_L
+/* 11598 */   MCD_OPC_FilterValue, 38, 16, 0, 0, // Skip to: 11619
+/* 11603 */   MCD_OPC_CheckPredicate, 1, 127, 5, 0, // Skip to: 13015
+/* 11608 */   MCD_OPC_CheckField, 7, 1, 0, 120, 5, 0, // Skip to: 13015
+/* 11615 */   MCD_OPC_Decode, 248, 6, 16, // Opcode: MSUBRS_Q_rrr1_U_U
+/* 11619 */   MCD_OPC_FilterValue, 39, 16, 0, 0, // Skip to: 11640
+/* 11624 */   MCD_OPC_CheckPredicate, 1, 106, 5, 0, // Skip to: 13015
+/* 11629 */   MCD_OPC_CheckField, 7, 1, 0, 99, 5, 0, // Skip to: 13015
+/* 11636 */   MCD_OPC_Decode, 247, 6, 16, // Opcode: MSUBRS_Q_rrr1_L_L
+/* 11640 */   MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 11661
+/* 11645 */   MCD_OPC_CheckPredicate, 1, 85, 5, 0, // Skip to: 13015
+/* 11650 */   MCD_OPC_CheckField, 7, 1, 1, 78, 5, 0, // Skip to: 13015
+/* 11657 */   MCD_OPC_Decode, 207, 6, 16, // Opcode: MSUBADRS_H_rrr1_UL
+/* 11661 */   MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 11682
+/* 11666 */   MCD_OPC_CheckPredicate, 1, 64, 5, 0, // Skip to: 13015
+/* 11671 */   MCD_OPC_CheckField, 7, 1, 1, 57, 5, 0, // Skip to: 13015
+/* 11678 */   MCD_OPC_Decode, 206, 6, 16, // Opcode: MSUBADRS_H_rrr1_LU
+/* 11682 */   MCD_OPC_FilterValue, 46, 16, 0, 0, // Skip to: 11703
+/* 11687 */   MCD_OPC_CheckPredicate, 1, 43, 5, 0, // Skip to: 13015
+/* 11692 */   MCD_OPC_CheckField, 7, 1, 1, 36, 5, 0, // Skip to: 13015
+/* 11699 */   MCD_OPC_Decode, 205, 6, 16, // Opcode: MSUBADRS_H_rrr1_LL
+/* 11703 */   MCD_OPC_FilterValue, 47, 16, 0, 0, // Skip to: 11724
+/* 11708 */   MCD_OPC_CheckPredicate, 1, 22, 5, 0, // Skip to: 13015
+/* 11713 */   MCD_OPC_CheckField, 7, 1, 1, 15, 5, 0, // Skip to: 13015
+/* 11720 */   MCD_OPC_Decode, 208, 6, 16, // Opcode: MSUBADRS_H_rrr1_UU
+/* 11724 */   MCD_OPC_FilterValue, 56, 31, 0, 0, // Skip to: 11760
+/* 11729 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11732 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11746
+/* 11737 */   MCD_OPC_CheckPredicate, 1, 249, 4, 0, // Skip to: 13015
+/* 11742 */   MCD_OPC_Decode, 145, 7, 16, // Opcode: MSUBS_Q_rrr1_e_U
+/* 11746 */   MCD_OPC_FilterValue, 1, 240, 4, 0, // Skip to: 13015
+/* 11751 */   MCD_OPC_CheckPredicate, 1, 235, 4, 0, // Skip to: 13015
+/* 11756 */   MCD_OPC_Decode, 217, 6, 16, // Opcode: MSUBADS_H_rrr1_UL
+/* 11760 */   MCD_OPC_FilterValue, 57, 31, 0, 0, // Skip to: 11796
+/* 11765 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11768 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11782
+/* 11773 */   MCD_OPC_CheckPredicate, 1, 213, 4, 0, // Skip to: 13015
+/* 11778 */   MCD_OPC_Decode, 143, 7, 16, // Opcode: MSUBS_Q_rrr1_e_L
+/* 11782 */   MCD_OPC_FilterValue, 1, 204, 4, 0, // Skip to: 13015
+/* 11787 */   MCD_OPC_CheckPredicate, 1, 199, 4, 0, // Skip to: 13015
+/* 11792 */   MCD_OPC_Decode, 216, 6, 16, // Opcode: MSUBADS_H_rrr1_LU
+/* 11796 */   MCD_OPC_FilterValue, 58, 16, 0, 0, // Skip to: 11817
+/* 11801 */   MCD_OPC_CheckPredicate, 1, 185, 4, 0, // Skip to: 13015
+/* 11806 */   MCD_OPC_CheckField, 7, 1, 1, 178, 4, 0, // Skip to: 13015
+/* 11813 */   MCD_OPC_Decode, 215, 6, 16, // Opcode: MSUBADS_H_rrr1_LL
+/* 11817 */   MCD_OPC_FilterValue, 59, 31, 0, 0, // Skip to: 11853
+/* 11822 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11825 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11839
+/* 11830 */   MCD_OPC_CheckPredicate, 1, 156, 4, 0, // Skip to: 13015
+/* 11835 */   MCD_OPC_Decode, 142, 7, 16, // Opcode: MSUBS_Q_rrr1_e
+/* 11839 */   MCD_OPC_FilterValue, 1, 147, 4, 0, // Skip to: 13015
+/* 11844 */   MCD_OPC_CheckPredicate, 1, 142, 4, 0, // Skip to: 13015
+/* 11849 */   MCD_OPC_Decode, 218, 6, 16, // Opcode: MSUBADS_H_rrr1_UU
+/* 11853 */   MCD_OPC_FilterValue, 60, 31, 0, 0, // Skip to: 11889
+/* 11858 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11861 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11875
+/* 11866 */   MCD_OPC_CheckPredicate, 1, 120, 4, 0, // Skip to: 13015
+/* 11871 */   MCD_OPC_Decode, 146, 7, 16, // Opcode: MSUBS_Q_rrr1_e_U_U
+/* 11875 */   MCD_OPC_FilterValue, 1, 111, 4, 0, // Skip to: 13015
+/* 11880 */   MCD_OPC_CheckPredicate, 1, 106, 4, 0, // Skip to: 13015
+/* 11885 */   MCD_OPC_Decode, 199, 6, 16, // Opcode: MSUBADMS_H_rrr1_UL
+/* 11889 */   MCD_OPC_FilterValue, 61, 31, 0, 0, // Skip to: 11925
+/* 11894 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11897 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11911
+/* 11902 */   MCD_OPC_CheckPredicate, 1, 84, 4, 0, // Skip to: 13015
+/* 11907 */   MCD_OPC_Decode, 144, 7, 16, // Opcode: MSUBS_Q_rrr1_e_L_L
+/* 11911 */   MCD_OPC_FilterValue, 1, 75, 4, 0, // Skip to: 13015
+/* 11916 */   MCD_OPC_CheckPredicate, 1, 70, 4, 0, // Skip to: 13015
+/* 11921 */   MCD_OPC_Decode, 198, 6, 16, // Opcode: MSUBADMS_H_rrr1_LU
+/* 11925 */   MCD_OPC_FilterValue, 62, 31, 0, 0, // Skip to: 11961
+/* 11930 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11933 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11947
+/* 11938 */   MCD_OPC_CheckPredicate, 1, 48, 4, 0, // Skip to: 13015
+/* 11943 */   MCD_OPC_Decode, 244, 6, 16, // Opcode: MSUBRS_H_rrr1_UL_2
+/* 11947 */   MCD_OPC_FilterValue, 1, 39, 4, 0, // Skip to: 13015
+/* 11952 */   MCD_OPC_CheckPredicate, 1, 34, 4, 0, // Skip to: 13015
+/* 11957 */   MCD_OPC_Decode, 197, 6, 16, // Opcode: MSUBADMS_H_rrr1_LL
+/* 11961 */   MCD_OPC_FilterValue, 63, 25, 4, 0, // Skip to: 13015
+/* 11966 */   MCD_OPC_CheckPredicate, 1, 20, 4, 0, // Skip to: 13015
+/* 11971 */   MCD_OPC_CheckField, 7, 1, 1, 13, 4, 0, // Skip to: 13015
+/* 11978 */   MCD_OPC_Decode, 200, 6, 16, // Opcode: MSUBADMS_H_rrr1_UU
+/* 11982 */   MCD_OPC_FilterValue, 101, 45, 0, 0, // Skip to: 12032
+/* 11987 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 11990 */   MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 12006
+/* 11995 */   MCD_OPC_CheckField, 26, 2, 0, 245, 3, 0, // Skip to: 13015
+/* 12002 */   MCD_OPC_Decode, 155, 9, 17, // Opcode: ST_Q_abs
+/* 12006 */   MCD_OPC_FilterValue, 1, 236, 3, 0, // Skip to: 13015
+/* 12011 */   MCD_OPC_ExtractField, 26, 2,  // Inst{27-26} ...
+/* 12014 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12023
+/* 12019 */   MCD_OPC_Decode, 211, 9, 17, // Opcode: SWAP_W_abs
+/* 12023 */   MCD_OPC_FilterValue, 1, 219, 3, 0, // Skip to: 13015
+/* 12028 */   MCD_OPC_Decode, 177, 4, 17, // Opcode: LDMST_abs
+/* 12032 */   MCD_OPC_FilterValue, 103, 35, 0, 0, // Skip to: 12072
+/* 12037 */   MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
+/* 12040 */   MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 12056
+/* 12045 */   MCD_OPC_CheckField, 7, 1, 0, 195, 3, 0, // Skip to: 13015
+/* 12052 */   MCD_OPC_Decode, 228, 3, 18, // Opcode: INS_T
+/* 12056 */   MCD_OPC_FilterValue, 1, 186, 3, 0, // Skip to: 13015
+/* 12061 */   MCD_OPC_CheckField, 7, 1, 0, 179, 3, 0, // Skip to: 13015
+/* 12068 */   MCD_OPC_Decode, 227, 3, 18, // Opcode: INSN_T
+/* 12072 */   MCD_OPC_FilterValue, 105, 145, 0, 0, // Skip to: 12222
+/* 12077 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 12080 */   MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 12208
+/* 12085 */   MCD_OPC_ExtractField, 22, 6,  // Inst{27-22} ...
+/* 12088 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12097
+/* 12093 */   MCD_OPC_Decode, 217, 9, 19, // Opcode: SWAP_W_bo_r
+/* 12097 */   MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 12106
+/* 12102 */   MCD_OPC_Decode, 182, 4, 19, // Opcode: LDMST_bo_r
+/* 12106 */   MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 12120
+/* 12111 */   MCD_OPC_CheckPredicate, 5, 131, 3, 0, // Skip to: 13015
+/* 12116 */   MCD_OPC_Decode, 204, 9, 19, // Opcode: SWAPMSK_W_bo_r
+/* 12120 */   MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 12134
+/* 12125 */   MCD_OPC_CheckPredicate, 5, 117, 3, 0, // Skip to: 13015
+/* 12130 */   MCD_OPC_Decode, 137, 3, 19, // Opcode: CMPSWAP_W_bo_r
+/* 12134 */   MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 12143
+/* 12139 */   MCD_OPC_Decode, 213, 9, 19, // Opcode: SWAP_W_bo_c
+/* 12143 */   MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 12152
+/* 12148 */   MCD_OPC_Decode, 179, 4, 19, // Opcode: LDMST_bo_c
+/* 12152 */   MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 12166
+/* 12157 */   MCD_OPC_CheckPredicate, 5, 85, 3, 0, // Skip to: 13015
+/* 12162 */   MCD_OPC_Decode, 200, 9, 19, // Opcode: SWAPMSK_W_bo_c
+/* 12166 */   MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 12180
+/* 12171 */   MCD_OPC_CheckPredicate, 5, 71, 3, 0, // Skip to: 13015
+/* 12176 */   MCD_OPC_Decode, 134, 3, 19, // Opcode: CMPSWAP_W_bo_c
+/* 12180 */   MCD_OPC_FilterValue, 32, 9, 0, 0, // Skip to: 12194
+/* 12185 */   MCD_OPC_CheckPredicate, 0, 57, 3, 0, // Skip to: 13015
+/* 12190 */   MCD_OPC_Decode, 214, 9, 19, // Opcode: SWAP_W_bo_i
+/* 12194 */   MCD_OPC_FilterValue, 34, 48, 3, 0, // Skip to: 13015
+/* 12199 */   MCD_OPC_CheckPredicate, 5, 43, 3, 0, // Skip to: 13015
+/* 12204 */   MCD_OPC_Decode, 201, 9, 19, // Opcode: SWAPMSK_W_bo_i
+/* 12208 */   MCD_OPC_FilterValue, 1, 34, 3, 0, // Skip to: 13015
+/* 12213 */   MCD_OPC_CheckPredicate, 0, 29, 3, 0, // Skip to: 13015
+/* 12218 */   MCD_OPC_Decode, 247, 8, 28, // Opcode: ST_B_bol
+/* 12222 */   MCD_OPC_FilterValue, 107, 15, 1, 0, // Skip to: 12498
+/* 12227 */   MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 12230 */   MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 12246
+/* 12235 */   MCD_OPC_CheckField, 7, 1, 0, 5, 3, 0, // Skip to: 13015
+/* 12242 */   MCD_OPC_Decode, 141, 8, 32, // Opcode: PACK_rrr
+/* 12246 */   MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 12267
+/* 12251 */   MCD_OPC_CheckPredicate, 6, 247, 2, 0, // Skip to: 13015
+/* 12256 */   MCD_OPC_CheckField, 7, 1, 0, 240, 2, 0, // Skip to: 13015
+/* 12263 */   MCD_OPC_Decode, 142, 3, 32, // Opcode: CRCN_rrr
+/* 12267 */   MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 12288
+/* 12272 */   MCD_OPC_CheckPredicate, 2, 226, 2, 0, // Skip to: 13015
+/* 12277 */   MCD_OPC_CheckField, 7, 1, 0, 219, 2, 0, // Skip to: 13015
+/* 12284 */   MCD_OPC_Decode, 163, 2, 32, // Opcode: ADD_F_rrr
+/* 12288 */   MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 12309
+/* 12293 */   MCD_OPC_CheckPredicate, 2, 205, 2, 0, // Skip to: 13015
+/* 12298 */   MCD_OPC_CheckField, 7, 1, 0, 198, 2, 0, // Skip to: 13015
+/* 12305 */   MCD_OPC_Decode, 192, 9, 32, // Opcode: SUB_F_rrr
+/* 12309 */   MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 12330
+/* 12314 */   MCD_OPC_CheckPredicate, 2, 184, 2, 0, // Skip to: 13015
+/* 12319 */   MCD_OPC_CheckField, 7, 1, 0, 177, 2, 0, // Skip to: 13015
+/* 12326 */   MCD_OPC_Decode, 133, 6, 32, // Opcode: MADD_F_rrr
+/* 12330 */   MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 12351
+/* 12335 */   MCD_OPC_CheckPredicate, 2, 163, 2, 0, // Skip to: 13015
+/* 12340 */   MCD_OPC_CheckField, 7, 1, 0, 156, 2, 0, // Skip to: 13015
+/* 12347 */   MCD_OPC_Decode, 155, 7, 32, // Opcode: MSUB_F_rrr
+/* 12351 */   MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 12372
+/* 12356 */   MCD_OPC_CheckPredicate, 2, 142, 2, 0, // Skip to: 13015
+/* 12361 */   MCD_OPC_CheckField, 7, 1, 0, 135, 2, 0, // Skip to: 13015
+/* 12368 */   MCD_OPC_Decode, 234, 3, 32, // Opcode: IXMIN_rrr
+/* 12372 */   MCD_OPC_FilterValue, 36, 16, 0, 0, // Skip to: 12393
+/* 12377 */   MCD_OPC_CheckPredicate, 2, 121, 2, 0, // Skip to: 13015
+/* 12382 */   MCD_OPC_CheckField, 7, 1, 0, 114, 2, 0, // Skip to: 13015
+/* 12389 */   MCD_OPC_Decode, 233, 3, 32, // Opcode: IXMIN_U_rrr
+/* 12393 */   MCD_OPC_FilterValue, 40, 16, 0, 0, // Skip to: 12414
+/* 12398 */   MCD_OPC_CheckPredicate, 2, 100, 2, 0, // Skip to: 13015
+/* 12403 */   MCD_OPC_CheckField, 7, 1, 0, 93, 2, 0, // Skip to: 13015
+/* 12410 */   MCD_OPC_Decode, 232, 3, 32, // Opcode: IXMAX_rrr
+/* 12414 */   MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 12435
+/* 12419 */   MCD_OPC_CheckPredicate, 2, 79, 2, 0, // Skip to: 13015
+/* 12424 */   MCD_OPC_CheckField, 7, 1, 0, 72, 2, 0, // Skip to: 13015
+/* 12431 */   MCD_OPC_Decode, 231, 3, 32, // Opcode: IXMAX_U_rrr
+/* 12435 */   MCD_OPC_FilterValue, 52, 16, 0, 0, // Skip to: 12456
+/* 12440 */   MCD_OPC_CheckPredicate, 1, 58, 2, 0, // Skip to: 13015
+/* 12445 */   MCD_OPC_CheckField, 7, 1, 0, 51, 2, 0, // Skip to: 13015
+/* 12452 */   MCD_OPC_Decode, 158, 3, 32, // Opcode: DVADJ_rrr
+/* 12456 */   MCD_OPC_FilterValue, 56, 16, 0, 0, // Skip to: 12477
+/* 12461 */   MCD_OPC_CheckPredicate, 1, 37, 2, 0, // Skip to: 13015
+/* 12466 */   MCD_OPC_CheckField, 7, 1, 0, 30, 2, 0, // Skip to: 13015
+/* 12473 */   MCD_OPC_Decode, 173, 3, 32, // Opcode: DVSTEP_U_rrr
+/* 12477 */   MCD_OPC_FilterValue, 60, 21, 2, 0, // Skip to: 13015
+/* 12482 */   MCD_OPC_CheckPredicate, 1, 16, 2, 0, // Skip to: 13015
+/* 12487 */   MCD_OPC_CheckField, 7, 1, 0, 9, 2, 0, // Skip to: 13015
+/* 12494 */   MCD_OPC_Decode, 176, 3, 32, // Opcode: DVSTEP_rrr
+/* 12498 */   MCD_OPC_FilterValue, 109, 21, 0, 0, // Skip to: 12524
+/* 12503 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 12506 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12515
+/* 12511 */   MCD_OPC_Decode, 246, 2, 29, // Opcode: CALL_b
+/* 12515 */   MCD_OPC_FilterValue, 1, 239, 1, 0, // Skip to: 13015
+/* 12520 */   MCD_OPC_Decode, 243, 2, 29, // Opcode: CALLA_b
+/* 12524 */   MCD_OPC_FilterValue, 111, 21, 0, 0, // Skip to: 12550
+/* 12529 */   MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 12532 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12541
+/* 12537 */   MCD_OPC_Decode, 165, 4, 37, // Opcode: JZ_T_brn
+/* 12541 */   MCD_OPC_FilterValue, 1, 213, 1, 0, // Skip to: 13015
+/* 12546 */   MCD_OPC_Decode, 156, 4, 37, // Opcode: JNZ_T_brn
+/* 12550 */   MCD_OPC_FilterValue, 115, 110, 0, 0, // Skip to: 12665
+/* 12555 */   MCD_OPC_ExtractField, 16, 12,  // Inst{27-16} ...
+/* 12558 */   MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 12579
+/* 12563 */   MCD_OPC_CheckPredicate, 1, 191, 1, 0, // Skip to: 13015
+/* 12568 */   MCD_OPC_CheckField, 7, 1, 0, 184, 1, 0, // Skip to: 13015
+/* 12575 */   MCD_OPC_Decode, 224, 7, 38, // Opcode: MUL_rr2
+/* 12579 */   MCD_OPC_FilterValue, 104, 16, 0, 0, // Skip to: 12600
+/* 12584 */   MCD_OPC_CheckPredicate, 1, 170, 1, 0, // Skip to: 13015
+/* 12589 */   MCD_OPC_CheckField, 7, 1, 0, 163, 1, 0, // Skip to: 13015
+/* 12596 */   MCD_OPC_Decode, 221, 7, 38, // Opcode: MUL_U_rr2
+/* 12600 */   MCD_OPC_FilterValue, 106, 16, 0, 0, // Skip to: 12621
+/* 12605 */   MCD_OPC_CheckPredicate, 1, 149, 1, 0, // Skip to: 13015
+/* 12610 */   MCD_OPC_CheckField, 7, 1, 0, 142, 1, 0, // Skip to: 13015
+/* 12617 */   MCD_OPC_Decode, 225, 7, 38, // Opcode: MUL_rr2_e
+/* 12621 */   MCD_OPC_FilterValue, 136, 1, 16, 0, 0, // Skip to: 12643
+/* 12627 */   MCD_OPC_CheckPredicate, 1, 127, 1, 0, // Skip to: 13015
+/* 12632 */   MCD_OPC_CheckField, 7, 1, 0, 120, 1, 0, // Skip to: 13015
+/* 12639 */   MCD_OPC_Decode, 200, 7, 38, // Opcode: MULS_U_rr2
+/* 12643 */   MCD_OPC_FilterValue, 138, 1, 110, 1, 0, // Skip to: 13015
+/* 12649 */   MCD_OPC_CheckPredicate, 1, 105, 1, 0, // Skip to: 13015
+/* 12654 */   MCD_OPC_CheckField, 7, 1, 0, 98, 1, 0, // Skip to: 13015
+/* 12661 */   MCD_OPC_Decode, 203, 7, 38, // Opcode: MULS_rr2
+/* 12665 */   MCD_OPC_FilterValue, 117, 130, 0, 0, // Skip to: 12800
+/* 12670 */   MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 12673 */   MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 12694
+/* 12678 */   MCD_OPC_CheckPredicate, 2, 76, 1, 0, // Skip to: 13015
+/* 12683 */   MCD_OPC_CheckField, 7, 1, 0, 69, 1, 0, // Skip to: 13015
+/* 12690 */   MCD_OPC_Decode, 219, 9, 14, // Opcode: TLBDEMAP_rr
+/* 12694 */   MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 12715
+/* 12699 */   MCD_OPC_CheckPredicate, 2, 55, 1, 0, // Skip to: 13015
+/* 12704 */   MCD_OPC_CheckField, 7, 1, 0, 48, 1, 0, // Skip to: 13015
+/* 12711 */   MCD_OPC_Decode, 220, 9, 14, // Opcode: TLBFLUSH_A_rr
+/* 12715 */   MCD_OPC_FilterValue, 20, 16, 0, 0, // Skip to: 12736
+/* 12720 */   MCD_OPC_CheckPredicate, 2, 34, 1, 0, // Skip to: 13015
+/* 12725 */   MCD_OPC_CheckField, 7, 1, 0, 27, 1, 0, // Skip to: 13015
+/* 12732 */   MCD_OPC_Decode, 221, 9, 14, // Opcode: TLBFLUSH_B_rr
+/* 12736 */   MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 12757
+/* 12741 */   MCD_OPC_CheckPredicate, 2, 13, 1, 0, // Skip to: 13015
+/* 12746 */   MCD_OPC_CheckField, 7, 1, 0, 6, 1, 0, // Skip to: 13015
+/* 12753 */   MCD_OPC_Decode, 223, 9, 14, // Opcode: TLBPROBE_A_rr
+/* 12757 */   MCD_OPC_FilterValue, 36, 16, 0, 0, // Skip to: 12778
+/* 12762 */   MCD_OPC_CheckPredicate, 2, 248, 0, 0, // Skip to: 13015
+/* 12767 */   MCD_OPC_CheckField, 7, 1, 0, 241, 0, 0, // Skip to: 13015
+/* 12774 */   MCD_OPC_Decode, 224, 9, 14, // Opcode: TLBPROBE_I_rr
+/* 12778 */   MCD_OPC_FilterValue, 128, 2, 231, 0, 0, // Skip to: 13015
+/* 12784 */   MCD_OPC_CheckPredicate, 2, 226, 0, 0, // Skip to: 13015
+/* 12789 */   MCD_OPC_CheckField, 7, 1, 0, 219, 0, 0, // Skip to: 13015
+/* 12796 */   MCD_OPC_Decode, 222, 9, 14, // Opcode: TLBMAP_rr
+/* 12800 */   MCD_OPC_FilterValue, 119, 18, 0, 0, // Skip to: 12823
+/* 12805 */   MCD_OPC_CheckField, 21, 2, 0, 203, 0, 0, // Skip to: 13015
+/* 12812 */   MCD_OPC_CheckField, 7, 1, 0, 196, 0, 0, // Skip to: 13015
+/* 12819 */   MCD_OPC_Decode, 149, 3, 33, // Opcode: DEXTR_rrpw
+/* 12823 */   MCD_OPC_FilterValue, 121, 31, 0, 0, // Skip to: 12859
+/* 12828 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 12831 */   MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12845
+/* 12836 */   MCD_OPC_CheckPredicate, 0, 174, 0, 0, // Skip to: 13015
+/* 12841 */   MCD_OPC_Decode, 222, 4, 28, // Opcode: LD_B_bol
+/* 12845 */   MCD_OPC_FilterValue, 1, 165, 0, 0, // Skip to: 13015
+/* 12850 */   MCD_OPC_CheckPredicate, 0, 160, 0, 0, // Skip to: 13015
+/* 12855 */   MCD_OPC_Decode, 146, 9, 28, // Opcode: ST_H_bol
+/* 12859 */   MCD_OPC_FilterValue, 123, 26, 0, 0, // Skip to: 12890
+/* 12864 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 12867 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12876
+/* 12872 */   MCD_OPC_Decode, 174, 6, 22, // Opcode: MOVH_rlc
+/* 12876 */   MCD_OPC_FilterValue, 1, 134, 0, 0, // Skip to: 13015
+/* 12881 */   MCD_OPC_CheckPredicate, 0, 129, 0, 0, // Skip to: 13015
+/* 12886 */   MCD_OPC_Decode, 188, 6, 22, // Opcode: MOV_rlc_e
+/* 12890 */   MCD_OPC_FilterValue, 125, 60, 0, 0, // Skip to: 12955
+/* 12895 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 12898 */   MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 12924
+/* 12903 */   MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 12906 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12915
+/* 12911 */   MCD_OPC_Decode, 236, 3, 30, // Opcode: JEQ_A_brr
+/* 12915 */   MCD_OPC_FilterValue, 1, 95, 0, 0, // Skip to: 13015
+/* 12920 */   MCD_OPC_Decode, 145, 4, 30, // Opcode: JNE_A_brr
+/* 12924 */   MCD_OPC_FilterValue, 1, 86, 0, 0, // Skip to: 13015
+/* 12929 */   MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 12932 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12941
+/* 12937 */   MCD_OPC_Decode, 160, 5, 30, // Opcode: LOOP_brr
+/* 12941 */   MCD_OPC_FilterValue, 1, 69, 0, 0, // Skip to: 13015
+/* 12946 */   MCD_OPC_CheckPredicate, 1, 64, 0, 0, // Skip to: 13015
+/* 12951 */   MCD_OPC_Decode, 159, 5, 30, // Opcode: LOOPU_brr
+/* 12955 */   MCD_OPC_FilterValue, 127, 55, 0, 0, // Skip to: 13015
+/* 12960 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 12963 */   MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 12989
+/* 12968 */   MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 12971 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12980
+/* 12976 */   MCD_OPC_Decode, 250, 3, 30, // Opcode: JGE_brr
+/* 12980 */   MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 13015
+/* 12985 */   MCD_OPC_Decode, 248, 3, 30, // Opcode: JGE_U_brr
+/* 12989 */   MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 13015
+/* 12994 */   MCD_OPC_ExtractField, 31, 1,  // Inst{31} ...
+/* 12997 */   MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 13006
+/* 13002 */   MCD_OPC_Decode, 249, 3, 31, // Opcode: JGE_brc
+/* 13006 */   MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 13015
+/* 13011 */   MCD_OPC_Decode, 247, 3, 31, // Opcode: JGE_U_brc
+/* 13015 */   MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTablev11016[] = {
+/* 0 */       MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 3 */       MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 74
+/* 8 */       MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 11 */      MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 32
+/* 16 */      MCD_OPC_CheckPredicate, 4, 59, 5, 0, // Skip to: 1360
+/* 21 */      MCD_OPC_CheckField, 12, 4, 1, 52, 5, 0, // Skip to: 1360
+/* 28 */      MCD_OPC_Decode, 175, 6, 0, // Opcode: MOVZ_A_sr
+/* 32 */      MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 46
+/* 37 */      MCD_OPC_CheckPredicate, 4, 38, 5, 0, // Skip to: 1360
+/* 42 */      MCD_OPC_Decode, 190, 9, 8, // Opcode: SUB_A_sc_v110
+/* 46 */      MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 60
+/* 51 */      MCD_OPC_CheckPredicate, 4, 24, 5, 0, // Skip to: 1360
+/* 56 */      MCD_OPC_Decode, 178, 6, 1, // Opcode: MOV_AA_srr_srr_v110
+/* 60 */      MCD_OPC_FilterValue, 3, 15, 5, 0, // Skip to: 1360
+/* 65 */      MCD_OPC_CheckPredicate, 4, 10, 5, 0, // Skip to: 1360
+/* 70 */      MCD_OPC_Decode, 202, 2, 8, // Opcode: BISR_sc_v110
+/* 74 */      MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 138
+/* 79 */      MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 82 */      MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 96
+/* 87 */      MCD_OPC_CheckPredicate, 4, 244, 4, 0, // Skip to: 1360
+/* 92 */      MCD_OPC_Decode, 175, 9, 11, // Opcode: ST_W_ssr_v110
+/* 96 */      MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 110
+/* 101 */     MCD_OPC_CheckPredicate, 4, 230, 4, 0, // Skip to: 1360
+/* 106 */     MCD_OPC_Decode, 223, 4, 3, // Opcode: LD_B_slr_post_v110
+/* 110 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 124
+/* 115 */     MCD_OPC_CheckPredicate, 4, 216, 4, 0, // Skip to: 1360
+/* 120 */     MCD_OPC_Decode, 238, 8, 11, // Opcode: ST_A_ssr_v110
+/* 124 */     MCD_OPC_FilterValue, 3, 207, 4, 0, // Skip to: 1360
+/* 129 */     MCD_OPC_CheckPredicate, 4, 202, 4, 0, // Skip to: 1360
+/* 134 */     MCD_OPC_Decode, 210, 4, 3, // Opcode: LD_BU_slr_post_v110
+/* 138 */     MCD_OPC_FilterValue, 6, 45, 0, 0, // Skip to: 188
+/* 143 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 146 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 160
+/* 151 */     MCD_OPC_CheckPredicate, 4, 180, 4, 0, // Skip to: 1360
+/* 156 */     MCD_OPC_Decode, 170, 5, 1, // Opcode: LT_U_srrv110
+/* 160 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 174
+/* 165 */     MCD_OPC_CheckPredicate, 4, 166, 4, 0, // Skip to: 1360
+/* 170 */     MCD_OPC_Decode, 169, 5, 2, // Opcode: LT_U_srcv110
+/* 174 */     MCD_OPC_FilterValue, 3, 157, 4, 0, // Skip to: 1360
+/* 179 */     MCD_OPC_CheckPredicate, 4, 152, 4, 0, // Skip to: 1360
+/* 184 */     MCD_OPC_Decode, 193, 6, 8, // Opcode: MOV_sc_v110
+/* 188 */     MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 252
+/* 193 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 196 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 210
+/* 201 */     MCD_OPC_CheckPredicate, 4, 130, 4, 0, // Skip to: 1360
+/* 206 */     MCD_OPC_Decode, 226, 4, 5, // Opcode: LD_B_sro_v110
+/* 210 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 224
+/* 215 */     MCD_OPC_CheckPredicate, 4, 116, 4, 0, // Skip to: 1360
+/* 220 */     MCD_OPC_Decode, 132, 5, 5, // Opcode: LD_H_sro_v110
+/* 224 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 238
+/* 229 */     MCD_OPC_CheckPredicate, 4, 102, 4, 0, // Skip to: 1360
+/* 234 */     MCD_OPC_Decode, 215, 4, 5, // Opcode: LD_BU_sro_v110
+/* 238 */     MCD_OPC_FilterValue, 3, 93, 4, 0, // Skip to: 1360
+/* 243 */     MCD_OPC_CheckPredicate, 4, 88, 4, 0, // Skip to: 1360
+/* 248 */     MCD_OPC_Decode, 154, 5, 5, // Opcode: LD_W_sro_v110
+/* 252 */     MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 288
+/* 257 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 260 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 274
+/* 265 */     MCD_OPC_CheckPredicate, 4, 66, 4, 0, // Skip to: 1360
+/* 270 */     MCD_OPC_Decode, 242, 2, 1, // Opcode: CADD_srr_v110
+/* 274 */     MCD_OPC_FilterValue, 1, 57, 4, 0, // Skip to: 1360
+/* 279 */     MCD_OPC_CheckPredicate, 4, 52, 4, 0, // Skip to: 1360
+/* 284 */     MCD_OPC_Decode, 236, 2, 1, // Opcode: CADDN_srr_v110
+/* 288 */     MCD_OPC_FilterValue, 12, 59, 0, 0, // Skip to: 352
+/* 293 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 296 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 310
+/* 301 */     MCD_OPC_CheckPredicate, 4, 30, 4, 0, // Skip to: 1360
+/* 306 */     MCD_OPC_Decode, 198, 4, 4, // Opcode: LD_A_slro_v110
+/* 310 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 324
+/* 315 */     MCD_OPC_CheckPredicate, 4, 16, 4, 0, // Skip to: 1360
+/* 320 */     MCD_OPC_Decode, 154, 9, 12, // Opcode: ST_H_ssro_v110
+/* 324 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 338
+/* 329 */     MCD_OPC_CheckPredicate, 4, 2, 4, 0, // Skip to: 1360
+/* 334 */     MCD_OPC_Decode, 255, 8, 12, // Opcode: ST_B_ssro_v110
+/* 338 */     MCD_OPC_FilterValue, 3, 249, 3, 0, // Skip to: 1360
+/* 343 */     MCD_OPC_CheckPredicate, 4, 244, 3, 0, // Skip to: 1360
+/* 348 */     MCD_OPC_Decode, 177, 9, 12, // Opcode: ST_W_ssro_v110
+/* 352 */     MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 388
+/* 357 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 360 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 374
+/* 365 */     MCD_OPC_CheckPredicate, 4, 222, 3, 0, // Skip to: 1360
+/* 370 */     MCD_OPC_Decode, 167, 4, 13, // Opcode: JZ_T_sbrn_v110
+/* 374 */     MCD_OPC_FilterValue, 1, 213, 3, 0, // Skip to: 1360
+/* 379 */     MCD_OPC_CheckPredicate, 4, 208, 3, 0, // Skip to: 1360
+/* 384 */     MCD_OPC_Decode, 158, 4, 13, // Opcode: JNZ_T_sbrn_v110
+/* 388 */     MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 402
+/* 393 */     MCD_OPC_CheckPredicate, 4, 194, 3, 0, // Skip to: 1360
+/* 398 */     MCD_OPC_Decode, 147, 2, 7, // Opcode: ADDSC_A_srrs_v110
+/* 402 */     MCD_OPC_FilterValue, 18, 108, 0, 0, // Skip to: 515
+/* 407 */     MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 410 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 431
+/* 415 */     MCD_OPC_CheckPredicate, 4, 172, 3, 0, // Skip to: 1360
+/* 420 */     MCD_OPC_CheckField, 6, 2, 3, 165, 3, 0, // Skip to: 1360
+/* 427 */     MCD_OPC_Decode, 167, 8, 0, // Opcode: SAT_B_sr_v110
+/* 431 */     MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 452
+/* 436 */     MCD_OPC_CheckPredicate, 4, 151, 3, 0, // Skip to: 1360
+/* 441 */     MCD_OPC_CheckField, 6, 2, 3, 144, 3, 0, // Skip to: 1360
+/* 448 */     MCD_OPC_Decode, 164, 8, 0, // Opcode: SAT_BU_sr_v110
+/* 452 */     MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 473
+/* 457 */     MCD_OPC_CheckPredicate, 4, 130, 3, 0, // Skip to: 1360
+/* 462 */     MCD_OPC_CheckField, 6, 2, 3, 123, 3, 0, // Skip to: 1360
+/* 469 */     MCD_OPC_Decode, 173, 8, 0, // Opcode: SAT_H_sr_v110
+/* 473 */     MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 494
+/* 478 */     MCD_OPC_CheckPredicate, 4, 109, 3, 0, // Skip to: 1360
+/* 483 */     MCD_OPC_CheckField, 6, 2, 3, 102, 3, 0, // Skip to: 1360
+/* 490 */     MCD_OPC_Decode, 170, 8, 0, // Opcode: SAT_HU_sr_v110
+/* 494 */     MCD_OPC_FilterValue, 5, 93, 3, 0, // Skip to: 1360
+/* 499 */     MCD_OPC_CheckPredicate, 4, 88, 3, 0, // Skip to: 1360
+/* 504 */     MCD_OPC_CheckField, 6, 2, 3, 81, 3, 0, // Skip to: 1360
+/* 511 */     MCD_OPC_Decode, 161, 8, 0, // Opcode: RSUB_sr_sr_v110
+/* 515 */     MCD_OPC_FilterValue, 20, 45, 0, 0, // Skip to: 565
+/* 520 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 523 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 537
+/* 528 */     MCD_OPC_CheckPredicate, 4, 59, 3, 0, // Skip to: 1360
+/* 533 */     MCD_OPC_Decode, 151, 9, 11, // Opcode: ST_H_ssr_pos_v110
+/* 537 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 551
+/* 542 */     MCD_OPC_CheckPredicate, 4, 45, 3, 0, // Skip to: 1360
+/* 547 */     MCD_OPC_Decode, 237, 8, 11, // Opcode: ST_A_ssr_pos_v110
+/* 551 */     MCD_OPC_FilterValue, 2, 36, 3, 0, // Skip to: 1360
+/* 556 */     MCD_OPC_CheckPredicate, 4, 31, 3, 0, // Skip to: 1360
+/* 561 */     MCD_OPC_Decode, 174, 9, 11, // Opcode: ST_W_ssr_pos_v110
+/* 565 */     MCD_OPC_FilterValue, 22, 59, 0, 0, // Skip to: 629
+/* 570 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 573 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 587
+/* 578 */     MCD_OPC_CheckPredicate, 4, 9, 3, 0, // Skip to: 1360
+/* 583 */     MCD_OPC_Decode, 198, 2, 1, // Opcode: AND_srr_v110
+/* 587 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 601
+/* 592 */     MCD_OPC_CheckPredicate, 4, 251, 2, 0, // Skip to: 1360
+/* 597 */     MCD_OPC_Decode, 140, 8, 1, // Opcode: OR_srr_v110
+/* 601 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 615
+/* 606 */     MCD_OPC_CheckPredicate, 4, 237, 2, 0, // Skip to: 1360
+/* 611 */     MCD_OPC_Decode, 196, 2, 8, // Opcode: AND_sc_v110
+/* 615 */     MCD_OPC_FilterValue, 3, 228, 2, 0, // Skip to: 1360
+/* 620 */     MCD_OPC_CheckPredicate, 4, 223, 2, 0, // Skip to: 1360
+/* 625 */     MCD_OPC_Decode, 138, 8, 8, // Opcode: OR_sc_v110
+/* 629 */     MCD_OPC_FilterValue, 24, 59, 0, 0, // Skip to: 693
+/* 634 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 637 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 651
+/* 642 */     MCD_OPC_CheckPredicate, 4, 201, 2, 0, // Skip to: 1360
+/* 647 */     MCD_OPC_Decode, 234, 8, 5, // Opcode: ST_A_sro_v110
+/* 651 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 665
+/* 656 */     MCD_OPC_CheckPredicate, 4, 187, 2, 0, // Skip to: 1360
+/* 661 */     MCD_OPC_Decode, 211, 4, 3, // Opcode: LD_BU_slr_v110
+/* 665 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 679
+/* 670 */     MCD_OPC_CheckPredicate, 4, 173, 2, 0, // Skip to: 1360
+/* 675 */     MCD_OPC_Decode, 224, 4, 3, // Opcode: LD_B_slr_v110
+/* 679 */     MCD_OPC_FilterValue, 3, 164, 2, 0, // Skip to: 1360
+/* 684 */     MCD_OPC_CheckPredicate, 4, 159, 2, 0, // Skip to: 1360
+/* 689 */     MCD_OPC_Decode, 128, 5, 3, // Opcode: LD_H_slr_v110
+/* 693 */     MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 714
+/* 698 */     MCD_OPC_CheckPredicate, 4, 145, 2, 0, // Skip to: 1360
+/* 703 */     MCD_OPC_CheckField, 6, 2, 1, 138, 2, 0, // Skip to: 1360
+/* 710 */     MCD_OPC_Decode, 174, 4, 9, // Opcode: J_sb_v110
+/* 714 */     MCD_OPC_FilterValue, 30, 59, 0, 0, // Skip to: 778
+/* 719 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 722 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 736
+/* 727 */     MCD_OPC_CheckPredicate, 4, 116, 2, 0, // Skip to: 1360
+/* 732 */     MCD_OPC_Decode, 244, 3, 6, // Opcode: JEQ_sbr_v110
+/* 736 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 750
+/* 741 */     MCD_OPC_CheckPredicate, 4, 102, 2, 0, // Skip to: 1360
+/* 746 */     MCD_OPC_Decode, 171, 4, 6, // Opcode: JZ_sbr_v110
+/* 750 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 764
+/* 755 */     MCD_OPC_CheckPredicate, 4, 88, 2, 0, // Skip to: 1360
+/* 760 */     MCD_OPC_Decode, 153, 4, 6, // Opcode: JNE_sbr_v110
+/* 764 */     MCD_OPC_FilterValue, 3, 79, 2, 0, // Skip to: 1360
+/* 769 */     MCD_OPC_CheckPredicate, 4, 74, 2, 0, // Skip to: 1360
+/* 774 */     MCD_OPC_Decode, 162, 4, 6, // Opcode: JNZ_sbr_v110
+/* 778 */     MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 799
+/* 783 */     MCD_OPC_CheckPredicate, 4, 60, 2, 0, // Skip to: 1360
+/* 788 */     MCD_OPC_CheckField, 6, 2, 0, 53, 2, 0, // Skip to: 1360
+/* 795 */     MCD_OPC_Decode, 185, 6, 1, // Opcode: MOV_D_srr_srr_v110
+/* 799 */     MCD_OPC_FilterValue, 36, 59, 0, 0, // Skip to: 863
+/* 804 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 807 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 821
+/* 812 */     MCD_OPC_CheckPredicate, 4, 31, 2, 0, // Skip to: 1360
+/* 817 */     MCD_OPC_Decode, 255, 4, 3, // Opcode: LD_H_slr_post_v110
+/* 821 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 835
+/* 826 */     MCD_OPC_CheckPredicate, 4, 17, 2, 0, // Skip to: 1360
+/* 831 */     MCD_OPC_Decode, 195, 4, 3, // Opcode: LD_A_slr_post_v110
+/* 835 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 849
+/* 840 */     MCD_OPC_CheckPredicate, 4, 3, 2, 0, // Skip to: 1360
+/* 845 */     MCD_OPC_Decode, 149, 5, 3, // Opcode: LD_W_slr_post_v110
+/* 849 */     MCD_OPC_FilterValue, 3, 250, 1, 0, // Skip to: 1360
+/* 854 */     MCD_OPC_CheckPredicate, 4, 245, 1, 0, // Skip to: 1360
+/* 859 */     MCD_OPC_Decode, 252, 8, 11, // Opcode: ST_B_ssr_pos_v110
+/* 863 */     MCD_OPC_FilterValue, 38, 31, 0, 0, // Skip to: 899
+/* 868 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 871 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 885
+/* 876 */     MCD_OPC_CheckPredicate, 4, 223, 1, 0, // Skip to: 1360
+/* 881 */     MCD_OPC_Decode, 220, 8, 2, // Opcode: SH_src_v110
+/* 885 */     MCD_OPC_FilterValue, 2, 214, 1, 0, // Skip to: 1360
+/* 890 */     MCD_OPC_CheckPredicate, 4, 209, 1, 0, // Skip to: 1360
+/* 895 */     MCD_OPC_Decode, 191, 8, 2, // Opcode: SHA_src_v110
+/* 899 */     MCD_OPC_FilterValue, 40, 59, 0, 0, // Skip to: 963
+/* 904 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 907 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 921
+/* 912 */     MCD_OPC_CheckPredicate, 4, 187, 1, 0, // Skip to: 1360
+/* 917 */     MCD_OPC_Decode, 200, 4, 5, // Opcode: LD_A_sro_v110
+/* 921 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 935
+/* 926 */     MCD_OPC_CheckPredicate, 4, 173, 1, 0, // Skip to: 1360
+/* 931 */     MCD_OPC_Decode, 148, 9, 5, // Opcode: ST_H_sro_v110
+/* 935 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 949
+/* 940 */     MCD_OPC_CheckPredicate, 4, 159, 1, 0, // Skip to: 1360
+/* 945 */     MCD_OPC_Decode, 249, 8, 5, // Opcode: ST_B_sro_v110
+/* 949 */     MCD_OPC_FilterValue, 3, 150, 1, 0, // Skip to: 1360
+/* 954 */     MCD_OPC_CheckPredicate, 4, 145, 1, 0, // Skip to: 1360
+/* 959 */     MCD_OPC_Decode, 171, 9, 5, // Opcode: ST_W_sro_v110
+/* 963 */     MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 984
+/* 968 */     MCD_OPC_CheckPredicate, 4, 131, 1, 0, // Skip to: 1360
+/* 973 */     MCD_OPC_CheckField, 6, 2, 0, 124, 1, 0, // Skip to: 1360
+/* 980 */     MCD_OPC_Decode, 240, 8, 12, // Opcode: ST_A_ssro_v110
+/* 984 */     MCD_OPC_FilterValue, 46, 59, 0, 0, // Skip to: 1048
+/* 989 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 992 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1006
+/* 997 */     MCD_OPC_CheckPredicate, 4, 102, 1, 0, // Skip to: 1360
+/* 1002 */    MCD_OPC_Decode, 169, 4, 9, // Opcode: JZ_sb_v110
+/* 1006 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1020
+/* 1011 */    MCD_OPC_CheckPredicate, 4, 88, 1, 0, // Skip to: 1360
+/* 1016 */    MCD_OPC_Decode, 241, 3, 10, // Opcode: JEQ_sbc_v110
+/* 1020 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1034
+/* 1025 */    MCD_OPC_CheckPredicate, 4, 74, 1, 0, // Skip to: 1360
+/* 1030 */    MCD_OPC_Decode, 160, 4, 9, // Opcode: JNZ_sb_v110
+/* 1034 */    MCD_OPC_FilterValue, 3, 65, 1, 0, // Skip to: 1360
+/* 1039 */    MCD_OPC_CheckPredicate, 4, 60, 1, 0, // Skip to: 1360
+/* 1044 */    MCD_OPC_Decode, 150, 4, 10, // Opcode: JNE_sbc_v110
+/* 1048 */    MCD_OPC_FilterValue, 48, 16, 0, 0, // Skip to: 1069
+/* 1053 */    MCD_OPC_CheckPredicate, 4, 46, 1, 0, // Skip to: 1360
+/* 1058 */    MCD_OPC_CheckField, 6, 2, 0, 39, 1, 0, // Skip to: 1360
+/* 1065 */    MCD_OPC_Decode, 182, 6, 1, // Opcode: MOV_A_srr_v110
+/* 1069 */    MCD_OPC_FilterValue, 50, 45, 0, 0, // Skip to: 1119
+/* 1074 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1077 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1091
+/* 1082 */    MCD_OPC_CheckPredicate, 4, 17, 1, 0, // Skip to: 1360
+/* 1087 */    MCD_OPC_Decode, 178, 3, 1, // Opcode: DVSTEPv110
+/* 1091 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1105
+/* 1096 */    MCD_OPC_CheckPredicate, 4, 3, 1, 0, // Skip to: 1360
+/* 1101 */    MCD_OPC_Decode, 160, 3, 1, // Opcode: DVADJ_srr_v110
+/* 1105 */    MCD_OPC_FilterValue, 2, 250, 0, 0, // Skip to: 1360
+/* 1110 */    MCD_OPC_CheckPredicate, 4, 245, 0, 0, // Skip to: 1360
+/* 1115 */    MCD_OPC_Decode, 175, 3, 1, // Opcode: DVSTEP_Uv110
+/* 1119 */    MCD_OPC_FilterValue, 52, 59, 0, 0, // Skip to: 1183
+/* 1124 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1127 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1141
+/* 1132 */    MCD_OPC_CheckPredicate, 4, 223, 0, 0, // Skip to: 1360
+/* 1137 */    MCD_OPC_Decode, 225, 4, 4, // Opcode: LD_B_slro_v110
+/* 1141 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1155
+/* 1146 */    MCD_OPC_CheckPredicate, 4, 209, 0, 0, // Skip to: 1360
+/* 1151 */    MCD_OPC_Decode, 130, 5, 4, // Opcode: LD_H_slro_v110
+/* 1155 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1169
+/* 1160 */    MCD_OPC_CheckPredicate, 4, 195, 0, 0, // Skip to: 1360
+/* 1165 */    MCD_OPC_Decode, 213, 4, 4, // Opcode: LD_BU_slro_v110
+/* 1169 */    MCD_OPC_FilterValue, 3, 186, 0, 0, // Skip to: 1360
+/* 1174 */    MCD_OPC_CheckPredicate, 4, 181, 0, 0, // Skip to: 1360
+/* 1179 */    MCD_OPC_Decode, 152, 5, 4, // Opcode: LD_W_slro_v110
+/* 1183 */    MCD_OPC_FilterValue, 54, 23, 0, 0, // Skip to: 1211
+/* 1188 */    MCD_OPC_CheckPredicate, 4, 167, 0, 0, // Skip to: 1360
+/* 1193 */    MCD_OPC_CheckField, 12, 4, 0, 160, 0, 0, // Skip to: 1360
+/* 1200 */    MCD_OPC_CheckField, 6, 2, 0, 153, 0, 0, // Skip to: 1360
+/* 1207 */    MCD_OPC_Decode, 241, 7, 0, // Opcode: NOR_sr_v110
+/* 1211 */    MCD_OPC_FilterValue, 56, 59, 0, 0, // Skip to: 1275
+/* 1216 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1219 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1233
+/* 1224 */    MCD_OPC_CheckPredicate, 4, 131, 0, 0, // Skip to: 1360
+/* 1229 */    MCD_OPC_Decode, 150, 5, 3, // Opcode: LD_W_slr_v110
+/* 1233 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1247
+/* 1238 */    MCD_OPC_CheckPredicate, 4, 117, 0, 0, // Skip to: 1360
+/* 1243 */    MCD_OPC_Decode, 253, 8, 11, // Opcode: ST_B_ssr_v110
+/* 1247 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1261
+/* 1252 */    MCD_OPC_CheckPredicate, 4, 103, 0, 0, // Skip to: 1360
+/* 1257 */    MCD_OPC_Decode, 196, 4, 3, // Opcode: LD_A_slr_v110
+/* 1261 */    MCD_OPC_FilterValue, 3, 94, 0, 0, // Skip to: 1360
+/* 1266 */    MCD_OPC_CheckPredicate, 4, 89, 0, 0, // Skip to: 1360
+/* 1271 */    MCD_OPC_Decode, 152, 9, 11, // Opcode: ST_H_ssr_v110
+/* 1275 */    MCD_OPC_FilterValue, 60, 16, 0, 0, // Skip to: 1296
+/* 1280 */    MCD_OPC_CheckPredicate, 4, 75, 0, 0, // Skip to: 1360
+/* 1285 */    MCD_OPC_CheckField, 6, 2, 0, 68, 0, 0, // Skip to: 1360
+/* 1292 */    MCD_OPC_Decode, 255, 3, 6, // Opcode: JI_sbr_v110
+/* 1296 */    MCD_OPC_FilterValue, 62, 59, 0, 0, // Skip to: 1360
+/* 1301 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1304 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1318
+/* 1309 */    MCD_OPC_CheckPredicate, 4, 46, 0, 0, // Skip to: 1360
+/* 1314 */    MCD_OPC_Decode, 135, 4, 6, // Opcode: JLTZ_sbr_v110
+/* 1318 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1332
+/* 1323 */    MCD_OPC_CheckPredicate, 4, 32, 0, 0, // Skip to: 1360
+/* 1328 */    MCD_OPC_Decode, 252, 3, 6, // Opcode: JGTZ_sbr_v110
+/* 1332 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1346
+/* 1337 */    MCD_OPC_CheckPredicate, 4, 18, 0, 0, // Skip to: 1360
+/* 1342 */    MCD_OPC_Decode, 131, 4, 6, // Opcode: JLEZ_sbr_v110
+/* 1346 */    MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 1360
+/* 1351 */    MCD_OPC_CheckPredicate, 4, 4, 0, 0, // Skip to: 1360
+/* 1356 */    MCD_OPC_Decode, 246, 3, 6, // Opcode: JGEZ_sbr_v110
+/* 1360 */    MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTablev11032[] = {
+/* 0 */       MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
+/* 3 */       MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 71
+/* 8 */       MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 11 */      MCD_OPC_FilterValue, 192, 2, 9, 0, 0, // Skip to: 26
+/* 17 */      MCD_OPC_CheckPredicate, 4, 75, 6, 0, // Skip to: 1633
+/* 22 */      MCD_OPC_Decode, 151, 3, 14, // Opcode: DIFSC_A_rr_v110
+/* 26 */      MCD_OPC_FilterValue, 128, 3, 9, 0, 0, // Skip to: 41
+/* 32 */      MCD_OPC_CheckPredicate, 4, 60, 6, 0, // Skip to: 1633
+/* 37 */      MCD_OPC_Decode, 145, 2, 14, // Opcode: ADDSC_A_rr_v110
+/* 41 */      MCD_OPC_FilterValue, 132, 3, 9, 0, 0, // Skip to: 56
+/* 47 */      MCD_OPC_CheckPredicate, 4, 45, 6, 0, // Skip to: 1633
+/* 52 */      MCD_OPC_Decode, 179, 9, 14, // Opcode: SUBSC_A_rr
+/* 56 */      MCD_OPC_FilterValue, 136, 3, 35, 6, 0, // Skip to: 1633
+/* 62 */      MCD_OPC_CheckPredicate, 4, 30, 6, 0, // Skip to: 1633
+/* 67 */      MCD_OPC_Decode, 143, 2, 14, // Opcode: ADDSC_AT_rr_v110
+/* 71 */      MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 137
+/* 76 */      MCD_OPC_ExtractField, 16, 8,  // Inst{23-16} ...
+/* 79 */      MCD_OPC_FilterValue, 104, 9, 0, 0, // Skip to: 93
+/* 84 */      MCD_OPC_CheckPredicate, 4, 8, 6, 0, // Skip to: 1633
+/* 89 */      MCD_OPC_Decode, 192, 5, 15, // Opcode: MADDM_U_rrr2_v110
+/* 93 */      MCD_OPC_FilterValue, 106, 9, 0, 0, // Skip to: 107
+/* 98 */      MCD_OPC_CheckPredicate, 4, 250, 5, 0, // Skip to: 1633
+/* 103 */     MCD_OPC_Decode, 194, 5, 15, // Opcode: MADDM_rrr2_v110
+/* 107 */     MCD_OPC_FilterValue, 232, 1, 9, 0, 0, // Skip to: 122
+/* 113 */     MCD_OPC_CheckPredicate, 4, 235, 5, 0, // Skip to: 1633
+/* 118 */     MCD_OPC_Decode, 182, 5, 15, // Opcode: MADDMS_U_rrr2_v110
+/* 122 */     MCD_OPC_FilterValue, 234, 1, 225, 5, 0, // Skip to: 1633
+/* 128 */     MCD_OPC_CheckPredicate, 4, 220, 5, 0, // Skip to: 1633
+/* 133 */     MCD_OPC_Decode, 184, 5, 15, // Opcode: MADDMS_rrr2_v110
+/* 137 */     MCD_OPC_FilterValue, 11, 78, 0, 0, // Skip to: 220
+/* 142 */     MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 145 */     MCD_OPC_FilterValue, 136, 2, 9, 0, 0, // Skip to: 160
+/* 151 */     MCD_OPC_CheckPredicate, 4, 197, 5, 0, // Skip to: 1633
+/* 156 */     MCD_OPC_Decode, 149, 2, 14, // Opcode: ADDS_B_rr
+/* 160 */     MCD_OPC_FilterValue, 168, 2, 9, 0, 0, // Skip to: 175
+/* 166 */     MCD_OPC_CheckPredicate, 4, 182, 5, 0, // Skip to: 1633
+/* 171 */     MCD_OPC_Decode, 181, 9, 14, // Opcode: SUBS_B_rr
+/* 175 */     MCD_OPC_FilterValue, 172, 2, 9, 0, 0, // Skip to: 190
+/* 181 */     MCD_OPC_CheckPredicate, 4, 167, 5, 0, // Skip to: 1633
+/* 186 */     MCD_OPC_Decode, 180, 9, 14, // Opcode: SUBS_BU_rr
+/* 190 */     MCD_OPC_FilterValue, 188, 2, 9, 0, 0, // Skip to: 205
+/* 196 */     MCD_OPC_CheckPredicate, 4, 152, 5, 0, // Skip to: 1633
+/* 201 */     MCD_OPC_Decode, 251, 1, 14, // Opcode: ABSDIFS_B_rr_v110
+/* 205 */     MCD_OPC_FilterValue, 244, 2, 142, 5, 0, // Skip to: 1633
+/* 211 */     MCD_OPC_CheckPredicate, 4, 137, 5, 0, // Skip to: 1633
+/* 216 */     MCD_OPC_Decode, 131, 2, 14, // Opcode: ABSS_B_rr_v110
+/* 220 */     MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 258
+/* 225 */     MCD_OPC_ExtractField, 12, 20,  // Inst{31-12} ...
+/* 228 */     MCD_OPC_FilterValue, 128, 40, 9, 0, 0, // Skip to: 243
+/* 234 */     MCD_OPC_CheckPredicate, 4, 114, 5, 0, // Skip to: 1633
+/* 239 */     MCD_OPC_Decode, 150, 8, 21, // Opcode: RET_sys_v110
+/* 243 */     MCD_OPC_FilterValue, 128, 48, 104, 5, 0, // Skip to: 1633
+/* 249 */     MCD_OPC_CheckPredicate, 4, 99, 5, 0, // Skip to: 1633
+/* 254 */     MCD_OPC_Decode, 153, 8, 21, // Opcode: RFE_sys_sys_v110
+/* 258 */     MCD_OPC_FilterValue, 15, 78, 0, 0, // Skip to: 341
+/* 263 */     MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 266 */     MCD_OPC_FilterValue, 128, 1, 9, 0, 0, // Skip to: 281
+/* 272 */     MCD_OPC_CheckPredicate, 4, 76, 5, 0, // Skip to: 1633
+/* 277 */     MCD_OPC_Decode, 196, 8, 14, // Opcode: SH_B_rr
+/* 281 */     MCD_OPC_FilterValue, 132, 1, 9, 0, 0, // Skip to: 296
+/* 287 */     MCD_OPC_CheckPredicate, 4, 61, 5, 0, // Skip to: 1633
+/* 292 */     MCD_OPC_Decode, 185, 8, 14, // Opcode: SHA_B_rr
+/* 296 */     MCD_OPC_FilterValue, 240, 1, 9, 0, 0, // Skip to: 311
+/* 302 */     MCD_OPC_CheckPredicate, 4, 46, 5, 0, // Skip to: 1633
+/* 307 */     MCD_OPC_Decode, 254, 2, 14, // Opcode: CLZ_B_rr_v110
+/* 311 */     MCD_OPC_FilterValue, 244, 1, 9, 0, 0, // Skip to: 326
+/* 317 */     MCD_OPC_CheckPredicate, 4, 31, 5, 0, // Skip to: 1633
+/* 322 */     MCD_OPC_Decode, 248, 2, 14, // Opcode: CLO_B_rr_v110
+/* 326 */     MCD_OPC_FilterValue, 248, 1, 21, 5, 0, // Skip to: 1633
+/* 332 */     MCD_OPC_CheckPredicate, 4, 16, 5, 0, // Skip to: 1633
+/* 337 */     MCD_OPC_Decode, 251, 2, 14, // Opcode: CLS_B_rr_v110
+/* 341 */     MCD_OPC_FilterValue, 19, 59, 0, 0, // Skip to: 405
+/* 346 */     MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
+/* 349 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 363
+/* 354 */     MCD_OPC_CheckPredicate, 4, 250, 4, 0, // Skip to: 1633
+/* 359 */     MCD_OPC_Decode, 191, 5, 24, // Opcode: MADDM_U_rcr_v110
+/* 363 */     MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 377
+/* 368 */     MCD_OPC_CheckPredicate, 4, 236, 4, 0, // Skip to: 1633
+/* 373 */     MCD_OPC_Decode, 193, 5, 24, // Opcode: MADDM_rcr_v110
+/* 377 */     MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 391
+/* 382 */     MCD_OPC_CheckPredicate, 4, 222, 4, 0, // Skip to: 1633
+/* 387 */     MCD_OPC_Decode, 181, 5, 24, // Opcode: MADDMS_U_rcr_v110
+/* 391 */     MCD_OPC_FilterValue, 7, 213, 4, 0, // Skip to: 1633
+/* 396 */     MCD_OPC_CheckPredicate, 4, 208, 4, 0, // Skip to: 1633
+/* 401 */     MCD_OPC_Decode, 183, 5, 24, // Opcode: MADDMS_rcr_v110
+/* 405 */     MCD_OPC_FilterValue, 33, 87, 0, 0, // Skip to: 497
+/* 410 */     MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 413 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 427
+/* 418 */     MCD_OPC_CheckPredicate, 4, 186, 4, 0, // Skip to: 1633
+/* 423 */     MCD_OPC_Decode, 238, 2, 32, // Opcode: CADD_A_rrr_v110
+/* 427 */     MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 441
+/* 432 */     MCD_OPC_CheckPredicate, 4, 172, 4, 0, // Skip to: 1633
+/* 437 */     MCD_OPC_Decode, 232, 2, 32, // Opcode: CADDN_A_rrr_v110
+/* 441 */     MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 455
+/* 446 */     MCD_OPC_CheckPredicate, 4, 158, 4, 0, // Skip to: 1633
+/* 451 */     MCD_OPC_Decode, 145, 3, 32, // Opcode: CSUB_A__rrr_v110
+/* 455 */     MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 469
+/* 460 */     MCD_OPC_CheckPredicate, 4, 144, 4, 0, // Skip to: 1633
+/* 465 */     MCD_OPC_Decode, 143, 3, 32, // Opcode: CSUBN_A__rrr_v110
+/* 469 */     MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 483
+/* 474 */     MCD_OPC_CheckPredicate, 4, 130, 4, 0, // Skip to: 1633
+/* 479 */     MCD_OPC_Decode, 179, 8, 32, // Opcode: SEL_A_rrr_v110
+/* 483 */     MCD_OPC_FilterValue, 20, 121, 4, 0, // Skip to: 1633
+/* 488 */     MCD_OPC_CheckPredicate, 4, 116, 4, 0, // Skip to: 1633
+/* 493 */     MCD_OPC_Decode, 175, 8, 32, // Opcode: SELN_A_rrr_v110
+/* 497 */     MCD_OPC_FilterValue, 35, 61, 0, 0, // Skip to: 563
+/* 502 */     MCD_OPC_ExtractField, 16, 8,  // Inst{23-16} ...
+/* 505 */     MCD_OPC_FilterValue, 104, 9, 0, 0, // Skip to: 519
+/* 510 */     MCD_OPC_CheckPredicate, 4, 94, 4, 0, // Skip to: 1633
+/* 515 */     MCD_OPC_Decode, 238, 6, 15, // Opcode: MSUBM_U_rrr2v110
+/* 519 */     MCD_OPC_FilterValue, 106, 9, 0, 0, // Skip to: 533
+/* 524 */     MCD_OPC_CheckPredicate, 4, 80, 4, 0, // Skip to: 1633
+/* 529 */     MCD_OPC_Decode, 240, 6, 15, // Opcode: MSUBM_rrr2v110
+/* 533 */     MCD_OPC_FilterValue, 232, 1, 9, 0, 0, // Skip to: 548
+/* 539 */     MCD_OPC_CheckPredicate, 4, 65, 4, 0, // Skip to: 1633
+/* 544 */     MCD_OPC_Decode, 228, 6, 15, // Opcode: MSUBMS_U_rrr2v110
+/* 548 */     MCD_OPC_FilterValue, 234, 1, 55, 4, 0, // Skip to: 1633
+/* 554 */     MCD_OPC_CheckPredicate, 4, 50, 4, 0, // Skip to: 1633
+/* 559 */     MCD_OPC_Decode, 230, 6, 15, // Opcode: MSUBMS_rrr2v110
+/* 563 */     MCD_OPC_FilterValue, 43, 45, 0, 0, // Skip to: 613
+/* 568 */     MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 571 */     MCD_OPC_FilterValue, 32, 9, 0, 0, // Skip to: 585
+/* 576 */     MCD_OPC_CheckPredicate, 4, 28, 4, 0, // Skip to: 1633
+/* 581 */     MCD_OPC_Decode, 159, 3, 32, // Opcode: DVADJ_rrr_v110
+/* 585 */     MCD_OPC_FilterValue, 36, 9, 0, 0, // Skip to: 599
+/* 590 */     MCD_OPC_CheckPredicate, 4, 14, 4, 0, // Skip to: 1633
+/* 595 */     MCD_OPC_Decode, 177, 3, 32, // Opcode: DVSTEP_rrrv110
+/* 599 */     MCD_OPC_FilterValue, 40, 5, 4, 0, // Skip to: 1633
+/* 604 */     MCD_OPC_CheckPredicate, 4, 0, 4, 0, // Skip to: 1633
+/* 609 */     MCD_OPC_Decode, 174, 3, 32, // Opcode: DVSTEP_U_rrrv110
+/* 613 */     MCD_OPC_FilterValue, 45, 45, 0, 0, // Skip to: 663
+/* 618 */     MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 621 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 635
+/* 626 */     MCD_OPC_CheckPredicate, 4, 234, 3, 0, // Skip to: 1633
+/* 631 */     MCD_OPC_Decode, 245, 2, 14, // Opcode: CALLI_rr_v110
+/* 635 */     MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 649
+/* 640 */     MCD_OPC_CheckPredicate, 4, 220, 3, 0, // Skip to: 1633
+/* 645 */     MCD_OPC_Decode, 133, 4, 14, // Opcode: JLI_rr_v110
+/* 649 */     MCD_OPC_FilterValue, 12, 211, 3, 0, // Skip to: 1633
+/* 654 */     MCD_OPC_CheckPredicate, 4, 206, 3, 0, // Skip to: 1633
+/* 659 */     MCD_OPC_Decode, 254, 3, 14, // Opcode: JI_rr_v110
+/* 663 */     MCD_OPC_FilterValue, 51, 59, 0, 0, // Skip to: 727
+/* 668 */     MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
+/* 671 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 685
+/* 676 */     MCD_OPC_CheckPredicate, 4, 184, 3, 0, // Skip to: 1633
+/* 681 */     MCD_OPC_Decode, 237, 6, 24, // Opcode: MSUBM_U_rcrv110
+/* 685 */     MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 699
+/* 690 */     MCD_OPC_CheckPredicate, 4, 170, 3, 0, // Skip to: 1633
+/* 695 */     MCD_OPC_Decode, 239, 6, 24, // Opcode: MSUBM_rcrv110
+/* 699 */     MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 713
+/* 704 */     MCD_OPC_CheckPredicate, 4, 156, 3, 0, // Skip to: 1633
+/* 709 */     MCD_OPC_Decode, 227, 6, 24, // Opcode: MSUBMS_U_rcrv110
+/* 713 */     MCD_OPC_FilterValue, 7, 147, 3, 0, // Skip to: 1633
+/* 718 */     MCD_OPC_CheckPredicate, 4, 142, 3, 0, // Skip to: 1633
+/* 723 */     MCD_OPC_Decode, 229, 6, 24, // Opcode: MSUBMS_rcrv110
+/* 727 */     MCD_OPC_FilterValue, 67, 96, 0, 0, // Skip to: 828
+/* 732 */     MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 735 */     MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 749
+/* 740 */     MCD_OPC_CheckPredicate, 4, 74, 0, 0, // Skip to: 819
+/* 745 */     MCD_OPC_Decode, 143, 6, 16, // Opcode: MADD_Q_rrr1_UU2_v110
+/* 749 */     MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 763
+/* 754 */     MCD_OPC_CheckPredicate, 4, 60, 0, 0, // Skip to: 819
+/* 759 */     MCD_OPC_Decode, 212, 5, 16, // Opcode: MADDR_Q_rrr1_v110
+/* 763 */     MCD_OPC_FilterValue, 30, 9, 0, 0, // Skip to: 777
+/* 768 */     MCD_OPC_CheckPredicate, 4, 46, 0, 0, // Skip to: 819
+/* 773 */     MCD_OPC_Decode, 209, 5, 16, // Opcode: MADDR_H_rrr1_v110
+/* 777 */     MCD_OPC_FilterValue, 36, 9, 0, 0, // Skip to: 791
+/* 782 */     MCD_OPC_CheckPredicate, 4, 32, 0, 0, // Skip to: 819
+/* 787 */     MCD_OPC_Decode, 246, 5, 16, // Opcode: MADDS_Q_rrr1_UU2_v110
+/* 791 */     MCD_OPC_FilterValue, 38, 9, 0, 0, // Skip to: 805
+/* 796 */     MCD_OPC_CheckPredicate, 4, 18, 0, 0, // Skip to: 819
+/* 801 */     MCD_OPC_Decode, 203, 5, 16, // Opcode: MADDRS_Q_rrr1_v110
+/* 805 */     MCD_OPC_FilterValue, 62, 9, 0, 0, // Skip to: 819
+/* 810 */     MCD_OPC_CheckPredicate, 4, 4, 0, 0, // Skip to: 819
+/* 815 */     MCD_OPC_Decode, 200, 5, 16, // Opcode: MADDRS_H_rrr1_v110
+/* 819 */     MCD_OPC_CheckPredicate, 4, 41, 3, 0, // Skip to: 1633
+/* 824 */     MCD_OPC_Decode, 190, 5, 16, // Opcode: MADDM_Q_rrr1_v110
+/* 828 */     MCD_OPC_FilterValue, 73, 45, 0, 0, // Skip to: 878
+/* 833 */     MCD_OPC_ExtractField, 22, 6,  // Inst{27-22} ...
+/* 836 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 850
+/* 841 */     MCD_OPC_CheckPredicate, 4, 19, 3, 0, // Skip to: 1633
+/* 846 */     MCD_OPC_Decode, 208, 9, 19, // Opcode: SWAP_A_bo_pos
+/* 850 */     MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 864
+/* 855 */     MCD_OPC_CheckPredicate, 4, 5, 3, 0, // Skip to: 1633
+/* 860 */     MCD_OPC_Decode, 209, 9, 19, // Opcode: SWAP_A_bo_pre
+/* 864 */     MCD_OPC_FilterValue, 34, 252, 2, 0, // Skip to: 1633
+/* 869 */     MCD_OPC_CheckPredicate, 4, 247, 2, 0, // Skip to: 1633
+/* 874 */     MCD_OPC_Decode, 206, 9, 19, // Opcode: SWAP_A_bo_bso
+/* 878 */     MCD_OPC_FilterValue, 75, 61, 0, 0, // Skip to: 944
+/* 883 */     MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 886 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 900
+/* 891 */     MCD_OPC_CheckPredicate, 4, 225, 2, 0, // Skip to: 1633
+/* 896 */     MCD_OPC_Decode, 203, 2, 14, // Opcode: BMERGAE_rr_v110
+/* 900 */     MCD_OPC_FilterValue, 32, 9, 0, 0, // Skip to: 914
+/* 905 */     MCD_OPC_CheckPredicate, 4, 211, 2, 0, // Skip to: 1633
+/* 910 */     MCD_OPC_Decode, 143, 8, 14, // Opcode: PARITY_rr_v110
+/* 914 */     MCD_OPC_FilterValue, 192, 2, 9, 0, 0, // Skip to: 929
+/* 920 */     MCD_OPC_CheckPredicate, 4, 196, 2, 0, // Skip to: 1633
+/* 925 */     MCD_OPC_Decode, 228, 9, 14, // Opcode: UNPACK_rr_rr_v110
+/* 929 */     MCD_OPC_FilterValue, 128, 3, 186, 2, 0, // Skip to: 1633
+/* 935 */     MCD_OPC_CheckPredicate, 4, 181, 2, 0, // Skip to: 1633
+/* 940 */     MCD_OPC_Decode, 206, 2, 14, // Opcode: BSPLIT_rr_v110
+/* 944 */     MCD_OPC_FilterValue, 79, 87, 0, 0, // Skip to: 1036
+/* 949 */     MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 952 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 966
+/* 957 */     MCD_OPC_CheckPredicate, 4, 159, 2, 0, // Skip to: 1633
+/* 962 */     MCD_OPC_Decode, 172, 3, 14, // Opcode: DVINIT_rr_v110
+/* 966 */     MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 980
+/* 971 */     MCD_OPC_CheckPredicate, 4, 145, 2, 0, // Skip to: 1633
+/* 976 */     MCD_OPC_Decode, 170, 3, 14, // Opcode: DVINIT_U_rr_v110
+/* 980 */     MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 994
+/* 985 */     MCD_OPC_CheckPredicate, 4, 131, 2, 0, // Skip to: 1633
+/* 990 */     MCD_OPC_Decode, 168, 3, 14, // Opcode: DVINIT_H_rr_v110
+/* 994 */     MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1008
+/* 999 */     MCD_OPC_CheckPredicate, 4, 117, 2, 0, // Skip to: 1633
+/* 1004 */    MCD_OPC_Decode, 166, 3, 14, // Opcode: DVINIT_HU_rr_v110
+/* 1008 */    MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 1022
+/* 1013 */    MCD_OPC_CheckPredicate, 4, 103, 2, 0, // Skip to: 1633
+/* 1018 */    MCD_OPC_Decode, 164, 3, 14, // Opcode: DVINIT_B_rr_v110
+/* 1022 */    MCD_OPC_FilterValue, 20, 94, 2, 0, // Skip to: 1633
+/* 1027 */    MCD_OPC_CheckPredicate, 4, 89, 2, 0, // Skip to: 1633
+/* 1032 */    MCD_OPC_Decode, 162, 3, 14, // Opcode: DVINIT_BU_rr_v110
+/* 1036 */    MCD_OPC_FilterValue, 83, 31, 0, 0, // Skip to: 1072
+/* 1041 */    MCD_OPC_ExtractField, 21, 7,  // Inst{27-21} ...
+/* 1044 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1058
+/* 1049 */    MCD_OPC_CheckPredicate, 4, 67, 2, 0, // Skip to: 1633
+/* 1054 */    MCD_OPC_Decode, 187, 7, 20, // Opcode: MULM_U_rc
+/* 1058 */    MCD_OPC_FilterValue, 3, 58, 2, 0, // Skip to: 1633
+/* 1063 */    MCD_OPC_CheckPredicate, 4, 53, 2, 0, // Skip to: 1633
+/* 1068 */    MCD_OPC_Decode, 189, 7, 20, // Opcode: MULM_rc
+/* 1072 */    MCD_OPC_FilterValue, 99, 101, 0, 0, // Skip to: 1178
+/* 1077 */    MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 1080 */    MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1094
+/* 1085 */    MCD_OPC_CheckPredicate, 4, 31, 2, 0, // Skip to: 1633
+/* 1090 */    MCD_OPC_Decode, 165, 7, 16, // Opcode: MSUB_Q_rrr1_UU2_v110
+/* 1094 */    MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1108
+/* 1099 */    MCD_OPC_CheckPredicate, 4, 17, 2, 0, // Skip to: 1633
+/* 1104 */    MCD_OPC_Decode, 130, 7, 16, // Opcode: MSUBR_Q_rrr1_v110
+/* 1108 */    MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 1122
+/* 1113 */    MCD_OPC_CheckPredicate, 4, 3, 2, 0, // Skip to: 1633
+/* 1118 */    MCD_OPC_Decode, 236, 6, 16, // Opcode: MSUBM_Q_rrr1_v110
+/* 1122 */    MCD_OPC_FilterValue, 30, 9, 0, 0, // Skip to: 1136
+/* 1127 */    MCD_OPC_CheckPredicate, 4, 245, 1, 0, // Skip to: 1633
+/* 1132 */    MCD_OPC_Decode, 255, 6, 16, // Opcode: MSUBR_H_rrr1_v110
+/* 1136 */    MCD_OPC_FilterValue, 36, 9, 0, 0, // Skip to: 1150
+/* 1141 */    MCD_OPC_CheckPredicate, 4, 231, 1, 0, // Skip to: 1633
+/* 1146 */    MCD_OPC_Decode, 140, 7, 16, // Opcode: MSUBS_Q_rrr1_UU2_v110
+/* 1150 */    MCD_OPC_FilterValue, 38, 9, 0, 0, // Skip to: 1164
+/* 1155 */    MCD_OPC_CheckPredicate, 4, 217, 1, 0, // Skip to: 1633
+/* 1160 */    MCD_OPC_Decode, 249, 6, 16, // Opcode: MSUBRS_Q_rrr1_v110
+/* 1164 */    MCD_OPC_FilterValue, 62, 208, 1, 0, // Skip to: 1633
+/* 1169 */    MCD_OPC_CheckPredicate, 4, 203, 1, 0, // Skip to: 1633
+/* 1174 */    MCD_OPC_Decode, 246, 6, 16, // Opcode: MSUBRS_H_rrr1_v110
+/* 1178 */    MCD_OPC_FilterValue, 105, 31, 0, 0, // Skip to: 1214
+/* 1183 */    MCD_OPC_ExtractField, 22, 6,  // Inst{27-22} ...
+/* 1186 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1200
+/* 1191 */    MCD_OPC_CheckPredicate, 4, 181, 1, 0, // Skip to: 1633
+/* 1196 */    MCD_OPC_Decode, 210, 9, 19, // Opcode: SWAP_A_bo_r
+/* 1200 */    MCD_OPC_FilterValue, 18, 172, 1, 0, // Skip to: 1633
+/* 1205 */    MCD_OPC_CheckPredicate, 4, 167, 1, 0, // Skip to: 1633
+/* 1210 */    MCD_OPC_Decode, 207, 9, 19, // Opcode: SWAP_A_bo_c
+/* 1214 */    MCD_OPC_FilterValue, 115, 77, 0, 0, // Skip to: 1296
+/* 1219 */    MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 1222 */    MCD_OPC_FilterValue, 40, 9, 0, 0, // Skip to: 1236
+/* 1227 */    MCD_OPC_CheckPredicate, 4, 145, 1, 0, // Skip to: 1633
+/* 1232 */    MCD_OPC_Decode, 226, 7, 14, // Opcode: MUL_rr_v110
+/* 1236 */    MCD_OPC_FilterValue, 160, 3, 9, 0, 0, // Skip to: 1251
+/* 1242 */    MCD_OPC_CheckPredicate, 4, 130, 1, 0, // Skip to: 1633
+/* 1247 */    MCD_OPC_Decode, 188, 7, 14, // Opcode: MULM_U_rr
+/* 1251 */    MCD_OPC_FilterValue, 168, 3, 9, 0, 0, // Skip to: 1266
+/* 1257 */    MCD_OPC_CheckPredicate, 4, 115, 1, 0, // Skip to: 1633
+/* 1262 */    MCD_OPC_Decode, 190, 7, 14, // Opcode: MULM_rr
+/* 1266 */    MCD_OPC_FilterValue, 160, 4, 9, 0, 0, // Skip to: 1281
+/* 1272 */    MCD_OPC_CheckPredicate, 4, 100, 1, 0, // Skip to: 1633
+/* 1277 */    MCD_OPC_Decode, 201, 7, 14, // Opcode: MULS_U_rr_v110
+/* 1281 */    MCD_OPC_FilterValue, 168, 4, 90, 1, 0, // Skip to: 1633
+/* 1287 */    MCD_OPC_CheckPredicate, 4, 85, 1, 0, // Skip to: 1633
+/* 1292 */    MCD_OPC_Decode, 204, 7, 14, // Opcode: MULS_rr_v110
+/* 1296 */    MCD_OPC_FilterValue, 131, 1, 45, 0, 0, // Skip to: 1347
+/* 1302 */    MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 1305 */    MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 1319
+/* 1310 */    MCD_OPC_CheckPredicate, 4, 62, 1, 0, // Skip to: 1633
+/* 1315 */    MCD_OPC_Decode, 138, 6, 16, // Opcode: MADD_H_rrr1_v110
+/* 1319 */    MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 1333
+/* 1324 */    MCD_OPC_CheckPredicate, 4, 48, 1, 0, // Skip to: 1633
+/* 1329 */    MCD_OPC_Decode, 189, 5, 16, // Opcode: MADDM_H_rrr1_v110
+/* 1333 */    MCD_OPC_FilterValue, 56, 39, 1, 0, // Skip to: 1633
+/* 1338 */    MCD_OPC_CheckPredicate, 4, 34, 1, 0, // Skip to: 1633
+/* 1343 */    MCD_OPC_Decode, 241, 5, 16, // Opcode: MADDS_H_rrr1_v110
+/* 1347 */    MCD_OPC_FilterValue, 143, 1, 31, 0, 0, // Skip to: 1384
+/* 1353 */    MCD_OPC_ExtractField, 21, 7,  // Inst{27-21} ...
+/* 1356 */    MCD_OPC_FilterValue, 32, 9, 0, 0, // Skip to: 1370
+/* 1361 */    MCD_OPC_CheckPredicate, 4, 11, 1, 0, // Skip to: 1633
+/* 1366 */    MCD_OPC_Decode, 195, 8, 20, // Opcode: SH_B_rc
+/* 1370 */    MCD_OPC_FilterValue, 33, 2, 1, 0, // Skip to: 1633
+/* 1375 */    MCD_OPC_CheckPredicate, 4, 253, 0, 0, // Skip to: 1633
+/* 1380 */    MCD_OPC_Decode, 184, 8, 20, // Opcode: SHA_B_rc
+/* 1384 */    MCD_OPC_FilterValue, 147, 1, 31, 0, 0, // Skip to: 1421
+/* 1390 */    MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 1393 */    MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 1407
+/* 1398 */    MCD_OPC_CheckPredicate, 4, 230, 0, 0, // Skip to: 1633
+/* 1403 */    MCD_OPC_Decode, 219, 7, 14, // Opcode: MUL_Q_rr_v110
+/* 1407 */    MCD_OPC_FilterValue, 24, 221, 0, 0, // Skip to: 1633
+/* 1412 */    MCD_OPC_CheckPredicate, 4, 216, 0, 0, // Skip to: 1633
+/* 1417 */    MCD_OPC_Decode, 198, 7, 14, // Opcode: MULR_Q_rr_v110
+/* 1421 */    MCD_OPC_FilterValue, 161, 1, 59, 0, 0, // Skip to: 1486
+/* 1427 */    MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
+/* 1430 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1444
+/* 1435 */    MCD_OPC_CheckPredicate, 4, 193, 0, 0, // Skip to: 1633
+/* 1440 */    MCD_OPC_Decode, 237, 2, 24, // Opcode: CADD_A_rcr_v110
+/* 1444 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1458
+/* 1449 */    MCD_OPC_CheckPredicate, 4, 179, 0, 0, // Skip to: 1633
+/* 1454 */    MCD_OPC_Decode, 231, 2, 24, // Opcode: CADDN_A_rcr_v110
+/* 1458 */    MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1472
+/* 1463 */    MCD_OPC_CheckPredicate, 4, 165, 0, 0, // Skip to: 1633
+/* 1468 */    MCD_OPC_Decode, 178, 8, 24, // Opcode: SEL_A_rcr_v110
+/* 1472 */    MCD_OPC_FilterValue, 5, 156, 0, 0, // Skip to: 1633
+/* 1477 */    MCD_OPC_CheckPredicate, 4, 151, 0, 0, // Skip to: 1633
+/* 1482 */    MCD_OPC_Decode, 174, 8, 24, // Opcode: SELN_A_rcr_v110
+/* 1486 */    MCD_OPC_FilterValue, 163, 1, 45, 0, 0, // Skip to: 1537
+/* 1492 */    MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 1495 */    MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 1509
+/* 1500 */    MCD_OPC_CheckPredicate, 4, 128, 0, 0, // Skip to: 1633
+/* 1505 */    MCD_OPC_Decode, 160, 7, 16, // Opcode: MSUB_H_rrr1_v110
+/* 1509 */    MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 1523
+/* 1514 */    MCD_OPC_CheckPredicate, 4, 114, 0, 0, // Skip to: 1633
+/* 1519 */    MCD_OPC_Decode, 235, 6, 16, // Opcode: MSUBM_H_rrr1_v110
+/* 1523 */    MCD_OPC_FilterValue, 56, 105, 0, 0, // Skip to: 1633
+/* 1528 */    MCD_OPC_CheckPredicate, 4, 100, 0, 0, // Skip to: 1633
+/* 1533 */    MCD_OPC_Decode, 135, 7, 16, // Opcode: MSUBS_H_rrr1_v110
+/* 1537 */    MCD_OPC_FilterValue, 179, 1, 31, 0, 0, // Skip to: 1574
+/* 1543 */    MCD_OPC_ExtractField, 18, 10,  // Inst{27-18} ...
+/* 1546 */    MCD_OPC_FilterValue, 48, 9, 0, 0, // Skip to: 1560
+/* 1551 */    MCD_OPC_CheckPredicate, 4, 77, 0, 0, // Skip to: 1633
+/* 1556 */    MCD_OPC_Decode, 195, 7, 14, // Opcode: MULR_H_rr_v110
+/* 1560 */    MCD_OPC_FilterValue, 96, 68, 0, 0, // Skip to: 1633
+/* 1565 */    MCD_OPC_CheckPredicate, 4, 63, 0, 0, // Skip to: 1633
+/* 1570 */    MCD_OPC_Decode, 210, 7, 14, // Opcode: MUL_H_rr_v110
+/* 1574 */    MCD_OPC_FilterValue, 227, 1, 31, 0, 0, // Skip to: 1611
+/* 1580 */    MCD_OPC_ExtractField, 18, 6,  // Inst{23-18} ...
+/* 1583 */    MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1597
+/* 1588 */    MCD_OPC_CheckPredicate, 4, 40, 0, 0, // Skip to: 1633
+/* 1593 */    MCD_OPC_Decode, 214, 6, 16, // Opcode: MSUBADR_H_rrr1_v110
+/* 1597 */    MCD_OPC_FilterValue, 44, 31, 0, 0, // Skip to: 1633
+/* 1602 */    MCD_OPC_CheckPredicate, 4, 26, 0, 0, // Skip to: 1633
+/* 1607 */    MCD_OPC_Decode, 209, 6, 16, // Opcode: MSUBADRS_H_rrr1_v110
+/* 1611 */    MCD_OPC_FilterValue, 229, 1, 16, 0, 0, // Skip to: 1633
+/* 1617 */    MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 1633
+/* 1622 */    MCD_OPC_CheckField, 26, 2, 2, 4, 0, 0, // Skip to: 1633
+/* 1629 */    MCD_OPC_Decode, 205, 9, 17, // Opcode: SWAP_A_abs
+/* 1633 */    MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTablev16132[] = {
+/* 0 */       MCD_OPC_CheckPredicate, 7, 19, 0, 0, // Skip to: 24
+/* 5 */       MCD_OPC_CheckField, 21, 7, 1, 12, 0, 0, // Skip to: 24
+/* 12 */      MCD_OPC_CheckField, 0, 8, 173, 1, 4, 0, 0, // Skip to: 24
+/* 20 */      MCD_OPC_Decode, 200, 2, 20, // Opcode: BISR_rc_v161
+/* 24 */      MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTablev16216[] = {
+/* 0 */       MCD_OPC_CheckPredicate, 6, 18, 0, 0, // Skip to: 23
+/* 5 */       MCD_OPC_CheckField, 12, 4, 0, 11, 0, 0, // Skip to: 23
+/* 12 */      MCD_OPC_CheckField, 0, 8, 70, 4, 0, 0, // Skip to: 23
+/* 19 */      MCD_OPC_Decode, 242, 7, 0, // Opcode: NOT_sr_v162
+/* 23 */      MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTablev16232[] = {
+/* 0 */       MCD_OPC_CheckPredicate, 6, 19, 0, 0, // Skip to: 24
+/* 5 */       MCD_OPC_CheckField, 18, 10, 136, 1, 11, 0, 0, // Skip to: 24
+/* 13 */      MCD_OPC_CheckField, 0, 8, 75, 4, 0, 0, // Skip to: 24
+/* 20 */      MCD_OPC_Decode, 144, 8, 14, // Opcode: POPCNT_W_rr
+/* 24 */      MCD_OPC_Fail,
+  0
+};
+
+static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) {
+  switch (Idx) {
+  default: /* llvm_unreachable("Invalid index!"); */
+  case 0:
+    return (TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV160Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV161Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV162Ops));
+  case 1:
+    return (TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV120Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV130Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV131Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV160Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV161Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV162Ops));
+  case 2:
+    return (TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV130Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV131Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV160Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV161Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV162Ops));
+  case 3:
+    return (TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV131Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV160Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV161Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV162Ops));
+  case 4:
+    return (TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV110Ops));
+  case 5:
+    return (TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV161Ops) || TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV162Ops));
+  case 6:
+    return (TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV162Ops));
+  case 7:
+    return (TriCore_getFeatureBits(Inst->csh->mode, TRICORE_HasV161Ops));
+  }
+}
+
+#define DecodeToMCInst(fname, fieldname, InsnType) \
+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
+		uint64_t Address, void *Decoder) \
+{ \
+  switch (Idx) { \
+  default: /* llvm_unreachable("Invalid index!"); */ \
+  case 0: \
+    if (DecodeSRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 1: \
+    if (DecodeSRRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 2: \
+    if (DecodeSRCInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 3: \
+    if (DecodeSLRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 4: \
+    if (DecodeSLROInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 5: \
+    if (DecodeSROInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 6: \
+    if (DecodeSBRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 7: \
+    if (DecodeSRRSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 8: \
+    if (DecodeSCInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 9: \
+    if (DecodeSBInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 10: \
+    if (DecodeSBCInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 11: \
+    if (DecodeSSRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 12: \
+    if (DecodeSSROInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 13: \
+    if (DecodeSBRNInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 14: \
+    if (DecodeRRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 15: \
+    if (DecodeRRR2Instruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 16: \
+    if (DecodeRRR1Instruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 17: \
+    if (DecodeABSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 18: \
+    if (DecodeBITInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 19: \
+    if (DecodeBOInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 20: \
+    if (DecodeRCInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 21: \
+    if (DecodeSYSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 22: \
+    if (DecodeRLCInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 23: \
+    if (DecodeRR1Instruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 24: \
+    if (DecodeRCRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 25: \
+    if (DecodeRRRWInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 26: \
+    if (DecodeRCRRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 27: \
+    if (DecodeRRRRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 28: \
+    if (DecodeBOLInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 29: \
+    if (DecodeBInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 30: \
+    if (DecodeBRRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 31: \
+    if (DecodeBRCInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 32: \
+    if (DecodeRRRInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 33: \
+    if (DecodeRRPWInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 34: \
+    if (DecodeRCPWInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 35: \
+    if (DecodeABSBInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 36: \
+    if (DecodeRCRWInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 37: \
+    if (DecodeBRNInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  case 38: \
+    if (DecodeRR2Instruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
+    return S; \
+  } \
+}
+
+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
+           InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
+{ \
+  const uint8_t *Ptr = DecodeTable; \
+  uint64_t CurFieldValue = 0, ExpectedValue; \
+  DecodeStatus S = MCDisassembler_Success; \
+  unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
+  InsnType Val, FieldValue, PositiveMask, NegativeMask; \
+  bool Pred, Fail; \
+  for (;;) { \
+    switch (*Ptr) { \
+    default: \
+      return MCDisassembler_Fail; \
+    case MCD_OPC_ExtractField: { \
+      Start = *++Ptr; \
+      Len = *++Ptr; \
+      ++Ptr; \
+      CurFieldValue = fieldname(insn, Start, Len); \
+      break; \
+    } \
+    case MCD_OPC_FilterValue: { \
+      Val = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      NumToSkip |= (*Ptr++) << 16; \
+      if (Val != CurFieldValue) \
+        Ptr += NumToSkip; \
+      break; \
+    } \
+    case MCD_OPC_CheckField: { \
+      Start = *++Ptr; \
+      Len = *++Ptr; \
+      FieldValue = fieldname(insn, Start, Len); \
+      ExpectedValue = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      NumToSkip |= (*Ptr++) << 16; \
+      if (ExpectedValue != FieldValue) \
+        Ptr += NumToSkip; \
+      break; \
+    } \
+    case MCD_OPC_CheckPredicate: { \
+      PIdx = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      NumToSkip |= (*Ptr++) << 16; \
+      Pred = checkDecoderPredicate(MI, PIdx); \
+      if (!Pred) \
+        Ptr += NumToSkip; \
+      break; \
+    } \
+    case MCD_OPC_Decode: { \
+      Opc = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      DecodeIdx = decodeULEB128(Ptr, &Len); \
+      Ptr += Len; \
+      MCInst_clear(MI); \
+      MCInst_setOpcode(MI, Opc); \
+      return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
+    } \
+    case MCD_OPC_TryDecode: { \
+      /* Decode the Opcode value. */ \
+      Opc = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      DecodeIdx = decodeULEB128(Ptr, &Len); \
+      Ptr += Len; \
+      /* NumToSkip is a plain 24-bit integer. */ \
+      NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      NumToSkip |= (*Ptr++) << 16; \
+      /* Perform the decode operation. */ \
+      MCInst_setOpcode(MI, Opc); \
+      if (decoder(S, DecodeIdx, insn, MI, Address, MRI)) { \
+        /* Decoding complete. */ \
+        return S; \
+      } else { \
+        /* If the decoding was incomplete, skip. */ \
+        Ptr += NumToSkip; \
+        /* Reset decode status. This also drops a SoftFail status that could be */ \
+        /* set before the decode attempt. */ \
+        S = MCDisassembler_Success; \
+      } \
+      break; \
+    } \
+    case MCD_OPC_SoftFail: { \
+      PositiveMask = decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NegativeMask = decodeULEB128(Ptr, &Len); \
+      Ptr += Len; \
+      Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+      if (Fail) \
+        S = MCDisassembler_SoftFail; \
+      break; \
+    } \
+    case MCD_OPC_Fail: { \
+      return MCDisassembler_Fail; \
+    } \
+    } \
+  } \
+}
+
+FieldFromInstruction(fieldFromInstruction_2, uint16_t)
+DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t)
+DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t)
+
+FieldFromInstruction(fieldFromInstruction_4, uint32_t)
+DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
+DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
\ No newline at end of file
diff --git a/arch/TriCore/TriCoreGenInstrInfo.inc b/arch/TriCore/TriCoreGenInstrInfo.inc
new file mode 100644
index 0000000000..790cbdbc63
--- /dev/null
+++ b/arch/TriCore/TriCoreGenInstrInfo.inc
@@ -0,0 +1,2693 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+
+  enum {
+    TRICORE_PHI	= 0,
+    TRICORE_INLINEASM	= 1,
+    TRICORE_INLINEASM_BR	= 2,
+    TRICORE_CFI_INSTRUCTION	= 3,
+    TRICORE_EH_LABEL	= 4,
+    TRICORE_GC_LABEL	= 5,
+    TRICORE_ANNOTATION_LABEL	= 6,
+    TRICORE_KILL	= 7,
+    TRICORE_EXTRACT_SUBREG	= 8,
+    TRICORE_INSERT_SUBREG	= 9,
+    TRICORE_IMPLICIT_DEF	= 10,
+    TRICORE_SUBREG_TO_REG	= 11,
+    TRICORE_COPY_TO_REGCLASS	= 12,
+    TRICORE_DBG_VALUE	= 13,
+    TRICORE_DBG_VALUE_LIST	= 14,
+    TRICORE_DBG_INSTR_REF	= 15,
+    TRICORE_DBG_PHI	= 16,
+    TRICORE_DBG_LABEL	= 17,
+    TRICORE_REG_SEQUENCE	= 18,
+    TRICORE_COPY	= 19,
+    TRICORE_BUNDLE	= 20,
+    TRICORE_LIFETIME_START	= 21,
+    TRICORE_LIFETIME_END	= 22,
+    TRICORE_PSEUDO_PROBE	= 23,
+    TRICORE_ARITH_FENCE	= 24,
+    TRICORE_STACKMAP	= 25,
+    TRICORE_FENTRY_CALL	= 26,
+    TRICORE_PATCHPOINT	= 27,
+    TRICORE_LOAD_STACK_GUARD	= 28,
+    TRICORE_PREALLOCATED_SETUP	= 29,
+    TRICORE_PREALLOCATED_ARG	= 30,
+    TRICORE_STATEPOINT	= 31,
+    TRICORE_LOCAL_ESCAPE	= 32,
+    TRICORE_FAULTING_OP	= 33,
+    TRICORE_PATCHABLE_OP	= 34,
+    TRICORE_PATCHABLE_FUNCTION_ENTER	= 35,
+    TRICORE_PATCHABLE_RET	= 36,
+    TRICORE_PATCHABLE_FUNCTION_EXIT	= 37,
+    TRICORE_PATCHABLE_TAIL_CALL	= 38,
+    TRICORE_PATCHABLE_EVENT_CALL	= 39,
+    TRICORE_PATCHABLE_TYPED_EVENT_CALL	= 40,
+    TRICORE_ICALL_BRANCH_FUNNEL	= 41,
+    TRICORE_MEMBARRIER	= 42,
+    TRICORE_G_ASSERT_SEXT	= 43,
+    TRICORE_G_ASSERT_ZEXT	= 44,
+    TRICORE_G_ASSERT_ALIGN	= 45,
+    TRICORE_G_ADD	= 46,
+    TRICORE_G_SUB	= 47,
+    TRICORE_G_MUL	= 48,
+    TRICORE_G_SDIV	= 49,
+    TRICORE_G_UDIV	= 50,
+    TRICORE_G_SREM	= 51,
+    TRICORE_G_UREM	= 52,
+    TRICORE_G_SDIVREM	= 53,
+    TRICORE_G_UDIVREM	= 54,
+    TRICORE_G_AND	= 55,
+    TRICORE_G_OR	= 56,
+    TRICORE_G_XOR	= 57,
+    TRICORE_G_IMPLICIT_DEF	= 58,
+    TRICORE_G_PHI	= 59,
+    TRICORE_G_FRAME_INDEX	= 60,
+    TRICORE_G_GLOBAL_VALUE	= 61,
+    TRICORE_G_EXTRACT	= 62,
+    TRICORE_G_UNMERGE_VALUES	= 63,
+    TRICORE_G_INSERT	= 64,
+    TRICORE_G_MERGE_VALUES	= 65,
+    TRICORE_G_BUILD_VECTOR	= 66,
+    TRICORE_G_BUILD_VECTOR_TRUNC	= 67,
+    TRICORE_G_CONCAT_VECTORS	= 68,
+    TRICORE_G_PTRTOINT	= 69,
+    TRICORE_G_INTTOPTR	= 70,
+    TRICORE_G_BITCAST	= 71,
+    TRICORE_G_FREEZE	= 72,
+    TRICORE_G_INTRINSIC_FPTRUNC_ROUND	= 73,
+    TRICORE_G_INTRINSIC_TRUNC	= 74,
+    TRICORE_G_INTRINSIC_ROUND	= 75,
+    TRICORE_G_INTRINSIC_LRINT	= 76,
+    TRICORE_G_INTRINSIC_ROUNDEVEN	= 77,
+    TRICORE_G_READCYCLECOUNTER	= 78,
+    TRICORE_G_LOAD	= 79,
+    TRICORE_G_SEXTLOAD	= 80,
+    TRICORE_G_ZEXTLOAD	= 81,
+    TRICORE_G_INDEXED_LOAD	= 82,
+    TRICORE_G_INDEXED_SEXTLOAD	= 83,
+    TRICORE_G_INDEXED_ZEXTLOAD	= 84,
+    TRICORE_G_STORE	= 85,
+    TRICORE_G_INDEXED_STORE	= 86,
+    TRICORE_G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 87,
+    TRICORE_G_ATOMIC_CMPXCHG	= 88,
+    TRICORE_G_ATOMICRMW_XCHG	= 89,
+    TRICORE_G_ATOMICRMW_ADD	= 90,
+    TRICORE_G_ATOMICRMW_SUB	= 91,
+    TRICORE_G_ATOMICRMW_AND	= 92,
+    TRICORE_G_ATOMICRMW_NAND	= 93,
+    TRICORE_G_ATOMICRMW_OR	= 94,
+    TRICORE_G_ATOMICRMW_XOR	= 95,
+    TRICORE_G_ATOMICRMW_MAX	= 96,
+    TRICORE_G_ATOMICRMW_MIN	= 97,
+    TRICORE_G_ATOMICRMW_UMAX	= 98,
+    TRICORE_G_ATOMICRMW_UMIN	= 99,
+    TRICORE_G_ATOMICRMW_FADD	= 100,
+    TRICORE_G_ATOMICRMW_FSUB	= 101,
+    TRICORE_G_ATOMICRMW_FMAX	= 102,
+    TRICORE_G_ATOMICRMW_FMIN	= 103,
+    TRICORE_G_ATOMICRMW_UINC_WRAP	= 104,
+    TRICORE_G_ATOMICRMW_UDEC_WRAP	= 105,
+    TRICORE_G_FENCE	= 106,
+    TRICORE_G_BRCOND	= 107,
+    TRICORE_G_BRINDIRECT	= 108,
+    TRICORE_G_INVOKE_REGION_START	= 109,
+    TRICORE_G_INTRINSIC	= 110,
+    TRICORE_G_INTRINSIC_W_SIDE_EFFECTS	= 111,
+    TRICORE_G_ANYEXT	= 112,
+    TRICORE_G_TRUNC	= 113,
+    TRICORE_G_CONSTANT	= 114,
+    TRICORE_G_FCONSTANT	= 115,
+    TRICORE_G_VASTART	= 116,
+    TRICORE_G_VAARG	= 117,
+    TRICORE_G_SEXT	= 118,
+    TRICORE_G_SEXT_INREG	= 119,
+    TRICORE_G_ZEXT	= 120,
+    TRICORE_G_SHL	= 121,
+    TRICORE_G_LSHR	= 122,
+    TRICORE_G_ASHR	= 123,
+    TRICORE_G_FSHL	= 124,
+    TRICORE_G_FSHR	= 125,
+    TRICORE_G_ROTR	= 126,
+    TRICORE_G_ROTL	= 127,
+    TRICORE_G_ICMP	= 128,
+    TRICORE_G_FCMP	= 129,
+    TRICORE_G_SELECT	= 130,
+    TRICORE_G_UADDO	= 131,
+    TRICORE_G_UADDE	= 132,
+    TRICORE_G_USUBO	= 133,
+    TRICORE_G_USUBE	= 134,
+    TRICORE_G_SADDO	= 135,
+    TRICORE_G_SADDE	= 136,
+    TRICORE_G_SSUBO	= 137,
+    TRICORE_G_SSUBE	= 138,
+    TRICORE_G_UMULO	= 139,
+    TRICORE_G_SMULO	= 140,
+    TRICORE_G_UMULH	= 141,
+    TRICORE_G_SMULH	= 142,
+    TRICORE_G_UADDSAT	= 143,
+    TRICORE_G_SADDSAT	= 144,
+    TRICORE_G_USUBSAT	= 145,
+    TRICORE_G_SSUBSAT	= 146,
+    TRICORE_G_USHLSAT	= 147,
+    TRICORE_G_SSHLSAT	= 148,
+    TRICORE_G_SMULFIX	= 149,
+    TRICORE_G_UMULFIX	= 150,
+    TRICORE_G_SMULFIXSAT	= 151,
+    TRICORE_G_UMULFIXSAT	= 152,
+    TRICORE_G_SDIVFIX	= 153,
+    TRICORE_G_UDIVFIX	= 154,
+    TRICORE_G_SDIVFIXSAT	= 155,
+    TRICORE_G_UDIVFIXSAT	= 156,
+    TRICORE_G_FADD	= 157,
+    TRICORE_G_FSUB	= 158,
+    TRICORE_G_FMUL	= 159,
+    TRICORE_G_FMA	= 160,
+    TRICORE_G_FMAD	= 161,
+    TRICORE_G_FDIV	= 162,
+    TRICORE_G_FREM	= 163,
+    TRICORE_G_FPOW	= 164,
+    TRICORE_G_FPOWI	= 165,
+    TRICORE_G_FEXP	= 166,
+    TRICORE_G_FEXP2	= 167,
+    TRICORE_G_FLOG	= 168,
+    TRICORE_G_FLOG2	= 169,
+    TRICORE_G_FLOG10	= 170,
+    TRICORE_G_FNEG	= 171,
+    TRICORE_G_FPEXT	= 172,
+    TRICORE_G_FPTRUNC	= 173,
+    TRICORE_G_FPTOSI	= 174,
+    TRICORE_G_FPTOUI	= 175,
+    TRICORE_G_SITOFP	= 176,
+    TRICORE_G_UITOFP	= 177,
+    TRICORE_G_FABS	= 178,
+    TRICORE_G_FCOPYSIGN	= 179,
+    TRICORE_G_IS_FPCLASS	= 180,
+    TRICORE_G_FCANONICALIZE	= 181,
+    TRICORE_G_FMINNUM	= 182,
+    TRICORE_G_FMAXNUM	= 183,
+    TRICORE_G_FMINNUM_IEEE	= 184,
+    TRICORE_G_FMAXNUM_IEEE	= 185,
+    TRICORE_G_FMINIMUM	= 186,
+    TRICORE_G_FMAXIMUM	= 187,
+    TRICORE_G_PTR_ADD	= 188,
+    TRICORE_G_PTRMASK	= 189,
+    TRICORE_G_SMIN	= 190,
+    TRICORE_G_SMAX	= 191,
+    TRICORE_G_UMIN	= 192,
+    TRICORE_G_UMAX	= 193,
+    TRICORE_G_ABS	= 194,
+    TRICORE_G_LROUND	= 195,
+    TRICORE_G_LLROUND	= 196,
+    TRICORE_G_BR	= 197,
+    TRICORE_G_BRJT	= 198,
+    TRICORE_G_INSERT_VECTOR_ELT	= 199,
+    TRICORE_G_EXTRACT_VECTOR_ELT	= 200,
+    TRICORE_G_SHUFFLE_VECTOR	= 201,
+    TRICORE_G_CTTZ	= 202,
+    TRICORE_G_CTTZ_ZERO_UNDEF	= 203,
+    TRICORE_G_CTLZ	= 204,
+    TRICORE_G_CTLZ_ZERO_UNDEF	= 205,
+    TRICORE_G_CTPOP	= 206,
+    TRICORE_G_BSWAP	= 207,
+    TRICORE_G_BITREVERSE	= 208,
+    TRICORE_G_FCEIL	= 209,
+    TRICORE_G_FCOS	= 210,
+    TRICORE_G_FSIN	= 211,
+    TRICORE_G_FSQRT	= 212,
+    TRICORE_G_FFLOOR	= 213,
+    TRICORE_G_FRINT	= 214,
+    TRICORE_G_FNEARBYINT	= 215,
+    TRICORE_G_ADDRSPACE_CAST	= 216,
+    TRICORE_G_BLOCK_ADDR	= 217,
+    TRICORE_G_JUMP_TABLE	= 218,
+    TRICORE_G_DYN_STACKALLOC	= 219,
+    TRICORE_G_STRICT_FADD	= 220,
+    TRICORE_G_STRICT_FSUB	= 221,
+    TRICORE_G_STRICT_FMUL	= 222,
+    TRICORE_G_STRICT_FDIV	= 223,
+    TRICORE_G_STRICT_FREM	= 224,
+    TRICORE_G_STRICT_FMA	= 225,
+    TRICORE_G_STRICT_FSQRT	= 226,
+    TRICORE_G_READ_REGISTER	= 227,
+    TRICORE_G_WRITE_REGISTER	= 228,
+    TRICORE_G_MEMCPY	= 229,
+    TRICORE_G_MEMCPY_INLINE	= 230,
+    TRICORE_G_MEMMOVE	= 231,
+    TRICORE_G_MEMSET	= 232,
+    TRICORE_G_BZERO	= 233,
+    TRICORE_G_VECREDUCE_SEQ_FADD	= 234,
+    TRICORE_G_VECREDUCE_SEQ_FMUL	= 235,
+    TRICORE_G_VECREDUCE_FADD	= 236,
+    TRICORE_G_VECREDUCE_FMUL	= 237,
+    TRICORE_G_VECREDUCE_FMAX	= 238,
+    TRICORE_G_VECREDUCE_FMIN	= 239,
+    TRICORE_G_VECREDUCE_ADD	= 240,
+    TRICORE_G_VECREDUCE_MUL	= 241,
+    TRICORE_G_VECREDUCE_AND	= 242,
+    TRICORE_G_VECREDUCE_OR	= 243,
+    TRICORE_G_VECREDUCE_XOR	= 244,
+    TRICORE_G_VECREDUCE_SMAX	= 245,
+    TRICORE_G_VECREDUCE_SMIN	= 246,
+    TRICORE_G_VECREDUCE_UMAX	= 247,
+    TRICORE_G_VECREDUCE_UMIN	= 248,
+    TRICORE_G_SBFX	= 249,
+    TRICORE_G_UBFX	= 250,
+    TRICORE_ABSDIFS_B_rr_v110	= 251,
+    TRICORE_ABSDIFS_H_rr	= 252,
+    TRICORE_ABSDIFS_rc	= 253,
+    TRICORE_ABSDIFS_rr	= 254,
+    TRICORE_ABSDIF_B_rr	= 255,
+    TRICORE_ABSDIF_H_rr	= 256,
+    TRICORE_ABSDIF_rc	= 257,
+    TRICORE_ABSDIF_rr	= 258,
+    TRICORE_ABSS_B_rr_v110	= 259,
+    TRICORE_ABSS_H_rr	= 260,
+    TRICORE_ABSS_rr	= 261,
+    TRICORE_ABS_B_rr	= 262,
+    TRICORE_ABS_H_rr	= 263,
+    TRICORE_ABS_rr	= 264,
+    TRICORE_ADDC_rc	= 265,
+    TRICORE_ADDC_rr	= 266,
+    TRICORE_ADDIH_A_rlc	= 267,
+    TRICORE_ADDIH_rlc	= 268,
+    TRICORE_ADDI_rlc	= 269,
+    TRICORE_ADDSC_AT_rr	= 270,
+    TRICORE_ADDSC_AT_rr_v110	= 271,
+    TRICORE_ADDSC_A_rr	= 272,
+    TRICORE_ADDSC_A_rr_v110	= 273,
+    TRICORE_ADDSC_A_srrs	= 274,
+    TRICORE_ADDSC_A_srrs_v110	= 275,
+    TRICORE_ADDS_BU_rr_v110	= 276,
+    TRICORE_ADDS_B_rr	= 277,
+    TRICORE_ADDS_H	= 278,
+    TRICORE_ADDS_HU	= 279,
+    TRICORE_ADDS_U	= 280,
+    TRICORE_ADDS_U_rc	= 281,
+    TRICORE_ADDS_rc	= 282,
+    TRICORE_ADDS_rr	= 283,
+    TRICORE_ADDS_srr	= 284,
+    TRICORE_ADDX_rc	= 285,
+    TRICORE_ADDX_rr	= 286,
+    TRICORE_ADD_A_rr	= 287,
+    TRICORE_ADD_A_src	= 288,
+    TRICORE_ADD_A_srr	= 289,
+    TRICORE_ADD_B_rr	= 290,
+    TRICORE_ADD_F_rrr	= 291,
+    TRICORE_ADD_H_rr	= 292,
+    TRICORE_ADD_rc	= 293,
+    TRICORE_ADD_rr	= 294,
+    TRICORE_ADD_src	= 295,
+    TRICORE_ADD_src_15a	= 296,
+    TRICORE_ADD_src_a15	= 297,
+    TRICORE_ADD_srr	= 298,
+    TRICORE_ADD_srr_15a	= 299,
+    TRICORE_ADD_srr_a15	= 300,
+    TRICORE_ANDN_T	= 301,
+    TRICORE_ANDN_rc	= 302,
+    TRICORE_ANDN_rr	= 303,
+    TRICORE_AND_ANDN_T	= 304,
+    TRICORE_AND_AND_T	= 305,
+    TRICORE_AND_EQ_rc	= 306,
+    TRICORE_AND_EQ_rr	= 307,
+    TRICORE_AND_GE_U_rc	= 308,
+    TRICORE_AND_GE_U_rr	= 309,
+    TRICORE_AND_GE_rc	= 310,
+    TRICORE_AND_GE_rr	= 311,
+    TRICORE_AND_LT_U_rc	= 312,
+    TRICORE_AND_LT_U_rr	= 313,
+    TRICORE_AND_LT_rc	= 314,
+    TRICORE_AND_LT_rr	= 315,
+    TRICORE_AND_NE_rc	= 316,
+    TRICORE_AND_NE_rr	= 317,
+    TRICORE_AND_NOR_T	= 318,
+    TRICORE_AND_OR_T	= 319,
+    TRICORE_AND_T	= 320,
+    TRICORE_AND_rc	= 321,
+    TRICORE_AND_rr	= 322,
+    TRICORE_AND_sc	= 323,
+    TRICORE_AND_sc_v110	= 324,
+    TRICORE_AND_srr	= 325,
+    TRICORE_AND_srr_v110	= 326,
+    TRICORE_BISR_rc	= 327,
+    TRICORE_BISR_rc_v161	= 328,
+    TRICORE_BISR_sc	= 329,
+    TRICORE_BISR_sc_v110	= 330,
+    TRICORE_BMERGAE_rr_v110	= 331,
+    TRICORE_BMERGE_rr	= 332,
+    TRICORE_BSPLIT_rr	= 333,
+    TRICORE_BSPLIT_rr_v110	= 334,
+    TRICORE_CACHEA_I_bo_bso	= 335,
+    TRICORE_CACHEA_I_bo_c	= 336,
+    TRICORE_CACHEA_I_bo_pos	= 337,
+    TRICORE_CACHEA_I_bo_pre	= 338,
+    TRICORE_CACHEA_I_bo_r	= 339,
+    TRICORE_CACHEA_WI_bo_bso	= 340,
+    TRICORE_CACHEA_WI_bo_c	= 341,
+    TRICORE_CACHEA_WI_bo_pos	= 342,
+    TRICORE_CACHEA_WI_bo_pre	= 343,
+    TRICORE_CACHEA_WI_bo_r	= 344,
+    TRICORE_CACHEA_W_bo_bso	= 345,
+    TRICORE_CACHEA_W_bo_c	= 346,
+    TRICORE_CACHEA_W_bo_pos	= 347,
+    TRICORE_CACHEA_W_bo_pre	= 348,
+    TRICORE_CACHEA_W_bo_r	= 349,
+    TRICORE_CACHEI_I_bo_bso	= 350,
+    TRICORE_CACHEI_I_bo_pos	= 351,
+    TRICORE_CACHEI_I_bo_pre	= 352,
+    TRICORE_CACHEI_WI_bo_bso	= 353,
+    TRICORE_CACHEI_WI_bo_pos	= 354,
+    TRICORE_CACHEI_WI_bo_pre	= 355,
+    TRICORE_CACHEI_W_bo_bso	= 356,
+    TRICORE_CACHEI_W_bo_pos	= 357,
+    TRICORE_CACHEI_W_bo_pre	= 358,
+    TRICORE_CADDN_A_rcr_v110	= 359,
+    TRICORE_CADDN_A_rrr_v110	= 360,
+    TRICORE_CADDN_rcr	= 361,
+    TRICORE_CADDN_rrr	= 362,
+    TRICORE_CADDN_src	= 363,
+    TRICORE_CADDN_srr_v110	= 364,
+    TRICORE_CADD_A_rcr_v110	= 365,
+    TRICORE_CADD_A_rrr_v110	= 366,
+    TRICORE_CADD_rcr	= 367,
+    TRICORE_CADD_rrr	= 368,
+    TRICORE_CADD_src	= 369,
+    TRICORE_CADD_srr_v110	= 370,
+    TRICORE_CALLA_b	= 371,
+    TRICORE_CALLI_rr	= 372,
+    TRICORE_CALLI_rr_v110	= 373,
+    TRICORE_CALL_b	= 374,
+    TRICORE_CALL_sb	= 375,
+    TRICORE_CLO_B_rr_v110	= 376,
+    TRICORE_CLO_H_rr	= 377,
+    TRICORE_CLO_rr	= 378,
+    TRICORE_CLS_B_rr_v110	= 379,
+    TRICORE_CLS_H_rr	= 380,
+    TRICORE_CLS_rr	= 381,
+    TRICORE_CLZ_B_rr_v110	= 382,
+    TRICORE_CLZ_H_rr	= 383,
+    TRICORE_CLZ_rr	= 384,
+    TRICORE_CMOVN_src	= 385,
+    TRICORE_CMOVN_srr	= 386,
+    TRICORE_CMOV_src	= 387,
+    TRICORE_CMOV_srr	= 388,
+    TRICORE_CMPSWAP_W_bo_bso	= 389,
+    TRICORE_CMPSWAP_W_bo_c	= 390,
+    TRICORE_CMPSWAP_W_bo_pos	= 391,
+    TRICORE_CMPSWAP_W_bo_pre	= 392,
+    TRICORE_CMPSWAP_W_bo_r	= 393,
+    TRICORE_CMP_F_rr	= 394,
+    TRICORE_CRC32B_W_rr	= 395,
+    TRICORE_CRC32L_W_rr	= 396,
+    TRICORE_CRC32_B_rr	= 397,
+    TRICORE_CRCN_rrr	= 398,
+    TRICORE_CSUBN_A__rrr_v110	= 399,
+    TRICORE_CSUBN_rrr	= 400,
+    TRICORE_CSUB_A__rrr_v110	= 401,
+    TRICORE_CSUB_rrr	= 402,
+    TRICORE_DEBUG_sr	= 403,
+    TRICORE_DEBUG_sys	= 404,
+    TRICORE_DEXTR_rrpw	= 405,
+    TRICORE_DEXTR_rrrr	= 406,
+    TRICORE_DIFSC_A_rr_v110	= 407,
+    TRICORE_DISABLE_sys	= 408,
+    TRICORE_DISABLE_sys_1	= 409,
+    TRICORE_DIV_F_rr	= 410,
+    TRICORE_DIV_U_rr	= 411,
+    TRICORE_DIV_rr	= 412,
+    TRICORE_DSYNC_sys	= 413,
+    TRICORE_DVADJ_rrr	= 414,
+    TRICORE_DVADJ_rrr_v110	= 415,
+    TRICORE_DVADJ_srr_v110	= 416,
+    TRICORE_DVINIT_BU_rr	= 417,
+    TRICORE_DVINIT_BU_rr_v110	= 418,
+    TRICORE_DVINIT_B_rr	= 419,
+    TRICORE_DVINIT_B_rr_v110	= 420,
+    TRICORE_DVINIT_HU_rr	= 421,
+    TRICORE_DVINIT_HU_rr_v110	= 422,
+    TRICORE_DVINIT_H_rr	= 423,
+    TRICORE_DVINIT_H_rr_v110	= 424,
+    TRICORE_DVINIT_U_rr	= 425,
+    TRICORE_DVINIT_U_rr_v110	= 426,
+    TRICORE_DVINIT_rr	= 427,
+    TRICORE_DVINIT_rr_v110	= 428,
+    TRICORE_DVSTEP_U_rrr	= 429,
+    TRICORE_DVSTEP_U_rrrv110	= 430,
+    TRICORE_DVSTEP_Uv110	= 431,
+    TRICORE_DVSTEP_rrr	= 432,
+    TRICORE_DVSTEP_rrrv110	= 433,
+    TRICORE_DVSTEPv110	= 434,
+    TRICORE_ENABLE_sys	= 435,
+    TRICORE_EQANY_B_rc	= 436,
+    TRICORE_EQANY_B_rr	= 437,
+    TRICORE_EQANY_H_rc	= 438,
+    TRICORE_EQANY_H_rr	= 439,
+    TRICORE_EQZ_A_rr	= 440,
+    TRICORE_EQ_A_rr	= 441,
+    TRICORE_EQ_B_rr	= 442,
+    TRICORE_EQ_H_rr	= 443,
+    TRICORE_EQ_W_rr	= 444,
+    TRICORE_EQ_rc	= 445,
+    TRICORE_EQ_rr	= 446,
+    TRICORE_EQ_src	= 447,
+    TRICORE_EQ_srr	= 448,
+    TRICORE_EXTR_U_rrpw	= 449,
+    TRICORE_EXTR_U_rrrr	= 450,
+    TRICORE_EXTR_U_rrrw	= 451,
+    TRICORE_EXTR_rrpw	= 452,
+    TRICORE_EXTR_rrrr	= 453,
+    TRICORE_EXTR_rrrw	= 454,
+    TRICORE_FCALLA_b	= 455,
+    TRICORE_FCALLA_i	= 456,
+    TRICORE_FCALL_b	= 457,
+    TRICORE_FRET_sr	= 458,
+    TRICORE_FRET_sys	= 459,
+    TRICORE_FTOHP_rr	= 460,
+    TRICORE_FTOIZ_rr	= 461,
+    TRICORE_FTOI_rr	= 462,
+    TRICORE_FTOQ31Z_rr	= 463,
+    TRICORE_FTOQ31_rr	= 464,
+    TRICORE_FTOUZ_rr	= 465,
+    TRICORE_FTOU_rr	= 466,
+    TRICORE_GE_A_rr	= 467,
+    TRICORE_GE_U_rc	= 468,
+    TRICORE_GE_U_rr	= 469,
+    TRICORE_GE_rc	= 470,
+    TRICORE_GE_rr	= 471,
+    TRICORE_HPTOF_rr	= 472,
+    TRICORE_IMASK_rcpw	= 473,
+    TRICORE_IMASK_rcrw	= 474,
+    TRICORE_IMASK_rrpw	= 475,
+    TRICORE_IMASK_rrrw	= 476,
+    TRICORE_INSERT_rcpw	= 477,
+    TRICORE_INSERT_rcrr	= 478,
+    TRICORE_INSERT_rcrw	= 479,
+    TRICORE_INSERT_rrpw	= 480,
+    TRICORE_INSERT_rrrr	= 481,
+    TRICORE_INSERT_rrrw	= 482,
+    TRICORE_INSN_T	= 483,
+    TRICORE_INS_T	= 484,
+    TRICORE_ISYNC_sys	= 485,
+    TRICORE_ITOF_rr	= 486,
+    TRICORE_IXMAX_U_rrr	= 487,
+    TRICORE_IXMAX_rrr	= 488,
+    TRICORE_IXMIN_U_rrr	= 489,
+    TRICORE_IXMIN_rrr	= 490,
+    TRICORE_JA_b	= 491,
+    TRICORE_JEQ_A_brr	= 492,
+    TRICORE_JEQ_brc	= 493,
+    TRICORE_JEQ_brr	= 494,
+    TRICORE_JEQ_sbc1	= 495,
+    TRICORE_JEQ_sbc2	= 496,
+    TRICORE_JEQ_sbc_v110	= 497,
+    TRICORE_JEQ_sbr1	= 498,
+    TRICORE_JEQ_sbr2	= 499,
+    TRICORE_JEQ_sbr_v110	= 500,
+    TRICORE_JGEZ_sbr	= 501,
+    TRICORE_JGEZ_sbr_v110	= 502,
+    TRICORE_JGE_U_brc	= 503,
+    TRICORE_JGE_U_brr	= 504,
+    TRICORE_JGE_brc	= 505,
+    TRICORE_JGE_brr	= 506,
+    TRICORE_JGTZ_sbr	= 507,
+    TRICORE_JGTZ_sbr_v110	= 508,
+    TRICORE_JI_rr	= 509,
+    TRICORE_JI_rr_v110	= 510,
+    TRICORE_JI_sbr_v110	= 511,
+    TRICORE_JI_sr	= 512,
+    TRICORE_JLA_b	= 513,
+    TRICORE_JLEZ_sbr	= 514,
+    TRICORE_JLEZ_sbr_v110	= 515,
+    TRICORE_JLI_rr	= 516,
+    TRICORE_JLI_rr_v110	= 517,
+    TRICORE_JLTZ_sbr	= 518,
+    TRICORE_JLTZ_sbr_v110	= 519,
+    TRICORE_JLT_U_brc	= 520,
+    TRICORE_JLT_U_brr	= 521,
+    TRICORE_JLT_brc	= 522,
+    TRICORE_JLT_brr	= 523,
+    TRICORE_JL_b	= 524,
+    TRICORE_JNED_brc	= 525,
+    TRICORE_JNED_brr	= 526,
+    TRICORE_JNEI_brc	= 527,
+    TRICORE_JNEI_brr	= 528,
+    TRICORE_JNE_A_brr	= 529,
+    TRICORE_JNE_brc	= 530,
+    TRICORE_JNE_brr	= 531,
+    TRICORE_JNE_sbc1	= 532,
+    TRICORE_JNE_sbc2	= 533,
+    TRICORE_JNE_sbc_v110	= 534,
+    TRICORE_JNE_sbr1	= 535,
+    TRICORE_JNE_sbr2	= 536,
+    TRICORE_JNE_sbr_v110	= 537,
+    TRICORE_JNZ_A_brr	= 538,
+    TRICORE_JNZ_A_sbr	= 539,
+    TRICORE_JNZ_T_brn	= 540,
+    TRICORE_JNZ_T_sbrn	= 541,
+    TRICORE_JNZ_T_sbrn_v110	= 542,
+    TRICORE_JNZ_sb	= 543,
+    TRICORE_JNZ_sb_v110	= 544,
+    TRICORE_JNZ_sbr	= 545,
+    TRICORE_JNZ_sbr_v110	= 546,
+    TRICORE_JZ_A_brr	= 547,
+    TRICORE_JZ_A_sbr	= 548,
+    TRICORE_JZ_T_brn	= 549,
+    TRICORE_JZ_T_sbrn	= 550,
+    TRICORE_JZ_T_sbrn_v110	= 551,
+    TRICORE_JZ_sb	= 552,
+    TRICORE_JZ_sb_v110	= 553,
+    TRICORE_JZ_sbr	= 554,
+    TRICORE_JZ_sbr_v110	= 555,
+    TRICORE_J_b	= 556,
+    TRICORE_J_sb	= 557,
+    TRICORE_J_sb_v110	= 558,
+    TRICORE_LDLCX_abs	= 559,
+    TRICORE_LDLCX_bo_bso	= 560,
+    TRICORE_LDMST_abs	= 561,
+    TRICORE_LDMST_bo_bso	= 562,
+    TRICORE_LDMST_bo_c	= 563,
+    TRICORE_LDMST_bo_pos	= 564,
+    TRICORE_LDMST_bo_pre	= 565,
+    TRICORE_LDMST_bo_r	= 566,
+    TRICORE_LDUCX_abs	= 567,
+    TRICORE_LDUCX_bo_bso	= 568,
+    TRICORE_LD_A_abs	= 569,
+    TRICORE_LD_A_bo_bso	= 570,
+    TRICORE_LD_A_bo_c	= 571,
+    TRICORE_LD_A_bo_pos	= 572,
+    TRICORE_LD_A_bo_pre	= 573,
+    TRICORE_LD_A_bo_r	= 574,
+    TRICORE_LD_A_bol	= 575,
+    TRICORE_LD_A_sc	= 576,
+    TRICORE_LD_A_slr	= 577,
+    TRICORE_LD_A_slr_post	= 578,
+    TRICORE_LD_A_slr_post_v110	= 579,
+    TRICORE_LD_A_slr_v110	= 580,
+    TRICORE_LD_A_slro	= 581,
+    TRICORE_LD_A_slro_v110	= 582,
+    TRICORE_LD_A_sro	= 583,
+    TRICORE_LD_A_sro_v110	= 584,
+    TRICORE_LD_BU_abs	= 585,
+    TRICORE_LD_BU_bo_bso	= 586,
+    TRICORE_LD_BU_bo_c	= 587,
+    TRICORE_LD_BU_bo_pos	= 588,
+    TRICORE_LD_BU_bo_pre	= 589,
+    TRICORE_LD_BU_bo_r	= 590,
+    TRICORE_LD_BU_bol	= 591,
+    TRICORE_LD_BU_slr	= 592,
+    TRICORE_LD_BU_slr_post	= 593,
+    TRICORE_LD_BU_slr_post_v110	= 594,
+    TRICORE_LD_BU_slr_v110	= 595,
+    TRICORE_LD_BU_slro	= 596,
+    TRICORE_LD_BU_slro_v110	= 597,
+    TRICORE_LD_BU_sro	= 598,
+    TRICORE_LD_BU_sro_v110	= 599,
+    TRICORE_LD_B_abs	= 600,
+    TRICORE_LD_B_bo_bso	= 601,
+    TRICORE_LD_B_bo_c	= 602,
+    TRICORE_LD_B_bo_pos	= 603,
+    TRICORE_LD_B_bo_pre	= 604,
+    TRICORE_LD_B_bo_r	= 605,
+    TRICORE_LD_B_bol	= 606,
+    TRICORE_LD_B_slr_post_v110	= 607,
+    TRICORE_LD_B_slr_v110	= 608,
+    TRICORE_LD_B_slro_v110	= 609,
+    TRICORE_LD_B_sro_v110	= 610,
+    TRICORE_LD_DA_abs	= 611,
+    TRICORE_LD_DA_bo_bso	= 612,
+    TRICORE_LD_DA_bo_c	= 613,
+    TRICORE_LD_DA_bo_pos	= 614,
+    TRICORE_LD_DA_bo_pre	= 615,
+    TRICORE_LD_DA_bo_r	= 616,
+    TRICORE_LD_D_abs	= 617,
+    TRICORE_LD_D_bo_bso	= 618,
+    TRICORE_LD_D_bo_c	= 619,
+    TRICORE_LD_D_bo_pos	= 620,
+    TRICORE_LD_D_bo_pre	= 621,
+    TRICORE_LD_D_bo_r	= 622,
+    TRICORE_LD_HU_abs	= 623,
+    TRICORE_LD_HU_bo_bso	= 624,
+    TRICORE_LD_HU_bo_c	= 625,
+    TRICORE_LD_HU_bo_pos	= 626,
+    TRICORE_LD_HU_bo_pre	= 627,
+    TRICORE_LD_HU_bo_r	= 628,
+    TRICORE_LD_HU_bol	= 629,
+    TRICORE_LD_H_abs	= 630,
+    TRICORE_LD_H_bo_bso	= 631,
+    TRICORE_LD_H_bo_c	= 632,
+    TRICORE_LD_H_bo_pos	= 633,
+    TRICORE_LD_H_bo_pre	= 634,
+    TRICORE_LD_H_bo_r	= 635,
+    TRICORE_LD_H_bol	= 636,
+    TRICORE_LD_H_slr	= 637,
+    TRICORE_LD_H_slr_post	= 638,
+    TRICORE_LD_H_slr_post_v110	= 639,
+    TRICORE_LD_H_slr_v110	= 640,
+    TRICORE_LD_H_slro	= 641,
+    TRICORE_LD_H_slro_v110	= 642,
+    TRICORE_LD_H_sro	= 643,
+    TRICORE_LD_H_sro_v110	= 644,
+    TRICORE_LD_Q_abs	= 645,
+    TRICORE_LD_Q_bo_bso	= 646,
+    TRICORE_LD_Q_bo_c	= 647,
+    TRICORE_LD_Q_bo_pos	= 648,
+    TRICORE_LD_Q_bo_pre	= 649,
+    TRICORE_LD_Q_bo_r	= 650,
+    TRICORE_LD_W_abs	= 651,
+    TRICORE_LD_W_bo_bso	= 652,
+    TRICORE_LD_W_bo_c	= 653,
+    TRICORE_LD_W_bo_pos	= 654,
+    TRICORE_LD_W_bo_pre	= 655,
+    TRICORE_LD_W_bo_r	= 656,
+    TRICORE_LD_W_bol	= 657,
+    TRICORE_LD_W_sc	= 658,
+    TRICORE_LD_W_slr	= 659,
+    TRICORE_LD_W_slr_post	= 660,
+    TRICORE_LD_W_slr_post_v110	= 661,
+    TRICORE_LD_W_slr_v110	= 662,
+    TRICORE_LD_W_slro	= 663,
+    TRICORE_LD_W_slro_v110	= 664,
+    TRICORE_LD_W_sro	= 665,
+    TRICORE_LD_W_sro_v110	= 666,
+    TRICORE_LEA_abs	= 667,
+    TRICORE_LEA_bo_bso	= 668,
+    TRICORE_LEA_bol	= 669,
+    TRICORE_LHA_abs	= 670,
+    TRICORE_LOOPU_brr	= 671,
+    TRICORE_LOOP_brr	= 672,
+    TRICORE_LOOP_sbr	= 673,
+    TRICORE_LT_A_rr	= 674,
+    TRICORE_LT_B	= 675,
+    TRICORE_LT_BU	= 676,
+    TRICORE_LT_H	= 677,
+    TRICORE_LT_HU	= 678,
+    TRICORE_LT_U_rc	= 679,
+    TRICORE_LT_U_rr	= 680,
+    TRICORE_LT_U_srcv110	= 681,
+    TRICORE_LT_U_srrv110	= 682,
+    TRICORE_LT_W	= 683,
+    TRICORE_LT_WU	= 684,
+    TRICORE_LT_rc	= 685,
+    TRICORE_LT_rr	= 686,
+    TRICORE_LT_src	= 687,
+    TRICORE_LT_srr	= 688,
+    TRICORE_MADDMS_H_rrr1_LL	= 689,
+    TRICORE_MADDMS_H_rrr1_LU	= 690,
+    TRICORE_MADDMS_H_rrr1_UL	= 691,
+    TRICORE_MADDMS_H_rrr1_UU	= 692,
+    TRICORE_MADDMS_U_rcr_v110	= 693,
+    TRICORE_MADDMS_U_rrr2_v110	= 694,
+    TRICORE_MADDMS_rcr_v110	= 695,
+    TRICORE_MADDMS_rrr2_v110	= 696,
+    TRICORE_MADDM_H_rrr1_LL	= 697,
+    TRICORE_MADDM_H_rrr1_LU	= 698,
+    TRICORE_MADDM_H_rrr1_UL	= 699,
+    TRICORE_MADDM_H_rrr1_UU	= 700,
+    TRICORE_MADDM_H_rrr1_v110	= 701,
+    TRICORE_MADDM_Q_rrr1_v110	= 702,
+    TRICORE_MADDM_U_rcr_v110	= 703,
+    TRICORE_MADDM_U_rrr2_v110	= 704,
+    TRICORE_MADDM_rcr_v110	= 705,
+    TRICORE_MADDM_rrr2_v110	= 706,
+    TRICORE_MADDRS_H_rrr1_LL	= 707,
+    TRICORE_MADDRS_H_rrr1_LU	= 708,
+    TRICORE_MADDRS_H_rrr1_UL	= 709,
+    TRICORE_MADDRS_H_rrr1_UL_2	= 710,
+    TRICORE_MADDRS_H_rrr1_UU	= 711,
+    TRICORE_MADDRS_H_rrr1_v110	= 712,
+    TRICORE_MADDRS_Q_rrr1_L_L	= 713,
+    TRICORE_MADDRS_Q_rrr1_U_U	= 714,
+    TRICORE_MADDRS_Q_rrr1_v110	= 715,
+    TRICORE_MADDR_H_rrr1_LL	= 716,
+    TRICORE_MADDR_H_rrr1_LU	= 717,
+    TRICORE_MADDR_H_rrr1_UL	= 718,
+    TRICORE_MADDR_H_rrr1_UL_2	= 719,
+    TRICORE_MADDR_H_rrr1_UU	= 720,
+    TRICORE_MADDR_H_rrr1_v110	= 721,
+    TRICORE_MADDR_Q_rrr1_L_L	= 722,
+    TRICORE_MADDR_Q_rrr1_U_U	= 723,
+    TRICORE_MADDR_Q_rrr1_v110	= 724,
+    TRICORE_MADDSUMS_H_rrr1_LL	= 725,
+    TRICORE_MADDSUMS_H_rrr1_LU	= 726,
+    TRICORE_MADDSUMS_H_rrr1_UL	= 727,
+    TRICORE_MADDSUMS_H_rrr1_UU	= 728,
+    TRICORE_MADDSUM_H_rrr1_LL	= 729,
+    TRICORE_MADDSUM_H_rrr1_LU	= 730,
+    TRICORE_MADDSUM_H_rrr1_UL	= 731,
+    TRICORE_MADDSUM_H_rrr1_UU	= 732,
+    TRICORE_MADDSURS_H_rrr1_LL	= 733,
+    TRICORE_MADDSURS_H_rrr1_LU	= 734,
+    TRICORE_MADDSURS_H_rrr1_UL	= 735,
+    TRICORE_MADDSURS_H_rrr1_UU	= 736,
+    TRICORE_MADDSUR_H_rrr1_LL	= 737,
+    TRICORE_MADDSUR_H_rrr1_LU	= 738,
+    TRICORE_MADDSUR_H_rrr1_UL	= 739,
+    TRICORE_MADDSUR_H_rrr1_UU	= 740,
+    TRICORE_MADDSUS_H_rrr1_LL	= 741,
+    TRICORE_MADDSUS_H_rrr1_LU	= 742,
+    TRICORE_MADDSUS_H_rrr1_UL	= 743,
+    TRICORE_MADDSUS_H_rrr1_UU	= 744,
+    TRICORE_MADDSU_H_rrr1_LL	= 745,
+    TRICORE_MADDSU_H_rrr1_LU	= 746,
+    TRICORE_MADDSU_H_rrr1_UL	= 747,
+    TRICORE_MADDSU_H_rrr1_UU	= 748,
+    TRICORE_MADDS_H_rrr1_LL	= 749,
+    TRICORE_MADDS_H_rrr1_LU	= 750,
+    TRICORE_MADDS_H_rrr1_UL	= 751,
+    TRICORE_MADDS_H_rrr1_UU	= 752,
+    TRICORE_MADDS_H_rrr1_v110	= 753,
+    TRICORE_MADDS_Q_rrr1	= 754,
+    TRICORE_MADDS_Q_rrr1_L	= 755,
+    TRICORE_MADDS_Q_rrr1_L_L	= 756,
+    TRICORE_MADDS_Q_rrr1_U	= 757,
+    TRICORE_MADDS_Q_rrr1_UU2_v110	= 758,
+    TRICORE_MADDS_Q_rrr1_U_U	= 759,
+    TRICORE_MADDS_Q_rrr1_e	= 760,
+    TRICORE_MADDS_Q_rrr1_e_L	= 761,
+    TRICORE_MADDS_Q_rrr1_e_L_L	= 762,
+    TRICORE_MADDS_Q_rrr1_e_U	= 763,
+    TRICORE_MADDS_Q_rrr1_e_U_U	= 764,
+    TRICORE_MADDS_U_rcr	= 765,
+    TRICORE_MADDS_U_rcr_e	= 766,
+    TRICORE_MADDS_U_rrr2	= 767,
+    TRICORE_MADDS_U_rrr2_e	= 768,
+    TRICORE_MADDS_rcr	= 769,
+    TRICORE_MADDS_rcr_e	= 770,
+    TRICORE_MADDS_rrr2	= 771,
+    TRICORE_MADDS_rrr2_e	= 772,
+    TRICORE_MADD_F_rrr	= 773,
+    TRICORE_MADD_H_rrr1_LL	= 774,
+    TRICORE_MADD_H_rrr1_LU	= 775,
+    TRICORE_MADD_H_rrr1_UL	= 776,
+    TRICORE_MADD_H_rrr1_UU	= 777,
+    TRICORE_MADD_H_rrr1_v110	= 778,
+    TRICORE_MADD_Q_rrr1	= 779,
+    TRICORE_MADD_Q_rrr1_L	= 780,
+    TRICORE_MADD_Q_rrr1_L_L	= 781,
+    TRICORE_MADD_Q_rrr1_U	= 782,
+    TRICORE_MADD_Q_rrr1_UU2_v110	= 783,
+    TRICORE_MADD_Q_rrr1_U_U	= 784,
+    TRICORE_MADD_Q_rrr1_e	= 785,
+    TRICORE_MADD_Q_rrr1_e_L	= 786,
+    TRICORE_MADD_Q_rrr1_e_L_L	= 787,
+    TRICORE_MADD_Q_rrr1_e_U	= 788,
+    TRICORE_MADD_Q_rrr1_e_U_U	= 789,
+    TRICORE_MADD_U_rcr	= 790,
+    TRICORE_MADD_U_rrr2	= 791,
+    TRICORE_MADD_rcr	= 792,
+    TRICORE_MADD_rcr_e	= 793,
+    TRICORE_MADD_rrr2	= 794,
+    TRICORE_MADD_rrr2_e	= 795,
+    TRICORE_MAX_B	= 796,
+    TRICORE_MAX_BU	= 797,
+    TRICORE_MAX_H	= 798,
+    TRICORE_MAX_HU	= 799,
+    TRICORE_MAX_U_rc	= 800,
+    TRICORE_MAX_U_rr	= 801,
+    TRICORE_MAX_rc	= 802,
+    TRICORE_MAX_rr	= 803,
+    TRICORE_MFCR_rlc	= 804,
+    TRICORE_MIN_B	= 805,
+    TRICORE_MIN_BU	= 806,
+    TRICORE_MIN_H	= 807,
+    TRICORE_MIN_HU	= 808,
+    TRICORE_MIN_U_rc	= 809,
+    TRICORE_MIN_U_rr	= 810,
+    TRICORE_MIN_rc	= 811,
+    TRICORE_MIN_rr	= 812,
+    TRICORE_MOVH_A_rlc	= 813,
+    TRICORE_MOVH_rlc	= 814,
+    TRICORE_MOVZ_A_sr	= 815,
+    TRICORE_MOV_AA_rr	= 816,
+    TRICORE_MOV_AA_srr_srr	= 817,
+    TRICORE_MOV_AA_srr_srr_v110	= 818,
+    TRICORE_MOV_A_rr	= 819,
+    TRICORE_MOV_A_src	= 820,
+    TRICORE_MOV_A_srr	= 821,
+    TRICORE_MOV_A_srr_v110	= 822,
+    TRICORE_MOV_D_rr	= 823,
+    TRICORE_MOV_D_srr_srr	= 824,
+    TRICORE_MOV_D_srr_srr_v110	= 825,
+    TRICORE_MOV_U_rlc	= 826,
+    TRICORE_MOV_rlc	= 827,
+    TRICORE_MOV_rlc_e	= 828,
+    TRICORE_MOV_rr	= 829,
+    TRICORE_MOV_rr_e	= 830,
+    TRICORE_MOV_rr_eab	= 831,
+    TRICORE_MOV_sc	= 832,
+    TRICORE_MOV_sc_v110	= 833,
+    TRICORE_MOV_src	= 834,
+    TRICORE_MOV_src_e	= 835,
+    TRICORE_MOV_srr	= 836,
+    TRICORE_MSUBADMS_H_rrr1_LL	= 837,
+    TRICORE_MSUBADMS_H_rrr1_LU	= 838,
+    TRICORE_MSUBADMS_H_rrr1_UL	= 839,
+    TRICORE_MSUBADMS_H_rrr1_UU	= 840,
+    TRICORE_MSUBADM_H_rrr1_LL	= 841,
+    TRICORE_MSUBADM_H_rrr1_LU	= 842,
+    TRICORE_MSUBADM_H_rrr1_UL	= 843,
+    TRICORE_MSUBADM_H_rrr1_UU	= 844,
+    TRICORE_MSUBADRS_H_rrr1_LL	= 845,
+    TRICORE_MSUBADRS_H_rrr1_LU	= 846,
+    TRICORE_MSUBADRS_H_rrr1_UL	= 847,
+    TRICORE_MSUBADRS_H_rrr1_UU	= 848,
+    TRICORE_MSUBADRS_H_rrr1_v110	= 849,
+    TRICORE_MSUBADR_H_rrr1_LL	= 850,
+    TRICORE_MSUBADR_H_rrr1_LU	= 851,
+    TRICORE_MSUBADR_H_rrr1_UL	= 852,
+    TRICORE_MSUBADR_H_rrr1_UU	= 853,
+    TRICORE_MSUBADR_H_rrr1_v110	= 854,
+    TRICORE_MSUBADS_H_rrr1_LL	= 855,
+    TRICORE_MSUBADS_H_rrr1_LU	= 856,
+    TRICORE_MSUBADS_H_rrr1_UL	= 857,
+    TRICORE_MSUBADS_H_rrr1_UU	= 858,
+    TRICORE_MSUBAD_H_rrr1_LL	= 859,
+    TRICORE_MSUBAD_H_rrr1_LU	= 860,
+    TRICORE_MSUBAD_H_rrr1_UL	= 861,
+    TRICORE_MSUBAD_H_rrr1_UU	= 862,
+    TRICORE_MSUBMS_H_rrr1_LL	= 863,
+    TRICORE_MSUBMS_H_rrr1_LU	= 864,
+    TRICORE_MSUBMS_H_rrr1_UL	= 865,
+    TRICORE_MSUBMS_H_rrr1_UU	= 866,
+    TRICORE_MSUBMS_U_rcrv110	= 867,
+    TRICORE_MSUBMS_U_rrr2v110	= 868,
+    TRICORE_MSUBMS_rcrv110	= 869,
+    TRICORE_MSUBMS_rrr2v110	= 870,
+    TRICORE_MSUBM_H_rrr1_LL	= 871,
+    TRICORE_MSUBM_H_rrr1_LU	= 872,
+    TRICORE_MSUBM_H_rrr1_UL	= 873,
+    TRICORE_MSUBM_H_rrr1_UU	= 874,
+    TRICORE_MSUBM_H_rrr1_v110	= 875,
+    TRICORE_MSUBM_Q_rrr1_v110	= 876,
+    TRICORE_MSUBM_U_rcrv110	= 877,
+    TRICORE_MSUBM_U_rrr2v110	= 878,
+    TRICORE_MSUBM_rcrv110	= 879,
+    TRICORE_MSUBM_rrr2v110	= 880,
+    TRICORE_MSUBRS_H_rrr1_LL	= 881,
+    TRICORE_MSUBRS_H_rrr1_LU	= 882,
+    TRICORE_MSUBRS_H_rrr1_UL	= 883,
+    TRICORE_MSUBRS_H_rrr1_UL_2	= 884,
+    TRICORE_MSUBRS_H_rrr1_UU	= 885,
+    TRICORE_MSUBRS_H_rrr1_v110	= 886,
+    TRICORE_MSUBRS_Q_rrr1_L_L	= 887,
+    TRICORE_MSUBRS_Q_rrr1_U_U	= 888,
+    TRICORE_MSUBRS_Q_rrr1_v110	= 889,
+    TRICORE_MSUBR_H_rrr1_LL	= 890,
+    TRICORE_MSUBR_H_rrr1_LU	= 891,
+    TRICORE_MSUBR_H_rrr1_UL	= 892,
+    TRICORE_MSUBR_H_rrr1_UL_2	= 893,
+    TRICORE_MSUBR_H_rrr1_UU	= 894,
+    TRICORE_MSUBR_H_rrr1_v110	= 895,
+    TRICORE_MSUBR_Q_rrr1_L_L	= 896,
+    TRICORE_MSUBR_Q_rrr1_U_U	= 897,
+    TRICORE_MSUBR_Q_rrr1_v110	= 898,
+    TRICORE_MSUBS_H_rrr1_LL	= 899,
+    TRICORE_MSUBS_H_rrr1_LU	= 900,
+    TRICORE_MSUBS_H_rrr1_UL	= 901,
+    TRICORE_MSUBS_H_rrr1_UU	= 902,
+    TRICORE_MSUBS_H_rrr1_v110	= 903,
+    TRICORE_MSUBS_Q_rrr1	= 904,
+    TRICORE_MSUBS_Q_rrr1_L	= 905,
+    TRICORE_MSUBS_Q_rrr1_L_L	= 906,
+    TRICORE_MSUBS_Q_rrr1_U	= 907,
+    TRICORE_MSUBS_Q_rrr1_UU2_v110	= 908,
+    TRICORE_MSUBS_Q_rrr1_U_U	= 909,
+    TRICORE_MSUBS_Q_rrr1_e	= 910,
+    TRICORE_MSUBS_Q_rrr1_e_L	= 911,
+    TRICORE_MSUBS_Q_rrr1_e_L_L	= 912,
+    TRICORE_MSUBS_Q_rrr1_e_U	= 913,
+    TRICORE_MSUBS_Q_rrr1_e_U_U	= 914,
+    TRICORE_MSUBS_U_rcr	= 915,
+    TRICORE_MSUBS_U_rcr_e	= 916,
+    TRICORE_MSUBS_U_rrr2	= 917,
+    TRICORE_MSUBS_U_rrr2_e	= 918,
+    TRICORE_MSUBS_rcr	= 919,
+    TRICORE_MSUBS_rcr_e	= 920,
+    TRICORE_MSUBS_rrr2	= 921,
+    TRICORE_MSUBS_rrr2_e	= 922,
+    TRICORE_MSUB_F_rrr	= 923,
+    TRICORE_MSUB_H_rrr1_LL	= 924,
+    TRICORE_MSUB_H_rrr1_LU	= 925,
+    TRICORE_MSUB_H_rrr1_UL	= 926,
+    TRICORE_MSUB_H_rrr1_UU	= 927,
+    TRICORE_MSUB_H_rrr1_v110	= 928,
+    TRICORE_MSUB_Q_rrr1	= 929,
+    TRICORE_MSUB_Q_rrr1_L	= 930,
+    TRICORE_MSUB_Q_rrr1_L_L	= 931,
+    TRICORE_MSUB_Q_rrr1_U	= 932,
+    TRICORE_MSUB_Q_rrr1_UU2_v110	= 933,
+    TRICORE_MSUB_Q_rrr1_U_U	= 934,
+    TRICORE_MSUB_Q_rrr1_e	= 935,
+    TRICORE_MSUB_Q_rrr1_e_L	= 936,
+    TRICORE_MSUB_Q_rrr1_e_L_L	= 937,
+    TRICORE_MSUB_Q_rrr1_e_U	= 938,
+    TRICORE_MSUB_Q_rrr1_e_U_U	= 939,
+    TRICORE_MSUB_U_rcr	= 940,
+    TRICORE_MSUB_U_rrr2	= 941,
+    TRICORE_MSUB_rcr	= 942,
+    TRICORE_MSUB_rcr_e	= 943,
+    TRICORE_MSUB_rrr2	= 944,
+    TRICORE_MSUB_rrr2_e	= 945,
+    TRICORE_MTCR_rlc	= 946,
+    TRICORE_MULMS_H_rr1_LL2e	= 947,
+    TRICORE_MULMS_H_rr1_LU2e	= 948,
+    TRICORE_MULMS_H_rr1_UL2e	= 949,
+    TRICORE_MULMS_H_rr1_UU2e	= 950,
+    TRICORE_MULM_H_rr1_LL2e	= 951,
+    TRICORE_MULM_H_rr1_LU2e	= 952,
+    TRICORE_MULM_H_rr1_UL2e	= 953,
+    TRICORE_MULM_H_rr1_UU2e	= 954,
+    TRICORE_MULM_U_rc	= 955,
+    TRICORE_MULM_U_rr	= 956,
+    TRICORE_MULM_rc	= 957,
+    TRICORE_MULM_rr	= 958,
+    TRICORE_MULR_H_rr1_LL2e	= 959,
+    TRICORE_MULR_H_rr1_LU2e	= 960,
+    TRICORE_MULR_H_rr1_UL2e	= 961,
+    TRICORE_MULR_H_rr1_UU2e	= 962,
+    TRICORE_MULR_H_rr_v110	= 963,
+    TRICORE_MULR_Q_rr1_2LL	= 964,
+    TRICORE_MULR_Q_rr1_2UU	= 965,
+    TRICORE_MULR_Q_rr_v110	= 966,
+    TRICORE_MULS_U_rc	= 967,
+    TRICORE_MULS_U_rr2	= 968,
+    TRICORE_MULS_U_rr_v110	= 969,
+    TRICORE_MULS_rc	= 970,
+    TRICORE_MULS_rr2	= 971,
+    TRICORE_MULS_rr_v110	= 972,
+    TRICORE_MUL_F_rrr	= 973,
+    TRICORE_MUL_H_rr1_LL2e	= 974,
+    TRICORE_MUL_H_rr1_LU2e	= 975,
+    TRICORE_MUL_H_rr1_UL2e	= 976,
+    TRICORE_MUL_H_rr1_UU2e	= 977,
+    TRICORE_MUL_H_rr_v110	= 978,
+    TRICORE_MUL_Q_rr1_2	= 979,
+    TRICORE_MUL_Q_rr1_2LL	= 980,
+    TRICORE_MUL_Q_rr1_2UU	= 981,
+    TRICORE_MUL_Q_rr1_2_L	= 982,
+    TRICORE_MUL_Q_rr1_2_Le	= 983,
+    TRICORE_MUL_Q_rr1_2_U	= 984,
+    TRICORE_MUL_Q_rr1_2_Ue	= 985,
+    TRICORE_MUL_Q_rr1_2__e	= 986,
+    TRICORE_MUL_Q_rr_v110	= 987,
+    TRICORE_MUL_U_rc	= 988,
+    TRICORE_MUL_U_rr2	= 989,
+    TRICORE_MUL_rc	= 990,
+    TRICORE_MUL_rc_e	= 991,
+    TRICORE_MUL_rr2	= 992,
+    TRICORE_MUL_rr2_e	= 993,
+    TRICORE_MUL_rr_v110	= 994,
+    TRICORE_MUL_srr	= 995,
+    TRICORE_NAND_T	= 996,
+    TRICORE_NAND_rc	= 997,
+    TRICORE_NAND_rr	= 998,
+    TRICORE_NEZ_A	= 999,
+    TRICORE_NE_A	= 1000,
+    TRICORE_NE_rc	= 1001,
+    TRICORE_NE_rr	= 1002,
+    TRICORE_NOP_sr	= 1003,
+    TRICORE_NOP_sys	= 1004,
+    TRICORE_NOR_T	= 1005,
+    TRICORE_NOR_rc	= 1006,
+    TRICORE_NOR_rr	= 1007,
+    TRICORE_NOR_sr	= 1008,
+    TRICORE_NOR_sr_v110	= 1009,
+    TRICORE_NOT_sr_v162	= 1010,
+    TRICORE_ORN_T	= 1011,
+    TRICORE_ORN_rc	= 1012,
+    TRICORE_ORN_rr	= 1013,
+    TRICORE_OR_ANDN_T	= 1014,
+    TRICORE_OR_AND_T	= 1015,
+    TRICORE_OR_EQ_rc	= 1016,
+    TRICORE_OR_EQ_rr	= 1017,
+    TRICORE_OR_GE_U_rc	= 1018,
+    TRICORE_OR_GE_U_rr	= 1019,
+    TRICORE_OR_GE_rc	= 1020,
+    TRICORE_OR_GE_rr	= 1021,
+    TRICORE_OR_LT_U_rc	= 1022,
+    TRICORE_OR_LT_U_rr	= 1023,
+    TRICORE_OR_LT_rc	= 1024,
+    TRICORE_OR_LT_rr	= 1025,
+    TRICORE_OR_NE_rc	= 1026,
+    TRICORE_OR_NE_rr	= 1027,
+    TRICORE_OR_NOR_T	= 1028,
+    TRICORE_OR_OR_T	= 1029,
+    TRICORE_OR_T	= 1030,
+    TRICORE_OR_rc	= 1031,
+    TRICORE_OR_rr	= 1032,
+    TRICORE_OR_sc	= 1033,
+    TRICORE_OR_sc_v110	= 1034,
+    TRICORE_OR_srr	= 1035,
+    TRICORE_OR_srr_v110	= 1036,
+    TRICORE_PACK_rrr	= 1037,
+    TRICORE_PARITY_rr	= 1038,
+    TRICORE_PARITY_rr_v110	= 1039,
+    TRICORE_POPCNT_W_rr	= 1040,
+    TRICORE_Q31TOF_rr	= 1041,
+    TRICORE_QSEED_F_rr	= 1042,
+    TRICORE_RESTORE_sys	= 1043,
+    TRICORE_RET_sr	= 1044,
+    TRICORE_RET_sys	= 1045,
+    TRICORE_RET_sys_v110	= 1046,
+    TRICORE_RFE_sr	= 1047,
+    TRICORE_RFE_sys_sys	= 1048,
+    TRICORE_RFE_sys_sys_v110	= 1049,
+    TRICORE_RFM_sys	= 1050,
+    TRICORE_RSLCX_sys	= 1051,
+    TRICORE_RSTV_sys	= 1052,
+    TRICORE_RSUBS_U_rc	= 1053,
+    TRICORE_RSUBS_rc	= 1054,
+    TRICORE_RSUB_rc	= 1055,
+    TRICORE_RSUB_sr_sr	= 1056,
+    TRICORE_RSUB_sr_sr_v110	= 1057,
+    TRICORE_SAT_BU_rr	= 1058,
+    TRICORE_SAT_BU_sr	= 1059,
+    TRICORE_SAT_BU_sr_v110	= 1060,
+    TRICORE_SAT_B_rr	= 1061,
+    TRICORE_SAT_B_sr	= 1062,
+    TRICORE_SAT_B_sr_v110	= 1063,
+    TRICORE_SAT_HU_rr	= 1064,
+    TRICORE_SAT_HU_sr	= 1065,
+    TRICORE_SAT_HU_sr_v110	= 1066,
+    TRICORE_SAT_H_rr	= 1067,
+    TRICORE_SAT_H_sr	= 1068,
+    TRICORE_SAT_H_sr_v110	= 1069,
+    TRICORE_SELN_A_rcr_v110	= 1070,
+    TRICORE_SELN_A_rrr_v110	= 1071,
+    TRICORE_SELN_rcr	= 1072,
+    TRICORE_SELN_rrr	= 1073,
+    TRICORE_SEL_A_rcr_v110	= 1074,
+    TRICORE_SEL_A_rrr_v110	= 1075,
+    TRICORE_SEL_rcr	= 1076,
+    TRICORE_SEL_rrr	= 1077,
+    TRICORE_SHAS_rc	= 1078,
+    TRICORE_SHAS_rr	= 1079,
+    TRICORE_SHA_B_rc	= 1080,
+    TRICORE_SHA_B_rr	= 1081,
+    TRICORE_SHA_H_rc	= 1082,
+    TRICORE_SHA_H_rr	= 1083,
+    TRICORE_SHA_rc	= 1084,
+    TRICORE_SHA_rr	= 1085,
+    TRICORE_SHA_src	= 1086,
+    TRICORE_SHA_src_v110	= 1087,
+    TRICORE_SHUFFLE_rc	= 1088,
+    TRICORE_SH_ANDN_T	= 1089,
+    TRICORE_SH_AND_T	= 1090,
+    TRICORE_SH_B_rc	= 1091,
+    TRICORE_SH_B_rr	= 1092,
+    TRICORE_SH_EQ_rc	= 1093,
+    TRICORE_SH_EQ_rr	= 1094,
+    TRICORE_SH_GE_U_rc	= 1095,
+    TRICORE_SH_GE_U_rr	= 1096,
+    TRICORE_SH_GE_rc	= 1097,
+    TRICORE_SH_GE_rr	= 1098,
+    TRICORE_SH_H_rc	= 1099,
+    TRICORE_SH_H_rr	= 1100,
+    TRICORE_SH_LT_U_rc	= 1101,
+    TRICORE_SH_LT_U_rr	= 1102,
+    TRICORE_SH_LT_rc	= 1103,
+    TRICORE_SH_LT_rr	= 1104,
+    TRICORE_SH_NAND_T	= 1105,
+    TRICORE_SH_NE_rc	= 1106,
+    TRICORE_SH_NE_rr	= 1107,
+    TRICORE_SH_NOR_T	= 1108,
+    TRICORE_SH_ORN_T	= 1109,
+    TRICORE_SH_OR_T	= 1110,
+    TRICORE_SH_XNOR_T	= 1111,
+    TRICORE_SH_XOR_T	= 1112,
+    TRICORE_SH_rc	= 1113,
+    TRICORE_SH_rr	= 1114,
+    TRICORE_SH_src	= 1115,
+    TRICORE_SH_src_v110	= 1116,
+    TRICORE_STLCX_abs	= 1117,
+    TRICORE_STLCX_bo_bso	= 1118,
+    TRICORE_STUCX_abs	= 1119,
+    TRICORE_STUCX_bo_bso	= 1120,
+    TRICORE_ST_A_abs	= 1121,
+    TRICORE_ST_A_bo_bso	= 1122,
+    TRICORE_ST_A_bo_c	= 1123,
+    TRICORE_ST_A_bo_pos	= 1124,
+    TRICORE_ST_A_bo_pre	= 1125,
+    TRICORE_ST_A_bo_r	= 1126,
+    TRICORE_ST_A_bol	= 1127,
+    TRICORE_ST_A_sc	= 1128,
+    TRICORE_ST_A_sro	= 1129,
+    TRICORE_ST_A_sro_v110	= 1130,
+    TRICORE_ST_A_ssr	= 1131,
+    TRICORE_ST_A_ssr_pos	= 1132,
+    TRICORE_ST_A_ssr_pos_v110	= 1133,
+    TRICORE_ST_A_ssr_v110	= 1134,
+    TRICORE_ST_A_ssro	= 1135,
+    TRICORE_ST_A_ssro_v110	= 1136,
+    TRICORE_ST_B_abs	= 1137,
+    TRICORE_ST_B_bo_bso	= 1138,
+    TRICORE_ST_B_bo_c	= 1139,
+    TRICORE_ST_B_bo_pos	= 1140,
+    TRICORE_ST_B_bo_pre	= 1141,
+    TRICORE_ST_B_bo_r	= 1142,
+    TRICORE_ST_B_bol	= 1143,
+    TRICORE_ST_B_sro	= 1144,
+    TRICORE_ST_B_sro_v110	= 1145,
+    TRICORE_ST_B_ssr	= 1146,
+    TRICORE_ST_B_ssr_pos	= 1147,
+    TRICORE_ST_B_ssr_pos_v110	= 1148,
+    TRICORE_ST_B_ssr_v110	= 1149,
+    TRICORE_ST_B_ssro	= 1150,
+    TRICORE_ST_B_ssro_v110	= 1151,
+    TRICORE_ST_DA_abs	= 1152,
+    TRICORE_ST_DA_bo_bso	= 1153,
+    TRICORE_ST_DA_bo_c	= 1154,
+    TRICORE_ST_DA_bo_pos	= 1155,
+    TRICORE_ST_DA_bo_pre	= 1156,
+    TRICORE_ST_DA_bo_r	= 1157,
+    TRICORE_ST_D_abs	= 1158,
+    TRICORE_ST_D_bo_bso	= 1159,
+    TRICORE_ST_D_bo_c	= 1160,
+    TRICORE_ST_D_bo_pos	= 1161,
+    TRICORE_ST_D_bo_pre	= 1162,
+    TRICORE_ST_D_bo_r	= 1163,
+    TRICORE_ST_H_abs	= 1164,
+    TRICORE_ST_H_bo_bso	= 1165,
+    TRICORE_ST_H_bo_c	= 1166,
+    TRICORE_ST_H_bo_pos	= 1167,
+    TRICORE_ST_H_bo_pre	= 1168,
+    TRICORE_ST_H_bo_r	= 1169,
+    TRICORE_ST_H_bol	= 1170,
+    TRICORE_ST_H_sro	= 1171,
+    TRICORE_ST_H_sro_v110	= 1172,
+    TRICORE_ST_H_ssr	= 1173,
+    TRICORE_ST_H_ssr_pos	= 1174,
+    TRICORE_ST_H_ssr_pos_v110	= 1175,
+    TRICORE_ST_H_ssr_v110	= 1176,
+    TRICORE_ST_H_ssro	= 1177,
+    TRICORE_ST_H_ssro_v110	= 1178,
+    TRICORE_ST_Q_abs	= 1179,
+    TRICORE_ST_Q_bo_bso	= 1180,
+    TRICORE_ST_Q_bo_c	= 1181,
+    TRICORE_ST_Q_bo_pos	= 1182,
+    TRICORE_ST_Q_bo_pre	= 1183,
+    TRICORE_ST_Q_bo_r	= 1184,
+    TRICORE_ST_T	= 1185,
+    TRICORE_ST_W_abs	= 1186,
+    TRICORE_ST_W_bo_bso	= 1187,
+    TRICORE_ST_W_bo_c	= 1188,
+    TRICORE_ST_W_bo_pos	= 1189,
+    TRICORE_ST_W_bo_pre	= 1190,
+    TRICORE_ST_W_bo_r	= 1191,
+    TRICORE_ST_W_bol	= 1192,
+    TRICORE_ST_W_sc	= 1193,
+    TRICORE_ST_W_sro	= 1194,
+    TRICORE_ST_W_sro_v110	= 1195,
+    TRICORE_ST_W_ssr	= 1196,
+    TRICORE_ST_W_ssr_pos	= 1197,
+    TRICORE_ST_W_ssr_pos_v110	= 1198,
+    TRICORE_ST_W_ssr_v110	= 1199,
+    TRICORE_ST_W_ssro	= 1200,
+    TRICORE_ST_W_ssro_v110	= 1201,
+    TRICORE_SUBC_rr	= 1202,
+    TRICORE_SUBSC_A_rr	= 1203,
+    TRICORE_SUBS_BU_rr	= 1204,
+    TRICORE_SUBS_B_rr	= 1205,
+    TRICORE_SUBS_HU_rr	= 1206,
+    TRICORE_SUBS_H_rr	= 1207,
+    TRICORE_SUBS_U_rr	= 1208,
+    TRICORE_SUBS_rr	= 1209,
+    TRICORE_SUBS_srr	= 1210,
+    TRICORE_SUBX_rr	= 1211,
+    TRICORE_SUB_A_rr	= 1212,
+    TRICORE_SUB_A_sc	= 1213,
+    TRICORE_SUB_A_sc_v110	= 1214,
+    TRICORE_SUB_B_rr	= 1215,
+    TRICORE_SUB_F_rrr	= 1216,
+    TRICORE_SUB_H_rr	= 1217,
+    TRICORE_SUB_rr	= 1218,
+    TRICORE_SUB_srr	= 1219,
+    TRICORE_SUB_srr_15a	= 1220,
+    TRICORE_SUB_srr_a15	= 1221,
+    TRICORE_SVLCX_sys	= 1222,
+    TRICORE_SWAPMSK_W_bo_bso	= 1223,
+    TRICORE_SWAPMSK_W_bo_c	= 1224,
+    TRICORE_SWAPMSK_W_bo_i	= 1225,
+    TRICORE_SWAPMSK_W_bo_pos	= 1226,
+    TRICORE_SWAPMSK_W_bo_pre	= 1227,
+    TRICORE_SWAPMSK_W_bo_r	= 1228,
+    TRICORE_SWAP_A_abs	= 1229,
+    TRICORE_SWAP_A_bo_bso	= 1230,
+    TRICORE_SWAP_A_bo_c	= 1231,
+    TRICORE_SWAP_A_bo_pos	= 1232,
+    TRICORE_SWAP_A_bo_pre	= 1233,
+    TRICORE_SWAP_A_bo_r	= 1234,
+    TRICORE_SWAP_W_abs	= 1235,
+    TRICORE_SWAP_W_bo_bso	= 1236,
+    TRICORE_SWAP_W_bo_c	= 1237,
+    TRICORE_SWAP_W_bo_i	= 1238,
+    TRICORE_SWAP_W_bo_pos	= 1239,
+    TRICORE_SWAP_W_bo_pre	= 1240,
+    TRICORE_SWAP_W_bo_r	= 1241,
+    TRICORE_SYSCALL_rc	= 1242,
+    TRICORE_TLBDEMAP_rr	= 1243,
+    TRICORE_TLBFLUSH_A_rr	= 1244,
+    TRICORE_TLBFLUSH_B_rr	= 1245,
+    TRICORE_TLBMAP_rr	= 1246,
+    TRICORE_TLBPROBE_A_rr	= 1247,
+    TRICORE_TLBPROBE_I_rr	= 1248,
+    TRICORE_TRAPSV_sys	= 1249,
+    TRICORE_TRAPV_sys	= 1250,
+    TRICORE_UNPACK_rr_rr	= 1251,
+    TRICORE_UNPACK_rr_rr_v110	= 1252,
+    TRICORE_UPDFL_rr	= 1253,
+    TRICORE_UTOF_rr	= 1254,
+    TRICORE_WAIT_sys	= 1255,
+    TRICORE_XNOR_T	= 1256,
+    TRICORE_XNOR_rc	= 1257,
+    TRICORE_XNOR_rr	= 1258,
+    TRICORE_XOR_EQ_rc	= 1259,
+    TRICORE_XOR_EQ_rr	= 1260,
+    TRICORE_XOR_GE_U_rc	= 1261,
+    TRICORE_XOR_GE_U_rr	= 1262,
+    TRICORE_XOR_GE_rc	= 1263,
+    TRICORE_XOR_GE_rr	= 1264,
+    TRICORE_XOR_LT_U_rc	= 1265,
+    TRICORE_XOR_LT_U_rr	= 1266,
+    TRICORE_XOR_LT_rc	= 1267,
+    TRICORE_XOR_LT_rr	= 1268,
+    TRICORE_XOR_NE_rc	= 1269,
+    TRICORE_XOR_NE_rr	= 1270,
+    TRICORE_XOR_T	= 1271,
+    TRICORE_XOR_rc	= 1272,
+    TRICORE_XOR_rr	= 1273,
+    TRICORE_XOR_srr	= 1274,
+    INSTRUCTION_LIST_END = 1275
+  };
+
+#endif // GET_INSTRINFO_ENUM
+
+#ifdef GET_INSTRINFO_MC_DESC
+#undef GET_INSTRINFO_MC_DESC
+
+
+static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /* = 0 */ }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /* = 0 */ }, };
+static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo13[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo14[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo38[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo45[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo46[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo47[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo48[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo49[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo50[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo51[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo52[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo53[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo54[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo55[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo56[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo57[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo58[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo59[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo60[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo61[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo62[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo63[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo64[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo65[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo66[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo67[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo68[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo69[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo70[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo71[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo72[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo73[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo74[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo75[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo76[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo77[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo78[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo79[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo80[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo81[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo82[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo83[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo84[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo85[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo86[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo87[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo88[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo89[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo90[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo91[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo92[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo93[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo94[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo95[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo96[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo97[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo98[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo99[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo100[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo101[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo102[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo103[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo104[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo105[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo106[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo107[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo108[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo109[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo110[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo111[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+
+static const MCInstrDesc TriCoreInsts[] = {
+  { 2, OperandInfo47 },  // Inst #1274 = XOR_srr
+  { 3, OperandInfo45 },  // Inst #1273 = XOR_rr
+  { 3, OperandInfo46 },  // Inst #1272 = XOR_rc
+  { 5, OperandInfo59 },  // Inst #1271 = XOR_T
+  { 3, OperandInfo45 },  // Inst #1270 = XOR_NE_rr
+  { 3, OperandInfo46 },  // Inst #1269 = XOR_NE_rc
+  { 3, OperandInfo45 },  // Inst #1268 = XOR_LT_rr
+  { 3, OperandInfo46 },  // Inst #1267 = XOR_LT_rc
+  { 3, OperandInfo45 },  // Inst #1266 = XOR_LT_U_rr
+  { 3, OperandInfo46 },  // Inst #1265 = XOR_LT_U_rc
+  { 3, OperandInfo45 },  // Inst #1264 = XOR_GE_rr
+  { 3, OperandInfo46 },  // Inst #1263 = XOR_GE_rc
+  { 3, OperandInfo45 },  // Inst #1262 = XOR_GE_U_rr
+  { 3, OperandInfo46 },  // Inst #1261 = XOR_GE_U_rc
+  { 3, OperandInfo45 },  // Inst #1260 = XOR_EQ_rr
+  { 3, OperandInfo46 },  // Inst #1259 = XOR_EQ_rc
+  { 3, OperandInfo45 },  // Inst #1258 = XNOR_rr
+  { 3, OperandInfo46 },  // Inst #1257 = XNOR_rc
+  { 5, OperandInfo59 },  // Inst #1256 = XNOR_T
+  { 0, 0 },  // Inst #1255 = WAIT_sys
+  { 2, OperandInfo47 },  // Inst #1254 = UTOF_rr
+  { 1, OperandInfo71 },  // Inst #1253 = UPDFL_rr
+  { 2, OperandInfo60 },  // Inst #1252 = UNPACK_rr_rr_v110
+  { 2, OperandInfo60 },  // Inst #1251 = UNPACK_rr_rr
+  { 0, 0 },  // Inst #1250 = TRAPV_sys
+  { 0, 0 },  // Inst #1249 = TRAPSV_sys
+  { 1, OperandInfo71 },  // Inst #1248 = TLBPROBE_I_rr
+  { 1, OperandInfo71 },  // Inst #1247 = TLBPROBE_A_rr
+  { 1, OperandInfo111 },  // Inst #1246 = TLBMAP_rr
+  { 0, 0 },  // Inst #1245 = TLBFLUSH_B_rr
+  { 0, 0 },  // Inst #1244 = TLBFLUSH_A_rr
+  { 1, OperandInfo71 },  // Inst #1243 = TLBDEMAP_rr
+  { 1, OperandInfo2 },  // Inst #1242 = SYSCALL_rc
+  { 2, OperandInfo107 },  // Inst #1241 = SWAP_W_bo_r
+  { 3, OperandInfo90 },  // Inst #1240 = SWAP_W_bo_pre
+  { 3, OperandInfo90 },  // Inst #1239 = SWAP_W_bo_pos
+  { 3, OperandInfo91 },  // Inst #1238 = SWAP_W_bo_i
+  { 3, OperandInfo106 },  // Inst #1237 = SWAP_W_bo_c
+  { 3, OperandInfo90 },  // Inst #1236 = SWAP_W_bo_bso
+  { 2, OperandInfo58 },  // Inst #1235 = SWAP_W_abs
+  { 2, OperandInfo105 },  // Inst #1234 = SWAP_A_bo_r
+  { 3, OperandInfo48 },  // Inst #1233 = SWAP_A_bo_pre
+  { 3, OperandInfo48 },  // Inst #1232 = SWAP_A_bo_pos
+  { 3, OperandInfo93 },  // Inst #1231 = SWAP_A_bo_c
+  { 3, OperandInfo48 },  // Inst #1230 = SWAP_A_bo_bso
+  { 2, OperandInfo55 },  // Inst #1229 = SWAP_A_abs
+  { 2, OperandInfo109 },  // Inst #1228 = SWAPMSK_W_bo_r
+  { 3, OperandInfo66 },  // Inst #1227 = SWAPMSK_W_bo_pre
+  { 3, OperandInfo66 },  // Inst #1226 = SWAPMSK_W_bo_pos
+  { 3, OperandInfo67 },  // Inst #1225 = SWAPMSK_W_bo_i
+  { 3, OperandInfo108 },  // Inst #1224 = SWAPMSK_W_bo_c
+  { 3, OperandInfo66 },  // Inst #1223 = SWAPMSK_W_bo_bso
+  { 0, 0 },  // Inst #1222 = SVLCX_sys
+  { 2, OperandInfo47 },  // Inst #1221 = SUB_srr_a15
+  { 2, OperandInfo47 },  // Inst #1220 = SUB_srr_15a
+  { 2, OperandInfo47 },  // Inst #1219 = SUB_srr
+  { 3, OperandInfo45 },  // Inst #1218 = SUB_rr
+  { 3, OperandInfo45 },  // Inst #1217 = SUB_H_rr
+  { 4, OperandInfo57 },  // Inst #1216 = SUB_F_rrr
+  { 3, OperandInfo45 },  // Inst #1215 = SUB_B_rr
+  { 1, OperandInfo2 },  // Inst #1214 = SUB_A_sc_v110
+  { 1, OperandInfo2 },  // Inst #1213 = SUB_A_sc
+  { 3, OperandInfo54 },  // Inst #1212 = SUB_A_rr
+  { 3, OperandInfo45 },  // Inst #1211 = SUBX_rr
+  { 2, OperandInfo47 },  // Inst #1210 = SUBS_srr
+  { 3, OperandInfo45 },  // Inst #1209 = SUBS_rr
+  { 3, OperandInfo45 },  // Inst #1208 = SUBS_U_rr
+  { 3, OperandInfo45 },  // Inst #1207 = SUBS_H_rr
+  { 3, OperandInfo45 },  // Inst #1206 = SUBS_HU_rr
+  { 3, OperandInfo45 },  // Inst #1205 = SUBS_B_rr
+  { 3, OperandInfo45 },  // Inst #1204 = SUBS_BU_rr
+  { 4, OperandInfo52 },  // Inst #1203 = SUBSC_A_rr
+  { 3, OperandInfo45 },  // Inst #1202 = SUBC_rr
+  { 2, OperandInfo58 },  // Inst #1201 = ST_W_ssro_v110
+  { 2, OperandInfo58 },  // Inst #1200 = ST_W_ssro
+  { 2, OperandInfo101 },  // Inst #1199 = ST_W_ssr_v110
+  { 2, OperandInfo101 },  // Inst #1198 = ST_W_ssr_pos_v110
+  { 2, OperandInfo101 },  // Inst #1197 = ST_W_ssr_pos
+  { 2, OperandInfo101 },  // Inst #1196 = ST_W_ssr
+  { 2, OperandInfo55 },  // Inst #1195 = ST_W_sro_v110
+  { 2, OperandInfo55 },  // Inst #1194 = ST_W_sro
+  { 1, OperandInfo2 },  // Inst #1193 = ST_W_sc
+  { 3, OperandInfo53 },  // Inst #1192 = ST_W_bol
+  { 2, OperandInfo107 },  // Inst #1191 = ST_W_bo_r
+  { 3, OperandInfo90 },  // Inst #1190 = ST_W_bo_pre
+  { 3, OperandInfo90 },  // Inst #1189 = ST_W_bo_pos
+  { 3, OperandInfo106 },  // Inst #1188 = ST_W_bo_c
+  { 3, OperandInfo90 },  // Inst #1187 = ST_W_bo_bso
+  { 2, OperandInfo58 },  // Inst #1186 = ST_W_abs
+  { 3, OperandInfo110 },  // Inst #1185 = ST_T
+  { 2, OperandInfo107 },  // Inst #1184 = ST_Q_bo_r
+  { 3, OperandInfo90 },  // Inst #1183 = ST_Q_bo_pre
+  { 3, OperandInfo90 },  // Inst #1182 = ST_Q_bo_pos
+  { 3, OperandInfo106 },  // Inst #1181 = ST_Q_bo_c
+  { 3, OperandInfo90 },  // Inst #1180 = ST_Q_bo_bso
+  { 2, OperandInfo58 },  // Inst #1179 = ST_Q_abs
+  { 2, OperandInfo58 },  // Inst #1178 = ST_H_ssro_v110
+  { 2, OperandInfo58 },  // Inst #1177 = ST_H_ssro
+  { 2, OperandInfo101 },  // Inst #1176 = ST_H_ssr_v110
+  { 2, OperandInfo101 },  // Inst #1175 = ST_H_ssr_pos_v110
+  { 2, OperandInfo101 },  // Inst #1174 = ST_H_ssr_pos
+  { 2, OperandInfo101 },  // Inst #1173 = ST_H_ssr
+  { 2, OperandInfo55 },  // Inst #1172 = ST_H_sro_v110
+  { 2, OperandInfo55 },  // Inst #1171 = ST_H_sro
+  { 3, OperandInfo53 },  // Inst #1170 = ST_H_bol
+  { 2, OperandInfo107 },  // Inst #1169 = ST_H_bo_r
+  { 3, OperandInfo90 },  // Inst #1168 = ST_H_bo_pre
+  { 3, OperandInfo90 },  // Inst #1167 = ST_H_bo_pos
+  { 3, OperandInfo106 },  // Inst #1166 = ST_H_bo_c
+  { 3, OperandInfo90 },  // Inst #1165 = ST_H_bo_bso
+  { 2, OperandInfo58 },  // Inst #1164 = ST_H_abs
+  { 2, OperandInfo109 },  // Inst #1163 = ST_D_bo_r
+  { 3, OperandInfo66 },  // Inst #1162 = ST_D_bo_pre
+  { 3, OperandInfo66 },  // Inst #1161 = ST_D_bo_pos
+  { 3, OperandInfo108 },  // Inst #1160 = ST_D_bo_c
+  { 3, OperandInfo66 },  // Inst #1159 = ST_D_bo_bso
+  { 2, OperandInfo87 },  // Inst #1158 = ST_D_abs
+  { 2, OperandInfo95 },  // Inst #1157 = ST_DA_bo_r
+  { 3, OperandInfo93 },  // Inst #1156 = ST_DA_bo_pre
+  { 3, OperandInfo93 },  // Inst #1155 = ST_DA_bo_pos
+  { 3, OperandInfo94 },  // Inst #1154 = ST_DA_bo_c
+  { 3, OperandInfo93 },  // Inst #1153 = ST_DA_bo_bso
+  { 2, OperandInfo61 },  // Inst #1152 = ST_DA_abs
+  { 2, OperandInfo58 },  // Inst #1151 = ST_B_ssro_v110
+  { 2, OperandInfo58 },  // Inst #1150 = ST_B_ssro
+  { 2, OperandInfo101 },  // Inst #1149 = ST_B_ssr_v110
+  { 2, OperandInfo101 },  // Inst #1148 = ST_B_ssr_pos_v110
+  { 2, OperandInfo101 },  // Inst #1147 = ST_B_ssr_pos
+  { 2, OperandInfo101 },  // Inst #1146 = ST_B_ssr
+  { 2, OperandInfo55 },  // Inst #1145 = ST_B_sro_v110
+  { 2, OperandInfo55 },  // Inst #1144 = ST_B_sro
+  { 3, OperandInfo53 },  // Inst #1143 = ST_B_bol
+  { 2, OperandInfo107 },  // Inst #1142 = ST_B_bo_r
+  { 3, OperandInfo90 },  // Inst #1141 = ST_B_bo_pre
+  { 3, OperandInfo90 },  // Inst #1140 = ST_B_bo_pos
+  { 3, OperandInfo106 },  // Inst #1139 = ST_B_bo_c
+  { 3, OperandInfo90 },  // Inst #1138 = ST_B_bo_bso
+  { 2, OperandInfo58 },  // Inst #1137 = ST_B_abs
+  { 2, OperandInfo55 },  // Inst #1136 = ST_A_ssro_v110
+  { 2, OperandInfo55 },  // Inst #1135 = ST_A_ssro
+  { 2, OperandInfo56 },  // Inst #1134 = ST_A_ssr_v110
+  { 2, OperandInfo56 },  // Inst #1133 = ST_A_ssr_pos_v110
+  { 2, OperandInfo56 },  // Inst #1132 = ST_A_ssr_pos
+  { 2, OperandInfo56 },  // Inst #1131 = ST_A_ssr
+  { 2, OperandInfo55 },  // Inst #1130 = ST_A_sro_v110
+  { 2, OperandInfo55 },  // Inst #1129 = ST_A_sro
+  { 1, OperandInfo2 },  // Inst #1128 = ST_A_sc
+  { 3, OperandInfo48 },  // Inst #1127 = ST_A_bol
+  { 2, OperandInfo105 },  // Inst #1126 = ST_A_bo_r
+  { 3, OperandInfo48 },  // Inst #1125 = ST_A_bo_pre
+  { 3, OperandInfo48 },  // Inst #1124 = ST_A_bo_pos
+  { 3, OperandInfo93 },  // Inst #1123 = ST_A_bo_c
+  { 3, OperandInfo48 },  // Inst #1122 = ST_A_bo_bso
+  { 2, OperandInfo55 },  // Inst #1121 = ST_A_abs
+  { 2, OperandInfo55 },  // Inst #1120 = STUCX_bo_bso
+  { 1, OperandInfo2 },  // Inst #1119 = STUCX_abs
+  { 2, OperandInfo55 },  // Inst #1118 = STLCX_bo_bso
+  { 1, OperandInfo2 },  // Inst #1117 = STLCX_abs
+  { 2, OperandInfo58 },  // Inst #1116 = SH_src_v110
+  { 2, OperandInfo58 },  // Inst #1115 = SH_src
+  { 3, OperandInfo45 },  // Inst #1114 = SH_rr
+  { 3, OperandInfo46 },  // Inst #1113 = SH_rc
+  { 5, OperandInfo59 },  // Inst #1112 = SH_XOR_T
+  { 5, OperandInfo59 },  // Inst #1111 = SH_XNOR_T
+  { 5, OperandInfo59 },  // Inst #1110 = SH_OR_T
+  { 5, OperandInfo59 },  // Inst #1109 = SH_ORN_T
+  { 5, OperandInfo59 },  // Inst #1108 = SH_NOR_T
+  { 3, OperandInfo45 },  // Inst #1107 = SH_NE_rr
+  { 3, OperandInfo46 },  // Inst #1106 = SH_NE_rc
+  { 5, OperandInfo59 },  // Inst #1105 = SH_NAND_T
+  { 3, OperandInfo45 },  // Inst #1104 = SH_LT_rr
+  { 3, OperandInfo46 },  // Inst #1103 = SH_LT_rc
+  { 3, OperandInfo45 },  // Inst #1102 = SH_LT_U_rr
+  { 3, OperandInfo46 },  // Inst #1101 = SH_LT_U_rc
+  { 3, OperandInfo45 },  // Inst #1100 = SH_H_rr
+  { 3, OperandInfo46 },  // Inst #1099 = SH_H_rc
+  { 3, OperandInfo45 },  // Inst #1098 = SH_GE_rr
+  { 3, OperandInfo46 },  // Inst #1097 = SH_GE_rc
+  { 3, OperandInfo45 },  // Inst #1096 = SH_GE_U_rr
+  { 3, OperandInfo46 },  // Inst #1095 = SH_GE_U_rc
+  { 3, OperandInfo45 },  // Inst #1094 = SH_EQ_rr
+  { 3, OperandInfo46 },  // Inst #1093 = SH_EQ_rc
+  { 3, OperandInfo45 },  // Inst #1092 = SH_B_rr
+  { 3, OperandInfo46 },  // Inst #1091 = SH_B_rc
+  { 5, OperandInfo59 },  // Inst #1090 = SH_AND_T
+  { 5, OperandInfo59 },  // Inst #1089 = SH_ANDN_T
+  { 3, OperandInfo46 },  // Inst #1088 = SHUFFLE_rc
+  { 2, OperandInfo58 },  // Inst #1087 = SHA_src_v110
+  { 2, OperandInfo58 },  // Inst #1086 = SHA_src
+  { 3, OperandInfo45 },  // Inst #1085 = SHA_rr
+  { 3, OperandInfo46 },  // Inst #1084 = SHA_rc
+  { 3, OperandInfo45 },  // Inst #1083 = SHA_H_rr
+  { 3, OperandInfo46 },  // Inst #1082 = SHA_H_rc
+  { 3, OperandInfo45 },  // Inst #1081 = SHA_B_rr
+  { 3, OperandInfo46 },  // Inst #1080 = SHA_B_rc
+  { 3, OperandInfo45 },  // Inst #1079 = SHAS_rr
+  { 3, OperandInfo46 },  // Inst #1078 = SHAS_rc
+  { 4, OperandInfo57 },  // Inst #1077 = SEL_rrr
+  { 4, OperandInfo64 },  // Inst #1076 = SEL_rcr
+  { 4, OperandInfo63 },  // Inst #1075 = SEL_A_rrr_v110
+  { 4, OperandInfo52 },  // Inst #1074 = SEL_A_rcr_v110
+  { 4, OperandInfo57 },  // Inst #1073 = SELN_rrr
+  { 4, OperandInfo64 },  // Inst #1072 = SELN_rcr
+  { 4, OperandInfo63 },  // Inst #1071 = SELN_A_rrr_v110
+  { 4, OperandInfo52 },  // Inst #1070 = SELN_A_rcr_v110
+  { 1, OperandInfo71 },  // Inst #1069 = SAT_H_sr_v110
+  { 1, OperandInfo71 },  // Inst #1068 = SAT_H_sr
+  { 2, OperandInfo47 },  // Inst #1067 = SAT_H_rr
+  { 1, OperandInfo71 },  // Inst #1066 = SAT_HU_sr_v110
+  { 1, OperandInfo71 },  // Inst #1065 = SAT_HU_sr
+  { 2, OperandInfo47 },  // Inst #1064 = SAT_HU_rr
+  { 1, OperandInfo71 },  // Inst #1063 = SAT_B_sr_v110
+  { 1, OperandInfo71 },  // Inst #1062 = SAT_B_sr
+  { 2, OperandInfo47 },  // Inst #1061 = SAT_B_rr
+  { 1, OperandInfo71 },  // Inst #1060 = SAT_BU_sr_v110
+  { 1, OperandInfo71 },  // Inst #1059 = SAT_BU_sr
+  { 2, OperandInfo47 },  // Inst #1058 = SAT_BU_rr
+  { 1, OperandInfo71 },  // Inst #1057 = RSUB_sr_sr_v110
+  { 1, OperandInfo71 },  // Inst #1056 = RSUB_sr_sr
+  { 3, OperandInfo46 },  // Inst #1055 = RSUB_rc
+  { 3, OperandInfo46 },  // Inst #1054 = RSUBS_rc
+  { 3, OperandInfo46 },  // Inst #1053 = RSUBS_U_rc
+  { 0, 0 },  // Inst #1052 = RSTV_sys
+  { 0, 0 },  // Inst #1051 = RSLCX_sys
+  { 0, 0 },  // Inst #1050 = RFM_sys
+  { 0, 0 },  // Inst #1049 = RFE_sys_sys_v110
+  { 0, 0 },  // Inst #1048 = RFE_sys_sys
+  { 0, 0 },  // Inst #1047 = RFE_sr
+  { 0, 0 },  // Inst #1046 = RET_sys_v110
+  { 0, 0 },  // Inst #1045 = RET_sys
+  { 0, 0 },  // Inst #1044 = RET_sr
+  { 1, OperandInfo71 },  // Inst #1043 = RESTORE_sys
+  { 2, OperandInfo47 },  // Inst #1042 = QSEED_F_rr
+  { 3, OperandInfo45 },  // Inst #1041 = Q31TOF_rr
+  { 2, OperandInfo47 },  // Inst #1040 = POPCNT_W_rr
+  { 2, OperandInfo47 },  // Inst #1039 = PARITY_rr_v110
+  { 2, OperandInfo47 },  // Inst #1038 = PARITY_rr
+  { 4, OperandInfo83 },  // Inst #1037 = PACK_rrr
+  { 2, OperandInfo47 },  // Inst #1036 = OR_srr_v110
+  { 2, OperandInfo47 },  // Inst #1035 = OR_srr
+  { 1, OperandInfo2 },  // Inst #1034 = OR_sc_v110
+  { 1, OperandInfo2 },  // Inst #1033 = OR_sc
+  { 3, OperandInfo45 },  // Inst #1032 = OR_rr
+  { 3, OperandInfo46 },  // Inst #1031 = OR_rc
+  { 5, OperandInfo59 },  // Inst #1030 = OR_T
+  { 5, OperandInfo59 },  // Inst #1029 = OR_OR_T
+  { 5, OperandInfo59 },  // Inst #1028 = OR_NOR_T
+  { 3, OperandInfo45 },  // Inst #1027 = OR_NE_rr
+  { 3, OperandInfo46 },  // Inst #1026 = OR_NE_rc
+  { 3, OperandInfo45 },  // Inst #1025 = OR_LT_rr
+  { 3, OperandInfo46 },  // Inst #1024 = OR_LT_rc
+  { 3, OperandInfo45 },  // Inst #1023 = OR_LT_U_rr
+  { 3, OperandInfo46 },  // Inst #1022 = OR_LT_U_rc
+  { 3, OperandInfo45 },  // Inst #1021 = OR_GE_rr
+  { 3, OperandInfo46 },  // Inst #1020 = OR_GE_rc
+  { 3, OperandInfo45 },  // Inst #1019 = OR_GE_U_rr
+  { 3, OperandInfo46 },  // Inst #1018 = OR_GE_U_rc
+  { 3, OperandInfo45 },  // Inst #1017 = OR_EQ_rr
+  { 3, OperandInfo46 },  // Inst #1016 = OR_EQ_rc
+  { 5, OperandInfo59 },  // Inst #1015 = OR_AND_T
+  { 5, OperandInfo59 },  // Inst #1014 = OR_ANDN_T
+  { 3, OperandInfo45 },  // Inst #1013 = ORN_rr
+  { 3, OperandInfo46 },  // Inst #1012 = ORN_rc
+  { 5, OperandInfo59 },  // Inst #1011 = ORN_T
+  { 1, OperandInfo71 },  // Inst #1010 = NOT_sr_v162
+  { 1, OperandInfo71 },  // Inst #1009 = NOR_sr_v110
+  { 1, OperandInfo71 },  // Inst #1008 = NOR_sr
+  { 3, OperandInfo45 },  // Inst #1007 = NOR_rr
+  { 3, OperandInfo46 },  // Inst #1006 = NOR_rc
+  { 5, OperandInfo59 },  // Inst #1005 = NOR_T
+  { 0, 0 },  // Inst #1004 = NOP_sys
+  { 0, 0 },  // Inst #1003 = NOP_sr
+  { 3, OperandInfo45 },  // Inst #1002 = NE_rr
+  { 3, OperandInfo46 },  // Inst #1001 = NE_rc
+  { 3, OperandInfo75 },  // Inst #1000 = NE_A
+  { 2, OperandInfo74 },  // Inst #999 = NEZ_A
+  { 3, OperandInfo45 },  // Inst #998 = NAND_rr
+  { 3, OperandInfo46 },  // Inst #997 = NAND_rc
+  { 5, OperandInfo59 },  // Inst #996 = NAND_T
+  { 2, OperandInfo47 },  // Inst #995 = MUL_srr
+  { 3, OperandInfo45 },  // Inst #994 = MUL_rr_v110
+  { 3, OperandInfo72 },  // Inst #993 = MUL_rr2_e
+  { 3, OperandInfo45 },  // Inst #992 = MUL_rr2
+  { 3, OperandInfo104 },  // Inst #991 = MUL_rc_e
+  { 3, OperandInfo46 },  // Inst #990 = MUL_rc
+  { 3, OperandInfo72 },  // Inst #989 = MUL_U_rr2
+  { 3, OperandInfo104 },  // Inst #988 = MUL_U_rc
+  { 4, OperandInfo64 },  // Inst #987 = MUL_Q_rr_v110
+  { 4, OperandInfo103 },  // Inst #986 = MUL_Q_rr1_2__e
+  { 4, OperandInfo103 },  // Inst #985 = MUL_Q_rr1_2_Ue
+  { 4, OperandInfo64 },  // Inst #984 = MUL_Q_rr1_2_U
+  { 4, OperandInfo103 },  // Inst #983 = MUL_Q_rr1_2_Le
+  { 4, OperandInfo64 },  // Inst #982 = MUL_Q_rr1_2_L
+  { 4, OperandInfo64 },  // Inst #981 = MUL_Q_rr1_2UU
+  { 4, OperandInfo64 },  // Inst #980 = MUL_Q_rr1_2LL
+  { 4, OperandInfo64 },  // Inst #979 = MUL_Q_rr1_2
+  { 4, OperandInfo103 },  // Inst #978 = MUL_H_rr_v110
+  { 4, OperandInfo103 },  // Inst #977 = MUL_H_rr1_UU2e
+  { 4, OperandInfo103 },  // Inst #976 = MUL_H_rr1_UL2e
+  { 4, OperandInfo103 },  // Inst #975 = MUL_H_rr1_LU2e
+  { 4, OperandInfo103 },  // Inst #974 = MUL_H_rr1_LL2e
+  { 3, OperandInfo45 },  // Inst #973 = MUL_F_rrr
+  { 3, OperandInfo45 },  // Inst #972 = MULS_rr_v110
+  { 3, OperandInfo45 },  // Inst #971 = MULS_rr2
+  { 3, OperandInfo46 },  // Inst #970 = MULS_rc
+  { 3, OperandInfo45 },  // Inst #969 = MULS_U_rr_v110
+  { 3, OperandInfo45 },  // Inst #968 = MULS_U_rr2
+  { 3, OperandInfo46 },  // Inst #967 = MULS_U_rc
+  { 4, OperandInfo64 },  // Inst #966 = MULR_Q_rr_v110
+  { 4, OperandInfo64 },  // Inst #965 = MULR_Q_rr1_2UU
+  { 4, OperandInfo64 },  // Inst #964 = MULR_Q_rr1_2LL
+  { 4, OperandInfo64 },  // Inst #963 = MULR_H_rr_v110
+  { 4, OperandInfo64 },  // Inst #962 = MULR_H_rr1_UU2e
+  { 4, OperandInfo64 },  // Inst #961 = MULR_H_rr1_UL2e
+  { 4, OperandInfo64 },  // Inst #960 = MULR_H_rr1_LU2e
+  { 4, OperandInfo64 },  // Inst #959 = MULR_H_rr1_LL2e
+  { 3, OperandInfo72 },  // Inst #958 = MULM_rr
+  { 3, OperandInfo104 },  // Inst #957 = MULM_rc
+  { 3, OperandInfo72 },  // Inst #956 = MULM_U_rr
+  { 3, OperandInfo104 },  // Inst #955 = MULM_U_rc
+  { 4, OperandInfo103 },  // Inst #954 = MULM_H_rr1_UU2e
+  { 4, OperandInfo103 },  // Inst #953 = MULM_H_rr1_UL2e
+  { 4, OperandInfo103 },  // Inst #952 = MULM_H_rr1_LU2e
+  { 4, OperandInfo103 },  // Inst #951 = MULM_H_rr1_LL2e
+  { 4, OperandInfo103 },  // Inst #950 = MULMS_H_rr1_UU2e
+  { 4, OperandInfo103 },  // Inst #949 = MULMS_H_rr1_UL2e
+  { 4, OperandInfo103 },  // Inst #948 = MULMS_H_rr1_LU2e
+  { 4, OperandInfo103 },  // Inst #947 = MULMS_H_rr1_LL2e
+  { 2, OperandInfo102 },  // Inst #946 = MTCR_rlc
+  { 4, OperandInfo73 },  // Inst #945 = MSUB_rrr2_e
+  { 4, OperandInfo57 },  // Inst #944 = MSUB_rrr2
+  { 4, OperandInfo97 },  // Inst #943 = MSUB_rcr_e
+  { 4, OperandInfo64 },  // Inst #942 = MSUB_rcr
+  { 4, OperandInfo73 },  // Inst #941 = MSUB_U_rrr2
+  { 4, OperandInfo97 },  // Inst #940 = MSUB_U_rcr
+  { 5, OperandInfo96 },  // Inst #939 = MSUB_Q_rrr1_e_U_U
+  { 5, OperandInfo96 },  // Inst #938 = MSUB_Q_rrr1_e_U
+  { 5, OperandInfo96 },  // Inst #937 = MSUB_Q_rrr1_e_L_L
+  { 5, OperandInfo96 },  // Inst #936 = MSUB_Q_rrr1_e_L
+  { 5, OperandInfo96 },  // Inst #935 = MSUB_Q_rrr1_e
+  { 5, OperandInfo98 },  // Inst #934 = MSUB_Q_rrr1_U_U
+  { 5, OperandInfo98 },  // Inst #933 = MSUB_Q_rrr1_UU2_v110
+  { 5, OperandInfo98 },  // Inst #932 = MSUB_Q_rrr1_U
+  { 5, OperandInfo98 },  // Inst #931 = MSUB_Q_rrr1_L_L
+  { 5, OperandInfo98 },  // Inst #930 = MSUB_Q_rrr1_L
+  { 5, OperandInfo98 },  // Inst #929 = MSUB_Q_rrr1
+  { 5, OperandInfo96 },  // Inst #928 = MSUB_H_rrr1_v110
+  { 5, OperandInfo96 },  // Inst #927 = MSUB_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #926 = MSUB_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #925 = MSUB_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #924 = MSUB_H_rrr1_LL
+  { 4, OperandInfo57 },  // Inst #923 = MSUB_F_rrr
+  { 4, OperandInfo73 },  // Inst #922 = MSUBS_rrr2_e
+  { 4, OperandInfo57 },  // Inst #921 = MSUBS_rrr2
+  { 4, OperandInfo97 },  // Inst #920 = MSUBS_rcr_e
+  { 4, OperandInfo64 },  // Inst #919 = MSUBS_rcr
+  { 4, OperandInfo73 },  // Inst #918 = MSUBS_U_rrr2_e
+  { 4, OperandInfo57 },  // Inst #917 = MSUBS_U_rrr2
+  { 4, OperandInfo97 },  // Inst #916 = MSUBS_U_rcr_e
+  { 4, OperandInfo64 },  // Inst #915 = MSUBS_U_rcr
+  { 5, OperandInfo96 },  // Inst #914 = MSUBS_Q_rrr1_e_U_U
+  { 5, OperandInfo96 },  // Inst #913 = MSUBS_Q_rrr1_e_U
+  { 5, OperandInfo96 },  // Inst #912 = MSUBS_Q_rrr1_e_L_L
+  { 5, OperandInfo96 },  // Inst #911 = MSUBS_Q_rrr1_e_L
+  { 5, OperandInfo96 },  // Inst #910 = MSUBS_Q_rrr1_e
+  { 5, OperandInfo98 },  // Inst #909 = MSUBS_Q_rrr1_U_U
+  { 5, OperandInfo98 },  // Inst #908 = MSUBS_Q_rrr1_UU2_v110
+  { 5, OperandInfo98 },  // Inst #907 = MSUBS_Q_rrr1_U
+  { 5, OperandInfo98 },  // Inst #906 = MSUBS_Q_rrr1_L_L
+  { 5, OperandInfo98 },  // Inst #905 = MSUBS_Q_rrr1_L
+  { 5, OperandInfo98 },  // Inst #904 = MSUBS_Q_rrr1
+  { 5, OperandInfo96 },  // Inst #903 = MSUBS_H_rrr1_v110
+  { 5, OperandInfo96 },  // Inst #902 = MSUBS_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #901 = MSUBS_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #900 = MSUBS_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #899 = MSUBS_H_rrr1_LL
+  { 5, OperandInfo98 },  // Inst #898 = MSUBR_Q_rrr1_v110
+  { 5, OperandInfo98 },  // Inst #897 = MSUBR_Q_rrr1_U_U
+  { 5, OperandInfo98 },  // Inst #896 = MSUBR_Q_rrr1_L_L
+  { 5, OperandInfo99 },  // Inst #895 = MSUBR_H_rrr1_v110
+  { 5, OperandInfo98 },  // Inst #894 = MSUBR_H_rrr1_UU
+  { 5, OperandInfo99 },  // Inst #893 = MSUBR_H_rrr1_UL_2
+  { 5, OperandInfo98 },  // Inst #892 = MSUBR_H_rrr1_UL
+  { 5, OperandInfo98 },  // Inst #891 = MSUBR_H_rrr1_LU
+  { 5, OperandInfo98 },  // Inst #890 = MSUBR_H_rrr1_LL
+  { 5, OperandInfo98 },  // Inst #889 = MSUBRS_Q_rrr1_v110
+  { 5, OperandInfo98 },  // Inst #888 = MSUBRS_Q_rrr1_U_U
+  { 5, OperandInfo98 },  // Inst #887 = MSUBRS_Q_rrr1_L_L
+  { 5, OperandInfo99 },  // Inst #886 = MSUBRS_H_rrr1_v110
+  { 5, OperandInfo98 },  // Inst #885 = MSUBRS_H_rrr1_UU
+  { 5, OperandInfo99 },  // Inst #884 = MSUBRS_H_rrr1_UL_2
+  { 5, OperandInfo98 },  // Inst #883 = MSUBRS_H_rrr1_UL
+  { 5, OperandInfo98 },  // Inst #882 = MSUBRS_H_rrr1_LU
+  { 5, OperandInfo98 },  // Inst #881 = MSUBRS_H_rrr1_LL
+  { 4, OperandInfo73 },  // Inst #880 = MSUBM_rrr2v110
+  { 4, OperandInfo97 },  // Inst #879 = MSUBM_rcrv110
+  { 4, OperandInfo73 },  // Inst #878 = MSUBM_U_rrr2v110
+  { 4, OperandInfo97 },  // Inst #877 = MSUBM_U_rcrv110
+  { 5, OperandInfo96 },  // Inst #876 = MSUBM_Q_rrr1_v110
+  { 5, OperandInfo96 },  // Inst #875 = MSUBM_H_rrr1_v110
+  { 5, OperandInfo96 },  // Inst #874 = MSUBM_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #873 = MSUBM_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #872 = MSUBM_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #871 = MSUBM_H_rrr1_LL
+  { 4, OperandInfo73 },  // Inst #870 = MSUBMS_rrr2v110
+  { 4, OperandInfo97 },  // Inst #869 = MSUBMS_rcrv110
+  { 4, OperandInfo73 },  // Inst #868 = MSUBMS_U_rrr2v110
+  { 4, OperandInfo97 },  // Inst #867 = MSUBMS_U_rcrv110
+  { 5, OperandInfo96 },  // Inst #866 = MSUBMS_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #865 = MSUBMS_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #864 = MSUBMS_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #863 = MSUBMS_H_rrr1_LL
+  { 5, OperandInfo96 },  // Inst #862 = MSUBAD_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #861 = MSUBAD_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #860 = MSUBAD_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #859 = MSUBAD_H_rrr1_LL
+  { 5, OperandInfo96 },  // Inst #858 = MSUBADS_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #857 = MSUBADS_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #856 = MSUBADS_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #855 = MSUBADS_H_rrr1_LL
+  { 5, OperandInfo98 },  // Inst #854 = MSUBADR_H_rrr1_v110
+  { 5, OperandInfo98 },  // Inst #853 = MSUBADR_H_rrr1_UU
+  { 5, OperandInfo98 },  // Inst #852 = MSUBADR_H_rrr1_UL
+  { 5, OperandInfo98 },  // Inst #851 = MSUBADR_H_rrr1_LU
+  { 5, OperandInfo98 },  // Inst #850 = MSUBADR_H_rrr1_LL
+  { 5, OperandInfo98 },  // Inst #849 = MSUBADRS_H_rrr1_v110
+  { 5, OperandInfo98 },  // Inst #848 = MSUBADRS_H_rrr1_UU
+  { 5, OperandInfo98 },  // Inst #847 = MSUBADRS_H_rrr1_UL
+  { 5, OperandInfo98 },  // Inst #846 = MSUBADRS_H_rrr1_LU
+  { 5, OperandInfo98 },  // Inst #845 = MSUBADRS_H_rrr1_LL
+  { 5, OperandInfo96 },  // Inst #844 = MSUBADM_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #843 = MSUBADM_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #842 = MSUBADM_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #841 = MSUBADM_H_rrr1_LL
+  { 5, OperandInfo96 },  // Inst #840 = MSUBADMS_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #839 = MSUBADMS_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #838 = MSUBADMS_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #837 = MSUBADMS_H_rrr1_LL
+  { 2, OperandInfo47 },  // Inst #836 = MOV_srr
+  { 2, OperandInfo87 },  // Inst #835 = MOV_src_e
+  { 2, OperandInfo58 },  // Inst #834 = MOV_src
+  { 1, OperandInfo2 },  // Inst #833 = MOV_sc_v110
+  { 1, OperandInfo2 },  // Inst #832 = MOV_sc
+  { 3, OperandInfo72 },  // Inst #831 = MOV_rr_eab
+  { 3, OperandInfo72 },  // Inst #830 = MOV_rr_e
+  { 3, OperandInfo45 },  // Inst #829 = MOV_rr
+  { 2, OperandInfo87 },  // Inst #828 = MOV_rlc_e
+  { 2, OperandInfo58 },  // Inst #827 = MOV_rlc
+  { 2, OperandInfo58 },  // Inst #826 = MOV_U_rlc
+  { 2, OperandInfo74 },  // Inst #825 = MOV_D_srr_srr_v110
+  { 2, OperandInfo74 },  // Inst #824 = MOV_D_srr_srr
+  { 3, OperandInfo75 },  // Inst #823 = MOV_D_rr
+  { 2, OperandInfo101 },  // Inst #822 = MOV_A_srr_v110
+  { 2, OperandInfo101 },  // Inst #821 = MOV_A_srr
+  { 2, OperandInfo55 },  // Inst #820 = MOV_A_src
+  { 3, OperandInfo100 },  // Inst #819 = MOV_A_rr
+  { 2, OperandInfo56 },  // Inst #818 = MOV_AA_srr_srr_v110
+  { 2, OperandInfo56 },  // Inst #817 = MOV_AA_srr_srr
+  { 3, OperandInfo54 },  // Inst #816 = MOV_AA_rr
+  { 1, OperandInfo65 },  // Inst #815 = MOVZ_A_sr
+  { 2, OperandInfo58 },  // Inst #814 = MOVH_rlc
+  { 2, OperandInfo55 },  // Inst #813 = MOVH_A_rlc
+  { 3, OperandInfo45 },  // Inst #812 = MIN_rr
+  { 3, OperandInfo46 },  // Inst #811 = MIN_rc
+  { 3, OperandInfo45 },  // Inst #810 = MIN_U_rr
+  { 3, OperandInfo46 },  // Inst #809 = MIN_U_rc
+  { 3, OperandInfo45 },  // Inst #808 = MIN_HU
+  { 3, OperandInfo45 },  // Inst #807 = MIN_H
+  { 3, OperandInfo45 },  // Inst #806 = MIN_BU
+  { 3, OperandInfo45 },  // Inst #805 = MIN_B
+  { 2, OperandInfo58 },  // Inst #804 = MFCR_rlc
+  { 3, OperandInfo45 },  // Inst #803 = MAX_rr
+  { 3, OperandInfo46 },  // Inst #802 = MAX_rc
+  { 3, OperandInfo45 },  // Inst #801 = MAX_U_rr
+  { 3, OperandInfo46 },  // Inst #800 = MAX_U_rc
+  { 3, OperandInfo45 },  // Inst #799 = MAX_HU
+  { 3, OperandInfo45 },  // Inst #798 = MAX_H
+  { 3, OperandInfo45 },  // Inst #797 = MAX_BU
+  { 3, OperandInfo45 },  // Inst #796 = MAX_B
+  { 4, OperandInfo73 },  // Inst #795 = MADD_rrr2_e
+  { 4, OperandInfo57 },  // Inst #794 = MADD_rrr2
+  { 4, OperandInfo97 },  // Inst #793 = MADD_rcr_e
+  { 4, OperandInfo64 },  // Inst #792 = MADD_rcr
+  { 4, OperandInfo73 },  // Inst #791 = MADD_U_rrr2
+  { 4, OperandInfo97 },  // Inst #790 = MADD_U_rcr
+  { 5, OperandInfo96 },  // Inst #789 = MADD_Q_rrr1_e_U_U
+  { 5, OperandInfo96 },  // Inst #788 = MADD_Q_rrr1_e_U
+  { 5, OperandInfo96 },  // Inst #787 = MADD_Q_rrr1_e_L_L
+  { 5, OperandInfo96 },  // Inst #786 = MADD_Q_rrr1_e_L
+  { 5, OperandInfo96 },  // Inst #785 = MADD_Q_rrr1_e
+  { 5, OperandInfo98 },  // Inst #784 = MADD_Q_rrr1_U_U
+  { 5, OperandInfo98 },  // Inst #783 = MADD_Q_rrr1_UU2_v110
+  { 5, OperandInfo98 },  // Inst #782 = MADD_Q_rrr1_U
+  { 5, OperandInfo98 },  // Inst #781 = MADD_Q_rrr1_L_L
+  { 5, OperandInfo98 },  // Inst #780 = MADD_Q_rrr1_L
+  { 5, OperandInfo98 },  // Inst #779 = MADD_Q_rrr1
+  { 5, OperandInfo96 },  // Inst #778 = MADD_H_rrr1_v110
+  { 5, OperandInfo96 },  // Inst #777 = MADD_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #776 = MADD_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #775 = MADD_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #774 = MADD_H_rrr1_LL
+  { 4, OperandInfo57 },  // Inst #773 = MADD_F_rrr
+  { 4, OperandInfo73 },  // Inst #772 = MADDS_rrr2_e
+  { 4, OperandInfo57 },  // Inst #771 = MADDS_rrr2
+  { 4, OperandInfo97 },  // Inst #770 = MADDS_rcr_e
+  { 4, OperandInfo64 },  // Inst #769 = MADDS_rcr
+  { 4, OperandInfo73 },  // Inst #768 = MADDS_U_rrr2_e
+  { 4, OperandInfo57 },  // Inst #767 = MADDS_U_rrr2
+  { 4, OperandInfo97 },  // Inst #766 = MADDS_U_rcr_e
+  { 4, OperandInfo64 },  // Inst #765 = MADDS_U_rcr
+  { 5, OperandInfo96 },  // Inst #764 = MADDS_Q_rrr1_e_U_U
+  { 5, OperandInfo96 },  // Inst #763 = MADDS_Q_rrr1_e_U
+  { 5, OperandInfo96 },  // Inst #762 = MADDS_Q_rrr1_e_L_L
+  { 5, OperandInfo96 },  // Inst #761 = MADDS_Q_rrr1_e_L
+  { 5, OperandInfo96 },  // Inst #760 = MADDS_Q_rrr1_e
+  { 5, OperandInfo98 },  // Inst #759 = MADDS_Q_rrr1_U_U
+  { 5, OperandInfo98 },  // Inst #758 = MADDS_Q_rrr1_UU2_v110
+  { 5, OperandInfo98 },  // Inst #757 = MADDS_Q_rrr1_U
+  { 5, OperandInfo98 },  // Inst #756 = MADDS_Q_rrr1_L_L
+  { 5, OperandInfo98 },  // Inst #755 = MADDS_Q_rrr1_L
+  { 5, OperandInfo98 },  // Inst #754 = MADDS_Q_rrr1
+  { 5, OperandInfo96 },  // Inst #753 = MADDS_H_rrr1_v110
+  { 5, OperandInfo96 },  // Inst #752 = MADDS_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #751 = MADDS_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #750 = MADDS_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #749 = MADDS_H_rrr1_LL
+  { 5, OperandInfo96 },  // Inst #748 = MADDSU_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #747 = MADDSU_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #746 = MADDSU_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #745 = MADDSU_H_rrr1_LL
+  { 5, OperandInfo96 },  // Inst #744 = MADDSUS_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #743 = MADDSUS_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #742 = MADDSUS_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #741 = MADDSUS_H_rrr1_LL
+  { 5, OperandInfo98 },  // Inst #740 = MADDSUR_H_rrr1_UU
+  { 5, OperandInfo98 },  // Inst #739 = MADDSUR_H_rrr1_UL
+  { 5, OperandInfo98 },  // Inst #738 = MADDSUR_H_rrr1_LU
+  { 5, OperandInfo98 },  // Inst #737 = MADDSUR_H_rrr1_LL
+  { 5, OperandInfo98 },  // Inst #736 = MADDSURS_H_rrr1_UU
+  { 5, OperandInfo98 },  // Inst #735 = MADDSURS_H_rrr1_UL
+  { 5, OperandInfo98 },  // Inst #734 = MADDSURS_H_rrr1_LU
+  { 5, OperandInfo98 },  // Inst #733 = MADDSURS_H_rrr1_LL
+  { 5, OperandInfo96 },  // Inst #732 = MADDSUM_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #731 = MADDSUM_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #730 = MADDSUM_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #729 = MADDSUM_H_rrr1_LL
+  { 5, OperandInfo96 },  // Inst #728 = MADDSUMS_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #727 = MADDSUMS_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #726 = MADDSUMS_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #725 = MADDSUMS_H_rrr1_LL
+  { 5, OperandInfo98 },  // Inst #724 = MADDR_Q_rrr1_v110
+  { 5, OperandInfo98 },  // Inst #723 = MADDR_Q_rrr1_U_U
+  { 5, OperandInfo98 },  // Inst #722 = MADDR_Q_rrr1_L_L
+  { 5, OperandInfo99 },  // Inst #721 = MADDR_H_rrr1_v110
+  { 5, OperandInfo98 },  // Inst #720 = MADDR_H_rrr1_UU
+  { 5, OperandInfo99 },  // Inst #719 = MADDR_H_rrr1_UL_2
+  { 5, OperandInfo98 },  // Inst #718 = MADDR_H_rrr1_UL
+  { 5, OperandInfo98 },  // Inst #717 = MADDR_H_rrr1_LU
+  { 5, OperandInfo98 },  // Inst #716 = MADDR_H_rrr1_LL
+  { 5, OperandInfo98 },  // Inst #715 = MADDRS_Q_rrr1_v110
+  { 5, OperandInfo98 },  // Inst #714 = MADDRS_Q_rrr1_U_U
+  { 5, OperandInfo98 },  // Inst #713 = MADDRS_Q_rrr1_L_L
+  { 5, OperandInfo99 },  // Inst #712 = MADDRS_H_rrr1_v110
+  { 5, OperandInfo98 },  // Inst #711 = MADDRS_H_rrr1_UU
+  { 5, OperandInfo99 },  // Inst #710 = MADDRS_H_rrr1_UL_2
+  { 5, OperandInfo98 },  // Inst #709 = MADDRS_H_rrr1_UL
+  { 5, OperandInfo98 },  // Inst #708 = MADDRS_H_rrr1_LU
+  { 5, OperandInfo98 },  // Inst #707 = MADDRS_H_rrr1_LL
+  { 4, OperandInfo73 },  // Inst #706 = MADDM_rrr2_v110
+  { 4, OperandInfo97 },  // Inst #705 = MADDM_rcr_v110
+  { 4, OperandInfo73 },  // Inst #704 = MADDM_U_rrr2_v110
+  { 4, OperandInfo97 },  // Inst #703 = MADDM_U_rcr_v110
+  { 5, OperandInfo96 },  // Inst #702 = MADDM_Q_rrr1_v110
+  { 5, OperandInfo96 },  // Inst #701 = MADDM_H_rrr1_v110
+  { 5, OperandInfo96 },  // Inst #700 = MADDM_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #699 = MADDM_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #698 = MADDM_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #697 = MADDM_H_rrr1_LL
+  { 4, OperandInfo73 },  // Inst #696 = MADDMS_rrr2_v110
+  { 4, OperandInfo97 },  // Inst #695 = MADDMS_rcr_v110
+  { 4, OperandInfo73 },  // Inst #694 = MADDMS_U_rrr2_v110
+  { 4, OperandInfo97 },  // Inst #693 = MADDMS_U_rcr_v110
+  { 5, OperandInfo96 },  // Inst #692 = MADDMS_H_rrr1_UU
+  { 5, OperandInfo96 },  // Inst #691 = MADDMS_H_rrr1_UL
+  { 5, OperandInfo96 },  // Inst #690 = MADDMS_H_rrr1_LU
+  { 5, OperandInfo96 },  // Inst #689 = MADDMS_H_rrr1_LL
+  { 2, OperandInfo47 },  // Inst #688 = LT_srr
+  { 2, OperandInfo58 },  // Inst #687 = LT_src
+  { 3, OperandInfo45 },  // Inst #686 = LT_rr
+  { 3, OperandInfo46 },  // Inst #685 = LT_rc
+  { 3, OperandInfo45 },  // Inst #684 = LT_WU
+  { 3, OperandInfo45 },  // Inst #683 = LT_W
+  { 2, OperandInfo47 },  // Inst #682 = LT_U_srrv110
+  { 2, OperandInfo58 },  // Inst #681 = LT_U_srcv110
+  { 3, OperandInfo45 },  // Inst #680 = LT_U_rr
+  { 3, OperandInfo46 },  // Inst #679 = LT_U_rc
+  { 3, OperandInfo45 },  // Inst #678 = LT_HU
+  { 3, OperandInfo45 },  // Inst #677 = LT_H
+  { 3, OperandInfo45 },  // Inst #676 = LT_BU
+  { 3, OperandInfo45 },  // Inst #675 = LT_B
+  { 3, OperandInfo75 },  // Inst #674 = LT_A_rr
+  { 2, OperandInfo55 },  // Inst #673 = LOOP_sbr
+  { 2, OperandInfo55 },  // Inst #672 = LOOP_brr
+  { 1, OperandInfo2 },  // Inst #671 = LOOPU_brr
+  { 2, OperandInfo55 },  // Inst #670 = LHA_abs
+  { 3, OperandInfo48 },  // Inst #669 = LEA_bol
+  { 3, OperandInfo48 },  // Inst #668 = LEA_bo_bso
+  { 2, OperandInfo55 },  // Inst #667 = LEA_abs
+  { 2, OperandInfo55 },  // Inst #666 = LD_W_sro_v110
+  { 2, OperandInfo55 },  // Inst #665 = LD_W_sro
+  { 2, OperandInfo58 },  // Inst #664 = LD_W_slro_v110
+  { 2, OperandInfo58 },  // Inst #663 = LD_W_slro
+  { 2, OperandInfo74 },  // Inst #662 = LD_W_slr_v110
+  { 2, OperandInfo74 },  // Inst #661 = LD_W_slr_post_v110
+  { 2, OperandInfo74 },  // Inst #660 = LD_W_slr_post
+  { 2, OperandInfo74 },  // Inst #659 = LD_W_slr
+  { 1, OperandInfo2 },  // Inst #658 = LD_W_sc
+  { 3, OperandInfo90 },  // Inst #657 = LD_W_bol
+  { 2, OperandInfo92 },  // Inst #656 = LD_W_bo_r
+  { 3, OperandInfo90 },  // Inst #655 = LD_W_bo_pre
+  { 3, OperandInfo90 },  // Inst #654 = LD_W_bo_pos
+  { 3, OperandInfo91 },  // Inst #653 = LD_W_bo_c
+  { 3, OperandInfo90 },  // Inst #652 = LD_W_bo_bso
+  { 2, OperandInfo58 },  // Inst #651 = LD_W_abs
+  { 2, OperandInfo92 },  // Inst #650 = LD_Q_bo_r
+  { 3, OperandInfo90 },  // Inst #649 = LD_Q_bo_pre
+  { 3, OperandInfo90 },  // Inst #648 = LD_Q_bo_pos
+  { 3, OperandInfo91 },  // Inst #647 = LD_Q_bo_c
+  { 3, OperandInfo90 },  // Inst #646 = LD_Q_bo_bso
+  { 2, OperandInfo58 },  // Inst #645 = LD_Q_abs
+  { 2, OperandInfo55 },  // Inst #644 = LD_H_sro_v110
+  { 2, OperandInfo55 },  // Inst #643 = LD_H_sro
+  { 2, OperandInfo58 },  // Inst #642 = LD_H_slro_v110
+  { 2, OperandInfo58 },  // Inst #641 = LD_H_slro
+  { 2, OperandInfo74 },  // Inst #640 = LD_H_slr_v110
+  { 2, OperandInfo74 },  // Inst #639 = LD_H_slr_post_v110
+  { 2, OperandInfo74 },  // Inst #638 = LD_H_slr_post
+  { 2, OperandInfo74 },  // Inst #637 = LD_H_slr
+  { 3, OperandInfo90 },  // Inst #636 = LD_H_bol
+  { 2, OperandInfo92 },  // Inst #635 = LD_H_bo_r
+  { 3, OperandInfo90 },  // Inst #634 = LD_H_bo_pre
+  { 3, OperandInfo90 },  // Inst #633 = LD_H_bo_pos
+  { 3, OperandInfo91 },  // Inst #632 = LD_H_bo_c
+  { 3, OperandInfo90 },  // Inst #631 = LD_H_bo_bso
+  { 2, OperandInfo58 },  // Inst #630 = LD_H_abs
+  { 3, OperandInfo90 },  // Inst #629 = LD_HU_bol
+  { 2, OperandInfo92 },  // Inst #628 = LD_HU_bo_r
+  { 3, OperandInfo90 },  // Inst #627 = LD_HU_bo_pre
+  { 3, OperandInfo90 },  // Inst #626 = LD_HU_bo_pos
+  { 3, OperandInfo91 },  // Inst #625 = LD_HU_bo_c
+  { 3, OperandInfo90 },  // Inst #624 = LD_HU_bo_bso
+  { 2, OperandInfo58 },  // Inst #623 = LD_HU_abs
+  { 2, OperandInfo68 },  // Inst #622 = LD_D_bo_r
+  { 3, OperandInfo66 },  // Inst #621 = LD_D_bo_pre
+  { 3, OperandInfo66 },  // Inst #620 = LD_D_bo_pos
+  { 3, OperandInfo67 },  // Inst #619 = LD_D_bo_c
+  { 3, OperandInfo66 },  // Inst #618 = LD_D_bo_bso
+  { 2, OperandInfo87 },  // Inst #617 = LD_D_abs
+  { 2, OperandInfo95 },  // Inst #616 = LD_DA_bo_r
+  { 3, OperandInfo93 },  // Inst #615 = LD_DA_bo_pre
+  { 3, OperandInfo93 },  // Inst #614 = LD_DA_bo_pos
+  { 3, OperandInfo94 },  // Inst #613 = LD_DA_bo_c
+  { 3, OperandInfo93 },  // Inst #612 = LD_DA_bo_bso
+  { 2, OperandInfo61 },  // Inst #611 = LD_DA_abs
+  { 2, OperandInfo55 },  // Inst #610 = LD_B_sro_v110
+  { 2, OperandInfo58 },  // Inst #609 = LD_B_slro_v110
+  { 2, OperandInfo74 },  // Inst #608 = LD_B_slr_v110
+  { 2, OperandInfo74 },  // Inst #607 = LD_B_slr_post_v110
+  { 3, OperandInfo90 },  // Inst #606 = LD_B_bol
+  { 2, OperandInfo92 },  // Inst #605 = LD_B_bo_r
+  { 3, OperandInfo90 },  // Inst #604 = LD_B_bo_pre
+  { 3, OperandInfo90 },  // Inst #603 = LD_B_bo_pos
+  { 3, OperandInfo91 },  // Inst #602 = LD_B_bo_c
+  { 3, OperandInfo90 },  // Inst #601 = LD_B_bo_bso
+  { 2, OperandInfo58 },  // Inst #600 = LD_B_abs
+  { 2, OperandInfo55 },  // Inst #599 = LD_BU_sro_v110
+  { 2, OperandInfo55 },  // Inst #598 = LD_BU_sro
+  { 2, OperandInfo58 },  // Inst #597 = LD_BU_slro_v110
+  { 2, OperandInfo58 },  // Inst #596 = LD_BU_slro
+  { 2, OperandInfo74 },  // Inst #595 = LD_BU_slr_v110
+  { 2, OperandInfo74 },  // Inst #594 = LD_BU_slr_post_v110
+  { 2, OperandInfo74 },  // Inst #593 = LD_BU_slr_post
+  { 2, OperandInfo74 },  // Inst #592 = LD_BU_slr
+  { 3, OperandInfo90 },  // Inst #591 = LD_BU_bol
+  { 2, OperandInfo92 },  // Inst #590 = LD_BU_bo_r
+  { 3, OperandInfo90 },  // Inst #589 = LD_BU_bo_pre
+  { 3, OperandInfo90 },  // Inst #588 = LD_BU_bo_pos
+  { 3, OperandInfo91 },  // Inst #587 = LD_BU_bo_c
+  { 3, OperandInfo90 },  // Inst #586 = LD_BU_bo_bso
+  { 2, OperandInfo58 },  // Inst #585 = LD_BU_abs
+  { 2, OperandInfo55 },  // Inst #584 = LD_A_sro_v110
+  { 2, OperandInfo55 },  // Inst #583 = LD_A_sro
+  { 2, OperandInfo55 },  // Inst #582 = LD_A_slro_v110
+  { 2, OperandInfo55 },  // Inst #581 = LD_A_slro
+  { 2, OperandInfo56 },  // Inst #580 = LD_A_slr_v110
+  { 2, OperandInfo56 },  // Inst #579 = LD_A_slr_post_v110
+  { 2, OperandInfo56 },  // Inst #578 = LD_A_slr_post
+  { 2, OperandInfo56 },  // Inst #577 = LD_A_slr
+  { 1, OperandInfo2 },  // Inst #576 = LD_A_sc
+  { 3, OperandInfo48 },  // Inst #575 = LD_A_bol
+  { 2, OperandInfo89 },  // Inst #574 = LD_A_bo_r
+  { 3, OperandInfo48 },  // Inst #573 = LD_A_bo_pre
+  { 3, OperandInfo48 },  // Inst #572 = LD_A_bo_pos
+  { 3, OperandInfo88 },  // Inst #571 = LD_A_bo_c
+  { 3, OperandInfo48 },  // Inst #570 = LD_A_bo_bso
+  { 2, OperandInfo55 },  // Inst #569 = LD_A_abs
+  { 2, OperandInfo55 },  // Inst #568 = LDUCX_bo_bso
+  { 1, OperandInfo2 },  // Inst #567 = LDUCX_abs
+  { 2, OperandInfo68 },  // Inst #566 = LDMST_bo_r
+  { 3, OperandInfo66 },  // Inst #565 = LDMST_bo_pre
+  { 3, OperandInfo66 },  // Inst #564 = LDMST_bo_pos
+  { 3, OperandInfo67 },  // Inst #563 = LDMST_bo_c
+  { 3, OperandInfo66 },  // Inst #562 = LDMST_bo_bso
+  { 2, OperandInfo87 },  // Inst #561 = LDMST_abs
+  { 2, OperandInfo55 },  // Inst #560 = LDLCX_bo_bso
+  { 1, OperandInfo2 },  // Inst #559 = LDLCX_abs
+  { 1, OperandInfo2 },  // Inst #558 = J_sb_v110
+  { 1, OperandInfo2 },  // Inst #557 = J_sb
+  { 1, OperandInfo2 },  // Inst #556 = J_b
+  { 2, OperandInfo58 },  // Inst #555 = JZ_sbr_v110
+  { 2, OperandInfo58 },  // Inst #554 = JZ_sbr
+  { 1, OperandInfo2 },  // Inst #553 = JZ_sb_v110
+  { 1, OperandInfo2 },  // Inst #552 = JZ_sb
+  { 2, OperandInfo86 },  // Inst #551 = JZ_T_sbrn_v110
+  { 2, OperandInfo86 },  // Inst #550 = JZ_T_sbrn
+  { 3, OperandInfo85 },  // Inst #549 = JZ_T_brn
+  { 2, OperandInfo55 },  // Inst #548 = JZ_A_sbr
+  { 2, OperandInfo55 },  // Inst #547 = JZ_A_brr
+  { 2, OperandInfo58 },  // Inst #546 = JNZ_sbr_v110
+  { 2, OperandInfo58 },  // Inst #545 = JNZ_sbr
+  { 1, OperandInfo2 },  // Inst #544 = JNZ_sb_v110
+  { 1, OperandInfo2 },  // Inst #543 = JNZ_sb
+  { 2, OperandInfo86 },  // Inst #542 = JNZ_T_sbrn_v110
+  { 2, OperandInfo86 },  // Inst #541 = JNZ_T_sbrn
+  { 3, OperandInfo85 },  // Inst #540 = JNZ_T_brn
+  { 2, OperandInfo55 },  // Inst #539 = JNZ_A_sbr
+  { 2, OperandInfo55 },  // Inst #538 = JNZ_A_brr
+  { 2, OperandInfo58 },  // Inst #537 = JNE_sbr_v110
+  { 2, OperandInfo58 },  // Inst #536 = JNE_sbr2
+  { 2, OperandInfo58 },  // Inst #535 = JNE_sbr1
+  { 2, OperandInfo7 },  // Inst #534 = JNE_sbc_v110
+  { 2, OperandInfo7 },  // Inst #533 = JNE_sbc2
+  { 2, OperandInfo7 },  // Inst #532 = JNE_sbc1
+  { 3, OperandInfo46 },  // Inst #531 = JNE_brr
+  { 3, OperandInfo84 },  // Inst #530 = JNE_brc
+  { 3, OperandInfo48 },  // Inst #529 = JNE_A_brr
+  { 3, OperandInfo46 },  // Inst #528 = JNEI_brr
+  { 3, OperandInfo84 },  // Inst #527 = JNEI_brc
+  { 3, OperandInfo46 },  // Inst #526 = JNED_brr
+  { 3, OperandInfo84 },  // Inst #525 = JNED_brc
+  { 1, OperandInfo2 },  // Inst #524 = JL_b
+  { 3, OperandInfo46 },  // Inst #523 = JLT_brr
+  { 3, OperandInfo84 },  // Inst #522 = JLT_brc
+  { 3, OperandInfo46 },  // Inst #521 = JLT_U_brr
+  { 3, OperandInfo84 },  // Inst #520 = JLT_U_brc
+  { 2, OperandInfo58 },  // Inst #519 = JLTZ_sbr_v110
+  { 2, OperandInfo58 },  // Inst #518 = JLTZ_sbr
+  { 1, OperandInfo65 },  // Inst #517 = JLI_rr_v110
+  { 1, OperandInfo65 },  // Inst #516 = JLI_rr
+  { 2, OperandInfo58 },  // Inst #515 = JLEZ_sbr_v110
+  { 2, OperandInfo58 },  // Inst #514 = JLEZ_sbr
+  { 1, OperandInfo2 },  // Inst #513 = JLA_b
+  { 1, OperandInfo65 },  // Inst #512 = JI_sr
+  { 1, OperandInfo65 },  // Inst #511 = JI_sbr_v110
+  { 1, OperandInfo65 },  // Inst #510 = JI_rr_v110
+  { 1, OperandInfo65 },  // Inst #509 = JI_rr
+  { 2, OperandInfo58 },  // Inst #508 = JGTZ_sbr_v110
+  { 2, OperandInfo58 },  // Inst #507 = JGTZ_sbr
+  { 3, OperandInfo46 },  // Inst #506 = JGE_brr
+  { 3, OperandInfo84 },  // Inst #505 = JGE_brc
+  { 3, OperandInfo46 },  // Inst #504 = JGE_U_brr
+  { 3, OperandInfo84 },  // Inst #503 = JGE_U_brc
+  { 2, OperandInfo58 },  // Inst #502 = JGEZ_sbr_v110
+  { 2, OperandInfo58 },  // Inst #501 = JGEZ_sbr
+  { 2, OperandInfo58 },  // Inst #500 = JEQ_sbr_v110
+  { 2, OperandInfo58 },  // Inst #499 = JEQ_sbr2
+  { 2, OperandInfo58 },  // Inst #498 = JEQ_sbr1
+  { 2, OperandInfo7 },  // Inst #497 = JEQ_sbc_v110
+  { 2, OperandInfo7 },  // Inst #496 = JEQ_sbc2
+  { 2, OperandInfo7 },  // Inst #495 = JEQ_sbc1
+  { 3, OperandInfo46 },  // Inst #494 = JEQ_brr
+  { 3, OperandInfo84 },  // Inst #493 = JEQ_brc
+  { 3, OperandInfo48 },  // Inst #492 = JEQ_A_brr
+  { 1, OperandInfo2 },  // Inst #491 = JA_b
+  { 4, OperandInfo73 },  // Inst #490 = IXMIN_rrr
+  { 4, OperandInfo73 },  // Inst #489 = IXMIN_U_rrr
+  { 4, OperandInfo73 },  // Inst #488 = IXMAX_rrr
+  { 4, OperandInfo73 },  // Inst #487 = IXMAX_U_rrr
+  { 2, OperandInfo47 },  // Inst #486 = ITOF_rr
+  { 0, 0 },  // Inst #485 = ISYNC_sys
+  { 5, OperandInfo59 },  // Inst #484 = INS_T
+  { 5, OperandInfo59 },  // Inst #483 = INSN_T
+  { 5, OperandInfo77 },  // Inst #482 = INSERT_rrrw
+  { 4, OperandInfo83 },  // Inst #481 = INSERT_rrrr
+  { 5, OperandInfo69 },  // Inst #480 = INSERT_rrpw
+  { 5, OperandInfo69 },  // Inst #479 = INSERT_rcrw
+  { 4, OperandInfo82 },  // Inst #478 = INSERT_rcrr
+  { 5, OperandInfo81 },  // Inst #477 = INSERT_rcpw
+  { 5, OperandInfo80 },  // Inst #476 = IMASK_rrrw
+  { 5, OperandInfo79 },  // Inst #475 = IMASK_rrpw
+  { 5, OperandInfo79 },  // Inst #474 = IMASK_rcrw
+  { 5, OperandInfo78 },  // Inst #473 = IMASK_rcpw
+  { 2, OperandInfo47 },  // Inst #472 = HPTOF_rr
+  { 3, OperandInfo45 },  // Inst #471 = GE_rr
+  { 3, OperandInfo46 },  // Inst #470 = GE_rc
+  { 3, OperandInfo45 },  // Inst #469 = GE_U_rr
+  { 3, OperandInfo46 },  // Inst #468 = GE_U_rc
+  { 3, OperandInfo75 },  // Inst #467 = GE_A_rr
+  { 2, OperandInfo47 },  // Inst #466 = FTOU_rr
+  { 2, OperandInfo47 },  // Inst #465 = FTOUZ_rr
+  { 3, OperandInfo45 },  // Inst #464 = FTOQ31_rr
+  { 3, OperandInfo45 },  // Inst #463 = FTOQ31Z_rr
+  { 2, OperandInfo47 },  // Inst #462 = FTOI_rr
+  { 2, OperandInfo47 },  // Inst #461 = FTOIZ_rr
+  { 2, OperandInfo47 },  // Inst #460 = FTOHP_rr
+  { 0, 0 },  // Inst #459 = FRET_sys
+  { 0, 0 },  // Inst #458 = FRET_sr
+  { 1, OperandInfo2 },  // Inst #457 = FCALL_b
+  { 1, OperandInfo65 },  // Inst #456 = FCALLA_i
+  { 1, OperandInfo2 },  // Inst #455 = FCALLA_b
+  { 5, OperandInfo77 },  // Inst #454 = EXTR_rrrw
+  { 3, OperandInfo76 },  // Inst #453 = EXTR_rrrr
+  { 5, OperandInfo69 },  // Inst #452 = EXTR_rrpw
+  { 5, OperandInfo77 },  // Inst #451 = EXTR_U_rrrw
+  { 3, OperandInfo76 },  // Inst #450 = EXTR_U_rrrr
+  { 5, OperandInfo69 },  // Inst #449 = EXTR_U_rrpw
+  { 2, OperandInfo47 },  // Inst #448 = EQ_srr
+  { 2, OperandInfo58 },  // Inst #447 = EQ_src
+  { 3, OperandInfo45 },  // Inst #446 = EQ_rr
+  { 3, OperandInfo46 },  // Inst #445 = EQ_rc
+  { 3, OperandInfo45 },  // Inst #444 = EQ_W_rr
+  { 3, OperandInfo45 },  // Inst #443 = EQ_H_rr
+  { 3, OperandInfo45 },  // Inst #442 = EQ_B_rr
+  { 3, OperandInfo75 },  // Inst #441 = EQ_A_rr
+  { 2, OperandInfo74 },  // Inst #440 = EQZ_A_rr
+  { 3, OperandInfo45 },  // Inst #439 = EQANY_H_rr
+  { 3, OperandInfo46 },  // Inst #438 = EQANY_H_rc
+  { 3, OperandInfo45 },  // Inst #437 = EQANY_B_rr
+  { 3, OperandInfo46 },  // Inst #436 = EQANY_B_rc
+  { 0, 0 },  // Inst #435 = ENABLE_sys
+  { 2, OperandInfo60 },  // Inst #434 = DVSTEPv110
+  { 4, OperandInfo73 },  // Inst #433 = DVSTEP_rrrv110
+  { 4, OperandInfo73 },  // Inst #432 = DVSTEP_rrr
+  { 2, OperandInfo60 },  // Inst #431 = DVSTEP_Uv110
+  { 4, OperandInfo73 },  // Inst #430 = DVSTEP_U_rrrv110
+  { 4, OperandInfo73 },  // Inst #429 = DVSTEP_U_rrr
+  { 3, OperandInfo72 },  // Inst #428 = DVINIT_rr_v110
+  { 3, OperandInfo72 },  // Inst #427 = DVINIT_rr
+  { 3, OperandInfo72 },  // Inst #426 = DVINIT_U_rr_v110
+  { 3, OperandInfo72 },  // Inst #425 = DVINIT_U_rr
+  { 3, OperandInfo72 },  // Inst #424 = DVINIT_H_rr_v110
+  { 3, OperandInfo72 },  // Inst #423 = DVINIT_H_rr
+  { 3, OperandInfo72 },  // Inst #422 = DVINIT_HU_rr_v110
+  { 3, OperandInfo72 },  // Inst #421 = DVINIT_HU_rr
+  { 3, OperandInfo72 },  // Inst #420 = DVINIT_B_rr_v110
+  { 3, OperandInfo72 },  // Inst #419 = DVINIT_B_rr
+  { 3, OperandInfo72 },  // Inst #418 = DVINIT_BU_rr_v110
+  { 3, OperandInfo72 },  // Inst #417 = DVINIT_BU_rr
+  { 2, OperandInfo60 },  // Inst #416 = DVADJ_srr_v110
+  { 4, OperandInfo73 },  // Inst #415 = DVADJ_rrr_v110
+  { 4, OperandInfo73 },  // Inst #414 = DVADJ_rrr
+  { 0, 0 },  // Inst #413 = DSYNC_sys
+  { 3, OperandInfo72 },  // Inst #412 = DIV_rr
+  { 3, OperandInfo72 },  // Inst #411 = DIV_U_rr
+  { 3, OperandInfo45 },  // Inst #410 = DIV_F_rr
+  { 1, OperandInfo71 },  // Inst #409 = DISABLE_sys_1
+  { 0, 0 },  // Inst #408 = DISABLE_sys
+  { 4, OperandInfo70 },  // Inst #407 = DIFSC_A_rr_v110
+  { 4, OperandInfo57 },  // Inst #406 = DEXTR_rrrr
+  { 5, OperandInfo69 },  // Inst #405 = DEXTR_rrpw
+  { 0, 0 },  // Inst #404 = DEBUG_sys
+  { 0, 0 },  // Inst #403 = DEBUG_sr
+  { 4, OperandInfo57 },  // Inst #402 = CSUB_rrr
+  { 4, OperandInfo63 },  // Inst #401 = CSUB_A__rrr_v110
+  { 4, OperandInfo57 },  // Inst #400 = CSUBN_rrr
+  { 4, OperandInfo63 },  // Inst #399 = CSUBN_A__rrr_v110
+  { 4, OperandInfo57 },  // Inst #398 = CRCN_rrr
+  { 3, OperandInfo45 },  // Inst #397 = CRC32_B_rr
+  { 3, OperandInfo45 },  // Inst #396 = CRC32L_W_rr
+  { 3, OperandInfo45 },  // Inst #395 = CRC32B_W_rr
+  { 3, OperandInfo45 },  // Inst #394 = CMP_F_rr
+  { 2, OperandInfo68 },  // Inst #393 = CMPSWAP_W_bo_r
+  { 3, OperandInfo66 },  // Inst #392 = CMPSWAP_W_bo_pre
+  { 3, OperandInfo66 },  // Inst #391 = CMPSWAP_W_bo_pos
+  { 3, OperandInfo67 },  // Inst #390 = CMPSWAP_W_bo_c
+  { 3, OperandInfo66 },  // Inst #389 = CMPSWAP_W_bo_bso
+  { 2, OperandInfo47 },  // Inst #388 = CMOV_srr
+  { 2, OperandInfo58 },  // Inst #387 = CMOV_src
+  { 2, OperandInfo47 },  // Inst #386 = CMOVN_srr
+  { 2, OperandInfo58 },  // Inst #385 = CMOVN_src
+  { 2, OperandInfo47 },  // Inst #384 = CLZ_rr
+  { 2, OperandInfo47 },  // Inst #383 = CLZ_H_rr
+  { 2, OperandInfo47 },  // Inst #382 = CLZ_B_rr_v110
+  { 2, OperandInfo47 },  // Inst #381 = CLS_rr
+  { 2, OperandInfo47 },  // Inst #380 = CLS_H_rr
+  { 2, OperandInfo47 },  // Inst #379 = CLS_B_rr_v110
+  { 2, OperandInfo47 },  // Inst #378 = CLO_rr
+  { 2, OperandInfo47 },  // Inst #377 = CLO_H_rr
+  { 2, OperandInfo47 },  // Inst #376 = CLO_B_rr_v110
+  { 1, OperandInfo2 },  // Inst #375 = CALL_sb
+  { 1, OperandInfo2 },  // Inst #374 = CALL_b
+  { 1, OperandInfo65 },  // Inst #373 = CALLI_rr_v110
+  { 1, OperandInfo65 },  // Inst #372 = CALLI_rr
+  { 1, OperandInfo2 },  // Inst #371 = CALLA_b
+  { 2, OperandInfo47 },  // Inst #370 = CADD_srr_v110
+  { 2, OperandInfo58 },  // Inst #369 = CADD_src
+  { 4, OperandInfo57 },  // Inst #368 = CADD_rrr
+  { 4, OperandInfo64 },  // Inst #367 = CADD_rcr
+  { 4, OperandInfo63 },  // Inst #366 = CADD_A_rrr_v110
+  { 4, OperandInfo52 },  // Inst #365 = CADD_A_rcr_v110
+  { 2, OperandInfo47 },  // Inst #364 = CADDN_srr_v110
+  { 2, OperandInfo58 },  // Inst #363 = CADDN_src
+  { 4, OperandInfo57 },  // Inst #362 = CADDN_rrr
+  { 4, OperandInfo64 },  // Inst #361 = CADDN_rcr
+  { 4, OperandInfo63 },  // Inst #360 = CADDN_A_rrr_v110
+  { 4, OperandInfo52 },  // Inst #359 = CADDN_A_rcr_v110
+  { 2, OperandInfo55 },  // Inst #358 = CACHEI_W_bo_pre
+  { 2, OperandInfo55 },  // Inst #357 = CACHEI_W_bo_pos
+  { 2, OperandInfo55 },  // Inst #356 = CACHEI_W_bo_bso
+  { 2, OperandInfo55 },  // Inst #355 = CACHEI_WI_bo_pre
+  { 2, OperandInfo55 },  // Inst #354 = CACHEI_WI_bo_pos
+  { 2, OperandInfo55 },  // Inst #353 = CACHEI_WI_bo_bso
+  { 2, OperandInfo55 },  // Inst #352 = CACHEI_I_bo_pre
+  { 2, OperandInfo55 },  // Inst #351 = CACHEI_I_bo_pos
+  { 2, OperandInfo55 },  // Inst #350 = CACHEI_I_bo_bso
+  { 1, OperandInfo62 },  // Inst #349 = CACHEA_W_bo_r
+  { 2, OperandInfo55 },  // Inst #348 = CACHEA_W_bo_pre
+  { 2, OperandInfo55 },  // Inst #347 = CACHEA_W_bo_pos
+  { 2, OperandInfo61 },  // Inst #346 = CACHEA_W_bo_c
+  { 2, OperandInfo55 },  // Inst #345 = CACHEA_W_bo_bso
+  { 1, OperandInfo62 },  // Inst #344 = CACHEA_WI_bo_r
+  { 2, OperandInfo55 },  // Inst #343 = CACHEA_WI_bo_pre
+  { 2, OperandInfo55 },  // Inst #342 = CACHEA_WI_bo_pos
+  { 2, OperandInfo61 },  // Inst #341 = CACHEA_WI_bo_c
+  { 2, OperandInfo55 },  // Inst #340 = CACHEA_WI_bo_bso
+  { 1, OperandInfo62 },  // Inst #339 = CACHEA_I_bo_r
+  { 2, OperandInfo55 },  // Inst #338 = CACHEA_I_bo_pre
+  { 2, OperandInfo55 },  // Inst #337 = CACHEA_I_bo_pos
+  { 2, OperandInfo61 },  // Inst #336 = CACHEA_I_bo_c
+  { 2, OperandInfo55 },  // Inst #335 = CACHEA_I_bo_bso
+  { 2, OperandInfo60 },  // Inst #334 = BSPLIT_rr_v110
+  { 2, OperandInfo60 },  // Inst #333 = BSPLIT_rr
+  { 3, OperandInfo45 },  // Inst #332 = BMERGE_rr
+  { 3, OperandInfo45 },  // Inst #331 = BMERGAE_rr_v110
+  { 1, OperandInfo2 },  // Inst #330 = BISR_sc_v110
+  { 1, OperandInfo2 },  // Inst #329 = BISR_sc
+  { 1, OperandInfo2 },  // Inst #328 = BISR_rc_v161
+  { 1, OperandInfo2 },  // Inst #327 = BISR_rc
+  { 2, OperandInfo47 },  // Inst #326 = AND_srr_v110
+  { 2, OperandInfo47 },  // Inst #325 = AND_srr
+  { 1, OperandInfo2 },  // Inst #324 = AND_sc_v110
+  { 1, OperandInfo2 },  // Inst #323 = AND_sc
+  { 3, OperandInfo45 },  // Inst #322 = AND_rr
+  { 3, OperandInfo46 },  // Inst #321 = AND_rc
+  { 5, OperandInfo59 },  // Inst #320 = AND_T
+  { 5, OperandInfo59 },  // Inst #319 = AND_OR_T
+  { 5, OperandInfo59 },  // Inst #318 = AND_NOR_T
+  { 3, OperandInfo45 },  // Inst #317 = AND_NE_rr
+  { 3, OperandInfo46 },  // Inst #316 = AND_NE_rc
+  { 3, OperandInfo45 },  // Inst #315 = AND_LT_rr
+  { 3, OperandInfo46 },  // Inst #314 = AND_LT_rc
+  { 3, OperandInfo45 },  // Inst #313 = AND_LT_U_rr
+  { 3, OperandInfo46 },  // Inst #312 = AND_LT_U_rc
+  { 3, OperandInfo45 },  // Inst #311 = AND_GE_rr
+  { 3, OperandInfo46 },  // Inst #310 = AND_GE_rc
+  { 3, OperandInfo45 },  // Inst #309 = AND_GE_U_rr
+  { 3, OperandInfo46 },  // Inst #308 = AND_GE_U_rc
+  { 3, OperandInfo45 },  // Inst #307 = AND_EQ_rr
+  { 3, OperandInfo46 },  // Inst #306 = AND_EQ_rc
+  { 5, OperandInfo59 },  // Inst #305 = AND_AND_T
+  { 5, OperandInfo59 },  // Inst #304 = AND_ANDN_T
+  { 3, OperandInfo45 },  // Inst #303 = ANDN_rr
+  { 3, OperandInfo46 },  // Inst #302 = ANDN_rc
+  { 5, OperandInfo59 },  // Inst #301 = ANDN_T
+  { 2, OperandInfo47 },  // Inst #300 = ADD_srr_a15
+  { 2, OperandInfo47 },  // Inst #299 = ADD_srr_15a
+  { 2, OperandInfo47 },  // Inst #298 = ADD_srr
+  { 2, OperandInfo58 },  // Inst #297 = ADD_src_a15
+  { 2, OperandInfo58 },  // Inst #296 = ADD_src_15a
+  { 2, OperandInfo58 },  // Inst #295 = ADD_src
+  { 3, OperandInfo45 },  // Inst #294 = ADD_rr
+  { 3, OperandInfo46 },  // Inst #293 = ADD_rc
+  { 3, OperandInfo45 },  // Inst #292 = ADD_H_rr
+  { 4, OperandInfo57 },  // Inst #291 = ADD_F_rrr
+  { 3, OperandInfo45 },  // Inst #290 = ADD_B_rr
+  { 2, OperandInfo56 },  // Inst #289 = ADD_A_srr
+  { 2, OperandInfo55 },  // Inst #288 = ADD_A_src
+  { 3, OperandInfo54 },  // Inst #287 = ADD_A_rr
+  { 3, OperandInfo45 },  // Inst #286 = ADDX_rr
+  { 3, OperandInfo46 },  // Inst #285 = ADDX_rc
+  { 2, OperandInfo47 },  // Inst #284 = ADDS_srr
+  { 3, OperandInfo45 },  // Inst #283 = ADDS_rr
+  { 3, OperandInfo46 },  // Inst #282 = ADDS_rc
+  { 3, OperandInfo46 },  // Inst #281 = ADDS_U_rc
+  { 3, OperandInfo45 },  // Inst #280 = ADDS_U
+  { 3, OperandInfo45 },  // Inst #279 = ADDS_HU
+  { 3, OperandInfo45 },  // Inst #278 = ADDS_H
+  { 3, OperandInfo45 },  // Inst #277 = ADDS_B_rr
+  { 3, OperandInfo45 },  // Inst #276 = ADDS_BU_rr_v110
+  { 3, OperandInfo53 },  // Inst #275 = ADDSC_A_srrs_v110
+  { 3, OperandInfo48 },  // Inst #274 = ADDSC_A_srrs
+  { 4, OperandInfo52 },  // Inst #273 = ADDSC_A_rr_v110
+  { 4, OperandInfo51 },  // Inst #272 = ADDSC_A_rr
+  { 3, OperandInfo50 },  // Inst #271 = ADDSC_AT_rr_v110
+  { 3, OperandInfo49 },  // Inst #270 = ADDSC_AT_rr
+  { 3, OperandInfo46 },  // Inst #269 = ADDI_rlc
+  { 3, OperandInfo46 },  // Inst #268 = ADDIH_rlc
+  { 3, OperandInfo48 },  // Inst #267 = ADDIH_A_rlc
+  { 3, OperandInfo45 },  // Inst #266 = ADDC_rr
+  { 3, OperandInfo46 },  // Inst #265 = ADDC_rc
+  { 2, OperandInfo47 },  // Inst #264 = ABS_rr
+  { 2, OperandInfo47 },  // Inst #263 = ABS_H_rr
+  { 2, OperandInfo47 },  // Inst #262 = ABS_B_rr
+  { 3, OperandInfo45 },  // Inst #261 = ABSS_rr
+  { 3, OperandInfo45 },  // Inst #260 = ABSS_H_rr
+  { 3, OperandInfo45 },  // Inst #259 = ABSS_B_rr_v110
+  { 3, OperandInfo45 },  // Inst #258 = ABSDIF_rr
+  { 3, OperandInfo46 },  // Inst #257 = ABSDIF_rc
+  { 3, OperandInfo45 },  // Inst #256 = ABSDIF_H_rr
+  { 3, OperandInfo45 },  // Inst #255 = ABSDIF_B_rr
+  { 3, OperandInfo45 },  // Inst #254 = ABSDIFS_rr
+  { 3, OperandInfo45 },  // Inst #253 = ABSDIFS_rc
+  { 3, OperandInfo45 },  // Inst #252 = ABSDIFS_H_rr
+  { 3, OperandInfo45 },  // Inst #251 = ABSDIFS_B_rr_v110
+  { 4, OperandInfo44 },  // Inst #250 = G_UBFX
+  { 4, OperandInfo44 },  // Inst #249 = G_SBFX
+  { 2, OperandInfo23 },  // Inst #248 = G_VECREDUCE_UMIN
+  { 2, OperandInfo23 },  // Inst #247 = G_VECREDUCE_UMAX
+  { 2, OperandInfo23 },  // Inst #246 = G_VECREDUCE_SMIN
+  { 2, OperandInfo23 },  // Inst #245 = G_VECREDUCE_SMAX
+  { 2, OperandInfo23 },  // Inst #244 = G_VECREDUCE_XOR
+  { 2, OperandInfo23 },  // Inst #243 = G_VECREDUCE_OR
+  { 2, OperandInfo23 },  // Inst #242 = G_VECREDUCE_AND
+  { 2, OperandInfo23 },  // Inst #241 = G_VECREDUCE_MUL
+  { 2, OperandInfo23 },  // Inst #240 = G_VECREDUCE_ADD
+  { 2, OperandInfo23 },  // Inst #239 = G_VECREDUCE_FMIN
+  { 2, OperandInfo23 },  // Inst #238 = G_VECREDUCE_FMAX
+  { 2, OperandInfo23 },  // Inst #237 = G_VECREDUCE_FMUL
+  { 2, OperandInfo23 },  // Inst #236 = G_VECREDUCE_FADD
+  { 3, OperandInfo40 },  // Inst #235 = G_VECREDUCE_SEQ_FMUL
+  { 3, OperandInfo40 },  // Inst #234 = G_VECREDUCE_SEQ_FADD
+  { 3, OperandInfo22 },  // Inst #233 = G_BZERO
+  { 4, OperandInfo43 },  // Inst #232 = G_MEMSET
+  { 4, OperandInfo43 },  // Inst #231 = G_MEMMOVE
+  { 3, OperandInfo40 },  // Inst #230 = G_MEMCPY_INLINE
+  { 4, OperandInfo43 },  // Inst #229 = G_MEMCPY
+  { 2, OperandInfo42 },  // Inst #228 = G_WRITE_REGISTER
+  { 2, OperandInfo21 },  // Inst #227 = G_READ_REGISTER
+  { 2, OperandInfo25 },  // Inst #226 = G_STRICT_FSQRT
+  { 4, OperandInfo19 },  // Inst #225 = G_STRICT_FMA
+  { 3, OperandInfo18 },  // Inst #224 = G_STRICT_FREM
+  { 3, OperandInfo18 },  // Inst #223 = G_STRICT_FDIV
+  { 3, OperandInfo18 },  // Inst #222 = G_STRICT_FMUL
+  { 3, OperandInfo18 },  // Inst #221 = G_STRICT_FSUB
+  { 3, OperandInfo18 },  // Inst #220 = G_STRICT_FADD
+  { 3, OperandInfo26 },  // Inst #219 = G_DYN_STACKALLOC
+  { 2, OperandInfo21 },  // Inst #218 = G_JUMP_TABLE
+  { 2, OperandInfo21 },  // Inst #217 = G_BLOCK_ADDR
+  { 2, OperandInfo23 },  // Inst #216 = G_ADDRSPACE_CAST
+  { 2, OperandInfo25 },  // Inst #215 = G_FNEARBYINT
+  { 2, OperandInfo25 },  // Inst #214 = G_FRINT
+  { 2, OperandInfo25 },  // Inst #213 = G_FFLOOR
+  { 2, OperandInfo25 },  // Inst #212 = G_FSQRT
+  { 2, OperandInfo25 },  // Inst #211 = G_FSIN
+  { 2, OperandInfo25 },  // Inst #210 = G_FCOS
+  { 2, OperandInfo25 },  // Inst #209 = G_FCEIL
+  { 2, OperandInfo25 },  // Inst #208 = G_BITREVERSE
+  { 2, OperandInfo25 },  // Inst #207 = G_BSWAP
+  { 2, OperandInfo23 },  // Inst #206 = G_CTPOP
+  { 2, OperandInfo23 },  // Inst #205 = G_CTLZ_ZERO_UNDEF
+  { 2, OperandInfo23 },  // Inst #204 = G_CTLZ
+  { 2, OperandInfo23 },  // Inst #203 = G_CTTZ_ZERO_UNDEF
+  { 2, OperandInfo23 },  // Inst #202 = G_CTTZ
+  { 4, OperandInfo41 },  // Inst #201 = G_SHUFFLE_VECTOR
+  { 3, OperandInfo40 },  // Inst #200 = G_EXTRACT_VECTOR_ELT
+  { 4, OperandInfo39 },  // Inst #199 = G_INSERT_VECTOR_ELT
+  { 3, OperandInfo38 },  // Inst #198 = G_BRJT
+  { 1, OperandInfo2 },  // Inst #197 = G_BR
+  { 2, OperandInfo23 },  // Inst #196 = G_LLROUND
+  { 2, OperandInfo23 },  // Inst #195 = G_LROUND
+  { 2, OperandInfo25 },  // Inst #194 = G_ABS
+  { 3, OperandInfo18 },  // Inst #193 = G_UMAX
+  { 3, OperandInfo18 },  // Inst #192 = G_UMIN
+  { 3, OperandInfo18 },  // Inst #191 = G_SMAX
+  { 3, OperandInfo18 },  // Inst #190 = G_SMIN
+  { 3, OperandInfo33 },  // Inst #189 = G_PTRMASK
+  { 3, OperandInfo33 },  // Inst #188 = G_PTR_ADD
+  { 3, OperandInfo18 },  // Inst #187 = G_FMAXIMUM
+  { 3, OperandInfo18 },  // Inst #186 = G_FMINIMUM
+  { 3, OperandInfo18 },  // Inst #185 = G_FMAXNUM_IEEE
+  { 3, OperandInfo18 },  // Inst #184 = G_FMINNUM_IEEE
+  { 3, OperandInfo18 },  // Inst #183 = G_FMAXNUM
+  { 3, OperandInfo18 },  // Inst #182 = G_FMINNUM
+  { 2, OperandInfo25 },  // Inst #181 = G_FCANONICALIZE
+  { 3, OperandInfo32 },  // Inst #180 = G_IS_FPCLASS
+  { 3, OperandInfo33 },  // Inst #179 = G_FCOPYSIGN
+  { 2, OperandInfo25 },  // Inst #178 = G_FABS
+  { 2, OperandInfo23 },  // Inst #177 = G_UITOFP
+  { 2, OperandInfo23 },  // Inst #176 = G_SITOFP
+  { 2, OperandInfo23 },  // Inst #175 = G_FPTOUI
+  { 2, OperandInfo23 },  // Inst #174 = G_FPTOSI
+  { 2, OperandInfo23 },  // Inst #173 = G_FPTRUNC
+  { 2, OperandInfo23 },  // Inst #172 = G_FPEXT
+  { 2, OperandInfo25 },  // Inst #171 = G_FNEG
+  { 2, OperandInfo25 },  // Inst #170 = G_FLOG10
+  { 2, OperandInfo25 },  // Inst #169 = G_FLOG2
+  { 2, OperandInfo25 },  // Inst #168 = G_FLOG
+  { 2, OperandInfo25 },  // Inst #167 = G_FEXP2
+  { 2, OperandInfo25 },  // Inst #166 = G_FEXP
+  { 3, OperandInfo33 },  // Inst #165 = G_FPOWI
+  { 3, OperandInfo18 },  // Inst #164 = G_FPOW
+  { 3, OperandInfo18 },  // Inst #163 = G_FREM
+  { 3, OperandInfo18 },  // Inst #162 = G_FDIV
+  { 4, OperandInfo19 },  // Inst #161 = G_FMAD
+  { 4, OperandInfo19 },  // Inst #160 = G_FMA
+  { 3, OperandInfo18 },  // Inst #159 = G_FMUL
+  { 3, OperandInfo18 },  // Inst #158 = G_FSUB
+  { 3, OperandInfo18 },  // Inst #157 = G_FADD
+  { 4, OperandInfo37 },  // Inst #156 = G_UDIVFIXSAT
+  { 4, OperandInfo37 },  // Inst #155 = G_SDIVFIXSAT
+  { 4, OperandInfo37 },  // Inst #154 = G_UDIVFIX
+  { 4, OperandInfo37 },  // Inst #153 = G_SDIVFIX
+  { 4, OperandInfo37 },  // Inst #152 = G_UMULFIXSAT
+  { 4, OperandInfo37 },  // Inst #151 = G_SMULFIXSAT
+  { 4, OperandInfo37 },  // Inst #150 = G_UMULFIX
+  { 4, OperandInfo37 },  // Inst #149 = G_SMULFIX
+  { 3, OperandInfo33 },  // Inst #148 = G_SSHLSAT
+  { 3, OperandInfo33 },  // Inst #147 = G_USHLSAT
+  { 3, OperandInfo18 },  // Inst #146 = G_SSUBSAT
+  { 3, OperandInfo18 },  // Inst #145 = G_USUBSAT
+  { 3, OperandInfo18 },  // Inst #144 = G_SADDSAT
+  { 3, OperandInfo18 },  // Inst #143 = G_UADDSAT
+  { 3, OperandInfo18 },  // Inst #142 = G_SMULH
+  { 3, OperandInfo18 },  // Inst #141 = G_UMULH
+  { 4, OperandInfo30 },  // Inst #140 = G_SMULO
+  { 4, OperandInfo30 },  // Inst #139 = G_UMULO
+  { 5, OperandInfo36 },  // Inst #138 = G_SSUBE
+  { 4, OperandInfo30 },  // Inst #137 = G_SSUBO
+  { 5, OperandInfo36 },  // Inst #136 = G_SADDE
+  { 4, OperandInfo30 },  // Inst #135 = G_SADDO
+  { 5, OperandInfo36 },  // Inst #134 = G_USUBE
+  { 4, OperandInfo30 },  // Inst #133 = G_USUBO
+  { 5, OperandInfo36 },  // Inst #132 = G_UADDE
+  { 4, OperandInfo30 },  // Inst #131 = G_UADDO
+  { 4, OperandInfo30 },  // Inst #130 = G_SELECT
+  { 4, OperandInfo35 },  // Inst #129 = G_FCMP
+  { 4, OperandInfo35 },  // Inst #128 = G_ICMP
+  { 3, OperandInfo33 },  // Inst #127 = G_ROTL
+  { 3, OperandInfo33 },  // Inst #126 = G_ROTR
+  { 4, OperandInfo34 },  // Inst #125 = G_FSHR
+  { 4, OperandInfo34 },  // Inst #124 = G_FSHL
+  { 3, OperandInfo33 },  // Inst #123 = G_ASHR
+  { 3, OperandInfo33 },  // Inst #122 = G_LSHR
+  { 3, OperandInfo33 },  // Inst #121 = G_SHL
+  { 2, OperandInfo23 },  // Inst #120 = G_ZEXT
+  { 3, OperandInfo17 },  // Inst #119 = G_SEXT_INREG
+  { 2, OperandInfo23 },  // Inst #118 = G_SEXT
+  { 3, OperandInfo32 },  // Inst #117 = G_VAARG
+  { 1, OperandInfo20 },  // Inst #116 = G_VASTART
+  { 2, OperandInfo21 },  // Inst #115 = G_FCONSTANT
+  { 2, OperandInfo21 },  // Inst #114 = G_CONSTANT
+  { 2, OperandInfo23 },  // Inst #113 = G_TRUNC
+  { 2, OperandInfo23 },  // Inst #112 = G_ANYEXT
+  { 1, OperandInfo2 },  // Inst #111 = G_INTRINSIC_W_SIDE_EFFECTS
+  { 1, OperandInfo2 },  // Inst #110 = G_INTRINSIC
+  { 0, 0 },  // Inst #109 = G_INVOKE_REGION_START
+  { 1, OperandInfo20 },  // Inst #108 = G_BRINDIRECT
+  { 2, OperandInfo21 },  // Inst #107 = G_BRCOND
+  { 2, OperandInfo10 },  // Inst #106 = G_FENCE
+  { 3, OperandInfo31 },  // Inst #105 = G_ATOMICRMW_UDEC_WRAP
+  { 3, OperandInfo31 },  // Inst #104 = G_ATOMICRMW_UINC_WRAP
+  { 3, OperandInfo31 },  // Inst #103 = G_ATOMICRMW_FMIN
+  { 3, OperandInfo31 },  // Inst #102 = G_ATOMICRMW_FMAX
+  { 3, OperandInfo31 },  // Inst #101 = G_ATOMICRMW_FSUB
+  { 3, OperandInfo31 },  // Inst #100 = G_ATOMICRMW_FADD
+  { 3, OperandInfo31 },  // Inst #99 = G_ATOMICRMW_UMIN
+  { 3, OperandInfo31 },  // Inst #98 = G_ATOMICRMW_UMAX
+  { 3, OperandInfo31 },  // Inst #97 = G_ATOMICRMW_MIN
+  { 3, OperandInfo31 },  // Inst #96 = G_ATOMICRMW_MAX
+  { 3, OperandInfo31 },  // Inst #95 = G_ATOMICRMW_XOR
+  { 3, OperandInfo31 },  // Inst #94 = G_ATOMICRMW_OR
+  { 3, OperandInfo31 },  // Inst #93 = G_ATOMICRMW_NAND
+  { 3, OperandInfo31 },  // Inst #92 = G_ATOMICRMW_AND
+  { 3, OperandInfo31 },  // Inst #91 = G_ATOMICRMW_SUB
+  { 3, OperandInfo31 },  // Inst #90 = G_ATOMICRMW_ADD
+  { 3, OperandInfo31 },  // Inst #89 = G_ATOMICRMW_XCHG
+  { 4, OperandInfo30 },  // Inst #88 = G_ATOMIC_CMPXCHG
+  { 5, OperandInfo29 },  // Inst #87 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
+  { 5, OperandInfo28 },  // Inst #86 = G_INDEXED_STORE
+  { 2, OperandInfo23 },  // Inst #85 = G_STORE
+  { 5, OperandInfo27 },  // Inst #84 = G_INDEXED_ZEXTLOAD
+  { 5, OperandInfo27 },  // Inst #83 = G_INDEXED_SEXTLOAD
+  { 5, OperandInfo27 },  // Inst #82 = G_INDEXED_LOAD
+  { 2, OperandInfo23 },  // Inst #81 = G_ZEXTLOAD
+  { 2, OperandInfo23 },  // Inst #80 = G_SEXTLOAD
+  { 2, OperandInfo23 },  // Inst #79 = G_LOAD
+  { 1, OperandInfo20 },  // Inst #78 = G_READCYCLECOUNTER
+  { 2, OperandInfo25 },  // Inst #77 = G_INTRINSIC_ROUNDEVEN
+  { 2, OperandInfo23 },  // Inst #76 = G_INTRINSIC_LRINT
+  { 2, OperandInfo25 },  // Inst #75 = G_INTRINSIC_ROUND
+  { 2, OperandInfo25 },  // Inst #74 = G_INTRINSIC_TRUNC
+  { 3, OperandInfo26 },  // Inst #73 = G_INTRINSIC_FPTRUNC_ROUND
+  { 2, OperandInfo25 },  // Inst #72 = G_FREEZE
+  { 2, OperandInfo23 },  // Inst #71 = G_BITCAST
+  { 2, OperandInfo23 },  // Inst #70 = G_INTTOPTR
+  { 2, OperandInfo23 },  // Inst #69 = G_PTRTOINT
+  { 2, OperandInfo23 },  // Inst #68 = G_CONCAT_VECTORS
+  { 2, OperandInfo23 },  // Inst #67 = G_BUILD_VECTOR_TRUNC
+  { 2, OperandInfo23 },  // Inst #66 = G_BUILD_VECTOR
+  { 2, OperandInfo23 },  // Inst #65 = G_MERGE_VALUES
+  { 4, OperandInfo24 },  // Inst #64 = G_INSERT
+  { 2, OperandInfo23 },  // Inst #63 = G_UNMERGE_VALUES
+  { 3, OperandInfo22 },  // Inst #62 = G_EXTRACT
+  { 2, OperandInfo21 },  // Inst #61 = G_GLOBAL_VALUE
+  { 2, OperandInfo21 },  // Inst #60 = G_FRAME_INDEX
+  { 1, OperandInfo20 },  // Inst #59 = G_PHI
+  { 1, OperandInfo20 },  // Inst #58 = G_IMPLICIT_DEF
+  { 3, OperandInfo18 },  // Inst #57 = G_XOR
+  { 3, OperandInfo18 },  // Inst #56 = G_OR
+  { 3, OperandInfo18 },  // Inst #55 = G_AND
+  { 4, OperandInfo19 },  // Inst #54 = G_UDIVREM
+  { 4, OperandInfo19 },  // Inst #53 = G_SDIVREM
+  { 3, OperandInfo18 },  // Inst #52 = G_UREM
+  { 3, OperandInfo18 },  // Inst #51 = G_SREM
+  { 3, OperandInfo18 },  // Inst #50 = G_UDIV
+  { 3, OperandInfo18 },  // Inst #49 = G_SDIV
+  { 3, OperandInfo18 },  // Inst #48 = G_MUL
+  { 3, OperandInfo18 },  // Inst #47 = G_SUB
+  { 3, OperandInfo18 },  // Inst #46 = G_ADD
+  { 3, OperandInfo17 },  // Inst #45 = G_ASSERT_ALIGN
+  { 3, OperandInfo17 },  // Inst #44 = G_ASSERT_ZEXT
+  { 3, OperandInfo17 },  // Inst #43 = G_ASSERT_SEXT
+  { 0, 0 },  // Inst #42 = MEMBARRIER
+  { 0, 0 },  // Inst #41 = ICALL_BRANCH_FUNNEL
+  { 3, OperandInfo16 },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
+  { 2, OperandInfo15 },  // Inst #39 = PATCHABLE_EVENT_CALL
+  { 0, 0 },  // Inst #38 = PATCHABLE_TAIL_CALL
+  { 0, 0 },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
+  { 0, 0 },  // Inst #36 = PATCHABLE_RET
+  { 0, 0 },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
+  { 0, 0 },  // Inst #34 = PATCHABLE_OP
+  { 1, OperandInfo2 },  // Inst #33 = FAULTING_OP
+  { 2, OperandInfo14 },  // Inst #32 = LOCAL_ESCAPE
+  { 0, 0 },  // Inst #31 = STATEPOINT
+  { 3, OperandInfo13 },  // Inst #30 = PREALLOCATED_ARG
+  { 1, OperandInfo3 },  // Inst #29 = PREALLOCATED_SETUP
+  { 1, OperandInfo12 },  // Inst #28 = LOAD_STACK_GUARD
+  { 6, OperandInfo11 },  // Inst #27 = PATCHPOINT
+  { 0, 0 },  // Inst #26 = FENTRY_CALL
+  { 2, OperandInfo10 },  // Inst #25 = STACKMAP
+  { 2, OperandInfo9 },  // Inst #24 = ARITH_FENCE
+  { 4, OperandInfo8 },  // Inst #23 = PSEUDO_PROBE
+  { 1, OperandInfo3 },  // Inst #22 = LIFETIME_END
+  { 1, OperandInfo3 },  // Inst #21 = LIFETIME_START
+  { 0, 0 },  // Inst #20 = BUNDLE
+  { 2, OperandInfo7 },  // Inst #19 = COPY
+  { 2, OperandInfo7 },  // Inst #18 = REG_SEQUENCE
+  { 1, OperandInfo2 },  // Inst #17 = DBG_LABEL
+  { 0, 0 },  // Inst #16 = DBG_PHI
+  { 0, 0 },  // Inst #15 = DBG_INSTR_REF
+  { 0, 0 },  // Inst #14 = DBG_VALUE_LIST
+  { 0, 0 },  // Inst #13 = DBG_VALUE
+  { 3, OperandInfo4 },  // Inst #12 = COPY_TO_REGCLASS
+  { 4, OperandInfo6 },  // Inst #11 = SUBREG_TO_REG
+  { 1, OperandInfo2 },  // Inst #10 = IMPLICIT_DEF
+  { 4, OperandInfo5 },  // Inst #9 = INSERT_SUBREG
+  { 3, OperandInfo4 },  // Inst #8 = EXTRACT_SUBREG
+  { 0, 0 },  // Inst #7 = KILL
+  { 1, OperandInfo3 },  // Inst #6 = ANNOTATION_LABEL
+  { 1, OperandInfo3 },  // Inst #5 = GC_LABEL
+  { 1, OperandInfo3 },  // Inst #4 = EH_LABEL
+  { 1, OperandInfo3 },  // Inst #3 = CFI_INSTRUCTION
+  { 0, 0 },  // Inst #2 = INLINEASM_BR
+  { 0, 0 },  // Inst #1 = INLINEASM
+  { 1, OperandInfo2 },  // Inst #0 = PHI
+};
+
+#endif // GET_INSTRINFO_MC_DESC
+
+
diff --git a/arch/TriCore/TriCoreGenRegisterInfo.inc b/arch/TriCore/TriCoreGenRegisterInfo.inc
new file mode 100644
index 0000000000..7004b21707
--- /dev/null
+++ b/arch/TriCore/TriCoreGenRegisterInfo.inc
@@ -0,0 +1,295 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  TRICORE_NoRegister,
+  TRICORE_FCX = 1,
+  TRICORE_PC = 2,
+  TRICORE_PCXI = 3,
+  TRICORE_PSW = 4,
+  TRICORE_A0 = 5,
+  TRICORE_A1 = 6,
+  TRICORE_A2 = 7,
+  TRICORE_A3 = 8,
+  TRICORE_A4 = 9,
+  TRICORE_A5 = 10,
+  TRICORE_A6 = 11,
+  TRICORE_A7 = 12,
+  TRICORE_A8 = 13,
+  TRICORE_A9 = 14,
+  TRICORE_A10 = 15,
+  TRICORE_A11 = 16,
+  TRICORE_A12 = 17,
+  TRICORE_A13 = 18,
+  TRICORE_A14 = 19,
+  TRICORE_A15 = 20,
+  TRICORE_D0 = 21,
+  TRICORE_D1 = 22,
+  TRICORE_D2 = 23,
+  TRICORE_D3 = 24,
+  TRICORE_D4 = 25,
+  TRICORE_D5 = 26,
+  TRICORE_D6 = 27,
+  TRICORE_D7 = 28,
+  TRICORE_D8 = 29,
+  TRICORE_D9 = 30,
+  TRICORE_D10 = 31,
+  TRICORE_D11 = 32,
+  TRICORE_D12 = 33,
+  TRICORE_D13 = 34,
+  TRICORE_D14 = 35,
+  TRICORE_D15 = 36,
+  TRICORE_E0 = 37,
+  TRICORE_E2 = 38,
+  TRICORE_E4 = 39,
+  TRICORE_E6 = 40,
+  TRICORE_E8 = 41,
+  TRICORE_E10 = 42,
+  TRICORE_E12 = 43,
+  TRICORE_E14 = 44,
+  TRICORE_P0 = 45,
+  TRICORE_P2 = 46,
+  TRICORE_P4 = 47,
+  TRICORE_P6 = 48,
+  TRICORE_P8 = 49,
+  TRICORE_P10 = 50,
+  TRICORE_P12 = 51,
+  TRICORE_P14 = 52,
+  TRICORE_A0_A1 = 53,
+  TRICORE_A2_A3 = 54,
+  TRICORE_A4_A5 = 55,
+  TRICORE_A6_A7 = 56,
+  TRICORE_A8_A9 = 57,
+  TRICORE_A10_A11 = 58,
+  TRICORE_A12_A13 = 59,
+  TRICORE_A14_A15 = 60,
+  NUM_TARGET_REGS // 61
+};
+
+// Register classes
+
+enum {
+  TriCore_RARegClassID = 0,
+  TriCore_RDRegClassID = 1,
+  TriCore_PSRegsRegClassID = 2,
+  TriCore_PairAddrRegsRegClassID = 3,
+  TriCore_RERegClassID = 4,
+  TriCore_RPRegClassID = 5,
+
+};
+
+// Subregister indices
+
+enum {
+  TriCore_NoSubRegister,
+  TriCore_subreg_even,	// 1
+  TriCore_subreg_odd,	// 2
+  TriCore_NUM_TARGET_SUBREGS
+};
+#endif // GET_REGINFO_ENUM
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg TriCoreRegDiffLists[] = {
+  /* 0 */ 65434, 1, 0,
+  /* 3 */ 65450, 1, 0,
+  /* 6 */ 65482, 1, 0,
+  /* 9 */ 65488, 1, 0,
+  /* 12 */ 65489, 1, 0,
+  /* 15 */ 65490, 1, 0,
+  /* 18 */ 65491, 1, 0,
+  /* 21 */ 65492, 1, 0,
+  /* 24 */ 65493, 1, 0,
+  /* 27 */ 65494, 1, 0,
+  /* 30 */ 65495, 1, 0,
+  /* 33 */ 65496, 1, 0,
+  /* 36 */ 65497, 1, 0,
+  /* 39 */ 65498, 1, 0,
+  /* 42 */ 65499, 1, 0,
+  /* 45 */ 65500, 1, 0,
+  /* 48 */ 65501, 1, 0,
+  /* 51 */ 65502, 1, 0,
+  /* 54 */ 65503, 1, 0,
+  /* 57 */ 65520, 1, 0,
+  /* 60 */ 65521, 1, 0,
+  /* 63 */ 65522, 1, 0,
+  /* 66 */ 65523, 1, 0,
+  /* 69 */ 65524, 1, 0,
+  /* 72 */ 65525, 1, 0,
+  /* 75 */ 65526, 1, 0,
+  /* 78 */ 65527, 1, 0,
+  /* 81 */ 32, 8, 0,
+  /* 84 */ 33, 8, 0,
+  /* 87 */ 34, 8, 0,
+  /* 90 */ 35, 8, 0,
+  /* 93 */ 36, 8, 0,
+  /* 96 */ 37, 8, 0,
+  /* 99 */ 38, 8, 0,
+  /* 102 */ 39, 8, 0,
+  /* 105 */ 40, 8, 0,
+  /* 108 */ 9, 0,
+  /* 110 */ 10, 0,
+  /* 112 */ 11, 0,
+  /* 114 */ 12, 0,
+  /* 116 */ 13, 0,
+  /* 118 */ 14, 0,
+  /* 120 */ 15, 0,
+  /* 122 */ 16, 0,
+  /* 124 */ 65535, 0,
+};
+
+static const uint16_t TriCoreSubRegIdxLists[] = {
+  /* 0 */ 1, 2, 0,
+};
+
+static const MCRegisterDesc TriCoreRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 201, 2, 2, 2, 1985, 0 },
+  { 189, 2, 2, 2, 1985, 0 },
+  { 192, 2, 2, 2, 1985, 0 },
+  { 197, 2, 2, 2, 1985, 0 },
+  { 16, 2, 105, 2, 1985, 0 },
+  { 43, 2, 102, 2, 1985, 0 },
+  { 65, 2, 102, 2, 1985, 0 },
+  { 92, 2, 99, 2, 1985, 0 },
+  { 114, 2, 99, 2, 1985, 0 },
+  { 141, 2, 96, 2, 1985, 0 },
+  { 147, 2, 96, 2, 1985, 0 },
+  { 162, 2, 93, 2, 1985, 0 },
+  { 168, 2, 93, 2, 1985, 0 },
+  { 183, 2, 90, 2, 1985, 0 },
+  { 0, 2, 90, 2, 1985, 0 },
+  { 32, 2, 87, 2, 1985, 0 },
+  { 49, 2, 87, 2, 1985, 0 },
+  { 81, 2, 84, 2, 1985, 0 },
+  { 98, 2, 84, 2, 1985, 0 },
+  { 130, 2, 81, 2, 1985, 0 },
+  { 19, 2, 122, 2, 1985, 0 },
+  { 46, 2, 120, 2, 1985, 0 },
+  { 68, 2, 120, 2, 1985, 0 },
+  { 95, 2, 118, 2, 1985, 0 },
+  { 117, 2, 118, 2, 1985, 0 },
+  { 144, 2, 116, 2, 1985, 0 },
+  { 150, 2, 116, 2, 1985, 0 },
+  { 165, 2, 114, 2, 1985, 0 },
+  { 171, 2, 114, 2, 1985, 0 },
+  { 186, 2, 112, 2, 1985, 0 },
+  { 4, 2, 112, 2, 1985, 0 },
+  { 36, 2, 110, 2, 1985, 0 },
+  { 53, 2, 110, 2, 1985, 0 },
+  { 85, 2, 108, 2, 1985, 0 },
+  { 102, 2, 108, 2, 1985, 0 },
+  { 134, 2, 82, 2, 1985, 0 },
+  { 22, 57, 2, 0, 98, 2 },
+  { 71, 60, 2, 0, 98, 2 },
+  { 120, 63, 2, 0, 98, 2 },
+  { 153, 66, 2, 0, 98, 2 },
+  { 174, 69, 2, 0, 98, 2 },
+  { 8, 72, 2, 0, 98, 2 },
+  { 57, 75, 2, 0, 98, 2 },
+  { 106, 78, 2, 0, 98, 2 },
+  { 25, 33, 2, 0, 50, 2 },
+  { 74, 36, 2, 0, 50, 2 },
+  { 123, 39, 2, 0, 50, 2 },
+  { 156, 42, 2, 0, 50, 2 },
+  { 177, 45, 2, 0, 50, 2 },
+  { 12, 48, 2, 0, 50, 2 },
+  { 61, 51, 2, 0, 50, 2 },
+  { 110, 54, 2, 0, 50, 2 },
+  { 40, 9, 2, 0, 2, 2 },
+  { 89, 12, 2, 0, 2, 2 },
+  { 138, 15, 2, 0, 2, 2 },
+  { 159, 18, 2, 0, 2, 2 },
+  { 180, 21, 2, 0, 2, 2 },
+  { 28, 24, 2, 0, 2, 2 },
+  { 77, 27, 2, 0, 2, 2 },
+  { 126, 30, 2, 0, 2, 2 },
+};
+
+  // RA Register Class...
+  static const MCPhysReg RA[] = {
+    TRICORE_A0, TRICORE_A1, TRICORE_A2, TRICORE_A3, TRICORE_A4, TRICORE_A5, TRICORE_A6, TRICORE_A7, TRICORE_A8, TRICORE_A9, TRICORE_A10, TRICORE_A11, TRICORE_A12, TRICORE_A13, TRICORE_A14, TRICORE_A15, 
+  };
+
+  // RA Bit set.
+  static const uint8_t RABits[] = {
+    0xe0, 0xff, 0x1f, 
+  };
+
+  // RD Register Class...
+  static const MCPhysReg RD[] = {
+    TRICORE_D0, TRICORE_D1, TRICORE_D2, TRICORE_D3, TRICORE_D4, TRICORE_D5, TRICORE_D6, TRICORE_D7, TRICORE_D8, TRICORE_D9, TRICORE_D10, TRICORE_D11, TRICORE_D12, TRICORE_D13, TRICORE_D14, TRICORE_D15, 
+  };
+
+  // RD Bit set.
+  static const uint8_t RDBits[] = {
+    0x00, 0x00, 0xe0, 0xff, 0x1f, 
+  };
+
+  // PSRegs Register Class...
+  static const MCPhysReg PSRegs[] = {
+    TRICORE_PSW, TRICORE_PCXI, TRICORE_PC, TRICORE_FCX, 
+  };
+
+  // PSRegs Bit set.
+  static const uint8_t PSRegsBits[] = {
+    0x1e, 
+  };
+
+  // PairAddrRegs Register Class...
+  static const MCPhysReg PairAddrRegs[] = {
+    TRICORE_A0_A1, TRICORE_A2_A3, TRICORE_A4_A5, TRICORE_A6_A7, TRICORE_A8_A9, TRICORE_A10_A11, TRICORE_A12_A13, TRICORE_A14_A15, 
+  };
+
+  // PairAddrRegs Bit set.
+  static const uint8_t PairAddrRegsBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
+  };
+
+  // RE Register Class...
+  static const MCPhysReg RE[] = {
+    TRICORE_E0, TRICORE_E2, TRICORE_E4, TRICORE_E6, TRICORE_E8, TRICORE_E10, TRICORE_E12, TRICORE_E14, 
+  };
+
+  // RE Bit set.
+  static const uint8_t REBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
+  };
+
+  // RP Register Class...
+  static const MCPhysReg RP[] = {
+    TRICORE_P0, TRICORE_P2, TRICORE_P4, TRICORE_P6, TRICORE_P8, TRICORE_P10, TRICORE_P12, TRICORE_P14, 
+  };
+
+  // RP Bit set.
+  static const uint8_t RPBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
+  };
+
+static const MCRegisterClass TriCoreMCRegisterClasses[] = {
+  { RA, RABits, sizeof(RABits) },
+  { RD, RDBits, sizeof(RDBits) },
+  { PSRegs, PSRegsBits, sizeof(PSRegsBits) },
+  { PairAddrRegs, PairAddrRegsBits, sizeof(PairAddrRegsBits) },
+  { RE, REBits, sizeof(REBits) },
+  { RP, RPBits, sizeof(RPBits) },
+};
+
+#endif // GET_REGINFO_MC_DESC
+
+
+
diff --git a/arch/TriCore/TriCoreGenSubtargetInfo.inc b/arch/TriCore/TriCoreGenSubtargetInfo.inc
new file mode 100644
index 0000000000..e9700cb294
--- /dev/null
+++ b/arch/TriCore/TriCoreGenSubtargetInfo.inc
@@ -0,0 +1,40 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  TRICORE_HasV110Ops = 0,
+  TRICORE_HasV120Ops = 1,
+  TRICORE_HasV130Ops = 2,
+  TRICORE_HasV131Ops = 3,
+  TRICORE_HasV160Ops = 4,
+  TRICORE_HasV161Ops = 5,
+  TRICORE_HasV162Ops = 6,
+  TRICORE_TRICORE_PCP = 7,
+  TRICORE_TRICORE_PCP2 = 8,
+  TRICORE_TRICORE_RIDER_A = 9,
+  TRICORE_TRICORE_V1_1 = 10,
+  TRICORE_TRICORE_V1_2 = 11,
+  TRICORE_TRICORE_V1_3 = 12,
+  TRICORE_TRICORE_V1_3_1 = 13,
+  TRICORE_TRICORE_V1_6 = 14,
+  TRICORE_TRICORE_V1_6_1 = 15,
+  TRICORE_TRICORE_V1_6_2 = 16,
+  TRICORE_NumSubtargetFeatures = 17
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+
diff --git a/arch/TriCore/TriCoreInstPrinter.c b/arch/TriCore/TriCoreInstPrinter.c
new file mode 100644
index 0000000000..254b7d073e
--- /dev/null
+++ b/arch/TriCore/TriCoreInstPrinter.c
@@ -0,0 +1,540 @@
+//===- TriCoreInstPrinter.cpp - Convert TriCore MCInst to assembly syntax -===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an TriCore MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_TRICORE
+
+#include <platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "../../SStream.h"
+#include "../../utils.h"
+#include "TriCoreInstPrinter.h"
+#include "TriCoreMapping.h"
+
+static const char *getRegisterName(unsigned RegNo);
+
+static void printInstruction(MCInst *, uint64_t, SStream *);
+
+static void printOperand(MCInst *MI, int OpNum, SStream *O);
+
+void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
+{
+	/*
+	   if (((cs_struct *)ud)->detail != CS_OPT_ON)
+	   return;
+	 */
+}
+
+#define GET_INSTRINFO_ENUM
+
+#include "TriCoreGenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+
+#include "TriCoreGenRegisterInfo.inc"
+
+static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp);
+
+static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp);
+
+static inline void fill_tricore_register(MCInst *MI, uint32_t reg)
+{
+	if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail))
+		return;
+	cs_tricore *tricore = &MI->flat_insn->detail->tricore;
+	tricore->operands[tricore->op_count].type = TRICORE_OP_REG;
+	tricore->operands[tricore->op_count].reg = reg;
+	tricore->op_count++;
+}
+
+static inline void fill_tricore_imm(MCInst *MI, int32_t imm)
+{
+	if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail))
+		return;
+	cs_tricore *tricore = &MI->flat_insn->detail->tricore;
+	if (tricore->op_count >= 1 &&
+	    tricore->operands[tricore->op_count - 1].type == TRICORE_OP_REG &&
+	    fixup_op_mem(MI, tricore->operands[tricore->op_count - 1].reg,
+			 imm)) {
+		return;
+	}
+	tricore->operands[tricore->op_count].type = TRICORE_OP_IMM;
+	tricore->operands[tricore->op_count].imm = imm;
+	tricore->op_count++;
+}
+
+static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp)
+{
+	switch (TriCore_map_insn_id(pInst->csh, pInst->Opcode)) {
+	case TRICORE_INS_LDMST:
+	case TRICORE_INS_LDLCX:
+	case TRICORE_INS_LD_A:
+	case TRICORE_INS_LD_B:
+	case TRICORE_INS_LD_BU:
+	case TRICORE_INS_LD_H:
+	case TRICORE_INS_LD_HU:
+	case TRICORE_INS_LD_D:
+	case TRICORE_INS_LD_DA:
+	case TRICORE_INS_LD_W:
+	case TRICORE_INS_LD_Q:
+	case TRICORE_INS_STLCX:
+	case TRICORE_INS_STUCX:
+	case TRICORE_INS_ST_A:
+	case TRICORE_INS_ST_B:
+	case TRICORE_INS_ST_H:
+	case TRICORE_INS_ST_D:
+	case TRICORE_INS_ST_DA:
+	case TRICORE_INS_ST_W:
+	case TRICORE_INS_ST_Q:
+	case TRICORE_INS_CACHEI_I:
+	case TRICORE_INS_CACHEI_W:
+	case TRICORE_INS_CACHEI_WI:
+	case TRICORE_INS_CACHEA_I:
+	case TRICORE_INS_CACHEA_W:
+	case TRICORE_INS_CACHEA_WI:
+	case TRICORE_INS_CMPSWAP_W:
+	case TRICORE_INS_SWAP_A:
+	case TRICORE_INS_SWAP_W:
+	case TRICORE_INS_SWAPMSK_W:
+	case TRICORE_INS_LEA:
+	case TRICORE_INS_LHA: {
+		switch (MCInst_getOpcode(pInst)) {
+		case TRICORE_LDMST_abs:
+		case TRICORE_LDLCX_abs:
+		case TRICORE_LD_A_abs:
+		case TRICORE_LD_B_abs:
+		case TRICORE_LD_BU_abs:
+		case TRICORE_LD_H_abs:
+		case TRICORE_LD_HU_abs:
+		case TRICORE_LD_D_abs:
+		case TRICORE_LD_DA_abs:
+		case TRICORE_LD_W_abs:
+		case TRICORE_LD_Q_abs:
+		case TRICORE_STLCX_abs:
+		case TRICORE_STUCX_abs:
+		case TRICORE_ST_A_abs:
+		case TRICORE_ST_B_abs:
+		case TRICORE_ST_H_abs:
+		case TRICORE_ST_D_abs:
+		case TRICORE_ST_DA_abs:
+		case TRICORE_ST_W_abs:
+		case TRICORE_ST_Q_abs:
+		case TRICORE_SWAP_A_abs:
+		case TRICORE_SWAP_W_abs:
+		case TRICORE_LEA_abs:
+		case TRICORE_LHA_abs: {
+			return false;
+		}
+		}
+		cs_tricore *tc = &pInst->flat_insn->detail->tricore;
+		fill_mem(tc, reg, disp);
+		return true;
+	}
+	}
+	return false;
+}
+
+static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp)
+{
+	cs_tricore_op *op = &tc->operands[tc->op_count - 1];
+	op->type = TRICORE_OP_MEM;
+	op->mem.base = base;
+	op->mem.disp = disp;
+}
+
+static void printOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *Op;
+	if (OpNum >= MI->size)
+		return;
+
+	Op = MCInst_getOperand(MI, OpNum);
+
+	if (MCOperand_isReg(Op)) {
+		unsigned reg = MCOperand_getReg(Op);
+		SStream_concat(O, "%%%s", getRegisterName(reg));
+		fill_tricore_register(MI, reg);
+	} else if (MCOperand_isImm(Op)) {
+		int64_t Imm = MCOperand_getImm(Op);
+
+		if (Imm >= 0) {
+			if (Imm > HEX_THRESHOLD)
+				SStream_concat(O, "0x%" PRIx64, Imm);
+			else
+				SStream_concat(O, "%" PRIu64, Imm);
+		} else {
+			if (Imm < -HEX_THRESHOLD)
+				SStream_concat(O, "-0x%" PRIx64, -Imm);
+			else
+				SStream_concat(O, "-%" PRIu64, -Imm);
+		}
+
+		fill_tricore_imm(MI, (int32_t)Imm);
+	}
+}
+
+static inline unsigned int get_msb(unsigned int value)
+{
+	unsigned int msb = 0;
+	while (value > 0) {
+		value >>= 1; // Shift bits to the right
+		msb++; // Increment the position of the MSB
+	}
+	return msb;
+}
+
+static inline int32_t sign_ext_n(int32_t imm, unsigned n)
+{
+	n = get_msb(imm) > n ? get_msb(imm) : n;
+	int32_t mask = 1 << (n - 1);
+	int32_t sign_extended = (imm ^ mask) - mask;
+	return sign_extended;
+}
+
+static inline void SS_print_hex(SStream *O, int32_t imm)
+{
+	if (imm > HEX_THRESHOLD)
+		SStream_concat(O, "0x%x", imm);
+	else
+		SStream_concat(O, "%u", imm);
+}
+
+static inline void SS_print_sign_hex(SStream *O, int32_t imm)
+{
+	if (imm >= 0) {
+		SS_print_hex(O, imm);
+	} else {
+		if (imm < -HEX_THRESHOLD)
+			SStream_concat(O, "-0x%x", -imm);
+		else
+			SStream_concat(O, "-%u", -imm);
+	}
+}
+
+static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int32_t imm = (int32_t)MCOperand_getImm(MO);
+		imm = sign_ext_n(imm, n);
+		SS_print_sign_hex(O, imm);
+		fill_tricore_imm(MI, imm);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static void off4_fixup(MCInst *MI, uint64_t *off4)
+{
+	switch (MCInst_getOpcode(MI)) {
+	case TRICORE_LD_A_slro:
+	case TRICORE_LD_A_sro:
+	case TRICORE_LD_W_slro:
+	case TRICORE_LD_W_sro:
+	case TRICORE_ST_A_sro:
+	case TRICORE_ST_A_ssro:
+	case TRICORE_ST_W_sro:
+	case TRICORE_ST_W_ssro: {
+		*off4 *= 4;
+		break;
+	}
+	case TRICORE_LD_H_sro:
+	case TRICORE_LD_H_slro:
+	case TRICORE_ST_H_sro:
+	case TRICORE_ST_H_ssro: {
+		*off4 *= 2;
+		break;
+	}
+	}
+}
+
+static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		uint64_t imm = MCOperand_getImm(MO);
+		for (unsigned i = n + 1; i < 32; ++i) {
+			imm &= ~(1 << i);
+		}
+		if (n == 4) {
+			off4_fixup(MI, &imm);
+		}
+
+		if (imm >= 0) {
+			if (imm > HEX_THRESHOLD)
+				SStream_concat(O, "0x%x", imm);
+			else
+				SStream_concat(O, "%u", imm);
+		} else {
+			if (imm < -HEX_THRESHOLD)
+				SStream_concat(O, "-0x%x", -imm);
+			else
+				SStream_concat(O, "-%u", -imm);
+		}
+		fill_tricore_imm(MI, imm);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static void printOff18Imm(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		uint32_t imm = (uint32_t)MCOperand_getImm(MO);
+		imm = ((imm & 0x3C000) << 14) | (imm & 0x3fff);
+		SStream_concat(O, "0x%x", imm);
+		fill_tricore_imm(MI, (int32_t)imm);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void fixup_tricore_disp(MCInst *MI, int OpNum, int32_t disp)
+{
+	if (MI->csh->detail != CS_OPT_ON)
+		return;
+
+	cs_tricore *tricore = &MI->flat_insn->detail->tricore;
+	if (OpNum <= 0) {
+		fill_tricore_imm(MI, disp);
+		return;
+	}
+
+	if (tricore->operands[tricore->op_count - 1].type != TRICORE_OP_REG)
+		return;
+	fill_mem(tricore, tricore->operands[tricore->op_count - 1].reg, disp);
+}
+
+static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int32_t disp = (int32_t)MCOperand_getImm(MO);
+		switch (MCInst_getOpcode(MI)) {
+		case TRICORE_CALL_b:
+		case TRICORE_FCALL_b: {
+			disp = (int32_t)MI->address + sign_ext_n(disp * 2, 24);
+			break;
+		}
+		case TRICORE_CALLA_b:
+		case TRICORE_FCALLA_b:
+		case TRICORE_JA_b:
+		case TRICORE_JLA_b:
+			// = {disp24[23:20], 7’b0000000, disp24[19:0], 1’b0};
+			disp = ((disp & 0xf00000) << 28) |
+			       ((disp & 0xfffff) << 1);
+			break;
+		case TRICORE_J_b:
+		case TRICORE_JL_b:
+			disp = (int32_t)MI->address + sign_ext_n(disp, 24) * 2;
+			break;
+		}
+
+		SS_print_sign_hex(O, disp);
+		fixup_tricore_disp(MI, OpNum, disp);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int32_t disp = (int32_t)MCOperand_getImm(MO);
+		switch (MCInst_getOpcode(MI)) {
+		case TRICORE_JEQ_brc:
+		case TRICORE_JEQ_brr:
+		case TRICORE_JEQ_A_brr:
+		case TRICORE_JGE_brc:
+		case TRICORE_JGE_brr:
+		case TRICORE_JGE_U_brc:
+		case TRICORE_JGE_U_brr:
+		case TRICORE_JLT_brc:
+		case TRICORE_JLT_brr:
+		case TRICORE_JLT_U_brc:
+		case TRICORE_JLT_U_brr:
+		case TRICORE_JNE_brc:
+		case TRICORE_JNE_brr:
+		case TRICORE_JNE_A_brr:
+		case TRICORE_JNED_brc:
+		case TRICORE_JNED_brr:
+		case TRICORE_JNEI_brc:
+		case TRICORE_JNEI_brr:
+		case TRICORE_JNZ_A_brr:
+		case TRICORE_JNZ_T_brn:
+		case TRICORE_JZ_A_brr:
+		case TRICORE_JZ_T_brn:
+			disp = (int32_t)MI->address + sign_ext_n(disp, 15) * 2;
+			break;
+		case TRICORE_LOOP_brr:
+		case TRICORE_LOOPU_brr:
+			disp = (int32_t)MI->address + sign_ext_n(disp * 2, 15);
+			break;
+		default:
+			// handle other cases, if any
+			break;
+		}
+
+		SS_print_sign_hex(O, disp);
+		fixup_tricore_disp(MI, OpNum, disp);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int32_t disp = (int32_t)MCOperand_getImm(MO);
+		switch (MCInst_getOpcode(MI)) {
+		case TRICORE_CALL_sb:
+			disp = (int32_t)MI->address + sign_ext_n(2 * disp, 8);
+			break;
+		case TRICORE_J_sb:
+		case TRICORE_JNZ_sb:
+		case TRICORE_JZ_sb:
+			disp = (int32_t)MI->address + sign_ext_n(disp, 8) * 2;
+			break;
+		default:
+			// handle other cases, if any
+			break;
+		}
+
+		SS_print_sign_hex(O, disp);
+		fixup_tricore_disp(MI, OpNum, disp);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int32_t disp = (int32_t)MCOperand_getImm(MO);
+		switch (MCInst_getOpcode(MI)) {
+		case TRICORE_JEQ_sbc1:
+		case TRICORE_JEQ_sbr1:
+		case TRICORE_JGEZ_sbr:
+		case TRICORE_JGTZ_sbr:
+		case TRICORE_JLEZ_sbr:
+		case TRICORE_JLTZ_sbr:
+		case TRICORE_JNE_sbc1:
+		case TRICORE_JNE_sbr1:
+		case TRICORE_JNZ_sbr:
+		case TRICORE_JNZ_A_sbr:
+		case TRICORE_JNZ_T_sbrn:
+		case TRICORE_JZ_sbr:
+		case TRICORE_JZ_A_sbr:
+		case TRICORE_JZ_T_sbrn:
+			disp = (int32_t)MI->address + disp * 2;
+			break;
+		case TRICORE_JEQ_sbc2:
+		case TRICORE_JEQ_sbr2:
+		case TRICORE_JNE_sbc2:
+		case TRICORE_JNE_sbr2:
+			disp = (int32_t)MI->address + (disp + 16) * 2;
+			break;
+		case TRICORE_LOOP_sbr:
+			// {27b’111111111111111111111111111, disp4, 0};
+			disp = (int32_t)MI->address +
+			       ((0b111111111111111111111111111 << 5) |
+				(disp << 1));
+			break;
+		default:
+			// handle other cases, if any
+			break;
+		}
+
+		SS_print_sign_hex(O, disp);
+		fixup_tricore_disp(MI, OpNum, disp);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+#define printSExtImm_(n)                                                \
+	static void printSExtImm_##n(MCInst *MI, int OpNum, SStream *O) \
+	{                                                               \
+		print_sign_ext(MI, OpNum, O, n);                        \
+	}
+
+#define printZExtImm_(n)                                                \
+	static void printZExtImm_##n(MCInst *MI, int OpNum, SStream *O) \
+	{                                                               \
+		print_zero_ext(MI, OpNum, O, n);                        \
+	}
+
+// clang-format off
+
+printSExtImm_(16)
+printSExtImm_(10)
+printSExtImm_(9)
+printSExtImm_(4)
+
+printZExtImm_(16)
+printZExtImm_(9)
+printZExtImm_(8)
+printZExtImm_(4)
+printZExtImm_(2);
+
+// clang-format on
+
+static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		uint32_t imm = MCOperand_getImm(MO);
+		// {27b’111111111111111111111111111, disp4, 0};
+		imm = 0b11111111111111111111111111100000 | (imm << 1);
+
+		SS_print_sign_hex(O, imm);
+		fill_tricore_imm(MI, imm);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+/// Returned by getMnemonic() of the AsmPrinters.
+typedef struct {
+	const char *first; // Menmonic
+	uint64_t second; // Bits
+} MnemonicBitsInfo;
+
+void set_mem_access(MCInst *MI, unsigned int access)
+{
+	// TODO: TriCore
+}
+
+#define PRINT_ALIAS_INSTR
+
+#include "TriCoreGenAsmWriter.inc"
+
+const char *TriCore_getRegisterName(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return getRegisterName(id);
+#else
+	return NULL;
+#endif
+}
+
+void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	printInstruction(MI, MI->address, O);
+}
+
+#endif
diff --git a/arch/TriCore/TriCoreInstPrinter.h b/arch/TriCore/TriCoreInstPrinter.h
new file mode 100644
index 0000000000..2313baa1b0
--- /dev/null
+++ b/arch/TriCore/TriCoreInstPrinter.h
@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_TRICOREINSTPRINTER_H
+#define CS_TRICOREINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "./TriCoreMapping.h"
+
+const char *TriCore_getRegisterName(csh handle, unsigned int id);
+
+void TriCore_printInst(MCInst *MI, SStream *O, void *Info);
+
+void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci);
+
+#endif
diff --git a/arch/TriCore/TriCoreInstrFormats.td b/arch/TriCore/TriCoreInstrFormats.td
new file mode 100644
index 0000000000..0c6f187511
--- /dev/null
+++ b/arch/TriCore/TriCoreInstrFormats.td
@@ -0,0 +1,773 @@
+//==-- TriCoreInstrFormats.td - TriCore Instruction Formats -*- tablegen -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Describe TriCore instructions format
+//
+//  CPU INSTRUCTION FORMATS
+//
+//  op1     - primary operation code
+//  op2     - secondary operation code
+//  s1      - source register 1
+//  s2      - source register 2
+//  s3      - source register 3
+//  d       - destination register
+//  b       - bit value
+//  n       -
+//            - multiplication result shift value (0b00 or 0b01)
+//            - address shift value in add scale
+//            - default to zero in all other operations using the RR format
+//            - coprocessor number for coprocessor instructions
+//  const[b=(4|9|16)]  - b bits immediate value
+//  disp[b=(4|8|15|24)]  - b bits displacement value
+//  off[b=(4|10|16)] - b bits offset value
+//
+//===----------------------------------------------------------------------===//
+
+class InstTriCore<dag outs, dag ins, string asmstr, list<dag> pattern>
+    : Instruction {
+
+  let Namespace = "TriCore";
+  /// outs and ins are inherited from the instruction class.
+  dag OutOperandList = outs;
+  dag InOperandList  = ins;
+  let AsmString   = asmstr;
+  let Pattern = pattern;
+}
+
+// TriCore pseudo instructions format
+class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
+   : InstTriCore<outs, ins, asmstr, pattern> {
+  let isPseudo = 1;
+}
+
+//===----------------------------------------------------------------------===//
+// Generic 16-bit Instruction Format
+//===----------------------------------------------------------------------===//
+class T16<dag outs, dag ins, string asmstr, list<dag> pattern>
+    : InstTriCore<outs, ins, asmstr, pattern> {
+  field bits<16> Inst;
+  let Size = 2;
+  field bits<16> SoftFail = 0;
+}
+
+//===----------------------------------------------------------------------===//
+// Generic 32-bit Instruction Format
+//===----------------------------------------------------------------------===//
+class T32<dag outs, dag ins, string asmstr, list<dag> pattern>
+    : InstTriCore<outs, ins, asmstr, pattern> {
+  field bits<32> Inst;
+  let Size = 4;
+  field bits<32> SoftFail = 0;
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SB Instruction Format: <disp8|op1>
+//===----------------------------------------------------------------------===//
+class SB<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+        : T16<outs, ins, asmstr, pattern> {
+
+  bits<8> disp8;
+  let Inst{15-8} = disp8;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSBInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SBC Instruction Format: <const4|disp4|op1>
+//===----------------------------------------------------------------------===//
+class SBC<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+        : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> const4;
+  bits<4> disp4;
+
+  let Inst{15-12} = const4;
+  let Inst{11-8} = disp4;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSBCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SBR Instruction Format: <s2|disp4|op1>
+//===----------------------------------------------------------------------===//
+class SBR<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+        : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> disp4;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = disp4;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSBRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SBRN Instruction Format: <n|disp4|op1>
+//===----------------------------------------------------------------------===//
+class SBRN<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+        : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> n;
+  bits<4> disp4;
+
+  let Inst{15-12} = n;
+  let Inst{11-8} = disp4;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSBRNInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SC Instruction Format: <const8|op1>
+//===----------------------------------------------------------------------===//
+class SC<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<8> const8;
+
+  let Inst{15-8} = const8;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SLR Instruction Format: <s2|d|op1>
+//===----------------------------------------------------------------------===//
+class SLR<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> d;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSLRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SLRO Instruction Format: <off4|d|op1>
+//===----------------------------------------------------------------------===//
+class SLRO<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> off4;
+  bits<4> d;
+
+  let Inst{15-12} = off4;
+  let Inst{11-8} = d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSLROInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SR Instruction Format: <op2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SR<bits<8> op1, bits<4> op2, dag outs, dag ins, string asmstr,
+      list<dag> pattern> : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s1_d;
+
+  let Inst{15-12} = op2;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SRC Instruction Format: <const4|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SRC<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> const4;
+  bits<4> s1_d;
+
+  let Inst{15-12} = const4;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSRCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SRO Instruction Format: <s2|off4|op1>
+//===----------------------------------------------------------------------===//
+class SRO<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> off4;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = off4;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSROInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SRR Instruction Format: <s2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SRR<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> s1_d;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SRRS Instruction Format: <s2|s1/d|n|op1>
+//===----------------------------------------------------------------------===//
+class SRRS<bits<6> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> s1_d;
+  bits<2> n;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1_d;
+  let Inst{7-6} = n;
+  let Inst{5-0} = op1;
+  let DecoderMethod = "DecodeSRRSInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SSR Instruction Format: <s2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SSR<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSSRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SSRO Instruction Format: <s2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SSRO<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> off4;
+  bits<4> s1;
+
+  let Inst{15-12} = off4;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSSROInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit ABS Instruction Format:
+// <off18[9:6]|op2|off18[13:10]|off18[5:0]|off18[17:14]|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class ABS<bits<8> op1, bits<2> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<18> off18;
+  bits<4> s1_d;
+
+  let Inst{31-28} = off18{9-6};
+  let Inst{27-26} = op2;
+  let Inst{25-22} = off18{13-10};
+  let Inst{21-16} = off18{5-0};
+  let Inst{15-12} = off18{17-14};
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeABSInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit ABSB Instruction Format:
+// <off18[9:6]|op2|off18[13:10]|off18[5:0]|off18[17:14]|b|bpos3|op1>
+//===----------------------------------------------------------------------===//
+class ABSB<bits<8> op1, bits<2> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<18> off18;
+  bits<1> b;
+  bits<3> bpos3;
+
+  let Inst{31-28} = off18{9-6};
+  let Inst{27-26} = op2;
+  let Inst{25-22} = off18{13-10};
+  let Inst{21-16} = off18{5-0};
+  let Inst{15-12} = off18{17-14};
+  let Inst{11} = b;
+  let Inst{10-8} = bpos3;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeABSBInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit B Instruction Format:
+// <disp24[15:0]|disp24[23:16]|op1>
+//===----------------------------------------------------------------------===//
+class B<bits<8> op1, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<24> disp24;
+
+  let Inst{31-16} = disp24{15-0};
+  let Inst{15-8} = disp24{23-16};
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BIT Instruction Format: <d|pos2|op2|pos1|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class BIT<bits<8> op1, bits<2> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<5> pos2;
+  bits<5> pos1;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-23} = pos2;
+  let Inst{22-21} = op2;
+  let Inst{20-16} = pos1;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBITInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BO Instruction Format: <off10[9:6]|op2|off10[5:0]|s2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class BO<bits<8> op1, bits<6> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<10> off10;
+  bits<4> s2;
+  bits<4> s1_d;
+
+  let Inst{31-28} = off10{9-6};
+  let Inst{27-22} = op2;
+  let Inst{21-16} = off10{5-0};
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBOInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BOL Instruction Format:
+// <off16[9:6]|off16[15:10]|off16[5:0]|s2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class BOL<bits<8> op1, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<16> off16;
+  bits<4> s2;
+  bits<4> s1_d;
+
+  let Inst{31-28} = off16{9-6};
+  let Inst{27-22} = off16{15-10};
+  let Inst{21-16} = off16{5-0};
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBOLInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BRC Instruction Format: <op2|disp15|const4|s1|op1>
+//===----------------------------------------------------------------------===//
+class BRC<bits<8> op1, bits<1> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<15> disp15;
+  bits<4> const4;
+  bits<4> s1;
+
+  let Inst{31} = op2;
+  let Inst{30-16} = disp15;
+  let Inst{15-12} = const4;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBRCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BRN Instruction Format: <op2|disp15|n[3:0]|s1|n[4]|op1>
+//===----------------------------------------------------------------------===//
+class BRN<bits<7> op1, bits<1> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<15> disp15;
+  bits<5> n;
+  bits<4> s1;
+
+  let Inst{31} = op2;
+  let Inst{30-16} = disp15;
+  let Inst{15-12} = n{3-0};
+  let Inst{11-8} = s1;
+  let Inst{7} = n{4};
+  let Inst{6-0} = op1;
+  let DecoderMethod = "DecodeBRNInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BRR Instruction Format: <op2|disp15|const4|s1|op1>
+//===----------------------------------------------------------------------===//
+class BRR<bits<8> op1, bits<1> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<15> disp15;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31} = op2;
+  let Inst{30-16} = disp15;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RC Instruction Format: <d|op2|const9|s1|op1>
+//===----------------------------------------------------------------------===//
+class RC<bits<8> op1, bits<7> op2, dag outs, dag ins, string asmstr,
+                  list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<9> const9;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-21} = op2;
+  let Inst{20-12} = const9;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RCPW Instruction Format: <d|pos|op2|width|const4|s1|op1>
+//===----------------------------------------------------------------------===//
+class RCPW<bits<8> op1, bits<2> op2 , dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<5> pos;
+  bits<5> width;
+  bits<4> const4;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-23} = pos;
+  let Inst{22-21} = op2;
+  let Inst{20-16} = width;
+  let Inst{15-12} = const4;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRCPWInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RCR Instruction Format: <d|s3|op2|const9|s1|op1>
+//===----------------------------------------------------------------------===//
+class RCR<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<9> const9;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-21} = op2;
+  let Inst{20-12} = const9;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRCRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RCRR Instruction Format: <d|s3|op2|-|const4|s1|op1>
+//===----------------------------------------------------------------------===//
+class RCRR<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<4> const4;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-21} = op2;
+  let Inst{20-16} = 0;
+  let Inst{15-12} = const4;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRCRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RCRW Instruction Format: <d|s3|op2|width|const4|s1|op1>
+//===----------------------------------------------------------------------===//
+class RCRW<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<5> width;
+  bits<4> const4;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-21} = op2;
+  let Inst{20-16} = width;
+  let Inst{15-12} = const4;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRCRWInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RLC Instruction Format: <d|const16|s1|op1>
+//===----------------------------------------------------------------------===//
+class RLC<bits<8> op1, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<16> const16;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-12} = const16;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRLCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RR Instruction Format: <d|op2|-|n|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RR<bits<8> op1, bits<8> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<2> n;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-20} = op2;
+  let Inst{19-18} = 0;
+  let Inst{17-16} = n;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RR1 Instruction Format: <d|op2|n|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RR1<bits<8> op1, bits<10> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<2> n;
+  bits<4> s2;
+  bits<4> s1;
+
+
+  let Inst{31-28} = d;
+  let Inst{27-18} = op2;
+  let Inst{17-16} = n;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRR1Instruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RR2 Instruction Format: <d|op2|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RR2<bits<8> op1, bits<12> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-16} = op2;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRR2Instruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRPW Instruction Format: <d|pos|op2|width|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRPW<bits<8> op1, bits<2> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<5> pos;
+  bits<5> width;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-23} = pos;
+  let Inst{22-21} = op2;
+  let Inst{20-16} = width;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRPWInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRR Instruction Format: <d|s3|op2|-|n|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRR<bits<8> op1, bits<4> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<2> n;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-20} = op2;
+  let Inst{19-18} = 0;
+  let Inst{17-16} = n;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRR1 Instruction Format: <d|s3|op2|n|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRR1<bits<8> op1, bits<6> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<2> n;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-18} = op2;
+  let Inst{17-16} = n;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRR1Instruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRR2 Instruction Format: <d|s3|op2|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRR2<bits<8> op1, bits<8> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> s1;
+  bits<4> s2;
+  bits<4> s3;
+  bits<4> d;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-16} = op2;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRR2Instruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRRR Instruction Format: <d|s3|op2|-|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRRR<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-21} = op2;
+  let Inst{20-16} = 0;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRRW Instruction Format: <d|s3|op2|width|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRRW<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<5> width;
+  bits<4> s2;
+  bits<4> s1;  
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-21} = op2;
+  let Inst{20-16} = width;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRRWInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit SYS Instruction Format: <-|op2|-|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SYS<bits<8> op1, bits<6> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> s1_d;
+
+  let Inst{31-28} = 0;
+  let Inst{27-22} = op2;
+  let Inst{21-12} = 0;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSYSInstruction";
+}
diff --git a/arch/TriCore/TriCoreInstrInfo.td b/arch/TriCore/TriCoreInstrInfo.td
new file mode 100644
index 0000000000..bf32b7ac44
--- /dev/null
+++ b/arch/TriCore/TriCoreInstrInfo.td
@@ -0,0 +1,1873 @@
+//===-- TriCoreInstrInfo.td - Target Description for TriCore ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the TriCore instructions in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction format superclass.
+//===----------------------------------------------------------------------===//
+
+include "TriCoreInstrFormats.td"
+
+//===----------------------------------------------------------------------===//
+// TriCore specific DAG Nodes.
+//
+
+// Call
+def SDT_TriCoreCmp      : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
+                           SDTCisSameAs<1, 2>,
+                           SDTCisVT<3, i32>]>;
+def SDT_TriCoreImask    : SDTypeProfile<1, 3, [SDTCisVT<0, i64>,
+                           SDTCisVT<1, i32>,
+                           SDTCisVT<2, i32>,
+                           SDTCisVT<3, i32>]>;
+
+def SDT_TriCoreExtract  : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
+                           SDTCisVT<1, i32>,
+                           SDTCisVT<2, i32>,
+                           SDTCisVT<3, i32>]>;
+
+def SDT_TriCoreLCmp     : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
+                           SDTCisSameAs<1, 2>,
+                           SDTCisSameAs<2, 3>,
+                           SDTCisVT<4, i32>]>;
+def SDT_TriCoreBrCC     : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
+                           SDTCisVT<1, i32>,
+                           SDTCisVT<2, i32>]>;
+def SDT_TriCoreCall     : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
+def SDT_TriCoreSelectCC : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
+                           SDTCisSameAs<1, 2>,
+                           SDTCisVT<3, i32>,
+                           SDTCisVT<4, i32>]>;
+def SDT_TriCoreWrapper  : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
+                           SDTCisPtrTy<0>]>;
+
+def SDT_TriCoreShift    : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
+                           SDTCisVT<1, i32>,
+                           SDTCisVT<2, i32>]>;
+
+def SDT_TriCoreMovei32  : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
+                           SDTCisVT<0, i32>]>;
+
+def SDT_TriCoreMovei64  : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
+                           SDTCisVT<0, i64>]>;
+
+def TriCoreAbs     : SDNode<"TriCoreISD::ABS", SDTIntUnaryOp>;
+def TriCoreAbsDif  : SDNode<"TriCoreISD::ABSDIF", SDTIntBinOp>;
+def TriCoreBrCC    : SDNode<"TriCoreISD::BR_CC",
+                      SDT_TriCoreBrCC, [SDNPHasChain, SDNPInGlue]>;
+def TriCoreCall    : SDNode<"TriCoreISD::CALL", SDT_TriCoreCall,
+                      [ SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic ]>;
+def TriCoreCmp     : SDNode<"TriCoreISD::CMP",
+                      SDT_TriCoreCmp, [SDNPOutGlue]>;
+def TriCoreLogicCmp: SDNode<"TriCoreISD::LOGICCMP",
+                      SDT_TriCoreLCmp, [SDNPInGlue, SDNPOutGlue]>;
+def TriCoreWrapper : SDNode<"TriCoreISD::Wrapper", SDT_TriCoreWrapper>;
+def TriCoreImask   : SDNode<"TriCoreISD::IMASK", SDT_TriCoreImask>;
+def TriCoreSh      : SDNode<"TriCoreISD::SH",  SDT_TriCoreShift>;
+def TriCoreSha     : SDNode<"TriCoreISD::SHA", SDT_TriCoreShift>;
+def TriCoreExtr    : SDNode<"TriCoreISD::EXTR", SDT_TriCoreExtract>;
+def TriCoreSelectCC: SDNode<"TriCoreISD::SELECT_CC", SDT_TriCoreSelectCC, []>;
+
+def load_sym : SDNode<"TriCoreISD::LOAD_SYM", SDTIntUnaryOp>;
+
+def movei32 : SDNode<"TriCoreISD::MOVEi32", SDT_TriCoreMovei32>;
+
+
+def jmptarget : Operand<OtherVT> {
+  let PrintMethod = "printPCRelImmOperand";
+}
+
+// Operand for printing out a condition code.
+def cc : Operand<i32> {
+  let PrintMethod = "printCCOperand";
+}
+
+def isPointer : Predicate<"isPointer() == true">;
+def isnotPointer : Predicate<"isPointer() == false">;
+
+// TriCore Condition Codes
+def TriCore_COND_EQ : PatLeaf<(i32 0)>;
+def TriCore_COND_NE : PatLeaf<(i32 1)>;
+def TriCore_COND_GE : PatLeaf<(i32 2)>;
+def TriCore_COND_LT : PatLeaf<(i32 3)>;
+// TriCore Logic Codes
+def TriCore_LOGIC_AND_EQ : PatLeaf<(i32 0)>;
+def TriCore_LOGIC_AND_NE : PatLeaf<(i32 1)>;
+def TriCore_LOGIC_AND_GE : PatLeaf<(i32 2)>;
+def TriCore_LOGIC_AND_LT : PatLeaf<(i32 3)>;
+def TriCore_LOGIC_OR_EQ  : PatLeaf<(i32 0)>;
+def TriCore_LOGIC_OR_NE  : PatLeaf<(i32 1)>;
+def TriCore_LOGIC_OR_GE  : PatLeaf<(i32 12)>;
+def TriCore_LOGIC_OR_LT  : PatLeaf<(i32 13)>;
+
+// These are target-independent nodes, but have target-specific formats.
+def SDT_TriCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
+def SDT_TriCoreCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
+                                        SDTCisVT<1, i32> ]>;
+
+def TriCoreRetFlag    : SDNode<"TriCoreISD::RET_FLAG", SDTNone,
+                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_TriCoreCallSeqStart,
+                           [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
+def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_TriCoreCallSeqEnd,
+                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+                           SDNPSideEffect]>;
+
+//===----------------------------------------------------------------------===//
+// Instruction Pattern Stuff
+//===----------------------------------------------------------------------===//
+
+// Lower 32 bits of a 64-bit word
+def LO32 : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant((uint32_t) N->getZExtValue(), SDLoc(N),
+   MVT::i32);
+}]>;
+
+// Higher 32 bits of a 64-bit word
+def HI32 : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant((uint32_t) (N->getZExtValue()>>32), SDLoc(N),
+   MVT::i32);
+}]>;
+
+def INVERT_VAL : SDNodeXForm<imm, [{
+ outs() << "vall: "<< N->getZExtValue() <<"\n";
+ return CurDAG->getTargetConstant(-N->getZExtValue(), SDLoc(N), MVT::i32);
+}]>;
+
+def SHIFTAMT : SDNodeXForm<imm, [{
+ outs() << "vall: "<< N->getZExtValue() <<"\n";
+ return CurDAG->getTargetConstant(N->getZExtValue() - 32, SDLoc(N), MVT::i32);
+}]>;
+
+def SHIFTAMT_POS : SDNodeXForm<imm, [{
+ outs() << "vall: "<< N->getZExtValue() <<"\n";
+ return CurDAG->getTargetConstant((32 - N->getZExtValue()), SDLoc(N), MVT::i32);
+}]>;
+
+def SHIFTAMT_NEG : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(-(N->getZExtValue() - 32), SDLoc(N),
+   MVT::i32);
+}]>;
+
+def imm32_64 : PatLeaf<(imm),
+[{
+  uint64_t val = N->getZExtValue();
+  return val >= 32 && val < 64;
+}]>;
+
+def imm0_31 : PatLeaf<(imm),
+[{
+  uint64_t val = N->getZExtValue();
+ outs() <<"imm0_31: " << val << "\n";
+  return val > 0 && val < 32;
+}]>;
+
+//Operands
+def s4imm      : Operand<i32> { let PrintMethod = "printSExtImm<4>";  }
+def s6imm      : Operand<i32> { let PrintMethod = "printSExtImm<6>";  }
+def s8imm      : Operand<i32> { let PrintMethod = "printSExtImm<8>";  }
+def s9imm      : Operand<i32> { let PrintMethod = "printSExtImm<9>";  }
+def s10imm     : Operand<i32> { let PrintMethod = "printSExtImm<10>";  }
+def s16imm     : Operand<i32> { let PrintMethod = "printSExtImm<16>"; }
+def s24imm     : Operand<i32> { let PrintMethod = "printSExtImm<24>"; }
+def u8imm      : Operand<i32> { let PrintMethod = "printZExtImm<8>";  }
+def u4imm      : Operand<i32> { let PrintMethod = "printZExtImm<4>";  }
+def u2imm      : Operand<i32> { let PrintMethod = "printZExtImm<2>";  }
+def u9imm      : Operand<i32> { let PrintMethod = "printZExtImm<9>";  }
+def u16imm     : Operand<i32> { let PrintMethod = "printZExtImm<16>";  }
+
+def oext4imm: Operand<i32> { let PrintMethod = "printOExtImm<4>";  }
+
+def off18imm   : Operand<i32> { let PrintMethod = "printOff18Imm";  }
+
+def disp24imm  : Operand<i32> { let PrintMethod = "printDisp24Imm";  }
+def disp15imm   : Operand<i32> { let PrintMethod = "printDisp15Imm";  }
+def disp8imm   : Operand<i32> { let PrintMethod = "printDisp8Imm";  }
+def disp4imm   : Operand<i32> { let PrintMethod = "printDisp4Imm";  }
+
+def PairAddrRegsOp : RegisterOperand<PairAddrRegs, "printPairAddrRegsOperand">;
+
+//Nodes
+def immSExt4  : PatLeaf<(imm), [{ return isInt<4>(N->getSExtValue()); }]>;
+def immSExt6  : PatLeaf<(imm), [{ return isInt<6>(N->getSExtValue()); }]>;
+def immSExt9  : PatLeaf<(imm), [{ return isInt<9>(N->getSExtValue()); }]>;
+def immSExt10  : PatLeaf<(imm), [{ return isInt<10>(N->getSExtValue()); }]>;
+def immSExt16  : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
+def immSExt24  : PatLeaf<(imm), [{ return isInt<24>(N->getSExtValue()); }]>;
+
+def immZExt2 : ImmLeaf<i32, [{return Imm == (Imm & 0x3);}]>;
+def immZExt4 : ImmLeaf<i32, [{return Imm == (Imm & 0xf);}]>;
+def immZExt8 : ImmLeaf<i32, [{return Imm == (Imm & 0xff);}]>;
+def immZExt9 : ImmLeaf<i32, [{return Imm == (Imm & 0x1ff);}]>;
+def immZExt16 : ImmLeaf<i32, [{return Imm == (Imm & 0xffff);}]>;
+
+/// 16-Bit Opcode Formats
+
+class ISC_D15C<bits<8> op1, string asmstr, Operand TypeC=u8imm> 
+    : SC<op1, (outs), (ins TypeC:$const8),
+      asmstr # " %d15, $const8", []>;
+
+class ISC_A10C<bits<8> op1, string asmstr, Operand TypeC=u8imm> 
+    : SC<op1, (outs), (ins TypeC:$const8),
+      asmstr # " %sp, $const8", []>;
+
+class ISC_A15A10C<bits<8> op1, string asmstr, Operand TypeC=u8imm> 
+    : SC<op1, (outs), (ins TypeC:$const8),
+      asmstr # " %a15, [%sp]$const8", []>;
+
+class ISC_D15A10C<bits<8> op1, string asmstr, Operand TypeC=u8imm> 
+    : SC<op1, (outs), (ins TypeC:$const8),
+      asmstr # " %d15, [%sp]$const8", []>;
+
+class ISC_A10CA15<bits<8> op1, string asmstr, Operand TypeC=u8imm> 
+    : SC<op1, (outs), (ins TypeC:$const8),
+      asmstr # " [%sp]$const8, %a15", []>;
+
+class ISC_A10CD15<bits<8> op1, string asmstr, Operand TypeC=u8imm> 
+    : SC<op1, (outs), (ins TypeC:$const8),
+      asmstr # " [%sp]$const8, %d15", []>;
+
+class ISC_C<bits<8> op1, string asmstr, Operand TypeC=u8imm> 
+    : SC<op1, (outs), (ins TypeC:$const8),
+      asmstr # " $const8", []>;
+
+class ISRC_dC<bits<8> op1, string asmstr, RegisterClass RCd=RD, Operand TypeC=s4imm> 
+    : SRC<op1, (outs RCd:$d), (ins TypeC:$const4),
+          asmstr # " $d, $const4", []>;
+
+class ISRC_dD15C<bits<8> op1, string asmstr, RegisterClass RCd=RD, Operand TypeC=s4imm> 
+    : SRC<op1, (outs RCd:$d), (ins TypeC:$const4),
+      asmstr # " $d, %d15, $const4", []>;
+
+class ISRC_D15dC<bits<8> op1, string asmstr, RegisterClass RCd=RD, Operand TypeC=s4imm> 
+    : SRC<op1, (outs RCd:$d), (ins TypeC:$const4),
+      asmstr # " %d15, $d, $const4", []>;
+
+multiclass mISRR_SRC<bits<8> op_srr, bits<8> op_src, string asmstr,
+                     RegisterClass RCd=RD, RegisterClass RC2=RD, Operand Oc=u4imm, string posfix="">{
+  def _srr#posfix: SRR<op_srr, (outs RCd:$d), (ins RC2:$s2),
+                asmstr # " %d15, $d, $s2", []>;
+  def _src#posfix: SRC<op_src, (outs RCd:$d), (ins Oc:$const4),
+                asmstr # " %d15, $d, $const4", []>;
+}
+
+multiclass mISRC_a15a<bits<8> op1, bits<8> op2, bits<8> op3,
+                        string asmstr> {
+  def _src : ISRC_dC<op1, asmstr>;
+  def _src_a15 : ISRC_dD15C<op2, asmstr>, Requires<[HasV120_UP]>;
+  def _src_15a : ISRC_D15dC<op3, asmstr>;
+}
+
+/// 32-Bit Opcode Formats
+
+/// RC
+
+class IRC_C<bits<8> op1, bits<7> op2, string asmstr>
+    : RC<op1, op2, (outs), (ins s9imm:$const9),
+      asmstr # " $const9", []>;
+
+class IRC<bits<8> op1, bits<7> op2, string asmstr, RegisterClass RCd=RD, RegisterClass RC1=RD, Operand TypeC=s9imm>
+    : RC<op1, op2, (outs RCd:$d), (ins RC1:$s1, TypeC:$const9),
+         asmstr # " $d, $s1, $const9", []>;
+
+/// RR
+
+class IRR_0<bits<8> op1, bits<8> op2, string asmstr>: RR<op1, op2, (outs), (ins), asmstr, []>;
+
+class IRR_R1<bits<8> op1, bits<8> op2, string asmstr, RegisterClass RC=RD>
+    : RR<op1, op2, (outs), (ins RC:$s1), asmstr # " $s1", []>;
+class IRR_R2<bits<8> op1, bits<8> op2, string asmstr, RegisterClass RC=RD>
+    : RR<op1, op2, (outs), (ins RC:$s2), asmstr # " $s2", []>;
+
+/// op R[c], R[a]
+class IRR_a<bits<8> op1, bits<8> op2, string asmstr, RegisterClass cd=RD, RegisterClass c1=RD>
+    : RR<op1, op2, (outs cd:$d), (ins c1:$s1),
+      asmstr # " $d, $s1", []>;
+
+/// op R[c], R[b]
+class IRR_b<bits<8> op1, bits<8> op2, string asmstr, RegisterClass cd=RD, RegisterClass c2=RD>
+    : RR<op1, op2, (outs cd:$d), (ins c2:$s1, c2:$s2),
+         asmstr # " $d, $s2", []>;
+
+/// R[c], R[a], R[b]
+class IRR_2<bits<8> op1, bits<8> op2, string asmstr
+          , RegisterClass cd=RD, RegisterClass c1=RD, RegisterClass c2=RD>
+    : RR<op1, op2, (outs cd:$d), (ins c1:$s1, c2:$s2), asmstr, []>;
+
+class IRR_dab<bits<8> op1, bits<8> op2, string asmstr,
+              RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD>
+    : IRR_2<op1, op2, asmstr # " $d, $s1, $s2", RCd, RC1, RC2>;
+
+class IRR_dba<bits<8> op1, bits<8> op2, string asmstr,
+              RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD>
+    : IRR_2<op1, op2, asmstr # " $d, $s2, $s1", RCd, RC1, RC2>;
+
+class IRR_dabn<bits<8> op1, bits<8> op2, string asmstr,
+              RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD, Operand TypeC=u2imm>
+    : RR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, TypeC:$n), asmstr#" $d, $s1, $s2, $n", []>;
+class IRR_dban<bits<8> op1, bits<8> op2, string asmstr,
+              RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD, Operand TypeC=u2imm>
+    : RR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, TypeC:$n), asmstr#" $d, $s2, $s1, $n", []>;
+
+multiclass mIRR_RC<bits<8> rr1, bits<8> rr2, bits<8> rc1, bits<7> rc2, string asmstr,
+                   RegisterClass RCd=RD, RegisterClass RC1=RD, Operand TypeC=s9imm> {
+  def _rr : IRR_dab<rr1, rr2, asmstr, RCd, RC1>;
+  def _rc : IRC<rc1, rc2, asmstr, RCd, RC1, TypeC>;
+}
+
+class IRLC<bits<8> op1, string asmstr, Operand TypeC=s16imm, RegisterClass RCd=RD, RegisterClass RC1=RD>
+    : RLC<op1, (outs RCd:$d), (ins RC1:$s1, TypeC:$const16),
+      asmstr # " $d, $s1, $const16",
+      []>;
+
+
+class ISRR_db<bits<8> op1, string asmstr, RegisterClass RCd=RD, RegisterClass RC2=RD>
+    : SRR<op1, (outs RCd:$d), (ins RC2:$s2),
+      asmstr # " $d, $s2", []>;
+
+class ISRR_dD15b<bits<8> op1, string asmstr, RegisterClass RCd=RD, RegisterClass RC2=RD>
+    : SRR<op1, (outs RCd:$d), (ins RC2:$s2),
+      asmstr # " $d, %d15, $s2", []>;
+
+class ISRR_D15db<bits<8> op1, string asmstr, RegisterClass RCd=RD, RegisterClass RC2=RD>
+    : SRR<op1, (outs RCd:$d), (ins RC2:$s2),
+      asmstr # " %d15, $d, $s2", []>;
+
+
+multiclass mISRR_s<bits<8> op1, string asmstr>{
+    def _srr : ISRR_db<op1, asmstr>;
+}
+
+multiclass mISRR_a15a<bits<8> op1, bits<8> op2, bits<8> op3,
+                    string asmstr>{
+  def _srr     : ISRR_db<op1, asmstr>;
+  def _srr_a15 : ISRR_dD15b<op2, asmstr>, Requires<[HasV120_UP]>;
+  def _srr_15a : ISRR_D15db<op3, asmstr>;
+}
+
+class IBIT<bits<8> op1, bits<2> op2, string asmstr>
+    : BIT<op1, op2, (outs RD:$d), (ins RD:$s1, RD:$s2, u4imm:$pos1, u4imm:$pos_r),
+      asmstr # " $d, $s1, $pos1, $s2, $pos_r",
+      []>;
+
+class NsRequires<list<Predicate> Ps> : Requires<Ps> {
+  string DecoderNamespace = !cond(!eq(HasV110, !head(Ps)): "v110",
+                                  !eq(HasV120, !head(Ps)): "v120",
+                                  !eq(HasV130, !head(Ps)): "v130",
+                                  !eq(HasV131, !head(Ps)): "v131",
+                                  !eq(HasV160, !head(Ps)): "v160",
+                                  !eq(HasV161, !head(Ps)): "v161",
+                                  !eq(HasV162, !head(Ps)): "v162",
+                                  true: "");
+}
+
+//===----------------------------------------------------------------------===//
+// Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+// Arithmetic Instructions
+
+// Absolute Value Instructions
+let Defs = [PSW] in {
+   def ABS_rr : RR<0x0B, 0x1C, (outs RD:$d),
+                              (ins RD:$s2),
+                  "abs $d, $s2",
+                  [(set RD:$d, (TriCoreAbs RD:$s2))]>;
+   def ABS_B_rr : RR<0x0B, 0x5C, (outs RD:$d),
+                                (ins RD:$s2),
+                                 "abs.b $d, $s2",
+                  [(set RD:$d, (TriCoreAbs RD:$s2))]>;
+   def ABS_H_rr : RR<0x0B, 0x7C, (outs RD:$d),
+                                (ins RD:$s2),
+                                 "abs.h $d, $s2",
+                  [(set RD:$d, (TriCoreAbs RD:$s2))]>;
+
+   def ABSDIF_rc : RC<0x8B, 0x0E, (outs RD:$d),
+                  (ins RD:$s1, s9imm:$const9), "absdif $d, $s1, $const9",
+                  [(set RD:$d, (TriCoreAbsDif RD:$s1, immSExt9:$const9))]>;
+   def ABSDIF_rr : RR<0x0B, 0x0E, (outs RD:$d),
+                  (ins RD:$s1, RD:$s2), "absdif $d, $s1, $s2",
+                  [(set RD:$d, (TriCoreAbsDif RD:$s1, RD:$s2))]>;
+   def ABSDIF_B_rr : RR<0x0B, 0x4E, (outs RD:$d),
+                  (ins RD:$s1, RD:$s2), "absdif.b $d, $s1, $s2",
+                  [(set RD:$d, (TriCoreAbsDif RD:$s1, RD:$s2))]>;
+   def ABSDIF_H_rr : RR<0x0B, 0x6E, (outs RD:$d),
+                  (ins RD:$s1, RD:$s2), "absdif.h $d, $s1, $s2",
+                  [(set RD:$d, (TriCoreAbsDif RD:$s1, RD:$s2))]>;
+
+   def ABSDIFS_rc : RC<0x8B, 0x0F, (outs RD:$d),
+                  (ins RD:$s1, RD:$s2), "absdifs $d, $s1, $s2",
+                  [(set RD:$d, (TriCoreAbsDif RD:$s1, RD:$s2))]>;
+   def ABSDIFS_rr : RR<0x0B, 0x0F, (outs RD:$d),
+                  (ins RD:$s1, RD:$s2), "absdifs $d, $s1, $s2",
+                  [(set RD:$d, (TriCoreAbsDif RD:$s1, RD:$s2))]>;
+   def ABSDIFS_B_rr_v110 : RR<0x0B, 0x4F, (outs RD:$d),
+                        (ins RD:$s1, RD:$s2), "absdifs.b $d, $s1, $s2",
+                        [(set RD:$d, (TriCoreAbsDif RD:$s1, RD:$s2))]>
+                    , NsRequires<[HasV110]>;
+   def ABSDIFS_H_rr : RR<0x0B, 0x6F, (outs RD:$d),
+                  (ins RD:$s1, RD:$s2), "absdifs.h $d, $s1, $s2",
+                  [(set RD:$d, (TriCoreAbsDif RD:$s1, RD:$s2))]>;
+
+   def ABSS_rr : RR<0x0B, 0x1D, (outs RD:$d),
+                  (ins RD:$s1, RD:$s2), "abss $d, $s2",
+                  [(set RD:$d, (TriCoreAbsDif RD:$s1, RD:$s2))]>;
+   def ABSS_B_rr_v110 : RR<0x0B, 0x5D, (outs RD:$d),
+                        (ins RD:$s1, RD:$s2), "abss.b $d, $s2",
+                        [(set RD:$d, (TriCoreAbsDif RD:$s1, RD:$s2))]>
+                    , NsRequires<[HasV110]>;
+   def ABSS_H_rr : RR<0x0B, 0x7D, (outs RD:$d),
+                  (ins RD:$s1, RD:$s2), "abss.h $d, $s2",
+                  [(set RD:$d, (TriCoreAbsDif RD:$s1, RD:$s2))]>;
+}
+
+multiclass mIB_H<bits<8> brr1, bits<8> brr2, bits<8> hrr1, bits<8> hrr2,
+                        string asmstr> {
+  def _B_rr : IRR_dab<brr1, brr2, asmstr # ".b">;
+  def _H_rr : IRR_dab<hrr1, hrr2, asmstr # ".h">;
+}
+
+// - ADD Instructions
+
+defm ADD : mIRR_RC<0x0B, 0x00, 0x8B, 0x00, "add">,
+           mISRC_a15a<0xC2, 0x92, 0x9A, "add">,
+           mISRR_a15a<0x42, 0x12, 0x1A, "add">,
+           mIB_H<0x0B, 0x40, 0x0B, 0x60, "add">;
+
+multiclass mIRR_SRC_SRR__A<bits<8> rr1, bits<8> rr2, bits<8> src1, bits<8> srr1,
+                        string asmstr> {
+  def _rr : IRR_dab<rr1, rr2, asmstr, RA, RA, RA>;
+  def _src : ISRC_dC<src1, asmstr, RA>, Requires<[HasV120_UP]>;
+  def _srr : ISRR_db<srr1, asmstr, RA, RA>, Requires<[HasV120_UP]>;
+}
+
+defm ADD_A : mIRR_SRC_SRR__A<0x01, 0x01, 0xB0, 0x30, "add.a">;
+defm ADDC : mIRR_RC<0x0B, 0x05, 0x8B, 0x05, "addc">;
+
+multiclass mIRLC<bits<8> op1, bits<8> op2, bits<8> op3, string asmstr>{
+  def _rlc    : IRLC<op1, asmstr>;
+  def H_rlc   : IRLC<op2, asmstr # "h", u16imm>;
+  def H_A_rlc : IRLC<op3, asmstr # "h.a", u16imm, RA, RA>;
+}
+
+defm ADDI : mIRLC<0x1B, 0x9B, 0x11, "addi">;
+
+multiclass mIH_HU_U<bits<8> h1, bits<8> h2,
+                    bits<8> hu1, bits<8> hu2,
+                    bits<8> u1, bits<8> u2,
+                    string asmstr>{
+  def _H  : IRR_dab<h1, h2, asmstr # ".h">;
+  def _HU : IRR_dab<hu1,hu2,asmstr # ".hu">;
+  def _U  : IRR_dab<u1, u2, asmstr # ".u">;
+}
+
+defm ADDS : mIRR_RC<0x0B, 0x02, 0x8B, 0x02, "adds">,
+            mISRR_s<0x22, "adds">,
+            mIH_HU_U<0x0B, 0x62, 0x0B, 0x63, 0x0B, 0x03, "adds">;
+def ADDS_U_rc : IRC<0x8B, 0x03, "adds.u">;
+def ADDS_B_rr : IRR_dab<0x0B, 0x42, "adds.b">, NsRequires<[HasV110]>;
+
+def ADDSC_A_srrs_v110 : SRRS<0x10, (outs RA:$d), (ins RD:$s2, u2imm:$n),
+                            "addsc.a $d, $s2, $n", []>
+                      , NsRequires<[HasV110]>;
+def ADDSC_A_srrs: SRRS<0x10, (outs RA:$d), (ins RA:$s2, u2imm:$n),
+                      "addsc.a $d, $s2, %d15, $n", []>
+                , Requires<[HasV120_UP]>;
+
+def ADDSC_A_rr_v110: IRR_dabn<0x01, 0x60, "addsc.a", RA, RA, RD>, NsRequires<[HasV110]>;
+def ADDSC_A_rr     : IRR_dban<0x01, 0x60, "addsc.a", RA, RD, RA>, Requires<[HasV120_UP]>;
+
+def ADDSC_AT_rr_v110 : IRR_dab<0x01, 0x62, "addsc.at", RA, RA>, NsRequires<[HasV110]>;
+def ADDSC_AT_rr : IRR_dba<0x01, 0x62, "addsc.at", RA, RD, RA>, Requires<[HasV120_UP]>;
+
+def ADDS_BU_rr_v110 : IRR_dab<0x0B, 0x43, "adds.bu">, Requires<[HasV110]>;
+
+defm ADDX : mIRR_RC<0x0B, 0x04, 0x8B, 0x04, "addx">;
+
+
+/// AND Instructions
+
+defm AND : mIRR_RC<0x0F, 0x08, 0x8F, 0x08, "and">;
+
+def AND_srr      : ISRR_db<0x26, "and">, Requires<[HasV120_UP]>;
+def AND_srr_v110 : ISRR_db<0x16, "and">, NsRequires<[HasV110]>;
+def AND_sc       : ISC_D15C<0x16, "and">, Requires<[HasV120_UP]>;
+def AND_sc_v110  : ISC_D15C<0x96, "and">, NsRequires<[HasV110]>;
+
+def AND_AND_T  : IBIT<0x47, 0x00, "and.and.t">;
+def AND_ANDN_T : IBIT<0x47, 0x03, "and.andn.t">;
+def AND_NOR_T  : IBIT<0x47, 0x02, "and.nor.t">;
+def AND_OR_T   : IBIT<0x47, 0x01, "and.or.t">;
+def AND_T      : IBIT<0x87, 0x00, "and.t">;
+def ANDN_T     : IBIT<0x87, 0x03, "andn.t">;
+
+defm AND_EQ   : mIRR_RC<0x0B, 0x20, 0x8B, 0x20, "and.eq">;
+defm AND_GE   : mIRR_RC<0x0B, 0x24, 0x8B, 0x24, "and.ge">;
+defm AND_GE_U : mIRR_RC<0x0B, 0x25, 0x8B, 0x25, "and.ge.u">;
+defm AND_LT   : mIRR_RC<0x0B, 0x22, 0x8B, 0x22, "and.lt">;
+defm AND_LT_U : mIRR_RC<0x0B, 0x23, 0x8B, 0x23, "and.lt.u">;
+defm AND_NE   : mIRR_RC<0x0B, 0x21, 0x8B, 0x21, "and.ne">;
+
+defm ANDN     : mIRR_RC<0x0F, 0x0E, 0x8F, 0x0E, "andn">;
+
+/// BISR
+def BISR_rc : IRC_C<0xAD, 0x00, "bisr">;
+def BISR_rc_v161 : IRC_C<0xAD, 0x01, "bisr">, NsRequires<[HasV161]>;
+
+def BISR_sc_v110 : ISC_C<0xC0, "bisr">, NsRequires<[HasV110]>;
+def BISR_sc : ISC_C<0xE0, "bisr">, Requires<[HasV120_UP]>;
+
+/// Multiple Instructions (RR)
+def BMERGAE_rr_v110 : IRR_dab<0x4B, 0x00, "bmerge">, NsRequires<[HasV110]>;
+def BMERGE_rr : IRR_dab<0x4B, 0x01, "bmerge">, Requires<[HasV120_UP]>;
+
+def BSPLIT_rr_v110: IRR_a<0x4B, 0x60, "bsplit", RE>, NsRequires<[HasV110]>;
+def BSPLIT_rr     : IRR_a<0x4B, 0x09, "bsplit", RE>, Requires<[HasV120_UP]>;
+
+/// BO Opcode Formats
+// A[b], off10 (BO) (Base + Short Offset Addressing Mode)
+class IBO_bso<bits<8> op1, bits<6> op2, string asmstr> 
+    : BO<op1, op2, (outs), (ins RA:$s2, s10imm:$off10),
+      asmstr # " [$s2]$off10", []>;
+// P[b] (BO) (Bit Reverse Addressing Mode)
+class IBO_r<bits<8> op1, bits<6> op2, string asmstr> 
+    : BO<op1, op2, (outs), (ins RP:$s2),
+      asmstr # " [${s2}+r]", []>;
+// P[b], off10 (BO) (Circular Addressing Mode)
+class IBO_c<bits<8> op1, bits<6> op2, string asmstr> 
+    : BO<op1, op2, (outs), (ins RP:$s2, s10imm:$off10),
+      asmstr # " [${s2}+c]$off10", []>;
+// A[b], off10 (BO) (Post-increment Addressing Mode)
+
+class IBO_pos<bits<8> op1, bits<6> op2, string asmstr> 
+    : BO<op1, op2, (outs), (ins RA:$s2, s10imm:$off10),
+      asmstr # " [${s2}+]$off10", []>;
+// A[b], off10 (BO) (Pre-increment Addressing Mode)
+class IBO_pre<bits<8> op1, bits<6> op2, string asmstr> 
+    : BO<op1, op2, (outs), (ins RA:$s2, s10imm:$off10),
+      asmstr # " [+${s2}]$off10", []>;
+
+
+multiclass mI_CACHEI_<bits<8> prefix, bits<6> op12, bits<6> op22, bits<6> op32, string asmstr> {
+    def _bo_bso : IBO_bso<prefix, op12, asmstr>;
+    def _bo_pos : IBO_pos<prefix, op22, asmstr>;
+    def _bo_pre : IBO_pre<prefix, op32, asmstr>;
+}
+
+multiclass mI_CACHE_<bits<8> prefixi, bits<8> prefix_r_c, bits<6> bso, bits<6> pos_r, bits<6> pre_c, string asmstr>{
+  defm "" : mI_CACHEI_<prefixi, bso, pos_r, pre_c, asmstr>;
+  def _bo_r: IBO_r<prefix_r_c, pos_r, asmstr>;
+  def _bo_c: IBO_c<prefix_r_c, pre_c, asmstr>;
+}
+
+/// CACHEA.* Instructions
+
+defm CACHEA_I : mI_CACHE_<0x89, 0xA9, 0x2E, 0x0E, 0x1E, "cachea.i">, Requires<[HasV120_UP]>;
+defm CACHEA_W : mI_CACHE_<0x89, 0xA9, 0x2C, 0x0C, 0x1C, "cachea.w">, Requires<[HasV120_UP]>;
+defm CACHEA_WI: mI_CACHE_<0x89, 0xA9, 0x2D, 0x0D, 0x1D, "cachea.wi">, Requires<[HasV120_UP]>;
+
+defm CACHEI_W : mI_CACHEI_<0x89, 0x2B, 0x0B, 0x1B, "cachei.w">, Requires<[HasV131_UP]>;
+defm CACHEI_I : mI_CACHEI_<0x89, 0x2A, 0x0A, 0x1A, "cachei.i">, Requires<[HasV160_UP]>;
+defm CACHEI_WI: mI_CACHEI_<0x89, 0x2F, 0x0F, 0x1F, "cachei.wi">, Requires<[HasV131_UP]>;
+
+
+/// RRR Opcodes Formats
+
+class IRRR<bits<8>op1, bits<4> op2, string asmstr,
+           RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD, RegisterClass RC3=RD>
+    : RRR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, RC3:$s3),
+          asmstr # " $d, $s3, $s1, $s2", []>;
+
+class IRRR_d31<bits<8>op1, bits<4> op2, string asmstr,
+             RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD, RegisterClass RC3=RD>
+    : RRR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, RC3:$s3), asmstr # " $d, $s3, $s1", []>;
+
+class IRRR_d32<bits<8>op1, bits<4> op2, string asmstr,
+              RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC2=RD, RegisterClass RC3=RD>
+    : RRR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, RC3:$s3),
+          asmstr # " $d, $s3, $s2", []>;
+
+/// RCR Opcodes Formats
+class IRCR<bits<8> op1, bits<3> op2, string asmstr,
+           RegisterClass RCd=RD, RegisterClass RC1=RD, RegisterClass RC3=RD, Operand TypeC=s9imm>
+    : RCR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC3:$s3, TypeC:$const9),
+          asmstr # " $d, $s3, $s1, $const9", []>;
+
+multiclass mIRCR<bits<8>op1, bits<3> op2, bits<8>op3, bits<3> op4, string asmstr>{
+  def _rcr   : IRCR<op1, op2, asmstr>;
+  def _rcr_e : IRCR<op3, op4, asmstr, RE, RD, RE, s9imm>, Requires<[HasV120_UP]>;
+}
+
+/// CADD Instructions
+def CADD_srr_v110 : ISRR_dD15b<0x0A, "cadd">, NsRequires<[HasV110]>;
+
+def CADD_rcr : IRCR<0xAB, 0x00, "cadd">;
+def CADD_rrr : IRRR<0x2B, 0x00, "cadd">;
+def CADD_src : ISRC_dD15C<0x8A, "cadd">;
+
+multiclass mI_CADDnA_CSUBnA_v110_<bits<8> rrr1, bits<4> rrr2, bits<8> rcr1, bits<3> rcr2, string asmstr>{
+  def _rrr_v110: IRRR<rrr1, rrr2, asmstr, RA, RA, RA, RD>, NsRequires<[HasV110]>;
+  if !or(!eq(asmstr, "cadd.a"), !eq(asmstr, "caddn.a")) then {
+    def _rcr_v110: RCR<rcr1, rcr2, (outs RA:$d), (ins RA:$s1, RD:$s3, s9imm:$const9),
+                     asmstr#" $d, $s3, $s1, $const9", []>
+               , NsRequires<[HasV110]>;
+  }
+}
+
+defm CADD_A: mI_CADDnA_CSUBnA_v110_<0x21, 0x00, 0xA1, 0x00, "cadd.a">;
+
+def CADDN_srr_v110  : ISRR_dD15b<0x4A, "caddn">
+                    , NsRequires<[HasV110]>;
+
+def CADDN_rcr : IRCR<0xAB, 0x01, "caddn">;
+def CADDN_rrr : IRRR<0x2B, 0x01, "caddn">;
+def CADDN_src : ISRC_dD15C<0xCA, "caddn">;
+
+defm CADDN_A: mI_CADDnA_CSUBnA_v110_<0x21, 0x01, 0xA1, 0x01, "caddn.a">;
+
+// Call Instructions
+
+class IB<bits<8> op1, string asmstr>
+    : B<op1, (outs), (ins disp24imm:$disp24),
+        asmstr # " $disp24", []>;
+
+// The target of a 24-bit call instruction.
+def call_target : Operand<i32> {
+  let EncoderMethod = "encodeCallTarget";
+}
+
+class ISB<bits<8> op1, string asmstr>
+    : SB<op1, (outs), (ins disp8imm:$disp8), asmstr # " $disp8", []>;
+
+class ISB_D15D<bits<8> op1, string asmstr>
+    : SB<op1, (outs), (ins disp8imm:$disp8), asmstr # " %d15, $disp8", []>;
+
+let isCall = 1,
+    Defs = [A11],
+    Uses = [A10] in {
+  def CALL_b    : IB<0x6D, "call">;
+  def CALL_sb   : ISB<0x5C, "call">, Requires<[HasV120_UP]>;
+  def CALLA_b   : IB<0xED, "calla">;
+  def CALLI_rr_v110: IRR_R2<0x2D, 0x00, "calli", RA>, NsRequires<[HasV110]>;
+  def CALLI_rr  : IRR_R1<0x2D, 0x00, "calli", RA>, Requires<[HasV120_UP]>;
+}
+
+multiclass mI_H<bits<8> op1,bits<8> op2,bits<8> op3, bits<8> op4, string asmstr> {
+  def _rr   : IRR_a<op1, op2, asmstr>;
+  def _H_rr : IRR_a<op3, op4, asmstr # ".h">;
+}
+
+defm CLO : mI_H<0x0F, 0x1C, 0x0F, 0x7D, "clo">;
+def CLO_B_rr_v110 : IRR_a<0x0F, 0x3D, "clo.b">, NsRequires<[HasV110]>;
+defm CLS : mI_H<0x0F, 0x1D, 0x0F, 0x7E, "cls">;
+def CLS_B_rr_v110 : IRR_a<0x0F, 0x3E, "cls.b">, NsRequires<[HasV110]>;
+defm CLZ : mI_H<0x0F, 0x1B, 0x0F, 0x7C, "clz">;
+def CLZ_B_rr_v110 : IRR_a<0x0F, 0x3C, "clz.b">, NsRequires<[HasV110]>;
+
+def CMOV_src  : ISRC_dD15C<0xAA, "cmov">;
+def CMOV_srr  : ISRR_dD15b<0x2A, "cmov">;
+def CMOVN_src : ISRC_dD15C<0xEA, "cmovn">;
+def CMOVN_srr : ISRR_dD15b<0x6A, "cmovn">;
+
+// A[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode)
+class IBO_bsoAbOEa<bits<8> op1, bits<6> op2, string asmstr> 
+    : BO<op1, op2, (outs), (ins RE:$s1, RA:$s2, s10imm:$off10),
+      asmstr # " [$s2]$off10, $s1", []>;
+// P[b], E[a] (BO)(Bit-reverse Addressing Mode)
+class IBO_rPbEa<bits<8> op1, bits<6> op2, string asmstr> 
+    : BO<op1, op2, (outs), (ins RE:$s1, RP:$s2),
+      asmstr # " [${s2}+r], $s1", []>;
+// P[b], off10, E[a] (BO)(Circular Addressing Mode)
+class IBO_cPbOEa<bits<8> op1, bits<6> op2, string asmstr> 
+    : BO<op1, op2, (outs), (ins RE:$s1, RP:$s2, s10imm:$off10),
+      asmstr # " [${s2}+c]$off10, $s1", []>;
+// A[b], off10, E[a] (BO)(Post-increment Addressing Mode)
+class IBO_posAbOEa<bits<8> op1, bits<6> op2, string asmstr> 
+    : BO<op1, op2, (outs), (ins RE:$s1, RA:$s2, s10imm:$off10),
+      asmstr # " [${s2}+]$off10, $s1", []>;
+// A[b], off10, E[a] (BO)(Pre-increment Addressing Mode)
+class IBO_preAbOEa<bits<8> op1, bits<6> op2, string asmstr> 
+    : BO<op1, op2, (outs), (ins RE:$s1, RA:$s2, s10imm:$off10),
+      asmstr # " [+$s2]$off10, $s1", []>;
+
+
+multiclass mIBO_Ea<bits<8> bso1, bits<6> bso2, ///_bso
+                   bits<8> r1, bits<6> r2, ///_r
+                   bits<8> c1, bits<6> c2, ///_c
+                   bits<8> pos1, bits<6> pos_r, ///_post
+                   bits<8> pre1, bits<6> pre_c, ///_pre
+                   string asmstr>{
+  def _bo_bso  : IBO_bsoAbOEa<bso1, bso2, asmstr>;
+  def _bo_pos  : IBO_posAbOEa<pos1, pos_r, asmstr>;
+  def _bo_pre  : IBO_preAbOEa<pre1, pre_c, asmstr>;
+  def _bo_r    : IBO_rPbEa<r1, r2, asmstr>;
+  def _bo_c    : IBO_cPbOEa<c1, c2, asmstr>;
+}
+
+defm CMPSWAP_W : mIBO_Ea<0x49, 0x23, 0x69, 0x03,
+                         0x69, 0x13, 0x49,0x03,
+                         0x49, 0x13, "cmpswap.w">
+               , Requires<[HasV161_UP]>;
+
+def CRC32_B_rr  : IRR_dba<0x4B, 0x06, "crc32.b">, Requires<[HasV162]>;
+def CRC32B_W_rr : IRR_dba<0x4B, 0x03, "crc32b.w">, Requires<[HasV162]>;
+def CRC32L_W_rr : IRR_dba<0x4B, 0x07, "crc32l.w">, Requires<[HasV162]>;
+def CRCN_rrr    : IRRR<0x6B, 0x01, "crcn">, Requires<[HasV162]>;
+
+def CSUB_rrr    : IRRR<0x2B, 0x02, "csub">;
+def CSUBN_rrr   : IRRR<0x2B, 0x03, "csubn">;
+
+defm CSUB_A_: mI_CADDnA_CSUBnA_v110_<0x21, 0x02, 0, 0, "csub.a">;
+defm CSUBN_A_: mI_CADDnA_CSUBnA_v110_<0x21, 0x03, 0, 0, "csubn.a">;
+
+class ISR_0<bits<8> op1, bits<4> op2, string asmstr>
+    : SR<op1, op2, (outs), (ins),
+        asmstr, []>;
+
+class ISR_1<bits<8> op1, bits<4> op2, string asmstr, RegisterClass RC1=RD>
+    : SR<op1, op2, (outs), (ins RC1:$s1),
+        asmstr # " $s1", []>;
+
+class ISYS_0<bits<8> op1, bits<6> op2, string asmstr>
+    : SYS<op1, op2, (outs), (ins),
+        asmstr, []>;
+class ISYS_1<bits<8> op1, bits<6> op2, string asmstr, RegisterClass RC1=RD>
+    : SYS<op1, op2, (outs), (ins RC1:$s1),
+        asmstr # " $s1", []>;
+
+def DEBUG_sr  : ISR_0<0x00, 0x0A, "debug">;
+def DEBUG_sys : ISYS_0<0x0D, 0x04, "debug">;
+
+/// RRRR Instruction Formats
+/// op D[c], D[a], D[b], D[d]
+class IRRRR<bits<8> op1, bits<3> op2, string asmstr> 
+    : RRRR<op1, op2, (outs RD:$d), (ins RD:$s1, RD:$s2, RD:$s3),
+            asmstr # " $d, $s1, $s2, $s3", []>;
+/// op D[c], D[a], D[d]
+class IRRRR_ad<bits<8> op1, bits<3> op2, string asmstr, RegisterClass RC3=RD> 
+    : RRRR<op1, op2, (outs RD:$d), (ins RD:$s1, RC3:$s3),
+            asmstr # " $d, $s1, $s3", []>;
+
+/// op D[c], D[a], D[b], D[d], width
+class IRRRW_cabdw<bits<8> op1, bits<3> op2, string asmstr>
+     : RRRW<op1, op2, (outs RD:$d), (ins RD:$s1, RD:$s2, RD:$s3, i32imm:$width),
+            asmstr # " $d, $s1, $s2, $s3, $width", []>;
+/// op D[c], D[a], D[d], width
+class IRRRW_cadw<bits<8> op1, bits<3> op2, string asmstr>
+     : RRRW<op1, op2, (outs RD:$d), (ins RD:$s1, RD:$s2, RD:$s3, i32imm:$width),
+            asmstr # " $d, $s1, $s3, $width", []>;
+/// op E[c], D[b], D[d], width
+class IRRRW_cEbdw<bits<8> op1, bits<3> op2, string asmstr>
+     : RRRW<op1, op2, (outs RE:$d), (ins RD:$s1, RD:$s2, RD:$s3, i32imm:$width),
+            asmstr # " $d, $s2, $s3, $width", []>;
+
+def DEXTR_rrpw : RRPW<0x77, 0x00, (outs RD:$d), (ins RD:$s1, RD:$s2, i32imm:$pos, i32imm:$width),
+                      "dextr $d, $s1, $s2, $pos", []>;
+def DEXTR_rrrr : IRRRR<0x17, 0x04, "dextr">;
+
+def DIFSC_A_rr_v110 : IRR_dabn<0x01, 0x50, "difsc.a", RD, RA, RA>, NsRequires<[HasV110]>;
+
+def DISABLE_sys   : ISYS_0<0x0D, 0x0D, "disable">;
+def DISABLE_sys_1 : ISYS_1<0x0D, 0x0F, "disable">, Requires<[HasV160_UP]>;
+
+def DSYNC_sys : ISYS_0<0x0D, 0x12, "dsync">;
+
+def DVADJ_srr_v110 : ISRR_db<0x72, "dvadj", RE, RD>, NsRequires<[HasV110]>;
+def DVADJ_rrr_v110 : IRRR_d32<0x2B, 0x08, "dvadj", RE, RD, RD, RE>, NsRequires<[HasV110]>;
+def DVADJ_rrr : IRRR_d32<0x6B, 0x0D, "dvadj", RE, RD, RD, RE>, Requires<[HasV120_UP]>;
+
+multiclass mI_U_RR_Eab<bits<8> op1, bits<8> op2, bits<8> op3, bits<8> op4,
+                string asmstr, string posfix = ""> {
+  def _rr   # posfix : IRR_dab<op1, op2, asmstr, RE>;
+  def _U_rr # posfix : IRR_dab<op3, op4, asmstr # ".u", RE>;
+}
+
+multiclass mIU_RR_Eab<bits<8> op1, bits<8> op2, bits<8> op3, bits<8> op4,
+                string asmstr, string posfix = ""> {
+  def _rr  # posfix : IRR_dab<op1, op2, asmstr, RE>;
+  def U_rr # posfix : IRR_dab<op3, op4, asmstr # "u", RE>;
+}
+
+multiclass mI_DVINIT_<bits<8> oprefix,
+                   bits<8> op, bits<8> op_u,
+                   bits<8> opb, bits<8> opbu,
+                   bits<8> oph, bits<8> ophu,
+                   string asmstr, string posfix = ""> {
+defm "": mI_U_RR_Eab<oprefix, op,  oprefix, op_u, asmstr, posfix>;
+defm _B: mIU_RR_Eab <oprefix, opb, oprefix, opbu, asmstr # ".b", posfix>;
+defm _H: mIU_RR_Eab <oprefix, oph, oprefix, ophu, asmstr # ".h", posfix>;
+}
+
+defm DIV     : mI_U_RR_Eab<0x4B, 0x20, 0x4B, 0x21, "div">, Requires<[HasV160_UP]>;
+
+defm DVINIT : mI_DVINIT_<0x4F, 0x00, 0x01, 0x04, 0x05, 0x02, 0x03, "dvinit", "_v110">, NsRequires<[HasV110]>;
+defm DVINIT : mI_DVINIT_<0x4B, 0x1A, 0x0A, 0x5A, 0x4A, 0x3A, 0x2A, "dvinit">, Requires<[HasV120_UP]>;
+
+multiclass mI_U_RRR_EEdb<bits<8> op1, bits<4> op2, bits<8> op3, bits<4> op4,
+                string asmstr, string posfix = ""> {
+  def _rrr # posfix  : IRRR_d32<op1, op2, asmstr, RE, RD, RD, RE>;
+  def _U_rrr # posfix: IRRR_d32<op3, op4, asmstr # ".u", RE, RD, RD, RE>;
+}
+
+multiclass mI_U_SRR_sds2<bits<8> op1, bits<8> op2, string asmstr, 
+                        string posfix = "", RegisterClass RC1, RegisterClass RC2>{
+  def "" # posfix: ISRR_db<op1, asmstr, RC1, RC2>;
+  def _U # posfix: ISRR_db<op2, asmstr # ".u", RC1, RC2>;
+}
+
+defm DVSTEP : mI_U_SRR_sds2<0x32, 0xB2, "dvstep", "v110", RE, RD>, NsRequires<[HasV110]>;
+defm DVSTEP : mI_U_RRR_EEdb<0x2B, 0x09, 0x2B, 0x0A, "dvstep", "v110">, NsRequires<[HasV110]>;
+defm DVSTEP : mI_U_RRR_EEdb<0x6B, 0x0F, 0x6B, 0x0E, "dvstep">, Requires<[HasV120_UP]>;
+
+def ENABLE_sys   : ISYS_0<0x0D, 0x0C, "enable">;
+
+multiclass mIB_H_W<bits<8> brr1, bits<8> brr2,
+                   bits<8> hrr1, bits<8> hrr2,
+                   bits<8> wrr1, bits<8> wrr2,
+                   string asmstr>
+        :  mIB_H<brr1, brr2, hrr1, hrr2, asmstr>{
+  def _W_rr : IRR_dab<wrr1, wrr2, asmstr # ".w">;
+}
+
+defm EQ    : mIRR_RC<0x0B, 0x10, 0x8B, 0x10, "eq">
+           , mIB_H_W<0x0B, 0x50, 0x0B, 0x70, 0x0B, 0x90, "eq">;
+def EQ_src : ISRC_D15dC<0xBA, "eq">;
+def EQ_srr : ISRR_D15db<0x3A, "eq">;
+def EQ_A_rr: IRR_dab<0x01, 0x40, "eq.a", RD, RA, RA>;
+
+defm EQANY_B : mIRR_RC<0x0B, 0x56, 0x8B, 0x56, "eqany.b">;
+defm EQANY_H : mIRR_RC<0x0B, 0x76, 0x8B, 0x76, "eqany.h">;
+
+def EQZ_A_rr : IRR_a<0x01, 0x48, "eqz.a", RD, RA>;
+
+def EXTR_rrpw : RRPW<0x37, 0x02, (outs RD:$d), (ins RD:$s1, RD:$s2, i32imm:$pos, i32imm:$width),
+                    "extr $d, $s1, $pos, $width", []>;
+def EXTR_rrrr : IRRRR_ad<0x17, 0x02, "extr", RE>;
+def EXTR_rrrw : IRRRW_cadw<0x57, 0x02, "extr">;
+
+def EXTR_U_rrpw : RRPW<0x37, 0x03, (outs RD:$d), (ins RD:$s1, RD:$s2, i32imm:$pos, i32imm:$width),
+                      "extr.u $d, $s1, $pos, $width", []>;
+def EXTR_U_rrrr : IRRRR_ad<0x17, 0x03, "extr.u", RE>;
+def EXTR_U_rrrw : IRRRW_cadw<0x57, 0x03, "extr.u">;
+
+def FCALL_b  : IB<0x61, "fcall">, Requires<[HasV160_UP]>;
+def FCALLA_b : IB<0xE1, "fcalla">, Requires<[HasV160_UP]>;
+def FCALLA_i : IRR_R1<0x2D, 0x01, "fcalli", RA>, Requires<[HasV160_UP]>;
+
+def FRET_sr : ISR_0<0x00, 0x07, "fret">, Requires<[HasV160_UP]>;
+def FRET_sys : ISYS_0<0x0D, 0x03, "fret">, Requires<[HasV160_UP]>;
+
+multiclass mI_U__RR_RC<bits<8> op1, bits<8> op2, bits<8> op3, bits<7> op4,
+                      bits<8> uop1, bits<8> uop2, bits<8> uop3, bits<7> uop4,
+                      string asmstr> {
+  defm ""  : mIRR_RC<op1, op2, op3, op4, asmstr>;
+  defm _U  : mIRR_RC<uop1, uop2, uop3, uop4, asmstr # ".u">;
+}
+
+defm GE : mI_U__RR_RC<0x0B, 0x14, 0x8B, 0x14,
+                     0x0B, 0x15, 0x8B, 0x15, "ge">;
+def GE_A_rr : IRR_dab<0x01, 0x43, "ge.a", RD, RA, RA>;
+
+def IMASK_rcpw : RCPW<0xB7, 0x01, (outs RE:$d), (ins RD:$s1, i32imm:$const4, i32imm:$pos, i32imm:$width),
+                      "imask $d, $const4, $pos, $width", []>;
+def IMASK_rcrw : RCRW<0xD7, 0x01, (outs RE:$d), (ins RD:$s1, RD:$s3, i32imm:$const4, i32imm:$width),
+                      "imask $d, $const4, $s3, $width", []>;
+def IMASK_rrpw : RRPW<0x37, 0x01, (outs RE:$d), (ins RD:$s1, RD:$s2, i32imm:$pos, i32imm:$width),
+                      "imask $d, $s2, $pos, $width", []>;
+def IMASK_rrrw : IRRRW_cEbdw<0x57, 0x01, "imask">;
+
+def INS_T  : IBIT<0x67, 0x00, "ins.t">;
+def INSN_T : IBIT<0x67, 0x01, "insn.t">;
+
+def INSERT_rcpw : RCPW<0xB7, 0x00,  (outs RD:$d), (ins RD:$s1, i32imm:$const4, i32imm:$pos, i32imm:$width),
+                      "insert $d, $s1, $const4, $pos, $width", []>;
+def INSERT_rcrr : RCRR<0x97, 0x00, (outs RD:$d), (ins RD:$s1, i32imm:$const4, RE:$s3),
+                      "insert $d, $s1, $const4, $s3", []>;
+def INSERT_rcrw : RCRW<0xD7, 0x00, (outs RD:$d), (ins RD:$s1, RD:$s3, i32imm:$const4, i32imm:$width),
+                        "insert $d, $s1, $const4, $s3, $width", []>;
+def INSERT_rrpw : RRPW<0x37, 0x00, (outs RD:$d), (ins RD:$s1, RD:$s2, i32imm:$pos, i32imm:$width),
+                      "insert $d, $s1, $s2, $pos, $width", []>;
+def INSERT_rrrr : RRRW<0x17, 0x00, (outs RD:$d), (ins RD:$s1, RD:$s2, RE:$s3),
+                      "insert $d, $s1, $s2, $s3", []>;
+def INSERT_rrrw : IRRRW_cabdw<0x57, 0x00, "insert">;
+
+def ISYNC_sys : ISYS_0<0x0D, 0x13, "isync">;
+
+defm IXMAX : mI_U_RRR_EEdb<0x6B, 0x0A, 0x6B, 0x0B, "ixmax">, Requires<[HasV130_UP]>;
+defm IXMIN : mI_U_RRR_EEdb<0x6B, 0x08, 0x6B, 0x09, "ixmin">, Requires<[HasV130_UP]>;
+
+def J_b  : IB<0x1D, "j">;
+def J_sb_v110 : ISB<0x5C, "j">, NsRequires<[HasV110]>;
+def J_sb : ISB<0x3C, "j">, Requires<[HasV120_UP]>;
+def JA_b : IB<0x9D, "ja">;
+
+// disp15
+class IBRR_0<bits<8> op1, bits<1> op2, string asmstr>
+    : BRR<op1, op2, (outs), (ins disp15imm:$disp15), asmstr # " $disp15", []>;
+// A[a], disp15
+class IBRR_1<bits<8> op1, bits<1> op2, string asmstr>
+    : BRR<op1, op2, (outs), (ins RA:$s1, disp15imm:$disp15), asmstr # " $s1, $disp15", []>;
+// D[a], D[b], disp15
+class IBRR<bits<8> op1, bits<1> op2, string asmstr, RegisterClass RC1=RD, RegisterClass RC2=RD>
+    : BRR<op1, op2, (outs), (ins RC1:$s1, RC2:$s2, disp15imm:$disp15),
+          asmstr # " $s1, $s2, $disp15", []>;
+
+
+class IBRC<bits<8> op1, bits<1> op2, string asmstr, Operand TypeC=u4imm>
+    : BRC<op1, op2, (outs), (ins RD:$s1, TypeC:$const4, disp15imm:$disp15),
+      !strconcat(asmstr, " $s1, $const4, $disp15"), []>;
+
+class ISBC<bits<8> op1, string asmstr>
+    : SBC<op1, (outs), (ins disp4imm:$disp4, s4imm:$const4),
+      !strconcat(asmstr, " %d15, $const4, $disp4"), []>;
+
+// D[15], D[b], disp4 (SBR)
+class ISBR_15b<bits<8> op1, string asmstr>
+    : SBR<op1, (outs), (ins RD:$s2, disp4imm:$disp4),
+      !strconcat(asmstr, " %d15, $s2, $disp4"), []>;
+// D[b], disp4 (SBR)
+class ISBR_b<bits<8> op1, string asmstr, RegisterClass RC2=RD>
+    : SBR<op1, (outs), (ins RC2:$s2, disp4imm:$disp4),
+      !strconcat(asmstr, " $s2, $disp4"), []>;
+
+// D[b](SBR)
+class ISBR<bits<8> op1, string asmstr, RegisterClass RC2=RD>
+    : SBR<op1, (outs), (ins RC2:$s2),
+      !strconcat(asmstr, " $s2"), []>;
+
+multiclass mIBRC_BRR<bits<8> c1, bits<1> c2, bits<8> r1, bits<1> r2, string asmstr, Operand TypeC=u4imm>{
+  def _brc : IBRC<c1, c2, asmstr, TypeC>;
+  def _brr : IBRR<r1, r2, asmstr>;
+}
+
+multiclass mI_JnEq_<bits<8> c1, bits<1> c2, bits<8> r1, bits<1> r2,
+                    bits<8> x1, bits<8> x2, bits<8> x3, bits<8> x4,
+                    bits<8> x5, bits<1> x6, bits<8> v1, bits<8> v2, string asmstr>{
+  defm "": mIBRC_BRR<c1, c2, r1, r2, asmstr, s4imm>;
+
+  def _sbr_v110 : ISBR_15b<v1, asmstr>, NsRequires<[HasV110]>;
+  def _sbc_v110 : ISBC<v2, asmstr>, NsRequires<[HasV110]>;
+
+  def _sbc1 : ISBC<x1, asmstr>, Requires<[HasV120_UP]>;
+  def _sbc2 : ISBC<x2, asmstr>, Requires<[HasV160_UP]>;
+  
+  if !eq(asmstr, "jne") then def _sbr1 : ISBR_15b<x3, asmstr>, Requires<[HasV120_UP]>;
+  if !eq(asmstr, "jeq") then def _sbr1 : ISBR_15b<x3, asmstr>, Requires<[HasV130_UP]>;
+
+  def _sbr2 : ISBR_15b<x4, asmstr>, Requires<[HasV160_UP]>;
+  def _A_brr: IBRR<x5, x6, asmstr # ".a", RA, RA>;
+}
+
+defm JEQ : mI_JnEq_<0xDF, 0x00, 0x5F, 0x00,
+                    0x1E, 0x9E, 0x3E, 0xBE,
+                    0x7D, 0x00, 0x1E, 0x6E, "jeq">; 
+
+defm JGE   : mIBRC_BRR<0xFF, 0x00, 0x7F, 0x00, "jge", s4imm>;
+defm JGE_U : mIBRC_BRR<0xFF, 0x01, 0x7F, 0x01, "jge.u">;
+
+def JGEZ_sbr_v110 : ISBR_b<0xFE, "jgez">, NsRequires<[HasV110]>;
+def JGEZ_sbr : ISBR_b<0xCE, "jgez">, Requires<[HasV120_UP]>;
+def JGTZ_sbr_v110 : ISBR_b<0x7E, "jgtz">, NsRequires<[HasV110]>;
+def JGTZ_sbr : ISBR_b<0x4E, "jgtz">, Requires<[HasV120_UP]>;
+
+def JI_sbr_v110 : ISBR<0x3C, "ji", RA>, NsRequires<[HasV110]>;
+def JI_rr_v110  : IRR_R1<0x2D, 0x03, "ji", RA>, NsRequires<[HasV110]>;
+def JI_rr : IRR_R1<0x2D, 0x03, "ji", RA>, Requires<[HasV120_UP]>;
+def JI_sr : SR<0xDC, 0x00, (outs), (ins RA:$s1), "ji $s1", []>, Requires<[HasV120_UP]>;
+
+def JL_b  : IB<0x5D, "jl">;
+def JLA_b : IB<0xDD, "jla">;
+
+def JLEZ_sbr_v110 : ISBR_b<0xBE, "jlez">, NsRequires<[HasV110]>;
+def JLEZ_sbr : ISBR_b<0x8E, "jlez">, Requires<[HasV120_UP]>;
+
+def JLI_rr_v110 : IRR_R1<0x2D, 0x02, "jli", RA>, NsRequires<[HasV110]>;
+def JLI_rr : IRR_R1<0x2D, 0x02, "jli", RA>, Requires<[HasV120_UP]>;
+
+defm JLT   : mIBRC_BRR<0xBF, 0x00, 0x3F, 0x00, "jlt">;
+defm JLT_U : mIBRC_BRR<0xBF, 0x01, 0x3F, 0x01, "jlt.u">;
+
+def JLTZ_sbr_v110 : ISBR_b<0x3E, "jltz">, NsRequires<[HasV110]>;
+def JLTZ_sbr : ISBR_b<0x0E, "jltz">, Requires<[HasV120_UP]>;
+
+defm JNE : mI_JnEq_<0xDF, 0x01, 0x5F, 0x01,
+                    0x5E, 0xDE, 0x7E, 0xFE,
+                    0x7D, 0x01, 0x9E, 0xEE, "jne">;
+
+defm JNED : mIBRC_BRR<0x9F, 0x01, 0x1F, 0x01, "jned">;
+defm JNEI : mIBRC_BRR<0x9F, 0x00, 0x1F, 0x00, "jnei">;
+
+multiclass mI_JnZ_<bits<8> sb, bits<8> sbr,
+                   bits<8> abrr1, bits<1> abrr2, bits<8> asbr,
+                   bits<7> brn1, bits<1> brn2, bits<8> sbrn,
+                   bits<8> sbv, bits<8> sbrv, bits<8> sbrnv,
+                   string asmstr> {
+  def _sb_v110  : ISB_D15D<sbv, asmstr>, NsRequires<[HasV110]>;
+  def _sbr_v110 : ISBR_b<sbrv, asmstr>, NsRequires<[HasV110]>;
+  def _T_sbrn_v110: SBRN<sbrnv, (outs), (ins i32imm:$n, disp4imm:$disp4), asmstr # ".t %d15, $n, $disp4", []>
+             , NsRequires<[HasV110]>;
+
+  def _sb  : ISB_D15D<sb, asmstr>, Requires<[HasV120_UP]>;
+  def _sbr : ISBR_b<sbr, asmstr>, Requires<[HasV120_UP]>;
+  def _A_brr : IBRR_1<abrr1, abrr2, asmstr # ".a">;
+  def _A_sbr : ISBR_b<asbr, asmstr # ".a", RA>;
+  def _T_brn : BRN<brn1, brn2, (outs), (ins RD:$s1, i32imm:$n, disp15imm:$disp15), asmstr # ".t $s1, $n, $disp15", []>;
+  def _T_sbrn: SBRN<sbrn, (outs), (ins i32imm:$n, disp4imm:$disp4), asmstr # ".t %d15, $n, $disp4", []>
+             , Requires<[HasV120_UP]>;
+}
+
+defm JNZ : mI_JnZ_<0xEE, 0xF6, 0xBD, 0x01, 0x7C, 0x6F, 0x01, 0xAE, 0xAE, 0xDE, 0x4E, "jnz">;
+defm JZ  : mI_JnZ_<0x6E, 0x76, 0xBD, 0x00, 0xBC, 0x6F, 0x00, 0x2E, 0x2E, 0x5E, 0x0E, "jz">;
+
+
+class IABS_off18<bits<8> op1, bits<2> op2, string asmstr> 
+    : ABS<op1, op2, (outs), (ins off18imm:$off18),
+      asmstr # " $off18", []>;
+class IABS_RO<bits<8> op1, bits<2> op2, string asmstr, RegisterClass dc> 
+    : ABS<op1, op2, (outs dc:$d), (ins off18imm:$off18),
+      asmstr # " $d, $off18", []>;
+class IABS_OR<bits<8> op1, bits<2> op2, string asmstr, RegisterClass s1c> 
+    : ABS<op1, op2, (outs), (ins s1c:$s1, off18imm:$off18),
+      asmstr # " $off18, $s1", []>;
+
+class IBOL_RAaO<bits<8> op1, string asmstr, RegisterClass RC> 
+    : BOL<op1, (outs RC:$s1), (ins RA:$s2, s16imm:$off16),
+      asmstr # " $s1, [$s2]$off16", []>;
+
+class IBOL_AbOR<bits<8> op1, string asmstr, RegisterClass RC> 
+    : BOL<op1, (outs RA:$s2), (ins RC:$s1, s16imm:$off16),
+      asmstr # " [$s2]$off16, $s1", []>;
+
+class ISLR<bits<8> op1, string asmstr, RegisterClass dc>
+    : SLR<op1, (outs dc:$d), (ins RA:$s2),
+      asmstr # " $d, [$s2]", []>;
+class ISLR_pos<bits<8> op1, string asmstr, RegisterClass dc>
+    : SLR<op1, (outs dc:$d), (ins RA:$s2),
+      asmstr # " $d, [${s2}+]", []>;
+
+class ISLRO<bits<8> op1, string asmstr, RegisterClass dc>
+    : SLRO<op1, (outs dc:$d), (ins u4imm:$off4),
+      asmstr # " $d, [%a15]$off4", []>;
+
+class ISRO_A15RO<bits<8> op1, string asmstr, RegisterClass s2c>
+    : SRO<op1, (outs), (ins s2c:$s2, u4imm:$off4),
+      asmstr # " %a15, [$s2]$off4", []>;
+
+class ISRO_ROA15<bits<8> op1, string asmstr, RegisterClass s2c>
+    : SRO<op1, (outs), (ins s2c:$s2, u4imm:$off4),
+      asmstr # " [$s2]$off4, %a15", []>;
+
+class ISRO_D15RO<bits<8> op1, string asmstr, RegisterClass s2c>
+    : SRO<op1, (outs), (ins s2c:$s2, u4imm:$off4),
+      asmstr # " %d15, [$s2]$off4", []>;
+
+class ISRO_ROD15<bits<8> op1, string asmstr, RegisterClass s2c>
+    : SRO<op1, (outs), (ins s2c:$s2, u4imm:$off4),
+      asmstr # " [$s2]$off4, %d15", []>;
+
+// A|D[a], A[b], off10 (BO) (Base + Short Offset Addressing Mode)
+class IBO_RAbso<bits<8> op1, bits<6> op2, string asmstr, RegisterClass dc> 
+    : BO<op1, op2, (outs dc:$d), (ins RA:$s2, s10imm:$off10),
+      asmstr # " $d, [$s2]$off10", []>;
+// A|D[a], P[b] (BO) (Bit Reverse Addressing Mode)
+class IBO_RPr<bits<8> op1, bits<6> op2, string asmstr, RegisterClass dc>
+    : BO<op1, op2, (outs dc:$d), (ins RP:$s2),
+      asmstr # " $d, [${s2}+r]", []>;
+// A|D[a], P[b], off10 (BO) (Circular Addressing Mode)
+class IBO_RPc<bits<8> op1, bits<6> op2, string asmstr, RegisterClass dc> 
+    : BO<op1, op2, (outs dc:$d), (ins RP:$s2, s10imm:$off10),
+      asmstr # " $d, [${s2}+c]$off10", []>;
+// A|D[a], A[b], off10 (BO)(Post-increment Addressing Mode)
+class IBO_RApos<bits<8> op1, bits<6> op2, string asmstr, RegisterClass dc>
+    : BO<op1, op2, (outs), (ins dc:$s1, RA:$s2, s10imm:$off10),
+      asmstr # " $s1, [${s2}+]$off10", []>;
+// A|D[a], A[b], off10 (BO) (Pre-increment Addressing Mode)
+class IBO_RApre<bits<8> op1, bits<6> op2, string asmstr, RegisterClass dc>
+    : BO<op1, op2, (outs), (ins dc:$s1, RA:$s2, s10imm:$off10),
+      asmstr # " $s1, [+${s2}]$off10", []>;
+
+
+multiclass mI_LD_<bits<8> abs1, bits<2> abs2,   ///_abs
+                    bits<8> prefix1, bits<8> prefix2,
+                    bits<6> bso2, ///_bso
+                    bits<6> pos_r, ///_pos|_r
+                    bits<6> pre_c, ///_pre|_c
+                    string asmstr, RegisterClass RC>{
+  def _abs     : IABS_RO<abs1, abs2, asmstr, RC>;
+  def _bo_bso  : IBO_RAbso<prefix1, bso2, asmstr, RC>;
+  def _bo_pos  : IBO_RApos<prefix1, pos_r, asmstr, RC>;
+  def _bo_pre  : IBO_RApre<prefix1, pre_c, asmstr, RC>;
+  def _bo_r    : IBO_RPr<prefix2, pos_r, asmstr, RC>;
+  def _bo_c    : IBO_RPc<prefix2, pre_c, asmstr, RC>;
+}
+
+multiclass mI_LD_2_<bits<8> slr, bits<8> slrp, bits<8> slro, bits<8> sro,
+                    string asmstr, RegisterClass RC, string posfix="">{
+  def _slr # posfix: ISLR<slr, asmstr, RC>;
+  def _slr_post # posfix: ISLR_pos<slrp, asmstr, RC>;
+  def _slro # posfix: ISLRO<slro, asmstr, RC>;
+  if !eq(RC, RD) then def _sro # posfix: ISRO_D15RO<sro, asmstr, RA>;
+  if !eq(RC, RA) then def _sro # posfix: ISRO_A15RO<sro, asmstr, RA>;
+}
+
+defm LD_A: mI_LD_<0x85, 0x02, 0x09, 0x29, 0x26, 0x06, 0x16, "ld.a", RA>;
+defm LD_A: mI_LD_2_<0xB8, 0x64, 0x0C, 0x28, "ld.a", RA, "_v110">, NsRequires<[HasV110]>;
+defm LD_A: mI_LD_2_<0xD4, 0xC4, 0xC8, 0xCC, "ld.a", RA>, Requires<[HasV120_UP]>;
+def LD_A_bol : IBOL_RAaO<0x99, "ld.a", RA>;
+def LD_A_sc  : ISC_A15A10C<0xD8, "ld.a">, Requires<[HasV120_UP]>;
+
+defm LD_B: mI_LD_2_<0x98, 0x44, 0x34, 0x08, "ld.b", RD, "_v110">, NsRequires<[HasV110]>;
+defm LD_B: mI_LD_<0x05, 0x00, 0x09, 0x29, 0x20, 0x00, 0x10,"ld.b", RD>;
+def LD_B_bol : IBOL_RAaO<0x79, "ld.b", RD>, Requires<[HasV160_UP]>;
+
+defm LD_BU: mI_LD_<0x05, 0x01, 0x09, 0x29, 0x21, 0x01, 0x11, "ld.bu", RD>;
+defm LD_BU: mI_LD_2_<0x58, 0xC4, 0xB4, 0x88, "ld.bu", RD, "_v110">, NsRequires<[HasV110]>;
+defm LD_BU: mI_LD_2_<0x14, 0x04, 0x08, 0x0C, "ld.bu", RD>, Requires<[HasV120_UP]>;
+def LD_BU_bol : IBOL_RAaO<0x39, "ld.bu", RD>, Requires<[HasV160_UP]>;
+
+defm LD_D  : mI_LD_<0x85, 0x01, 0x09, 0x29, 0x25, 0x05, 0x15, "ld.d", RE>;
+defm LD_DA : mI_LD_<0x85, 0x03, 0x09, 0x29, 0x27, 0x07, 0x17, "ld.da", RP>;
+
+defm LD_H  : mI_LD_<0x05, 0x02, 0x09, 0x29, 0x22, 0x02, 0x12, "ld.h", RD>;
+defm LD_H: mI_LD_2_<0xD8, 0x24, 0x74, 0x48, "ld.h", RD, "_v110">, NsRequires<[HasV110]>;
+defm LD_H: mI_LD_2_<0x94, 0x84, 0x88, 0x8C, "ld.h", RD>, Requires<[HasV120_UP]>;
+def LD_H_bol : IBOL_RAaO<0xC9, "ld.h", RD>, Requires<[HasV160_UP]>;
+
+defm LD_HU  : mI_LD_<0x05, 0x03, 0x09, 0x29, 0x23, 0x03, 0x13, "ld.hu", RD>;
+def LD_HU_bol : IBOL_RAaO<0xB9, "ld.hu", RD>, Requires<[HasV160_UP]>;
+
+defm LD_Q  : mI_LD_<0x45, 0x00, 0x09, 0x29, 0x28, 0x08, 0x18, "ld.q", RD>;
+
+defm LD_W: mI_LD_<0x85, 0x00, 0x09, 0x29, 0x24, 0x04, 0x14, "ld.w", RD>;
+defm LD_W: mI_LD_2_<0x38, 0xA4, 0xF4, 0xC8, "ld.w", RD, "_v110">, NsRequires<[HasV110]>;
+defm LD_W: mI_LD_2_<0x54, 0x44, 0x48, 0x4C, "ld.w", RD>, Requires<[HasV120_UP]>;
+def LD_W_bol : IBOL_RAaO<0x19, "ld.w", RD>;
+def LD_W_sc  : ISC_D15A10C<0x58, "ld.w">, Requires<[HasV120_UP]>;
+
+
+def LDLCX_abs    : IABS_off18<0x15, 0x02, "ldlcx">;
+def LDLCX_bo_bso : IBO_bso<0x49, 0x24, "ldlcx">;
+
+def LDMST_abs : IABS_OR<0xE5, 0x01, "ldmst", RE>;
+defm LDMST    : mIBO_Ea<0x49, 0x21, 0x69, 0x01, 0x69, 0x11, 0x49, 0x01, 0x49, 0x11, "ldmst">;
+
+def LDUCX_abs    : IABS_off18<0x15, 0x03, "lducx">;
+def LDUCX_bo_bso : IBO_bso<0x49, 0x25, "lducx">;
+
+def LEA_abs    : IABS_RO<0xC5, 0x00, "lea", RA>;
+def LEA_bo_bso : IBO_RAbso<0x49, 0x28, "lea", RA>;
+def LEA_bol    : IBOL_RAaO<0xD9, "lea", RA>;
+
+def LHA_abs    : IABS_RO<0xC5, 0x01, "lha", RA>, Requires<[HasV162_UP]>;
+
+def LOOP_brr : IBRR_1<0xFD, 0x00, "loop">;
+
+def LOOP_sbr : SBR<0xFC, (outs), (ins RA:$s2, oext4imm:$disp4),
+                   "loop $s2, $disp4", []>;
+def LOOPU_brr : IBRR_0<0xFD, 0x01, "loopu">, Requires<[HasV120_UP]>;
+
+defm LT : mIRR_RC<0x0B, 0x12, 0x8B, 0x12, "lt">;
+defm LT : mISRR_SRC<0x7A, 0xFA, "lt", RD, RD, s4imm>;
+
+defm LT_U : mIRR_RC<0x0B, 0x13, 0x8B, 0x13, "lt.u">;
+defm LT_U : mISRR_SRC<0x06, 0x86, "lt.u", RD, RD, u4imm, "v110">, NsRequires<[HasV110]>;
+def LT_A_rr : IRR_dab<0x01, 0x42, "lt.a", RD, RA, RA>;
+
+multiclass mIU__RR_ab<bits<8> op1, bits<8> op2,
+                      bits<8> uop1, bits<8> uop2,
+                      string asmstr> {
+  def ""  : IRR_dab<op1, op2, asmstr>;
+  def U   : IRR_dab<uop1, uop2, asmstr # "u">;
+}
+
+defm LT_B : mIU__RR_ab<0x0B, 0x52, 0x0B, 0x53, "lt.b">;
+defm LT_H : mIU__RR_ab<0x0B, 0x72, 0x0B, 0x73, "lt.h">;
+defm LT_W : mIU__RR_ab<0x0B, 0x92, 0x0B, 0x93, "lt.w">;
+
+class IRRR1_label<bits<8> op1, bits<6> op2, string asmstr, RegisterClass RC, string label>
+    : RRR1<op1, op2, (outs RC:$d), (ins RD:$s1, RD:$s2, RC:$s3, u2imm:$n),
+           asmstr # " $d, $s3, $s1, ${s2}" # label # ", $n", []>;
+class IRRR1_label2<bits<8> op1, bits<6> op2, string asmstr, RegisterClass RC, string label1, string label2>
+    : RRR1<op1, op2, (outs RC:$d), (ins RD:$s1, RD:$s2, RC:$s3, u2imm:$n),
+           asmstr # " $d, $s3, ${s1}" # label1 # ", ${s2}" # label2 # ", $n", []>;
+class IRRR1_n<bits<8> op1, bits<6> op2, string asmstr, RegisterClass RC=RD>
+    : RRR1<op1, op2, (outs RC:$d), (ins RD:$s1, RD:$s2, RC:$s3, u2imm:$n),
+           asmstr # " $d, $s3, $s1, $s2, $n", []>;
+class IRRR1<bits<8> op1, bits<6> op2, string asmstr, RegisterClass RC=RD>
+    : RRR1<op1, op2, (outs RC:$d), (ins RD:$s1, RD:$s2, RC:$s3, u2imm:$n),
+           asmstr # " $d, $s3, $s1, $s2", []>;
+
+class IRRR2<bits<8> op1, bits<8> op2, string asmstr, RegisterClass RC>
+    : RRR2<op1, op2, (outs RC:$d), (ins RD:$s1, RD:$s2, RC:$s3),
+           asmstr # " $d, $s3, $s1, $s2", []>;
+
+multiclass mIRRR2<bits<8> op1, bits<8> op2, bits<8> op3, bits<8> op4, string asmstr>{
+  def _rrr2   : IRRR2<op1, op2, asmstr, RD>;
+  def _rrr2_e : IRRR2<op3, op4, asmstr, RE>, Requires<[HasV120_UP]>;
+}
+
+multiclass mIRCR_RRR2<bits<8> op_rcr1, bits<3> op_rcr2, bits<8> op_rrr21, bits<8> op_rrr22,
+                      string asmstr, string posfix="",
+                      Operand Type3=s9imm, RegisterClass RC1=RE, RegisterClass RC2=RD>{
+  def _rcr#posfix: IRCR<op_rcr1, op_rcr2, asmstr, RC1, RC2, RC1, Type3>;
+  def _rrr2#posfix: IRRR2<op_rrr21, op_rrr22, asmstr, RC1>;
+}
+
+multiclass mIRRR1_LU2<bits<8> prefix, bits<6> ll, bits<6> lu,
+                      bits<6> ul, bits<6> uu,
+                      string asmstr, RegisterClass RC>{
+  def _rrr1_LL : IRRR1_label<prefix, ll, asmstr, RC, "ll">;
+  def _rrr1_LU : IRRR1_label<prefix, lu, asmstr, RC, "lu">;
+  def _rrr1_UL : IRRR1_label<prefix, ul, asmstr, RC, "ul">;
+  def _rrr1_UU : IRRR1_label<prefix, uu, asmstr, RC, "uu">;
+}
+multiclass mI_MADD_H_MSUB_H_<bits<8> pre, bits<6> ll, bits<6> lu,
+                       bits<6> ul, bits<6> uu, string asmstr, bit hasv110=true, RegisterClass RC=RE>{
+  if hasv110 then {
+      if !or(!eq("maddm.h", asmstr), !eq("msubm.h", asmstr)) then
+        def _rrr1_v110 : IRRR1<pre, ul, asmstr, RC>, NsRequires<[HasV110]>;
+      else
+        def _rrr1_v110 : IRRR1_n<pre, ul, asmstr, RC>, NsRequires<[HasV110]>;
+  }
+  defm "" : mIRRR1_LU2<pre, ll, lu, ul, uu, asmstr, RC>, Requires<[HasV120_UP]>;
+}
+
+multiclass mI_MADDRsH_MSUBRsH_<bits<8> pre2, bits<6> ul2, bits<8> pre1, bits<6> ll, bits<6> lu,
+                      bits<6> ul, bits<6> uu, string asmstr>{ 
+  def _rrr1_v110: RRR1<pre2, ul2, (outs RD:$d), (ins RD:$s1, RD:$s2, RE:$s3, u2imm:$n),
+                       asmstr # " $d, $s3, $s1, $s2, $n", []>, NsRequires<[HasV110]>;
+  def _rrr1_UL_2: RRR1<pre2, ul2, (outs RD:$d), (ins RD:$s1, RD:$s2, RE:$s3, u2imm:$n),
+                       asmstr # " $d, $s3, $s1, ${s2}ul, $n", []>, Requires<[HasV120_UP]>;
+  defm "" : mIRRR1_LU2<pre1, ll, lu, ul, uu, asmstr, RD>, Requires<[HasV120_UP]>;
+}
+
+multiclass mI_MADDsQ_MSUBsQ_<bits<8> prefix, bits<6> op, bits<6> eop, bits<6> l, bits<6> el, bits<6> u, bits<6> eu,
+                             bits<6> ll, bits<6> ell, bits<6> uu, bits<6> euu, string asmstr>{
+  def _rrr1_UU2_v110: IRRR1_n<prefix, uu, asmstr, RD>, NsRequires<[HasV110]>;
+  def _rrr1: IRRR1_n<prefix, op, asmstr, RD>, Requires<[HasV120_UP]>;
+  def _rrr1_e: IRRR1_n<prefix, eop, asmstr, RE>, Requires<[HasV120_UP]>;
+  def _rrr1_L: IRRR1_label<prefix, l, asmstr, RD, "l">, Requires<[HasV120_UP]>;
+  def _rrr1_e_L: IRRR1_label<prefix, el, asmstr, RE, "l">, Requires<[HasV120_UP]>;
+  def _rrr1_U: IRRR1_label<prefix, u, asmstr, RD, "u">, Requires<[HasV120_UP]>;
+  def _rrr1_e_U: IRRR1_label<prefix, eu, asmstr, RE, "u">, Requires<[HasV120_UP]>;
+  def _rrr1_L_L: IRRR1_label2<prefix, ll, asmstr, RD, "l", "l">, Requires<[HasV120_UP]>;
+  def _rrr1_e_L_L: IRRR1_label2<prefix, ell, asmstr, RE, "l", "l">, Requires<[HasV120_UP]>;
+  def _rrr1_U_U: IRRR1_label2<prefix, uu, asmstr, RD, "u", "u">, Requires<[HasV120_UP]>;
+  def _rrr1_e_U_U: IRRR1_label2<prefix, euu, asmstr, RE, "u", "u">, Requires<[HasV120_UP]>;
+}
+
+defm MADD : mIRCR<0x13, 0x01, 0x13, 0x03, "madd">
+          , mIRRR2<0x03, 0x0A, 0x03, 0x6A, "madd">;
+
+defm MADDS : mIRCR<0x13, 0x05, 0x13, 0x07, "madds">
+           , mIRRR2<0x03, 0x8A, 0x03, 0xEA, "madds">;
+
+defm MADD_H  : mI_MADD_H_MSUB_H_<0x83, 0x1A, 0x19, 0x18, 0x1B, "madd.h">;
+defm MADDS_H : mI_MADD_H_MSUB_H_<0x83, 0x3A, 0x39, 0x38, 0x3B, "madds.h">;
+
+defm MADD_Q  : mI_MADDsQ_MSUBsQ_<0x43, 0x02, 0x1B, 0x01, 0x19, 0x00, 0x18, 0x05, 0x1D, 0x04, 0x1C, "madd.q">;
+defm MADDS_Q : mI_MADDsQ_MSUBsQ_<0x43, 0x22, 0x3B, 0x21, 0x39, 0x20, 0x38, 0x25, 0x3D, 0x24, 0x3C, "madds.q">;
+
+defm MADD_U: mIRCR_RRR2<0x13, 0x02, 0x03, 0x68, "madd.u", "", u9imm>, Requires<[HasV120_UP]>;
+
+defm MADDS_U: mIRCR<0x13, 0x04, 0x13, 0x06, "madds.u">
+             , mIRRR2<0x03, 0x88, 0x03, 0xE8, "madds.u">;
+
+defm MADDM: mIRCR_RRR2<0x13, 0x03, 0x03, 0x6A, "maddm", "_v110">, NsRequires<[HasV110]>;
+def MADDM_Q_rrr1_v110: IRRR1<0x43, 0x70, "maddm.q", RE>, NsRequires<[HasV110]>;
+defm MADDM_U: mIRCR_RRR2<0x13, 0x02, 0x03, 0x68, "maddm.u", "_v110", u9imm>, NsRequires<[HasV110]>;
+
+defm MADDM_H  : mI_MADD_H_MSUB_H_<0x83, 0x1E, 0x1D, 0x1C, 0x1F, "maddm.h">;
+
+defm MADDMS: mIRCR_RRR2<0x13, 0x07, 0x03, 0xEA, "maddms", "_v110">, NsRequires<[HasV110]>;
+defm MADDMS_U: mIRCR_RRR2<0x13, 0x06, 0x03, 0xE8, "maddms.u", "_v110", u9imm>, NsRequires<[HasV110]>;
+defm MADDMS_H : mI_MADD_H_MSUB_H_<0x83, 0x3E, 0x3D, 0x3C, 0x3F, "maddms.h", false>;
+
+defm MADDR_H  : mI_MADDRsH_MSUBRsH_<0x43, 0x1E, 0x83, 0x0E, 0x0D, 0x0C, 0x0F, "maddr.h">;
+defm MADDRS_H : mI_MADDRsH_MSUBRsH_<0x43, 0x3E, 0x83, 0x2E, 0x2D, 0x2C, 0x2F, "maddrs.h">;
+
+multiclass mI_MADDRsQ_MSUBRsQ_<bits<8> prefix, bits<6> op, bits<6> eop, string asmstr> {
+  def _rrr1_L_L : IRRR1_label2<prefix, op, asmstr, RD, "l", "l">, Requires<[HasV120_UP]>;
+  def _rrr1_U_U : IRRR1_label2<prefix, eop, asmstr, RD, "u", "u">, Requires<[HasV120_UP]>;
+  def _rrr1_v110: IRRR1_n<prefix, eop, asmstr, RD>, NsRequires<[HasV110]>;
+}
+
+defm MADDR_Q : mI_MADDRsQ_MSUBRsQ_<0x43, 0x07, 0x06, "maddr.q">;
+defm MADDRS_Q: mI_MADDRsQ_MSUBRsQ_<0x43, 0x27, 0x26, "maddrs.q">;
+
+defm MADDSU_H   : mI_MADD_H_MSUB_H_<0xC3, 0x1A, 0x19, 0x18, 0x1B, "maddsu.h", false>;
+defm MADDSUS_H  : mI_MADD_H_MSUB_H_<0xC3, 0x3A, 0x39, 0x38, 0x3B, "maddsus.h", false>;
+defm MADDSUM_H  : mI_MADD_H_MSUB_H_<0xC3, 0x1E, 0x1D, 0x1C, 0x1F, "maddsum.h", false>;
+defm MADDSUMS_H : mI_MADD_H_MSUB_H_<0xC3, 0x3E, 0x3D, 0x3C, 0x3F, "maddsums.h", false>;
+defm MADDSUR_H  : mI_MADD_H_MSUB_H_<0xC3, 0x0E, 0x0D, 0x0C, 0x0F, "maddsur.h", false, RD>;
+defm MADDSURS_H : mI_MADD_H_MSUB_H_<0xC3, 0x2E, 0x2D, 0x2C, 0x2F, "maddsurs.h", false, RD>;
+
+defm MAX   : mIRR_RC<0x0B, 0x1A, 0x8B, 0x1A, "max">;
+defm MAX_U : mIRR_RC<0x0B, 0x1B, 0x8B, 0x1B, "max.u">;
+
+defm MAX_B : mIU__RR_ab<0x0B, 0x5A, 0x0B, 0x5B, "max.b">;
+defm MAX_H : mIU__RR_ab<0x0B, 0x7A, 0x0B, 0x7B, "max.h">;
+
+defm MIN   : mIRR_RC<0x0B, 0x18, 0x8B, 0x18, "min">;
+defm MIN_U : mIRR_RC<0x0B, 0x19, 0x8B, 0x19, "min.u">;
+
+defm MIN_B : mIU__RR_ab<0x0B, 0x58, 0x0B, 0x59, "min.b">;
+defm MIN_H : mIU__RR_ab<0x0B, 0x78, 0x0B, 0x79, "min.h">;
+
+class IRLC_1<bits<8> op1, string asmstr, RegisterClass RC=RD, Operand TypeC=u16imm>
+    : RLC<op1, (outs RC:$d), (ins TypeC:$const16),
+      asmstr # " $d, $const16", []>;
+
+class ISRC_1<bits<8> op1, string asmstr, RegisterClass RC=RD> 
+    : SRC<op1, (outs RC:$d), (ins s4imm:$const4),
+      asmstr # " $d, $const4", []>;
+
+def MOV_rlc  : IRLC_1<0x3B, "mov", RD, s16imm>;
+def MOV_rlc_e: IRLC_1<0xFB, "mov", RE>, Requires<[HasV160_UP]>;
+
+def MOV_rr  : IRR_b<0x0B, 0x1F, "mov">;
+def MOV_rr_e: IRR_b<0x0B, 0x80, "mov", RE>, Requires<[HasV160_UP]>;
+def MOV_rr_eab : IRR_dab<0x0B, 0x81, "mov", RE>, Requires<[HasV160_UP]>;
+
+def MOV_sc_v110: ISC_D15C<0xC6, "mov">, NsRequires<[HasV110]>;
+def MOV_sc : ISC_D15C<0xDA, "mov">, Requires<[HasV120_UP]>;
+
+def MOV_src: ISRC_dC<0x82, "mov">;
+def MOV_src_e: ISRC_1<0xD2, "mov", RE>, Requires<[HasV160_UP]>;
+
+def MOV_srr  : ISRR_db<0x02, "mov">;
+
+multiclass mI_MOV_srr<bits<8> srr110,bits<8> srr1, string asmstr, RegisterClass RCd=RA, RegisterClass RC1=RD>{
+  def _srr_v110: ISRR_db<srr110, asmstr, RCd, RC1>, NsRequires<[HasV110]>;
+  def _srr: ISRR_db<srr1, asmstr, RCd, RC1>, Requires<[HasV120_UP]>;
+}
+
+multiclass mI_MOVA_<bits<8> rr1, bits<8> rr2, bits<8> src1, bits<8> srr110,bits<8> srr1, string asmstr> {
+  def _rr : IRR_b<rr1, rr2, asmstr, RA>;
+  def _src: ISRC_dC<src1, asmstr, RA, u4imm>, Requires<[HasV120_UP]>;
+  defm "" : mI_MOV_srr<srr110, srr1, asmstr>;
+}
+
+defm MOV_A : mI_MOVA_<0x01, 0x63, 0xA0, 0x30, 0x60, "mov.a">;
+
+def MOV_AA_rr : IRR_b<0x01, 0x00, "mov.aa", RA, RA>;
+defm MOV_AA_srr: mI_MOV_srr<0x80, 0x40, "mov.aa", RA, RA>;
+
+def MOV_D_rr : IRR_b<0x01, 0x4C, "mov.d", RD, RA>;
+defm MOV_D_srr : mI_MOV_srr<0x20, 0x80, "mov.d", RD, RA>;
+
+def MOV_U_rlc  : IRLC_1<0xBB, "mov.u">;
+def MOVH_rlc   : IRLC_1<0x7B, "movh", RD, u16imm>;
+def MOVH_A_rlc : IRLC_1<0x91, "movh.a", RA, u16imm>;
+def MOVZ_A_sr: ISR_1<0x00, 0x01, "movz.a", RA>, NsRequires<[HasV110]>;
+
+defm MSUB : mIRCR<0x33, 0x01, 0x33, 0x03, "msub">
+          , mIRRR2<0x23, 0x0A, 0x23, 0x6A, "msub">;
+defm MSUBS: mIRCR<0x33, 0x05, 0x33, 0x07, "msubs">
+          , mIRRR2<0x23, 0x8A, 0x23, 0xEA, "msubs">;
+
+defm MSUB_H  : mI_MADD_H_MSUB_H_<0xA3, 0x1A, 0x19, 0x18, 0x1B, "msub.h">;
+defm MSUBS_H : mI_MADD_H_MSUB_H_<0xA3, 0x3A, 0x39, 0x38, 0x3B, "msubs.h">;
+defm MSUB_Q  : mI_MADDsQ_MSUBsQ_<0x63, 0x02, 0x1B, 0x01, 0x19, 0x00, 0x18, 0x05, 0x1D, 0x04, 0x1C, "msub.q">;
+defm MSUBS_Q : mI_MADDsQ_MSUBsQ_<0x63, 0x22, 0x3B, 0x21, 0x39, 0x20, 0x38, 0x25, 0x3D, 0x24, 0x3C, "msubs.q">;
+
+defm MSUB_U: mIRCR_RRR2<0x33, 0x02, 0x23, 0x68, "msub.u", "", u9imm>, Requires<[HasV120_UP]>;
+defm MSUBS_U : mIRCR<0x33, 0x04, 0x33, 0x06, "msubs.u">
+             , mIRRR2<0x23, 0x88, 0x23, 0xE8, "msubs.u">;
+
+defm MSUBAD_H   : mI_MADD_H_MSUB_H_<0xE3, 0x1A, 0x19, 0x18, 0x1B, "msubad.h", false>;
+defm MSUBADS_H  : mI_MADD_H_MSUB_H_<0xE3, 0x3A, 0x39, 0x38, 0x3B, "msubads.h", false>;
+defm MSUBADM_H  : mI_MADD_H_MSUB_H_<0xE3, 0x1E, 0x1D, 0x1C, 0x1F, "msubadm.h", false>;
+defm MSUBADMS_H : mI_MADD_H_MSUB_H_<0xE3, 0x3E, 0x3D, 0x3C, 0x3F, "msubadms.h", false>;
+defm MSUBADR_H  : mI_MADD_H_MSUB_H_<0xE3, 0x0E, 0x0D, 0x0C, 0x0F, "msubadr.h", true, RD>;
+defm MSUBADRS_H : mI_MADD_H_MSUB_H_<0xE3, 0x2E, 0x2D, 0x2C, 0x2F, "msubadrs.h", true, RD>;
+
+defm MSUBM: mIRCR_RRR2<0x33, 0x03, 0x23, 0x6A, "msubm", "v110">, NsRequires<[HasV110]>;
+def  MSUBM_Q_rrr1_v110: IRRR1<0x63, 0x1C, "msubm.q", RE>, NsRequires<[HasV110]>;
+defm MSUBM_U: mIRCR_RRR2<0x33, 0x02, 0x23, 0x68, "msubm.u", "v110">, NsRequires<[HasV110]>;
+defm MSUBMS: mIRCR_RRR2<0x33, 0x07, 0x23, 0xEA, "msubms", "v110">, NsRequires<[HasV110]>;
+defm MSUBMS_U: mIRCR_RRR2<0x33, 0x06, 0x23, 0xE8, "msubms.u", "v110">, NsRequires<[HasV110]>;
+
+defm MSUBM_H    : mI_MADD_H_MSUB_H_<0xA3, 0x1E, 0x1D, 0x1C, 0x1F, "msubm.h">;
+defm MSUBMS_H   : mI_MADD_H_MSUB_H_<0xA3, 0x3E, 0x3D, 0x3C, 0x3F, "msubms.h", false>;
+
+defm MSUBR_H : mI_MADDRsH_MSUBRsH_<0x63, 0x1E, 0xA3, 0x0E, 0x0D, 0x0C, 0x0F, "msubr.h">;
+defm MSUBRS_H: mI_MADDRsH_MSUBRsH_<0x63, 0x3E, 0xA3, 0x2E, 0x2D, 0x2C, 0x2F, "msubrs.h">;
+
+defm MSUBR_Q : mI_MADDRsQ_MSUBRsQ_<0x63, 0x07, 0x06, "msubr.q">;
+defm MSUBRS_Q: mI_MADDRsQ_MSUBRsQ_<0x63, 0x27, 0x26, "msubrs.q">;
+
+class IRLC_CR<bits<8> op1, string asmstr, RegisterClass RC=RD>
+    : RLC<op1, (outs), (ins s16imm:$const16, RC:$d),
+          asmstr # " $const16, $d", []>;
+
+def MTCR_rlc : IRLC_CR<0xCD, "mtcr">;
+def MFCR_rlc : IRLC_1 <0x4D, "mfcr">;
+
+class IRR2<bits<8> op1, bits<12> op2, string asmstr,
+           RegisterClass RCd=RD, RegisterClass RCa=RD, RegisterClass RCb=RD>
+    : RR2<op1, op2, (outs RCd:$d), (ins RCa:$s1, RCb:$s2), asmstr # " $d, $s1, $s2", []>;
+
+def MUL_rc  : RC<0x53, 0x01, (outs RD:$d), (ins RD:$s1, s9imm:$const9),
+                "mul $d, $s1, $const9", []>;
+def MUL_rc_e: RC<0x53, 0x03, (outs RE:$d), (ins RD:$s1, s9imm:$const9),
+                "mul $d, $s1, $const9", []>
+            , Requires<[HasV120_UP]>;
+
+def MUL_rr2  : IRR2<0x73, 0x0A, "mul">, Requires<[HasV120_UP]>;
+def MUL_rr2_e: IRR2<0x73, 0x6A, "mul", RE>, Requires<[HasV120_UP]>;
+
+def MUL_srr : ISRR_db<0xE2, "mul">;
+def MUL_rr_v110: IRR_dab<0x73, 0x0A, "mul">, NsRequires<[HasV110]>;
+
+multiclass mI_MUL_<bits<8> rc1, bits<7> rc2, bits<8> oprr1, bits<12> oprr2, string asmstr,
+                   RegisterClass RCd=RD>{
+  if !eq(asmstr, "mul.u") then
+      def _rc  : IRC<rc1, rc2, asmstr, RCd>, Requires<[HasV120_UP]>;
+  else{
+      def _rc  : IRC<rc1, rc2, asmstr, RCd>;
+      def _rr_v110: IRR_dab<oprr1, oprr2{7-0}, asmstr, RCd>, NsRequires<[HasV110]>;
+  }
+
+  def _rr2 : IRR2<oprr1, oprr2, asmstr, RCd>, Requires<[HasV120_UP]>;
+}
+
+defm MULS : mI_MUL_<0x53, 0x05, 0x73, 0x8A, "muls", RD>;
+
+class IRR1<bits<8> op1, bits<10> op2, string asmstr,
+           RegisterClass RCd, string labela, string labelb>
+    : RR1<op1, op2, (outs RCd:$d), (ins RD:$s1, RD:$s2, u2imm:$n),
+          asmstr # " $d, ${s1}" # labela # ", ${s2}" # labelb # ", $n", []>;
+
+multiclass mI_MUL_H_<bits<8> pre, bits<10> ll, bits<10> lu, bits<10> ul, bits<10> uu, string asmstr
+                   , bit hasv110=false, bits<8> rr=0, RegisterClass RCd=RE>{
+  if hasv110 then
+    def _rr_v110 : IRR_dabn<pre, rr, asmstr, RCd>, NsRequires<[HasV110]>;
+  def _rr1_LL2e : IRR1<pre, ll, asmstr, RCd, "", "ll">, Requires<[HasV120_UP]>;
+  def _rr1_LU2e : IRR1<pre, lu, asmstr, RCd, "", "lu">, Requires<[HasV120_UP]>;
+  def _rr1_UL2e : IRR1<pre, ul, asmstr, RCd, "", "ul">, Requires<[HasV120_UP]>;
+  def _rr1_UU2e : IRR1<pre, uu, asmstr, RCd, "", "uu">, Requires<[HasV120_UP]>;
+}
+
+defm MUL_H : mI_MUL_H_<0xB3, 0x1A, 0x19, 0x18, 0x1B, "mul.h", true, 0x18>;
+
+multiclass mI_MULQ_<bits<8> pre, bits<8> rr, bits<10> op1, bits<10> op2, bits<10> op3, bits<10> op4,
+                      bits<10> op5, bits<10> op6, bits<10> op7, bits<10> op8, string asmstr>{
+  def _rr_v110 : IRR_dabn<pre, rr, asmstr, RD>, NsRequires<[HasV110]>;
+  def _rr1_2   : IRR1<pre, op1, asmstr, RD, "", "">, Requires<[HasV120_UP]>;
+  def _rr1_2__e: IRR1<pre, op2, asmstr, RE, "", "">, Requires<[HasV120_UP]>;
+
+  def _rr1_2_L : IRR1<pre, op3, asmstr, RD, "", "l">, Requires<[HasV120_UP]>;
+  def _rr1_2_Le: IRR1<pre, op4, asmstr, RE, "", "l">, Requires<[HasV120_UP]>;
+  def _rr1_2_U : IRR1<pre, op5, asmstr, RD, "", "u">, Requires<[HasV120_UP]>;
+  def _rr1_2_Ue: IRR1<pre, op6, asmstr, RE, "", "u">, Requires<[HasV120_UP]>;
+
+  def _rr1_2LL : IRR1<pre, op7, asmstr, RD, "l", "l">, Requires<[HasV120_UP]>;
+  def _rr1_2UU : IRR1<pre, op8, asmstr, RD, "u", "u">, Requires<[HasV120_UP]>;
+}
+
+defm MUL_Q : mI_MULQ_<0x93, 0x04, 0x02, 0x1B, 0x01, 0x19, 0x00, 0x18, 0x05, 0x04, "mul.q">;
+
+defm MUL_U : mI_MUL_<0x53, 0x02, 0x73, 0x68, "mul.u", RE>;
+defm MULS_U : mI_MUL_<0x53, 0x04, 0x73, 0x88, "muls.u", RD>;
+
+defm MULM: mIRR_RC<0x73, 0x6A, 0x53, 0x03, "mulm", RE>, NsRequires<[HasV110]>;
+defm MULM_U: mIRR_RC<0x73, 0x68, 0x53, 0x02, "mulm.u", RE>, NsRequires<[HasV110]>;
+defm MULMS_H: mI_MUL_H_<0xB3, 0x3E,0x3D, 0x3C, 0x3F, "mulms.h">;
+
+defm MULM_H : mI_MUL_H_<0xB3, 0x1E, 0x1D, 0x1C, 0x1F, "mulm.h">;
+defm MULR_H : mI_MUL_H_<0xB3, 0x0E, 0x0D, 0x0C, 0x0F, "mulr.h", true, 0x0C, RD>;
+
+def MULR_Q_rr_v110 : IRR_dabn<0x93, 0x06, "mulr.q">, NsRequires<[HasV110]>;
+def MULR_Q_rr1_2LL : IRR1<0x93, 0x07, "mulr.q", RD, "l", "l">, Requires<[HasV120_UP]>;
+def MULR_Q_rr1_2UU : IRR1<0x93, 0x06, "mulr.q", RD, "u", "u">, Requires<[HasV120_UP]>;
+
+defm NAND : mIRR_RC<0x0F, 0x09, 0x8F, 0x09, "nand">;
+def NAND_T : IBIT<0x07, 0x00, "nand.t">;
+
+defm NE : mIRR_RC<0x0B, 0x11, 0x8B, 0x11, "ne">;
+def NE_A : IRR_dab<0x01, 0x41, "ne.a", RD, RA, RA>;
+def NEZ_A : IRR_a<0x01, 0x49, "nez.a", RD, RA>;
+
+def NOP_sr : ISR_0<0x00, 0x00, "nop">;
+def NOP_sys : ISYS_0<0x0D, 0x00, "nop">;
+
+multiclass mISR_1<bits<8> sr1op1, bits<4> sr1op2, bits<8> sr2op1, bits<4> sr2op2,
+                string asmstr>{
+  def _sr : ISR_1<sr1op1, sr1op2, asmstr>, Requires<[HasV120_UP]>;
+  def _sr_v110 : ISR_1<sr2op1, sr2op2, asmstr>, NsRequires<[HasV110]>;
+}
+
+defm NOR : mIRR_RC<0x0F, 0x0B, 0x8F, 0x0B, "nor">;
+def NOR_T : IBIT<0x87, 0x02, "nor.t">;
+
+defm NOR : mISR_1<0x46, 0x00, 0x36, 0x00, "nor">;
+
+def NOT_sr_v162 : ISR_1<0x46, 0x00, "not">, NsRequires<[HasV162]>;
+
+
+defm OR : mIRR_RC<0x0F, 0x0A, 0x8F, 0x0A, "or", RD, RD, u9imm>;
+def OR_sc : ISC_D15C<0x96, "or">, Requires<[HasV120_UP]>;
+def OR_srr : ISRR_db<0xA6, "or">, Requires<[HasV120_UP]>;
+def OR_sc_v110 : ISC_D15C<0xD6, "or">, NsRequires<[HasV110]>;
+def OR_srr_v110 : ISRR_db<0x56, "or">, NsRequires<[HasV110]>;
+
+def OR_AND_T  : IBIT<0xC7, 0x00, "or.and.t">;
+def OR_ANDN_T : IBIT<0xC7, 0x03, "or.andn.t">;
+def OR_NOR_T  : IBIT<0xC7, 0x02, "or.nor.t">;
+def OR_OR_T   : IBIT<0xC7, 0x01, "or.or.t">;
+
+defm OR_EQ   : mIRR_RC<0x0B, 0x27, 0x8B, 0x27, "or.eq">;
+defm OR_GE   : mIRR_RC<0x0B, 0x2B, 0x8B, 0x2B, "or.ge">;
+defm OR_GE_U : mIRR_RC<0x0B, 0x2C, 0x8B, 0x2C, "or.ge.u">;
+defm OR_LT   : mIRR_RC<0x0B, 0x29, 0x8B, 0x29, "or.lt">;
+defm OR_LT_U : mIRR_RC<0x0B, 0x2A, 0x8B, 0x2A, "or.lt.u">;
+defm OR_NE   : mIRR_RC<0x0B, 0x28, 0x8B, 0x28, "or.ne">;
+
+def OR_T : IBIT<0x87, 0x01, "or.t">;
+
+defm ORN : mIRR_RC<0x0F, 0x0F, 0x8F, 0x0F, "orn">;
+
+def ORN_T : IBIT<0x07, 0x01, "orn.t">;
+
+def PACK_rrr : IRRR_d31<0x6B, 0x00, "pack", RD, RD, RD, RE>;
+
+multiclass mISYS_0<bits<8> sys1op1, bits<6> sys1op2, bits<8> sys2op1, bits<6> sys2op2,
+                string asmstr>{
+  def _sys : ISYS_0<sys1op1, sys1op2, asmstr>, Requires<[HasV120_UP]>;
+  def _sys_v110 : ISYS_0<sys2op1, sys2op2, asmstr>, NsRequires<[HasV110]>;
+}
+
+def PARITY_rr : IRR_a<0x4B, 0x02, "parity">, Requires<[HasV120_UP]>;
+def PARITY_rr_v110 : IRR_a<0x4B, 0x08, "parity">, NsRequires<[HasV110]>;
+
+def POPCNT_W_rr : IRR_a<0x4B, 0x22, "popcnt.w">, NsRequires<[HasV162]>;
+
+def RESTORE_sys : ISYS_1<0x0D, 0x0E, "restore">, Requires<[HasV160_UP]>;
+
+def RET_sr : ISR_0<0x00, 0x09, "ret">;
+defm RET : mISYS_0<0x0D, 0x06, 0x0D, 0x05, "ret">;
+
+def RFE_sr : ISR_0<0x00, 0x08, "rfe">;
+defm RFE_sys : mISYS_0<0x0D, 0x07, 0x0D, 0x06, "rfe">;
+
+def RFM_sys : ISYS_0<0x0D, 0x05, "rfm">;
+
+def RSLCX_sys : ISYS_0<0x0D, 0x09, "rslcx">;
+
+def RSTV_sys : ISYS_0<0x2F, 0x00, "rstv">;
+
+def RSUB_rc : IRC<0x8B, 0x08, "rsub">;
+defm RSUB_sr : mISR_1<0x32, 0x05, 0xD2, 0x05, "rsub">;
+
+def RSUBS_rc   : IRC<0x8B, 0x0A, "rsubs">;
+def RSUBS_U_rc : IRC<0x8B, 0x0B, "rsubs.u">;
+
+multiclass mI_SAT_<bits<8> r1, bits<8> r2, bits<8> s1, bits<4> s2, bits<8> vs1, bits<4> vs2, string asmstr>{
+  def _rr : IRR_a<r1, r2, asmstr>;
+  defm "" : mISR_1<s1, s2, vs1, vs2, asmstr>;
+}
+
+defm SAT_B  : mI_SAT_<0x0B, 0x5E, 0x32, 0x00, 0xD2, 0x00, "sat.b">;
+defm SAT_BU : mI_SAT_<0x0B, 0x5F, 0x32, 0x01, 0xD2, 0x01, "sat.bu">;
+defm SAT_H  : mI_SAT_<0x0B, 0x7E, 0x32, 0x02, 0xD2, 0x02, "sat.h">;
+defm SAT_HU : mI_SAT_<0x0B, 0x7F, 0x32, 0x03, 0xD2, 0x03, "sat.hu">;
+
+def SEL_rcr : IRCR<0xAB, 0x04, "sel">;
+def SEL_rrr : IRRR<0x2B, 0x04, "sel">;
+
+def SEL_A_rcr_v110: IRCR<0xA1, 0x04, "sel.a", RA, RA>, NsRequires<[HasV110]>;
+def SEL_A_rrr_v110: IRRR<0x21, 0x04, "sel.a", RA, RA, RA>, NsRequires<[HasV110]>;
+
+def SELN_rcr : IRCR<0xAB, 0x05, "seln">;
+def SELN_rrr : IRRR<0x2B, 0x05, "seln">;
+
+def SELN_A_rcr_v110: IRCR<0xA1, 0x05, "seln.a", RA, RA>, NsRequires<[HasV110]>;
+def SELN_A_rrr_v110: IRRR<0x21, 0x05, "seln.a", RA, RA, RA>, NsRequires<[HasV110]>;
+
+multiclass mISRC_1<bits<8> op1, bits<8> op2, string asmstr>{
+  def _src: ISRC_1<op1, asmstr>, Requires<[HasV120_UP]>;
+  def _src_v110: ISRC_1<op2, asmstr>, NsRequires<[HasV110]>;
+}
+
+defm SH : mISRC_1<0x06, 0x26, "sh">;
+defm SH : mIRR_RC<0x0F, 0x00, 0x8F, 0x00, "sh">;
+defm SH_B : mIRR_RC<0x0F, 0x20, 0x8F, 0x20, "sh.b">, NsRequires<[HasV110]>;
+defm SH_H : mIRR_RC<0x0F, 0x40, 0x8F, 0x40, "sh.h">;
+
+defm SH_EQ : mIRR_RC<0x0B, 0x37, 0x8B, 0x37, "sh.eq">;
+defm SH_NE : mIRR_RC<0x0B, 0x38, 0x8B, 0x38, "sh.ne">;
+defm SH_GE : mIRR_RC<0x0B, 0x3B, 0x8B, 0x3B, "sh.ge">;
+defm SH_GE_U : mIRR_RC<0x0B, 0x3C, 0x8B, 0x3C, "sh.ge.u">;
+defm SH_LT : mIRR_RC<0x0B, 0x39, 0x8B, 0x39, "sh.lt">;
+defm SH_LT_U : mIRR_RC<0x0B, 0x3A, 0x8B, 0x3A, "sh.lt.u">;
+
+def SH_AND_T  : IBIT<0x27, 0x00, "sh.and.t">;
+def SH_ANDN_T : IBIT<0x27, 0x03, "sh.andn.t">;
+def SH_NAND_T : IBIT<0xA7, 0x00, "sh.nand.t">;
+def SH_NOR_T  : IBIT<0x27, 0x02, "sh.nor.t">;
+def SH_OR_T   : IBIT<0x27, 0x01, "sh.or.t">;
+def SH_ORN_T  : IBIT<0xA7, 0x01, "sh.orn.t">;
+def SH_XNOR_T : IBIT<0xA7, 0x02, "sh.xnor.t">;
+def SH_XOR_T  : IBIT<0xA7, 0x03, "sh.xor.t">;
+
+
+defm SHA : mISRC_1<0x86, 0xA6, "sha">;
+defm SHA : mIRR_RC<0x0F, 0x01, 0x8F, 0x01, "sha">;
+defm SHA_B : mIRR_RC<0x0F, 0x21, 0x8F, 0x21, "sha.b">, NsRequires<[HasV110]>;
+defm SHA_H : mIRR_RC<0x0F, 0x41, 0x8F, 0x41, "sha.h">;
+defm SHAS : mIRR_RC<0x0F, 0x02, 0x8F, 0x02, "shas">;
+
+def SHUFFLE_rc : IRC<0x8F, 0x07, "shuffle">, Requires<[HasV162]>;
+
+// A[b], off10, A[a] (BO)(Base + Short Offset Addressing Mode)
+class IBO_bso_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass RC> 
+    : BO<op1, op2, (outs RC:$d), (ins RA:$s1, s10imm:$off10),
+      asmstr # " [$s1]$off10, $d", []>;
+// P[b], A[a] (BO)(Bit-reverse Addressing Mode)
+class IBO_r_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass RC>
+    : BO<op1, op2, (outs RP:$d), (ins RC:$s1),
+      asmstr # " [${d}+r], $s1", []>;
+// P[b], off10, A[a] (BO)(Circular Addressing Mode)
+class IBO_c_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass RC> 
+    : BO<op1, op2, (outs RP:$d), (ins RC:$s1, s10imm:$off10),
+      asmstr # " [${d}+c]$off10, $s1", []>;
+// A[b], off10, A[a] (BO)(Post-increment Addressing Mode)
+class IBO_pos_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass RC>
+    : BO<op1, op2, (outs), (ins RC:$s1, RA:$s2, s10imm:$off10),
+      asmstr # " [${s2}+]$off10, $s1", []>;
+// A[b], off10, A[a] (BO)(Pre-increment Addressing Mode)
+class IBO_pre_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass RC>
+    : BO<op1, op2, (outs), (ins RC:$s1, RA:$s2, s10imm:$off10),
+      asmstr # " [+${s2}]$off10, $s1", []>;
+
+
+multiclass mIBO_st<bits<8> prefix1, bits<8> prefix2,
+                  bits<6> bso2, ///_bso
+                  bits<6> pos_r, ///_pos|_r
+                  bits<6> pre_c, ///_pre|_c
+                  string asmstr, RegisterClass RC>{
+  def _bo_bso  : IBO_bso_st<prefix1, bso2, asmstr, RC>;
+  def _bo_pos  : IBO_pos_st<prefix1, pos_r, asmstr, RC>;
+  def _bo_pre  : IBO_pre_st<prefix1, pre_c, asmstr, RC>;
+  def _bo_r    : IBO_r_st<prefix2, pos_r, asmstr, RC>;
+  def _bo_c    : IBO_c_st<prefix2, pre_c, asmstr, RC>;
+}
+
+multiclass mI_ST_<bits<8> abs1, bits<2> abs2,   ///_abs
+                    bits<8> prefix1, bits<8> prefix2,
+                    bits<6> bso, ///_bso
+                    bits<6> pos_r, ///_pos|_r
+                    bits<6> pre_c, ///_pre|_c
+                    string asmstr, RegisterClass RC>
+          : mIBO_st<prefix1, prefix2, bso, pos_r, pre_c, asmstr, RC>{
+  def _abs : IABS_OR<abs1, abs2, asmstr, RC>;
+}
+
+defm ST_A  : mI_ST_<0xA5, 0x02, 0x89, 0xA9, 0x26, 0x06, 0x16, "st.a", RA>;
+defm ST_B  : mI_ST_<0x25, 0x00, 0x89, 0xA9, 0x20, 0x00, 0x10, "st.b", RD>;
+defm ST_D  : mI_ST_<0xA5, 0x01, 0x89, 0xA9, 0x25, 0x05, 0x15, "st.d", RE>;
+defm ST_DA : mI_ST_<0xA5, 0x03, 0x89, 0xA9, 0x27, 0x07, 0x17, "st.da", RP>;
+defm ST_H  : mI_ST_<0x25, 0x02, 0x89, 0xA9, 0x22, 0x02, 0x12, "st.h", RD>;
+defm ST_Q  : mI_ST_<0x65, 0x00, 0x89, 0xA9, 0x28, 0x08, 0x18, "st.q", RD>;
+
+multiclass mI_ST_2_<bits<8> sro, bits<8> ssr, bits<8> ssrpos, bits<8> ssro,
+                             bits<8> srov, bits<8> ssrv, bits<8> ssrposv, bits<8> ssrov,
+                             string asmstr,  RegisterClass RC>{
+  if !eq(RC,RD) then {
+    def _sro_v110: ISRO_ROD15<srov, asmstr, RA>, NsRequires<[HasV110]>;
+    def _sro  : ISRO_ROD15<sro, asmstr, RA>, Requires<[HasV120_UP]>;
+  } else if !eq(RC,RA) then {
+    def _sro_v110: ISRO_ROA15<srov, asmstr, RA>, NsRequires<[HasV110]>;
+    def _sro  : ISRO_ROA15<sro, asmstr, RA>, Requires<[HasV120_UP]>;
+  }
+  def _ssr_v110    : SSR<ssrv, (outs RA:$d), (ins RC:$s1),
+                        asmstr # " [$d], $s1", []>
+                  , NsRequires<[HasV110]>;
+  def _ssr_pos_v110: SSR<ssrposv, (outs RA:$d), (ins RC:$s1),
+                        asmstr # " [${d}+], $s1", []>
+                  , NsRequires<[HasV110]>;
+  def _ssro_v110: SSRO<ssrov, (outs), (ins RC:$s1, u4imm:$off4),
+                      asmstr # " [%a15]$off4, $s1", []>
+                , NsRequires<[HasV110]>;
+
+  def _ssr     : SSR<ssr, (outs RA:$d), (ins RC:$s1),
+                     asmstr # " [$d], $s1", []>
+              , Requires<[HasV120_UP]>;
+  def _ssr_pos : SSR<ssrpos, (outs RA:$d), (ins RC:$s1),
+                     asmstr # " [${d}+], $s1", []>
+              , Requires<[HasV120_UP]>;
+  def _ssro    : SSRO<ssro, (outs), (ins RC:$s1, u4imm:$off4),
+                      asmstr # " [%a15]$off4, $s1", []>
+              , Requires<[HasV120_UP]>;
+}
+
+def ST_A_bol : IBOL_AbOR<0xB5, "st.a", RA>, Requires<[HasV160_UP]>;
+def ST_A_sc : ISC_A10CA15<0xF8, "st.a">, Requires<[HasV120_UP]>;
+defm ST_A : mI_ST_2_<0xEC, 0xF4, 0xE4, 0xE8, 0x18, 0x84, 0x54, 0x2C, "st.a", RA>;
+
+def ST_B_bol : IBOL_AbOR<0xE9, "st.b", RD>, Requires<[HasV160_UP]>;
+defm ST_B : mI_ST_2_<0x2C, 0x34, 0x24, 0x28, 0xA8, 0x78, 0xE4, 0x8C, "st.b", RD>;
+
+def ST_H_bol : IBOL_AbOR<0xF9, "st.h", RD>, Requires<[HasV160_UP]>;
+defm ST_H : mI_ST_2_<0xAC, 0xB4, 0xA4, 0xA8, 0x68, 0xF8, 0x14, 0x4C, "st.h", RD>;
+
+def ST_T : ABSB<0xD5, 0x00, (outs), (ins off18imm:$off18, i32imm:$bpos3, i32imm:$b),
+                "st.t $off18, $bpos3, $b", []>;
+
+defm ST_W : mI_ST_<0xA5, 0x00, 0x89, 0xA9, 0x24, 0x04, 0x14, "st.w", RD>
+          , mI_ST_2_<0x6C, 0x74, 0x64, 0x68, 0xE8, 0x04, 0x94, 0xCC, "st.w", RD>;
+def ST_W_bol : IBOL_AbOR<0x59, "st.w", RD>;
+def ST_W_sc : ISC_A10CD15<0x78, "st.w">, Requires<[HasV120_UP]>;
+
+def STLCX_abs : IABS_off18<0x15, 0x00, "stlcx">; 
+def STLCX_bo_bso : IBO_bso<0x49, 0x26, "stlcx">; 
+
+def STUCX_abs : IABS_off18<0x15, 0x01, "stucx">; 
+def STUCX_bo_bso : IBO_bso<0x49, 0x27, "stucx">; 
+
+def SUB_rr : IRR_dab<0x0B, 0x08, "sub">;
+defm SUB : mISRR_a15a<0xA2, 0x52, 0x5A, "sub">
+         , mIB_H<0x0B, 0x48, 0x0B, 0x68, "sub">;
+
+
+multiclass mISC_A10C<bits<8> scv, bits<8> sc, string asmstr>{
+  def _sc_v110: ISC_A10C<scv, asmstr>, NsRequires<[HasV110]>;
+  def _sc     : ISC_A10C<sc, asmstr>, Requires<[HasV120_UP]>;
+}
+
+def SUB_A_rr : IRR_dab<0x01, 0x02, "sub.a", RA, RA, RA>;
+defm SUB_A : mISC_A10C<0x40, 0x20, "sub.a">;
+def SUBSC_A_rr: IRR_dabn<0x01, 0x61, "subsc.a", RA, RA, RD>, NsRequires<[HasV110]>;
+
+def SUBC_rr : IRR_dab<0x0B, 0x0D, "subc">;
+
+def SUBS_rr : IRR_dab<0x0B, 0x0A, "subs">;
+def SUBS_srr : ISRR_db<0x62, "subs">;
+
+def SUBS_U_rr : IRR_dab<0x0B, 0x0B, "subs.u">;
+def SUBS_B_rr : IRR_dab<0x0B, 0x4A, "subs.b">, NsRequires<[HasV110]>;
+def SUBS_BU_rr: IRR_dab<0x0B, 0x4B, "subs.bu">, NsRequires<[HasV110]>;
+def SUBS_H_rr : IRR_dab<0x0B, 0x6A, "subs.h">;
+def SUBS_HU_rr: IRR_dab<0x0B, 0x6B, "subs.hu">;
+def SUBX_rr : IRR_dab<0x0B, 0x0C, "subx">;
+
+def SVLCX_sys : ISYS_0<0x0D, 0x08, "svlcx">;
+
+multiclass mI_SWAP_1<bits<8> prefix_bso_pos_pre, bits<8> prefix_r_c,
+                    bits<6> bso, ///_bso
+                    bits<6> pos_r, ///_pos|_r
+                    bits<6> pre_c, ///_pre|_c
+                    string asmstr, RegisterClass RC=RA>{
+  def _bo_bso: BO<prefix_bso_pos_pre, bso, (outs RC:$d), (ins RA:$s1, s10imm:$off10),
+                  asmstr # " [$s1]$off10, $d", []>;
+  def _bo_pos: BO<prefix_bso_pos_pre, pos_r, (outs), (ins RC:$s1, RA:$s2, s10imm:$off10),
+                  asmstr # " [${s2}+]$off10, $s1", []>;
+  def _bo_pre: BO<prefix_bso_pos_pre, pre_c, (outs), (ins RC:$s1, RA:$s2, s10imm:$off10),
+                  asmstr # " [+${s2}]$off10, $s1", []>;
+
+  def _bo_r  : BO<prefix_r_c, pos_r, (outs RP:$d), (ins RC:$s1),
+                  asmstr # " [${d}+r], $s1", []>;
+  def _bo_c  : BO<prefix_r_c, pre_c, (outs RP:$d), (ins RC:$s1, s10imm:$off10),
+                  asmstr # " [${d}+c]$off10, $s1", []>;
+}
+
+multiclass mI_SWAP_<bits<8> abs1, bits<2> abs2,   ///_abs
+                    bits<8> prefix_bso_pos_pre, bits<8> prefix_r_c,
+                    bits<6> bso, ///_bso
+                    bits<6> pos_r, ///_pos|_r
+                    bits<6> pre_c, ///_pre|_c
+                    string asmstr, RegisterClass RC=RA>{
+  def _abs: IABS_OR<abs1, abs2, asmstr, RC>;
+  defm "" : mI_SWAP_1<prefix_bso_pos_pre, prefix_r_c, bso, pos_r, pre_c, asmstr, RC>;
+}
+
+defm SWAP_A    : mI_SWAP_<0xE5, 0x02, 0x49, 0x69, 0x22, 0x02, 0x12, "swap.a">, NsRequires<[HasV110]>;
+defm SWAP_W    : mI_SWAP_<0xE5, 0x00, 0x49, 0x69, 0x20, 0x00, 0x10, "swap.w", RD>;
+def SWAP_W_bo_i: BO<0x69, 0x20, (outs RD:$d), (ins RP:$s1, s10imm:$off10),
+                          "swap.w [${s1}+i], $d", []>, Requires<[HasV160_UP]>;
+
+defm SWAPMSK_W : mI_SWAP_1<0x49, 0x69, 0x22, 0x02, 0x12, "swapmsk.w", RE>, Requires<[HasV161_UP]>;
+def SWAPMSK_W_bo_i: BO<0x69, 0x22, (outs RE:$d), (ins RP:$s1, s10imm:$off10),
+                          "swapmsk.w [${s1}+i], $d", []>, Requires<[HasV161_UP]>;
+
+def SYSCALL_rc : IRC_C<0xAD, 0x04, "syscall">;
+
+def TLBDEMAP_rr  : IRR_R1<0x75, 0x00, "tlbdemap">, Requires<[HasV130_UP]>;
+def TLBFLUSH_A_rr: IRR_0<0x75, 0x04, "tlbflush.a">, Requires<[HasV130_UP]>;
+def TLBFLUSH_B_rr: IRR_0<0x75, 0x05, "tlbflush.b">, Requires<[HasV130_UP]>;
+def TLBMAP_rr  : IRR_R1<0x75, 0x40, "tlbmap", RE>, Requires<[HasV130_UP]>;
+def TLBPROBE_A_rr: IRR_R1<0x75, 0x08, "tlbprobe.a">, Requires<[HasV130_UP]>;
+def TLBPROBE_I_rr: IRR_R1<0x75, 0x09, "tlbprobe.i">, Requires<[HasV130_UP]>;
+
+def TRAPSV_sys : ISYS_0<0x0D, 0x15, "trapsv">;
+def TRAPV_sys  : ISYS_0<0x0D, 0x14, "trapv">;
+
+multiclass mIRR_a<bits<8> pre, bits<8> op1, bits<8> op2, string asmstr, RegisterClass RC=RD>{
+  def _rr_v110: IRR_a<pre, op1, asmstr, RC>, NsRequires<[HasV110]>;
+  def _rr : IRR_a<pre, op2, asmstr, RC>, Requires<[HasV120_UP]>;
+}
+
+defm UNPACK_rr : mIRR_a<0x4B, 0x50, 0x08, "unpack", RE>;
+
+def WAIT_sys  : ISYS_0<0x0D, 0x16, "wait">, Requires<[HasV161_UP]>;
+
+defm XNOR : mIRR_RC<0x0F, 0x0D, 0x8F, 0x0D, "xnor">;
+def XNOR_T : IBIT<0x07, 0x02, "xnor.t">;
+
+defm XOR : mIRR_RC<0x0F, 0x0C, 0x8F, 0x0C, "xor">;
+def XOR_srr : ISRR_db<0xC6, "xor">, Requires<[HasV120_UP]>;
+def XOR_T : IBIT<0x07, 0x03, "xor.t">;
+
+defm XOR_EQ   : mIRR_RC<0x0B, 0x2F, 0x8B, 0x2F, "xor.eq">;
+defm XOR_NE   : mIRR_RC<0x0B, 0x30, 0x8B, 0x30, "xor.ne">;
+defm XOR_GE   : mIRR_RC<0x0B, 0x33, 0x8B, 0x33, "xor.ge">;
+defm XOR_GE_U : mIRR_RC<0x0B, 0x34, 0x8B, 0x34, "xor.ge.u">;
+defm XOR_LT   : mIRR_RC<0x0B, 0x31, 0x8B, 0x31, "xor.lt">;
+defm XOR_LT_U : mIRR_RC<0x0B, 0x32, 0x8B, 0x32, "xor.lt.u">;
+
+
+
+/// FPU Instructions
+
+def MADD_F_rrr : IRRR<0x6B, 0x06, "madd.f">, Requires<[HasV130_UP]>;
+def MSUB_F_rrr : IRRR<0x6B, 0x07, "msub.f">, Requires<[HasV130_UP]>;
+def ADD_F_rrr : IRRR_d31<0x6B, 0x02, "add.f">, Requires<[HasV130_UP]>;
+def SUB_F_rrr : IRRR_d31<0x6B, 0x03, "sub.f">, Requires<[HasV130_UP]>;
+def MUL_F_rrr : IRR_dab<0x4B, 0x04, "mul.f">, Requires<[HasV130_UP]>;
+def DIV_F_rr  : IRR_dab<0x4B, 0x05, "div.f">, Requires<[HasV130_UP]>;
+def CMP_F_rr  : IRR_dab<0x4B, 0x00, "cmp.f">, Requires<[HasV130_UP]>;
+
+def FTOI_rr   : IRR_a<0x4B, 0x10, "ftoi">, Requires<[HasV130_UP]>;
+def FTOIZ_rr  : IRR_a<0x4B, 0x13, "ftoiz">, Requires<[HasV131_UP]>;
+
+def FTOQ31_rr : IRR_dab<0x4B, 0x11, "ftoq31">, Requires<[HasV130_UP]>;
+def FTOQ31Z_rr: IRR_dab<0x4B, 0x18, "ftoq31z">, Requires<[HasV131_UP]>;
+
+def FTOU_rr   : IRR_a<0x4B, 0x12, "ftou">, Requires<[HasV130_UP]>;
+def FTOUZ_rr  : IRR_a<0x4B, 0x17, "ftouz">, Requires<[HasV131_UP]>;
+
+def FTOHP_rr  : IRR_a<0x4B, 0x25, "ftohp">, Requires<[HasV162_UP]>;
+
+def HPTOF_rr  : IRR_a<0x4B, 0x24, "hptof">, Requires<[HasV162_UP]>;
+def ITOF_rr   : IRR_a<0x4B, 0x14, "itof">, Requires<[HasV130_UP]>;
+
+def Q31TOF_rr  : IRR_dab<0x4B, 0x15, "q31tof">, Requires<[HasV130_UP]>;
+def QSEED_F_rr : IRR_a<0x4B, 0x19, "qseed.f">, Requires<[HasV130_UP]>;
+
+def UPDFL_rr   : IRR_R1<0x4B, 0x0C, "updfl">, Requires<[HasV130_UP]>;
+def UTOF_rr    : IRR_a<0x4B, 0x16, "utof">, Requires<[HasV130_UP]>;
diff --git a/arch/TriCore/TriCoreMapping.c b/arch/TriCore/TriCoreMapping.c
new file mode 100644
index 0000000000..d9e998e55e
--- /dev/null
+++ b/arch/TriCore/TriCoreMapping.c
@@ -0,0 +1,133 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_TRICORE
+
+#include <stdio.h> // debug
+#include <string.h>
+
+#include "../../utils.h"
+
+#include "TriCoreMapping.h"
+
+#define GET_INSTRINFO_ENUM
+
+#include "TriCoreGenInstrInfo.inc"
+
+static insn_map insns[] = {
+	// dummy item
+	{ 0,
+	  0,
+#ifndef CAPSTONE_DIET
+	  { 0 },
+	  { 0 },
+	  { 0 },
+	  0,
+	  0
+#endif
+	},
+
+#include "TriCoreGenCSMappingInsn.inc"
+};
+
+unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id)
+{
+	unsigned short i =
+		insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+	if (i != 0) {
+		return insns[i].mapid;
+	}
+	return 0;
+}
+
+// given internal insn id, return public instruction info
+void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	unsigned short i;
+
+	i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+	if (i != 0) {
+		insn->id = insns[i].mapid;
+
+		if (h->detail) {
+#ifndef CAPSTONE_DIET
+			memcpy(insn->detail->regs_read, insns[i].regs_use,
+			       sizeof(insns[i].regs_use));
+			insn->detail->regs_read_count =
+				(uint8_t)count_positive(insns[i].regs_use);
+
+			memcpy(insn->detail->regs_write, insns[i].regs_mod,
+			       sizeof(insns[i].regs_mod));
+			insn->detail->regs_write_count =
+				(uint8_t)count_positive(insns[i].regs_mod);
+
+			memcpy(insn->detail->groups, insns[i].groups,
+			       sizeof(insns[i].groups));
+			insn->detail->groups_count =
+				(uint8_t)count_positive8(insns[i].groups);
+
+			if (insns[i].branch || insns[i].indirect_branch) {
+				// this insn also belongs to JUMP group. add JUMP group
+				insn->detail
+					->groups[insn->detail->groups_count] =
+					TRICORE_GRP_JUMP;
+				insn->detail->groups_count++;
+			}
+#endif
+		}
+	}
+}
+
+#ifndef CAPSTONE_DIET
+
+static const char *insn_names[] = {
+	NULL,
+
+#include "TriCoreGenCSMappingInsnName.inc"
+};
+
+// special alias insn
+static name_map alias_insn_names[] = { { 0, NULL } };
+#endif
+
+const char *TriCore_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	unsigned int i;
+
+	if (id >= TRICORE_INS_ENDING)
+		return NULL;
+
+	// handle special alias first
+	for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
+		if (alias_insn_names[i].id == id)
+			return alias_insn_names[i].name;
+	}
+
+	return insn_names[id];
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	{ TRICORE_GRP_INVALID, NULL },
+	{ TRICORE_GRP_CALL, "call" },
+	{ TRICORE_GRP_JUMP, "jump" },
+};
+#endif
+
+const char *TriCore_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= TRICORE_GRP_ENDING)
+		return NULL;
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#endif
diff --git a/arch/TriCore/TriCoreMapping.h b/arch/TriCore/TriCoreMapping.h
new file mode 100644
index 0000000000..1eac1d3515
--- /dev/null
+++ b/arch/TriCore/TriCoreMapping.h
@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_TRICORE_MAP_H
+#define CS_TRICORE_MAP_H
+
+#include <capstone/capstone.h>
+
+unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id);
+
+// given internal insn id, return public instruction info
+void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *TriCore_insn_name(csh handle, unsigned int id);
+
+const char *TriCore_group_name(csh handle, unsigned int id);
+
+#endif
diff --git a/arch/TriCore/TriCoreModule.c b/arch/TriCore/TriCoreModule.c
new file mode 100644
index 0000000000..a0aca3b4b3
--- /dev/null
+++ b/arch/TriCore/TriCoreModule.c
@@ -0,0 +1,40 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_TRICORE
+
+#include "../../utils.h"
+#include "TriCoreDisassembler.h"
+#include "TriCoreInstPrinter.h"
+#include "TriCoreMapping.h"
+
+cs_err TRICORE_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	TriCore_init(mri);
+	ud->printer = TriCore_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = TriCore_getInstruction;
+	ud->post_printer = TriCore_post_printer;
+
+	ud->reg_name = TriCore_getRegisterName;
+	ud->insn_id = TriCore_get_insn_id;
+	ud->insn_name = TriCore_insn_name;
+	ud->group_name = TriCore_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX)
+		handle->syntax = (int)value;
+
+	return CS_ERR_OK;
+}
+
+#endif
diff --git a/arch/TriCore/TriCoreModule.h b/arch/TriCore/TriCoreModule.h
new file mode 100644
index 0000000000..73a58df1cf
--- /dev/null
+++ b/arch/TriCore/TriCoreModule.h
@@ -0,0 +1,11 @@
+//
+// Created by aya on 3/4/23.
+//
+
+#ifndef CAPSTONE_TRICODEMODULE_H
+#define CAPSTONE_TRICODEMODULE_H
+
+cs_err TRICORE_global_init(cs_struct *ud);
+cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif // CAPSTONE_TRICODEMODULE_H
diff --git a/arch/TriCore/TriCoreRegisterInfo.td b/arch/TriCore/TriCoreRegisterInfo.td
new file mode 100644
index 0000000000..a6a3bbf61b
--- /dev/null
+++ b/arch/TriCore/TriCoreRegisterInfo.td
@@ -0,0 +1,153 @@
+//==-- TriCoreRegisterInfo.td - TriCore Register defs ------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Declarations that describe the TriCore register file
+//===----------------------------------------------------------------------===//
+
+class TriCoreReg<string n, list<string> altNames = []> : Register<n, altNames> {
+  field bits<16> Num;
+  let Namespace = "TriCore";
+  let HWEncoding = Num;
+}
+
+// General Purpose Data Registers
+class TriCoreDataReg<bits<16> num, string n, list<string> altNames = []> : TriCoreReg<n, altNames> {
+  let Num = num;
+}
+
+// General Purpose Address Registers
+class TriCoreAddrReg<bits<16> num, string n, list<string> altNames = []> : TriCoreReg<n, altNames> {
+  let Num = num;
+}
+
+// Program Status Register
+class TriCorePSReg<bits<16> num, string n, list<string> altNames = []> : TriCoreReg<n, altNames> {
+  let Num = num;
+}
+
+class TriCoreRegWithSubregs<bits<16> num, string n, list<Register> subregs>
+: RegisterWithSubRegs<n, subregs> {
+  field bits<16> Num;
+
+  let Num = num;
+  let Namespace = "TriCore";
+}
+
+//===----------------------------------------------------------------------===//
+//@Registers
+//===----------------------------------------------------------------------===//
+// The register string, such as "d0" or "d13" will show on "llvm-objdump -d"
+
+def D0 : TriCoreDataReg<0, "d0">, DwarfRegNum<[0]>;
+def D1 : TriCoreDataReg<1, "d1">, DwarfRegNum<[1]>;
+def D2 : TriCoreDataReg<2, "d2">, DwarfRegNum<[2]>;
+def D3 : TriCoreDataReg<3, "d3">, DwarfRegNum<[3]>;
+def D4 : TriCoreDataReg<4, "d4">, DwarfRegNum<[4]>;
+def D5 : TriCoreDataReg<5, "d5">, DwarfRegNum<[5]>;
+def D6 : TriCoreDataReg<6, "d6">, DwarfRegNum<[6]>;
+def D7 : TriCoreDataReg<7, "d7">, DwarfRegNum<[7]>;
+def D8 : TriCoreDataReg<8, "d8">, DwarfRegNum<[8]>;
+def D9 : TriCoreDataReg<9, "d9">, DwarfRegNum<[9]>;
+def D10 : TriCoreDataReg<10, "d10">, DwarfRegNum<[10]>;
+def D11 : TriCoreDataReg<11, "d11">, DwarfRegNum<[11]>;
+def D12 : TriCoreDataReg<12, "d12">, DwarfRegNum<[12]>;
+def D13 : TriCoreDataReg<13, "d13">, DwarfRegNum<[13]>;
+def D14 : TriCoreDataReg<14, "d14">, DwarfRegNum<[14]>;
+def D15 : TriCoreDataReg<15, "d15">, DwarfRegNum<[15]>;
+
+
+def A0 : TriCoreAddrReg<0, "a0">, DwarfRegNum<[16]>;
+def A1 : TriCoreAddrReg<1, "a1">, DwarfRegNum<[17]>;
+def A2 : TriCoreAddrReg<2, "a2">, DwarfRegNum<[18]>;
+def A3 : TriCoreAddrReg<3, "a3">, DwarfRegNum<[19]>;
+def A4 : TriCoreAddrReg<4, "a4">, DwarfRegNum<[20]>;
+def A5 : TriCoreAddrReg<5, "a5">, DwarfRegNum<[21]>;
+def A6 : TriCoreAddrReg<6, "a6">, DwarfRegNum<[22]>;
+def A7 : TriCoreAddrReg<7, "a7">, DwarfRegNum<[23]>;
+def A8 : TriCoreAddrReg<8, "a8">, DwarfRegNum<[24]>;
+def A9 : TriCoreAddrReg<9, "a9">, DwarfRegNum<[25]>;
+def A10 : TriCoreAddrReg<10, "sp", ["a10"]>, DwarfRegNum<[26]>;
+def A11 : TriCoreAddrReg<11, "a11">, DwarfRegNum<[27]>;
+def A12 : TriCoreAddrReg<12, "a12">, DwarfRegNum<[28]>;
+def A13 : TriCoreAddrReg<13, "a13">, DwarfRegNum<[29]>;
+def A14 : TriCoreAddrReg<14, "a14">, DwarfRegNum<[30]>;
+def A15 : TriCoreAddrReg<15, "a15">, DwarfRegNum<[31]>;
+
+let Namespace = "TriCore" in {
+def subreg_even : SubRegIndex<32>;
+def subreg_odd  : SubRegIndex<32, 32>;
+}
+
+//Extended 64-bit registers
+let SubRegIndices = [subreg_even, subreg_odd] in {
+def E0 : TriCoreRegWithSubregs<0,   "e0",  [D0,D1]   >, DwarfRegNum<[32]>;
+def E2 : TriCoreRegWithSubregs<2,   "e2",  [D2,D3]   >, DwarfRegNum<[33]>;
+def E4 : TriCoreRegWithSubregs<4,   "e4",  [D4,D5]   >, DwarfRegNum<[34]>;
+def E6 : TriCoreRegWithSubregs<6,   "e6",  [D6,D7]   >, DwarfRegNum<[35]>;
+def E8 : TriCoreRegWithSubregs<8,   "e8",  [D8,D9]   >, DwarfRegNum<[36]>;
+def E10 : TriCoreRegWithSubregs<10, "e10", [D10,D11] >, DwarfRegNum<[37]>;
+def E12 : TriCoreRegWithSubregs<12, "e12", [D12,D13] >, DwarfRegNum<[38]>;
+def E14 : TriCoreRegWithSubregs<14, "e14", [D14,D15] >, DwarfRegNum<[39]>;
+}
+
+let SubRegIndices = [subreg_even, subreg_odd] in {
+def P0 : TriCoreRegWithSubregs<0,   "p0",  [A0,A1]   >, DwarfRegNum<[40]>;
+def P2 : TriCoreRegWithSubregs<2,   "p2",  [A2,A3]   >, DwarfRegNum<[41]>;
+def P4 : TriCoreRegWithSubregs<4,   "p4",  [A4,A5]   >, DwarfRegNum<[42]>;
+def P6 : TriCoreRegWithSubregs<6,   "p6",  [A6,A7]   >, DwarfRegNum<[43]>;
+def P8 : TriCoreRegWithSubregs<8,   "p8",  [A8,A9]   >, DwarfRegNum<[44]>;
+def P10 : TriCoreRegWithSubregs<10, "p10", [A10,A11] >, DwarfRegNum<[45]>;
+def P12 : TriCoreRegWithSubregs<12, "p12", [A12,A13] >, DwarfRegNum<[46]>;
+def P14 : TriCoreRegWithSubregs<14, "p14", [A14,A15] >, DwarfRegNum<[47]>;
+}
+
+//Program Status Information Registers
+def PSW  : TriCorePSReg<0, "psw">, DwarfRegNum<[40]>;
+def PCXI : TriCorePSReg<1, "pcxi">, DwarfRegNum<[41]>;
+def PC   : TriCorePSReg<2, "pc">, DwarfRegNum<[42]>;
+def FCX  : TriCorePSReg<3, "fcx">, DwarfRegNum<[43]>;
+
+//===----------------------------------------------------------------------===//
+//@Register Classes
+//===----------------------------------------------------------------------===//
+
+def RD : RegisterClass<"TriCore", [i32], 32, (add
+    D0,  D1,  D2,  D3,  D4,
+    D5,  D6,  D7,  D8,  D9,
+    D10, D11, D12, D13, D14,
+    D15)>;
+
+def RA : RegisterClass<"TriCore", [i32], 32, (add
+    A0,  A1,  A2,  A3,  A4,
+    A5,  A6,  A7,  A8,  A9,
+    A10, A11, A12, A13, A14,
+    A15)>;
+
+def RE : RegisterClass<"TriCore", [i64], 64, (add
+    E0, E2, E4,
+    E6, E8, E10,
+    E12, E14)>;
+
+def RP : RegisterClass<"TriCore", [i64], 64, (add
+    P0, P2, P4,
+    P6, P8, P10,
+    P12, P14)>;
+
+def PSRegs : RegisterClass<"TriCore", [i32], 32, (add
+    PSW, PCXI, PC, FCX)>;
+
+def TuplesPairAddrRegs : RegisterTuples<[subreg_even, subreg_odd],
+                                        [(add A0,A2,A4,A6,A8,A10,A12,A14),
+                                        (add A1,A3,A5,A7,A9,A11,A13,A15)]>;
+
+def PairAddrRegs : RegisterClass<"TriCore", [i64], 64,
+                                (add TuplesPairAddrRegs)> {
+    let Size = 64;
+}
diff --git a/bindings/const_generator.py b/bindings/const_generator.py
index a42e203b7b..938583f6fa 100644
--- a/bindings/const_generator.py
+++ b/bindings/const_generator.py
@@ -5,7 +5,7 @@
 
 INCL_DIR = '../include/capstone/'
 
-include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h' ]
+include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'tricore.h' ]
 
 template = {
     'java': {
@@ -52,6 +52,7 @@
             'mos65xx.h': 'mos65xx',
             'bpf.h': 'bpf',
             'riscv.h': 'riscv',
+            'tricore.h': ['TRICORE', 'TriCore'],
             'comment_open': '#',
             'comment_close': '',
         },
@@ -199,6 +200,11 @@ def gen(lang):
             print("Warning: No binding found for %s" % target)
             continue
         prefix = templ[target]
+        prefixs = []
+        if isinstance(prefix, list):
+            prefixs = prefix
+            prefix = prefix[0].lower()
+
         outfile = open(templ['out_file'] %(prefix), 'wb')   # open as binary prevents windows newlines
         outfile.write((templ['header'] % (prefix)).encode("utf-8"))
 
@@ -237,7 +243,13 @@ def gen(lang):
                 xline.insert(1, '=')            # insert an = so the expression below can parse it
                 line = ' '.join(xline)
 
-            if not line.startswith(prefix.upper()):
+            def is_with_prefix(x):
+                if prefixs:
+                    return any(x.startswith(pre) for pre in prefixs)
+                else:
+                    return x.startswith(prefix.upper())
+
+            if not is_with_prefix(line):
                 continue
 
             tmp = line.strip().split(',')
@@ -249,91 +261,93 @@ def gen(lang):
                 t = re.sub(r'\((\d+)ULL << (\d+)\)', r'\1 << \2', t)    # (1ULL<<1) to 1 << 1
                 f = re.split('\s+', t)
 
-                if f[0].startswith(prefix.upper()):
-                    if len(f) > 1 and f[1] not in ('//', '///<', '='):
-                        print("Error: Unable to convert %s" % f)
-                        continue
-                    elif len(f) > 1 and f[1] == '=':
-                        rhs = ''.join(f[2:])
-                    else:
-                        rhs = str(count)
-                        count += 1
-
-                    try:
-                        count = int(rhs) + 1
-                        if (count == 1):
-                            outfile.write(("\n").encode("utf-8"))
-                    except ValueError:
-                        if lang == 'ocaml':
-                            # ocaml uses lsl for '<<', lor for '|'
-                            rhs = rhs.replace('<<', ' lsl ')
-                            rhs = rhs.replace('|', ' lor ')
-                            # ocaml variable has _ as prefix
-                            if rhs[0].isalpha():
-                                rhs = '_' + rhs
-
-                    if lang == 'swift':
-                        value = eval(rhs, None, values)
-                        exec('%s = %d' %(f[0].strip(), value), None, values)
-                    else:
-                        value = rhs
-
-                    name = f[0].strip()
-
-                    if 'rename' in templ:
-                        # constant renaming
-                        for pattern, replacement in templ['rename'].items():
-                            if re.match(pattern, name):
-                                name = re.sub(pattern, replacement, name)
-                                break
-
-
-                    if 'enum_header' in templ:
-                        # separate constants by enums based on name
-                        enum, name = pascalize_const(name)
-                        if enum not in enums:
-                            if len(enums) > 0:
-                                write_enum_extra_options(outfile, templ, last_enum, enums[last_enum])
-                                outfile.write((templ['enum_footer']).encode("utf-8"))
-                            last_enum = enum
-
-                            if 'enum_doc' in templ:
-                                for doc_line in doc_lines:
-                                    outfile.write((templ['enum_doc'] %(doc_line)).encode("utf-8"))
-                                doc_lines = []
+                if not is_with_prefix(f[0]):
+                    continue
 
-                            if 'option_sets' in templ and enum in templ['option_sets']:
-                                outfile.write((templ['option_set_header'] %(enum, templ['option_sets'][enum])).encode("utf-8"))
-                            else:
-                                outfile.write((templ['enum_header'] %(enum, enum_type(enum, templ))).encode("utf-8"))
-                            enums[enum] = {}
+                if len(f) > 1 and f[1] not in ('//', '///<', '='):
+                    print("Error: Unable to convert %s" % f)
+                    continue
+                elif len(f) > 1 and f[1] == '=':
+                    rhs = ''.join(f[2:])
+                else:
+                    rhs = str(count)
+                    count += 1
+
+                try:
+                    count = int(rhs) + 1
+                    if (count == 1):
+                        outfile.write(("\n").encode("utf-8"))
+                except ValueError:
+                    if lang == 'ocaml':
+                        # ocaml uses lsl for '<<', lor for '|'
+                        rhs = rhs.replace('<<', ' lsl ')
+                        rhs = rhs.replace('|', ' lor ')
+                        # ocaml variable has _ as prefix
+                        if rhs[0].isalpha():
+                            rhs = '_' + rhs
+
+                if lang == 'swift':
+                    value = eval(rhs, None, values)
+                    exec('%s = %d' %(f[0].strip(), value), None, values)
+                else:
+                    value = rhs
+
+                name = f[0].strip()
+
+                if 'rename' in templ:
+                    # constant renaming
+                    for pattern, replacement in templ['rename'].items():
+                        if re.match(pattern, name):
+                            name = re.sub(pattern, replacement, name)
+                            break
+
+
+                if 'enum_header' in templ:
+                    # separate constants by enums based on name
+                    enum, name = pascalize_const(name)
+                    if enum not in enums:
+                        if len(enums) > 0:
+                            write_enum_extra_options(outfile, templ, last_enum, enums[last_enum])
+                            outfile.write((templ['enum_footer']).encode("utf-8"))
+                        last_enum = enum
+
+                        if 'enum_doc' in templ:
+                            for doc_line in doc_lines:
+                                outfile.write((templ['enum_doc'] %(doc_line)).encode("utf-8"))
+                            doc_lines = []
 
                         if 'option_sets' in templ and enum in templ['option_sets']:
-                            # option set format
-                            line_format = templ['option_format'].format(option='%s',type=enum,value='%s')
-                            if value == 0:
-                                continue # skip empty option
-                            # option set values need not be literals
-                            value = rhs
-                        elif 'dup_line_format' in templ and value in enums[enum].values():
-                            # different format for duplicate values?
-                            line_format = templ['dup_line_format']
+                            outfile.write((templ['option_set_header'] %(enum, templ['option_sets'][enum])).encode("utf-8"))
                         else:
-                            line_format = templ['line_format']
-                        enums[enum][name] = value
-
-                        # escape reserved words
-                        if 'reserved_words' in templ and name in templ['reserved_words']:
-                            name = templ['reserved_word_format'] %(name)
-
-                        # print documentation?
-                        if 'doc_line_format' in templ and '///<' in line:
-                            doc = line.split('///<')[1].strip()
-                            outfile.write((templ['doc_line_format'] %(doc)).encode("utf-8"))
+                            outfile.write((templ['enum_header'] %(enum, enum_type(enum, templ))).encode("utf-8"))
+                        enums[enum] = {}
+
+                    if 'option_sets' in templ and enum in templ['option_sets']:
+                        # option set format
+                        line_format = templ['option_format'].format(option='%s',type=enum,value='%s')
+                        if value == 0:
+                            continue # skip empty option
+                        # option set values need not be literals
+                        value = rhs
+                    elif 'dup_line_format' in templ and value in enums[enum].values():
+                        # different format for duplicate values?
+                        line_format = templ['dup_line_format']
                     else:
                         line_format = templ['line_format']
+                    enums[enum][name] = value
+
+                    # escape reserved words
+                    if 'reserved_words' in templ and name in templ['reserved_words']:
+                        name = templ['reserved_word_format'] %(name)
+
+                    # print documentation?
+                    if 'doc_line_format' in templ and '///<' in line:
+                        doc = line.split('///<')[1].strip()
+                        outfile.write((templ['doc_line_format'] %(doc)).encode("utf-8"))
+                else:
+                    line_format = templ['line_format']
 
-                    outfile.write((line_format %(name, value)).encode("utf-8"))
+                outfile.write((line_format %(name, value)).encode("utf-8"))
 
         if 'enum_footer' in templ:
             write_enum_extra_options(outfile, templ, enum, enums[enum])
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index 9543eac2ed..71cae77e1a 100755
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -38,6 +38,7 @@
     'CS_ARCH_BPF',
     'CS_ARCH_RISCV',
     'CS_ARCH_MOS65XX',
+    'CS_ARCH_TRICORE',
     'CS_ARCH_ALL',
 
     'CS_MODE_LITTLE_ENDIAN',
@@ -88,6 +89,13 @@
     'CS_MODE_MOS65XX_65816_LONG_M',
     'CS_MODE_MOS65XX_65816_LONG_X',
     'CS_MODE_MOS65XX_65816_LONG_MX',
+    'CS_MODE_TRICORE_110',
+    'CS_MODE_TRICORE_120',
+    'CS_MODE_TRICORE_130',
+    'CS_MODE_TRICORE_131',
+    'CS_MODE_TRICORE_160',
+    'CS_MODE_TRICORE_161',
+    'CS_MODE_TRICORE_162',
 
     'CS_OPT_SYNTAX',
     'CS_OPT_SYNTAX_DEFAULT',
@@ -174,7 +182,9 @@
 CS_ARCH_WASM = 13
 CS_ARCH_BPF = 14
 CS_ARCH_RISCV = 15
-CS_ARCH_MAX = 16
+# CS_ARCH_SH = 16
+CS_ARCH_TRICORE = 17
+CS_ARCH_MAX = 18
 CS_ARCH_ALL = 0xFFFF
 
 # disasm mode
@@ -226,6 +236,13 @@
 CS_MODE_MOS65XX_65816_LONG_M = (1 << 5) # MOS65XXX WDC 65816, 16-bit m, 8-bit x 
 CS_MODE_MOS65XX_65816_LONG_X = (1 << 6) # MOS65XXX WDC 65816, 8-bit m, 16-bit x
 CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X
+CS_MODE_TRICORE_110 = 1 << 1 # Tricore 1.1
+CS_MODE_TRICORE_120 = 1 << 2 # Tricore 1.2
+CS_MODE_TRICORE_130 = 1 << 3 # Tricore 1.3
+CS_MODE_TRICORE_131 = 1 << 4 # Tricore 1.3.1
+CS_MODE_TRICORE_160 = 1 << 5 # Tricore 1.6
+CS_MODE_TRICORE_161 = 1 << 6 # Tricore 1.6.1
+CS_MODE_TRICORE_162 = 1 << 7 # Tricore 1.6.2
 
 # Capstone option type
 CS_OPT_SYNTAX = 1    # Intel X86 asm syntax (CS_ARCH_X86 arch)
@@ -366,7 +383,7 @@ def copy_ctypes_list(src):
     return [copy_ctypes(n) for n in src]
 
 # Weird import placement because these modules are needed by the below code but need the above functions
-from . import arm, arm64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, bpf, riscv
+from . import arm, arm64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, bpf, riscv, tricore
 
 class _cs_arch(ctypes.Union):
     _fields_ = (
@@ -385,6 +402,7 @@ class _cs_arch(ctypes.Union):
         ('mos65xx', mos65xx.CsMOS65xx),
         ('bpf', bpf.CsBPF),
         ('riscv', riscv.CsRISCV),
+        ('tricore', tricore.CsTriCore),
     )
 
 class _cs_detail(ctypes.Structure):
@@ -708,6 +726,8 @@ def __gen_detail(self):
             (self.operands) = bpf.get_arch_info(self._raw.detail.contents.arch.bpf)
         elif arch == CS_ARCH_RISCV:
             (self.operands) = riscv.get_arch_info(self._raw.detail.contents.arch.riscv)
+        elif arch == CS_ARCH_TRICORE:
+            (self.operands) = riscv.get_arch_info(self._raw.detail.contents.arch.tricore)
 
 
     def __getattr__(self, name):
@@ -1173,7 +1193,7 @@ def debug():
         "mips": CS_ARCH_MIPS, "ppc": CS_ARCH_PPC, "sparc": CS_ARCH_SPARC,
         "sysz": CS_ARCH_SYSZ, 'xcore': CS_ARCH_XCORE, "tms320c64x": CS_ARCH_TMS320C64X,
         "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
-        'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV,
+        'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
     }
 
     all_archs = ""
diff --git a/bindings/python/capstone/tricore.py b/bindings/python/capstone/tricore.py
new file mode 100644
index 0000000000..53ba251e8d
--- /dev/null
+++ b/bindings/python/capstone/tricore.py
@@ -0,0 +1,45 @@
+# Capstone Python bindings, by billow <billow.fun@gmail.com>
+
+import ctypes, copy
+from .tricore_const import *
+
+class TriCoreOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint8),
+        ('disp', ctypes.c_int32),
+    )
+
+
+class TriCoreOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int32),
+        ('mem', TriCoreOpMem),
+    )
+
+
+class TriCoreOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', TriCoreOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+
+# Instruction structure
+class CsTriCore(ctypes.Structure):
+    _fields_ = (
+        ('op_count', ctypes.c_uint8),
+        ('operands', TriCoreOp * 8),
+    )
diff --git a/bindings/python/capstone/tricore_const.py b/bindings/python/capstone/tricore_const.py
new file mode 100644
index 0000000000..338894b6d8
--- /dev/null
+++ b/bindings/python/capstone/tricore_const.py
@@ -0,0 +1,488 @@
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tricore_const.py]
+
+# Operand type for instruction's operands
+
+TRICORE_OP_INVALID = 0
+TRICORE_OP_REG = 1
+TRICORE_OP_IMM = 2
+TRICORE_OP_MEM = 3
+
+# TriCore registers
+
+TRICORE_REG_INVALID = 0
+TRICORE_REG_FCX = 1
+TRICORE_REG_PC = 2
+TRICORE_REG_PCXI = 3
+TRICORE_REG_PSW = 4
+TRICORE_REG_A0 = 5
+TRICORE_REG_A1 = 6
+TRICORE_REG_A2 = 7
+TRICORE_REG_A3 = 8
+TRICORE_REG_A4 = 9
+TRICORE_REG_A5 = 10
+TRICORE_REG_A6 = 11
+TRICORE_REG_A7 = 12
+TRICORE_REG_A8 = 13
+TRICORE_REG_A9 = 14
+TRICORE_REG_A10 = 15
+TRICORE_REG_A11 = 16
+TRICORE_REG_A12 = 17
+TRICORE_REG_A13 = 18
+TRICORE_REG_A14 = 19
+TRICORE_REG_A15 = 20
+TRICORE_REG_D0 = 21
+TRICORE_REG_D1 = 22
+TRICORE_REG_D2 = 23
+TRICORE_REG_D3 = 24
+TRICORE_REG_D4 = 25
+TRICORE_REG_D5 = 26
+TRICORE_REG_D6 = 27
+TRICORE_REG_D7 = 28
+TRICORE_REG_D8 = 29
+TRICORE_REG_D9 = 30
+TRICORE_REG_D10 = 31
+TRICORE_REG_D11 = 32
+TRICORE_REG_D12 = 33
+TRICORE_REG_D13 = 34
+TRICORE_REG_D14 = 35
+TRICORE_REG_D15 = 36
+TRICORE_REG_E0 = 37
+TRICORE_REG_E2 = 38
+TRICORE_REG_E4 = 39
+TRICORE_REG_E6 = 40
+TRICORE_REG_E8 = 41
+TRICORE_REG_E10 = 42
+TRICORE_REG_E12 = 43
+TRICORE_REG_E14 = 44
+TRICORE_REG_P0 = 45
+TRICORE_REG_P2 = 46
+TRICORE_REG_P4 = 47
+TRICORE_REG_P6 = 48
+TRICORE_REG_P8 = 49
+TRICORE_REG_P10 = 50
+TRICORE_REG_P12 = 51
+TRICORE_REG_P14 = 52
+TRICORE_REG_A0_A1 = 53
+TRICORE_REG_A2_A3 = 54
+TRICORE_REG_A4_A5 = 55
+TRICORE_REG_A6_A7 = 56
+TRICORE_REG_A8_A9 = 57
+TRICORE_REG_A10_A11 = 58
+TRICORE_REG_A12_A13 = 59
+TRICORE_REG_A14_A15 = 60
+TRICORE_REG_ENDING = 61
+
+# TriCore instruction
+
+TRICORE_INS_INVALID = 0
+TRICORE_INS_XOR_T = 1
+TRICORE_INS_ABSDIFS_B = 2
+TRICORE_INS_ABSDIFS_H = 3
+TRICORE_INS_ABSDIFS = 4
+TRICORE_INS_ABSDIF_B = 5
+TRICORE_INS_ABSDIF_H = 6
+TRICORE_INS_ABSDIF = 7
+TRICORE_INS_ABSS_B = 8
+TRICORE_INS_ABSS_H = 9
+TRICORE_INS_ABSS = 10
+TRICORE_INS_ABS_B = 11
+TRICORE_INS_ABS_H = 12
+TRICORE_INS_ABS = 13
+TRICORE_INS_ADDC = 14
+TRICORE_INS_ADDIH_A = 15
+TRICORE_INS_ADDIH = 16
+TRICORE_INS_ADDI = 17
+TRICORE_INS_ADDSC_AT = 18
+TRICORE_INS_ADDSC_A = 19
+TRICORE_INS_ADDS_BU = 20
+TRICORE_INS_ADDS_B = 21
+TRICORE_INS_ADDS_H = 22
+TRICORE_INS_ADDS_HU = 23
+TRICORE_INS_ADDS_U = 24
+TRICORE_INS_ADDS = 25
+TRICORE_INS_ADDX = 26
+TRICORE_INS_ADD_A = 27
+TRICORE_INS_ADD_B = 28
+TRICORE_INS_ADD_F = 29
+TRICORE_INS_ADD_H = 30
+TRICORE_INS_ADD = 31
+TRICORE_INS_ANDN_T = 32
+TRICORE_INS_ANDN = 33
+TRICORE_INS_AND_ANDN_T = 34
+TRICORE_INS_AND_AND_T = 35
+TRICORE_INS_AND_EQ = 36
+TRICORE_INS_AND_GE_U = 37
+TRICORE_INS_AND_GE = 38
+TRICORE_INS_AND_LT_U = 39
+TRICORE_INS_AND_LT = 40
+TRICORE_INS_AND_NE = 41
+TRICORE_INS_AND_NOR_T = 42
+TRICORE_INS_AND_OR_T = 43
+TRICORE_INS_AND_T = 44
+TRICORE_INS_AND = 45
+TRICORE_INS_BISR = 46
+TRICORE_INS_BMERGE = 47
+TRICORE_INS_BSPLIT = 48
+TRICORE_INS_CACHEA_I = 49
+TRICORE_INS_CACHEA_WI = 50
+TRICORE_INS_CACHEA_W = 51
+TRICORE_INS_CACHEI_I = 52
+TRICORE_INS_CACHEI_WI = 53
+TRICORE_INS_CACHEI_W = 54
+TRICORE_INS_CADDN_A = 55
+TRICORE_INS_CADDN = 56
+TRICORE_INS_CADD_A = 57
+TRICORE_INS_CADD = 58
+TRICORE_INS_CALLA = 59
+TRICORE_INS_CALLI = 60
+TRICORE_INS_CALL = 61
+TRICORE_INS_CLO_B = 62
+TRICORE_INS_CLO_H = 63
+TRICORE_INS_CLO = 64
+TRICORE_INS_CLS_B = 65
+TRICORE_INS_CLS_H = 66
+TRICORE_INS_CLS = 67
+TRICORE_INS_CLZ_B = 68
+TRICORE_INS_CLZ_H = 69
+TRICORE_INS_CLZ = 70
+TRICORE_INS_CMOVN = 71
+TRICORE_INS_CMOV = 72
+TRICORE_INS_CMPSWAP_W = 73
+TRICORE_INS_CMP_F = 74
+TRICORE_INS_CRC32B_W = 75
+TRICORE_INS_CRC32L_W = 76
+TRICORE_INS_CRC32_B = 77
+TRICORE_INS_CRCN = 78
+TRICORE_INS_CSUBN_A = 79
+TRICORE_INS_CSUBN = 80
+TRICORE_INS_CSUB_A = 81
+TRICORE_INS_CSUB = 82
+TRICORE_INS_DEBUG = 83
+TRICORE_INS_DEXTR = 84
+TRICORE_INS_DIFSC_A = 85
+TRICORE_INS_DISABLE = 86
+TRICORE_INS_DIV_F = 87
+TRICORE_INS_DIV_U = 88
+TRICORE_INS_DIV = 89
+TRICORE_INS_DSYNC = 90
+TRICORE_INS_DVADJ = 91
+TRICORE_INS_DVINIT_BU = 92
+TRICORE_INS_DVINIT_B = 93
+TRICORE_INS_DVINIT_HU = 94
+TRICORE_INS_DVINIT_H = 95
+TRICORE_INS_DVINIT_U = 96
+TRICORE_INS_DVINIT = 97
+TRICORE_INS_DVSTEP_U = 98
+TRICORE_INS_DVSTEP = 99
+TRICORE_INS_ENABLE = 100
+TRICORE_INS_EQANY_B = 101
+TRICORE_INS_EQANY_H = 102
+TRICORE_INS_EQZ_A = 103
+TRICORE_INS_EQ_A = 104
+TRICORE_INS_EQ_B = 105
+TRICORE_INS_EQ_H = 106
+TRICORE_INS_EQ_W = 107
+TRICORE_INS_EQ = 108
+TRICORE_INS_EXTR_U = 109
+TRICORE_INS_EXTR = 110
+TRICORE_INS_FCALLA = 111
+TRICORE_INS_FCALLI = 112
+TRICORE_INS_FCALL = 113
+TRICORE_INS_FRET = 114
+TRICORE_INS_FTOHP = 115
+TRICORE_INS_FTOIZ = 116
+TRICORE_INS_FTOI = 117
+TRICORE_INS_FTOQ31Z = 118
+TRICORE_INS_FTOQ31 = 119
+TRICORE_INS_FTOUZ = 120
+TRICORE_INS_FTOU = 121
+TRICORE_INS_GE_A = 122
+TRICORE_INS_GE_U = 123
+TRICORE_INS_GE = 124
+TRICORE_INS_HPTOF = 125
+TRICORE_INS_IMASK = 126
+TRICORE_INS_INSERT = 127
+TRICORE_INS_INSN_T = 128
+TRICORE_INS_INS_T = 129
+TRICORE_INS_ISYNC = 130
+TRICORE_INS_ITOF = 131
+TRICORE_INS_IXMAX_U = 132
+TRICORE_INS_IXMAX = 133
+TRICORE_INS_IXMIN_U = 134
+TRICORE_INS_IXMIN = 135
+TRICORE_INS_JA = 136
+TRICORE_INS_JEQ_A = 137
+TRICORE_INS_JEQ = 138
+TRICORE_INS_JGEZ = 139
+TRICORE_INS_JGE_U = 140
+TRICORE_INS_JGE = 141
+TRICORE_INS_JGTZ = 142
+TRICORE_INS_JI = 143
+TRICORE_INS_JLA = 144
+TRICORE_INS_JLEZ = 145
+TRICORE_INS_JLI = 146
+TRICORE_INS_JLTZ = 147
+TRICORE_INS_JLT_U = 148
+TRICORE_INS_JLT = 149
+TRICORE_INS_JL = 150
+TRICORE_INS_JNED = 151
+TRICORE_INS_JNEI = 152
+TRICORE_INS_JNE_A = 153
+TRICORE_INS_JNE = 154
+TRICORE_INS_JNZ_A = 155
+TRICORE_INS_JNZ_T = 156
+TRICORE_INS_JNZ = 157
+TRICORE_INS_JZ_A = 158
+TRICORE_INS_JZ_T = 159
+TRICORE_INS_JZ = 160
+TRICORE_INS_J = 161
+TRICORE_INS_LDLCX = 162
+TRICORE_INS_LDMST = 163
+TRICORE_INS_LDUCX = 164
+TRICORE_INS_LD_A = 165
+TRICORE_INS_LD_BU = 166
+TRICORE_INS_LD_B = 167
+TRICORE_INS_LD_DA = 168
+TRICORE_INS_LD_D = 169
+TRICORE_INS_LD_HU = 170
+TRICORE_INS_LD_H = 171
+TRICORE_INS_LD_Q = 172
+TRICORE_INS_LD_W = 173
+TRICORE_INS_LEA = 174
+TRICORE_INS_LHA = 175
+TRICORE_INS_LOOPU = 176
+TRICORE_INS_LOOP = 177
+TRICORE_INS_LT_A = 178
+TRICORE_INS_LT_B = 179
+TRICORE_INS_LT_BU = 180
+TRICORE_INS_LT_H = 181
+TRICORE_INS_LT_HU = 182
+TRICORE_INS_LT_U = 183
+TRICORE_INS_LT_W = 184
+TRICORE_INS_LT_WU = 185
+TRICORE_INS_LT = 186
+TRICORE_INS_MADDMS_H = 187
+TRICORE_INS_MADDMS_U = 188
+TRICORE_INS_MADDMS = 189
+TRICORE_INS_MADDM_H = 190
+TRICORE_INS_MADDM_Q = 191
+TRICORE_INS_MADDM_U = 192
+TRICORE_INS_MADDM = 193
+TRICORE_INS_MADDRS_H = 194
+TRICORE_INS_MADDRS_Q = 195
+TRICORE_INS_MADDR_H = 196
+TRICORE_INS_MADDR_Q = 197
+TRICORE_INS_MADDSUMS_H = 198
+TRICORE_INS_MADDSUM_H = 199
+TRICORE_INS_MADDSURS_H = 200
+TRICORE_INS_MADDSUR_H = 201
+TRICORE_INS_MADDSUS_H = 202
+TRICORE_INS_MADDSU_H = 203
+TRICORE_INS_MADDS_H = 204
+TRICORE_INS_MADDS_Q = 205
+TRICORE_INS_MADDS_U = 206
+TRICORE_INS_MADDS = 207
+TRICORE_INS_MADD_F = 208
+TRICORE_INS_MADD_H = 209
+TRICORE_INS_MADD_Q = 210
+TRICORE_INS_MADD_U = 211
+TRICORE_INS_MADD = 212
+TRICORE_INS_MAX_B = 213
+TRICORE_INS_MAX_BU = 214
+TRICORE_INS_MAX_H = 215
+TRICORE_INS_MAX_HU = 216
+TRICORE_INS_MAX_U = 217
+TRICORE_INS_MAX = 218
+TRICORE_INS_MFCR = 219
+TRICORE_INS_MIN_B = 220
+TRICORE_INS_MIN_BU = 221
+TRICORE_INS_MIN_H = 222
+TRICORE_INS_MIN_HU = 223
+TRICORE_INS_MIN_U = 224
+TRICORE_INS_MIN = 225
+TRICORE_INS_MOVH_A = 226
+TRICORE_INS_MOVH = 227
+TRICORE_INS_MOVZ_A = 228
+TRICORE_INS_MOV_AA = 229
+TRICORE_INS_MOV_A = 230
+TRICORE_INS_MOV_D = 231
+TRICORE_INS_MOV_U = 232
+TRICORE_INS_MOV = 233
+TRICORE_INS_MSUBADMS_H = 234
+TRICORE_INS_MSUBADM_H = 235
+TRICORE_INS_MSUBADRS_H = 236
+TRICORE_INS_MSUBADR_H = 237
+TRICORE_INS_MSUBADS_H = 238
+TRICORE_INS_MSUBAD_H = 239
+TRICORE_INS_MSUBMS_H = 240
+TRICORE_INS_MSUBMS_U = 241
+TRICORE_INS_MSUBMS = 242
+TRICORE_INS_MSUBM_H = 243
+TRICORE_INS_MSUBM_Q = 244
+TRICORE_INS_MSUBM_U = 245
+TRICORE_INS_MSUBM = 246
+TRICORE_INS_MSUBRS_H = 247
+TRICORE_INS_MSUBRS_Q = 248
+TRICORE_INS_MSUBR_H = 249
+TRICORE_INS_MSUBR_Q = 250
+TRICORE_INS_MSUBS_H = 251
+TRICORE_INS_MSUBS_Q = 252
+TRICORE_INS_MSUBS_U = 253
+TRICORE_INS_MSUBS = 254
+TRICORE_INS_MSUB_F = 255
+TRICORE_INS_MSUB_H = 256
+TRICORE_INS_MSUB_Q = 257
+TRICORE_INS_MSUB_U = 258
+TRICORE_INS_MSUB = 259
+TRICORE_INS_MTCR = 260
+TRICORE_INS_MULMS_H = 261
+TRICORE_INS_MULM_H = 262
+TRICORE_INS_MULM_U = 263
+TRICORE_INS_MULM = 264
+TRICORE_INS_MULR_H = 265
+TRICORE_INS_MULR_Q = 266
+TRICORE_INS_MULS_U = 267
+TRICORE_INS_MULS = 268
+TRICORE_INS_MUL_F = 269
+TRICORE_INS_MUL_H = 270
+TRICORE_INS_MUL_Q = 271
+TRICORE_INS_MUL_U = 272
+TRICORE_INS_MUL = 273
+TRICORE_INS_NAND_T = 274
+TRICORE_INS_NAND = 275
+TRICORE_INS_NEZ_A = 276
+TRICORE_INS_NE_A = 277
+TRICORE_INS_NE = 278
+TRICORE_INS_NOP = 279
+TRICORE_INS_NOR_T = 280
+TRICORE_INS_NOR = 281
+TRICORE_INS_NOT = 282
+TRICORE_INS_ORN_T = 283
+TRICORE_INS_ORN = 284
+TRICORE_INS_OR_ANDN_T = 285
+TRICORE_INS_OR_AND_T = 286
+TRICORE_INS_OR_EQ = 287
+TRICORE_INS_OR_GE_U = 288
+TRICORE_INS_OR_GE = 289
+TRICORE_INS_OR_LT_U = 290
+TRICORE_INS_OR_LT = 291
+TRICORE_INS_OR_NE = 292
+TRICORE_INS_OR_NOR_T = 293
+TRICORE_INS_OR_OR_T = 294
+TRICORE_INS_OR_T = 295
+TRICORE_INS_OR = 296
+TRICORE_INS_PACK = 297
+TRICORE_INS_PARITY = 298
+TRICORE_INS_POPCNT_W = 299
+TRICORE_INS_Q31TOF = 300
+TRICORE_INS_QSEED_F = 301
+TRICORE_INS_RESTORE = 302
+TRICORE_INS_RET = 303
+TRICORE_INS_RFE = 304
+TRICORE_INS_RFM = 305
+TRICORE_INS_RSLCX = 306
+TRICORE_INS_RSTV = 307
+TRICORE_INS_RSUBS_U = 308
+TRICORE_INS_RSUBS = 309
+TRICORE_INS_RSUB = 310
+TRICORE_INS_SAT_BU = 311
+TRICORE_INS_SAT_B = 312
+TRICORE_INS_SAT_HU = 313
+TRICORE_INS_SAT_H = 314
+TRICORE_INS_SELN_A = 315
+TRICORE_INS_SELN = 316
+TRICORE_INS_SEL_A = 317
+TRICORE_INS_SEL = 318
+TRICORE_INS_SHAS = 319
+TRICORE_INS_SHA_B = 320
+TRICORE_INS_SHA_H = 321
+TRICORE_INS_SHA = 322
+TRICORE_INS_SHUFFLE = 323
+TRICORE_INS_SH_ANDN_T = 324
+TRICORE_INS_SH_AND_T = 325
+TRICORE_INS_SH_B = 326
+TRICORE_INS_SH_EQ = 327
+TRICORE_INS_SH_GE_U = 328
+TRICORE_INS_SH_GE = 329
+TRICORE_INS_SH_H = 330
+TRICORE_INS_SH_LT_U = 331
+TRICORE_INS_SH_LT = 332
+TRICORE_INS_SH_NAND_T = 333
+TRICORE_INS_SH_NE = 334
+TRICORE_INS_SH_NOR_T = 335
+TRICORE_INS_SH_ORN_T = 336
+TRICORE_INS_SH_OR_T = 337
+TRICORE_INS_SH_XNOR_T = 338
+TRICORE_INS_SH_XOR_T = 339
+TRICORE_INS_SH = 340
+TRICORE_INS_STLCX = 341
+TRICORE_INS_STUCX = 342
+TRICORE_INS_ST_A = 343
+TRICORE_INS_ST_B = 344
+TRICORE_INS_ST_DA = 345
+TRICORE_INS_ST_D = 346
+TRICORE_INS_ST_H = 347
+TRICORE_INS_ST_Q = 348
+TRICORE_INS_ST_T = 349
+TRICORE_INS_ST_W = 350
+TRICORE_INS_SUBC = 351
+TRICORE_INS_SUBSC_A = 352
+TRICORE_INS_SUBS_BU = 353
+TRICORE_INS_SUBS_B = 354
+TRICORE_INS_SUBS_HU = 355
+TRICORE_INS_SUBS_H = 356
+TRICORE_INS_SUBS_U = 357
+TRICORE_INS_SUBS = 358
+TRICORE_INS_SUBX = 359
+TRICORE_INS_SUB_A = 360
+TRICORE_INS_SUB_B = 361
+TRICORE_INS_SUB_F = 362
+TRICORE_INS_SUB_H = 363
+TRICORE_INS_SUB = 364
+TRICORE_INS_SVLCX = 365
+TRICORE_INS_SWAPMSK_W = 366
+TRICORE_INS_SWAP_A = 367
+TRICORE_INS_SWAP_W = 368
+TRICORE_INS_SYSCALL = 369
+TRICORE_INS_TLBDEMAP = 370
+TRICORE_INS_TLBFLUSH_A = 371
+TRICORE_INS_TLBFLUSH_B = 372
+TRICORE_INS_TLBMAP = 373
+TRICORE_INS_TLBPROBE_A = 374
+TRICORE_INS_TLBPROBE_I = 375
+TRICORE_INS_TRAPSV = 376
+TRICORE_INS_TRAPV = 377
+TRICORE_INS_UNPACK = 378
+TRICORE_INS_UPDFL = 379
+TRICORE_INS_UTOF = 380
+TRICORE_INS_WAIT = 381
+TRICORE_INS_XNOR_T = 382
+TRICORE_INS_XNOR = 383
+TRICORE_INS_XOR_EQ = 384
+TRICORE_INS_XOR_GE_U = 385
+TRICORE_INS_XOR_GE = 386
+TRICORE_INS_XOR_LT_U = 387
+TRICORE_INS_XOR_LT = 388
+TRICORE_INS_XOR_NE = 389
+TRICORE_INS_XOR = 390
+TRICORE_INS_ENDING = 391
+
+# Group of TriCore instructions
+TRICORE_GRP_INVALID = 392
+
+# Generic groups
+TRICORE_GRP_CALL = 393
+TRICORE_GRP_JUMP = 394
+TRICORE_GRP_ENDING = 395
+
+TRICORE_FEATURE_INVALID = 0
+TRICORE_FEATURE_HasV110 = 128
+TRICORE_FEATURE_HasV120_UP = 129
+TRICORE_FEATURE_HasV130_UP = 130
+TRICORE_FEATURE_HasV161 = 131
+TRICORE_FEATURE_HasV160_UP = 132
+TRICORE_FEATURE_HasV131_UP = 133
+TRICORE_FEATURE_HasV161_UP = 134
+TRICORE_FEATURE_HasV162 = 135
+TRICORE_FEATURE_HasV162_UP = 136
+TRICORE_FEATURE_ENDING = 137
diff --git a/bindings/python/test_tricore.py b/bindings/python/test_tricore.py
new file mode 100755
index 0000000000..7fad11007e
--- /dev/null
+++ b/bindings/python/test_tricore.py
@@ -0,0 +1,65 @@
+#!/usr/bin/env python
+
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+from __future__ import print_function
+from capstone import *
+from capstone.tricore import *
+from xprint import to_x, to_hex
+
+TRICORE_CODE = b"\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19" \
+               b"\xff\xc0\x70\x19\xff\x20\x10"
+
+all_tests = (
+    (CS_ARCH_TRICORE, CS_MODE_TRICORE_162, TRICORE_CODE, "TriCore"),
+)
+
+
+def print_insn_detail(insn):
+    # print address, mnemonic and operands
+    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
+
+    # "data" instruction generated by SKIPDATA option has no detail
+    if insn.id == 0:
+        return
+
+    if len(insn.operands) > 0:
+        print("\top_count: %u" % len(insn.operands))
+        c = 0
+        for i in insn.operands:
+            if i.type == TRICORE_OP_REG:
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+            if i.type == TRICORE_OP_IMM:
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
+            if i.type == TRICORE_OP_MEM:
+                print("\t\toperands[%u].type: MEM" % c)
+                if i.mem.base != 0:
+                    print("\t\t\toperands[%u].mem.base: REG = %s" \
+                          % (c, insn.reg_name(i.mem.base)))
+                if i.mem.disp != 0:
+                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
+                          % (c, to_x(i.mem.disp)))
+            c += 1
+
+
+# ## Test class Cs
+def test_class():
+    for (arch, mode, code, comment) in all_tests:
+        print("*" * 16)
+        print("Platform: %s" % comment)
+        print("Code: %s" % to_hex(code))
+        print("Disasm:")
+
+        try:
+            md = Cs(arch, mode)
+            md.detail = True
+            for insn in md.disasm(code, 0x1000):
+                print_insn_detail(insn)
+                print()
+                print("0x%x:\n" % (insn.address + insn.size))
+        except CsError as e:
+            print("ERROR: %s" % e)
+
+
+if __name__ == '__main__':
+    test_class()
diff --git a/config.mk b/config.mk
index f82f834e66..a098de44f3 100644
--- a/config.mk
+++ b/config.mk
@@ -4,7 +4,7 @@
 ################################################################################
 # Specify which archs you want to compile in. By default, we build all archs.
 
-CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh
+CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore
 
 
 ################################################################################
diff --git a/cs.c b/cs.c
index 2588c340b8..1b7ba05f01 100644
--- a/cs.c
+++ b/cs.c
@@ -69,6 +69,7 @@
 #include "arch/MOS65XX/MOS65XXModule.h"
 #include "arch/BPF/BPFModule.h"
 #include "arch/SH/SHModule.h"
+#include "arch/TriCore/TriCoreModule.h"
 
 static const struct {
 	// constructor initialization
@@ -243,6 +244,17 @@ static const struct {
 #else
 	{ NULL, NULL, 0 },
 #endif
+#ifdef CAPSTONE_HAS_TRICORE
+	{
+		TRICORE_global_init,
+		TRICORE_option,
+		~(CS_MODE_TRICORE_110 | CS_MODE_TRICORE_120 | CS_MODE_TRICORE_130
+		| CS_MODE_TRICORE_131 | CS_MODE_TRICORE_160 | CS_MODE_TRICORE_161
+		| CS_MODE_TRICORE_162 | CS_MODE_LITTLE_ENDIAN),
+	},
+#else
+	{ NULL, NULL, 0 },
+#endif
 };
 
 // bitmask of enabled architectures
@@ -298,6 +310,9 @@ static const uint32_t all_arch = 0
 #ifdef CAPSTONE_HAS_SH
 	| (1 << CS_ARCH_SH)
 #endif
+#ifdef CAPSTONE_HAS_TRICORE
+	| (1 << CS_ARCH_TRICORE)
+#endif
 ;
 
 #if defined(CAPSTONE_USE_SYS_DYN_MEM)
@@ -368,9 +383,9 @@ bool CAPSTONE_API cs_support(int query)
 				    (1 << CS_ARCH_SYSZ)  | (1 << CS_ARCH_XCORE)      |
 				    (1 << CS_ARCH_M68K)  | (1 << CS_ARCH_TMS320C64X) |
 				    (1 << CS_ARCH_M680X) | (1 << CS_ARCH_EVM)        |
-				    (1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX)    | 
+				    (1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX)    |
 				    (1 << CS_ARCH_WASM)  | (1 << CS_ARCH_BPF)        |
-				    (1 << CS_ARCH_SH));
+				    (1 << CS_ARCH_SH)    | (1 << CS_ARCH_TRICORE));
 
 	if ((unsigned int)query < CS_ARCH_MAX)
 		return all_arch & (1 << query);
@@ -674,6 +689,10 @@ static uint8_t skipdata_size(cs_struct *handle)
 			return 4;
 		case CS_ARCH_SH:
 			return 2;
+		case CS_ARCH_TRICORE:
+			// TriCore instruction's length can be 2 or 4 bytes,
+			// so we just skip 2 bytes
+			return 2;
 	}
 }
 
@@ -1179,7 +1198,7 @@ bool CAPSTONE_API cs_disasm_iter(csh ud, const uint8_t **code, size_t *size,
 	return true;
 }
 
-// return friendly name of regiser in a string
+// return friendly name of register in a string
 CAPSTONE_EXPORT
 const char * CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
 {
@@ -1405,6 +1424,11 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type)
 				if (insn->detail->riscv.operands[i].type == (riscv_op_type)op_type)
 					count++;
 			break;
+		case CS_ARCH_TRICORE:
+			for (i = 0; i < insn->detail->tricore.op_count; i++)
+				if (insn->detail->tricore.operands[i].type == (tricore_op_type)op_type)
+					count++;
+			break;
 	}
 
 	return count;
@@ -1506,6 +1530,14 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type,
 					return i;
 			}
 			break;
+		case CS_ARCH_TRICORE:
+			for (i = 0; i < insn->detail->tricore.op_count; i++) {
+				if (insn->detail->tricore.operands[i].type == (tricore_op_type)op_type)
+					count++;
+				if (count == post)
+					return i;
+			}
+			break;
 		case CS_ARCH_M68K:
 			for (i = 0; i < insn->detail->m68k.op_count; i++) {
 				if (insn->detail->m68k.operands[i].type == (m68k_op_type)op_type)
diff --git a/cstool/cstool.c b/cstool/cstool.c
index 7e6347d990..68e9051563 100644
--- a/cstool/cstool.c
+++ b/cstool/cstool.c
@@ -104,8 +104,14 @@ static struct {
 	{ "sh4a", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU },
 	{ "sh4abe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU },
 	{ "sh4al-dsp", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU },
-	{ "sh4al-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU},
-
+	{ "sh4al-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU },
+	{ "tc110", CS_ARCH_TRICORE, CS_MODE_TRICORE_110 },
+	{ "tc120", CS_ARCH_TRICORE, CS_MODE_TRICORE_120 },
+	{ "tc130", CS_ARCH_TRICORE, CS_MODE_TRICORE_130 },
+	{ "tc131", CS_ARCH_TRICORE, CS_MODE_TRICORE_131 },
+	{ "tc160", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 },
+	{ "tc161", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 },
+	{ "tc162", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 },
 	{ NULL }
 };
 
@@ -126,6 +132,7 @@ void print_insn_detail_wasm(csh handle, cs_insn *ins);
 void print_insn_detail_mos65xx(csh handle, cs_insn *ins);
 void print_insn_detail_bpf(csh handle, cs_insn *ins);
 void print_insn_detail_sh(csh handle, cs_insn *ins);
+void print_insn_detail_tricore(csh handle, cs_insn *ins);
 
 static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins);
 
@@ -319,6 +326,16 @@ static void usage(char *prog)
 		printf("        sh4al-dspbe superh SH4AL-DSP big endian\n");
 	}
 
+	if (cs_support(CS_ARCH_TRICORE)) {
+		printf("        tc110       tricore V1.1\n");
+		printf("        tc120       tricore V1.2\n");
+		printf("        tc130       tricore V1.3\n");
+		printf("        tc131       tricore V1.3.1\n");
+		printf("        tc160       tricore V1.6\n");
+		printf("        tc161       tricore V1.6.1\n");
+		printf("        tc162       tricore V1.6.2\n");
+	}
+
 	printf("\nExtra options:\n");
 	printf("        -d show detailed information of the instructions\n");
 	printf("        -s decode in SKIPDATA mode\n");
@@ -382,6 +399,9 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
 		case CS_ARCH_SH:
 			print_insn_detail_sh(handle, ins);
 			break;
+		case CS_ARCH_TRICORE:
+			print_insn_detail_tricore(handle, ins);
+			break;
 		default: break;
 	}
 
@@ -477,7 +497,7 @@ int main(int argc, char **argv)
 				if (cs_support(CS_ARCH_EVM)) {
 					printf("evm=1 ");
 				}
-				
+
 				if (cs_support(CS_ARCH_WASM)) {
 					printf("wasm=1 ");
 				}
@@ -506,6 +526,10 @@ int main(int argc, char **argv)
 					printf("x86_reduce=1 ");
 				}
 
+				if (cs_support(CS_ARCH_TRICORE)) {
+					printf("tricore=1 ");
+				}
+
 				printf("\n");
 				return 0;
 			case 'h':
diff --git a/cstool/cstool_tricore.c b/cstool/cstool_tricore.c
new file mode 100644
index 0000000000..45b0f53b20
--- /dev/null
+++ b/cstool/cstool_tricore.c
@@ -0,0 +1,71 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <capstone/capstone.h>
+
+void print_insn_detail_tricore(csh handle, cs_insn *ins)
+{
+	cs_tricore *tricore;
+	int i;
+	cs_regs regs_read, regs_write;
+	uint8_t regs_read_count, regs_write_count;
+
+	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
+	if (ins->detail == NULL)
+		return;
+
+	tricore = &(ins->detail->tricore);
+
+	if (tricore->op_count)
+		printf("\top_count: %u\n", tricore->op_count);
+
+	for (i = 0; i < tricore->op_count; i++) {
+		cs_tricore_op *op = &(tricore->operands[i]);
+		switch ((int)op->type) {
+		default:
+			break;
+		case TRICORE_OP_REG:
+			printf("\t\toperands[%u].type: REG = %s\n", i,
+			       cs_reg_name(handle, op->reg));
+			break;
+		case TRICORE_OP_IMM:
+			printf("\t\toperands[%u].type: IMM = 0x%x\n", i,
+			       op->imm);
+			break;
+		case TRICORE_OP_MEM:
+			printf("\t\toperands[%u].type: MEM\n", i);
+			if (op->mem.base != TRICORE_REG_INVALID)
+				printf("\t\t\toperands[%u].mem.base: REG = %s\n",
+				       i, cs_reg_name(handle, op->mem.base));
+			if (op->mem.disp != 0)
+				printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i,
+				       op->mem.disp);
+			break;
+		}
+
+		// Print out all registers accessed by this instruction (either implicit or
+		// explicit)
+		if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
+				    regs_write, &regs_write_count)) {
+			if (regs_read_count) {
+				printf("\tRegisters read:");
+				for (i = 0; i < regs_read_count; i++) {
+					printf(" %s",
+					       cs_reg_name(handle,
+							   regs_read[i]));
+				}
+				printf("\n");
+			}
+
+			if (regs_write_count) {
+				printf("\tRegisters modified:");
+				for (i = 0; i < regs_write_count; i++) {
+					printf(" %s",
+					       cs_reg_name(handle,
+							   regs_write[i]));
+				}
+				printf("\n");
+			}
+		}
+	}
+}
\ No newline at end of file
diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h
index 0140c00131..d765d3f375 100644
--- a/include/capstone/capstone.h
+++ b/include/capstone/capstone.h
@@ -89,6 +89,7 @@ typedef enum cs_arch {
 	CS_ARCH_BPF,		///< Berkeley Packet Filter architecture (including eBPF)
 	CS_ARCH_RISCV,          ///< RISCV architecture
 	CS_ARCH_SH,             ///< SH architecture
+	CS_ARCH_TRICORE,	///< TriCore architecture
 	CS_ARCH_MAX,
 	CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
 } cs_arch;
@@ -151,7 +152,7 @@ typedef enum cs_mode {
 	CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02
 	CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02
 	CS_MODE_MOS65XX_65816 = 1 << 4, ///< MOS65XXX WDC 65816, 8-bit m/x
-	CS_MODE_MOS65XX_65816_LONG_M = (1 << 5), ///< MOS65XXX WDC 65816, 16-bit m, 8-bit x 
+	CS_MODE_MOS65XX_65816_LONG_M = (1 << 5), ///< MOS65XXX WDC 65816, 16-bit m, 8-bit x
 	CS_MODE_MOS65XX_65816_LONG_X = (1 << 6), ///< MOS65XXX WDC 65816, 8-bit m, 16-bit x
 	CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X,
 	CS_MODE_SH2 = 1 << 1,    ///< SH2
@@ -161,6 +162,13 @@ typedef enum cs_mode {
 	CS_MODE_SH4A = 1 << 5,   ///< SH4A
 	CS_MODE_SHFPU = 1 << 6,  ///< w/ FPU
 	CS_MODE_SHDSP = 1 << 7,  ///< w/ DSP
+	CS_MODE_TRICORE_110 = 1 << 1, ///< Tricore 1.1
+	CS_MODE_TRICORE_120 = 1 << 2, ///< Tricore 1.2
+	CS_MODE_TRICORE_130 = 1 << 3, ///< Tricore 1.3
+	CS_MODE_TRICORE_131 = 1 << 4, ///< Tricore 1.3.1
+	CS_MODE_TRICORE_160 = 1 << 5, ///< Tricore 1.6
+	CS_MODE_TRICORE_161 = 1 << 6, ///< Tricore 1.6.1
+	CS_MODE_TRICORE_162 = 1 << 7, ///< Tricore 1.6.2
 } cs_mode;
 
 typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);
@@ -289,6 +297,7 @@ typedef struct cs_opt_skipdata {
 	/// WASM:    1 bytes.
 	/// MOS65XX: 1 bytes.
 	/// BPF:     8 bytes.
+	/// TriCore: 2 bytes.
 	cs_skipdata_cb_t callback; 	// default value is NULL
 
 	/// User-defined data to be passed to @callback function pointer.
@@ -313,6 +322,7 @@ typedef struct cs_opt_skipdata {
 #include "mos65xx.h"
 #include "bpf.h"
 #include "sh.h"
+#include "tricore.h"
 
 /// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
 /// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))
@@ -348,6 +358,7 @@ typedef struct cs_detail {
 		cs_bpf bpf;	///< Berkeley Packet Filter architecture (including eBPF)
 		cs_riscv riscv; ///< RISCV architecture
 		cs_sh sh;        ///< SH architecture
+		cs_tricore tricore; ///< TriCore architecture
 	};
 } cs_detail;
 
diff --git a/include/capstone/tricore.h b/include/capstone/tricore.h
new file mode 100644
index 0000000000..aa63d65993
--- /dev/null
+++ b/include/capstone/tricore.h
@@ -0,0 +1,561 @@
+#ifndef CAPSTONE_TRICORE_H
+#define CAPSTONE_TRICORE_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable : 4201)
+#endif
+
+//> Operand type for instruction's operands
+typedef enum tricore_op_type {
+	TRICORE_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
+	TRICORE_OP_REG, // = CS_OP_REG (Register operand).
+	TRICORE_OP_IMM, // = CS_OP_IMM (Immediate operand).
+	TRICORE_OP_MEM, // = CS_OP_MEM (Memory operand).
+} tricore_op_type;
+
+// Instruction's operand referring to memory
+// This is associated with TRICORE_OP_MEM operand type above
+typedef struct tricore_op_mem {
+	uint8_t base; // base register
+	int32_t disp; // displacement/offset value
+} tricore_op_mem;
+
+// Instruction operand
+typedef struct cs_tricore_op {
+	tricore_op_type type; // operand type
+	union {
+		unsigned int reg; // register value for REG operand
+		int32_t imm; // immediate value for IMM operand
+		tricore_op_mem mem; // base/disp value for MEM operand
+	};
+} cs_tricore_op;
+
+// Instruction structure
+typedef struct cs_tricore {
+	// Number of operands of this instruction,
+	// or 0 when instruction has no operand.
+	uint8_t op_count;
+	cs_tricore_op operands[8]; // operands for this instruction.
+} cs_tricore;
+
+//> TriCore registers
+typedef enum tricore_reg {
+	// generate content <TriCoreGenCSRegEnum.inc> begin
+	// clang-format off
+
+	TRICORE_REG_INVALID = 0,
+	TRICORE_REG_FCX = 1,
+	TRICORE_REG_PC = 2,
+	TRICORE_REG_PCXI = 3,
+	TRICORE_REG_PSW = 4,
+	TRICORE_REG_A0 = 5,
+	TRICORE_REG_A1 = 6,
+	TRICORE_REG_A2 = 7,
+	TRICORE_REG_A3 = 8,
+	TRICORE_REG_A4 = 9,
+	TRICORE_REG_A5 = 10,
+	TRICORE_REG_A6 = 11,
+	TRICORE_REG_A7 = 12,
+	TRICORE_REG_A8 = 13,
+	TRICORE_REG_A9 = 14,
+	TRICORE_REG_A10 = 15,
+	TRICORE_REG_A11 = 16,
+	TRICORE_REG_A12 = 17,
+	TRICORE_REG_A13 = 18,
+	TRICORE_REG_A14 = 19,
+	TRICORE_REG_A15 = 20,
+	TRICORE_REG_D0 = 21,
+	TRICORE_REG_D1 = 22,
+	TRICORE_REG_D2 = 23,
+	TRICORE_REG_D3 = 24,
+	TRICORE_REG_D4 = 25,
+	TRICORE_REG_D5 = 26,
+	TRICORE_REG_D6 = 27,
+	TRICORE_REG_D7 = 28,
+	TRICORE_REG_D8 = 29,
+	TRICORE_REG_D9 = 30,
+	TRICORE_REG_D10 = 31,
+	TRICORE_REG_D11 = 32,
+	TRICORE_REG_D12 = 33,
+	TRICORE_REG_D13 = 34,
+	TRICORE_REG_D14 = 35,
+	TRICORE_REG_D15 = 36,
+	TRICORE_REG_E0 = 37,
+	TRICORE_REG_E2 = 38,
+	TRICORE_REG_E4 = 39,
+	TRICORE_REG_E6 = 40,
+	TRICORE_REG_E8 = 41,
+	TRICORE_REG_E10 = 42,
+	TRICORE_REG_E12 = 43,
+	TRICORE_REG_E14 = 44,
+	TRICORE_REG_P0 = 45,
+	TRICORE_REG_P2 = 46,
+	TRICORE_REG_P4 = 47,
+	TRICORE_REG_P6 = 48,
+	TRICORE_REG_P8 = 49,
+	TRICORE_REG_P10 = 50,
+	TRICORE_REG_P12 = 51,
+	TRICORE_REG_P14 = 52,
+	TRICORE_REG_A0_A1 = 53,
+	TRICORE_REG_A2_A3 = 54,
+	TRICORE_REG_A4_A5 = 55,
+	TRICORE_REG_A6_A7 = 56,
+	TRICORE_REG_A8_A9 = 57,
+	TRICORE_REG_A10_A11 = 58,
+	TRICORE_REG_A12_A13 = 59,
+	TRICORE_REG_A14_A15 = 60,
+	TRICORE_REG_ENDING, // 61
+
+	// clang-format on
+	// generate content <TriCoreGenCSRegEnum.inc> end
+} tricore_reg;
+
+//> TriCore instruction
+typedef enum tricore_insn {
+	TRICORE_INS_INVALID = 0,
+	// generate content <TriCoreGenCSInsnEnum.inc> begin
+	// clang-format off
+
+	TRICORE_INS_XOR_T,
+	TRICORE_INS_ABSDIFS_B,
+	TRICORE_INS_ABSDIFS_H,
+	TRICORE_INS_ABSDIFS,
+	TRICORE_INS_ABSDIF_B,
+	TRICORE_INS_ABSDIF_H,
+	TRICORE_INS_ABSDIF,
+	TRICORE_INS_ABSS_B,
+	TRICORE_INS_ABSS_H,
+	TRICORE_INS_ABSS,
+	TRICORE_INS_ABS_B,
+	TRICORE_INS_ABS_H,
+	TRICORE_INS_ABS,
+	TRICORE_INS_ADDC,
+	TRICORE_INS_ADDIH_A,
+	TRICORE_INS_ADDIH,
+	TRICORE_INS_ADDI,
+	TRICORE_INS_ADDSC_AT,
+	TRICORE_INS_ADDSC_A,
+	TRICORE_INS_ADDS_BU,
+	TRICORE_INS_ADDS_B,
+	TRICORE_INS_ADDS_H,
+	TRICORE_INS_ADDS_HU,
+	TRICORE_INS_ADDS_U,
+	TRICORE_INS_ADDS,
+	TRICORE_INS_ADDX,
+	TRICORE_INS_ADD_A,
+	TRICORE_INS_ADD_B,
+	TRICORE_INS_ADD_F,
+	TRICORE_INS_ADD_H,
+	TRICORE_INS_ADD,
+	TRICORE_INS_ANDN_T,
+	TRICORE_INS_ANDN,
+	TRICORE_INS_AND_ANDN_T,
+	TRICORE_INS_AND_AND_T,
+	TRICORE_INS_AND_EQ,
+	TRICORE_INS_AND_GE_U,
+	TRICORE_INS_AND_GE,
+	TRICORE_INS_AND_LT_U,
+	TRICORE_INS_AND_LT,
+	TRICORE_INS_AND_NE,
+	TRICORE_INS_AND_NOR_T,
+	TRICORE_INS_AND_OR_T,
+	TRICORE_INS_AND_T,
+	TRICORE_INS_AND,
+	TRICORE_INS_BISR,
+	TRICORE_INS_BMERGE,
+	TRICORE_INS_BSPLIT,
+	TRICORE_INS_CACHEA_I,
+	TRICORE_INS_CACHEA_WI,
+	TRICORE_INS_CACHEA_W,
+	TRICORE_INS_CACHEI_I,
+	TRICORE_INS_CACHEI_WI,
+	TRICORE_INS_CACHEI_W,
+	TRICORE_INS_CADDN_A,
+	TRICORE_INS_CADDN,
+	TRICORE_INS_CADD_A,
+	TRICORE_INS_CADD,
+	TRICORE_INS_CALLA,
+	TRICORE_INS_CALLI,
+	TRICORE_INS_CALL,
+	TRICORE_INS_CLO_B,
+	TRICORE_INS_CLO_H,
+	TRICORE_INS_CLO,
+	TRICORE_INS_CLS_B,
+	TRICORE_INS_CLS_H,
+	TRICORE_INS_CLS,
+	TRICORE_INS_CLZ_B,
+	TRICORE_INS_CLZ_H,
+	TRICORE_INS_CLZ,
+	TRICORE_INS_CMOVN,
+	TRICORE_INS_CMOV,
+	TRICORE_INS_CMPSWAP_W,
+	TRICORE_INS_CMP_F,
+	TRICORE_INS_CRC32B_W,
+	TRICORE_INS_CRC32L_W,
+	TRICORE_INS_CRC32_B,
+	TRICORE_INS_CRCN,
+	TRICORE_INS_CSUBN_A,
+	TRICORE_INS_CSUBN,
+	TRICORE_INS_CSUB_A,
+	TRICORE_INS_CSUB,
+	TRICORE_INS_DEBUG,
+	TRICORE_INS_DEXTR,
+	TRICORE_INS_DIFSC_A,
+	TRICORE_INS_DISABLE,
+	TRICORE_INS_DIV_F,
+	TRICORE_INS_DIV_U,
+	TRICORE_INS_DIV,
+	TRICORE_INS_DSYNC,
+	TRICORE_INS_DVADJ,
+	TRICORE_INS_DVINIT_BU,
+	TRICORE_INS_DVINIT_B,
+	TRICORE_INS_DVINIT_HU,
+	TRICORE_INS_DVINIT_H,
+	TRICORE_INS_DVINIT_U,
+	TRICORE_INS_DVINIT,
+	TRICORE_INS_DVSTEP_U,
+	TRICORE_INS_DVSTEP,
+	TRICORE_INS_ENABLE,
+	TRICORE_INS_EQANY_B,
+	TRICORE_INS_EQANY_H,
+	TRICORE_INS_EQZ_A,
+	TRICORE_INS_EQ_A,
+	TRICORE_INS_EQ_B,
+	TRICORE_INS_EQ_H,
+	TRICORE_INS_EQ_W,
+	TRICORE_INS_EQ,
+	TRICORE_INS_EXTR_U,
+	TRICORE_INS_EXTR,
+	TRICORE_INS_FCALLA,
+	TRICORE_INS_FCALLI,
+	TRICORE_INS_FCALL,
+	TRICORE_INS_FRET,
+	TRICORE_INS_FTOHP,
+	TRICORE_INS_FTOIZ,
+	TRICORE_INS_FTOI,
+	TRICORE_INS_FTOQ31Z,
+	TRICORE_INS_FTOQ31,
+	TRICORE_INS_FTOUZ,
+	TRICORE_INS_FTOU,
+	TRICORE_INS_GE_A,
+	TRICORE_INS_GE_U,
+	TRICORE_INS_GE,
+	TRICORE_INS_HPTOF,
+	TRICORE_INS_IMASK,
+	TRICORE_INS_INSERT,
+	TRICORE_INS_INSN_T,
+	TRICORE_INS_INS_T,
+	TRICORE_INS_ISYNC,
+	TRICORE_INS_ITOF,
+	TRICORE_INS_IXMAX_U,
+	TRICORE_INS_IXMAX,
+	TRICORE_INS_IXMIN_U,
+	TRICORE_INS_IXMIN,
+	TRICORE_INS_JA,
+	TRICORE_INS_JEQ_A,
+	TRICORE_INS_JEQ,
+	TRICORE_INS_JGEZ,
+	TRICORE_INS_JGE_U,
+	TRICORE_INS_JGE,
+	TRICORE_INS_JGTZ,
+	TRICORE_INS_JI,
+	TRICORE_INS_JLA,
+	TRICORE_INS_JLEZ,
+	TRICORE_INS_JLI,
+	TRICORE_INS_JLTZ,
+	TRICORE_INS_JLT_U,
+	TRICORE_INS_JLT,
+	TRICORE_INS_JL,
+	TRICORE_INS_JNED,
+	TRICORE_INS_JNEI,
+	TRICORE_INS_JNE_A,
+	TRICORE_INS_JNE,
+	TRICORE_INS_JNZ_A,
+	TRICORE_INS_JNZ_T,
+	TRICORE_INS_JNZ,
+	TRICORE_INS_JZ_A,
+	TRICORE_INS_JZ_T,
+	TRICORE_INS_JZ,
+	TRICORE_INS_J,
+	TRICORE_INS_LDLCX,
+	TRICORE_INS_LDMST,
+	TRICORE_INS_LDUCX,
+	TRICORE_INS_LD_A,
+	TRICORE_INS_LD_BU,
+	TRICORE_INS_LD_B,
+	TRICORE_INS_LD_DA,
+	TRICORE_INS_LD_D,
+	TRICORE_INS_LD_HU,
+	TRICORE_INS_LD_H,
+	TRICORE_INS_LD_Q,
+	TRICORE_INS_LD_W,
+	TRICORE_INS_LEA,
+	TRICORE_INS_LHA,
+	TRICORE_INS_LOOPU,
+	TRICORE_INS_LOOP,
+	TRICORE_INS_LT_A,
+	TRICORE_INS_LT_B,
+	TRICORE_INS_LT_BU,
+	TRICORE_INS_LT_H,
+	TRICORE_INS_LT_HU,
+	TRICORE_INS_LT_U,
+	TRICORE_INS_LT_W,
+	TRICORE_INS_LT_WU,
+	TRICORE_INS_LT,
+	TRICORE_INS_MADDMS_H,
+	TRICORE_INS_MADDMS_U,
+	TRICORE_INS_MADDMS,
+	TRICORE_INS_MADDM_H,
+	TRICORE_INS_MADDM_Q,
+	TRICORE_INS_MADDM_U,
+	TRICORE_INS_MADDM,
+	TRICORE_INS_MADDRS_H,
+	TRICORE_INS_MADDRS_Q,
+	TRICORE_INS_MADDR_H,
+	TRICORE_INS_MADDR_Q,
+	TRICORE_INS_MADDSUMS_H,
+	TRICORE_INS_MADDSUM_H,
+	TRICORE_INS_MADDSURS_H,
+	TRICORE_INS_MADDSUR_H,
+	TRICORE_INS_MADDSUS_H,
+	TRICORE_INS_MADDSU_H,
+	TRICORE_INS_MADDS_H,
+	TRICORE_INS_MADDS_Q,
+	TRICORE_INS_MADDS_U,
+	TRICORE_INS_MADDS,
+	TRICORE_INS_MADD_F,
+	TRICORE_INS_MADD_H,
+	TRICORE_INS_MADD_Q,
+	TRICORE_INS_MADD_U,
+	TRICORE_INS_MADD,
+	TRICORE_INS_MAX_B,
+	TRICORE_INS_MAX_BU,
+	TRICORE_INS_MAX_H,
+	TRICORE_INS_MAX_HU,
+	TRICORE_INS_MAX_U,
+	TRICORE_INS_MAX,
+	TRICORE_INS_MFCR,
+	TRICORE_INS_MIN_B,
+	TRICORE_INS_MIN_BU,
+	TRICORE_INS_MIN_H,
+	TRICORE_INS_MIN_HU,
+	TRICORE_INS_MIN_U,
+	TRICORE_INS_MIN,
+	TRICORE_INS_MOVH_A,
+	TRICORE_INS_MOVH,
+	TRICORE_INS_MOVZ_A,
+	TRICORE_INS_MOV_AA,
+	TRICORE_INS_MOV_A,
+	TRICORE_INS_MOV_D,
+	TRICORE_INS_MOV_U,
+	TRICORE_INS_MOV,
+	TRICORE_INS_MSUBADMS_H,
+	TRICORE_INS_MSUBADM_H,
+	TRICORE_INS_MSUBADRS_H,
+	TRICORE_INS_MSUBADR_H,
+	TRICORE_INS_MSUBADS_H,
+	TRICORE_INS_MSUBAD_H,
+	TRICORE_INS_MSUBMS_H,
+	TRICORE_INS_MSUBMS_U,
+	TRICORE_INS_MSUBMS,
+	TRICORE_INS_MSUBM_H,
+	TRICORE_INS_MSUBM_Q,
+	TRICORE_INS_MSUBM_U,
+	TRICORE_INS_MSUBM,
+	TRICORE_INS_MSUBRS_H,
+	TRICORE_INS_MSUBRS_Q,
+	TRICORE_INS_MSUBR_H,
+	TRICORE_INS_MSUBR_Q,
+	TRICORE_INS_MSUBS_H,
+	TRICORE_INS_MSUBS_Q,
+	TRICORE_INS_MSUBS_U,
+	TRICORE_INS_MSUBS,
+	TRICORE_INS_MSUB_F,
+	TRICORE_INS_MSUB_H,
+	TRICORE_INS_MSUB_Q,
+	TRICORE_INS_MSUB_U,
+	TRICORE_INS_MSUB,
+	TRICORE_INS_MTCR,
+	TRICORE_INS_MULMS_H,
+	TRICORE_INS_MULM_H,
+	TRICORE_INS_MULM_U,
+	TRICORE_INS_MULM,
+	TRICORE_INS_MULR_H,
+	TRICORE_INS_MULR_Q,
+	TRICORE_INS_MULS_U,
+	TRICORE_INS_MULS,
+	TRICORE_INS_MUL_F,
+	TRICORE_INS_MUL_H,
+	TRICORE_INS_MUL_Q,
+	TRICORE_INS_MUL_U,
+	TRICORE_INS_MUL,
+	TRICORE_INS_NAND_T,
+	TRICORE_INS_NAND,
+	TRICORE_INS_NEZ_A,
+	TRICORE_INS_NE_A,
+	TRICORE_INS_NE,
+	TRICORE_INS_NOP,
+	TRICORE_INS_NOR_T,
+	TRICORE_INS_NOR,
+	TRICORE_INS_NOT,
+	TRICORE_INS_ORN_T,
+	TRICORE_INS_ORN,
+	TRICORE_INS_OR_ANDN_T,
+	TRICORE_INS_OR_AND_T,
+	TRICORE_INS_OR_EQ,
+	TRICORE_INS_OR_GE_U,
+	TRICORE_INS_OR_GE,
+	TRICORE_INS_OR_LT_U,
+	TRICORE_INS_OR_LT,
+	TRICORE_INS_OR_NE,
+	TRICORE_INS_OR_NOR_T,
+	TRICORE_INS_OR_OR_T,
+	TRICORE_INS_OR_T,
+	TRICORE_INS_OR,
+	TRICORE_INS_PACK,
+	TRICORE_INS_PARITY,
+	TRICORE_INS_POPCNT_W,
+	TRICORE_INS_Q31TOF,
+	TRICORE_INS_QSEED_F,
+	TRICORE_INS_RESTORE,
+	TRICORE_INS_RET,
+	TRICORE_INS_RFE,
+	TRICORE_INS_RFM,
+	TRICORE_INS_RSLCX,
+	TRICORE_INS_RSTV,
+	TRICORE_INS_RSUBS_U,
+	TRICORE_INS_RSUBS,
+	TRICORE_INS_RSUB,
+	TRICORE_INS_SAT_BU,
+	TRICORE_INS_SAT_B,
+	TRICORE_INS_SAT_HU,
+	TRICORE_INS_SAT_H,
+	TRICORE_INS_SELN_A,
+	TRICORE_INS_SELN,
+	TRICORE_INS_SEL_A,
+	TRICORE_INS_SEL,
+	TRICORE_INS_SHAS,
+	TRICORE_INS_SHA_B,
+	TRICORE_INS_SHA_H,
+	TRICORE_INS_SHA,
+	TRICORE_INS_SHUFFLE,
+	TRICORE_INS_SH_ANDN_T,
+	TRICORE_INS_SH_AND_T,
+	TRICORE_INS_SH_B,
+	TRICORE_INS_SH_EQ,
+	TRICORE_INS_SH_GE_U,
+	TRICORE_INS_SH_GE,
+	TRICORE_INS_SH_H,
+	TRICORE_INS_SH_LT_U,
+	TRICORE_INS_SH_LT,
+	TRICORE_INS_SH_NAND_T,
+	TRICORE_INS_SH_NE,
+	TRICORE_INS_SH_NOR_T,
+	TRICORE_INS_SH_ORN_T,
+	TRICORE_INS_SH_OR_T,
+	TRICORE_INS_SH_XNOR_T,
+	TRICORE_INS_SH_XOR_T,
+	TRICORE_INS_SH,
+	TRICORE_INS_STLCX,
+	TRICORE_INS_STUCX,
+	TRICORE_INS_ST_A,
+	TRICORE_INS_ST_B,
+	TRICORE_INS_ST_DA,
+	TRICORE_INS_ST_D,
+	TRICORE_INS_ST_H,
+	TRICORE_INS_ST_Q,
+	TRICORE_INS_ST_T,
+	TRICORE_INS_ST_W,
+	TRICORE_INS_SUBC,
+	TRICORE_INS_SUBSC_A,
+	TRICORE_INS_SUBS_BU,
+	TRICORE_INS_SUBS_B,
+	TRICORE_INS_SUBS_HU,
+	TRICORE_INS_SUBS_H,
+	TRICORE_INS_SUBS_U,
+	TRICORE_INS_SUBS,
+	TRICORE_INS_SUBX,
+	TRICORE_INS_SUB_A,
+	TRICORE_INS_SUB_B,
+	TRICORE_INS_SUB_F,
+	TRICORE_INS_SUB_H,
+	TRICORE_INS_SUB,
+	TRICORE_INS_SVLCX,
+	TRICORE_INS_SWAPMSK_W,
+	TRICORE_INS_SWAP_A,
+	TRICORE_INS_SWAP_W,
+	TRICORE_INS_SYSCALL,
+	TRICORE_INS_TLBDEMAP,
+	TRICORE_INS_TLBFLUSH_A,
+	TRICORE_INS_TLBFLUSH_B,
+	TRICORE_INS_TLBMAP,
+	TRICORE_INS_TLBPROBE_A,
+	TRICORE_INS_TLBPROBE_I,
+	TRICORE_INS_TRAPSV,
+	TRICORE_INS_TRAPV,
+	TRICORE_INS_UNPACK,
+	TRICORE_INS_UPDFL,
+	TRICORE_INS_UTOF,
+	TRICORE_INS_WAIT,
+	TRICORE_INS_XNOR_T,
+	TRICORE_INS_XNOR,
+	TRICORE_INS_XOR_EQ,
+	TRICORE_INS_XOR_GE_U,
+	TRICORE_INS_XOR_GE,
+	TRICORE_INS_XOR_LT_U,
+	TRICORE_INS_XOR_LT,
+	TRICORE_INS_XOR_NE,
+	TRICORE_INS_XOR,
+
+	// clang-format on
+	// generate content <TriCoreGenCSInsnEnum.inc> end
+	TRICORE_INS_ENDING, // <-- mark the end of the list of instructions
+} tricore_insn;
+
+//> Group of TriCore instructions
+typedef enum tricore_insn_group {
+	TRICORE_GRP_INVALID, ///< = CS_GRP_INVALID
+	//> Generic groups
+	TRICORE_GRP_CALL, ///< = CS_GRP_CALL
+	TRICORE_GRP_JUMP, ///< = CS_GRP_JUMP
+	TRICORE_GRP_ENDING, ///< = mark the end of the list of groups
+} tricore_insn_group;
+
+typedef enum tricore_feature_t {
+	TRICORE_FEATURE_INVALID = 0,
+	// generate content <TriCoreGenCSFeatureEnum.inc> begin
+	// clang-format off
+
+	TRICORE_FEATURE_HasV110 = 128,
+	TRICORE_FEATURE_HasV120_UP,
+	TRICORE_FEATURE_HasV130_UP,
+	TRICORE_FEATURE_HasV161,
+	TRICORE_FEATURE_HasV160_UP,
+	TRICORE_FEATURE_HasV131_UP,
+	TRICORE_FEATURE_HasV161_UP,
+	TRICORE_FEATURE_HasV162,
+	TRICORE_FEATURE_HasV162_UP,
+
+	// clang-format on
+	// generate content <TriCoreGenCSFeatureEnum.inc> end
+	TRICORE_FEATURE_ENDING, // <-- mark the end of the list of features
+} tricore_feature;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/suite/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.cs b/suite/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.cs
new file mode 100644
index 0000000000..28dcc023e5
--- /dev/null
+++ b/suite/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.cs
@@ -0,0 +1,1162 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None
+0x40,0x4f           = mov.aa	%a15, %a4
+0x02,0x48           = mov	%d8, %d4
+# 0x6d,0xff,0x9d,0xff = call	-0xc6
+0x02,0x29           = mov	%d9, %d2
+0x02,0x94           = mov	%d4, %d9
+# 0x6d,0xff,0x02,0xfe = call	-0x3fc
+0xda,0x20           = mov	%d15, 32
+# 0x7f,0xf8,0x0b,0x80 = jge.u	%d8, %d15, 0x16
+# 0x09,0xff,0x08,0x29 = ld.w	%d15, [%a15]136
+0x82,0x10           = mov	%d0, 1
+0x0f,0x80,0x10,0x00 = sha	%d0, %d0, %d8
+0xa6,0x0f           = or	%d15, %d0
+# 0x89,0xff,0x08,0x29 = st.w	[%a15]136, %d15
+# 0x3c,0x0b           = j	0x16
+# 0x09,0xf0,0x0c,0x29 = ld.w	%d0, [%a15]140
+0x82,0x11           = mov	%d1, 1
+0x8f,0xf8,0x01,0xf1 = and	%d15, %d8, 31
+0x0f,0xf1,0x10,0x10 = sha	%d1, %d1, %d15
+0xa6,0x10           = or	%d0, %d1
+# 0x89,0xf0,0x0c,0x29 = st.w	[%a15]140, %d0
+# 0x6d,0xff,0xb3,0xff = call	-0x9a
+0x02,0x5f           = mov	%d15, %d5
+# 0xff,0x88,0x1f,0x80 = jge.u	%d8, 8, 0x3e
+0x3b,0xf0,0x01,0x40 = mov	%d4, 31
+0x40,0xf4           = mov.aa	%a4, %a15
+# 0x6d,0x00,0x1b,0x00 = call	0x36
+0x8b,0x08,0x01,0x10 = add	%d1, %d8, 16
+0x0f,0x10,0x10,0x00 = sha	%d0, %d0, %d1
+# 0x5e,0x17           = jne	%d15, 1, 0xe
+# 0x09,0xff,0x00,0x29 = ld.w	%d15, [%a15]128
+# 0x89,0xff,0x00,0x29 = st.w	[%a15]128, %d15
+# 0x3c,0x08           = j	0x10
+0x82,0xf1           = mov	%d1, -1
+0xc6,0x10           = xor	%d0, %d1
+0x26,0x0f           = and	%d15, %d0
+# 0x6d,0xff,0xbe,0xff = call	-0x84
+# 0x6d,0xff,0x58,0xff = call	-0x150
+# 0x6d,0xff,0xbd,0xfd = call	-0x486
+# 0x7f,0xf8,0x0d,0x80 = jge.u	%d8, %d15, 0x1a
+# 0x3c,0x0d           = j	0x1a
+0x82,0xff           = mov	%d15, -1
+0xc6,0xf1           = xor	%d1, %d15
+0x26,0x10           = and	%d0, %d1
+# 0x6d,0xff,0x6a,0xff = call	-0x12c
+# 0x6d,0xff,0x94,0xfa = call	-0xad8
+# 0x09,0xff,0x40,0x28 = ld.bu	%d15, [%a15]128
+0x16,0x1f           = and	%d15, 31
+0xc2,0x1f           = add	%d15, 1
+0x4b,0x0f,0x61,0xf1 = utof	%d15, %d15
+0x4b,0xf2,0x51,0x20 = div.f	%d2, %d2, %d15
+# 0x3c,0x01           = j	0x2
+# 0x6d,0xff,0x87,0xfa = call	-0xaf2
+# 0x09,0xff,0x41,0x28 = ld.bu	%d15, [%a15]129
+0x16,0x03           = and	%d15, 3
+# 0xbf,0x45,0x0b,0x80 = jlt.u	%d5, 4, 0x16
+0xc2,0xc5           = add	%d5, -4
+# 0x6f,0x04,0x05,0x00 = jz.t	%d4, 0, 0xa
+0x3b,0x90,0x00,0x40 = mov	%d4, 9
+# 0x3c,0x03           = j	0x6
+0x3b,0x80,0x00,0x40 = mov	%d4, 8
+0xda,0x04           = mov	%d15, 4
+0x03,0xf4,0x0a,0xf5 = madd	%d15, %d5, %d4, %d15
+0x53,0x4f,0x20,0xf0 = mul	%d15, %d15, 4
+0x91,0x00,0x00,0xf8 = movh.a	%a15, 32768
+0xd9,0xff,0xa8,0x92 = lea	%a15, [%a15]10856
+0x10,0xff           = addsc.a	%a15, %a15, %d15, 0
+# 0x54,0xff           = ld.w	%d15, [%a15]
+0x60,0xf2           = mov.a	%a2, %d15
+0x37,0x04,0x68,0x00 = extr.u	%d0, %d4, 0, 8
+0x37,0x0f,0x02,0xf4 = insert	%d15, %d15, %d0, 8, 2
+0x37,0x0f,0x81,0xf7 = insert	%d15, %d15, %d0, 15, 1
+# 0x6d,0xff,0x9a,0xff = call	-0xcc
+# 0x6d,0xff,0x4e,0xff = call	-0x164
+0x37,0x0f,0x05,0xf0 = insert	%d15, %d15, %d0, 0, 5
+# 0x6d,0xff,0x83,0xff = call	-0xfa
+# 0x6d,0xff,0x37,0xff = call	-0x192
+0x02,0x4f           = mov	%d15, %d4
+# 0x6d,0xff,0x32,0xfa = call	-0xb9c
+0x4b,0x02,0x71,0x01 = ftouz	%d0, %d2
+0x4b,0xf0,0x11,0x22 = div.u	%e2, %d0, %d15
+0x9a,0xf2           = add	%d15, %d2, -1
+0x8b,0x3f,0x20,0x43 = min.u	%d4, %d15, 3
+0x9a,0x14           = add	%d15, %d4, 1
+0x4b,0xf0,0x11,0x82 = div.u	%e8, %d0, %d15
+# 0x6d,0xff,0xc3,0xff = call	-0x7a
+0x02,0x82           = mov	%d2, %d8
+# 0x6d,0xff,0x1e,0xfa = call	-0xbc4
+0x8f,0x20,0x00,0x10 = sh	%d1, %d0, 2
+0x4b,0xf1,0x11,0x22 = div.u	%e2, %d1, %d15
+0x9a,0x22           = add	%d15, %d2, 2
+0x06,0xef           = sh	%d15, -2
+0xc2,0xff           = add	%d15, -1
+0x8b,0xff,0x21,0xf3 = min.u	%d15, %d15, 31
+0x92,0x11           = add	%d1, %d15, 1
+0x4b,0x10,0x11,0x82 = div.u	%e8, %d0, %d1
+0x3b,0x00,0xd0,0x12 = mov	%d1, 11520
+0x9b,0x11,0x13,0x10 = addih	%d1, %d1, 305
+# 0x7f,0x81,0x0a,0x80 = jge.u	%d1, %d8, 0x14
+0x4b,0x10,0x11,0x02 = div.u	%e0, %d0, %d1
+0x02,0x08           = mov	%d8, %d0
+0x3b,0x90,0xd0,0x03 = mov	%d0, 15625
+0x06,0x50           = sh	%d0, 5
+# 0x3f,0x08,0x08,0x80 = jlt.u	%d8, %d0, 0x10
+0x3b,0x00,0xd0,0x02 = mov	%d0, 11520
+0x9b,0x10,0x13,0x00 = addih	%d0, %d0, 305
+# 0x7f,0x80,0x04,0x80 = jge.u	%d0, %d8, 0x8
+0x82,0x08           = mov	%d8, 0
+# 0x3c,0x05           = j	0xa
+0x02,0xf4           = mov	%d4, %d15
+# 0x6d,0xff,0xa6,0xff = call	-0xb4
+0x37,0x4f,0x01,0xf7 = insert	%d15, %d15, %d4, 14, 1
+# 0x6d,0xff,0x26,0xff = call	-0x1b4
+# 0x6d,0xff,0xda,0xfe = call	-0x24c
+# 0xdf,0x04,0x31,0x00 = jeq	%d4, 0, 0x62
+# 0x4c,0x41           = ld.w	%d15, [%a4]4
+0x8b,0x87,0x01,0x00 = add	%d0, %d7, 24
+0x0f,0x04,0x10,0x40 = sha	%d4, %d4, %d0
+0xa6,0x4f           = or	%d15, %d4
+# 0x6c,0x41           = st.w	[%a4]4, %d15
+0x82,0x30           = mov	%d0, 3
+0x53,0x47,0x20,0x10 = mul	%d1, %d7, 4
+0x0f,0x10,0x00,0x00 = sh	%d0, %d0, %d1
+0x53,0x47,0x20,0x00 = mul	%d0, %d7, 4
+0x0f,0x05,0x10,0x50 = sha	%d5, %d5, %d0
+0xa6,0x5f           = or	%d15, %d5
+# 0x76,0x6b           = jz	%d6, 0x16
+0xc2,0x31           = add	%d1, 3
+# 0x3c,0x0c           = j	0x18
+0x8b,0x87,0x01,0x10 = add	%d1, %d7, 24
+# 0x6d,0xff,0xdc,0xfe = call	-0x248
+# 0x09,0xff,0x43,0x28 = ld.bu	%d15, [%a15]131
+0x96,0x80           = or	%d15, 128
+# 0x89,0xff,0x03,0x28 = st.b	[%a15]131, %d15
+# 0x6d,0xff,0x8d,0xfe = call	-0x2e6
+0x82,0x00           = mov	%d0, 0
+0x82,0x01           = mov	%d1, 0
+# 0x3c,0x0e           = j	0x1c
+0x3b,0x00,0x40,0xf0 = mov	%d15, 1024
+0xe2,0x1f           = mul	%d15, %d1
+0x10,0xf2           = addsc.a	%a2, %a15, %d15, 0
+# 0x39,0x2f,0x43,0x20 = ld.bu	%d15, [%a2]1155
+0x37,0x0f,0x61,0xf2 = extr.u	%d15, %d15, 4, 1
+# 0x6e,0x03           = jz	%d15, 0x6
+0xc2,0x11           = add	%d1, 1
+# 0xbf,0x81,0xf3,0xff = jlt.u	%d1, 8, -0x1a
+# 0xdf,0x10,0xee,0x7f = jeq	%d0, 1, -0x24
+0x40,0x4c           = mov.aa	%a12, %a4
+0x40,0x5f           = mov.aa	%a15, %a5
+# 0xc8,0x52           = ld.a	%a2, [%a15]20
+# 0xd4,0x2d           = ld.a	%a13, [%a2]
+# 0x09,0x2e,0x84,0x09 = ld.a	%a14, [%a2]4
+# 0x89,0xc2,0x84,0x09 = st.a	[%a12]4, %a2
+# 0x09,0xc2,0x84,0x09 = ld.a	%a2, [%a12]4
+# 0x09,0x29,0x48,0x08 = ld.bu	%d9, [%a2]8
+# 0x09,0xfa,0x0c,0x08 = ld.b	%d10, [%a15]12
+0x40,0xd4           = mov.aa	%a4, %a13
+# 0x6d,0xff,0xa6,0xfe = call	-0x2b4
+# 0x08,0xe0           = ld.bu	%d0, [%a15]14
+0x53,0x4a,0x20,0xf0 = mul	%d15, %d10, 4
+0x10,0xe2           = addsc.a	%a2, %a14, %d15, 0
+0x10,0xe4           = addsc.a	%a4, %a14, %d15, 0
+# 0x09,0x41,0x41,0x68 = ld.bu	%d1, [%a4]385
+0x37,0x01,0x81,0x01 = insert	%d0, %d1, %d0, 3, 1
+# 0x89,0x20,0x01,0x68 = st.b	[%a2]385, %d0
+# 0x08,0xf0           = ld.bu	%d0, [%a15]15
+# 0x09,0x4f,0x42,0x68 = ld.bu	%d15, [%a4]386
+0x37,0x0f,0x04,0xf0 = insert	%d15, %d15, %d0, 0, 4
+# 0x89,0x2f,0x02,0x68 = st.b	[%a2]386, %d15
+# 0x09,0xf0,0x50,0x08 = ld.bu	%d0, [%a15]16
+# 0x09,0x4f,0x40,0x68 = ld.bu	%d15, [%a4]384
+0x37,0x0f,0x02,0xf2 = insert	%d15, %d15, %d0, 4, 2
+# 0x89,0x2f,0x00,0x68 = st.b	[%a2]384, %d15
+# 0x09,0xf0,0x51,0x08 = ld.bu	%d0, [%a15]17
+0x37,0x0f,0x02,0xf3 = insert	%d15, %d15, %d0, 6, 2
+# 0x08,0x10           = ld.bu	%d0, [%a15]1
+# 0x09,0x4f,0x41,0x68 = ld.bu	%d15, [%a4]385
+0x37,0x0f,0x01,0xf1 = insert	%d15, %d15, %d0, 2, 1
+# 0x89,0x2f,0x01,0x68 = st.b	[%a2]385, %d15
+# 0x08,0xd0           = ld.bu	%d0, [%a15]13
+0x37,0x0f,0x02,0xf0 = insert	%d15, %d15, %d0, 0, 2
+# 0x09,0xf0,0x53,0x08 = ld.bu	%d0, [%a15]19
+# 0x08,0x30           = ld.bu	%d0, [%a15]3
+0x37,0x0f,0x81,0xf2 = insert	%d15, %d15, %d0, 5, 1
+# 0x14,0xf0           = ld.bu	%d0, [%a15]
+0x37,0x0f,0x01,0xf2 = insert	%d15, %d15, %d0, 4, 1
+# 0x09,0xf0,0x52,0x08 = ld.bu	%d0, [%a15]18
+0x37,0x0f,0x04,0xf2 = insert	%d15, %d15, %d0, 4, 4
+0x8b,0x09,0x01,0xf0 = add	%d15, %d9, 16
+0x37,0x0f,0x68,0x40 = extr.u	%d4, %d15, 0, 8
+# 0x6d,0xff,0x19,0xfe = call	-0x3ce
+# 0x08,0x2f           = ld.bu	%d15, [%a15]2
+# 0xee,0x08           = jnz	%d15, 0x10
+# 0x4c,0xe2           = ld.w	%d15, [%a14]8
+0x0f,0xa0,0x10,0x00 = sha	%d0, %d0, %d10
+# 0x6c,0xe2           = st.w	[%a14]8, %d15
+# 0x3c,0x09           = j	0x12
+# 0x6d,0xff,0xbc,0xfd = call	-0x488
+# 0x08,0xb0           = ld.bu	%d0, [%a15]11
+# 0x09,0xc2,0x00,0x08 = ld.b	%d2, [%a12]
+# 0x09,0xe1,0x20,0x49 = ld.w	%d1, [%a14]288
+0xda,0x0f           = mov	%d15, 15
+0x53,0x42,0x20,0x30 = mul	%d3, %d2, 4
+0x0f,0x3f,0x00,0xf0 = sh	%d15, %d15, %d3
+0x82,0xf3           = mov	%d3, -1
+0xc6,0x3f           = xor	%d15, %d3
+0x26,0xf1           = and	%d1, %d15
+# 0x89,0xe1,0x20,0x49 = st.w	[%a14]288, %d1
+# 0x09,0xef,0x20,0x49 = ld.w	%d15, [%a14]288
+0x53,0x42,0x20,0x10 = mul	%d1, %d2, 4
+# 0x89,0xef,0x20,0x49 = st.w	[%a14]288, %d15
+# 0x09,0xff,0xc6,0x08 = ld.hu	%d15, [%a15]6
+# 0x6e,0x20           = jz	%d15, 0x40
+# 0x08,0xb5           = ld.bu	%d5, [%a15]11
+# 0x6d,0xff,0x22,0xfe = call	-0x3bc
+# 0x09,0xf0,0x0c,0x08 = ld.b	%d0, [%a15]12
+0xda,0x01           = mov	%d15, 1
+0x0f,0x0f,0x10,0xf0 = sha	%d15, %d15, %d0
+# 0x89,0xef,0x10,0x49 = st.w	[%a14]272, %d15
+# 0x08,0x90           = ld.bu	%d0, [%a15]9
+# 0x14,0x21           = ld.bu	%d1, [%a2]
+0x37,0x0f,0x68,0xf0 = extr.u	%d15, %d15, 0, 8
+0x37,0xf1,0x08,0xf0 = insert	%d15, %d1, %d15, 0, 8
+# 0x34,0x2f           = st.b	[%a2], %d15
+# 0x0c,0x21           = ld.bu	%d15, [%a2]1
+0x37,0x0f,0x82,0xf1 = insert	%d15, %d15, %d0, 3, 2
+# 0x2c,0x21           = st.b	[%a2]1, %d15
+# 0x0c,0x23           = ld.bu	%d15, [%a2]3
+0x96,0x02           = or	%d15, 2
+# 0x2c,0x23           = st.b	[%a2]3, %d15
+0x96,0x04           = or	%d15, 4
+# 0x08,0xff           = ld.bu	%d15, [%a15]15
+# 0xff,0x8f,0x1a,0x80 = jge.u	%d15, 8, 0x34
+# 0x08,0xa0           = ld.bu	%d0, [%a15]10
+# 0x08,0xf1           = ld.bu	%d1, [%a15]15
+# 0x09,0xe2,0x30,0x49 = ld.w	%d2, [%a14]304
+0x53,0x41,0x20,0x30 = mul	%d3, %d1, 4
+0x26,0xf2           = and	%d2, %d15
+# 0x89,0xe2,0x30,0x49 = st.w	[%a14]304, %d2
+# 0x09,0xef,0x30,0x49 = ld.w	%d15, [%a14]304
+0x53,0x41,0x20,0x10 = mul	%d1, %d1, 4
+# 0x89,0xef,0x30,0x49 = st.w	[%a14]304, %d15
+# 0x3c,0x1b           = j	0x36
+# 0x09,0xe2,0x34,0x49 = ld.w	%d2, [%a14]308
+0x3b,0xf0,0x00,0x30 = mov	%d3, 15
+0x9a,0x81           = add	%d15, %d1, -8
+0x0f,0xf3,0x00,0x30 = sh	%d3, %d3, %d15
+0xc6,0xf3           = xor	%d3, %d15
+0x26,0x32           = and	%d2, %d3
+# 0x89,0xe2,0x34,0x49 = st.w	[%a14]308, %d2
+# 0x09,0xef,0x34,0x49 = ld.w	%d15, [%a14]308
+0xc2,0x81           = add	%d1, -8
+# 0x89,0xef,0x34,0x49 = st.w	[%a14]308, %d15
+# 0x09,0xff,0xc4,0x08 = ld.hu	%d15, [%a15]4
+# 0x6e,0x29           = jz	%d15, 0x52
+# 0x08,0xa5           = ld.bu	%d5, [%a15]10
+# 0x6d,0xff,0xcb,0xfd = call	-0x46a
+0x53,0x40,0x20,0xf0 = mul	%d15, %d0, 4
+0x10,0xe5           = addsc.a	%a5, %a14, %d15, 0
+# 0x39,0x5f,0x03,0x80 = ld.bu	%d15, [%a5]515
+# 0xe9,0x4f,0x03,0x80 = st.b	[%a4]515, %d15
+0xbb,0xf0,0xff,0xff = mov.u	%d15, 65535
+# 0x89,0xef,0x14,0x49 = st.w	[%a14]276, %d15
+# 0x08,0x80           = ld.bu	%d0, [%a15]8
+# 0x6d,0xff,0x1e,0xfd = call	-0x5c4
+# 0x2c,0xc1           = st.b	[%a12]1, %d15
+# 0x09,0xff,0x0c,0x08 = ld.b	%d15, [%a15]12
+# 0x34,0xcf           = st.b	[%a12], %d15
+0xd9,0xff,0x9c,0x82 = lea	%a15, [%a15]10780
+0x49,0xff,0x00,0x0a = lea	%a15, [%a15]0
+0x49,0x42,0x00,0x0a = lea	%a2, [%a4]0
+0xa0,0x56           = mov.a	%a6, 5
+# 0x44,0xff           = ld.w	%d15, [%a15+]
+# 0x64,0x2f           = st.w	[%a2+], %d15
+# 0xfc,0x6e           = loop	%a6, -0x4
+# 0x89,0x45,0x94,0x09 = st.a	[%a4]20, %a5
+# 0xd4,0xf2           = ld.a	%a2, [%a15]
+# 0xd4,0x2c           = ld.a	%a12, [%a2]
+# 0x08,0x4f           = ld.bu	%d15, [%a15]4
+0x3b,0x00,0x40,0x00 = mov	%d0, 1024
+0xe2,0x0f           = mul	%d15, %d0
+0x10,0xc2           = addsc.a	%a2, %a12, %d15, 0
+0xd9,0x2d,0x40,0x20 = lea	%a13, [%a2]1152
+# 0x89,0x4d,0x84,0x09 = st.a	[%a4]4, %a13
+# 0xd4,0x22           = ld.a	%a2, [%a2]
+# 0xf4,0x42           = st.a	[%a4], %a2
+# 0x08,0x49           = ld.bu	%d9, [%a15]4
+# 0x89,0x49,0x08,0x08 = st.b	[%a4]8, %d9
+0x40,0xc4           = mov.aa	%a4, %a12
+# 0x6d,0xff,0x5c,0xfd = call	-0x548
+0x02,0x2a           = mov	%d10, %d2
+0x8b,0x09,0x01,0x00 = add	%d0, %d9, 16
+0x37,0x00,0x68,0x40 = extr.u	%d4, %d0, 0, 8
+# 0x6d,0xff,0x2e,0xfd = call	-0x5a4
+# 0x09,0xff,0x6f,0x08 = ld.bu	%d15, [%a15]47
+# 0x5e,0x1b           = jne	%d15, 1, 0x16
+0x82,0x14           = mov	%d4, 1
+# 0x09,0xf5,0x62,0x08 = ld.bu	%d5, [%a15]34
+# 0x09,0xf6,0x63,0x08 = ld.bu	%d6, [%a15]35
+0x82,0x07           = mov	%d7, 0
+# 0x6d,0xff,0x06,0xfe = call	-0x3f4
+0x82,0x04           = mov	%d4, 0
+0x82,0x05           = mov	%d5, 0
+0x82,0x06           = mov	%d6, 0
+# 0x6d,0xff,0xfe,0xfd = call	-0x404
+# 0x09,0xff,0x70,0x08 = ld.bu	%d15, [%a15]48
+# 0x09,0xf5,0x5a,0x08 = ld.bu	%d5, [%a15]26
+# 0x09,0xf6,0x5b,0x08 = ld.bu	%d6, [%a15]27
+0x82,0x17           = mov	%d7, 1
+# 0x6d,0xff,0xf2,0xfd = call	-0x41c
+# 0x6d,0xff,0xea,0xfd = call	-0x42c
+# 0x09,0xff,0x71,0x08 = ld.bu	%d15, [%a15]49
+# 0x09,0xf5,0x6a,0x08 = ld.bu	%d5, [%a15]42
+# 0x09,0xf6,0x6b,0x08 = ld.bu	%d6, [%a15]43
+0x82,0x27           = mov	%d7, 2
+# 0x6d,0xff,0xde,0xfd = call	-0x444
+# 0x6d,0xff,0xd6,0xfd = call	-0x454
+# 0x08,0x5f           = ld.bu	%d15, [%a15]5
+# 0x5f,0x9f,0x23,0x00 = jeq	%d15, %d9, 0x46
+0x53,0x89,0x20,0x00 = mul	%d0, %d9, 8
+0x91,0x00,0x00,0x28 = movh.a	%a2, 32768
+0xd9,0x22,0x88,0xc2 = lea	%a2, [%a2]11016
+0x01,0x20,0x00,0x26 = addsc.a	%a2, %a2, %d0, 0
+0x10,0x22           = addsc.a	%a2, %a2, %d15, 0
+# 0x14,0x20           = ld.bu	%d0, [%a2]
+# 0x09,0xdf,0x40,0x18 = ld.bu	%d15, [%a13]64
+0x82,0x41           = mov	%d1, 4
+0x4b,0x10,0x01,0x22 = div	%e2, %d0, %d1
+0x37,0x3f,0x02,0xf0 = insert	%d15, %d15, %d3, 0, 2
+# 0x89,0xdf,0x00,0x18 = st.b	[%a13]64, %d15
+# 0x09,0xd1,0x00,0x19 = ld.w	%d1, [%a13]64
+0xda,0x08           = mov	%d15, 8
+0x82,0x42           = mov	%d2, 4
+0x4b,0x20,0x01,0x22 = div	%e2, %d0, %d2
+0xa6,0xf1           = or	%d1, %d15
+# 0x89,0xd1,0x00,0x19 = st.w	[%a13]64, %d1
+0xda,0x00           = mov	%d15, 0
+# 0x14,0xd0           = ld.bu	%d0, [%a13]
+0x37,0xf0,0x02,0xf0 = insert	%d15, %d0, %d15, 0, 2
+# 0x34,0xdf           = st.b	[%a13], %d15
+# 0x09,0xff,0x6e,0x08 = ld.bu	%d15, [%a15]46
+0x37,0xf0,0x02,0xf2 = insert	%d15, %d0, %d15, 4, 2
+# 0xdf,0x1f,0x5d,0x80 = jne	%d15, 1, 0xba
+0x49,0xf2,0x1c,0x0a = lea	%a2, [%a15]28
+# 0x09,0xff,0x61,0x08 = ld.bu	%d15, [%a15]33
+# 0x6e,0x2d           = jz	%d15, 0x5a
+# 0x09,0xdf,0x44,0x28 = ld.bu	%d15, [%a13]132
+# 0x89,0xdf,0x04,0x28 = st.b	[%a13]132, %d15
+# 0x09,0xf0,0x5f,0x08 = ld.bu	%d0, [%a15]31
+# 0x09,0xd1,0x00,0x29 = ld.w	%d1, [%a13]128
+0x82,0x12           = mov	%d2, 1
+0x37,0x21,0x81,0x17 = insert	%d1, %d1, %d2, 15, 1
+0x37,0xf1,0x82,0x16 = insert	%d1, %d1, %d15, 13, 2
+0x37,0x01,0x04,0x14 = insert	%d1, %d1, %d0, 8, 4
+# 0x89,0xd1,0x00,0x29 = st.w	[%a13]128, %d1
+# 0xfe,0x04           = jne	%d15, %d0, 0x28
+# 0x09,0xff,0x5e,0x08 = ld.bu	%d15, [%a15]30
+0x37,0x21,0x81,0x1b = insert	%d1, %d1, %d2, 23, 1
+0x37,0xf1,0x04,0x18 = insert	%d1, %d1, %d15, 16, 4
+# 0x3c,0x07           = j	0xe
+0xb7,0x0f,0x01,0xf1 = insert	%d15, %d15, 0, 2, 1
+# 0xbe,0x05           = jeq	%d15, %d0, 0x2a
+# 0x09,0xf0,0x60,0x08 = ld.bu	%d0, [%a15]32
+# 0x14,0x2f           = ld.bu	%d15, [%a2]
+# 0x3c,0x02           = j	0x4
+# 0x09,0xd0,0x45,0x28 = ld.bu	%d0, [%a13]133
+0x37,0xf0,0x01,0xf1 = insert	%d15, %d0, %d15, 2, 1
+# 0x89,0xdf,0x05,0x28 = st.b	[%a13]133, %d15
+0x49,0xf2,0x14,0x0a = lea	%a2, [%a15]20
+# 0x09,0xff,0x59,0x08 = ld.bu	%d15, [%a15]25
+# 0x09,0xdf,0x64,0x28 = ld.bu	%d15, [%a13]164
+# 0x89,0xdf,0x24,0x28 = st.b	[%a13]164, %d15
+# 0x09,0xf0,0x57,0x08 = ld.bu	%d0, [%a15]23
+# 0x09,0xd1,0x20,0x29 = ld.w	%d1, [%a13]160
+# 0x89,0xd1,0x20,0x29 = st.w	[%a13]160, %d1
+# 0x09,0xff,0x56,0x08 = ld.bu	%d15, [%a15]22
+# 0x09,0xf0,0x58,0x08 = ld.bu	%d0, [%a15]24
+# 0x09,0xd0,0x64,0x28 = ld.bu	%d0, [%a13]164
+0x37,0xf0,0x01,0xf2 = insert	%d15, %d0, %d15, 4, 1
+# 0xdf,0x1f,0x57,0x80 = jne	%d15, 1, 0xae
+0x49,0xf2,0x24,0x0a = lea	%a2, [%a15]36
+# 0x09,0xff,0x69,0x08 = ld.bu	%d15, [%a15]41
+# 0x39,0xcf,0x04,0x80 = ld.bu	%d15, [%a12]516
+# 0xe9,0xcf,0x04,0x80 = st.b	[%a12]516, %d15
+# 0x09,0xf0,0x67,0x08 = ld.bu	%d0, [%a15]39
+# 0x19,0xc1,0x00,0x80 = ld.w	%d1, [%a12]512
+# 0x59,0xc1,0x00,0x80 = st.w	[%a12]512, %d1
+# 0x09,0xff,0x66,0x08 = ld.bu	%d15, [%a15]38
+# 0x09,0xf0,0x68,0x08 = ld.bu	%d0, [%a15]40
+# 0x39,0xc0,0x04,0x80 = ld.bu	%d0, [%a12]516
+# 0x7e,0x93           = jne	%d15, %d9, 0x6
+0xda,0x03           = mov	%d15, 3
+# 0x09,0xf5,0x6c,0x08 = ld.bu	%d5, [%a15]44
+# 0x6d,0xff,0x7a,0xfb = call	-0x90c
+# 0x3c,0x36           = j	0x6c
+0x53,0x61,0x20,0xf0 = mul	%d15, %d1, 6
+# 0x09,0x20,0x4a,0x08 = ld.bu	%d0, [%a2]10
+0x53,0x41,0x20,0xf0 = mul	%d15, %d1, 4
+0x10,0xd2           = addsc.a	%a2, %a13, %d15, 0
+0x10,0xd4           = addsc.a	%a4, %a13, %d15, 0
+# 0x09,0x4f,0x61,0x08 = ld.bu	%d15, [%a4]33
+0x37,0x0f,0x03,0xf0 = insert	%d15, %d15, %d0, 0, 3
+# 0x89,0x2f,0x21,0x08 = st.b	[%a2]33, %d15
+# 0x09,0x2f,0x06,0x09 = ld.w	%d15, [%a2]6
+0x4b,0xaf,0x41,0xf0 = mul.f	%d15, %d15, %d10
+0x4b,0x0f,0x71,0x01 = ftouz	%d0, %d15
+0xc2,0xe0           = add	%d0, -2
+0xda,0x1f           = mov	%d15, 31
+# 0x7f,0x0f,0x07,0x80 = jge.u	%d15, %d0, 0xe
+0xda,0x10           = mov	%d15, 16
+0x8b,0xf2,0x00,0x00 = add	%d0, %d2, 15
+0x8b,0xf0,0x2f,0x03 = min.u	%d0, %d0, 255
+# 0x09,0x4f,0x60,0x08 = ld.bu	%d15, [%a4]32
+0x37,0x00,0x68,0x00 = extr.u	%d0, %d0, 0, 8
+# 0x89,0x2f,0x20,0x08 = st.b	[%a2]32, %d15
+# 0xbf,0x21,0xcb,0xff = jlt.u	%d1, 2, -0x6a
+# 0x6d,0xff,0x18,0xfb = call	-0x9d0
+0xd9,0xff,0xb4,0x82 = lea	%a15, [%a15]10804
+0xa0,0xc6           = mov.a	%a6, 12
+# 0x2c,0x44           = st.b	[%a4]4, %d15
+# 0xf4,0x45           = st.a	[%a4], %a5
+# 0x0c,0x44           = ld.bu	%d15, [%a4]4
+# 0x2c,0x45           = st.b	[%a4]5, %d15
+# 0x89,0x4f,0x2c,0x08 = st.b	[%a4]44, %d15
+0x40,0x5c           = mov.aa	%a12, %a5
+# 0xd4,0xcd           = ld.a	%a13, [%a12]
+# 0xf4,0x4d           = st.a	[%a4], %a13
+# 0x6d,0xff,0x85,0xfa = call	-0xaf6
+0x02,0x2f           = mov	%d15, %d2
+# 0x6d,0xff,0xd6,0xf8 = call	-0xe54
+# 0x74,0xd0           = st.w	[%a13], %d0
+# 0x6d,0xff,0x9c,0xfa = call	-0xac8
+# 0x09,0xc4,0x5d,0x08 = ld.bu	%d4, [%a12]29
+# 0x6d,0xff,0x00,0xfc = call	-0x800
+# 0x4c,0xc5           = ld.w	%d15, [%a12]20
+0x4b,0x0f,0x71,0x41 = ftouz	%d4, %d15
+# 0x6d,0xff,0xc6,0xfb = call	-0x874
+# 0xf6,0x23           = jnz	%d2, 0x6
+# 0x3c,0x63           = j	0xc6
+# 0x4c,0xc4           = ld.w	%d15, [%a12]16
+# 0x6d,0xff,0xa9,0xfb = call	-0x8ae
+# 0x6d,0xff,0x45,0xfb = call	-0x976
+# 0x3c,0x34           = j	0x68
+0x10,0xcf           = addsc.a	%a15, %a12, %d15, 0
+0x10,0xdf           = addsc.a	%a15, %a13, %d15, 0
+# 0x09,0xff,0x61,0x28 = ld.bu	%d15, [%a15]161
+# 0x89,0x2f,0x21,0x28 = st.b	[%a2]161, %d15
+# 0x48,0x1f           = ld.w	%d15, [%a15]4
+0x4b,0x2f,0x41,0xf0 = mul.f	%d15, %d15, %d2
+0x4b,0xf0,0x11,0x42 = div.u	%e4, %d0, %d15
+0x8b,0xf4,0x00,0x00 = add	%d0, %d4, 15
+# 0x09,0x2f,0x60,0x28 = ld.bu	%d15, [%a2]160
+# 0x89,0xff,0x20,0x28 = st.b	[%a15]160, %d15
+# 0xbf,0x21,0xcd,0xff = jlt.u	%d1, 2, -0x66
+# 0x09,0xcf,0x5c,0x08 = ld.bu	%d15, [%a12]28
+# 0xde,0x1e           = jne	%d15, 1, 0x3c
+0x82,0x09           = mov	%d9, 0
+# 0x3c,0x17           = j	0x2e
+0x8b,0x09,0x01,0x40 = add	%d4, %d9, 16
+# 0x6d,0xff,0xde,0xfa = call	-0xa44
+0xe2,0x9f           = mul	%d15, %d9
+0xd9,0xff,0x40,0x20 = lea	%a15, [%a15]1152
+# 0x34,0xff           = st.b	[%a15], %d15
+# 0x6d,0xff,0x89,0xfa = call	-0xaee
+0xc2,0x19           = add	%d9, 1
+# 0xbf,0x89,0xea,0xff = jlt.u	%d9, 8, -0x2c
+# 0x6d,0xff,0xe8,0xfb = call	-0x830
+# 0xf4,0xf5           = st.a	[%a15], %a5
+0xbb,0x00,0x68,0xf9 = mov.u	%d15, 38528
+0x9b,0x8f,0xb9,0xf4 = addih	%d15, %d15, 19352
+# 0x6c,0xf5           = st.w	[%a15]20, %d15
+0x40,0x54           = mov.aa	%a4, %a5
+# 0x6d,0xff,0xee,0xfa = call	-0xa24
+# 0x68,0x42           = st.w	[%a15]16, %d2
+# 0x6d,0xff,0x73,0xf5 = call	-0x151a
+# 0x68,0x62           = st.w	[%a15]24, %d2
+# 0x2c,0xf8           = st.b	[%a15]8, %d15
+0x3b,0xd0,0x7b,0xf3 = mov	%d15, 14269
+0x9b,0x6f,0x58,0xf3 = addih	%d15, %d15, 13702
+# 0x6c,0xf1           = st.w	[%a15]4, %d15
+# 0x2c,0xfe           = st.b	[%a15]14, %d15
+# 0x89,0xff,0x0a,0x09 = st.w	[%a15]10, %d15
+# 0x89,0xff,0x1c,0x08 = st.b	[%a15]28, %d15
+# 0x89,0xff,0x1d,0x08 = st.b	[%a15]29, %d15
+0x91,0x30,0x00,0xff = movh.a	%a15, 61443
+# 0x39,0xff,0x37,0x06 = ld.bu	%d15, [%a15]24631
+0x37,0x0f,0x62,0xf2 = extr.u	%d15, %d15, 4, 2
+# 0xee,0x06           = jnz	%d15, 0xc
+0xbb,0x00,0xc2,0x2b = mov.u	%d2, 48160
+0x9b,0xe2,0xcb,0x24 = addih	%d2, %d2, 19646
+# 0x3c,0x11           = j	0x22
+# 0x5e,0x19           = jne	%d15, 1, 0x12
+0x91,0x00,0x00,0xf6 = movh.a	%a15, 24576
+0xd9,0xff,0x08,0x00 = lea	%a15, [%a15]8
+0x4b,0x0f,0x61,0x21 = utof	%d2, %d15
+0x82,0x02           = mov	%d2, 0
+0xd9,0xff,0x00,0x06 = lea	%a15, [%a15]24576
+# 0x6d,0xff,0xde,0xff = call	-0x44
+# 0x09,0xff,0x54,0x08 = ld.bu	%d15, [%a15]20
+0x16,0x01           = and	%d15, 1
+# 0x5e,0x1a           = jne	%d15, 1, 0x14
+0x16,0x7f           = and	%d15, 127
+0x4b,0x0f,0x41,0xf1 = itof	%d15, %d15
+# 0x3c,0x29           = j	0x52
+0x37,0x0f,0xe1,0xf1 = extr.u	%d15, %d15, 3, 1
+# 0x5e,0x1e           = jne	%d15, 1, 0x1c
+0xbb,0x00,0xc2,0x0b = mov.u	%d0, 48160
+0x9b,0xe0,0xcb,0x04 = addih	%d0, %d0, 19646
+# 0x09,0xff,0x5c,0x08 = ld.bu	%d15, [%a15]28
+0x4b,0xf0,0x51,0x20 = div.f	%d2, %d0, %d15
+0x37,0x0f,0xe7,0xf0 = extr.u	%d15, %d15, 1, 7
+0x4b,0xf2,0x41,0x10 = mul.f	%d1, %d2, %d15
+0x92,0x10           = add	%d0, %d15, 1
+# 0x09,0xff,0x5b,0x08 = ld.bu	%d15, [%a15]27
+0x16,0x0f           = and	%d15, 15
+0xe2,0xf0           = mul	%d0, %d15
+0x4b,0x00,0x41,0xf1 = itof	%d15, %d0
+0x4b,0xf1,0x51,0x20 = div.f	%d2, %d1, %d15
+# 0x39,0xff,0x33,0x06 = ld.bu	%d15, [%a15]24627
+# 0x3e,0x04           = jeq	%d15, %d0, 0x8
+# 0x3e,0x08           = jeq	%d15, %d0, 0x10
+# 0x3c,0x0a           = j	0x14
+# 0x3c,0x06           = j	0xc
+# 0x6d,0xff,0xb2,0xff = call	-0x9c
+# 0x6d,0xff,0xe8,0xff = call	-0x30
+# 0x39,0xff,0x31,0x06 = ld.bu	%d15, [%a15]24625
+0x37,0x0f,0x64,0x02 = extr.u	%d0, %d15, 4, 4
+# 0x3e,0x0c           = jeq	%d15, %d0, 0x18
+# 0xbe,0x0c           = jeq	%d15, %d0, 0x38
+0xda,0x02           = mov	%d15, 2
+# 0xbe,0x0f           = jeq	%d15, %d0, 0x3e
+# 0x5f,0x0f,0x22,0x00 = jeq	%d15, %d0, 0x44
+# 0x5f,0x0f,0x24,0x00 = jeq	%d15, %d0, 0x48
+# 0x3c,0x27           = j	0x4e
+# 0x39,0xff,0x32,0x06 = ld.bu	%d15, [%a15]24626
+# 0xee,0x03           = jnz	%d15, 0x6
+0x7b,0x00,0x1f,0xf4 = movh	%d15, 16880
+# 0x3c,0x12           = j	0x24
+0x7b,0x00,0x27,0xf4 = movh	%d15, 17008
+0x7b,0x00,0x2f,0xf4 = movh	%d15, 17136
+0x7b,0x00,0x37,0xf4 = movh	%d15, 17264
+0x91,0x00,0x00,0x26 = movh.a	%a2, 24576
+0xd9,0x22,0x08,0x00 = lea	%a2, [%a2]8
+# 0x09,0xff,0x10,0x19 = ld.w	%d15, [%a15]80
+# 0x74,0x2f           = st.w	[%a2], %d15
+# 0x6d,0x00,0x43,0x04 = call	0x886
+# 0x6d,0x00,0x54,0x04 = call	0x8a8
+# 0x6d,0x00,0x91,0x02 = call	0x522
+0x91,0x30,0x00,0x2f = movh.a	%a2, 61443
+# 0x39,0x2f,0x30,0x46 = ld.bu	%d15, [%a2]24880
+0x37,0x0f,0xe1,0xb1 = extr.u	%d11, %d15, 3, 1
+0x96,0x08           = or	%d15, 8
+# 0xe9,0x2f,0x30,0x46 = st.b	[%a2]24880
+# 0x6d,0x00,0x4a,0x04 = call	0x894
+0x02,0xa4           = mov	%d4, %d10
+# 0x6d,0x00,0xa4,0x02 = call	0x548
+# 0x39,0x2f,0x33,0x06 = ld.bu	%d15, [%a2]24627
+0x37,0x0f,0xe1,0xf3 = extr.u	%d15, %d15, 7, 1
+# 0xee,0xfa           = jnz	%d15, -0xc
+0xb7,0x0f,0x02,0xf2 = insert	%d15, %d15, 0, 4, 2
+# 0xe9,0x2f,0x33,0x06 = st.b	[%a2]24627
+0x96,0x40           = or	%d15, 64
+# 0x39,0x2f,0x18,0x06 = ld.bu	%d15, [%a2]24600
+0x96,0x10           = or	%d15, 16
+# 0xe9,0x2f,0x18,0x06 = st.b	[%a2]24600
+# 0x39,0x2f,0x37,0x06 = ld.bu	%d15, [%a2]24631
+0xb7,0x1f,0x02,0xf2 = insert	%d15, %d15, 1, 4, 2
+# 0xe9,0x2f,0x37,0x06 = st.b	[%a2]24631
+# 0x6d,0x00,0xc4,0x01 = call	0x388
+0xa6,0x28           = or	%d8, %d2
+# 0x6d,0x00,0x29,0x04 = call	0x852
+# 0xdf,0x08,0x92,0x81 = jne	%d8, 0, 0x324
+# 0x6d,0x00,0x5a,0x02 = call	0x4b4
+# 0x39,0x2f,0x14,0x06 = ld.bu	%d15, [%a2]24596
+0x37,0x0f,0xe1,0xf2 = extr.u	%d15, %d15, 5, 1
+# 0x6e,0xfa           = jz	%d15, -0xc
+# 0x39,0x20,0x1c,0x06 = ld.bu	%d0, [%a2]24604
+# 0x08,0xaf           = ld.bu	%d15, [%a15]10
+0x37,0xf0,0x07,0xf0 = insert	%d15, %d0, %d15, 0, 7
+# 0xe9,0x2f,0x1c,0x06 = st.b	[%a2]24604
+# 0x39,0x20,0x1b,0x06 = ld.bu	%d0, [%a2]24603
+# 0x08,0x8f           = ld.bu	%d15, [%a15]8
+0x37,0xf0,0x04,0xf0 = insert	%d15, %d0, %d15, 0, 4
+# 0xe9,0x2f,0x1b,0x06 = st.b	[%a2]24603
+# 0x39,0x20,0x19,0x06 = ld.bu	%d0, [%a2]24601
+# 0x08,0x9f           = ld.bu	%d15, [%a15]9
+0x37,0xf0,0x87,0xf0 = insert	%d15, %d0, %d15, 1, 7
+# 0xe9,0x2f,0x19,0x06 = st.b	[%a2]24601
+# 0x39,0x2f,0x1a,0x06 = ld.bu	%d15, [%a2]24602
+0xb7,0x0f,0x01,0xf0 = insert	%d15, %d15, 0, 0, 1
+# 0xe9,0x2f,0x1a,0x06 = st.b	[%a2]24602
+0x96,0x20           = or	%d15, 32
+0x96,0x01           = or	%d15, 1
+0xbb,0x70,0x71,0x4b = mov.u	%d4, 46871
+0x9b,0x14,0x85,0x43 = addih	%d4, %d4, 14417
+# 0x6d,0x00,0xbb,0x01 = call	0x376
+0x37,0x0f,0x61,0xf1 = extr.u	%d15, %d15, 2, 1
+# 0x48,0x34           = ld.w	%d4, [%a15]12
+# 0x6d,0x00,0x8c,0x01 = call	0x318
+# 0x19,0x20,0x30,0x06 = ld.w	%d0, [%a2]24624
+# 0x48,0x5f           = ld.w	%d15, [%a15]20
+0xc6,0x1f           = xor	%d15, %d1
+0x26,0xf0           = and	%d0, %d15
+# 0x48,0x41           = ld.w	%d1, [%a15]16
+0x26,0x1f           = and	%d15, %d1
+0xa6,0xf0           = or	%d0, %d15
+0x37,0xf0,0x02,0x0e = insert	%d0, %d0, %d15, 28, 2
+0x37,0xf0,0x01,0x0f = insert	%d0, %d0, %d15, 30, 1
+0xd9,0x22,0x30,0x06 = lea	%a2, [%a2]24624
+# 0x74,0x20           = st.w	[%a2], %d0
+# 0x19,0x20,0x34,0x06 = ld.w	%d0, [%a2]24628
+# 0x48,0x7f           = ld.w	%d15, [%a15]28
+# 0x48,0x61           = ld.w	%d1, [%a15]24
+0xd9,0x22,0x34,0x06 = lea	%a2, [%a2]24628
+# 0x39,0x2f,0x03,0x16 = ld.bu	%d15, [%a2]24643
+# 0x19,0x20,0x00,0x16 = ld.w	%d0, [%a2]24640
+# 0x48,0x9f           = ld.w	%d15, [%a15]36
+# 0x48,0x81           = ld.w	%d1, [%a15]32
+0xd9,0x22,0x00,0x16 = lea	%a2, [%a2]24640
+# 0x39,0x2f,0x0f,0x16 = ld.bu	%d15, [%a2]24655
+# 0x19,0x20,0x0c,0x16 = ld.w	%d0, [%a2]24652
+# 0x48,0xbf           = ld.w	%d15, [%a15]44
+# 0x48,0xa1           = ld.w	%d1, [%a15]40
+0xd9,0x22,0x0c,0x16 = lea	%a2, [%a2]24652
+# 0x19,0x20,0x00,0x26 = ld.w	%d0, [%a2]24704
+# 0x48,0xdf           = ld.w	%d15, [%a15]52
+# 0x48,0xc1           = ld.w	%d1, [%a15]48
+0xd9,0x22,0x00,0x26 = lea	%a2, [%a2]24704
+# 0x19,0x20,0x04,0x26 = ld.w	%d0, [%a2]24708
+# 0x48,0xff           = ld.w	%d15, [%a15]60
+# 0x48,0xe1           = ld.w	%d1, [%a15]56
+0xd9,0x22,0x04,0x26 = lea	%a2, [%a2]24708
+# 0x19,0x2f,0x08,0x26 = ld.w	%d15, [%a2]24712
+# 0x09,0xf0,0x04,0x19 = ld.w	%d0, [%a15]68
+# 0x09,0xf1,0x00,0x19 = ld.w	%d1, [%a15]64
+0xd9,0x22,0x08,0x26 = lea	%a2, [%a2]24712
+# 0x6d,0x00,0xf1,0x02 = call	0x5e2
+0x91,0x00,0x80,0x2f = movh.a	%a2, 63488
+# 0x19,0x2f,0x14,0x02 = ld.w	%d15, [%a2]8212
+# 0x09,0xf0,0x0c,0x19 = ld.w	%d0, [%a15]76
+# 0x09,0xf1,0x08,0x19 = ld.w	%d1, [%a15]72
+# 0x6d,0x00,0xe8,0x00 = call	0x1d0
+0xd9,0x22,0x14,0x02 = lea	%a2, [%a2]8212
+# 0x6d,0x00,0xab,0x02 = call	0x556
+0x82,0x0c           = mov	%d12, 0
+# 0x3c,0x37           = j	0x6e
+# 0x6d,0x00,0x03,0x01 = call	0x206
+0x53,0xcc,0x20,0xf0 = mul	%d15, %d12, 12
+# 0xc8,0x12           = ld.a	%a2, [%a15]4
+# 0x6d,0x00,0xb3,0x02 = call	0x566
+# 0x4c,0x22           = ld.w	%d15, [%a2]8
+# 0x6e,0x09           = jz	%d15, 0x12
+# 0x09,0x22,0x88,0x09 = ld.a	%a2, [%a2]8
+# 0x2d,0x02,0x00,0x00 = calli	%a2
+# 0x09,0x24,0x02,0x09 = ld.w	%d4, [%a2]2
+# 0x6d,0x00,0x91,0x00 = call	0x122
+0xc2,0x1c           = add	%d12, 1
+0x37,0x0c,0x68,0xc0 = extr.u	%d12, %d12, 0, 8
+# 0x14,0xff           = ld.bu	%d15, [%a15]
+# 0x3f,0xfc,0xc9,0xff = jlt.u	%d12, %d15, -0x6e
+# 0x6d,0x00,0xca,0x00 = call	0x194
+# 0x39,0xff,0x18,0x06 = ld.bu	%d15, [%a15]24600
+0xb7,0x0f,0x01,0xf3 = insert	%d15, %d15, 0, 6, 1
+# 0xe9,0xff,0x18,0x06 = st.b	[%a15]24600
+# 0x6d,0x00,0x87,0x02 = call	0x50e
+# 0x6d,0x00,0x92,0x00 = call	0x124
+# 0x39,0xff,0x2c,0x46 = ld.bu	%d15, [%a15]24876
+# 0xe9,0xff,0x2c,0x46 = st.b	[%a15]24876
+# 0x39,0xff,0x30,0x46 = ld.bu	%d15, [%a15]24880
+0x37,0xbf,0x81,0xf1 = insert	%d15, %d15, %d11, 3, 1
+# 0xe9,0xff,0x30,0x46 = st.b	[%a15]24880
+# 0x6d,0x00,0x47,0x02 = call	0x48e
+0x3b,0x00,0x28,0x80 = mov	%d8, 640
+# 0x6d,0x00,0x1f,0x02 = call	0x43e
+# 0x39,0xf0,0x10,0x06 = ld.bu	%d0, [%a15]24592
+0xb7,0x00,0x82,0x02 = insert	%d0, %d0, 0, 5, 2
+# 0xe9,0xf0,0x10,0x06 = st.b	[%a15]24592
+# 0x39,0xf0,0x12,0x06 = ld.bu	%d0, [%a15]24594
+# 0x54,0xf1           = ld.w	%d1, [%a15]
+0x3b,0x00,0x5a,0xf2 = mov	%d15, 9632
+0x9b,0x6f,0x02,0xf0 = addih	%d15, %d15, 38
+0x37,0xf0,0x05,0xf0 = insert	%d15, %d0, %d15, 0, 5
+# 0xe9,0xff,0x12,0x06 = st.b	[%a15]24594
+# 0x39,0xff,0x10,0x06 = ld.bu	%d15, [%a15]24592
+# 0xe9,0xff,0x10,0x06 = st.b	[%a15]24592
+0xc2,0xf8           = add	%d8, -1
+# 0xf6,0x83           = jnz	%d8, 0x6
+0x82,0x19           = mov	%d9, 1
+# 0x6f,0x1f,0xf8,0x7f = jz.t	%d15, 1, -0x10
+# 0x39,0xff,0x11,0x06 = ld.bu	%d15, [%a15]24593
+# 0x6f,0x0f,0xf2,0x7f = jz.t	%d15, 0, -0x1c
+# 0x6d,0x00,0x34,0x00 = call	0x68
+# 0x6d,0x00,0xea,0x01 = call	0x3d4
+0x02,0x92           = mov	%d2, %d9
+# 0x6d,0xff,0x21,0xfd = call	-0x5be
+# 0x39,0xff,0x35,0x06 = ld.bu	%d15, [%a15]24629
+0x4b,0xf2,0x51,0xf0 = div.f	%d15, %d2, %d15
+0x4b,0x8f,0x41,0xf0 = mul.f	%d15, %d15, %d8
+0x4b,0x0f,0x71,0xf1 = ftouz	%d15, %d15
+# 0x85,0xf1,0x10,0x00 = ld.w	%d1, f0000010
+# 0x85,0xf0,0x10,0x00 = ld.w	%d0, f0000010
+0xa2,0x10           = sub	%d0, %d1
+# 0x3f,0xf0,0xfd,0xff = jlt.u	%d0, %d15, -0x6
+# 0x4d,0xc0,0xe1,0xff = mfcr	%d15, $core_id
+0x16,0x07           = and	%d15, 7
+0x53,0xcf,0x20,0xf0 = mul	%d15, %d15, 12
+0x60,0xff           = mov.a	%a15, %d15
+0x91,0x30,0x00,0x3f = movh.a	%a3, 61443
+0x30,0xf3           = add.a	%a3, %a15
+0xd9,0x3f,0x00,0x46 = lea	%a15, [%a3]24832
+# 0x2e,0x1b           = jz.t	%d15, 1, 0x16
+0x8f,0x24,0x20,0xf0 = sha	%d15, %d4, 2
+# 0x54,0xf0           = ld.w	%d0, [%a15]
+0x37,0x00,0x70,0x08 = extr.u	%d0, %d0, 16, 16
+0x8f,0x00,0x21,0x00 = sha	%d0, %d0, 16
+# 0x74,0xff           = st.w	[%a15], %d15
+0x86,0x24           = sha	%d4, 2
+0x8f,0x24,0x40,0xf1 = or	%d15, %d4, 2
+# 0xdf,0x1f,0xfe,0x7f = jeq	%d15, 1, -0x4
+# 0x19,0xff,0x30,0x36 = ld.w	%d15, [%a15]24816
+# 0x6f,0x1f,0x12,0x00 = jz.t	%d15, 1, 0x24
+# 0x19,0xf0,0x30,0x36 = ld.w	%d0, [%a15]24816
+# 0x59,0xff,0x30,0x36 = st.w	[%a15]24816
+# 0xdf,0x1f,0xfb,0x7f = jeq	%d15, 1, -0xa
+0xd9,0xff,0x00,0x46 = lea	%a15, [%a15]24832
+# 0x2c,0xf4           = st.b	[%a15]4, %d15
+0x8f,0x34,0x40,0xf1 = or	%d15, %d4, 3
+# 0x6f,0x0f,0xff,0x7f = jz.t	%d15, 0, -0x2
+# 0x39,0xff,0x34,0x36 = ld.bu	%d15, [%a15]24820
+# 0xe9,0xff,0x34,0x36 = st.b	[%a15]24820
+# 0x6f,0x0f,0xfc,0x7f = jz.t	%d15, 0, -0x8
+0xb7,0x0f,0x81,0xf1 = insert	%d15, %d15, 0, 3, 1
+0x37,0x0f,0x6e,0xf1 = extr.u	%d15, %d15, 2, 14
+0x8f,0xff,0x83,0x21 = xor	%d2, %d15, 63
+0xd9,0xff,0x30,0x36 = lea	%a15, [%a15]24816
+0x20,0x08           = sub.a	%sp, 8
+0x40,0xbf           = mov.aa	%a15, %a11
+0x80,0xf2           = mov.d	%d2, %a15
+0x37,0x03,0x68,0xf4 = extr.u	%d15, %d3, 8, 8
+0xb7,0x0f,0x08,0xf0 = insert	%d15, %d15, 0, 0, 8
+0x37,0xf3,0x08,0x34 = insert	%d3, %d3, %d15, 8, 8
+0x37,0x04,0x68,0xf0 = extr.u	%d15, %d4, 0, 8
+0x37,0xf3,0x08,0x30 = insert	%d3, %d3, %d15, 0, 8
+0x37,0x03,0x68,0x08 = extr.u	%d0, %d3, 16, 8
+0x37,0xf0,0x03,0xf0 = insert	%d15, %d0, %d15, 0, 3
+0x37,0xf3,0x08,0x38 = insert	%d3, %d3, %d15, 16, 8
+# 0x89,0xa2,0x40,0x09 = st.d	[%sp], %e2
+# 0x09,0xa0,0x40,0x09 = ld.d	%e0, [%sp]
+0xb7,0x1f,0x08,0xf0 = insert	%d15, %d15, 1, 0, 8
+0xb7,0x2f,0x08,0xf0 = insert	%d15, %d15, 2, 0, 8
+0xb7,0x3f,0x08,0xf0 = insert	%d15, %d15, 3, 0, 8
+0xb7,0x4f,0x08,0xf0 = insert	%d15, %d15, 4, 0, 8
+0xb7,0x5f,0x08,0xf0 = insert	%d15, %d15, 5, 0, 8
+0xb7,0x7f,0x08,0xf0 = insert	%d15, %d15, 7, 0, 8
+0xd9,0xff,0x2c,0x11 = lea	%a15, [%a15]4204
+# 0xdc,0x0f           = ji	%a15
+0xd9,0xff,0x28,0x01 = lea	%a15, [%a15]4136
+0xd9,0xff,0xe4,0xf0 = lea	%a15, [%a15]4068
+0xd9,0xff,0xe0,0xe0 = lea	%a15, [%a15]4000
+0xd9,0xff,0xdc,0xd0 = lea	%a15, [%a15]3932
+0xd9,0xff,0xd8,0xc0 = lea	%a15, [%a15]3864
+0xd9,0xff,0x32,0x31 = lea	%a15, [%a15]4338
+0xd9,0xff,0x30,0x21 = lea	%a15, [%a15]4272
+# 0x6d,0x00,0x2f,0x00 = call	0x5e
+0x82,0x50           = mov	%d0, 5
+# 0x3e,0x28           = jeq	%d15, %d2, 0x10
+0x91,0x10,0x00,0x30 = movh.a	%a3, 1
+0xd9,0x33,0xc0,0x4f = lea	%a3, [%a3]-768
+# 0x54,0x31           = ld.w	%d1, [%a3]
+# 0x4d,0x00,0xd0,0x1f = mfcr	%d1, $dbgsr
+0x37,0x01,0xe2,0xf0 = extr.u	%d15, %d1, 1, 2
+# 0x5e,0x13           = jne	%d15, 1, 0x6
+# 0xee,0x13           = jnz	%d15, 0x26
+0x53,0x42,0x20,0xf0 = mul	%d15, %d2, 4
+0xd9,0x3f,0x14,0x36 = lea	%a15, [%a3]24788
+# 0x08,0x1f           = ld.bu	%d15, [%a15]1
+# 0x5e,0x32           = jne	%d15, 3, 0x4
+0x82,0x20           = mov	%d0, 2
+0x02,0x02           = mov	%d2, %d0
+0x82,0x32           = mov	%d2, 3
+0x53,0x80,0x20,0xf0 = mul	%d15, %d0, 8
+0xd9,0xff,0x8c,0x62 = lea	%a15, [%a15]10636
+# 0xd4,0xff           = ld.a	%a15, [%a15]
+# 0x7d,0x4f,0x0d,0x80 = jne.a	%a15, %a4, 0x1a
+0x37,0x0f,0x68,0x20 = extr.u	%d2, %d15, 0, 8
+# 0x3c,0x04           = j	0x8
+0xc2,0x10           = add	%d0, 1
+# 0xbf,0x30,0xea,0xff = jlt.u	%d0, 3, -0x2c
+# 0x6d,0xff,0xe0,0xff = call	-0x40
+0x02,0x28           = mov	%d8, %d2
+# 0x1e,0x32           = jeq	%d15, 3, 0x4
+# 0x5e,0x43           = jne	%d15, 4, 0x6
+# 0x5e,0x23           = jne	%d15, 2, 0x6
+0x82,0x1a           = mov	%d10, 1
+0x82,0x0a           = mov	%d10, 0
+# 0xdf,0x19,0x49,0x80 = jne	%d9, 1, 0x92
+# 0x5f,0x8f,0x28,0x00 = jeq	%d15, %d8, 0x50
+# 0x6d,0x00,0xa5,0x0b = call	0x174a
+0x02,0x84           = mov	%d4, %d8
+# 0x6d,0x00,0x0a,0x0a = call	0x1414
+0x91,0x30,0x00,0xcf = movh.a	%a12, 61443
+0xd9,0xcc,0x14,0x36 = lea	%a12, [%a12]24788
+# 0x6d,0xff,0xc0,0xff = call	-0x80
+0x37,0xaf,0x02,0xf0 = insert	%d15, %d15, %d10, 0, 2
+# 0x6d,0x00,0xc3,0x0b = call	0x1786
+# 0x54,0x3f           = ld.w	%d15, [%a3]
+0xb7,0x2f,0x82,0xf0 = insert	%d15, %d15, 2, 1, 2
+# 0x74,0x3f           = st.w	[%a3], %d15
+# 0x3c,0x1c           = j	0x38
+# 0x6d,0x00,0x6b,0x0b = call	0x16d6
+0x02,0x2b           = mov	%d11, %d2
+0x02,0xb4           = mov	%d4, %d11
+# 0x6d,0x00,0xbc,0x09 = call	0x1378
+0xd9,0xff,0x14,0x36 = lea	%a15, [%a15]24788
+0x53,0x48,0x20,0xf0 = mul	%d15, %d8, 4
+0xd9,0x22,0x14,0x36 = lea	%a2, [%a2]24788
+# 0x6d,0x00,0x72,0x0b = call	0x16e4
+# 0xff,0x3f,0x0b,0x80 = jge.u	%d15, 3, 0x16
+0x53,0x8f,0x20,0xf0 = mul	%d15, %d15, 8
+0xa0,0x0f           = mov.a	%a15, 0
+# 0x7d,0xf4,0x04,0x80 = jne.a	%a4, %a15, 0x8
+# 0x3c,0x10           = j	0x20
+0x30,0x43           = add.a	%a3, %a4
+0x49,0x33,0x08,0x8a = lea	%a3, [%a3]-504
+0x06,0xf4           = sh	%d4, -1
+0x37,0x4f,0x9f,0xf0 = insert	%d15, %d15, %d4, 1, 31
+# 0x6d,0xff,0xd6,0xff = call	-0x54
+0x26,0x2f           = and	%d15, %d2
+# 0x6d,0xff,0x28,0xff = call	-0x1b0
+# 0xf6,0x26           = jnz	%d2, 0xc
+# 0x6d,0xff,0x71,0xff = call	-0x11e
+0x02,0xf2           = mov	%d2, %d15
+0x80,0x4f           = mov.d	%d15, %a4
+0xb7,0x0f,0x1c,0xf0 = insert	%d15, %d15, 0, 0, 28
+0x7b,0x00,0x00,0x0d = movh	%d0, 53248
+# 0x7e,0x0d           = jne	%d15, %d0, 0x1a
+0xb7,0x0f,0x0c,0xfa = insert	%d15, %d15, 0, 20, 12
+0xb7,0x7f,0x03,0xfe = insert	%d15, %d15, 7, 28, 3
+# 0x4d,0xc0,0xe1,0x0f = mfcr	%d0, $core_id
+0x7b,0x00,0x00,0x11 = movh	%d1, 4096
+0xe2,0x10           = mul	%d0, %d1
+0xa2,0x0f           = sub	%d15, %d0
+# 0x6d,0x00,0x5b,0x06 = call	0xcb6
+# 0x39,0x2f,0x35,0x06 = ld.bu	%d15, [%a2]24629
+0x7b,0xa0,0x47,0x04 = movh	%d0, 17530
+0x4b,0x0f,0x51,0xf0 = div.f	%d15, %d15, %d0
+0x4b,0x08,0x61,0x01 = utof	%d0, %d8
+0x4b,0x0f,0x41,0xf0 = mul.f	%d15, %d15, %d0
+# 0x85,0xff,0x10,0x00 = ld.w	%d15, f0000010
+0xa2,0x1f           = sub	%d15, %d1
+# 0x3f,0x0f,0x04,0x80 = jlt.u	%d15, %d0, 0x8
+# 0xdf,0x7f,0xf6,0xff = jne	%d15, 7, -0x14
+0xd7,0x10,0x21,0x0f = imask	%e0, 1, %d15, 1
+# 0x49,0x40,0x40,0x08 = ldmst	[%a4]0, %e0
+0x8f,0xff,0x83,0x81 = xor	%d8, %d15, 63
+0x91,0x20,0x00,0xa7 = movh.a	%sp, 28674
+0xd9,0xaa,0x40,0x89 = lea	%sp, [%sp]-27136
+0x3b,0x00,0x98,0xf0 = mov	%d15, 2432
+# 0xcd,0x4f,0xe0,0x0f = mtcr	$psw, %d15
+# 0x4d,0x00,0xe0,0xff = mfcr	%d15, $pcxi
+0xb7,0x0f,0x14,0xf0 = insert	%d15, %d15, 0, 0, 20
+# 0xcd,0x0f,0xe0,0x0f = mtcr	$pcxi, %d15
+# 0x76,0x17           = jz	%d1, 0xe
+# 0xcd,0x4f,0x20,0x09 = mtcr	$pcon1, %d15
+0x8f,0x7f,0x00,0x21 = and	%d2, %d15, 7
+0x53,0xc2,0x20,0xf0 = mul	%d15, %d2, 12
+0x37,0x00,0x6e,0x01 = extr.u	%d0, %d0, 2, 14
+0x8f,0xf0,0x83,0x31 = xor	%d3, %d0, 63
+0x8f,0x23,0x20,0xf0 = sha	%d15, %d3, 2
+# 0x74,0xf0           = st.w	[%a15], %d0
+# 0x76,0x13           = jz	%d1, 0x6
+0x37,0x0f,0x81,0xf0 = insert	%d15, %d15, %d0, 1, 1
+# 0xcd,0xcf,0x20,0x09 = mtcr	$pcon0, %d15
+0x86,0x23           = sha	%d3, 2
+0x8f,0x33,0x40,0xf1 = or	%d15, %d3, 3
+# 0xcd,0x0f,0x04,0x09 = mtcr	$dcon0, %d15
+0x8f,0x28,0x20,0xf0 = sha	%d15, %d8, 2
+0xd9,0xff,0x00,0x40 = lea	%a15, [%a15]256
+0x80,0xff           = mov.d	%d15, %a15
+# 0xcd,0x4f,0xe2,0x0f = mtcr	$btv, %d15
+0x91,0xf0,0x01,0xf8 = movh.a	%a15, 32799
+0xd9,0xff,0x00,0x04 = lea	%a15, [%a15]16384
+# 0xcd,0x0f,0xe2,0x0f = mtcr	$biv, %d15
+0x91,0x20,0x00,0xf7 = movh.a	%a15, 28674
+0xd9,0xff,0x80,0xc9 = lea	%a15, [%a15]-25856
+# 0xcd,0x8f,0xe2,0x0f = mtcr	$isp, %d15
+0x96,0x03           = or	%d15, 3
+0x91,0x00,0x00,0x00 = movh.a	%a0, 0
+0xd9,0x00,0x00,0x00 = lea	%a0, [%a0]0
+0x91,0x00,0x00,0x10 = movh.a	%a1, 0
+0xd9,0x11,0x00,0x00 = lea	%a1, [%a1]0
+0x91,0x00,0x00,0x80 = movh.a	%a8, 0
+0xd9,0x88,0x00,0x00 = lea	%a8, [%a8]0
+0x91,0x00,0x00,0x90 = movh.a	%a9, 0
+0xd9,0x99,0x00,0x00 = lea	%a9, [%a9]0
+0xd9,0xff,0xc0,0x09 = lea	%a15, [%a15]-25600
+0x91,0x20,0x00,0x27 = movh.a	%a2, 28674
+0xd9,0x22,0xc0,0x0b = lea	%a2, [%a2]-17408
+0xa0,0x04           = mov.a	%a4, 0
+0x80,0x20           = mov.d	%d0, %a2
+0xa2,0xf0           = sub	%d0, %d15
+0xda,0x40           = mov	%d15, 64
+# 0x3c,0x1e           = j	0x3c
+0x8f,0x4f,0x1f,0x10 = sh	%d1, %d15, -12
+0xbb,0xf0,0xff,0x2f = mov.u	%d2, 65535
+0x06,0x62           = sh	%d2, 6
+0x06,0xaf           = sh	%d15, -6
+# 0xf6,0x06           = jnz	%d0, 0xc
+# 0xcd,0x81,0xe3,0x0f = mtcr	$fcx, %d1
+# 0x74,0x41           = st.w	[%a4], %d1
+0x9a,0xd4           = add	%d15, %d4, -3
+# 0x7e,0x05           = jne	%d15, %d0, 0xa
+# 0xcd,0xc1,0xe3,0x0f = mtcr	$lcx, %d1
+0x49,0xff,0x00,0x1a = lea	%a15, [%a15]64
+# 0x3f,0x40,0xe3,0xff = jlt.u	%d0, %d4, -0x3a
+# 0x74,0x4f           = st.w	[%a4], %d15
+# 0x6d,0x00,0x65,0x09 = call	0x12ca
+# 0x6d,0x00,0xf9,0x07 = call	0xff2
+# 0x6d,0x00,0x3a,0x08 = call	0x1074
+# 0x6d,0xff,0xf2,0xfc = call	-0x61c
+# 0x6d,0x00,0x9a,0x08 = call	0x1134
+# 0x6d,0x00,0xdc,0x08 = call	0x11b8
+0x91,0x00,0x00,0x48 = movh.a	%a4, 32768
+0xd9,0x44,0x88,0x72 = lea	%a4, [%a4]10696
+# 0x6d,0x00,0xf0,0x04 = call	0x9e0
+0x91,0x30,0x88,0x4f = movh.a	%a4, 63619
+0xd9,0xff,0xac,0x30 = lea	%a15, [%a15]2284
+0x80,0xf4           = mov.d	%d4, %a15
+# 0x6d,0xff,0x0d,0xfe = call	-0x3e6
+0x91,0x50,0x88,0x4f = movh.a	%a4, 63621
+0xd9,0xff,0xc2,0x00 = lea	%a15, [%a15]3074
+# 0x6d,0xff,0x04,0xfe = call	-0x3f8
+0xd9,0xff,0x0a,0xa0 = lea	%a15, [%a15]650
+0xd9,0xff,0x44,0x60 = lea	%a15, [%a15]1412
+0xd9,0xff,0x0c,0x46 = lea	%a15, [%a15]24844
+0x8f,0xff,0x83,0x11 = xor	%d1, %d15, 63
+0x91,0x20,0x00,0xa6 = movh.a	%sp, 24578
+0xd9,0xaa,0x40,0x8b = lea	%sp, [%sp]-18944
+# 0x76,0x27           = jz	%d2, 0xe
+0x8f,0x7f,0x00,0x31 = and	%d3, %d15, 7
+0x53,0xc3,0x20,0xf0 = mul	%d15, %d3, 12
+0x8f,0xf0,0x83,0x41 = xor	%d4, %d0, 63
+# 0x76,0x23           = jz	%d2, 0x6
+0x8f,0x21,0x20,0xf0 = sha	%d15, %d1, 2
+0xd9,0xff,0x00,0x86 = lea	%a15, [%a15]25088
+0xd9,0xff,0x00,0x05 = lea	%a15, [%a15]20480
+0x91,0x20,0x00,0xf6 = movh.a	%a15, 24578
+0xd9,0xff,0x80,0xcb = lea	%a15, [%a15]-17664
+0x86,0x21           = sha	%d1, 2
+0x8f,0x31,0x40,0xf1 = or	%d15, %d1, 3
+0xd9,0xff,0xc0,0x0b = lea	%a15, [%a15]-17408
+0x91,0x20,0x00,0x26 = movh.a	%a2, 24578
+0xd9,0x22,0xc0,0x0d = lea	%a2, [%a2]-9216
+0xd9,0xff,0x02,0xc0 = lea	%a15, [%a15]770
+0xd9,0xff,0x18,0x46 = lea	%a15, [%a15]24856
+0x91,0x20,0x00,0xa5 = movh.a	%sp, 20482
+0xd9,0xff,0x00,0x03 = lea	%a15, [%a15]12288
+0x91,0x20,0x00,0xf5 = movh.a	%a15, 20482
+0x91,0x20,0x00,0x25 = movh.a	%a2, 20482
+# 0x6d,0x00,0x71,0x12 = call	0x24e2
+# 0x15,0xd0,0xc0,0xe3 = stlcx	d0003f80
+# 0x15,0xd0,0xc0,0xf7 = stucx	d0003fc0
+# 0x4d,0x40,0xe0,0xff = mfcr	%d15, $psw
+0xb7,0x2f,0x02,0xf5 = insert	%d15, %d15, 2, 10, 2
+# 0x4d,0x40,0x20,0xf9 = mfcr	%d15, $pcon1
+0xc5,0x02,0x3f,0x00 = lea	%a2, 0x3f
+0xa0,0x35           = mov.a	%a5, 3
+0x89,0x40,0xc1,0x03 = cachei.wi	[%a4+]1
+# 0xfc,0x5e           = loop	%a5, -0x4
+0x49,0xff,0x20,0x0a = lea	%a15, [%a15]32
+# 0xfc,0x29           = loop	%a2, -0xe
+# 0x6f,0x0f,0xfe,0xff = jnz.t	%d15, 0, -0x4
+# 0x6f,0x1f,0xfa,0xff = jnz.t	%d15, 1, -0xc
+# 0x85,0xdf,0xc4,0xf3 = ld.w	%d15, d0003fc4
+# 0x15,0xd0,0xc0,0xff = lducx	d0003fc0
+# 0x15,0xd0,0xc0,0xeb = ldlcx	d0003f80
+# 0x1d,0x00,0x03,0x00 = j	0x6
+# 0x6d,0x00,0x02,0x01 = call	0x204
+# 0x6d,0x00,0xe1,0x00 = call	0x1c2
+# 0x6d,0x00,0x0d,0x00 = call	0x1a
+0xd9,0xff,0x0c,0x00 = lea	%a15, [%a15]12
+# 0x39,0xff,0x05,0x80 = ld.bu	%d15, [%a15]517
+# 0xe9,0xff,0x05,0x80 = st.b	[%a15]517, %d15
+0x20,0x20           = sub.a	%sp, 32
+0x49,0xa4,0x00,0x0a = lea	%a4, [%sp]0
+0x91,0x20,0x00,0x5f = movh.a	%a5, 61442
+# 0x6d,0x00,0x72,0x12 = call	0x24e4
+0x91,0x00,0x00,0x46 = movh.a	%a4, 24576
+0xd9,0x44,0x0c,0x00 = lea	%a4, [%a4]12
+0x49,0xa5,0x00,0x0a = lea	%a5, [%sp]0
+# 0x6d,0x00,0xea,0x11 = call	0x23d4
+0x20,0x38           = sub.a	%sp, 56
+0x91,0x00,0x00,0x56 = movh.a	%a5, 24576
+0xd9,0x55,0x0c,0x00 = lea	%a5, [%a5]12
+# 0x6d,0x00,0xfa,0x11 = call	0x23f4
+# 0x2c,0xa4           = st.b	[%sp]4, %d15
+# 0x2c,0xa5           = st.b	[%sp]5, %d15
+# 0x89,0xaf,0x31,0x08 = st.b	[%sp]49, %d15
+# 0x89,0xaf,0x24,0x08 = st.b	[%sp]36, %d15
+# 0x89,0xaf,0x28,0x08 = st.b	[%sp]40, %d15
+0xd9,0x44,0x30,0x00 = lea	%a4, [%a4]48
+# 0x6d,0x00,0xf3,0x0f = call	0x1fe6
+0x20,0x60           = sub.a	%sp, 96
+# 0x3c,0x50           = j	0xa0
+0x53,0x88,0x21,0xf0 = mul	%d15, %d8, 24
+0x10,0xaf           = addsc.a	%a15, %sp, %d15, 0
+0x49,0xf4,0x00,0x0a = lea	%a4, [%a15]0
+0xd9,0x55,0x30,0x00 = lea	%a5, [%a5]48
+# 0x6d,0x00,0xc6,0x10 = call	0x218c
+0xd9,0x22,0x00,0x00 = lea	%a2, [%a2]0
+0x01,0x28,0x00,0x26 = addsc.a	%a2, %a2, %d8, 0
+# 0x09,0x2f,0x00,0x08 = ld.b	%d15, [%a2]
+# 0x2c,0xfc           = st.b	[%a15]12, %d15
+# 0x28,0xf8           = st.b	[%a15]15, %d8
+# 0x2c,0xf2           = st.b	[%a15]2, %d15
+0x53,0x88,0x20,0xf0 = mul	%d15, %d8, 8
+0xd9,0xff,0x10,0x00 = lea	%a15, [%a15]16
+0x10,0xf4           = addsc.a	%a4, %a15, %d15, 0
+0x49,0xf5,0x00,0x0a = lea	%a5, [%a15]0
+# 0x6d,0x00,0x41,0x0f = call	0x1e82
+0x0f,0xf0,0x10,0x00 = sha	%d0, %d0, %d15
+0xd9,0x22,0x0c,0x00 = lea	%a2, [%a2]12
+0xd9,0xff,0x30,0x00 = lea	%a15, [%a15]48
+# 0x08,0x81           = ld.bu	%d1, [%a15]8
+0x10,0x2f           = addsc.a	%a15, %a2, %d15, 0
+# 0x09,0xff,0x00,0x69 = ld.w	%d15, [%a15]384
+0x82,0xf2           = mov	%d2, -1
+0xc6,0x02           = xor	%d2, %d0
+# 0x89,0xf0,0x00,0x69 = st.w	[%a15]384, %d0
+0xc2,0x18           = add	%d8, 1
+# 0xbf,0x48,0xb1,0xff = jlt.u	%d8, 4, -0x9e
+0x53,0x84,0x20,0xf0 = mul	%d15, %d4, 8
+# 0x09,0x22,0x84,0x09 = ld.a	%a2, [%a2]4
+# 0x19,0xff,0x00,0xa0 = ld.w	%d15, [%a15]640
+0x37,0x0f,0x68,0x0c = extr.u	%d0, %d15, 24, 8
+# 0x6f,0x70,0xec,0x7f = jz.t	%d0, 7, -0x28
+0x37,0x0f,0x70,0x20 = extr.u	%d2, %d15, 0, 16
+# 0x6d,0x00,0x50,0x0c = call	0x18a0
+0x02,0x24           = mov	%d4, %d2
+# 0x6d,0x00,0xf9,0x0a = call	0x15f2
+# 0x6d,0x00,0x5f,0x0c = call	0x18be
+# 0x6d,0x00,0x38,0x0b = call	0x1670
+0xd9,0x44,0x04,0x00 = lea	%a4, [%a4]4
+# 0x6d,0x00,0x44,0x00 = call	0x88
+# 0x6d,0x00,0x27,0x01 = call	0x24e
+# 0x6d,0xff,0xb7,0xfe = call	-0x292
+# 0xb4,0xaf           = st.h	[%sp], %d15
+# 0xac,0xa1           = st.h	[%sp]2, %d15
+# 0xac,0xa2           = st.h	[%sp]4, %d15
+# 0xac,0xa3           = st.h	[%sp]6, %d15
+# 0x3c,0x14           = j	0x28
+# 0x6d,0xff,0xbd,0xff = call	-0x86
+# 0xb4,0xa2           = st.h	[%sp], %d2
+# 0x6d,0xff,0xb9,0xff = call	-0x8e
+# 0x89,0xa2,0x82,0x08 = st.h	[%sp]2, %d2
+0x82,0x24           = mov	%d4, 2
+# 0x6d,0xff,0xb4,0xff = call	-0x98
+# 0x89,0xa2,0x84,0x08 = st.h	[%sp]4, %d2
+0x82,0x34           = mov	%d4, 3
+# 0x6d,0xff,0xaf,0xff = call	-0xa2
+# 0x89,0xa2,0x86,0x08 = st.h	[%sp]6, %d2
+# 0x3c,0xed           = j	-0x26
+0x3b,0xf0,0x0f,0x00 = mov	%d0, 255
+0x06,0x3f           = sh	%d15, 3
+0xc6,0xf0           = xor	%d0, %d15
+0xc2,0xf4           = add	%d4, -1
+0x60,0x4f           = mov.a	%a15, %d4
+0xb7,0x0f,0x02,0xf0 = insert	%d15, %d15, 0, 0, 2
+0xb0,0x14           = add.a	%a4, 1
+# 0x54,0x2f           = ld.w	%d15, [%a2]
+0x77,0x00,0x00,0x04 = dextr	%d0, %d0, %d0, 8
+# 0xfc,0xf6           = loop	%a15, -0x14
+0x8f,0x3f,0x00,0x10 = sh	%d1, %d15, 3
+0x80,0x41           = mov.d	%d1, %a4
+0xb7,0x01,0x02,0x20 = insert	%d2, %d1, 0, 0, 2
+# 0x09,0x51,0x01,0x00 = ld.b	%d1, [%a5+]1
+0x8f,0x3f,0x00,0x30 = sh	%d3, %d15, 3
+0x0f,0x31,0x10,0x10 = sha	%d1, %d1, %d3
+0x60,0x22           = mov.a	%a2, %d2
+# 0x54,0x22           = ld.w	%d2, [%a2]
+0x26,0x02           = and	%d2, %d0
+0xa6,0x12           = or	%d2, %d1
+# 0x74,0x22           = st.w	[%a2], %d2
+# 0xfd,0xf0,0xed,0x7f = loop	%a15, -0x26
+0x82,0x0b           = mov	%d11, 0
+# 0xc8,0x1c           = ld.a	%a12, [%a15]4
+# 0xc8,0x2d           = ld.a	%a13, [%a15]8
+# 0x48,0x3c           = ld.w	%d12, [%a15]12
+# 0x09,0xff,0x10,0x01 = ld.w	%d15, [%a15+]16
+# 0xdf,0x1f,0x23,0x80 = jne	%d15, 1, 0x46
+0x80,0xcf           = mov.d	%d15, %a12
+0x80,0xd0           = mov.d	%d0, %a13
+0x8f,0x10,0x00,0x01 = and	%d0, %d0, 1
+# 0x6e,0x04           = jz	%d15, 0x8
+0xc2,0xfc           = add	%d12, -1
+# 0x04,0xdf           = ld.bu	%d15, [%a13+]
+# 0x24,0xcf           = st.b	[%a12+], %d15
+# 0x76,0xcf           = jz	%d12, 0x1e
+0x8f,0x3c,0x00,0x01 = and	%d0, %d12, 3
+0x8f,0xec,0x1f,0xf0 = sh	%d15, %d12, -2
+0x02,0xf1           = mov	%d1, %d15
+0x40,0xd2           = mov.aa	%a2, %a13
+0xc2,0xf1           = add	%d1, -1
+0x60,0x14           = mov.a	%a4, %d1
+# 0x44,0x21           = ld.w	%d1, [%a2+]
+# 0x64,0xc1           = st.w	[%a12+], %d1
+# 0xfc,0x4e           = loop	%a4, -0x4
+0x90,0xdd           = addsc.a	%a13, %a13, %d15, 2
+0x02,0x0c           = mov	%d12, %d0
+# 0xdf,0x0c,0xe0,0x7f = jeq	%d12, 0, -0x40
+0x60,0xc2           = mov.a	%a2, %d12
+# 0xfc,0x2e           = loop	%a2, -0x4
+# 0x3c,0xd9           = j	-0x4e
+# 0xde,0x25           = jne	%d15, 2, 0x2a
+# 0x2e,0x03           = jz.t	%d15, 0, 0x6
+# 0x24,0xc9           = st.b	[%a12+], %d9
+# 0xdf,0x0c,0xd3,0x7f = jeq	%d12, 0, -0x5a
+0x8f,0x3c,0x00,0xf1 = and	%d15, %d12, 3
+0x06,0xec           = sh	%d12, -2
+# 0x76,0xc5           = jz	%d12, 0xa
+# 0x64,0xca           = st.w	[%a12+], %d10
+# 0xfc,0x2f           = loop	%a2, -0x2
+# 0x6e,0xc9           = jz	%d15, -0x6e
+# 0x24,0xcb           = st.b	[%a12+], %d11
+# 0x3c,0xc4           = j	-0x78
+0x8f,0x0f,0x1f,0x00 = sh	%d0, %d15, -16
+# 0xdf,0x00,0x2e,0x00 = jeq	%d0, 0, 0x5c
+0x8f,0x3f,0x00,0x01 = and	%d0, %d15, 3
+# 0xdf,0x10,0x2b,0x80 = jne	%d0, 1, 0x56
+0x8f,0x3f,0x00,0xd1 = and	%d13, %d15, 3
+0x80,0xdf           = mov.d	%d15, %a13
+# 0xfe,0xdb           = jne	%d15, %d13, 0x36
+# 0x76,0xdb           = jz	%d13, 0x16
+0x02,0xd4           = mov	%d4, %d13
+0x40,0xd5           = mov.aa	%a5, %a13
+# 0x6d,0x00,0x53,0x00 = call	0xa6
+0x01,0xcd,0x00,0xc6 = addsc.a	%a12, %a12, %d13, 0
+0x01,0xdd,0x00,0xd6 = addsc.a	%a13, %a13, %d13, 0
+0xa2,0xdc           = sub	%d12, %d13
+# 0xdf,0x0c,0x9b,0x7f = jeq	%d12, 0, -0xca
+0x02,0xc4           = mov	%d4, %d12
+# 0x6d,0x00,0x38,0x00 = call	0x70
+# 0x3c,0x94           = j	-0xd8
+# 0xdf,0x2f,0x91,0xff = jne	%d15, 2, -0xde
+# 0x6e,0x07           = jz	%d15, 0xe
+# 0x6d,0x00,0x15,0x00 = call	0x2a
+0x10,0xcc           = addsc.a	%a12, %a12, %d15, 0
+0xa2,0xfc           = sub	%d12, %d15
+# 0xdf,0x0c,0x86,0x7f = jeq	%d12, 0, -0xf4
+0x8f,0x3c,0x00,0x41 = and	%d4, %d12, 3
+# 0x64,0xc8           = st.w	[%a12+], %d8
+# 0xdf,0x04,0x7c,0x7f = jeq	%d4, 0, -0x108
+# 0x6d,0x00,0x04,0x00 = call	0x8
+# 0x1d,0xff,0x77,0xff = j	-0x112
+0xd9,0x44,0x94,0xd2 = lea	%a4, [%a4]11092
+# 0x1d,0x00,0x02,0x00 = j	0x4
+# 0x6d,0x00,0x15,0x0c = call	0x182a
+# 0x6d,0x00,0xbe,0x0a = call	0x157c
+# 0x6d,0x00,0x0e,0x00 = call	0x1c
+# 0x6d,0x00,0xf1,0x00 = call	0x1e2
+# 0x3c,0x00           = j	0x0
+0xb7,0x6f,0x08,0xf0 = insert	%d15, %d15, 6, 0, 8
diff --git a/suite/MC/TriCore/ADC_Queued_Scan_1_KIT_TC397_TFT.s.cs b/suite/MC/TriCore/ADC_Queued_Scan_1_KIT_TC397_TFT.s.cs
new file mode 100644
index 0000000000..91d40b080d
--- /dev/null
+++ b/suite/MC/TriCore/ADC_Queued_Scan_1_KIT_TC397_TFT.s.cs
@@ -0,0 +1,1383 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None
+0x02,0xf2           = mov	%d2, %d15
+0xde,0x1c           = jne	%d15, 1, 0x38
+# 0x19,0xff,0x28,0xa6 = ld.w	%d15,[%a15]25256
+0x7f,0x20,0x09,0x80 = jge.u	%d0, %d2, 0x12
+0xb0,0x14           = add.a	%a4, 1
+0x4b,0x02,0x71,0x41 = ftouz	%d4, %d2
+0x91,0x50,0x02,0xff = movh.a	%a15, 61477
+# 0x19,0xff,0x00,0x0d = ld.w	%d15,[%a15]-12288
+# 0x09,0x22,0x84,0x09 = ld.a	%a2,[%a2]4
+0x53,0x41,0x20,0x30 = mul	%d3, %d1, 4
+0xdf,0x2f,0x91,0xff = jne	%d15, 2, -0xde
+0x6d,0xff,0x53,0xfc = call	-0x75a
+0x06,0xf4           = sh	%d4, -1
+0x7f,0xf9,0x0f,0x80 = jge.u	%d9, %d15, 0x1e
+# 0x09,0xff,0x6d,0x08 = ld.bu	%d15,[%a15]45
+0x7b,0xd0,0x38,0x01 = movh	%d0, 5005
+# 0x09,0xcf,0x4e,0x18 = ld.bu	%d15,[%a12]78
+# 0x08,0x81           = ld.bu	%d1,[%a15]8
+0x37,0x0f,0x68,0x40 = extr.u	%d4, %d15, 0, 8
+0x6d,0xff,0x01,0xfb = call	-0x9fe
+0x37,0x03,0x68,0x08 = extr.u	%d0, %d3, 16, 8
+0x02,0x82           = mov	%d2, %d8
+0x6d,0x00,0x26,0x0e = call	0x1c4c
+0x3b,0x00,0x98,0xf0 = mov	%d15, 2432
+0x91,0x40,0x00,0xf7 = movh.a	%a15, 28676
+0x8f,0x23,0x20,0xf0 = sha	%d15, %d3, 2
+# 0xe9,0x2f,0x00,0x80 = st.b	[%a2]512,%d15
+0x6d,0x00,0x61,0x01 = call	0x2c2
+0x6f,0x1f,0xfa,0xff = jnz.t	%d15, 1, -0xc
+# 0x09,0xcf,0x04,0x19 = ld.w	%d15,[%a12]68
+0x6d,0xff,0x75,0xfc = call	-0x716
+0xee,0x05           = jnz	%d15, 0xa
+0x6d,0xff,0xfc,0xfe = call	-0x208
+# 0x2c,0x45           = st.b	[%a4]5,%d15
+# 0xcd,0x4f,0x20,0x09 = mtcr	$pcon1,%d15
+0x8f,0xff,0x83,0x31 = xor	%d3, %d15, 63
+0x6d,0xff,0xca,0xfc = call	-0x66c
+0x30,0xf3           = add.a	%a3, %a15
+# 0x59,0x2f,0x10,0x26 = st.w	[%a2]24720
+# 0x39,0x2f,0x30,0x06 = ld.bu	%d15,[%a2]24624
+# 0x89,0x4f,0x0f,0x18 = st.b	[%a4]79,%d15
+0x3e,0x12           = jeq	%d15, %d1, 0x4
+0xdf,0x00,0x2e,0x00 = jeq	%d0, 0, 0x5c
+# 0x2c,0x44           = st.b	[%a4]4,%d15
+0x3c,0x31           = j	0x62
+0x6e,0x1d           = jz	%d15, 0x3a
+0x40,0x5f           = mov.aa	%a15, %a5
+# 0x09,0xc4,0x7d,0x08 = ld.bu	%d4,[%a12]61
+0x9b,0xc0,0xfc,0x03 = addih	%d0, %d0, 16332
+0x37,0x4f,0x9f,0xf0 = insert	%d15, %d15, %d4, 1, 31
+# 0x54,0x23           = ld.w	%d3,[%a2]
+# 0x04,0xdf           = ld.bu	%d15,[%a13+]
+0x0f,0xf3,0x00,0x30 = sh	%d3, %d3, %d15
+0xb7,0x5f,0x08,0xf0 = insert	%d15, %d15, 5, 0, 8
+0x91,0x60,0x88,0x4f = movh.a	%a4, 63622
+0x40,0xc5           = mov.aa	%a5, %a12
+# 0xe9,0x2f,0x1a,0x06 = st.b	[%a2]24602
+0xb7,0x0f,0x1c,0xf0 = insert	%d15, %d15, 0, 0, 28
+0x76,0xc5           = jz	%d12, 0xa
+0x8f,0xff,0x83,0x91 = xor	%d9, %d15, 63
+0xc6,0x1f           = xor	%d15, %d1
+0x8f,0xec,0x1f,0xf0 = sh	%d15, %d12, -2
+0xc2,0xf4           = add	%d4, -1
+0x5e,0x23           = jne	%d15, 2, 0x6
+0x8f,0x24,0x00,0xf0 = sh	%d15, %d4, 2
+0x8f,0x24,0x20,0xf0 = sha	%d15, %d4, 2
+# 0x09,0xf3,0x04,0x19 = ld.w	%d3,[%a15]68
+# 0x09,0xfa,0x0c,0x08 = ld.b	%d10,[%a15]12
+0x1d,0x00,0x03,0x00 = j	0x6
+0x02,0x0c           = mov	%d12, %d0
+# 0x89,0xff,0x25,0x48 = st.b	[%a15]293,%d15
+0x02,0xf4           = mov	%d4, %d15
+0xd9,0x22,0xb8,0xd2 = lea	%a2, [%a2]11128
+# 0x09,0xc0,0x6b,0x08 = ld.bu	%d0,[%a12]43
+0xd9,0x22,0x40,0x00 = lea	%a2, [%a2]1024
+0x91,0x50,0x02,0x2f = movh.a	%a2, 61477
+0xa2,0xdc           = sub	%d12, %d13
+# 0x09,0x20,0x4a,0x28 = ld.bu	%d0,[%a2]138
+# 0x48,0xb3           = ld.w	%d3,[%a15]44
+0x4b,0xf1,0x51,0x00 = div.f	%d0, %d1, %d15
+0x57,0x00,0x62,0xff = extr.u	%d15, %d0, %d15, 2
+# 0x54,0x4f           = ld.w	%d15,[%a4]
+0xdf,0x10,0xee,0x7f = jeq	%d0, 1, -0x24
+0x3c,0x34           = j	0x68
+# 0x08,0xa1           = ld.bu	%d1,[%a15]10
+0x2e,0x1b           = jz.t	%d15, 1, 0x16
+# 0x89,0xef,0x10,0x69 = st.w	[%a14]400,%d15
+0x91,0x00,0x09,0xf8 = movh.a	%a15, 32912
+0x6f,0x0f,0xfc,0x7f = jz.t	%d15, 0, -0x8
+0xde,0x25           = jne	%d15, 2, 0x2a
+# 0x2c,0xfc           = st.b	[%a15]12,%d15
+0x37,0x00,0x62,0xfa = extr.u	%d15, %d0, 20, 2
+0x0f,0x2f,0x00,0xf0 = sh	%d15, %d15, %d2
+0xd9,0xff,0x18,0x96 = lea	%a15, [%a15]25176
+0x37,0x01,0x10,0x10 = insert	%d1, %d1, %d0, 0, 16
+0xd9,0xff,0x88,0x72 = lea	%a15, [%a15]10696
+0x10,0xdf           = addsc.a	%a15, %a13, %d15, 0
+0x6f,0x7f,0xec,0x7f = jz.t	%d15, 7, -0x28
+0x49,0x42,0x00,0x0a = lea	%a2, [%a4]0
+0xbe,0x9c           = jeq	%d15, %d9, 0x38
+# 0x59,0x2f,0x10,0x06 = st.w	[%a2]24592
+0x09,0xff,0xca,0x28 = ld.hu	%d15, [%a15]138
+0xfc,0x2e           = loop	%a2, -0x4
+# 0x54,0x3f           = ld.w	%d15,[%a3]
+# 0xc8,0x2d           = ld.a	%a13,[%a15]8
+0x7b,0x00,0x00,0x0d = movh	%d0, 53248
+0x3e,0x0a           = jeq	%d15, %d0, 0x14
+# 0x19,0x2f,0xa0,0x56 = ld.w	%d15,[%a2]26976
+# 0x89,0xef,0x20,0x69 = st.w	[%a14]416,%d15
+# 0x09,0xf0,0x52,0x08 = ld.bu	%d0,[%a15]18
+0x9b,0xef,0xcb,0xf4 = addih	%d15, %d15, 19646
+0x82,0x18           = mov	%d8, 1
+# 0x09,0x50,0x66,0x08 = ld.bu	%d0,[%a5]38
+# 0x54,0x22           = ld.w	%d2,[%a2]
+0x91,0x00,0x00,0x00 = movh.a	%a0, 0
+# 0x09,0xcf,0x43,0x18 = ld.bu	%d15,[%a12]67
+0x37,0xf0,0x03,0xf0 = insert	%d15, %d0, %d15, 0, 3
+0x3f,0x02,0x08,0x80 = jlt.u	%d2, %d0, 0x10
+# 0x89,0xe1,0x00,0x39 = st.w	[%a14]192,%d1
+0xb4,0xc2           = st.h	[%a12], %d2
+0xd9,0x44,0x20,0x93 = lea	%a4, [%a4]12896
+0x37,0x03,0x68,0xf4 = extr.u	%d15, %d3, 8, 8
+0x89,0x40,0xc1,0x03 = cachei.wi	[%a4+]1
+0x1d,0x00,0x9c,0x00 = j	0x138
+0x5e,0x26           = jne	%d15, 2, 0xc
+0x7b,0x80,0x2c,0x04 = movh	%d0, 17096
+0x8f,0x2a,0x20,0xf0 = sha	%d15, %d10, 2
+0x6d,0xff,0x2f,0xf8 = call	-0xfa2
+0xda,0x7f           = mov	%d15, 127
+0xbe,0x65           = jeq	%d15, %d6, 0x2a
+# 0xf4,0xf2           = st.a	[%a15],%a2
+0x91,0x00,0x00,0x10 = movh.a	%a1, 0
+0xbf,0x20,0xef,0xff = jlt.u	%d0, 2, -0x22
+0x6e,0x36           = jz	%d15, 0x6c
+# 0x09,0xc5,0x74,0x08 = ld.bu	%d5,[%a12]52
+0x80,0x50           = mov.d	%d0, %a5
+0x6d,0xb8,0x80,0x11 = call	-0x8fdd00
+# 0x59,0x20,0x00,0x16 = st.w	[%a2]24640
+0x40,0xd5           = mov.aa	%a5, %a13
+0x6e,0xc9           = jz	%d15, -0x6e
+0x53,0x4a,0x20,0x20 = mul	%d2, %d10, 4
+# 0x44,0xff           = ld.w	%d15,[%a15+]
+# 0xd4,0xf4           = ld.a	%a4,[%a15]
+0x26,0x32           = and	%d2, %d3
+0x82,0x08           = mov	%d8, 0
+0x6d,0x00,0x41,0x01 = call	0x282
+0x6d,0x00,0xe7,0x07 = call	0xfce
+0x37,0x4f,0x04,0xf8 = insert	%d15, %d15, %d4, 16, 4
+0x15,0xd0,0xc0,0xe3 = stlcx	0xd0003f80
+0x7f,0xf9,0x0d,0x80 = jge.u	%d9, %d15, 0x1a
+0x26,0x02           = and	%d2, %d0
+0xd9,0xff,0x30,0x03 = lea	%a15, [%a15]12336
+0x3b,0x00,0x40,0xf0 = mov	%d15, 1024
+# 0x09,0xef,0x30,0x69 = ld.w	%d15,[%a14]432
+# 0x19,0x20,0x28,0x06 = ld.w	%d0,[%a2]24616
+0x6d,0xe8,0x17,0x00 = call	-0x2fffd2
+0x6d,0x00,0x5d,0x00 = call	0xba
+0x8f,0xff,0x83,0x81 = xor	%d8, %d15, 63
+# 0xcd,0xcf,0x20,0x09 = mtcr	$pcon0,%d15
+# 0x39,0xff,0x30,0x06 = ld.bu	%d15,[%a15]24624
+0x9b,0x1f,0x8d,0xf3 = addih	%d15, %d15, 14545
+# 0x09,0xc4,0x75,0x08 = ld.bu	%d4,[%a12]53
+0x3b,0x00,0x00,0x31 = mov	%d3, 4096
+# 0x4d,0xc0,0xe1,0xff = mfcr	%d15,$core_id
+0x53,0x40,0x20,0xf0 = mul	%d15, %d0, 4
+0xa0,0x66           = mov.a	%a6, 6
+0x26,0x2f           = and	%d15, %d2
+0x3f,0x10,0xee,0xff = jlt.u	%d0, %d1, -0x24
+0xda,0xbc           = mov	%d15, 188
+0x53,0x4a,0x20,0xf0 = mul	%d15, %d10, 4
+0x91,0x10,0x00,0xf1 = movh.a	%a15, 4097
+# 0x0c,0xc4           = ld.bu	%d15,[%a12]4
+0x8b,0xff,0x21,0xf3 = min.u	%d15, %d15, 31
+0x4b,0xaf,0x41,0xf0 = mul.f	%d15, %d15, %d10
+0xbb,0x00,0xc2,0xfb = mov.u	%d15, 48160
+0x3c,0x0e           = j	0x1c
+0x91,0x40,0x88,0x4f = movh.a	%a4, 63620
+# 0x19,0x20,0x28,0xa6 = ld.w	%d0,[%a2]25256
+# 0x39,0x20,0x1c,0x06 = ld.bu	%d0,[%a2]24604
+# 0x89,0x4f,0x0d,0x18 = st.b	[%a4]77,%d15
+# 0xd4,0xcd           = ld.a	%a13,[%a12]
+0x96,0x40           = or	%d15, 64
+0x6d,0xff,0xae,0xf8 = call	-0xea4
+0x37,0x00,0x62,0xf2 = extr.u	%d15, %d0, 4, 2
+0x6f,0x0f,0xf3,0x7f = jz.t	%d15, 0, -0x1a
+0x1d,0x00,0xd4,0x01 = j	0x3a8
+0x91,0x10,0x88,0xff = movh.a	%a15, 63617
+# 0x09,0xe2,0x34,0x69 = ld.w	%d2,[%a14]436
+# 0x48,0x3c           = ld.w	%d12,[%a15]12
+# 0x14,0x21           = ld.bu	%d1,[%a2]
+# 0xe9,0x2f,0x0b,0x48 = st.b	[%a2]-32501
+# 0x89,0x44,0x10,0x59 = st.w	[%a4]336,%d4
+0xd9,0x22,0x00,0x00 = lea	%a2, [%a2]0
+0x37,0x0f,0x01,0xff = insert	%d15, %d15, %d0, 30, 1
+0x3b,0x00,0x00,0x01 = mov	%d0, 4096
+# 0x19,0x4f,0x28,0xa6 = ld.w	%d15,[%a4]25256
+# 0x09,0xcf,0x51,0x18 = ld.bu	%d15,[%a12]81
+# 0x39,0x2f,0x0b,0x48 = ld.bu	%d15,[%a2]-32501
+0x3b,0x00,0xd0,0x02 = mov	%d0, 11520
+# 0xe8,0x1e           = st.a	[%a15]4,%a14
+# 0x09,0x21,0x4b,0x28 = ld.bu	%d1,[%a2]139
+0x02,0xd4           = mov	%d4, %d13
+0x60,0x4f           = mov.a	%a15, %d4
+0xdf,0x1f,0xfb,0x7f = jeq	%d15, 1, -0xa
+0xc2,0xf0           = add	%d0, -1
+0x4b,0xf0,0x11,0x42 = div.u	%e4, %d0, %d15
+0x01,0x28,0x00,0x26 = addsc.a	%a2, %a2, %d8, 0
+# 0x54,0x20           = ld.w	%d0,[%a2]
+# 0xe9,0x2f,0x2a,0x06 = st.b	[%a2]24618
+# 0x08,0x4f           = ld.bu	%d15,[%a15]4
+0x49,0x55,0x0c,0x0a = lea	%a5, [%a5]12
+0xa6,0x20           = or	%d0, %d2
+0x91,0x00,0x00,0x57 = movh.a	%a5, 28672
+# 0x89,0xaf,0x01,0x18 = st.b	[%sp]65,%d15
+0x82,0x06           = mov	%d6, 0
+# 0x09,0x20,0x48,0x28 = ld.bu	%d0,[%a2]136
+0x60,0x14           = mov.a	%a4, %d1
+# 0xc8,0x15           = ld.a	%a5,[%a15]4
+0x3c,0x08           = j	0x10
+0x3b,0xf0,0x0f,0x00 = mov	%d0, 255
+0xd9,0x22,0xc0,0x07 = lea	%a2, [%a2]31744
+# 0x48,0x2f           = ld.w	%d15,[%a15]8
+0x6d,0x00,0xbe,0x02 = call	0x57c
+# 0x09,0x51,0x01,0x00 = ld.b	%d1,[%a5+]1
+0xa2,0x8f           = sub	%d15, %d8
+0x80,0x4f           = mov.d	%d15, %a4
+# 0x74,0xff           = st.w	[%a15],%d15
+# 0x4c,0x41           = ld.w	%d15,[%a4]4
+0x3c,0x05           = j	0xa
+0x6d,0xff,0x67,0xfc = call	-0x732
+0x4b,0x00,0x61,0xf1 = utof	%d15, %d0
+0x82,0xf3           = mov	%d3, -1
+# 0xcd,0x4f,0xe2,0x0f = mtcr	$btv,%d15
+0xdf,0x0c,0xe0,0x7f = jeq	%d12, 0, -0x40
+0x3c,0x0d           = j	0x1a
+0x3f,0xf1,0xef,0x7f = jlt	%d1, %d15, -0x22
+# 0x19,0x20,0x34,0x06 = ld.w	%d0,[%a2]24628
+0x91,0x00,0x00,0x90 = movh.a	%a9, 0
+# 0x39,0x2f,0x1a,0x06 = ld.bu	%d15,[%a2]24602
+0x53,0xc8,0x21,0xf0 = mul	%d15, %d8, 28
+0xa0,0x15           = mov.a	%a5, 1
+0x37,0x01,0x81,0x01 = insert	%d0, %d1, %d0, 3, 1
+0x40,0xd2           = mov.aa	%a2, %a13
+# 0x89,0xef,0x00,0x38 = st.b	[%a14]192,%d15
+0x37,0xf0,0x03,0x00 = insert	%d0, %d0, %d15, 0, 3
+# 0x08,0x20           = ld.bu	%d0,[%a15]2
+0x91,0x00,0x0c,0xf8 = movh.a	%a15, 32960
+0xda,0x1d           = mov	%d15, 29
+0xbf,0x89,0x05,0x80 = jlt.u	%d9, 8, 0xa
+0x3c,0x0c           = j	0x18
+0x49,0xff,0x0c,0x0a = lea	%a15, [%a15]12
+# 0x09,0xef,0x45,0x48 = ld.bu	%d15,[%a14]261
+0x37,0x01,0x81,0x00 = insert	%d0, %d1, %d0, 1, 1
+# 0x19,0x2f,0x00,0x16 = ld.w	%d15,[%a2]24640
+0x91,0x30,0x00,0x4f = movh.a	%a4, 61443
+0xc2,0xff           = add	%d15, -1
+0x02,0x90           = mov	%d0, %d9
+# 0x34,0x2f           = st.b	[%a2],%d15
+# 0x34,0xcf           = st.b	[%a12],%d15
+0x3e,0x47           = jeq	%d15, %d4, 0xe
+0xf6,0x02           = jnz	%d0, 0x4
+# 0x54,0xf1           = ld.w	%d1,[%a15]
+0xd9,0x22,0x28,0xa6 = lea	%a2, [%a2]25256
+# 0x19,0xff,0x10,0x16 = ld.w	%d15,[%a15]24656
+# 0x4c,0x52           = ld.w	%d15,[%a5]8
+0x3b,0x90,0xd0,0x33 = mov	%d3, 15625
+0x02,0x49           = mov	%d9, %d4
+0x5e,0x16           = jne	%d15, 1, 0xc
+# 0x08,0x8f           = ld.bu	%d15,[%a15]8
+0x91,0x00,0x03,0xf8 = movh.a	%a15, 32816
+0xd9,0x3f,0x0c,0x96 = lea	%a15, [%a3]25164
+# 0x09,0xff,0x65,0x48 = ld.bu	%d15,[%a15]293
+0x3e,0x5a           = jeq	%d15, %d5, 0x14
+0x0f,0x3f,0x00,0xf0 = sh	%d15, %d15, %d3
+0x37,0x00,0x70,0x08 = extr.u	%d0, %d0, 16, 16
+# 0x89,0xa2,0x40,0x09 = st.d	[%sp],%e2
+# 0x19,0x2f,0x30,0x06 = ld.w	%d15,[%a2]24624
+0x91,0xc0,0x88,0x4f = movh.a	%a4, 63628
+# 0x0c,0x44           = ld.bu	%d15,[%a4]4
+0x8f,0x28,0x00,0xf0 = sh	%d15, %d8, 2
+0x06,0xef           = sh	%d15, -2
+0xa2,0x1f           = sub	%d15, %d1
+0xd9,0x55,0x08,0x60 = lea	%a5, [%a5]392
+0x37,0x0f,0x81,0xf2 = insert	%d15, %d15, %d0, 5, 1
+0xc2,0x19           = add	%d9, 1
+0x3e,0x66           = jeq	%d15, %d6, 0xc
+0x4b,0xf1,0x41,0x10 = mul.f	%d1, %d1, %d15
+# 0x09,0xf4,0xb0,0x19 = ld.a	%a4,[%a15]112
+0x6d,0x00,0xf9,0x07 = call	0xff2
+0x02,0x92           = mov	%d2, %d9
+0x6d,0xff,0x05,0xfc = call	-0x7f6
+0x0f,0xf0,0x10,0x00 = sha	%d0, %d0, %d15
+0x8f,0x3f,0x00,0xd1 = and	%d13, %d15, 3
+0x6d,0xff,0xac,0xff = call	-0xa8
+# 0x39,0xff,0x2e,0x08 = ld.bu	%d15,[%a15]-32722
+0x3b,0x00,0x40,0x00 = mov	%d0, 1024
+0xa6,0x12           = or	%d2, %d1
+0x3c,0x33           = j	0x66
+0xbb,0x00,0x52,0x0c = mov.u	%d0, 50464
+0x8f,0x3c,0x00,0xf1 = and	%d15, %d12, 3
+# 0x74,0x41           = st.w	[%a4],%d1
+0x6d,0xff,0x0c,0xfb = call	-0x9e8
+0x16,0x03           = and	%d15, 3
+0x91,0x30,0x00,0xff = movh.a	%a15, 61443
+0xf6,0x06           = jnz	%d0, 0xc
+0x91,0x00,0x00,0x28 = movh.a	%a2, 32768
+0xd9,0xff,0x80,0xc5 = lea	%a15, [%a15]23296
+0x37,0x10,0x01,0x01 = insert	%d0, %d0, %d1, 2, 1
+0x82,0x16           = mov	%d6, 1
+# 0xc8,0x12           = ld.a	%a2,[%a15]4
+# 0x09,0xf0,0x69,0x08 = ld.bu	%d0,[%a15]41
+0x91,0x00,0x0f,0xfa = movh.a	%a15, 41200
+0x8f,0xff,0x83,0x21 = xor	%d2, %d15, 63
+# 0x09,0xff,0x00,0x19 = ld.w	%d15,[%a15]64
+0x91,0x20,0x88,0x4f = movh.a	%a4, 63618
+# 0x48,0x93           = ld.w	%d3,[%a15]36
+# 0x89,0x4f,0x18,0x08 = st.b	[%a4]24,%d15
+0x80,0xf0           = mov.d	%d0, %a15
+# 0x85,0xff,0x10,0x01 = ld.w	%d15,f0001010
+0x53,0x44,0x20,0xf0 = mul	%d15, %d4, 4
+# 0x09,0xff,0x43,0x28 = ld.bu	%d15,[%a15]131
+0xc2,0x12           = add	%d2, 1
+0x4b,0x04,0x11,0x22 = div.u	%e2, %d4, %d0
+# 0x09,0xef,0x65,0x48 = ld.bu	%d15,[%a14]293
+# 0x09,0xf0,0x20,0x19 = ld.w	%d0,[%a15]96
+# 0x85,0xf1,0x10,0x01 = ld.w	%d1,f0001010
+0x6e,0x30           = jz	%d15, 0x60
+0x4b,0xbf,0x41,0xf0 = mul.f	%d15, %d15, %d11
+0xd9,0xff,0x00,0x00 = lea	%a15, [%a15]0
+0x53,0xc9,0x20,0x00 = mul	%d0, %d9, 12
+0x3b,0xb0,0x7f,0x00 = mov	%d0, 2043
+0x3c,0x1f           = j	0x3e
+0x4b,0x0f,0x61,0xf1 = utof	%d15, %d15
+# 0x09,0xff,0x6b,0x08 = ld.bu	%d15,[%a15]43
+# 0xc8,0x1c           = ld.a	%a12,[%a15]4
+0x3b,0x90,0xd0,0x03 = mov	%d0, 15625
+# 0x09,0xe0,0x48,0x28 = ld.bu	%d0,[%a14]136
+# 0x59,0x2f,0xa8,0x56 = st.w	[%a2]26984
+# 0x59,0x4f,0x28,0xa6 = st.w	[%a4]25256
+0xb7,0x0f,0x01,0xf1 = insert	%d15, %d15, 0, 2, 1
+0x4b,0x0f,0x41,0xf0 = mul.f	%d15, %d15, %d0
+# 0x08,0xcf           = ld.bu	%d15,[%a15]12
+0x6d,0xb8,0xf4,0x11 = call	-0x8fdc18
+0x6e,0x1a           = jz	%d15, 0x34
+0x49,0x33,0x08,0x8a = lea	%a3, [%a3]-504
+0xc2,0x10           = add	%d0, 1
+0x37,0x5f,0x02,0xf0 = insert	%d15, %d15, %d5, 0, 2
+0x37,0x0f,0x62,0xf3 = extr.u	%d15, %d15, 6, 2
+# 0x09,0xf0,0x18,0x19 = ld.w	%d0,[%a15]88
+# 0x09,0xf0,0x59,0x08 = ld.bu	%d0,[%a15]25
+0xd9,0xff,0xb8,0x42 = lea	%a15, [%a15]10552
+# 0x19,0x2f,0xa4,0x56 = ld.w	%d15,[%a2]26980
+0x6d,0xff,0x45,0xfc = call	-0x776
+0x5f,0x2f,0xf4,0xff = jne	%d15, %d2, -0x18
+0xd9,0xff,0x74,0x30 = lea	%a15, [%a15]1268
+0x82,0x15           = mov	%d5, 1
+# 0x89,0xff,0x05,0x58 = st.b	[%a15]325,%d15
+# 0x09,0x4f,0x00,0x59 = ld.w	%d15,[%a4]320
+# 0x19,0x40,0x30,0x06 = ld.w	%d0,[%a4]24624
+0xdc,0x0b           = ji	%a11
+0xbb,0x00,0x40,0x2f = mov.u	%d2, 62464
+0xbb,0xf0,0xff,0x2f = mov.u	%d2, 65535
+0x6d,0x00,0x9e,0x03 = call	0x73c
+0x82,0x00           = mov	%d0, 0
+0x2d,0x0f,0x20,0x00 = jli	%a15
+0xbf,0x10,0x15,0x80 = jlt.u	%d0, 1, 0x2a
+# 0x85,0xf8,0x10,0x01 = ld.w	%d8,f0001010
+# 0x59,0x2f,0xa4,0x56 = st.w	[%a2]26980
+0x3c,0xd9           = j	-0x4e
+# 0x64,0xca           = st.w	[%a12+],%d10
+# 0x08,0xd0           = ld.bu	%d0,[%a15]13
+0x3e,0x58           = jeq	%d15, %d5, 0x10
+0x80,0xff           = mov.d	%d15, %a15
+0x37,0x04,0xe8,0x0b = extr.u	%d0, %d4, 23, 8
+# 0x09,0xff,0x0c,0x08 = ld.b	%d15,[%a15]12
+0x10,0xcc           = addsc.a	%a12, %a12, %d15, 0
+# 0x09,0xef,0x40,0x38 = ld.bu	%d15,[%a14]192
+# 0x39,0x2f,0x24,0x06 = ld.bu	%d15,[%a2]24612
+0x37,0x0f,0x62,0xf6 = extr.u	%d15, %d15, 12, 2
+0x37,0x0f,0xe7,0xf0 = extr.u	%d15, %d15, 1, 7
+# 0x39,0x41,0x01,0x80 = ld.bu	%d1,[%a4]513
+# 0x09,0xef,0x20,0x69 = ld.w	%d15,[%a14]416
+0x3c,0xc4           = j	-0x78
+# 0x64,0xc8           = st.w	[%a12+],%d8
+0x4b,0xf0,0x51,0x20 = div.f	%d2, %d0, %d15
+# 0x09,0xe2,0x30,0x69 = ld.w	%d2,[%a14]432
+0x82,0x07           = mov	%d7, 0
+0x3c,0x0b           = j	0x16
+# 0x39,0x2f,0x1b,0x06 = ld.bu	%d15,[%a2]24603
+0x6d,0xff,0xa6,0xff = call	-0xb4
+0x3f,0xf9,0x65,0xff = jlt.u	%d9, %d15, -0x136
+# 0x09,0xc2,0x84,0x09 = ld.a	%a2,[%a12]4
+# 0x09,0xc5,0x76,0x08 = ld.bu	%d5,[%a12]54
+0x37,0xf0,0x81,0xf1 = insert	%d15, %d0, %d15, 3, 1
+0x82,0x14           = mov	%d4, 1
+0x6e,0x0e           = jz	%d15, 0x1c
+0x53,0x41,0x20,0x10 = mul	%d1, %d1, 4
+0x10,0xf4           = addsc.a	%a4, %a15, %d15, 0
+0xa2,0x10           = sub	%d0, %d1
+0x6d,0x00,0x56,0x01 = call	0x2ac
+0x4b,0xf0,0x41,0xf0 = mul.f	%d15, %d0, %d15
+# 0x48,0x1f           = ld.w	%d15,[%a15]4
+# 0x89,0x2f,0x0a,0x28 = st.b	[%a2]138,%d15
+0x6d,0x88,0x80,0x11 = call	-0xefdd00
+0x3e,0x4b           = jeq	%d15, %d4, 0x16
+0xd9,0x11,0x00,0x00 = lea	%a1, [%a1]0
+0x4b,0xf0,0x51,0xf0 = div.f	%d15, %d0, %d15
+# 0x54,0xf0           = ld.w	%d0,[%a15]
+0x9b,0xe0,0xcb,0x04 = addih	%d0, %d0, 19646
+0x3c,0x20           = j	0x40
+0x37,0xf0,0x01,0xf0 = insert	%d15, %d0, %d15, 0, 1
+0xd9,0xff,0xc0,0x09 = lea	%a15, [%a15]-25600
+0xd9,0x44,0x28,0xa6 = lea	%a4, [%a4]25256
+0x6d,0xe8,0x90,0x0f = call	-0x2fe0e0
+# 0x08,0xaf           = ld.bu	%d15,[%a15]10
+0x60,0xf2           = mov.a	%a2, %d15
+0xda,0x1f           = mov	%d15, 31
+0x49,0xff,0x00,0x0a = lea	%a15, [%a15]0
+# 0x09,0x4f,0x04,0x29 = ld.w	%d15,[%a4]132
+# 0x09,0xc5,0x7e,0x08 = ld.bu	%d5,[%a12]62
+# 0x89,0xef,0x05,0x48 = st.b	[%a14]261,%d15
+# 0x14,0x2f           = ld.bu	%d15,[%a2]
+0x8f,0xf9,0x03,0xf1 = and	%d15, %d9, 63
+0xa6,0xf0           = or	%d0, %d15
+0x09,0xa0,0xc4,0x08 = ld.hu	%d0, [%sp]4
+# 0x09,0xf0,0x10,0x29 = ld.w	%d0,[%a15]144
+# 0x54,0x41           = ld.w	%d1,[%a4]
+# 0x89,0xff,0x03,0x28 = st.b	[%a15]131,%d15
+# 0x89,0xef,0x25,0x48 = st.b	[%a14]293,%d15
+# 0x59,0x20,0x2c,0x06 = st.w	[%a2]24620
+0x8f,0x29,0x20,0xf0 = sha	%d15, %d9, 2
+0x6d,0xff,0xab,0xfb = call	-0x8aa
+0x82,0x12           = mov	%d2, 1
+0xbb,0x00,0x68,0xf9 = mov.u	%d15, 38528
+0xfc,0x29           = loop	%a2, -0xe
+0x3b,0x00,0x10,0xf0 = mov	%d15, 256
+# 0x14,0xf0           = ld.bu	%d0,[%a15]
+0xd9,0x88,0x00,0x00 = lea	%a8, [%a8]0
+# 0x39,0x2f,0x43,0x20 = ld.bu	%d15,[%a2]1155
+0x8f,0x34,0x40,0xf1 = or	%d15, %d4, 3
+# 0x48,0xd3           = ld.w	%d3,[%a15]52
+0x91,0x00,0x06,0xfa = movh.a	%a15, 41056
+# 0x89,0xef,0x00,0x28 = st.b	[%a14]128,%d15
+0x8f,0x3c,0x00,0x41 = and	%d4, %d12, 3
+0x4b,0x01,0x51,0x00 = div.f	%d0, %d1, %d0
+0x91,0x10,0x00,0xf3 = movh.a	%a15, 12289
+0xc2,0xf3           = add	%d3, -1
+0x3c,0x00           = j	0x0
+0x37,0x04,0x68,0xf0 = extr.u	%d15, %d4, 0, 8
+0x0f,0x04,0x10,0x40 = sha	%d4, %d4, %d0
+0x8b,0xf0,0x2f,0x03 = min.u	%d0, %d0, 255
+0x6d,0xff,0x00,0xfb = call	-0xa00
+0x40,0x4f           = mov.aa	%a15, %a4
+0xbb,0xd0,0xcc,0x0c = mov.u	%d0, 52429
+0x37,0x4f,0x82,0xf6 = insert	%d15, %d15, %d4, 13, 2
+# 0x89,0x2f,0x08,0x28 = st.b	[%a2]136,%d15
+0x96,0x03           = or	%d15, 3
+0xc2,0x1f           = add	%d15, 1
+0xd9,0xff,0xf4,0x42 = lea	%a15, [%a15]11572
+0x10,0xff           = addsc.a	%a15, %a15, %d15, 0
+# 0x59,0x2f,0xa0,0x06 = st.w	[%a2]26656
+# 0x89,0xff,0x05,0x48 = st.b	[%a15]261,%d15
+0x4b,0x10,0x41,0x00 = mul.f	%d0, %d0, %d1
+# 0x08,0xa0           = ld.bu	%d0,[%a15]10
+# 0x39,0xff,0x33,0x06 = ld.bu	%d15,[%a15]24627
+0xb7,0x7f,0x08,0xf0 = insert	%d15, %d15, 7, 0, 8
+0xd9,0xff,0xa4,0x72 = lea	%a15, [%a15]10724
+# 0x89,0xff,0x20,0x28 = st.b	[%a15]160,%d15
+# 0x39,0xff,0x1b,0x06 = ld.bu	%d15,[%a15]24603
+0x8b,0x14,0x1f,0x00 = add	%d0, %d4, -15
+0x6d,0xff,0xb6,0xfa = call	-0xa94
+0x06,0xaf           = sh	%d15, -6
+0xe2,0x10           = mul	%d0, %d1
+0xdc,0x0f           = ji	%a15
+0x37,0x0f,0x02,0xfe = insert	%d15, %d15, %d0, 28, 2
+0x7f,0xf9,0x03,0x80 = jge.u	%d9, %d15, 0x6
+0x91,0x10,0x00,0x23 = movh.a	%a2, 12289
+# 0x24,0xc9           = st.b	[%a12+],%d9
+0xd9,0xff,0x0c,0x40 = lea	%a15, [%a15]268
+0x8b,0x09,0x01,0x00 = add	%d0, %d9, 16
+0x42,0xf0           = add	%d0, %d15
+# 0x89,0xe1,0x20,0x69 = st.w	[%a14]416,%d1
+# 0x59,0x2f,0xa0,0x56 = st.w	[%a2]26976
+# 0x09,0x29,0x48,0x08 = ld.bu	%d9,[%a2]8
+# 0x59,0x20,0x00,0x26 = st.w	[%a2]24704
+0x6f,0x1f,0xfc,0x7f = jz.t	%d15, 1, -0x8
+0x3c,0x64           = j	0xc8
+0x6d,0xff,0x0e,0xfb = call	-0x9e4
+0xee,0x06           = jnz	%d15, 0xc
+0x6d,0xff,0x32,0xff = call	-0x19c
+0x37,0x0f,0x6e,0xf1 = extr.u	%d15, %d15, 2, 14
+0x16,0x01           = and	%d15, 1
+0x6d,0x00,0xb7,0x00 = call	0x16e
+0x4b,0x08,0x61,0x01 = utof	%d0, %d8
+0x91,0x00,0x0f,0xf8 = movh.a	%a15, 33008
+# 0x08,0xf0           = ld.bu	%d0,[%a15]15
+0x40,0xc4           = mov.aa	%a4, %a12
+0x7b,0x00,0x00,0x14 = movh	%d1, 16384
+0x37,0x00,0x68,0x00 = extr.u	%d0, %d0, 0, 8
+0xb7,0x6f,0x08,0xf0 = insert	%d15, %d15, 6, 0, 8
+# 0x89,0x4f,0x04,0x29 = st.w	[%a4]132,%d15
+0xdf,0x1f,0x70,0x80 = jne	%d15, 1, 0xe0
+# 0x09,0xff,0x5c,0x08 = ld.bu	%d15,[%a15]28
+0xda,0x10           = mov	%d15, 16
+0x9a,0x81           = add	%d15, %d1, -8
+# 0x19,0x40,0x28,0xa6 = ld.w	%d0,[%a4]25256
+0xfc,0x2f           = loop	%a2, -0x2
+0xda,0x15           = mov	%d15, 21
+# 0x09,0xcf,0x7d,0x08 = ld.bu	%d15,[%a12]61
+0xd9,0xff,0x26,0xb2 = lea	%a15, [%a15]8934
+0x0f,0x05,0x10,0x50 = sha	%d5, %d5, %d0
+0xb0,0x4c           = add.a	%a12, 4
+# 0x09,0x24,0x00,0x08 = ld.b	%d4,[%a2]
+0xd9,0xff,0x00,0x06 = lea	%a15, [%a15]24576
+0x82,0x11           = mov	%d1, 1
+# 0xd4,0x22           = ld.a	%a2,[%a2]
+0x6f,0x20,0xf2,0x7f = jz.t	%d0, 2, -0x1c
+# 0x74,0x20           = st.w	[%a2],%d0
+0x3f,0x40,0xe3,0xff = jlt.u	%d0, %d4, -0x3a
+# 0x59,0x2f,0x14,0x26 = st.w	[%a2]24724
+0x76,0x6d           = jz	%d6, 0x1a
+0x49,0xcf,0x28,0x0a = lea	%a15, [%a12]40
+# 0x89,0x4f,0x25,0x08 = st.b	[%a4]37,%d15
+0xd9,0xaa,0x40,0x89 = lea	%sp, [%sp]-27136
+# 0x4d,0x40,0xe0,0xff = mfcr	%d15,$psw
+0x4b,0x1f,0x51,0xf0 = div.f	%d15, %d15, %d1
+0xbb,0x00,0xc2,0x1b = mov.u	%d1, 48160
+0xdf,0x1f,0x54,0x80 = jne	%d15, 1, 0xa8
+# 0x2c,0xa4           = st.b	[%sp]4,%d15
+0x6d,0x00,0x2d,0x07 = call	0xe5a
+0x0f,0x91,0x10,0x10 = sha	%d1, %d1, %d9
+0x80,0xd0           = mov.d	%d0, %a13
+0x4b,0x0f,0x71,0x01 = ftouz	%d0, %d15
+0xdf,0x04,0x7c,0x7f = jeq	%d4, 0, -0x108
+# 0x48,0xff           = ld.w	%d15,[%a15]60
+0x09,0xff,0xc6,0x08 = ld.hu	%d15, [%a15]6
+# 0x09,0xef,0x24,0x69 = ld.w	%d15,[%a14]420
+# 0xcd,0x4f,0xe0,0x0f = mtcr	$psw,%d15
+# 0x89,0x4f,0x0e,0x18 = st.b	[%a4]78,%d15
+0xdf,0x12,0x03,0x80 = jne	%d2, 1, 0x6
+# 0x09,0x4f,0x44,0x58 = ld.bu	%d15,[%a4]324
+0xd9,0xff,0x38,0xf2 = lea	%a15, [%a15]9208
+0x02,0xf1           = mov	%d1, %d15
+0x6d,0xff,0x80,0xff = call	-0x100
+0x86,0x24           = sha	%d4, 2
+0xfc,0x5e           = loop	%a5, -0x4
+0x7b,0x00,0x20,0x04 = movh	%d0, 16896
+0x53,0x20,0x20,0xf0 = mul	%d15, %d0, 2
+0x01,0xd0,0x00,0x26 = addsc.a	%a2, %a13, %d0, 0
+# 0x19,0x20,0x0c,0x16 = ld.w	%d0,[%a2]24652
+0x4b,0xf2,0x51,0xa0 = div.f	%d10, %d2, %d15
+# 0x89,0x4f,0x24,0x08 = st.b	[%a4]36,%d15
+0x5f,0x6f,0x23,0x00 = jeq	%d15, %d6, 0x46
+0x6d,0xff,0xdf,0xfa = call	-0xa42
+# 0x09,0xc4,0x72,0x08 = ld.bu	%d4,[%a12]50
+# 0x89,0xef,0x30,0x69 = st.w	[%a14]432,%d15
+# 0x24,0xcb           = st.b	[%a12+],%d11
+0xe2,0x1f           = mul	%d15, %d1
+0xc2,0x31           = add	%d1, 3
+0x9b,0x81,0xb9,0x14 = addih	%d1, %d1, 19352
+0x20,0x28           = sub.a	%sp, 40
+0xd9,0xff,0x0c,0xb0 = lea	%a15, [%a15]716
+# 0x39,0x4f,0x00,0x80 = ld.bu	%d15,[%a4]512
+0xbf,0x38,0xef,0xff = jlt.u	%d8, 3, -0x22
+0x37,0x0f,0x04,0xf0 = insert	%d15, %d15, %d0, 0, 4
+# 0x09,0x2f,0x48,0x28 = ld.bu	%d15,[%a2]136
+# 0x89,0x4f,0x26,0x08 = st.b	[%a4]38,%d15
+# 0x09,0xf3,0x24,0x19 = ld.w	%d3,[%a15]100
+# 0x74,0x3f           = st.w	[%a3],%d15
+# 0x39,0xff,0x2c,0x08 = ld.bu	%d15,[%a15]-32724
+0x7f,0x0f,0x07,0x80 = jge.u	%d15, %d0, 0xe
+0x3f,0xf0,0x05,0x80 = jlt.u	%d0, %d15, 0xa
+0x4e,0xf3           = jgtz	%d15, 0x6
+0x8f,0x00,0x21,0x00 = sha	%d0, %d0, 16
+0x80,0xf4           = mov.d	%d4, %a15
+# 0x89,0x4f,0x10,0x18 = st.b	[%a4]80,%d15
+0x6d,0xff,0xe6,0xfc = call	-0x634
+# 0x09,0xc4,0x7a,0x08 = ld.bu	%d4,[%a12]58
+# 0x39,0xff,0x19,0x06 = ld.bu	%d15,[%a15]24601
+0x02,0x28           = mov	%d8, %d2
+0xd9,0xff,0x70,0x20 = lea	%a15, [%a15]1200
+0xd9,0xff,0x24,0x96 = lea	%a15, [%a15]25188
+0xee,0x07           = jnz	%d15, 0xe
+0x9a,0xd4           = add	%d15, %d4, -3
+# 0xe9,0x20,0x01,0x80 = st.b	[%a2]513,%d0
+0xd9,0xff,0x0c,0x96 = lea	%a15, [%a15]25164
+0x06,0x3f           = sh	%d15, 3
+# 0x89,0x4f,0x04,0x58 = st.b	[%a4]324,%d15
+# 0x89,0xef,0x24,0x69 = st.w	[%a14]420,%d15
+0x0f,0x0f,0xb0,0xf1 = clz	%d15, %d15
+0xd9,0xff,0x00,0x40 = lea	%a15, [%a15]256
+# 0x89,0x20,0x0b,0x28 = st.b	[%a2]139,%d0
+0x91,0x00,0x0c,0xfa = movh.a	%a15, 41152
+0xe2,0x0f           = mul	%d15, %d0
+0x0f,0xf1,0x10,0x10 = sha	%d1, %d1, %d15
+0x6d,0x00,0xce,0x0d = call	0x1b9c
+0x4b,0x00,0x41,0xf1 = itof	%d15, %d0
+# 0x09,0xef,0x34,0x69 = ld.w	%d15,[%a14]436
+# 0x14,0x20           = ld.bu	%d0,[%a2]
+0xb7,0x0f,0x0c,0xfa = insert	%d15, %d15, 0, 20, 12
+# 0xe9,0xf0,0x2c,0xa6 = st.b	[%a15]25260
+0x8f,0xf9,0x01,0xf1 = and	%d15, %d9, 31
+0x6d,0xff,0x7b,0xfc = call	-0x70a
+0x4b,0x0f,0x41,0xf1 = itof	%d15, %d15
+0x53,0x4f,0x20,0xf0 = mul	%d15, %d15, 4
+0xb7,0x0f,0x01,0xfc = insert	%d15, %d15, 0, 24, 1
+0x89,0xcf,0x8a,0x28 = st.h	[%a12]138, %d15
+# 0x89,0xf0,0x08,0x29 = st.w	[%a15]136,%d0
+0xd9,0x22,0x04,0x00 = lea	%a2, [%a2]4
+0x49,0xcf,0x38,0x0a = lea	%a15, [%a12]56
+0x91,0x40,0x00,0xf6 = movh.a	%a15, 24580
+# 0x74,0xf1           = st.w	[%a15],%d1
+0xda,0x02           = mov	%d15, 2
+0xc6,0x3f           = xor	%d15, %d3
+0x96,0x80           = or	%d15, 128
+0x37,0x1f,0x02,0xf0 = insert	%d15, %d15, %d1, 0, 2
+0xa6,0x0f           = or	%d15, %d0
+0xa6,0x10           = or	%d0, %d1
+0x6d,0xff,0x78,0xfb = call	-0x910
+0x06,0xec           = sh	%d12, -2
+0x6e,0xef           = jz	%d15, -0x22
+# 0x09,0x4f,0x44,0x48 = ld.bu	%d15,[%a4]260
+0x37,0x01,0x70,0x20 = extr.u	%d2, %d1, 0, 16
+0x42,0xf1           = add	%d1, %d15
+# 0x09,0xcf,0x4c,0x18 = ld.bu	%d15,[%a12]76
+0x53,0x41,0x20,0xf0 = mul	%d15, %d1, 4
+0x5e,0x1b           = jne	%d15, 1, 0x16
+0xdf,0x0c,0x9b,0x7f = jeq	%d12, 0, -0xca
+0x3b,0x00,0x05,0x40 = mov	%d4, 80
+# 0x08,0x9f           = ld.bu	%d15,[%a15]9
+0xae,0x75           = jnz.t	%d15, 7, 0xa
+0xe2,0x90           = mul	%d0, %d9
+# 0x39,0xf0,0x0b,0x48 = ld.bu	%d0,[%a15]-32501
+0xd9,0xff,0x34,0x23 = lea	%a15, [%a15]12468
+# 0x09,0xff,0x10,0x01 = ld.w	%d15,[%a15+]16
+0x3f,0xf0,0xfd,0xff = jlt.u	%d0, %d15, -0x6
+0x26,0xf0           = and	%d0, %d15
+0x86,0x21           = sha	%d1, 2
+# 0x39,0xf0,0x2c,0xa6 = ld.bu	%d0,[%a15]25260
+0x82,0x17           = mov	%d7, 1
+0xbb,0x70,0x71,0xfb = mov.u	%d15, 46871
+0x60,0x22           = mov.a	%a2, %d2
+0x6d,0xff,0xd2,0xe7 = call	-0x305c
+# 0x74,0x4f           = st.w	[%a4],%d15
+0xbc,0xf1           = jz.a	%a15, 0x2
+# 0x59,0x20,0x28,0x06 = st.w	[%a2]24616
+# 0x89,0x4f,0x20,0x49 = st.w	[%a4]288,%d15
+0xda,0x00           = mov	%d15, 0
+0x91,0x10,0x00,0x24 = movh.a	%a2, 16385
+0x37,0x0f,0xe1,0xf3 = extr.u	%d15, %d15, 7, 1
+0x10,0xcf           = addsc.a	%a15, %a12, %d15, 0
+0x3c,0x27           = j	0x4e
+0x6d,0xe8,0x80,0x11 = call	-0x2fdd00
+0x3c,0x0a           = j	0x14
+0x80,0xf2           = mov.d	%d2, %a15
+0x96,0x01           = or	%d15, 1
+# 0x09,0xc6,0x77,0x08 = ld.bu	%d6,[%a12]55
+0x9a,0x20           = add	%d15, %d0, 2
+0x7b,0x00,0xf0,0x13 = movh	%d1, 16128
+# 0x89,0xe2,0x34,0x69 = st.w	[%a14]436,%d2
+0x40,0xbf           = mov.aa	%a15, %a11
+0x37,0xf3,0x08,0x30 = insert	%d3, %d3, %d15, 0, 8
+# 0x09,0xff,0x45,0x48 = ld.bu	%d15,[%a15]261
+0x60,0xc2           = mov.a	%a2, %d12
+0x37,0xf0,0x02,0x06 = insert	%d0, %d0, %d15, 12, 2
+0x7f,0x0f,0x04,0x80 = jge.u	%d15, %d0, 0x8
+0x37,0xf0,0x02,0x0e = insert	%d0, %d0, %d15, 28, 2
+0x26,0x30           = and	%d0, %d3
+0xd9,0x22,0xc0,0x0b = lea	%a2, [%a2]-17408
+0x76,0xcf           = jz	%d12, 0x1e
+0xda,0x14           = mov	%d15, 20
+0x96,0x04           = or	%d15, 4
+0x26,0x10           = and	%d0, %d1
+0xc5,0x06,0x14,0x00 = lea	%a6, 0x14
+0xda,0x0c           = mov	%d15, 12
+0x6d,0xff,0xb8,0xf2 = call	-0x1a90
+0x3c,0x94           = j	-0xd8
+0x16,0x0f           = and	%d15, 15
+0x37,0x5f,0x04,0xf4 = insert	%d15, %d15, %d5, 8, 4
+0xd9,0x00,0x00,0x00 = lea	%a0, [%a0]0
+0x8f,0x24,0x40,0xf1 = or	%d15, %d4, 2
+0xdf,0x04,0x3b,0x00 = jeq	%d4, 0, 0x76
+0xa6,0xf1           = or	%d1, %d15
+# 0x54,0xff           = ld.w	%d15,[%a15]
+0xdf,0x0c,0x86,0x7f = jeq	%d12, 0, -0xf4
+0x3e,0x4a           = jeq	%d15, %d4, 0x14
+0xff,0xc9,0x03,0x80 = jge.u	%d9, 12, 0x6
+0x82,0x19           = mov	%d9, 1
+# 0x64,0xc1           = st.w	[%a12+],%d1
+# 0x2c,0xf4           = st.b	[%a15]4,%d15
+0x10,0xe5           = addsc.a	%a5, %a14, %d15, 0
+0x37,0x0f,0xe2,0xf0 = extr.u	%d15, %d15, 1, 2
+# 0x19,0xf0,0x18,0x06 = ld.w	%d0,[%a15]24600
+# 0x59,0x2f,0x0c,0x26 = st.w	[%a2]24716
+0x3c,0x07           = j	0xe
+0x3e,0x1b           = jeq	%d15, %d1, 0x16
+# 0x39,0x2f,0x33,0x06 = ld.bu	%d15,[%a2]24627
+0x3e,0x67           = jeq	%d15, %d6, 0xe
+0x0f,0x0f,0x10,0xf0 = sha	%d15, %d15, %d0
+0xd9,0x99,0x00,0x00 = lea	%a9, [%a9]0
+0xdf,0x1f,0x7f,0x80 = jne	%d15, 1, 0xfe
+0x15,0xd0,0xc0,0xf7 = stucx	0xd0003fc0
+0x4b,0xf0,0x11,0x02 = div.u	%e0, %d0, %d15
+# 0x4c,0x51           = ld.w	%d15,[%a5]4
+0x4b,0x0f,0x71,0xf1 = ftouz	%d15, %d15
+0x3f,0x0f,0x04,0x80 = jlt.u	%d15, %d0, 0x8
+0x82,0x0b           = mov	%d11, 0
+# 0x09,0xff,0x45,0x58 = ld.bu	%d15,[%a15]325
+# 0x39,0x4f,0x01,0x80 = ld.bu	%d15,[%a4]513
+# 0x28,0x89           = st.b	[%a15]8,%d9
+0x76,0x91           = jz	%d9, 0x2
+0x30,0x43           = add.a	%a3, %a4
+0x3e,0x4e           = jeq	%d15, %d4, 0x1c
+# 0x59,0x2f,0x30,0x06 = st.w	[%a2]24624
+# 0x59,0x2f,0xa0,0x76 = st.w	[%a2]27104
+# 0x2c,0x21           = st.b	[%a2]1,%d15
+0x91,0x40,0x00,0x26 = movh.a	%a2, 24580
+# 0x08,0xc0           = ld.bu	%d0,[%a15]12
+0x6d,0xff,0xf4,0xfa = call	-0xa18
+0x1d,0x00,0x02,0x00 = j	0x4
+# 0x09,0xc0,0x4b,0x18 = ld.bu	%d0,[%a12]75
+# 0x08,0x1f           = ld.bu	%d15,[%a15]1
+0x37,0x0f,0x61,0xf2 = extr.u	%d15, %d15, 4, 1
+0x1e,0x12           = jeq	%d15, 1, 0x4
+0x49,0xa4,0x00,0x0a = lea	%a4, [%sp]0
+# 0xc8,0x14           = ld.a	%a4,[%a15]4
+0x7f,0xf9,0x04,0x80 = jge.u	%d9, %d15, 0x8
+0x8f,0x10,0x00,0x01 = and	%d0, %d0, 1
+0x49,0xf2,0x1c,0x0a = lea	%a2, [%a15]28
+0xfe,0xdb           = jne	%d15, %d13, 0x36
+0x37,0x00,0xe7,0x00 = extr.u	%d0, %d0, 1, 7
+0x3b,0xf0,0x00,0x30 = mov	%d3, 15
+0x6e,0x09           = jz	%d15, 0x12
+0x7e,0x05           = jne	%d15, %d0, 0xa
+# 0x39,0x2f,0x2c,0x08 = ld.bu	%d15,[%a2]-32724
+0x82,0x04           = mov	%d4, 0
+0x15,0xd0,0xc0,0xff = lducx	0xd0003fc0
+# 0x74,0x22           = st.w	[%a2],%d2
+0xd9,0xff,0x30,0x96 = lea	%a15, [%a15]25200
+0x8f,0xff,0x83,0x11 = xor	%d1, %d15, 63
+0x5e,0x14           = jne	%d15, 1, 0x8
+# 0x09,0x2e,0x84,0x09 = ld.a	%a14,[%a2]4
+0x7f,0xf9,0x0b,0x80 = jge.u	%d9, %d15, 0x16
+0xd7,0x10,0x21,0x0f = imask	%e0, 1, %d15, 1
+# 0x09,0x2b,0x02,0x09 = ld.w	%d11,[%a2]2
+# 0x89,0x4f,0x12,0x18 = st.b	[%a4]82,%d15
+0x01,0xdd,0x00,0xd6 = addsc.a	%a13, %a13, %d13, 0
+0xd9,0x44,0x08,0x60 = lea	%a4, [%a4]392
+0x37,0xf0,0x02,0x02 = insert	%d0, %d0, %d15, 4, 2
+0x3e,0x93           = jeq	%d15, %d9, 0x6
+0x6d,0xd0,0xf4,0x11 = call	-0x5fdc18
+# 0x39,0x2f,0x0f,0x16 = ld.bu	%d15,[%a2]24655
+0x40,0xd4           = mov.aa	%a4, %a13
+0x4b,0x0f,0x71,0x41 = ftouz	%d4, %d15
+# 0x89,0x2f,0x00,0x28 = st.b	[%a2]128,%d15
+0xbf,0xc9,0x06,0x80 = jlt.u	%d9, 12, 0xc
+0xd9,0xff,0xec,0xe2 = lea	%a15, [%a15]12204
+0x37,0x00,0xe1,0x00 = extr.u	%d0, %d0, 1, 1
+0x96,0x08           = or	%d15, 8
+0xdf,0x0c,0xd3,0x7f = jeq	%d12, 0, -0x5a
+0x91,0x00,0x00,0x47 = movh.a	%a4, 28672
+0xfd,0xf0,0xed,0x7f = loop	%a15, -0x26
+# 0x19,0x20,0x30,0x06 = ld.w	%d0,[%a2]24624
+0xd9,0x44,0x18,0x60 = lea	%a4, [%a4]408
+0x82,0x30           = mov	%d0, 3
+0xdf,0x10,0xea,0x7f = jeq	%d0, 1, -0x2c
+0xda,0x96           = mov	%d15, 150
+0xa2,0xfc           = sub	%d12, %d15
+# 0x09,0xc5,0x6e,0x08 = ld.bu	%d5,[%a12]46
+0x49,0x33,0x14,0x8a = lea	%a3, [%a3]-492
+# 0x09,0xe1,0x20,0x69 = ld.w	%d1,[%a14]416
+0x37,0x09,0x68,0x90 = extr.u	%d9, %d9, 0, 8
+0x37,0xf0,0x03,0x0c = insert	%d0, %d0, %d15, 24, 3
+0x8f,0x3f,0x00,0x30 = sh	%d3, %d15, 3
+0x6f,0x1f,0x12,0x00 = jz.t	%d15, 1, 0x24
+0x40,0x5c           = mov.aa	%a12, %a5
+# 0x19,0x2f,0x10,0x26 = ld.w	%d15,[%a2]24720
+0x91,0x20,0x00,0x30 = movh.a	%a3, 2
+0xb7,0x3f,0x08,0xf0 = insert	%d15, %d15, 3, 0, 8
+0x6d,0xd0,0x80,0x11 = call	-0x5fdd00
+0x3c,0x16           = j	0x2c
+0xee,0x04           = jnz	%d15, 0x8
+0x4b,0xf2,0x51,0xf0 = div.f	%d15, %d2, %d15
+0x3f,0x0f,0xfd,0xff = jlt.u	%d15, %d0, -0x6
+0xd9,0xff,0x0c,0x60 = lea	%a15, [%a15]396
+0x26,0xf1           = and	%d1, %d15
+0x6d,0xff,0xc5,0xfe = call	-0x276
+0x3c,0x06           = j	0xc
+0x6d,0x00,0x63,0x00 = call	0xc6
+# 0x19,0x20,0x2c,0x06 = ld.w	%d0,[%a2]24620
+0x37,0x0f,0x83,0xf1 = insert	%d15, %d15, %d0, 3, 3
+# 0x19,0x2f,0x0c,0x26 = ld.w	%d15,[%a2]24716
+# 0x39,0xff,0x2c,0xa6 = ld.bu	%d15,[%a15]25260
+# 0x59,0xff,0x28,0xa6 = st.w	[%a15]25256
+0x15,0xd0,0xc0,0xeb = ldlcx	0xd0003f80
+0x82,0x01           = mov	%d1, 0
+0x37,0x00,0x48,0xf0 = extr	%d15, %d0, 0, 8
+0x3c,0x19           = j	0x32
+0x6d,0xff,0x1f,0xfb = call	-0x9c2
+0x37,0xf0,0x87,0x04 = insert	%d0, %d0, %d15, 9, 7
+# 0xe9,0x2f,0x02,0x80 = st.b	[%a2]514,%d15
+0x6d,0xff,0x43,0xfd = call	-0x57a
+0x3f,0x10,0x97,0xff = jlt.u	%d0, %d1, -0xd2
+0x3c,0x21           = j	0x42
+# 0x09,0xf0,0x53,0x08 = ld.bu	%d0,[%a15]19
+# 0x09,0xf3,0x0c,0x19 = ld.w	%d3,[%a15]76
+0x8f,0x21,0x00,0xf0 = sh	%d15, %d1, 2
+0x49,0xff,0x20,0x0a = lea	%a15, [%a15]32
+0x37,0x0f,0x62,0xf2 = extr.u	%d15, %d15, 4, 2
+0x53,0x4a,0x20,0x10 = mul	%d1, %d10, 4
+0xb7,0x00,0x81,0x01 = insert	%d0, %d0, 0, 3, 1
+0xa0,0x04           = mov.a	%a4, 0
+0x37,0x0f,0xe1,0xf2 = extr.u	%d15, %d15, 5, 1
+0x6d,0x00,0x1b,0x0e = call	0x1c36
+0x0f,0x0f,0x00,0xf0 = sh	%d15, %d15, %d0
+0x37,0x00,0x61,0x03 = extr.u	%d0, %d0, 6, 1
+0x10,0xf2           = addsc.a	%a2, %a15, %d15, 0
+0x4b,0xf1,0x51,0x20 = div.f	%d2, %d1, %d15
+0x37,0x0f,0x05,0xf8 = insert	%d15, %d15, %d0, 16, 5
+# 0x14,0x5f           = ld.bu	%d15,[%a5]
+0x82,0xf1           = mov	%d1, -1
+0x6d,0xff,0x8b,0xfb = call	-0x8ea
+0x37,0xf3,0x08,0x34 = insert	%d3, %d3, %d15, 8, 8
+0xa2,0xf0           = sub	%d0, %d15
+0x3c,0x0f           = j	0x1e
+0x3c,0xfe           = j	-0x4
+# 0x14,0xcf           = ld.bu	%d15,[%a12]
+0x6d,0xff,0x57,0xfc = call	-0x752
+0x91,0x00,0x00,0x27 = movh.a	%a2, 28672
+# 0x19,0xf1,0x00,0xc0 = ld.w	%d1,[%a15]768
+# 0x09,0xff,0x6c,0x08 = ld.bu	%d15,[%a15]44
+0x82,0xf2           = mov	%d2, -1
+0x40,0xe4           = mov.aa	%a4, %a14
+0xbb,0x00,0xc2,0x2b = mov.u	%d2, 48160
+0x9b,0xb0,0xbf,0x04 = addih	%d0, %d0, 19451
+0x6d,0xe8,0xe1,0x0e = call	-0x2fe23e
+0x6d,0xff,0x4b,0xfb = call	-0x96a
+# 0x19,0x2f,0x34,0xa6 = ld.w	%d15,[%a2]25268
+0x7f,0x20,0x04,0x80 = jge.u	%d0, %d2, 0x8
+0x6d,0xff,0x6f,0xfc = call	-0x722
+0x3c,0x23           = j	0x46
+0xdf,0x0f,0x08,0x82 = jne	%d15, 0, 0x410
+0x82,0xff           = mov	%d15, -1
+# 0x09,0xf0,0x10,0x19 = ld.w	%d0,[%a15]80
+# 0x89,0x4f,0x04,0x48 = st.b	[%a4]260,%d15
+0x49,0xa5,0x00,0x0a = lea	%a5, [%sp]0
+# 0x09,0xf3,0x14,0x19 = ld.w	%d3,[%a15]84
+0xef,0x4f,0x04,0x00 = jz.t	%d15, 20, 0x8
+0x16,0x07           = and	%d15, 7
+0x37,0x0f,0x01,0xf1 = insert	%d15, %d15, %d0, 2, 1
+0x37,0xf0,0x01,0x0f = insert	%d0, %d0, %d15, 30, 1
+0x8f,0x3c,0x00,0x01 = and	%d0, %d12, 3
+0x6d,0x00,0x0f,0x01 = call	0x21e
+0x53,0xcf,0x20,0xf0 = mul	%d15, %d15, 12
+# 0x39,0x4f,0x02,0x80 = ld.bu	%d15,[%a4]514
+# 0x09,0xcf,0x4f,0x18 = ld.bu	%d15,[%a12]79
+0xdf,0x1f,0xfa,0x7f = jeq	%d15, 1, -0xc
+# 0x09,0x2f,0x60,0x28 = ld.bu	%d15,[%a2]160
+# 0x54,0x40           = ld.w	%d0,[%a4]
+0x7b,0xa0,0x47,0x04 = movh	%d0, 17530
+# 0x09,0xcf,0x53,0x18 = ld.bu	%d15,[%a12]83
+# 0x09,0xf3,0x1c,0x19 = ld.w	%d3,[%a15]92
+0x8f,0x3f,0x00,0x01 = and	%d0, %d15, 3
+0xd9,0xff,0x08,0xa6 = lea	%a15, [%a15]25224
+0x3c,0x13           = j	0x26
+0x49,0xfc,0x14,0x0a = lea	%a12, [%a15]20
+0x6d,0xff,0x83,0xfc = call	-0x6fa
+# 0x48,0xef           = ld.w	%d15,[%a15]56
+# 0x59,0xf0,0x18,0x06 = st.w	[%a15]24600
+0xee,0x02           = jnz	%d15, 0x4
+0x6d,0xff,0xce,0xfb = call	-0x864
+# 0x64,0x2f           = st.w	[%a2+],%d15
+# 0x48,0xaf           = ld.w	%d15,[%a15]40
+0x91,0x30,0x00,0x3f = movh.a	%a3, 61443
+0x91,0x00,0x09,0xfa = movh.a	%a15, 41104
+0x8f,0xff,0x83,0x41 = xor	%d4, %d15, 63
+0x6d,0x00,0xb4,0x07 = call	0xf68
+0xd9,0xff,0x24,0xf0 = lea	%a15, [%a15]996
+# 0x08,0x10           = ld.bu	%d0,[%a15]1
+0x6d,0xff,0xb8,0xff = call	-0x90
+0x37,0x00,0x62,0xfe = extr.u	%d15, %d0, 28, 2
+# 0x09,0xf0,0x08,0x29 = ld.w	%d0,[%a15]136
+0xb7,0x7f,0x03,0xfe = insert	%d15, %d15, 7, 28, 3
+# 0xf4,0x45           = st.a	[%a4],%a5
+0xbb,0x00,0xa0,0x1b = mov.u	%d1, 47616
+0xda,0x20           = mov	%d15, 32
+0x3c,0x17           = j	0x2e
+0x37,0x0f,0x02,0xf3 = insert	%d15, %d15, %d0, 6, 2
+0x01,0xf0,0x00,0xf6 = addsc.a	%a15, %a15, %d0, 0
+# 0xcc,0x21           = ld.a	%a15,[%a2]4
+0xd9,0x2e,0x40,0x00 = lea	%a14, [%a2]1024
+# 0x89,0x4f,0x00,0x49 = st.w	[%a4]256,%d15
+0x6d,0xa0,0xf4,0x11 = call	-0xbfdc18
+0x32,0x5f           = rsub	%d15
+0x3c,0x25           = j	0x4a
+0x53,0xc2,0x20,0xf0 = mul	%d15, %d2, 12
+# 0x09,0xc0,0x7b,0x08 = ld.bu	%d0,[%a12]59
+0x91,0x20,0x00,0x5f = movh.a	%a5, 61442
+# 0x09,0x50,0x65,0x08 = ld.bu	%d0,[%a5]37
+0xd9,0x44,0x3c,0x50 = lea	%a4, [%a4]380
+0xfc,0x6e           = loop	%a6, -0x4
+0xb7,0x2f,0x08,0xf0 = insert	%d15, %d15, 2, 0, 8
+0x91,0x10,0x00,0xf5 = movh.a	%a15, 20481
+0xd9,0xff,0xc4,0xc2 = lea	%a15, [%a15]12036
+0xbf,0x81,0x03,0x80 = jlt.u	%d1, 8, 0x6
+0xbf,0x21,0xcd,0xff = jlt.u	%d1, 2, -0x66
+0x82,0x20           = mov	%d0, 2
+0x6f,0x10,0xf2,0x7f = jz.t	%d0, 1, -0x1c
+# 0x89,0xef,0x34,0x69 = st.w	[%a14]436,%d15
+0x0f,0x10,0x00,0x00 = sh	%d0, %d0, %d1
+# 0x09,0x20,0x40,0x28 = ld.bu	%d0,[%a2]128
+# 0x2c,0xa5           = st.b	[%sp]5,%d15
+# 0xc8,0x62           = ld.a	%a2,[%a15]24
+# 0x39,0x20,0x14,0x06 = ld.bu	%d0,[%a2]24596
+# 0x09,0xc6,0x6f,0x08 = ld.bu	%d6,[%a12]47
+0x3e,0x46           = jeq	%d15, %d4, 0xc
+0xbb,0x00,0x68,0x19 = mov.u	%d1, 38528
+# 0xcd,0x81,0xe3,0x0f = mtcr	$fcx,%d1
+0x6e,0x04           = jz	%d15, 0x8
+0x6e,0xf6           = jz	%d15, -0x14
+0x9b,0x8f,0xb9,0xf4 = addih	%d15, %d15, 19352
+0x37,0x0f,0x02,0xf0 = insert	%d15, %d15, %d0, 0, 2
+# 0x09,0xc5,0x73,0x08 = ld.bu	%d5,[%a12]51
+0x6d,0xff,0x22,0xfb = call	-0x9bc
+# 0x89,0x4f,0x09,0x18 = st.b	[%a4]73,%d15
+0x37,0x0f,0x04,0xf2 = insert	%d15, %d15, %d0, 4, 4
+# 0x85,0xdf,0xc4,0xf3 = ld.w	%d15,d0003fc4
+0x42,0x01           = add	%d1, %d0
+0x37,0x01,0x68,0xfc = extr.u	%d15, %d1, 24, 8
+# 0x59,0x2f,0x08,0x26 = st.w	[%a2]24712
+0xc6,0x2f           = xor	%d15, %d2
+# 0x09,0x4f,0x64,0x48 = ld.bu	%d15,[%a4]292
+# 0x19,0x2f,0x14,0x26 = ld.w	%d15,[%a2]24724
+0xbe,0x6a           = jeq	%d15, %d6, 0x34
+# 0x48,0xcf           = ld.w	%d15,[%a15]48
+0xbf,0x89,0x06,0x80 = jlt.u	%d9, 8, 0xc
+0xd9,0xff,0x7a,0x50 = lea	%a15, [%a15]1402
+0x6d,0xff,0xef,0xfb = call	-0x822
+# 0x89,0xef,0x14,0x69 = st.w	[%a14]404,%d15
+0x6f,0x0f,0xff,0x7f = jz.t	%d15, 0, -0x2
+0x6d,0x00,0xf1,0x00 = call	0x1e2
+0x6d,0x00,0x26,0x05 = call	0xa4c
+0xc2,0x18           = add	%d8, 1
+0x6d,0x00,0x1a,0x09 = call	0x1234
+0x26,0x3f           = and	%d15, %d3
+0xa6,0x5f           = or	%d15, %d5
+0x4b,0x00,0x41,0x01 = itof	%d0, %d0
+0x37,0x0f,0x02,0xf2 = insert	%d15, %d15, %d0, 4, 2
+# 0x09,0xcf,0x50,0x18 = ld.bu	%d15,[%a12]80
+0x96,0x02           = or	%d15, 2
+0x8f,0x24,0x00,0x00 = sh	%d0, %d4, 2
+# 0xcd,0x0f,0x04,0x09 = mtcr	$dcon0,%d15
+# 0x09,0xc4,0x6a,0x08 = ld.bu	%d4,[%a12]42
+0x6d,0xff,0xe0,0xfb = call	-0x840
+0x6d,0xff,0x5b,0xfc = call	-0x74a
+0xc2,0xe0           = add	%d0, -2
+# 0x09,0xc5,0x7b,0x08 = ld.bu	%d5,[%a12]59
+0xde,0x28           = jne	%d15, 2, 0x30
+0x37,0xf0,0x05,0xf2 = insert	%d15, %d0, %d15, 4, 5
+# 0x08,0x80           = ld.bu	%d0,[%a15]8
+0xd9,0xaa,0x40,0x85 = lea	%sp, [%sp]22016
+# 0x39,0xff,0x1c,0x06 = ld.bu	%d15,[%a15]24604
+0x7f,0xf0,0x19,0x00 = jge	%d0, %d15, 0x32
+0xf6,0x24           = jnz	%d2, 0x8
+# 0x19,0xf0,0x18,0x16 = ld.w	%d0,[%a15]24664
+# 0x89,0x45,0x94,0x09 = st.a	[%a4]20,%a5
+0x7e,0x0d           = jne	%d15, %d0, 0x1a
+0x6d,0xff,0x8b,0xff = call	-0xea
+# 0x09,0xc0,0x73,0x08 = ld.bu	%d0,[%a12]51
+# 0xf4,0x4d           = st.a	[%a4],%a13
+0x10,0xe2           = addsc.a	%a2, %a14, %d15, 0
+# 0x39,0x20,0x24,0x06 = ld.bu	%d0,[%a2]24612
+0xb7,0x01,0x02,0x20 = insert	%d2, %d1, 0, 0, 2
+0x06,0x1f           = sh	%d15, 1
+0x91,0x10,0x00,0xa4 = movh.a	%sp, 16385
+0x3f,0xf2,0xf3,0x7f = jlt	%d2, %d15, -0x1a
+0x6d,0x00,0x25,0x0d = call	0x1a4a
+0x3c,0x01           = j	0x2
+0x9b,0xb1,0xa5,0x14 = addih	%d1, %d1, 19035
+0xb7,0x04,0x08,0xfc = insert	%d15, %d4, 0, 24, 8
+0x4b,0xf2,0x41,0xf0 = mul.f	%d15, %d2, %d15
+0x20,0x08           = sub.a	%sp, 8
+# 0x39,0x2f,0x03,0x16 = ld.bu	%d15,[%a2]24643
+# 0x09,0xef,0x45,0x58 = ld.bu	%d15,[%a14]325
+0x6d,0x00,0x91,0x00 = call	0x122
+0xbf,0xc9,0x07,0x80 = jlt.u	%d9, 12, 0xe
+0x7b,0x00,0x00,0xf4 = movh	%d15, 16384
+# 0x09,0xcf,0x75,0x08 = ld.bu	%d15,[%a12]53
+0x6d,0x00,0x4b,0x00 = call	0x96
+0x02,0x8f           = mov	%d15, %d8
+0x3c,0x1b           = j	0x36
+0xb7,0x0f,0x08,0xf0 = insert	%d15, %d15, 0, 0, 8
+0xae,0x17           = jnz.t	%d15, 1, 0xe
+0x8b,0x09,0x01,0xf0 = add	%d15, %d9, 16
+0x53,0x47,0x20,0x10 = mul	%d1, %d7, 4
+0x37,0xf0,0x01,0x00 = insert	%d0, %d0, %d15, 0, 1
+0x6d,0xa0,0x80,0x11 = call	-0xbfdd00
+# 0x54,0x2f           = ld.w	%d15,[%a2]
+0x3c,0x1a           = j	0x34
+0x37,0xf3,0x08,0x38 = insert	%d3, %d3, %d15, 16, 8
+0xb7,0x1f,0x08,0xf0 = insert	%d15, %d15, 1, 0, 8
+# 0x08,0x7f           = ld.bu	%d15,[%a15]7
+# 0x48,0x8f           = ld.w	%d15,[%a15]32
+# 0x09,0x4f,0x00,0x29 = ld.w	%d15,[%a4]128
+0x7e,0x92           = jne	%d15, %d9, 0x4
+# 0x44,0x21           = ld.w	%d1,[%a2+]
+0x91,0x00,0x06,0xf8 = movh.a	%a15, 32864
+0xd9,0x55,0x3c,0x50 = lea	%a5, [%a5]380
+0x3e,0x0e           = jeq	%d15, %d0, 0x1c
+0xdf,0x10,0x0a,0x80 = jne	%d0, 1, 0x14
+0xd9,0xff,0x80,0xc9 = lea	%a15, [%a15]-25856
+0x91,0x10,0x00,0xa1 = movh.a	%sp, 4097
+# 0x2c,0xc1           = st.b	[%a12]1,%d15
+0x8b,0xff,0x01,0xf1 = rsub	%d15, %d15, 31
+0x82,0x05           = mov	%d5, 0
+0x3c,0x12           = j	0x24
+0xd9,0xff,0xc8,0x22 = lea	%a15, [%a15]11400
+0x91,0x10,0x00,0x25 = movh.a	%a2, 20481
+0xc6,0xf1           = xor	%d1, %d15
+0x6e,0x07           = jz	%d15, 0xe
+0x3e,0x56           = jeq	%d15, %d5, 0xc
+0x3c,0x09           = j	0x12
+0x91,0x00,0x00,0xf8 = movh.a	%a15, 32768
+0x7e,0x09           = jne	%d15, %d0, 0x12
+# 0xcd,0x8f,0xe2,0x0f = mtcr	$isp,%d15
+# 0x89,0x44,0x10,0x49 = st.w	[%a4]272,%d4
+0x53,0x47,0x20,0x00 = mul	%d0, %d7, 4
+0xfe,0x04           = jne	%d15, %d0, 0x28
+0x02,0x84           = mov	%d4, %d8
+0x6d,0x00,0x15,0x00 = call	0x2a
+# 0x2c,0x23           = st.b	[%a2]3,%d15
+# 0x09,0xf0,0x0c,0x08 = ld.b	%d0,[%a15]12
+# 0x59,0x2f,0x34,0xa6 = st.w	[%a2]25268
+0x49,0xf5,0x00,0x0a = lea	%a5, [%a15]0
+# 0x19,0x20,0x18,0x06 = ld.w	%d0,[%a2]24600
+# 0x08,0xff           = ld.bu	%d15,[%a15]15
+# 0x09,0xc5,0x6b,0x08 = ld.bu	%d5,[%a12]43
+# 0x09,0x2f,0x61,0x28 = ld.bu	%d15,[%a2]161
+# 0x09,0xff,0x5b,0x08 = ld.bu	%d15,[%a15]27
+# 0x89,0x4f,0x0b,0x18 = st.b	[%a4]75,%d15
+0x8f,0x21,0x20,0xf0 = sha	%d15, %d1, 2
+0x3e,0x06           = jeq	%d15, %d0, 0xc
+0x01,0xcd,0x00,0xc6 = addsc.a	%a12, %a12, %d13, 0
+0xd9,0xff,0xc0,0x05 = lea	%a15, [%a15]23552
+# 0x08,0xbf           = ld.bu	%d15,[%a15]11
+0x37,0x0f,0x68,0xf0 = extr.u	%d15, %d15, 0, 8
+# 0x89,0xef,0x05,0x58 = st.b	[%a14]325,%d15
+0x6d,0x00,0xc6,0x07 = call	0xf8c
+0x37,0xf0,0x02,0x0a = insert	%d0, %d0, %d15, 20, 2
+0xc2,0x81           = add	%d1, -8
+0x37,0xf0,0x02,0xf0 = insert	%d15, %d0, %d15, 0, 2
+0xda,0x0f           = mov	%d15, 15
+0x6d,0x00,0xd8,0x0c = call	0x19b0
+# 0x09,0xe1,0x24,0x69 = ld.w	%d1,[%a14]420
+0x8b,0x5f,0x20,0xf3 = min.u	%d15, %d15, 5
+0x49,0xf4,0x00,0x0a = lea	%a4, [%a15]0
+0x37,0x0f,0x05,0xf0 = insert	%d15, %d15, %d0, 0, 5
+0x3b,0x00,0x00,0x06 = mov	%d0, 24576
+0x91,0x00,0x10,0xf8 = movh.a	%a15, 33024
+# 0x08,0xe0           = ld.bu	%d0,[%a15]14
+# 0x89,0x4f,0x00,0x29 = st.w	[%a4]128,%d15
+0xda,0x05           = mov	%d15, 5
+# 0x0c,0x23           = ld.bu	%d15,[%a2]3
+0x6f,0x20,0xf8,0x7f = jz.t	%d0, 2, -0x10
+0x02,0x2f           = mov	%d15, %d2
+0xa6,0x30           = or	%d0, %d3
+0x91,0x10,0x00,0xa5 = movh.a	%sp, 20481
+0x7b,0xc0,0xff,0x0f = movh	%d0, 65532
+0x6d,0x00,0xd3,0x0d = call	0x1ba6
+0x4b,0x30,0x11,0x42 = div.u	%e4, %d0, %d3
+0x1e,0x17           = jeq	%d15, 1, 0xe
+0x26,0x0f           = and	%d15, %d0
+0x8f,0x0f,0x1f,0x00 = sh	%d0, %d15, -16
+# 0x09,0xcf,0x41,0x18 = ld.bu	%d15,[%a12]65
+0x0f,0x31,0x10,0x10 = sha	%d1, %d1, %d3
+0x53,0x01,0x21,0xf0 = mul	%d15, %d1, 16
+0xd9,0xff,0x3c,0x50 = lea	%a15, [%a15]380
+0x49,0xff,0x00,0x1a = lea	%a15, [%a15]64
+0x80,0xcf           = mov.d	%d15, %a12
+0xd9,0xff,0x24,0x50 = lea	%a15, [%a15]356
+0x91,0x00,0x03,0xfa = movh.a	%a15, 41008
+0x80,0x41           = mov.d	%d1, %a4
+0x6b,0x0f,0x61,0x41 = madd.f	%d4, %d1, %d15, %d0
+# 0x74,0xd0           = st.w	[%a13],%d0
+# 0x59,0x20,0x0c,0x16 = st.w	[%a2]24652
+0x0f,0xf1,0x00,0x10 = sh	%d1, %d1, %d15
+# 0x89,0x4f,0x0c,0x18 = st.b	[%a4]76,%d15
+0x6d,0x00,0xc3,0x06 = call	0xd86
+# 0x08,0xb0           = ld.bu	%d0,[%a15]11
+0xc2,0x11           = add	%d1, 1
+0x91,0x10,0x00,0xa3 = movh.a	%sp, 12289
+0x6d,0xff,0xee,0xe8 = call	-0x2e24
+0x37,0x0f,0x81,0xf7 = insert	%d15, %d15, %d0, 15, 1
+# 0xd4,0xf2           = ld.a	%a2,[%a15]
+0x91,0x30,0x00,0x2f = movh.a	%a2, 61443
+0xbe,0x40           = jeq	%d15, %d4, 0x20
+0x40,0x4c           = mov.aa	%a12, %a4
+# 0x59,0x2f,0x04,0x26 = st.w	[%a2]24708
+0x7e,0x91           = jne	%d15, %d9, 0x2
+0x3c,0x03           = j	0x6
+0x53,0x00,0x21,0xf0 = mul	%d15, %d0, 16
+0xe2,0x9f           = mul	%d15, %d9
+0x37,0x00,0x68,0x40 = extr.u	%d4, %d0, 0, 8
+0x91,0x40,0x00,0xa6 = movh.a	%sp, 24580
+# 0x89,0x4f,0x00,0x59 = st.w	[%a4]320,%d15
+0x6d,0xff,0xed,0xf7 = call	-0x1026
+0x3c,0x02           = j	0x4
+0xbf,0x30,0xe1,0xff = jlt.u	%d0, 3, -0x3e
+0xdf,0x0f,0xb1,0x80 = jne	%d15, 0, 0x162
+0x91,0x40,0x00,0xa7 = movh.a	%sp, 28676
+0x10,0xef           = addsc.a	%a15, %a14, %d15, 0
+# 0x09,0x44,0x41,0x08 = ld.bu	%d4,[%a4]1
+0x4e,0x33           = jgtz	%d3, 0x6
+# 0x19,0x20,0x00,0x26 = ld.w	%d0,[%a2]24704
+0x4b,0x0f,0x51,0xf0 = div.f	%d15, %d15, %d0
+# 0x19,0xf0,0x28,0xa6 = ld.w	%d0,[%a15]25256
+# 0x09,0xcf,0x4d,0x18 = ld.bu	%d15,[%a12]77
+0xa6,0x64           = or	%d4, %d6
+0xb7,0x0f,0x81,0xf0 = insert	%d15, %d15, 0, 1, 1
+# 0x4d,0x40,0x20,0xf9 = mfcr	%d15,$pcon1
+0x6d,0xff,0x8b,0xfe = call	-0x2ea
+0x53,0x80,0x20,0xf0 = mul	%d15, %d0, 8
+0x06,0x50           = sh	%d0, 5
+# 0x08,0xf1           = ld.bu	%d1,[%a15]15
+# 0x09,0xe1,0x00,0x39 = ld.w	%d1,[%a14]192
+# 0x2c,0xff           = st.b	[%a15]15,%d15
+0x80,0x20           = mov.d	%d0, %a2
+0xd9,0xff,0x28,0xa6 = lea	%a15, [%a15]25256
+0x82,0x10           = mov	%d0, 1
+0x37,0xf0,0x02,0xf2 = insert	%d15, %d0, %d15, 4, 2
+# 0x0c,0xc5           = ld.bu	%d15,[%a12]5
+0x40,0xf4           = mov.aa	%a4, %a15
+0x3c,0x11           = j	0x22
+0x09,0xff,0xc4,0x08 = ld.hu	%d15, [%a15]4
+0x6d,0x00,0xcd,0x07 = call	0xf9a
+# 0x09,0xf0,0x51,0x08 = ld.bu	%d0,[%a15]17
+# 0x08,0x90           = ld.bu	%d0,[%a15]9
+0x91,0x10,0x00,0xf4 = movh.a	%a15, 16385
+# 0x09,0xcf,0x52,0x18 = ld.bu	%d15,[%a12]82
+# 0x89,0xc2,0x84,0x09 = st.a	[%a12]4,%a2
+0x49,0x40,0x40,0x08 = ldmst	[%a4]0, %e0
+0xc2,0xf1           = add	%d1, -1
+# 0x39,0x2f,0x11,0x06 = ld.bu	%d15,[%a2]24593
+# 0x89,0xff,0x21,0x28 = st.b	[%a15]161,%d15
+0x76,0x03           = jz	%d0, 0x6
+0x3b,0x00,0x00,0xf3 = mov	%d15, 12288
+0x6d,0xff,0x9b,0xfc = call	-0x6ca
+0x6d,0xff,0x04,0xfa = call	-0xbf8
+0x90,0xdd           = addsc.a	%a13, %a13, %d15, 2
+0xda,0x40           = mov	%d15, 64
+# 0x89,0x4f,0x0a,0x18 = st.b	[%a4]74,%d15
+0xbf,0xc9,0x05,0x80 = jlt.u	%d9, 12, 0xa
+0xdf,0x1f,0x29,0x80 = jne	%d15, 1, 0x52
+0xff,0xc9,0x04,0x80 = jge.u	%d9, 12, 0x8
+0x91,0x80,0x88,0x4f = movh.a	%a4, 63624
+0xd9,0xff,0x6c,0x10 = lea	%a15, [%a15]1132
+0xda,0x01           = mov	%d15, 1
+0x82,0x27           = mov	%d7, 2
+0xee,0xf6           = jnz	%d15, -0x14
+0x37,0xf0,0x03,0x04 = insert	%d0, %d0, %d15, 8, 3
+# 0x59,0x20,0x34,0x06 = st.w	[%a2]24628
+# 0x0c,0x21           = ld.bu	%d15,[%a2]1
+# 0x59,0x2f,0x28,0xa6 = st.w	[%a2]25256
+# 0x08,0xdf           = ld.bu	%d15,[%a15]13
+# 0x19,0x2f,0xa8,0x56 = ld.w	%d15,[%a2]26984
+0x6d,0x00,0x6d,0x03 = call	0x6da
+0xb7,0x2f,0x02,0xf5 = insert	%d15, %d15, 2, 10, 2
+# 0x39,0x2f,0x2a,0x06 = ld.bu	%d15,[%a2]24618
+0x10,0xd2           = addsc.a	%a2, %a13, %d15, 0
+0x91,0x10,0x00,0x21 = movh.a	%a2, 4097
+# 0x14,0xff           = ld.bu	%d15,[%a15]
+# 0xcd,0xc1,0xe3,0x0f = mtcr	$lcx,%d1
+0x26,0xf2           = and	%d2, %d15
+# 0x39,0x2f,0x14,0x06 = ld.bu	%d15,[%a2]24596
+# 0x39,0x2f,0x10,0x06 = ld.bu	%d15,[%a2]24592
+0x82,0x24           = mov	%d4, 2
+0x16,0x5f           = and	%d15, 95
+0x8b,0x87,0x01,0x10 = add	%d1, %d7, 24
+0xd9,0x44,0xb0,0xd2 = lea	%a4, [%a4]11120
+0xd9,0xff,0x68,0x00 = lea	%a15, [%a15]1064
+0x4b,0x0f,0x41,0x00 = mul.f	%d0, %d15, %d0
+0xdf,0x10,0xf6,0x7f = jeq	%d0, 1, -0x14
+0xb7,0x0f,0x81,0xf1 = insert	%d15, %d15, 0, 3, 1
+0x53,0x88,0x20,0xf0 = mul	%d15, %d8, 8
+0x6d,0xff,0xaa,0xf9 = call	-0xcac
+0xb7,0x4f,0x08,0xf0 = insert	%d15, %d15, 4, 0, 8
+0xfc,0xf6           = loop	%a15, -0x14
+# 0x09,0xc5,0x7c,0x08 = ld.bu	%d5,[%a12]60
+0x37,0x0f,0xe1,0xf0 = extr.u	%d15, %d15, 1, 1
+0x37,0x0f,0x81,0xfb = insert	%d15, %d15, %d0, 23, 1
+0x4e,0x03           = jgtz	%d0, 0x6
+# 0x09,0xa0,0x40,0x09 = ld.d	%e0,[%sp]
+# 0x89,0x4f,0x24,0x48 = st.b	[%a4]292,%d15
+# 0x89,0xf0,0x10,0x29 = st.w	[%a15]144,%d0
+0x02,0x24           = mov	%d4, %d2
+0xc6,0x10           = xor	%d0, %d1
+0xfc,0x4e           = loop	%a4, -0x4
+0x06,0x63           = sh	%d3, 6
+# 0x09,0xf3,0x00,0x19 = ld.w	%d3,[%a15]64
+0x6d,0xff,0x99,0xfb = call	-0x8ce
+0xd9,0xff,0x14,0x23 = lea	%a15, [%a15]12436
+0xbb,0xf0,0xff,0xff = mov.u	%d15, 65535
+0x02,0x94           = mov	%d4, %d9
+0x53,0xcf,0x20,0x10 = mul	%d1, %d15, 12
+0xc6,0xf0           = xor	%d0, %d15
+# 0x09,0x4f,0x00,0x49 = ld.w	%d15,[%a4]256
+0xb7,0x0f,0x02,0xf0 = insert	%d15, %d15, 0, 0, 2
+# 0x14,0x4f           = ld.bu	%d15,[%a4]
+# 0xe9,0xff,0x2c,0xa6 = st.b	[%a15]25260
+# 0x19,0xff,0x34,0xa6 = ld.w	%d15,[%a15]25268
+0xd9,0xff,0xe8,0xc2 = lea	%a15, [%a15]12072
+0x76,0xdb           = jz	%d13, 0x16
+# 0xd4,0x2d           = ld.a	%a13,[%a2]
+0xdf,0x1f,0xfe,0x7f = jeq	%d15, 1, -0x4
+# 0x89,0x4f,0x13,0x18 = st.b	[%a4]83,%d15
+0x6d,0x00,0x8a,0x00 = call	0x114
+0x10,0xe4           = addsc.a	%a4, %a14, %d15, 0
+# 0xcc,0x51           = ld.a	%a15,[%a5]4
+0x3c,0x1e           = j	0x3c
+0x82,0x0a           = mov	%d10, 0
+0x82,0x21           = mov	%d1, 2
+0x8f,0xff,0x83,0xf1 = xor	%d15, %d15, 63
+0xb7,0x1f,0x81,0x1b = insert	%d1, %d15, 1, 23, 1
+0x3c,0x1d           = j	0x3a
+0x6f,0x10,0xf8,0x7f = jz.t	%d0, 1, -0x10
+0x0f,0x10,0x10,0x00 = sha	%d0, %d0, %d1
+0x4b,0x0f,0x41,0x10 = mul.f	%d1, %d15, %d0
+0x3b,0x20,0xfe,0x0f = mov	%d0, -30
+0x6d,0x00,0x04,0x00 = call	0x8
+0x3e,0x16           = jeq	%d15, %d1, 0xc
+# 0x89,0x4f,0x11,0x18 = st.b	[%a4]81,%d15
+0x8f,0x4f,0x1f,0x10 = sh	%d1, %d15, -12
+0x3b,0xf0,0x05,0x20 = mov	%d2, 95
+0xef,0x8f,0x0a,0x00 = jz.t	%d15, 24, 0x14
+# 0x59,0x20,0x30,0x06 = st.w	[%a2]24624
+0xda,0x03           = mov	%d15, 3
+# 0x09,0xf0,0x50,0x08 = ld.bu	%d0,[%a15]16
+0x6d,0xff,0x62,0xfb = call	-0x93c
+0x91,0x40,0x00,0x27 = movh.a	%a2, 28676
+0xa6,0x4f           = or	%d15, %d4
+0xd9,0xff,0x00,0x0e = lea	%a15, [%a15]-8192
+# 0x09,0xf0,0x68,0x08 = ld.bu	%d0,[%a15]40
+# 0xe9,0x2f,0x01,0x80 = st.b	[%a2]513,%d15
+0xd9,0x44,0x0c,0x96 = lea	%a4, [%a4]25164
+0x6f,0x0f,0xfe,0xff = jnz.t	%d15, 0, -0x4
+# 0x85,0xf0,0x10,0x01 = ld.w	%d0,f0001010
+# 0x09,0xc5,0x6c,0x08 = ld.bu	%d5,[%a12]44
+# 0x08,0xef           = ld.bu	%d15,[%a15]14
+0x37,0x0f,0x81,0xff = insert	%d15, %d15, %d0, 31, 1
+0x6d,0xff,0x63,0xfb = call	-0x93a
+0x06,0x24           = sh	%d4, 2
+0xdf,0x1f,0x23,0x80 = jne	%d15, 1, 0x46
+# 0x09,0xc9,0x44,0x08 = ld.bu	%d9,[%a12]4
+0x37,0xf1,0x08,0xf0 = insert	%d15, %d1, %d15, 0, 8
+0x9b,0xe1,0xcb,0x14 = addih	%d1, %d1, 19646
+0x8b,0x87,0x01,0x00 = add	%d0, %d7, 24
+# 0x89,0xe2,0x30,0x69 = st.w	[%a14]432,%d2
+0xdf,0x10,0x2b,0x80 = jne	%d0, 1, 0x56
+0x6d,0x00,0x53,0x00 = call	0xa6
+0x9b,0xe2,0xcb,0x24 = addih	%d2, %d2, 19646
+# 0x89,0xe1,0x24,0x69 = st.w	[%a14]420,%d1
+# 0x09,0xe0,0x40,0x28 = ld.bu	%d0,[%a14]128
+0x6d,0x00,0x9f,0x09 = call	0x133e
+# 0x09,0x50,0x64,0x08 = ld.bu	%d0,[%a5]36
+# 0xe9,0x4f,0x03,0xa0 = st.b	[%a4]643,%d15
+# 0x09,0xf0,0x0c,0x29 = ld.w	%d0,[%a15]140
+0xc5,0x02,0x3f,0x10 = lea	%a2, 0x7f
+0x49,0xcf,0x30,0x0a = lea	%a15, [%a12]48
+# 0x4d,0xc0,0xe1,0x0f = mfcr	%d0,$core_id
+# 0xc8,0x1f           = ld.a	%a15,[%a15]4
+# 0x39,0xff,0x34,0x06 = ld.bu	%d15,[%a15]24628
+# 0x09,0xc6,0x7f,0x08 = ld.bu	%d6,[%a12]63
+# 0x24,0xcf           = st.b	[%a12+],%d15
+0xbe,0x60           = jeq	%d15, %d6, 0x20
+# 0x08,0x6f           = ld.bu	%d15,[%a15]6
+0x37,0x0f,0x65,0xf2 = extr.u	%d15, %d15, 4, 5
+0x53,0x69,0x20,0xf0 = mul	%d15, %d9, 6
+0xd9,0xff,0x78,0x40 = lea	%a15, [%a15]1336
+0x7e,0x93           = jne	%d15, %d9, 0x6
+0x91,0x00,0x00,0x80 = movh.a	%a8, 0
+# 0x19,0x20,0x00,0x16 = ld.w	%d0,[%a2]24640
+0x10,0x2f           = addsc.a	%a15, %a2, %d15, 0
+0xd9,0xff,0x20,0xe0 = lea	%a15, [%a15]928
+# 0x09,0xf0,0x08,0x19 = ld.w	%d0,[%a15]72
+0x6f,0x00,0x1f,0x80 = jnz.t	%d0, 0, 0x3e
+0x8b,0x60,0x09,0xf1 = rsub	%d15, %d0, 150
+0xff,0x8f,0x1a,0x80 = jge.u	%d15, 8, 0x34
+# 0x2c,0x48           = st.b	[%a4]8,%d15
+# 0x89,0xef,0x08,0x28 = st.b	[%a14]136,%d15
+0x3e,0x04           = jeq	%d15, %d0, 0x8
+# 0x09,0xf0,0x28,0x19 = ld.w	%d0,[%a15]104
+0x1d,0xff,0x77,0xff = j	-0x112
+0x02,0x48           = mov	%d8, %d4
+0x20,0x58           = sub.a	%sp, 88
+# 0x19,0x2f,0x28,0xa6 = ld.w	%d15,[%a2]25256
+0x37,0x0f,0x82,0xf6 = insert	%d15, %d15, %d0, 13, 2
+0x60,0xff           = mov.a	%a15, %d15
+0xbb,0x00,0xc2,0x0b = mov.u	%d0, 48160
+0x10,0xaf           = addsc.a	%a15, %sp, %d15, 0
+0x6d,0x00,0xf0,0x04 = call	0x9e0
+0x6e,0x03           = jz	%d15, 0x6
+# 0x59,0x20,0x18,0x06 = st.w	[%a2]24600
+# 0x09,0xcf,0x48,0x18 = ld.bu	%d15,[%a12]72
+0x6d,0xff,0x01,0xfc = call	-0x7fe
+# 0x09,0xcf,0x6d,0x08 = ld.bu	%d15,[%a12]45
+0x3b,0xf0,0x49,0x02 = mov	%d0, 9375
+0x8f,0x31,0x40,0xf1 = or	%d15, %d1, 3
+# 0x39,0x2f,0x37,0x06 = ld.bu	%d15,[%a2]24631
+0x6d,0xff,0x9c,0xf8 = call	-0xec8
+0x8f,0xff,0x83,0xa1 = xor	%d10, %d15, 63
+0x4b,0xf0,0x11,0x22 = div.u	%e2, %d0, %d15
+# 0x19,0xf1,0x20,0x06 = ld.w	%d1,[%a15]24608
+0x86,0x20           = sha	%d0, 2
+0x37,0xf0,0x02,0x0f = insert	%d0, %d0, %d15, 30, 2
+# 0x89,0xaf,0x2c,0x08 = st.b	[%sp]44,%d15
+0x1e,0x13           = jeq	%d15, 1, 0x6
+0xd9,0x44,0xe0,0x22 = lea	%a4, [%a4]11424
+0x06,0x62           = sh	%d2, 6
+0x7b,0x00,0x00,0x11 = movh	%d1, 4096
+# 0x09,0x4f,0x20,0x49 = ld.w	%d15,[%a4]288
+# 0x59,0xf1,0x20,0x06 = st.w	[%a15]24608
+0x8b,0xf2,0x00,0x00 = add	%d0, %d2, 15
+0x8f,0x00,0x01,0x00 = sh	%d0, %d0, 16
+0xa2,0x0f           = sub	%d15, %d0
+0x9b,0x10,0x13,0x00 = addih	%d0, %d0, 305
+0xe2,0xf0           = mul	%d0, %d15
+0x8f,0x3f,0x00,0x10 = sh	%d1, %d15, 3
+0x80,0xdf           = mov.d	%d15, %a13
+0x92,0x10           = add	%d0, %d15, 1
+0x6e,0xe8           = jz	%d15, -0x30
+0x10,0x22           = addsc.a	%a2, %a2, %d15, 0
+0x82,0x26           = mov	%d6, 2
+0x82,0x02           = mov	%d2, 0
+0xbe,0x41           = jeq	%d15, %d4, 0x22
+# 0x89,0x44,0x30,0x49 = st.w	[%a4]304,%d4
+# 0xcd,0x0f,0xe2,0x0f = mtcr	$biv,%d15
+0xd9,0xff,0x3c,0x96 = lea	%a15, [%a15]25212
+# 0x19,0x2f,0x04,0x26 = ld.w	%d15,[%a2]24708
+0x6d,0xff,0xc5,0xff = call	-0x76
+# 0x09,0xcf,0x42,0x18 = ld.bu	%d15,[%a12]66
+# 0x59,0x2f,0xb4,0x06 = st.w	[%a2]26676
+0x3b,0x00,0x02,0x60 = mov	%d6, 32
+# 0x09,0xcf,0x49,0x18 = ld.bu	%d15,[%a12]73
+# 0x19,0x2f,0x10,0x06 = ld.w	%d15,[%a2]24592
+0x26,0xf3           = and	%d3, %d15
+# 0x74,0x2f           = st.w	[%a2],%d15
+0x82,0x09           = mov	%d9, 0
+0x2e,0x03           = jz.t	%d15, 0, 0x6
+0xb7,0x0f,0x01,0xf0 = insert	%d15, %d15, 0, 0, 1
+0x37,0x0f,0x01,0xf6 = insert	%d15, %d15, %d0, 12, 1
+0xc6,0x30           = xor	%d0, %d3
+0x06,0x21           = sh	%d1, 2
+0x6d,0xe8,0xf4,0x11 = call	-0x2fdc18
+# 0x09,0x45,0x84,0x09 = ld.a	%a5,[%a4]4
+0x6d,0xff,0x6e,0xfe = call	-0x324
+0x6d,0xff,0x1e,0xe9 = call	-0x2dc4
+0x7f,0xf9,0x02,0x80 = jge.u	%d9, %d15, 0x4
+# 0xc8,0x52           = ld.a	%a2,[%a15]20
+0x6d,0xff,0x68,0xfb = call	-0x930
+# 0xd4,0xc2           = ld.a	%a2,[%a12]
+# 0x39,0x5f,0x03,0xa0 = ld.bu	%d15,[%a5]643
+0x77,0x00,0x00,0x04 = dextr	%d0, %d0, %d0, 8
+0x91,0x00,0x00,0x48 = movh.a	%a4, 32768
+0xc6,0xf3           = xor	%d3, %d15
+0xc2,0xfc           = add	%d12, -1
+0x3e,0x08           = jeq	%d15, %d0, 0x10
+0x6d,0x00,0x38,0x00 = call	0x70
+# 0x09,0xc4,0x6d,0x08 = ld.bu	%d4,[%a12]45
+# 0x89,0xf0,0x0c,0x29 = st.w	[%a15]140,%d0
+0x37,0x0f,0x82,0xf2 = insert	%d15, %d15, %d0, 5, 2
+0x02,0x4f           = mov	%d15, %d4
+0x91,0x00,0x00,0xf7 = movh.a	%a15, 28672
+0x4b,0xf2,0x51,0x20 = div.f	%d2, %d2, %d15
+0xbe,0x10           = jeq	%d15, %d1, 0x20
+0x37,0xf0,0x01,0xf3 = insert	%d15, %d0, %d15, 6, 1
+0x02,0xc4           = mov	%d4, %d12
+# 0x19,0x2f,0x08,0x26 = ld.w	%d15,[%a2]24712
+0x09,0xc0,0xca,0x28 = ld.hu	%d0, [%a12]138
+0xda,0x08           = mov	%d15, 8
+# 0xe9,0x2f,0x1c,0x06 = st.b	[%a2]24604
+0xbf,0x38,0xce,0xff = jlt.u	%d8, 3, -0x64
+0xd9,0xff,0x08,0x23 = lea	%a15, [%a15]12424
diff --git a/suite/MC/TriCore/J_Call_Loop.s.cs b/suite/MC/TriCore/J_Call_Loop.s.cs
new file mode 100644
index 0000000000..b4d7ce1955
--- /dev/null
+++ b/suite/MC/TriCore/J_Call_Loop.s.cs
@@ -0,0 +1,281 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None
+0x6d,0xff,0x9d,0xff = call	-0xc6
+0x6d,0xff,0x02,0xfe = call	-0x3fc
+0x7f,0xf8,0x0b,0x80 = jge.u	%d8, %d15, 0x16
+0x3c,0x0b           = j	0x16
+0x6d,0xff,0xb3,0xff = call	-0x9a
+0xff,0x88,0x1f,0x80 = jge.u	%d8, 8, 0x3e
+0x6d,0x00,0x1b,0x00 = call	0x36
+0x5e,0x17           = jne	%d15, 1, 0xe
+0x3c,0x08           = j	0x10
+0x6d,0xff,0xbe,0xff = call	-0x84
+0x6d,0xff,0x58,0xff = call	-0x150
+0x6d,0xff,0xbd,0xfd = call	-0x486
+0x7f,0xf8,0x0d,0x80 = jge.u	%d8, %d15, 0x1a
+0x3c,0x0d           = j	0x1a
+0x6d,0xff,0x6a,0xff = call	-0x12c
+0x6d,0xff,0x94,0xfa = call	-0xad8
+0x3c,0x01           = j	0x2
+0x6d,0xff,0x87,0xfa = call	-0xaf2
+0xbf,0x45,0x0b,0x80 = jlt.u	%d5, 4, 0x16
+0x6f,0x04,0x05,0x00 = jz.t	%d4, 0, 0xa
+0x3c,0x03           = j	0x6
+0x6d,0xff,0x9a,0xff = call	-0xcc
+0x6d,0xff,0x4e,0xff = call	-0x164
+0x6d,0xff,0x83,0xff = call	-0xfa
+0x6d,0xff,0x37,0xff = call	-0x192
+0x6d,0xff,0x32,0xfa = call	-0xb9c
+0x6d,0xff,0xc3,0xff = call	-0x7a
+0x6d,0xff,0x1e,0xfa = call	-0xbc4
+0x7f,0x81,0x0a,0x80 = jge.u	%d1, %d8, 0x14
+0x3f,0x08,0x08,0x80 = jlt.u	%d8, %d0, 0x10
+0x7f,0x80,0x04,0x80 = jge.u	%d0, %d8, 0x8
+0x3c,0x05           = j	0xa
+0x6d,0xff,0xa6,0xff = call	-0xb4
+0x6d,0xff,0x26,0xff = call	-0x1b4
+0x6d,0xff,0xda,0xfe = call	-0x24c
+0xdf,0x04,0x31,0x00 = jeq	%d4, 0, 0x62
+0x76,0x6b           = jz	%d6, 0x16
+0x3c,0x0c           = j	0x18
+0x6d,0xff,0xdc,0xfe = call	-0x248
+0x6d,0xff,0x8d,0xfe = call	-0x2e6
+0x3c,0x0e           = j	0x1c
+0x6e,0x03           = jz	%d15, 0x6
+0xbf,0x81,0xf3,0xff = jlt.u	%d1, 8, -0x1a
+0xdf,0x10,0xee,0x7f = jeq	%d0, 1, -0x24
+0x6d,0xff,0xa6,0xfe = call	-0x2b4
+0x6d,0xff,0x19,0xfe = call	-0x3ce
+0xee,0x08           = jnz	%d15, 0x10
+0x3c,0x09           = j	0x12
+0x6d,0xff,0xbc,0xfd = call	-0x488
+0x6e,0x20           = jz	%d15, 0x40
+0x6d,0xff,0x22,0xfe = call	-0x3bc
+0xff,0x8f,0x1a,0x80 = jge.u	%d15, 8, 0x34
+0x3c,0x1b           = j	0x36
+0x6e,0x29           = jz	%d15, 0x52
+0x6d,0xff,0xcb,0xfd = call	-0x46a
+0x6d,0xff,0x1e,0xfd = call	-0x5c4
+0xfc,0x6e           = loop	%a6, -0x4
+0x6d,0xff,0x5c,0xfd = call	-0x548
+0x6d,0xff,0x2e,0xfd = call	-0x5a4
+0x5e,0x1b           = jne	%d15, 1, 0x16
+0x6d,0xff,0x06,0xfe = call	-0x3f4
+0x6d,0xff,0xfe,0xfd = call	-0x404
+0x6d,0xff,0xf2,0xfd = call	-0x41c
+0x6d,0xff,0xea,0xfd = call	-0x42c
+0x6d,0xff,0xde,0xfd = call	-0x444
+0x6d,0xff,0xd6,0xfd = call	-0x454
+0x5f,0x9f,0x23,0x00 = jeq	%d15, %d9, 0x46
+0xdf,0x1f,0x5d,0x80 = jne	%d15, 1, 0xba
+0x6e,0x2d           = jz	%d15, 0x5a
+0xfe,0x04           = jne	%d15, %d0, 0x28
+0x3c,0x07           = j	0xe
+0xbe,0x05           = jeq	%d15, %d0, 0x2a
+0x3c,0x02           = j	0x4
+0xdf,0x1f,0x57,0x80 = jne	%d15, 1, 0xae
+0x7e,0x93           = jne	%d15, %d9, 0x6
+0x6d,0xff,0x7a,0xfb = call	-0x90c
+0x3c,0x36           = j	0x6c
+0x7f,0x0f,0x07,0x80 = jge.u	%d15, %d0, 0xe
+0xbf,0x21,0xcb,0xff = jlt.u	%d1, 2, -0x6a
+0x6d,0xff,0x18,0xfb = call	-0x9d0
+0x6d,0xff,0x85,0xfa = call	-0xaf6
+0x6d,0xff,0xd6,0xf8 = call	-0xe54
+0x6d,0xff,0x9c,0xfa = call	-0xac8
+0x6d,0xff,0x00,0xfc = call	-0x800
+0x6d,0xff,0xc6,0xfb = call	-0x874
+0xf6,0x23           = jnz	%d2, 0x6
+0x3c,0x63           = j	0xc6
+0x6d,0xff,0xa9,0xfb = call	-0x8ae
+0x6d,0xff,0x45,0xfb = call	-0x976
+0x3c,0x34           = j	0x68
+0xbf,0x21,0xcd,0xff = jlt.u	%d1, 2, -0x66
+0xde,0x1e           = jne	%d15, 1, 0x3c
+0x3c,0x17           = j	0x2e
+0x6d,0xff,0xde,0xfa = call	-0xa44
+0x6d,0xff,0x89,0xfa = call	-0xaee
+0xbf,0x89,0xea,0xff = jlt.u	%d9, 8, -0x2c
+0x6d,0xff,0xe8,0xfb = call	-0x830
+0x6d,0xff,0xee,0xfa = call	-0xa24
+0x6d,0xff,0x73,0xf5 = call	-0x151a
+0xee,0x06           = jnz	%d15, 0xc
+0x3c,0x11           = j	0x22
+0x5e,0x19           = jne	%d15, 1, 0x12
+0x6d,0xff,0xde,0xff = call	-0x44
+0x5e,0x1a           = jne	%d15, 1, 0x14
+0x3c,0x29           = j	0x52
+0x5e,0x1e           = jne	%d15, 1, 0x1c
+0x3e,0x04           = jeq	%d15, %d0, 0x8
+0x3e,0x08           = jeq	%d15, %d0, 0x10
+0x3c,0x0a           = j	0x14
+0x3c,0x06           = j	0xc
+0x6d,0xff,0xb2,0xff = call	-0x9c
+0x6d,0xff,0xe8,0xff = call	-0x30
+0x3e,0x0c           = jeq	%d15, %d0, 0x18
+0xbe,0x0c           = jeq	%d15, %d0, 0x38
+0xbe,0x0f           = jeq	%d15, %d0, 0x3e
+0x5f,0x0f,0x22,0x00 = jeq	%d15, %d0, 0x44
+0x5f,0x0f,0x24,0x00 = jeq	%d15, %d0, 0x48
+0x3c,0x27           = j	0x4e
+0xee,0x03           = jnz	%d15, 0x6
+0x3c,0x12           = j	0x24
+0x6d,0x00,0x43,0x04 = call	0x886
+0x6d,0x00,0x54,0x04 = call	0x8a8
+0x6d,0x00,0x91,0x02 = call	0x522
+0x6d,0x00,0x4a,0x04 = call	0x894
+0x6d,0x00,0xa4,0x02 = call	0x548
+0xee,0xfa           = jnz	%d15, -0xc
+0x6d,0x00,0xc4,0x01 = call	0x388
+0x6d,0x00,0x29,0x04 = call	0x852
+0xdf,0x08,0x92,0x81 = jne	%d8, 0, 0x324
+0x6d,0x00,0x5a,0x02 = call	0x4b4
+0x6e,0xfa           = jz	%d15, -0xc
+0x6d,0x00,0xbb,0x01 = call	0x376
+0x6d,0x00,0x8c,0x01 = call	0x318
+0x6d,0x00,0xf1,0x02 = call	0x5e2
+0x6d,0x00,0xe8,0x00 = call	0x1d0
+0x6d,0x00,0xab,0x02 = call	0x556
+0x3c,0x37           = j	0x6e
+0x6d,0x00,0x03,0x01 = call	0x206
+0x6d,0x00,0xb3,0x02 = call	0x566
+0x6e,0x09           = jz	%d15, 0x12
+0x2d,0x02,0x00,0x00 = calli	%a2
+0x6d,0x00,0x91,0x00 = call	0x122
+0x3f,0xfc,0xc9,0xff = jlt.u	%d12, %d15, -0x6e
+0x6d,0x00,0xca,0x00 = call	0x194
+0x6d,0x00,0x87,0x02 = call	0x50e
+0x6d,0x00,0x92,0x00 = call	0x124
+0x6d,0x00,0x47,0x02 = call	0x48e
+0x6d,0x00,0x1f,0x02 = call	0x43e
+0xf6,0x83           = jnz	%d8, 0x6
+0x6f,0x1f,0xf8,0x7f = jz.t	%d15, 1, -0x10
+0x6f,0x0f,0xf2,0x7f = jz.t	%d15, 0, -0x1c
+0x6d,0x00,0x34,0x00 = call	0x68
+0x6d,0x00,0xea,0x01 = call	0x3d4
+0x6d,0xff,0x21,0xfd = call	-0x5be
+0x3f,0xf0,0xfd,0xff = jlt.u	%d0, %d15, -0x6
+0x2e,0x1b           = jz.t	%d15, 1, 0x16
+0xdf,0x1f,0xfe,0x7f = jeq	%d15, 1, -0x4
+0x6f,0x1f,0x12,0x00 = jz.t	%d15, 1, 0x24
+0xdf,0x1f,0xfb,0x7f = jeq	%d15, 1, -0xa
+0x6f,0x0f,0xff,0x7f = jz.t	%d15, 0, -0x2
+0x6f,0x0f,0xfc,0x7f = jz.t	%d15, 0, -0x8
+0xdc,0x0f           = ji	%a15
+0x6d,0x00,0x2f,0x00 = call	0x5e
+0x3e,0x28           = jeq	%d15, %d2, 0x10
+0x5e,0x13           = jne	%d15, 1, 0x6
+0xee,0x13           = jnz	%d15, 0x26
+0x5e,0x32           = jne	%d15, 3, 0x4
+0x7d,0x4f,0x0d,0x80 = jne.a	%a15, %a4, 0x1a
+0x3c,0x04           = j	0x8
+0xbf,0x30,0xea,0xff = jlt.u	%d0, 3, -0x2c
+0x6d,0xff,0xe0,0xff = call	-0x40
+0x1e,0x32           = jeq	%d15, 3, 0x4
+0x5e,0x43           = jne	%d15, 4, 0x6
+0x5e,0x23           = jne	%d15, 2, 0x6
+0xdf,0x19,0x49,0x80 = jne	%d9, 1, 0x92
+0x5f,0x8f,0x28,0x00 = jeq	%d15, %d8, 0x50
+0x6d,0x00,0xa5,0x0b = call	0x174a
+0x6d,0x00,0x0a,0x0a = call	0x1414
+0x6d,0xff,0xc0,0xff = call	-0x80
+0x6d,0x00,0xc3,0x0b = call	0x1786
+0x3c,0x1c           = j	0x38
+0x6d,0x00,0x6b,0x0b = call	0x16d6
+0x6d,0x00,0xbc,0x09 = call	0x1378
+0x6d,0x00,0x72,0x0b = call	0x16e4
+0xff,0x3f,0x0b,0x80 = jge.u	%d15, 3, 0x16
+0x7d,0xf4,0x04,0x80 = jne.a	%a4, %a15, 0x8
+0x3c,0x10           = j	0x20
+0x6d,0xff,0xd6,0xff = call	-0x54
+0x6d,0xff,0x28,0xff = call	-0x1b0
+0xf6,0x26           = jnz	%d2, 0xc
+0x6d,0xff,0x71,0xff = call	-0x11e
+0x7e,0x0d           = jne	%d15, %d0, 0x1a
+0x6d,0x00,0x5b,0x06 = call	0xcb6
+0x3f,0x0f,0x04,0x80 = jlt.u	%d15, %d0, 0x8
+0xdf,0x7f,0xf6,0xff = jne	%d15, 7, -0x14
+0x76,0x17           = jz	%d1, 0xe
+0x76,0x13           = jz	%d1, 0x6
+0x3c,0x1e           = j	0x3c
+0xf6,0x06           = jnz	%d0, 0xc
+0x7e,0x05           = jne	%d15, %d0, 0xa
+0x3f,0x40,0xe3,0xff = jlt.u	%d0, %d4, -0x3a
+0x6d,0x00,0x65,0x09 = call	0x12ca
+0x6d,0x00,0xf9,0x07 = call	0xff2
+0x6d,0x00,0x3a,0x08 = call	0x1074
+0x6d,0xff,0xf2,0xfc = call	-0x61c
+0x6d,0x00,0x9a,0x08 = call	0x1134
+0x6d,0x00,0xdc,0x08 = call	0x11b8
+0x6d,0x00,0xf0,0x04 = call	0x9e0
+0x6d,0xff,0x0d,0xfe = call	-0x3e6
+0x6d,0xff,0x04,0xfe = call	-0x3f8
+0x76,0x27           = jz	%d2, 0xe
+0x76,0x23           = jz	%d2, 0x6
+0x6d,0x00,0x71,0x12 = call	0x24e2
+0xfc,0x5e           = loop	%a5, -0x4
+0xfc,0x29           = loop	%a2, -0xe
+0x6f,0x0f,0xfe,0xff = jnz.t	%d15, 0, -0x4
+0x6f,0x1f,0xfa,0xff = jnz.t	%d15, 1, -0xc
+0x1d,0x00,0x03,0x00 = j	0x6
+0x6d,0x00,0x02,0x01 = call	0x204
+0x6d,0x00,0xe1,0x00 = call	0x1c2
+0x6d,0x00,0x0d,0x00 = call	0x1a
+0x6d,0x00,0x72,0x12 = call	0x24e4
+0x6d,0x00,0xea,0x11 = call	0x23d4
+0x6d,0x00,0xfa,0x11 = call	0x23f4
+0x6d,0x00,0xf3,0x0f = call	0x1fe6
+0x3c,0x50           = j	0xa0
+0x6d,0x00,0xc6,0x10 = call	0x218c
+0x6d,0x00,0x41,0x0f = call	0x1e82
+0xbf,0x48,0xb1,0xff = jlt.u	%d8, 4, -0x9e
+0x6f,0x70,0xec,0x7f = jz.t	%d0, 7, -0x28
+0x6d,0x00,0x50,0x0c = call	0x18a0
+0x6d,0x00,0xf9,0x0a = call	0x15f2
+0x6d,0x00,0x5f,0x0c = call	0x18be
+0x6d,0x00,0x38,0x0b = call	0x1670
+0x6d,0x00,0x44,0x00 = call	0x88
+0x6d,0x00,0x27,0x01 = call	0x24e
+0x6d,0xff,0xb7,0xfe = call	-0x292
+0x3c,0x14           = j	0x28
+0x6d,0xff,0xbd,0xff = call	-0x86
+0x6d,0xff,0xb9,0xff = call	-0x8e
+0x6d,0xff,0xb4,0xff = call	-0x98
+0x6d,0xff,0xaf,0xff = call	-0xa2
+0x3c,0xed           = j	-0x26
+0xfc,0xf6           = loop	%a15, -0x14
+0xfd,0xf0,0xed,0x7f = loop	%a15, -0x26
+0xdf,0x1f,0x23,0x80 = jne	%d15, 1, 0x46
+0x6e,0x04           = jz	%d15, 0x8
+0x76,0xcf           = jz	%d12, 0x1e
+0xfc,0x4e           = loop	%a4, -0x4
+0xdf,0x0c,0xe0,0x7f = jeq	%d12, 0, -0x40
+0xfc,0x2e           = loop	%a2, -0x4
+0x3c,0xd9           = j	-0x4e
+0xde,0x25           = jne	%d15, 2, 0x2a
+0x2e,0x03           = jz.t	%d15, 0, 0x6
+0xdf,0x0c,0xd3,0x7f = jeq	%d12, 0, -0x5a
+0x76,0xc5           = jz	%d12, 0xa
+0xfc,0x2f           = loop	%a2, -0x2
+0x6e,0xc9           = jz	%d15, -0x6e
+0x3c,0xc4           = j	-0x78
+0xdf,0x00,0x2e,0x00 = jeq	%d0, 0, 0x5c
+0xdf,0x10,0x2b,0x80 = jne	%d0, 1, 0x56
+0xfe,0xdb           = jne	%d15, %d13, 0x36
+0x76,0xdb           = jz	%d13, 0x16
+0x6d,0x00,0x53,0x00 = call	0xa6
+0xdf,0x0c,0x9b,0x7f = jeq	%d12, 0, -0xca
+0x6d,0x00,0x38,0x00 = call	0x70
+0x3c,0x94           = j	-0xd8
+0xdf,0x2f,0x91,0xff = jne	%d15, 2, -0xde
+0x6e,0x07           = jz	%d15, 0xe
+0x6d,0x00,0x15,0x00 = call	0x2a
+0xdf,0x0c,0x86,0x7f = jeq	%d12, 0, -0xf4
+0xdf,0x04,0x7c,0x7f = jeq	%d4, 0, -0x108
+0x6d,0x00,0x04,0x00 = call	0x8
+0x1d,0xff,0x77,0xff = j	-0x112
+0x1d,0x00,0x02,0x00 = j	0x4
+0x6d,0x00,0x15,0x0c = call	0x182a
+0x6d,0x00,0xbe,0x0a = call	0x157c
+0x6d,0x00,0x0e,0x00 = call	0x1c
+0x6d,0x00,0xf1,0x00 = call	0x1e2
+0x3c,0x00           = j	0x0
diff --git a/suite/MC/TriCore/LoadStore.s.cs b/suite/MC/TriCore/LoadStore.s.cs
new file mode 100644
index 0000000000..9fa09414ad
--- /dev/null
+++ b/suite/MC/TriCore/LoadStore.s.cs
@@ -0,0 +1,318 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None
+0x09,0xff,0x08,0x29 = ld.w	%d15, [%a15]136
+0x89,0xff,0x08,0x29 = st.w	[%a15]136, %d15
+0x09,0xf0,0x0c,0x29 = ld.w	%d0, [%a15]140
+0x89,0xf0,0x0c,0x29 = st.w	[%a15]140, %d0
+0x09,0xff,0x00,0x29 = ld.w	%d15, [%a15]128
+0x89,0xff,0x00,0x29 = st.w	[%a15]128, %d15
+0x09,0xff,0x40,0x28 = ld.bu	%d15, [%a15]128
+0x09,0xff,0x41,0x28 = ld.bu	%d15, [%a15]129
+0x54,0xff           = ld.w	%d15, [%a15]
+0x4c,0x41           = ld.w	%d15, [%a4]4
+0x6c,0x41           = st.w	[%a4]4, %d15
+0x09,0xff,0x43,0x28 = ld.bu	%d15, [%a15]131
+0x89,0xff,0x03,0x28 = st.b	[%a15]131, %d15
+0x39,0x2f,0x43,0x20 = ld.bu	%d15, [%a2]1155
+0xc8,0x52           = ld.a	%a2, [%a15]20
+0xd4,0x2d           = ld.a	%a13, [%a2]
+0x09,0x2e,0x84,0x09 = ld.a	%a14, [%a2]4
+0x89,0xc2,0x84,0x09 = st.a	[%a12]4, %a2
+0x09,0xc2,0x84,0x09 = ld.a	%a2, [%a12]4
+0x09,0x29,0x48,0x08 = ld.bu	%d9, [%a2]8
+0x09,0xfa,0x0c,0x08 = ld.b	%d10, [%a15]12
+0x08,0xe0           = ld.bu	%d0, [%a15]14
+0x09,0x41,0x41,0x68 = ld.bu	%d1, [%a4]385
+0x89,0x20,0x01,0x68 = st.b	[%a2]385, %d0
+0x08,0xf0           = ld.bu	%d0, [%a15]15
+0x09,0x4f,0x42,0x68 = ld.bu	%d15, [%a4]386
+0x89,0x2f,0x02,0x68 = st.b	[%a2]386, %d15
+0x09,0xf0,0x50,0x08 = ld.bu	%d0, [%a15]16
+0x09,0x4f,0x40,0x68 = ld.bu	%d15, [%a4]384
+0x89,0x2f,0x00,0x68 = st.b	[%a2]384, %d15
+0x09,0xf0,0x51,0x08 = ld.bu	%d0, [%a15]17
+0x08,0x10           = ld.bu	%d0, [%a15]1
+0x09,0x4f,0x41,0x68 = ld.bu	%d15, [%a4]385
+0x89,0x2f,0x01,0x68 = st.b	[%a2]385, %d15
+0x08,0xd0           = ld.bu	%d0, [%a15]13
+0x09,0xf0,0x53,0x08 = ld.bu	%d0, [%a15]19
+0x08,0x30           = ld.bu	%d0, [%a15]3
+0x14,0xf0           = ld.bu	%d0, [%a15]
+0x09,0xf0,0x52,0x08 = ld.bu	%d0, [%a15]18
+0x08,0x2f           = ld.bu	%d15, [%a15]2
+0x4c,0xe2           = ld.w	%d15, [%a14]8
+0x6c,0xe2           = st.w	[%a14]8, %d15
+0x08,0xb0           = ld.bu	%d0, [%a15]11
+0x09,0xc2,0x00,0x08 = ld.b	%d2, [%a12]0
+0x09,0xe1,0x20,0x49 = ld.w	%d1, [%a14]288
+0x89,0xe1,0x20,0x49 = st.w	[%a14]288, %d1
+0x09,0xef,0x20,0x49 = ld.w	%d15, [%a14]288
+0x89,0xef,0x20,0x49 = st.w	[%a14]288, %d15
+0x09,0xff,0xc6,0x08 = ld.hu	%d15, [%a15]6
+0x08,0xb5           = ld.bu	%d5, [%a15]11
+0x09,0xf0,0x0c,0x08 = ld.b	%d0, [%a15]12
+0x89,0xef,0x10,0x49 = st.w	[%a14]272, %d15
+0x08,0x90           = ld.bu	%d0, [%a15]9
+0x14,0x21           = ld.bu	%d1, [%a2]
+0x34,0x2f           = st.b	[%a2], %d15
+0x0c,0x21           = ld.bu	%d15, [%a2]1
+0x2c,0x21           = st.b	[%a2]1, %d15
+0x0c,0x23           = ld.bu	%d15, [%a2]3
+0x2c,0x23           = st.b	[%a2]3, %d15
+0x08,0xff           = ld.bu	%d15, [%a15]15
+0x08,0xa0           = ld.bu	%d0, [%a15]10
+0x08,0xf1           = ld.bu	%d1, [%a15]15
+0x09,0xe2,0x30,0x49 = ld.w	%d2, [%a14]304
+0x89,0xe2,0x30,0x49 = st.w	[%a14]304, %d2
+0x09,0xef,0x30,0x49 = ld.w	%d15, [%a14]304
+0x89,0xef,0x30,0x49 = st.w	[%a14]304, %d15
+0x09,0xe2,0x34,0x49 = ld.w	%d2, [%a14]308
+0x89,0xe2,0x34,0x49 = st.w	[%a14]308, %d2
+0x09,0xef,0x34,0x49 = ld.w	%d15, [%a14]308
+0x89,0xef,0x34,0x49 = st.w	[%a14]308, %d15
+0x09,0xff,0xc4,0x08 = ld.hu	%d15, [%a15]4
+0x08,0xa5           = ld.bu	%d5, [%a15]10
+0x39,0x5f,0x03,0x80 = ld.bu	%d15, [%a5]515
+0xe9,0x4f,0x03,0x80 = st.b	[%a4]515, %d15
+0x89,0xef,0x14,0x49 = st.w	[%a14]276, %d15
+0x08,0x80           = ld.bu	%d0, [%a15]8
+0x2c,0xc1           = st.b	[%a12]1, %d15
+0x09,0xff,0x0c,0x08 = ld.b	%d15, [%a15]12
+0x34,0xcf           = st.b	[%a12], %d15
+0x44,0xff           = ld.w	%d15, [%a15+]
+0x64,0x2f           = st.w	[%a2+], %d15
+0x89,0x45,0x94,0x09 = st.a	[%a4]20, %a5
+0xd4,0xf2           = ld.a	%a2, [%a15]
+0xd4,0x2c           = ld.a	%a12, [%a2]
+0x08,0x4f           = ld.bu	%d15, [%a15]4
+0x89,0x4d,0x84,0x09 = st.a	[%a4]4, %a13
+0xd4,0x22           = ld.a	%a2, [%a2]
+0xf4,0x42           = st.a	[%a4], %a2
+0x08,0x49           = ld.bu	%d9, [%a15]4
+0x89,0x49,0x08,0x08 = st.b	[%a4]8, %d9
+0x09,0xff,0x6f,0x08 = ld.bu	%d15, [%a15]47
+0x09,0xf5,0x62,0x08 = ld.bu	%d5, [%a15]34
+0x09,0xf6,0x63,0x08 = ld.bu	%d6, [%a15]35
+0x09,0xff,0x70,0x08 = ld.bu	%d15, [%a15]48
+0x09,0xf5,0x5a,0x08 = ld.bu	%d5, [%a15]26
+0x09,0xf6,0x5b,0x08 = ld.bu	%d6, [%a15]27
+0x09,0xff,0x71,0x08 = ld.bu	%d15, [%a15]49
+0x09,0xf5,0x6a,0x08 = ld.bu	%d5, [%a15]42
+0x09,0xf6,0x6b,0x08 = ld.bu	%d6, [%a15]43
+0x08,0x5f           = ld.bu	%d15, [%a15]5
+0x14,0x20           = ld.bu	%d0, [%a2]
+0x09,0xdf,0x40,0x18 = ld.bu	%d15, [%a13]64
+0x89,0xdf,0x00,0x18 = st.b	[%a13]64, %d15
+0x09,0xd1,0x00,0x19 = ld.w	%d1, [%a13]64
+0x89,0xd1,0x00,0x19 = st.w	[%a13]64, %d1
+0x14,0xd0           = ld.bu	%d0, [%a13]
+0x34,0xdf           = st.b	[%a13], %d15
+0x09,0xff,0x6e,0x08 = ld.bu	%d15, [%a15]46
+0x09,0xff,0x61,0x08 = ld.bu	%d15, [%a15]33
+0x09,0xdf,0x44,0x28 = ld.bu	%d15, [%a13]132
+0x89,0xdf,0x04,0x28 = st.b	[%a13]132, %d15
+0x09,0xf0,0x5f,0x08 = ld.bu	%d0, [%a15]31
+0x09,0xd1,0x00,0x29 = ld.w	%d1, [%a13]128
+0x89,0xd1,0x00,0x29 = st.w	[%a13]128, %d1
+0x09,0xff,0x5e,0x08 = ld.bu	%d15, [%a15]30
+0x09,0xf0,0x60,0x08 = ld.bu	%d0, [%a15]32
+0x14,0x2f           = ld.bu	%d15, [%a2]
+0x09,0xd0,0x45,0x28 = ld.bu	%d0, [%a13]133
+0x89,0xdf,0x05,0x28 = st.b	[%a13]133, %d15
+0x09,0xff,0x59,0x08 = ld.bu	%d15, [%a15]25
+0x09,0xdf,0x64,0x28 = ld.bu	%d15, [%a13]164
+0x89,0xdf,0x24,0x28 = st.b	[%a13]164, %d15
+0x09,0xf0,0x57,0x08 = ld.bu	%d0, [%a15]23
+0x09,0xd1,0x20,0x29 = ld.w	%d1, [%a13]160
+0x89,0xd1,0x20,0x29 = st.w	[%a13]160, %d1
+0x09,0xff,0x56,0x08 = ld.bu	%d15, [%a15]22
+0x09,0xf0,0x58,0x08 = ld.bu	%d0, [%a15]24
+0x09,0xd0,0x64,0x28 = ld.bu	%d0, [%a13]164
+0x09,0xff,0x69,0x08 = ld.bu	%d15, [%a15]41
+0x39,0xcf,0x04,0x80 = ld.bu	%d15, [%a12]516
+0xe9,0xcf,0x04,0x80 = st.b	[%a12]516, %d15
+0x09,0xf0,0x67,0x08 = ld.bu	%d0, [%a15]39
+0x19,0xc1,0x00,0x80 = ld.w	%d1, [%a12]512
+0x59,0xc1,0x00,0x80 = st.w	[%a12]512, %d1
+0x09,0xff,0x66,0x08 = ld.bu	%d15, [%a15]38
+0x09,0xf0,0x68,0x08 = ld.bu	%d0, [%a15]40
+0x39,0xc0,0x04,0x80 = ld.bu	%d0, [%a12]516
+0x09,0xf5,0x6c,0x08 = ld.bu	%d5, [%a15]44
+0x09,0x20,0x4a,0x08 = ld.bu	%d0, [%a2]10
+0x09,0x4f,0x61,0x08 = ld.bu	%d15, [%a4]33
+0x89,0x2f,0x21,0x08 = st.b	[%a2]33, %d15
+0x09,0x2f,0x06,0x09 = ld.w	%d15, [%a2]6
+0x09,0x4f,0x60,0x08 = ld.bu	%d15, [%a4]32
+0x89,0x2f,0x20,0x08 = st.b	[%a2]32, %d15
+0x2c,0x44           = st.b	[%a4]4, %d15
+0xf4,0x45           = st.a	[%a4], %a5
+0x0c,0x44           = ld.bu	%d15, [%a4]4
+0x2c,0x45           = st.b	[%a4]5, %d15
+0x89,0x4f,0x2c,0x08 = st.b	[%a4]44, %d15
+0xd4,0xcd           = ld.a	%a13, [%a12]
+0xf4,0x4d           = st.a	[%a4], %a13
+0x74,0xd0           = st.w	[%a13], %d0
+0x09,0xc4,0x5d,0x08 = ld.bu	%d4, [%a12]29
+0x4c,0xc5           = ld.w	%d15, [%a12]20
+0x4c,0xc4           = ld.w	%d15, [%a12]16
+0x09,0xff,0x61,0x28 = ld.bu	%d15, [%a15]161
+0x89,0x2f,0x21,0x28 = st.b	[%a2]161, %d15
+0x48,0x1f           = ld.w	%d15, [%a15]4
+0x09,0x2f,0x60,0x28 = ld.bu	%d15, [%a2]160
+0x89,0xff,0x20,0x28 = st.b	[%a15]160, %d15
+0x09,0xcf,0x5c,0x08 = ld.bu	%d15, [%a12]28
+0x34,0xff           = st.b	[%a15], %d15
+0xf4,0xf5           = st.a	[%a15], %a5
+0x6c,0xf5           = st.w	[%a15]20, %d15
+0x68,0x42           = st.w	[%a15]16, %d2
+0x68,0x62           = st.w	[%a15]24, %d2
+0x2c,0xf8           = st.b	[%a15]8, %d15
+0x6c,0xf1           = st.w	[%a15]4, %d15
+0x2c,0xfe           = st.b	[%a15]14, %d15
+0x89,0xff,0x0a,0x09 = st.w	[%a15]10, %d15
+0x89,0xff,0x1c,0x08 = st.b	[%a15]28, %d15
+0x89,0xff,0x1d,0x08 = st.b	[%a15]29, %d15
+0x39,0xff,0x37,0x06 = ld.bu	%d15, [%a15]24631
+0x09,0xff,0x54,0x08 = ld.bu	%d15, [%a15]20
+0x09,0xff,0x5c,0x08 = ld.bu	%d15, [%a15]28
+0x09,0xff,0x5b,0x08 = ld.bu	%d15, [%a15]27
+0x39,0xff,0x33,0x06 = ld.bu	%d15, [%a15]24627
+0x39,0xff,0x31,0x06 = ld.bu	%d15, [%a15]24625
+0x39,0xff,0x32,0x06 = ld.bu	%d15, [%a15]24626
+0x09,0xff,0x10,0x19 = ld.w	%d15, [%a15]80
+0x74,0x2f           = st.w	[%a2], %d15
+0x39,0x2f,0x30,0x46 = ld.bu	%d15, [%a2]24880
+0xe9,0x2f,0x30,0x46 = st.b	[%a2]24880, %d15
+0x39,0x2f,0x33,0x06 = ld.bu	%d15, [%a2]24627
+0xe9,0x2f,0x33,0x06 = st.b	[%a2]24627, %d15
+0x39,0x2f,0x18,0x06 = ld.bu	%d15, [%a2]24600
+0xe9,0x2f,0x18,0x06 = st.b	[%a2]24600, %d15
+0x39,0x2f,0x37,0x06 = ld.bu	%d15, [%a2]24631
+0xe9,0x2f,0x37,0x06 = st.b	[%a2]24631, %d15
+0x39,0x2f,0x14,0x06 = ld.bu	%d15, [%a2]24596
+0x39,0x20,0x1c,0x06 = ld.bu	%d0, [%a2]24604
+0x08,0xaf           = ld.bu	%d15, [%a15]10
+0xe9,0x2f,0x1c,0x06 = st.b	[%a2]24604, %d15
+0x39,0x20,0x1b,0x06 = ld.bu	%d0, [%a2]24603
+0x08,0x8f           = ld.bu	%d15, [%a15]8
+0xe9,0x2f,0x1b,0x06 = st.b	[%a2]24603, %d15
+0x39,0x20,0x19,0x06 = ld.bu	%d0, [%a2]24601
+0x08,0x9f           = ld.bu	%d15, [%a15]9
+0xe9,0x2f,0x19,0x06 = st.b	[%a2]24601, %d15
+0x39,0x2f,0x1a,0x06 = ld.bu	%d15, [%a2]24602
+0xe9,0x2f,0x1a,0x06 = st.b	[%a2]24602, %d15
+0x48,0x34           = ld.w	%d4, [%a15]12
+0x19,0x20,0x30,0x06 = ld.w	%d0, [%a2]24624
+0x48,0x5f           = ld.w	%d15, [%a15]20
+0x48,0x41           = ld.w	%d1, [%a15]16
+0x74,0x20           = st.w	[%a2], %d0
+0x19,0x20,0x34,0x06 = ld.w	%d0, [%a2]24628
+0x48,0x7f           = ld.w	%d15, [%a15]28
+0x48,0x61           = ld.w	%d1, [%a15]24
+0x39,0x2f,0x03,0x16 = ld.bu	%d15, [%a2]24643
+0x19,0x20,0x00,0x16 = ld.w	%d0, [%a2]24640
+0x48,0x9f           = ld.w	%d15, [%a15]36
+0x48,0x81           = ld.w	%d1, [%a15]32
+0x39,0x2f,0x0f,0x16 = ld.bu	%d15, [%a2]24655
+0x19,0x20,0x0c,0x16 = ld.w	%d0, [%a2]24652
+0x48,0xbf           = ld.w	%d15, [%a15]44
+0x48,0xa1           = ld.w	%d1, [%a15]40
+0x19,0x20,0x00,0x26 = ld.w	%d0, [%a2]24704
+0x48,0xdf           = ld.w	%d15, [%a15]52
+0x48,0xc1           = ld.w	%d1, [%a15]48
+0x19,0x20,0x04,0x26 = ld.w	%d0, [%a2]24708
+0x48,0xff           = ld.w	%d15, [%a15]60
+0x48,0xe1           = ld.w	%d1, [%a15]56
+0x19,0x2f,0x08,0x26 = ld.w	%d15, [%a2]24712
+0x09,0xf0,0x04,0x19 = ld.w	%d0, [%a15]68
+0x09,0xf1,0x00,0x19 = ld.w	%d1, [%a15]64
+0x19,0x2f,0x14,0x02 = ld.w	%d15, [%a2]8212
+0x09,0xf0,0x0c,0x19 = ld.w	%d0, [%a15]76
+0x09,0xf1,0x08,0x19 = ld.w	%d1, [%a15]72
+0xc8,0x12           = ld.a	%a2, [%a15]4
+0x4c,0x22           = ld.w	%d15, [%a2]8
+0x09,0x22,0x88,0x09 = ld.a	%a2, [%a2]8
+0x09,0x24,0x02,0x09 = ld.w	%d4, [%a2]2
+0x14,0xff           = ld.bu	%d15, [%a15]
+0x39,0xff,0x18,0x06 = ld.bu	%d15, [%a15]24600
+0xe9,0xff,0x18,0x06 = st.b	[%a15]24600, %d15
+0x39,0xff,0x2c,0x46 = ld.bu	%d15, [%a15]24876
+0xe9,0xff,0x2c,0x46 = st.b	[%a15]24876, %d15
+0x39,0xff,0x30,0x46 = ld.bu	%d15, [%a15]24880
+0xe9,0xff,0x30,0x46 = st.b	[%a15]24880, %d15
+0x39,0xf0,0x10,0x06 = ld.bu	%d0, [%a15]24592
+0xe9,0xf0,0x10,0x06 = st.b	[%a15]24592, %d0
+0x39,0xf0,0x12,0x06 = ld.bu	%d0, [%a15]24594
+0x54,0xf1           = ld.w	%d1, [%a15]
+0xe9,0xff,0x12,0x06 = st.b	[%a15]24594, %d15
+0x39,0xff,0x10,0x06 = ld.bu	%d15, [%a15]24592
+0xe9,0xff,0x10,0x06 = st.b	[%a15]24592, %d15
+0x39,0xff,0x11,0x06 = ld.bu	%d15, [%a15]24593
+0x39,0xff,0x35,0x06 = ld.bu	%d15, [%a15]24629
+0x85,0xf1,0x10,0x00 = ld.w	%d1, 0xf0000010
+0x85,0xf0,0x10,0x00 = ld.w	%d0, 0xf0000010
+0x54,0xf0           = ld.w	%d0, [%a15]
+0x74,0xff           = st.w	[%a15], %d15
+0x19,0xff,0x30,0x36 = ld.w	%d15, [%a15]24816
+0x19,0xf0,0x30,0x36 = ld.w	%d0, [%a15]24816
+0x59,0xff,0x30,0x36 = st.w	[%a15]24816, %d15
+0x2c,0xf4           = st.b	[%a15]4, %d15
+0x39,0xff,0x34,0x36 = ld.bu	%d15, [%a15]24820
+0xe9,0xff,0x34,0x36 = st.b	[%a15]24820, %d15
+0x89,0xa2,0x40,0x09 = st.d	[%sp]0, %e2
+0x09,0xa0,0x40,0x09 = ld.d	%e0, [%sp]0
+0x54,0x31           = ld.w	%d1, [%a3]
+0x08,0x1f           = ld.bu	%d15, [%a15]1
+0xd4,0xff           = ld.a	%a15, [%a15]
+0x54,0x3f           = ld.w	%d15, [%a3]
+0x74,0x3f           = st.w	[%a3], %d15
+0x39,0x2f,0x35,0x06 = ld.bu	%d15, [%a2]24629
+0x85,0xff,0x10,0x00 = ld.w	%d15, 0xf0000010
+0x49,0x40,0x40,0x08 = ldmst	[%a4]0, %e0
+0x74,0xf0           = st.w	[%a15], %d0
+0x74,0x41           = st.w	[%a4], %d1
+0x74,0x4f           = st.w	[%a4], %d15
+0x15,0xd0,0xc0,0xe3 = stlcx	0xd0003f80
+0x15,0xd0,0xc0,0xf7 = stucx	0xd0003fc0
+0x85,0xdf,0xc4,0xf3 = ld.w	%d15, 0xd0003fc4
+0x15,0xd0,0xc0,0xff = lducx	0xd0003fc0
+0x15,0xd0,0xc0,0xeb = ldlcx	0xd0003f80
+0x39,0xff,0x05,0x80 = ld.bu	%d15, [%a15]517
+0xe9,0xff,0x05,0x80 = st.b	[%a15]517, %d15
+0x2c,0xa4           = st.b	[%sp]4, %d15
+0x2c,0xa5           = st.b	[%sp]5, %d15
+0x89,0xaf,0x31,0x08 = st.b	[%sp]49, %d15
+0x89,0xaf,0x24,0x08 = st.b	[%sp]36, %d15
+0x89,0xaf,0x28,0x08 = st.b	[%sp]40, %d15
+0x09,0x2f,0x00,0x08 = ld.b	%d15, [%a2]0
+0x2c,0xfc           = st.b	[%a15]12, %d15
+0x28,0xf8           = st.b	[%a15]15, %d8
+0x2c,0xf2           = st.b	[%a15]2, %d15
+0x08,0x81           = ld.bu	%d1, [%a15]8
+0x09,0xff,0x00,0x69 = ld.w	%d15, [%a15]384
+0x89,0xf0,0x00,0x69 = st.w	[%a15]384, %d0
+0x09,0x22,0x84,0x09 = ld.a	%a2, [%a2]4
+0x19,0xff,0x00,0xa0 = ld.w	%d15, [%a15]640
+0xb4,0xaf           = st.h	[%sp], %d15
+0xac,0xa1           = st.h	[%sp]2, %d15
+0xac,0xa2           = st.h	[%sp]4, %d15
+0xac,0xa3           = st.h	[%sp]6, %d15
+0xb4,0xa2           = st.h	[%sp], %d2
+0x89,0xa2,0x82,0x08 = st.h	[%sp]2, %d2
+0x89,0xa2,0x84,0x08 = st.h	[%sp]4, %d2
+0x89,0xa2,0x86,0x08 = st.h	[%sp]6, %d2
+0x54,0x2f           = ld.w	%d15, [%a2]
+0x09,0x51,0x01,0x00 = ld.b	%d1, [%a5+]1
+0x54,0x22           = ld.w	%d2, [%a2]
+0x74,0x22           = st.w	[%a2], %d2
+0xc8,0x1c           = ld.a	%a12, [%a15]4
+0xc8,0x2d           = ld.a	%a13, [%a15]8
+0x48,0x3c           = ld.w	%d12, [%a15]12
+0x09,0xff,0x10,0x01 = ld.w	%d15, [%a15+]16
+0x04,0xdf           = ld.bu	%d15, [%a13+]
+0x24,0xcf           = st.b	[%a12+], %d15
+0x44,0x21           = ld.w	%d1, [%a2+]
+0x64,0xc1           = st.w	[%a12+], %d1
+0x24,0xc9           = st.b	[%a12+], %d9
+0x64,0xca           = st.w	[%a12+], %d10
+0x24,0xcb           = st.b	[%a12+], %d11
+0x64,0xc8           = st.w	[%a12+], %d8
diff --git a/suite/MC/TriCore/debug.s.cs b/suite/MC/TriCore/debug.s.cs
new file mode 100644
index 0000000000..1eb83d75b4
--- /dev/null
+++ b/suite/MC/TriCore/debug.s.cs
@@ -0,0 +1,2 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_131, None
+0x4b, 0x00, 0x00, 0x00 = cmp.f %d0, %d0, %d0
\ No newline at end of file
diff --git a/suite/MC/TriCore/iLLD_TC375_ADS_Bluetooth_RFCOMM.s.cs b/suite/MC/TriCore/iLLD_TC375_ADS_Bluetooth_RFCOMM.s.cs
new file mode 100644
index 0000000000..4ce1675114
--- /dev/null
+++ b/suite/MC/TriCore/iLLD_TC375_ADS_Bluetooth_RFCOMM.s.cs
@@ -0,0 +1,3285 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None
+0xc2,0xf4           = add	%d4, -1
+0x37,0x04,0x50,0x40 = extr	%d4, %d4, 0, 16
+# 0xd4,0x4f           = ld.a	%a15,[%a4]
+0x09,0x4f,0xc4,0x08 = ld.hu	%d15, [%a4]4
+0x10,0xff           = addsc.a	%a15, %a15, %d15, 0
+# 0x14,0xff           = ld.bu	%d15,[%a15]
+# 0x34,0x5f           = st.b	[%a5],%d15
+0xb0,0x15           = add.a	%a5, 1
+0xc2,0x1f           = add	%d15, 1
+0xac,0x42           = st.h	[%a4]4, %d15
+0x09,0x40,0xc6,0x08 = ld.hu	%d0, [%a4]6
+0x3f,0x0f,0x04,0x80 = jlt.u	%d15, %d0, 0x8
+0xda,0x00           = mov	%d15, 0
+0xff,0x14,0xea,0x7f = jge	%d4, 1, -0x2c
+0x40,0x52           = mov.aa	%a2, %a5
+0x3c,0x01           = j	0x2
+# 0x14,0x5f           = ld.bu	%d15,[%a5]
+# 0x34,0xff           = st.b	[%a15],%d15
+0x02,0x5f           = mov	%d15, %d5
+0xc2,0x34           = add	%d4, 3
+0xb7,0x04,0x02,0x00 = insert	%d0, %d4, 0, 0, 2
+0x37,0x00,0x50,0x80 = extr	%d8, %d0, 0, 16
+0x8b,0xc8,0x01,0x00 = add	%d0, %d8, 28
+0x8b,0x80,0x00,0x40 = add	%d4, %d0, 8
+0x6d,0x00,0x07,0x14 = call	0x280e
+0xbc,0x26           = jz.a	%a2, 0xc
+0x40,0x24           = mov.aa	%a4, %a2
+0x0b,0x8f,0x10,0x48 = mov	%e4, %d15, %d8
+0x6d,0x00,0x32,0x00 = call	0x64
+0xb7,0x04,0x02,0xf0 = insert	%d15, %d4, 0, 0, 2
+0x37,0x0f,0x50,0x00 = extr	%d0, %d15, 0, 16
+# 0x89,0x4f,0x18,0x08 = st.b	[%a4]24,%d15
+0xda,0x01           = mov	%d15, 1
+# 0x89,0x4f,0x19,0x08 = st.b	[%a4]25,%d15
+0x80,0x4f           = mov.d	%d15, %a4
+0x8b,0xcf,0x01,0xf0 = add	%d15, %d15, 28
+0xc2,0x7f           = add	%d15, 7
+0xb7,0x0f,0x03,0xf0 = insert	%d15, %d15, 0, 0, 3
+# 0x74,0x4f           = st.w	[%a4],%d15
+0xac,0x47           = st.h	[%a4]14, %d15
+# 0x89,0x4f,0x0a,0x09 = st.w	[%a4]10,%d15
+# 0x89,0x4f,0x06,0x09 = st.w	[%a4]6,%d15
+0xac,0x49           = st.h	[%a4]18, %d15
+0xac,0x48           = st.h	[%a4]16, %d15
+0x89,0x40,0x94,0x08 = st.h	[%a4]20, %d0
+0x89,0x45,0x96,0x08 = st.h	[%a4]22, %d5
+0x40,0x42           = mov.aa	%a2, %a4
+# 0x4d,0xc0,0xe2,0xff = mfcr	%d15,$icr
+0x37,0x0f,0xe1,0xf7 = extr.u	%d15, %d15, 15, 1
+0x8b,0x0f,0x20,0x02 = ne	%d0, %d15, 0
+0x8c,0x42           = ld.h	%d15, [%a4]4
+0x0b,0xf4,0x80,0xf1 = min	%d15, %d4, %d15
+0x37,0x0f,0x50,0x10 = extr	%d1, %d15, 0, 16
+0x8c,0x4b           = ld.h	%d15, [%a4]22
+0x4b,0xf1,0x01,0x22 = div	%e2, %d1, %d15
+0xa2,0x31           = sub	%d1, %d3
+0x37,0x01,0x50,0x20 = extr	%d2, %d1, 0, 16
+0xa2,0x24           = sub	%d4, %d2
+0x8c,0x4a           = ld.h	%d15, [%a4]20
+0x76,0x03           = jz	%d0, 0x6
+0x02,0x40           = mov	%d0, %d4
+0x3f,0xf0,0x05,0x00 = jlt	%d0, %d15, 0xa
+0x7f,0x0f,0x05,0x00 = jge	%d15, %d0, 0xa
+0x82,0x02           = mov	%d2, 0
+0x1d,0x00,0x9e,0x00 = j	0x13c
+0x8b,0x0f,0x20,0x42 = ne	%d4, %d15, 0
+0xa2,0xf0           = sub	%d0, %d15
+0x4e,0x0d           = jgtz	%d0, 0x1a
+0x82,0x00           = mov	%d0, 0
+# 0x89,0x40,0x06,0x09 = st.w	[%a4]6,%d0
+0x82,0x10           = mov	%d0, 1
+# 0x89,0x40,0x18,0x08 = st.b	[%a4]24,%d0
+0x76,0x43           = jz	%d4, 0x6
+0x82,0x12           = mov	%d2, 1
+0x1d,0x00,0x83,0x00 = j	0x106
+0x91,0x20,0x00,0xf8 = movh.a	%a15, 32770
+0xd9,0xff,0xa4,0xba = lea	%a15, [%a15]-21788
+# 0x09,0xf2,0x40,0x09 = ld.d	%e2,[%a15]
+0x0b,0x26,0x10,0xf1 = ne	%d15, %d6, %d2
+0x0b,0x37,0x80,0xf2 = or.ne	%d15, %d7, %d3
+0xee,0x08           = jnz	%d15, 0x10
+0x3c,0x26           = j	0x4c
+# 0x4d,0xc0,0xe2,0x1f = mfcr	%d1,$icr
+0x37,0x01,0xe1,0x17 = extr.u	%d1, %d1, 15, 1
+0x8b,0x01,0x20,0xf2 = ne	%d15, %d1, 0
+# 0x85,0xf1,0x10,0x01 = ld.w	%d1,f0001010
+0x82,0x03           = mov	%d3, 0
+0x02,0x12           = mov	%d2, %d1
+# 0x85,0xf9,0x2c,0x01 = ld.w	%d9,f000102c
+0x82,0x08           = mov	%d8, 0
+0xa6,0x82           = or	%d2, %d8
+0xa6,0x93           = or	%d3, %d9
+# 0x09,0xf8,0x40,0x09 = ld.d	%e8,[%a15]
+0x26,0x82           = and	%d2, %d8
+0x26,0x93           = and	%d3, %d9
+0x6e,0x03           = jz	%d15, 0x6
+0x0b,0x62,0x40,0x20 = addx	%d2, %d2, %d6
+0x0b,0x73,0x50,0x30 = addc	%d3, %d3, %d7
+# 0x09,0x4f,0x58,0x08 = ld.bu	%d15,[%a4]24
+0xee,0x37           = jnz	%d15, 0x6e
+# 0x09,0xf0,0x40,0x09 = ld.d	%e0,[%a15]
+0x0b,0x02,0x10,0xf1 = ne	%d15, %d2, %d0
+0x0b,0x13,0x80,0xf2 = or.ne	%d15, %d3, %d1
+0xee,0x03           = jnz	%d15, 0x6
+0x3c,0x28           = j	0x50
+0x8b,0x0f,0x20,0xf2 = ne	%d15, %d15, 0
+# 0x85,0xf0,0x10,0x01 = ld.w	%d0,f0001010
+0x82,0x05           = mov	%d5, 0
+0x02,0x04           = mov	%d4, %d0
+# 0x85,0xf1,0x2c,0x01 = ld.w	%d1,f000102c
+0xa6,0x40           = or	%d0, %d4
+0xa6,0x51           = or	%d1, %d5
+# 0x09,0xf4,0x40,0x09 = ld.d	%e4,[%a15]
+0x26,0x40           = and	%d0, %d4
+0x26,0x51           = and	%d1, %d5
+0x0b,0x20,0x50,0xf1 = ge.u	%d15, %d0, %d2
+0x0b,0x31,0x00,0xf2 = and.eq	%d15, %d1, %d3
+0x0b,0x13,0x90,0xf2 = or.lt	%d15, %d3, %d1
+0x6e,0xc8           = jz	%d15, -0x70
+0x8b,0x1f,0x00,0x22 = eq	%d2, %d15, 1
+0xa2,0x5f           = sub	%d15, %d5
+# 0x09,0x4f,0x0a,0x09 = ld.w	%d15,[%a4]10
+0x6e,0x0f           = jz	%d15, 0x1e
+0x4e,0xf7           = jgtz	%d15, 0xe
+0xa2,0x54           = sub	%d4, %d5
+0x37,0x04,0x50,0x20 = extr	%d2, %d4, 0, 16
+0x20,0x08           = sub.a	%sp, 8
+0x40,0x4f           = mov.aa	%a15, %a4
+0x40,0x5c           = mov.aa	%a12, %a5
+0x02,0x48           = mov	%d8, %d4
+0x82,0x09           = mov	%d9, 0
+0xdf,0x08,0xd4,0x00 = jeq	%d8, 0, 0x1a8
+# 0xd4,0xf2           = ld.a	%a2,[%a15]
+# 0xf4,0xa2           = st.a	[%sp],%a2
+0x88,0xaf           = ld.h	%d15, [%a15]20
+0xac,0xa3           = st.h	[%sp]6, %d15
+0x88,0x8f           = ld.h	%d15, [%a15]16
+0xac,0xa2           = st.h	[%sp]4, %d15
+0x91,0x20,0x00,0x28 = movh.a	%a2, 32770
+0xd9,0x22,0xa4,0xba = lea	%a2, [%a2]-21788
+# 0x09,0x20,0x40,0x09 = ld.d	%e0,[%a2]
+0x0b,0x06,0x10,0xf1 = ne	%d15, %d6, %d0
+0x0b,0x17,0x80,0xf2 = or.ne	%d15, %d7, %d1
+# 0x09,0x2a,0x40,0x09 = ld.d	%e10,[%a2]
+0x02,0x02           = mov	%d2, %d0
+0xa6,0x20           = or	%d0, %d2
+0xa6,0x31           = or	%d1, %d3
+# 0x09,0x22,0x40,0x09 = ld.d	%e2,[%a2]
+0x26,0x20           = and	%d0, %d2
+0x26,0x31           = and	%d1, %d3
+0x0b,0x60,0x40,0xa0 = addx	%d10, %d0, %d6
+0x0b,0x71,0x50,0xb0 = addc	%d11, %d1, %d7
+0x40,0xf4           = mov.aa	%a4, %a15
+0x02,0x84           = mov	%d4, %d8
+0x6d,0xff,0x85,0xfd = call	-0x4f6
+0x02,0x2f           = mov	%d15, %d2
+0x6e,0x0e           = jz	%d15, 0x1c
+0x49,0xa4,0x00,0x0a = lea	%a4, [%sp]0
+0x40,0xc5           = mov.aa	%a5, %a12
+0x02,0xf4           = mov	%d4, %d15
+0x6d,0xff,0x47,0xfd = call	-0x572
+0x40,0x2c           = mov.aa	%a12, %a2
+0x6d,0x00,0x87,0x00 = call	0x10e
+0x02,0x28           = mov	%d8, %d2
+0xdf,0x09,0x38,0x80 = jne	%d9, 0, 0x70
+0x0b,0x0a,0x10,0xf1 = ne	%d15, %d10, %d0
+0x0b,0x1b,0x80,0xf2 = or.ne	%d15, %d11, %d1
+0x0b,0xa0,0x50,0xf1 = ge.u	%d15, %d0, %d10
+0x0b,0xb1,0x00,0xf2 = and.eq	%d15, %d1, %d11
+0x0b,0x1b,0x90,0xf2 = or.lt	%d15, %d11, %d1
+0x6e,0x05           = jz	%d15, 0xa
+# 0x89,0xff,0x06,0x09 = st.w	[%a15]6,%d15
+0x3c,0x43           = j	0x86
+0xdf,0x08,0x40,0x00 = jeq	%d8, 0, 0x80
+# 0x09,0xff,0x58,0x08 = ld.bu	%d15,[%a15]24
+0x8b,0x0f,0x00,0x92 = eq	%d9, %d15, 0
+0xdf,0x08,0x71,0xff = jne	%d8, 0, -0x11e
+0x09,0xaf,0xc4,0x08 = ld.hu	%d15, [%sp]4
+0xac,0xf8           = st.h	[%a15]16, %d15
+0x02,0x82           = mov	%d2, %d8
+0x6e,0x07           = jz	%d15, 0xe
+0x8c,0x49           = ld.h	%d15, [%a4]18
+0x09,0x41,0x84,0x08 = ld.h	%d1, [%a4]4
+0xa2,0x1f           = sub	%d15, %d1
+0x02,0x42           = mov	%d2, %d4
+0x3f,0xf2,0x05,0x00 = jlt	%d2, %d15, 0xa
+0x7f,0x2f,0x05,0x00 = jge	%d15, %d2, 0xa
+0x1d,0x00,0xaa,0x00 = j	0x154
+0x8b,0x0f,0x20,0x32 = ne	%d3, %d15, 0
+0x09,0x40,0x84,0x08 = ld.h	%d0, [%a4]4
+0x52,0x00           = sub	%d0, %d15, %d0
+0x3f,0x20,0x0e,0x00 = jlt	%d0, %d2, 0x1c
+# 0x89,0x40,0x0a,0x09 = st.w	[%a4]10,%d0
+# 0x89,0x40,0x19,0x08 = st.b	[%a4]25,%d0
+0x76,0x33           = jz	%d3, 0x6
+0x1d,0x00,0x8c,0x00 = j	0x118
+# 0x4d,0xc0,0xe2,0x0f = mfcr	%d0,$icr
+0x37,0x00,0xe1,0x07 = extr.u	%d0, %d0, 15, 1
+0x8b,0x00,0x20,0xf2 = ne	%d15, %d0, 0
+0x0b,0x60,0x40,0x40 = addx	%d4, %d0, %d6
+0x0b,0x71,0x50,0x50 = addc	%d5, %d1, %d7
+0xa2,0x0f           = sub	%d15, %d0
+0xa2,0xf2           = sub	%d2, %d15
+0x0b,0x2f,0xa0,0xf1 = max	%d15, %d15, %d2
+# 0x09,0x4f,0x59,0x08 = ld.bu	%d15,[%a4]25
+0x0b,0x04,0x10,0xf1 = ne	%d15, %d4, %d0
+0x0b,0x15,0x80,0xf2 = or.ne	%d15, %d5, %d1
+0x0b,0x40,0x50,0xf1 = ge.u	%d15, %d0, %d4
+0x0b,0x51,0x00,0xf2 = and.eq	%d15, %d1, %d5
+0x0b,0x15,0x90,0xf2 = or.lt	%d15, %d5, %d1
+0x8b,0x0f,0x20,0x12 = ne	%d1, %d15, 0
+0x12,0x50           = add	%d0, %d15, %d5
+0x89,0x40,0x84,0x08 = st.h	[%a4]4, %d0
+0x09,0x40,0x8e,0x08 = ld.h	%d0, [%a4]14
+0x0b,0xf0,0xa0,0xf1 = max	%d15, %d0, %d15
+# 0x09,0x4f,0x06,0x09 = ld.w	%d15,[%a4]6
+0x76,0x13           = jz	%d1, 0x6
+0x88,0x9f           = ld.h	%d15, [%a15]18
+0x6d,0xff,0xa7,0xfc = call	-0x6b2
+0x6d,0xff,0x5f,0xfc = call	-0x742
+0x6d,0xff,0x55,0xfe = call	-0x356
+# 0x89,0xff,0x0a,0x09 = st.w	[%a15]10,%d15
+# 0x09,0xff,0x59,0x08 = ld.bu	%d15,[%a15]25
+0xac,0xf9           = st.h	[%a15]18, %d15
+0x53,0x44,0x20,0xf0 = mul	%d15, %d4, 4
+0xd9,0xff,0x90,0x9a = lea	%a15, [%a15]-21936
+# 0x54,0xf1           = ld.w	%d1,[%a15]
+0x40,0x4c           = mov.aa	%a12, %a4
+0xb0,0x4c           = add.a	%a12, 4
+0x91,0x30,0x00,0xff = movh.a	%a15, 61443
+0xd9,0xff,0x00,0x06 = lea	%a15, [%a15]24576
+0x91,0x30,0x00,0x2f = movh.a	%a2, 61443
+# 0x39,0x2f,0x1b,0x06 = ld.bu	%d15,[%a2]24603
+0x37,0x0f,0x62,0xf3 = extr.u	%d15, %d15, 6, 2
+0xee,0x06           = jnz	%d15, 0xc
+0xbb,0x00,0xc2,0xfb = mov.u	%d15, 48160
+0x9b,0xef,0xcb,0xf4 = addih	%d15, %d15, 19646
+0x3c,0x1a           = j	0x34
+0x5e,0x16           = jne	%d15, 1, 0xc
+0xbb,0x00,0x68,0xf9 = mov.u	%d15, 38528
+0x9b,0x8f,0xb9,0xf4 = addih	%d15, %d15, 19352
+0x3c,0x0e           = j	0x1c
+0x5e,0x26           = jne	%d15, 2, 0xc
+0x3c,0x02           = j	0x4
+# 0x09,0xf0,0x59,0x08 = ld.bu	%d0,[%a15]25
+0x37,0x00,0xe7,0x00 = extr.u	%d0, %d0, 1, 7
+0xc2,0x10           = add	%d0, 1
+0x4b,0x00,0x41,0x01 = itof	%d0, %d0
+0x4b,0x0f,0x41,0x00 = mul.f	%d0, %d15, %d0
+# 0x09,0xff,0x5b,0x08 = ld.bu	%d15,[%a15]27
+0x16,0x07           = and	%d15, 7
+0x4b,0x0f,0x41,0xf1 = itof	%d15, %d15
+0x4b,0xf0,0x51,0xf0 = div.f	%d15, %d0, %d15
+0x7b,0x80,0x2c,0x04 = movh	%d0, 17096
+0x4b,0x01,0x51,0x00 = div.f	%d0, %d1, %d0
+0x7b,0x00,0x00,0x14 = movh	%d1, 16384
+0x4b,0x10,0x41,0x00 = mul.f	%d0, %d0, %d1
+0xbb,0x00,0xa0,0x1b = mov.u	%d1, 47616
+0x9b,0xb1,0xa5,0x14 = addih	%d1, %d1, 19035
+0x4b,0x1f,0x51,0xf0 = div.f	%d15, %d15, %d1
+0x4b,0xf0,0x41,0xf0 = mul.f	%d15, %d0, %d15
+# 0x54,0x4f           = ld.w	%d15,[%a4]
+0x7b,0x00,0x20,0x04 = movh	%d0, 16896
+0x7b,0x00,0xf0,0x13 = movh	%d1, 16128
+0x6b,0x0f,0x61,0x41 = madd.f	%d4, %d1, %d15, %d0
+0x6d,0x00,0xd2,0x14 = call	0x29a4
+0xb4,0xc2           = st.h	[%a12], %d2
+0x20,0x10           = sub.a	%sp, 16
+0xd9,0xff,0x80,0x9a = lea	%a15, [%a15]-21952
+0x49,0xff,0x00,0x0a = lea	%a15, [%a15]0
+0x49,0xa2,0x00,0x0a = lea	%a2, [%sp]0
+0xa0,0xf4           = mov.a	%a4, 15
+# 0x04,0xff           = ld.bu	%d15,[%a15+]
+# 0x24,0x2f           = st.b	[%a2+],%d15
+0xfc,0x4e           = loop	%a4, -0x4
+# 0x39,0xff,0x01,0x16 = ld.bu	%d15,[%a15]24641
+0x37,0x0f,0x62,0xf2 = extr.u	%d15, %d15, 4, 2
+0x3e,0x04           = jeq	%d15, %d0, 0x8
+0x82,0x20           = mov	%d0, 2
+0xbe,0x07           = jeq	%d15, %d0, 0x2e
+0x3c,0x1c           = j	0x38
+0x82,0x14           = mov	%d4, 1
+0x6d,0x00,0x07,0x01 = call	0x20e
+0x16,0x0f           = and	%d15, 15
+0x6e,0x0c           = jz	%d15, 0x18
+0x10,0xaf           = addsc.a	%a15, %sp, %d15, 0
+0x4b,0x0f,0x61,0xf1 = utof	%d15, %d15
+0x4b,0xf2,0x51,0x80 = div.f	%d8, %d2, %d15
+0x3c,0x08           = j	0x10
+0xbb,0x00,0x68,0x89 = mov.u	%d8, 38528
+0x9b,0x88,0xb9,0x84 = addih	%d8, %d8, 19352
+# 0x09,0xf0,0x69,0x08 = ld.bu	%d0,[%a15]41
+0x4b,0x0f,0x41,0x10 = mul.f	%d1, %d15, %d0
+# 0x09,0xff,0x6b,0x08 = ld.bu	%d15,[%a15]43
+0x92,0x10           = add	%d0, %d15, 1
+# 0x09,0xff,0x6c,0x08 = ld.bu	%d15,[%a15]44
+0xe2,0xf0           = mul	%d0, %d15
+0x4b,0x00,0x41,0xf1 = itof	%d15, %d0
+0x4b,0xf1,0x51,0x20 = div.f	%d2, %d1, %d15
+# 0x09,0xf0,0x68,0x08 = ld.bu	%d0,[%a15]40
+0x6f,0x00,0x1f,0x80 = jnz.t	%d0, 0, 0x3e
+# 0x09,0xff,0x6d,0x08 = ld.bu	%d15,[%a15]45
+0xbb,0xd0,0xcc,0x0c = mov.u	%d0, 52429
+0x9b,0xc0,0xfc,0x03 = addih	%d0, %d0, 16332
+0x4b,0x0f,0x41,0xf0 = mul.f	%d15, %d15, %d0
+0x3c,0x19           = j	0x32
+0x53,0x20,0x20,0xf0 = mul	%d15, %d0, 2
+# 0x09,0xff,0x5c,0x08 = ld.bu	%d15,[%a15]28
+# 0x39,0xff,0x33,0x06 = ld.bu	%d15,[%a15]24627
+0x3e,0x08           = jeq	%d15, %d0, 0x10
+0x3c,0x23           = j	0x46
+0xbb,0x00,0xc2,0x2b = mov.u	%d2, 48160
+0x9b,0xe2,0xcb,0x24 = addih	%d2, %d2, 19646
+0x3c,0x1f           = j	0x3e
+0x3e,0x46           = jeq	%d15, %d4, 0xc
+0x3e,0x47           = jeq	%d15, %d4, 0xe
+0xda,0x02           = mov	%d15, 2
+0xbe,0x41           = jeq	%d15, %d4, 0x22
+0x3c,0x13           = j	0x26
+0x6d,0xff,0xa6,0xff = call	-0xb4
+0x3c,0x12           = j	0x24
+0x6d,0xff,0xfc,0xfe = call	-0x208
+# 0x39,0xff,0x34,0x06 = ld.bu	%d15,[%a15]24628
+0xae,0x75           = jnz.t	%d15, 7, 0xa
+0x7b,0x00,0x00,0xf4 = movh	%d15, 16384
+0x4b,0xf2,0x51,0x20 = div.f	%d2, %d2, %d15
+0x3c,0x06           = j	0xc
+0x6d,0xff,0x32,0xff = call	-0x19c
+0x3c,0x03           = j	0x6
+0xd9,0x22,0x28,0xa6 = lea	%a2, [%a2]25256
+# 0x54,0x2f           = ld.w	%d15,[%a2]
+0x37,0x0f,0x6e,0xf1 = extr.u	%d15, %d15, 2, 14
+0x8f,0xff,0x83,0x11 = xor	%d1, %d15, 63
+# 0x19,0x2f,0x28,0xa6 = ld.w	%d15,[%a2]25256
+0x6f,0x1f,0x12,0x00 = jz.t	%d15, 1, 0x24
+0x8f,0x21,0x20,0xf0 = sha	%d15, %d1, 2
+0x96,0x01           = or	%d15, 1
+# 0x19,0x20,0x28,0xa6 = ld.w	%d0,[%a2]25256
+0x37,0x00,0x70,0x08 = extr.u	%d0, %d0, 16, 16
+0x8f,0x00,0x21,0x00 = sha	%d0, %d0, 16
+0xa6,0x0f           = or	%d15, %d0
+# 0x59,0x2f,0x28,0xa6 = st.w	[%a2]25256
+0x96,0x02           = or	%d15, 2
+0x16,0x01           = and	%d15, 1
+0xdf,0x1f,0xfb,0x7f = jeq	%d15, 1, -0xa
+0x3b,0x00,0x00,0x01 = mov	%d0, 4096
+0x3c,0x05           = j	0xa
+0xc2,0xf0           = add	%d0, -1
+0x4e,0x03           = jgtz	%d0, 0x6
+# 0x39,0x2f,0x33,0x06 = ld.bu	%d15,[%a2]24627
+0x37,0x0f,0xe1,0xf3 = extr.u	%d15, %d15, 7, 1
+0xee,0xf6           = jnz	%d15, -0x14
+# 0x19,0x2f,0x30,0x06 = ld.w	%d15,[%a2]24624
+0x37,0x0f,0x02,0xfe = insert	%d15, %d15, %d0, 28, 2
+0x37,0x0f,0x01,0xff = insert	%d15, %d15, %d0, 30, 1
+# 0x59,0x2f,0x30,0x06 = st.w	[%a2]24624
+0xda,0xbc           = mov	%d15, 188
+# 0x59,0x2f,0xb4,0x06 = st.w	[%a2]26676
+# 0x19,0x2f,0xa0,0x56 = ld.w	%d15,[%a2]26976
+0x3b,0x20,0xfe,0x0f = mov	%d0, -30
+0x26,0x0f           = and	%d15, %d0
+# 0x59,0x2f,0xa0,0x56 = st.w	[%a2]26976
+# 0x19,0x2f,0xa4,0x56 = ld.w	%d15,[%a2]26980
+# 0x59,0x2f,0xa4,0x56 = st.w	[%a2]26980
+# 0x19,0x2f,0xa8,0x56 = ld.w	%d15,[%a2]26984
+# 0x59,0x2f,0xa8,0x56 = st.w	[%a2]26984
+# 0x39,0x2f,0x1a,0x06 = ld.bu	%d15,[%a2]24602
+0xb7,0x0f,0x01,0xf0 = insert	%d15, %d15, 0, 0, 1
+# 0xe9,0x2f,0x1a,0x06 = st.b	[%a2]24602
+# 0x39,0x2f,0x2a,0x06 = ld.bu	%d15,[%a2]24618
+# 0xe9,0x2f,0x2a,0x06 = st.b	[%a2]24618
+0x3b,0x00,0x00,0xf3 = mov	%d15, 12288
+0xc2,0xff           = add	%d15, -1
+0x4e,0xf3           = jgtz	%d15, 0x6
+0x3c,0x0d           = j	0x1a
+# 0x39,0x20,0x14,0x06 = ld.bu	%d0,[%a2]24596
+0x6f,0x10,0xf8,0x7f = jz.t	%d0, 1, -0x10
+# 0x39,0x20,0x24,0x06 = ld.bu	%d0,[%a2]24612
+0x6f,0x10,0xf2,0x7f = jz.t	%d0, 1, -0x1c
+# 0x08,0x4f           = ld.bu	%d15,[%a15]4
+0x1e,0x13           = jeq	%d15, 1, 0x6
+0xde,0x28           = jne	%d15, 2, 0x30
+# 0x19,0x2f,0x10,0x06 = ld.w	%d15,[%a2]24592
+0x37,0x0f,0x82,0xf2 = insert	%d15, %d15, %d0, 5, 2
+# 0x54,0xf0           = ld.w	%d0,[%a15]
+0x3b,0x90,0xd0,0x33 = mov	%d3, 15625
+0x06,0x63           = sh	%d3, 6
+0x4b,0x30,0x11,0x42 = div.u	%e4, %d0, %d3
+0x8b,0x14,0x1f,0x00 = add	%d0, %d4, -15
+0x37,0x00,0x68,0x00 = extr.u	%d0, %d0, 0, 8
+0x37,0x0f,0x05,0xf8 = insert	%d15, %d15, %d0, 16, 5
+# 0x59,0x2f,0x10,0x06 = st.w	[%a2]24592
+# 0x19,0x20,0x18,0x06 = ld.w	%d0,[%a2]24600
+# 0x08,0x6f           = ld.bu	%d15,[%a15]6
+0x37,0xf0,0x03,0x0c = insert	%d0, %d0, %d15, 24, 3
+# 0x08,0x7f           = ld.bu	%d15,[%a15]7
+0x37,0xf0,0x87,0x04 = insert	%d0, %d0, %d15, 9, 7
+0x37,0xf0,0x02,0x0f = insert	%d0, %d0, %d15, 30, 2
+# 0x59,0x20,0x18,0x06 = st.w	[%a2]24600
+# 0x19,0x20,0x28,0x06 = ld.w	%d0,[%a2]24616
+# 0x08,0xef           = ld.bu	%d15,[%a15]14
+0x37,0xf0,0x01,0x00 = insert	%d0, %d0, %d15, 0, 1
+# 0x08,0xaf           = ld.bu	%d15,[%a15]10
+# 0x08,0xbf           = ld.bu	%d15,[%a15]11
+# 0x59,0x20,0x28,0x06 = st.w	[%a2]24616
+0x3c,0x11           = j	0x22
+0x37,0x00,0xe1,0x00 = extr.u	%d0, %d0, 1, 1
+0xdf,0x10,0xf6,0x7f = jeq	%d0, 1, -0x14
+0xdf,0x10,0xee,0x7f = jeq	%d0, 1, -0x24
+0x3b,0x00,0x00,0x06 = mov	%d0, 24576
+0x3c,0x16           = j	0x2c
+# 0x39,0x2f,0x14,0x06 = ld.bu	%d15,[%a2]24596
+0x37,0x0f,0xe1,0xf2 = extr.u	%d15, %d15, 5, 1
+0x6e,0xf6           = jz	%d15, -0x14
+# 0x39,0x2f,0x24,0x06 = ld.bu	%d15,[%a2]24612
+0x6e,0xef           = jz	%d15, -0x22
+0x37,0x0f,0x61,0xf2 = extr.u	%d15, %d15, 4, 1
+0x6e,0xe8           = jz	%d15, -0x30
+# 0x39,0x20,0x1c,0x06 = ld.bu	%d0,[%a2]24604
+# 0x08,0x8f           = ld.bu	%d15,[%a15]8
+0x37,0xf0,0x03,0xf0 = insert	%d15, %d0, %d15, 0, 3
+# 0xe9,0x2f,0x1c,0x06 = st.b	[%a2]24604
+# 0x19,0x20,0x2c,0x06 = ld.w	%d0,[%a2]24620
+# 0x08,0xcf           = ld.bu	%d15,[%a15]12
+0x37,0xf0,0x03,0x00 = insert	%d0, %d0, %d15, 0, 3
+# 0x08,0xdf           = ld.bu	%d15,[%a15]13
+0x37,0xf0,0x03,0x04 = insert	%d0, %d0, %d15, 8, 3
+# 0x59,0x20,0x2c,0x06 = st.w	[%a2]24620
+0x3b,0xf0,0x49,0x02 = mov	%d0, 9375
+0x06,0x50           = sh	%d0, 5
+0x3c,0x0c           = j	0x18
+# 0x39,0x2f,0x10,0x06 = ld.bu	%d15,[%a2]24592
+0xae,0x17           = jnz.t	%d15, 1, 0xe
+# 0x39,0x2f,0x11,0x06 = ld.bu	%d15,[%a2]24593
+0x6f,0x0f,0xf3,0x7f = jz.t	%d15, 0, -0x1a
+0x96,0x04           = or	%d15, 4
+0x6f,0x20,0xf8,0x7f = jz.t	%d0, 2, -0x10
+0x6f,0x20,0xf2,0x7f = jz.t	%d0, 2, -0x1c
+0xda,0x05           = mov	%d15, 5
+# 0x59,0x2f,0xa0,0x06 = st.w	[%a2]26656
+0xda,0x1d           = mov	%d15, 29
+# 0x59,0x2f,0xa0,0x76 = st.w	[%a2]27104
+# 0x19,0x20,0x30,0x06 = ld.w	%d0,[%a2]24624
+0x37,0xf0,0x02,0x0e = insert	%d0, %d0, %d15, 28, 2
+0x37,0xf0,0x01,0x0f = insert	%d0, %d0, %d15, 30, 1
+0x3b,0x00,0x00,0x31 = mov	%d3, 4096
+0xc2,0xf3           = add	%d3, -1
+0x4e,0x33           = jgtz	%d3, 0x6
+# 0x59,0x20,0x30,0x06 = st.w	[%a2]24624
+0x86,0x21           = sha	%d1, 2
+0x8f,0x31,0x40,0xf1 = or	%d15, %d1, 3
+0x6f,0x0f,0xfc,0x7f = jz.t	%d15, 0, -0x8
+0xee,0x05           = jnz	%d15, 0xa
+# 0x09,0xf4,0x98,0x19 = ld.a	%a4,[%a15]88
+0x6d,0x00,0x85,0x02 = call	0x50a
+0xdf,0x0f,0xcf,0x81 = jne	%d15, 0, 0x39e
+0x49,0xf2,0x1c,0x0a = lea	%a2, [%a15]28
+0x91,0x30,0x00,0x4f = movh.a	%a4, 61443
+0xd9,0x44,0x28,0xa6 = lea	%a4, [%a4]25256
+# 0x19,0x4f,0x28,0xa6 = ld.w	%d15,[%a4]25256
+# 0x19,0x40,0x28,0xa6 = ld.w	%d0,[%a4]25256
+# 0x59,0x4f,0x28,0xa6 = st.w	[%a4]25256
+# 0x19,0x40,0x30,0x06 = ld.w	%d0,[%a4]24624
+# 0x48,0x8f           = ld.w	%d15,[%a15]32
+0x82,0xf3           = mov	%d3, -1
+0xc6,0x3f           = xor	%d15, %d3
+0x26,0xf0           = and	%d0, %d15
+# 0x54,0x23           = ld.w	%d3,[%a2]
+0x26,0x3f           = and	%d15, %d3
+0xa6,0xf0           = or	%d0, %d15
+# 0x19,0x20,0x34,0x06 = ld.w	%d0,[%a2]24628
+0x37,0x00,0x62,0xf2 = extr.u	%d15, %d0, 4, 2
+0xee,0x07           = jnz	%d15, 0xe
+0x37,0x00,0x62,0xfa = extr.u	%d15, %d0, 20, 2
+0xee,0x04           = jnz	%d15, 0x8
+0x37,0x00,0x62,0xfe = extr.u	%d15, %d0, 28, 2
+0x6e,0x36           = jz	%d15, 0x6c
+# 0x48,0xaf           = ld.w	%d15,[%a15]40
+# 0x48,0x93           = ld.w	%d3,[%a15]36
+0x37,0xf0,0x02,0x02 = insert	%d0, %d0, %d15, 4, 2
+0x37,0xf0,0x02,0x0a = insert	%d0, %d0, %d15, 20, 2
+# 0x39,0x2f,0x37,0x06 = ld.bu	%d15,[%a2]24631
+# 0x59,0x20,0x34,0x06 = st.w	[%a2]24628
+# 0x19,0x2f,0x00,0x16 = ld.w	%d15,[%a2]24640
+0x37,0x0f,0x62,0xf6 = extr.u	%d15, %d15, 12, 2
+0x6e,0x30           = jz	%d15, 0x60
+# 0x19,0x20,0x00,0x16 = ld.w	%d0,[%a2]24640
+# 0x48,0xcf           = ld.w	%d15,[%a15]48
+# 0x48,0xb3           = ld.w	%d3,[%a15]44
+0x37,0xf0,0x02,0x06 = insert	%d0, %d0, %d15, 12, 2
+# 0x39,0x2f,0x03,0x16 = ld.bu	%d15,[%a2]24643
+# 0x59,0x20,0x00,0x16 = st.w	[%a2]24640
+# 0x19,0x20,0x0c,0x16 = ld.w	%d0,[%a2]24652
+# 0x48,0xef           = ld.w	%d15,[%a15]56
+# 0x48,0xd3           = ld.w	%d3,[%a15]52
+# 0x39,0x2f,0x0f,0x16 = ld.bu	%d15,[%a2]24655
+# 0x59,0x20,0x0c,0x16 = st.w	[%a2]24652
+# 0x19,0x20,0x00,0x26 = ld.w	%d0,[%a2]24704
+# 0x09,0xff,0x00,0x19 = ld.w	%d15,[%a15]64
+# 0x09,0xf3,0x00,0x19 = ld.w	%d3,[%a15]64
+# 0x48,0xff           = ld.w	%d15,[%a15]60
+0x26,0xf3           = and	%d3, %d15
+0xa6,0x30           = or	%d0, %d3
+# 0x59,0x20,0x00,0x26 = st.w	[%a2]24704
+# 0x19,0x2f,0x04,0x26 = ld.w	%d15,[%a2]24708
+# 0x09,0xf0,0x08,0x19 = ld.w	%d0,[%a15]72
+0xc6,0x30           = xor	%d0, %d3
+# 0x09,0xf3,0x04,0x19 = ld.w	%d3,[%a15]68
+0x26,0x30           = and	%d0, %d3
+# 0x59,0x2f,0x04,0x26 = st.w	[%a2]24708
+# 0x19,0x2f,0x08,0x26 = ld.w	%d15,[%a2]24712
+# 0x09,0xf0,0x10,0x19 = ld.w	%d0,[%a15]80
+# 0x09,0xf3,0x0c,0x19 = ld.w	%d3,[%a15]76
+# 0x59,0x2f,0x08,0x26 = st.w	[%a2]24712
+0xdf,0x0f,0xb1,0x80 = jne	%d15, 0, 0x162
+0x49,0xfc,0x14,0x0a = lea	%a12, [%a15]20
+0x8f,0xff,0x83,0xa1 = xor	%d10, %d15, 63
+0x1d,0x00,0x9c,0x00 = j	0x138
+0x8f,0x2a,0x20,0xf0 = sha	%d15, %d10, 2
+0x82,0x18           = mov	%d8, 1
+0x53,0x69,0x20,0xf0 = mul	%d15, %d9, 6
+# 0xc8,0x62           = ld.a	%a2,[%a15]24
+0x10,0x22           = addsc.a	%a2, %a2, %d15, 0
+# 0x14,0x2f           = ld.bu	%d15,[%a2]
+0x96,0x03           = or	%d15, 3
+# 0x09,0x2b,0x02,0x09 = ld.w	%d11,[%a2]2
+0x82,0x04           = mov	%d4, 0
+0x6d,0xff,0x58,0xfb = call	-0x950
+# 0x39,0x2f,0x30,0x06 = ld.bu	%d15,[%a2]24624
+0x4b,0xf2,0x51,0xf0 = div.f	%d15, %d2, %d15
+0x4b,0xbf,0x41,0xf0 = mul.f	%d15, %d15, %d11
+0x4b,0x0f,0x71,0xf1 = ftouz	%d15, %d15
+0xa2,0x10           = sub	%d0, %d1
+0x3f,0xf0,0xfd,0xff = jlt.u	%d0, %d15, -0x6
+0xc2,0x19           = add	%d9, 1
+0x37,0x09,0x68,0x90 = extr.u	%d9, %d9, 0, 8
+# 0x14,0xcf           = ld.bu	%d15,[%a12]
+0x3f,0xf9,0x65,0xff = jlt.u	%d9, %d15, -0x136
+0x02,0x8f           = mov	%d15, %d8
+0x02,0xf2           = mov	%d2, %d15
+# 0x14,0x4f           = ld.bu	%d15,[%a4]
+# 0x09,0x44,0x41,0x08 = ld.bu	%d4,[%a4]1
+0xdf,0x1f,0x29,0x80 = jne	%d15, 1, 0x52
+0x6d,0xff,0xab,0xf9 = call	-0xcaa
+0x6d,0x00,0x38,0x01 = call	0x270
+0x6d,0x00,0x48,0x00 = call	0x90
+# 0x19,0xf1,0x20,0x06 = ld.w	%d1,[%a15]24608
+0x09,0xa0,0xc4,0x08 = ld.hu	%d0, [%sp]4
+0xbb,0x00,0x40,0x2f = mov.u	%d2, 62464
+0x37,0x01,0x10,0x10 = insert	%d1, %d1, %d0, 0, 16
+# 0x59,0xf1,0x20,0x06 = st.w	[%a15]24608
+# 0x19,0xf0,0x18,0x06 = ld.w	%d0,[%a15]24600
+0x82,0x11           = mov	%d1, 1
+0x37,0x10,0x01,0x01 = insert	%d0, %d0, %d1, 2, 1
+# 0x59,0xf0,0x18,0x06 = st.w	[%a15]24600
+0x6d,0x00,0x4a,0x01 = call	0x294
+# 0x4d,0xc0,0xe1,0xff = mfcr	%d15,$core_id
+0x53,0xcf,0x20,0xf0 = mul	%d15, %d15, 12
+0x60,0xff           = mov.a	%a15, %d15
+0x91,0x30,0x00,0x3f = movh.a	%a3, 61443
+0x30,0xf3           = add.a	%a3, %a15
+0xd9,0x3f,0x0c,0x96 = lea	%a15, [%a3]25164
+# 0x54,0xff           = ld.w	%d15,[%a15]
+0x2e,0x1b           = jz.t	%d15, 1, 0x16
+0x8f,0x24,0x20,0xf0 = sha	%d15, %d4, 2
+# 0x74,0xff           = st.w	[%a15],%d15
+0x86,0x24           = sha	%d4, 2
+0x8f,0x24,0x40,0xf1 = or	%d15, %d4, 2
+0xdf,0x1f,0xfe,0x7f = jeq	%d15, 1, -0x4
+# 0x19,0xff,0x28,0xa6 = ld.w	%d15,[%a15]25256
+# 0x19,0xf0,0x28,0xa6 = ld.w	%d0,[%a15]25256
+# 0x59,0xff,0x28,0xa6 = st.w	[%a15]25256
+0xd9,0xff,0x0c,0x96 = lea	%a15, [%a15]25164
+0x96,0x08           = or	%d15, 8
+# 0x2c,0xf4           = st.b	[%a15]4,%d15
+0x8f,0x34,0x40,0xf1 = or	%d15, %d4, 3
+0x6f,0x0f,0xff,0x7f = jz.t	%d15, 0, -0x2
+# 0x39,0xff,0x2c,0xa6 = ld.bu	%d15,[%a15]25260
+# 0xe9,0xff,0x2c,0xa6 = st.b	[%a15]25260
+0x8f,0xff,0x83,0x21 = xor	%d2, %d15, 63
+0xd9,0xff,0x28,0xa6 = lea	%a15, [%a15]25256
+0x0b,0x45,0x10,0xa8 = mov	%e10, %d5, %d4
+0x49,0xfc,0x10,0x0a = lea	%a12, [%a15]16
+0x82,0x40           = mov	%d0, 4
+0x4b,0x0a,0x01,0x82 = div	%e8, %d10, %d0
+0x8f,0x3a,0x00,0xf1 = and	%d15, %d10, 3
+0x53,0x8f,0x20,0xc0 = mul	%d12, %d15, 8
+0x91,0x40,0x00,0x2f = movh.a	%a2, 61444
+0xd9,0x22,0x80,0x0c = lea	%a2, [%a2]-14336
+0x7d,0x2f,0x15,0x80 = jne.a	%a15, %a2, 0x2a
+0x6d,0x00,0xbd,0x07 = call	0xf7a
+0x6d,0x00,0xb9,0x06 = call	0xd72
+# 0x09,0xf0,0x20,0x19 = ld.w	%d0,[%a15]96
+0x0f,0xa1,0x10,0x10 = sha	%d1, %d1, %d10
+0x82,0xf2           = mov	%d2, -1
+0xc6,0x21           = xor	%d1, %d2
+0x26,0x10           = and	%d0, %d1
+# 0x89,0xf0,0x20,0x19 = st.w	[%a15]96,%d0
+0x6d,0x00,0xcc,0x07 = call	0xf98
+0x53,0x48,0x20,0xf0 = mul	%d15, %d8, 4
+0x10,0xcf           = addsc.a	%a15, %a12, %d15, 0
+0xda,0xff           = mov	%d15, 255
+0x0f,0xcf,0x00,0xf0 = sh	%d15, %d15, %d12
+0x0f,0xcb,0x10,0xb0 = sha	%d11, %d11, %d12
+0x02,0xf3           = mov	%d3, %d15
+0x02,0xb2           = mov	%d2, %d11
+0x49,0xf2,0x40,0x08 = ldmst	[%a15]0, %e2
+0x0b,0x45,0x10,0x88 = mov	%e8, %d5, %d4
+0x6d,0x00,0x9a,0x07 = call	0xf34
+0x02,0x2a           = mov	%d10, %d2
+0x02,0xa4           = mov	%d4, %d10
+0x6d,0x00,0x96,0x06 = call	0xd2c
+0x49,0xff,0x00,0x1a = lea	%a15, [%a15]64
+0xda,0x08           = mov	%d15, 8
+0x4b,0xf8,0x01,0x02 = div	%e0, %d8, %d15
+0x8f,0x78,0x00,0xf1 = and	%d15, %d8, 7
+0x53,0x4f,0x20,0x40 = mul	%d4, %d15, 4
+0x53,0x40,0x20,0xf0 = mul	%d15, %d0, 4
+0xda,0x0f           = mov	%d15, 15
+0x0f,0x4f,0x00,0xf0 = sh	%d15, %d15, %d4
+0x0f,0x49,0x10,0x90 = sha	%d9, %d9, %d4
+0x02,0x92           = mov	%d2, %d9
+0x6d,0x00,0x9e,0x07 = call	0xf3c
+0x40,0xbf           = mov.aa	%a15, %a11
+0x80,0xf2           = mov.d	%d2, %a15
+0x37,0x03,0x68,0xf4 = extr.u	%d15, %d3, 8, 8
+0xb7,0x0f,0x08,0xf0 = insert	%d15, %d15, 0, 0, 8
+0x37,0xf3,0x08,0x34 = insert	%d3, %d3, %d15, 8, 8
+0x37,0x04,0x68,0xf0 = extr.u	%d15, %d4, 0, 8
+0x37,0xf3,0x08,0x30 = insert	%d3, %d3, %d15, 0, 8
+0x37,0x03,0x68,0x08 = extr.u	%d0, %d3, 16, 8
+0x37,0xf3,0x08,0x38 = insert	%d3, %d3, %d15, 16, 8
+# 0x89,0xa2,0x40,0x09 = st.d	[%sp],%e2
+# 0x09,0xa0,0x40,0x09 = ld.d	%e0,[%sp]
+0xb7,0x1f,0x08,0xf0 = insert	%d15, %d15, 1, 0, 8
+0xb7,0x2f,0x08,0xf0 = insert	%d15, %d15, 2, 0, 8
+0xb7,0x3f,0x08,0xf0 = insert	%d15, %d15, 3, 0, 8
+0xb7,0x4f,0x08,0xf0 = insert	%d15, %d15, 4, 0, 8
+0xb7,0x5f,0x08,0xf0 = insert	%d15, %d15, 5, 0, 8
+0xb7,0x7f,0x08,0xf0 = insert	%d15, %d15, 7, 0, 8
+0xb7,0x0f,0x1c,0xf0 = insert	%d15, %d15, 0, 0, 28
+0x7b,0x00,0x00,0x0d = movh	%d0, 53248
+0x7e,0x0d           = jne	%d15, %d0, 0x1a
+0xb7,0x0f,0x0c,0xfa = insert	%d15, %d15, 0, 20, 12
+0xb7,0x7f,0x03,0xfe = insert	%d15, %d15, 7, 28, 3
+# 0x4d,0xc0,0xe1,0x0f = mfcr	%d0,$core_id
+0x7b,0x00,0x00,0x11 = movh	%d1, 4096
+0xe2,0x10           = mul	%d0, %d1
+0x6d,0x00,0x0c,0x03 = call	0x618
+0x7b,0xa0,0x47,0x04 = movh	%d0, 17530
+0x4b,0x0f,0x51,0xf0 = div.f	%d15, %d15, %d0
+0x4b,0x08,0x61,0x01 = utof	%d0, %d8
+0x4b,0x0f,0x71,0x01 = ftouz	%d0, %d15
+0x3c,0x09           = j	0x12
+# 0x85,0xff,0x10,0x01 = ld.w	%d15,f0001010
+0x82,0x19           = mov	%d9, 1
+0xdf,0x7f,0xf6,0xff = jne	%d15, 7, -0x14
+0xd7,0x10,0x21,0x0f = imask	%e0, 1, %d15, 1
+0x49,0x40,0x40,0x08 = ldmst	[%a4]0, %e0
+0x6d,0x00,0x26,0x10 = call	0x204c
+0x6d,0x00,0x22,0x0f = call	0x1e44
+# 0x14,0xf0           = ld.bu	%d0,[%a15]
+0xb7,0x00,0x01,0x00 = insert	%d0, %d0, 0, 0, 1
+# 0x34,0xf0           = st.b	[%a15],%d0
+0x6d,0x00,0x3b,0x10 = call	0x2076
+# 0x09,0x4f,0x4c,0x18 = ld.bu	%d15,[%a4]76
+0x16,0x1f           = and	%d15, 31
+0x3e,0x07           = jeq	%d15, %d0, 0xe
+0x5f,0x0f,0x28,0x00 = jeq	%d15, %d0, 0x50
+0x3c,0x29           = j	0x52
+# 0x39,0xff,0x00,0x16 = ld.bu	%d15,[%a15]24640
+0x82,0x24           = mov	%d4, 2
+0x6d,0x00,0xfc,0x09 = call	0x13f8
+0x6d,0x00,0xcc,0x08 = call	0x1198
+0x3c,0x17           = j	0x2e
+0x53,0x80,0x20,0xf0 = mul	%d15, %d0, 8
+0xd9,0xff,0x50,0xea = lea	%a15, [%a15]-22640
+# 0xd4,0xff           = ld.a	%a15,[%a15]
+0x7d,0x4f,0x0d,0x80 = jne.a	%a15, %a4, 0x1a
+# 0x48,0x1f           = ld.w	%d15,[%a15]4
+0x37,0x0f,0x48,0x20 = extr	%d2, %d15, 0, 8
+0x3c,0x04           = j	0x8
+0xbf,0xc0,0xea,0xff = jlt.u	%d0, 12, -0x2c
+0x6d,0xff,0xa8,0xff = call	-0xb0
+0x09,0xff,0xd4,0x08 = ld.hu	%d15, [%a15]20
+0x37,0x0f,0x6c,0xf0 = extr.u	%d15, %d15, 0, 12
+0x6d,0xff,0xd4,0xff = call	-0x58
+0x53,0xc2,0x20,0xf0 = mul	%d15, %d2, 12
+0x91,0x40,0x00,0x3f = movh.a	%a3, 61444
+0xd9,0x3f,0x10,0x18 = lea	%a15, [%a3]-32688
+0x49,0xf2,0x08,0x0a = lea	%a2, [%a15]8
+0x6d,0xff,0xc6,0xff = call	-0x74
+0xd9,0x32,0x10,0x18 = lea	%a2, [%a3]-32688
+0xb0,0x42           = add.a	%a2, 4
+0x6d,0xff,0xb9,0xff = call	-0x8e
+0x49,0x4f,0x08,0x1a = lea	%a15, [%a4]72
+0xff,0x14,0xfc,0xff = jge.u	%d4, 1, -0x8
+0x0b,0x54,0x10,0x88 = mov	%e8, %d4, %d5
+0x02,0x6a           = mov	%d10, %d6
+# 0x89,0xa7,0x08,0x09 = st.w	[%sp]8,%d7
+# 0x09,0xff,0x4c,0x18 = ld.bu	%d15,[%a15]76
+# 0x78,0x03           = st.w	[%sp]12,%d15
+0x6d,0xff,0xb1,0xff = call	-0x9e
+0xc2,0x18           = add	%d8, 1
+0x8b,0x48,0x60,0xf3 = max.u	%d15, %d8, 4
+0x37,0x0f,0x68,0xf0 = extr.u	%d15, %d15, 0, 8
+# 0x74,0xaf           = st.w	[%sp],%d15
+0x8b,0x1a,0x60,0xf3 = max.u	%d15, %d10, 1
+# 0x78,0x01           = st.w	[%sp]4,%d15
+# 0x54,0xaf           = ld.w	%d15,[%sp]
+0x4b,0xf9,0x41,0x50 = mul.f	%d5, %d9, %d15
+0x3b,0xf0,0x26,0xf1 = mov	%d15, 4719
+0x9b,0x3f,0xa8,0xf3 = addih	%d15, %d15, 14979
+0x4b,0xf5,0x41,0x30 = mul.f	%d3, %d5, %d15
+0x4b,0x52,0x51,0x00 = div.f	%d0, %d2, %d5
+0x4b,0x00,0x71,0x61 = ftouz	%d6, %d0
+0x8f,0x46,0x1f,0xf0 = sh	%d15, %d6, -12
+0x6e,0x0d           = jz	%d15, 0x1a
+0x7b,0x00,0x18,0x14 = movh	%d1, 16768
+0x4b,0x19,0x41,0x10 = mul.f	%d1, %d9, %d1
+0x4b,0x12,0x51,0x10 = div.f	%d1, %d2, %d1
+0x4b,0x01,0x71,0x11 = ftouz	%d1, %d1
+0x8f,0x41,0x1f,0xf0 = sh	%d15, %d1, -12
+0x6e,0x02           = jz	%d15, 0x4
+0x02,0x69           = mov	%d9, %d6
+0x82,0x07           = mov	%d7, 0
+0x4b,0x00,0x61,0x01 = utof	%d0, %d0
+0x4b,0x02,0x41,0xf0 = mul.f	%d15, %d2, %d0
+0x4b,0x06,0x61,0x01 = utof	%d0, %d6
+0x4b,0x0f,0x51,0x00 = div.f	%d0, %d15, %d0
+0x6b,0x00,0x31,0xf5 = sub.f	%d15, %d5, %d0
+0x82,0x01           = mov	%d1, 0
+0x4b,0x1f,0x01,0xf0 = cmp.f	%d15, %d15, %d1
+0xae,0x04           = jnz.t	%d15, 0, 0x8
+0x6b,0x00,0x31,0xb5 = sub.f	%d11, %d5, %d0
+0x67,0xff,0xbf,0xbf = insn.t	%d11, %d15, 31, %d15, 31
+0x4b,0x3b,0x01,0xf0 = cmp.f	%d15, %d11, %d3
+0x16,0x03           = and	%d15, 3
+0x82,0x2d           = mov	%d13, 2
+0x3c,0x39           = j	0x72
+0xdf,0x2d,0x05,0x80 = jne	%d13, 2, 0xa
+0x82,0x1e           = mov	%d14, 1
+0x3c,0x07           = j	0xe
+0x73,0xd7,0x0a,0x00 = mul	%d0, %d7, %d13
+0x4b,0x80,0x11,0x02 = div.u	%e0, %d0, %d8
+0x8b,0x10,0x00,0xe0 = add	%d14, %d0, 1
+0x4b,0x0d,0x61,0xa1 = utof	%d10, %d13
+0x4b,0xa2,0x41,0xa0 = mul.f	%d10, %d2, %d10
+0x03,0x6d,0x0a,0xc0 = madd	%d12, %d0, %d13, %d6
+0x4b,0x0c,0x61,0xf1 = utof	%d15, %d12
+0x4b,0xfa,0x51,0xc0 = div.f	%d12, %d10, %d15
+0x6b,0x0c,0x31,0xf5 = sub.f	%d15, %d5, %d12
+0x82,0x0a           = mov	%d10, 0
+0x4b,0xaf,0x01,0xf0 = cmp.f	%d15, %d15, %d10
+0x6b,0x0c,0x31,0xa5 = sub.f	%d10, %d5, %d12
+0x67,0xff,0xbf,0xaf = insn.t	%d10, %d15, 31, %d15, 31
+0x4b,0xab,0x01,0xf0 = cmp.f	%d15, %d11, %d10
+0x37,0x0f,0x61,0xf1 = extr.u	%d15, %d15, 2, 1
+0x6e,0x06           = jz	%d15, 0xc
+0x02,0xab           = mov	%d11, %d10
+0x02,0xd8           = mov	%d8, %d13
+0x03,0x6d,0x0a,0x90 = madd	%d9, %d0, %d13, %d6
+0x02,0x07           = mov	%d7, %d0
+0x7f,0x0e,0xde,0xff = jge.u	%d14, %d0, -0x44
+0xc2,0x1d           = add	%d13, 1
+0xf6,0x47           = jnz	%d4, 0xe
+0x73,0x6d,0x0a,0xf0 = mul	%d15, %d13, %d6
+0x3b,0xf0,0xff,0x00 = mov	%d0, 4095
+0x7f,0xf0,0xc3,0xff = jge.u	%d0, %d15, -0x7a
+0x6d,0x00,0x36,0x00 = call	0x6c
+0x09,0xff,0xe0,0x08 = ld.hu	%d15, [%a15]32
+0x37,0x09,0x70,0x00 = extr.u	%d0, %d9, 0, 16
+0x37,0x0f,0x0c,0xf0 = insert	%d15, %d15, %d0, 0, 12
+0x89,0xff,0xa0,0x08 = st.h	[%a15]32, %d15
+0x09,0xff,0xe2,0x08 = ld.hu	%d15, [%a15]34
+0x37,0x08,0x70,0x00 = extr.u	%d0, %d8, 0, 16
+0x89,0xff,0xa2,0x08 = st.h	[%a15]34, %d15
+# 0x09,0xf0,0x56,0x08 = ld.bu	%d0,[%a15]22
+0x37,0xf0,0x04,0xf0 = insert	%d15, %d0, %d15, 0, 4
+# 0x89,0xff,0x16,0x08 = st.b	[%a15]22,%d15
+# 0x09,0xf0,0x57,0x08 = ld.bu	%d0,[%a15]23
+# 0x58,0x01           = ld.w	%d15,[%sp]4
+# 0x89,0xff,0x17,0x08 = st.b	[%a15]23,%d15
+# 0x58,0x02           = ld.w	%d15,[%sp]8
+0x37,0xf0,0x81,0xf3 = insert	%d15, %d0, %d15, 7, 1
+# 0x09,0xa4,0x0c,0x09 = ld.w	%d4,[%sp]12
+0x6d,0x00,0x05,0x00 = call	0xa
+0x37,0x4f,0x05,0xf0 = insert	%d15, %d15, %d4, 0, 5
+# 0x89,0x4f,0x0c,0x18 = st.b	[%a4]76,%d15
+0xf6,0x49           = jnz	%d4, 0x12
+# 0x09,0x4f,0x4f,0x18 = ld.bu	%d15,[%a4]79
+0xee,0xfb           = jnz	%d15, -0xa
+0xdf,0x1f,0xfb,0xff = jne	%d15, 1, -0xa
+0x49,0x4f,0x04,0x1a = lea	%a15, [%a4]68
+# 0x09,0x44,0x88,0x09 = ld.a	%a4,[%a4]8
+0x6d,0x00,0x56,0x10 = call	0x20ac
+# 0x09,0x44,0x84,0x09 = ld.a	%a4,[%a4]4
+0x6d,0x00,0xf8,0x10 = call	0x21f0
+# 0x09,0xff,0x50,0x08 = ld.bu	%d15,[%a15]16
+# 0x89,0xff,0x10,0x08 = st.b	[%a15]16,%d15
+0x6d,0x00,0xa0,0x11 = call	0x2340
+# 0xc8,0x14           = ld.a	%a4,[%a15]4
+0x6d,0x00,0x9b,0x11 = call	0x2336
+# 0x2c,0xfc           = st.b	[%a15]12,%d15
+0x0b,0x45,0x10,0x68 = mov	%e6, %d5, %d4
+# 0x09,0x28,0x40,0x09 = ld.d	%e8,[%a2]
+0x0b,0x60,0x40,0x80 = addx	%d8, %d0, %d6
+0x0b,0x71,0x50,0x90 = addc	%d9, %d1, %d7
+# 0x09,0xc4,0x84,0x09 = ld.a	%a4,[%a12]4
+0x09,0x44,0x94,0x08 = ld.h	%d4, [%a4]20
+0x6d,0x00,0xa1,0x10 = call	0x2142
+0x6e,0x3e           = jz	%d15, 0x7c
+# 0xd4,0xcf           = ld.a	%a15,[%a12]
+0xba,0x0f           = eq	%d15, %d15, 0
+0xee,0x38           = jnz	%d15, 0x70
+0x0b,0x08,0x10,0x21 = ne	%d2, %d8, %d0
+0x0b,0x19,0x80,0x22 = or.ne	%d2, %d9, %d1
+0xf6,0x23           = jnz	%d2, 0x6
+0x8b,0x00,0x20,0x02 = ne	%d0, %d0, 0
+# 0x85,0xf5,0x2c,0x01 = ld.w	%d5,f000102c
+0xa6,0x42           = or	%d2, %d4
+0xa6,0x53           = or	%d3, %d5
+0x26,0x42           = and	%d2, %d4
+0x26,0x53           = and	%d3, %d5
+0x0b,0x82,0x50,0x01 = ge.u	%d0, %d2, %d8
+0x0b,0x93,0x00,0x02 = and.eq	%d0, %d3, %d9
+0x0b,0x39,0x90,0x02 = or.lt	%d0, %d9, %d3
+0xdf,0x00,0xc5,0x7f = jeq	%d0, 0, -0x76
+# 0xcc,0x42           = ld.a	%a15,[%a4]8
+0x88,0x22           = ld.h	%d2, [%a15]4
+0x49,0xf2,0x19,0x0a = lea	%a2, [%a15]25
+# 0x09,0x42,0x10,0x09 = ld.w	%d2,[%a4]16
+# 0x09,0x42,0x54,0x09 = ld.d	%e2,[%a4]20
+# 0xcc,0x41           = ld.a	%a15,[%a4]4
+0x88,0x20           = ld.h	%d0, [%a15]4
+0x37,0x0f,0x50,0x20 = extr	%d2, %d15, 0, 16
+# 0xf4,0xa4           = st.a	[%sp],%a4
+0x40,0x5d           = mov.aa	%a13, %a5
+# 0xd4,0xdf           = ld.a	%a15,[%a13]
+# 0xf4,0x4f           = st.a	[%a4],%a15
+0x6d,0xff,0x98,0xfd = call	-0x4d0
+0x6d,0xff,0x0d,0xff = call	-0x1e6
+# 0x09,0xf0,0x5a,0x08 = ld.bu	%d0,[%a15]26
+0x37,0xf0,0x02,0xf0 = insert	%d15, %d0, %d15, 0, 2
+# 0x89,0xff,0x1a,0x08 = st.b	[%a15]26,%d15
+0x09,0xdf,0xc8,0x08 = ld.hu	%d15, [%a13]8
+0x09,0xf0,0xd4,0x08 = ld.hu	%d0, [%a15]20
+0x37,0x0f,0x70,0xf0 = extr.u	%d15, %d15, 0, 16
+0x37,0xf0,0x0c,0xf0 = insert	%d15, %d0, %d15, 0, 12
+0xac,0xfa           = st.h	[%a15]20, %d15
+# 0x09,0xd4,0x6c,0x08 = ld.bu	%d4,[%a13]44
+0x6d,0xff,0xf7,0xfe = call	-0x212
+# 0x09,0xd4,0x04,0x09 = ld.w	%d4,[%a13]4
+# 0x09,0xd5,0x4a,0x08 = ld.bu	%d5,[%a13]10
+# 0x09,0xd6,0x4d,0x08 = ld.bu	%d6,[%a13]13
+# 0x09,0xd7,0x4c,0x08 = ld.bu	%d7,[%a13]12
+0x6d,0xff,0x1a,0xfe = call	-0x3cc
+0x6d,0xff,0xe7,0xfe = call	-0x232
+# 0x09,0xdf,0x7c,0x08 = ld.bu	%d15,[%a13]60
+0x37,0x0f,0x01,0xf2 = insert	%d15, %d15, %d0, 4, 1
+# 0x2c,0xf7           = st.b	[%a15]7,%d15
+# 0x09,0xdf,0x56,0x08 = ld.bu	%d15,[%a13]22
+# 0x09,0xf0,0x5b,0x08 = ld.bu	%d0,[%a15]27
+0x37,0xf0,0x01,0xf3 = insert	%d15, %d0, %d15, 6, 1
+# 0x89,0xff,0x1b,0x08 = st.b	[%a15]27,%d15
+# 0x09,0xdf,0x54,0x08 = ld.bu	%d15,[%a13]20
+# 0x09,0xdf,0x51,0x08 = ld.bu	%d15,[%a13]17
+0x37,0xf0,0x83,0xf0 = insert	%d15, %d0, %d15, 1, 3
+# 0x89,0xff,0x19,0x08 = st.b	[%a15]25,%d15
+# 0x09,0xdf,0x53,0x08 = ld.bu	%d15,[%a13]19
+0x37,0xf0,0x01,0xf2 = insert	%d15, %d0, %d15, 4, 1
+# 0x09,0xdf,0x55,0x08 = ld.bu	%d15,[%a13]21
+# 0x09,0xf0,0x5c,0x08 = ld.bu	%d0,[%a15]28
+# 0x89,0xff,0x1c,0x08 = st.b	[%a15]28,%d15
+# 0x09,0xd0,0x58,0x08 = ld.bu	%d0,[%a13]24
+0x37,0x0f,0x02,0xf3 = insert	%d15, %d15, %d0, 6, 2
+# 0x09,0xdf,0x59,0x08 = ld.bu	%d15,[%a13]25
+# 0x09,0xf0,0x50,0x08 = ld.bu	%d0,[%a15]16
+0x37,0xf0,0x02,0xf3 = insert	%d15, %d0, %d15, 6, 2
+# 0x09,0xdf,0x50,0x08 = ld.bu	%d15,[%a13]16
+0x09,0xf0,0xd8,0x08 = ld.hu	%d0, [%a15]24
+0x37,0xf0,0x03,0xf3 = insert	%d15, %d0, %d15, 6, 3
+0xac,0xfc           = st.h	[%a15]24, %d15
+# 0x09,0xd0,0x5a,0x08 = ld.bu	%d0,[%a13]26
+0x8b,0xf0,0x20,0x03 = min.u	%d0, %d0, 15
+0x37,0x0f,0x04,0xf0 = insert	%d15, %d15, %d0, 0, 4
+# 0x2c,0xfd           = st.b	[%a15]13,%d15
+# 0x09,0xdf,0x5b,0x08 = ld.bu	%d15,[%a13]27
+# 0x09,0xf0,0x51,0x08 = ld.bu	%d0,[%a15]17
+0x8b,0xff,0x20,0xf3 = min.u	%d15, %d15, 15
+# 0x89,0xff,0x11,0x08 = st.b	[%a15]17,%d15
+# 0x09,0xd0,0x5d,0x08 = ld.bu	%d0,[%a13]29
+0x37,0x0f,0x02,0xf2 = insert	%d15, %d15, %d0, 4, 2
+# 0x09,0xdf,0x5e,0x08 = ld.bu	%d15,[%a13]30
+0x37,0xf0,0x02,0xf2 = insert	%d15, %d0, %d15, 4, 2
+# 0x09,0xdf,0x52,0x08 = ld.bu	%d15,[%a13]18
+# 0x09,0xdc,0xa8,0x09 = ld.a	%a12,[%a13]40
+0xbd,0x0c,0x79,0x00 = jz.a	%a12, 0xf2
+# 0xd4,0xce           = ld.a	%a14,[%a12]
+0xbd,0x0e,0x28,0x00 = jz.a	%a14, 0x50
+# 0x09,0xc0,0x04,0x08 = ld.b	%d0,[%a12]4
+# 0x09,0xc9,0x5d,0x08 = ld.bu	%d9,[%a12]29
+# 0x4c,0xe1           = ld.w	%d15,[%a14]4
+0x6e,0x21           = jz	%d15, 0x42
+# 0x09,0xe4,0x84,0x09 = ld.a	%a4,[%a14]4
+# 0x09,0xe4,0x48,0x08 = ld.bu	%d4,[%a14]8
+0x37,0x00,0x68,0x50 = extr.u	%d5, %d0, 0, 8
+0x6d,0x00,0x3a,0x05 = call	0xa74
+0x02,0x95           = mov	%d5, %d9
+0x6d,0x00,0x65,0x05 = call	0xaca
+# 0xd4,0xe2           = ld.a	%a2,[%a14]
+# 0x0c,0x27           = ld.bu	%d15,[%a2]7
+0x37,0x0f,0x81,0xf2 = insert	%d15, %d15, %d0, 5, 1
+# 0x2c,0x27           = st.b	[%a2]7,%d15
+# 0x0c,0xec           = ld.bu	%d15,[%a14]12
+# 0x09,0x20,0x46,0x08 = ld.bu	%d0,[%a2]6
+# 0x2c,0x26           = st.b	[%a2]6,%d15
+# 0x09,0xce,0x88,0x09 = ld.a	%a14,[%a12]8
+0xbd,0x0e,0x1e,0x00 = jz.a	%a14, 0x3c
+# 0x09,0xc0,0x0c,0x08 = ld.b	%d0,[%a12]12
+0x6e,0x17           = jz	%d15, 0x2e
+0x6d,0x00,0x10,0x05 = call	0xa20
+0x6d,0x00,0x3b,0x05 = call	0xa76
+# 0x09,0x20,0x44,0x08 = ld.bu	%d0,[%a2]4
+# 0x2c,0x24           = st.b	[%a2]4,%d15
+# 0x09,0xce,0x90,0x09 = ld.a	%a14,[%a12]16
+0xbd,0x0e,0x15,0x00 = jz.a	%a14, 0x2a
+# 0x09,0xc5,0x54,0x08 = ld.bu	%d5,[%a12]20
+0xa6,0xf5           = or	%d5, %d15
+0x6d,0x00,0xf2,0x04 = call	0x9e4
+0x6d,0x00,0x1d,0x05 = call	0xa3a
+# 0x09,0xce,0x98,0x09 = ld.a	%a14,[%a12]24
+# 0x09,0xc5,0x5c,0x08 = ld.bu	%d5,[%a12]28
+0x6d,0x00,0xdb,0x04 = call	0x9b6
+0x6d,0x00,0x06,0x05 = call	0xa0c
+0x6d,0xff,0xf0,0xfd = call	-0x420
+# 0x89,0xff,0x00,0x19 = st.w	[%a15]64,%d15
+0x82,0xff           = mov	%d15, -1
+# 0x6c,0xff           = st.w	[%a15]60,%d15
+# 0xd4,0xa2           = ld.a	%a2,[%sp]
+# 0x2c,0x2e           = st.b	[%a2]14,%d15
+# 0x09,0xdf,0x6d,0x08 = ld.bu	%d15,[%a13]45
+0x2e,0x0c           = jz.t	%d15, 0, 0x18
+# 0x09,0xf0,0x42,0x18 = ld.bu	%d0,[%a15]66
+0x37,0xf0,0x01,0xf0 = insert	%d15, %d0, %d15, 0, 1
+# 0x89,0xff,0x02,0x18 = st.b	[%a15]66,%d15
+0x2e,0x1c           = jz.t	%d15, 1, 0x18
+0x37,0xf0,0x01,0xf1 = insert	%d15, %d0, %d15, 2, 1
+0x2e,0x2c           = jz.t	%d15, 2, 0x18
+# 0x09,0xf0,0x43,0x18 = ld.bu	%d0,[%a15]67
+# 0x89,0xff,0x03,0x18 = st.b	[%a15]67,%d15
+0x2e,0x3c           = jz.t	%d15, 3, 0x18
+0x37,0xf0,0x81,0xf1 = insert	%d15, %d0, %d15, 3, 1
+0x2e,0x4c           = jz.t	%d15, 4, 0x18
+# 0x2c,0x2d           = st.b	[%a2]13,%d15
+# 0x2c,0x2c           = st.b	[%a2]12,%d15
+# 0x09,0xdf,0x7d,0x08 = ld.bu	%d15,[%a13]61
+# 0x2c,0x2f           = st.b	[%a2]15,%d15
+0xd2,0x00           = mov	%e0, 0
+# 0x89,0x20,0x54,0x09 = st.d	[%a2]20,%e0
+# 0x6c,0x24           = st.w	[%a2]16,%d15
+# 0x0c,0x2f           = ld.bu	%d15,[%a2]15
+0x3b,0xc0,0x00,0x90 = mov	%d9, 12
+# 0x4c,0xdc           = ld.w	%d15,[%a13]48
+# 0x09,0xd4,0xb0,0x09 = ld.a	%a4,[%a13]48
+0x09,0xd4,0xae,0x08 = ld.h	%d4, [%a13]46
+0x6d,0x00,0xbe,0x0f = call	0x1f7c
+# 0xd4,0xa4           = ld.a	%a4,[%sp]
+# 0x89,0x42,0x84,0x09 = st.a	[%a4]4,%a2
+0x6d,0x00,0x73,0x0f = call	0x1ee6
+# 0x4c,0xde           = ld.w	%d15,[%a13]56
+# 0x09,0xd4,0xb8,0x09 = ld.a	%a4,[%a13]56
+0x09,0xd4,0xb4,0x08 = ld.h	%d4, [%a13]52
+0x6d,0x00,0xa9,0x0f = call	0x1f52
+# 0x89,0x42,0x88,0x09 = st.a	[%a4]8,%a2
+0x6d,0x00,0x5e,0x0f = call	0x1ebc
+# 0x09,0xd9,0x66,0x08 = ld.bu	%d9,[%a13]38
+0x09,0xdf,0xe2,0x08 = ld.hu	%d15, [%a13]34
+0xdf,0x19,0x22,0x80 = jne	%d9, 1, 0x44
+0x6d,0xff,0x5e,0xfc = call	-0x744
+# 0x14,0x20           = ld.bu	%d0,[%a2]
+0x37,0xf0,0x08,0xf0 = insert	%d15, %d0, %d15, 0, 8
+# 0x34,0x2f           = st.b	[%a2],%d15
+# 0x0c,0x21           = ld.bu	%d15,[%a2]1
+0x37,0x9f,0x83,0xf1 = insert	%d15, %d15, %d9, 3, 3
+# 0x2c,0x21           = st.b	[%a2]1,%d15
+# 0x0c,0x23           = ld.bu	%d15,[%a2]3
+# 0x2c,0x23           = st.b	[%a2]3,%d15
+0x09,0xdf,0xe0,0x08 = ld.hu	%d15, [%a13]32
+0x6d,0xff,0x46,0xfc = call	-0x774
+0x09,0xdf,0xe4,0x08 = ld.hu	%d15, [%a13]36
+0x6d,0xff,0x08,0xfc = call	-0x7f0
+0x37,0xf0,0x81,0xf0 = insert	%d15, %d0, %d15, 1, 1
+0x37,0x0f,0x81,0xf0 = insert	%d15, %d15, %d0, 1, 1
+# 0xf4,0x45           = st.a	[%a4],%a5
+# 0x89,0x4f,0x3c,0x08 = st.b	[%a4]60,%d15
+# 0x89,0x4f,0x2c,0x08 = st.b	[%a4]44,%d15
+0xac,0x44           = st.h	[%a4]8, %d15
+0x7b,0x10,0x7e,0xf4 = movh	%d15, 18401
+# 0x6c,0x41           = st.w	[%a4]4,%d15
+0xda,0x03           = mov	%d15, 3
+# 0x2c,0x4a           = st.b	[%a4]10,%d15
+# 0x2c,0x4c           = st.b	[%a4]12,%d15
+# 0x2c,0x4d           = st.b	[%a4]13,%d15
+# 0x89,0x4f,0x10,0x08 = st.b	[%a4]16,%d15
+# 0x89,0x4f,0x11,0x08 = st.b	[%a4]17,%d15
+# 0x89,0x4f,0x12,0x08 = st.b	[%a4]18,%d15
+# 0x89,0x4f,0x13,0x08 = st.b	[%a4]19,%d15
+# 0x89,0x4f,0x16,0x08 = st.b	[%a4]22,%d15
+# 0x89,0x4f,0x14,0x08 = st.b	[%a4]20,%d15
+0xda,0x07           = mov	%d15, 7
+# 0x89,0x4f,0x15,0x08 = st.b	[%a4]21,%d15
+# 0x89,0x4f,0x1a,0x08 = st.b	[%a4]26,%d15
+# 0x89,0x4f,0x1b,0x08 = st.b	[%a4]27,%d15
+# 0x89,0x4f,0x1c,0x08 = st.b	[%a4]28,%d15
+# 0x89,0x4f,0x1d,0x08 = st.b	[%a4]29,%d15
+# 0x89,0x4f,0x1e,0x08 = st.b	[%a4]30,%d15
+0x89,0x4f,0xa2,0x08 = st.h	[%a4]34, %d15
+0x89,0x4f,0xa0,0x08 = st.h	[%a4]32, %d15
+0x89,0x4f,0xa4,0x08 = st.h	[%a4]36, %d15
+# 0x89,0x4f,0x26,0x08 = st.b	[%a4]38,%d15
+# 0x89,0x4f,0x2d,0x08 = st.b	[%a4]45,%d15
+0xa0,0x0f           = mov.a	%a15, 0
+# 0xec,0x4a           = st.a	[%a4]40,%a15
+# 0xec,0x4e           = st.a	[%a4]56,%a15
+# 0xec,0x4c           = st.a	[%a4]48,%a15
+0x89,0x4f,0xae,0x08 = st.h	[%a4]46, %d15
+0x89,0x4f,0xb4,0x08 = st.h	[%a4]52, %d15
+# 0x89,0x4f,0x3d,0x08 = st.b	[%a4]61,%d15
+0xee,0x2b           = jnz	%d15, 0x56
+# 0xc8,0x12           = ld.a	%a2,[%a15]4
+0x8c,0x22           = ld.h	%d15, [%a2]4
+0xee,0x22           = jnz	%d15, 0x44
+# 0x08,0xff           = ld.bu	%d15,[%a15]15
+0x3e,0x0a           = jeq	%d15, %d0, 0x14
+0x3c,0x14           = j	0x28
+0x49,0xa5,0x00,0x0a = lea	%a5, [%sp]0
+0xd2,0x06           = mov	%e6, 0
+0x6d,0x00,0xbd,0x0e = call	0x1d7a
+0x49,0xa5,0x04,0x0a = lea	%a5, [%sp]4
+0x3b,0xc0,0x00,0x40 = mov	%d4, 12
+0x6d,0x00,0xb4,0x0e = call	0x1d68
+# 0x0c,0xac           = ld.bu	%d15,[%sp]12
+# 0x34,0xaf           = st.b	[%sp],%d15
+# 0xd4,0xf4           = ld.a	%a4,[%a15]
+0x6d,0xff,0x60,0xfc = call	-0x740
+# 0x09,0xff,0x76,0x08 = ld.bu	%d15,[%a15]54
+0x6e,0x09           = jz	%d15, 0x12
+# 0x09,0xff,0x7e,0x08 = ld.bu	%d15,[%a15]62
+# 0x89,0xff,0x3e,0x08 = st.b	[%a15]62,%d15
+# 0x0c,0x4e           = ld.bu	%d15,[%a4]14
+# 0x2c,0x4e           = st.b	[%a4]14,%d15
+# 0x09,0xff,0x77,0x08 = ld.bu	%d15,[%a15]55
+# 0x09,0xff,0x7f,0x08 = ld.bu	%d15,[%a15]63
+# 0x89,0xff,0x3f,0x08 = st.b	[%a15]63,%d15
+0x37,0x0f,0xe1,0xf1 = extr.u	%d15, %d15, 3, 1
+0x37,0x0f,0x61,0xf3 = extr.u	%d15, %d15, 6, 1
+0x96,0x40           = or	%d15, 64
+0x96,0x10           = or	%d15, 16
+0x20,0x20           = sub.a	%sp, 32
+0xbe,0x08           = jeq	%d15, %d0, 0x30
+0x3c,0x56           = j	0xac
+# 0x09,0x2f,0x52,0x08 = ld.bu	%d15,[%a2]18
+0x6d,0xff,0x0f,0xfb = call	-0x9e2
+# 0xc8,0x24           = ld.a	%a4,[%a15]8
+0x6d,0x00,0x4c,0x0f = call	0x1e98
+0x76,0x23           = jz	%d2, 0x6
+0x3c,0x40           = j	0x80
+0x3c,0x38           = j	0x70
+# 0x89,0xa0,0x50,0x09 = st.d	[%sp]16,%e0
+0x6d,0xff,0xda,0xfa = call	-0xa4c
+# 0x14,0xaf           = ld.bu	%d15,[%sp]
+# 0x89,0xaf,0x18,0x08 = st.b	[%sp]24,%d15
+0x49,0xa5,0x10,0x0a = lea	%a5, [%sp]16
+0x6d,0x00,0x13,0x0f = call	0x1e26
+0xee,0xc4           = jnz	%d15, -0x78
+0x20,0x18           = sub.a	%sp, 24
+# 0x89,0xf0,0x54,0x09 = st.d	[%a15]20,%e0
+# 0x48,0x4f           = ld.w	%d15,[%a15]16
+# 0x6c,0xf4           = st.w	[%a15]16,%d15
+0xee,0x40           = jnz	%d15, 0x80
+0x3e,0x05           = jeq	%d15, %d0, 0xa
+0x5f,0x0f,0x29,0x00 = jeq	%d15, %d0, 0x52
+# 0x89,0xaf,0x10,0x08 = st.b	[%sp]16,%d15
+0x37,0x0f,0x70,0x00 = extr.u	%d0, %d15, 0, 16
+# 0x0c,0x2e           = ld.bu	%d15,[%a2]14
+# 0x09,0xaf,0x50,0x08 = ld.bu	%d15,[%sp]16
+0x8b,0x0f,0x01,0xf1 = rsub	%d15, %d15, 16
+0x7f,0xf0,0x03,0x80 = jge.u	%d0, %d15, 0x6
+0x02,0x0f           = mov	%d15, %d0
+0x37,0x0f,0x50,0x40 = extr	%d4, %d15, 0, 16
+0x6d,0x00,0xae,0x0d = call	0x1b5c
+0x6d,0xff,0x5d,0xfb = call	-0x946
+0x6d,0x00,0x9f,0x0d = call	0x1b3e
+# 0x0c,0xa8           = ld.bu	%d15,[%sp]8
+# 0x2c,0xac           = st.b	[%sp]12,%d15
+0x49,0xa5,0x0c,0x0a = lea	%a5, [%sp]12
+0x6d,0xff,0x4c,0xfb = call	-0x968
+0x40,0x6f           = mov.aa	%a15, %a6
+0x94,0xf4           = ld.h	%d4, [%a15]
+0x6d,0x00,0x8a,0x0d = call	0x1b14
+0x94,0xff           = ld.h	%d15, [%a15]
+0xa2,0x2f           = sub	%d15, %d2
+0xb4,0xff           = st.h	[%a15], %d15
+0x8b,0x02,0x00,0x22 = eq	%d2, %d2, 0
+# 0x6c,0x44           = st.w	[%a4]16,%d15
+0x3b,0xc0,0x04,0x50 = mov	%d5, 76
+0x6d,0x00,0xa5,0x21 = call	0x434a
+# 0xf4,0xfc           = st.a	[%a15],%a12
+0x91,0x00,0x00,0x28 = movh.a	%a2, 32768
+0xd9,0x22,0xa8,0xa1 = lea	%a2, [%a2]6824
+# 0xe8,0x22           = st.a	[%a15]8,%a2
+0xd9,0x22,0xb8,0x61 = lea	%a2, [%a2]6584
+# 0xe8,0x32           = st.a	[%a15]12,%a2
+0xd9,0x22,0x22,0x61 = lea	%a2, [%a2]4514
+# 0xe8,0x42           = st.a	[%a15]16,%a2
+0xd9,0x22,0x2c,0x61 = lea	%a2, [%a2]4524
+# 0xe8,0x52           = st.a	[%a15]20,%a2
+0xd9,0x22,0x06,0x71 = lea	%a2, [%a2]4550
+# 0xe8,0x62           = st.a	[%a15]24,%a2
+0xd9,0x22,0x1a,0x71 = lea	%a2, [%a2]4570
+# 0xe8,0x72           = st.a	[%a15]28,%a2
+0xd9,0x22,0x1a,0x11 = lea	%a2, [%a2]4186
+# 0xe8,0x82           = st.a	[%a15]32,%a2
+0xd9,0x22,0x26,0x11 = lea	%a2, [%a2]4198
+# 0xe8,0x92           = st.a	[%a15]36,%a2
+0xd9,0x22,0x1a,0x21 = lea	%a2, [%a2]4250
+# 0xe8,0xa2           = st.a	[%a15]40,%a2
+0xd9,0x22,0x08,0x21 = lea	%a2, [%a2]4232
+# 0xe8,0xb2           = st.a	[%a15]44,%a2
+0xd9,0x22,0x32,0x11 = lea	%a2, [%a2]4210
+# 0xe8,0xc2           = st.a	[%a15]48,%a2
+0xd9,0x22,0x96,0x01 = lea	%a2, [%a2]6166
+# 0xe8,0xd2           = st.a	[%a15]52,%a2
+0xd9,0x22,0x92,0x31 = lea	%a2, [%a2]6354
+# 0xe8,0xe2           = st.a	[%a15]56,%a2
+0xd9,0x22,0x48,0xe1 = lea	%a2, [%a2]6024
+# 0xe8,0xf2           = st.a	[%a15]60,%a2
+0xd9,0x22,0x36,0x61 = lea	%a2, [%a2]4534
+# 0x89,0xf2,0x80,0x19 = st.a	[%a15]64
+0xd9,0x22,0x3e,0x61 = lea	%a2, [%a2]4542
+# 0x89,0xf2,0x84,0x19 = st.a	[%a15]68
+0xd9,0x22,0x96,0x71 = lea	%a2, [%a2]6614
+# 0x89,0xf2,0x88,0x19 = st.a	[%a15]72
+0x40,0x6d           = mov.aa	%a13, %a6
+0x09,0x20,0x94,0x08 = ld.h	%d0, [%a2]20
+0x37,0x00,0x70,0xa0 = extr.u	%d10, %d0, 0, 16
+0x94,0xd0           = ld.h	%d0, [%a13]
+0xdf,0x00,0x31,0x00 = jeq	%d0, 0, 0x62
+0xee,0x1f           = jnz	%d15, 0x3e
+0x94,0xdf           = ld.h	%d15, [%a13]
+0x7f,0xfa,0x1d,0x00 = jge	%d10, %d15, 0x3a
+0x37,0x0a,0x50,0x40 = extr	%d4, %d10, 0, 16
+0x0b,0x89,0x10,0x68 = mov	%e6, %d9, %d8
+0x6d,0x00,0x02,0x0e = call	0x1c04
+0x6d,0xff,0x25,0xfe = call	-0x3b6
+0x01,0xca,0x00,0x56 = addsc.a	%a5, %a12, %d10, 0
+0xa2,0xaf           = sub	%d15, %d10
+0x6d,0x00,0xf4,0x0d = call	0x1be8
+0x6d,0xff,0x16,0xfe = call	-0x3d4
+0x94,0xd4           = ld.h	%d4, [%a13]
+0x6d,0x00,0xe8,0x0d = call	0x1bd0
+0x6d,0xff,0x0a,0xfe = call	-0x3ec
+0xa2,0x8f           = sub	%d15, %d8
+0xb4,0xdf           = st.h	[%a13], %d15
+0x8b,0x08,0x00,0x22 = eq	%d2, %d8, 0
+0xb4,0xa4           = st.h	[%sp], %d4
+0xac,0xa1           = st.h	[%sp]2, %d15
+0x49,0xa6,0x02,0x0a = lea	%a6, [%sp]2
+# 0x09,0x24,0x40,0x09 = ld.d	%e4,[%a2]
+# 0xc8,0x22           = ld.a	%a2,[%a15]8
+0x2d,0x02,0x00,0x00 = calli	%a2
+# 0x89,0xa4,0x98,0x09 = st.a	[%sp]24,%a4
+0x91,0x20,0x00,0xd8 = movh.a	%a13, 32770
+0xd9,0xdd,0xac,0xba = lea	%a13, [%a13]-21780
+0x1d,0x00,0x98,0x00 = j	0x130
+# 0x89,0xa2,0x88,0x09 = st.a	[%sp]8
+0x82,0x0b           = mov	%d11, 0
+0x82,0x0c           = mov	%d12, 0
+# 0xf4,0xad           = st.a	[%sp],%a13
+# 0xf8,0x01           = st.a	[%sp]4,%a15
+0x91,0x20,0x00,0x58 = movh.a	%a5, 32770
+0xd9,0x55,0x98,0xca = lea	%a5, [%a5]-21736
+0x40,0xc4           = mov.aa	%a4, %a12
+0x6d,0xff,0x22,0xf5 = call	-0x15bc
+0x3c,0x6e           = j	0xdc
+0xd9,0xff,0x88,0xda = lea	%a15, [%a15]-21688
+# 0xf8,0x04           = st.a	[%sp]16,%a15
+0xd9,0xff,0xa4,0xda = lea	%a15, [%a15]-21660
+# 0xf8,0x05           = st.a	[%sp]20,%a15
+0xd9,0xff,0xac,0xba = lea	%a15, [%a15]-21780
+0x49,0xa4,0x08,0x0a = lea	%a4, [%sp]8
+0x6d,0xff,0xba,0xfd = call	-0x48c
+0x76,0x28           = jz	%d2, 0x10
+0x82,0x1b           = mov	%d11, 1
+0xd9,0xff,0xa8,0xda = lea	%a15, [%a15]-21656
+0x49,0xa5,0x14,0x0a = lea	%a5, [%sp]20
+0x6d,0xff,0xac,0xfd = call	-0x4a8
+0x82,0x1c           = mov	%d12, 1
+0xd9,0xff,0xb0,0xda = lea	%a15, [%a15]-21648
+0x76,0xb6           = jz	%d11, 0xc
+0xd9,0xff,0x80,0xea = lea	%a15, [%a15]-21632
+0x76,0xc5           = jz	%d12, 0xa
+0xd9,0xff,0x8c,0xea = lea	%a15, [%a15]-21620
+# 0x09,0xa4,0x88,0x09 = ld.a	%a4,[%sp]8
+0xd9,0x55,0x9c,0xea = lea	%a5, [%a5]-21604
+0x6d,0x00,0xcd,0x0c = call	0x199a
+0x7c,0x2a           = jnz.a	%a2, 0x14
+# 0x09,0xae,0x88,0x09 = ld.a	%a14,[%sp]8
+0x6d,0x00,0xae,0x0c = call	0x195c
+0x01,0xe2,0x00,0x26 = addsc.a	%a2, %a14, %d2, 0
+0xf6,0x82           = jnz	%d8, 0x4
+0xb0,0x22           = add.a	%a2, 2
+0x01,0x42,0x20,0x20 = sub.a	%a2, %a2, %a4
+0x80,0x2f           = mov.d	%d15, %a2
+0xac,0xa6           = st.h	[%sp]12, %d15
+0x6d,0xff,0xc9,0xf4 = call	-0x166e
+# 0x09,0xa5,0x88,0x09 = ld.a	%a5,[%sp]8
+0x49,0xa6,0x0c,0x0a = lea	%a6, [%sp]12
+# 0xcc,0xc2           = ld.a	%a15,[%a12]8
+# 0xd4,0xc4           = ld.a	%a4,[%a12]
+0x2d,0x0f,0x00,0x00 = calli	%a15
+# 0xd8,0x02           = ld.a	%a15,[%sp]8
+0x8c,0xa6           = ld.h	%d15, [%sp]12
+# 0xf8,0x02           = st.a	[%sp]8,%a15
+0x76,0x82           = jz	%d8, 0x4
+# 0x09,0xff,0x00,0x08 = ld.b	%d15,[%a15]
+0xee,0x90           = jnz	%d15, -0xe0
+0x6d,0xff,0xa9,0xf4 = call	-0x16ae
+# 0xd8,0x06           = ld.a	%a15,[%sp]24
+# 0x48,0x3f           = ld.w	%d15,[%a15]12
+0xf6,0xa6           = jnz	%d10, 0xc
+0x82,0x1a           = mov	%d10, 1
+0xd9,0xdd,0xb0,0xba = lea	%a13, [%a13]-21776
+0x49,0xff,0x10,0x0a = lea	%a15, [%a15]16
+# 0xf8,0x06           = st.a	[%sp]24,%a15
+0x76,0x92           = jz	%d9, 0x4
+0xdf,0x0f,0x68,0xff = jne	%d15, 0, -0x130
+# 0x89,0xa4,0x84,0x09 = st.a	[%sp]4,%a4
+0x40,0x6c           = mov.aa	%a12, %a6
+# 0xd8,0x01           = ld.a	%a15,[%sp]4
+0x49,0xa6,0x04,0x0a = lea	%a6, [%sp]4
+0x49,0xa7,0x08,0x0a = lea	%a7, [%sp]8
+0x40,0x54           = mov.aa	%a4, %a5
+0x40,0xf5           = mov.aa	%a5, %a15
+0x6d,0xff,0x0c,0xfc = call	-0x7e8
+0x40,0x2d           = mov.aa	%a13, %a2
+0xbd,0x0d,0x22,0x00 = jz.a	%a13, 0x44
+# 0x4c,0xd3           = ld.w	%d15,[%a13]12
+0xee,0x09           = jnz	%d15, 0x12
+0x6d,0xff,0x3f,0xff = call	-0x182
+0x3c,0x15           = j	0x2a
+0xee,0x0c           = jnz	%d15, 0x18
+# 0x09,0xa2,0x88,0x09 = ld.a	%a2,[%sp]8
+# 0xd4,0x2f           = ld.a	%a15,[%a2]
+# 0xf4,0xaf           = st.a	[%sp],%a15
+0xd9,0x55,0xb4,0xba = lea	%a5, [%a5]-21772
+0x6d,0xff,0x6c,0xf4 = call	-0x1728
+0x82,0x15           = mov	%d5, 1
+0x40,0xd4           = mov.aa	%a4, %a13
+0x6d,0xff,0x2a,0xff = call	-0x1ac
+0x3c,0x0a           = j	0x14
+0xd9,0x55,0xb8,0xba = lea	%a5, [%a5]-21768
+0x6d,0xff,0x5d,0xf4 = call	-0x1746
+0x40,0x5f           = mov.aa	%a15, %a5
+# 0x09,0x4f,0x00,0x08 = ld.b	%d15,[%a4]
+0xee,0x17           = jnz	%d15, 0x2e
+0x53,0x49,0x20,0xf0 = mul	%d15, %d9, 4
+0x10,0xf2           = addsc.a	%a2, %a15, %d15, 0
+# 0x09,0x2f,0x04,0x59 = ld.w	%d15,[%a2]324
+0x6e,0x0b           = jz	%d15, 0x16
+# 0x09,0x24,0x84,0x59 = ld.a	%a4,[%a2]324
+0x6d,0x00,0x0e,0x00 = call	0x1c
+0xbf,0x19,0xef,0x7f = jlt	%d9, 1, -0x22
+0x40,0xc6           = mov.aa	%a6, %a12
+0x6d,0x00,0xb0,0x00 = call	0x160
+0x10,0x4f           = addsc.a	%a15, %a4, %d15, 0
+0xa0,0x02           = mov.a	%a2, 0
+0xbf,0x10,0xfa,0xff = jlt.u	%d0, 1, -0xc
+# 0x2c,0x44           = st.b	[%a4]4,%d15
+# 0xec,0x44           = st.a	[%a4]16,%a15
+# 0xec,0x47           = st.a	[%a4]28,%a15
+# 0xec,0x45           = st.a	[%a4]20,%a15
+# 0xec,0x46           = st.a	[%a4]24,%a15
+# 0xec,0x43           = st.a	[%a4]12,%a15
+# 0x89,0x4f,0x20,0x08 = st.b	[%a4]32,%d15
+# 0x2c,0x46           = st.b	[%a4]6,%d15
+# 0x2c,0x45           = st.b	[%a4]5,%d15
+0x3b,0x00,0x16,0x50 = mov	%d5, 352
+0x6d,0x00,0x5f,0x0f = call	0x1ebe
+0x49,0xc2,0x0c,0x0a = lea	%a2, [%a12]12
+0x49,0xf4,0x08,0x5a = lea	%a4, [%a15]328
+0xa0,0x55           = mov.a	%a5, 5
+# 0x44,0x2f           = ld.w	%d15,[%a2+]
+# 0x64,0x4f           = st.w	[%a4+],%d15
+0xfc,0x5e           = loop	%a5, -0x4
+# 0x89,0xff,0x1c,0x58 = st.b	[%a15]348,%d15
+# 0xd4,0xc2           = ld.a	%a2,[%a12]
+# 0xf4,0xf2           = st.a	[%a15],%a2
+# 0x09,0xc0,0x45,0x08 = ld.bu	%d0,[%a12]5
+0x37,0x0f,0x01,0xf0 = insert	%d15, %d15, %d0, 0, 1
+# 0x09,0xc0,0x46,0x08 = ld.bu	%d0,[%a12]6
+0x37,0x0f,0x01,0xf1 = insert	%d15, %d15, %d0, 2, 1
+# 0x09,0xc0,0x44,0x08 = ld.bu	%d0,[%a12]4
+0x37,0x0f,0x81,0xf1 = insert	%d15, %d15, %d0, 3, 1
+# 0x89,0xff,0x00,0x58 = st.b	[%a15]320,%d15
+# 0x89,0xff,0x3f,0x48 = st.b	[%a15]319,%d15
+0x49,0xf2,0x3f,0x2a = lea	%a2, [%a15]191
+0x91,0x00,0x00,0x47 = movh.a	%a4, 28672
+0xd9,0x44,0x4c,0xb0 = lea	%a4, [%a4]1740
+0x3b,0x00,0x50,0x50 = mov	%d5, 1280
+0x6d,0x00,0x28,0x0f = call	0x1e50
+0x91,0x00,0x00,0x27 = movh.a	%a2, 28672
+0xd9,0x22,0x4c,0xb0 = lea	%a2, [%a2]1740
+0x10,0xc4           = addsc.a	%a4, %a12, %d15, 0
+# 0x89,0x24,0x84,0x59 = st.a	[%a2]324,%a4
+0xbf,0x10,0xf5,0x7f = jlt	%d0, 1, -0x16
+0x10,0x24           = addsc.a	%a4, %a2, %d15, 0
+0x9a,0xf0           = add	%d15, %d0, -1
+0x53,0x4f,0x20,0xf0 = mul	%d15, %d15, 4
+0x10,0x25           = addsc.a	%a5, %a2, %d15, 0
+# 0xd4,0x55           = ld.a	%a5,[%a5]
+0x49,0x55,0x00,0x2a = lea	%a5, [%a5]128
+0xda,0x0a           = mov	%d15, 10
+0x3f,0xf0,0xf3,0x7f = jlt	%d0, %d15, -0x1a
+0x89,0xff,0xba,0x08 = st.h	[%a15]58, %d15
+# 0xd4,0x24           = ld.a	%a4,[%a2]
+0xd9,0x55,0x88,0xca = lea	%a5, [%a5]-21752
+0x6d,0xff,0xfa,0xe1 = call	-0x3c0c
+0x2e,0x0f           = jz.t	%d15, 0, 0x1e
+0x6d,0xff,0x81,0xf7 = call	-0x10fe
+0xd9,0x55,0x90,0xca = lea	%a5, [%a5]-21744
+0x6d,0xff,0x7a,0xf7 = call	-0x110c
+0x49,0xf5,0x3e,0x0a = lea	%a5, [%a15]62
+0x49,0xfc,0x3f,0x2a = lea	%a12, [%a15]191
+0x49,0xfd,0x08,0x0a = lea	%a13, [%a15]8
+0xae,0x13           = jnz.t	%d15, 1, 0x6
+0x1d,0x00,0x6e,0x01 = j	0x2dc
+# 0x09,0xff,0x18,0x59 = ld.w	%d15,[%a15]344
+# 0x09,0xff,0x5c,0x58 = ld.bu	%d15,[%a15]348
+# 0x09,0xf2,0x8c,0x59 = ld.a	%a2,[%a15]332
+# 0x09,0xf4,0x98,0x59 = ld.a	%a4,[%a15]344
+0x1d,0x00,0x60,0x01 = j	0x2c0
+0x8b,0x08,0x08,0xf1 = rsub	%d15, %d8, 128
+0xb0,0x05           = add.a	%a5, 0
+0xd2,0x04           = mov	%e4, 0
+# 0x09,0x27,0x8c,0x09 = ld.a	%a7,[%a2]12
+0x2d,0x07,0x00,0x00 = calli	%a7
+0x8c,0xa2           = ld.h	%d15, [%sp]4
+0x42,0xf8           = add	%d8, %d15
+0x1d,0x00,0x4a,0x01 = j	0x294
+0x01,0xf9,0x00,0x26 = addsc.a	%a2, %a15, %d9, 0
+# 0x09,0x20,0x3e,0x08 = ld.b	%d0,[%a2]62
+0x5f,0x0f,0x6e,0x00 = jeq	%d15, %d0, 0xdc
+0x5f,0x0f,0x2a,0x00 = jeq	%d15, %d0, 0x54
+0xda,0x0d           = mov	%d15, 13
+0x5f,0x0f,0x25,0x00 = jeq	%d15, %d0, 0x4a
+0xda,0x1b           = mov	%d15, 27
+0x5f,0x0f,0xc4,0x00 = jeq	%d15, %d0, 0x188
+0xda,0x31           = mov	%d15, 49
+0x5f,0x0f,0xdf,0x00 = jeq	%d15, %d0, 0x1be
+0xda,0x32           = mov	%d15, 50
+0x5f,0x0f,0xdc,0x00 = jeq	%d15, %d0, 0x1b8
+0xda,0x33           = mov	%d15, 51
+0x5f,0x0f,0xd9,0x00 = jeq	%d15, %d0, 0x1b2
+0xda,0x34           = mov	%d15, 52
+0x5f,0x0f,0xd6,0x00 = jeq	%d15, %d0, 0x1ac
+0xda,0x41           = mov	%d15, 65
+0x5f,0x0f,0xc2,0x00 = jeq	%d15, %d0, 0x184
+0xda,0x42           = mov	%d15, 66
+0x5f,0x0f,0xbf,0x00 = jeq	%d15, %d0, 0x17e
+0xda,0x43           = mov	%d15, 67
+0x5f,0x0f,0xbc,0x00 = jeq	%d15, %d0, 0x178
+0xda,0x44           = mov	%d15, 68
+0x5f,0x0f,0xb9,0x00 = jeq	%d15, %d0, 0x172
+0xda,0x5b           = mov	%d15, 91
+0x5f,0x0f,0xad,0x00 = jeq	%d15, %d0, 0x15a
+0xda,0x7e           = mov	%d15, 126
+0x5f,0x0f,0xd3,0x00 = jeq	%d15, %d0, 0x1a6
+0x1d,0x00,0xe1,0x00 = j	0x1c2
+0x09,0xf0,0xb6,0x08 = ld.h	%d0, [%a15]54
+0xda,0x80           = mov	%d15, 128
+0x7f,0xf0,0x27,0x00 = jge	%d0, %d15, 0x4e
+0x09,0xff,0xb6,0x08 = ld.h	%d15, [%a15]54
+0x10,0xc2           = addsc.a	%a2, %a12, %d15, 0
+# 0x09,0xff,0x78,0x08 = ld.bu	%d15,[%a15]56
+0x6e,0x1a           = jz	%d15, 0x34
+0x3b,0x90,0x00,0xb0 = mov	%d11, 9
+0x3c,0x0f           = j	0x1e
+0x53,0x4b,0x20,0xf0 = mul	%d15, %d11, 4
+0x10,0xd2           = addsc.a	%a2, %a13, %d15, 0
+0x9a,0xfb           = add	%d15, %d11, -1
+# 0xd4,0x25           = ld.a	%a5,[%a2]
+0x3b,0x00,0x08,0x40 = mov	%d4, 128
+0x6d,0x00,0x36,0x0e = call	0x1c6c
+0xc2,0xfb           = add	%d11, -1
+0xff,0x1b,0xf2,0x7f = jge	%d11, 1, -0x1c
+# 0xd4,0xd4           = ld.a	%a4,[%a13]
+0x6d,0x00,0x2d,0x0e = call	0x1c5a
+0x6d,0xff,0x03,0xfe = call	-0x3fa
+0x2e,0x08           = jz.t	%d15, 0, 0x10
+0x6d,0xff,0x47,0xf6 = call	-0x1372
+0x89,0xff,0xb6,0x08 = st.h	[%a15]54, %d15
+0x89,0xff,0xb4,0x08 = st.h	[%a15]52, %d15
+# 0x89,0xff,0x38,0x08 = st.b	[%a15]56,%d15
+0x1d,0x00,0xa0,0x00 = j	0x140
+0x09,0xff,0xb4,0x08 = ld.h	%d15, [%a15]52
+0xbf,0x1f,0x5c,0x00 = jlt	%d15, 1, 0xb8
+0x6f,0x3f,0x37,0x00 = jz.t	%d15, 3, 0x6e
+0xd9,0x55,0xa0,0xca = lea	%a5, [%a5]-21728
+0x6d,0xff,0x2b,0xf6 = call	-0x13aa
+# 0x09,0x20,0x3f,0x28 = ld.b	%d0,[%a2]191
+# 0x74,0xa0           = st.w	[%sp],%d0
+0xd9,0x55,0xa4,0xca = lea	%a5, [%a5]-21724
+0x6d,0xff,0x1d,0xf6 = call	-0x13c6
+0x37,0x0f,0x50,0xf0 = extr	%d15, %d15, 0, 16
+0x3f,0x0f,0xf0,0x7f = jlt	%d15, %d0, -0x20
+0xd9,0x55,0xa8,0xca = lea	%a5, [%a5]-21720
+0x6d,0xff,0x0f,0xf6 = call	-0x13e2
+0x6d,0xff,0x06,0xf6 = call	-0x13f4
+0xc2,0x1b           = add	%d11, 1
+0x09,0xf0,0xb4,0x08 = ld.h	%d0, [%a15]52
+0x3f,0xfb,0xf2,0x7f = jlt	%d11, %d15, -0x1c
+0x49,0x24,0x3e,0x2a = lea	%a4, [%a2]190
+0x10,0xc5           = addsc.a	%a5, %a12, %d15, 0
+0x09,0xf4,0xb6,0x08 = ld.h	%d4, [%a15]54
+0xa2,0xf4           = sub	%d4, %d15
+0x6d,0x00,0xc7,0x0d = call	0x1b8e
+# 0x89,0x2f,0x3e,0x28 = st.b	[%a2]190,%d15
+0x3c,0x3c           = j	0x78
+# 0x09,0xff,0x7f,0x48 = ld.bu	%d15,[%a15]319
+0x5e,0x15           = jne	%d15, 1, 0xa
+0x3c,0x33           = j	0x66
+0x5e,0x2d           = jne	%d15, 2, 0x1a
+# 0x09,0x24,0x3e,0x08 = ld.b	%d4,[%a2]62
+0x6d,0xff,0xe1,0xfa = call	-0xa3e
+0x3c,0x22           = j	0x44
+0x5e,0x2b           = jne	%d15, 2, 0x16
+# 0x09,0x2f,0x3e,0x08 = ld.b	%d15,[%a2]62
+0x5e,0x3c           = jne	%d15, 3, 0x18
+# 0x09,0xf4,0x00,0x58 = ld.b	%d4,[%a15]320
+0x3b,0xe0,0x07,0x50 = mov	%d5, 126
+0x6d,0xff,0xc2,0xfa = call	-0xa7c
+0xdf,0x0a,0x33,0x00 = jeq	%d10, 0, 0x66
+0xda,0x7f           = mov	%d15, 127
+0x7f,0xf0,0x28,0x00 = jge	%d0, %d15, 0x50
+0x01,0xf9,0x00,0x46 = addsc.a	%a4, %a15, %d9, 0
+# 0x09,0x4f,0x3e,0x08 = ld.b	%d15,[%a4]62
+0x0b,0x0f,0xa0,0xf1 = max	%d15, %d15, %d0
+# 0x89,0xff,0x3c,0x08 = st.b	[%a15]60,%d15
+0x49,0xf5,0x3c,0x0a = lea	%a5, [%a15]60
+0x6d,0xff,0x6c,0xf5 = call	-0x1528
+0x37,0x09,0x50,0x90 = extr	%d9, %d9, 0, 16
+0x3f,0x89,0xb8,0x7e = jlt	%d9, %d8, -0x290
+0xbd,0x04,0x11,0x00 = jz.a	%a4, 0x22
+0xb0,0x14           = add.a	%a4, 1
+# 0x09,0x40,0x00,0x08 = ld.b	%d0,[%a4]
+0xda,0x20           = mov	%d15, 32
+0x5f,0x0f,0xf9,0x7f = jeq	%d15, %d0, -0xe
+0xda,0x09           = mov	%d15, 9
+0x5f,0x0f,0xf4,0x7f = jeq	%d15, %d0, -0x18
+0x49,0xaa,0x00,0x8a = lea	%sp, [%sp]-512
+# 0xd4,0xfd           = ld.a	%a13,[%a15]
+0x3b,0x00,0x10,0x40 = mov	%d4, 256
+0x6d,0x00,0x1a,0x00 = call	0x34
+0xdf,0x02,0x12,0x00 = jeq	%d2, 0, 0x24
+0x49,0xa5,0x00,0x4a = lea	%a5, [%sp]256
+0x6d,0x00,0x11,0x00 = call	0x22
+0x76,0x29           = jz	%d2, 0x12
+0x49,0xa4,0x00,0x4a = lea	%a4, [%sp]256
+0x6d,0xff,0x8b,0xe1 = call	-0x3cea
+0xf6,0x22           = jnz	%d2, 0x4
+# 0xf4,0xfd           = st.a	[%a15],%a13
+# 0xf4,0xce           = st.a	[%a12],%a14
+0x6d,0x00,0xd0,0x02 = call	0x5a0
+0x7c,0x23           = jnz.a	%a2, 0x6
+0x3c,0x48           = j	0x90
+# 0x09,0x20,0x00,0x08 = ld.b	%d0,[%a2]
+0xda,0x22           = mov	%d15, 34
+0xfe,0x0c           = jne	%d15, %d0, 0x38
+0xb0,0x12           = add.a	%a2, 1
+0x7f,0x89,0x08,0x00 = jge	%d9, %d8, 0x10
+# 0x34,0x40           = st.b	[%a4],%d0
+# 0x09,0x2f,0x00,0x08 = ld.b	%d15,[%a2]
+0x5f,0x0f,0xf1,0xff = jne	%d15, %d0, -0x1e
+0x3e,0x03           = jeq	%d15, %d0, 0x6
+0x3c,0x2b           = j	0x56
+0x3c,0x24           = j	0x48
+# 0x34,0x4f           = st.b	[%a4],%d15
+0x6e,0x0a           = jz	%d15, 0x14
+0x3e,0x06           = jeq	%d15, %d0, 0xc
+0x5f,0x0f,0xed,0xff = jne	%d15, %d0, -0x26
+0x8e,0x87           = jlez	%d8, 0xe
+0xc2,0xf8           = add	%d8, -1
+0x0b,0x89,0x80,0xf1 = min	%d15, %d9, %d8
+0x6d,0x00,0x87,0x02 = call	0x50e
+# 0xf4,0xc2           = st.a	[%a12],%a2
+0x49,0xaa,0x30,0xba = lea	%sp, [%sp]-272
+# 0x89,0xa6,0x88,0x49 = st.a	[%sp]264,%a6
+0x40,0x7c           = mov.aa	%a12, %a7
+0x40,0x4d           = mov.aa	%a13, %a4
+0xa0,0x0e           = mov.a	%a14, 0
+0x6e,0x04           = jz	%d15, 0x8
+# 0x4c,0x43           = ld.w	%d15,[%a4]12
+0xee,0x02           = jnz	%d15, 0x4
+# 0x74,0xc0           = st.w	[%a12],%d0
+0x3c,0x2e           = j	0x5c
+# 0xd4,0xd2           = ld.a	%a2,[%a13]
+0x02,0x98           = mov	%d8, %d9
+0x49,0xa4,0x04,0x0a = lea	%a4, [%sp]4
+0x6d,0x00,0x50,0x01 = call	0x2a0
+0xdf,0x02,0xf9,0xff = jne	%d2, 0, -0xe
+# 0x54,0xc0           = ld.w	%d0,[%a12]
+0x7f,0x80,0x18,0x80 = jge.u	%d0, %d8, 0x30
+0x49,0xa5,0x08,0x0a = lea	%a5, [%sp]8
+0x6d,0x00,0x69,0x01 = call	0x2d2
+0xf6,0x2e           = jnz	%d2, 0x1c
+0xf6,0xa5           = jnz	%d10, 0xa
+0x02,0x89           = mov	%d9, %d8
+# 0x74,0xc8           = st.w	[%a12],%d8
+# 0x09,0xa4,0x84,0x09 = ld.a	%a4,[%sp]4
+# 0x09,0xa2,0x88,0x49 = ld.a	%a2,[%sp]264
+# 0xf4,0x24           = st.a	[%a2],%a4
+0x40,0xde           = mov.aa	%a14, %a13
+0xf6,0xa3           = jnz	%d10, 0x6
+0x76,0xb2           = jz	%d11, 0x4
+0x49,0xdd,0x10,0x0a = lea	%a13, [%a13]16
+0xc2,0x1a           = add	%d10, 1
+# 0x54,0xdf           = ld.w	%d15,[%a13]
+0xee,0xd2           = jnz	%d15, -0x5c
+0x40,0xe2           = mov.aa	%a2, %a14
+# 0x89,0xa5,0x84,0x09 = st.a	[%sp]4,%a5
+0x40,0x7d           = mov.aa	%a13, %a7
+0x3c,0x20           = j	0x40
+0x6e,0x19           = jz	%d15, 0x32
+0x49,0xa7,0x00,0x0a = lea	%a7, [%sp]0
+# 0x09,0xa5,0x84,0x09 = ld.a	%a5,[%sp]4
+0x6d,0xff,0xa1,0xff = call	-0xbe
+0xbc,0x2c           = jz.a	%a2, 0x18
+0x7f,0xf8,0x0a,0x80 = jge.u	%d8, %d15, 0x14
+# 0x54,0xa8           = ld.w	%d8,[%sp]
+0x40,0x2e           = mov.aa	%a14, %a2
+# 0x09,0x22,0x84,0x59 = ld.a	%a2,[%a2]324
+# 0xf4,0xd2           = st.a	[%a13],%a2
+0xbf,0x19,0xe1,0x7f = jlt	%d9, 1, -0x3e
+# 0x89,0xa2,0x84,0x09 = st.a	[%sp]4,%a2
+0xbd,0x02,0x30,0x00 = jz.a	%a2, 0x60
+# 0x4c,0x23           = ld.w	%d15,[%a2]12
+# 0xd4,0xf6           = ld.a	%a6,[%a15]
+0x6d,0x00,0xd8,0x02 = call	0x5b0
+# 0x09,0x25,0x88,0x09 = ld.a	%a5,[%a2]8
+0x2e,0x26           = jz.t	%d15, 2, 0xc
+0x3b,0xf0,0x0f,0x40 = mov	%d4, 255
+0x6d,0x00,0xe2,0x03 = call	0x7c4
+0x2e,0x27           = jz.t	%d15, 2, 0xe
+0x3b,0x10,0x08,0x40 = mov	%d4, 129
+0x6d,0x00,0xda,0x03 = call	0x7b4
+0x2e,0x4a           = jz.t	%d15, 4, 0x14
+# 0xf4,0xac           = st.a	[%sp],%a12
+0xd9,0x55,0xac,0xca = lea	%a5, [%a5]-21716
+0x6d,0xff,0x13,0xf8 = call	-0xfda
+# 0x09,0xcf,0x00,0x08 = ld.b	%d15,[%a12]
+0x6e,0x14           = jz	%d15, 0x28
+0x6d,0x00,0xc3,0x03 = call	0x786
+0xd9,0x55,0x8c,0xda = lea	%a5, [%a5]-21684
+0x6d,0xff,0xfc,0xf7 = call	-0x1008
+0x01,0x2f,0x10,0xf4 = ne.a	%d15, %a15, %a2
+0x1d,0x00,0x18,0x02 = j	0x430
+0x49,0xf2,0x30,0x0a = lea	%a2, [%a15]48
+# 0xd4,0x2c           = ld.a	%a12,[%a2]
+0x3e,0x8c           = jeq	%d15, %d8, 0x18
+0x5f,0x8f,0x66,0x00 = jeq	%d15, %d8, 0xcc
+0x5f,0x8f,0xef,0x00 = jeq	%d15, %d8, 0x1de
+0x5f,0x8f,0x07,0x01 = jeq	%d15, %d8, 0x20e
+0x1d,0x00,0x17,0x01 = j	0x22e
+0x09,0xff,0xba,0x08 = ld.h	%d15, [%a15]58
+0x5e,0xf5           = jne	%d15, -1, 0xa
+0x3c,0x0b           = j	0x16
+0x09,0xf0,0xba,0x08 = ld.h	%d0, [%a15]58
+0x7f,0xf0,0x07,0x00 = jge	%d0, %d15, 0xe
+0x6d,0x00,0x85,0x12 = call	0x250a
+0x6f,0x3f,0x30,0x00 = jz.t	%d15, 3, 0x60
+0x6d,0xff,0xa0,0xfa = call	-0xac0
+0x3f,0x0f,0xf6,0x7f = jlt	%d15, %d0, -0x14
+0x6d,0xff,0x92,0xfa = call	-0xadc
+0x6d,0xff,0x84,0xfa = call	-0xaf8
+0x6d,0xff,0x7b,0xfa = call	-0xb0a
+0x6d,0x00,0x49,0x12 = call	0x2492
+0x89,0xf2,0xb4,0x08 = st.h	[%a15]52, %d2
+0x1d,0x00,0xbc,0x00 = j	0x178
+0x1e,0xf4           = jeq	%d15, -1, 0x8
+0x6f,0x3f,0x2c,0x00 = jz.t	%d15, 3, 0x58
+0x6d,0xff,0x5b,0xfa = call	-0xb4a
+0x6d,0xff,0x4d,0xfa = call	-0xb66
+0x6d,0xff,0x3f,0xfa = call	-0xb82
+0x3c,0x4c           = j	0x98
+0x6d,0x00,0xf8,0x11 = call	0x23f0
+0x6d,0xff,0x13,0xfa = call	-0xbda
+0x6d,0xff,0x05,0xfa = call	-0xbf6
+0x6d,0xff,0xf7,0xf9 = call	-0xc12
+0x6d,0xff,0xee,0xf9 = call	-0xc24
+0x6d,0x00,0xbc,0x11 = call	0x2378
+0x3c,0x2f           = j	0x5e
+0x7f,0x0f,0x16,0x00 = jge	%d15, %d0, 0x2c
+0x2e,0x3e           = jz.t	%d15, 3, 0x1c
+0x6d,0xff,0xcc,0xf9 = call	-0xc68
+0x8e,0xff           = jlez	%d15, 0x1e
+0x2e,0x38           = jz.t	%d15, 3, 0x10
+0x6d,0xff,0xba,0xf9 = call	-0xc8c
+0x5f,0x9f,0xef,0x80 = jne	%d15, %d9, 0x1de
+0x5f,0x8f,0x21,0x00 = jeq	%d15, %d8, 0x42
+0x5f,0x8f,0x78,0x00 = jeq	%d15, %d8, 0xf0
+0x5f,0x8f,0xc7,0x00 = jeq	%d15, %d8, 0x18e
+0xbf,0x1f,0x13,0x00 = jlt	%d15, 1, 0x26
+0x6d,0xff,0x96,0xf9 = call	-0xcd4
+0x1d,0x00,0xcb,0x00 = j	0x196
+0x7f,0x0f,0x55,0x00 = jge	%d15, %d0, 0xaa
+0x7f,0xf0,0x50,0x00 = jge	%d0, %d15, 0xa0
+0x6e,0x2d           = jz	%d15, 0x5a
+0x6d,0xff,0x76,0xf9 = call	-0xd14
+0x6d,0xff,0x68,0xf9 = call	-0xd30
+0x3f,0x0f,0xf2,0x7f = jlt	%d15, %d0, -0x1c
+0x6d,0xff,0x5a,0xf9 = call	-0xd4c
+0x3f,0xf8,0xf2,0x7f = jlt	%d8, %d15, -0x1c
+0x01,0xc0,0x00,0x26 = addsc.a	%a2, %a12, %d0, 0
+0x3c,0x70           = j	0xe0
+0x7f,0x0f,0x4d,0x00 = jge	%d15, %d0, 0x9a
+0x6f,0x3f,0x2f,0x00 = jz.t	%d15, 3, 0x5e
+0x09,0xf8,0xb4,0x08 = ld.h	%d8, [%a15]52
+0x9a,0x18           = add	%d15, %d8, 1
+0x6d,0xff,0x1a,0xf9 = call	-0xdcc
+0x3f,0xf8,0xf0,0x7f = jlt	%d8, %d15, -0x20
+0x6d,0xff,0x0d,0xf9 = call	-0xde6
+0x6d,0xff,0x04,0xf9 = call	-0xdf8
+0x3f,0xf8,0xf3,0x7f = jlt	%d8, %d15, -0x1a
+0x49,0x25,0x01,0x0a = lea	%a5, [%a2]1
+0x92,0xf4           = add	%d4, %d15, -1
+0x6d,0x00,0xc5,0x10 = call	0x218a
+# 0x89,0x2f,0x3f,0xf8 = st.b	[%a2]-1,%d15
+0x3c,0x1e           = j	0x3c
+0x6d,0xff,0xd0,0xf8 = call	-0xe60
+0x3f,0x0f,0xe8,0x7f = jlt	%d15, %d0, -0x30
+0x49,0xaa,0x38,0xba = lea	%sp, [%sp]-264
+0xee,0x1d           = jnz	%d15, 0x3a
+0x49,0xa6,0x08,0x4a = lea	%a6, [%sp]264
+0x6d,0x00,0x3b,0x18 = call	0x3076
+0x6d,0x00,0xc4,0x17 = call	0x2f88
+0x89,0xa2,0x80,0x48 = st.h	[%sp]256, %d2
+0x49,0xa6,0x00,0x4a = lea	%a6, [%sp]256
+0x8f,0x24,0x00,0xf0 = sh	%d15, %d4, 2
+# 0x54,0x40           = ld.w	%d0,[%a4]
+0x8f,0x00,0x01,0x00 = sh	%d0, %d0, 16
+0x06,0x24           = sh	%d4, 2
+0x8b,0x5f,0x20,0xf3 = min.u	%d15, %d15, 5
+0x6d,0xff,0xac,0xff = call	-0xa8
+0x6d,0x00,0x8f,0x00 = call	0x11e
+0x6d,0xff,0x7b,0xff = call	-0x10a
+0xb7,0x0f,0x81,0xf1 = insert	%d15, %d15, 0, 3, 1
+0x6d,0x00,0x5d,0x00 = call	0xba
+0x6d,0xff,0xb8,0xff = call	-0x90
+0x6d,0x00,0x96,0x00 = call	0x12c
+0x02,0x4f           = mov	%d15, %d4
+0x6d,0xff,0x86,0xff = call	-0xf4
+# 0x39,0xf0,0x2c,0xa6 = ld.bu	%d0,[%a15]25260
+0xb7,0x00,0x81,0x01 = insert	%d0, %d0, 0, 3, 1
+# 0xe9,0xf0,0x2c,0xa6 = st.b	[%a15]25260
+0x6d,0x00,0x63,0x00 = call	0xc6
+0x91,0x20,0x00,0x30 = movh.a	%a3, 2
+0x30,0x43           = add.a	%a3, %a4
+0x49,0x33,0x08,0x8a = lea	%a3, [%a3]-504
+# 0x54,0x3f           = ld.w	%d15,[%a3]
+0x06,0xf4           = sh	%d4, -1
+0x37,0x4f,0x9f,0xf0 = insert	%d15, %d15, %d4, 1, 31
+# 0x74,0x3f           = st.w	[%a3],%d15
+0x49,0x33,0x14,0x8a = lea	%a3, [%a3]-492
+0xef,0x8f,0x0a,0x00 = jz.t	%d15, 24, 0x14
+0xb7,0x0f,0x01,0xfc = insert	%d15, %d15, 0, 24, 1
+0xbb,0x00,0xc2,0x0b = mov.u	%d0, 48160
+0x9b,0xe0,0xcb,0x04 = addih	%d0, %d0, 19646
+# 0x39,0xff,0x1b,0x06 = ld.bu	%d15,[%a15]24603
+0xbb,0x00,0x68,0x19 = mov.u	%d1, 38528
+0x9b,0x81,0xb9,0x14 = addih	%d1, %d1, 19352
+0xbb,0x00,0xc2,0x1b = mov.u	%d1, 48160
+0x9b,0xe1,0xcb,0x14 = addih	%d1, %d1, 19646
+0x6e,0x1d           = jz	%d15, 0x3a
+# 0x39,0xff,0x19,0x06 = ld.bu	%d15,[%a15]24601
+0x37,0x0f,0xe7,0xf0 = extr.u	%d15, %d15, 1, 7
+0x4b,0xf1,0x41,0x10 = mul.f	%d1, %d1, %d15
+# 0x39,0xff,0x1c,0x06 = ld.bu	%d15,[%a15]24604
+0x4b,0x00,0x61,0xf1 = utof	%d15, %d0
+0x4b,0xf1,0x51,0x00 = div.f	%d0, %d1, %d15
+# 0x39,0xff,0x30,0x06 = ld.bu	%d15,[%a15]24624
+0x4b,0xf0,0x51,0x20 = div.f	%d2, %d0, %d15
+0x6d,0x00,0x14,0x01 = call	0x228
+0x6d,0x00,0x71,0x0a = call	0x14e2
+0x91,0x00,0x00,0x10 = movh.a	%a1, 0
+0xd9,0x11,0x00,0x00 = lea	%a1, [%a1]0
+0x3b,0x00,0x98,0xf0 = mov	%d15, 2432
+# 0xcd,0x4f,0xe0,0x0f = mtcr	$psw,%d15
+# 0x19,0xff,0x10,0x16 = ld.w	%d15,[%a15]24656
+0x7b,0xd0,0x38,0x01 = movh	%d0, 5005
+0x8f,0xbf,0x0f,0x01 = and	%d0, %d15, 251
+0xbf,0x10,0x13,0x80 = jlt.u	%d0, 1, 0x26
+0x16,0xfb           = and	%d15, 251
+# 0x19,0xf0,0x18,0x16 = ld.w	%d0,[%a15]24664
+0x0f,0x0f,0xb0,0xf1 = clz	%d15, %d15
+0x8b,0xff,0x01,0xf1 = rsub	%d15, %d15, 31
+0x06,0x1f           = sh	%d15, 1
+0x57,0x00,0x62,0xff = extr.u	%d15, %d0, %d15, 2
+0x5e,0x23           = jne	%d15, 2, 0x6
+0xef,0x4f,0x04,0x00 = jz.t	%d15, 20, 0x8
+0x91,0x10,0x88,0xff = movh.a	%a15, 63617
+# 0x19,0xff,0x00,0x0d = ld.w	%d15,[%a15]-12288
+0x37,0x0f,0xe2,0xf0 = extr.u	%d15, %d15, 1, 2
+0x1e,0x17           = jeq	%d15, 1, 0xe
+0xd9,0xff,0xcc,0xaa = lea	%a15, [%a15]-20852
+0xdc,0x0f           = ji	%a15
+0xd9,0xff,0xf0,0xaa = lea	%a15, [%a15]-20816
+0x91,0x00,0x00,0xf8 = movh.a	%a15, 32768
+0xd9,0xff,0xdc,0xa2 = lea	%a15, [%a15]11932
+0x2d,0x0f,0x20,0x00 = jli	%a15
+0xd9,0xff,0xee,0xe2 = lea	%a15, [%a15]12206
+0xd9,0xff,0xf4,0xca = lea	%a15, [%a15]-20684
+0x91,0x40,0x00,0xa7 = movh.a	%sp, 28676
+0xd9,0xaa,0x40,0x89 = lea	%sp, [%sp]-27136
+0x91,0x40,0x00,0xf7 = movh.a	%a15, 28676
+0xd9,0xff,0xc0,0x09 = lea	%a15, [%a15]-25600
+0x91,0x40,0x00,0x27 = movh.a	%a2, 28676
+0xd9,0x22,0xc0,0x0b = lea	%a2, [%a2]-17408
+0x80,0x20           = mov.d	%d0, %a2
+0x80,0xff           = mov.d	%d15, %a15
+0xda,0x40           = mov	%d15, 64
+0x4b,0xf0,0x11,0x42 = div.u	%e4, %d0, %d15
+0x8f,0x4f,0x1f,0x10 = sh	%d1, %d15, -12
+0xbb,0xf0,0xff,0x2f = mov.u	%d2, 65535
+0x06,0x62           = sh	%d2, 6
+0x26,0x2f           = and	%d15, %d2
+0x06,0xaf           = sh	%d15, -6
+0xa6,0xf1           = or	%d1, %d15
+0xf6,0x06           = jnz	%d0, 0xc
+# 0xcd,0x81,0xe3,0x0f = mtcr	$fcx,%d1
+# 0x74,0xf1           = st.w	[%a15],%d1
+0x9a,0xd4           = add	%d15, %d4, -3
+0x7e,0x05           = jne	%d15, %d0, 0xa
+# 0xcd,0xc1,0xe3,0x0f = mtcr	$lcx,%d1
+0x49,0x44,0x00,0x1a = lea	%a4, [%a4]64
+0x3f,0x40,0xe3,0xff = jlt.u	%d0, %d4, -0x3a
+0xd9,0xff,0xf8,0xea = lea	%a15, [%a15]-20552
+0xd9,0xff,0x10,0x0b = lea	%a15, [%a15]-20464
+0x8f,0xff,0x83,0x41 = xor	%d4, %d15, 63
+0x8f,0xff,0x83,0xf1 = xor	%d15, %d15, 63
+0xd9,0x44,0x0c,0x96 = lea	%a4, [%a4]25164
+0x6d,0xff,0xf4,0x4b = call	-0x16818
+0x6d,0xff,0x09,0x4c = call	-0x167ee
+0x91,0x20,0x00,0x48 = movh.a	%a4, 32770
+0xd9,0x44,0xa8,0x9a = lea	%a4, [%a4]-21912
+0x6d,0xff,0xf2,0x38 = call	-0x18e1c
+0xdf,0x12,0x03,0x80 = jne	%d2, 1, 0x6
+0xd9,0xff,0x1c,0x0b = lea	%a15, [%a15]-20452
+0x91,0x20,0x88,0x4f = movh.a	%a4, 63618
+0x91,0x00,0x03,0xfa = movh.a	%a15, 41008
+0xd9,0xff,0x00,0x80 = lea	%a15, [%a15]512
+0x80,0xf4           = mov.d	%d4, %a15
+0x6d,0xff,0x16,0x4c = call	-0x167d4
+0xd9,0xff,0xe4,0x2a = lea	%a15, [%a15]-21340
+0x8f,0xff,0x83,0x81 = xor	%d8, %d15, 63
+0x8f,0xff,0x83,0x91 = xor	%d9, %d15, 63
+0x8f,0x28,0x00,0xf0 = sh	%d15, %d8, 2
+0xb7,0x0f,0x81,0xf0 = insert	%d15, %d15, 0, 1, 1
+# 0xcd,0xcf,0x20,0x09 = mtcr	$pcon0,%d15
+# 0xcd,0x0f,0x04,0x09 = mtcr	$dcon0,%d15
+0x91,0x00,0x00,0x00 = movh.a	%a0, 0
+0xd9,0x00,0x00,0x00 = lea	%a0, [%a0]0
+0x91,0x00,0x00,0x80 = movh.a	%a8, 0
+0xd9,0x88,0x00,0x00 = lea	%a8, [%a8]0
+0x91,0x00,0x00,0x90 = movh.a	%a9, 0
+0xd9,0x99,0x00,0x00 = lea	%a9, [%a9]0
+0xd9,0xff,0x00,0x40 = lea	%a15, [%a15]256
+# 0xcd,0x4f,0xe2,0x0f = mtcr	$btv,%d15
+0x91,0x00,0x03,0xf8 = movh.a	%a15, 32816
+0xd9,0xff,0x00,0x0e = lea	%a15, [%a15]-8192
+# 0xcd,0x0f,0xe2,0x0f = mtcr	$biv,%d15
+0xd9,0xff,0x80,0xc9 = lea	%a15, [%a15]-25856
+# 0xcd,0x8f,0xe2,0x0f = mtcr	$isp,%d15
+0x6d,0xff,0x67,0x4c = call	-0x16732
+0x02,0x94           = mov	%d4, %d9
+0x6d,0xff,0x7f,0x4c = call	-0x16702
+0x91,0x00,0x00,0xf0 = movh.a	%a15, 0
+0xd9,0xff,0x00,0x00 = lea	%a15, [%a15]0
+0xbc,0xf3           = jz.a	%a15, 0x6
+0xed,0x00,0x00,0x00 = calla	0
+0x6d,0xff,0x80,0x4c = call	-0x16700
+0x6d,0xff,0x9e,0x4c = call	-0x166c4
+0x6d,0xff,0x7b,0x4c = call	-0x1670a
+0xd9,0xff,0x3c,0x0b = lea	%a15, [%a15]-20420
+0x3c,0x00           = j	0x0
+# 0x85,0xf8,0x10,0x01 = ld.w	%d8,f0001010
+0xd9,0xff,0x18,0x96 = lea	%a15, [%a15]25176
+0x91,0x40,0x00,0xa6 = movh.a	%sp, 24580
+0x8f,0x21,0x00,0xf0 = sh	%d15, %d1, 2
+0x91,0x00,0x06,0xf8 = movh.a	%a15, 32864
+0xd9,0xff,0x00,0x0c = lea	%a15, [%a15]-16384
+0x91,0x40,0x00,0xf6 = movh.a	%a15, 24580
+0x06,0x21           = sh	%d1, 2
+0x91,0x40,0x00,0x26 = movh.a	%a2, 24580
+0x6d,0xe8,0xc9,0x21 = call	-0x2fbc6e
+0xbb,0x70,0x71,0xfb = mov.u	%d15, 46871
+0x9b,0x1f,0x8d,0xf3 = addih	%d15, %d15, 14545
+0x4b,0xf2,0x41,0xf0 = mul.f	%d15, %d2, %d15
+0x3f,0x0f,0xfd,0xff = jlt.u	%d15, %d0, -0x6
+0x91,0x40,0x88,0x4f = movh.a	%a4, 63620
+0xd9,0xff,0x20,0x80 = lea	%a15, [%a15]544
+0x6d,0xe8,0x3d,0x22 = call	-0x2fbb86
+0xd9,0xff,0x30,0xf0 = lea	%a15, [%a15]1008
+0xd9,0xff,0x24,0x96 = lea	%a15, [%a15]25188
+0x91,0x10,0x00,0xa5 = movh.a	%sp, 20481
+0xd9,0xaa,0x40,0x85 = lea	%sp, [%sp]22016
+0x91,0x10,0x00,0xf5 = movh.a	%a15, 20481
+0xd9,0xff,0x80,0xc5 = lea	%a15, [%a15]23296
+0xd9,0xff,0xc0,0x05 = lea	%a15, [%a15]23552
+0x91,0x10,0x00,0x25 = movh.a	%a2, 20481
+0xd9,0x22,0xc0,0x07 = lea	%a2, [%a2]31744
+0x6d,0xe8,0xcf,0x20 = call	-0x2fbe62
+0xd9,0xff,0x60,0x00 = lea	%a15, [%a15]1056
+0x6d,0xff,0x6b,0x4b = call	-0x1692a
+0x15,0xd0,0xc0,0xe3 = stlcx	0xd0003f80
+0x15,0xd0,0xc0,0xf7 = stucx	0xd0003fc0
+# 0x4d,0x40,0xe0,0xff = mfcr	%d15,$psw
+0xb7,0x2f,0x02,0xf5 = insert	%d15, %d15, 2, 10, 2
+# 0x4d,0x40,0x20,0xf9 = mfcr	%d15,$pcon1
+# 0xcd,0x4f,0x20,0x09 = mtcr	$pcon1,%d15
+0xc5,0x02,0x3f,0x10 = lea	%a2, 0x7f
+0xa0,0x15           = mov.a	%a5, 1
+0x89,0x40,0xc1,0x03 = cachei.wi	[%a4+]1
+0x49,0xff,0x20,0x0a = lea	%a15, [%a15]32
+0xfc,0x29           = loop	%a2, -0xe
+0x6f,0x0f,0xfe,0xff = jnz.t	%d15, 0, -0x4
+0x6f,0x1f,0xfa,0xff = jnz.t	%d15, 1, -0xc
+# 0x85,0xdf,0xc4,0xf3 = ld.w	%d15,d0003fc4
+0x15,0xd0,0xc0,0xff = lducx	0xd0003fc0
+0x15,0xd0,0xc0,0xeb = ldlcx	0xd0003f80
+0x1d,0x00,0x03,0x00 = j	0x6
+0xd9,0x44,0xa8,0x4a = lea	%a4, [%a4]-22232
+# 0x19,0x2f,0x34,0xa6 = ld.w	%d15,[%a2]25268
+0x8f,0xff,0x83,0x31 = xor	%d3, %d15, 63
+0x91,0x50,0x02,0x2f = movh.a	%a2, 61477
+# 0x39,0x2f,0x2c,0x08 = ld.bu	%d15,[%a2]-32724
+0xdf,0x1f,0x70,0x80 = jne	%d15, 1, 0xe0
+# 0x09,0x45,0x84,0x09 = ld.a	%a5,[%a4]4
+0x3c,0x64           = j	0xc8
+0x8f,0x23,0x20,0xf0 = sha	%d15, %d3, 2
+0x7b,0xc0,0xff,0x0f = movh	%d0, 65532
+# 0x59,0x2f,0x34,0xa6 = st.w	[%a2]25268
+0x37,0x0f,0xe1,0xf0 = extr.u	%d15, %d15, 1, 1
+0xdf,0x1f,0xfa,0x7f = jeq	%d15, 1, -0xc
+# 0xcc,0x51           = ld.a	%a15,[%a5]4
+# 0x54,0x20           = ld.w	%d0,[%a2]
+# 0x48,0x2f           = ld.w	%d15,[%a15]8
+0x82,0xf1           = mov	%d1, -1
+0xc6,0x1f           = xor	%d15, %d1
+# 0x74,0x20           = st.w	[%a2],%d0
+0x49,0xff,0x0c,0x0a = lea	%a15, [%a15]12
+0x80,0xf0           = mov.d	%d0, %a15
+0x53,0xcf,0x20,0x10 = mul	%d1, %d15, 12
+# 0x4c,0x51           = ld.w	%d15,[%a5]4
+0x42,0xf1           = add	%d1, %d15
+0x3f,0x10,0xee,0xff = jlt.u	%d0, %d1, -0x24
+# 0x39,0x2f,0x0b,0x48 = ld.bu	%d15,[%a2]-32501
+# 0xe9,0x2f,0x0b,0x48 = st.b	[%a2]-32501
+# 0x19,0xff,0x34,0xa6 = ld.w	%d15,[%a15]25268
+0x6f,0x1f,0xfc,0x7f = jz.t	%d15, 1, -0x8
+0x3b,0x00,0x10,0xf0 = mov	%d15, 256
+0x91,0x50,0x02,0xff = movh.a	%a15, 61477
+# 0x39,0xf0,0x0b,0x48 = ld.bu	%d0,[%a15]-32501
+0x37,0x00,0x61,0x03 = extr.u	%d0, %d0, 6, 1
+# 0x4c,0x52           = ld.w	%d15,[%a5]8
+0xbb,0x00,0x52,0x0c = mov.u	%d0, 50464
+0x9b,0xb0,0xbf,0x04 = addih	%d0, %d0, 19451
+0x49,0x55,0x0c,0x0a = lea	%a5, [%a5]12
+0x80,0x50           = mov.d	%d0, %a5
+# 0x4c,0x41           = ld.w	%d15,[%a4]4
+0x3f,0x10,0x97,0xff = jlt.u	%d0, %d1, -0xd2
+0xdc,0x0b           = ji	%a11
+0xd9,0x22,0xb0,0x4a = lea	%a2, [%a2]-22224
+# 0x39,0xff,0x2c,0x08 = ld.bu	%d15,[%a15]-32724
+0xde,0x1c           = jne	%d15, 1, 0x38
+# 0xcc,0x21           = ld.a	%a15,[%a2]4
+# 0x54,0x41           = ld.w	%d1,[%a4]
+0x26,0xf1           = and	%d1, %d15
+0x3e,0x12           = jeq	%d15, %d1, 0x4
+0xc2,0x12           = add	%d2, 1
+0x3f,0xf2,0xf3,0x7f = jlt	%d2, %d15, -0x1a
+0xdf,0x10,0x0a,0x80 = jne	%d0, 1, 0x14
+# 0x39,0xff,0x2e,0x08 = ld.bu	%d15,[%a15]-32722
+0x1e,0x12           = jeq	%d15, 1, 0x4
+0xf6,0x02           = jnz	%d0, 0x4
+0x91,0x00,0x00,0xe8 = movh.a	%a14, 32768
+0xd9,0xee,0x08,0xf0 = lea	%a14, [%a14]968
+0xdc,0x0e           = ji	%a14
+0x91,0x00,0x00,0xf7 = movh.a	%a15, 28672
+0xd9,0xff,0x28,0x00 = lea	%a15, [%a15]40
+# 0xc8,0xe2           = ld.a	%a2,[%a15]56
+0xd9,0xee,0x2e,0xe0 = lea	%a14, [%a14]942
+# 0xc8,0xd2           = ld.a	%a2,[%a15]52
+0xd9,0xee,0x14,0xe0 = lea	%a14, [%a14]916
+# 0xc8,0xf2           = ld.a	%a2,[%a15]60
+0x20,0x60           = sub.a	%sp, 96
+0xc5,0xf5,0x80,0xc0 = lea	%a5, 0xf0000b00
+0x6d,0x00,0xf3,0x08 = call	0x11e6
+# 0x2c,0xaa           = st.b	[%sp]10,%d15
+# 0x2c,0xad           = st.b	[%sp]13,%d15
+0xd9,0xff,0x10,0x20 = lea	%a15, [%a15]144
+0x49,0xa2,0x00,0x1a = lea	%a2, [%sp]64
+0xa0,0x74           = mov.a	%a4, 7
+# 0x44,0xff           = ld.w	%d15,[%a15+]
+# 0x64,0x2f           = st.w	[%a2+],%d15
+0x49,0xaf,0x00,0x1a = lea	%a15, [%sp]64
+# 0xf8,0x0a           = st.a	[%sp]40,%a15
+0xd9,0xff,0x18,0x60 = lea	%a15, [%a15]408
+# 0xf8,0x0c           = st.a	[%sp]48,%a15
+0x89,0xaf,0xae,0x08 = st.h	[%sp]46, %d15
+0xd9,0xff,0x34,0x10 = lea	%a15, [%a15]116
+# 0xf8,0x0e           = st.a	[%sp]56,%a15
+0x89,0xaf,0xb4,0x08 = st.h	[%sp]52, %d15
+0x89,0xaf,0xa0,0x08 = st.h	[%sp]32, %d15
+0x89,0xaf,0xa2,0x08 = st.h	[%sp]34, %d15
+0x89,0xaf,0xa4,0x08 = st.h	[%sp]36, %d15
+# 0x89,0xaf,0x26,0x08 = st.b	[%sp]38,%d15
+0xd9,0x44,0x0c,0x00 = lea	%a4, [%a4]12
+0x6d,0x00,0x6d,0x06 = call	0xcda
+0xd9,0x44,0x28,0x00 = lea	%a4, [%a4]40
+0x91,0x00,0x00,0x57 = movh.a	%a5, 28672
+0xd9,0x55,0x0c,0x00 = lea	%a5, [%a5]12
+0x6d,0x00,0x5f,0x0a = call	0x14be
+0x91,0x40,0x00,0xff = movh.a	%a15, 61444
+0xd9,0xff,0x40,0x4b = lea	%a15, [%a15]-19200
+0x82,0x30           = mov	%d0, 3
+0x0f,0x0f,0x10,0xf0 = sha	%d15, %d15, %d0
+# 0x6c,0xf1           = st.w	[%a15]4,%d15
+0x91,0x40,0x00,0x4f = movh.a	%a4, 61444
+0xd9,0x44,0x40,0x4b = lea	%a4, [%a4]-19200
+0x82,0x34           = mov	%d4, 3
+0x3b,0x00,0x08,0x50 = mov	%d5, 128
+0x6d,0x00,0x45,0x0c = call	0x188a
+0x82,0x54           = mov	%d4, 5
+0x3b,0x00,0x01,0x50 = mov	%d5, 16
+0x6d,0x00,0x3c,0x0c = call	0x1878
+0x82,0x50           = mov	%d0, 5
+# 0x48,0x9f           = ld.w	%d15,[%a15]36
+0x57,0x0f,0x61,0xf0 = extr.u	%d15, %d15, %d0, 1
+0xdf,0x1f,0xf3,0x7f = jeq	%d15, 1, -0x1a
+0x6e,0xf3           = jz	%d15, -0x1a
+0xc5,0xff,0x00,0x01 = lea	%a15, 0xf0001000
+0xbc,0xf1           = jz.a	%a15, 0x2
+0x6d,0x00,0xc8,0x0e = call	0x1d90
+0x4b,0x0f,0x31,0xf1 = ftoiz	%d15, %d15
+0x3b,0x80,0x3e,0x00 = mov	%d0, 1000
+0x4b,0x0f,0x11,0x02 = div.u	%e0, %d15, %d0
+0x40,0x45           = mov.aa	%a5, %a4
+0x49,0xa6,0x00,0x0a = lea	%a6, [%sp]0
+# 0xc8,0xa2           = ld.a	%a2,[%a15]40
+0xd9,0xff,0x30,0x20 = lea	%a15, [%a15]176
+0xa0,0x34           = mov.a	%a4, 3
+0x82,0x44           = mov	%d4, 4
+0x6d,0xff,0x2c,0xff = call	-0x1a8
+0xd9,0xff,0x34,0x20 = lea	%a15, [%a15]180
+0x6d,0x00,0x03,0x00 = call	0x6
+0xd9,0xff,0x38,0x20 = lea	%a15, [%a15]184
+0x3b,0x80,0x00,0x00 = mov	%d0, 8
+0x8f,0xf4,0x0f,0xf1 = and	%d15, %d4, 255
+# 0x2c,0xa4           = st.b	[%sp]4,%d15
+0x37,0x04,0x68,0xf4 = extr.u	%d15, %d4, 8, 8
+# 0x2c,0xa5           = st.b	[%sp]5,%d15
+0x37,0x04,0x68,0xf8 = extr.u	%d15, %d4, 16, 8
+# 0x2c,0xa6           = st.b	[%sp]6,%d15
+0x37,0x04,0x68,0xfc = extr.u	%d15, %d4, 24, 8
+# 0x2c,0xa7           = st.b	[%sp]7,%d15
+0x6d,0xff,0xb5,0xff = call	-0x96
+0xd9,0xff,0x00,0x30 = lea	%a15, [%a15]192
+0xa0,0x94           = mov.a	%a4, 9
+0x3b,0xa0,0x00,0x00 = mov	%d0, 10
+# 0x2c,0xa8           = st.b	[%sp]8,%d15
+# 0x2c,0xa9           = st.b	[%sp]9,%d15
+0x6d,0xff,0x94,0xff = call	-0xd8
+0xd9,0xff,0x0c,0x30 = lea	%a15, [%a15]204
+0x3b,0x80,0x00,0x40 = mov	%d4, 8
+0x6d,0x00,0x16,0x00 = call	0x2c
+0xd9,0xff,0x14,0x30 = lea	%a15, [%a15]212
+0x9a,0x48           = add	%d15, %d8, 4
+# 0x2c,0xa3           = st.b	[%sp]3,%d15
+0x8f,0xf5,0x0f,0xf1 = and	%d15, %d5, 255
+0x37,0x05,0x68,0xf4 = extr.u	%d15, %d5, 8, 8
+0x37,0x05,0x68,0xf8 = extr.u	%d15, %d5, 16, 8
+0x37,0x05,0x68,0xfc = extr.u	%d15, %d5, 24, 8
+0x6d,0xff,0x43,0xff = call	-0x17a
+0xd9,0xff,0x1c,0x30 = lea	%a15, [%a15]220
+0xa0,0xb4           = mov.a	%a4, 11
+0x3b,0xc0,0x00,0x00 = mov	%d0, 12
+# 0x2c,0xab           = st.b	[%sp]11,%d15
+0x6d,0xff,0x67,0xff = call	-0x132
+0x7b,0x10,0x00,0xf0 = movh	%d15, 1
+0x3b,0x80,0x3e,0x40 = mov	%d4, 1000
+0x6d,0xff,0xbc,0xfd = call	-0x488
+0x0b,0x23,0x10,0x48 = mov	%e4, %d3, %d2
+0x49,0xa5,0x02,0x0a = lea	%a5, [%sp]2
+# 0xc8,0x32           = ld.a	%a2,[%a15]12
+0xdf,0x12,0x11,0x80 = jne	%d2, 1, 0x22
+0x01,0xa0,0x00,0xf6 = addsc.a	%a15, %sp, %d0, 0
+# 0x08,0x2f           = ld.bu	%d15,[%a15]2
+0x01,0xc0,0x00,0xf6 = addsc.a	%a15, %a12, %d0, 0
+# 0x14,0xf1           = ld.bu	%d1,[%a15]
+0x94,0xaf           = ld.h	%d15, [%sp]
+0x3f,0xf0,0xf6,0xff = jlt.u	%d0, %d15, -0x14
+0xd9,0xff,0x14,0x10 = lea	%a15, [%a15]84
+0xa0,0xa4           = mov.a	%a4, 10
+0x3b,0xb0,0x00,0x00 = mov	%d0, 11
+0xd9,0xff,0x20,0x10 = lea	%a15, [%a15]96
+0xa0,0x64           = mov.a	%a4, 6
+0x82,0x74           = mov	%d4, 7
+0xd9,0xff,0x28,0x10 = lea	%a15, [%a15]104
+0x6d,0x00,0x04,0x00 = call	0x8
+0xd9,0xff,0x30,0x10 = lea	%a15, [%a15]112
+0x6d,0xff,0x53,0xff = call	-0x15a
+0xd9,0xff,0x38,0x10 = lea	%a15, [%a15]120
+0x6d,0xff,0x9d,0xff = call	-0xc6
+0xd9,0xff,0x00,0x20 = lea	%a15, [%a15]128
+0x6d,0xff,0x89,0xff = call	-0xee
+0xd9,0xff,0x08,0x20 = lea	%a15, [%a15]136
+0x6d,0x00,0x18,0x00 = call	0x30
+0x6d,0x00,0xf7,0x00 = call	0x1ee
+0x6d,0x00,0x92,0x01 = call	0x324
+0xdf,0x02,0xf8,0x7f = jeq	%d2, 0, -0x10
+0x7b,0x00,0x05,0x40 = movh	%d4, 80
+0x3b,0xc0,0x05,0x50 = mov	%d5, 92
+0xbb,0x80,0x02,0x4a = mov.u	%d4, 41000
+0x9b,0x34,0x42,0x4a = addih	%d4, %d4, 42019
+0x6d,0x00,0xbc,0x00 = call	0x178
+0x3b,0x00,0x40,0x41 = mov	%d4, 5120
+0x9b,0x04,0x05,0x40 = addih	%d4, %d4, 80
+0x3b,0x50,0xeb,0x56 = mov	%d5, 28341
+0x6d,0xff,0x83,0xff = call	-0xfa
+0xbb,0xe0,0x3c,0x4b = mov.u	%d4, 46030
+0x9b,0x34,0x98,0x4d = addih	%d4, %d4, 55683
+0x6d,0x00,0xab,0x00 = call	0x156
+0x53,0x59,0x2f,0xf0 = mul	%d15, %d9, 245
+# 0x08,0x1f           = ld.bu	%d15,[%a15]1
+0x8f,0x8f,0x01,0x00 = sh	%d0, %d15, 24
+0x8f,0x0f,0x01,0xf0 = sh	%d15, %d15, 16
+# 0x08,0x3f           = ld.bu	%d15,[%a15]3
+0x8f,0x8f,0x00,0xf0 = sh	%d15, %d15, 8
+0x0f,0xf0,0xa0,0x50 = or	%d5, %d0, %d15
+# 0x14,0xf4           = ld.bu	%d4,[%a15]
+0xb0,0x54           = add.a	%a4, 5
+0x6d,0x00,0x8a,0x02 = call	0x514
+0x3f,0x89,0xd6,0xff = jlt.u	%d9, %d8, -0x54
+0xd9,0xee,0x9e,0x70 = lea	%a14, [%a14]2526
+0xd9,0xff,0x3c,0xa0 = lea	%a15, [%a15]700
+0xd9,0xee,0x84,0x70 = lea	%a14, [%a14]2500
+0xd9,0xee,0xaa,0x60 = lea	%a14, [%a14]2474
+0xd9,0x55,0x60,0xba = lea	%a5, [%a5]-22816
+0x6d,0x00,0x81,0x11 = call	0x2302
+0xd9,0x55,0x64,0xba = lea	%a5, [%a5]-22812
+0x6d,0x00,0x7a,0x11 = call	0x22f4
+0xd9,0x55,0x2c,0xda = lea	%a5, [%a5]-23700
+0x6d,0x00,0x73,0x11 = call	0x22e6
+0xd9,0x55,0x14,0xea = lea	%a5, [%a5]-23660
+0x6d,0x00,0x6c,0x11 = call	0x22d8
+0xd9,0x55,0x3c,0xea = lea	%a5, [%a5]-23620
+0x6d,0x00,0x65,0x11 = call	0x22ca
+0xd9,0x55,0x20,0xfa = lea	%a5, [%a5]-23584
+0x6d,0x00,0x5e,0x11 = call	0x22bc
+0xd9,0x55,0x34,0xfa = lea	%a5, [%a5]-23564
+0x6d,0x00,0x57,0x11 = call	0x22ae
+0xd9,0x55,0x5c,0x0a = lea	%a5, [%a5]-23524
+0x6d,0x00,0x50,0x11 = call	0x22a0
+0xd9,0x55,0x74,0x0a = lea	%a5, [%a5]-23500
+0x6d,0x00,0x49,0x11 = call	0x2292
+0xd9,0x55,0x50,0x1a = lea	%a5, [%a5]-23472
+0x6d,0x00,0x42,0x11 = call	0x2284
+0xd9,0x55,0x68,0x1a = lea	%a5, [%a5]-23448
+0x6d,0x00,0x3b,0x11 = call	0x2276
+0xd9,0x55,0x4c,0x2a = lea	%a5, [%a5]-23412
+0x6d,0x00,0x34,0x11 = call	0x2268
+0xd9,0x55,0x6c,0x2a = lea	%a5, [%a5]-23380
+0x6d,0x00,0x2d,0x11 = call	0x225a
+0xd9,0x55,0x48,0x3a = lea	%a5, [%a5]-23352
+0x6d,0x00,0x26,0x11 = call	0x224c
+0xd9,0x55,0x64,0x3a = lea	%a5, [%a5]-23324
+0x6d,0x00,0x1f,0x11 = call	0x223e
+0xd9,0x55,0x48,0x4a = lea	%a5, [%a5]-23288
+0x6d,0x00,0x18,0x11 = call	0x2230
+0xd9,0x55,0x70,0x4a = lea	%a5, [%a5]-23248
+0x6d,0x00,0x11,0x11 = call	0x2222
+0x6d,0x00,0x0a,0x11 = call	0x2214
+0x40,0x64           = mov.aa	%a4, %a6
+0x6d,0xff,0x7f,0xff = call	-0x102
+0xda,0x30           = mov	%d15, 48
+0xbe,0x0d           = jeq	%d15, %d0, 0x3a
+0x5f,0x0f,0x2c,0x00 = jeq	%d15, %d0, 0x58
+0x3c,0x3b           = j	0x76
+0xd9,0xff,0x00,0x0a = lea	%a15, [%a15]-24576
+0x86,0x5f           = sha	%d15, 5
+0x86,0x6f           = sha	%d15, 6
+0xd9,0x55,0x7c,0x4a = lea	%a5, [%a5]-23236
+0x6d,0x00,0xdb,0x10 = call	0x21b6
+0x3c,0x3a           = j	0x74
+0x9b,0x1f,0x00,0xf0 = addih	%d15, %d15, 1
+0xd9,0x55,0x54,0x5a = lea	%a5, [%a5]-23212
+0x6d,0x00,0xca,0x10 = call	0x2194
+0xd9,0x55,0x64,0x5a = lea	%a5, [%a5]-23196
+0x6d,0x00,0xb9,0x10 = call	0x2172
+0x3c,0x18           = j	0x30
+0xd9,0x55,0x74,0x5a = lea	%a5, [%a5]-23180
+0x6d,0x00,0xa3,0x10 = call	0x2146
+0xd9,0x44,0x00,0x0a = lea	%a4, [%a4]-24576
+0x6d,0x00,0xe5,0x09 = call	0x13ca
+0x82,0x64           = mov	%d4, 6
+0x6d,0x00,0xdc,0x09 = call	0x13b8
+0xc5,0xf5,0x80,0x40 = lea	%a5, 0xf0000900
+0x6d,0x00,0xe0,0x05 = call	0xbc0
+0x7b,0x60,0x61,0xf4 = movh	%d15, 17942
+0xd9,0xff,0x64,0x7a = lea	%a15, [%a15]-23068
+0xd9,0xff,0x68,0x60 = lea	%a15, [%a15]1448
+0xd9,0xff,0x44,0x20 = lea	%a15, [%a15]1156
+0xda,0x04           = mov	%d15, 4
+0xda,0x0c           = mov	%d15, 12
+0xd9,0x44,0x08,0xc0 = lea	%a4, [%a4]776
+0x6d,0x00,0x5a,0x03 = call	0x6b4
+0xd9,0x44,0x3c,0xa0 = lea	%a4, [%a4]700
+0xd9,0x55,0x08,0xc0 = lea	%a5, [%a5]776
+0x6d,0x00,0x4c,0x07 = call	0xe98
+0x20,0x28           = sub.a	%sp, 40
+0x6d,0x00,0x37,0x00 = call	0x6e
+0x6d,0xff,0xdc,0xff = call	-0x48
+0x6d,0x00,0x7f,0x00 = call	0xfe
+0xd9,0x55,0x64,0x8a = lea	%a5, [%a5]-23004
+0x6d,0x00,0xfc,0x11 = call	0x23f8
+0xd9,0x55,0x40,0x9a = lea	%a5, [%a5]-22976
+0x6d,0x00,0xf2,0x11 = call	0x23e4
+0x6d,0x00,0x79,0x1a = call	0x34f2
+0xd9,0xff,0x50,0xca = lea	%a15, [%a15]-22768
+0xd9,0x44,0x24,0xc0 = lea	%a4, [%a4]804
+0x6d,0x00,0xe2,0x19 = call	0x33c4
+0x6d,0x00,0x24,0x1a = call	0x3448
+0x6d,0xff,0x27,0x38 = call	-0x18fb2
+0x3c,0x27           = j	0x4e
+0x0b,0x40,0x40,0x20 = addx	%d2, %d0, %d4
+0x0b,0x51,0x50,0x30 = addc	%d3, %d1, %d5
+0x6e,0xca           = jz	%d15, -0x6c
+0x6d,0xff,0x97,0x3e = call	-0x182d2
+0x02,0x24           = mov	%d4, %d2
+0x6d,0xff,0xeb,0x3d = call	-0x1842a
+0x6d,0xff,0xa6,0x3e = call	-0x182b4
+0x6d,0xff,0x2a,0x3e = call	-0x183ac
+0xd9,0x44,0xec,0x10 = lea	%a4, [%a4]3180
+0x6d,0xff,0x66,0x35 = call	-0x19534
+0x6d,0xff,0x0b,0x2a = call	-0x1abea
+0x6d,0xff,0x94,0x2a = call	-0x1aad8
+0xdf,0x12,0x49,0x80 = jne	%d2, 1, 0x92
+0x6d,0xff,0xb1,0x2a = call	-0x1aa9e
+0x6d,0xff,0xd0,0x2b = call	-0x1a860
+0x5e,0x1a           = jne	%d15, 1, 0x14
+0x91,0x00,0x00,0x48 = movh.a	%a4, 32768
+0xd9,0x44,0xfc,0xb5 = lea	%a4, [%a4]24316
+0x3b,0x80,0x07,0x40 = mov	%d4, 120
+0x6d,0xff,0xc5,0x29 = call	-0x1ac76
+0x3b,0x00,0x40,0x40 = mov	%d4, 1024
+0x9b,0x74,0x02,0x40 = addih	%d4, %d4, 39
+0x6d,0xff,0xdd,0x2a = call	-0x1aa46
+0x6d,0xff,0x23,0x2c = call	-0x1a7ba
+0x6d,0xff,0x82,0x2b = call	-0x1a8fc
+0xdf,0x02,0x21,0x80 = jne	%d2, 0, 0x42
+0xbb,0x00,0x20,0x4c = mov.u	%d4, 49664
+0x9b,0x14,0x00,0x40 = addih	%d4, %d4, 1
+0x6d,0xff,0xf0,0x2a = call	-0x1aa20
+0x6d,0xff,0x29,0x2c = call	-0x1a7ae
+0x6d,0xff,0x75,0x2a = call	-0x1ab16
+0x6d,0xff,0x94,0x2b = call	-0x1a8d8
+0x91,0x10,0x00,0x48 = movh.a	%a4, 32769
+0xd9,0x44,0x14,0x7d = lea	%a4, [%a4]-11820
+0x3b,0xb0,0x0d,0x40 = mov	%d4, 219
+0x6d,0xff,0x9d,0x29 = call	-0x1acc6
+0x6d,0xff,0x64,0x2b = call	-0x1a938
+0x5e,0x17           = jne	%d15, 1, 0xe
+0x6d,0xff,0xb3,0x2a = call	-0x1aa9a
+0x6d,0xff,0xf9,0x2b = call	-0x1a80e
+0x3b,0x60,0x09,0x40 = mov	%d4, 150
+0x6d,0x00,0x09,0x00 = call	0x12
+0x6d,0xff,0x92,0x2c = call	-0x1a6dc
+0x6d,0xff,0x9d,0x2d = call	-0x1a4c6
+0x3c,0xfe           = j	-0x4
+0x3b,0xf0,0x0f,0x00 = mov	%d0, 255
+0x06,0x3f           = sh	%d15, 3
+0x0f,0xf0,0x10,0x00 = sha	%d0, %d0, %d15
+0xc6,0xf0           = xor	%d0, %d15
+0x60,0x4f           = mov.a	%a15, %d4
+0xb7,0x0f,0x02,0xf0 = insert	%d15, %d15, 0, 0, 2
+0x60,0xf2           = mov.a	%a2, %d15
+# 0x74,0x2f           = st.w	[%a2],%d15
+0x77,0x00,0x00,0x04 = dextr	%d0, %d0, %d0, 8
+0xfc,0xf6           = loop	%a15, -0x14
+0x8f,0x3f,0x00,0x10 = sh	%d1, %d15, 3
+0x0f,0x10,0x10,0x00 = sha	%d0, %d0, %d1
+0xc6,0x10           = xor	%d0, %d1
+0x80,0x41           = mov.d	%d1, %a4
+0xb7,0x01,0x02,0x20 = insert	%d2, %d1, 0, 0, 2
+# 0x09,0x51,0x01,0x00 = ld.b	%d1,[%a5+]1
+0x8f,0x3f,0x00,0x30 = sh	%d3, %d15, 3
+0x0f,0x31,0x10,0x10 = sha	%d1, %d1, %d3
+0x60,0x22           = mov.a	%a2, %d2
+# 0x54,0x22           = ld.w	%d2,[%a2]
+0x26,0x02           = and	%d2, %d0
+0xa6,0x12           = or	%d2, %d1
+# 0x74,0x22           = st.w	[%a2],%d2
+0xfd,0xf0,0xed,0x7f = loop	%a15, -0x26
+# 0xc8,0x1c           = ld.a	%a12,[%a15]4
+# 0xc8,0x2d           = ld.a	%a13,[%a15]8
+# 0x48,0x3c           = ld.w	%d12,[%a15]12
+# 0x09,0xff,0x10,0x01 = ld.w	%d15,[%a15+]16
+0xdf,0x1f,0x23,0x80 = jne	%d15, 1, 0x46
+0x80,0xcf           = mov.d	%d15, %a12
+0x80,0xd0           = mov.d	%d0, %a13
+0x8f,0x10,0x00,0x01 = and	%d0, %d0, 1
+0xfe,0x04           = jne	%d15, %d0, 0x28
+0xc2,0xfc           = add	%d12, -1
+# 0x04,0xdf           = ld.bu	%d15,[%a13+]
+# 0x24,0xcf           = st.b	[%a12+],%d15
+0x76,0xcf           = jz	%d12, 0x1e
+0x8f,0x3c,0x00,0x01 = and	%d0, %d12, 3
+0x8f,0xec,0x1f,0xf0 = sh	%d15, %d12, -2
+0x02,0xf1           = mov	%d1, %d15
+0x40,0xd2           = mov.aa	%a2, %a13
+0xc2,0xf1           = add	%d1, -1
+0x60,0x14           = mov.a	%a4, %d1
+# 0x44,0x21           = ld.w	%d1,[%a2+]
+# 0x64,0xc1           = st.w	[%a12+],%d1
+0x90,0xdd           = addsc.a	%a13, %a13, %d15, 2
+0x02,0x0c           = mov	%d12, %d0
+0xdf,0x0c,0xe0,0x7f = jeq	%d12, 0, -0x40
+0x60,0xc2           = mov.a	%a2, %d12
+0xfc,0x2e           = loop	%a2, -0x4
+0x3c,0xd9           = j	-0x4e
+0xde,0x25           = jne	%d15, 2, 0x2a
+0x2e,0x03           = jz.t	%d15, 0, 0x6
+# 0x24,0xc9           = st.b	[%a12+],%d9
+0xdf,0x0c,0xd3,0x7f = jeq	%d12, 0, -0x5a
+0x8f,0x3c,0x00,0xf1 = and	%d15, %d12, 3
+0x06,0xec           = sh	%d12, -2
+# 0x64,0xca           = st.w	[%a12+],%d10
+0xfc,0x2f           = loop	%a2, -0x2
+0x6e,0xc9           = jz	%d15, -0x6e
+# 0x24,0xcb           = st.b	[%a12+],%d11
+0x3c,0xc4           = j	-0x78
+0x8f,0x0f,0x1f,0x00 = sh	%d0, %d15, -16
+0xdf,0x00,0x2e,0x00 = jeq	%d0, 0, 0x5c
+0x8f,0x3f,0x00,0x01 = and	%d0, %d15, 3
+0xdf,0x10,0x2b,0x80 = jne	%d0, 1, 0x56
+0x8f,0x3f,0x00,0xd1 = and	%d13, %d15, 3
+0x80,0xdf           = mov.d	%d15, %a13
+0xfe,0xdb           = jne	%d15, %d13, 0x36
+0x76,0xdb           = jz	%d13, 0x16
+0x02,0xd4           = mov	%d4, %d13
+0x40,0xd5           = mov.aa	%a5, %a13
+0x6d,0x00,0xef,0x06 = call	0xdde
+0x01,0xcd,0x00,0xc6 = addsc.a	%a12, %a12, %d13, 0
+0x01,0xdd,0x00,0xd6 = addsc.a	%a13, %a13, %d13, 0
+0xa2,0xdc           = sub	%d12, %d13
+0xdf,0x0c,0x9b,0x7f = jeq	%d12, 0, -0xca
+0x02,0xc4           = mov	%d4, %d12
+0x6d,0x00,0xd4,0x06 = call	0xda8
+0x3c,0x94           = j	-0xd8
+0xdf,0x2f,0x91,0xff = jne	%d15, 2, -0xde
+0x6d,0x00,0xb1,0x06 = call	0xd62
+0x10,0xcc           = addsc.a	%a12, %a12, %d15, 0
+0xa2,0xfc           = sub	%d12, %d15
+0xdf,0x0c,0x86,0x7f = jeq	%d12, 0, -0xf4
+0x8f,0x3c,0x00,0x41 = and	%d4, %d12, 3
+# 0x64,0xc8           = st.w	[%a12+],%d8
+0xdf,0x04,0x7c,0x7f = jeq	%d4, 0, -0x108
+0x6d,0x00,0xa0,0x06 = call	0xd40
+0x1d,0xff,0x77,0xff = j	-0x112
+0xd9,0x44,0x34,0x8b = lea	%a4, [%a4]-19916
+0x1d,0x00,0x02,0x00 = j	0x4
+0x80,0x44           = mov.d	%d4, %a4
+0x80,0x55           = mov.d	%d5, %a5
+0xa6,0x54           = or	%d4, %d5
+0x6f,0x04,0x04,0x00 = jz.t	%d4, 0, 0x8
+# 0x64,0x45           = st.w	[%a4+],%d5
+# 0x44,0x55           = ld.w	%d5,[%a5+]
+0x8b,0x05,0xc0,0xfa = eqany.b	%d15, %d5, 0
+0x6e,0xfc           = jz	%d15, -0x8
+0xb0,0xc5           = add.a	%a5, -4
+# 0x09,0x5f,0x01,0x00 = ld.b	%d15,[%a5+]1
+# 0x24,0x4f           = st.b	[%a4+],%d15
+0xee,0xfd           = jnz	%d15, -0x6
+0x6f,0x04,0x0d,0x80 = jnz.t	%d4, 0, 0x1a
+# 0x44,0x4f           = ld.w	%d15,[%a4+]
+0x8b,0x0f,0xc0,0x4a = eqany.b	%d4, %d15, 0
+0x7e,0x55           = jne	%d15, %d5, 0xa
+0xdf,0x04,0xfb,0x7f = jeq	%d4, 0, -0xa
+0xb0,0xc4           = add.a	%a4, -4
+# 0x04,0x4f           = ld.bu	%d15,[%a4+]
+0xca,0xff           = caddn	%d15, %d15, -1
+# 0x04,0x55           = ld.bu	%d5,[%a5+]
+0x5f,0x5f,0xfd,0x7f = jeq	%d15, %d5, -0x6
+0xab,0xf5,0x3f,0x55 = caddn	%d5, %d5, %d5, -1
+0x52,0x52           = sub	%d2, %d15, %d5
+0xbf,0x85,0x23,0x80 = jlt.u	%d5, 8, 0x46
+0x2e,0x05           = jz.t	%d15, 0, 0xa
+0xc2,0xf5           = add	%d5, -1
+# 0x34,0x44           = st.b	[%a4],%d4
+0x49,0x4f,0x01,0x0a = lea	%a15, [%a4]1
+0x2e,0x14           = jz.t	%d15, 1, 0x8
+# 0x24,0xf4           = st.b	[%a15+],%d4
+0xc2,0xe5           = add	%d5, -2
+0x8f,0x75,0x00,0xf1 = and	%d15, %d5, 7
+0x06,0xd5           = sh	%d5, -3
+0xdf,0x05,0x12,0x00 = jeq	%d5, 0, 0x24
+0x76,0x4a           = jz	%d4, 0x14
+0x37,0x04,0x68,0x00 = extr.u	%d0, %d4, 0, 8
+0x8f,0x80,0x20,0x10 = sha	%d1, %d0, 8
+0xa6,0x10           = or	%d0, %d1
+0x8f,0x00,0x21,0x10 = sha	%d1, %d0, 16
+0x02,0x01           = mov	%d1, %d0
+0x60,0x52           = mov.a	%a2, %d5
+# 0x89,0xf0,0x48,0x01 = st.d	[%a15+]8,%e0
+0x02,0xf5           = mov	%d5, %d15
+0x76,0x55           = jz	%d5, 0xa
+0x6e,0x65           = jz	%d15, 0xca
+0x92,0x49           = add	%d9, %d15, 4
+0xdf,0x09,0x63,0x00 = jeq	%d9, 0, 0xc6
+0xd9,0xff,0xe4,0x10 = lea	%a15, [%a15]3172
+0xee,0x15           = jnz	%d15, 0x2a
+0x6d,0xff,0x49,0xff = call	-0x16e
+0x32,0x5f           = rsub	%d15
+0x92,0x44           = add	%d4, %d15, 4
+0xdf,0xf0,0x51,0x00 = jeq	%d0, -1, 0xa2
+# 0xb5,0x42,0xe0,0x10 = st.a	[%a4]3168
+# 0xd4,0xfc           = ld.a	%a12,[%a15]
+0xb0,0xfc           = add.a	%a12, -1
+# 0x54,0xcf           = ld.w	%d15,[%a12]
+0x6f,0x0f,0xfc,0xff = jnz.t	%d15, 0, -0x8
+0x3c,0x1d           = j	0x3a
+0xb7,0x08,0x01,0xf0 = insert	%d15, %d8, 0, 0, 1
+0x6f,0x08,0x18,0x80 = jnz.t	%d8, 0, 0x30
+0xee,0x11           = jnz	%d15, 0x22
+0x6d,0xff,0x23,0xff = call	-0x1ba
+0x49,0xf4,0x04,0x0a = lea	%a4, [%a15]4
+0x7d,0x42,0x0f,0x80 = jne.a	%a2, %a4, 0x1e
+0x32,0x58           = rsub	%d8
+0x6d,0xff,0x1b,0xff = call	-0x1ca
+0x1e,0xf8           = jeq	%d15, -1, 0x10
+# 0x74,0xca           = st.w	[%a12],%d10
+0x40,0xcf           = mov.aa	%a15, %a12
+0x40,0xfc           = mov.aa	%a12, %a15
+# 0x54,0xc8           = ld.w	%d8,[%a12]
+0x76,0x85           = jz	%d8, 0xa
+0x6f,0x08,0xe2,0xff = jnz.t	%d8, 0, -0x3c
+0x3f,0x98,0xe0,0xff = jlt.u	%d8, %d9, -0x40
+0xdf,0x08,0x26,0x80 = jne	%d8, 0, 0x4c
+0xbf,0x19,0x18,0x00 = jlt	%d9, 1, 0x30
+0x6d,0xff,0x04,0xff = call	-0x1f8
+0x9e,0xf2           = jeq	%d15, -1, 0x24
+0x49,0xcf,0x04,0x0a = lea	%a15, [%a12]4
+0x01,0xf2,0x20,0xf4 = lt.a	%d15, %a2, %a15
+0xee,0x0d           = jnz	%d15, 0x1a
+0x01,0x2f,0x30,0xf4 = ge.a	%d15, %a15, %a2
+0xee,0x12           = jnz	%d15, 0x24
+0x10,0x2f           = addsc.a	%a15, %a2, %d15, 0
+0x6d,0xff,0xf3,0xfe = call	-0x21a
+0x5e,0xf3           = jne	%d15, -1, 0x6
+0x01,0xcf,0x20,0x20 = sub.a	%a2, %a15, %a12
+# 0x74,0xcf           = st.w	[%a12],%d15
+0x01,0xc9,0x00,0xf6 = addsc.a	%a15, %a12, %d9, 0
+# 0x74,0xfa           = st.w	[%a15],%d10
+0x9a,0x49           = add	%d15, %d9, 4
+0x3f,0xf8,0x07,0x80 = jlt.u	%d8, %d15, 0xe
+0xa2,0x98           = sub	%d8, %d9
+# 0x74,0xf8           = st.w	[%a15],%d8
+0x8f,0x19,0x40,0xf1 = or	%d15, %d9, 1
+0x49,0xc2,0x04,0x0a = lea	%a2, [%a12]4
+0xbd,0x04,0x31,0x00 = jz.a	%a4, 0x62
+0x91,0x00,0x00,0xd7 = movh.a	%a13, 28672
+0xb7,0x0f,0x01,0x80 = insert	%d8, %d15, 0, 0, 1
+0xd9,0xdd,0xe4,0x10 = lea	%a13, [%a13]3172
+0x01,0xc8,0x00,0xe6 = addsc.a	%a14, %a12, %d8, 0
+# 0x54,0xef           = ld.w	%d15,[%a14]
+0xae,0x03           = jnz.t	%d15, 0, 0x6
+0x3c,0xf9           = j	-0xe
+0x01,0xf0,0x00,0x26 = addsc.a	%a2, %a15, %d0, 0
+0x7d,0xc2,0x05,0x80 = jne.a	%a2, %a12, 0xa
+0x42,0x08           = add	%d8, %d0
+0xee,0x10           = jnz	%d15, 0x20
+0xb0,0x4e           = add.a	%a14, 4
+0x7d,0xe2,0x0a,0x80 = jne.a	%a2, %a14, 0x14
+0x6d,0xff,0xaa,0xff = call	-0xac
+0x1e,0xf3           = jeq	%d15, -1, 0x6
+0x0b,0x0f,0x90,0xf1 = min.u	%d15, %d15, %d0
+# 0x74,0xdf           = st.w	[%a13],%d15
+0xd9,0xff,0x04,0x00 = lea	%a15, [%a15]4
+0x91,0x30,0x00,0x57 = movh.a	%a5, 28675
+0xd9,0x55,0xc0,0x87 = lea	%a5, [%a5]32256
+0x01,0x24,0x00,0x46 = addsc.a	%a4, %a2, %d4, 0
+0x01,0x54,0x20,0xf4 = lt.a	%d15, %a4, %a5
+0x91,0x40,0x00,0x57 = movh.a	%a5, 28676
+0xd9,0x55,0xc0,0x88 = lea	%a5, [%a5]-29184
+0x01,0x45,0x30,0xf4 = ge.a	%d15, %a5, %a4
+# 0xf4,0xf4           = st.a	[%a15],%a4
+# 0x89,0xa6,0x8c,0x09 = st.a	[%sp]12,%a6
+# 0x78,0x02           = st.w	[%sp]8,%d15
+# 0x09,0xd4,0x00,0x08 = ld.b	%d4,[%a13]
+0xdf,0x04,0x50,0x02 = jeq	%d4, 0, 0x4a0
+0xda,0x25           = mov	%d15, 37
+0x7e,0x44           = jne	%d15, %d4, 0x8
+# 0x09,0xd0,0x01,0x04 = ld.b	%d0,[+%a13]1
+0x7e,0x08           = jne	%d15, %d0, 0x10
+0xb0,0x1d           = add.a	%a13, 1
+0x6d,0x00,0x48,0x02 = call	0x490
+0x3c,0xf1           = j	-0x1e
+0x0b,0xaa,0x10,0x88 = mov	%e8, %d10, %d10
+# 0x09,0xdf,0x01,0x00 = ld.b	%d15,[%a13+]1
+0x3b,0xd0,0x02,0x00 = mov	%d0, 45
+0x7e,0x04           = jne	%d15, %d0, 0x8
+0x8f,0x1a,0x40,0xa1 = or	%d10, %d10, 1
+0x3b,0xb0,0x02,0x00 = mov	%d0, 43
+0x7e,0x07           = jne	%d15, %d0, 0xe
+0xbb,0xf0,0xfe,0x0f = mov.u	%d0, 65519
+0x26,0xa0           = and	%d0, %d10
+0x8f,0x80,0x40,0xa1 = or	%d10, %d0, 8
+0x3c,0xf0           = j	-0x20
+0x3b,0x00,0x02,0x00 = mov	%d0, 32
+0x7e,0x06           = jne	%d15, %d0, 0xc
+0x6f,0x3a,0xec,0xff = jnz.t	%d10, 3, -0x28
+0x8f,0x0a,0x41,0xa1 = or	%d10, %d10, 16
+0x3c,0xe8           = j	-0x30
+0x3b,0x00,0x03,0x00 = mov	%d0, 48
+0x8f,0x2a,0x40,0xa1 = or	%d10, %d10, 2
+0x3c,0xe2           = j	-0x3c
+0x3b,0x30,0x02,0x00 = mov	%d0, 35
+0x8f,0x4a,0x40,0xa1 = or	%d10, %d10, 4
+0x3c,0xdc           = j	-0x48
+0x3b,0xa0,0x02,0x00 = mov	%d0, 42
+0xfe,0x03           = jne	%d15, %d0, 0x26
+# 0xd8,0x03           = ld.a	%a15,[%sp]12
+0xb0,0x4f           = add.a	%a15, 4
+# 0xf8,0x03           = st.a	[%sp]12,%a15
+# 0x09,0xf8,0x3c,0xf9 = ld.w	%d8,[%a15]-4
+0xce,0x84           = jgez	%d8, 0x8
+0x13,0xa8,0x20,0xff = madd	%d15, %d15, %d8, 10
+0x8b,0x0f,0x1d,0x80 = add	%d8, %d15, -48
+0x8b,0x0f,0x1d,0x00 = add	%d0, %d15, -48
+0xbf,0xa0,0xf6,0xff = jlt.u	%d0, 10, -0x14
+0x3b,0xe0,0x02,0x00 = mov	%d0, 46
+0x5f,0x0f,0x23,0x80 = jne	%d15, %d0, 0x46
+0x8f,0x0a,0x42,0xa1 = or	%d10, %d10, 32
+0xfe,0x05           = jne	%d15, %d0, 0x2a
+# 0x09,0xf9,0x3c,0xf9 = ld.w	%d9,[%a15]-4
+0xce,0x96           = jgez	%d9, 0xc
+0x8f,0x1a,0x40,0xf1 = or	%d15, %d10, 1
+0xbb,0xf0,0xfd,0xaf = mov.u	%d10, 65503
+0x26,0xfa           = and	%d10, %d15
+0x13,0xa9,0x20,0xff = madd	%d15, %d15, %d9, 10
+0x8b,0x0f,0x1d,0x90 = add	%d9, %d15, -48
+0x3b,0xc0,0x06,0x00 = mov	%d0, 108
+0x8f,0x0a,0x48,0xa1 = or	%d10, %d10, 128
+0x3b,0x80,0x06,0x00 = mov	%d0, 104
+0x8f,0x0a,0x44,0xa1 = or	%d10, %d10, 64
+0x3b,0xc0,0x04,0x00 = mov	%d0, 76
+0x8f,0x0a,0x50,0xa1 = or	%d10, %d10, 256
+0x3b,0xa0,0x06,0x00 = mov	%d0, 106
+0xb7,0x1a,0x81,0xa4 = insert	%d10, %d10, 1, 9, 1
+0x3b,0xa0,0x07,0x00 = mov	%d0, 122
+0xb7,0x1a,0x01,0xa5 = insert	%d10, %d10, 1, 10, 1
+0x3b,0x40,0x07,0x00 = mov	%d0, 116
+0xfe,0x01           = jne	%d15, %d0, 0x22
+0xb7,0x1a,0x81,0xa5 = insert	%d10, %d10, 1, 11, 1
+# 0x09,0xd0,0x00,0x08 = ld.b	%d0,[%a13]
+0xb7,0x1a,0x01,0xa6 = insert	%d10, %d10, 1, 12, 1
+0x3b,0x30,0x06,0x00 = mov	%d0, 99
+0x5f,0x0f,0x2f,0x80 = jne	%d15, %d0, 0x5e
+0x8f,0x1a,0x00,0xf1 = and	%d15, %d10, 1
+0xee,0x0e           = jnz	%d15, 0x1c
+0x3b,0x00,0x02,0x40 = mov	%d4, 32
+0x6d,0x00,0x9f,0x01 = call	0x33e
+0x7f,0x89,0x04,0x00 = jge	%d9, %d8, 0x8
+0xff,0x28,0xf6,0x7f = jge	%d8, 2, -0x14
+# 0x09,0xf0,0x3c,0xf9 = ld.w	%d0,[%a15]-4
+0x37,0x00,0x48,0x40 = extr	%d4, %d0, 0, 8
+0x6d,0x00,0x8e,0x01 = call	0x31c
+0xdf,0x0f,0x37,0x7f = jeq	%d15, 0, -0x192
+0x6d,0x00,0x84,0x01 = call	0x308
+0x7f,0x89,0x2c,0x7f = jge	%d9, %d8, -0x1a8
+0x1d,0xff,0x28,0xff = j	-0x1b0
+0x3b,0x40,0x06,0x00 = mov	%d0, 100
+0xbe,0x01           = jeq	%d15, %d0, 0x22
+0x3b,0x90,0x06,0x00 = mov	%d0, 105
+0x3e,0x0e           = jeq	%d15, %d0, 0x1c
+0x3b,0xf0,0x06,0x00 = mov	%d0, 111
+0x3e,0x0b           = jeq	%d15, %d0, 0x16
+0x3b,0x80,0x07,0x00 = mov	%d0, 120
+0x3b,0x80,0x05,0x00 = mov	%d0, 88
+0x3b,0x50,0x07,0x00 = mov	%d0, 117
+0x5f,0x0f,0x59,0x80 = jne	%d15, %d0, 0xb2
+0x7e,0x02           = jne	%d15, %d0, 0x4
+0x3b,0x00,0x08,0x01 = mov	%d0, 4224
+0x0f,0x0a,0x80,0x10 = and	%d1, %d10, %d0
+0x5f,0x01,0x04,0x00 = jeq	%d1, %d0, 0x8
+0x6f,0x9a,0x05,0x00 = jz.t	%d10, 9, 0xa
+0x3b,0x80,0x00,0x10 = mov	%d1, 8
+0x5f,0x10,0x09,0x80 = jne	%d0, %d1, 0x12
+0x49,0xff,0x08,0x0a = lea	%a15, [%a15]8
+# 0x09,0xf0,0x78,0xf9 = ld.d	%e0,[%a15]-8
+0x0b,0x00,0x00,0x08 = mov	%e0, %d0
+0x0b,0x01,0x10,0x48 = mov	%e4, %d1, %d0
+0x3b,0x00,0x04,0x01 = mov	%d0, 4160
+0x5f,0x01,0x0d,0x80 = jne	%d1, %d0, 0x1a
+0x37,0x04,0x48,0x00 = extr	%d0, %d4, 0, 8
+0x37,0x04,0x68,0x40 = extr.u	%d4, %d4, 0, 8
+0x3b,0x00,0x04,0x00 = mov	%d0, 64
+0x5f,0x01,0x0b,0x80 = jne	%d1, %d0, 0x16
+0x76,0x26           = jz	%d2, 0xc
+0x37,0x04,0x50,0x00 = extr	%d0, %d4, 0, 16
+0x0b,0x00,0x00,0x48 = mov	%e4, %d0
+0x37,0x04,0x70,0x40 = extr.u	%d4, %d4, 0, 16
+0x6f,0x5a,0x06,0x00 = jz.t	%d10, 5, 0xc
+0xbb,0xd0,0xff,0x0f = mov.u	%d0, 65533
+0x26,0x0a           = and	%d10, %d0
+0x0b,0xfa,0x10,0x68 = mov	%e6, %d10, %d15
+# 0x89,0xa4,0x40,0x09 = st.d	[%sp],%e4
+0x0b,0x89,0x10,0x48 = mov	%e4, %d9, %d8
+0x3b,0x30,0x07,0x00 = mov	%d0, 115
+0xfe,0x06           = jne	%d15, %d0, 0x2c
+0x6f,0x5a,0x06,0x80 = jnz.t	%d10, 5, 0xc
+0xbb,0xf0,0xff,0x9f = mov.u	%d9, 65535
+0x9b,0xf9,0xff,0x97 = addih	%d9, %d9, 32767
+0x0b,0xa8,0x10,0x48 = mov	%e4, %d8, %d10
+0x02,0x96           = mov	%d6, %d9
+0x49,0xa6,0x08,0x0a = lea	%a6, [%sp]8
+# 0x09,0xf4,0xbc,0xf9 = ld.a	%a4,[%a15]-4
+0x6d,0x00,0xab,0x02 = call	0x556
+0x1d,0xff,0xa6,0xfe = j	-0x2b4
+0x3b,0x60,0x06,0x00 = mov	%d0, 102
+0xbe,0x06           = jeq	%d15, %d0, 0x2c
+0x3b,0x60,0x04,0x00 = mov	%d0, 70
+0xbe,0x03           = jeq	%d15, %d0, 0x26
+0x3b,0x50,0x06,0x00 = mov	%d0, 101
+0xbe,0x00           = jeq	%d15, %d0, 0x20
+0x3b,0x50,0x04,0x00 = mov	%d0, 69
+0x3e,0x0d           = jeq	%d15, %d0, 0x1a
+0x3b,0x70,0x06,0x00 = mov	%d0, 103
+0x3b,0x70,0x04,0x00 = mov	%d0, 71
+0x3b,0x10,0x06,0x00 = mov	%d0, 97
+0x3b,0x10,0x04,0x00 = mov	%d0, 65
+0x8f,0x0a,0x02,0x11 = and	%d1, %d10, 32
+0xab,0x69,0x80,0x91 = sel	%d9, %d1, %d9, 6
+0x02,0xf6           = mov	%d6, %d15
+0x3c,0x2c           = j	0x58
+0x3b,0x20,0x07,0x00 = mov	%d0, 114
+0xfe,0x08           = jne	%d15, %d0, 0x30
+0x6f,0x6a,0x08,0x00 = jz.t	%d10, 6, 0x10
+0x09,0xf0,0x3c,0xfa = ld.q	%d0, [%a15]-4
+0x8f,0x0a,0x02,0xf1 = and	%d15, %d10, 32
+0xea,0x69           = cmovn	%d9, %d15, 6
+0x4b,0xf0,0x51,0xf1 = q31tof	%d15, %d0, %d15
+0x3b,0x60,0x06,0x60 = mov	%d6, 102
+0x3b,0x20,0x05,0x00 = mov	%d0, 82
+0xfe,0x09           = jne	%d15, %d0, 0x32
+# 0x09,0xf4,0x78,0xf9 = ld.d	%e4,[%a15]-8
+0x6d,0xff,0x32,0xd5 = call	-0x559c
+# 0x74,0xa2           = st.w	[%sp],%d2
+0x02,0xa7           = mov	%d7, %d10
+0x6d,0xff,0x2b,0xfa = call	-0xbaa
+0x1d,0xff,0x4d,0xfe = j	-0x366
+0x3b,0x00,0x07,0x00 = mov	%d0, 112
+0x5f,0x0f,0x5d,0x80 = jne	%d15, %d0, 0xba
+0x6f,0x8a,0x45,0x00 = jz.t	%d10, 8, 0x8a
+0x6f,0x0a,0x0e,0x80 = jnz.t	%d10, 0, 0x1c
+0xda,0x11           = mov	%d15, 17
+0x6d,0x00,0x91,0x00 = call	0x122
+0x3f,0x8f,0xf8,0xff = jlt.u	%d15, %d8, -0x10
+0xa0,0x3e           = mov.a	%a14, 3
+# 0x09,0xff,0x3f,0xf4 = ld.b	%d15,[+%a15]-1
+0x37,0x0f,0x68,0x40 = extr.u	%d4, %d15, 0, 8
+0x6d,0x00,0x00,0x01 = call	0x200
+0xfc,0xe7           = loop	%a14, -0x12
+0x3b,0xa0,0x03,0x40 = mov	%d4, 58
+0x6d,0x00,0x79,0x00 = call	0xf2
+0x49,0xff,0x04,0x0a = lea	%a15, [%a15]4
+0x6d,0x00,0xeb,0x00 = call	0x1d6
+0x6d,0x00,0x62,0x00 = call	0xc4
+0x1d,0xff,0x04,0xfe = j	-0x3f8
+0x02,0x45           = mov	%d5, %d4
+0x8f,0x2a,0x40,0x71 = or	%d7, %d10, 2
+# 0x89,0xa0,0x40,0x09 = st.d	[%sp],%e0
+0x3b,0x80,0x07,0x60 = mov	%d6, 120
+0x6d,0x00,0xdf,0x00 = call	0x1be
+0x1d,0xff,0xee,0xfd = j	-0x424
+0x3b,0xe0,0x06,0x00 = mov	%d0, 110
+0x5f,0x0f,0x37,0x80 = jne	%d15, %d0, 0x6e
+0x0f,0x0a,0x80,0xf0 = and	%d15, %d10, %d0
+0x6f,0x9a,0x0e,0x00 = jz.t	%d10, 9, 0x1c
+# 0x09,0xff,0xbc,0xf9 = ld.a	%a15,[%a15]-4
+# 0x09,0xa0,0x08,0x09 = ld.w	%d0,[%sp]8
+# 0x89,0xf0,0x40,0x09 = st.d	[%a15],%e0
+0x1d,0xff,0xd7,0xfd = j	-0x452
+0x7e,0xaa           = jne	%d15, %d10, 0x14
+0x1d,0xff,0xc9,0xfd = j	-0x46e
+0x5f,0x0a,0x0b,0x80 = jne	%d10, %d0, 0x16
+0x1d,0xff,0xbe,0xfd = j	-0x484
+0x1d,0xff,0xb5,0xfd = j	-0x496
+0xda,0x19           = mov	%d15, 25
+# 0x59,0xff,0xcc,0x10 = st.w	[%a15]3148
+# 0x09,0xa2,0x08,0x09 = ld.w	%d2,[%sp]8
+0x6d,0x00,0xb8,0x01 = call	0x370
+0x6f,0x08,0x19,0x80 = jnz.t	%d8, 0, 0x32
+0x6d,0xff,0x42,0xfe = call	-0x37c
+0x3f,0xfa,0xf9,0x7f = jlt	%d10, %d15, -0xe
+0x3f,0xf9,0xf7,0x7f = jlt	%d9, %d15, -0x12
+0xc2,0xf9           = add	%d9, -1
+# 0x09,0xf4,0x01,0x00 = ld.b	%d4,[%a15+]1
+0xdf,0x04,0x11,0x00 = jeq	%d4, 0, 0x22
+0x6d,0xff,0x33,0xfe = call	-0x39a
+0x8a,0xff           = cadd	%d15, %d15, -1
+0xdf,0x09,0xf6,0xff = jne	%d9, 0, -0x14
+0x6d,0xff,0x28,0xfe = call	-0x3b0
+0xee,0xf9           = jnz	%d15, -0xe
+0x02,0x6e           = mov	%d14, %d6
+0xda,0x58           = mov	%d15, 88
+0x02,0x79           = mov	%d9, %d7
+# 0x09,0xac,0x60,0x09 = ld.d	%e12,[%sp]32
+0x5f,0xef,0x73,0x00 = jeq	%d15, %d14, 0xe6
+0xda,0x64           = mov	%d15, 100
+0x3e,0xed           = jeq	%d15, %d14, 0x1a
+0xda,0x69           = mov	%d15, 105
+0x3e,0xeb           = jeq	%d15, %d14, 0x16
+0xda,0x6f           = mov	%d15, 111
+0x5f,0xef,0x6c,0x00 = jeq	%d15, %d14, 0xd8
+0xda,0x75           = mov	%d15, 117
+0xbe,0xe4           = jeq	%d15, %d14, 0x28
+0xda,0x78           = mov	%d15, 120
+0x5f,0xef,0x67,0x00 = jeq	%d15, %d14, 0xce
+0x1d,0x00,0xed,0x00 = j	0x1da
+0x0b,0x0c,0x50,0xf1 = ge.u	%d15, %d12, %d0
+0x0b,0x1d,0x00,0xf2 = and.eq	%d15, %d13, %d1
+0x0b,0xd1,0x90,0xf2 = or.lt	%d15, %d1, %d13
+0x3b,0xd0,0x02,0x80 = mov	%d8, 45
+0x0b,0xc0,0xc0,0xc0 = subx	%d12, %d0, %d12
+0x0b,0xd1,0xd0,0xd0 = subc	%d13, %d1, %d13
+0x0b,0xcd,0x10,0x48 = mov	%e4, %d13, %d12
+0x40,0xa4           = mov.aa	%a4, %sp
+0x3b,0xa0,0x00,0x60 = mov	%d6, 10
+0x6d,0xff,0x93,0xff = call	-0xda
+0xf6,0xb6           = jnz	%d11, 0xc
+0xba,0x0c           = eq	%d15, %d12, 0
+0x8b,0x0d,0x00,0xf4 = and.eq	%d15, %d13, 0
+0xdf,0x0f,0xdf,0x80 = jne	%d15, 0, 0x1be
+0x6d,0x00,0x9b,0x02 = call	0x536
+0x37,0x02,0x68,0xc0 = extr.u	%d12, %d2, 0, 8
+0xdf,0x08,0x11,0x80 = jne	%d8, 0, 0x22
+0x3e,0xe8           = jeq	%d15, %d14, 0x10
+0x8f,0x89,0x01,0x01 = and	%d0, %d9, 24
+0x3b,0xb0,0x02,0x80 = mov	%d8, 43
+0x8f,0x89,0x01,0xf1 = and	%d15, %d9, 24
+0x8b,0x0f,0x01,0xf2 = eq	%d15, %d15, 16
+0xab,0x08,0xa2,0x8f = seln	%d8, %d15, %d8, 32
+0x76,0x8c           = jz	%d8, 0x18
+0xab,0xfa,0x1f,0xaa = cadd	%d10, %d10, %d10, -1
+0x8f,0x39,0x00,0xf1 = and	%d15, %d9, 3
+0x6d,0xff,0x11,0xff = call	-0x1de
+0x6f,0x09,0x14,0x80 = jnz.t	%d9, 0, 0x28
+0x8f,0x29,0x00,0xf1 = and	%d15, %d9, 2
+0x86,0x4f           = sha	%d15, 4
+0x8b,0x0f,0x02,0xf0 = add	%d15, %d15, 32
+0x6d,0xff,0x01,0xff = call	-0x1fe
+0xc2,0xfa           = add	%d10, -1
+0x7f,0xab,0x04,0x00 = jge	%d11, %d10, 0x8
+0x3f,0xac,0xf8,0x7f = jlt	%d12, %d10, -0x10
+0x76,0x8e           = jz	%d8, 0x1c
+0x6d,0xff,0xf6,0xfe = call	-0x214
+0x61,0xff,0x0f,0xd5 = fcall	-0x55e2
+0x6d,0xff,0xf0,0xfe = call	-0x220
+0x3f,0xbc,0xf9,0x7f = jlt	%d12, %d11, -0xe
+0x1d,0x00,0x8a,0x00 = j	0x114
+0x8b,0xfe,0x26,0x82 = ne	%d8, %d14, 111
+0x8f,0x38,0x20,0xf0 = sha	%d15, %d8, 3
+0x8b,0x8f,0x00,0x60 = add	%d6, %d15, 8
+0x6d,0xff,0x3a,0xff = call	-0x18c
+0xfe,0xe3           = jne	%d15, %d14, 0x26
+0x40,0xa2           = mov.aa	%a2, %sp
+0x6e,0x10           = jz	%d15, 0x20
+0x8b,0xf0,0x1b,0xf0 = add	%d15, %d0, -65
+0x37,0x0f,0x68,0x10 = extr.u	%d1, %d15, 0, 8
+0x3f,0x1f,0x05,0x80 = jlt.u	%d15, %d1, 0xa
+0x8b,0x00,0x02,0xf0 = add	%d15, %d0, 32
+# 0x09,0x2f,0x01,0x04 = ld.b	%d15,[+%a2]1
+0xee,0xf2           = jnz	%d15, -0x1c
+0x6d,0x00,0x34,0x02 = call	0x468
+0x37,0x02,0x68,0xf0 = extr.u	%d15, %d2, 0, 8
+# 0x78,0x06           = st.w	[%sp]24,%d15
+0x8b,0x0c,0x20,0xf2 = ne	%d15, %d12, 0
+0x8b,0x0d,0x00,0xf5 = or.ne	%d15, %d13, 0
+0xee,0x0a           = jnz	%d15, 0x14
+0xdf,0x08,0x6a,0x80 = jne	%d8, 0, 0xd4
+0x6f,0x29,0x68,0x00 = jz.t	%d9, 2, 0xd0
+0xbb,0xb0,0xff,0xff = mov.u	%d15, 65531
+0x26,0xf9           = and	%d9, %d15
+0x6f,0x29,0x1b,0x00 = jz.t	%d9, 2, 0x36
+0x6f,0x19,0x13,0x00 = jz.t	%d9, 1, 0x26
+0x61,0xff,0xcd,0xd4 = fcall	-0x5666
+0x6d,0xff,0xae,0xfe = call	-0x2a4
+0x02,0xe4           = mov	%d4, %d14
+0x6d,0xff,0xa7,0xfe = call	-0x2b2
+0x7e,0xe5           = jne	%d15, %d14, 0xa
+# 0x58,0x06           = ld.w	%d15,[%sp]24
+0x3f,0xbf,0x03,0x00 = jlt	%d15, %d11, 0x6
+0x92,0x1b           = add	%d11, %d15, 1
+0x6f,0x29,0x09,0x00 = jz.t	%d9, 2, 0x12
+0x76,0x87           = jz	%d8, 0xe
+0xc2,0x2b           = add	%d11, 2
+0xc2,0x2f           = add	%d15, 2
+0x6f,0x09,0x15,0x80 = jnz.t	%d9, 0, 0x2a
+0x8b,0x0f,0x02,0xc0 = add	%d12, %d15, 32
+0x6d,0xff,0x84,0xfe = call	-0x2f8
+0x7f,0xab,0x05,0x00 = jge	%d11, %d10, 0xa
+0x3f,0xaf,0xf7,0x7f = jlt	%d15, %d10, -0x12
+0x6f,0x29,0x19,0x00 = jz.t	%d9, 2, 0x32
+0xdf,0x08,0x17,0x00 = jeq	%d8, 0, 0x2e
+0x61,0xff,0x95,0xd4 = fcall	-0x56d6
+0x6d,0xff,0x76,0xfe = call	-0x314
+0x6d,0xff,0x6f,0xfe = call	-0x322
+0x61,0xff,0x86,0xd4 = fcall	-0x56f4
+0x6d,0xff,0x67,0xfe = call	-0x332
+0x3f,0xbf,0xf8,0x7f = jlt	%d15, %d11, -0x10
+0xbb,0xf0,0xf7,0x4f = mov.u	%d4, 65407
+0xbb,0xf0,0xff,0x6f = mov.u	%d6, 65535
+0x26,0x94           = and	%d4, %d9
+0x02,0xa5           = mov	%d5, %d10
+0x9b,0xf6,0xff,0x67 = addih	%d6, %d6, 32767
+0x3b,0x00,0x03,0x40 = mov	%d4, 48
+# 0x54,0x5f           = ld.w	%d15,[%a5]
+# 0x74,0x5f           = st.w	[%a5],%d15
+0x49,0xfd,0x16,0x0a = lea	%a13, [%a15]22
+0x02,0x68           = mov	%d8, %d6
+# 0x34,0xdf           = st.b	[%a13],%d15
+0x02,0x86           = mov	%d6, %d8
+0x0b,0xab,0x10,0x48 = mov	%e4, %d11, %d10
+0x6d,0xff,0x07,0xd5 = call	-0x55f2
+0x23,0x82,0x0a,0x0a = msub	%d0, %d10, %d2, %d8
+0x0b,0x23,0x10,0xa8 = mov	%e10, %d3, %d2
+0x8b,0xa0,0x60,0xf2 = lt.u	%d15, %d0, 10
+0xca,0x70           = caddn	%d0, %d15, 7
+0x8b,0x00,0x03,0xf0 = add	%d15, %d0, 48
+# 0x89,0xdf,0x3f,0xf4 = st.b	[+%a13]-1,%d15
+0x8b,0x02,0x20,0xf2 = ne	%d15, %d2, 0
+0x8b,0x03,0x00,0xf5 = or.ne	%d15, %d3, 0
+0xee,0xeb           = jnz	%d15, -0x2a
+# 0x24,0xff           = st.b	[%a15+],%d15
+0xee,0xfe           = jnz	%d15, -0x4
+0x40,0xc2           = mov.aa	%a2, %a12
+0x8f,0xc8,0x3f,0x40 = sha	%d4, %d8, -4
+0x0b,0x4f,0x20,0x01 = lt	%d0, %d15, %d4
+0xda,0x37           = mov	%d15, 55
+0xab,0x0f,0x83,0xf0 = sel	%d15, %d0, %d15, 48
+0x42,0xf4           = add	%d4, %d15
+0x6d,0xff,0x75,0xff = call	-0x116
+0x8f,0xf8,0x00,0x01 = and	%d0, %d8, 15
+0x0b,0x0f,0x20,0x11 = lt	%d1, %d15, %d0
+0xab,0x0f,0x83,0x41 = sel	%d4, %d1, %d15, 48
+0x42,0x04           = add	%d4, %d0
+0x1d,0xff,0x68,0xff = j	-0x130
+0x6d,0xff,0xbd,0xf9 = call	-0xc86
+0x20,0x50           = sub.a	%sp, 80
+# 0x89,0xa4,0x38,0x09 = st.w	[%sp]56,%d4
+# 0x89,0xa6,0x2c,0x09 = st.w	[%sp]44,%d6
+# 0x89,0xa7,0x34,0x09 = st.w	[%sp]52,%d7
+# 0x09,0xaa,0x10,0x19 = ld.w	%d10,[%sp]80
+# 0x78,0x0c           = st.w	[%sp]48,%d15
+# 0x89,0xa9,0x08,0x19 = st.w	[%sp]72,%d9
+# 0x89,0xa9,0x28,0x09 = st.w	[%sp]40,%d9
+0x02,0xa0           = mov	%d0, %d10
+# 0x89,0xa9,0x00,0x19 = st.w	[%sp]64,%d9
+0xb7,0x00,0x89,0xfb = insert	%d15, %d0, 0, 23, 9
+# 0x78,0x11           = st.w	[%sp]68,%d15
+0x37,0x00,0xe8,0xfb = extr.u	%d15, %d0, 23, 8
+# 0x78,0x08           = st.w	[%sp]32,%d15
+0x02,0x58           = mov	%d8, %d5
+0x02,0x9d           = mov	%d13, %d9
+0x8b,0xff,0x0f,0xc2 = eq	%d12, %d15, 255
+0x7b,0x00,0xf8,0xb3 = movh	%d11, 16256
+0x76,0xc6           = jz	%d12, 0xc
+# 0x58,0x11           = ld.w	%d15,[%sp]68
+0x02,0x9c           = mov	%d12, %d9
+# 0x09,0xad,0x30,0x09 = ld.w	%d13,[%sp]48
+# 0x58,0x08           = ld.w	%d15,[%sp]32
+# 0x78,0x13           = st.w	[%sp]76,%d15
+0xf6,0x8a           = jnz	%d8, 0x14
+# 0x58,0x0b           = ld.w	%d15,[%sp]44
+0x7e,0x03           = jne	%d15, %d0, 0x6
+# 0x58,0x0d           = ld.w	%d15,[%sp]52
+0x6f,0x5f,0x21,0x80 = jnz.t	%d15, 5, 0x42
+0x82,0x78           = mov	%d8, 7
+0x8f,0x3f,0x00,0x00 = sh	%d0, %d15, 3
+0x8f,0xc3,0x1f,0x10 = sh	%d1, %d3, -4
+0x77,0x23,0x00,0x0e = dextr	%d0, %d3, %d2, 28
+0x0b,0x01,0x10,0x28 = mov	%e2, %d1, %d0
+0xfb,0xf0,0x00,0x00 = mov	%e0, 15
+0xba,0x00           = eq	%d15, %d0, 0
+0x8b,0x01,0x00,0xf4 = and.eq	%d15, %d1, 0
+# 0x78,0x0f           = st.w	[%sp]60,%d15
+0x6d,0x00,0x14,0x08 = call	0x1028
+0x76,0x25           = jz	%d2, 0xa
+0xda,0x2d           = mov	%d15, 45
+0x67,0xaa,0xbf,0xaf = insn.t	%d10, %d10, 31, %d10, 31
+0x8f,0x8f,0x01,0x01 = and	%d0, %d15, 24
+0xda,0x2b           = mov	%d15, 43
+0x8b,0x00,0x01,0x02 = eq	%d0, %d0, 16
+# 0x58,0x0f           = ld.w	%d15,[%sp]60
+0xab,0x0f,0xa2,0xf0 = seln	%d15, %d0, %d15, 32
+# 0x09,0xa0,0x00,0x19 = ld.w	%d0,[%sp]64
+0xaa,0x10           = cmov	%d0, %d15, 1
+# 0x89,0xa0,0x00,0x19 = st.w	[%sp]64,%d0
+0xdf,0x0d,0x16,0x00 = jeq	%d13, 0, 0x2c
+0xd9,0xff,0xa0,0xea = lea	%a15, [%a15]-21600
+0x2e,0x37           = jz.t	%d15, 3, 0xe
+0xd9,0xff,0x24,0x00 = lea	%a15, [%a15]36
+0x3c,0x1b           = j	0x36
+0xd9,0xff,0x08,0x10 = lea	%a15, [%a15]72
+0xdf,0x0c,0x1d,0x00 = jeq	%d12, 0, 0x3a
+0x2e,0x36           = jz.t	%d15, 3, 0xc
+0xd9,0xff,0x0c,0x10 = lea	%a15, [%a15]76
+0xd9,0xff,0x10,0x10 = lea	%a15, [%a15]80
+# 0x58,0x10           = ld.w	%d15,[%sp]64
+0xbb,0x90,0xff,0x0f = mov.u	%d0, 65529
+0x92,0x39           = add	%d9, %d15, 3
+# 0x78,0x0d           = st.w	[%sp]52,%d15
+0x1d,0x00,0x8c,0x01 = j	0x318
+0x5f,0x0f,0x27,0x80 = jne	%d15, %d0, 0x4e
+0xab,0x1f,0x18,0xff = cadd	%d15, %d15, %d15, -127
+0x92,0x30           = add	%d0, %d15, 3
+0xf6,0x83           = jnz	%d8, 0x6
+0x2e,0x22           = jz.t	%d15, 2, 0x4
+0x42,0x80           = add	%d0, %d8
+0x3b,0xc0,0xf9,0x1f = mov	%d1, -100
+0xc2,0x20           = add	%d0, 2
+0x7f,0xf1,0x06,0x00 = jge	%d1, %d15, 0xc
+0x3b,0x40,0x06,0x10 = mov	%d1, 100
+0x3f,0x1f,0x04,0x00 = jlt	%d15, %d1, 0x8
+0x3b,0x60,0xff,0x1f = mov	%d1, -10
+0x3b,0xa0,0x00,0x10 = mov	%d1, 10
+# 0x58,0x0c           = ld.w	%d15,[%sp]48
+0x12,0x09           = add	%d9, %d15, %d0
+0x1d,0x00,0x5f,0x01 = j	0x2be
+0x49,0xaf,0x0a,0x0a = lea	%a15, [%sp]10
+0x6e,0x75           = jz	%d15, 0xea
+0x49,0xa4,0x14,0x0a = lea	%a4, [%sp]20
+0x6d,0x00,0xd0,0x08 = call	0x11a0
+# 0x09,0xac,0x14,0x09 = ld.w	%d12,[%sp]20
+0x37,0x0c,0xe8,0xfb = extr.u	%d15, %d12, 23, 8
+0x6e,0x55           = jz	%d15, 0xaa
+0xbb,0xf0,0x28,0xec = mov.u	%d14, 49807
+0x49,0xae,0x13,0x0a = lea	%a14, [%sp]19
+0x7b,0x00,0x12,0xd4 = movh	%d13, 16672
+0x9b,0x5e,0xcf,0xe3 = addih	%d14, %d14, 15605
+0x3c,0x3f           = j	0x7e
+0x49,0xa2,0x0a,0x0a = lea	%a2, [%sp]10
+0x7d,0x2e,0x0c,0x80 = jne.a	%a14, %a2, 0x18
+0x49,0xaf,0x12,0x0a = lea	%a15, [%sp]18
+0xa0,0x72           = mov.a	%a2, 7
+# 0x09,0xf0,0x3f,0xf4 = ld.b	%d0,[+%a15]-1
+# 0x89,0xe0,0x3f,0xf4 = st.b	[+%a14]-1
+0xfc,0x2c           = loop	%a2, -0x8
+# 0x58,0x05           = ld.w	%d15,[%sp]20
+0x9b,0xc0,0xdc,0x03 = addih	%d0, %d0, 15820
+0x4b,0x0f,0x41,0x40 = mul.f	%d4, %d15, %d0
+0x6d,0x00,0xa7,0x08 = call	0x114e
+# 0x89,0xa2,0x06,0x09 = st.w	[%sp]6,%d2
+0xdf,0x09,0x14,0x80 = jne	%d9, 0, 0x28
+0x6b,0x0e,0x21,0xf2 = add.f	%d15, %d2, %d14
+0x4b,0xdb,0x41,0xb0 = mul.f	%d11, %d11, %d13
+0x4b,0xdf,0x41,0x40 = mul.f	%d4, %d15, %d13
+0x6d,0xff,0x22,0xfe = call	-0x3bc
+0x76,0x2a           = jz	%d2, 0x14
+0x4b,0xbc,0x51,0x40 = div.f	%d4, %d12, %d11
+0x6d,0x00,0x93,0x08 = call	0x1126
+# 0x09,0xaf,0x06,0x09 = ld.w	%d15,[%sp]6
+0x6b,0x0e,0x21,0xff = add.f	%d15, %d15, %d14
+0x6d,0xff,0x10,0xfe = call	-0x3e0
+0x8b,0x02,0x03,0xf0 = add	%d15, %d2, 48
+# 0x89,0xef,0x3f,0xf4 = st.b	[+%a14]-1,%d15
+# 0x58,0x0a           = ld.w	%d15,[%sp]40
+# 0x78,0x0a           = st.w	[%sp]40,%d15
+0x37,0x0f,0xe8,0xfb = extr.u	%d15, %d15, 23, 8
+0xee,0xbf           = jnz	%d15, -0x82
+# 0x04,0xef           = ld.bu	%d15,[%a14+]
+0x49,0xa2,0x13,0x0a = lea	%a2, [%sp]19
+0x01,0x2e,0x20,0xf4 = lt.a	%d15, %a14, %a2
+0xee,0xfa           = jnz	%d15, -0xc
+0x4b,0x0a,0x01,0xf0 = cmp.f	%d15, %d10, %d0
+0x6f,0x2f,0x12,0x00 = jz.t	%d15, 2, 0x24
+0x7b,0x00,0x12,0x04 = movh	%d0, 16672
+0x4b,0x0a,0x41,0xa0 = mul.f	%d10, %d10, %d0
+0x4b,0x0a,0x41,0xf0 = mul.f	%d15, %d10, %d0
+# 0x89,0xaf,0x06,0x09 = st.w	[%sp]6,%d15
+0x4b,0xbf,0x01,0xf0 = cmp.f	%d15, %d15, %d11
+0x6f,0x0f,0xf5,0xff = jnz.t	%d15, 0, -0x16
+0x3b,0x60,0x06,0x10 = mov	%d1, 102
+0x02,0x80           = mov	%d0, %d8
+0x3e,0x14           = jeq	%d15, %d1, 0x8
+0x3b,0x60,0x04,0x10 = mov	%d1, 70
+0x7e,0x13           = jne	%d15, %d1, 0x6
+0x12,0x80           = add	%d0, %d15, %d8
+0x3b,0x50,0x06,0x10 = mov	%d1, 101
+0x3b,0x50,0x04,0x10 = mov	%d1, 69
+0x7e,0x12           = jne	%d15, %d1, 0x4
+0xce,0x03           = jgez	%d0, 0x6
+0x8b,0x70,0x00,0xf3 = min	%d15, %d0, 7
+0x10,0xa2           = addsc.a	%a2, %sp, %d15, 0
+0x49,0x2e,0x0a,0x0a = lea	%a14, [%a2]10
+0x7b,0x00,0x12,0xf4 = movh	%d15, 16672
+0x49,0xa4,0x06,0x0a = lea	%a4, [%sp]6
+0x4b,0xfa,0x41,0x40 = mul.f	%d4, %d10, %d15
+0x6d,0x00,0x3d,0x08 = call	0x107a
+# 0x09,0xa4,0x06,0x09 = ld.w	%d4,[%sp]6
+0x6d,0xff,0xbf,0xfd = call	-0x482
+0x01,0xfe,0x20,0xf4 = lt.a	%d15, %a14, %a15
+0x01,0x2f,0x20,0xf4 = lt.a	%d15, %a15, %a2
+0xee,0xe9           = jnz	%d15, -0x2e
+# 0x09,0xef,0x00,0x08 = ld.b	%d15,[%a14]
+0x40,0xef           = mov.aa	%a15, %a14
+0xc2,0x5f           = add	%d15, 5
+0x01,0xef,0x30,0xf4 = ge.a	%d15, %a15, %a14
+# 0x09,0xef,0x3f,0xf4 = ld.b	%d15,[+%a14]-1
+# 0x34,0xef           = st.b	[%a14],%d15
+0x49,0xef,0x01,0x0a = lea	%a15, [%a14]1
+# 0x09,0xe0,0x00,0x08 = ld.b	%d0,[%a14]
+0xda,0x39           = mov	%d15, 57
+0x3f,0x0f,0xeb,0x7f = jlt	%d15, %d0, -0x2a
+# 0x89,0xf9,0x3f,0xf0 = st.b	[%a15+]-1,%d9
+# 0x09,0xf0,0x00,0x08 = ld.b	%d0,[%a15]
+0x5f,0x0f,0xf6,0x7f = jeq	%d15, %d0, -0x14
+0x5f,0x0f,0x3c,0x00 = jeq	%d15, %d0, 0x78
+0x5f,0x0f,0x38,0x00 = jeq	%d15, %d0, 0x70
+0x3f,0xf8,0x04,0x00 = jlt	%d8, %d15, 0x8
+0xff,0xdf,0x33,0x00 = jge	%d15, -3, 0x66
+0x3b,0x50,0x06,0x20 = mov	%d2, 101
+# 0x09,0xa1,0x0a,0x08 = ld.b	%d1,[%sp]10
+0x3e,0x24           = jeq	%d15, %d2, 0x8
+0x3b,0x50,0x04,0x20 = mov	%d2, 69
+0x7e,0x2c           = jne	%d15, %d2, 0x18
+0x49,0xaf,0x0b,0x0a = lea	%a15, [%sp]11
+0xae,0x22           = jnz.t	%d15, 2, 0x4
+0x76,0x15           = jz	%d1, 0xa
+0x8b,0xf8,0x1f,0x20 = add	%d2, %d8, -1
+0x2e,0x23           = jz.t	%d15, 2, 0x6
+0xb0,0x1f           = add.a	%a15, 1
+0xc2,0x11           = add	%d1, 1
+0x3f,0x21,0xf9,0x7f = jlt	%d1, %d2, -0xe
+0x8b,0x40,0x00,0x90 = add	%d9, %d0, 4
+0x3c,0x45           = j	0x8a
+0x7e,0x0f           = jne	%d15, %d0, 0x1e
+# 0x09,0xa0,0x28,0x09 = ld.w	%d0,[%sp]40
+0xfa,0x10           = lt	%d15, %d0, 1
+0xab,0x10,0xa0,0x9f = seln	%d9, %d15, %d0, 1
+0x42,0xf9           = add	%d9, %d15
+0xf6,0x84           = jnz	%d8, 0x8
+0x6f,0x2f,0x34,0x00 = jz.t	%d15, 2, 0x68
+0x1a,0x89           = add	%d15, %d9, %d8
+0x92,0x19           = add	%d9, %d15, 1
+0x3c,0x30           = j	0x60
+0x4e,0xf4           = jgtz	%d15, 0x8
+# 0x09,0xa1,0x28,0x09 = ld.w	%d1,[%sp]40
+0x12,0x19           = add	%d9, %d15, %d1
+0x02,0x1f           = mov	%d15, %d1
+0x76,0x12           = jz	%d1, 0x4
+0xab,0xf0,0x1f,0x00 = cadd	%d0, %d0, %d0, -1
+0xf6,0x04           = jnz	%d0, 0x8
+0x6f,0x2f,0x17,0x00 = jz.t	%d15, 2, 0x2e
+0x76,0x07           = jz	%d0, 0xe
+0xff,0x1f,0xfc,0x7f = jge	%d15, 1, -0x8
+0x16,0x04           = and	%d15, 4
+0x2b,0x09,0x00,0x9f = cadd	%d9, %d15, %d9, %d0
+0x61,0xff,0x77,0xda = fcall	-0x4b12
+# 0x09,0xa4,0x3c,0x09 = ld.w	%d4,[%sp]60
+0x6d,0x00,0x44,0x04 = call	0x888
+0xbd,0x0f,0x1a,0x80 = jnz.a	%a15, 0x34
+0xfe,0x02           = jne	%d15, %d0, 0x24
+0x61,0xff,0x4c,0xda = fcall	-0x4b68
+0x6d,0x00,0x2f,0x04 = call	0x85e
+0x8b,0x7f,0x01,0x40 = add	%d4, %d15, 23
+0x6d,0x00,0x29,0x04 = call	0x852
+# 0x78,0x12           = st.w	[%sp]72,%d15
+0x6f,0x0f,0x16,0x80 = jnz.t	%d15, 0, 0x2c
+# 0x58,0x0e           = ld.w	%d15,[%sp]56
+0xa2,0x9f           = sub	%d15, %d9
+0x61,0xff,0x4d,0xda = fcall	-0x4b66
+0x16,0x02           = and	%d15, 2
+0x8b,0x0f,0x02,0x40 = add	%d4, %d15, 32
+0x6d,0x00,0x15,0x04 = call	0x82a
+# 0x78,0x0e           = st.w	[%sp]56,%d15
+0xff,0x1f,0xf1,0x7f = jge	%d15, 1, -0x1e
+0x6e,0x08           = jz	%d15, 0x10
+0x61,0xff,0x3a,0xda = fcall	-0x4b8c
+0x6d,0x00,0x07,0x04 = call	0x80e
+0xbc,0xfa           = jz.a	%a15, 0x14
+0x6d,0x00,0x10,0x04 = call	0x820
+0xc2,0x3f           = add	%d15, 3
+0x1d,0x00,0x8a,0x01 = j	0x314
+0x5f,0x0f,0x9f,0x80 = jne	%d15, %d0, 0x13e
+0x8f,0x28,0x20,0x00 = sha	%d0, %d8, 2
+# 0x58,0x13           = ld.w	%d15,[%sp]76
+0x8b,0x70,0x01,0x01 = rsub	%d0, %d0, 23
+0x8b,0x1f,0x03,0xa1 = rsub	%d10, %d15, 49
+0xbf,0x10,0x22,0x00 = jlt	%d0, 1, 0x44
+0xda,0x17           = mov	%d15, 23
+0x7f,0xf0,0x08,0x00 = jge	%d0, %d15, 0x10
+0x0f,0x02,0x10,0x20 = sha	%d2, %d2, %d0
+0x0f,0x02,0x00,0xf0 = sh	%d15, %d2, %d0
+0xc6,0xf2           = xor	%d2, %d15
+0xf6,0x14           = jnz	%d1, 0x8
+0xa6,0x2f           = or	%d15, %d2
+0xef,0x7f,0x06,0x00 = jz.t	%d15, 23, 0xc
+0x3b,0x20,0x03,0xa0 = mov	%d10, 50
+# 0x58,0x12           = ld.w	%d15,[%sp]72
+0x61,0xff,0xe0,0xd9 = fcall	-0x4c40
+0x6d,0x00,0xbd,0x03 = call	0x77a
+0x61,0xff,0xe9,0xd9 = fcall	-0x4c2e
+0x6d,0x00,0xb7,0x03 = call	0x76e
+0x2e,0x25           = jz.t	%d15, 2, 0xa
+0x61,0xff,0xda,0xd9 = fcall	-0x4c4c
+0x6d,0x00,0xb0,0x03 = call	0x760
+0x3b,0x80,0x01,0xb0 = mov	%d11, 24
+# 0x54,0xd0           = ld.w	%d0,[%a13]
+0x8f,0x1f,0x00,0xa0 = sh	%d10, %d15, 1
+# 0x74,0xd0           = st.w	[%a13],%d0
+0xdf,0x0b,0x11,0x00 = jeq	%d11, 0, 0x22
+0xc2,0xcb           = add	%d11, -4
+0x02,0xb0           = mov	%d0, %d11
+0x32,0x50           = rsub	%d0
+0x0f,0x0a,0x00,0xf0 = sh	%d15, %d10, %d0
+0x8b,0x0f,0x03,0x40 = add	%d4, %d15, 48
+0x7f,0x4f,0x06,0x00 = jge	%d15, %d4, 0xc
+0x8b,0x6f,0x1c,0xf0 = add	%d15, %d15, -58
+0x6d,0x00,0x91,0x03 = call	0x722
+0xff,0x18,0xe9,0x7f = jge	%d8, 1, -0x2e
+0x8b,0xff,0x00,0x40 = add	%d4, %d15, 15
+0x6d,0x00,0x88,0x03 = call	0x710
+0xce,0xf6           = jgez	%d15, 0xc
+0x3b,0xd0,0x02,0x40 = mov	%d4, 45
+0x3b,0xb0,0x02,0x40 = mov	%d4, 43
+0x6d,0x00,0x7c,0x03 = call	0x6f8
+0x42,0xf0           = add	%d0, %d15
+# 0x34,0xf1           = st.b	[%a15],%d1
+0x4b,0x1f,0x01,0x22 = div	%e2, %d15, %d1
+0x8b,0x03,0x03,0xf0 = add	%d15, %d3, 48
+# 0x09,0xa2,0x20,0x09 = ld.w	%d2,[%sp]32
+0x4b,0x12,0x01,0x22 = div	%e2, %d2, %d1
+# 0x89,0xa2,0x60,0x09 = st.d	[%sp]32,%e2
+0xdf,0x02,0xee,0xff = jne	%d2, 0, -0x24
+0x6d,0x00,0x68,0x03 = call	0x6d0
+0x1d,0x00,0xe5,0x00 = j	0x1ca
+0x5f,0x0f,0x78,0x00 = jeq	%d15, %d0, 0xf0
+0x5f,0x0f,0x74,0x00 = jeq	%d15, %d0, 0xe8
+0xff,0xdf,0x6f,0x00 = jge	%d15, -3, 0xde
+# 0x09,0xa0,0x0a,0x08 = ld.b	%d0,[%sp]10
+0xab,0x1f,0x20,0xa0 = caddn	%d10, %d0, %d15, 1
+0x76,0x09           = jz	%d0, 0x12
+0x3b,0x70,0x06,0x10 = mov	%d1, 103
+0x3b,0x70,0x04,0x10 = mov	%d1, 71
+0x61,0xff,0x60,0xd9 = fcall	-0x4d40
+0x76,0x06           = jz	%d0, 0xc
+0x37,0x00,0x68,0x40 = extr.u	%d4, %d0, 0, 8
+0x6d,0x00,0x27,0x03 = call	0x64e
+0xee,0x0b           = jnz	%d15, 0x16
+0xae,0x29           = jnz.t	%d15, 2, 0x12
+0x61,0xff,0x41,0xd9 = fcall	-0x4d7e
+0x6d,0x00,0x17,0x03 = call	0x62e
+0xf6,0x0a           = jnz	%d0, 0x14
+0xae,0x28           = jnz.t	%d15, 2, 0x10
+0x7e,0x1d           = jne	%d15, %d1, 0x1a
+0x61,0xff,0x35,0xd9 = fcall	-0x4d96
+0x76,0x05           = jz	%d0, 0xa
+0x6d,0x00,0xfd,0x02 = call	0x5fa
+0x3f,0x8b,0xe7,0x7f = jlt	%d11, %d8, -0x32
+0x61,0xff,0x26,0xd9 = fcall	-0x4db4
+0x8f,0xdf,0x0f,0x41 = and	%d4, %d15, 253
+0x6d,0x00,0xf2,0x02 = call	0x5e4
+0x0e,0xa4           = jltz	%d10, 0x8
+0x32,0x5a           = rsub	%d10
+0x6d,0x00,0xe4,0x02 = call	0x5c8
+0x61,0xff,0x02,0xd9 = fcall	-0x4dfc
+0x8b,0x00,0x03,0x40 = add	%d4, %d0, 48
+0x6d,0x00,0xdd,0x02 = call	0x5ba
+0x61,0xff,0xfb,0xd8 = fcall	-0x4e0a
+0x8b,0x01,0x03,0x40 = add	%d4, %d1, 48
+0x6d,0x00,0xd6,0x02 = call	0x5ac
+0x3c,0x62           = j	0xc4
+# 0x09,0xaa,0x28,0x09 = ld.w	%d10,[%sp]40
+0x4e,0xa8           = jgtz	%d10, 0x10
+0x61,0xff,0xe9,0xd8 = fcall	-0x4e2e
+0x6d,0x00,0xcc,0x02 = call	0x598
+0x6d,0x00,0xbf,0x02 = call	0x57e
+0xab,0xf8,0x1f,0x88 = cadd	%d8, %d8, %d8, -1
+0xff,0x1a,0xea,0x7f = jge	%d10, 1, -0x2c
+0x61,0xff,0xd2,0xd8 = fcall	-0x4e5c
+0x3b,0xe0,0x02,0x40 = mov	%d4, 46
+0x6d,0x00,0x95,0x02 = call	0x52a
+0x76,0x8b           = jz	%d8, 0x16
+0xff,0x1f,0xf5,0x7f = jge	%d15, 1, -0x16
+0x61,0xff,0xbd,0xd8 = fcall	-0x4e86
+# 0x04,0xf4           = ld.bu	%d4,[%a15+]
+0x6d,0x00,0x8b,0x02 = call	0x516
+0x76,0x83           = jz	%d8, 0x6
+0xee,0xf7           = jnz	%d15, -0x12
+0x2e,0x2b           = jz.t	%d15, 2, 0x16
+0x61,0xff,0x94,0xd8 = fcall	-0x4ed8
+0x6d,0x00,0x77,0x02 = call	0x4ee
+0xdf,0x08,0xf9,0xff = jne	%d8, 0, -0xe
+0x6d,0x00,0x69,0x02 = call	0x4d2
+0xff,0x1f,0xf7,0x7f = jge	%d15, 1, -0x12
+0x61,0x00,0x06,0x00 = fcall	0xc
+0x61,0x00,0x0e,0x00 = fcall	0x1c
+0x37,0x0a,0x68,0x00 = extr.u	%d0, %d10, 0, 8
+0x4b,0xf0,0x11,0x02 = div.u	%e0, %d0, %d15
+0x6d,0xff,0xeb,0xff = call	-0x2a
+# 0x09,0xff,0x01,0x00 = ld.b	%d15,[%a15+]1
+0xbc,0xf4           = jz.a	%a15, 0x8
+0x9d,0x00,0x00,0x00 = ja	0
+# 0x4c,0x42           = ld.w	%d15,[%a4]8
+0x7f,0xf0,0x06,0x80 = jge.u	%d0, %d15, 0xc
+# 0x34,0xf4           = st.b	[%a15],%d4
+# 0xec,0x41           = st.a	[%a4]4,%a15
+0xd9,0x22,0x8c,0xf0 = lea	%a2, [%a2]3020
+0x90,0x22           = addsc.a	%a2, %a2, %d15, 2
+0xee,0xf1           = jnz	%d15, -0x1e
+# 0x04,0x5f           = ld.bu	%d15,[%a5+]
+0x76,0x47           = jz	%d4, 0xe
+0xdf,0x04,0xfd,0xff = jne	%d4, 0, -0x6
+0xee,0xff           = jnz	%d15, -0x2
+0x01,0xf4,0x20,0xf0 = sub.a	%a15, %a4, %a15
+0xc2,0xf2           = add	%d2, -1
+0x3c,0xff           = j	-0x2
+0x8f,0x14,0x1e,0x20 = sh	%d2, %d4, -31
+0x37,0x0f,0xe8,0x1b = extr.u	%d1, %d15, 23, 8
+0x8f,0x1f,0x1e,0x00 = sh	%d0, %d15, -31
+0x7e,0x17           = jne	%d15, %d1, 0xe
+# 0x74,0x44           = st.w	[%a4],%d4
+0xb7,0x0f,0x89,0xfb = insert	%d15, %d15, 0, 23, 9
+0x6e,0x12           = jz	%d15, 0x24
+0x8f,0xf0,0x01,0x50 = sh	%d5, %d0, 31
+0x7f,0xf1,0x09,0x00 = jge	%d1, %d15, 0x12
+0xb7,0x0f,0x81,0xff = insert	%d15, %d15, 0, 31, 1
+0xa6,0x5f           = or	%d15, %d5
+0xda,0x96           = mov	%d15, 150
+0x3f,0xf1,0x0a,0x00 = jlt	%d1, %d15, 0x14
+0x8f,0xf0,0x01,0x20 = sh	%d2, %d0, 31
+0xa6,0xf2           = or	%d2, %d15
+0xb7,0x04,0x89,0x0b = insert	%d0, %d4, 0, 23, 9
+0x8f,0x71,0x01,0x20 = sh	%d2, %d1, 23
+0x8b,0x61,0x09,0x11 = rsub	%d1, %d1, 150
+0x0f,0x13,0x00,0x30 = sh	%d3, %d3, %d1
+0xb7,0x00,0x89,0x0b = insert	%d0, %d0, 0, 23, 9
+0xa6,0x52           = or	%d2, %d5
+0xa6,0x02           = or	%d2, %d0
+# 0x74,0x42           = st.w	[%a4],%d2
+0x6b,0x02,0x31,0xf4 = sub.f	%d15, %d4, %d2
+0xb7,0x0f,0x81,0x2f = insert	%d2, %d15, 0, 31, 1
+0x8f,0x84,0x1e,0xf0 = sh	%d15, %d4, -24
+0x8f,0x0f,0x08,0x01 = and	%d0, %d15, 128
+0xb7,0x04,0x08,0xfc = insert	%d15, %d4, 0, 24, 8
+0x37,0x04,0xe8,0x1b = extr.u	%d1, %d4, 23, 8
+0xb7,0x1f,0x81,0x2b = insert	%d2, %d15, 1, 23, 1
+0x7f,0xf1,0x04,0x80 = jge.u	%d1, %d15, 0x8
+0x7f,0x1f,0x04,0x80 = jge.u	%d15, %d1, 0x8
+0x8b,0x61,0x09,0xf1 = rsub	%d15, %d1, 150
+0x0f,0xf2,0x00,0x20 = sh	%d2, %d2, %d15
+0x37,0x02,0x48,0x20 = extr	%d2, %d2, 0, 8
+0x76,0x04           = jz	%d0, 0x8
+0x32,0x52           = rsub	%d2
+0x37,0x04,0xe8,0x0b = extr.u	%d0, %d4, 23, 8
+0xb7,0x1f,0x81,0x1b = insert	%d1, %d15, 1, 23, 1
+0x3f,0xf0,0x05,0x80 = jlt.u	%d0, %d15, 0xa
+0x7f,0x0f,0x04,0x80 = jge.u	%d15, %d0, 0x8
+0x8b,0x60,0x09,0xf1 = rsub	%d15, %d0, 150
+0x0f,0xf1,0x00,0x10 = sh	%d1, %d1, %d15
+0x37,0x01,0x70,0x20 = extr.u	%d2, %d1, 0, 16
+0x07,0x57,0xff,0xcf = xor.t	%d12, %d7, 31, %d5, 31
+0x87,0x55,0xbf,0xdf = or.t	%d13, %d5, 31, %d5, 31
+0xce,0x57           = jgez	%d5, 0xe
+0x46,0x05           = not	%d5
+0x46,0x04           = not	%d4
+0x8b,0x14,0x80,0x40 = addx	%d4, %d4, 1
+0x8b,0x05,0xa0,0x50 = addc	%d5, %d5, 0
+0xce,0x77           = jgez	%d7, 0xe
+0x46,0x07           = not	%d7
+0x46,0x06           = not	%d6
+0x8b,0x16,0x80,0x60 = addx	%d6, %d6, 1
+0x8b,0x07,0xa0,0x70 = addc	%d7, %d7, 0
+0x3a,0x26           = eq	%d15, %d6, %d2
+0x0b,0x27,0x00,0xf2 = and.eq	%d15, %d7, %d2
+0x3c,0x4f           = j	0x9e
+0x0b,0x64,0x30,0xf1 = lt.u	%d15, %d4, %d6
+0x0b,0x75,0x00,0xf2 = and.eq	%d15, %d5, %d7
+0x0b,0x75,0xa0,0xf2 = or.lt.u	%d15, %d5, %d7
+0x02,0x51           = mov	%d1, %d5
+0x3a,0x64           = eq	%d15, %d4, %d6
+0x3b,0x00,0x04,0xe0 = mov	%d14, 64
+0x0b,0x60,0x30,0xf1 = lt.u	%d15, %d0, %d6
+0x0b,0x71,0x00,0xf2 = and.eq	%d15, %d1, %d7
+0x0b,0x71,0xa0,0xf2 = or.lt.u	%d15, %d1, %d7
+0xde,0x10           = jne	%d15, 1, 0x20
+0x87,0x55,0x9f,0xff = and.t	%d15, %d5, 31, %d5, 31
+0x06,0x11           = sh	%d1, 1
+0x67,0x01,0x80,0x1f = ins.t	%d1, %d1, 0, %d0, 31
+0x8b,0x1f,0xe0,0x06 = sh.eq	%d0, %d15, 1
+0x02,0x59           = mov	%d9, %d5
+0x06,0x15           = sh	%d5, 1
+0x67,0x45,0x80,0x5f = ins.t	%d5, %d5, 0, %d4, 31
+0x06,0x14           = sh	%d4, 1
+0xc2,0xfe           = add	%d14, -1
+0x3c,0xeb           = j	-0x2a
+0x06,0xf0           = sh	%d0, -1
+0x67,0x10,0x1f,0x00 = ins.t	%d0, %d0, 31, %d1, 0
+0x06,0xf1           = sh	%d1, -1
+0xc2,0x1e           = add	%d14, 1
+0x7a,0xe8           = lt	%d15, %d8, %d14
+0x0b,0x60,0xc0,0xa0 = subx	%d10, %d0, %d6
+0x0b,0x71,0xd0,0xb0 = subc	%d11, %d1, %d7
+0x07,0xbb,0x9f,0xff = nand.t	%d15, %d11, 31, %d11, 31
+0x06,0x13           = sh	%d3, 1
+0x67,0x23,0x80,0x3f = ins.t	%d3, %d3, 0, %d2, 31
+0x8b,0x1f,0xe0,0x26 = sh.eq	%d2, %d15, 1
+0x02,0xb1           = mov	%d1, %d11
+0x3f,0xe8,0xe6,0x7f = jlt	%d8, %d14, -0x34
+0x76,0xc7           = jz	%d12, 0xe
+0x46,0x03           = not	%d3
+0x46,0x02           = not	%d2
+0x8b,0x12,0x80,0x20 = addx	%d2, %d2, 1
+0x8b,0x03,0xa0,0x30 = addc	%d3, %d3, 0
+0xdf,0x2d,0x0b,0x00 = jeq	%d13, 2, 0x16
+0x07,0x1d,0xe0,0xff = xor.t	%d15, %d13, 0, %d1, 31
+0x76,0xf7           = jz	%d15, 0xe
+0x46,0x01           = not	%d1
+0x46,0x00           = not	%d0
+0x8b,0x10,0x80,0x00 = addx	%d0, %d0, 1
+0x8b,0x01,0xa0,0x10 = addc	%d1, %d1, 0
+0x0f,0x05,0xd0,0x11 = cls	%d1, %d5
+0x17,0x45,0x80,0x01 = dextr	%d0, %d5, %d4, %d1
+0x0b,0x00,0xd0,0x01 = abss	%d0, %d0
+0x0f,0x00,0xb0,0x21 = clz	%d2, %d0
+0x42,0x21           = add	%d1, %d2
+0x8b,0x01,0x01,0x11 = rsub	%d1, %d1, 16
+0x0f,0x20,0x10,0x00 = sha	%d0, %d0, %d2
+0x6b,0x05,0x00,0x20 = pack	%d2, %e0, %d5
+0xd9,0xff,0x08,0x00 = lea	%a15, [%a15]8
+0xa0,0x04           = mov.a	%a4, 0
+0x1d,0x00,0x08,0x00 = j	0x10
+0xd9,0x44,0xa0,0xe5 = lea	%a4, [%a4]23456
+0x1d,0xff,0xb3,0xff = j	-0x9a
+0x6d,0xff,0xe8,0xff = call	-0x30
+0xd9,0xff,0x38,0x30 = lea	%a15, [%a15]248
+# 0xc4,0xf2           = ld.a	%a2,[%a15+]
+0xee,0xfc           = jnz	%d15, -0x8
+# 0xf4,0xa5           = st.a	[%sp],%a5
+# 0xc8,0x34           = ld.a	%a4,[%a15]12
+0x7d,0x24,0x04,0x00 = jeq.a	%a4, %a2, 0x8
+0x40,0xfd           = mov.aa	%a13, %a15
+0x6d,0xff,0x91,0xff = call	-0xde
+0x7d,0xef,0x03,0x00 = jeq.a	%a15, %a14, 0x6
+0x40,0xcd           = mov.aa	%a13, %a12
+0xd9,0x44,0xe8,0x10 = lea	%a4, [%a4]3176
+0x1d,0x00,0x1b,0x00 = j	0x36
+0xb7,0x6f,0x08,0xf0 = insert	%d15, %d15, 6, 0, 8
+0x6d,0xe8,0xbd,0x14 = call	-0x2fd686
+0x6d,0xe8,0x11,0x14 = call	-0x2fd7de
+0x6d,0xe8,0x91,0x0b = call	-0x2fe8de
+0xd9,0xff,0xc8,0x41 = lea	%a15, [%a15]7432
+0xd9,0xff,0xc4,0x31 = lea	%a15, [%a15]7364
+0xd9,0xff,0xc0,0x21 = lea	%a15, [%a15]7296
+0xd9,0xff,0xfc,0x01 = lea	%a15, [%a15]7228
+0xd9,0xff,0xb8,0xf1 = lea	%a15, [%a15]7160
+0xd9,0xff,0xb4,0xe1 = lea	%a15, [%a15]7092
+0xd9,0xff,0xce,0x61 = lea	%a15, [%a15]7566
+0xd9,0xff,0xcc,0x51 = lea	%a15, [%a15]7500
+0xd9,0xff,0x2c,0x80 = lea	%a15, [%a15]556
diff --git a/suite/MC/TriCore/tc110.s.cs b/suite/MC/TriCore/tc110.s.cs
new file mode 100644
index 0000000000..7d08bc3f66
--- /dev/null
+++ b/suite/MC/TriCore/tc110.s.cs
@@ -0,0 +1,625 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_110, None
+0x0b, 0x00, 0xc0, 0x01 = abs %d0, %d0
+0x0b, 0x00, 0xc0, 0x05 = abs.b %d0, %d0
+0x0b, 0x00, 0xc0, 0x07 = abs.h %d0, %d0
+0x0b, 0x00, 0xe0, 0x00 = absdif %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x01 = absdif %d0, %d0, 0
+0x0b, 0x00, 0xe0, 0x04 = absdif.b %d0, %d0, %d0
+0x0b, 0x00, 0xe0, 0x06 = absdif.h %d0, %d0, %d0
+0x0b, 0x00, 0xf0, 0x00 = absdifs %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x01 = absdifs %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x04 = absdifs.b %d0, %d0, %d0
+0x0b, 0x00, 0xf0, 0x06 = absdifs.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x01 = abss %d0, %d0
+0x0b, 0x00, 0xd0, 0x05 = abss.b %d0, %d0
+0x0b, 0x00, 0xd0, 0x07 = abss.h %d0, %d0
+0x1a, 0x00 = add %d15, %d0, %d0
+0x42, 0x00 = add %d0, %d0
+0x9a, 0x00 = add %d15, %d0, 0
+0xc2, 0x00 = add %d0, 0
+0x0b, 0x00, 0x00, 0x00 = add %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x00 = add %d0, %d0, 0
+0x01, 0x00, 0x10, 0x00 = add.a %a0, %a0, %a0
+0x0b, 0x00, 0x00, 0x04 = add.b %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x06 = add.h %d0, %d0, %d0
+0x0b, 0x00, 0x50, 0x00 = addc %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x00 = addc %d0, %d0, 0
+0x1b, 0x00, 0x00, 0x00 = addi %d0, %d0, 0
+0x9b, 0x00, 0x00, 0x00 = addih %d0, %d0, 0
+0x11, 0x00, 0x00, 0x00 = addih.a %a0, %a0, 0
+0x22, 0x00 = adds %d0, %d0
+0x0b, 0x00, 0x20, 0x00 = adds %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x00 = adds %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x04 = adds.b %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x04 = adds.bu %d0, %d0, %d0
+0x0b, 0x00, 0x20, 0x06 = adds.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x06 = adds.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x00 = adds.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x00 = adds.u %d0, %d0, 0
+0x10, 0x00 = addsc.a %a0, %d0, 0
+0x01, 0x00, 0x00, 0x06 = addsc.a %a0, %a0, %d0, 0
+0x01, 0x00, 0x20, 0x06 = addsc.at %a0, %a0, %d0
+0x0b, 0x00, 0x40, 0x00 = addx %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x00 = addx %d0, %d0, 0
+0x16, 0x00 = and %d0, %d0
+0x96, 0x00 = and %d15, 0
+0x0f, 0x00, 0x80, 0x00 = and %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x01 = and %d0, %d0, 0
+0x47, 0x00, 0x00, 0x00 = and.and.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x60, 0x00 = and.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x00, 0x02 = and.eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x04 = and.eq %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x02 = and.ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x04 = and.ge %d0, %d0, 0
+0x0b, 0x00, 0x50, 0x02 = and.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x04 = and.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x02 = and.lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x04 = and.lt %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x02 = and.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x04 = and.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x02 = and.ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x04 = and.ne %d0, %d0, 0
+0x47, 0x00, 0x40, 0x00 = and.nor.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x20, 0x00 = and.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x00, 0x00 = and.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xe0, 0x00 = andn %d0, %d0, %d0
+0x8f, 0x00, 0xc0, 0x01 = andn %d0, %d0, 0
+0x87, 0x00, 0x60, 0x00 = andn.t %d0, %d0, 0, %d0, 0
+0xc0, 0x00 = bisr 0
+0xad, 0x00, 0x00, 0x00 = bisr 0
+0x4b, 0x00, 0x00, 0x00 = bmerge %d0, %d0, %d0
+0x4b, 0x00, 0x00, 0x06 = bsplit %e0, %d0
+0x0a, 0x00 = cadd %d0, %d15, %d0
+0x8a, 0x00 = cadd %d0, %d15, 0
+0x2b, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, %d0
+0xab, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, 0
+0x21, 0x00, 0x00, 0x00 = cadd.a %a0, %d0, %a0, %a0
+0xa1, 0x00, 0x00, 0x00 = cadd.a %a0, %d0, %a0, 0
+0x4a, 0x00 = caddn %d0, %d15, %d0
+0xca, 0x00 = caddn %d0, %d15, 0
+0x2b, 0x00, 0x10, 0x00 = caddn %d0, %d0, %d0, %d0
+0xab, 0x00, 0x20, 0x00 = caddn %d0, %d0, %d0, 0
+0x21, 0x00, 0x10, 0x00 = caddn.a %a0, %d0, %a0, %a0
+0xa1, 0x00, 0x20, 0x00 = caddn.a %a0, %d0, %a0, 0
+0x6d, 0x00, 0x00, 0x00 = call 0
+0xed, 0x00, 0x00, 0x00 = calla 0
+0x2d, 0x00, 0x00, 0x00 = calli %a0
+0x0f, 0x00, 0xc0, 0x01 = clo %d0, %d0
+0x0f, 0x00, 0xd0, 0x03 = clo.b %d0, %d0
+0x0f, 0x00, 0xd0, 0x07 = clo.h %d0, %d0
+0x0f, 0x00, 0xd0, 0x01 = cls %d0, %d0
+0x0f, 0x00, 0xe0, 0x03 = cls.b %d0, %d0
+0x0f, 0x00, 0xe0, 0x07 = cls.h %d0, %d0
+0x0f, 0x00, 0xb0, 0x01 = clz %d0, %d0
+0x0f, 0x00, 0xc0, 0x03 = clz.b %d0, %d0
+0x0f, 0x00, 0xc0, 0x07 = clz.h %d0, %d0
+0x2a, 0x00 = cmov %d0, %d15, %d0
+0xaa, 0x00 = cmov %d0, %d15, 0
+0x6a, 0x00 = cmovn %d0, %d15, %d0
+0xea, 0x00 = cmovn %d0, %d15, 0
+0x2b, 0x00, 0x20, 0x00 = csub %d0, %d0, %d0, %d0
+0x21, 0x00, 0x20, 0x00 = csub.a %a0, %d0, %a0, %a0
+0x2b, 0x00, 0x30, 0x00 = csubn %d0, %d0, %d0, %d0
+0x21, 0x00, 0x30, 0x00 = csubn.a %a0, %d0, %a0, %a0
+0x00, 0xa0 = debug
+0x0d, 0x00, 0x00, 0x01 = debug
+0x77, 0x00, 0x00, 0x00 = dextr %d0, %d0, %d0, 0
+0x17, 0x00, 0x80, 0x00 = dextr %d0, %d0, %d0, %d0
+0x01, 0x00, 0x00, 0x05 = difsc.a %d0, %a0, %a0, 0
+0x0d, 0x00, 0x40, 0x03 = disable
+0x0d, 0x00, 0x80, 0x04 = dsync
+0x72, 0x00 = dvadj %e0, %d0
+0x2b, 0x00, 0x80, 0x00 = dvadj %e0, %e0, %d0
+0x4f, 0x00, 0x00, 0x00 = dvinit %e0, %d0, %d0
+0x4f, 0x00, 0x40, 0x00 = dvinit.b %e0, %d0, %d0
+0x4f, 0x00, 0x50, 0x00 = dvinit.bu %e0, %d0, %d0
+0x4f, 0x00, 0x20, 0x00 = dvinit.h %e0, %d0, %d0
+0x4f, 0x00, 0x30, 0x00 = dvinit.hu %e0, %d0, %d0
+0x4f, 0x00, 0x10, 0x00 = dvinit.u %e0, %d0, %d0
+0x32, 0x00 = dvstep %e0, %d0
+0x2b, 0x00, 0x90, 0x00 = dvstep %e0, %e0, %d0
+0xb2, 0x00 = dvstep.u %e0, %d0
+0x2b, 0x00, 0xa0, 0x00 = dvstep.u %e0, %e0, %d0
+0x0d, 0x00, 0x00, 0x03 = enable
+0x3a, 0x00 = eq %d15, %d0, %d0
+0xba, 0x00 = eq %d15, %d0, 0
+0x0b, 0x00, 0x00, 0x01 = eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x02 = eq %d0, %d0, 0
+0x01, 0x00, 0x00, 0x04 = eq.a %d0, %a0, %a0
+0x0b, 0x00, 0x00, 0x05 = eq.b %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x07 = eq.h %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x09 = eq.w %d0, %d0, %d0
+0x0b, 0x00, 0x60, 0x05 = eqany.b %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0a = eqany.b %d0, %d0, 0
+0x0b, 0x00, 0x60, 0x07 = eqany.h %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0e = eqany.h %d0, %d0, 0
+0x01, 0x00, 0x80, 0x04 = eqz.a %d0, %a0
+0x17, 0x00, 0x40, 0x00 = extr %d0, %d0, %e0
+0x37, 0x00, 0x40, 0x00 = extr %d0, %d0, 0, 0
+0x57, 0x00, 0x40, 0x00 = extr %d0, %d0, %d0, 0
+0x17, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %e0
+0x37, 0x00, 0x60, 0x00 = extr.u %d0, %d0, 0, 0
+0x57, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x01 = ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x02 = ge %d0, %d0, 0
+0x01, 0x00, 0x30, 0x04 = ge.a %d0, %a0, %a0
+0x0b, 0x00, 0x50, 0x01 = ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x02 = ge.u %d0, %d0, 0
+0x37, 0x00, 0x20, 0x00 = imask %e0, %d0, 0, 0
+0x57, 0x00, 0x20, 0x00 = imask %e0, %d0, %d0, 0
+0xb7, 0x00, 0x20, 0x00 = imask %e0, 0, 0, 0
+0xd7, 0x00, 0x20, 0x00 = imask %e0, 0, %d0, 0
+0x67, 0x00, 0x00, 0x00 = ins.t %d0, %d0, 0, %d0, 0
+0x17, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %e0
+0x37, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, 0, 0
+0x57, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %d0, 0
+0x97, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %e0
+0xb7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, 0, 0
+0xd7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %d0, 0
+0x67, 0x00, 0x20, 0x00 = insn.t %d0, %d0, 0, %d0, 0
+0x0d, 0x00, 0xc0, 0x04 = isync
+0x5c, 0x00 = j 0
+0x1d, 0x00, 0x00, 0x00 = j 0
+0x9d, 0x00, 0x00, 0x00 = ja 0
+0x1e, 0x00 = jeq %d15, %d0, 0
+0x6e, 0x00 = jeq %d15, 0, 0
+0x5f, 0x00, 0x00, 0x00 = jeq %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x00 = jeq %d0, 0, 0
+0x7d, 0x00, 0x00, 0x00 = jeq.a %a0, %a0, 0
+0x7f, 0x00, 0x00, 0x00 = jge %d0, %d0, 0
+0xff, 0x00, 0x00, 0x00 = jge %d0, 0, 0
+0x7f, 0x00, 0x00, 0x80 = jge.u %d0, %d0, 0
+0xff, 0x00, 0x00, 0x80 = jge.u %d0, 0, 0
+0xfe, 0x00 = jgez %d0, 0
+0x7e, 0x00 = jgtz %d0, 0
+0x3c, 0x00 = ji %a0
+0x2d, 0x00, 0x30, 0x00 = ji %a0
+0x5d, 0x00, 0x00, 0x00 = jl 0
+0xdd, 0x00, 0x00, 0x00 = jla 0
+0xbe, 0x00 = jlez %d0, 0
+0x2d, 0x00, 0x20, 0x00 = jli %a0
+0x3f, 0x00, 0x00, 0x00 = jlt %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x00 = jlt %d0, 0, 0
+0x3f, 0x00, 0x00, 0x80 = jlt.u %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x80 = jlt.u %d0, 0, 0
+0x3e, 0x00 = jltz %d0, 0
+0x9e, 0x00 = jne %d15, %d0, 0
+0xee, 0x00 = jne %d15, 0, 0
+0x5f, 0x00, 0x00, 0x80 = jne %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x80 = jne %d0, 0, 0
+0x7d, 0x00, 0x00, 0x80 = jne.a %a0, %a0, 0
+0x1f, 0x00, 0x00, 0x80 = jned %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x80 = jned %d0, 0, 0
+0x1f, 0x00, 0x00, 0x00 = jnei %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x00 = jnei %d0, 0, 0
+0xae, 0x00 = jnz %d15, 0
+0xde, 0x00 = jnz %d0, 0
+0x7c, 0x00 = jnz.a %a0, 0
+0xbd, 0x00, 0x00, 0x80 = jnz.a %a0, 0
+0x4e, 0x00 = jnz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x80 = jnz.t %d0, 0, 0
+0x2e, 0x00 = jz %d15, 0
+0x5e, 0x00 = jz %d0, 0
+0xbc, 0x00 = jz.a %a0, 0
+0xbd, 0x00, 0x00, 0x00 = jz.a %a0, 0
+0x0e, 0x00 = jz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x00 = jz.t %d0, 0, 0
+0x0c, 0x00 = ld.a %a0, [%a15]0
+0x28, 0x00 = ld.a %a15, [%a0]0
+0x64, 0x00 = ld.a %a0, [%a0+]
+0xb8, 0x00 = ld.a %a0, [%a0]
+0x99, 0x00, 0x00, 0x00 = ld.a %a0, [%a0]0
+0x09, 0x00, 0x80, 0x01 = ld.a %a0, [%a0+]0
+0x29, 0x00, 0x80, 0x01 = ld.a %a0, [%p0+r]
+0x09, 0x00, 0x80, 0x05 = ld.a %a0, [+%a0]0
+0x29, 0x00, 0x80, 0x05 = ld.a %a0, [%p0+c]0
+0x85, 0x00, 0x00, 0x08 = ld.a %a0, 0
+0x09, 0x00, 0x80, 0x09 = ld.a %a0, [%a0]0
+0x08, 0x00 = ld.b %d15, [%a0]0
+0x34, 0x00 = ld.b %d0, [%a15]0
+0x44, 0x00 = ld.b %d0, [%a0+]
+0x98, 0x00 = ld.b %d0, [%a0]
+0x05, 0x00, 0x00, 0x00 = ld.b %d0, 0
+0x09, 0x00, 0x00, 0x00 = ld.b %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x00 = ld.b %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x04 = ld.b %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x04 = ld.b %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x08 = ld.b %d0, [%a0]0
+0x58, 0x00 = ld.bu %d0, [%a0]
+0x88, 0x00 = ld.bu %d15, [%a0]0
+0xb4, 0x00 = ld.bu %d0, [%a15]0
+0xc4, 0x00 = ld.bu %d0, [%a0+]
+0x09, 0x00, 0x40, 0x00 = ld.bu %d0, [%a0+]0
+0x29, 0x00, 0x40, 0x00 = ld.bu %d0, [%p0+r]
+0x05, 0x00, 0x00, 0x04 = ld.bu %d0, 0
+0x09, 0x00, 0x40, 0x04 = ld.bu %d0, [+%a0]0
+0x29, 0x00, 0x40, 0x04 = ld.bu %d0, [%p0+c]0
+0x09, 0x00, 0x40, 0x08 = ld.bu %d0, [%a0]0
+0x09, 0x00, 0x40, 0x01 = ld.d %e0, [%a0+]0
+0x29, 0x00, 0x40, 0x01 = ld.d %e0, [%p0+r]
+0x85, 0x00, 0x00, 0x04 = ld.d %e0, 0
+0x09, 0x00, 0x40, 0x05 = ld.d %e0, [+%a0]0
+0x29, 0x00, 0x40, 0x05 = ld.d %e0, [%p0+c]0
+0x09, 0x00, 0x40, 0x09 = ld.d %e0, [%a0]0
+0x09, 0x00, 0xc0, 0x01 = ld.da %p0, [%a0+]0
+0x29, 0x00, 0xc0, 0x01 = ld.da %p0, [%p0+r]
+0x09, 0x00, 0xc0, 0x05 = ld.da %p0, [+%a0]0
+0x29, 0x00, 0xc0, 0x05 = ld.da %p0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x09 = ld.da %p0, [%a0]0
+0x85, 0x00, 0x00, 0x0c = ld.da %p0, 0
+0x24, 0x00 = ld.h %d0, [%a0+]
+0x48, 0x00 = ld.h %d15, [%a0]0
+0x74, 0x00 = ld.h %d0, [%a15]0
+0xd8, 0x00 = ld.h %d0, [%a0]
+0x09, 0x00, 0x80, 0x00 = ld.h %d0, [%a0+]0
+0x29, 0x00, 0x80, 0x00 = ld.h %d0, [%p0+r]
+0x09, 0x00, 0x80, 0x04 = ld.h %d0, [+%a0]0
+0x29, 0x00, 0x80, 0x04 = ld.h %d0, [%p0+c]0
+0x05, 0x00, 0x00, 0x08 = ld.h %d0, 0
+0x09, 0x00, 0x80, 0x08 = ld.h %d0, [%a0]0
+0x09, 0x00, 0xc0, 0x00 = ld.hu %d0, [%a0+]0
+0x29, 0x00, 0xc0, 0x00 = ld.hu %d0, [%p0+r]
+0x09, 0x00, 0xc0, 0x04 = ld.hu %d0, [+%a0]0
+0x29, 0x00, 0xc0, 0x04 = ld.hu %d0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x08 = ld.hu %d0, [%a0]0
+0x05, 0x00, 0x00, 0x0c = ld.hu %d0, 0
+0x45, 0x00, 0x00, 0x00 = ld.q %d0, 0
+0x09, 0x00, 0x00, 0x02 = ld.q %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x02 = ld.q %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x06 = ld.q %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x06 = ld.q %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x0a = ld.q %d0, [%a0]0
+0x38, 0x00 = ld.w %d0, [%a0]
+0xa4, 0x00 = ld.w %d0, [%a0+]
+0xc8, 0x00 = ld.w %d15, [%a0]0
+0xf4, 0x00 = ld.w %d0, [%a15]0
+0x19, 0x00, 0x00, 0x00 = ld.w %d0, [%a0]0
+0x85, 0x00, 0x00, 0x00 = ld.w %d0, 0
+0x09, 0x00, 0x00, 0x01 = ld.w %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x01 = ld.w %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x05 = ld.w %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x05 = ld.w %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x09 = ld.w %d0, [%a0]0
+0x15, 0x00, 0x00, 0x08 = ldlcx 0
+0x49, 0x00, 0x00, 0x09 = ldlcx [%a0]0
+0x49, 0x00, 0x40, 0x00 = ldmst [%a0+]0, %e0
+0x69, 0x00, 0x40, 0x00 = ldmst [%p0+r], %e0
+0xe5, 0x00, 0x00, 0x04 = ldmst 0, %e0
+0x49, 0x00, 0x40, 0x04 = ldmst [+%a0]0, %e0
+0x69, 0x00, 0x40, 0x04 = ldmst [%p0+c]0, %e0
+0x49, 0x00, 0x40, 0x08 = ldmst [%a0]0, %e0
+0x49, 0x00, 0x40, 0x09 = lducx [%a0]0
+0x15, 0x00, 0x00, 0x0c = lducx 0
+0xc5, 0x00, 0x00, 0x00 = lea %a0, 0
+0xd9, 0x00, 0x00, 0x00 = lea %a0, [%a0]0
+0x49, 0x00, 0x00, 0x0a = lea %a0, [%a0]0
+0xfc, 0x00 = loop %a0, -0x20
+0xfd, 0x00, 0x00, 0x00 = loop %a0, 0
+0x7a, 0x00 = lt %d15, %d0, %d0
+0xfa, 0x00 = lt %d15, %d0, 0
+0x0b, 0x00, 0x20, 0x01 = lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x02 = lt %d0, %d0, 0
+0x01, 0x00, 0x20, 0x04 = lt.a %d0, %a0, %a0
+0x0b, 0x00, 0x20, 0x05 = lt.b %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x05 = lt.bu %d0, %d0, %d0
+0x0b, 0x00, 0x20, 0x07 = lt.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x07 = lt.hu %d0, %d0, %d0
+0x06, 0x00 = lt.u %d15, %d0, %d0
+0x86, 0x00 = lt.u %d15, %d0, 0
+0x0b, 0x00, 0x30, 0x01 = lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x02 = lt.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x09 = lt.w %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x09 = lt.wu %d0, %d0, %d0
+0x03, 0x00, 0x0a, 0x00 = madd %d0, %d0, %d0, %d0
+0x13, 0x00, 0x20, 0x00 = madd %d0, %d0, %d0, 0
+0x83, 0x00, 0x60, 0x00 = madd.h %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0x10, 0x00 = madd.q %d0, %d0, %d0, %d0, 0
+0x13, 0x00, 0x60, 0x00 = maddm %e0, %e0, %d0, 0
+0x03, 0x00, 0x6a, 0x00 = maddm %e0, %e0, %d0, %d0
+0x83, 0x00, 0x70, 0x00 = maddm.h %e0, %e0, %d0, %d0
+0x43, 0x00, 0x70, 0x00 = maddm.q %e0, %e0, %d0, %d0
+0x13, 0x00, 0x40, 0x00 = maddm.u %e0, %e0, %d0, 0
+0x03, 0x00, 0x68, 0x00 = maddm.u %e0, %e0, %d0, %d0
+0x13, 0x00, 0xe0, 0x00 = maddms %e0, %e0, %d0, 0
+0x03, 0x00, 0xea, 0x00 = maddms %e0, %e0, %d0, %d0
+0x13, 0x00, 0xc0, 0x00 = maddms.u %e0, %e0, %d0, 0
+0x03, 0x00, 0xe8, 0x00 = maddms.u %e0, %e0, %d0, %d0
+0x43, 0x00, 0x78, 0x00 = maddr.h %d0, %e0, %d0, %d0, 0
+0x43, 0x00, 0x18, 0x00 = maddr.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0xf8, 0x00 = maddrs.h %d0, %e0, %d0, %d0, 0
+0x43, 0x00, 0x98, 0x00 = maddrs.q %d0, %d0, %d0, %d0, 0
+0x03, 0x00, 0x8a, 0x00 = madds %d0, %d0, %d0, %d0
+0x13, 0x00, 0xa0, 0x00 = madds %d0, %d0, %d0, 0
+0x83, 0x00, 0xe0, 0x00 = madds.h %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0x90, 0x00 = madds.q %d0, %d0, %d0, %d0, 0
+0x13, 0x00, 0x80, 0x00 = madds.u %d0, %d0, %d0, 0
+0x03, 0x00, 0x88, 0x00 = madds.u %d0, %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x01 = max %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x03 = max %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x05 = max.b %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x05 = max.bu %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x07 = max.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x07 = max.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x01 = max.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x03 = max.u %d0, %d0, 0
+0x4d, 0x00, 0x00, 0x00 = mfcr %d0, 0
+0x0b, 0x00, 0x80, 0x01 = min %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x03 = min %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x05 = min.b %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x05 = min.bu %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x07 = min.h %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x07 = min.hu %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x01 = min.u %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x03 = min.u %d0, %d0, 0
+0x02, 0x00 = mov %d0, %d0
+0x82, 0x00 = mov %d0, 0
+0xc6, 0x00 = mov %d15, 0
+0x3b, 0x00, 0x00, 0x00 = mov %d0, 0
+0x0b, 0x00, 0xf0, 0x01 = mov %d0, %d0
+0x30, 0x00 = mov.a %a0, %d0
+0x01, 0x00, 0x30, 0x06 = mov.a %a0, %d0
+0x80, 0x00 = mov.aa %a0, %a0
+0x01, 0x00, 0x00, 0x00 = mov.aa %a0, %a0
+0x20, 0x00 = mov.d %d0, %a0
+0x01, 0x00, 0xc0, 0x04 = mov.d %d0, %a0
+0xbb, 0x00, 0x00, 0x00 = mov.u %d0, 0
+0x7b, 0x00, 0x00, 0x00 = movh %d0, 0
+0x91, 0x00, 0x00, 0x00 = movh.a %a0, 0
+0x00, 0x10 = movz.a %a0
+0x23, 0x00, 0x0a, 0x00 = msub %d0, %d0, %d0, %d0
+0x33, 0x00, 0x20, 0x00 = msub %d0, %d0, %d0, 0
+0xa3, 0x00, 0x60, 0x00 = msub.h %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0x10, 0x00 = msub.q %d0, %d0, %d0, %d0, 0
+0x33, 0x00, 0x60, 0x00 = msubm %e0, %e0, %d0, 0
+0x23, 0x00, 0x6a, 0x00 = msubm %e0, %e0, %d0, %d0
+0xa3, 0x00, 0x70, 0x00 = msubm.h %e0, %e0, %d0, %d0
+0x63, 0x00, 0x70, 0x00 = msubm.q %e0, %e0, %d0, %d0
+0x33, 0x00, 0x40, 0x00 = msubm.u %e0, %e0, %d0, 0
+0x23, 0x00, 0x68, 0x00 = msubm.u %e0, %e0, %d0, %d0
+0x33, 0x00, 0xe0, 0x00 = msubms %e0, %e0, %d0, 0
+0x23, 0x00, 0xea, 0x00 = msubms %e0, %e0, %d0, %d0
+0x33, 0x00, 0xc0, 0x00 = msubms.u %e0, %e0, %d0, 0
+0x23, 0x00, 0xe8, 0x00 = msubms.u %e0, %e0, %d0, %d0
+0x63, 0x00, 0x78, 0x00 = msubr.h %d0, %e0, %d0, %d0, 0
+0x63, 0x00, 0x18, 0x00 = msubr.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0xf8, 0x00 = msubrs.h %d0, %e0, %d0, %d0, 0
+0x63, 0x00, 0x98, 0x00 = msubrs.q %d0, %d0, %d0, %d0, 0
+0x23, 0x00, 0x8a, 0x00 = msubs %d0, %d0, %d0, %d0
+0x33, 0x00, 0xa0, 0x00 = msubs %d0, %d0, %d0, 0
+0xa3, 0x00, 0xe0, 0x00 = msubs.h %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0x90, 0x00 = msubs.q %d0, %d0, %d0, %d0, 0
+0x33, 0x00, 0x80, 0x00 = msubs.u %d0, %d0, %d0, 0
+0x23, 0x00, 0x88, 0x00 = msubs.u %d0, %d0, %d0, %d0
+0xcd, 0x00, 0x00, 0x00 = mtcr 0, %d0
+0xe2, 0x00 = mul %d0, %d0
+0x53, 0x00, 0x20, 0x00 = mul %d0, %d0, 0
+0x73, 0x00, 0xa0, 0x00 = mul %d0, %d0, %d0
+0xb3, 0x00, 0x80, 0x01 = mul.h %e0, %d0, %d0, 0
+0x93, 0x00, 0x40, 0x00 = mul.q %d0, %d0, %d0, 0
+0x53, 0x00, 0x60, 0x00 = mulm %e0, %d0, 0
+0x73, 0x00, 0xa0, 0x06 = mulm %e0, %d0, %d0
+0x53, 0x00, 0x40, 0x00 = mulm.u %e0, %d0, 0
+0x73, 0x00, 0x80, 0x06 = mulm.u %e0, %d0, %d0
+0xb3, 0x00, 0xc0, 0x00 = mulr.h %d0, %d0, %d0, 0
+0x93, 0x00, 0x60, 0x00 = mulr.q %d0, %d0, %d0, 0
+0x53, 0x00, 0xa0, 0x00 = muls %d0, %d0, 0
+0x73, 0x00, 0xa0, 0x08 = muls %d0, %d0, %d0
+0x53, 0x00, 0x80, 0x00 = muls.u %d0, %d0, 0
+0x73, 0x00, 0x80, 0x08 = muls.u %d0, %d0, %d0
+0x0f, 0x00, 0x90, 0x00 = nand %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x01 = nand %d0, %d0, 0
+0x07, 0x00, 0x00, 0x00 = nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x10, 0x01 = ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x02 = ne %d0, %d0, 0
+0x01, 0x00, 0x10, 0x04 = ne.a %d0, %a0, %a0
+0x01, 0x00, 0x90, 0x04 = nez.a %d0, %a0
+0x00, 0x00 = nop
+0x0d, 0x00, 0x00, 0x00 = nop
+0x36, 0x00 = nor %d0
+0x0f, 0x00, 0xb0, 0x00 = nor %d0, %d0, %d0
+0x8f, 0x00, 0x60, 0x01 = nor %d0, %d0, 0
+0x87, 0x00, 0x40, 0x00 = nor.t %d0, %d0, 0, %d0, 0
+0x56, 0x00 = or %d0, %d0
+0xd6, 0x00 = or %d15, 0
+0x0f, 0x00, 0xa0, 0x00 = or %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x01 = or %d0, %d0, 0
+0xc7, 0x00, 0x00, 0x00 = or.and.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x60, 0x00 = or.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x02 = or.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x04 = or.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x02 = or.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x05 = or.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x02 = or.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x05 = or.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x02 = or.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x05 = or.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x02 = or.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x05 = or.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x02 = or.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x05 = or.ne %d0, %d0, 0
+0xc7, 0x00, 0x40, 0x00 = or.nor.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x20, 0x00 = or.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x20, 0x00 = or.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xf0, 0x00 = orn %d0, %d0, %d0
+0x8f, 0x00, 0xe0, 0x01 = orn %d0, %d0, 0
+0x07, 0x00, 0x20, 0x00 = orn.t %d0, %d0, 0, %d0, 0
+0x6b, 0x00, 0x00, 0x00 = pack %d0, %e0, %d0
+0x4b, 0x00, 0x80, 0x00 = parity %d0, %d0
+0x00, 0x90 = ret
+0x0d, 0x00, 0x40, 0x01 = ret
+0x00, 0x80 = rfe
+0x0d, 0x00, 0x80, 0x01 = rfe
+0x0d, 0x00, 0x40, 0x02 = rslcx
+0x2f, 0x00, 0x00, 0x00 = rstv
+0xd2, 0x50 = rsub %d0
+0x8b, 0x00, 0x00, 0x01 = rsub %d0, %d0, 0
+0x8b, 0x00, 0x40, 0x01 = rsubs %d0, %d0, 0
+0x8b, 0x00, 0x60, 0x01 = rsubs.u %d0, %d0, 0
+0xd2, 0x00 = sat.b %d0
+0x0b, 0x00, 0xe0, 0x05 = sat.b %d0, %d0
+0xd2, 0x10 = sat.bu %d0
+0x0b, 0x00, 0xf0, 0x05 = sat.bu %d0, %d0
+0xd2, 0x20 = sat.h %d0
+0x0b, 0x00, 0xe0, 0x07 = sat.h %d0, %d0
+0xd2, 0x30 = sat.hu %d0
+0x0b, 0x00, 0xf0, 0x07 = sat.hu %d0, %d0
+0x2b, 0x00, 0x40, 0x00 = sel %d0, %d0, %d0, %d0
+0xab, 0x00, 0x80, 0x00 = sel %d0, %d0, %d0, 0
+0x21, 0x00, 0x40, 0x00 = sel.a %a0, %d0, %a0, %a0
+0xa1, 0x00, 0x80, 0x00 = sel.a %a0, %d0, %a0, 0
+0x2b, 0x00, 0x50, 0x00 = seln %d0, %d0, %d0, %d0
+0xab, 0x00, 0xa0, 0x00 = seln %d0, %d0, %d0, 0
+0x21, 0x00, 0x50, 0x00 = seln.a %a0, %d0, %a0, %a0
+0xa1, 0x00, 0xa0, 0x00 = seln.a %a0, %d0, %a0, 0
+0x26, 0x00 = sh %d0, 0
+0x0f, 0x00, 0x00, 0x00 = sh %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x00 = sh %d0, %d0, 0
+0x27, 0x00, 0x00, 0x00 = sh.and.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x60, 0x00 = sh.andn.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0x00, 0x02 = sh.b %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x04 = sh.b %d0, %d0, 0
+0x0b, 0x00, 0x70, 0x03 = sh.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x06 = sh.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x03 = sh.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x07 = sh.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x03 = sh.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x07 = sh.ge.u %d0, %d0, 0
+0x0f, 0x00, 0x00, 0x04 = sh.h %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x08 = sh.h %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x03 = sh.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x07 = sh.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x03 = sh.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x07 = sh.lt.u %d0, %d0, 0
+0xa7, 0x00, 0x00, 0x00 = sh.nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x80, 0x03 = sh.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x07 = sh.ne %d0, %d0, 0
+0x27, 0x00, 0x40, 0x00 = sh.nor.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x20, 0x00 = sh.or.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x20, 0x00 = sh.orn.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x40, 0x00 = sh.xnor.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x60, 0x00 = sh.xor.t %d0, %d0, 0, %d0, 0
+0xa6, 0x00 = sha %d0, 0
+0x0f, 0x00, 0x10, 0x00 = sha %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x00 = sha %d0, %d0, 0
+0x0f, 0x00, 0x10, 0x02 = sha.b %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x04 = sha.b %d0, %d0, 0
+0x0f, 0x00, 0x10, 0x04 = sha.h %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x08 = sha.h %d0, %d0, 0
+0x0f, 0x00, 0x20, 0x00 = shas %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x00 = shas %d0, %d0, 0
+0x18, 0x00 = st.a [%a0]0, %a15
+0x2c, 0x00 = st.a [%a15]0, %a0
+0x54, 0x00 = st.a [%a0+], %a0
+0x84, 0x00 = st.a [%a0], %a0
+0x89, 0x00, 0x80, 0x01 = st.a [%a0+]0, %a0
+0xa9, 0x00, 0x80, 0x01 = st.a [%p0+r], %a0
+0x89, 0x00, 0x80, 0x05 = st.a [+%a0]0, %a0
+0xa9, 0x00, 0x80, 0x05 = st.a [%p0+c]0, %a0
+0xa5, 0x00, 0x00, 0x08 = st.a 0, %a0
+0x89, 0x00, 0x80, 0x09 = st.a [%a0]0, %a0
+0x78, 0x00 = st.b [%a0], %d0
+0x8c, 0x00 = st.b [%a15]0, %d0
+0xa8, 0x00 = st.b [%a0]0, %d15
+0xe4, 0x00 = st.b [%a0+], %d0
+0x25, 0x00, 0x00, 0x00 = st.b 0, %d0
+0x89, 0x00, 0x00, 0x00 = st.b [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x00 = st.b [%p0+r], %d0
+0x89, 0x00, 0x00, 0x04 = st.b [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x04 = st.b [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x08 = st.b [%a0]0, %d0
+0x89, 0x00, 0x40, 0x01 = st.d [%a0+]0, %e0
+0xa9, 0x00, 0x40, 0x01 = st.d [%p0+r], %e0
+0xa5, 0x00, 0x00, 0x04 = st.d 0, %e0
+0x89, 0x00, 0x40, 0x05 = st.d [+%a0]0, %e0
+0xa9, 0x00, 0x40, 0x05 = st.d [%p0+c]0, %e0
+0x89, 0x00, 0x40, 0x09 = st.d [%a0]0, %e0
+0x89, 0x00, 0xc0, 0x01 = st.da [%a0+]0, %p0
+0xa9, 0x00, 0xc0, 0x01 = st.da [%p0+r], %p0
+0x89, 0x00, 0xc0, 0x05 = st.da [+%a0]0, %p0
+0xa9, 0x00, 0xc0, 0x05 = st.da [%p0+c]0, %p0
+0x89, 0x00, 0xc0, 0x09 = st.da [%a0]0, %p0
+0xa5, 0x00, 0x00, 0x0c = st.da 0, %p0
+0x14, 0x00 = st.h [%a0+], %d0
+0x4c, 0x00 = st.h [%a15]0, %d0
+0x68, 0x00 = st.h [%a0]0, %d15
+0xf8, 0x00 = st.h [%a0], %d0
+0x89, 0x00, 0x80, 0x00 = st.h [%a0+]0, %d0
+0xa9, 0x00, 0x80, 0x00 = st.h [%p0+r], %d0
+0x89, 0x00, 0x80, 0x04 = st.h [+%a0]0, %d0
+0xa9, 0x00, 0x80, 0x04 = st.h [%p0+c]0, %d0
+0x25, 0x00, 0x00, 0x08 = st.h 0, %d0
+0x89, 0x00, 0x80, 0x08 = st.h [%a0]0, %d0
+0x65, 0x00, 0x00, 0x00 = st.q 0, %d0
+0x89, 0x00, 0x00, 0x02 = st.q [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x02 = st.q [%p0+r], %d0
+0x89, 0x00, 0x00, 0x06 = st.q [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x06 = st.q [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x0a = st.q [%a0]0, %d0
+0xd5, 0x00, 0x00, 0x00 = st.t 0, 0, 0
+0x04, 0x00 = st.w [%a0], %d0
+0x94, 0x00 = st.w [%a0+], %d0
+0xcc, 0x00 = st.w [%a15]0, %d0
+0xe8, 0x00 = st.w [%a0]0, %d15
+0x59, 0x00, 0x00, 0x00 = st.w [%a0]0, %d0
+0xa5, 0x00, 0x00, 0x00 = st.w 0, %d0
+0x89, 0x00, 0x00, 0x01 = st.w [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x01 = st.w [%p0+r], %d0
+0x89, 0x00, 0x00, 0x05 = st.w [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x05 = st.w [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x09 = st.w [%a0]0, %d0
+0x15, 0x00, 0x00, 0x00 = stlcx 0
+0x49, 0x00, 0x80, 0x09 = stlcx [%a0]0
+0x15, 0x00, 0x00, 0x04 = stucx 0
+0x49, 0x00, 0xc0, 0x09 = stucx [%a0]0
+0x5a, 0x00 = sub %d15, %d0, %d0
+0xa2, 0x00 = sub %d0, %d0
+0x0b, 0x00, 0x80, 0x00 = sub %d0, %d0, %d0
+0x40, 0x00 = sub.a %sp, 0
+0x01, 0x00, 0x20, 0x00 = sub.a %a0, %a0, %a0
+0x0b, 0x00, 0x80, 0x04 = sub.b %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x06 = sub.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x00 = subc %d0, %d0, %d0
+0x62, 0x00 = subs %d0, %d0
+0x0b, 0x00, 0xa0, 0x00 = subs %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x04 = subs.b %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x04 = subs.bu %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x06 = subs.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x06 = subs.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x00 = subs.u %d0, %d0, %d0
+0x01, 0x00, 0x10, 0x06 = subsc.a %a0, %a0, %d0, 0
+0x0b, 0x00, 0xc0, 0x00 = subx %d0, %d0, %d0
+0x0d, 0x00, 0x00, 0x02 = svlcx
+0x49, 0x00, 0x80, 0x00 = swap.a [%a0+]0, %a0
+0x69, 0x00, 0x80, 0x00 = swap.a [%p0+r], %a0
+0x49, 0x00, 0x80, 0x04 = swap.a [+%a0]0, %a0
+0x69, 0x00, 0x80, 0x04 = swap.a [%p0+c]0, %a0
+0xe5, 0x00, 0x00, 0x08 = swap.a 0, %a0
+0x49, 0x00, 0x80, 0x08 = swap.a [%a0]0, %a0
+0x49, 0x00, 0x00, 0x00 = swap.w [%a0+]0, %d0
+0x69, 0x00, 0x00, 0x00 = swap.w [%p0+r], %d0
+0xe5, 0x00, 0x00, 0x00 = swap.w 0, %d0
+0x49, 0x00, 0x00, 0x04 = swap.w [+%a0]0, %d0
+0x69, 0x00, 0x00, 0x04 = swap.w [%p0+c]0, %d0
+0x49, 0x00, 0x00, 0x08 = swap.w [%a0]0, %d0
+0xad, 0x00, 0x80, 0x00 = syscall 0
+0x0d, 0x00, 0x40, 0x05 = trapsv
+0x0d, 0x00, 0x00, 0x05 = trapv
+0x4b, 0x00, 0x00, 0x05 = unpack %e0, %d0
+0x0f, 0x00, 0xd0, 0x00 = xnor %d0, %d0, %d0
+0x8f, 0x00, 0xa0, 0x01 = xnor %d0, %d0, 0
+0x07, 0x00, 0x40, 0x00 = xnor.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xc0, 0x00 = xor %d0, %d0, %d0
+0x8f, 0x00, 0x80, 0x01 = xor %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x02 = xor.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x05 = xor.eq %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x03 = xor.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x06 = xor.ge %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x03 = xor.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x06 = xor.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x03 = xor.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x06 = xor.lt %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x03 = xor.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x06 = xor.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x00, 0x03 = xor.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x06 = xor.ne %d0, %d0, 0
+0x07, 0x00, 0x60, 0x00 = xor.t %d0, %d0, 0, %d0, 0
diff --git a/suite/MC/TriCore/tc120.s.cs b/suite/MC/TriCore/tc120.s.cs
new file mode 100644
index 0000000000..f7de3213cb
--- /dev/null
+++ b/suite/MC/TriCore/tc120.s.cs
@@ -0,0 +1,760 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_120, None
+0x0b, 0x00, 0xc0, 0x01 = abs %d0, %d0
+0x0b, 0x00, 0xc0, 0x05 = abs.b %d0, %d0
+0x0b, 0x00, 0xc0, 0x07 = abs.h %d0, %d0
+0x0b, 0x00, 0xe0, 0x00 = absdif %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x01 = absdif %d0, %d0, 0
+0x0b, 0x00, 0xe0, 0x04 = absdif.b %d0, %d0, %d0
+0x0b, 0x00, 0xe0, 0x06 = absdif.h %d0, %d0, %d0
+0x0b, 0x00, 0xf0, 0x00 = absdifs %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x01 = absdifs %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x06 = absdifs.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x01 = abss %d0, %d0
+0x0b, 0x00, 0xd0, 0x07 = abss.h %d0, %d0
+0x12, 0x00 = add %d0, %d15, %d0
+0x92, 0x00 = add %d0, %d15, 0
+0x1a, 0x00 = add %d15, %d0, %d0
+0x42, 0x00 = add %d0, %d0
+0x9a, 0x00 = add %d15, %d0, 0
+0xc2, 0x00 = add %d0, 0
+0x0b, 0x00, 0x00, 0x00 = add %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x00 = add %d0, %d0, 0
+0x30, 0x00 = add.a %a0, %a0
+0xb0, 0x00 = add.a %a0, 0
+0x01, 0x00, 0x10, 0x00 = add.a %a0, %a0, %a0
+0x0b, 0x00, 0x00, 0x04 = add.b %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x06 = add.h %d0, %d0, %d0
+0x0b, 0x00, 0x50, 0x00 = addc %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x00 = addc %d0, %d0, 0
+0x1b, 0x00, 0x00, 0x00 = addi %d0, %d0, 0
+0x9b, 0x00, 0x00, 0x00 = addih %d0, %d0, 0
+0x11, 0x00, 0x00, 0x00 = addih.a %a0, %a0, 0
+0x22, 0x00 = adds %d0, %d0
+0x0b, 0x00, 0x20, 0x00 = adds %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x00 = adds %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x06 = adds.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x06 = adds.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x00 = adds.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x00 = adds.u %d0, %d0, 0
+0x10, 0x00 = addsc.a %a0, %a0, %d15, 0
+0x01, 0x00, 0x00, 0x06 = addsc.a %a0, %a0, %d0, 0
+0x01, 0x00, 0x20, 0x06 = addsc.at %a0, %a0, %d0
+0x0b, 0x00, 0x40, 0x00 = addx %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x00 = addx %d0, %d0, 0
+0x26, 0x00 = and %d0, %d0
+0x16, 0x00 = and %d15, 0
+0x0f, 0x00, 0x80, 0x00 = and %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x01 = and %d0, %d0, 0
+0x47, 0x00, 0x00, 0x00 = and.and.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x60, 0x00 = and.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x00, 0x02 = and.eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x04 = and.eq %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x02 = and.ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x04 = and.ge %d0, %d0, 0
+0x0b, 0x00, 0x50, 0x02 = and.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x04 = and.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x02 = and.lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x04 = and.lt %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x02 = and.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x04 = and.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x02 = and.ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x04 = and.ne %d0, %d0, 0
+0x47, 0x00, 0x40, 0x00 = and.nor.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x20, 0x00 = and.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x00, 0x00 = and.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xe0, 0x00 = andn %d0, %d0, %d0
+0x8f, 0x00, 0xc0, 0x01 = andn %d0, %d0, 0
+0x87, 0x00, 0x60, 0x00 = andn.t %d0, %d0, 0, %d0, 0
+0xe0, 0x00 = bisr 0
+0xad, 0x00, 0x00, 0x00 = bisr 0
+0x4b, 0x00, 0x10, 0x00 = bmerge %d0, %d0, %d0
+0x4b, 0x00, 0x90, 0x00 = bsplit %e0, %d0
+0x89, 0x00, 0x80, 0x03 = cachea.i [%a0+]0
+0xa9, 0x00, 0x80, 0x03 = cachea.i [%p0+r]
+0x89, 0x00, 0x80, 0x07 = cachea.i [+%a0]0
+0xa9, 0x00, 0x80, 0x07 = cachea.i [%p0+c]0
+0x89, 0x00, 0x80, 0x0b = cachea.i [%a0]0
+0x89, 0x00, 0x00, 0x03 = cachea.w [%a0+]0
+0xa9, 0x00, 0x00, 0x03 = cachea.w [%p0+r]
+0x89, 0x00, 0x00, 0x07 = cachea.w [+%a0]0
+0xa9, 0x00, 0x00, 0x07 = cachea.w [%p0+c]0
+0x89, 0x00, 0x00, 0x0b = cachea.w [%a0]0
+0x89, 0x00, 0x40, 0x03 = cachea.wi [%a0+]0
+0xa9, 0x00, 0x40, 0x03 = cachea.wi [%p0+r]
+0x89, 0x00, 0x40, 0x07 = cachea.wi [+%a0]0
+0xa9, 0x00, 0x40, 0x07 = cachea.wi [%p0+c]0
+0x89, 0x00, 0x40, 0x0b = cachea.wi [%a0]0
+0x8a, 0x00 = cadd %d0, %d15, 0
+0x2b, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, %d0
+0xab, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, 0
+0xca, 0x00 = caddn %d0, %d15, 0
+0x2b, 0x00, 0x10, 0x00 = caddn %d0, %d0, %d0, %d0
+0xab, 0x00, 0x20, 0x00 = caddn %d0, %d0, %d0, 0
+0x5c, 0x00 = call 0
+0x6d, 0x00, 0x00, 0x00 = call 0
+0xed, 0x00, 0x00, 0x00 = calla 0
+0x2d, 0x00, 0x00, 0x00 = calli %a0
+0x0f, 0x00, 0xc0, 0x01 = clo %d0, %d0
+0x0f, 0x00, 0xd0, 0x07 = clo.h %d0, %d0
+0x0f, 0x00, 0xd0, 0x01 = cls %d0, %d0
+0x0f, 0x00, 0xe0, 0x07 = cls.h %d0, %d0
+0x0f, 0x00, 0xb0, 0x01 = clz %d0, %d0
+0x0f, 0x00, 0xc0, 0x07 = clz.h %d0, %d0
+0x2a, 0x00 = cmov %d0, %d15, %d0
+0xaa, 0x00 = cmov %d0, %d15, 0
+0x6a, 0x00 = cmovn %d0, %d15, %d0
+0xea, 0x00 = cmovn %d0, %d15, 0
+0x2b, 0x00, 0x20, 0x00 = csub %d0, %d0, %d0, %d0
+0x2b, 0x00, 0x30, 0x00 = csubn %d0, %d0, %d0, %d0
+0x00, 0xa0 = debug
+0x0d, 0x00, 0x00, 0x01 = debug
+0x77, 0x00, 0x00, 0x00 = dextr %d0, %d0, %d0, 0
+0x17, 0x00, 0x80, 0x00 = dextr %d0, %d0, %d0, %d0
+0x0d, 0x00, 0x40, 0x03 = disable
+0x0d, 0x00, 0x80, 0x04 = dsync
+0x6b, 0x00, 0xd0, 0x00 = dvadj %e0, %e0, %d0
+0x4b, 0x00, 0xa0, 0x01 = dvinit %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x05 = dvinit.b %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x04 = dvinit.bu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x03 = dvinit.h %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x02 = dvinit.hu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x00 = dvinit.u %e0, %d0, %d0
+0x6b, 0x00, 0xf0, 0x00 = dvstep %e0, %e0, %d0
+0x6b, 0x00, 0xe0, 0x00 = dvstep.u %e0, %e0, %d0
+0x0d, 0x00, 0x00, 0x03 = enable
+0x3a, 0x00 = eq %d15, %d0, %d0
+0xba, 0x00 = eq %d15, %d0, 0
+0x0b, 0x00, 0x00, 0x01 = eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x02 = eq %d0, %d0, 0
+0x01, 0x00, 0x00, 0x04 = eq.a %d0, %a0, %a0
+0x0b, 0x00, 0x00, 0x05 = eq.b %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x07 = eq.h %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x09 = eq.w %d0, %d0, %d0
+0x0b, 0x00, 0x60, 0x05 = eqany.b %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0a = eqany.b %d0, %d0, 0
+0x0b, 0x00, 0x60, 0x07 = eqany.h %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0e = eqany.h %d0, %d0, 0
+0x01, 0x00, 0x80, 0x04 = eqz.a %d0, %a0
+0x17, 0x00, 0x40, 0x00 = extr %d0, %d0, %e0
+0x37, 0x00, 0x40, 0x00 = extr %d0, %d0, 0, 0
+0x57, 0x00, 0x40, 0x00 = extr %d0, %d0, %d0, 0
+0x17, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %e0
+0x37, 0x00, 0x60, 0x00 = extr.u %d0, %d0, 0, 0
+0x57, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x01 = ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x02 = ge %d0, %d0, 0
+0x01, 0x00, 0x30, 0x04 = ge.a %d0, %a0, %a0
+0x0b, 0x00, 0x50, 0x01 = ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x02 = ge.u %d0, %d0, 0
+0x37, 0x00, 0x20, 0x00 = imask %e0, %d0, 0, 0
+0x57, 0x00, 0x20, 0x00 = imask %e0, %d0, %d0, 0
+0xb7, 0x00, 0x20, 0x00 = imask %e0, 0, 0, 0
+0xd7, 0x00, 0x20, 0x00 = imask %e0, 0, %d0, 0
+0x67, 0x00, 0x00, 0x00 = ins.t %d0, %d0, 0, %d0, 0
+0x17, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %e0
+0x37, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, 0, 0
+0x57, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %d0, 0
+0x97, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %e0
+0xb7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, 0, 0
+0xd7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %d0, 0
+0x67, 0x00, 0x20, 0x00 = insn.t %d0, %d0, 0, %d0, 0
+0x0d, 0x00, 0xc0, 0x04 = isync
+0x3c, 0x00 = j 0
+0x1d, 0x00, 0x00, 0x00 = j 0
+0x9d, 0x00, 0x00, 0x00 = ja 0
+0x1e, 0x00 = jeq %d15, 0, 0
+0x5f, 0x00, 0x00, 0x00 = jeq %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x00 = jeq %d0, 0, 0
+0x7d, 0x00, 0x00, 0x00 = jeq.a %a0, %a0, 0
+0x7f, 0x00, 0x00, 0x00 = jge %d0, %d0, 0
+0xff, 0x00, 0x00, 0x00 = jge %d0, 0, 0
+0x7f, 0x00, 0x00, 0x80 = jge.u %d0, %d0, 0
+0xff, 0x00, 0x00, 0x80 = jge.u %d0, 0, 0
+0xce, 0x00 = jgez %d0, 0
+0x4e, 0x00 = jgtz %d0, 0
+0xdc, 0x00 = ji %a0
+0x2d, 0x00, 0x30, 0x00 = ji %a0
+0x5d, 0x00, 0x00, 0x00 = jl 0
+0xdd, 0x00, 0x00, 0x00 = jla 0
+0x8e, 0x00 = jlez %d0, 0
+0x2d, 0x00, 0x20, 0x00 = jli %a0
+0x3f, 0x00, 0x00, 0x00 = jlt %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x00 = jlt %d0, 0, 0
+0x3f, 0x00, 0x00, 0x80 = jlt.u %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x80 = jlt.u %d0, 0, 0
+0x0e, 0x00 = jltz %d0, 0
+0x7e, 0x00 = jne %d15, %d0, 0
+0x5e, 0x00 = jne %d15, 0, 0
+0x5f, 0x00, 0x00, 0x80 = jne %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x80 = jne %d0, 0, 0
+0x7d, 0x00, 0x00, 0x80 = jne.a %a0, %a0, 0
+0x1f, 0x00, 0x00, 0x80 = jned %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x80 = jned %d0, 0, 0
+0x1f, 0x00, 0x00, 0x00 = jnei %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x00 = jnei %d0, 0, 0
+0xee, 0x00 = jnz %d15, 0
+0xf6, 0x00 = jnz %d0, 0
+0x7c, 0x00 = jnz.a %a0, 0
+0xbd, 0x00, 0x00, 0x80 = jnz.a %a0, 0
+0xae, 0x00 = jnz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x80 = jnz.t %d0, 0, 0
+0x6e, 0x00 = jz %d15, 0
+0x76, 0x00 = jz %d0, 0
+0xbc, 0x00 = jz.a %a0, 0
+0xbd, 0x00, 0x00, 0x00 = jz.a %a0, 0
+0x2e, 0x00 = jz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x00 = jz.t %d0, 0, 0
+0xd8, 0x00 = ld.a %a15, [%sp]0
+0xc8, 0x00 = ld.a %a0, [%a15]0
+0xcc, 0x00 = ld.a %a15, [%a0]0
+0xc4, 0x00 = ld.a %a0, [%a0+]
+0xd4, 0x00 = ld.a %a0, [%a0]
+0x99, 0x00, 0x00, 0x00 = ld.a %a0, [%a0]0
+0x09, 0x00, 0x80, 0x01 = ld.a %a0, [%a0+]0
+0x29, 0x00, 0x80, 0x01 = ld.a %a0, [%p0+r]
+0x09, 0x00, 0x80, 0x05 = ld.a %a0, [+%a0]0
+0x29, 0x00, 0x80, 0x05 = ld.a %a0, [%p0+c]0
+0x85, 0x00, 0x00, 0x08 = ld.a %a0, 0
+0x09, 0x00, 0x80, 0x09 = ld.a %a0, [%a0]0
+0x05, 0x00, 0x00, 0x00 = ld.b %d0, 0
+0x09, 0x00, 0x00, 0x00 = ld.b %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x00 = ld.b %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x04 = ld.b %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x04 = ld.b %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x08 = ld.b %d0, [%a0]0
+0x14, 0x00 = ld.bu %d0, [%a0]
+0x0c, 0x00 = ld.bu %d15, [%a0]0
+0x08, 0x00 = ld.bu %d0, [%a15]0
+0x04, 0x00 = ld.bu %d0, [%a0+]
+0x09, 0x00, 0x40, 0x00 = ld.bu %d0, [%a0+]0
+0x29, 0x00, 0x40, 0x00 = ld.bu %d0, [%p0+r]
+0x05, 0x00, 0x00, 0x04 = ld.bu %d0, 0
+0x09, 0x00, 0x40, 0x04 = ld.bu %d0, [+%a0]0
+0x29, 0x00, 0x40, 0x04 = ld.bu %d0, [%p0+c]0
+0x09, 0x00, 0x40, 0x08 = ld.bu %d0, [%a0]0
+0x09, 0x00, 0x40, 0x01 = ld.d %e0, [%a0+]0
+0x29, 0x00, 0x40, 0x01 = ld.d %e0, [%p0+r]
+0x85, 0x00, 0x00, 0x04 = ld.d %e0, 0
+0x09, 0x00, 0x40, 0x05 = ld.d %e0, [+%a0]0
+0x29, 0x00, 0x40, 0x05 = ld.d %e0, [%p0+c]0
+0x09, 0x00, 0x40, 0x09 = ld.d %e0, [%a0]0
+0x09, 0x00, 0xc0, 0x01 = ld.da %p0, [%a0+]0
+0x29, 0x00, 0xc0, 0x01 = ld.da %p0, [%p0+r]
+0x09, 0x00, 0xc0, 0x05 = ld.da %p0, [+%a0]0
+0x29, 0x00, 0xc0, 0x05 = ld.da %p0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x09 = ld.da %p0, [%a0]0
+0x85, 0x00, 0x00, 0x0c = ld.da %p0, 0
+0x84, 0x00 = ld.h %d0, [%a0+]
+0x8c, 0x00 = ld.h %d15, [%a0]0
+0x88, 0x00 = ld.h %d0, [%a15]0
+0x94, 0x00 = ld.h %d0, [%a0]
+0x09, 0x00, 0x80, 0x00 = ld.h %d0, [%a0+]0
+0x29, 0x00, 0x80, 0x00 = ld.h %d0, [%p0+r]
+0x09, 0x00, 0x80, 0x04 = ld.h %d0, [+%a0]0
+0x29, 0x00, 0x80, 0x04 = ld.h %d0, [%p0+c]0
+0x05, 0x00, 0x00, 0x08 = ld.h %d0, 0
+0x09, 0x00, 0x80, 0x08 = ld.h %d0, [%a0]0
+0x09, 0x00, 0xc0, 0x00 = ld.hu %d0, [%a0+]0
+0x29, 0x00, 0xc0, 0x00 = ld.hu %d0, [%p0+r]
+0x09, 0x00, 0xc0, 0x04 = ld.hu %d0, [+%a0]0
+0x29, 0x00, 0xc0, 0x04 = ld.hu %d0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x08 = ld.hu %d0, [%a0]0
+0x05, 0x00, 0x00, 0x0c = ld.hu %d0, 0
+0x45, 0x00, 0x00, 0x00 = ld.q %d0, 0
+0x09, 0x00, 0x00, 0x02 = ld.q %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x02 = ld.q %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x06 = ld.q %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x06 = ld.q %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x0a = ld.q %d0, [%a0]0
+0x58, 0x00 = ld.w %d15, [%sp]0
+0x54, 0x00 = ld.w %d0, [%a0]
+0x44, 0x00 = ld.w %d0, [%a0+]
+0x4c, 0x00 = ld.w %d15, [%a0]0
+0x48, 0x00 = ld.w %d0, [%a15]0
+0x19, 0x00, 0x00, 0x00 = ld.w %d0, [%a0]0
+0x85, 0x00, 0x00, 0x00 = ld.w %d0, 0
+0x09, 0x00, 0x00, 0x01 = ld.w %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x01 = ld.w %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x05 = ld.w %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x05 = ld.w %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x09 = ld.w %d0, [%a0]0
+0x15, 0x00, 0x00, 0x08 = ldlcx 0
+0x49, 0x00, 0x00, 0x09 = ldlcx [%a0]0
+0x49, 0x00, 0x40, 0x00 = ldmst [%a0+]0, %e0
+0x69, 0x00, 0x40, 0x00 = ldmst [%p0+r], %e0
+0xe5, 0x00, 0x00, 0x04 = ldmst 0, %e0
+0x49, 0x00, 0x40, 0x04 = ldmst [+%a0]0, %e0
+0x69, 0x00, 0x40, 0x04 = ldmst [%p0+c]0, %e0
+0x49, 0x00, 0x40, 0x08 = ldmst [%a0]0, %e0
+0x49, 0x00, 0x40, 0x09 = lducx [%a0]0
+0x15, 0x00, 0x00, 0x0c = lducx 0
+0xc5, 0x00, 0x00, 0x00 = lea %a0, 0
+0xd9, 0x00, 0x00, 0x00 = lea %a0, [%a0]0
+0x49, 0x00, 0x00, 0x0a = lea %a0, [%a0]0
+0xfc, 0x00 = loop %a0, -0x20
+0xfd, 0x00, 0x00, 0x00 = loop %a0, 0
+0xfd, 0x00, 0x00, 0x80 = loopu 0
+0x7a, 0x00 = lt %d15, %d0, %d0
+0xfa, 0x00 = lt %d15, %d0, 0
+0x0b, 0x00, 0x20, 0x01 = lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x02 = lt %d0, %d0, 0
+0x01, 0x00, 0x20, 0x04 = lt.a %d0, %a0, %a0
+0x0b, 0x00, 0x20, 0x05 = lt.b %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x05 = lt.bu %d0, %d0, %d0
+0x0b, 0x00, 0x20, 0x07 = lt.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x07 = lt.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x01 = lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x02 = lt.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x09 = lt.w %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x09 = lt.wu %d0, %d0, %d0
+0x03, 0x00, 0x0a, 0x00 = madd %d0, %d0, %d0, %d0
+0x13, 0x00, 0x20, 0x00 = madd %d0, %d0, %d0, 0
+0x13, 0x00, 0x60, 0x00 = madd %e0, %e0, %d0, 0
+0x03, 0x00, 0x6a, 0x00 = madd %e0, %e0, %d0, %d0
+0x83, 0x00, 0x60, 0x00 = madd.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x64, 0x00 = madd.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x68, 0x00 = madd.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x6c, 0x00 = madd.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x10, 0x00 = madd.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x00, 0x00 = madd.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x04, 0x00 = madd.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x08, 0x00 = madd.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x14, 0x00 = madd.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0x60, 0x00 = madd.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0x64, 0x00 = madd.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0x6c, 0x00 = madd.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0x70, 0x00 = madd.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0x74, 0x00 = madd.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x40, 0x00 = madd.u %e0, %e0, %d0, 0
+0x03, 0x00, 0x68, 0x00 = madd.u %e0, %e0, %d0, %d0
+0x83, 0x00, 0x70, 0x00 = maddm.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x74, 0x00 = maddm.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x78, 0x00 = maddm.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x7c, 0x00 = maddm.h %e0, %e0, %d0, %d0uu, 0
+0x83, 0x00, 0xf0, 0x00 = maddms.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xf4, 0x00 = maddms.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xf8, 0x00 = maddms.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xfc, 0x00 = maddms.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x78, 0x00 = maddr.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x30, 0x00 = maddr.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0x34, 0x00 = maddr.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0x38, 0x00 = maddr.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0x3c, 0x00 = maddr.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x18, 0x00 = maddr.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x1c, 0x00 = maddr.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xf8, 0x00 = maddrs.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xb0, 0x00 = maddrs.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0xb4, 0x00 = maddrs.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0xb8, 0x00 = maddrs.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0xbc, 0x00 = maddrs.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x98, 0x00 = maddrs.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x9c, 0x00 = maddrs.q %d0, %d0, %d0l, %d0l, 0
+0x03, 0x00, 0x8a, 0x00 = madds %d0, %d0, %d0, %d0
+0x13, 0x00, 0xa0, 0x00 = madds %d0, %d0, %d0, 0
+0x13, 0x00, 0xe0, 0x00 = madds %e0, %e0, %d0, 0
+0x03, 0x00, 0xea, 0x00 = madds %e0, %e0, %d0, %d0
+0x83, 0x00, 0xe0, 0x00 = madds.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xe4, 0x00 = madds.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xe8, 0x00 = madds.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xec, 0x00 = madds.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x90, 0x00 = madds.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x80, 0x00 = madds.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x84, 0x00 = madds.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x88, 0x00 = madds.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x94, 0x00 = madds.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xe0, 0x00 = madds.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0xe4, 0x00 = madds.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0xec, 0x00 = madds.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0xf0, 0x00 = madds.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0xf4, 0x00 = madds.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x80, 0x00 = madds.u %d0, %d0, %d0, 0
+0x03, 0x00, 0x88, 0x00 = madds.u %d0, %d0, %d0, %d0
+0x13, 0x00, 0xc0, 0x00 = madds.u %e0, %e0, %d0, 0
+0x03, 0x00, 0xe8, 0x00 = madds.u %e0, %e0, %d0, %d0
+0xc3, 0x00, 0x60, 0x00 = maddsu.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x64, 0x00 = maddsu.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x68, 0x00 = maddsu.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x6c, 0x00 = maddsu.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x70, 0x00 = maddsum.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x74, 0x00 = maddsum.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x78, 0x00 = maddsum.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x7c, 0x00 = maddsum.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0xf0, 0x00 = maddsums.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xf4, 0x00 = maddsums.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xf8, 0x00 = maddsums.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xfc, 0x00 = maddsums.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x30, 0x00 = maddsur.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0x34, 0x00 = maddsur.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0x38, 0x00 = maddsur.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0x3c, 0x00 = maddsur.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xb0, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0xb4, 0x00 = maddsurs.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0xb8, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0xbc, 0x00 = maddsurs.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xe0, 0x00 = maddsus.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xe4, 0x00 = maddsus.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xe8, 0x00 = maddsus.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xec, 0x00 = maddsus.h %e0, %e0, %d0, %d0uu, 0
+0x0b, 0x00, 0xa0, 0x01 = max %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x03 = max %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x05 = max.b %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x05 = max.bu %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x07 = max.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x07 = max.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x01 = max.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x03 = max.u %d0, %d0, 0
+0x4d, 0x00, 0x00, 0x00 = mfcr %d0, 0
+0x0b, 0x00, 0x80, 0x01 = min %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x03 = min %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x05 = min.b %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x05 = min.bu %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x07 = min.h %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x07 = min.hu %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x01 = min.u %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x03 = min.u %d0, %d0, 0
+0x02, 0x00 = mov %d0, %d0
+0x82, 0x00 = mov %d0, 0
+0xda, 0x00 = mov %d15, 0
+0x3b, 0x00, 0x00, 0x00 = mov %d0, 0
+0x0b, 0x00, 0xf0, 0x01 = mov %d0, %d0
+0xa0, 0x00 = mov.a %a0, 0
+0x60, 0x00 = mov.a %a0, %d0
+0x01, 0x00, 0x30, 0x06 = mov.a %a0, %d0
+0x40, 0x00 = mov.aa %a0, %a0
+0x01, 0x00, 0x00, 0x00 = mov.aa %a0, %a0
+0x80, 0x00 = mov.d %d0, %a0
+0x01, 0x00, 0xc0, 0x04 = mov.d %d0, %a0
+0xbb, 0x00, 0x00, 0x00 = mov.u %d0, 0
+0x7b, 0x00, 0x00, 0x00 = movh %d0, 0
+0x91, 0x00, 0x00, 0x00 = movh.a %a0, 0
+0x23, 0x00, 0x0a, 0x00 = msub %d0, %d0, %d0, %d0
+0x33, 0x00, 0x20, 0x00 = msub %d0, %d0, %d0, 0
+0x33, 0x00, 0x60, 0x00 = msub %e0, %e0, %d0, 0
+0x23, 0x00, 0x6a, 0x00 = msub %e0, %e0, %d0, %d0
+0xa3, 0x00, 0x60, 0x00 = msub.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x64, 0x00 = msub.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x68, 0x00 = msub.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x6c, 0x00 = msub.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x10, 0x00 = msub.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x00, 0x00 = msub.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x04, 0x00 = msub.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x08, 0x00 = msub.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x14, 0x00 = msub.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0x60, 0x00 = msub.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0x64, 0x00 = msub.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0x6c, 0x00 = msub.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0x70, 0x00 = msub.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0x74, 0x00 = msub.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x40, 0x00 = msub.u %e0, %e0, %d0, 0
+0x23, 0x00, 0x68, 0x00 = msub.u %e0, %e0, %d0, %d0
+0xe3, 0x00, 0x60, 0x00 = msubad.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x64, 0x00 = msubad.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x68, 0x00 = msubad.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x6c, 0x00 = msubad.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x70, 0x00 = msubadm.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x74, 0x00 = msubadm.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x78, 0x00 = msubadm.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x7c, 0x00 = msubadm.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0xf0, 0x00 = msubadms.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xf4, 0x00 = msubadms.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xf8, 0x00 = msubadms.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xfc, 0x00 = msubadms.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x30, 0x00 = msubadr.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0x34, 0x00 = msubadr.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0x38, 0x00 = msubadr.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0x3c, 0x00 = msubadr.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xb0, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0xb4, 0x00 = msubadrs.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0xb8, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0xbc, 0x00 = msubadrs.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xe0, 0x00 = msubads.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xe4, 0x00 = msubads.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xe8, 0x00 = msubads.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xec, 0x00 = msubads.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0x70, 0x00 = msubm.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x74, 0x00 = msubm.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x78, 0x00 = msubm.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x7c, 0x00 = msubm.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0xf0, 0x00 = msubms.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xf4, 0x00 = msubms.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xf8, 0x00 = msubms.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xfc, 0x00 = msubms.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x78, 0x00 = msubr.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x30, 0x00 = msubr.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0x34, 0x00 = msubr.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0x38, 0x00 = msubr.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0x3c, 0x00 = msubr.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x18, 0x00 = msubr.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x1c, 0x00 = msubr.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xf8, 0x00 = msubrs.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb0, 0x00 = msubrs.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb4, 0x00 = msubrs.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0xb8, 0x00 = msubrs.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0xbc, 0x00 = msubrs.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x98, 0x00 = msubrs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x9c, 0x00 = msubrs.q %d0, %d0, %d0l, %d0l, 0
+0x23, 0x00, 0x8a, 0x00 = msubs %d0, %d0, %d0, %d0
+0x33, 0x00, 0xa0, 0x00 = msubs %d0, %d0, %d0, 0
+0x33, 0x00, 0xe0, 0x00 = msubs %e0, %e0, %d0, 0
+0x23, 0x00, 0xea, 0x00 = msubs %e0, %e0, %d0, %d0
+0xa3, 0x00, 0xe0, 0x00 = msubs.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xe4, 0x00 = msubs.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xe8, 0x00 = msubs.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xec, 0x00 = msubs.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x90, 0x00 = msubs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x80, 0x00 = msubs.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x84, 0x00 = msubs.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x88, 0x00 = msubs.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x94, 0x00 = msubs.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xe0, 0x00 = msubs.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0xe4, 0x00 = msubs.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0xec, 0x00 = msubs.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0xf0, 0x00 = msubs.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0xf4, 0x00 = msubs.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x80, 0x00 = msubs.u %d0, %d0, %d0, 0
+0x23, 0x00, 0x88, 0x00 = msubs.u %d0, %d0, %d0, %d0
+0x33, 0x00, 0xc0, 0x00 = msubs.u %e0, %e0, %d0, 0
+0x23, 0x00, 0xe8, 0x00 = msubs.u %e0, %e0, %d0, %d0
+0xcd, 0x00, 0x00, 0x00 = mtcr 0, %d0
+0xe2, 0x00 = mul %d0, %d0
+0x53, 0x00, 0x20, 0x00 = mul %d0, %d0, 0
+0x73, 0x00, 0x0a, 0x00 = mul %d0, %d0, %d0
+0x53, 0x00, 0x60, 0x00 = mul %e0, %d0, 0
+0x73, 0x00, 0x6a, 0x00 = mul %e0, %d0, %d0
+0xb3, 0x00, 0x60, 0x00 = mul.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x64, 0x00 = mul.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x68, 0x00 = mul.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x6c, 0x00 = mul.h %e0, %d0, %d0uu, 0
+0x93, 0x00, 0x00, 0x00 = mul.q %d0, %d0, %d0u, 0
+0x93, 0x00, 0x04, 0x00 = mul.q %d0, %d0, %d0l, 0
+0x93, 0x00, 0x08, 0x00 = mul.q %d0, %d0, %d0, 0
+0x93, 0x00, 0x10, 0x00 = mul.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x14, 0x00 = mul.q %d0, %d0l, %d0l, 0
+0x93, 0x00, 0x60, 0x00 = mul.q %e0, %d0, %d0u, 0
+0x93, 0x00, 0x64, 0x00 = mul.q %e0, %d0, %d0l, 0
+0x93, 0x00, 0x6c, 0x00 = mul.q %e0, %d0, %d0, 0
+0x53, 0x00, 0x40, 0x00 = mul.u %e0, %d0, 0
+0x73, 0x00, 0x68, 0x00 = mul.u %e0, %d0, %d0
+0xb3, 0x00, 0x70, 0x00 = mulm.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x74, 0x00 = mulm.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x78, 0x00 = mulm.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x7c, 0x00 = mulm.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0xf0, 0x00 = mulms.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0xf4, 0x00 = mulms.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0xf8, 0x00 = mulms.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0xfc, 0x00 = mulms.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0x30, 0x00 = mulr.h %d0, %d0, %d0ul, 0
+0xb3, 0x00, 0x34, 0x00 = mulr.h %d0, %d0, %d0lu, 0
+0xb3, 0x00, 0x38, 0x00 = mulr.h %d0, %d0, %d0ll, 0
+0xb3, 0x00, 0x3c, 0x00 = mulr.h %d0, %d0, %d0uu, 0
+0x93, 0x00, 0x18, 0x00 = mulr.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x1c, 0x00 = mulr.q %d0, %d0l, %d0l, 0
+0x53, 0x00, 0xa0, 0x00 = muls %d0, %d0, 0
+0x73, 0x00, 0x8a, 0x00 = muls %d0, %d0, %d0
+0x53, 0x00, 0x80, 0x00 = muls.u %d0, %d0, 0
+0x73, 0x00, 0x88, 0x00 = muls.u %d0, %d0, %d0
+0x0f, 0x00, 0x90, 0x00 = nand %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x01 = nand %d0, %d0, 0
+0x07, 0x00, 0x00, 0x00 = nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x10, 0x01 = ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x02 = ne %d0, %d0, 0
+0x01, 0x00, 0x10, 0x04 = ne.a %d0, %a0, %a0
+0x01, 0x00, 0x90, 0x04 = nez.a %d0, %a0
+0x00, 0x00 = nop
+0x0d, 0x00, 0x00, 0x00 = nop
+0x46, 0x00 = nor %d0
+0x0f, 0x00, 0xb0, 0x00 = nor %d0, %d0, %d0
+0x8f, 0x00, 0x60, 0x01 = nor %d0, %d0, 0
+0x87, 0x00, 0x40, 0x00 = nor.t %d0, %d0, 0, %d0, 0
+0xa6, 0x00 = or %d0, %d0
+0x96, 0x00 = or %d15, 0
+0x0f, 0x00, 0xa0, 0x00 = or %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x01 = or %d0, %d0, 0
+0xc7, 0x00, 0x00, 0x00 = or.and.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x60, 0x00 = or.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x02 = or.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x04 = or.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x02 = or.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x05 = or.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x02 = or.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x05 = or.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x02 = or.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x05 = or.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x02 = or.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x05 = or.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x02 = or.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x05 = or.ne %d0, %d0, 0
+0xc7, 0x00, 0x40, 0x00 = or.nor.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x20, 0x00 = or.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x20, 0x00 = or.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xf0, 0x00 = orn %d0, %d0, %d0
+0x8f, 0x00, 0xe0, 0x01 = orn %d0, %d0, 0
+0x07, 0x00, 0x20, 0x00 = orn.t %d0, %d0, 0, %d0, 0
+0x6b, 0x00, 0x00, 0x00 = pack %d0, %e0, %d0
+0x4b, 0x00, 0x20, 0x00 = parity %d0, %d0
+0x00, 0x90 = ret
+0x0d, 0x00, 0x80, 0x01 = ret
+0x00, 0x80 = rfe
+0x0d, 0x00, 0xc0, 0x01 = rfe
+0x0d, 0x00, 0x40, 0x01 = rfm
+0x0d, 0x00, 0x40, 0x02 = rslcx
+0x2f, 0x00, 0x00, 0x00 = rstv
+0x32, 0x50 = rsub %d0
+0x8b, 0x00, 0x00, 0x01 = rsub %d0, %d0, 0
+0x8b, 0x00, 0x40, 0x01 = rsubs %d0, %d0, 0
+0x8b, 0x00, 0x60, 0x01 = rsubs.u %d0, %d0, 0
+0x32, 0x00 = sat.b %d0
+0x0b, 0x00, 0xe0, 0x05 = sat.b %d0, %d0
+0x32, 0x10 = sat.bu %d0
+0x0b, 0x00, 0xf0, 0x05 = sat.bu %d0, %d0
+0x32, 0x20 = sat.h %d0
+0x0b, 0x00, 0xe0, 0x07 = sat.h %d0, %d0
+0x32, 0x30 = sat.hu %d0
+0x0b, 0x00, 0xf0, 0x07 = sat.hu %d0, %d0
+0x2b, 0x00, 0x40, 0x00 = sel %d0, %d0, %d0, %d0
+0xab, 0x00, 0x80, 0x00 = sel %d0, %d0, %d0, 0
+0x2b, 0x00, 0x50, 0x00 = seln %d0, %d0, %d0, %d0
+0xab, 0x00, 0xa0, 0x00 = seln %d0, %d0, %d0, 0
+0x06, 0x00 = sh %d0, 0
+0x0f, 0x00, 0x00, 0x00 = sh %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x00 = sh %d0, %d0, 0
+0x27, 0x00, 0x00, 0x00 = sh.and.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x60, 0x00 = sh.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x03 = sh.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x06 = sh.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x03 = sh.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x07 = sh.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x03 = sh.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x07 = sh.ge.u %d0, %d0, 0
+0x0f, 0x00, 0x00, 0x04 = sh.h %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x08 = sh.h %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x03 = sh.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x07 = sh.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x03 = sh.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x07 = sh.lt.u %d0, %d0, 0
+0xa7, 0x00, 0x00, 0x00 = sh.nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x80, 0x03 = sh.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x07 = sh.ne %d0, %d0, 0
+0x27, 0x00, 0x40, 0x00 = sh.nor.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x20, 0x00 = sh.or.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x20, 0x00 = sh.orn.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x40, 0x00 = sh.xnor.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x60, 0x00 = sh.xor.t %d0, %d0, 0, %d0, 0
+0x86, 0x00 = sha %d0, 0
+0x0f, 0x00, 0x10, 0x00 = sha %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x00 = sha %d0, %d0, 0
+0x0f, 0x00, 0x10, 0x04 = sha.h %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x08 = sha.h %d0, %d0, 0
+0x0f, 0x00, 0x20, 0x00 = shas %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x00 = shas %d0, %d0, 0
+0xf8, 0x00 = st.a [%sp]0, %a15
+0xec, 0x00 = st.a [%a0]0, %a15
+0xe8, 0x00 = st.a [%a15]0, %a0
+0xe4, 0x00 = st.a [%a0+], %a0
+0xf4, 0x00 = st.a [%a0], %a0
+0x89, 0x00, 0x80, 0x01 = st.a [%a0+]0, %a0
+0xa9, 0x00, 0x80, 0x01 = st.a [%p0+r], %a0
+0x89, 0x00, 0x80, 0x05 = st.a [+%a0]0, %a0
+0xa9, 0x00, 0x80, 0x05 = st.a [%p0+c]0, %a0
+0xa5, 0x00, 0x00, 0x08 = st.a 0, %a0
+0x89, 0x00, 0x80, 0x09 = st.a [%a0]0, %a0
+0x34, 0x00 = st.b [%a0], %d0
+0x28, 0x00 = st.b [%a15]0, %d0
+0x2c, 0x00 = st.b [%a0]0, %d15
+0x24, 0x00 = st.b [%a0+], %d0
+0x25, 0x00, 0x00, 0x00 = st.b 0, %d0
+0x89, 0x00, 0x00, 0x00 = st.b [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x00 = st.b [%p0+r], %d0
+0x89, 0x00, 0x00, 0x04 = st.b [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x04 = st.b [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x08 = st.b [%a0]0, %d0
+0x89, 0x00, 0x40, 0x01 = st.d [%a0+]0, %e0
+0xa9, 0x00, 0x40, 0x01 = st.d [%p0+r], %e0
+0xa5, 0x00, 0x00, 0x04 = st.d 0, %e0
+0x89, 0x00, 0x40, 0x05 = st.d [+%a0]0, %e0
+0xa9, 0x00, 0x40, 0x05 = st.d [%p0+c]0, %e0
+0x89, 0x00, 0x40, 0x09 = st.d [%a0]0, %e0
+0x89, 0x00, 0xc0, 0x01 = st.da [%a0+]0, %p0
+0xa9, 0x00, 0xc0, 0x01 = st.da [%p0+r], %p0
+0x89, 0x00, 0xc0, 0x05 = st.da [+%a0]0, %p0
+0xa9, 0x00, 0xc0, 0x05 = st.da [%p0+c]0, %p0
+0x89, 0x00, 0xc0, 0x09 = st.da [%a0]0, %p0
+0xa5, 0x00, 0x00, 0x0c = st.da 0, %p0
+0xa4, 0x00 = st.h [%a0+], %d0
+0xa8, 0x00 = st.h [%a15]0, %d0
+0xac, 0x00 = st.h [%a0]0, %d15
+0xb4, 0x00 = st.h [%a0], %d0
+0x89, 0x00, 0x80, 0x00 = st.h [%a0+]0, %d0
+0xa9, 0x00, 0x80, 0x00 = st.h [%p0+r], %d0
+0x89, 0x00, 0x80, 0x04 = st.h [+%a0]0, %d0
+0xa9, 0x00, 0x80, 0x04 = st.h [%p0+c]0, %d0
+0x25, 0x00, 0x00, 0x08 = st.h 0, %d0
+0x89, 0x00, 0x80, 0x08 = st.h [%a0]0, %d0
+0x65, 0x00, 0x00, 0x00 = st.q 0, %d0
+0x89, 0x00, 0x00, 0x02 = st.q [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x02 = st.q [%p0+r], %d0
+0x89, 0x00, 0x00, 0x06 = st.q [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x06 = st.q [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x0a = st.q [%a0]0, %d0
+0xd5, 0x00, 0x00, 0x00 = st.t 0, 0, 0
+0x78, 0x00 = st.w [%sp]0, %d15
+0x74, 0x00 = st.w [%a0], %d0
+0x64, 0x00 = st.w [%a0+], %d0
+0x68, 0x00 = st.w [%a15]0, %d0
+0x6c, 0x00 = st.w [%a0]0, %d15
+0x59, 0x00, 0x00, 0x00 = st.w [%a0]0, %d0
+0xa5, 0x00, 0x00, 0x00 = st.w 0, %d0
+0x89, 0x00, 0x00, 0x01 = st.w [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x01 = st.w [%p0+r], %d0
+0x89, 0x00, 0x00, 0x05 = st.w [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x05 = st.w [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x09 = st.w [%a0]0, %d0
+0x15, 0x00, 0x00, 0x00 = stlcx 0
+0x49, 0x00, 0x80, 0x09 = stlcx [%a0]0
+0x15, 0x00, 0x00, 0x04 = stucx 0
+0x49, 0x00, 0xc0, 0x09 = stucx [%a0]0
+0x52, 0x00 = sub %d0, %d15, %d0
+0x5a, 0x00 = sub %d15, %d0, %d0
+0xa2, 0x00 = sub %d0, %d0
+0x0b, 0x00, 0x80, 0x00 = sub %d0, %d0, %d0
+0x20, 0x00 = sub.a %sp, 0
+0x01, 0x00, 0x20, 0x00 = sub.a %a0, %a0, %a0
+0x0b, 0x00, 0x80, 0x04 = sub.b %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x06 = sub.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x00 = subc %d0, %d0, %d0
+0x62, 0x00 = subs %d0, %d0
+0x0b, 0x00, 0xa0, 0x00 = subs %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x06 = subs.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x06 = subs.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x00 = subs.u %d0, %d0, %d0
+0x0b, 0x00, 0xc0, 0x00 = subx %d0, %d0, %d0
+0x0d, 0x00, 0x00, 0x02 = svlcx
+0x49, 0x00, 0x00, 0x00 = swap.w [%a0+]0, %d0
+0x69, 0x00, 0x00, 0x00 = swap.w [%p0+r], %d0
+0xe5, 0x00, 0x00, 0x00 = swap.w 0, %d0
+0x49, 0x00, 0x00, 0x04 = swap.w [+%a0]0, %d0
+0x69, 0x00, 0x00, 0x04 = swap.w [%p0+c]0, %d0
+0x49, 0x00, 0x00, 0x08 = swap.w [%a0]0, %d0
+0xad, 0x00, 0x80, 0x00 = syscall 0
+0x0d, 0x00, 0x40, 0x05 = trapsv
+0x0d, 0x00, 0x00, 0x05 = trapv
+0x4b, 0x00, 0x80, 0x00 = unpack %e0, %d0
+0x0f, 0x00, 0xd0, 0x00 = xnor %d0, %d0, %d0
+0x8f, 0x00, 0xa0, 0x01 = xnor %d0, %d0, 0
+0x07, 0x00, 0x40, 0x00 = xnor.t %d0, %d0, 0, %d0, 0
+0xc6, 0x00 = xor %d0, %d0
+0x0f, 0x00, 0xc0, 0x00 = xor %d0, %d0, %d0
+0x8f, 0x00, 0x80, 0x01 = xor %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x02 = xor.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x05 = xor.eq %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x03 = xor.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x06 = xor.ge %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x03 = xor.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x06 = xor.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x03 = xor.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x06 = xor.lt %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x03 = xor.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x06 = xor.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x00, 0x03 = xor.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x06 = xor.ne %d0, %d0, 0
+0x07, 0x00, 0x60, 0x00 = xor.t %d0, %d0, 0, %d0, 0
diff --git a/suite/MC/TriCore/tc130.s.cs b/suite/MC/TriCore/tc130.s.cs
new file mode 100644
index 0000000000..875acd7884
--- /dev/null
+++ b/suite/MC/TriCore/tc130.s.cs
@@ -0,0 +1,786 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_130, None
+0x0b, 0x00, 0xc0, 0x01 = abs %d0, %d0
+0x0b, 0x00, 0xc0, 0x05 = abs.b %d0, %d0
+0x0b, 0x00, 0xc0, 0x07 = abs.h %d0, %d0
+0x0b, 0x00, 0xe0, 0x00 = absdif %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x01 = absdif %d0, %d0, 0
+0x0b, 0x00, 0xe0, 0x04 = absdif.b %d0, %d0, %d0
+0x0b, 0x00, 0xe0, 0x06 = absdif.h %d0, %d0, %d0
+0x0b, 0x00, 0xf0, 0x00 = absdifs %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x01 = absdifs %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x06 = absdifs.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x01 = abss %d0, %d0
+0x0b, 0x00, 0xd0, 0x07 = abss.h %d0, %d0
+0x12, 0x00 = add %d0, %d15, %d0
+0x92, 0x00 = add %d0, %d15, 0
+0x1a, 0x00 = add %d15, %d0, %d0
+0x42, 0x00 = add %d0, %d0
+0x9a, 0x00 = add %d15, %d0, 0
+0xc2, 0x00 = add %d0, 0
+0x0b, 0x00, 0x00, 0x00 = add %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x00 = add %d0, %d0, 0
+0x30, 0x00 = add.a %a0, %a0
+0xb0, 0x00 = add.a %a0, 0
+0x01, 0x00, 0x10, 0x00 = add.a %a0, %a0, %a0
+0x0b, 0x00, 0x00, 0x04 = add.b %d0, %d0, %d0
+0x6b, 0x00, 0x21, 0x00 = add.f %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x06 = add.h %d0, %d0, %d0
+0x0b, 0x00, 0x50, 0x00 = addc %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x00 = addc %d0, %d0, 0
+0x1b, 0x00, 0x00, 0x00 = addi %d0, %d0, 0
+0x9b, 0x00, 0x00, 0x00 = addih %d0, %d0, 0
+0x11, 0x00, 0x00, 0x00 = addih.a %a0, %a0, 0
+0x22, 0x00 = adds %d0, %d0
+0x0b, 0x00, 0x20, 0x00 = adds %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x00 = adds %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x06 = adds.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x06 = adds.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x00 = adds.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x00 = adds.u %d0, %d0, 0
+0x10, 0x00 = addsc.a %a0, %a0, %d15, 0
+0x01, 0x00, 0x00, 0x06 = addsc.a %a0, %a0, %d0, 0
+0x01, 0x00, 0x20, 0x06 = addsc.at %a0, %a0, %d0
+0x0b, 0x00, 0x40, 0x00 = addx %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x00 = addx %d0, %d0, 0
+0x26, 0x00 = and %d0, %d0
+0x16, 0x00 = and %d15, 0
+0x0f, 0x00, 0x80, 0x00 = and %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x01 = and %d0, %d0, 0
+0x47, 0x00, 0x00, 0x00 = and.and.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x60, 0x00 = and.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x00, 0x02 = and.eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x04 = and.eq %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x02 = and.ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x04 = and.ge %d0, %d0, 0
+0x0b, 0x00, 0x50, 0x02 = and.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x04 = and.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x02 = and.lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x04 = and.lt %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x02 = and.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x04 = and.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x02 = and.ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x04 = and.ne %d0, %d0, 0
+0x47, 0x00, 0x40, 0x00 = and.nor.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x20, 0x00 = and.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x00, 0x00 = and.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xe0, 0x00 = andn %d0, %d0, %d0
+0x8f, 0x00, 0xc0, 0x01 = andn %d0, %d0, 0
+0x87, 0x00, 0x60, 0x00 = andn.t %d0, %d0, 0, %d0, 0
+0xe0, 0x00 = bisr 0
+0xad, 0x00, 0x00, 0x00 = bisr 0
+0x4b, 0x00, 0x10, 0x00 = bmerge %d0, %d0, %d0
+0x4b, 0x00, 0x90, 0x00 = bsplit %e0, %d0
+0x89, 0x00, 0x80, 0x03 = cachea.i [%a0+]0
+0xa9, 0x00, 0x80, 0x03 = cachea.i [%p0+r]
+0x89, 0x00, 0x80, 0x07 = cachea.i [+%a0]0
+0xa9, 0x00, 0x80, 0x07 = cachea.i [%p0+c]0
+0x89, 0x00, 0x80, 0x0b = cachea.i [%a0]0
+0x89, 0x00, 0x00, 0x03 = cachea.w [%a0+]0
+0xa9, 0x00, 0x00, 0x03 = cachea.w [%p0+r]
+0x89, 0x00, 0x00, 0x07 = cachea.w [+%a0]0
+0xa9, 0x00, 0x00, 0x07 = cachea.w [%p0+c]0
+0x89, 0x00, 0x00, 0x0b = cachea.w [%a0]0
+0x89, 0x00, 0x40, 0x03 = cachea.wi [%a0+]0
+0xa9, 0x00, 0x40, 0x03 = cachea.wi [%p0+r]
+0x89, 0x00, 0x40, 0x07 = cachea.wi [+%a0]0
+0xa9, 0x00, 0x40, 0x07 = cachea.wi [%p0+c]0
+0x89, 0x00, 0x40, 0x0b = cachea.wi [%a0]0
+0x8a, 0x00 = cadd %d0, %d15, 0
+0x2b, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, %d0
+0xab, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, 0
+0xca, 0x00 = caddn %d0, %d15, 0
+0x2b, 0x00, 0x10, 0x00 = caddn %d0, %d0, %d0, %d0
+0xab, 0x00, 0x20, 0x00 = caddn %d0, %d0, %d0, 0
+0x5c, 0x00 = call 0
+0x6d, 0x00, 0x00, 0x00 = call 0
+0xed, 0x00, 0x00, 0x00 = calla 0
+0x2d, 0x00, 0x00, 0x00 = calli %a0
+0x0f, 0x00, 0xc0, 0x01 = clo %d0, %d0
+0x0f, 0x00, 0xd0, 0x07 = clo.h %d0, %d0
+0x0f, 0x00, 0xd0, 0x01 = cls %d0, %d0
+0x0f, 0x00, 0xe0, 0x07 = cls.h %d0, %d0
+0x0f, 0x00, 0xb0, 0x01 = clz %d0, %d0
+0x0f, 0x00, 0xc0, 0x07 = clz.h %d0, %d0
+0x2a, 0x00 = cmov %d0, %d15, %d0
+0xaa, 0x00 = cmov %d0, %d15, 0
+0x6a, 0x00 = cmovn %d0, %d15, %d0
+0xea, 0x00 = cmovn %d0, %d15, 0
+0x4b, 0x00, 0x00, 0x00 = cmp.f %d0, %d0, %d0
+0x2b, 0x00, 0x20, 0x00 = csub %d0, %d0, %d0, %d0
+0x2b, 0x00, 0x30, 0x00 = csubn %d0, %d0, %d0, %d0
+0x00, 0xa0 = debug
+0x0d, 0x00, 0x00, 0x01 = debug
+0x77, 0x00, 0x00, 0x00 = dextr %d0, %d0, %d0, 0
+0x17, 0x00, 0x80, 0x00 = dextr %d0, %d0, %d0, %d0
+0x0d, 0x00, 0x40, 0x03 = disable
+0x4b, 0x00, 0x51, 0x00 = div.f %d0, %d0, %d0
+0x0d, 0x00, 0x80, 0x04 = dsync
+0x6b, 0x00, 0xd0, 0x00 = dvadj %e0, %e0, %d0
+0x4b, 0x00, 0xa0, 0x01 = dvinit %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x05 = dvinit.b %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x04 = dvinit.bu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x03 = dvinit.h %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x02 = dvinit.hu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x00 = dvinit.u %e0, %d0, %d0
+0x6b, 0x00, 0xf0, 0x00 = dvstep %e0, %e0, %d0
+0x6b, 0x00, 0xe0, 0x00 = dvstep.u %e0, %e0, %d0
+0x0d, 0x00, 0x00, 0x03 = enable
+0x3a, 0x00 = eq %d15, %d0, %d0
+0xba, 0x00 = eq %d15, %d0, 0
+0x0b, 0x00, 0x00, 0x01 = eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x02 = eq %d0, %d0, 0
+0x01, 0x00, 0x00, 0x04 = eq.a %d0, %a0, %a0
+0x0b, 0x00, 0x00, 0x05 = eq.b %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x07 = eq.h %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x09 = eq.w %d0, %d0, %d0
+0x0b, 0x00, 0x60, 0x05 = eqany.b %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0a = eqany.b %d0, %d0, 0
+0x0b, 0x00, 0x60, 0x07 = eqany.h %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0e = eqany.h %d0, %d0, 0
+0x01, 0x00, 0x80, 0x04 = eqz.a %d0, %a0
+0x17, 0x00, 0x40, 0x00 = extr %d0, %d0, %e0
+0x37, 0x00, 0x40, 0x00 = extr %d0, %d0, 0, 0
+0x57, 0x00, 0x40, 0x00 = extr %d0, %d0, %d0, 0
+0x17, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %e0
+0x37, 0x00, 0x60, 0x00 = extr.u %d0, %d0, 0, 0
+0x57, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %d0, 0
+0x4b, 0x00, 0x01, 0x01 = ftoi %d0, %d0
+0x4b, 0x00, 0x11, 0x01 = ftoq31 %d0, %d0, %d0
+0x4b, 0x00, 0x21, 0x01 = ftou %d0, %d0
+0x0b, 0x00, 0x40, 0x01 = ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x02 = ge %d0, %d0, 0
+0x01, 0x00, 0x30, 0x04 = ge.a %d0, %a0, %a0
+0x0b, 0x00, 0x50, 0x01 = ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x02 = ge.u %d0, %d0, 0
+0x37, 0x00, 0x20, 0x00 = imask %e0, %d0, 0, 0
+0x57, 0x00, 0x20, 0x00 = imask %e0, %d0, %d0, 0
+0xb7, 0x00, 0x20, 0x00 = imask %e0, 0, 0, 0
+0xd7, 0x00, 0x20, 0x00 = imask %e0, 0, %d0, 0
+0x67, 0x00, 0x00, 0x00 = ins.t %d0, %d0, 0, %d0, 0
+0x17, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %e0
+0x37, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, 0, 0
+0x57, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %d0, 0
+0x97, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %e0
+0xb7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, 0, 0
+0xd7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %d0, 0
+0x67, 0x00, 0x20, 0x00 = insn.t %d0, %d0, 0, %d0, 0
+0x0d, 0x00, 0xc0, 0x04 = isync
+0x4b, 0x00, 0x41, 0x01 = itof %d0, %d0
+0x6b, 0x00, 0xa0, 0x00 = ixmax %e0, %e0, %d0
+0x6b, 0x00, 0xb0, 0x00 = ixmax.u %e0, %e0, %d0
+0x6b, 0x00, 0x80, 0x00 = ixmin %e0, %e0, %d0
+0x6b, 0x00, 0x90, 0x00 = ixmin.u %e0, %e0, %d0
+0x3c, 0x00 = j 0
+0x1d, 0x00, 0x00, 0x00 = j 0
+0x9d, 0x00, 0x00, 0x00 = ja 0
+0x3e, 0x00 = jeq %d15, %d0, 0
+0x1e, 0x00 = jeq %d15, 0, 0
+0x5f, 0x00, 0x00, 0x00 = jeq %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x00 = jeq %d0, 0, 0
+0x7d, 0x00, 0x00, 0x00 = jeq.a %a0, %a0, 0
+0x7f, 0x00, 0x00, 0x00 = jge %d0, %d0, 0
+0xff, 0x00, 0x00, 0x00 = jge %d0, 0, 0
+0x7f, 0x00, 0x00, 0x80 = jge.u %d0, %d0, 0
+0xff, 0x00, 0x00, 0x80 = jge.u %d0, 0, 0
+0xce, 0x00 = jgez %d0, 0
+0x4e, 0x00 = jgtz %d0, 0
+0xdc, 0x00 = ji %a0
+0x2d, 0x00, 0x30, 0x00 = ji %a0
+0x5d, 0x00, 0x00, 0x00 = jl 0
+0xdd, 0x00, 0x00, 0x00 = jla 0
+0x8e, 0x00 = jlez %d0, 0
+0x2d, 0x00, 0x20, 0x00 = jli %a0
+0x3f, 0x00, 0x00, 0x00 = jlt %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x00 = jlt %d0, 0, 0
+0x3f, 0x00, 0x00, 0x80 = jlt.u %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x80 = jlt.u %d0, 0, 0
+0x0e, 0x00 = jltz %d0, 0
+0x7e, 0x00 = jne %d15, %d0, 0
+0x5e, 0x00 = jne %d15, 0, 0
+0x5f, 0x00, 0x00, 0x80 = jne %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x80 = jne %d0, 0, 0
+0x7d, 0x00, 0x00, 0x80 = jne.a %a0, %a0, 0
+0x1f, 0x00, 0x00, 0x80 = jned %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x80 = jned %d0, 0, 0
+0x1f, 0x00, 0x00, 0x00 = jnei %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x00 = jnei %d0, 0, 0
+0xee, 0x00 = jnz %d15, 0
+0xf6, 0x00 = jnz %d0, 0
+0x7c, 0x00 = jnz.a %a0, 0
+0xbd, 0x00, 0x00, 0x80 = jnz.a %a0, 0
+0xae, 0x00 = jnz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x80 = jnz.t %d0, 0, 0
+0x6e, 0x00 = jz %d15, 0
+0x76, 0x00 = jz %d0, 0
+0xbc, 0x00 = jz.a %a0, 0
+0xbd, 0x00, 0x00, 0x00 = jz.a %a0, 0
+0x2e, 0x00 = jz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x00 = jz.t %d0, 0, 0
+0xd8, 0x00 = ld.a %a15, [%sp]0
+0xc8, 0x00 = ld.a %a0, [%a15]0
+0xcc, 0x00 = ld.a %a15, [%a0]0
+0xc4, 0x00 = ld.a %a0, [%a0+]
+0xd4, 0x00 = ld.a %a0, [%a0]
+0x99, 0x00, 0x00, 0x00 = ld.a %a0, [%a0]0
+0x09, 0x00, 0x80, 0x01 = ld.a %a0, [%a0+]0
+0x29, 0x00, 0x80, 0x01 = ld.a %a0, [%p0+r]
+0x09, 0x00, 0x80, 0x05 = ld.a %a0, [+%a0]0
+0x29, 0x00, 0x80, 0x05 = ld.a %a0, [%p0+c]0
+0x85, 0x00, 0x00, 0x08 = ld.a %a0, 0
+0x09, 0x00, 0x80, 0x09 = ld.a %a0, [%a0]0
+0x05, 0x00, 0x00, 0x00 = ld.b %d0, 0
+0x09, 0x00, 0x00, 0x00 = ld.b %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x00 = ld.b %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x04 = ld.b %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x04 = ld.b %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x08 = ld.b %d0, [%a0]0
+0x14, 0x00 = ld.bu %d0, [%a0]
+0x0c, 0x00 = ld.bu %d15, [%a0]0
+0x08, 0x00 = ld.bu %d0, [%a15]0
+0x04, 0x00 = ld.bu %d0, [%a0+]
+0x09, 0x00, 0x40, 0x00 = ld.bu %d0, [%a0+]0
+0x29, 0x00, 0x40, 0x00 = ld.bu %d0, [%p0+r]
+0x05, 0x00, 0x00, 0x04 = ld.bu %d0, 0
+0x09, 0x00, 0x40, 0x04 = ld.bu %d0, [+%a0]0
+0x29, 0x00, 0x40, 0x04 = ld.bu %d0, [%p0+c]0
+0x09, 0x00, 0x40, 0x08 = ld.bu %d0, [%a0]0
+0x09, 0x00, 0x40, 0x01 = ld.d %e0, [%a0+]0
+0x29, 0x00, 0x40, 0x01 = ld.d %e0, [%p0+r]
+0x85, 0x00, 0x00, 0x04 = ld.d %e0, 0
+0x09, 0x00, 0x40, 0x05 = ld.d %e0, [+%a0]0
+0x29, 0x00, 0x40, 0x05 = ld.d %e0, [%p0+c]0
+0x09, 0x00, 0x40, 0x09 = ld.d %e0, [%a0]0
+0x09, 0x00, 0xc0, 0x01 = ld.da %p0, [%a0+]0
+0x29, 0x00, 0xc0, 0x01 = ld.da %p0, [%p0+r]
+0x09, 0x00, 0xc0, 0x05 = ld.da %p0, [+%a0]0
+0x29, 0x00, 0xc0, 0x05 = ld.da %p0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x09 = ld.da %p0, [%a0]0
+0x85, 0x00, 0x00, 0x0c = ld.da %p0, 0
+0x84, 0x00 = ld.h %d0, [%a0+]
+0x8c, 0x00 = ld.h %d15, [%a0]0
+0x88, 0x00 = ld.h %d0, [%a15]0
+0x94, 0x00 = ld.h %d0, [%a0]
+0x09, 0x00, 0x80, 0x00 = ld.h %d0, [%a0+]0
+0x29, 0x00, 0x80, 0x00 = ld.h %d0, [%p0+r]
+0x09, 0x00, 0x80, 0x04 = ld.h %d0, [+%a0]0
+0x29, 0x00, 0x80, 0x04 = ld.h %d0, [%p0+c]0
+0x05, 0x00, 0x00, 0x08 = ld.h %d0, 0
+0x09, 0x00, 0x80, 0x08 = ld.h %d0, [%a0]0
+0x09, 0x00, 0xc0, 0x00 = ld.hu %d0, [%a0+]0
+0x29, 0x00, 0xc0, 0x00 = ld.hu %d0, [%p0+r]
+0x09, 0x00, 0xc0, 0x04 = ld.hu %d0, [+%a0]0
+0x29, 0x00, 0xc0, 0x04 = ld.hu %d0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x08 = ld.hu %d0, [%a0]0
+0x05, 0x00, 0x00, 0x0c = ld.hu %d0, 0
+0x45, 0x00, 0x00, 0x00 = ld.q %d0, 0
+0x09, 0x00, 0x00, 0x02 = ld.q %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x02 = ld.q %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x06 = ld.q %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x06 = ld.q %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x0a = ld.q %d0, [%a0]0
+0x58, 0x00 = ld.w %d15, [%sp]0
+0x54, 0x00 = ld.w %d0, [%a0]
+0x44, 0x00 = ld.w %d0, [%a0+]
+0x4c, 0x00 = ld.w %d15, [%a0]0
+0x48, 0x00 = ld.w %d0, [%a15]0
+0x19, 0x00, 0x00, 0x00 = ld.w %d0, [%a0]0
+0x85, 0x00, 0x00, 0x00 = ld.w %d0, 0
+0x09, 0x00, 0x00, 0x01 = ld.w %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x01 = ld.w %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x05 = ld.w %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x05 = ld.w %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x09 = ld.w %d0, [%a0]0
+0x15, 0x00, 0x00, 0x08 = ldlcx 0
+0x49, 0x00, 0x00, 0x09 = ldlcx [%a0]0
+0x49, 0x00, 0x40, 0x00 = ldmst [%a0+]0, %e0
+0x69, 0x00, 0x40, 0x00 = ldmst [%p0+r], %e0
+0xe5, 0x00, 0x00, 0x04 = ldmst 0, %e0
+0x49, 0x00, 0x40, 0x04 = ldmst [+%a0]0, %e0
+0x69, 0x00, 0x40, 0x04 = ldmst [%p0+c]0, %e0
+0x49, 0x00, 0x40, 0x08 = ldmst [%a0]0, %e0
+0x49, 0x00, 0x40, 0x09 = lducx [%a0]0
+0x15, 0x00, 0x00, 0x0c = lducx 0
+0xc5, 0x00, 0x00, 0x00 = lea %a0, 0
+0xd9, 0x00, 0x00, 0x00 = lea %a0, [%a0]0
+0x49, 0x00, 0x00, 0x0a = lea %a0, [%a0]0
+0xfc, 0x00 = loop %a0, -0x20
+0xfd, 0x00, 0x00, 0x00 = loop %a0, 0
+0xfd, 0x00, 0x00, 0x80 = loopu 0
+0x7a, 0x00 = lt %d15, %d0, %d0
+0xfa, 0x00 = lt %d15, %d0, 0
+0x0b, 0x00, 0x20, 0x01 = lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x02 = lt %d0, %d0, 0
+0x01, 0x00, 0x20, 0x04 = lt.a %d0, %a0, %a0
+0x0b, 0x00, 0x20, 0x05 = lt.b %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x05 = lt.bu %d0, %d0, %d0
+0x0b, 0x00, 0x20, 0x07 = lt.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x07 = lt.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x01 = lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x02 = lt.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x09 = lt.w %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x09 = lt.wu %d0, %d0, %d0
+0x03, 0x00, 0x0a, 0x00 = madd %d0, %d0, %d0, %d0
+0x13, 0x00, 0x20, 0x00 = madd %d0, %d0, %d0, 0
+0x13, 0x00, 0x60, 0x00 = madd %e0, %e0, %d0, 0
+0x03, 0x00, 0x6a, 0x00 = madd %e0, %e0, %d0, %d0
+0x6b, 0x00, 0x61, 0x00 = madd.f %d0, %d0, %d0, %d0
+0x83, 0x00, 0x60, 0x00 = madd.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x64, 0x00 = madd.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x68, 0x00 = madd.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x6c, 0x00 = madd.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x10, 0x00 = madd.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x00, 0x00 = madd.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x04, 0x00 = madd.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x08, 0x00 = madd.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x14, 0x00 = madd.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0x60, 0x00 = madd.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0x64, 0x00 = madd.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0x6c, 0x00 = madd.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0x70, 0x00 = madd.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0x74, 0x00 = madd.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x40, 0x00 = madd.u %e0, %e0, %d0, 0
+0x03, 0x00, 0x68, 0x00 = madd.u %e0, %e0, %d0, %d0
+0x83, 0x00, 0x70, 0x00 = maddm.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x74, 0x00 = maddm.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x78, 0x00 = maddm.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x7c, 0x00 = maddm.h %e0, %e0, %d0, %d0uu, 0
+0x83, 0x00, 0xf0, 0x00 = maddms.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xf4, 0x00 = maddms.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xf8, 0x00 = maddms.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xfc, 0x00 = maddms.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x78, 0x00 = maddr.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x30, 0x00 = maddr.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0x34, 0x00 = maddr.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0x38, 0x00 = maddr.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0x3c, 0x00 = maddr.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x18, 0x00 = maddr.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x1c, 0x00 = maddr.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xf8, 0x00 = maddrs.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xb0, 0x00 = maddrs.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0xb4, 0x00 = maddrs.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0xb8, 0x00 = maddrs.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0xbc, 0x00 = maddrs.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x98, 0x00 = maddrs.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x9c, 0x00 = maddrs.q %d0, %d0, %d0l, %d0l, 0
+0x03, 0x00, 0x8a, 0x00 = madds %d0, %d0, %d0, %d0
+0x13, 0x00, 0xa0, 0x00 = madds %d0, %d0, %d0, 0
+0x13, 0x00, 0xe0, 0x00 = madds %e0, %e0, %d0, 0
+0x03, 0x00, 0xea, 0x00 = madds %e0, %e0, %d0, %d0
+0x83, 0x00, 0xe0, 0x00 = madds.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xe4, 0x00 = madds.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xe8, 0x00 = madds.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xec, 0x00 = madds.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x90, 0x00 = madds.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x80, 0x00 = madds.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x84, 0x00 = madds.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x88, 0x00 = madds.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x94, 0x00 = madds.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xe0, 0x00 = madds.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0xe4, 0x00 = madds.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0xec, 0x00 = madds.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0xf0, 0x00 = madds.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0xf4, 0x00 = madds.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x80, 0x00 = madds.u %d0, %d0, %d0, 0
+0x03, 0x00, 0x88, 0x00 = madds.u %d0, %d0, %d0, %d0
+0x13, 0x00, 0xc0, 0x00 = madds.u %e0, %e0, %d0, 0
+0x03, 0x00, 0xe8, 0x00 = madds.u %e0, %e0, %d0, %d0
+0xc3, 0x00, 0x60, 0x00 = maddsu.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x64, 0x00 = maddsu.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x68, 0x00 = maddsu.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x6c, 0x00 = maddsu.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x70, 0x00 = maddsum.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x74, 0x00 = maddsum.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x78, 0x00 = maddsum.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x7c, 0x00 = maddsum.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0xf0, 0x00 = maddsums.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xf4, 0x00 = maddsums.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xf8, 0x00 = maddsums.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xfc, 0x00 = maddsums.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x30, 0x00 = maddsur.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0x34, 0x00 = maddsur.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0x38, 0x00 = maddsur.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0x3c, 0x00 = maddsur.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xb0, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0xb4, 0x00 = maddsurs.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0xb8, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0xbc, 0x00 = maddsurs.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xe0, 0x00 = maddsus.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xe4, 0x00 = maddsus.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xe8, 0x00 = maddsus.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xec, 0x00 = maddsus.h %e0, %e0, %d0, %d0uu, 0
+0x0b, 0x00, 0xa0, 0x01 = max %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x03 = max %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x05 = max.b %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x05 = max.bu %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x07 = max.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x07 = max.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x01 = max.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x03 = max.u %d0, %d0, 0
+0x4d, 0x00, 0x00, 0x00 = mfcr %d0, 0
+0x0b, 0x00, 0x80, 0x01 = min %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x03 = min %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x05 = min.b %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x05 = min.bu %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x07 = min.h %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x07 = min.hu %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x01 = min.u %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x03 = min.u %d0, %d0, 0
+0x02, 0x00 = mov %d0, %d0
+0x82, 0x00 = mov %d0, 0
+0xda, 0x00 = mov %d15, 0
+0x3b, 0x00, 0x00, 0x00 = mov %d0, 0
+0x0b, 0x00, 0xf0, 0x01 = mov %d0, %d0
+0xa0, 0x00 = mov.a %a0, 0
+0x60, 0x00 = mov.a %a0, %d0
+0x01, 0x00, 0x30, 0x06 = mov.a %a0, %d0
+0x40, 0x00 = mov.aa %a0, %a0
+0x01, 0x00, 0x00, 0x00 = mov.aa %a0, %a0
+0x80, 0x00 = mov.d %d0, %a0
+0x01, 0x00, 0xc0, 0x04 = mov.d %d0, %a0
+0xbb, 0x00, 0x00, 0x00 = mov.u %d0, 0
+0x7b, 0x00, 0x00, 0x00 = movh %d0, 0
+0x91, 0x00, 0x00, 0x00 = movh.a %a0, 0
+0x23, 0x00, 0x0a, 0x00 = msub %d0, %d0, %d0, %d0
+0x33, 0x00, 0x20, 0x00 = msub %d0, %d0, %d0, 0
+0x33, 0x00, 0x60, 0x00 = msub %e0, %e0, %d0, 0
+0x23, 0x00, 0x6a, 0x00 = msub %e0, %e0, %d0, %d0
+0x6b, 0x00, 0x71, 0x00 = msub.f %d0, %d0, %d0, %d0
+0xa3, 0x00, 0x60, 0x00 = msub.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x64, 0x00 = msub.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x68, 0x00 = msub.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x6c, 0x00 = msub.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x10, 0x00 = msub.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x00, 0x00 = msub.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x04, 0x00 = msub.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x08, 0x00 = msub.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x14, 0x00 = msub.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0x60, 0x00 = msub.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0x64, 0x00 = msub.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0x6c, 0x00 = msub.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0x70, 0x00 = msub.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0x74, 0x00 = msub.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x40, 0x00 = msub.u %e0, %e0, %d0, 0
+0x23, 0x00, 0x68, 0x00 = msub.u %e0, %e0, %d0, %d0
+0xe3, 0x00, 0x60, 0x00 = msubad.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x64, 0x00 = msubad.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x68, 0x00 = msubad.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x6c, 0x00 = msubad.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x70, 0x00 = msubadm.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x74, 0x00 = msubadm.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x78, 0x00 = msubadm.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x7c, 0x00 = msubadm.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0xf0, 0x00 = msubadms.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xf4, 0x00 = msubadms.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xf8, 0x00 = msubadms.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xfc, 0x00 = msubadms.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x30, 0x00 = msubadr.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0x34, 0x00 = msubadr.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0x38, 0x00 = msubadr.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0x3c, 0x00 = msubadr.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xb0, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0xb4, 0x00 = msubadrs.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0xb8, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0xbc, 0x00 = msubadrs.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xe0, 0x00 = msubads.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xe4, 0x00 = msubads.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xe8, 0x00 = msubads.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xec, 0x00 = msubads.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0x70, 0x00 = msubm.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x74, 0x00 = msubm.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x78, 0x00 = msubm.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x7c, 0x00 = msubm.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0xf0, 0x00 = msubms.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xf4, 0x00 = msubms.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xf8, 0x00 = msubms.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xfc, 0x00 = msubms.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x78, 0x00 = msubr.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x30, 0x00 = msubr.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0x34, 0x00 = msubr.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0x38, 0x00 = msubr.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0x3c, 0x00 = msubr.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x18, 0x00 = msubr.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x1c, 0x00 = msubr.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xf8, 0x00 = msubrs.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb0, 0x00 = msubrs.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb4, 0x00 = msubrs.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0xb8, 0x00 = msubrs.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0xbc, 0x00 = msubrs.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x98, 0x00 = msubrs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x9c, 0x00 = msubrs.q %d0, %d0, %d0l, %d0l, 0
+0x23, 0x00, 0x8a, 0x00 = msubs %d0, %d0, %d0, %d0
+0x33, 0x00, 0xa0, 0x00 = msubs %d0, %d0, %d0, 0
+0x33, 0x00, 0xe0, 0x00 = msubs %e0, %e0, %d0, 0
+0x23, 0x00, 0xea, 0x00 = msubs %e0, %e0, %d0, %d0
+0xa3, 0x00, 0xe0, 0x00 = msubs.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xe4, 0x00 = msubs.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xe8, 0x00 = msubs.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xec, 0x00 = msubs.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x90, 0x00 = msubs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x80, 0x00 = msubs.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x84, 0x00 = msubs.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x88, 0x00 = msubs.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x94, 0x00 = msubs.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xe0, 0x00 = msubs.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0xe4, 0x00 = msubs.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0xec, 0x00 = msubs.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0xf0, 0x00 = msubs.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0xf4, 0x00 = msubs.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x80, 0x00 = msubs.u %d0, %d0, %d0, 0
+0x23, 0x00, 0x88, 0x00 = msubs.u %d0, %d0, %d0, %d0
+0x33, 0x00, 0xc0, 0x00 = msubs.u %e0, %e0, %d0, 0
+0x23, 0x00, 0xe8, 0x00 = msubs.u %e0, %e0, %d0, %d0
+0xcd, 0x00, 0x00, 0x00 = mtcr 0, %d0
+0xe2, 0x00 = mul %d0, %d0
+0x53, 0x00, 0x20, 0x00 = mul %d0, %d0, 0
+0x73, 0x00, 0x0a, 0x00 = mul %d0, %d0, %d0
+0x53, 0x00, 0x60, 0x00 = mul %e0, %d0, 0
+0x73, 0x00, 0x6a, 0x00 = mul %e0, %d0, %d0
+0x4b, 0x00, 0x41, 0x00 = mul.f %d0, %d0, %d0
+0xb3, 0x00, 0x60, 0x00 = mul.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x64, 0x00 = mul.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x68, 0x00 = mul.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x6c, 0x00 = mul.h %e0, %d0, %d0uu, 0
+0x93, 0x00, 0x00, 0x00 = mul.q %d0, %d0, %d0u, 0
+0x93, 0x00, 0x04, 0x00 = mul.q %d0, %d0, %d0l, 0
+0x93, 0x00, 0x08, 0x00 = mul.q %d0, %d0, %d0, 0
+0x93, 0x00, 0x10, 0x00 = mul.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x14, 0x00 = mul.q %d0, %d0l, %d0l, 0
+0x93, 0x00, 0x60, 0x00 = mul.q %e0, %d0, %d0u, 0
+0x93, 0x00, 0x64, 0x00 = mul.q %e0, %d0, %d0l, 0
+0x93, 0x00, 0x6c, 0x00 = mul.q %e0, %d0, %d0, 0
+0x53, 0x00, 0x40, 0x00 = mul.u %e0, %d0, 0
+0x73, 0x00, 0x68, 0x00 = mul.u %e0, %d0, %d0
+0xb3, 0x00, 0x70, 0x00 = mulm.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x74, 0x00 = mulm.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x78, 0x00 = mulm.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x7c, 0x00 = mulm.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0xf0, 0x00 = mulms.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0xf4, 0x00 = mulms.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0xf8, 0x00 = mulms.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0xfc, 0x00 = mulms.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0x30, 0x00 = mulr.h %d0, %d0, %d0ul, 0
+0xb3, 0x00, 0x34, 0x00 = mulr.h %d0, %d0, %d0lu, 0
+0xb3, 0x00, 0x38, 0x00 = mulr.h %d0, %d0, %d0ll, 0
+0xb3, 0x00, 0x3c, 0x00 = mulr.h %d0, %d0, %d0uu, 0
+0x93, 0x00, 0x18, 0x00 = mulr.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x1c, 0x00 = mulr.q %d0, %d0l, %d0l, 0
+0x53, 0x00, 0xa0, 0x00 = muls %d0, %d0, 0
+0x73, 0x00, 0x8a, 0x00 = muls %d0, %d0, %d0
+0x53, 0x00, 0x80, 0x00 = muls.u %d0, %d0, 0
+0x73, 0x00, 0x88, 0x00 = muls.u %d0, %d0, %d0
+0x0f, 0x00, 0x90, 0x00 = nand %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x01 = nand %d0, %d0, 0
+0x07, 0x00, 0x00, 0x00 = nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x10, 0x01 = ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x02 = ne %d0, %d0, 0
+0x01, 0x00, 0x10, 0x04 = ne.a %d0, %a0, %a0
+0x01, 0x00, 0x90, 0x04 = nez.a %d0, %a0
+0x00, 0x00 = nop
+0x0d, 0x00, 0x00, 0x00 = nop
+0x46, 0x00 = nor %d0
+0x0f, 0x00, 0xb0, 0x00 = nor %d0, %d0, %d0
+0x8f, 0x00, 0x60, 0x01 = nor %d0, %d0, 0
+0x87, 0x00, 0x40, 0x00 = nor.t %d0, %d0, 0, %d0, 0
+0xa6, 0x00 = or %d0, %d0
+0x96, 0x00 = or %d15, 0
+0x0f, 0x00, 0xa0, 0x00 = or %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x01 = or %d0, %d0, 0
+0xc7, 0x00, 0x00, 0x00 = or.and.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x60, 0x00 = or.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x02 = or.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x04 = or.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x02 = or.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x05 = or.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x02 = or.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x05 = or.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x02 = or.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x05 = or.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x02 = or.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x05 = or.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x02 = or.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x05 = or.ne %d0, %d0, 0
+0xc7, 0x00, 0x40, 0x00 = or.nor.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x20, 0x00 = or.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x20, 0x00 = or.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xf0, 0x00 = orn %d0, %d0, %d0
+0x8f, 0x00, 0xe0, 0x01 = orn %d0, %d0, 0
+0x07, 0x00, 0x20, 0x00 = orn.t %d0, %d0, 0, %d0, 0
+0x6b, 0x00, 0x00, 0x00 = pack %d0, %e0, %d0
+0x4b, 0x00, 0x20, 0x00 = parity %d0, %d0
+0x4b, 0x00, 0x51, 0x01 = q31tof %d0, %d0, %d0
+0x4b, 0x00, 0x91, 0x01 = qseed.f %d0, %d0
+0x00, 0x90 = ret
+0x0d, 0x00, 0x80, 0x01 = ret
+0x00, 0x80 = rfe
+0x0d, 0x00, 0xc0, 0x01 = rfe
+0x0d, 0x00, 0x40, 0x01 = rfm
+0x0d, 0x00, 0x40, 0x02 = rslcx
+0x2f, 0x00, 0x00, 0x00 = rstv
+0x32, 0x50 = rsub %d0
+0x8b, 0x00, 0x00, 0x01 = rsub %d0, %d0, 0
+0x8b, 0x00, 0x40, 0x01 = rsubs %d0, %d0, 0
+0x8b, 0x00, 0x60, 0x01 = rsubs.u %d0, %d0, 0
+0x32, 0x00 = sat.b %d0
+0x0b, 0x00, 0xe0, 0x05 = sat.b %d0, %d0
+0x32, 0x10 = sat.bu %d0
+0x0b, 0x00, 0xf0, 0x05 = sat.bu %d0, %d0
+0x32, 0x20 = sat.h %d0
+0x0b, 0x00, 0xe0, 0x07 = sat.h %d0, %d0
+0x32, 0x30 = sat.hu %d0
+0x0b, 0x00, 0xf0, 0x07 = sat.hu %d0, %d0
+0x2b, 0x00, 0x40, 0x00 = sel %d0, %d0, %d0, %d0
+0xab, 0x00, 0x80, 0x00 = sel %d0, %d0, %d0, 0
+0x2b, 0x00, 0x50, 0x00 = seln %d0, %d0, %d0, %d0
+0xab, 0x00, 0xa0, 0x00 = seln %d0, %d0, %d0, 0
+0x06, 0x00 = sh %d0, 0
+0x0f, 0x00, 0x00, 0x00 = sh %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x00 = sh %d0, %d0, 0
+0x27, 0x00, 0x00, 0x00 = sh.and.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x60, 0x00 = sh.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x03 = sh.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x06 = sh.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x03 = sh.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x07 = sh.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x03 = sh.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x07 = sh.ge.u %d0, %d0, 0
+0x0f, 0x00, 0x00, 0x04 = sh.h %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x08 = sh.h %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x03 = sh.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x07 = sh.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x03 = sh.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x07 = sh.lt.u %d0, %d0, 0
+0xa7, 0x00, 0x00, 0x00 = sh.nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x80, 0x03 = sh.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x07 = sh.ne %d0, %d0, 0
+0x27, 0x00, 0x40, 0x00 = sh.nor.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x20, 0x00 = sh.or.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x20, 0x00 = sh.orn.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x40, 0x00 = sh.xnor.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x60, 0x00 = sh.xor.t %d0, %d0, 0, %d0, 0
+0x86, 0x00 = sha %d0, 0
+0x0f, 0x00, 0x10, 0x00 = sha %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x00 = sha %d0, %d0, 0
+0x0f, 0x00, 0x10, 0x04 = sha.h %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x08 = sha.h %d0, %d0, 0
+0x0f, 0x00, 0x20, 0x00 = shas %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x00 = shas %d0, %d0, 0
+0xf8, 0x00 = st.a [%sp]0, %a15
+0xec, 0x00 = st.a [%a0]0, %a15
+0xe8, 0x00 = st.a [%a15]0, %a0
+0xe4, 0x00 = st.a [%a0+], %a0
+0xf4, 0x00 = st.a [%a0], %a0
+0x89, 0x00, 0x80, 0x01 = st.a [%a0+]0, %a0
+0xa9, 0x00, 0x80, 0x01 = st.a [%p0+r], %a0
+0x89, 0x00, 0x80, 0x05 = st.a [+%a0]0, %a0
+0xa9, 0x00, 0x80, 0x05 = st.a [%p0+c]0, %a0
+0xa5, 0x00, 0x00, 0x08 = st.a 0, %a0
+0x89, 0x00, 0x80, 0x09 = st.a [%a0]0, %a0
+0x34, 0x00 = st.b [%a0], %d0
+0x28, 0x00 = st.b [%a15]0, %d0
+0x2c, 0x00 = st.b [%a0]0, %d15
+0x24, 0x00 = st.b [%a0+], %d0
+0x25, 0x00, 0x00, 0x00 = st.b 0, %d0
+0x89, 0x00, 0x00, 0x00 = st.b [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x00 = st.b [%p0+r], %d0
+0x89, 0x00, 0x00, 0x04 = st.b [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x04 = st.b [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x08 = st.b [%a0]0, %d0
+0x89, 0x00, 0x40, 0x01 = st.d [%a0+]0, %e0
+0xa9, 0x00, 0x40, 0x01 = st.d [%p0+r], %e0
+0xa5, 0x00, 0x00, 0x04 = st.d 0, %e0
+0x89, 0x00, 0x40, 0x05 = st.d [+%a0]0, %e0
+0xa9, 0x00, 0x40, 0x05 = st.d [%p0+c]0, %e0
+0x89, 0x00, 0x40, 0x09 = st.d [%a0]0, %e0
+0x89, 0x00, 0xc0, 0x01 = st.da [%a0+]0, %p0
+0xa9, 0x00, 0xc0, 0x01 = st.da [%p0+r], %p0
+0x89, 0x00, 0xc0, 0x05 = st.da [+%a0]0, %p0
+0xa9, 0x00, 0xc0, 0x05 = st.da [%p0+c]0, %p0
+0x89, 0x00, 0xc0, 0x09 = st.da [%a0]0, %p0
+0xa5, 0x00, 0x00, 0x0c = st.da 0, %p0
+0xa4, 0x00 = st.h [%a0+], %d0
+0xa8, 0x00 = st.h [%a15]0, %d0
+0xac, 0x00 = st.h [%a0]0, %d15
+0xb4, 0x00 = st.h [%a0], %d0
+0x89, 0x00, 0x80, 0x00 = st.h [%a0+]0, %d0
+0xa9, 0x00, 0x80, 0x00 = st.h [%p0+r], %d0
+0x89, 0x00, 0x80, 0x04 = st.h [+%a0]0, %d0
+0xa9, 0x00, 0x80, 0x04 = st.h [%p0+c]0, %d0
+0x25, 0x00, 0x00, 0x08 = st.h 0, %d0
+0x89, 0x00, 0x80, 0x08 = st.h [%a0]0, %d0
+0x65, 0x00, 0x00, 0x00 = st.q 0, %d0
+0x89, 0x00, 0x00, 0x02 = st.q [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x02 = st.q [%p0+r], %d0
+0x89, 0x00, 0x00, 0x06 = st.q [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x06 = st.q [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x0a = st.q [%a0]0, %d0
+0xd5, 0x00, 0x00, 0x00 = st.t 0, 0, 0
+0x78, 0x00 = st.w [%sp]0, %d15
+0x74, 0x00 = st.w [%a0], %d0
+0x64, 0x00 = st.w [%a0+], %d0
+0x68, 0x00 = st.w [%a15]0, %d0
+0x6c, 0x00 = st.w [%a0]0, %d15
+0x59, 0x00, 0x00, 0x00 = st.w [%a0]0, %d0
+0xa5, 0x00, 0x00, 0x00 = st.w 0, %d0
+0x89, 0x00, 0x00, 0x01 = st.w [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x01 = st.w [%p0+r], %d0
+0x89, 0x00, 0x00, 0x05 = st.w [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x05 = st.w [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x09 = st.w [%a0]0, %d0
+0x15, 0x00, 0x00, 0x00 = stlcx 0
+0x49, 0x00, 0x80, 0x09 = stlcx [%a0]0
+0x15, 0x00, 0x00, 0x04 = stucx 0
+0x49, 0x00, 0xc0, 0x09 = stucx [%a0]0
+0x52, 0x00 = sub %d0, %d15, %d0
+0x5a, 0x00 = sub %d15, %d0, %d0
+0xa2, 0x00 = sub %d0, %d0
+0x0b, 0x00, 0x80, 0x00 = sub %d0, %d0, %d0
+0x20, 0x00 = sub.a %sp, 0
+0x01, 0x00, 0x20, 0x00 = sub.a %a0, %a0, %a0
+0x0b, 0x00, 0x80, 0x04 = sub.b %d0, %d0, %d0
+0x6b, 0x00, 0x31, 0x00 = sub.f %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x06 = sub.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x00 = subc %d0, %d0, %d0
+0x62, 0x00 = subs %d0, %d0
+0x0b, 0x00, 0xa0, 0x00 = subs %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x06 = subs.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x06 = subs.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x00 = subs.u %d0, %d0, %d0
+0x0b, 0x00, 0xc0, 0x00 = subx %d0, %d0, %d0
+0x0d, 0x00, 0x00, 0x02 = svlcx
+0x49, 0x00, 0x00, 0x00 = swap.w [%a0+]0, %d0
+0x69, 0x00, 0x00, 0x00 = swap.w [%p0+r], %d0
+0xe5, 0x00, 0x00, 0x00 = swap.w 0, %d0
+0x49, 0x00, 0x00, 0x04 = swap.w [+%a0]0, %d0
+0x69, 0x00, 0x00, 0x04 = swap.w [%p0+c]0, %d0
+0x49, 0x00, 0x00, 0x08 = swap.w [%a0]0, %d0
+0xad, 0x00, 0x80, 0x00 = syscall 0
+0x75, 0x00, 0x00, 0x00 = tlbdemap %d0
+0x75, 0x00, 0x40, 0x00 = tlbflush.a
+0x75, 0x00, 0x50, 0x00 = tlbflush.b
+0x75, 0x00, 0x00, 0x04 = tlbmap %e0
+0x75, 0x00, 0x80, 0x00 = tlbprobe.a %d0
+0x75, 0x00, 0x90, 0x00 = tlbprobe.i %d0
+0x0d, 0x00, 0x40, 0x05 = trapsv
+0x0d, 0x00, 0x00, 0x05 = trapv
+0x4b, 0x00, 0x80, 0x00 = unpack %e0, %d0
+0x4b, 0x00, 0xc1, 0x00 = updfl %d0
+0x4b, 0x00, 0x61, 0x01 = utof %d0, %d0
+0x0f, 0x00, 0xd0, 0x00 = xnor %d0, %d0, %d0
+0x8f, 0x00, 0xa0, 0x01 = xnor %d0, %d0, 0
+0x07, 0x00, 0x40, 0x00 = xnor.t %d0, %d0, 0, %d0, 0
+0xc6, 0x00 = xor %d0, %d0
+0x0f, 0x00, 0xc0, 0x00 = xor %d0, %d0, %d0
+0x8f, 0x00, 0x80, 0x01 = xor %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x02 = xor.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x05 = xor.eq %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x03 = xor.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x06 = xor.ge %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x03 = xor.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x06 = xor.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x03 = xor.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x06 = xor.lt %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x03 = xor.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x06 = xor.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x00, 0x03 = xor.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x06 = xor.ne %d0, %d0, 0
+0x07, 0x00, 0x60, 0x00 = xor.t %d0, %d0, 0, %d0, 0
diff --git a/suite/MC/TriCore/tc131.s.cs b/suite/MC/TriCore/tc131.s.cs
new file mode 100644
index 0000000000..4cdaae85dc
--- /dev/null
+++ b/suite/MC/TriCore/tc131.s.cs
@@ -0,0 +1,795 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_131, None
+0x0b, 0x00, 0xc0, 0x01 = abs %d0, %d0
+0x0b, 0x00, 0xc0, 0x05 = abs.b %d0, %d0
+0x0b, 0x00, 0xc0, 0x07 = abs.h %d0, %d0
+0x0b, 0x00, 0xe0, 0x00 = absdif %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x01 = absdif %d0, %d0, 0
+0x0b, 0x00, 0xe0, 0x04 = absdif.b %d0, %d0, %d0
+0x0b, 0x00, 0xe0, 0x06 = absdif.h %d0, %d0, %d0
+0x0b, 0x00, 0xf0, 0x00 = absdifs %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x01 = absdifs %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x06 = absdifs.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x01 = abss %d0, %d0
+0x0b, 0x00, 0xd0, 0x07 = abss.h %d0, %d0
+0x12, 0x00 = add %d0, %d15, %d0
+0x92, 0x00 = add %d0, %d15, 0
+0x1a, 0x00 = add %d15, %d0, %d0
+0x42, 0x00 = add %d0, %d0
+0x9a, 0x00 = add %d15, %d0, 0
+0xc2, 0x00 = add %d0, 0
+0x0b, 0x00, 0x00, 0x00 = add %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x00 = add %d0, %d0, 0
+0x30, 0x00 = add.a %a0, %a0
+0xb0, 0x00 = add.a %a0, 0
+0x01, 0x00, 0x10, 0x00 = add.a %a0, %a0, %a0
+0x0b, 0x00, 0x00, 0x04 = add.b %d0, %d0, %d0
+0x6b, 0x00, 0x21, 0x00 = add.f %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x06 = add.h %d0, %d0, %d0
+0x0b, 0x00, 0x50, 0x00 = addc %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x00 = addc %d0, %d0, 0
+0x1b, 0x00, 0x00, 0x00 = addi %d0, %d0, 0
+0x9b, 0x00, 0x00, 0x00 = addih %d0, %d0, 0
+0x11, 0x00, 0x00, 0x00 = addih.a %a0, %a0, 0
+0x22, 0x00 = adds %d0, %d0
+0x0b, 0x00, 0x20, 0x00 = adds %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x00 = adds %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x06 = adds.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x06 = adds.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x00 = adds.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x00 = adds.u %d0, %d0, 0
+0x10, 0x00 = addsc.a %a0, %a0, %d15, 0
+0x01, 0x00, 0x00, 0x06 = addsc.a %a0, %a0, %d0, 0
+0x01, 0x00, 0x20, 0x06 = addsc.at %a0, %a0, %d0
+0x0b, 0x00, 0x40, 0x00 = addx %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x00 = addx %d0, %d0, 0
+0x26, 0x00 = and %d0, %d0
+0x16, 0x00 = and %d15, 0
+0x0f, 0x00, 0x80, 0x00 = and %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x01 = and %d0, %d0, 0
+0x47, 0x00, 0x00, 0x00 = and.and.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x60, 0x00 = and.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x00, 0x02 = and.eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x04 = and.eq %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x02 = and.ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x04 = and.ge %d0, %d0, 0
+0x0b, 0x00, 0x50, 0x02 = and.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x04 = and.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x02 = and.lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x04 = and.lt %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x02 = and.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x04 = and.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x02 = and.ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x04 = and.ne %d0, %d0, 0
+0x47, 0x00, 0x40, 0x00 = and.nor.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x20, 0x00 = and.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x00, 0x00 = and.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xe0, 0x00 = andn %d0, %d0, %d0
+0x8f, 0x00, 0xc0, 0x01 = andn %d0, %d0, 0
+0x87, 0x00, 0x60, 0x00 = andn.t %d0, %d0, 0, %d0, 0
+0xe0, 0x00 = bisr 0
+0xad, 0x00, 0x00, 0x00 = bisr 0
+0x4b, 0x00, 0x10, 0x00 = bmerge %d0, %d0, %d0
+0x4b, 0x00, 0x90, 0x00 = bsplit %e0, %d0
+0x89, 0x00, 0x80, 0x03 = cachea.i [%a0+]0
+0xa9, 0x00, 0x80, 0x03 = cachea.i [%p0+r]
+0x89, 0x00, 0x80, 0x07 = cachea.i [+%a0]0
+0xa9, 0x00, 0x80, 0x07 = cachea.i [%p0+c]0
+0x89, 0x00, 0x80, 0x0b = cachea.i [%a0]0
+0x89, 0x00, 0x00, 0x03 = cachea.w [%a0+]0
+0xa9, 0x00, 0x00, 0x03 = cachea.w [%p0+r]
+0x89, 0x00, 0x00, 0x07 = cachea.w [+%a0]0
+0xa9, 0x00, 0x00, 0x07 = cachea.w [%p0+c]0
+0x89, 0x00, 0x00, 0x0b = cachea.w [%a0]0
+0x89, 0x00, 0x40, 0x03 = cachea.wi [%a0+]0
+0xa9, 0x00, 0x40, 0x03 = cachea.wi [%p0+r]
+0x89, 0x00, 0x40, 0x07 = cachea.wi [+%a0]0
+0xa9, 0x00, 0x40, 0x07 = cachea.wi [%p0+c]0
+0x89, 0x00, 0x40, 0x0b = cachea.wi [%a0]0
+0x89, 0x00, 0xc0, 0x02 = cachei.w [%a0+]0
+0x89, 0x00, 0xc0, 0x06 = cachei.w [+%a0]0
+0x89, 0x00, 0xc0, 0x0a = cachei.w [%a0]0
+0x89, 0x00, 0xc0, 0x03 = cachei.wi [%a0+]0
+0x89, 0x00, 0xc0, 0x07 = cachei.wi [+%a0]0
+0x89, 0x00, 0xc0, 0x0b = cachei.wi [%a0]0
+0x8a, 0x00 = cadd %d0, %d15, 0
+0x2b, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, %d0
+0xab, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, 0
+0xca, 0x00 = caddn %d0, %d15, 0
+0x2b, 0x00, 0x10, 0x00 = caddn %d0, %d0, %d0, %d0
+0xab, 0x00, 0x20, 0x00 = caddn %d0, %d0, %d0, 0
+0x5c, 0x00 = call 0
+0x6d, 0x00, 0x00, 0x00 = call 0
+0xed, 0x00, 0x00, 0x00 = calla 0
+0x2d, 0x00, 0x00, 0x00 = calli %a0
+0x0f, 0x00, 0xc0, 0x01 = clo %d0, %d0
+0x0f, 0x00, 0xd0, 0x07 = clo.h %d0, %d0
+0x0f, 0x00, 0xd0, 0x01 = cls %d0, %d0
+0x0f, 0x00, 0xe0, 0x07 = cls.h %d0, %d0
+0x0f, 0x00, 0xb0, 0x01 = clz %d0, %d0
+0x0f, 0x00, 0xc0, 0x07 = clz.h %d0, %d0
+0x2a, 0x00 = cmov %d0, %d15, %d0
+0xaa, 0x00 = cmov %d0, %d15, 0
+0x6a, 0x00 = cmovn %d0, %d15, %d0
+0xea, 0x00 = cmovn %d0, %d15, 0
+0x4b, 0x00, 0x00, 0x00 = cmp.f %d0, %d0, %d0
+0x2b, 0x00, 0x20, 0x00 = csub %d0, %d0, %d0, %d0
+0x2b, 0x00, 0x30, 0x00 = csubn %d0, %d0, %d0, %d0
+0x00, 0xa0 = debug
+0x0d, 0x00, 0x00, 0x01 = debug
+0x77, 0x00, 0x00, 0x00 = dextr %d0, %d0, %d0, 0
+0x17, 0x00, 0x80, 0x00 = dextr %d0, %d0, %d0, %d0
+0x0d, 0x00, 0x40, 0x03 = disable
+0x4b, 0x00, 0x51, 0x00 = div.f %d0, %d0, %d0
+0x0d, 0x00, 0x80, 0x04 = dsync
+0x6b, 0x00, 0xd0, 0x00 = dvadj %e0, %e0, %d0
+0x4b, 0x00, 0xa0, 0x01 = dvinit %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x05 = dvinit.b %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x04 = dvinit.bu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x03 = dvinit.h %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x02 = dvinit.hu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x00 = dvinit.u %e0, %d0, %d0
+0x6b, 0x00, 0xf0, 0x00 = dvstep %e0, %e0, %d0
+0x6b, 0x00, 0xe0, 0x00 = dvstep.u %e0, %e0, %d0
+0x0d, 0x00, 0x00, 0x03 = enable
+0x3a, 0x00 = eq %d15, %d0, %d0
+0xba, 0x00 = eq %d15, %d0, 0
+0x0b, 0x00, 0x00, 0x01 = eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x02 = eq %d0, %d0, 0
+0x01, 0x00, 0x00, 0x04 = eq.a %d0, %a0, %a0
+0x0b, 0x00, 0x00, 0x05 = eq.b %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x07 = eq.h %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x09 = eq.w %d0, %d0, %d0
+0x0b, 0x00, 0x60, 0x05 = eqany.b %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0a = eqany.b %d0, %d0, 0
+0x0b, 0x00, 0x60, 0x07 = eqany.h %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0e = eqany.h %d0, %d0, 0
+0x01, 0x00, 0x80, 0x04 = eqz.a %d0, %a0
+0x17, 0x00, 0x40, 0x00 = extr %d0, %d0, %e0
+0x37, 0x00, 0x40, 0x00 = extr %d0, %d0, 0, 0
+0x57, 0x00, 0x40, 0x00 = extr %d0, %d0, %d0, 0
+0x17, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %e0
+0x37, 0x00, 0x60, 0x00 = extr.u %d0, %d0, 0, 0
+0x57, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %d0, 0
+0x4b, 0x00, 0x01, 0x01 = ftoi %d0, %d0
+0x4b, 0x00, 0x11, 0x01 = ftoq31 %d0, %d0, %d0
+0x4b, 0x00, 0x21, 0x01 = ftou %d0, %d0
+0x4b, 0x00, 0x31, 0x01 = ftoiz %d0, %d0
+0x4b, 0x00, 0x81, 0x01 = ftoq31z %d0, %d0, %d0
+0x4b, 0x00, 0x71, 0x01 = ftouz %d0, %d0
+0x0b, 0x00, 0x40, 0x01 = ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x02 = ge %d0, %d0, 0
+0x01, 0x00, 0x30, 0x04 = ge.a %d0, %a0, %a0
+0x0b, 0x00, 0x50, 0x01 = ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x02 = ge.u %d0, %d0, 0
+0x37, 0x00, 0x20, 0x00 = imask %e0, %d0, 0, 0
+0x57, 0x00, 0x20, 0x00 = imask %e0, %d0, %d0, 0
+0xb7, 0x00, 0x20, 0x00 = imask %e0, 0, 0, 0
+0xd7, 0x00, 0x20, 0x00 = imask %e0, 0, %d0, 0
+0x67, 0x00, 0x00, 0x00 = ins.t %d0, %d0, 0, %d0, 0
+0x17, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %e0
+0x37, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, 0, 0
+0x57, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %d0, 0
+0x97, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %e0
+0xb7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, 0, 0
+0xd7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %d0, 0
+0x67, 0x00, 0x20, 0x00 = insn.t %d0, %d0, 0, %d0, 0
+0x0d, 0x00, 0xc0, 0x04 = isync
+0x4b, 0x00, 0x41, 0x01 = itof %d0, %d0
+0x6b, 0x00, 0xa0, 0x00 = ixmax %e0, %e0, %d0
+0x6b, 0x00, 0xb0, 0x00 = ixmax.u %e0, %e0, %d0
+0x6b, 0x00, 0x80, 0x00 = ixmin %e0, %e0, %d0
+0x6b, 0x00, 0x90, 0x00 = ixmin.u %e0, %e0, %d0
+0x3c, 0x00 = j 0
+0x1d, 0x00, 0x00, 0x00 = j 0
+0x9d, 0x00, 0x00, 0x00 = ja 0
+0x3e, 0x00 = jeq %d15, %d0, 0
+0x1e, 0x00 = jeq %d15, 0, 0
+0x5f, 0x00, 0x00, 0x00 = jeq %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x00 = jeq %d0, 0, 0
+0x7d, 0x00, 0x00, 0x00 = jeq.a %a0, %a0, 0
+0x7f, 0x00, 0x00, 0x00 = jge %d0, %d0, 0
+0xff, 0x00, 0x00, 0x00 = jge %d0, 0, 0
+0x7f, 0x00, 0x00, 0x80 = jge.u %d0, %d0, 0
+0xff, 0x00, 0x00, 0x80 = jge.u %d0, 0, 0
+0xce, 0x00 = jgez %d0, 0
+0x4e, 0x00 = jgtz %d0, 0
+0xdc, 0x00 = ji %a0
+0x2d, 0x00, 0x30, 0x00 = ji %a0
+0x5d, 0x00, 0x00, 0x00 = jl 0
+0xdd, 0x00, 0x00, 0x00 = jla 0
+0x8e, 0x00 = jlez %d0, 0
+0x2d, 0x00, 0x20, 0x00 = jli %a0
+0x3f, 0x00, 0x00, 0x00 = jlt %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x00 = jlt %d0, 0, 0
+0x3f, 0x00, 0x00, 0x80 = jlt.u %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x80 = jlt.u %d0, 0, 0
+0x0e, 0x00 = jltz %d0, 0
+0x7e, 0x00 = jne %d15, %d0, 0
+0x5e, 0x00 = jne %d15, 0, 0
+0x5f, 0x00, 0x00, 0x80 = jne %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x80 = jne %d0, 0, 0
+0x7d, 0x00, 0x00, 0x80 = jne.a %a0, %a0, 0
+0x1f, 0x00, 0x00, 0x80 = jned %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x80 = jned %d0, 0, 0
+0x1f, 0x00, 0x00, 0x00 = jnei %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x00 = jnei %d0, 0, 0
+0xee, 0x00 = jnz %d15, 0
+0xf6, 0x00 = jnz %d0, 0
+0x7c, 0x00 = jnz.a %a0, 0
+0xbd, 0x00, 0x00, 0x80 = jnz.a %a0, 0
+0xae, 0x00 = jnz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x80 = jnz.t %d0, 0, 0
+0x6e, 0x00 = jz %d15, 0
+0x76, 0x00 = jz %d0, 0
+0xbc, 0x00 = jz.a %a0, 0
+0xbd, 0x00, 0x00, 0x00 = jz.a %a0, 0
+0x2e, 0x00 = jz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x00 = jz.t %d0, 0, 0
+0xd8, 0x00 = ld.a %a15, [%sp]0
+0xc8, 0x00 = ld.a %a0, [%a15]0
+0xcc, 0x00 = ld.a %a15, [%a0]0
+0xc4, 0x00 = ld.a %a0, [%a0+]
+0xd4, 0x00 = ld.a %a0, [%a0]
+0x99, 0x00, 0x00, 0x00 = ld.a %a0, [%a0]0
+0x09, 0x00, 0x80, 0x01 = ld.a %a0, [%a0+]0
+0x29, 0x00, 0x80, 0x01 = ld.a %a0, [%p0+r]
+0x09, 0x00, 0x80, 0x05 = ld.a %a0, [+%a0]0
+0x29, 0x00, 0x80, 0x05 = ld.a %a0, [%p0+c]0
+0x85, 0x00, 0x00, 0x08 = ld.a %a0, 0
+0x09, 0x00, 0x80, 0x09 = ld.a %a0, [%a0]0
+0x05, 0x00, 0x00, 0x00 = ld.b %d0, 0
+0x09, 0x00, 0x00, 0x00 = ld.b %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x00 = ld.b %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x04 = ld.b %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x04 = ld.b %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x08 = ld.b %d0, [%a0]0
+0x14, 0x00 = ld.bu %d0, [%a0]
+0x0c, 0x00 = ld.bu %d15, [%a0]0
+0x08, 0x00 = ld.bu %d0, [%a15]0
+0x04, 0x00 = ld.bu %d0, [%a0+]
+0x09, 0x00, 0x40, 0x00 = ld.bu %d0, [%a0+]0
+0x29, 0x00, 0x40, 0x00 = ld.bu %d0, [%p0+r]
+0x05, 0x00, 0x00, 0x04 = ld.bu %d0, 0
+0x09, 0x00, 0x40, 0x04 = ld.bu %d0, [+%a0]0
+0x29, 0x00, 0x40, 0x04 = ld.bu %d0, [%p0+c]0
+0x09, 0x00, 0x40, 0x08 = ld.bu %d0, [%a0]0
+0x09, 0x00, 0x40, 0x01 = ld.d %e0, [%a0+]0
+0x29, 0x00, 0x40, 0x01 = ld.d %e0, [%p0+r]
+0x85, 0x00, 0x00, 0x04 = ld.d %e0, 0
+0x09, 0x00, 0x40, 0x05 = ld.d %e0, [+%a0]0
+0x29, 0x00, 0x40, 0x05 = ld.d %e0, [%p0+c]0
+0x09, 0x00, 0x40, 0x09 = ld.d %e0, [%a0]0
+0x09, 0x00, 0xc0, 0x01 = ld.da %p0, [%a0+]0
+0x29, 0x00, 0xc0, 0x01 = ld.da %p0, [%p0+r]
+0x09, 0x00, 0xc0, 0x05 = ld.da %p0, [+%a0]0
+0x29, 0x00, 0xc0, 0x05 = ld.da %p0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x09 = ld.da %p0, [%a0]0
+0x85, 0x00, 0x00, 0x0c = ld.da %p0, 0
+0x84, 0x00 = ld.h %d0, [%a0+]
+0x8c, 0x00 = ld.h %d15, [%a0]0
+0x88, 0x00 = ld.h %d0, [%a15]0
+0x94, 0x00 = ld.h %d0, [%a0]
+0x09, 0x00, 0x80, 0x00 = ld.h %d0, [%a0+]0
+0x29, 0x00, 0x80, 0x00 = ld.h %d0, [%p0+r]
+0x09, 0x00, 0x80, 0x04 = ld.h %d0, [+%a0]0
+0x29, 0x00, 0x80, 0x04 = ld.h %d0, [%p0+c]0
+0x05, 0x00, 0x00, 0x08 = ld.h %d0, 0
+0x09, 0x00, 0x80, 0x08 = ld.h %d0, [%a0]0
+0x09, 0x00, 0xc0, 0x00 = ld.hu %d0, [%a0+]0
+0x29, 0x00, 0xc0, 0x00 = ld.hu %d0, [%p0+r]
+0x09, 0x00, 0xc0, 0x04 = ld.hu %d0, [+%a0]0
+0x29, 0x00, 0xc0, 0x04 = ld.hu %d0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x08 = ld.hu %d0, [%a0]0
+0x05, 0x00, 0x00, 0x0c = ld.hu %d0, 0
+0x45, 0x00, 0x00, 0x00 = ld.q %d0, 0
+0x09, 0x00, 0x00, 0x02 = ld.q %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x02 = ld.q %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x06 = ld.q %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x06 = ld.q %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x0a = ld.q %d0, [%a0]0
+0x58, 0x00 = ld.w %d15, [%sp]0
+0x54, 0x00 = ld.w %d0, [%a0]
+0x44, 0x00 = ld.w %d0, [%a0+]
+0x4c, 0x00 = ld.w %d15, [%a0]0
+0x48, 0x00 = ld.w %d0, [%a15]0
+0x19, 0x00, 0x00, 0x00 = ld.w %d0, [%a0]0
+0x85, 0x00, 0x00, 0x00 = ld.w %d0, 0
+0x09, 0x00, 0x00, 0x01 = ld.w %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x01 = ld.w %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x05 = ld.w %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x05 = ld.w %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x09 = ld.w %d0, [%a0]0
+0x15, 0x00, 0x00, 0x08 = ldlcx 0
+0x49, 0x00, 0x00, 0x09 = ldlcx [%a0]0
+0x49, 0x00, 0x40, 0x00 = ldmst [%a0+]0, %e0
+0x69, 0x00, 0x40, 0x00 = ldmst [%p0+r], %e0
+0xe5, 0x00, 0x00, 0x04 = ldmst 0, %e0
+0x49, 0x00, 0x40, 0x04 = ldmst [+%a0]0, %e0
+0x69, 0x00, 0x40, 0x04 = ldmst [%p0+c]0, %e0
+0x49, 0x00, 0x40, 0x08 = ldmst [%a0]0, %e0
+0x49, 0x00, 0x40, 0x09 = lducx [%a0]0
+0x15, 0x00, 0x00, 0x0c = lducx 0
+0xc5, 0x00, 0x00, 0x00 = lea %a0, 0
+0xd9, 0x00, 0x00, 0x00 = lea %a0, [%a0]0
+0x49, 0x00, 0x00, 0x0a = lea %a0, [%a0]0
+0xfc, 0x00 = loop %a0, -0x20
+0xfd, 0x00, 0x00, 0x00 = loop %a0, 0
+0xfd, 0x00, 0x00, 0x80 = loopu 0
+0x7a, 0x00 = lt %d15, %d0, %d0
+0xfa, 0x00 = lt %d15, %d0, 0
+0x0b, 0x00, 0x20, 0x01 = lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x02 = lt %d0, %d0, 0
+0x01, 0x00, 0x20, 0x04 = lt.a %d0, %a0, %a0
+0x0b, 0x00, 0x20, 0x05 = lt.b %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x05 = lt.bu %d0, %d0, %d0
+0x0b, 0x00, 0x20, 0x07 = lt.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x07 = lt.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x01 = lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x02 = lt.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x09 = lt.w %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x09 = lt.wu %d0, %d0, %d0
+0x03, 0x00, 0x0a, 0x00 = madd %d0, %d0, %d0, %d0
+0x13, 0x00, 0x20, 0x00 = madd %d0, %d0, %d0, 0
+0x13, 0x00, 0x60, 0x00 = madd %e0, %e0, %d0, 0
+0x03, 0x00, 0x6a, 0x00 = madd %e0, %e0, %d0, %d0
+0x6b, 0x00, 0x61, 0x00 = madd.f %d0, %d0, %d0, %d0
+0x83, 0x00, 0x60, 0x00 = madd.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x64, 0x00 = madd.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x68, 0x00 = madd.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x6c, 0x00 = madd.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x10, 0x00 = madd.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x00, 0x00 = madd.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x04, 0x00 = madd.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x08, 0x00 = madd.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x14, 0x00 = madd.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0x60, 0x00 = madd.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0x64, 0x00 = madd.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0x6c, 0x00 = madd.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0x70, 0x00 = madd.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0x74, 0x00 = madd.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x40, 0x00 = madd.u %e0, %e0, %d0, 0
+0x03, 0x00, 0x68, 0x00 = madd.u %e0, %e0, %d0, %d0
+0x83, 0x00, 0x70, 0x00 = maddm.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x74, 0x00 = maddm.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x78, 0x00 = maddm.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x7c, 0x00 = maddm.h %e0, %e0, %d0, %d0uu, 0
+0x83, 0x00, 0xf0, 0x00 = maddms.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xf4, 0x00 = maddms.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xf8, 0x00 = maddms.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xfc, 0x00 = maddms.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x78, 0x00 = maddr.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x30, 0x00 = maddr.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0x34, 0x00 = maddr.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0x38, 0x00 = maddr.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0x3c, 0x00 = maddr.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x18, 0x00 = maddr.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x1c, 0x00 = maddr.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xf8, 0x00 = maddrs.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xb0, 0x00 = maddrs.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0xb4, 0x00 = maddrs.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0xb8, 0x00 = maddrs.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0xbc, 0x00 = maddrs.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x98, 0x00 = maddrs.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x9c, 0x00 = maddrs.q %d0, %d0, %d0l, %d0l, 0
+0x03, 0x00, 0x8a, 0x00 = madds %d0, %d0, %d0, %d0
+0x13, 0x00, 0xa0, 0x00 = madds %d0, %d0, %d0, 0
+0x13, 0x00, 0xe0, 0x00 = madds %e0, %e0, %d0, 0
+0x03, 0x00, 0xea, 0x00 = madds %e0, %e0, %d0, %d0
+0x83, 0x00, 0xe0, 0x00 = madds.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xe4, 0x00 = madds.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xe8, 0x00 = madds.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xec, 0x00 = madds.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x90, 0x00 = madds.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x80, 0x00 = madds.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x84, 0x00 = madds.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x88, 0x00 = madds.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x94, 0x00 = madds.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xe0, 0x00 = madds.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0xe4, 0x00 = madds.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0xec, 0x00 = madds.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0xf0, 0x00 = madds.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0xf4, 0x00 = madds.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x80, 0x00 = madds.u %d0, %d0, %d0, 0
+0x03, 0x00, 0x88, 0x00 = madds.u %d0, %d0, %d0, %d0
+0x13, 0x00, 0xc0, 0x00 = madds.u %e0, %e0, %d0, 0
+0x03, 0x00, 0xe8, 0x00 = madds.u %e0, %e0, %d0, %d0
+0xc3, 0x00, 0x60, 0x00 = maddsu.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x64, 0x00 = maddsu.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x68, 0x00 = maddsu.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x6c, 0x00 = maddsu.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x70, 0x00 = maddsum.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x74, 0x00 = maddsum.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x78, 0x00 = maddsum.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x7c, 0x00 = maddsum.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0xf0, 0x00 = maddsums.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xf4, 0x00 = maddsums.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xf8, 0x00 = maddsums.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xfc, 0x00 = maddsums.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x30, 0x00 = maddsur.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0x34, 0x00 = maddsur.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0x38, 0x00 = maddsur.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0x3c, 0x00 = maddsur.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xb0, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0xb4, 0x00 = maddsurs.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0xb8, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0xbc, 0x00 = maddsurs.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xe0, 0x00 = maddsus.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xe4, 0x00 = maddsus.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xe8, 0x00 = maddsus.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xec, 0x00 = maddsus.h %e0, %e0, %d0, %d0uu, 0
+0x0b, 0x00, 0xa0, 0x01 = max %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x03 = max %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x05 = max.b %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x05 = max.bu %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x07 = max.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x07 = max.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x01 = max.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x03 = max.u %d0, %d0, 0
+0x4d, 0x00, 0x00, 0x00 = mfcr %d0, 0
+0x0b, 0x00, 0x80, 0x01 = min %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x03 = min %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x05 = min.b %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x05 = min.bu %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x07 = min.h %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x07 = min.hu %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x01 = min.u %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x03 = min.u %d0, %d0, 0
+0x02, 0x00 = mov %d0, %d0
+0x82, 0x00 = mov %d0, 0
+0xda, 0x00 = mov %d15, 0
+0x3b, 0x00, 0x00, 0x00 = mov %d0, 0
+0x0b, 0x00, 0xf0, 0x01 = mov %d0, %d0
+0xa0, 0x00 = mov.a %a0, 0
+0x60, 0x00 = mov.a %a0, %d0
+0x01, 0x00, 0x30, 0x06 = mov.a %a0, %d0
+0x40, 0x00 = mov.aa %a0, %a0
+0x01, 0x00, 0x00, 0x00 = mov.aa %a0, %a0
+0x80, 0x00 = mov.d %d0, %a0
+0x01, 0x00, 0xc0, 0x04 = mov.d %d0, %a0
+0xbb, 0x00, 0x00, 0x00 = mov.u %d0, 0
+0x7b, 0x00, 0x00, 0x00 = movh %d0, 0
+0x91, 0x00, 0x00, 0x00 = movh.a %a0, 0
+0x23, 0x00, 0x0a, 0x00 = msub %d0, %d0, %d0, %d0
+0x33, 0x00, 0x20, 0x00 = msub %d0, %d0, %d0, 0
+0x33, 0x00, 0x60, 0x00 = msub %e0, %e0, %d0, 0
+0x23, 0x00, 0x6a, 0x00 = msub %e0, %e0, %d0, %d0
+0x6b, 0x00, 0x71, 0x00 = msub.f %d0, %d0, %d0, %d0
+0xa3, 0x00, 0x60, 0x00 = msub.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x64, 0x00 = msub.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x68, 0x00 = msub.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x6c, 0x00 = msub.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x10, 0x00 = msub.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x00, 0x00 = msub.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x04, 0x00 = msub.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x08, 0x00 = msub.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x14, 0x00 = msub.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0x60, 0x00 = msub.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0x64, 0x00 = msub.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0x6c, 0x00 = msub.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0x70, 0x00 = msub.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0x74, 0x00 = msub.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x40, 0x00 = msub.u %e0, %e0, %d0, 0
+0x23, 0x00, 0x68, 0x00 = msub.u %e0, %e0, %d0, %d0
+0xe3, 0x00, 0x60, 0x00 = msubad.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x64, 0x00 = msubad.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x68, 0x00 = msubad.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x6c, 0x00 = msubad.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x70, 0x00 = msubadm.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x74, 0x00 = msubadm.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x78, 0x00 = msubadm.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x7c, 0x00 = msubadm.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0xf0, 0x00 = msubadms.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xf4, 0x00 = msubadms.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xf8, 0x00 = msubadms.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xfc, 0x00 = msubadms.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x30, 0x00 = msubadr.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0x34, 0x00 = msubadr.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0x38, 0x00 = msubadr.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0x3c, 0x00 = msubadr.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xb0, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0xb4, 0x00 = msubadrs.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0xb8, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0xbc, 0x00 = msubadrs.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xe0, 0x00 = msubads.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xe4, 0x00 = msubads.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xe8, 0x00 = msubads.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xec, 0x00 = msubads.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0x70, 0x00 = msubm.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x74, 0x00 = msubm.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x78, 0x00 = msubm.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x7c, 0x00 = msubm.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0xf0, 0x00 = msubms.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xf4, 0x00 = msubms.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xf8, 0x00 = msubms.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xfc, 0x00 = msubms.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x78, 0x00 = msubr.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x30, 0x00 = msubr.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0x34, 0x00 = msubr.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0x38, 0x00 = msubr.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0x3c, 0x00 = msubr.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x18, 0x00 = msubr.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x1c, 0x00 = msubr.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xf8, 0x00 = msubrs.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb0, 0x00 = msubrs.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb4, 0x00 = msubrs.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0xb8, 0x00 = msubrs.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0xbc, 0x00 = msubrs.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x98, 0x00 = msubrs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x9c, 0x00 = msubrs.q %d0, %d0, %d0l, %d0l, 0
+0x23, 0x00, 0x8a, 0x00 = msubs %d0, %d0, %d0, %d0
+0x33, 0x00, 0xa0, 0x00 = msubs %d0, %d0, %d0, 0
+0x33, 0x00, 0xe0, 0x00 = msubs %e0, %e0, %d0, 0
+0x23, 0x00, 0xea, 0x00 = msubs %e0, %e0, %d0, %d0
+0xa3, 0x00, 0xe0, 0x00 = msubs.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xe4, 0x00 = msubs.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xe8, 0x00 = msubs.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xec, 0x00 = msubs.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x90, 0x00 = msubs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x80, 0x00 = msubs.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x84, 0x00 = msubs.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x88, 0x00 = msubs.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x94, 0x00 = msubs.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xe0, 0x00 = msubs.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0xe4, 0x00 = msubs.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0xec, 0x00 = msubs.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0xf0, 0x00 = msubs.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0xf4, 0x00 = msubs.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x80, 0x00 = msubs.u %d0, %d0, %d0, 0
+0x23, 0x00, 0x88, 0x00 = msubs.u %d0, %d0, %d0, %d0
+0x33, 0x00, 0xc0, 0x00 = msubs.u %e0, %e0, %d0, 0
+0x23, 0x00, 0xe8, 0x00 = msubs.u %e0, %e0, %d0, %d0
+0xcd, 0x00, 0x00, 0x00 = mtcr 0, %d0
+0xe2, 0x00 = mul %d0, %d0
+0x53, 0x00, 0x20, 0x00 = mul %d0, %d0, 0
+0x73, 0x00, 0x0a, 0x00 = mul %d0, %d0, %d0
+0x53, 0x00, 0x60, 0x00 = mul %e0, %d0, 0
+0x73, 0x00, 0x6a, 0x00 = mul %e0, %d0, %d0
+0x4b, 0x00, 0x41, 0x00 = mul.f %d0, %d0, %d0
+0xb3, 0x00, 0x60, 0x00 = mul.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x64, 0x00 = mul.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x68, 0x00 = mul.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x6c, 0x00 = mul.h %e0, %d0, %d0uu, 0
+0x93, 0x00, 0x00, 0x00 = mul.q %d0, %d0, %d0u, 0
+0x93, 0x00, 0x04, 0x00 = mul.q %d0, %d0, %d0l, 0
+0x93, 0x00, 0x08, 0x00 = mul.q %d0, %d0, %d0, 0
+0x93, 0x00, 0x10, 0x00 = mul.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x14, 0x00 = mul.q %d0, %d0l, %d0l, 0
+0x93, 0x00, 0x60, 0x00 = mul.q %e0, %d0, %d0u, 0
+0x93, 0x00, 0x64, 0x00 = mul.q %e0, %d0, %d0l, 0
+0x93, 0x00, 0x6c, 0x00 = mul.q %e0, %d0, %d0, 0
+0x53, 0x00, 0x40, 0x00 = mul.u %e0, %d0, 0
+0x73, 0x00, 0x68, 0x00 = mul.u %e0, %d0, %d0
+0xb3, 0x00, 0x70, 0x00 = mulm.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x74, 0x00 = mulm.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x78, 0x00 = mulm.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x7c, 0x00 = mulm.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0xf0, 0x00 = mulms.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0xf4, 0x00 = mulms.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0xf8, 0x00 = mulms.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0xfc, 0x00 = mulms.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0x30, 0x00 = mulr.h %d0, %d0, %d0ul, 0
+0xb3, 0x00, 0x34, 0x00 = mulr.h %d0, %d0, %d0lu, 0
+0xb3, 0x00, 0x38, 0x00 = mulr.h %d0, %d0, %d0ll, 0
+0xb3, 0x00, 0x3c, 0x00 = mulr.h %d0, %d0, %d0uu, 0
+0x93, 0x00, 0x18, 0x00 = mulr.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x1c, 0x00 = mulr.q %d0, %d0l, %d0l, 0
+0x53, 0x00, 0xa0, 0x00 = muls %d0, %d0, 0
+0x73, 0x00, 0x8a, 0x00 = muls %d0, %d0, %d0
+0x53, 0x00, 0x80, 0x00 = muls.u %d0, %d0, 0
+0x73, 0x00, 0x88, 0x00 = muls.u %d0, %d0, %d0
+0x0f, 0x00, 0x90, 0x00 = nand %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x01 = nand %d0, %d0, 0
+0x07, 0x00, 0x00, 0x00 = nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x10, 0x01 = ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x02 = ne %d0, %d0, 0
+0x01, 0x00, 0x10, 0x04 = ne.a %d0, %a0, %a0
+0x01, 0x00, 0x90, 0x04 = nez.a %d0, %a0
+0x00, 0x00 = nop
+0x0d, 0x00, 0x00, 0x00 = nop
+0x46, 0x00 = nor %d0
+0x0f, 0x00, 0xb0, 0x00 = nor %d0, %d0, %d0
+0x8f, 0x00, 0x60, 0x01 = nor %d0, %d0, 0
+0x87, 0x00, 0x40, 0x00 = nor.t %d0, %d0, 0, %d0, 0
+0xa6, 0x00 = or %d0, %d0
+0x96, 0x00 = or %d15, 0
+0x0f, 0x00, 0xa0, 0x00 = or %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x01 = or %d0, %d0, 0
+0xc7, 0x00, 0x00, 0x00 = or.and.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x60, 0x00 = or.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x02 = or.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x04 = or.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x02 = or.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x05 = or.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x02 = or.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x05 = or.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x02 = or.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x05 = or.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x02 = or.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x05 = or.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x02 = or.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x05 = or.ne %d0, %d0, 0
+0xc7, 0x00, 0x40, 0x00 = or.nor.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x20, 0x00 = or.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x20, 0x00 = or.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xf0, 0x00 = orn %d0, %d0, %d0
+0x8f, 0x00, 0xe0, 0x01 = orn %d0, %d0, 0
+0x07, 0x00, 0x20, 0x00 = orn.t %d0, %d0, 0, %d0, 0
+0x6b, 0x00, 0x00, 0x00 = pack %d0, %e0, %d0
+0x4b, 0x00, 0x20, 0x00 = parity %d0, %d0
+0x4b, 0x00, 0x51, 0x01 = q31tof %d0, %d0, %d0
+0x4b, 0x00, 0x91, 0x01 = qseed.f %d0, %d0
+0x00, 0x90 = ret
+0x0d, 0x00, 0x80, 0x01 = ret
+0x00, 0x80 = rfe
+0x0d, 0x00, 0xc0, 0x01 = rfe
+0x0d, 0x00, 0x40, 0x01 = rfm
+0x0d, 0x00, 0x40, 0x02 = rslcx
+0x2f, 0x00, 0x00, 0x00 = rstv
+0x32, 0x50 = rsub %d0
+0x8b, 0x00, 0x00, 0x01 = rsub %d0, %d0, 0
+0x8b, 0x00, 0x40, 0x01 = rsubs %d0, %d0, 0
+0x8b, 0x00, 0x60, 0x01 = rsubs.u %d0, %d0, 0
+0x32, 0x00 = sat.b %d0
+0x0b, 0x00, 0xe0, 0x05 = sat.b %d0, %d0
+0x32, 0x10 = sat.bu %d0
+0x0b, 0x00, 0xf0, 0x05 = sat.bu %d0, %d0
+0x32, 0x20 = sat.h %d0
+0x0b, 0x00, 0xe0, 0x07 = sat.h %d0, %d0
+0x32, 0x30 = sat.hu %d0
+0x0b, 0x00, 0xf0, 0x07 = sat.hu %d0, %d0
+0x2b, 0x00, 0x40, 0x00 = sel %d0, %d0, %d0, %d0
+0xab, 0x00, 0x80, 0x00 = sel %d0, %d0, %d0, 0
+0x2b, 0x00, 0x50, 0x00 = seln %d0, %d0, %d0, %d0
+0xab, 0x00, 0xa0, 0x00 = seln %d0, %d0, %d0, 0
+0x06, 0x00 = sh %d0, 0
+0x0f, 0x00, 0x00, 0x00 = sh %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x00 = sh %d0, %d0, 0
+0x27, 0x00, 0x00, 0x00 = sh.and.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x60, 0x00 = sh.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x03 = sh.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x06 = sh.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x03 = sh.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x07 = sh.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x03 = sh.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x07 = sh.ge.u %d0, %d0, 0
+0x0f, 0x00, 0x00, 0x04 = sh.h %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x08 = sh.h %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x03 = sh.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x07 = sh.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x03 = sh.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x07 = sh.lt.u %d0, %d0, 0
+0xa7, 0x00, 0x00, 0x00 = sh.nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x80, 0x03 = sh.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x07 = sh.ne %d0, %d0, 0
+0x27, 0x00, 0x40, 0x00 = sh.nor.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x20, 0x00 = sh.or.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x20, 0x00 = sh.orn.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x40, 0x00 = sh.xnor.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x60, 0x00 = sh.xor.t %d0, %d0, 0, %d0, 0
+0x86, 0x00 = sha %d0, 0
+0x0f, 0x00, 0x10, 0x00 = sha %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x00 = sha %d0, %d0, 0
+0x0f, 0x00, 0x10, 0x04 = sha.h %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x08 = sha.h %d0, %d0, 0
+0x0f, 0x00, 0x20, 0x00 = shas %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x00 = shas %d0, %d0, 0
+0xf8, 0x00 = st.a [%sp]0, %a15
+0xec, 0x00 = st.a [%a0]0, %a15
+0xe8, 0x00 = st.a [%a15]0, %a0
+0xe4, 0x00 = st.a [%a0+], %a0
+0xf4, 0x00 = st.a [%a0], %a0
+0x89, 0x00, 0x80, 0x01 = st.a [%a0+]0, %a0
+0xa9, 0x00, 0x80, 0x01 = st.a [%p0+r], %a0
+0x89, 0x00, 0x80, 0x05 = st.a [+%a0]0, %a0
+0xa9, 0x00, 0x80, 0x05 = st.a [%p0+c]0, %a0
+0xa5, 0x00, 0x00, 0x08 = st.a 0, %a0
+0x89, 0x00, 0x80, 0x09 = st.a [%a0]0, %a0
+0x34, 0x00 = st.b [%a0], %d0
+0x28, 0x00 = st.b [%a15]0, %d0
+0x2c, 0x00 = st.b [%a0]0, %d15
+0x24, 0x00 = st.b [%a0+], %d0
+0x25, 0x00, 0x00, 0x00 = st.b 0, %d0
+0x89, 0x00, 0x00, 0x00 = st.b [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x00 = st.b [%p0+r], %d0
+0x89, 0x00, 0x00, 0x04 = st.b [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x04 = st.b [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x08 = st.b [%a0]0, %d0
+0x89, 0x00, 0x40, 0x01 = st.d [%a0+]0, %e0
+0xa9, 0x00, 0x40, 0x01 = st.d [%p0+r], %e0
+0xa5, 0x00, 0x00, 0x04 = st.d 0, %e0
+0x89, 0x00, 0x40, 0x05 = st.d [+%a0]0, %e0
+0xa9, 0x00, 0x40, 0x05 = st.d [%p0+c]0, %e0
+0x89, 0x00, 0x40, 0x09 = st.d [%a0]0, %e0
+0x89, 0x00, 0xc0, 0x01 = st.da [%a0+]0, %p0
+0xa9, 0x00, 0xc0, 0x01 = st.da [%p0+r], %p0
+0x89, 0x00, 0xc0, 0x05 = st.da [+%a0]0, %p0
+0xa9, 0x00, 0xc0, 0x05 = st.da [%p0+c]0, %p0
+0x89, 0x00, 0xc0, 0x09 = st.da [%a0]0, %p0
+0xa5, 0x00, 0x00, 0x0c = st.da 0, %p0
+0xa4, 0x00 = st.h [%a0+], %d0
+0xa8, 0x00 = st.h [%a15]0, %d0
+0xac, 0x00 = st.h [%a0]0, %d15
+0xb4, 0x00 = st.h [%a0], %d0
+0x89, 0x00, 0x80, 0x00 = st.h [%a0+]0, %d0
+0xa9, 0x00, 0x80, 0x00 = st.h [%p0+r], %d0
+0x89, 0x00, 0x80, 0x04 = st.h [+%a0]0, %d0
+0xa9, 0x00, 0x80, 0x04 = st.h [%p0+c]0, %d0
+0x25, 0x00, 0x00, 0x08 = st.h 0, %d0
+0x89, 0x00, 0x80, 0x08 = st.h [%a0]0, %d0
+0x65, 0x00, 0x00, 0x00 = st.q 0, %d0
+0x89, 0x00, 0x00, 0x02 = st.q [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x02 = st.q [%p0+r], %d0
+0x89, 0x00, 0x00, 0x06 = st.q [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x06 = st.q [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x0a = st.q [%a0]0, %d0
+0xd5, 0x00, 0x00, 0x00 = st.t 0, 0, 0
+0x78, 0x00 = st.w [%sp]0, %d15
+0x74, 0x00 = st.w [%a0], %d0
+0x64, 0x00 = st.w [%a0+], %d0
+0x68, 0x00 = st.w [%a15]0, %d0
+0x6c, 0x00 = st.w [%a0]0, %d15
+0x59, 0x00, 0x00, 0x00 = st.w [%a0]0, %d0
+0xa5, 0x00, 0x00, 0x00 = st.w 0, %d0
+0x89, 0x00, 0x00, 0x01 = st.w [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x01 = st.w [%p0+r], %d0
+0x89, 0x00, 0x00, 0x05 = st.w [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x05 = st.w [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x09 = st.w [%a0]0, %d0
+0x15, 0x00, 0x00, 0x00 = stlcx 0
+0x49, 0x00, 0x80, 0x09 = stlcx [%a0]0
+0x15, 0x00, 0x00, 0x04 = stucx 0
+0x49, 0x00, 0xc0, 0x09 = stucx [%a0]0
+0x52, 0x00 = sub %d0, %d15, %d0
+0x5a, 0x00 = sub %d15, %d0, %d0
+0xa2, 0x00 = sub %d0, %d0
+0x0b, 0x00, 0x80, 0x00 = sub %d0, %d0, %d0
+0x20, 0x00 = sub.a %sp, 0
+0x01, 0x00, 0x20, 0x00 = sub.a %a0, %a0, %a0
+0x0b, 0x00, 0x80, 0x04 = sub.b %d0, %d0, %d0
+0x6b, 0x00, 0x31, 0x00 = sub.f %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x06 = sub.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x00 = subc %d0, %d0, %d0
+0x62, 0x00 = subs %d0, %d0
+0x0b, 0x00, 0xa0, 0x00 = subs %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x06 = subs.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x06 = subs.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x00 = subs.u %d0, %d0, %d0
+0x0b, 0x00, 0xc0, 0x00 = subx %d0, %d0, %d0
+0x0d, 0x00, 0x00, 0x02 = svlcx
+0x49, 0x00, 0x00, 0x00 = swap.w [%a0+]0, %d0
+0x69, 0x00, 0x00, 0x00 = swap.w [%p0+r], %d0
+0xe5, 0x00, 0x00, 0x00 = swap.w 0, %d0
+0x49, 0x00, 0x00, 0x04 = swap.w [+%a0]0, %d0
+0x69, 0x00, 0x00, 0x04 = swap.w [%p0+c]0, %d0
+0x49, 0x00, 0x00, 0x08 = swap.w [%a0]0, %d0
+0xad, 0x00, 0x80, 0x00 = syscall 0
+0x75, 0x00, 0x00, 0x00 = tlbdemap %d0
+0x75, 0x00, 0x40, 0x00 = tlbflush.a
+0x75, 0x00, 0x50, 0x00 = tlbflush.b
+0x75, 0x00, 0x00, 0x04 = tlbmap %e0
+0x75, 0x00, 0x80, 0x00 = tlbprobe.a %d0
+0x75, 0x00, 0x90, 0x00 = tlbprobe.i %d0
+0x0d, 0x00, 0x40, 0x05 = trapsv
+0x0d, 0x00, 0x00, 0x05 = trapv
+0x4b, 0x00, 0x80, 0x00 = unpack %e0, %d0
+0x4b, 0x00, 0xc1, 0x00 = updfl %d0
+0x4b, 0x00, 0x61, 0x01 = utof %d0, %d0
+0x0f, 0x00, 0xd0, 0x00 = xnor %d0, %d0, %d0
+0x8f, 0x00, 0xa0, 0x01 = xnor %d0, %d0, 0
+0x07, 0x00, 0x40, 0x00 = xnor.t %d0, %d0, 0, %d0, 0
+0xc6, 0x00 = xor %d0, %d0
+0x0f, 0x00, 0xc0, 0x00 = xor %d0, %d0, %d0
+0x8f, 0x00, 0x80, 0x01 = xor %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x02 = xor.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x05 = xor.eq %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x03 = xor.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x06 = xor.ge %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x03 = xor.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x06 = xor.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x03 = xor.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x06 = xor.lt %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x03 = xor.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x06 = xor.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x00, 0x03 = xor.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x06 = xor.ne %d0, %d0, 0
+0x07, 0x00, 0x60, 0x00 = xor.t %d0, %d0, 0, %d0, 0
diff --git a/suite/MC/TriCore/tc160.s.cs b/suite/MC/TriCore/tc160.s.cs
new file mode 100644
index 0000000000..102b6c08b2
--- /dev/null
+++ b/suite/MC/TriCore/tc160.s.cs
@@ -0,0 +1,823 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_160, None
+0x0b, 0x00, 0xc0, 0x01 = abs %d0, %d0
+0x0b, 0x00, 0xc0, 0x05 = abs.b %d0, %d0
+0x0b, 0x00, 0xc0, 0x07 = abs.h %d0, %d0
+0x0b, 0x00, 0xe0, 0x00 = absdif %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x01 = absdif %d0, %d0, 0
+0x0b, 0x00, 0xe0, 0x04 = absdif.b %d0, %d0, %d0
+0x0b, 0x00, 0xe0, 0x06 = absdif.h %d0, %d0, %d0
+0x0b, 0x00, 0xf0, 0x00 = absdifs %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x01 = absdifs %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x06 = absdifs.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x01 = abss %d0, %d0
+0x0b, 0x00, 0xd0, 0x07 = abss.h %d0, %d0
+0x12, 0x00 = add %d0, %d15, %d0
+0x92, 0x00 = add %d0, %d15, 0
+0x1a, 0x00 = add %d15, %d0, %d0
+0x42, 0x00 = add %d0, %d0
+0x9a, 0x00 = add %d15, %d0, 0
+0xc2, 0x00 = add %d0, 0
+0x0b, 0x00, 0x00, 0x00 = add %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x00 = add %d0, %d0, 0
+0x30, 0x00 = add.a %a0, %a0
+0xb0, 0x00 = add.a %a0, 0
+0x01, 0x00, 0x10, 0x00 = add.a %a0, %a0, %a0
+0x0b, 0x00, 0x00, 0x04 = add.b %d0, %d0, %d0
+0x6b, 0x00, 0x21, 0x00 = add.f %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x06 = add.h %d0, %d0, %d0
+0x0b, 0x00, 0x50, 0x00 = addc %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x00 = addc %d0, %d0, 0
+0x1b, 0x00, 0x00, 0x00 = addi %d0, %d0, 0
+0x9b, 0x00, 0x00, 0x00 = addih %d0, %d0, 0
+0x11, 0x00, 0x00, 0x00 = addih.a %a0, %a0, 0
+0x22, 0x00 = adds %d0, %d0
+0x0b, 0x00, 0x20, 0x00 = adds %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x00 = adds %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x06 = adds.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x06 = adds.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x00 = adds.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x00 = adds.u %d0, %d0, 0
+0x10, 0x00 = addsc.a %a0, %a0, %d15, 0
+0x01, 0x00, 0x00, 0x06 = addsc.a %a0, %a0, %d0, 0
+0x01, 0x00, 0x20, 0x06 = addsc.at %a0, %a0, %d0
+0x0b, 0x00, 0x40, 0x00 = addx %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x00 = addx %d0, %d0, 0
+0x26, 0x00 = and %d0, %d0
+0x16, 0x00 = and %d15, 0
+0x0f, 0x00, 0x80, 0x00 = and %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x01 = and %d0, %d0, 0
+0x47, 0x00, 0x00, 0x00 = and.and.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x60, 0x00 = and.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x00, 0x02 = and.eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x04 = and.eq %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x02 = and.ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x04 = and.ge %d0, %d0, 0
+0x0b, 0x00, 0x50, 0x02 = and.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x04 = and.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x02 = and.lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x04 = and.lt %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x02 = and.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x04 = and.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x02 = and.ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x04 = and.ne %d0, %d0, 0
+0x47, 0x00, 0x40, 0x00 = and.nor.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x20, 0x00 = and.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x00, 0x00 = and.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xe0, 0x00 = andn %d0, %d0, %d0
+0x8f, 0x00, 0xc0, 0x01 = andn %d0, %d0, 0
+0x87, 0x00, 0x60, 0x00 = andn.t %d0, %d0, 0, %d0, 0
+0xe0, 0x00 = bisr 0
+0xad, 0x00, 0x00, 0x00 = bisr 0
+0x4b, 0x00, 0x10, 0x00 = bmerge %d0, %d0, %d0
+0x4b, 0x00, 0x90, 0x00 = bsplit %e0, %d0
+0x89, 0x00, 0x80, 0x03 = cachea.i [%a0+]0
+0xa9, 0x00, 0x80, 0x03 = cachea.i [%p0+r]
+0x89, 0x00, 0x80, 0x07 = cachea.i [+%a0]0
+0xa9, 0x00, 0x80, 0x07 = cachea.i [%p0+c]0
+0x89, 0x00, 0x80, 0x0b = cachea.i [%a0]0
+0x89, 0x00, 0x00, 0x03 = cachea.w [%a0+]0
+0xa9, 0x00, 0x00, 0x03 = cachea.w [%p0+r]
+0x89, 0x00, 0x00, 0x07 = cachea.w [+%a0]0
+0xa9, 0x00, 0x00, 0x07 = cachea.w [%p0+c]0
+0x89, 0x00, 0x00, 0x0b = cachea.w [%a0]0
+0x89, 0x00, 0x40, 0x03 = cachea.wi [%a0+]0
+0xa9, 0x00, 0x40, 0x03 = cachea.wi [%p0+r]
+0x89, 0x00, 0x40, 0x07 = cachea.wi [+%a0]0
+0xa9, 0x00, 0x40, 0x07 = cachea.wi [%p0+c]0
+0x89, 0x00, 0x40, 0x0b = cachea.wi [%a0]0
+0x89, 0x00, 0x80, 0x02 = cachei.i [%a0+]0
+0x89, 0x00, 0x80, 0x06 = cachei.i [+%a0]0
+0x89, 0x00, 0x80, 0x0a = cachei.i [%a0]0
+0x89, 0x00, 0xc0, 0x02 = cachei.w [%a0+]0
+0x89, 0x00, 0xc0, 0x06 = cachei.w [+%a0]0
+0x89, 0x00, 0xc0, 0x0a = cachei.w [%a0]0
+0x89, 0x00, 0xc0, 0x03 = cachei.wi [%a0+]0
+0x89, 0x00, 0xc0, 0x07 = cachei.wi [+%a0]0
+0x89, 0x00, 0xc0, 0x0b = cachei.wi [%a0]0
+0x8a, 0x00 = cadd %d0, %d15, 0
+0x2b, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, %d0
+0xab, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, 0
+0xca, 0x00 = caddn %d0, %d15, 0
+0x2b, 0x00, 0x10, 0x00 = caddn %d0, %d0, %d0, %d0
+0xab, 0x00, 0x20, 0x00 = caddn %d0, %d0, %d0, 0
+0x5c, 0x00 = call 0
+0x6d, 0x00, 0x00, 0x00 = call 0
+0xed, 0x00, 0x00, 0x00 = calla 0
+0x2d, 0x00, 0x00, 0x00 = calli %a0
+0x0f, 0x00, 0xc0, 0x01 = clo %d0, %d0
+0x0f, 0x00, 0xd0, 0x07 = clo.h %d0, %d0
+0x0f, 0x00, 0xd0, 0x01 = cls %d0, %d0
+0x0f, 0x00, 0xe0, 0x07 = cls.h %d0, %d0
+0x0f, 0x00, 0xb0, 0x01 = clz %d0, %d0
+0x0f, 0x00, 0xc0, 0x07 = clz.h %d0, %d0
+0x2a, 0x00 = cmov %d0, %d15, %d0
+0xaa, 0x00 = cmov %d0, %d15, 0
+0x6a, 0x00 = cmovn %d0, %d15, %d0
+0xea, 0x00 = cmovn %d0, %d15, 0
+0x4b, 0x00, 0x00, 0x00 = cmp.f %d0, %d0, %d0
+0x2b, 0x00, 0x20, 0x00 = csub %d0, %d0, %d0, %d0
+0x2b, 0x00, 0x30, 0x00 = csubn %d0, %d0, %d0, %d0
+0x00, 0xa0 = debug
+0x0d, 0x00, 0x00, 0x01 = debug
+0x77, 0x00, 0x00, 0x00 = dextr %d0, %d0, %d0, 0
+0x17, 0x00, 0x80, 0x00 = dextr %d0, %d0, %d0, %d0
+0x0d, 0x00, 0x40, 0x03 = disable
+0x0d, 0x00, 0xc0, 0x03 = disable %d0
+0x4b, 0x00, 0x01, 0x02 = div %e0, %d0, %d0
+0x4b, 0x00, 0x11, 0x02 = div.u %e0, %d0, %d0
+0x4b, 0x00, 0x51, 0x00 = div.f %d0, %d0, %d0
+0x0d, 0x00, 0x80, 0x04 = dsync
+0x6b, 0x00, 0xd0, 0x00 = dvadj %e0, %e0, %d0
+0x4b, 0x00, 0xa0, 0x01 = dvinit %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x05 = dvinit.b %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x04 = dvinit.bu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x03 = dvinit.h %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x02 = dvinit.hu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x00 = dvinit.u %e0, %d0, %d0
+0x6b, 0x00, 0xf0, 0x00 = dvstep %e0, %e0, %d0
+0x6b, 0x00, 0xe0, 0x00 = dvstep.u %e0, %e0, %d0
+0x0d, 0x00, 0x00, 0x03 = enable
+0x3a, 0x00 = eq %d15, %d0, %d0
+0xba, 0x00 = eq %d15, %d0, 0
+0x0b, 0x00, 0x00, 0x01 = eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x02 = eq %d0, %d0, 0
+0x01, 0x00, 0x00, 0x04 = eq.a %d0, %a0, %a0
+0x0b, 0x00, 0x00, 0x05 = eq.b %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x07 = eq.h %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x09 = eq.w %d0, %d0, %d0
+0x0b, 0x00, 0x60, 0x05 = eqany.b %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0a = eqany.b %d0, %d0, 0
+0x0b, 0x00, 0x60, 0x07 = eqany.h %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0e = eqany.h %d0, %d0, 0
+0x01, 0x00, 0x80, 0x04 = eqz.a %d0, %a0
+0x17, 0x00, 0x40, 0x00 = extr %d0, %d0, %e0
+0x37, 0x00, 0x40, 0x00 = extr %d0, %d0, 0, 0
+0x57, 0x00, 0x40, 0x00 = extr %d0, %d0, %d0, 0
+0x17, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %e0
+0x37, 0x00, 0x60, 0x00 = extr.u %d0, %d0, 0, 0
+0x57, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %d0, 0
+0x61, 0x00, 0x00, 0x00 = fcall 0
+0xe1, 0x00, 0x00, 0x00 = fcalla 0
+0x2d, 0x00, 0x10, 0x00 = fcalli %a0
+0x00, 0x70 = fret
+0x0d, 0x00, 0xc0, 0x00 = fret
+0x4b, 0x00, 0x01, 0x01 = ftoi %d0, %d0
+0x4b, 0x00, 0x11, 0x01 = ftoq31 %d0, %d0, %d0
+0x4b, 0x00, 0x21, 0x01 = ftou %d0, %d0
+0x4b, 0x00, 0x31, 0x01 = ftoiz %d0, %d0
+0x4b, 0x00, 0x81, 0x01 = ftoq31z %d0, %d0, %d0
+0x4b, 0x00, 0x71, 0x01 = ftouz %d0, %d0
+0x0b, 0x00, 0x40, 0x01 = ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x02 = ge %d0, %d0, 0
+0x01, 0x00, 0x30, 0x04 = ge.a %d0, %a0, %a0
+0x0b, 0x00, 0x50, 0x01 = ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x02 = ge.u %d0, %d0, 0
+0x37, 0x00, 0x20, 0x00 = imask %e0, %d0, 0, 0
+0x57, 0x00, 0x20, 0x00 = imask %e0, %d0, %d0, 0
+0xb7, 0x00, 0x20, 0x00 = imask %e0, 0, 0, 0
+0xd7, 0x00, 0x20, 0x00 = imask %e0, 0, %d0, 0
+0x67, 0x00, 0x00, 0x00 = ins.t %d0, %d0, 0, %d0, 0
+0x17, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %e0
+0x37, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, 0, 0
+0x57, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %d0, 0
+0x97, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %e0
+0xb7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, 0, 0
+0xd7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %d0, 0
+0x67, 0x00, 0x20, 0x00 = insn.t %d0, %d0, 0, %d0, 0
+0x0d, 0x00, 0xc0, 0x04 = isync
+0x4b, 0x00, 0x41, 0x01 = itof %d0, %d0
+0x6b, 0x00, 0xa0, 0x00 = ixmax %e0, %e0, %d0
+0x6b, 0x00, 0xb0, 0x00 = ixmax.u %e0, %e0, %d0
+0x6b, 0x00, 0x80, 0x00 = ixmin %e0, %e0, %d0
+0x6b, 0x00, 0x90, 0x00 = ixmin.u %e0, %e0, %d0
+0x3c, 0x00 = j 0
+0x1d, 0x00, 0x00, 0x00 = j 0
+0x9d, 0x00, 0x00, 0x00 = ja 0
+0xbe, 0x00 = jeq %d15, %d0, 0x20
+0x9e, 0x00 = jeq %d15, 0, 0x20
+0x3e, 0x00 = jeq %d15, %d0, 0
+0x1e, 0x00 = jeq %d15, 0, 0
+0x5f, 0x00, 0x00, 0x00 = jeq %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x00 = jeq %d0, 0, 0
+0x7d, 0x00, 0x00, 0x00 = jeq.a %a0, %a0, 0
+0x7f, 0x00, 0x00, 0x00 = jge %d0, %d0, 0
+0xff, 0x00, 0x00, 0x00 = jge %d0, 0, 0
+0x7f, 0x00, 0x00, 0x80 = jge.u %d0, %d0, 0
+0xff, 0x00, 0x00, 0x80 = jge.u %d0, 0, 0
+0xce, 0x00 = jgez %d0, 0
+0x4e, 0x00 = jgtz %d0, 0
+0xdc, 0x00 = ji %a0
+0x2d, 0x00, 0x30, 0x00 = ji %a0
+0x5d, 0x00, 0x00, 0x00 = jl 0
+0xdd, 0x00, 0x00, 0x00 = jla 0
+0x8e, 0x00 = jlez %d0, 0
+0x2d, 0x00, 0x20, 0x00 = jli %a0
+0x3f, 0x00, 0x00, 0x00 = jlt %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x00 = jlt %d0, 0, 0
+0x3f, 0x00, 0x00, 0x80 = jlt.u %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x80 = jlt.u %d0, 0, 0
+0x0e, 0x00 = jltz %d0, 0
+0xfe, 0x00 = jne %d15, %d0, 0x20
+0xde, 0x00 = jne %d15, 0, 0x20
+0x7e, 0x00 = jne %d15, %d0, 0
+0x5e, 0x00 = jne %d15, 0, 0
+0x5f, 0x00, 0x00, 0x80 = jne %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x80 = jne %d0, 0, 0
+0x7d, 0x00, 0x00, 0x80 = jne.a %a0, %a0, 0
+0x1f, 0x00, 0x00, 0x80 = jned %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x80 = jned %d0, 0, 0
+0x1f, 0x00, 0x00, 0x00 = jnei %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x00 = jnei %d0, 0, 0
+0xee, 0x00 = jnz %d15, 0
+0xf6, 0x00 = jnz %d0, 0
+0x7c, 0x00 = jnz.a %a0, 0
+0xbd, 0x00, 0x00, 0x80 = jnz.a %a0, 0
+0xae, 0x00 = jnz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x80 = jnz.t %d0, 0, 0
+0x6e, 0x00 = jz %d15, 0
+0x76, 0x00 = jz %d0, 0
+0xbc, 0x00 = jz.a %a0, 0
+0xbd, 0x00, 0x00, 0x00 = jz.a %a0, 0
+0x2e, 0x00 = jz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x00 = jz.t %d0, 0, 0
+0xd8, 0x00 = ld.a %a15, [%sp]0
+0xc8, 0x00 = ld.a %a0, [%a15]0
+0xcc, 0x00 = ld.a %a15, [%a0]0
+0xc4, 0x00 = ld.a %a0, [%a0+]
+0xd4, 0x00 = ld.a %a0, [%a0]
+0x99, 0x00, 0x00, 0x00 = ld.a %a0, [%a0]0
+0x09, 0x00, 0x80, 0x01 = ld.a %a0, [%a0+]0
+0x29, 0x00, 0x80, 0x01 = ld.a %a0, [%p0+r]
+0x09, 0x00, 0x80, 0x05 = ld.a %a0, [+%a0]0
+0x29, 0x00, 0x80, 0x05 = ld.a %a0, [%p0+c]0
+0x85, 0x00, 0x00, 0x08 = ld.a %a0, 0
+0x09, 0x00, 0x80, 0x09 = ld.a %a0, [%a0]0
+0x79, 0x00, 0x00, 0x00 = ld.b %d0, [%a0]0
+0x05, 0x00, 0x00, 0x00 = ld.b %d0, 0
+0x09, 0x00, 0x00, 0x00 = ld.b %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x00 = ld.b %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x04 = ld.b %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x04 = ld.b %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x08 = ld.b %d0, [%a0]0
+0x14, 0x00 = ld.bu %d0, [%a0]
+0x0c, 0x00 = ld.bu %d15, [%a0]0
+0x08, 0x00 = ld.bu %d0, [%a15]0
+0x04, 0x00 = ld.bu %d0, [%a0+]
+0x39, 0x00, 0x00, 0x00 = ld.bu %d0, [%a0]0
+0x09, 0x00, 0x40, 0x00 = ld.bu %d0, [%a0+]0
+0x29, 0x00, 0x40, 0x00 = ld.bu %d0, [%p0+r]
+0x05, 0x00, 0x00, 0x04 = ld.bu %d0, 0
+0x09, 0x00, 0x40, 0x04 = ld.bu %d0, [+%a0]0
+0x29, 0x00, 0x40, 0x04 = ld.bu %d0, [%p0+c]0
+0x09, 0x00, 0x40, 0x08 = ld.bu %d0, [%a0]0
+0x09, 0x00, 0x40, 0x01 = ld.d %e0, [%a0+]0
+0x29, 0x00, 0x40, 0x01 = ld.d %e0, [%p0+r]
+0x85, 0x00, 0x00, 0x04 = ld.d %e0, 0
+0x09, 0x00, 0x40, 0x05 = ld.d %e0, [+%a0]0
+0x29, 0x00, 0x40, 0x05 = ld.d %e0, [%p0+c]0
+0x09, 0x00, 0x40, 0x09 = ld.d %e0, [%a0]0
+0x09, 0x00, 0xc0, 0x01 = ld.da %p0, [%a0+]0
+0x29, 0x00, 0xc0, 0x01 = ld.da %p0, [%p0+r]
+0x09, 0x00, 0xc0, 0x05 = ld.da %p0, [+%a0]0
+0x29, 0x00, 0xc0, 0x05 = ld.da %p0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x09 = ld.da %p0, [%a0]0
+0x85, 0x00, 0x00, 0x0c = ld.da %p0, 0
+0x84, 0x00 = ld.h %d0, [%a0+]
+0x8c, 0x00 = ld.h %d15, [%a0]0
+0x88, 0x00 = ld.h %d0, [%a15]0
+0x94, 0x00 = ld.h %d0, [%a0]
+0xc9, 0x00, 0x00, 0x00 = ld.h %d0, [%a0]0
+0x09, 0x00, 0x80, 0x00 = ld.h %d0, [%a0+]0
+0x29, 0x00, 0x80, 0x00 = ld.h %d0, [%p0+r]
+0x09, 0x00, 0x80, 0x04 = ld.h %d0, [+%a0]0
+0x29, 0x00, 0x80, 0x04 = ld.h %d0, [%p0+c]0
+0x05, 0x00, 0x00, 0x08 = ld.h %d0, 0
+0x09, 0x00, 0x80, 0x08 = ld.h %d0, [%a0]0
+0xb9, 0x00, 0x00, 0x00 = ld.hu %d0, [%a0]0
+0x09, 0x00, 0xc0, 0x00 = ld.hu %d0, [%a0+]0
+0x29, 0x00, 0xc0, 0x00 = ld.hu %d0, [%p0+r]
+0x09, 0x00, 0xc0, 0x04 = ld.hu %d0, [+%a0]0
+0x29, 0x00, 0xc0, 0x04 = ld.hu %d0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x08 = ld.hu %d0, [%a0]0
+0x05, 0x00, 0x00, 0x0c = ld.hu %d0, 0
+0x45, 0x00, 0x00, 0x00 = ld.q %d0, 0
+0x09, 0x00, 0x00, 0x02 = ld.q %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x02 = ld.q %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x06 = ld.q %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x06 = ld.q %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x0a = ld.q %d0, [%a0]0
+0x58, 0x00 = ld.w %d15, [%sp]0
+0x54, 0x00 = ld.w %d0, [%a0]
+0x44, 0x00 = ld.w %d0, [%a0+]
+0x4c, 0x00 = ld.w %d15, [%a0]0
+0x48, 0x00 = ld.w %d0, [%a15]0
+0x19, 0x00, 0x00, 0x00 = ld.w %d0, [%a0]0
+0x85, 0x00, 0x00, 0x00 = ld.w %d0, 0
+0x09, 0x00, 0x00, 0x01 = ld.w %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x01 = ld.w %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x05 = ld.w %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x05 = ld.w %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x09 = ld.w %d0, [%a0]0
+0x15, 0x00, 0x00, 0x08 = ldlcx 0
+0x49, 0x00, 0x00, 0x09 = ldlcx [%a0]0
+0x49, 0x00, 0x40, 0x00 = ldmst [%a0+]0, %e0
+0x69, 0x00, 0x40, 0x00 = ldmst [%p0+r], %e0
+0xe5, 0x00, 0x00, 0x04 = ldmst 0, %e0
+0x49, 0x00, 0x40, 0x04 = ldmst [+%a0]0, %e0
+0x69, 0x00, 0x40, 0x04 = ldmst [%p0+c]0, %e0
+0x49, 0x00, 0x40, 0x08 = ldmst [%a0]0, %e0
+0x49, 0x00, 0x40, 0x09 = lducx [%a0]0
+0x15, 0x00, 0x00, 0x0c = lducx 0
+0xc5, 0x00, 0x00, 0x00 = lea %a0, 0
+0xd9, 0x00, 0x00, 0x00 = lea %a0, [%a0]0
+0x49, 0x00, 0x00, 0x0a = lea %a0, [%a0]0
+0xfc, 0x00 = loop %a0, -0x20
+0xfd, 0x00, 0x00, 0x00 = loop %a0, 0
+0xfd, 0x00, 0x00, 0x80 = loopu 0
+0x7a, 0x00 = lt %d15, %d0, %d0
+0xfa, 0x00 = lt %d15, %d0, 0
+0x0b, 0x00, 0x20, 0x01 = lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x02 = lt %d0, %d0, 0
+0x01, 0x00, 0x20, 0x04 = lt.a %d0, %a0, %a0
+0x0b, 0x00, 0x20, 0x05 = lt.b %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x05 = lt.bu %d0, %d0, %d0
+0x0b, 0x00, 0x20, 0x07 = lt.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x07 = lt.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x01 = lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x02 = lt.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x09 = lt.w %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x09 = lt.wu %d0, %d0, %d0
+0x03, 0x00, 0x0a, 0x00 = madd %d0, %d0, %d0, %d0
+0x13, 0x00, 0x20, 0x00 = madd %d0, %d0, %d0, 0
+0x13, 0x00, 0x60, 0x00 = madd %e0, %e0, %d0, 0
+0x03, 0x00, 0x6a, 0x00 = madd %e0, %e0, %d0, %d0
+0x6b, 0x00, 0x61, 0x00 = madd.f %d0, %d0, %d0, %d0
+0x83, 0x00, 0x60, 0x00 = madd.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x64, 0x00 = madd.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x68, 0x00 = madd.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x6c, 0x00 = madd.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x10, 0x00 = madd.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x00, 0x00 = madd.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x04, 0x00 = madd.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x08, 0x00 = madd.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x14, 0x00 = madd.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0x60, 0x00 = madd.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0x64, 0x00 = madd.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0x6c, 0x00 = madd.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0x70, 0x00 = madd.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0x74, 0x00 = madd.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x40, 0x00 = madd.u %e0, %e0, %d0, 0
+0x03, 0x00, 0x68, 0x00 = madd.u %e0, %e0, %d0, %d0
+0x83, 0x00, 0x70, 0x00 = maddm.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x74, 0x00 = maddm.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x78, 0x00 = maddm.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x7c, 0x00 = maddm.h %e0, %e0, %d0, %d0uu, 0
+0x83, 0x00, 0xf0, 0x00 = maddms.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xf4, 0x00 = maddms.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xf8, 0x00 = maddms.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xfc, 0x00 = maddms.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x78, 0x00 = maddr.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x30, 0x00 = maddr.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0x34, 0x00 = maddr.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0x38, 0x00 = maddr.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0x3c, 0x00 = maddr.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x18, 0x00 = maddr.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x1c, 0x00 = maddr.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xf8, 0x00 = maddrs.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xb0, 0x00 = maddrs.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0xb4, 0x00 = maddrs.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0xb8, 0x00 = maddrs.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0xbc, 0x00 = maddrs.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x98, 0x00 = maddrs.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x9c, 0x00 = maddrs.q %d0, %d0, %d0l, %d0l, 0
+0x03, 0x00, 0x8a, 0x00 = madds %d0, %d0, %d0, %d0
+0x13, 0x00, 0xa0, 0x00 = madds %d0, %d0, %d0, 0
+0x13, 0x00, 0xe0, 0x00 = madds %e0, %e0, %d0, 0
+0x03, 0x00, 0xea, 0x00 = madds %e0, %e0, %d0, %d0
+0x83, 0x00, 0xe0, 0x00 = madds.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xe4, 0x00 = madds.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xe8, 0x00 = madds.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xec, 0x00 = madds.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x90, 0x00 = madds.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x80, 0x00 = madds.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x84, 0x00 = madds.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x88, 0x00 = madds.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x94, 0x00 = madds.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xe0, 0x00 = madds.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0xe4, 0x00 = madds.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0xec, 0x00 = madds.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0xf0, 0x00 = madds.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0xf4, 0x00 = madds.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x80, 0x00 = madds.u %d0, %d0, %d0, 0
+0x03, 0x00, 0x88, 0x00 = madds.u %d0, %d0, %d0, %d0
+0x13, 0x00, 0xc0, 0x00 = madds.u %e0, %e0, %d0, 0
+0x03, 0x00, 0xe8, 0x00 = madds.u %e0, %e0, %d0, %d0
+0xc3, 0x00, 0x60, 0x00 = maddsu.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x64, 0x00 = maddsu.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x68, 0x00 = maddsu.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x6c, 0x00 = maddsu.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x70, 0x00 = maddsum.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x74, 0x00 = maddsum.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x78, 0x00 = maddsum.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x7c, 0x00 = maddsum.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0xf0, 0x00 = maddsums.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xf4, 0x00 = maddsums.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xf8, 0x00 = maddsums.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xfc, 0x00 = maddsums.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x30, 0x00 = maddsur.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0x34, 0x00 = maddsur.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0x38, 0x00 = maddsur.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0x3c, 0x00 = maddsur.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xb0, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0xb4, 0x00 = maddsurs.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0xb8, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0xbc, 0x00 = maddsurs.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xe0, 0x00 = maddsus.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xe4, 0x00 = maddsus.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xe8, 0x00 = maddsus.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xec, 0x00 = maddsus.h %e0, %e0, %d0, %d0uu, 0
+0x0b, 0x00, 0xa0, 0x01 = max %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x03 = max %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x05 = max.b %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x05 = max.bu %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x07 = max.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x07 = max.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x01 = max.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x03 = max.u %d0, %d0, 0
+0x4d, 0x00, 0x00, 0x00 = mfcr %d0, 0
+0x0b, 0x00, 0x80, 0x01 = min %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x03 = min %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x05 = min.b %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x05 = min.bu %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x07 = min.h %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x07 = min.hu %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x01 = min.u %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x03 = min.u %d0, %d0, 0
+0x02, 0x00 = mov %d0, %d0
+0x82, 0x00 = mov %d0, 0
+0xd2, 0x00 = mov %e0, 0
+0xda, 0x00 = mov %d15, 0
+0x3b, 0x00, 0x00, 0x00 = mov %d0, 0
+0x0b, 0x00, 0xf0, 0x01 = mov %d0, %d0
+0xfb, 0x00, 0x00, 0x00 = mov %e0, 0
+0x0b, 0x00, 0x00, 0x08 = mov %e0, %d0
+0x0b, 0x00, 0x10, 0x08 = mov %e0, %d0, %d0
+0xa0, 0x00 = mov.a %a0, 0
+0x60, 0x00 = mov.a %a0, %d0
+0x01, 0x00, 0x30, 0x06 = mov.a %a0, %d0
+0x40, 0x00 = mov.aa %a0, %a0
+0x01, 0x00, 0x00, 0x00 = mov.aa %a0, %a0
+0x80, 0x00 = mov.d %d0, %a0
+0x01, 0x00, 0xc0, 0x04 = mov.d %d0, %a0
+0xbb, 0x00, 0x00, 0x00 = mov.u %d0, 0
+0x7b, 0x00, 0x00, 0x00 = movh %d0, 0
+0x91, 0x00, 0x00, 0x00 = movh.a %a0, 0
+0x23, 0x00, 0x0a, 0x00 = msub %d0, %d0, %d0, %d0
+0x33, 0x00, 0x20, 0x00 = msub %d0, %d0, %d0, 0
+0x33, 0x00, 0x60, 0x00 = msub %e0, %e0, %d0, 0
+0x23, 0x00, 0x6a, 0x00 = msub %e0, %e0, %d0, %d0
+0x6b, 0x00, 0x71, 0x00 = msub.f %d0, %d0, %d0, %d0
+0xa3, 0x00, 0x60, 0x00 = msub.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x64, 0x00 = msub.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x68, 0x00 = msub.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x6c, 0x00 = msub.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x10, 0x00 = msub.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x00, 0x00 = msub.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x04, 0x00 = msub.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x08, 0x00 = msub.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x14, 0x00 = msub.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0x60, 0x00 = msub.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0x64, 0x00 = msub.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0x6c, 0x00 = msub.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0x70, 0x00 = msub.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0x74, 0x00 = msub.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x40, 0x00 = msub.u %e0, %e0, %d0, 0
+0x23, 0x00, 0x68, 0x00 = msub.u %e0, %e0, %d0, %d0
+0xe3, 0x00, 0x60, 0x00 = msubad.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x64, 0x00 = msubad.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x68, 0x00 = msubad.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x6c, 0x00 = msubad.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x70, 0x00 = msubadm.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x74, 0x00 = msubadm.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x78, 0x00 = msubadm.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x7c, 0x00 = msubadm.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0xf0, 0x00 = msubadms.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xf4, 0x00 = msubadms.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xf8, 0x00 = msubadms.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xfc, 0x00 = msubadms.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x30, 0x00 = msubadr.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0x34, 0x00 = msubadr.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0x38, 0x00 = msubadr.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0x3c, 0x00 = msubadr.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xb0, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0xb4, 0x00 = msubadrs.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0xb8, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0xbc, 0x00 = msubadrs.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xe0, 0x00 = msubads.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xe4, 0x00 = msubads.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xe8, 0x00 = msubads.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xec, 0x00 = msubads.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0x70, 0x00 = msubm.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x74, 0x00 = msubm.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x78, 0x00 = msubm.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x7c, 0x00 = msubm.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0xf0, 0x00 = msubms.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xf4, 0x00 = msubms.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xf8, 0x00 = msubms.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xfc, 0x00 = msubms.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x78, 0x00 = msubr.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x30, 0x00 = msubr.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0x34, 0x00 = msubr.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0x38, 0x00 = msubr.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0x3c, 0x00 = msubr.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x18, 0x00 = msubr.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x1c, 0x00 = msubr.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xf8, 0x00 = msubrs.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb0, 0x00 = msubrs.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb4, 0x00 = msubrs.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0xb8, 0x00 = msubrs.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0xbc, 0x00 = msubrs.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x98, 0x00 = msubrs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x9c, 0x00 = msubrs.q %d0, %d0, %d0l, %d0l, 0
+0x23, 0x00, 0x8a, 0x00 = msubs %d0, %d0, %d0, %d0
+0x33, 0x00, 0xa0, 0x00 = msubs %d0, %d0, %d0, 0
+0x33, 0x00, 0xe0, 0x00 = msubs %e0, %e0, %d0, 0
+0x23, 0x00, 0xea, 0x00 = msubs %e0, %e0, %d0, %d0
+0xa3, 0x00, 0xe0, 0x00 = msubs.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xe4, 0x00 = msubs.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xe8, 0x00 = msubs.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xec, 0x00 = msubs.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x90, 0x00 = msubs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x80, 0x00 = msubs.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x84, 0x00 = msubs.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x88, 0x00 = msubs.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x94, 0x00 = msubs.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xe0, 0x00 = msubs.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0xe4, 0x00 = msubs.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0xec, 0x00 = msubs.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0xf0, 0x00 = msubs.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0xf4, 0x00 = msubs.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x80, 0x00 = msubs.u %d0, %d0, %d0, 0
+0x23, 0x00, 0x88, 0x00 = msubs.u %d0, %d0, %d0, %d0
+0x33, 0x00, 0xc0, 0x00 = msubs.u %e0, %e0, %d0, 0
+0x23, 0x00, 0xe8, 0x00 = msubs.u %e0, %e0, %d0, %d0
+0xcd, 0x00, 0x00, 0x00 = mtcr 0, %d0
+0xe2, 0x00 = mul %d0, %d0
+0x53, 0x00, 0x20, 0x00 = mul %d0, %d0, 0
+0x73, 0x00, 0x0a, 0x00 = mul %d0, %d0, %d0
+0x53, 0x00, 0x60, 0x00 = mul %e0, %d0, 0
+0x73, 0x00, 0x6a, 0x00 = mul %e0, %d0, %d0
+0x4b, 0x00, 0x41, 0x00 = mul.f %d0, %d0, %d0
+0xb3, 0x00, 0x60, 0x00 = mul.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x64, 0x00 = mul.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x68, 0x00 = mul.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x6c, 0x00 = mul.h %e0, %d0, %d0uu, 0
+0x93, 0x00, 0x00, 0x00 = mul.q %d0, %d0, %d0u, 0
+0x93, 0x00, 0x04, 0x00 = mul.q %d0, %d0, %d0l, 0
+0x93, 0x00, 0x08, 0x00 = mul.q %d0, %d0, %d0, 0
+0x93, 0x00, 0x10, 0x00 = mul.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x14, 0x00 = mul.q %d0, %d0l, %d0l, 0
+0x93, 0x00, 0x60, 0x00 = mul.q %e0, %d0, %d0u, 0
+0x93, 0x00, 0x64, 0x00 = mul.q %e0, %d0, %d0l, 0
+0x93, 0x00, 0x6c, 0x00 = mul.q %e0, %d0, %d0, 0
+0x53, 0x00, 0x40, 0x00 = mul.u %e0, %d0, 0
+0x73, 0x00, 0x68, 0x00 = mul.u %e0, %d0, %d0
+0xb3, 0x00, 0x70, 0x00 = mulm.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x74, 0x00 = mulm.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x78, 0x00 = mulm.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x7c, 0x00 = mulm.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0xf0, 0x00 = mulms.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0xf4, 0x00 = mulms.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0xf8, 0x00 = mulms.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0xfc, 0x00 = mulms.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0x30, 0x00 = mulr.h %d0, %d0, %d0ul, 0
+0xb3, 0x00, 0x34, 0x00 = mulr.h %d0, %d0, %d0lu, 0
+0xb3, 0x00, 0x38, 0x00 = mulr.h %d0, %d0, %d0ll, 0
+0xb3, 0x00, 0x3c, 0x00 = mulr.h %d0, %d0, %d0uu, 0
+0x93, 0x00, 0x18, 0x00 = mulr.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x1c, 0x00 = mulr.q %d0, %d0l, %d0l, 0
+0x53, 0x00, 0xa0, 0x00 = muls %d0, %d0, 0
+0x73, 0x00, 0x8a, 0x00 = muls %d0, %d0, %d0
+0x53, 0x00, 0x80, 0x00 = muls.u %d0, %d0, 0
+0x73, 0x00, 0x88, 0x00 = muls.u %d0, %d0, %d0
+0x0f, 0x00, 0x90, 0x00 = nand %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x01 = nand %d0, %d0, 0
+0x07, 0x00, 0x00, 0x00 = nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x10, 0x01 = ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x02 = ne %d0, %d0, 0
+0x01, 0x00, 0x10, 0x04 = ne.a %d0, %a0, %a0
+0x01, 0x00, 0x90, 0x04 = nez.a %d0, %a0
+0x00, 0x00 = nop
+0x0d, 0x00, 0x00, 0x00 = nop
+0x46, 0x00 = nor %d0
+0x0f, 0x00, 0xb0, 0x00 = nor %d0, %d0, %d0
+0x8f, 0x00, 0x60, 0x01 = nor %d0, %d0, 0
+0x87, 0x00, 0x40, 0x00 = nor.t %d0, %d0, 0, %d0, 0
+0xa6, 0x00 = or %d0, %d0
+0x96, 0x00 = or %d15, 0
+0x0f, 0x00, 0xa0, 0x00 = or %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x01 = or %d0, %d0, 0
+0xc7, 0x00, 0x00, 0x00 = or.and.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x60, 0x00 = or.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x02 = or.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x04 = or.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x02 = or.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x05 = or.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x02 = or.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x05 = or.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x02 = or.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x05 = or.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x02 = or.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x05 = or.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x02 = or.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x05 = or.ne %d0, %d0, 0
+0xc7, 0x00, 0x40, 0x00 = or.nor.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x20, 0x00 = or.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x20, 0x00 = or.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xf0, 0x00 = orn %d0, %d0, %d0
+0x8f, 0x00, 0xe0, 0x01 = orn %d0, %d0, 0
+0x07, 0x00, 0x20, 0x00 = orn.t %d0, %d0, 0, %d0, 0
+0x6b, 0x00, 0x00, 0x00 = pack %d0, %e0, %d0
+0x4b, 0x00, 0x20, 0x00 = parity %d0, %d0
+0x4b, 0x00, 0x51, 0x01 = q31tof %d0, %d0, %d0
+0x4b, 0x00, 0x91, 0x01 = qseed.f %d0, %d0
+0x0d, 0x00, 0x80, 0x03 = restore %d0
+0x00, 0x90 = ret
+0x0d, 0x00, 0x80, 0x01 = ret
+0x00, 0x80 = rfe
+0x0d, 0x00, 0xc0, 0x01 = rfe
+0x0d, 0x00, 0x40, 0x01 = rfm
+0x0d, 0x00, 0x40, 0x02 = rslcx
+0x2f, 0x00, 0x00, 0x00 = rstv
+0x32, 0x50 = rsub %d0
+0x8b, 0x00, 0x00, 0x01 = rsub %d0, %d0, 0
+0x8b, 0x00, 0x40, 0x01 = rsubs %d0, %d0, 0
+0x8b, 0x00, 0x60, 0x01 = rsubs.u %d0, %d0, 0
+0x32, 0x00 = sat.b %d0
+0x0b, 0x00, 0xe0, 0x05 = sat.b %d0, %d0
+0x32, 0x10 = sat.bu %d0
+0x0b, 0x00, 0xf0, 0x05 = sat.bu %d0, %d0
+0x32, 0x20 = sat.h %d0
+0x0b, 0x00, 0xe0, 0x07 = sat.h %d0, %d0
+0x32, 0x30 = sat.hu %d0
+0x0b, 0x00, 0xf0, 0x07 = sat.hu %d0, %d0
+0x2b, 0x00, 0x40, 0x00 = sel %d0, %d0, %d0, %d0
+0xab, 0x00, 0x80, 0x00 = sel %d0, %d0, %d0, 0
+0x2b, 0x00, 0x50, 0x00 = seln %d0, %d0, %d0, %d0
+0xab, 0x00, 0xa0, 0x00 = seln %d0, %d0, %d0, 0
+0x06, 0x00 = sh %d0, 0
+0x0f, 0x00, 0x00, 0x00 = sh %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x00 = sh %d0, %d0, 0
+0x27, 0x00, 0x00, 0x00 = sh.and.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x60, 0x00 = sh.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x03 = sh.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x06 = sh.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x03 = sh.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x07 = sh.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x03 = sh.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x07 = sh.ge.u %d0, %d0, 0
+0x0f, 0x00, 0x00, 0x04 = sh.h %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x08 = sh.h %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x03 = sh.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x07 = sh.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x03 = sh.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x07 = sh.lt.u %d0, %d0, 0
+0xa7, 0x00, 0x00, 0x00 = sh.nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x80, 0x03 = sh.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x07 = sh.ne %d0, %d0, 0
+0x27, 0x00, 0x40, 0x00 = sh.nor.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x20, 0x00 = sh.or.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x20, 0x00 = sh.orn.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x40, 0x00 = sh.xnor.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x60, 0x00 = sh.xor.t %d0, %d0, 0, %d0, 0
+0x86, 0x00 = sha %d0, 0
+0x0f, 0x00, 0x10, 0x00 = sha %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x00 = sha %d0, %d0, 0
+0x0f, 0x00, 0x10, 0x04 = sha.h %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x08 = sha.h %d0, %d0, 0
+0x0f, 0x00, 0x20, 0x00 = shas %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x00 = shas %d0, %d0, 0
+0xf8, 0x00 = st.a [%sp]0, %a15
+0xec, 0x00 = st.a [%a0]0, %a15
+0xe8, 0x00 = st.a [%a15]0, %a0
+0xe4, 0x00 = st.a [%a0+], %a0
+0xf4, 0x00 = st.a [%a0], %a0
+0xb5, 0x00, 0x00, 0x00 = st.a [%a0]0, %a0
+0x89, 0x00, 0x80, 0x01 = st.a [%a0+]0, %a0
+0xa9, 0x00, 0x80, 0x01 = st.a [%p0+r], %a0
+0x89, 0x00, 0x80, 0x05 = st.a [+%a0]0, %a0
+0xa9, 0x00, 0x80, 0x05 = st.a [%p0+c]0, %a0
+0xa5, 0x00, 0x00, 0x08 = st.a 0, %a0
+0x89, 0x00, 0x80, 0x09 = st.a [%a0]0, %a0
+0x34, 0x00 = st.b [%a0], %d0
+0x28, 0x00 = st.b [%a15]0, %d0
+0x2c, 0x00 = st.b [%a0]0, %d15
+0x24, 0x00 = st.b [%a0+], %d0
+0xe9, 0x00, 0x00, 0x00 = st.b [%a0]0, %d0
+0x25, 0x00, 0x00, 0x00 = st.b 0, %d0
+0x89, 0x00, 0x00, 0x00 = st.b [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x00 = st.b [%p0+r], %d0
+0x89, 0x00, 0x00, 0x04 = st.b [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x04 = st.b [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x08 = st.b [%a0]0, %d0
+0x89, 0x00, 0x40, 0x01 = st.d [%a0+]0, %e0
+0xa9, 0x00, 0x40, 0x01 = st.d [%p0+r], %e0
+0xa5, 0x00, 0x00, 0x04 = st.d 0, %e0
+0x89, 0x00, 0x40, 0x05 = st.d [+%a0]0, %e0
+0xa9, 0x00, 0x40, 0x05 = st.d [%p0+c]0, %e0
+0x89, 0x00, 0x40, 0x09 = st.d [%a0]0, %e0
+0x89, 0x00, 0xc0, 0x01 = st.da [%a0+]0, %p0
+0xa9, 0x00, 0xc0, 0x01 = st.da [%p0+r], %p0
+0x89, 0x00, 0xc0, 0x05 = st.da [+%a0]0, %p0
+0xa9, 0x00, 0xc0, 0x05 = st.da [%p0+c]0, %p0
+0x89, 0x00, 0xc0, 0x09 = st.da [%a0]0, %p0
+0xa5, 0x00, 0x00, 0x0c = st.da 0, %p0
+0xa4, 0x00 = st.h [%a0+], %d0
+0xa8, 0x00 = st.h [%a15]0, %d0
+0xac, 0x00 = st.h [%a0]0, %d15
+0xb4, 0x00 = st.h [%a0], %d0
+0xf9, 0x00, 0x00, 0x00 = st.h [%a0]0, %d0
+0x89, 0x00, 0x80, 0x00 = st.h [%a0+]0, %d0
+0xa9, 0x00, 0x80, 0x00 = st.h [%p0+r], %d0
+0x89, 0x00, 0x80, 0x04 = st.h [+%a0]0, %d0
+0xa9, 0x00, 0x80, 0x04 = st.h [%p0+c]0, %d0
+0x25, 0x00, 0x00, 0x08 = st.h 0, %d0
+0x89, 0x00, 0x80, 0x08 = st.h [%a0]0, %d0
+0x65, 0x00, 0x00, 0x00 = st.q 0, %d0
+0x89, 0x00, 0x00, 0x02 = st.q [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x02 = st.q [%p0+r], %d0
+0x89, 0x00, 0x00, 0x06 = st.q [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x06 = st.q [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x0a = st.q [%a0]0, %d0
+0xd5, 0x00, 0x00, 0x00 = st.t 0, 0, 0
+0x78, 0x00 = st.w [%sp]0, %d15
+0x74, 0x00 = st.w [%a0], %d0
+0x64, 0x00 = st.w [%a0+], %d0
+0x68, 0x00 = st.w [%a15]0, %d0
+0x6c, 0x00 = st.w [%a0]0, %d15
+0x59, 0x00, 0x00, 0x00 = st.w [%a0]0, %d0
+0xa5, 0x00, 0x00, 0x00 = st.w 0, %d0
+0x89, 0x00, 0x00, 0x01 = st.w [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x01 = st.w [%p0+r], %d0
+0x89, 0x00, 0x00, 0x05 = st.w [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x05 = st.w [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x09 = st.w [%a0]0, %d0
+0x15, 0x00, 0x00, 0x00 = stlcx 0
+0x49, 0x00, 0x80, 0x09 = stlcx [%a0]0
+0x15, 0x00, 0x00, 0x04 = stucx 0
+0x49, 0x00, 0xc0, 0x09 = stucx [%a0]0
+0x52, 0x00 = sub %d0, %d15, %d0
+0x5a, 0x00 = sub %d15, %d0, %d0
+0xa2, 0x00 = sub %d0, %d0
+0x0b, 0x00, 0x80, 0x00 = sub %d0, %d0, %d0
+0x20, 0x00 = sub.a %sp, 0
+0x01, 0x00, 0x20, 0x00 = sub.a %a0, %a0, %a0
+0x0b, 0x00, 0x80, 0x04 = sub.b %d0, %d0, %d0
+0x6b, 0x00, 0x31, 0x00 = sub.f %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x06 = sub.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x00 = subc %d0, %d0, %d0
+0x62, 0x00 = subs %d0, %d0
+0x0b, 0x00, 0xa0, 0x00 = subs %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x06 = subs.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x06 = subs.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x00 = subs.u %d0, %d0, %d0
+0x0b, 0x00, 0xc0, 0x00 = subx %d0, %d0, %d0
+0x0d, 0x00, 0x00, 0x02 = svlcx
+0x49, 0x00, 0x00, 0x00 = swap.w [%a0+]0, %d0
+0x69, 0x00, 0x00, 0x00 = swap.w [%p0+r], %d0
+0xe5, 0x00, 0x00, 0x00 = swap.w 0, %d0
+0x49, 0x00, 0x00, 0x04 = swap.w [+%a0]0, %d0
+0x69, 0x00, 0x00, 0x04 = swap.w [%p0+c]0, %d0
+0x49, 0x00, 0x00, 0x08 = swap.w [%a0]0, %d0
+0x69, 0x00, 0x00, 0x08 = swap.w [%p0+i], %d0
+0xad, 0x00, 0x80, 0x00 = syscall 0
+0x75, 0x00, 0x00, 0x00 = tlbdemap %d0
+0x75, 0x00, 0x40, 0x00 = tlbflush.a
+0x75, 0x00, 0x50, 0x00 = tlbflush.b
+0x75, 0x00, 0x00, 0x04 = tlbmap %e0
+0x75, 0x00, 0x80, 0x00 = tlbprobe.a %d0
+0x75, 0x00, 0x90, 0x00 = tlbprobe.i %d0
+0x0d, 0x00, 0x40, 0x05 = trapsv
+0x0d, 0x00, 0x00, 0x05 = trapv
+0x4b, 0x00, 0x80, 0x00 = unpack %e0, %d0
+0x4b, 0x00, 0xc1, 0x00 = updfl %d0
+0x4b, 0x00, 0x61, 0x01 = utof %d0, %d0
+0x0f, 0x00, 0xd0, 0x00 = xnor %d0, %d0, %d0
+0x8f, 0x00, 0xa0, 0x01 = xnor %d0, %d0, 0
+0x07, 0x00, 0x40, 0x00 = xnor.t %d0, %d0, 0, %d0, 0
+0xc6, 0x00 = xor %d0, %d0
+0x0f, 0x00, 0xc0, 0x00 = xor %d0, %d0, %d0
+0x8f, 0x00, 0x80, 0x01 = xor %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x02 = xor.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x05 = xor.eq %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x03 = xor.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x06 = xor.ge %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x03 = xor.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x06 = xor.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x03 = xor.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x06 = xor.lt %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x03 = xor.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x06 = xor.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x00, 0x03 = xor.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x06 = xor.ne %d0, %d0, 0
+0x07, 0x00, 0x60, 0x00 = xor.t %d0, %d0, 0, %d0, 0
diff --git a/suite/MC/TriCore/tc161.s.cs b/suite/MC/TriCore/tc161.s.cs
new file mode 100644
index 0000000000..e4220199de
--- /dev/null
+++ b/suite/MC/TriCore/tc161.s.cs
@@ -0,0 +1,836 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_161, None
+0x0b, 0x00, 0xc0, 0x01 = abs %d0, %d0
+0x0b, 0x00, 0xc0, 0x05 = abs.b %d0, %d0
+0x0b, 0x00, 0xc0, 0x07 = abs.h %d0, %d0
+0x0b, 0x00, 0xe0, 0x00 = absdif %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x01 = absdif %d0, %d0, 0
+0x0b, 0x00, 0xe0, 0x04 = absdif.b %d0, %d0, %d0
+0x0b, 0x00, 0xe0, 0x06 = absdif.h %d0, %d0, %d0
+0x0b, 0x00, 0xf0, 0x00 = absdifs %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x01 = absdifs %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x06 = absdifs.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x01 = abss %d0, %d0
+0x0b, 0x00, 0xd0, 0x07 = abss.h %d0, %d0
+0x12, 0x00 = add %d0, %d15, %d0
+0x92, 0x00 = add %d0, %d15, 0
+0x1a, 0x00 = add %d15, %d0, %d0
+0x42, 0x00 = add %d0, %d0
+0x9a, 0x00 = add %d15, %d0, 0
+0xc2, 0x00 = add %d0, 0
+0x0b, 0x00, 0x00, 0x00 = add %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x00 = add %d0, %d0, 0
+0x30, 0x00 = add.a %a0, %a0
+0xb0, 0x00 = add.a %a0, 0
+0x01, 0x00, 0x10, 0x00 = add.a %a0, %a0, %a0
+0x0b, 0x00, 0x00, 0x04 = add.b %d0, %d0, %d0
+0x6b, 0x00, 0x21, 0x00 = add.f %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x06 = add.h %d0, %d0, %d0
+0x0b, 0x00, 0x50, 0x00 = addc %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x00 = addc %d0, %d0, 0
+0x1b, 0x00, 0x00, 0x00 = addi %d0, %d0, 0
+0x9b, 0x00, 0x00, 0x00 = addih %d0, %d0, 0
+0x11, 0x00, 0x00, 0x00 = addih.a %a0, %a0, 0
+0x22, 0x00 = adds %d0, %d0
+0x0b, 0x00, 0x20, 0x00 = adds %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x00 = adds %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x06 = adds.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x06 = adds.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x00 = adds.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x00 = adds.u %d0, %d0, 0
+0x10, 0x00 = addsc.a %a0, %a0, %d15, 0
+0x01, 0x00, 0x00, 0x06 = addsc.a %a0, %a0, %d0, 0
+0x01, 0x00, 0x20, 0x06 = addsc.at %a0, %a0, %d0
+0x0b, 0x00, 0x40, 0x00 = addx %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x00 = addx %d0, %d0, 0
+0x26, 0x00 = and %d0, %d0
+0x16, 0x00 = and %d15, 0
+0x0f, 0x00, 0x80, 0x00 = and %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x01 = and %d0, %d0, 0
+0x47, 0x00, 0x00, 0x00 = and.and.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x60, 0x00 = and.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x00, 0x02 = and.eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x04 = and.eq %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x02 = and.ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x04 = and.ge %d0, %d0, 0
+0x0b, 0x00, 0x50, 0x02 = and.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x04 = and.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x02 = and.lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x04 = and.lt %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x02 = and.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x04 = and.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x02 = and.ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x04 = and.ne %d0, %d0, 0
+0x47, 0x00, 0x40, 0x00 = and.nor.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x20, 0x00 = and.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x00, 0x00 = and.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xe0, 0x00 = andn %d0, %d0, %d0
+0x8f, 0x00, 0xc0, 0x01 = andn %d0, %d0, 0
+0x87, 0x00, 0x60, 0x00 = andn.t %d0, %d0, 0, %d0, 0
+0xe0, 0x00 = bisr 0
+0xad, 0x00, 0x00, 0x00 = bisr 0
+0xad, 0x00, 0x20, 0x00 = bisr 0
+0x4b, 0x00, 0x10, 0x00 = bmerge %d0, %d0, %d0
+0x4b, 0x00, 0x90, 0x00 = bsplit %e0, %d0
+0x89, 0x00, 0x80, 0x03 = cachea.i [%a0+]0
+0xa9, 0x00, 0x80, 0x03 = cachea.i [%p0+r]
+0x89, 0x00, 0x80, 0x07 = cachea.i [+%a0]0
+0xa9, 0x00, 0x80, 0x07 = cachea.i [%p0+c]0
+0x89, 0x00, 0x80, 0x0b = cachea.i [%a0]0
+0x89, 0x00, 0x00, 0x03 = cachea.w [%a0+]0
+0xa9, 0x00, 0x00, 0x03 = cachea.w [%p0+r]
+0x89, 0x00, 0x00, 0x07 = cachea.w [+%a0]0
+0xa9, 0x00, 0x00, 0x07 = cachea.w [%p0+c]0
+0x89, 0x00, 0x00, 0x0b = cachea.w [%a0]0
+0x89, 0x00, 0x40, 0x03 = cachea.wi [%a0+]0
+0xa9, 0x00, 0x40, 0x03 = cachea.wi [%p0+r]
+0x89, 0x00, 0x40, 0x07 = cachea.wi [+%a0]0
+0xa9, 0x00, 0x40, 0x07 = cachea.wi [%p0+c]0
+0x89, 0x00, 0x40, 0x0b = cachea.wi [%a0]0
+0x89, 0x00, 0x80, 0x02 = cachei.i [%a0+]0
+0x89, 0x00, 0x80, 0x06 = cachei.i [+%a0]0
+0x89, 0x00, 0x80, 0x0a = cachei.i [%a0]0
+0x89, 0x00, 0xc0, 0x02 = cachei.w [%a0+]0
+0x89, 0x00, 0xc0, 0x06 = cachei.w [+%a0]0
+0x89, 0x00, 0xc0, 0x0a = cachei.w [%a0]0
+0x89, 0x00, 0xc0, 0x03 = cachei.wi [%a0+]0
+0x89, 0x00, 0xc0, 0x07 = cachei.wi [+%a0]0
+0x89, 0x00, 0xc0, 0x0b = cachei.wi [%a0]0
+0x8a, 0x00 = cadd %d0, %d15, 0
+0x2b, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, %d0
+0xab, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, 0
+0xca, 0x00 = caddn %d0, %d15, 0
+0x2b, 0x00, 0x10, 0x00 = caddn %d0, %d0, %d0, %d0
+0xab, 0x00, 0x20, 0x00 = caddn %d0, %d0, %d0, 0
+0x5c, 0x00 = call 0
+0x6d, 0x00, 0x00, 0x00 = call 0
+0xed, 0x00, 0x00, 0x00 = calla 0
+0x2d, 0x00, 0x00, 0x00 = calli %a0
+0x0f, 0x00, 0xc0, 0x01 = clo %d0, %d0
+0x0f, 0x00, 0xd0, 0x07 = clo.h %d0, %d0
+0x0f, 0x00, 0xd0, 0x01 = cls %d0, %d0
+0x0f, 0x00, 0xe0, 0x07 = cls.h %d0, %d0
+0x0f, 0x00, 0xb0, 0x01 = clz %d0, %d0
+0x0f, 0x00, 0xc0, 0x07 = clz.h %d0, %d0
+0x2a, 0x00 = cmov %d0, %d15, %d0
+0xaa, 0x00 = cmov %d0, %d15, 0
+0x6a, 0x00 = cmovn %d0, %d15, %d0
+0xea, 0x00 = cmovn %d0, %d15, 0
+0x4b, 0x00, 0x00, 0x00 = cmp.f %d0, %d0, %d0
+0x49, 0x00, 0xc0, 0x08 = cmpswap.w [%a0]0, %e0
+0x69, 0x00, 0xc0, 0x00 = cmpswap.w [%p0+r], %e0
+0x69, 0x00, 0xc0, 0x04 = cmpswap.w [%p0+c]0, %e0
+0x49, 0x00, 0xc0, 0x00 = cmpswap.w [%a0+]0, %e0
+0x49, 0x00, 0xc0, 0x04 = cmpswap.w [+%a0]0, %e0
+0x2b, 0x00, 0x20, 0x00 = csub %d0, %d0, %d0, %d0
+0x2b, 0x00, 0x30, 0x00 = csubn %d0, %d0, %d0, %d0
+0x00, 0xa0 = debug
+0x0d, 0x00, 0x00, 0x01 = debug
+0x77, 0x00, 0x00, 0x00 = dextr %d0, %d0, %d0, 0
+0x17, 0x00, 0x80, 0x00 = dextr %d0, %d0, %d0, %d0
+0x0d, 0x00, 0x40, 0x03 = disable
+0x0d, 0x00, 0xc0, 0x03 = disable %d0
+0x4b, 0x00, 0x01, 0x02 = div %e0, %d0, %d0
+0x4b, 0x00, 0x11, 0x02 = div.u %e0, %d0, %d0
+0x4b, 0x00, 0x51, 0x00 = div.f %d0, %d0, %d0
+0x0d, 0x00, 0x80, 0x04 = dsync
+0x6b, 0x00, 0xd0, 0x00 = dvadj %e0, %e0, %d0
+0x4b, 0x00, 0xa0, 0x01 = dvinit %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x05 = dvinit.b %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x04 = dvinit.bu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x03 = dvinit.h %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x02 = dvinit.hu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x00 = dvinit.u %e0, %d0, %d0
+0x6b, 0x00, 0xf0, 0x00 = dvstep %e0, %e0, %d0
+0x6b, 0x00, 0xe0, 0x00 = dvstep.u %e0, %e0, %d0
+0x0d, 0x00, 0x00, 0x03 = enable
+0x3a, 0x00 = eq %d15, %d0, %d0
+0xba, 0x00 = eq %d15, %d0, 0
+0x0b, 0x00, 0x00, 0x01 = eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x02 = eq %d0, %d0, 0
+0x01, 0x00, 0x00, 0x04 = eq.a %d0, %a0, %a0
+0x0b, 0x00, 0x00, 0x05 = eq.b %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x07 = eq.h %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x09 = eq.w %d0, %d0, %d0
+0x0b, 0x00, 0x60, 0x05 = eqany.b %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0a = eqany.b %d0, %d0, 0
+0x0b, 0x00, 0x60, 0x07 = eqany.h %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0e = eqany.h %d0, %d0, 0
+0x01, 0x00, 0x80, 0x04 = eqz.a %d0, %a0
+0x17, 0x00, 0x40, 0x00 = extr %d0, %d0, %e0
+0x37, 0x00, 0x40, 0x00 = extr %d0, %d0, 0, 0
+0x57, 0x00, 0x40, 0x00 = extr %d0, %d0, %d0, 0
+0x17, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %e0
+0x37, 0x00, 0x60, 0x00 = extr.u %d0, %d0, 0, 0
+0x57, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %d0, 0
+0x61, 0x00, 0x00, 0x00 = fcall 0
+0xe1, 0x00, 0x00, 0x00 = fcalla 0
+0x2d, 0x00, 0x10, 0x00 = fcalli %a0
+0x00, 0x70 = fret
+0x0d, 0x00, 0xc0, 0x00 = fret
+0x4b, 0x00, 0x01, 0x01 = ftoi %d0, %d0
+0x4b, 0x00, 0x11, 0x01 = ftoq31 %d0, %d0, %d0
+0x4b, 0x00, 0x21, 0x01 = ftou %d0, %d0
+0x4b, 0x00, 0x31, 0x01 = ftoiz %d0, %d0
+0x4b, 0x00, 0x81, 0x01 = ftoq31z %d0, %d0, %d0
+0x4b, 0x00, 0x71, 0x01 = ftouz %d0, %d0
+0x0b, 0x00, 0x40, 0x01 = ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x02 = ge %d0, %d0, 0
+0x01, 0x00, 0x30, 0x04 = ge.a %d0, %a0, %a0
+0x0b, 0x00, 0x50, 0x01 = ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x02 = ge.u %d0, %d0, 0
+0x37, 0x00, 0x20, 0x00 = imask %e0, %d0, 0, 0
+0x57, 0x00, 0x20, 0x00 = imask %e0, %d0, %d0, 0
+0xb7, 0x00, 0x20, 0x00 = imask %e0, 0, 0, 0
+0xd7, 0x00, 0x20, 0x00 = imask %e0, 0, %d0, 0
+0x67, 0x00, 0x00, 0x00 = ins.t %d0, %d0, 0, %d0, 0
+0x17, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %e0
+0x37, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, 0, 0
+0x57, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %d0, 0
+0x97, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %e0
+0xb7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, 0, 0
+0xd7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %d0, 0
+0x67, 0x00, 0x20, 0x00 = insn.t %d0, %d0, 0, %d0, 0
+0x0d, 0x00, 0xc0, 0x04 = isync
+0x4b, 0x00, 0x41, 0x01 = itof %d0, %d0
+0x6b, 0x00, 0xa0, 0x00 = ixmax %e0, %e0, %d0
+0x6b, 0x00, 0xb0, 0x00 = ixmax.u %e0, %e0, %d0
+0x6b, 0x00, 0x80, 0x00 = ixmin %e0, %e0, %d0
+0x6b, 0x00, 0x90, 0x00 = ixmin.u %e0, %e0, %d0
+0x3c, 0x00 = j 0
+0x1d, 0x00, 0x00, 0x00 = j 0
+0x9d, 0x00, 0x00, 0x00 = ja 0
+0xbe, 0x00 = jeq %d15, %d0, 0x20
+0x9e, 0x00 = jeq %d15, 0, 0x20
+0x3e, 0x00 = jeq %d15, %d0, 0
+0x1e, 0x00 = jeq %d15, 0, 0
+0x5f, 0x00, 0x00, 0x00 = jeq %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x00 = jeq %d0, 0, 0
+0x7d, 0x00, 0x00, 0x00 = jeq.a %a0, %a0, 0
+0x7f, 0x00, 0x00, 0x00 = jge %d0, %d0, 0
+0xff, 0x00, 0x00, 0x00 = jge %d0, 0, 0
+0x7f, 0x00, 0x00, 0x80 = jge.u %d0, %d0, 0
+0xff, 0x00, 0x00, 0x80 = jge.u %d0, 0, 0
+0xce, 0x00 = jgez %d0, 0
+0x4e, 0x00 = jgtz %d0, 0
+0xdc, 0x00 = ji %a0
+0x2d, 0x00, 0x30, 0x00 = ji %a0
+0x5d, 0x00, 0x00, 0x00 = jl 0
+0xdd, 0x00, 0x00, 0x00 = jla 0
+0x8e, 0x00 = jlez %d0, 0
+0x2d, 0x00, 0x20, 0x00 = jli %a0
+0x3f, 0x00, 0x00, 0x00 = jlt %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x00 = jlt %d0, 0, 0
+0x3f, 0x00, 0x00, 0x80 = jlt.u %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x80 = jlt.u %d0, 0, 0
+0x0e, 0x00 = jltz %d0, 0
+0xfe, 0x00 = jne %d15, %d0, 0x20
+0xde, 0x00 = jne %d15, 0, 0x20
+0x7e, 0x00 = jne %d15, %d0, 0
+0x5e, 0x00 = jne %d15, 0, 0
+0x5f, 0x00, 0x00, 0x80 = jne %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x80 = jne %d0, 0, 0
+0x7d, 0x00, 0x00, 0x80 = jne.a %a0, %a0, 0
+0x1f, 0x00, 0x00, 0x80 = jned %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x80 = jned %d0, 0, 0
+0x1f, 0x00, 0x00, 0x00 = jnei %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x00 = jnei %d0, 0, 0
+0xee, 0x00 = jnz %d15, 0
+0xf6, 0x00 = jnz %d0, 0
+0x7c, 0x00 = jnz.a %a0, 0
+0xbd, 0x00, 0x00, 0x80 = jnz.a %a0, 0
+0xae, 0x00 = jnz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x80 = jnz.t %d0, 0, 0
+0x6e, 0x00 = jz %d15, 0
+0x76, 0x00 = jz %d0, 0
+0xbc, 0x00 = jz.a %a0, 0
+0xbd, 0x00, 0x00, 0x00 = jz.a %a0, 0
+0x2e, 0x00 = jz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x00 = jz.t %d0, 0, 0
+0xd8, 0x00 = ld.a %a15, [%sp]0
+0xc8, 0x00 = ld.a %a0, [%a15]0
+0xcc, 0x00 = ld.a %a15, [%a0]0
+0xc4, 0x00 = ld.a %a0, [%a0+]
+0xd4, 0x00 = ld.a %a0, [%a0]
+0x99, 0x00, 0x00, 0x00 = ld.a %a0, [%a0]0
+0x09, 0x00, 0x80, 0x01 = ld.a %a0, [%a0+]0
+0x29, 0x00, 0x80, 0x01 = ld.a %a0, [%p0+r]
+0x09, 0x00, 0x80, 0x05 = ld.a %a0, [+%a0]0
+0x29, 0x00, 0x80, 0x05 = ld.a %a0, [%p0+c]0
+0x85, 0x00, 0x00, 0x08 = ld.a %a0, 0
+0x09, 0x00, 0x80, 0x09 = ld.a %a0, [%a0]0
+0x79, 0x00, 0x00, 0x00 = ld.b %d0, [%a0]0
+0x05, 0x00, 0x00, 0x00 = ld.b %d0, 0
+0x09, 0x00, 0x00, 0x00 = ld.b %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x00 = ld.b %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x04 = ld.b %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x04 = ld.b %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x08 = ld.b %d0, [%a0]0
+0x14, 0x00 = ld.bu %d0, [%a0]
+0x0c, 0x00 = ld.bu %d15, [%a0]0
+0x08, 0x00 = ld.bu %d0, [%a15]0
+0x04, 0x00 = ld.bu %d0, [%a0+]
+0x39, 0x00, 0x00, 0x00 = ld.bu %d0, [%a0]0
+0x09, 0x00, 0x40, 0x00 = ld.bu %d0, [%a0+]0
+0x29, 0x00, 0x40, 0x00 = ld.bu %d0, [%p0+r]
+0x05, 0x00, 0x00, 0x04 = ld.bu %d0, 0
+0x09, 0x00, 0x40, 0x04 = ld.bu %d0, [+%a0]0
+0x29, 0x00, 0x40, 0x04 = ld.bu %d0, [%p0+c]0
+0x09, 0x00, 0x40, 0x08 = ld.bu %d0, [%a0]0
+0x09, 0x00, 0x40, 0x01 = ld.d %e0, [%a0+]0
+0x29, 0x00, 0x40, 0x01 = ld.d %e0, [%p0+r]
+0x85, 0x00, 0x00, 0x04 = ld.d %e0, 0
+0x09, 0x00, 0x40, 0x05 = ld.d %e0, [+%a0]0
+0x29, 0x00, 0x40, 0x05 = ld.d %e0, [%p0+c]0
+0x09, 0x00, 0x40, 0x09 = ld.d %e0, [%a0]0
+0x09, 0x00, 0xc0, 0x01 = ld.da %p0, [%a0+]0
+0x29, 0x00, 0xc0, 0x01 = ld.da %p0, [%p0+r]
+0x09, 0x00, 0xc0, 0x05 = ld.da %p0, [+%a0]0
+0x29, 0x00, 0xc0, 0x05 = ld.da %p0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x09 = ld.da %p0, [%a0]0
+0x85, 0x00, 0x00, 0x0c = ld.da %p0, 0
+0x84, 0x00 = ld.h %d0, [%a0+]
+0x8c, 0x00 = ld.h %d15, [%a0]0
+0x88, 0x00 = ld.h %d0, [%a15]0
+0x94, 0x00 = ld.h %d0, [%a0]
+0xc9, 0x00, 0x00, 0x00 = ld.h %d0, [%a0]0
+0x09, 0x00, 0x80, 0x00 = ld.h %d0, [%a0+]0
+0x29, 0x00, 0x80, 0x00 = ld.h %d0, [%p0+r]
+0x09, 0x00, 0x80, 0x04 = ld.h %d0, [+%a0]0
+0x29, 0x00, 0x80, 0x04 = ld.h %d0, [%p0+c]0
+0x05, 0x00, 0x00, 0x08 = ld.h %d0, 0
+0x09, 0x00, 0x80, 0x08 = ld.h %d0, [%a0]0
+0xb9, 0x00, 0x00, 0x00 = ld.hu %d0, [%a0]0
+0x09, 0x00, 0xc0, 0x00 = ld.hu %d0, [%a0+]0
+0x29, 0x00, 0xc0, 0x00 = ld.hu %d0, [%p0+r]
+0x09, 0x00, 0xc0, 0x04 = ld.hu %d0, [+%a0]0
+0x29, 0x00, 0xc0, 0x04 = ld.hu %d0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x08 = ld.hu %d0, [%a0]0
+0x05, 0x00, 0x00, 0x0c = ld.hu %d0, 0
+0x45, 0x00, 0x00, 0x00 = ld.q %d0, 0
+0x09, 0x00, 0x00, 0x02 = ld.q %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x02 = ld.q %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x06 = ld.q %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x06 = ld.q %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x0a = ld.q %d0, [%a0]0
+0x58, 0x00 = ld.w %d15, [%sp]0
+0x54, 0x00 = ld.w %d0, [%a0]
+0x44, 0x00 = ld.w %d0, [%a0+]
+0x4c, 0x00 = ld.w %d15, [%a0]0
+0x48, 0x00 = ld.w %d0, [%a15]0
+0x19, 0x00, 0x00, 0x00 = ld.w %d0, [%a0]0
+0x85, 0x00, 0x00, 0x00 = ld.w %d0, 0
+0x09, 0x00, 0x00, 0x01 = ld.w %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x01 = ld.w %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x05 = ld.w %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x05 = ld.w %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x09 = ld.w %d0, [%a0]0
+0x15, 0x00, 0x00, 0x08 = ldlcx 0
+0x49, 0x00, 0x00, 0x09 = ldlcx [%a0]0
+0x49, 0x00, 0x40, 0x00 = ldmst [%a0+]0, %e0
+0x69, 0x00, 0x40, 0x00 = ldmst [%p0+r], %e0
+0xe5, 0x00, 0x00, 0x04 = ldmst 0, %e0
+0x49, 0x00, 0x40, 0x04 = ldmst [+%a0]0, %e0
+0x69, 0x00, 0x40, 0x04 = ldmst [%p0+c]0, %e0
+0x49, 0x00, 0x40, 0x08 = ldmst [%a0]0, %e0
+0x49, 0x00, 0x40, 0x09 = lducx [%a0]0
+0x15, 0x00, 0x00, 0x0c = lducx 0
+0xc5, 0x00, 0x00, 0x00 = lea %a0, 0
+0xd9, 0x00, 0x00, 0x00 = lea %a0, [%a0]0
+0x49, 0x00, 0x00, 0x0a = lea %a0, [%a0]0
+0xfc, 0x00 = loop %a0, -0x20
+0xfd, 0x00, 0x00, 0x00 = loop %a0, 0
+0xfd, 0x00, 0x00, 0x80 = loopu 0
+0x7a, 0x00 = lt %d15, %d0, %d0
+0xfa, 0x00 = lt %d15, %d0, 0
+0x0b, 0x00, 0x20, 0x01 = lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x02 = lt %d0, %d0, 0
+0x01, 0x00, 0x20, 0x04 = lt.a %d0, %a0, %a0
+0x0b, 0x00, 0x20, 0x05 = lt.b %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x05 = lt.bu %d0, %d0, %d0
+0x0b, 0x00, 0x20, 0x07 = lt.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x07 = lt.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x01 = lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x02 = lt.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x09 = lt.w %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x09 = lt.wu %d0, %d0, %d0
+0x03, 0x00, 0x0a, 0x00 = madd %d0, %d0, %d0, %d0
+0x13, 0x00, 0x20, 0x00 = madd %d0, %d0, %d0, 0
+0x13, 0x00, 0x60, 0x00 = madd %e0, %e0, %d0, 0
+0x03, 0x00, 0x6a, 0x00 = madd %e0, %e0, %d0, %d0
+0x6b, 0x00, 0x61, 0x00 = madd.f %d0, %d0, %d0, %d0
+0x83, 0x00, 0x60, 0x00 = madd.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x64, 0x00 = madd.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x68, 0x00 = madd.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x6c, 0x00 = madd.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x10, 0x00 = madd.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x00, 0x00 = madd.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x04, 0x00 = madd.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x08, 0x00 = madd.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x14, 0x00 = madd.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0x60, 0x00 = madd.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0x64, 0x00 = madd.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0x6c, 0x00 = madd.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0x70, 0x00 = madd.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0x74, 0x00 = madd.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x40, 0x00 = madd.u %e0, %e0, %d0, 0
+0x03, 0x00, 0x68, 0x00 = madd.u %e0, %e0, %d0, %d0
+0x83, 0x00, 0x70, 0x00 = maddm.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x74, 0x00 = maddm.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x78, 0x00 = maddm.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x7c, 0x00 = maddm.h %e0, %e0, %d0, %d0uu, 0
+0x83, 0x00, 0xf0, 0x00 = maddms.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xf4, 0x00 = maddms.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xf8, 0x00 = maddms.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xfc, 0x00 = maddms.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x78, 0x00 = maddr.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x30, 0x00 = maddr.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0x34, 0x00 = maddr.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0x38, 0x00 = maddr.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0x3c, 0x00 = maddr.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x18, 0x00 = maddr.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x1c, 0x00 = maddr.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xf8, 0x00 = maddrs.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xb0, 0x00 = maddrs.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0xb4, 0x00 = maddrs.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0xb8, 0x00 = maddrs.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0xbc, 0x00 = maddrs.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x98, 0x00 = maddrs.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x9c, 0x00 = maddrs.q %d0, %d0, %d0l, %d0l, 0
+0x03, 0x00, 0x8a, 0x00 = madds %d0, %d0, %d0, %d0
+0x13, 0x00, 0xa0, 0x00 = madds %d0, %d0, %d0, 0
+0x13, 0x00, 0xe0, 0x00 = madds %e0, %e0, %d0, 0
+0x03, 0x00, 0xea, 0x00 = madds %e0, %e0, %d0, %d0
+0x83, 0x00, 0xe0, 0x00 = madds.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xe4, 0x00 = madds.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xe8, 0x00 = madds.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xec, 0x00 = madds.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x90, 0x00 = madds.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x80, 0x00 = madds.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x84, 0x00 = madds.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x88, 0x00 = madds.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x94, 0x00 = madds.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xe0, 0x00 = madds.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0xe4, 0x00 = madds.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0xec, 0x00 = madds.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0xf0, 0x00 = madds.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0xf4, 0x00 = madds.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x80, 0x00 = madds.u %d0, %d0, %d0, 0
+0x03, 0x00, 0x88, 0x00 = madds.u %d0, %d0, %d0, %d0
+0x13, 0x00, 0xc0, 0x00 = madds.u %e0, %e0, %d0, 0
+0x03, 0x00, 0xe8, 0x00 = madds.u %e0, %e0, %d0, %d0
+0xc3, 0x00, 0x60, 0x00 = maddsu.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x64, 0x00 = maddsu.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x68, 0x00 = maddsu.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x6c, 0x00 = maddsu.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x70, 0x00 = maddsum.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x74, 0x00 = maddsum.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x78, 0x00 = maddsum.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x7c, 0x00 = maddsum.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0xf0, 0x00 = maddsums.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xf4, 0x00 = maddsums.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xf8, 0x00 = maddsums.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xfc, 0x00 = maddsums.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x30, 0x00 = maddsur.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0x34, 0x00 = maddsur.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0x38, 0x00 = maddsur.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0x3c, 0x00 = maddsur.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xb0, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0xb4, 0x00 = maddsurs.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0xb8, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0xbc, 0x00 = maddsurs.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xe0, 0x00 = maddsus.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xe4, 0x00 = maddsus.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xe8, 0x00 = maddsus.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xec, 0x00 = maddsus.h %e0, %e0, %d0, %d0uu, 0
+0x0b, 0x00, 0xa0, 0x01 = max %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x03 = max %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x05 = max.b %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x05 = max.bu %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x07 = max.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x07 = max.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x01 = max.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x03 = max.u %d0, %d0, 0
+0x4d, 0x00, 0x00, 0x00 = mfcr %d0, 0
+0x0b, 0x00, 0x80, 0x01 = min %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x03 = min %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x05 = min.b %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x05 = min.bu %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x07 = min.h %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x07 = min.hu %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x01 = min.u %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x03 = min.u %d0, %d0, 0
+0x02, 0x00 = mov %d0, %d0
+0x82, 0x00 = mov %d0, 0
+0xd2, 0x00 = mov %e0, 0
+0xda, 0x00 = mov %d15, 0
+0x3b, 0x00, 0x00, 0x00 = mov %d0, 0
+0x0b, 0x00, 0xf0, 0x01 = mov %d0, %d0
+0xfb, 0x00, 0x00, 0x00 = mov %e0, 0
+0x0b, 0x00, 0x00, 0x08 = mov %e0, %d0
+0x0b, 0x00, 0x10, 0x08 = mov %e0, %d0, %d0
+0xa0, 0x00 = mov.a %a0, 0
+0x60, 0x00 = mov.a %a0, %d0
+0x01, 0x00, 0x30, 0x06 = mov.a %a0, %d0
+0x40, 0x00 = mov.aa %a0, %a0
+0x01, 0x00, 0x00, 0x00 = mov.aa %a0, %a0
+0x80, 0x00 = mov.d %d0, %a0
+0x01, 0x00, 0xc0, 0x04 = mov.d %d0, %a0
+0xbb, 0x00, 0x00, 0x00 = mov.u %d0, 0
+0x7b, 0x00, 0x00, 0x00 = movh %d0, 0
+0x91, 0x00, 0x00, 0x00 = movh.a %a0, 0
+0x23, 0x00, 0x0a, 0x00 = msub %d0, %d0, %d0, %d0
+0x33, 0x00, 0x20, 0x00 = msub %d0, %d0, %d0, 0
+0x33, 0x00, 0x60, 0x00 = msub %e0, %e0, %d0, 0
+0x23, 0x00, 0x6a, 0x00 = msub %e0, %e0, %d0, %d0
+0x6b, 0x00, 0x71, 0x00 = msub.f %d0, %d0, %d0, %d0
+0xa3, 0x00, 0x60, 0x00 = msub.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x64, 0x00 = msub.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x68, 0x00 = msub.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x6c, 0x00 = msub.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x10, 0x00 = msub.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x00, 0x00 = msub.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x04, 0x00 = msub.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x08, 0x00 = msub.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x14, 0x00 = msub.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0x60, 0x00 = msub.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0x64, 0x00 = msub.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0x6c, 0x00 = msub.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0x70, 0x00 = msub.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0x74, 0x00 = msub.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x40, 0x00 = msub.u %e0, %e0, %d0, 0
+0x23, 0x00, 0x68, 0x00 = msub.u %e0, %e0, %d0, %d0
+0xe3, 0x00, 0x60, 0x00 = msubad.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x64, 0x00 = msubad.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x68, 0x00 = msubad.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x6c, 0x00 = msubad.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x70, 0x00 = msubadm.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x74, 0x00 = msubadm.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x78, 0x00 = msubadm.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x7c, 0x00 = msubadm.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0xf0, 0x00 = msubadms.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xf4, 0x00 = msubadms.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xf8, 0x00 = msubadms.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xfc, 0x00 = msubadms.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x30, 0x00 = msubadr.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0x34, 0x00 = msubadr.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0x38, 0x00 = msubadr.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0x3c, 0x00 = msubadr.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xb0, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0xb4, 0x00 = msubadrs.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0xb8, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0xbc, 0x00 = msubadrs.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xe0, 0x00 = msubads.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xe4, 0x00 = msubads.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xe8, 0x00 = msubads.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xec, 0x00 = msubads.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0x70, 0x00 = msubm.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x74, 0x00 = msubm.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x78, 0x00 = msubm.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x7c, 0x00 = msubm.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0xf0, 0x00 = msubms.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xf4, 0x00 = msubms.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xf8, 0x00 = msubms.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xfc, 0x00 = msubms.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x78, 0x00 = msubr.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x30, 0x00 = msubr.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0x34, 0x00 = msubr.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0x38, 0x00 = msubr.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0x3c, 0x00 = msubr.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x18, 0x00 = msubr.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x1c, 0x00 = msubr.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xf8, 0x00 = msubrs.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb0, 0x00 = msubrs.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb4, 0x00 = msubrs.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0xb8, 0x00 = msubrs.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0xbc, 0x00 = msubrs.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x98, 0x00 = msubrs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x9c, 0x00 = msubrs.q %d0, %d0, %d0l, %d0l, 0
+0x23, 0x00, 0x8a, 0x00 = msubs %d0, %d0, %d0, %d0
+0x33, 0x00, 0xa0, 0x00 = msubs %d0, %d0, %d0, 0
+0x33, 0x00, 0xe0, 0x00 = msubs %e0, %e0, %d0, 0
+0x23, 0x00, 0xea, 0x00 = msubs %e0, %e0, %d0, %d0
+0xa3, 0x00, 0xe0, 0x00 = msubs.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xe4, 0x00 = msubs.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xe8, 0x00 = msubs.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xec, 0x00 = msubs.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x90, 0x00 = msubs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x80, 0x00 = msubs.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x84, 0x00 = msubs.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x88, 0x00 = msubs.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x94, 0x00 = msubs.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xe0, 0x00 = msubs.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0xe4, 0x00 = msubs.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0xec, 0x00 = msubs.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0xf0, 0x00 = msubs.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0xf4, 0x00 = msubs.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x80, 0x00 = msubs.u %d0, %d0, %d0, 0
+0x23, 0x00, 0x88, 0x00 = msubs.u %d0, %d0, %d0, %d0
+0x33, 0x00, 0xc0, 0x00 = msubs.u %e0, %e0, %d0, 0
+0x23, 0x00, 0xe8, 0x00 = msubs.u %e0, %e0, %d0, %d0
+0xcd, 0x00, 0x00, 0x00 = mtcr 0, %d0
+0xe2, 0x00 = mul %d0, %d0
+0x53, 0x00, 0x20, 0x00 = mul %d0, %d0, 0
+0x73, 0x00, 0x0a, 0x00 = mul %d0, %d0, %d0
+0x53, 0x00, 0x60, 0x00 = mul %e0, %d0, 0
+0x73, 0x00, 0x6a, 0x00 = mul %e0, %d0, %d0
+0x4b, 0x00, 0x41, 0x00 = mul.f %d0, %d0, %d0
+0xb3, 0x00, 0x60, 0x00 = mul.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x64, 0x00 = mul.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x68, 0x00 = mul.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x6c, 0x00 = mul.h %e0, %d0, %d0uu, 0
+0x93, 0x00, 0x00, 0x00 = mul.q %d0, %d0, %d0u, 0
+0x93, 0x00, 0x04, 0x00 = mul.q %d0, %d0, %d0l, 0
+0x93, 0x00, 0x08, 0x00 = mul.q %d0, %d0, %d0, 0
+0x93, 0x00, 0x10, 0x00 = mul.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x14, 0x00 = mul.q %d0, %d0l, %d0l, 0
+0x93, 0x00, 0x60, 0x00 = mul.q %e0, %d0, %d0u, 0
+0x93, 0x00, 0x64, 0x00 = mul.q %e0, %d0, %d0l, 0
+0x93, 0x00, 0x6c, 0x00 = mul.q %e0, %d0, %d0, 0
+0x53, 0x00, 0x40, 0x00 = mul.u %e0, %d0, 0
+0x73, 0x00, 0x68, 0x00 = mul.u %e0, %d0, %d0
+0xb3, 0x00, 0x70, 0x00 = mulm.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x74, 0x00 = mulm.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x78, 0x00 = mulm.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x7c, 0x00 = mulm.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0xf0, 0x00 = mulms.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0xf4, 0x00 = mulms.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0xf8, 0x00 = mulms.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0xfc, 0x00 = mulms.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0x30, 0x00 = mulr.h %d0, %d0, %d0ul, 0
+0xb3, 0x00, 0x34, 0x00 = mulr.h %d0, %d0, %d0lu, 0
+0xb3, 0x00, 0x38, 0x00 = mulr.h %d0, %d0, %d0ll, 0
+0xb3, 0x00, 0x3c, 0x00 = mulr.h %d0, %d0, %d0uu, 0
+0x93, 0x00, 0x18, 0x00 = mulr.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x1c, 0x00 = mulr.q %d0, %d0l, %d0l, 0
+0x53, 0x00, 0xa0, 0x00 = muls %d0, %d0, 0
+0x73, 0x00, 0x8a, 0x00 = muls %d0, %d0, %d0
+0x53, 0x00, 0x80, 0x00 = muls.u %d0, %d0, 0
+0x73, 0x00, 0x88, 0x00 = muls.u %d0, %d0, %d0
+0x0f, 0x00, 0x90, 0x00 = nand %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x01 = nand %d0, %d0, 0
+0x07, 0x00, 0x00, 0x00 = nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x10, 0x01 = ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x02 = ne %d0, %d0, 0
+0x01, 0x00, 0x10, 0x04 = ne.a %d0, %a0, %a0
+0x01, 0x00, 0x90, 0x04 = nez.a %d0, %a0
+0x00, 0x00 = nop
+0x0d, 0x00, 0x00, 0x00 = nop
+0x46, 0x00 = nor %d0
+0x0f, 0x00, 0xb0, 0x00 = nor %d0, %d0, %d0
+0x8f, 0x00, 0x60, 0x01 = nor %d0, %d0, 0
+0x87, 0x00, 0x40, 0x00 = nor.t %d0, %d0, 0, %d0, 0
+0xa6, 0x00 = or %d0, %d0
+0x96, 0x00 = or %d15, 0
+0x0f, 0x00, 0xa0, 0x00 = or %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x01 = or %d0, %d0, 0
+0xc7, 0x00, 0x00, 0x00 = or.and.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x60, 0x00 = or.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x02 = or.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x04 = or.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x02 = or.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x05 = or.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x02 = or.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x05 = or.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x02 = or.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x05 = or.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x02 = or.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x05 = or.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x02 = or.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x05 = or.ne %d0, %d0, 0
+0xc7, 0x00, 0x40, 0x00 = or.nor.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x20, 0x00 = or.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x20, 0x00 = or.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xf0, 0x00 = orn %d0, %d0, %d0
+0x8f, 0x00, 0xe0, 0x01 = orn %d0, %d0, 0
+0x07, 0x00, 0x20, 0x00 = orn.t %d0, %d0, 0, %d0, 0
+0x6b, 0x00, 0x00, 0x00 = pack %d0, %e0, %d0
+0x4b, 0x00, 0x20, 0x00 = parity %d0, %d0
+0x4b, 0x00, 0x51, 0x01 = q31tof %d0, %d0, %d0
+0x4b, 0x00, 0x91, 0x01 = qseed.f %d0, %d0
+0x0d, 0x00, 0x80, 0x03 = restore %d0
+0x00, 0x90 = ret
+0x0d, 0x00, 0x80, 0x01 = ret
+0x00, 0x80 = rfe
+0x0d, 0x00, 0xc0, 0x01 = rfe
+0x0d, 0x00, 0x40, 0x01 = rfm
+0x0d, 0x00, 0x40, 0x02 = rslcx
+0x2f, 0x00, 0x00, 0x00 = rstv
+0x32, 0x50 = rsub %d0
+0x8b, 0x00, 0x00, 0x01 = rsub %d0, %d0, 0
+0x8b, 0x00, 0x40, 0x01 = rsubs %d0, %d0, 0
+0x8b, 0x00, 0x60, 0x01 = rsubs.u %d0, %d0, 0
+0x32, 0x00 = sat.b %d0
+0x0b, 0x00, 0xe0, 0x05 = sat.b %d0, %d0
+0x32, 0x10 = sat.bu %d0
+0x0b, 0x00, 0xf0, 0x05 = sat.bu %d0, %d0
+0x32, 0x20 = sat.h %d0
+0x0b, 0x00, 0xe0, 0x07 = sat.h %d0, %d0
+0x32, 0x30 = sat.hu %d0
+0x0b, 0x00, 0xf0, 0x07 = sat.hu %d0, %d0
+0x2b, 0x00, 0x40, 0x00 = sel %d0, %d0, %d0, %d0
+0xab, 0x00, 0x80, 0x00 = sel %d0, %d0, %d0, 0
+0x2b, 0x00, 0x50, 0x00 = seln %d0, %d0, %d0, %d0
+0xab, 0x00, 0xa0, 0x00 = seln %d0, %d0, %d0, 0
+0x06, 0x00 = sh %d0, 0
+0x0f, 0x00, 0x00, 0x00 = sh %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x00 = sh %d0, %d0, 0
+0x27, 0x00, 0x00, 0x00 = sh.and.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x60, 0x00 = sh.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x03 = sh.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x06 = sh.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x03 = sh.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x07 = sh.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x03 = sh.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x07 = sh.ge.u %d0, %d0, 0
+0x0f, 0x00, 0x00, 0x04 = sh.h %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x08 = sh.h %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x03 = sh.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x07 = sh.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x03 = sh.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x07 = sh.lt.u %d0, %d0, 0
+0xa7, 0x00, 0x00, 0x00 = sh.nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x80, 0x03 = sh.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x07 = sh.ne %d0, %d0, 0
+0x27, 0x00, 0x40, 0x00 = sh.nor.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x20, 0x00 = sh.or.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x20, 0x00 = sh.orn.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x40, 0x00 = sh.xnor.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x60, 0x00 = sh.xor.t %d0, %d0, 0, %d0, 0
+0x86, 0x00 = sha %d0, 0
+0x0f, 0x00, 0x10, 0x00 = sha %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x00 = sha %d0, %d0, 0
+0x0f, 0x00, 0x10, 0x04 = sha.h %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x08 = sha.h %d0, %d0, 0
+0x0f, 0x00, 0x20, 0x00 = shas %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x00 = shas %d0, %d0, 0
+0xf8, 0x00 = st.a [%sp]0, %a15
+0xec, 0x00 = st.a [%a0]0, %a15
+0xe8, 0x00 = st.a [%a15]0, %a0
+0xe4, 0x00 = st.a [%a0+], %a0
+0xf4, 0x00 = st.a [%a0], %a0
+0xb5, 0x00, 0x00, 0x00 = st.a [%a0]0, %a0
+0x89, 0x00, 0x80, 0x01 = st.a [%a0+]0, %a0
+0xa9, 0x00, 0x80, 0x01 = st.a [%p0+r], %a0
+0x89, 0x00, 0x80, 0x05 = st.a [+%a0]0, %a0
+0xa9, 0x00, 0x80, 0x05 = st.a [%p0+c]0, %a0
+0xa5, 0x00, 0x00, 0x08 = st.a 0, %a0
+0x89, 0x00, 0x80, 0x09 = st.a [%a0]0, %a0
+0x34, 0x00 = st.b [%a0], %d0
+0x28, 0x00 = st.b [%a15]0, %d0
+0x2c, 0x00 = st.b [%a0]0, %d15
+0x24, 0x00 = st.b [%a0+], %d0
+0xe9, 0x00, 0x00, 0x00 = st.b [%a0]0, %d0
+0x25, 0x00, 0x00, 0x00 = st.b 0, %d0
+0x89, 0x00, 0x00, 0x00 = st.b [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x00 = st.b [%p0+r], %d0
+0x89, 0x00, 0x00, 0x04 = st.b [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x04 = st.b [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x08 = st.b [%a0]0, %d0
+0x89, 0x00, 0x40, 0x01 = st.d [%a0+]0, %e0
+0xa9, 0x00, 0x40, 0x01 = st.d [%p0+r], %e0
+0xa5, 0x00, 0x00, 0x04 = st.d 0, %e0
+0x89, 0x00, 0x40, 0x05 = st.d [+%a0]0, %e0
+0xa9, 0x00, 0x40, 0x05 = st.d [%p0+c]0, %e0
+0x89, 0x00, 0x40, 0x09 = st.d [%a0]0, %e0
+0x89, 0x00, 0xc0, 0x01 = st.da [%a0+]0, %p0
+0xa9, 0x00, 0xc0, 0x01 = st.da [%p0+r], %p0
+0x89, 0x00, 0xc0, 0x05 = st.da [+%a0]0, %p0
+0xa9, 0x00, 0xc0, 0x05 = st.da [%p0+c]0, %p0
+0x89, 0x00, 0xc0, 0x09 = st.da [%a0]0, %p0
+0xa5, 0x00, 0x00, 0x0c = st.da 0, %p0
+0xa4, 0x00 = st.h [%a0+], %d0
+0xa8, 0x00 = st.h [%a15]0, %d0
+0xac, 0x00 = st.h [%a0]0, %d15
+0xb4, 0x00 = st.h [%a0], %d0
+0xf9, 0x00, 0x00, 0x00 = st.h [%a0]0, %d0
+0x89, 0x00, 0x80, 0x00 = st.h [%a0+]0, %d0
+0xa9, 0x00, 0x80, 0x00 = st.h [%p0+r], %d0
+0x89, 0x00, 0x80, 0x04 = st.h [+%a0]0, %d0
+0xa9, 0x00, 0x80, 0x04 = st.h [%p0+c]0, %d0
+0x25, 0x00, 0x00, 0x08 = st.h 0, %d0
+0x89, 0x00, 0x80, 0x08 = st.h [%a0]0, %d0
+0x65, 0x00, 0x00, 0x00 = st.q 0, %d0
+0x89, 0x00, 0x00, 0x02 = st.q [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x02 = st.q [%p0+r], %d0
+0x89, 0x00, 0x00, 0x06 = st.q [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x06 = st.q [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x0a = st.q [%a0]0, %d0
+0xd5, 0x00, 0x00, 0x00 = st.t 0, 0, 0
+0x78, 0x00 = st.w [%sp]0, %d15
+0x74, 0x00 = st.w [%a0], %d0
+0x64, 0x00 = st.w [%a0+], %d0
+0x68, 0x00 = st.w [%a15]0, %d0
+0x6c, 0x00 = st.w [%a0]0, %d15
+0x59, 0x00, 0x00, 0x00 = st.w [%a0]0, %d0
+0xa5, 0x00, 0x00, 0x00 = st.w 0, %d0
+0x89, 0x00, 0x00, 0x01 = st.w [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x01 = st.w [%p0+r], %d0
+0x89, 0x00, 0x00, 0x05 = st.w [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x05 = st.w [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x09 = st.w [%a0]0, %d0
+0x15, 0x00, 0x00, 0x00 = stlcx 0
+0x49, 0x00, 0x80, 0x09 = stlcx [%a0]0
+0x15, 0x00, 0x00, 0x04 = stucx 0
+0x49, 0x00, 0xc0, 0x09 = stucx [%a0]0
+0x52, 0x00 = sub %d0, %d15, %d0
+0x5a, 0x00 = sub %d15, %d0, %d0
+0xa2, 0x00 = sub %d0, %d0
+0x0b, 0x00, 0x80, 0x00 = sub %d0, %d0, %d0
+0x20, 0x00 = sub.a %sp, 0
+0x01, 0x00, 0x20, 0x00 = sub.a %a0, %a0, %a0
+0x0b, 0x00, 0x80, 0x04 = sub.b %d0, %d0, %d0
+0x6b, 0x00, 0x31, 0x00 = sub.f %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x06 = sub.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x00 = subc %d0, %d0, %d0
+0x62, 0x00 = subs %d0, %d0
+0x0b, 0x00, 0xa0, 0x00 = subs %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x06 = subs.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x06 = subs.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x00 = subs.u %d0, %d0, %d0
+0x0b, 0x00, 0xc0, 0x00 = subx %d0, %d0, %d0
+0x0d, 0x00, 0x00, 0x02 = svlcx
+0x49, 0x00, 0x00, 0x00 = swap.w [%a0+]0, %d0
+0x69, 0x00, 0x00, 0x00 = swap.w [%p0+r], %d0
+0xe5, 0x00, 0x00, 0x00 = swap.w 0, %d0
+0x49, 0x00, 0x00, 0x04 = swap.w [+%a0]0, %d0
+0x69, 0x00, 0x00, 0x04 = swap.w [%p0+c]0, %d0
+0x49, 0x00, 0x00, 0x08 = swap.w [%a0]0, %d0
+0x69, 0x00, 0x00, 0x08 = swap.w [%p0+i], %d0
+0x49, 0x00, 0x80, 0x00 = swapmsk.w [%a0+]0, %e0
+0x69, 0x00, 0x80, 0x00 = swapmsk.w [%p0+r], %e0
+0x49, 0x00, 0x80, 0x04 = swapmsk.w [+%a0]0, %e0
+0x69, 0x00, 0x80, 0x04 = swapmsk.w [%p0+c]0, %e0
+0x49, 0x00, 0x80, 0x08 = swapmsk.w [%a0]0, %e0
+0x69, 0x00, 0x80, 0x08 = swapmsk.w [%p0+i], %e0
+0xad, 0x00, 0x80, 0x00 = syscall 0
+0x75, 0x00, 0x00, 0x00 = tlbdemap %d0
+0x75, 0x00, 0x40, 0x00 = tlbflush.a
+0x75, 0x00, 0x50, 0x00 = tlbflush.b
+0x75, 0x00, 0x00, 0x04 = tlbmap %e0
+0x75, 0x00, 0x80, 0x00 = tlbprobe.a %d0
+0x75, 0x00, 0x90, 0x00 = tlbprobe.i %d0
+0x0d, 0x00, 0x40, 0x05 = trapsv
+0x0d, 0x00, 0x00, 0x05 = trapv
+0x4b, 0x00, 0x80, 0x00 = unpack %e0, %d0
+0x4b, 0x00, 0xc1, 0x00 = updfl %d0
+0x4b, 0x00, 0x61, 0x01 = utof %d0, %d0
+0x0d, 0x00, 0x80, 0x05 = wait
+0x0f, 0x00, 0xd0, 0x00 = xnor %d0, %d0, %d0
+0x8f, 0x00, 0xa0, 0x01 = xnor %d0, %d0, 0
+0x07, 0x00, 0x40, 0x00 = xnor.t %d0, %d0, 0, %d0, 0
+0xc6, 0x00 = xor %d0, %d0
+0x0f, 0x00, 0xc0, 0x00 = xor %d0, %d0, %d0
+0x8f, 0x00, 0x80, 0x01 = xor %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x02 = xor.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x05 = xor.eq %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x03 = xor.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x06 = xor.ge %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x03 = xor.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x06 = xor.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x03 = xor.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x06 = xor.lt %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x03 = xor.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x06 = xor.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x00, 0x03 = xor.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x06 = xor.ne %d0, %d0, 0
+0x07, 0x00, 0x60, 0x00 = xor.t %d0, %d0, 0, %d0, 0
diff --git a/suite/MC/TriCore/tc162.s.cs b/suite/MC/TriCore/tc162.s.cs
new file mode 100644
index 0000000000..8590e2300d
--- /dev/null
+++ b/suite/MC/TriCore/tc162.s.cs
@@ -0,0 +1,843 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None
+0x0b, 0x00, 0xc0, 0x01 = abs %d0, %d0
+0x0b, 0x00, 0xc0, 0x05 = abs.b %d0, %d0
+0x0b, 0x00, 0xc0, 0x07 = abs.h %d0, %d0
+0x0b, 0x00, 0xe0, 0x00 = absdif %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x01 = absdif %d0, %d0, 0
+0x0b, 0x00, 0xe0, 0x04 = absdif.b %d0, %d0, %d0
+0x0b, 0x00, 0xe0, 0x06 = absdif.h %d0, %d0, %d0
+0x0b, 0x00, 0xf0, 0x00 = absdifs %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x01 = absdifs %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x06 = absdifs.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x01 = abss %d0, %d0
+0x0b, 0x00, 0xd0, 0x07 = abss.h %d0, %d0
+0x12, 0x00 = add %d0, %d15, %d0
+0x92, 0x00 = add %d0, %d15, 0
+0x1a, 0x00 = add %d15, %d0, %d0
+0x42, 0x00 = add %d0, %d0
+0x9a, 0x00 = add %d15, %d0, 0
+0xc2, 0x00 = add %d0, 0
+0x0b, 0x00, 0x00, 0x00 = add %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x00 = add %d0, %d0, 0
+0x30, 0x00 = add.a %a0, %a0
+0xb0, 0x00 = add.a %a0, 0
+0x01, 0x00, 0x10, 0x00 = add.a %a0, %a0, %a0
+0x0b, 0x00, 0x00, 0x04 = add.b %d0, %d0, %d0
+0x6b, 0x00, 0x21, 0x00 = add.f %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x06 = add.h %d0, %d0, %d0
+0x0b, 0x00, 0x50, 0x00 = addc %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x00 = addc %d0, %d0, 0
+0x1b, 0x00, 0x00, 0x00 = addi %d0, %d0, 0
+0x9b, 0x00, 0x00, 0x00 = addih %d0, %d0, 0
+0x11, 0x00, 0x00, 0x00 = addih.a %a0, %a0, 0
+0x22, 0x00 = adds %d0, %d0
+0x0b, 0x00, 0x20, 0x00 = adds %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x00 = adds %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x06 = adds.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x06 = adds.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x00 = adds.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x00 = adds.u %d0, %d0, 0
+0x10, 0x00 = addsc.a %a0, %a0, %d15, 0
+0x01, 0x00, 0x00, 0x06 = addsc.a %a0, %a0, %d0, 0
+0x01, 0x00, 0x20, 0x06 = addsc.at %a0, %a0, %d0
+0x0b, 0x00, 0x40, 0x00 = addx %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x00 = addx %d0, %d0, 0
+0x26, 0x00 = and %d0, %d0
+0x16, 0x00 = and %d15, 0
+0x0f, 0x00, 0x80, 0x00 = and %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x01 = and %d0, %d0, 0
+0x47, 0x00, 0x00, 0x00 = and.and.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x60, 0x00 = and.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x00, 0x02 = and.eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x04 = and.eq %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x02 = and.ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x04 = and.ge %d0, %d0, 0
+0x0b, 0x00, 0x50, 0x02 = and.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x04 = and.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x02 = and.lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x04 = and.lt %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x02 = and.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x04 = and.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x02 = and.ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x04 = and.ne %d0, %d0, 0
+0x47, 0x00, 0x40, 0x00 = and.nor.t %d0, %d0, 0, %d0, 0
+0x47, 0x00, 0x20, 0x00 = and.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x00, 0x00 = and.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xe0, 0x00 = andn %d0, %d0, %d0
+0x8f, 0x00, 0xc0, 0x01 = andn %d0, %d0, 0
+0x87, 0x00, 0x60, 0x00 = andn.t %d0, %d0, 0, %d0, 0
+0xe0, 0x00 = bisr 0
+0xad, 0x00, 0x00, 0x00 = bisr 0
+0x4b, 0x00, 0x10, 0x00 = bmerge %d0, %d0, %d0
+0x4b, 0x00, 0x90, 0x00 = bsplit %e0, %d0
+0x89, 0x00, 0x80, 0x03 = cachea.i [%a0+]0
+0xa9, 0x00, 0x80, 0x03 = cachea.i [%p0+r]
+0x89, 0x00, 0x80, 0x07 = cachea.i [+%a0]0
+0xa9, 0x00, 0x80, 0x07 = cachea.i [%p0+c]0
+0x89, 0x00, 0x80, 0x0b = cachea.i [%a0]0
+0x89, 0x00, 0x00, 0x03 = cachea.w [%a0+]0
+0xa9, 0x00, 0x00, 0x03 = cachea.w [%p0+r]
+0x89, 0x00, 0x00, 0x07 = cachea.w [+%a0]0
+0xa9, 0x00, 0x00, 0x07 = cachea.w [%p0+c]0
+0x89, 0x00, 0x00, 0x0b = cachea.w [%a0]0
+0x89, 0x00, 0x40, 0x03 = cachea.wi [%a0+]0
+0xa9, 0x00, 0x40, 0x03 = cachea.wi [%p0+r]
+0x89, 0x00, 0x40, 0x07 = cachea.wi [+%a0]0
+0xa9, 0x00, 0x40, 0x07 = cachea.wi [%p0+c]0
+0x89, 0x00, 0x40, 0x0b = cachea.wi [%a0]0
+0x89, 0x00, 0x80, 0x02 = cachei.i [%a0+]0
+0x89, 0x00, 0x80, 0x06 = cachei.i [+%a0]0
+0x89, 0x00, 0x80, 0x0a = cachei.i [%a0]0
+0x89, 0x00, 0xc0, 0x02 = cachei.w [%a0+]0
+0x89, 0x00, 0xc0, 0x06 = cachei.w [+%a0]0
+0x89, 0x00, 0xc0, 0x0a = cachei.w [%a0]0
+0x89, 0x00, 0xc0, 0x03 = cachei.wi [%a0+]0
+0x89, 0x00, 0xc0, 0x07 = cachei.wi [+%a0]0
+0x89, 0x00, 0xc0, 0x0b = cachei.wi [%a0]0
+0x8a, 0x00 = cadd %d0, %d15, 0
+0x2b, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, %d0
+0xab, 0x00, 0x00, 0x00 = cadd %d0, %d0, %d0, 0
+0xca, 0x00 = caddn %d0, %d15, 0
+0x2b, 0x00, 0x10, 0x00 = caddn %d0, %d0, %d0, %d0
+0xab, 0x00, 0x20, 0x00 = caddn %d0, %d0, %d0, 0
+0x5c, 0x00 = call 0
+0x6d, 0x00, 0x00, 0x00 = call 0
+0xed, 0x00, 0x00, 0x00 = calla 0
+0x2d, 0x00, 0x00, 0x00 = calli %a0
+0x0f, 0x00, 0xc0, 0x01 = clo %d0, %d0
+0x0f, 0x00, 0xd0, 0x07 = clo.h %d0, %d0
+0x0f, 0x00, 0xd0, 0x01 = cls %d0, %d0
+0x0f, 0x00, 0xe0, 0x07 = cls.h %d0, %d0
+0x0f, 0x00, 0xb0, 0x01 = clz %d0, %d0
+0x0f, 0x00, 0xc0, 0x07 = clz.h %d0, %d0
+0x2a, 0x00 = cmov %d0, %d15, %d0
+0xaa, 0x00 = cmov %d0, %d15, 0
+0x6a, 0x00 = cmovn %d0, %d15, %d0
+0xea, 0x00 = cmovn %d0, %d15, 0
+0x4b, 0x00, 0x00, 0x00 = cmp.f %d0, %d0, %d0
+0x49, 0x00, 0xc0, 0x08 = cmpswap.w [%a0]0, %e0
+0x69, 0x00, 0xc0, 0x00 = cmpswap.w [%p0+r], %e0
+0x69, 0x00, 0xc0, 0x04 = cmpswap.w [%p0+c]0, %e0
+0x49, 0x00, 0xc0, 0x00 = cmpswap.w [%a0+]0, %e0
+0x49, 0x00, 0xc0, 0x04 = cmpswap.w [+%a0]0, %e0
+0x4b, 0x00, 0x60, 0x00 = crc32.b %d0, %d0, %d0
+0x4b, 0x00, 0x30, 0x00 = crc32b.w %d0, %d0, %d0
+0x4b, 0x00, 0x70, 0x00 = crc32l.w %d0, %d0, %d0
+0x6b, 0x00, 0x10, 0x00 = crcn %d0, %d0, %d0, %d0
+0x2b, 0x00, 0x20, 0x00 = csub %d0, %d0, %d0, %d0
+0x2b, 0x00, 0x30, 0x00 = csubn %d0, %d0, %d0, %d0
+0x00, 0xa0 = debug
+0x0d, 0x00, 0x00, 0x01 = debug
+0x77, 0x00, 0x00, 0x00 = dextr %d0, %d0, %d0, 0
+0x17, 0x00, 0x80, 0x00 = dextr %d0, %d0, %d0, %d0
+0x0d, 0x00, 0x40, 0x03 = disable
+0x0d, 0x00, 0xc0, 0x03 = disable %d0
+0x4b, 0x00, 0x01, 0x02 = div %e0, %d0, %d0
+0x4b, 0x00, 0x11, 0x02 = div.u %e0, %d0, %d0
+0x4b, 0x00, 0x51, 0x00 = div.f %d0, %d0, %d0
+0x0d, 0x00, 0x80, 0x04 = dsync
+0x6b, 0x00, 0xd0, 0x00 = dvadj %e0, %e0, %d0
+0x4b, 0x00, 0xa0, 0x01 = dvinit %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x05 = dvinit.b %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x04 = dvinit.bu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x03 = dvinit.h %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x02 = dvinit.hu %e0, %d0, %d0
+0x4b, 0x00, 0xa0, 0x00 = dvinit.u %e0, %d0, %d0
+0x6b, 0x00, 0xf0, 0x00 = dvstep %e0, %e0, %d0
+0x6b, 0x00, 0xe0, 0x00 = dvstep.u %e0, %e0, %d0
+0x0d, 0x00, 0x00, 0x03 = enable
+0x3a, 0x00 = eq %d15, %d0, %d0
+0xba, 0x00 = eq %d15, %d0, 0
+0x0b, 0x00, 0x00, 0x01 = eq %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x02 = eq %d0, %d0, 0
+0x01, 0x00, 0x00, 0x04 = eq.a %d0, %a0, %a0
+0x0b, 0x00, 0x00, 0x05 = eq.b %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x07 = eq.h %d0, %d0, %d0
+0x0b, 0x00, 0x00, 0x09 = eq.w %d0, %d0, %d0
+0x0b, 0x00, 0x60, 0x05 = eqany.b %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0a = eqany.b %d0, %d0, 0
+0x0b, 0x00, 0x60, 0x07 = eqany.h %d0, %d0, %d0
+0x8b, 0x00, 0xc0, 0x0e = eqany.h %d0, %d0, 0
+0x01, 0x00, 0x80, 0x04 = eqz.a %d0, %a0
+0x17, 0x00, 0x40, 0x00 = extr %d0, %d0, %e0
+0x37, 0x00, 0x40, 0x00 = extr %d0, %d0, 0, 0
+0x57, 0x00, 0x40, 0x00 = extr %d0, %d0, %d0, 0
+0x17, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %e0
+0x37, 0x00, 0x60, 0x00 = extr.u %d0, %d0, 0, 0
+0x57, 0x00, 0x60, 0x00 = extr.u %d0, %d0, %d0, 0
+0x61, 0x00, 0x00, 0x00 = fcall 0
+0xe1, 0x00, 0x00, 0x00 = fcalla 0
+0x2d, 0x00, 0x10, 0x00 = fcalli %a0
+0x00, 0x70 = fret
+0x0d, 0x00, 0xc0, 0x00 = fret
+0x4b, 0x00, 0x01, 0x01 = ftoi %d0, %d0
+0x4b, 0x00, 0x11, 0x01 = ftoq31 %d0, %d0, %d0
+0x4b, 0x00, 0x21, 0x01 = ftou %d0, %d0
+0x4b, 0x00, 0x31, 0x01 = ftoiz %d0, %d0
+0x4b, 0x00, 0x81, 0x01 = ftoq31z %d0, %d0, %d0
+0x4b, 0x00, 0x71, 0x01 = ftouz %d0, %d0
+0x4b, 0x00, 0x51, 0x02 = ftohp %d0, %d0
+0x0b, 0x00, 0x40, 0x01 = ge %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x02 = ge %d0, %d0, 0
+0x01, 0x00, 0x30, 0x04 = ge.a %d0, %a0, %a0
+0x0b, 0x00, 0x50, 0x01 = ge.u %d0, %d0, %d0
+0x8b, 0x00, 0xa0, 0x02 = ge.u %d0, %d0, 0
+0x4b, 0x00, 0x41, 0x02 = hptof %d0, %d0
+0x37, 0x00, 0x20, 0x00 = imask %e0, %d0, 0, 0
+0x57, 0x00, 0x20, 0x00 = imask %e0, %d0, %d0, 0
+0xb7, 0x00, 0x20, 0x00 = imask %e0, 0, 0, 0
+0xd7, 0x00, 0x20, 0x00 = imask %e0, 0, %d0, 0
+0x67, 0x00, 0x00, 0x00 = ins.t %d0, %d0, 0, %d0, 0
+0x17, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %e0
+0x37, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, 0, 0
+0x57, 0x00, 0x00, 0x00 = insert %d0, %d0, %d0, %d0, 0
+0x97, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %e0
+0xb7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, 0, 0
+0xd7, 0x00, 0x00, 0x00 = insert %d0, %d0, 0, %d0, 0
+0x67, 0x00, 0x20, 0x00 = insn.t %d0, %d0, 0, %d0, 0
+0x0d, 0x00, 0xc0, 0x04 = isync
+0x4b, 0x00, 0x41, 0x01 = itof %d0, %d0
+0x6b, 0x00, 0xa0, 0x00 = ixmax %e0, %e0, %d0
+0x6b, 0x00, 0xb0, 0x00 = ixmax.u %e0, %e0, %d0
+0x6b, 0x00, 0x80, 0x00 = ixmin %e0, %e0, %d0
+0x6b, 0x00, 0x90, 0x00 = ixmin.u %e0, %e0, %d0
+0x3c, 0x00 = j 0
+0x1d, 0x00, 0x00, 0x00 = j 0
+0x9d, 0x00, 0x00, 0x00 = ja 0
+0xbe, 0x00 = jeq %d15, %d0, 0x20
+0x9e, 0x00 = jeq %d15, 0, 0x20
+0x3e, 0x00 = jeq %d15, %d0, 0
+0x1e, 0x00 = jeq %d15, 0, 0
+0x5f, 0x00, 0x00, 0x00 = jeq %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x00 = jeq %d0, 0, 0
+0x7d, 0x00, 0x00, 0x00 = jeq.a %a0, %a0, 0
+0x7f, 0x00, 0x00, 0x00 = jge %d0, %d0, 0
+0xff, 0x00, 0x00, 0x00 = jge %d0, 0, 0
+0x7f, 0x00, 0x00, 0x80 = jge.u %d0, %d0, 0
+0xff, 0x00, 0x00, 0x80 = jge.u %d0, 0, 0
+0xce, 0x00 = jgez %d0, 0
+0x4e, 0x00 = jgtz %d0, 0
+0xdc, 0x00 = ji %a0
+0x2d, 0x00, 0x30, 0x00 = ji %a0
+0x5d, 0x00, 0x00, 0x00 = jl 0
+0xdd, 0x00, 0x00, 0x00 = jla 0
+0x8e, 0x00 = jlez %d0, 0
+0x2d, 0x00, 0x20, 0x00 = jli %a0
+0x3f, 0x00, 0x00, 0x00 = jlt %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x00 = jlt %d0, 0, 0
+0x3f, 0x00, 0x00, 0x80 = jlt.u %d0, %d0, 0
+0xbf, 0x00, 0x00, 0x80 = jlt.u %d0, 0, 0
+0x0e, 0x00 = jltz %d0, 0
+0xfe, 0x00 = jne %d15, %d0, 0x20
+0xde, 0x00 = jne %d15, 0, 0x20
+0x7e, 0x00 = jne %d15, %d0, 0
+0x5e, 0x00 = jne %d15, 0, 0
+0x5f, 0x00, 0x00, 0x80 = jne %d0, %d0, 0
+0xdf, 0x00, 0x00, 0x80 = jne %d0, 0, 0
+0x7d, 0x00, 0x00, 0x80 = jne.a %a0, %a0, 0
+0x1f, 0x00, 0x00, 0x80 = jned %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x80 = jned %d0, 0, 0
+0x1f, 0x00, 0x00, 0x00 = jnei %d0, %d0, 0
+0x9f, 0x00, 0x00, 0x00 = jnei %d0, 0, 0
+0xee, 0x00 = jnz %d15, 0
+0xf6, 0x00 = jnz %d0, 0
+0x7c, 0x00 = jnz.a %a0, 0
+0xbd, 0x00, 0x00, 0x80 = jnz.a %a0, 0
+0xae, 0x00 = jnz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x80 = jnz.t %d0, 0, 0
+0x6e, 0x00 = jz %d15, 0
+0x76, 0x00 = jz %d0, 0
+0xbc, 0x00 = jz.a %a0, 0
+0xbd, 0x00, 0x00, 0x00 = jz.a %a0, 0
+0x2e, 0x00 = jz.t %d15, 0, 0
+0x6f, 0x00, 0x00, 0x00 = jz.t %d0, 0, 0
+0xd8, 0x00 = ld.a %a15, [%sp]0
+0xc8, 0x00 = ld.a %a0, [%a15]0
+0xcc, 0x00 = ld.a %a15, [%a0]0
+0xc4, 0x00 = ld.a %a0, [%a0+]
+0xd4, 0x00 = ld.a %a0, [%a0]
+0x99, 0x00, 0x00, 0x00 = ld.a %a0, [%a0]0
+0x09, 0x00, 0x80, 0x01 = ld.a %a0, [%a0+]0
+0x29, 0x00, 0x80, 0x01 = ld.a %a0, [%p0+r]
+0x09, 0x00, 0x80, 0x05 = ld.a %a0, [+%a0]0
+0x29, 0x00, 0x80, 0x05 = ld.a %a0, [%p0+c]0
+0x85, 0x00, 0x00, 0x08 = ld.a %a0, 0
+0x09, 0x00, 0x80, 0x09 = ld.a %a0, [%a0]0
+0x79, 0x00, 0x00, 0x00 = ld.b %d0, [%a0]0
+0x05, 0x00, 0x00, 0x00 = ld.b %d0, 0
+0x09, 0x00, 0x00, 0x00 = ld.b %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x00 = ld.b %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x04 = ld.b %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x04 = ld.b %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x08 = ld.b %d0, [%a0]0
+0x14, 0x00 = ld.bu %d0, [%a0]
+0x0c, 0x00 = ld.bu %d15, [%a0]0
+0x08, 0x00 = ld.bu %d0, [%a15]0
+0x04, 0x00 = ld.bu %d0, [%a0+]
+0x39, 0x00, 0x00, 0x00 = ld.bu %d0, [%a0]0
+0x09, 0x00, 0x40, 0x00 = ld.bu %d0, [%a0+]0
+0x29, 0x00, 0x40, 0x00 = ld.bu %d0, [%p0+r]
+0x05, 0x00, 0x00, 0x04 = ld.bu %d0, 0
+0x09, 0x00, 0x40, 0x04 = ld.bu %d0, [+%a0]0
+0x29, 0x00, 0x40, 0x04 = ld.bu %d0, [%p0+c]0
+0x09, 0x00, 0x40, 0x08 = ld.bu %d0, [%a0]0
+0x09, 0x00, 0x40, 0x01 = ld.d %e0, [%a0+]0
+0x29, 0x00, 0x40, 0x01 = ld.d %e0, [%p0+r]
+0x85, 0x00, 0x00, 0x04 = ld.d %e0, 0
+0x09, 0x00, 0x40, 0x05 = ld.d %e0, [+%a0]0
+0x29, 0x00, 0x40, 0x05 = ld.d %e0, [%p0+c]0
+0x09, 0x00, 0x40, 0x09 = ld.d %e0, [%a0]0
+0x09, 0x00, 0xc0, 0x01 = ld.da %p0, [%a0+]0
+0x29, 0x00, 0xc0, 0x01 = ld.da %p0, [%p0+r]
+0x09, 0x00, 0xc0, 0x05 = ld.da %p0, [+%a0]0
+0x29, 0x00, 0xc0, 0x05 = ld.da %p0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x09 = ld.da %p0, [%a0]0
+0x85, 0x00, 0x00, 0x0c = ld.da %p0, 0
+0x84, 0x00 = ld.h %d0, [%a0+]
+0x8c, 0x00 = ld.h %d15, [%a0]0
+0x88, 0x00 = ld.h %d0, [%a15]0
+0x94, 0x00 = ld.h %d0, [%a0]
+0xc9, 0x00, 0x00, 0x00 = ld.h %d0, [%a0]0
+0x09, 0x00, 0x80, 0x00 = ld.h %d0, [%a0+]0
+0x29, 0x00, 0x80, 0x00 = ld.h %d0, [%p0+r]
+0x09, 0x00, 0x80, 0x04 = ld.h %d0, [+%a0]0
+0x29, 0x00, 0x80, 0x04 = ld.h %d0, [%p0+c]0
+0x05, 0x00, 0x00, 0x08 = ld.h %d0, 0
+0x09, 0x00, 0x80, 0x08 = ld.h %d0, [%a0]0
+0xb9, 0x00, 0x00, 0x00 = ld.hu %d0, [%a0]0
+0x09, 0x00, 0xc0, 0x00 = ld.hu %d0, [%a0+]0
+0x29, 0x00, 0xc0, 0x00 = ld.hu %d0, [%p0+r]
+0x09, 0x00, 0xc0, 0x04 = ld.hu %d0, [+%a0]0
+0x29, 0x00, 0xc0, 0x04 = ld.hu %d0, [%p0+c]0
+0x09, 0x00, 0xc0, 0x08 = ld.hu %d0, [%a0]0
+0x05, 0x00, 0x00, 0x0c = ld.hu %d0, 0
+0x45, 0x00, 0x00, 0x00 = ld.q %d0, 0
+0x09, 0x00, 0x00, 0x02 = ld.q %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x02 = ld.q %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x06 = ld.q %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x06 = ld.q %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x0a = ld.q %d0, [%a0]0
+0x58, 0x00 = ld.w %d15, [%sp]0
+0x54, 0x00 = ld.w %d0, [%a0]
+0x44, 0x00 = ld.w %d0, [%a0+]
+0x4c, 0x00 = ld.w %d15, [%a0]0
+0x48, 0x00 = ld.w %d0, [%a15]0
+0x19, 0x00, 0x00, 0x00 = ld.w %d0, [%a0]0
+0x85, 0x00, 0x00, 0x00 = ld.w %d0, 0
+0x09, 0x00, 0x00, 0x01 = ld.w %d0, [%a0+]0
+0x29, 0x00, 0x00, 0x01 = ld.w %d0, [%p0+r]
+0x09, 0x00, 0x00, 0x05 = ld.w %d0, [+%a0]0
+0x29, 0x00, 0x00, 0x05 = ld.w %d0, [%p0+c]0
+0x09, 0x00, 0x00, 0x09 = ld.w %d0, [%a0]0
+0x15, 0x00, 0x00, 0x08 = ldlcx 0
+0x49, 0x00, 0x00, 0x09 = ldlcx [%a0]0
+0x49, 0x00, 0x40, 0x00 = ldmst [%a0+]0, %e0
+0x69, 0x00, 0x40, 0x00 = ldmst [%p0+r], %e0
+0xe5, 0x00, 0x00, 0x04 = ldmst 0, %e0
+0x49, 0x00, 0x40, 0x04 = ldmst [+%a0]0, %e0
+0x69, 0x00, 0x40, 0x04 = ldmst [%p0+c]0, %e0
+0x49, 0x00, 0x40, 0x08 = ldmst [%a0]0, %e0
+0x49, 0x00, 0x40, 0x09 = lducx [%a0]0
+0x15, 0x00, 0x00, 0x0c = lducx 0
+0xc5, 0x00, 0x00, 0x00 = lea %a0, 0
+0xd9, 0x00, 0x00, 0x00 = lea %a0, [%a0]0
+0x49, 0x00, 0x00, 0x0a = lea %a0, [%a0]0
+0xc5, 0x00, 0x00, 0x04 = lha %a0, 0
+0xfc, 0x00 = loop %a0, -0x20
+0xfd, 0x00, 0x00, 0x00 = loop %a0, 0
+0xfd, 0x00, 0x00, 0x80 = loopu 0
+0x7a, 0x00 = lt %d15, %d0, %d0
+0xfa, 0x00 = lt %d15, %d0, 0
+0x0b, 0x00, 0x20, 0x01 = lt %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x02 = lt %d0, %d0, 0
+0x01, 0x00, 0x20, 0x04 = lt.a %d0, %a0, %a0
+0x0b, 0x00, 0x20, 0x05 = lt.b %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x05 = lt.bu %d0, %d0, %d0
+0x0b, 0x00, 0x20, 0x07 = lt.h %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x07 = lt.hu %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x01 = lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x02 = lt.u %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x09 = lt.w %d0, %d0, %d0
+0x0b, 0x00, 0x30, 0x09 = lt.wu %d0, %d0, %d0
+0x03, 0x00, 0x0a, 0x00 = madd %d0, %d0, %d0, %d0
+0x13, 0x00, 0x20, 0x00 = madd %d0, %d0, %d0, 0
+0x13, 0x00, 0x60, 0x00 = madd %e0, %e0, %d0, 0
+0x03, 0x00, 0x6a, 0x00 = madd %e0, %e0, %d0, %d0
+0x6b, 0x00, 0x61, 0x00 = madd.f %d0, %d0, %d0, %d0
+0x83, 0x00, 0x60, 0x00 = madd.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x64, 0x00 = madd.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x68, 0x00 = madd.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x6c, 0x00 = madd.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x10, 0x00 = madd.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x00, 0x00 = madd.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x04, 0x00 = madd.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x08, 0x00 = madd.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x14, 0x00 = madd.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0x60, 0x00 = madd.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0x64, 0x00 = madd.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0x6c, 0x00 = madd.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0x70, 0x00 = madd.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0x74, 0x00 = madd.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x40, 0x00 = madd.u %e0, %e0, %d0, 0
+0x03, 0x00, 0x68, 0x00 = madd.u %e0, %e0, %d0, %d0
+0x83, 0x00, 0x70, 0x00 = maddm.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x74, 0x00 = maddm.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0x78, 0x00 = maddm.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0x7c, 0x00 = maddm.h %e0, %e0, %d0, %d0uu, 0
+0x83, 0x00, 0xf0, 0x00 = maddms.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xf4, 0x00 = maddms.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xf8, 0x00 = maddms.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xfc, 0x00 = maddms.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x78, 0x00 = maddr.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0x30, 0x00 = maddr.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0x34, 0x00 = maddr.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0x38, 0x00 = maddr.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0x3c, 0x00 = maddr.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x18, 0x00 = maddr.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x1c, 0x00 = maddr.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xf8, 0x00 = maddrs.h %d0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xb0, 0x00 = maddrs.h %d0, %d0, %d0, %d0ul, 0
+0x83, 0x00, 0xb4, 0x00 = maddrs.h %d0, %d0, %d0, %d0lu, 0
+0x83, 0x00, 0xb8, 0x00 = maddrs.h %d0, %d0, %d0, %d0ll, 0
+0x83, 0x00, 0xbc, 0x00 = maddrs.h %d0, %d0, %d0, %d0uu, 0
+0x43, 0x00, 0x98, 0x00 = maddrs.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x9c, 0x00 = maddrs.q %d0, %d0, %d0l, %d0l, 0
+0x03, 0x00, 0x8a, 0x00 = madds %d0, %d0, %d0, %d0
+0x13, 0x00, 0xa0, 0x00 = madds %d0, %d0, %d0, 0
+0x13, 0x00, 0xe0, 0x00 = madds %e0, %e0, %d0, 0
+0x03, 0x00, 0xea, 0x00 = madds %e0, %e0, %d0, %d0
+0x83, 0x00, 0xe0, 0x00 = madds.h %e0, %e0, %d0, %d0ul, 0
+0x83, 0x00, 0xe4, 0x00 = madds.h %e0, %e0, %d0, %d0lu, 0
+0x83, 0x00, 0xe8, 0x00 = madds.h %e0, %e0, %d0, %d0ll, 0
+0x83, 0x00, 0xec, 0x00 = madds.h %e0, %e0, %d0, %d0uu, 0
+0x43, 0x00, 0x90, 0x00 = madds.q %d0, %d0, %d0u, %d0u, 0
+0x43, 0x00, 0x80, 0x00 = madds.q %d0, %d0, %d0, %d0u, 0
+0x43, 0x00, 0x84, 0x00 = madds.q %d0, %d0, %d0, %d0l, 0
+0x43, 0x00, 0x88, 0x00 = madds.q %d0, %d0, %d0, %d0, 0
+0x43, 0x00, 0x94, 0x00 = madds.q %d0, %d0, %d0l, %d0l, 0
+0x43, 0x00, 0xe0, 0x00 = madds.q %e0, %e0, %d0, %d0u, 0
+0x43, 0x00, 0xe4, 0x00 = madds.q %e0, %e0, %d0, %d0l, 0
+0x43, 0x00, 0xec, 0x00 = madds.q %e0, %e0, %d0, %d0, 0
+0x43, 0x00, 0xf0, 0x00 = madds.q %e0, %e0, %d0u, %d0u, 0
+0x43, 0x00, 0xf4, 0x00 = madds.q %e0, %e0, %d0l, %d0l, 0
+0x13, 0x00, 0x80, 0x00 = madds.u %d0, %d0, %d0, 0
+0x03, 0x00, 0x88, 0x00 = madds.u %d0, %d0, %d0, %d0
+0x13, 0x00, 0xc0, 0x00 = madds.u %e0, %e0, %d0, 0
+0x03, 0x00, 0xe8, 0x00 = madds.u %e0, %e0, %d0, %d0
+0xc3, 0x00, 0x60, 0x00 = maddsu.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x64, 0x00 = maddsu.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x68, 0x00 = maddsu.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x6c, 0x00 = maddsu.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x70, 0x00 = maddsum.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0x74, 0x00 = maddsum.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0x78, 0x00 = maddsum.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0x7c, 0x00 = maddsum.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0xf0, 0x00 = maddsums.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xf4, 0x00 = maddsums.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xf8, 0x00 = maddsums.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xfc, 0x00 = maddsums.h %e0, %e0, %d0, %d0uu, 0
+0xc3, 0x00, 0x30, 0x00 = maddsur.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0x34, 0x00 = maddsur.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0x38, 0x00 = maddsur.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0x3c, 0x00 = maddsur.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xb0, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ul, 0
+0xc3, 0x00, 0xb4, 0x00 = maddsurs.h %d0, %d0, %d0, %d0lu, 0
+0xc3, 0x00, 0xb8, 0x00 = maddsurs.h %d0, %d0, %d0, %d0ll, 0
+0xc3, 0x00, 0xbc, 0x00 = maddsurs.h %d0, %d0, %d0, %d0uu, 0
+0xc3, 0x00, 0xe0, 0x00 = maddsus.h %e0, %e0, %d0, %d0ul, 0
+0xc3, 0x00, 0xe4, 0x00 = maddsus.h %e0, %e0, %d0, %d0lu, 0
+0xc3, 0x00, 0xe8, 0x00 = maddsus.h %e0, %e0, %d0, %d0ll, 0
+0xc3, 0x00, 0xec, 0x00 = maddsus.h %e0, %e0, %d0, %d0uu, 0
+0x0b, 0x00, 0xa0, 0x01 = max %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x03 = max %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x05 = max.b %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x05 = max.bu %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x07 = max.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x07 = max.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x01 = max.u %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x03 = max.u %d0, %d0, 0
+0x4d, 0x00, 0x00, 0x00 = mfcr %d0, 0
+0x0b, 0x00, 0x80, 0x01 = min %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x03 = min %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x05 = min.b %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x05 = min.bu %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x07 = min.h %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x07 = min.hu %d0, %d0, %d0
+0x0b, 0x00, 0x90, 0x01 = min.u %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x03 = min.u %d0, %d0, 0
+0x02, 0x00 = mov %d0, %d0
+0x82, 0x00 = mov %d0, 0
+0xd2, 0x00 = mov %e0, 0
+0xda, 0x00 = mov %d15, 0
+0x3b, 0x00, 0x00, 0x00 = mov %d0, 0
+0x0b, 0x00, 0xf0, 0x01 = mov %d0, %d0
+0xfb, 0x00, 0x00, 0x00 = mov %e0, 0
+0x0b, 0x00, 0x00, 0x08 = mov %e0, %d0
+0x0b, 0x00, 0x10, 0x08 = mov %e0, %d0, %d0
+0xa0, 0x00 = mov.a %a0, 0
+0x60, 0x00 = mov.a %a0, %d0
+0x01, 0x00, 0x30, 0x06 = mov.a %a0, %d0
+0x40, 0x00 = mov.aa %a0, %a0
+0x01, 0x00, 0x00, 0x00 = mov.aa %a0, %a0
+0x80, 0x00 = mov.d %d0, %a0
+0x01, 0x00, 0xc0, 0x04 = mov.d %d0, %a0
+0xbb, 0x00, 0x00, 0x00 = mov.u %d0, 0
+0x7b, 0x00, 0x00, 0x00 = movh %d0, 0
+0x91, 0x00, 0x00, 0x00 = movh.a %a0, 0
+0x23, 0x00, 0x0a, 0x00 = msub %d0, %d0, %d0, %d0
+0x33, 0x00, 0x20, 0x00 = msub %d0, %d0, %d0, 0
+0x33, 0x00, 0x60, 0x00 = msub %e0, %e0, %d0, 0
+0x23, 0x00, 0x6a, 0x00 = msub %e0, %e0, %d0, %d0
+0x6b, 0x00, 0x71, 0x00 = msub.f %d0, %d0, %d0, %d0
+0xa3, 0x00, 0x60, 0x00 = msub.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x64, 0x00 = msub.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x68, 0x00 = msub.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x6c, 0x00 = msub.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x10, 0x00 = msub.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x00, 0x00 = msub.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x04, 0x00 = msub.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x08, 0x00 = msub.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x14, 0x00 = msub.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0x60, 0x00 = msub.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0x64, 0x00 = msub.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0x6c, 0x00 = msub.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0x70, 0x00 = msub.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0x74, 0x00 = msub.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x40, 0x00 = msub.u %e0, %e0, %d0, 0
+0x23, 0x00, 0x68, 0x00 = msub.u %e0, %e0, %d0, %d0
+0xe3, 0x00, 0x60, 0x00 = msubad.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x64, 0x00 = msubad.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x68, 0x00 = msubad.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x6c, 0x00 = msubad.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x70, 0x00 = msubadm.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0x74, 0x00 = msubadm.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0x78, 0x00 = msubadm.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0x7c, 0x00 = msubadm.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0xf0, 0x00 = msubadms.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xf4, 0x00 = msubadms.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xf8, 0x00 = msubadms.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xfc, 0x00 = msubadms.h %e0, %e0, %d0, %d0uu, 0
+0xe3, 0x00, 0x30, 0x00 = msubadr.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0x34, 0x00 = msubadr.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0x38, 0x00 = msubadr.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0x3c, 0x00 = msubadr.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xb0, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ul, 0
+0xe3, 0x00, 0xb4, 0x00 = msubadrs.h %d0, %d0, %d0, %d0lu, 0
+0xe3, 0x00, 0xb8, 0x00 = msubadrs.h %d0, %d0, %d0, %d0ll, 0
+0xe3, 0x00, 0xbc, 0x00 = msubadrs.h %d0, %d0, %d0, %d0uu, 0
+0xe3, 0x00, 0xe0, 0x00 = msubads.h %e0, %e0, %d0, %d0ul, 0
+0xe3, 0x00, 0xe4, 0x00 = msubads.h %e0, %e0, %d0, %d0lu, 0
+0xe3, 0x00, 0xe8, 0x00 = msubads.h %e0, %e0, %d0, %d0ll, 0
+0xe3, 0x00, 0xec, 0x00 = msubads.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0x70, 0x00 = msubm.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x74, 0x00 = msubm.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0x78, 0x00 = msubm.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0x7c, 0x00 = msubm.h %e0, %e0, %d0, %d0uu, 0
+0xa3, 0x00, 0xf0, 0x00 = msubms.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xf4, 0x00 = msubms.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xf8, 0x00 = msubms.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xfc, 0x00 = msubms.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x78, 0x00 = msubr.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0x30, 0x00 = msubr.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0x34, 0x00 = msubr.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0x38, 0x00 = msubr.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0x3c, 0x00 = msubr.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x18, 0x00 = msubr.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x1c, 0x00 = msubr.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xf8, 0x00 = msubrs.h %d0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb0, 0x00 = msubrs.h %d0, %d0, %d0, %d0ul, 0
+0xa3, 0x00, 0xb4, 0x00 = msubrs.h %d0, %d0, %d0, %d0lu, 0
+0xa3, 0x00, 0xb8, 0x00 = msubrs.h %d0, %d0, %d0, %d0ll, 0
+0xa3, 0x00, 0xbc, 0x00 = msubrs.h %d0, %d0, %d0, %d0uu, 0
+0x63, 0x00, 0x98, 0x00 = msubrs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x9c, 0x00 = msubrs.q %d0, %d0, %d0l, %d0l, 0
+0x23, 0x00, 0x8a, 0x00 = msubs %d0, %d0, %d0, %d0
+0x33, 0x00, 0xa0, 0x00 = msubs %d0, %d0, %d0, 0
+0x33, 0x00, 0xe0, 0x00 = msubs %e0, %e0, %d0, 0
+0x23, 0x00, 0xea, 0x00 = msubs %e0, %e0, %d0, %d0
+0xa3, 0x00, 0xe0, 0x00 = msubs.h %e0, %e0, %d0, %d0ul, 0
+0xa3, 0x00, 0xe4, 0x00 = msubs.h %e0, %e0, %d0, %d0lu, 0
+0xa3, 0x00, 0xe8, 0x00 = msubs.h %e0, %e0, %d0, %d0ll, 0
+0xa3, 0x00, 0xec, 0x00 = msubs.h %e0, %e0, %d0, %d0uu, 0
+0x63, 0x00, 0x90, 0x00 = msubs.q %d0, %d0, %d0u, %d0u, 0
+0x63, 0x00, 0x80, 0x00 = msubs.q %d0, %d0, %d0, %d0u, 0
+0x63, 0x00, 0x84, 0x00 = msubs.q %d0, %d0, %d0, %d0l, 0
+0x63, 0x00, 0x88, 0x00 = msubs.q %d0, %d0, %d0, %d0, 0
+0x63, 0x00, 0x94, 0x00 = msubs.q %d0, %d0, %d0l, %d0l, 0
+0x63, 0x00, 0xe0, 0x00 = msubs.q %e0, %e0, %d0, %d0u, 0
+0x63, 0x00, 0xe4, 0x00 = msubs.q %e0, %e0, %d0, %d0l, 0
+0x63, 0x00, 0xec, 0x00 = msubs.q %e0, %e0, %d0, %d0, 0
+0x63, 0x00, 0xf0, 0x00 = msubs.q %e0, %e0, %d0u, %d0u, 0
+0x63, 0x00, 0xf4, 0x00 = msubs.q %e0, %e0, %d0l, %d0l, 0
+0x33, 0x00, 0x80, 0x00 = msubs.u %d0, %d0, %d0, 0
+0x23, 0x00, 0x88, 0x00 = msubs.u %d0, %d0, %d0, %d0
+0x33, 0x00, 0xc0, 0x00 = msubs.u %e0, %e0, %d0, 0
+0x23, 0x00, 0xe8, 0x00 = msubs.u %e0, %e0, %d0, %d0
+0xcd, 0x00, 0x00, 0x00 = mtcr 0, %d0
+0xe2, 0x00 = mul %d0, %d0
+0x53, 0x00, 0x20, 0x00 = mul %d0, %d0, 0
+0x73, 0x00, 0x0a, 0x00 = mul %d0, %d0, %d0
+0x53, 0x00, 0x60, 0x00 = mul %e0, %d0, 0
+0x73, 0x00, 0x6a, 0x00 = mul %e0, %d0, %d0
+0x4b, 0x00, 0x41, 0x00 = mul.f %d0, %d0, %d0
+0xb3, 0x00, 0x60, 0x00 = mul.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x64, 0x00 = mul.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x68, 0x00 = mul.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x6c, 0x00 = mul.h %e0, %d0, %d0uu, 0
+0x93, 0x00, 0x00, 0x00 = mul.q %d0, %d0, %d0u, 0
+0x93, 0x00, 0x04, 0x00 = mul.q %d0, %d0, %d0l, 0
+0x93, 0x00, 0x08, 0x00 = mul.q %d0, %d0, %d0, 0
+0x93, 0x00, 0x10, 0x00 = mul.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x14, 0x00 = mul.q %d0, %d0l, %d0l, 0
+0x93, 0x00, 0x60, 0x00 = mul.q %e0, %d0, %d0u, 0
+0x93, 0x00, 0x64, 0x00 = mul.q %e0, %d0, %d0l, 0
+0x93, 0x00, 0x6c, 0x00 = mul.q %e0, %d0, %d0, 0
+0x53, 0x00, 0x40, 0x00 = mul.u %e0, %d0, 0
+0x73, 0x00, 0x68, 0x00 = mul.u %e0, %d0, %d0
+0xb3, 0x00, 0x70, 0x00 = mulm.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0x74, 0x00 = mulm.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0x78, 0x00 = mulm.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0x7c, 0x00 = mulm.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0xf0, 0x00 = mulms.h %e0, %d0, %d0ul, 0
+0xb3, 0x00, 0xf4, 0x00 = mulms.h %e0, %d0, %d0lu, 0
+0xb3, 0x00, 0xf8, 0x00 = mulms.h %e0, %d0, %d0ll, 0
+0xb3, 0x00, 0xfc, 0x00 = mulms.h %e0, %d0, %d0uu, 0
+0xb3, 0x00, 0x30, 0x00 = mulr.h %d0, %d0, %d0ul, 0
+0xb3, 0x00, 0x34, 0x00 = mulr.h %d0, %d0, %d0lu, 0
+0xb3, 0x00, 0x38, 0x00 = mulr.h %d0, %d0, %d0ll, 0
+0xb3, 0x00, 0x3c, 0x00 = mulr.h %d0, %d0, %d0uu, 0
+0x93, 0x00, 0x18, 0x00 = mulr.q %d0, %d0u, %d0u, 0
+0x93, 0x00, 0x1c, 0x00 = mulr.q %d0, %d0l, %d0l, 0
+0x53, 0x00, 0xa0, 0x00 = muls %d0, %d0, 0
+0x73, 0x00, 0x8a, 0x00 = muls %d0, %d0, %d0
+0x53, 0x00, 0x80, 0x00 = muls.u %d0, %d0, 0
+0x73, 0x00, 0x88, 0x00 = muls.u %d0, %d0, %d0
+0x0f, 0x00, 0x90, 0x00 = nand %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x01 = nand %d0, %d0, 0
+0x07, 0x00, 0x00, 0x00 = nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x10, 0x01 = ne %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x02 = ne %d0, %d0, 0
+0x01, 0x00, 0x10, 0x04 = ne.a %d0, %a0, %a0
+0x01, 0x00, 0x90, 0x04 = nez.a %d0, %a0
+0x00, 0x00 = nop
+0x0d, 0x00, 0x00, 0x00 = nop
+0x0f, 0x00, 0xb0, 0x00 = nor %d0, %d0, %d0
+0x8f, 0x00, 0x60, 0x01 = nor %d0, %d0, 0
+0x87, 0x00, 0x40, 0x00 = nor.t %d0, %d0, 0, %d0, 0
+0xa6, 0x00 = or %d0, %d0
+0x96, 0x00 = or %d15, 0
+0x0f, 0x00, 0xa0, 0x00 = or %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x01 = or %d0, %d0, 0
+0xc7, 0x00, 0x00, 0x00 = or.and.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x60, 0x00 = or.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x02 = or.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x04 = or.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x02 = or.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x05 = or.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x02 = or.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x05 = or.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x02 = or.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x05 = or.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x02 = or.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x05 = or.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x80, 0x02 = or.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x05 = or.ne %d0, %d0, 0
+0xc7, 0x00, 0x40, 0x00 = or.nor.t %d0, %d0, 0, %d0, 0
+0xc7, 0x00, 0x20, 0x00 = or.or.t %d0, %d0, 0, %d0, 0
+0x87, 0x00, 0x20, 0x00 = or.t %d0, %d0, 0, %d0, 0
+0x0f, 0x00, 0xf0, 0x00 = orn %d0, %d0, %d0
+0x8f, 0x00, 0xe0, 0x01 = orn %d0, %d0, 0
+0x07, 0x00, 0x20, 0x00 = orn.t %d0, %d0, 0, %d0, 0
+0x6b, 0x00, 0x00, 0x00 = pack %d0, %e0, %d0
+0x4b, 0x00, 0x20, 0x00 = parity %d0, %d0
+0x4b, 0x00, 0x20, 0x02 = popcnt.w %d0, %d0
+0x4b, 0x00, 0x51, 0x01 = q31tof %d0, %d0, %d0
+0x4b, 0x00, 0x91, 0x01 = qseed.f %d0, %d0
+0x0d, 0x00, 0x80, 0x03 = restore %d0
+0x00, 0x90 = ret
+0x0d, 0x00, 0x80, 0x01 = ret
+0x00, 0x80 = rfe
+0x0d, 0x00, 0xc0, 0x01 = rfe
+0x0d, 0x00, 0x40, 0x01 = rfm
+0x0d, 0x00, 0x40, 0x02 = rslcx
+0x2f, 0x00, 0x00, 0x00 = rstv
+0x32, 0x50 = rsub %d0
+0x8b, 0x00, 0x00, 0x01 = rsub %d0, %d0, 0
+0x8b, 0x00, 0x40, 0x01 = rsubs %d0, %d0, 0
+0x8b, 0x00, 0x60, 0x01 = rsubs.u %d0, %d0, 0
+0x32, 0x00 = sat.b %d0
+0x0b, 0x00, 0xe0, 0x05 = sat.b %d0, %d0
+0x32, 0x10 = sat.bu %d0
+0x0b, 0x00, 0xf0, 0x05 = sat.bu %d0, %d0
+0x32, 0x20 = sat.h %d0
+0x0b, 0x00, 0xe0, 0x07 = sat.h %d0, %d0
+0x32, 0x30 = sat.hu %d0
+0x0b, 0x00, 0xf0, 0x07 = sat.hu %d0, %d0
+0x2b, 0x00, 0x40, 0x00 = sel %d0, %d0, %d0, %d0
+0xab, 0x00, 0x80, 0x00 = sel %d0, %d0, %d0, 0
+0x2b, 0x00, 0x50, 0x00 = seln %d0, %d0, %d0, %d0
+0xab, 0x00, 0xa0, 0x00 = seln %d0, %d0, %d0, 0
+0x06, 0x00 = sh %d0, 0
+0x0f, 0x00, 0x00, 0x00 = sh %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x00 = sh %d0, %d0, 0
+0x27, 0x00, 0x00, 0x00 = sh.and.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x60, 0x00 = sh.andn.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x70, 0x03 = sh.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x06 = sh.eq %d0, %d0, 0
+0x0b, 0x00, 0xb0, 0x03 = sh.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x07 = sh.ge %d0, %d0, 0
+0x0b, 0x00, 0xc0, 0x03 = sh.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x07 = sh.ge.u %d0, %d0, 0
+0x0f, 0x00, 0x00, 0x04 = sh.h %d0, %d0, %d0
+0x8f, 0x00, 0x00, 0x08 = sh.h %d0, %d0, 0
+0x0b, 0x00, 0x90, 0x03 = sh.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x07 = sh.lt %d0, %d0, 0
+0x0b, 0x00, 0xa0, 0x03 = sh.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x07 = sh.lt.u %d0, %d0, 0
+0xa7, 0x00, 0x00, 0x00 = sh.nand.t %d0, %d0, 0, %d0, 0
+0x0b, 0x00, 0x80, 0x03 = sh.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x07 = sh.ne %d0, %d0, 0
+0x27, 0x00, 0x40, 0x00 = sh.nor.t %d0, %d0, 0, %d0, 0
+0x27, 0x00, 0x20, 0x00 = sh.or.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x20, 0x00 = sh.orn.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x40, 0x00 = sh.xnor.t %d0, %d0, 0, %d0, 0
+0xa7, 0x00, 0x60, 0x00 = sh.xor.t %d0, %d0, 0, %d0, 0
+0x86, 0x00 = sha %d0, 0
+0x0f, 0x00, 0x10, 0x00 = sha %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x00 = sha %d0, %d0, 0
+0x0f, 0x00, 0x10, 0x04 = sha.h %d0, %d0, %d0
+0x8f, 0x00, 0x20, 0x08 = sha.h %d0, %d0, 0
+0x0f, 0x00, 0x20, 0x00 = shas %d0, %d0, %d0
+0x8f, 0x00, 0x40, 0x00 = shas %d0, %d0, 0
+0x8f, 0x00, 0xe0, 0x00 = shuffle %d0, %d0, 0
+0xf8, 0x00 = st.a [%sp]0, %a15
+0xec, 0x00 = st.a [%a0]0, %a15
+0xe8, 0x00 = st.a [%a15]0, %a0
+0xe4, 0x00 = st.a [%a0+], %a0
+0xf4, 0x00 = st.a [%a0], %a0
+0xb5, 0x00, 0x00, 0x00 = st.a [%a0]0, %a0
+0x89, 0x00, 0x80, 0x01 = st.a [%a0+]0, %a0
+0xa9, 0x00, 0x80, 0x01 = st.a [%p0+r], %a0
+0x89, 0x00, 0x80, 0x05 = st.a [+%a0]0, %a0
+0xa9, 0x00, 0x80, 0x05 = st.a [%p0+c]0, %a0
+0xa5, 0x00, 0x00, 0x08 = st.a 0, %a0
+0x89, 0x00, 0x80, 0x09 = st.a [%a0]0, %a0
+0x34, 0x00 = st.b [%a0], %d0
+0x28, 0x00 = st.b [%a15]0, %d0
+0x2c, 0x00 = st.b [%a0]0, %d15
+0x24, 0x00 = st.b [%a0+], %d0
+0xe9, 0x00, 0x00, 0x00 = st.b [%a0]0, %d0
+0x25, 0x00, 0x00, 0x00 = st.b 0, %d0
+0x89, 0x00, 0x00, 0x00 = st.b [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x00 = st.b [%p0+r], %d0
+0x89, 0x00, 0x00, 0x04 = st.b [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x04 = st.b [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x08 = st.b [%a0]0, %d0
+0x89, 0x00, 0x40, 0x01 = st.d [%a0+]0, %e0
+0xa9, 0x00, 0x40, 0x01 = st.d [%p0+r], %e0
+0xa5, 0x00, 0x00, 0x04 = st.d 0, %e0
+0x89, 0x00, 0x40, 0x05 = st.d [+%a0]0, %e0
+0xa9, 0x00, 0x40, 0x05 = st.d [%p0+c]0, %e0
+0x89, 0x00, 0x40, 0x09 = st.d [%a0]0, %e0
+0x89, 0x00, 0xc0, 0x01 = st.da [%a0+]0, %p0
+0xa9, 0x00, 0xc0, 0x01 = st.da [%p0+r], %p0
+0x89, 0x00, 0xc0, 0x05 = st.da [+%a0]0, %p0
+0xa9, 0x00, 0xc0, 0x05 = st.da [%p0+c]0, %p0
+0x89, 0x00, 0xc0, 0x09 = st.da [%a0]0, %p0
+0xa5, 0x00, 0x00, 0x0c = st.da 0, %p0
+0xa4, 0x00 = st.h [%a0+], %d0
+0xa8, 0x00 = st.h [%a15]0, %d0
+0xac, 0x00 = st.h [%a0]0, %d15
+0xb4, 0x00 = st.h [%a0], %d0
+0xf9, 0x00, 0x00, 0x00 = st.h [%a0]0, %d0
+0x89, 0x00, 0x80, 0x00 = st.h [%a0+]0, %d0
+0xa9, 0x00, 0x80, 0x00 = st.h [%p0+r], %d0
+0x89, 0x00, 0x80, 0x04 = st.h [+%a0]0, %d0
+0xa9, 0x00, 0x80, 0x04 = st.h [%p0+c]0, %d0
+0x25, 0x00, 0x00, 0x08 = st.h 0, %d0
+0x89, 0x00, 0x80, 0x08 = st.h [%a0]0, %d0
+0x65, 0x00, 0x00, 0x00 = st.q 0, %d0
+0x89, 0x00, 0x00, 0x02 = st.q [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x02 = st.q [%p0+r], %d0
+0x89, 0x00, 0x00, 0x06 = st.q [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x06 = st.q [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x0a = st.q [%a0]0, %d0
+0xd5, 0x00, 0x00, 0x00 = st.t 0, 0, 0
+0x78, 0x00 = st.w [%sp]0, %d15
+0x74, 0x00 = st.w [%a0], %d0
+0x64, 0x00 = st.w [%a0+], %d0
+0x68, 0x00 = st.w [%a15]0, %d0
+0x6c, 0x00 = st.w [%a0]0, %d15
+0x59, 0x00, 0x00, 0x00 = st.w [%a0]0, %d0
+0xa5, 0x00, 0x00, 0x00 = st.w 0, %d0
+0x89, 0x00, 0x00, 0x01 = st.w [%a0+]0, %d0
+0xa9, 0x00, 0x00, 0x01 = st.w [%p0+r], %d0
+0x89, 0x00, 0x00, 0x05 = st.w [+%a0]0, %d0
+0xa9, 0x00, 0x00, 0x05 = st.w [%p0+c]0, %d0
+0x89, 0x00, 0x00, 0x09 = st.w [%a0]0, %d0
+0x15, 0x00, 0x00, 0x00 = stlcx 0
+0x49, 0x00, 0x80, 0x09 = stlcx [%a0]0
+0x15, 0x00, 0x00, 0x04 = stucx 0
+0x49, 0x00, 0xc0, 0x09 = stucx [%a0]0
+0x52, 0x00 = sub %d0, %d15, %d0
+0x5a, 0x00 = sub %d15, %d0, %d0
+0xa2, 0x00 = sub %d0, %d0
+0x0b, 0x00, 0x80, 0x00 = sub %d0, %d0, %d0
+0x20, 0x00 = sub.a %sp, 0
+0x01, 0x00, 0x20, 0x00 = sub.a %a0, %a0, %a0
+0x0b, 0x00, 0x80, 0x04 = sub.b %d0, %d0, %d0
+0x6b, 0x00, 0x31, 0x00 = sub.f %d0, %d0, %d0
+0x0b, 0x00, 0x80, 0x06 = sub.h %d0, %d0, %d0
+0x0b, 0x00, 0xd0, 0x00 = subc %d0, %d0, %d0
+0x62, 0x00 = subs %d0, %d0
+0x0b, 0x00, 0xa0, 0x00 = subs %d0, %d0, %d0
+0x0b, 0x00, 0xa0, 0x06 = subs.h %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x06 = subs.hu %d0, %d0, %d0
+0x0b, 0x00, 0xb0, 0x00 = subs.u %d0, %d0, %d0
+0x0b, 0x00, 0xc0, 0x00 = subx %d0, %d0, %d0
+0x0d, 0x00, 0x00, 0x02 = svlcx
+0x49, 0x00, 0x00, 0x00 = swap.w [%a0+]0, %d0
+0x69, 0x00, 0x00, 0x00 = swap.w [%p0+r], %d0
+0xe5, 0x00, 0x00, 0x00 = swap.w 0, %d0
+0x49, 0x00, 0x00, 0x04 = swap.w [+%a0]0, %d0
+0x69, 0x00, 0x00, 0x04 = swap.w [%p0+c]0, %d0
+0x49, 0x00, 0x00, 0x08 = swap.w [%a0]0, %d0
+0x69, 0x00, 0x00, 0x08 = swap.w [%p0+i], %d0
+0x49, 0x00, 0x80, 0x00 = swapmsk.w [%a0+]0, %e0
+0x69, 0x00, 0x80, 0x00 = swapmsk.w [%p0+r], %e0
+0x49, 0x00, 0x80, 0x04 = swapmsk.w [+%a0]0, %e0
+0x69, 0x00, 0x80, 0x04 = swapmsk.w [%p0+c]0, %e0
+0x49, 0x00, 0x80, 0x08 = swapmsk.w [%a0]0, %e0
+0x69, 0x00, 0x80, 0x08 = swapmsk.w [%p0+i], %e0
+0xad, 0x00, 0x80, 0x00 = syscall 0
+0x75, 0x00, 0x00, 0x00 = tlbdemap %d0
+0x75, 0x00, 0x40, 0x00 = tlbflush.a
+0x75, 0x00, 0x50, 0x00 = tlbflush.b
+0x75, 0x00, 0x00, 0x04 = tlbmap %e0
+0x75, 0x00, 0x80, 0x00 = tlbprobe.a %d0
+0x75, 0x00, 0x90, 0x00 = tlbprobe.i %d0
+0x0d, 0x00, 0x40, 0x05 = trapsv
+0x0d, 0x00, 0x00, 0x05 = trapv
+0x4b, 0x00, 0x80, 0x00 = unpack %e0, %d0
+0x4b, 0x00, 0xc1, 0x00 = updfl %d0
+0x4b, 0x00, 0x61, 0x01 = utof %d0, %d0
+0x0d, 0x00, 0x80, 0x05 = wait
+0x0f, 0x00, 0xd0, 0x00 = xnor %d0, %d0, %d0
+0x8f, 0x00, 0xa0, 0x01 = xnor %d0, %d0, 0
+0x07, 0x00, 0x40, 0x00 = xnor.t %d0, %d0, 0, %d0, 0
+0xc6, 0x00 = xor %d0, %d0
+0x0f, 0x00, 0xc0, 0x00 = xor %d0, %d0, %d0
+0x8f, 0x00, 0x80, 0x01 = xor %d0, %d0, 0
+0x0b, 0x00, 0xf0, 0x02 = xor.eq %d0, %d0, %d0
+0x8b, 0x00, 0xe0, 0x05 = xor.eq %d0, %d0, 0
+0x0b, 0x00, 0x30, 0x03 = xor.ge %d0, %d0, %d0
+0x8b, 0x00, 0x60, 0x06 = xor.ge %d0, %d0, 0
+0x0b, 0x00, 0x40, 0x03 = xor.ge.u %d0, %d0, %d0
+0x8b, 0x00, 0x80, 0x06 = xor.ge.u %d0, %d0, 0
+0x0b, 0x00, 0x10, 0x03 = xor.lt %d0, %d0, %d0
+0x8b, 0x00, 0x20, 0x06 = xor.lt %d0, %d0, 0
+0x0b, 0x00, 0x20, 0x03 = xor.lt.u %d0, %d0, %d0
+0x8b, 0x00, 0x40, 0x06 = xor.lt.u %d0, %d0, 0
+0x0b, 0x00, 0x00, 0x03 = xor.ne %d0, %d0, %d0
+0x8b, 0x00, 0x00, 0x06 = xor.ne %d0, %d0, 0
+0x07, 0x00, 0x60, 0x00 = xor.t %d0, %d0, 0, %d0, 0
diff --git a/suite/capstone_get_setup.c b/suite/capstone_get_setup.c
index 08f96c6b4a..203e7cf837 100644
--- a/suite/capstone_get_setup.c
+++ b/suite/capstone_get_setup.c
@@ -70,6 +70,9 @@ int main()
 	if (cs_support(CS_SUPPORT_X86_REDUCE)) {
 		printf("x86_reduce=1 ");
 	}
+	if (cs_support(CS_ARCH_TRICORE)) {
+		printf("tricore=1 ");
+	}
 	printf("\n");
 
 	return 0;
diff --git a/suite/cstest/include/factory.h b/suite/cstest/include/factory.h
index 7df6c7838e..e2a1c4c6d7 100644
--- a/suite/cstest/include/factory.h
+++ b/suite/cstest/include/factory.h
@@ -23,5 +23,6 @@ char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins);
 char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins);
 char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins);
 char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins);
+char *get_detail_tricore(csh *handle, cs_mode mode, cs_insn *ins);
 
 #endif /* FACTORY_H */
diff --git a/suite/cstest/src/capstone_test.c b/suite/cstest/src/capstone_test.c
index a534e49b34..779ab251d6 100644
--- a/suite/cstest/src/capstone_test.c
+++ b/suite/cstest/src/capstone_test.c
@@ -181,6 +181,9 @@ int set_function(int arch)
 		case CS_ARCH_RISCV:
 			function = get_detail_riscv;
 			break;
+		case CS_ARCH_TRICORE:
+			function = get_detail_tricore;
+			break;
 		default:
 			return -1;
 	}
diff --git a/suite/cstest/src/main.c b/suite/cstest/src/main.c
index 88e1b3285a..67802d7d0c 100644
--- a/suite/cstest/src/main.c
+++ b/suite/cstest/src/main.c
@@ -20,6 +20,7 @@ static single_dict arches[] = {
 	{"CS_ARCH_M68K", CS_ARCH_M68K},
 	{"CS_ARCH_BPF", CS_ARCH_BPF},
 	{"CS_ARCH_RISCV", CS_ARCH_RISCV},
+	{"CS_ARCH_TRICORE", CS_ARCH_TRICORE},
 };
 
  static single_dict modes[] = {
@@ -61,6 +62,13 @@ static single_dict arches[] = {
 	{"CS_MODE_BPF_EXTENDED", CS_MODE_BPF_EXTENDED},
 	{"CS_MODE_RISCV32", CS_MODE_RISCV32},
 	{"CS_MODE_RISCV64", CS_MODE_RISCV64},
+	{"CS_MODE_TRICORE_110", CS_MODE_TRICORE_110},
+	{"CS_MODE_TRICORE_120", CS_MODE_TRICORE_120},
+	{"CS_MODE_TRICORE_130", CS_MODE_TRICORE_130},
+	{"CS_MODE_TRICORE_131", CS_MODE_TRICORE_131},
+	{"CS_MODE_TRICORE_160", CS_MODE_TRICORE_160},
+	{"CS_MODE_TRICORE_161", CS_MODE_TRICORE_161},
+	{"CS_MODE_TRICORE_162", CS_MODE_TRICORE_162},
 };
 
  static double_dict options[] = {
@@ -107,6 +115,13 @@ static single_dict arches[] = {
 	{"CS_MODE_M680X_HCS08", CS_OPT_MODE, CS_MODE_M680X_HCS08},
 	{"CS_MODE_RISCV32", CS_OPT_MODE, CS_MODE_RISCV32},
 	{"CS_MODE_RISCV64", CS_OPT_MODE, CS_MODE_RISCV64},
+	{"CS_MODE_TRICORE_110", CS_OPT_MODE, CS_MODE_TRICORE_110},
+	{"CS_MODE_TRICORE_120", CS_OPT_MODE, CS_MODE_TRICORE_120},
+	{"CS_MODE_TRICORE_130", CS_OPT_MODE, CS_MODE_TRICORE_130},
+	{"CS_MODE_TRICORE_131", CS_OPT_MODE, CS_MODE_TRICORE_131},
+	{"CS_MODE_TRICORE_160", CS_OPT_MODE, CS_MODE_TRICORE_160},
+	{"CS_MODE_TRICORE_161", CS_OPT_MODE, CS_MODE_TRICORE_161},
+	{"CS_MODE_TRICORE_162", CS_OPT_MODE, CS_MODE_TRICORE_162},
 	{"CS_OPT_UNSIGNED", CS_OPT_UNSIGNED, CS_OPT_ON},
 };
 
diff --git a/suite/cstest/src/tricore_detail.c b/suite/cstest/src/tricore_detail.c
new file mode 100644
index 0000000000..462d64aeaa
--- /dev/null
+++ b/suite/cstest/src/tricore_detail.c
@@ -0,0 +1,81 @@
+//
+// Created by aya on 3/24/23.
+//
+
+#include "factory.h"
+
+char *get_detail_tricore(csh *p_handle, cs_mode mode, cs_insn *ins)
+{
+	cs_tricore *tricore;
+	int i;
+	cs_regs regs_read, regs_write;
+	uint8_t regs_read_count, regs_write_count;
+
+	char *result;
+	result = (char *)malloc(sizeof(char));
+	result[0] = '\0';
+
+	if (ins->detail == NULL)
+		return result;
+
+	csh handle = *p_handle;
+
+	tricore = &(ins->detail->tricore);
+
+	if (tricore->op_count)
+		add_str(&result, "\top_count: %u\n", tricore->op_count);
+
+	for (i = 0; i < tricore->op_count; i++) {
+		cs_tricore_op *op = &(tricore->operands[i]);
+		switch ((int)op->type) {
+		default:
+			break;
+		case TRICORE_OP_REG:
+			add_str(&result, "\t\toperands[%u].type: REG = %s\n", i,
+				cs_reg_name(handle, op->reg));
+			break;
+		case TRICORE_OP_IMM:
+			add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n",
+				i, op->imm);
+			break;
+		case TRICORE_OP_MEM:
+			add_str(&result, "\t\toperands[%u].type: MEM\n", i);
+			if (op->mem.base != TRICORE_REG_INVALID)
+				add_str(&result,
+					"\t\t\toperands[%u].mem.base: REG = %s\n",
+					i, cs_reg_name(handle, op->mem.base));
+			if (op->mem.disp != 0)
+				add_str(&result,
+					"\t\t\toperands[%u].mem.disp: 0x%x\n",
+					i, op->mem.disp);
+			break;
+		}
+
+		// Print out all registers accessed by this instruction (either implicit or
+		// explicit)
+		if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
+				    regs_write, &regs_write_count)) {
+			if (regs_read_count) {
+				add_str(&result, "\tRegisters read:");
+				for (i = 0; i < regs_read_count; i++) {
+					add_str(&result, " %s",
+						cs_reg_name(handle,
+							    regs_read[i]));
+				}
+				add_str(&result, "\n");
+			}
+
+			if (regs_write_count) {
+				add_str(&result, "\tRegisters modified:");
+				for (i = 0; i < regs_write_count; i++) {
+					add_str(&result, " %s",
+						cs_reg_name(handle,
+							    regs_write[i]));
+				}
+				add_str(&result, "\n");
+			}
+		}
+	}
+
+	return result;
+}
diff --git a/suite/fuzz/platform.c b/suite/fuzz/platform.c
index d70cdfef11..95ada310cd 100644
--- a/suite/fuzz/platform.c
+++ b/suite/fuzz/platform.c
@@ -1,365 +1,404 @@
 #include "platform.h"
 
 struct platform platforms[] = {
-    {
-        // item 0
-        CS_ARCH_X86,
-        CS_MODE_32,
-        "X86 32 (Intel syntax)",
-        "x32"
-    },
-    {
-        // item 1
-        CS_ARCH_X86,
-        CS_MODE_64,
-        "X86 64 (Intel syntax)",
-        "x64"
-    },
-    {
-        // item 2
-        CS_ARCH_ARM,
-        CS_MODE_ARM,
-        "ARM",
-        "arm"
-    },
-    {
-        // item 3
-        CS_ARCH_ARM,
-        CS_MODE_THUMB,
-        "THUMB",
-        "thumb"
-    },
-    {
-        // item 4
-        CS_ARCH_ARM,
-        (cs_mode)(CS_MODE_ARM + CS_MODE_V8),
-        "Arm-V8",
-        "armv8"
-    },
-    {
-        // item 5
-        CS_ARCH_ARM,
-        (cs_mode)(CS_MODE_THUMB+CS_MODE_V8),
-        "THUMB+V8",
-        "thumbv8"
-    },
-    {
-        // item 6
-        CS_ARCH_ARM,
-        (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
-        "Thumb-MClass",
-        "cortexm"
-    },
-    {
-        // item 7
-        CS_ARCH_ARM64,
-        (cs_mode)0,
-        "ARM-64",
-        "arm64"
-    },
-    {
-        // item 8
-        CS_ARCH_MIPS,
-        (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
-        "MIPS-32 (Big-endian)",
-        "mipsbe"
-    },
-    {
-        // item 9
-        CS_ARCH_MIPS,
-        (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO),
-        "MIPS-32 (micro)",
-        "mipsmicro"
-    },
-    {
-        //item 10
-        CS_ARCH_MIPS,
-        CS_MODE_MIPS64,
-        "MIPS-64-EL (Little-endian)",
-        "mips64"
-    },
-    {
-        //item 11
-        CS_ARCH_MIPS,
-        CS_MODE_MIPS32,
-        "MIPS-32-EL (Little-endian)",
-        "mips"
-    },
-    {
-        //item 12
-        CS_ARCH_MIPS,
-        (cs_mode)(CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN),
-        "MIPS-64 (Big-endian)",
-        "mips64be"
-    },
-    {
-        //item 13
-        CS_ARCH_MIPS,
-        (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
-        "MIPS-32 | Micro (Big-endian)",
-        "mipsbemicro"
-    },
-    {
-        //item 14
-        CS_ARCH_PPC,
-        CS_MODE_64 | CS_MODE_BIG_ENDIAN,
-        "PPC-64",
-        "ppc64be"
-    },
-    {
-        //item 15
-        CS_ARCH_SPARC,
-        CS_MODE_BIG_ENDIAN,
-        "Sparc",
-        "sparc"
-    },
-    {
-        //item 16
-        CS_ARCH_SPARC,
-        (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
-        "SparcV9",
-        "sparcv9"
-    },
-    {
-        //item 17
-        CS_ARCH_SYSZ,
-        (cs_mode)0,
-        "SystemZ",
-        "systemz"
-    },
-    {
-        //item 18
-        CS_ARCH_XCORE,
-        (cs_mode)0,
-        "XCore",
-        "xcore"
-    },
-    {
-        //item 19
-        CS_ARCH_MIPS,
-        (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
-        "MIPS-32R6 (Big-endian)",
-        "mipsbe32r6"
-    },
-    {
-        //item 20
-        CS_ARCH_MIPS,
-        (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
-        "MIPS-32R6 (Micro+Big-endian)",
-        "mipsbe32r6micro"
-    },
-    {
-        //item 21
-        CS_ARCH_MIPS,
-        CS_MODE_MIPS32R6,
-        "MIPS-32R6 (Little-endian)",
-        "mips32r6"
-    },
-    {
-        //item 22
-        CS_ARCH_MIPS,
-        (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO),
-        "MIPS-32R6 (Micro+Little-endian)",
-        "mips32r6micro"
-    },
-    {
-        //item 23
-        CS_ARCH_M68K,
-        (cs_mode)0,
-        "M68K",
-        "m68k"
-    },
-    {
-        //item 24
-        CS_ARCH_M680X,
-        (cs_mode)CS_MODE_M680X_6809,
-        "M680X_M6809",
-        "m6809"
-    },
-    {
-        //item 25
-        CS_ARCH_EVM,
-        (cs_mode)0,
-        "EVM",
-        "evm"
-    },
-    {
-        //item 26
-        CS_ARCH_MOS65XX,
-        (cs_mode)0,
-        "MOS65XX",
-        "mos65xx"
-    },
-    {
-        //item 27
-        CS_ARCH_TMS320C64X,
-        CS_MODE_BIG_ENDIAN,
-        "tms320c64x",
-        "tms320c64x"
-    },
-    {
-        //item 28
-        CS_ARCH_WASM,
-        (cs_mode)0,
-        "WASM",
-        "wasm"
-    },
-    {
-        //item 29
-        CS_ARCH_BPF,
-        CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC,
-        "cBPF",
-        "bpf"
-    },
-    {
-        //item 30
-        CS_ARCH_BPF,
-        CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
-        "eBPF",
-        "ebpf"
-    },
-    {
-        //item 31
-        CS_ARCH_BPF,
-        CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC,
-        "cBPF",
-        "bpfbe"
-    },
-    {
-        //item 32
-        CS_ARCH_BPF,
-        CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED,
-        "eBPF",
-        "ebpfbe"
-    },
-    {
-        // item 33
-        CS_ARCH_X86,
-        CS_MODE_16,
-        "X86 16 (Intel syntax)",
-        "x16"
-    },
-    {
-        // item 34
-        CS_ARCH_M68K,
-        CS_MODE_M68K_040,
-        "M68K mode 40",
-        "m68k40"
-    },
-    {
-        //item 35
-        CS_ARCH_M680X,
-        (cs_mode)CS_MODE_M680X_6800,
-        "M680X_M6800",
-        "m6800"
-    },
-    {
-        //item 36
-        CS_ARCH_M680X,
-        (cs_mode)CS_MODE_M680X_6801,
-        "M680X_M6801",
-        "m6801"
-    },
-    {
-        //item 37
-        CS_ARCH_M680X,
-        (cs_mode)CS_MODE_M680X_6805,
-        "M680X_M6805",
-        "m6805"
-    },
-    {
-        //item 38
-        CS_ARCH_M680X,
-        (cs_mode)CS_MODE_M680X_6808,
-        "M680X_M6808",
-        "m6808"
-    },
-    {
-        //item 39
-        CS_ARCH_M680X,
-        (cs_mode)CS_MODE_M680X_6811,
-        "M680X_M6811",
-        "m6811"
-    },
-    {
-        //item 40
-        CS_ARCH_M680X,
-        (cs_mode)CS_MODE_M680X_CPU12,
-        "M680X_cpu12",
-        "cpu12"
-    },
-    {
-        //item 41
-        CS_ARCH_M680X,
-        (cs_mode)CS_MODE_M680X_6301,
-        "M680X_M6808",
-        "hd6301"
-    },
-    {
-        //item 42
-        CS_ARCH_M680X,
-        (cs_mode)CS_MODE_M680X_6309,
-        "M680X_M6808",
-        "hd6309"
-    },
-    {
-        //item 43
-        CS_ARCH_M680X,
-        (cs_mode)CS_MODE_M680X_HCS08,
-        "M680X_M6808",
-        "hcs08"
-    },
-    {
-        //item 44
-        CS_ARCH_RISCV,
-        CS_MODE_RISCV32,
-        "RISCV",
-        "riscv32"
-    },
-    {
-        //item 45
-        CS_ARCH_RISCV,
-        CS_MODE_RISCV64,
-        "RISCV",
-        "riscv64"
-    },
-    {
-        //item 46
-        CS_ARCH_PPC,
-        CS_MODE_64 | CS_MODE_BIG_ENDIAN | CS_MODE_QPX,
-        "ppc+qpx",
-        "ppc64beqpx"
-    },
+		{
+				// item 0
+				CS_ARCH_X86,
+				CS_MODE_32,
+				"X86 32 (Intel syntax)",
+				"x32"
+		},
+		{
+				// item 1
+				CS_ARCH_X86,
+				CS_MODE_64,
+				"X86 64 (Intel syntax)",
+				"x64"
+		},
+		{
+				// item 2
+				CS_ARCH_ARM,
+				CS_MODE_ARM,
+				"ARM",
+				"arm"
+		},
+		{
+				// item 3
+				CS_ARCH_ARM,
+				CS_MODE_THUMB,
+				"THUMB",
+				"thumb"
+		},
+		{
+				// item 4
+				CS_ARCH_ARM,
+				(cs_mode) (CS_MODE_ARM + CS_MODE_V8),
+				"Arm-V8",
+				"armv8"
+		},
+		{
+				// item 5
+				CS_ARCH_ARM,
+				(cs_mode) (CS_MODE_THUMB + CS_MODE_V8),
+				"THUMB+V8",
+				"thumbv8"
+		},
+		{
+				// item 6
+				CS_ARCH_ARM,
+				(cs_mode) (CS_MODE_THUMB + CS_MODE_MCLASS),
+				"Thumb-MClass",
+				"cortexm"
+		},
+		{
+				// item 7
+				CS_ARCH_ARM64,
+				(cs_mode) 0,
+				"ARM-64",
+				"arm64"
+		},
+		{
+				// item 8
+				CS_ARCH_MIPS,
+				(cs_mode) (CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
+				"MIPS-32 (Big-endian)",
+				"mipsbe"
+		},
+		{
+				// item 9
+				CS_ARCH_MIPS,
+				(cs_mode) (CS_MODE_MIPS32 + CS_MODE_MICRO),
+				"MIPS-32 (micro)",
+				"mipsmicro"
+		},
+		{
+				//item 10
+				CS_ARCH_MIPS,
+				CS_MODE_MIPS64,
+				"MIPS-64-EL (Little-endian)",
+				"mips64"
+		},
+		{
+				//item 11
+				CS_ARCH_MIPS,
+				CS_MODE_MIPS32,
+				"MIPS-32-EL (Little-endian)",
+				"mips"
+		},
+		{
+				//item 12
+				CS_ARCH_MIPS,
+				(cs_mode) (CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN),
+				"MIPS-64 (Big-endian)",
+				"mips64be"
+		},
+		{
+				//item 13
+				CS_ARCH_MIPS,
+				(cs_mode) (CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
+				"MIPS-32 | Micro (Big-endian)",
+				"mipsbemicro"
+		},
+		{
+				//item 14
+				CS_ARCH_PPC,
+				CS_MODE_64 | CS_MODE_BIG_ENDIAN,
+				"PPC-64",
+				"ppc64be"
+		},
+		{
+				//item 15
+				CS_ARCH_SPARC,
+				CS_MODE_BIG_ENDIAN,
+				"Sparc",
+				"sparc"
+		},
+		{
+				//item 16
+				CS_ARCH_SPARC,
+				(cs_mode) (CS_MODE_BIG_ENDIAN + CS_MODE_V9),
+				"SparcV9",
+				"sparcv9"
+		},
+		{
+				//item 17
+				CS_ARCH_SYSZ,
+				(cs_mode) 0,
+				"SystemZ",
+				"systemz"
+		},
+		{
+				//item 18
+				CS_ARCH_XCORE,
+				(cs_mode) 0,
+				"XCore",
+				"xcore"
+		},
+		{
+				//item 19
+				CS_ARCH_MIPS,
+				(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
+				"MIPS-32R6 (Big-endian)",
+				"mipsbe32r6"
+		},
+		{
+				//item 20
+				CS_ARCH_MIPS,
+				(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
+				"MIPS-32R6 (Micro+Big-endian)",
+				"mipsbe32r6micro"
+		},
+		{
+				//item 21
+				CS_ARCH_MIPS,
+				CS_MODE_MIPS32R6,
+				"MIPS-32R6 (Little-endian)",
+				"mips32r6"
+		},
+		{
+				//item 22
+				CS_ARCH_MIPS,
+				(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_MICRO),
+				"MIPS-32R6 (Micro+Little-endian)",
+				"mips32r6micro"
+		},
+		{
+				//item 23
+				CS_ARCH_M68K,
+				(cs_mode) 0,
+				"M68K",
+				"m68k"
+		},
+		{
+				//item 24
+				CS_ARCH_M680X,
+				(cs_mode) CS_MODE_M680X_6809,
+				"M680X_M6809",
+				"m6809"
+		},
+		{
+				//item 25
+				CS_ARCH_EVM,
+				(cs_mode) 0,
+				"EVM",
+				"evm"
+		},
+		{
+				//item 26
+				CS_ARCH_MOS65XX,
+				(cs_mode) 0,
+				"MOS65XX",
+				"mos65xx"
+		},
+		{
+				//item 27
+				CS_ARCH_TMS320C64X,
+				CS_MODE_BIG_ENDIAN,
+				"tms320c64x",
+				"tms320c64x"
+		},
+		{
+				//item 28
+				CS_ARCH_WASM,
+				(cs_mode) 0,
+				"WASM",
+				"wasm"
+		},
+		{
+				//item 29
+				CS_ARCH_BPF,
+				CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC,
+				"cBPF",
+				"bpf"
+		},
+		{
+				//item 30
+				CS_ARCH_BPF,
+				CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
+				"eBPF",
+				"ebpf"
+		},
+		{
+				//item 31
+				CS_ARCH_BPF,
+				CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC,
+				"cBPF",
+				"bpfbe"
+		},
+		{
+				//item 32
+				CS_ARCH_BPF,
+				CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED,
+				"eBPF",
+				"ebpfbe"
+		},
+		{
+				// item 33
+				CS_ARCH_X86,
+				CS_MODE_16,
+				"X86 16 (Intel syntax)",
+				"x16"
+		},
+		{
+				// item 34
+				CS_ARCH_M68K,
+				CS_MODE_M68K_040,
+				"M68K mode 40",
+				"m68k40"
+		},
+		{
+				//item 35
+				CS_ARCH_M680X,
+				(cs_mode) CS_MODE_M680X_6800,
+				"M680X_M6800",
+				"m6800"
+		},
+		{
+				//item 36
+				CS_ARCH_M680X,
+				(cs_mode) CS_MODE_M680X_6801,
+				"M680X_M6801",
+				"m6801"
+		},
+		{
+				//item 37
+				CS_ARCH_M680X,
+				(cs_mode) CS_MODE_M680X_6805,
+				"M680X_M6805",
+				"m6805"
+		},
+		{
+				//item 38
+				CS_ARCH_M680X,
+				(cs_mode) CS_MODE_M680X_6808,
+				"M680X_M6808",
+				"m6808"
+		},
+		{
+				//item 39
+				CS_ARCH_M680X,
+				(cs_mode) CS_MODE_M680X_6811,
+				"M680X_M6811",
+				"m6811"
+		},
+		{
+				//item 40
+				CS_ARCH_M680X,
+				(cs_mode) CS_MODE_M680X_CPU12,
+				"M680X_cpu12",
+				"cpu12"
+		},
+		{
+				//item 41
+				CS_ARCH_M680X,
+				(cs_mode) CS_MODE_M680X_6301,
+				"M680X_M6808",
+				"hd6301"
+		},
+		{
+				//item 42
+				CS_ARCH_M680X,
+				(cs_mode) CS_MODE_M680X_6309,
+				"M680X_M6808",
+				"hd6309"
+		},
+		{
+				//item 43
+				CS_ARCH_M680X,
+				(cs_mode) CS_MODE_M680X_HCS08,
+				"M680X_M6808",
+				"hcs08"
+		},
+		{
+				//item 44
+				CS_ARCH_RISCV,
+				CS_MODE_RISCV32,
+				"RISCV",
+				"riscv32"
+		},
+		{
+				//item 45
+				CS_ARCH_RISCV,
+				CS_MODE_RISCV64,
+				"RISCV",
+				"riscv64"
+		},
+		{
+				//item 46
+				CS_ARCH_PPC,
+				CS_MODE_64 | CS_MODE_BIG_ENDIAN | CS_MODE_QPX,
+				"ppc+qpx",
+				"ppc64beqpx"
+		},
+		{
+				CS_ARCH_TRICORE,
+				CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_110,
+				"TRICORE",
+				"tc110"
+		},
+		{
+				CS_ARCH_TRICORE,
+				CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_120,
+				"TRICORE",
+				"tc120"
+		},
+		{
+				CS_ARCH_TRICORE,
+				CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_130,
+				"TRICORE",
+				"tc130"
+		},
+		{
+				CS_ARCH_TRICORE,
+				CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_131,
+				"TRICORE",
+				"tc131"
+		},
+		{
+				CS_ARCH_TRICORE,
+				CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_160,
+				"TRICORE",
+				"tc160"
+		},
+		{
+				CS_ARCH_TRICORE,
+				CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_161,
+				"TRICORE",
+				"tc161"
+		},
+		{
+				CS_ARCH_TRICORE,
+				CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_162,
+				"TRICORE",
+				"tc162"
+		},
 
-    // dummy entry to mark the end of this array.
-    // DO NOT DELETE THIS
-    {
-        0,
-        0,
-        NULL,
-        NULL,
-    },
+		// dummy entry to mark the end of this array.
+		// DO NOT DELETE THIS
+		{
+				0,
+				0,
+				NULL,
+				NULL,
+		},
 };
 
 // get length of platforms[]
-unsigned int platform_len(void)
-{
-    unsigned int c;
+unsigned int platform_len(void) {
+	unsigned int c;
 
-    for(c = 0; platforms[c].cstoolname; c++);
+	for (c = 0; platforms[c].cstoolname; c++);
 
-    return c;
+	return c;
 }
 
 // get platform entry encoded n (first byte for input data of OSS fuzz)
-unsigned int get_platform_entry(uint8_t n)
-{
-    return n % platform_len();
+unsigned int get_platform_entry(uint8_t n) {
+	return n % platform_len();
 }
 
 // get cstoolname from encoded n (first byte for input data of OSS fuzz)
-const char *get_platform_cstoolname(uint8_t n)
-{
-    return platforms[get_platform_entry(n)].cstoolname;
+const char *get_platform_cstoolname(uint8_t n) {
+	return platforms[get_platform_entry(n)].cstoolname;
 }
 
diff --git a/suite/gencstest.py b/suite/gencstest.py
new file mode 100755
index 0000000000..b21358fc53
--- /dev/null
+++ b/suite/gencstest.py
@@ -0,0 +1,69 @@
+#!/usr/bin/env python3
+
+import sys
+import re
+
+# 80001c1a <IfxVadc_disableAccess>:
+# 80001c1a:	40 4f       	mov.aa %a15,%a4
+# 80001c1c:	02 48       	mov %d8,%d4
+# 80001c1e:	6d ff 9d ff 	call 80001b58 <IfxScuWdt_getSafetyWatchdogPassword>
+
+unique_set = set()
+
+
+def gen(filename):
+    with open(filename, 'r') as f:
+        for line in f:
+            caps = re.findall(r'([0-9a-f]+):\s+([0-9a-f]+) ([0-9a-f]+) ([0-9a-f]+)? ([0-9a-f]+)?\s+'
+                              r'(\S+) (\S+)', line)
+            if not caps:
+                continue
+            caps = caps[0]
+            addr = int(caps[0], 16)
+            hexstr = caps[1:5]
+            mnemonic: str = caps[5]
+            operands = caps[6]
+
+            def try_dedisp(x):
+                try:
+                    disp = int(x, 16)
+                    if disp > 0x80000000:
+                        x = hex(disp - addr)
+                    return x
+                except ValueError:
+                    pass
+                return x
+
+            def is_hex_string(s: str) -> bool:
+                if not s.isalnum():
+                    return False
+                return all(c.isdigit() or c.lower() in 'abcdef' for c in s) and any(c.lower() in 'abcdef' for c in s)
+
+            hexstr = ','.join(f'0x{x}' for x in hexstr if x)
+            fun = re.match(r'\s*<.+>\s*', operands)
+            # print(hex(addr), hexstr, mnemonic, operands)
+            if any([mnemonic.startswith(pre) for pre in
+                    ['mtcr', 'mfcr', 'st.a', 'st.b', 'st.d', 'st.w', 'ld.a', 'ld.b', 'ld.d', 'ld.w']]):
+                unique_set.add(f"# {hexstr.ljust(19)} = {mnemonic}\t{operands}")
+                continue
+
+            ops = operands.split(',')
+            if any([mnemonic.startswith(pre) for pre in ['j', 'call', 'loop', 'fcall']]) or fun:
+                re.sub(r'\s*<.+>\s*', '', operands)
+                # de relative addressing
+                ops = map(try_dedisp, ops)
+
+            ops = map(lambda x: '0x' + x if is_hex_string(x) and not x.startswith('0x') else x, ops)
+            operands = ', '.join(ops)
+            unique_set.add(f"{hexstr.ljust(19)} = {mnemonic}\t{operands}")
+
+    print('# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None')
+    print('\n'.join(unique_set))
+
+
+def main():
+    gen(sys.argv[1])
+
+
+if __name__ == '__main__':
+    main()
diff --git a/suite/test_corpus.py b/suite/test_corpus.py
index b55a684849..def608a0c8 100755
--- a/suite/test_corpus.py
+++ b/suite/test_corpus.py
@@ -32,6 +32,7 @@ def test_file(fname):
         "CS_ARCH_X86": CS_ARCH_X86,
         "CS_ARCH_XCORE": CS_ARCH_XCORE,
         "CS_ARCH_RISCV": CS_ARCH_RISCV,
+        "CS_ARCH_TRICORE": CS_ARCH_TRICORE,
     }
     
     modes = {
@@ -60,6 +61,13 @@ def test_file(fname):
         "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN,
         "CS_MODE_RISCV32": CS_MODE_RISCV32,
         "CS_MODE_RISCV64": CS_MODE_RISCV64,
+        "CS_MODE_TRICORE_110": CS_MODE_TRICORE_110,
+        "CS_MODE_TRICORE_120": CS_MODE_TRICORE_120,
+        "CS_MODE_TRICORE_130": CS_MODE_TRICORE_130,
+        "CS_MODE_TRICORE_131": CS_MODE_TRICORE_131,
+        "CS_MODE_TRICORE_160": CS_MODE_TRICORE_160,
+        "CS_MODE_TRICORE_161": CS_MODE_TRICORE_161,
+        "CS_MODE_TRICORE_162": CS_MODE_TRICORE_162,
     }
 
     mc_modes = {
@@ -96,6 +104,13 @@ def test_file(fname):
         ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_EXTENDED"): 32,
         ("CS_ARCH_RISCV", "CS_MODE_RISCV32"): 44,
         ("CS_ARCH_RISCV", "CS_MODE_RISCV64"): 45,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_110"): 47,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_120"): 48,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_130"): 49,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_131"): 50,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_160"): 51,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_161"): 52,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_162"): 53,
     }
 
     #if not option in ('', 'None'):
@@ -115,6 +130,7 @@ def test_file(fname):
             continue
         hex_code = code.replace('0x', '')
         hex_code = hex_code.replace(',', '')
+        hex_code = hex_code.replace(' ', '')
         try:
             hex_data = hex_code.strip().decode('hex')
         except:
diff --git a/suite/test_corpus3.py b/suite/test_corpus3.py
new file mode 100755
index 0000000000..88de76d086
--- /dev/null
+++ b/suite/test_corpus3.py
@@ -0,0 +1,163 @@
+#!/usr/bin/env python3
+# Test tool to compare Capstone output with llvm-mc. By Nguyen Anh Quynh, 2014
+import sys
+import os
+from capstone import *
+from pathlib import Path
+import codecs
+
+
+def test_file(fname):
+    print("Test %s" % fname)
+    fpath = Path(fname) if isinstance(fname, str) else fname
+    if fpath.is_dir():
+        if fpath.exists() is False:
+            return
+        for f in fpath.iterdir():
+            test_file(f)
+        return
+
+    with fpath.open() as f:
+        lines = f.readlines()
+
+    if not lines[0].startswith('# '):
+        print("ERROR: decoding information is missing")
+        return
+
+    # skip '# ' at the front, then split line to get out hexcode
+    # Note: option can be '', or 'None'
+    # print lines[0]
+    # print lines[0][2:].split(', ')
+    (arch, mode, option) = lines[0][2:].split(', ')
+    mode = mode.replace(' ', '')
+    option = option.strip()
+
+    archs = {
+        "CS_ARCH_ARM": CS_ARCH_ARM,
+        "CS_ARCH_ARM64": CS_ARCH_ARM64,
+        "CS_ARCH_MIPS": CS_ARCH_MIPS,
+        "CS_ARCH_PPC": CS_ARCH_PPC,
+        "CS_ARCH_SPARC": CS_ARCH_SPARC,
+        "CS_ARCH_SYSZ": CS_ARCH_SYSZ,
+        "CS_ARCH_X86": CS_ARCH_X86,
+        "CS_ARCH_XCORE": CS_ARCH_XCORE,
+        "CS_ARCH_RISCV": CS_ARCH_RISCV,
+        "CS_ARCH_TRICORE": CS_ARCH_TRICORE,
+    }
+
+    modes = {
+        "CS_MODE_16": CS_MODE_16,
+        "CS_MODE_32": CS_MODE_32,
+        "CS_MODE_64": CS_MODE_64,
+        "CS_MODE_MIPS32": CS_MODE_MIPS32,
+        "CS_MODE_MIPS64": CS_MODE_MIPS64,
+        "0": CS_MODE_ARM,
+        "CS_MODE_ARM": CS_MODE_ARM,
+        "CS_MODE_THUMB": CS_MODE_THUMB,
+        "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM + CS_MODE_V8,
+        "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB + CS_MODE_V8,
+        "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB + CS_MODE_MCLASS,
+        "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN,
+        "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN,
+        "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64 + CS_MODE_LITTLE_ENDIAN,
+        "CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64 + CS_MODE_BIG_ENDIAN,
+        "CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32 + CS_MODE_MICRO,
+        "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN,
+        "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN,
+        "CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9,
+        "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN,
+        "CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32 + CS_MODE_LITTLE_ENDIAN,
+        "CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN,
+        "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN,
+        "CS_MODE_RISCV32": CS_MODE_RISCV32,
+        "CS_MODE_RISCV64": CS_MODE_RISCV64,
+        "CS_MODE_TRICORE_110": CS_MODE_TRICORE_110,
+        "CS_MODE_TRICORE_120": CS_MODE_TRICORE_120,
+        "CS_MODE_TRICORE_130": CS_MODE_TRICORE_130,
+        "CS_MODE_TRICORE_131": CS_MODE_TRICORE_131,
+        "CS_MODE_TRICORE_160": CS_MODE_TRICORE_160,
+        "CS_MODE_TRICORE_161": CS_MODE_TRICORE_161,
+        "CS_MODE_TRICORE_162": CS_MODE_TRICORE_162,
+    }
+
+    mc_modes = {
+        ("CS_ARCH_X86", "CS_MODE_32"): 0,
+        ("CS_ARCH_X86", "CS_MODE_64"): 1,
+        ("CS_ARCH_ARM", "CS_MODE_ARM"): 2,
+        ("CS_ARCH_ARM", "CS_MODE_THUMB"): 3,
+        ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): 4,
+        ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): 5,
+        ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): 6,
+        ("CS_ARCH_ARM64", "0"): 7,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): 8,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): 9,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): 10,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): 11,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): 12,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 13,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): 13,
+        ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): 14,
+        ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN"): 15,
+        ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN+CS_MODE_V9"): 16,
+        ("CS_ARCH_SYSZ", "0"): 17,
+        ("CS_ARCH_XCORE", "0"): 18,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_BIG_ENDIAN"): 19,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 20,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6"): 21,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO"): 22,
+        ("CS_ARCH_M68K", "0"): 23,
+        ("CS_ARCH_M680X", "CS_MODE_M680X_6809"): 24,
+        ("CS_ARCH_EVM", "0"): 25,
+        ("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_CLASSIC"): 29,
+        ("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED"): 30,
+        ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_CLASSIC"): 31,
+        ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_EXTENDED"): 32,
+        ("CS_ARCH_RISCV", "CS_MODE_RISCV32"): 44,
+        ("CS_ARCH_RISCV", "CS_MODE_RISCV64"): 45,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_110"): 47,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_120"): 48,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_130"): 49,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_131"): 50,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_160"): 51,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_161"): 52,
+        ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_162"): 53,
+    }
+
+    # if not option in ('', 'None'):
+    #    print archs[arch], modes[mode], options[option]
+
+    for line in lines[1:]:
+        # ignore all the input lines having # in front.
+        if line.startswith('#'):
+            continue
+        if line.startswith('// '):
+            line = line[3:]
+        # print("Check %s" %line)
+        code = line.split(' = ')[0]
+        if len(code) < 2:
+            continue
+        if code.find('//') >= 0:
+            continue
+        hex_code = code.replace('0x', '').replace(',', '').replace(' ', '').strip()
+        try:
+            hex_data = bytes.fromhex(hex_code)
+            fpath = Path("fuzz/corpus/%s_%s" % (os.path.basename(fname), hex_code))
+            if fpath.parent.exists() is False:
+                fpath.parent.mkdir(parents=True)
+            with fpath.open('wb') as fout:
+                if (arch, mode) not in mc_modes:
+                    print("fail", arch, mode)
+                fout.write(mc_modes[(arch, mode)].to_bytes(1, 'little'))
+                fout.write(hex_data)
+        except Exception as e:
+            print(f"skipping: {hex_code} with: {e}")
+
+
+if __name__ == '__main__':
+    if len(sys.argv) == 1:
+        fnames = sys.stdin.readlines()
+        for fname in fnames:
+            test_file(fname.strip())
+    else:
+        # print("Usage: ./test_mc.py <input-file.s.cs>")
+        test_file(sys.argv[1])
diff --git a/tests/Makefile b/tests/Makefile
index 86a08e604f..a66df22fcc 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -129,6 +129,9 @@ ifneq (,$(findstring bpf,$(CAPSTONE_ARCHS)))
 CFLAGS += -DCAPSTONE_HAS_BPF
 SOURCES += test_bpf.c
 endif
+ifneq (,$(findstring tricore,$(CAPSTONE_ARCHS)))
+SOURCES += test_tricore.c
+endif
 
 OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o))
 BINARY = $(addprefix $(TESTDIR)/,$(SOURCES:.c=$(BIN_EXT)))
diff --git a/tests/test_iter.c b/tests/test_iter.c
index e3edfb0c85..b32b92110f 100644
--- a/tests/test_iter.c
+++ b/tests/test_iter.c
@@ -75,6 +75,10 @@ static void test()
 #define RISCV_CODE64 "\x13\x04\xa8\x7a"  // aaa80413
 #endif
 
+#ifdef CAPSTONE_HAS_TRICORE
+#define TRICORE_CODE "\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19\xff\xc0\x70\x19\xff\x20\x10"
+#endif
+
 struct platform platforms[] = {
 #ifdef CAPSTONE_HAS_X86
 		{
@@ -248,6 +252,15 @@ struct platform platforms[] = {
 			sizeof(RISCV_CODE64) - 1,
 			"RISCV64"
 		},
+#endif
+#ifdef CAPSTONE_HAS_TRICORE
+	    {
+		CS_ARCH_TRICORE,
+		CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_162,
+		(unsigned char*)TRICORE_CODE,
+		sizeof(TRICORE_CODE) - 1,
+		"TriCore"
+	    },
 #endif
 	};
 
diff --git a/tests/test_tricore.c b/tests/test_tricore.c
new file mode 100644
index 0000000000..fc90148188
--- /dev/null
+++ b/tests/test_tricore.c
@@ -0,0 +1,146 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#include <stdio.h>
+
+#include <capstone/platform.h>
+#include <capstone/capstone.h>
+
+struct platform {
+	cs_arch arch;
+	cs_mode mode;
+	unsigned char *code;
+	size_t size;
+	char *comment;
+};
+
+static csh handle;
+
+static void print_string_hex(char *comment, unsigned char *str, size_t len)
+{
+	unsigned char *c;
+
+	printf("%s", comment);
+	for (c = str; c < str + len; c++) {
+		printf("0x%02x ", *c & 0xff);
+	}
+
+	printf("\n");
+}
+
+static void print_insn_detail(cs_insn *ins)
+{
+	cs_tricore *tricore;
+	int i;
+
+	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
+	if (ins->detail == NULL)
+		return;
+
+	tricore = &(ins->detail->tricore);
+	if (tricore->op_count)
+		printf("\top_count: %u\n", tricore->op_count);
+
+	for (i = 0; i < tricore->op_count; i++) {
+		cs_tricore_op *op = &(tricore->operands[i]);
+		switch ((int)op->type) {
+		default:
+			break;
+		case TRICORE_OP_REG:
+			printf("\t\toperands[%u].type: REG = %s\n", i,
+			       cs_reg_name(handle, op->reg));
+			break;
+		case TRICORE_OP_IMM:
+			printf("\t\toperands[%u].type: IMM = 0x%x\n", i,
+			       op->imm);
+			break;
+		case TRICORE_OP_MEM:
+			printf("\t\toperands[%u].type: MEM\n", i);
+			if (op->mem.base != TRICORE_REG_INVALID)
+				printf("\t\t\toperands[%u].mem.base: REG = %s\n",
+				       i, cs_reg_name(handle, op->mem.base));
+			if (op->mem.disp != 0)
+				printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i,
+				       op->mem.disp);
+
+			break;
+		}
+	}
+
+	printf("\n");
+}
+
+static void test()
+{
+//#define TRICORE_CODE "\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19\xff\xc0\x70\x19\xff\x20\x10"
+#define TRICORE_CODE \
+	"\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01"
+
+	struct platform platforms[] = {
+		{
+			CS_ARCH_TRICORE,
+			CS_MODE_TRICORE_162,
+			(unsigned char *)TRICORE_CODE,
+			sizeof(TRICORE_CODE) - 1,
+			"TriCore",
+		},
+	};
+
+	uint64_t address = 0x1000;
+	cs_insn *insn;
+	int i;
+	size_t count;
+
+	for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) {
+		cs_err err =
+			cs_open(platforms[i].arch, platforms[i].mode, &handle);
+		if (err) {
+			printf("Failed on cs_open() with error returned: %u\n",
+			       err);
+			continue;
+		}
+
+		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
+
+		count = cs_disasm(handle, platforms[i].code, platforms[i].size,
+				  address, 0, &insn);
+		if (count) {
+			size_t j;
+
+			printf("****************\n");
+			printf("Platform: %s\n", platforms[i].comment);
+			print_string_hex("Code:", platforms[i].code,
+					 platforms[i].size);
+			printf("Disasm:\n");
+
+			for (j = 0; j < count; j++) {
+				printf("0x%" PRIx64 ":\t%s\t%s\n",
+				       insn[j].address, insn[j].mnemonic,
+				       insn[j].op_str);
+				print_insn_detail(&insn[j]);
+			}
+			printf("0x%" PRIx64 ":\n",
+			       insn[j - 1].address + insn[j - 1].size);
+
+			// free memory allocated by cs_disasm()
+			cs_free(insn, count);
+		} else {
+			printf("****************\n");
+			printf("Platform: %s\n", platforms[i].comment);
+			print_string_hex("Code:", platforms[i].code,
+					 platforms[i].size);
+			printf("ERROR: Failed to disasm given code!\n");
+		}
+
+		printf("\n");
+
+		cs_close(&handle);
+	}
+}
+
+int main()
+{
+	test();
+
+	return 0;
+}