diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index 71cae77e1a..b3ffc1bfe1 100755
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -407,12 +407,13 @@ class _cs_arch(ctypes.Union):
 
 class _cs_detail(ctypes.Structure):
     _fields_ = (
-        ('regs_read', ctypes.c_uint16 * 16),
+        ('regs_read', ctypes.c_uint16 * 20),
         ('regs_read_count', ctypes.c_ubyte),
         ('regs_write', ctypes.c_uint16 * 20),
         ('regs_write_count', ctypes.c_ubyte),
         ('groups', ctypes.c_ubyte * 8),
         ('groups_count', ctypes.c_ubyte),
+        ('writeback', ctypes.c_bool),
         ('arch', _cs_arch),
     )
 
@@ -725,9 +726,9 @@ def __gen_detail(self):
         elif arch == CS_ARCH_BPF:
             (self.operands) = bpf.get_arch_info(self._raw.detail.contents.arch.bpf)
         elif arch == CS_ARCH_RISCV:
-            (self.operands) = riscv.get_arch_info(self._raw.detail.contents.arch.riscv)
+            (self.need_effective_addr, self.operands) = riscv.get_arch_info(self._raw.detail.contents.arch.riscv)
         elif arch == CS_ARCH_TRICORE:
-            (self.operands) = riscv.get_arch_info(self._raw.detail.contents.arch.tricore)
+            (self.update_flags, self.operands) = tricore.get_arch_info(self._raw.detail.contents.arch.tricore)
 
 
     def __getattr__(self, name):
diff --git a/bindings/python/capstone/riscv.py b/bindings/python/capstone/riscv.py
index 6e33a75f7e..ca09db61f3 100644
--- a/bindings/python/capstone/riscv.py
+++ b/bindings/python/capstone/riscv.py
@@ -7,7 +7,7 @@
 # define the API
 class RISCVOpMem(ctypes.Structure):
     _fields_ = (
-        ('base', ctypes.c_uint8),
+        ('base', ctypes.c_uint),
         ('disp', ctypes.c_int64),
     )
 
@@ -39,11 +39,11 @@ def mem(self):
 
 class CsRISCV(ctypes.Structure):
     _fields_ = (
-	('need_effective_addr', ctypes.c_bool),
+        ('need_effective_addr', ctypes.c_bool),
         ('op_count',            ctypes.c_uint8),
         ('operands',            RISCVOp * 8),
     )
 
 def get_arch_info(a):
-    return (copy_ctypes_list(a.operands[:a.op_count]))
+    return (a.need_effective_addr, copy_ctypes_list(a.operands[:a.op_count]))
 
diff --git a/bindings/python/capstone/tricore.py b/bindings/python/capstone/tricore.py
index 53ba251e8d..9a48a9f795 100644
--- a/bindings/python/capstone/tricore.py
+++ b/bindings/python/capstone/tricore.py
@@ -1,6 +1,7 @@
 # Capstone Python bindings, by billow <billow.fun@gmail.com>
 
-import ctypes, copy
+import ctypes
+from . import copy_ctypes_list
 from .tricore_const import *
 
 class TriCoreOpMem(ctypes.Structure):
@@ -22,6 +23,7 @@ class TriCoreOp(ctypes.Structure):
     _fields_ = (
         ('type', ctypes.c_uint),
         ('value', TriCoreOpValue),
+        ('access', ctypes.c_uint8)
     )
 
     @property
@@ -42,4 +44,8 @@ class CsTriCore(ctypes.Structure):
     _fields_ = (
         ('op_count', ctypes.c_uint8),
         ('operands', TriCoreOp * 8),
+        ('update_flags', ctypes.c_bool),
     )
+
+def get_arch_info(a):
+    return (a.update_flags, copy_ctypes_list(a.operands[:a.op_count]))