diff --git a/CMakeLists.txt b/CMakeLists.txt index f116b958fb..132641681b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -45,8 +45,8 @@ option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by defau option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF) option(CAPSTONE_INSTALL "Generate install target" ${PROJECT_IS_TOP_LEVEL}) -set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE) -set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore) +set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA) +set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha) list(LENGTH SUPPORTED_ARCHITECTURES count) math(EXPR count "${count}-1") @@ -145,6 +145,7 @@ set(HEADERS_COMMON include/capstone/tricore.h include/capstone/platform.h include/capstone/sh.h + include/capstone/alpha.h ) set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c) @@ -569,6 +570,30 @@ if (CAPSTONE_TRICORE_SUPPORT) set(TEST_SOURCES ${TEST_SOURCES} test_tricore.c) endif () +if (CAPSTONE_ALPHA_SUPPORT) + add_definitions(-DCAPSTONE_HAS_ALPHA) + set(SOURCES_ALPHA + arch/Alpha/AlphaDisassembler.c + arch/Alpha/AlphaInstPrinter.c + arch/Alpha/AlphaMapping.c + arch/Alpha/AlphaModule.c + ) + set(HEADERS_ALPHA + arch/Alpha/AlphaDisassembler.h + arch/Alpha/AlphaGenAsmWriter.inc + arch/Alpha/AlphaGenDisassemblerTables.inc + arch/Alpha/AlphaGenInstrInfo.inc + arch/Alpha/AlphaGenRegisterInfo.inc + arch/Alpha/AlphaLinkage.h + arch/Alpha/AlphaMapping.h + arch/Alpha/AlphaModule.h + arch/Alpha/AlphaGenCSMappingInsnOp.inc + arch/Alpha/AlphaGenCSMappingInsn.inc + arch/Alpha/AlphaGenCSMappingInsnName.inc + ) + set(TEST_SOURCES ${TEST_SOURCES} test_alpha.c) +endif () + if (CAPSTONE_OSXKERNEL_SUPPORT) add_definitions(-DCAPSTONE_HAS_OSXKERNEL) endif() @@ -593,6 +618,7 @@ set(ALL_SOURCES ${SOURCES_RISCV} ${SOURCES_SH} ${SOURCES_TRICORE} + ${SOURCES_ALPHA} ) set(ALL_HEADERS @@ -616,6 +642,7 @@ set(ALL_HEADERS ${HEADERS_RISCV} ${HEADERS_SH} ${HEADERS_TRICORE} + ${HEADERS_ALPHA} ) ## properties @@ -679,6 +706,7 @@ source_group("Source\\BPF" FILES ${SOURCES_BPF}) source_group("Source\\RISCV" FILES ${SOURCES_RISCV}) source_group("Source\\SH" FILES ${SOURCES_SH}) source_group("Source\\TriCore" FILES ${SOURCES_TRICORE}) +source_group("Source\\Alpha" FILES ${SOURCES_ALPHA}) source_group("Include\\Common" FILES ${HEADERS_COMMON}) source_group("Include\\Engine" FILES ${HEADERS_ENGINE}) @@ -700,6 +728,7 @@ source_group("Include\\BPF" FILES ${HEADERS_BPF}) source_group("Include\\RISCV" FILES ${HEADERS_RISCV}) source_group("Include\\SH" FILES ${HEADERS_SH}) source_group("Include\\TriCore" FILES ${HEADERS_TRICORE}) +source_group("Include\\Alpha" FILES ${HEADERS_ALPHA}) ## installation if(CAPSTONE_INSTALL) diff --git a/COMPILE.TXT b/COMPILE.TXT index 76b715a0c7..17e89afc3a 100644 --- a/COMPILE.TXT +++ b/COMPILE.TXT @@ -85,6 +85,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install. /usr/include/capstone/arm.h /usr/include/capstone/arm64.h + /usr/include/capstone/alpha.h /usr/include/capstone/bpf.h /usr/include/capstone/capstone.h /usr/include/capstone/evm.h diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT index 1236082c5f..82fe478a17 100644 --- a/COMPILE_CMAKE.TXT +++ b/COMPILE_CMAKE.TXT @@ -21,6 +21,7 @@ Get CMake for free from http://www.cmake.org. - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM. - CAPSTONE_AARCH64_SUPPORT: support AARCH64. Run cmake with -DCAPSTONE_AARCH64_SUPPORT=0 to remove AARCH64. + - CAPSTONE_ALPHA_SUPPORT: support Alpha. Run cmake with -DCAPSTONE_ALPHA_SUPPORT=0 to remove Alpha. - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X. - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K. - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips. @@ -113,7 +114,7 @@ Get CMake for free from http://www.cmake.org. Will just target the x86 architecture. The list of available architectures is: ARM, AARCH64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX, - WASM, BPF, RISCV. + WASM, BPF, RISCV, Alpha. (4) You can also create an installation image with cmake, by using the 'install' target. Use: diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT index 17159ece64..33c1592d0e 100644 --- a/COMPILE_MSVC.TXT +++ b/COMPILE_MSVC.TXT @@ -32,6 +32,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required. - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support. - CAPSTONE_HAS_AARCH64: support AARCH64. Delete this to remove AARCH64 support. + - CAPSTONE_HAS_ALPHA: support Alpha. Delete this to remove Alpha support. - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support. - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support. - CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support. @@ -41,7 +42,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required. - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support. - CAPSTONE_HAS_TRICORE: support TriCore. Delete this to remove TriCore support. - By default, all 9 architectures are compiled in. + By default, all 11 architectures are compiled in. Besides, Capstone also allows some more customization via following macros. diff --git a/CREDITS.TXT b/CREDITS.TXT index 0f7265a6f3..e520e70816 100644 --- a/CREDITS.TXT +++ b/CREDITS.TXT @@ -88,3 +88,4 @@ fanfuqiang & citypw & porto703 : RISCV architecture. Josh "blacktop" Maine: Arm64 architecture improvements. Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support) Billow & Sidneyp : TriCore architecture. +Dmitry Sibirtsev: Alpha architecture. \ No newline at end of file diff --git a/HACK.TXT b/HACK.TXT index bb47b4d790..85249ef8e4 100644 --- a/HACK.TXT +++ b/HACK.TXT @@ -6,6 +6,7 @@ Capstone source is organized as followings. . <- core engine + README + COMPILE.TXT etc ├── arch <- code handling disasm engine for each arch │   ├── AArch64 <- AArch64 engine +│   ├── Alpha <- Alpha engine │   ├── ARM <- ARM engine │   ├── BPF <- Berkeley Packet Filter engine │   ├── EVM <- Ethereum engine diff --git a/Makefile b/Makefile index 88715bfeae..c1ce2221d3 100644 --- a/Makefile +++ b/Makefile @@ -325,12 +325,21 @@ ifneq (,$(findstring tricore,$(CAPSTONE_ARCHS))) LIBOBJ_TRICORE += $(LIBSRC_TRICORE:%.c=$(OBJDIR)/%.o) endif +DEP_ALPHA = +DEP_ALPHA +=$(wildcard arch/Alpha/Alpha*.inc) + +LIBOBJ_ALPHA = +ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_ALPHA + LIBSRC_ALPHA += $(wildcard arch/Alpha/Alpha*.c) + LIBOBJ_ALPHA += $(LIBSRC_ALPHA:%.c=$(OBJDIR)/%.o) +endif LIBOBJ = LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH) LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF) -LIBOBJ += $(LIBOBJ_TRICORE) +LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) ifeq ($(PKG_EXTRA),) @@ -466,6 +475,7 @@ $(LIBOBJ_WASM): $(DEP_WASM) $(LIBOBJ_MOS65XX): $(DEP_MOS65XX) $(LIBOBJ_BPF): $(DEP_BPF) $(LIBOBJ_TRICORE): $(DEP_TRICORE) +$(LIBOBJ_ALPHA): $(DEP_ALPHA) ifeq ($(CAPSTONE_STATIC),yes) $(ARCHIVE): $(LIBOBJ) @@ -552,12 +562,12 @@ dist: git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip TESTS = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore -TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf +TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf test_alpha TESTS += test_basic.static test_detail.static test_arm.static test_aarch64.static TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static -TESTS += test_mos65xx.static test_wasm.static test_bpf.static +TESTS += test_mos65xx.static test_wasm.static test_bpf.static test_alpha.static check: $(TESTS) diff --git a/Mapping.c b/Mapping.c index 0771631b78..1c70e77068 100644 --- a/Mapping.c +++ b/Mapping.c @@ -313,6 +313,7 @@ DEFINE_get_detail_op(arm, ARM); DEFINE_get_detail_op(ppc, PPC); DEFINE_get_detail_op(tricore, TriCore); DEFINE_get_detail_op(aarch64, AArch64); +DEFINE_get_detail_op(alpha, Alpha); /// Returns true if for this architecture the /// alias operands should be filled. diff --git a/Mapping.h b/Mapping.h index 208032999a..1bed623d0b 100644 --- a/Mapping.h +++ b/Mapping.h @@ -121,6 +121,7 @@ DECL_get_detail_op(arm, ARM); DECL_get_detail_op(ppc, PPC); DECL_get_detail_op(tricore, TriCore); DECL_get_detail_op(aarch64, AArch64); +DECL_get_detail_op(alpha, Alpha); /// Increments the detail->arch.op_count by one. #define DEFINE_inc_detail_op_count(arch, ARCH) \ @@ -144,6 +145,8 @@ DEFINE_inc_detail_op_count(tricore, TriCore); DEFINE_dec_detail_op_count(tricore, TriCore); DEFINE_inc_detail_op_count(aarch64, AArch64); DEFINE_dec_detail_op_count(aarch64, AArch64); +DEFINE_inc_detail_op_count(alpha, Alpha); +DEFINE_dec_detail_op_count(alpha, Alpha); /// Returns true if a memory operand is currently edited. static inline bool doing_mem(const MCInst *MI) @@ -169,6 +172,7 @@ DEFINE_get_arch_detail(arm, ARM); DEFINE_get_arch_detail(ppc, PPC); DEFINE_get_arch_detail(tricore, TriCore); DEFINE_get_arch_detail(aarch64, AArch64); +DEFINE_get_arch_detail(alpha, Alpha); static inline bool detail_is_set(const MCInst *MI) { diff --git a/arch/Alpha/AlphaDisassembler.c b/arch/Alpha/AlphaDisassembler.c new file mode 100644 index 0000000000..5c7c3413db --- /dev/null +++ b/arch/Alpha/AlphaDisassembler.c @@ -0,0 +1,113 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_ALPHA + +#include // DEBUG +#include +#include + +#include "../../utils.h" + +#include "../../MCFixedLenDisassembler.h" +#include "../../Mapping.h" + +#include "AlphaDisassembler.h" +#include "AlphaLinkage.h" + +static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +#include "AlphaGenDisassemblerTables.inc" + +#define GET_REGINFO_ENUM +#define GET_REGINFO_MC_DESC + +#include "AlphaGenRegisterInfo.inc" + +static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Register = GPRC[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Register = F4RC[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Register = F8RC[RegNo]; + MCOperand_CreateReg0(Inst, (Register)); + return MCDisassembler_Success; +} + +#define GET_SUBTARGETINFO_ENUM + +#include "AlphaGenInstrInfo.inc" + +DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes, + size_t ByteLen, MCInst *MI, + uint16_t *Size, uint64_t Address, + void *Info) +{ + if (!handle) { + return MCDisassembler_Fail; + } + + if (ByteLen < 4) { + *Size = 0; + return MCDisassembler_Fail; + } + + uint32_t Insn = readBytes32(MI, Bytes); + // Calling the auto-generated decoder function. + DecodeStatus Result = + decodeInstruction_4(DecoderTable32, MI, Insn, Address, NULL); + + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + + *Size = 4; + return MCDisassembler_Fail; +} + +void Alpha_init(MCRegisterInfo *MRI) +{ + MCRegisterInfo_InitMCRegisterInfo( + MRI, AlphaRegDesc, ARR_SIZE(AlphaRegDesc), 0, 0, AlphaMCRegisterClasses, + ARR_SIZE(AlphaMCRegisterClasses), 0, 0, AlphaRegDiffLists, 0, + AlphaSubRegIdxLists, 1, 0); +} + +#endif \ No newline at end of file diff --git a/arch/Alpha/AlphaDisassembler.h b/arch/Alpha/AlphaDisassembler.h new file mode 100644 index 0000000000..72b08c509b --- /dev/null +++ b/arch/Alpha/AlphaDisassembler.h @@ -0,0 +1,18 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_ALPHADISASSEMBLER_H +#define CS_ALPHADISASSEMBLER_H + +#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) +#include +#endif + +#include "../../MCDisassembler.h" +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include + +void Alpha_init(MCRegisterInfo *MRI); + +#endif // CS_ALPHADISASSEMBLER_H \ No newline at end of file diff --git a/arch/Alpha/AlphaGenAsmWriter.inc b/arch/Alpha/AlphaGenAsmWriter.inc new file mode 100644 index 0000000000..fcb3fcf0fc --- /dev/null +++ b/arch/Alpha/AlphaGenAsmWriter.inc @@ -0,0 +1,1509 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */ +/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#include +#include + +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ "; ADJDOWN \0" + /* 11 */ "; ADJUP \0" + /* 20 */ "lda \0" + /* 25 */ "sra \0" + /* 30 */ "stb \0" + /* 35 */ "sextb \0" + /* 42 */ "stl_c \0" + /* 49 */ "stq_c \0" + /* 56 */ "blbc \0" + /* 62 */ "cmovlbc \0" + /* 71 */ "rpcc \0" + /* 77 */ "bic \0" + /* 82 */ "rc \0" + /* 86 */ "cvttq/svc \0" + /* 97 */ "and \0" + /* 102 */ "fbge \0" + /* 108 */ "cmpbge \0" + /* 116 */ "fcmovge \0" + /* 125 */ "fble \0" + /* 131 */ "cmple \0" + /* 138 */ "cmpule \0" + /* 146 */ "fcmovle \0" + /* 155 */ "fbne \0" + /* 161 */ "jsr_coroutine \0" + /* 176 */ "fcmovne \0" + /* 185 */ "cpyse \0" + /* 192 */ "ldah \0" + /* 198 */ "msklh \0" + /* 205 */ "inslh \0" + /* 212 */ "extlh \0" + /* 219 */ "umulh \0" + /* 226 */ "mskqh \0" + /* 233 */ "insqh \0" + /* 240 */ "extqh \0" + /* 247 */ "mskwh \0" + /* 254 */ "inswh \0" + /* 261 */ "extwh \0" + /* 268 */ "cvtqs/sui \0" + /* 279 */ "cvtts/sui \0" + /* 290 */ "cvtqt/sui \0" + /* 301 */ "ldl_l \0" + /* 308 */ "ldq_l \0" + /* 315 */ "mskbl \0" + /* 322 */ "insbl \0" + /* 329 */ "extbl \0" + /* 336 */ "s4subl \0" + /* 344 */ "s8subl \0" + /* 352 */ "s4addl \0" + /* 360 */ "s8addl \0" + /* 368 */ "ldl \0" + /* 373 */ "mskll \0" + /* 380 */ "insll \0" + /* 387 */ "extll \0" + /* 394 */ "mull \0" + /* 400 */ "mskql \0" + /* 407 */ "insql \0" + /* 414 */ "extql \0" + /* 421 */ "srl \0" + /* 426 */ "stl \0" + /* 431 */ "mskwl \0" + /* 438 */ "inswl \0" + /* 445 */ "extwl \0" + /* 452 */ "cpysn \0" + /* 459 */ "ctpop \0" + /* 466 */ "s4subq \0" + /* 474 */ "s8subq \0" + /* 482 */ "s4addq \0" + /* 490 */ "s8addq \0" + /* 498 */ "ldq \0" + /* 503 */ "fbeq \0" + /* 509 */ "cmpeq \0" + /* 516 */ "fcmoveq \0" + /* 525 */ "mulq \0" + /* 531 */ "stq \0" + /* 536 */ "xor \0" + /* 541 */ "cvtst/s \0" + /* 550 */ "blbs \0" + /* 556 */ "cmovlbs \0" + /* 565 */ "lds \0" + /* 570 */ "itofs \0" + /* 577 */ "bis \0" + /* 582 */ "ftois \0" + /* 589 */ "rs \0" + /* 593 */ "sts \0" + /* 598 */ "cpys \0" + /* 604 */ "ldt \0" + /* 609 */ "itoft \0" + /* 616 */ "fbgt \0" + /* 622 */ "fcmovgt \0" + /* 631 */ "ftoit \0" + /* 638 */ "fblt \0" + /* 644 */ "cmplt \0" + /* 651 */ "cmpult \0" + /* 659 */ "fcmovlt \0" + /* 668 */ "zapnot \0" + /* 676 */ "ornot \0" + /* 683 */ "stt \0" + /* 688 */ "ldq_u \0" + /* 695 */ "stq_u \0" + /* 702 */ "ldbu \0" + /* 708 */ "cmptle/su \0" + /* 719 */ "cmptun/su \0" + /* 730 */ "cmpteq/su \0" + /* 741 */ "subs/su \0" + /* 750 */ "adds/su \0" + /* 759 */ "muls/su \0" + /* 768 */ "sqrts/su \0" + /* 778 */ "divs/su \0" + /* 787 */ "subt/su \0" + /* 796 */ "addt/su \0" + /* 805 */ "cmptlt/su \0" + /* 816 */ "mult/su \0" + /* 825 */ "sqrtt/su \0" + /* 835 */ "divt/su \0" + /* 844 */ "ldwu \0" + /* 850 */ "eqv \0" + /* 855 */ "stw \0" + /* 860 */ "sextw \0" + /* 867 */ "ctlz \0" + /* 873 */ "cttz \0" + /* 879 */ "bsr $26,$\0" + /* 889 */ "LSMARKER$\0" + /* 899 */ "wh64 (\0" + /* 906 */ "ecb (\0" + /* 912 */ "fetch (\0" + /* 920 */ "fetch_m (\0" + /* 930 */ "wh64en (\0" + /* 939 */ "jmp $31,\0" + /* 948 */ "br $31,\0" + /* 956 */ "# XRay Function Patchable RET.\0" + /* 987 */ "# XRay Typed Event Log.\0" + /* 1011 */ "# XRay Custom Event Log.\0" + /* 1036 */ "# XRay Function Enter.\0" + /* 1059 */ "# XRay Tail Call Exit.\0" + /* 1082 */ "# XRay Function Exit.\0" + /* 1104 */ "jsr $23,($27),0\0" + /* 1120 */ "jsr $26,($27),0\0" + /* 1136 */ "ret $31,($26),1\0" + /* 1152 */ "COND_BRANCH imm:\0" + /* 1169 */ "LIFETIME_END\0" + /* 1182 */ "PSEUDO_PROBE\0" + /* 1195 */ "BUNDLE\0" + /* 1202 */ "DBG_VALUE\0" + /* 1212 */ "DBG_INSTR_REF\0" + /* 1226 */ "DBG_PHI\0" + /* 1234 */ "DBG_LABEL\0" + /* 1244 */ "LIFETIME_START\0" + /* 1259 */ "DBG_VALUE_LIST\0" + /* 1274 */ "PCMARKER_\0" + /* 1284 */ "excb\0" + /* 1289 */ "wmb\0" + /* 1293 */ "trapb\0" + /* 1299 */ "#wtf\0" + /* 1304 */ "# FEntry call\0" +}; +#endif // CAPSTONE_DIET + + static const uint16_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 1203U, // DBG_VALUE + 1260U, // DBG_VALUE_LIST + 1213U, // DBG_INSTR_REF + 1227U, // DBG_PHI + 1235U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 1196U, // BUNDLE + 1245U, // LIFETIME_START + 1170U, // LIFETIME_END + 1183U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 1305U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 1037U, // PATCHABLE_FUNCTION_ENTER + 957U, // PATCHABLE_RET + 1083U, // PATCHABLE_FUNCTION_EXIT + 1060U, // PATCHABLE_TAIL_CALL + 1012U, // PATCHABLE_EVENT_CALL + 988U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 2049U, // ADJUSTSTACKDOWN + 2060U, // ADJUSTSTACKUP + 19320U, // ALTENT + 0U, // CAS32 + 0U, // CAS64 + 0U, // LAS32 + 0U, // LAS64 + 35706U, // MEMLABEL + 52475U, // PCLABEL + 0U, // SWAP32 + 0U, // SWAP64 + 1300U, // WTF + 4451U, // ADDLi + 4451U, // ADDLr + 4581U, // ADDQi + 4581U, // ADDQr + 4847U, // ADDS + 4893U, // ADDT + 4194U, // ANDi + 4194U, // ANDr + 2553U, // BEQ + 2152U, // BGE + 2666U, // BGT + 4174U, // BICi + 4174U, // BICr + 4674U, // BISi + 4674U, // BISr + 2105U, // BLBC + 2599U, // BLBS + 2175U, // BLE + 2688U, // BLT + 2205U, // BNE + 7093U, // BR + 23408U, // BSR + 4614U, // CMOVEQi + 4614U, // CMOVEQr + 4214U, // CMOVGEi + 4214U, // CMOVGEr + 4720U, // CMOVGTi + 4720U, // CMOVGTr + 4159U, // CMOVLBCi + 4159U, // CMOVLBCr + 4653U, // CMOVLBSi + 4653U, // CMOVLBSr + 4244U, // CMOVLEi + 4244U, // CMOVLEr + 4757U, // CMOVLTi + 4757U, // CMOVLTr + 4274U, // CMOVNEi + 4274U, // CMOVNEr + 4205U, // CMPBGE + 4205U, // CMPBGEi + 4606U, // CMPEQ + 4606U, // CMPEQi + 4228U, // CMPLE + 4228U, // CMPLEi + 4741U, // CMPLT + 4741U, // CMPLTi + 4827U, // CMPTEQ + 4805U, // CMPTLE + 4902U, // CMPTLT + 4816U, // CMPTUN + 4235U, // CMPULE + 4235U, // CMPULEi + 4748U, // CMPULT + 4748U, // CMPULTi + 35969U, // COND_BRANCH_F + 52353U, // COND_BRANCH_I + 4282U, // CPYSES + 4282U, // CPYSESt + 4282U, // CPYSET + 4549U, // CPYSNS + 4549U, // CPYSNSt + 4549U, // CPYSNT + 4549U, // CPYSNTs + 4695U, // CPYSS + 4695U, // CPYSSt + 4695U, // CPYST + 4695U, // CPYSTs + 4964U, // CTLZ + 4556U, // CTPOP + 4970U, // CTTZ + 4365U, // CVTQS + 4387U, // CVTQT + 4638U, // CVTST + 4183U, // CVTTQ + 4376U, // CVTTS + 4875U, // DIVS + 4932U, // DIVT + 5003U, // ECB + 4947U, // EQVi + 4947U, // EQVr + 1285U, // EXCB + 4426U, // EXTBL + 4426U, // EXTBLi + 4309U, // EXTLH + 4309U, // EXTLHi + 4484U, // EXTLL + 4484U, // EXTLLi + 4337U, // EXTQH + 4337U, // EXTQHi + 4511U, // EXTQL + 4511U, // EXTQLi + 4358U, // EXTWH + 4358U, // EXTWHi + 4542U, // EXTWL + 4542U, // EXTWLi + 2552U, // FBEQ + 2151U, // FBGE + 2665U, // FBGT + 2174U, // FBLE + 2687U, // FBLT + 2204U, // FBNE + 8709U, // FCMOVEQS + 8709U, // FCMOVEQT + 8309U, // FCMOVGES + 8309U, // FCMOVGET + 8815U, // FCMOVGTS + 8815U, // FCMOVGTT + 8339U, // FCMOVLES + 8339U, // FCMOVLET + 8852U, // FCMOVLTS + 8852U, // FCMOVLTT + 8369U, // FCMOVNES + 8369U, // FCMOVNET + 5009U, // FETCH + 5017U, // FETCH_M + 4679U, // FTOIS + 4728U, // FTOIT + 4419U, // INSBL + 4419U, // INSBLi + 4302U, // INSLH + 4302U, // INSLHi + 4477U, // INSLL + 4477U, // INSLLi + 4330U, // INSQH + 4330U, // INSQHi + 4504U, // INSQL + 4504U, // INSQLi + 4351U, // INSWH + 4351U, // INSWHi + 4535U, // INSWL + 4535U, // INSWLi + 4667U, // ITOFS + 4706U, // ITOFT + 19372U, // JMP + 1121U, // JSR + 34978U, // JSR_COROUTINE + 1105U, // JSRs + 2069U, // LDA + 2241U, // LDAH + 51393U, // LDAHg + 2241U, // LDAHr + 51221U, // LDAg + 2069U, // LDAr + 2751U, // LDBU + 2751U, // LDBUr + 2417U, // LDL + 2350U, // LDL_L + 2417U, // LDLr + 2547U, // LDQ + 2357U, // LDQ_L + 2737U, // LDQ_U + 2547U, // LDQl + 2547U, // LDQr + 2614U, // LDS + 2614U, // LDSr + 2653U, // LDT + 2653U, // LDTr + 2893U, // LDWU + 2893U, // LDWUr + 1291U, // MB + 4412U, // MSKBL + 4412U, // MSKBLi + 4295U, // MSKLH + 4295U, // MSKLHi + 4470U, // MSKLL + 4470U, // MSKLLi + 4323U, // MSKQH + 4323U, // MSKQHi + 4497U, // MSKQL + 4497U, // MSKQLi + 4344U, // MSKWH + 4344U, // MSKWHi + 4528U, // MSKWL + 4528U, // MSKWLi + 4491U, // MULLi + 4491U, // MULLr + 4622U, // MULQi + 4622U, // MULQr + 4856U, // MULS + 4913U, // MULT + 4773U, // ORNOTi + 4773U, // ORNOTr + 2131U, // RC + 1137U, // RETDAG + 1137U, // RETDAGp + 2120U, // RPCC + 2638U, // RS + 4449U, // S4ADDLi + 4449U, // S4ADDLr + 4579U, // S4ADDQi + 4579U, // S4ADDQr + 4433U, // S4SUBLi + 4433U, // S4SUBLr + 4563U, // S4SUBQi + 4563U, // S4SUBQr + 4457U, // S8ADDLi + 4457U, // S8ADDLr + 4587U, // S8ADDQi + 4587U, // S8ADDQr + 4441U, // S8SUBLi + 4441U, // S8SUBLr + 4571U, // S8SUBQi + 4571U, // S8SUBQr + 4132U, // SEXTB + 4957U, // SEXTW + 4479U, // SLi + 4479U, // SLr + 4865U, // SQRTS + 4922U, // SQRTT + 4122U, // SRAi + 4122U, // SRAr + 4518U, // SRLi + 4518U, // SRLr + 2079U, // STB + 2079U, // STBr + 2475U, // STL + 4139U, // STL_C + 2475U, // STLr + 2580U, // STQ + 4146U, // STQ_C + 2744U, // STQ_U + 2580U, // STQr + 2642U, // STS + 2642U, // STSr + 2732U, // STT + 2732U, // STTr + 2904U, // STW + 2904U, // STWr + 4435U, // SUBLi + 4435U, // SUBLr + 4565U, // SUBQi + 4565U, // SUBQr + 4838U, // SUBS + 4884U, // SUBT + 1294U, // TRAPB + 4316U, // UMULHi + 4316U, // UMULHr + 4996U, // WH64 + 5027U, // WH64EN + 1290U, // WMB + 4633U, // XORi + 4633U, // XORr + 4765U, // ZAPNOTi + }; + + static const uint8_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ADJUSTSTACKDOWN + 0U, // ADJUSTSTACKUP + 0U, // ALTENT + 0U, // CAS32 + 0U, // CAS64 + 0U, // LAS32 + 0U, // LAS64 + 0U, // MEMLABEL + 0U, // PCLABEL + 0U, // SWAP32 + 0U, // SWAP64 + 0U, // WTF + 1U, // ADDLi + 1U, // ADDLr + 1U, // ADDQi + 1U, // ADDQr + 1U, // ADDS + 1U, // ADDT + 1U, // ANDi + 1U, // ANDr + 5U, // BEQ + 5U, // BGE + 5U, // BGT + 1U, // BICi + 1U, // BICr + 1U, // BISi + 1U, // BISr + 5U, // BLBC + 5U, // BLBS + 5U, // BLE + 5U, // BLT + 5U, // BNE + 0U, // BR + 1U, // BSR + 1U, // CMOVEQi + 1U, // CMOVEQr + 1U, // CMOVGEi + 1U, // CMOVGEr + 1U, // CMOVGTi + 1U, // CMOVGTr + 1U, // CMOVLBCi + 1U, // CMOVLBCr + 1U, // CMOVLBSi + 1U, // CMOVLBSr + 1U, // CMOVLEi + 1U, // CMOVLEr + 1U, // CMOVLTi + 1U, // CMOVLTr + 1U, // CMOVNEi + 1U, // CMOVNEr + 1U, // CMPBGE + 1U, // CMPBGEi + 1U, // CMPEQ + 1U, // CMPEQi + 1U, // CMPLE + 1U, // CMPLEi + 1U, // CMPLT + 1U, // CMPLTi + 1U, // CMPTEQ + 1U, // CMPTLE + 1U, // CMPTLT + 1U, // CMPTUN + 1U, // CMPULE + 1U, // CMPULEi + 1U, // CMPULT + 1U, // CMPULTi + 1U, // COND_BRANCH_F + 1U, // COND_BRANCH_I + 1U, // CPYSES + 1U, // CPYSESt + 1U, // CPYSET + 1U, // CPYSNS + 1U, // CPYSNSt + 1U, // CPYSNT + 1U, // CPYSNTs + 1U, // CPYSS + 1U, // CPYSSt + 1U, // CPYST + 1U, // CPYSTs + 9U, // CTLZ + 9U, // CTPOP + 9U, // CTTZ + 9U, // CVTQS + 9U, // CVTQT + 9U, // CVTST + 9U, // CVTTQ + 9U, // CVTTS + 1U, // DIVS + 1U, // DIVT + 2U, // ECB + 1U, // EQVi + 1U, // EQVr + 0U, // EXCB + 1U, // EXTBL + 1U, // EXTBLi + 1U, // EXTLH + 1U, // EXTLHi + 1U, // EXTLL + 1U, // EXTLLi + 1U, // EXTQH + 1U, // EXTQHi + 1U, // EXTQL + 1U, // EXTQLi + 1U, // EXTWH + 1U, // EXTWHi + 1U, // EXTWL + 1U, // EXTWLi + 5U, // FBEQ + 5U, // FBGE + 5U, // FBGT + 5U, // FBLE + 5U, // FBLT + 5U, // FBNE + 0U, // FCMOVEQS + 0U, // FCMOVEQT + 0U, // FCMOVGES + 0U, // FCMOVGET + 0U, // FCMOVGTS + 0U, // FCMOVGTT + 0U, // FCMOVLES + 0U, // FCMOVLET + 0U, // FCMOVLTS + 0U, // FCMOVLTT + 0U, // FCMOVNES + 0U, // FCMOVNET + 2U, // FETCH + 2U, // FETCH_M + 9U, // FTOIS + 9U, // FTOIT + 1U, // INSBL + 1U, // INSBLi + 1U, // INSLH + 1U, // INSLHi + 1U, // INSLL + 1U, // INSLLi + 1U, // INSQH + 1U, // INSQHi + 1U, // INSQL + 1U, // INSQLi + 1U, // INSWH + 1U, // INSWHi + 1U, // INSWL + 1U, // INSWLi + 9U, // ITOFS + 9U, // ITOFT + 2U, // JMP + 0U, // JSR + 2U, // JSR_COROUTINE + 0U, // JSRs + 29U, // LDA + 29U, // LDAH + 2U, // LDAHg + 45U, // LDAHr + 2U, // LDAg + 61U, // LDAr + 29U, // LDBU + 61U, // LDBUr + 29U, // LDL + 29U, // LDL_L + 61U, // LDLr + 29U, // LDQ + 29U, // LDQ_L + 29U, // LDQ_U + 77U, // LDQl + 61U, // LDQr + 29U, // LDS + 61U, // LDSr + 29U, // LDT + 61U, // LDTr + 29U, // LDWU + 61U, // LDWUr + 0U, // MB + 1U, // MSKBL + 1U, // MSKBLi + 1U, // MSKLH + 1U, // MSKLHi + 1U, // MSKLL + 1U, // MSKLLi + 1U, // MSKQH + 1U, // MSKQHi + 1U, // MSKQL + 1U, // MSKQLi + 1U, // MSKWH + 1U, // MSKWHi + 1U, // MSKWL + 1U, // MSKWLi + 1U, // MULLi + 1U, // MULLr + 1U, // MULQi + 1U, // MULQr + 1U, // MULS + 1U, // MULT + 1U, // ORNOTi + 1U, // ORNOTr + 0U, // RC + 0U, // RETDAG + 0U, // RETDAGp + 0U, // RPCC + 0U, // RS + 1U, // S4ADDLi + 1U, // S4ADDLr + 1U, // S4ADDQi + 1U, // S4ADDQr + 1U, // S4SUBLi + 1U, // S4SUBLr + 1U, // S4SUBQi + 1U, // S4SUBQr + 1U, // S8ADDLi + 1U, // S8ADDLr + 1U, // S8ADDQi + 1U, // S8ADDQr + 1U, // S8SUBLi + 1U, // S8SUBLr + 1U, // S8SUBQi + 1U, // S8SUBQr + 9U, // SEXTB + 9U, // SEXTW + 1U, // SLi + 1U, // SLr + 9U, // SQRTS + 9U, // SQRTT + 1U, // SRAi + 1U, // SRAr + 1U, // SRLi + 1U, // SRLr + 3U, // STB + 61U, // STBr + 29U, // STL + 81U, // STL_C + 61U, // STLr + 29U, // STQ + 81U, // STQ_C + 3U, // STQ_U + 61U, // STQr + 29U, // STS + 61U, // STSr + 29U, // STT + 61U, // STTr + 29U, // STW + 61U, // STWr + 1U, // SUBLi + 1U, // SUBLr + 1U, // SUBQi + 1U, // SUBQr + 1U, // SUBS + 1U, // SUBT + 0U, // TRAPB + 1U, // UMULHi + 1U, // UMULHr + 2U, // WH64 + 2U, // WH64EN + 0U, // WMB + 1U, // XORi + 1U, // XORr + 1U, // ZAPNOTi + }; + + // Emit the opcode for the instruction. + uint32_t Bits = 0; + Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16; + MnemonicBitsInfo MBI = { +#ifndef CAPSTONE_DIET + AsmStrs+(Bits & 2047)-1, +#else + NULL, +#endif // CAPSTONE_DIET + Bits + }; + return MBI; +} + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) { + SStream_concat0(O, ""); + MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O); + + SStream_concat0(O, MnemonicInfo.first); + + uint32_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 11) & 7) { + default: assert(0 && "Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // ADJUSTSTACKDOWN, ADJUSTSTACKUP, ALTENT, MEMLABEL, PCLABEL, BEQ, BGE, B... + printOperand(MI, 0, O); + break; + case 2: + // ADDLi, ADDLr, ADDQi, ADDQr, ADDS, ADDT, ANDi, ANDr, BICi, BICr, BISi, ... + printOperand(MI, 1, O); + break; + case 3: + // BR, BSR + printOperandAddr(MI, Address, 0, O); + break; + case 4: + // FCMOVEQS, FCMOVEQT, FCMOVGES, FCMOVGET, FCMOVGTS, FCMOVGTT, FCMOVLES, ... + printOperand(MI, 3, O); + SStream_concat1(O, ','); + printOperand(MI, 2, O); + SStream_concat1(O, ','); + printOperand(MI, 0, O); + return; + break; + } + + + // Fragment 1 encoded into 4 bits for 13 unique commands. + switch ((Bits >> 14) & 15) { + default: assert(0 && "Invalid command number."); + case 0: + // ADJUSTSTACKDOWN, ADJUSTSTACKUP, BR, RC, RPCC, RS + return; + break; + case 1: + // ALTENT + SStream_concat0(O, "..ng:\n"); + return; + break; + case 2: + // MEMLABEL + SStream_concat1(O, '$'); + printOperand(MI, 1, O); + SStream_concat1(O, '$'); + printOperand(MI, 2, O); + SStream_concat1(O, '$'); + printOperand(MI, 3, O); + SStream_concat1(O, ':'); + return; + break; + case 3: + // PCLABEL + SStream_concat0(O, ":\n"); + return; + break; + case 4: + // ADDLi, ADDLr, ADDQi, ADDQr, ADDS, ADDT, ANDi, ANDr, BEQ, BGE, BGT, BIC... + SStream_concat1(O, ','); + break; + case 5: + // BSR + SStream_concat0(O, " ..ng"); + return; + break; + case 6: + // COND_BRANCH_F + SStream_concat0(O, ", F8RC:"); + printOperand(MI, 1, O); + SStream_concat0(O, ", bb:"); + printOperandAddr(MI, Address, 2, O); + return; + break; + case 7: + // COND_BRANCH_I + SStream_concat0(O, ", GPRC:"); + printOperand(MI, 1, O); + SStream_concat0(O, ", bb:"); + printOperandAddr(MI, Address, 2, O); + return; + break; + case 8: + // ECB, FETCH, FETCH_M, WH64, WH64EN + SStream_concat1(O, ')'); + return; + break; + case 9: + // JMP + SStream_concat0(O, ",0"); + return; + break; + case 10: + // JSR_COROUTINE + SStream_concat0(O, ",("); + printOperand(MI, 1, O); + SStream_concat0(O, "),"); + printOperand(MI, 2, O); + return; + break; + case 11: + // LDAHg, LDAg + SStream_concat0(O, ",0("); + printOperand(MI, 2, O); + SStream_concat0(O, ")\t\t!gpdisp!"); + printOperand(MI, 3, O); + return; + break; + case 12: + // STB, STQ_U + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat1(O, '('); + printOperand(MI, 2, O); + SStream_concat1(O, ')'); + return; + break; + } + + + // Fragment 2 encoded into 2 bits for 4 unique commands. + switch ((Bits >> 18) & 3) { + default: assert(0 && "Invalid command number."); + case 0: + // ADDLi, ADDLr, ADDQi, ADDQr, ADDS, ADDT, ANDi, ANDr, BICi, BICr, BISi, ... + printOperand(MI, 2, O); + break; + case 1: + // BEQ, BGE, BGT, BLBC, BLBS, BLE, BLT, BNE, FBEQ, FBGE, FBGT, FBLE, FBLT... + printOperandAddr(MI, Address, 1, O); + return; + break; + case 2: + // CTLZ, CTPOP, CTTZ, CVTQS, CVTQT, CVTST, CVTTQ, CVTTS, FTOIS, FTOIT, IT... + printOperand(MI, 0, O); + return; + break; + case 3: + // LDA, LDAH, LDAHr, LDAr, LDBU, LDBUr, LDL, LDL_L, LDLr, LDQ, LDQ_L, LDQ... + printOperand(MI, 1, O); + SStream_concat1(O, '('); + printOperand(MI, 2, O); + break; + } + + + // Fragment 3 encoded into 3 bits for 6 unique commands. + switch ((Bits >> 20) & 7) { + default: assert(0 && "Invalid command number."); + case 0: + // ADDLi, ADDLr, ADDQi, ADDQr, ADDS, ADDT, ANDi, ANDr, BICi, BICr, BISi, ... + SStream_concat1(O, ','); + printOperand(MI, 0, O); + return; + break; + case 1: + // LDA, LDAH, LDBU, LDL, LDL_L, LDQ, LDQ_L, LDQ_U, LDS, LDT, LDWU, STL, S... + SStream_concat1(O, ')'); + return; + break; + case 2: + // LDAHr + SStream_concat0(O, ")\t\t!gprelhigh"); + return; + break; + case 3: + // LDAr, LDBUr, LDLr, LDQr, LDSr, LDTr, LDWUr, STBr, STLr, STQr, STSr, ST... + SStream_concat0(O, ")\t\t!gprellow"); + return; + break; + case 4: + // LDQl + SStream_concat0(O, ")\t\t!literal"); + return; + break; + case 5: + // STL_C, STQ_C + SStream_concat1(O, '('); + printOperand(MI, 3, O); + SStream_concat1(O, ')'); + return; + break; + } + +} + + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo) { +#ifndef CAPSTONE_DIET + assert(RegNo && RegNo < 65 && "Invalid register number!"); + + static const char AsmStrs[] = { + /* 0 */ "$0\0" + /* 3 */ "$10\0" + /* 7 */ "$f10\0" + /* 12 */ "$20\0" + /* 16 */ "$f20\0" + /* 21 */ "$30\0" + /* 25 */ "$f30\0" + /* 30 */ "$f0\0" + /* 34 */ "$1\0" + /* 37 */ "$11\0" + /* 41 */ "$f11\0" + /* 46 */ "$21\0" + /* 50 */ "$f21\0" + /* 55 */ "$31\0" + /* 59 */ "$f31\0" + /* 64 */ "$f1\0" + /* 68 */ "$2\0" + /* 71 */ "$12\0" + /* 75 */ "$f12\0" + /* 80 */ "$22\0" + /* 84 */ "$f22\0" + /* 89 */ "$f2\0" + /* 93 */ "$3\0" + /* 96 */ "$13\0" + /* 100 */ "$f13\0" + /* 105 */ "$23\0" + /* 109 */ "$f23\0" + /* 114 */ "$f3\0" + /* 118 */ "$4\0" + /* 121 */ "$14\0" + /* 125 */ "$f14\0" + /* 130 */ "$24\0" + /* 134 */ "$f24\0" + /* 139 */ "$f4\0" + /* 143 */ "$5\0" + /* 146 */ "$15\0" + /* 150 */ "$f15\0" + /* 155 */ "$25\0" + /* 159 */ "$f25\0" + /* 164 */ "$f5\0" + /* 168 */ "$6\0" + /* 171 */ "$16\0" + /* 175 */ "$f16\0" + /* 180 */ "$26\0" + /* 184 */ "$f26\0" + /* 189 */ "$f6\0" + /* 193 */ "$7\0" + /* 196 */ "$17\0" + /* 200 */ "$f17\0" + /* 205 */ "$27\0" + /* 209 */ "$f27\0" + /* 214 */ "$f7\0" + /* 218 */ "$8\0" + /* 221 */ "$18\0" + /* 225 */ "$f18\0" + /* 230 */ "$28\0" + /* 234 */ "$f28\0" + /* 239 */ "$f8\0" + /* 243 */ "$9\0" + /* 246 */ "$19\0" + /* 250 */ "$f19\0" + /* 255 */ "$29\0" + /* 259 */ "$f29\0" + /* 264 */ "$f9\0" +}; + static const uint16_t RegAsmOffset[] = { + 30, 64, 89, 114, 139, 164, 189, 214, 239, 264, 7, 41, 75, 100, + 125, 150, 175, 200, 225, 250, 16, 50, 84, 109, 134, 159, 184, 209, + 234, 259, 25, 59, 0, 34, 68, 93, 118, 143, 168, 193, 218, 243, + 3, 37, 71, 96, 121, 146, 171, 196, 221, 246, 12, 46, 80, 105, + 130, 155, 180, 205, 230, 255, 21, 55, + }; + + assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && + "Invalid alt name index for register!"); + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif // CAPSTONE_DIET +} +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) { +#ifndef CAPSTONE_DIET + return false; +#endif // CAPSTONE_DIET +} + +#endif // PRINT_ALIAS_INSTR diff --git a/arch/Alpha/AlphaGenCSMappingInsn.inc b/arch/Alpha/AlphaGenCSMappingInsn.inc new file mode 100644 index 0000000000..8944ebb9fc --- /dev/null +++ b/arch/Alpha/AlphaGenCSMappingInsn.inc @@ -0,0 +1,3800 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */ +/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{ + /* PHINODE */ + Alpha_PHI /* 0 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_INLINEASM /* 1 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_INLINEASM_BR /* 2 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_CFI_INSTRUCTION /* 3 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_EH_LABEL /* 4 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_GC_LABEL /* 5 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_ANNOTATION_LABEL /* 6 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_KILL /* 7 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_EXTRACT_SUBREG /* 8 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_INSERT_SUBREG /* 9 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_IMPLICIT_DEF /* 10 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_SUBREG_TO_REG /* 11 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_COPY_TO_REGCLASS /* 12 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_VALUE */ + Alpha_DBG_VALUE /* 13 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_VALUE_LIST */ + Alpha_DBG_VALUE_LIST /* 14 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_INSTR_REF */ + Alpha_DBG_INSTR_REF /* 15 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_PHI */ + Alpha_DBG_PHI /* 16 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_LABEL */ + Alpha_DBG_LABEL /* 17 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_REG_SEQUENCE /* 18 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_COPY /* 19 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* BUNDLE */ + Alpha_BUNDLE /* 20 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* LIFETIME_START */ + Alpha_LIFETIME_START /* 21 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* LIFETIME_END */ + Alpha_LIFETIME_END /* 22 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* PSEUDO_PROBE */ + Alpha_PSEUDO_PROBE /* 23 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_ARITH_FENCE /* 24 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_STACKMAP /* 25 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # FEntry call */ + Alpha_FENTRY_CALL /* 26 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_PATCHPOINT /* 27 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_LOAD_STACK_GUARD /* 28 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_PREALLOCATED_SETUP /* 29 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_PREALLOCATED_ARG /* 30 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_STATEPOINT /* 31 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_LOCAL_ESCAPE /* 32 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_FAULTING_OP /* 33 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_PATCHABLE_OP /* 34 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Enter. */ + Alpha_PATCHABLE_FUNCTION_ENTER /* 35 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Patchable RET. */ + Alpha_PATCHABLE_RET /* 36 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Exit. */ + Alpha_PATCHABLE_FUNCTION_EXIT /* 37 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Tail Call Exit. */ + Alpha_PATCHABLE_TAIL_CALL /* 38 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Custom Event Log. */ + Alpha_PATCHABLE_EVENT_CALL /* 39 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Typed Event Log. */ + Alpha_PATCHABLE_TYPED_EVENT_CALL /* 40 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_ICALL_BRANCH_FUNNEL /* 41 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_MEMBARRIER /* 42 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ASSERT_SEXT /* 43 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ASSERT_ZEXT /* 44 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ASSERT_ALIGN /* 45 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ADD /* 46 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SUB /* 47 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_MUL /* 48 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SDIV /* 49 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UDIV /* 50 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SREM /* 51 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UREM /* 52 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SDIVREM /* 53 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UDIVREM /* 54 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_AND /* 55 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_OR /* 56 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_XOR /* 57 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_IMPLICIT_DEF /* 58 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_PHI /* 59 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FRAME_INDEX /* 60 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_GLOBAL_VALUE /* 61 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_EXTRACT /* 62 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UNMERGE_VALUES /* 63 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INSERT /* 64 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_MERGE_VALUES /* 65 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BUILD_VECTOR /* 66 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BUILD_VECTOR_TRUNC /* 67 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_CONCAT_VECTORS /* 68 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_PTRTOINT /* 69 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INTTOPTR /* 70 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BITCAST /* 71 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FREEZE /* 72 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INTRINSIC_FPTRUNC_ROUND /* 73 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INTRINSIC_TRUNC /* 74 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INTRINSIC_ROUND /* 75 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INTRINSIC_LRINT /* 76 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INTRINSIC_ROUNDEVEN /* 77 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_READCYCLECOUNTER /* 78 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_LOAD /* 79 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SEXTLOAD /* 80 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ZEXTLOAD /* 81 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INDEXED_LOAD /* 82 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INDEXED_SEXTLOAD /* 83 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INDEXED_ZEXTLOAD /* 84 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_STORE /* 85 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INDEXED_STORE /* 86 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMIC_CMPXCHG_WITH_SUCCESS /* 87 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMIC_CMPXCHG /* 88 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_XCHG /* 89 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_ADD /* 90 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_SUB /* 91 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_AND /* 92 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_NAND /* 93 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_OR /* 94 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_XOR /* 95 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_MAX /* 96 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_MIN /* 97 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_UMAX /* 98 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_UMIN /* 99 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_FADD /* 100 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_FSUB /* 101 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_FMAX /* 102 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_FMIN /* 103 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_UINC_WRAP /* 104 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ATOMICRMW_UDEC_WRAP /* 105 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FENCE /* 106 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BRCOND /* 107 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BRINDIRECT /* 108 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INVOKE_REGION_START /* 109 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INTRINSIC /* 110 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INTRINSIC_W_SIDE_EFFECTS /* 111 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ANYEXT /* 112 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_TRUNC /* 113 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_CONSTANT /* 114 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FCONSTANT /* 115 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VASTART /* 116 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VAARG /* 117 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SEXT /* 118 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SEXT_INREG /* 119 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ZEXT /* 120 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SHL /* 121 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_LSHR /* 122 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ASHR /* 123 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FSHL /* 124 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FSHR /* 125 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ROTR /* 126 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ROTL /* 127 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ICMP /* 128 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FCMP /* 129 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SELECT /* 130 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UADDO /* 131 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UADDE /* 132 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_USUBO /* 133 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_USUBE /* 134 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SADDO /* 135 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SADDE /* 136 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SSUBO /* 137 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SSUBE /* 138 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UMULO /* 139 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SMULO /* 140 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UMULH /* 141 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SMULH /* 142 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UADDSAT /* 143 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SADDSAT /* 144 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_USUBSAT /* 145 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SSUBSAT /* 146 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_USHLSAT /* 147 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SSHLSAT /* 148 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SMULFIX /* 149 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UMULFIX /* 150 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SMULFIXSAT /* 151 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UMULFIXSAT /* 152 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SDIVFIX /* 153 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UDIVFIX /* 154 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SDIVFIXSAT /* 155 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UDIVFIXSAT /* 156 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FADD /* 157 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FSUB /* 158 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FMUL /* 159 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FMA /* 160 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FMAD /* 161 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FDIV /* 162 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FREM /* 163 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FPOW /* 164 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FPOWI /* 165 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FEXP /* 166 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FEXP2 /* 167 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FLOG /* 168 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FLOG2 /* 169 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FLOG10 /* 170 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FNEG /* 171 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FPEXT /* 172 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FPTRUNC /* 173 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FPTOSI /* 174 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FPTOUI /* 175 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SITOFP /* 176 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UITOFP /* 177 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FABS /* 178 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FCOPYSIGN /* 179 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_IS_FPCLASS /* 180 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FCANONICALIZE /* 181 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FMINNUM /* 182 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FMAXNUM /* 183 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FMINNUM_IEEE /* 184 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FMAXNUM_IEEE /* 185 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FMINIMUM /* 186 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FMAXIMUM /* 187 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_PTR_ADD /* 188 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_PTRMASK /* 189 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SMIN /* 190 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SMAX /* 191 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UMIN /* 192 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UMAX /* 193 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ABS /* 194 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_LROUND /* 195 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_LLROUND /* 196 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BR /* 197 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BRJT /* 198 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_INSERT_VECTOR_ELT /* 199 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_EXTRACT_VECTOR_ELT /* 200 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SHUFFLE_VECTOR /* 201 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_CTTZ /* 202 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_CTTZ_ZERO_UNDEF /* 203 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_CTLZ /* 204 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_CTLZ_ZERO_UNDEF /* 205 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_CTPOP /* 206 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BSWAP /* 207 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BITREVERSE /* 208 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FCEIL /* 209 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FCOS /* 210 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FSIN /* 211 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FSQRT /* 212 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FFLOOR /* 213 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FRINT /* 214 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_FNEARBYINT /* 215 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_ADDRSPACE_CAST /* 216 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BLOCK_ADDR /* 217 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_JUMP_TABLE /* 218 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_DYN_STACKALLOC /* 219 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_STRICT_FADD /* 220 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_STRICT_FSUB /* 221 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_STRICT_FMUL /* 222 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_STRICT_FDIV /* 223 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_STRICT_FREM /* 224 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_STRICT_FMA /* 225 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_STRICT_FSQRT /* 226 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_READ_REGISTER /* 227 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_WRITE_REGISTER /* 228 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_MEMCPY /* 229 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_MEMCPY_INLINE /* 230 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_MEMMOVE /* 231 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_MEMSET /* 232 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_BZERO /* 233 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_SEQ_FADD /* 234 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_SEQ_FMUL /* 235 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_FADD /* 236 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_FMUL /* 237 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_FMAX /* 238 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_FMIN /* 239 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_ADD /* 240 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_MUL /* 241 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_AND /* 242 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_OR /* 243 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_XOR /* 244 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_SMAX /* 245 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_SMIN /* 246 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_UMAX /* 247 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_VECREDUCE_UMIN /* 248 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_SBFX /* 249 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_G_UBFX /* 250 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* ; ADJDOWN $amt1 */ + Alpha_ADJUSTSTACKDOWN /* 251 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* ; ADJUP $amt1 */ + Alpha_ADJUSTSTACKUP /* 252 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $$$TARGET..ng: + */ + Alpha_ALTENT /* 253 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_CAS32 /* 254 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_CAS64 /* 255 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_LAS32 /* 256 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_LAS64 /* 257 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* LSMARKER$$$i$$$j$$$k$$$m: */ + Alpha_MEMLABEL /* 258 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* PCMARKER_$num: + */ + Alpha_PCLABEL /* 259 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_SWAP32 /* 260 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Alpha_SWAP64 /* 261 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* #wtf */ + Alpha_WTF /* 262 */, Alpha_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* addl $RA,$L,$RC */ + Alpha_ADDLi /* 263 */, Alpha_INS_ADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* addl $RA,$RB,$RC */ + Alpha_ADDLr /* 264 */, Alpha_INS_ADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* addq $RA,$L,$RC */ + Alpha_ADDQi /* 265 */, Alpha_INS_ADDQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* addq $RA,$RB,$RC */ + Alpha_ADDQr /* 266 */, Alpha_INS_ADDQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* adds/su $RA,$RB,$RC */ + Alpha_ADDS /* 267 */, Alpha_INS_ADDSsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* addt/su $RA,$RB,$RC */ + Alpha_ADDT /* 268 */, Alpha_INS_ADDTsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* and $RA,$L,$RC */ + Alpha_ANDi /* 269 */, Alpha_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* and $RA,$RB,$RC */ + Alpha_ANDr /* 270 */, Alpha_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* beq $R,$dst */ + Alpha_BEQ /* 271 */, Alpha_INS_BEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* bge $R,$dst */ + Alpha_BGE /* 272 */, Alpha_INS_BGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* bgt $R,$dst */ + Alpha_BGT /* 273 */, Alpha_INS_BGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* bic $RA,$L,$RC */ + Alpha_BICi /* 274 */, Alpha_INS_BIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* bic $RA,$RB,$RC */ + Alpha_BICr /* 275 */, Alpha_INS_BIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* bis $RA,$L,$RC */ + Alpha_BISi /* 276 */, Alpha_INS_BIS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* bis $RA,$RB,$RC */ + Alpha_BISr /* 277 */, Alpha_INS_BIS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* blbc $R,$dst */ + Alpha_BLBC /* 278 */, Alpha_INS_BLBC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* blbs $R,$dst */ + Alpha_BLBS /* 279 */, Alpha_INS_BLBS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* ble $R,$dst */ + Alpha_BLE /* 280 */, Alpha_INS_BLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* blt $R,$dst */ + Alpha_BLT /* 281 */, Alpha_INS_BLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* bne $R,$dst */ + Alpha_BNE /* 282 */, Alpha_INS_BNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* br $$31,$DISP */ + Alpha_BR /* 283 */, Alpha_INS_BR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* bsr $$26,$$$DISP ..ng */ + Alpha_BSR /* 284 */, Alpha_INS_BSR, + #ifndef CAPSTONE_DIET + { Alpha_REG_R29, 0 }, { Alpha_REG_R0, Alpha_REG_R1, Alpha_REG_R2, Alpha_REG_R3, Alpha_REG_R4, Alpha_REG_R5, Alpha_REG_R6, Alpha_REG_R7, Alpha_REG_R8, Alpha_REG_R16, Alpha_REG_R17, Alpha_REG_R18, Alpha_REG_R19, Alpha_REG_R20, Alpha_REG_R21, Alpha_REG_R22, Alpha_REG_R23, Alpha_REG_R24, Alpha_REG_R25, Alpha_REG_R26, Alpha_REG_R27, Alpha_REG_R28, Alpha_REG_R29, Alpha_REG_F0, Alpha_REG_F1, Alpha_REG_F10, Alpha_REG_F11, Alpha_REG_F12, Alpha_REG_F13, Alpha_REG_F14, Alpha_REG_F15, Alpha_REG_F16, Alpha_REG_F17, Alpha_REG_F18, Alpha_REG_F19, Alpha_REG_F20, Alpha_REG_F21, Alpha_REG_F22, Alpha_REG_F23, Alpha_REG_F24, Alpha_REG_F25, Alpha_REG_F26, Alpha_REG_F27, Alpha_REG_F28, Alpha_REG_F29, Alpha_REG_F30, 0 }, { Alpha_GRP_CALL, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* cmoveq $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVEQi /* 285 */, Alpha_INS_CMOVEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmoveq $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVEQr /* 286 */, Alpha_INS_CMOVEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovge $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVGEi /* 287 */, Alpha_INS_CMOVGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovge $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVGEr /* 288 */, Alpha_INS_CMOVGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovgt $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVGTi /* 289 */, Alpha_INS_CMOVGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovgt $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVGTr /* 290 */, Alpha_INS_CMOVGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovlbc $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVLBCi /* 291 */, Alpha_INS_CMOVLBC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovlbc $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVLBCr /* 292 */, Alpha_INS_CMOVLBC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovlbs $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVLBSi /* 293 */, Alpha_INS_CMOVLBS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovlbs $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVLBSr /* 294 */, Alpha_INS_CMOVLBS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovle $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVLEi /* 295 */, Alpha_INS_CMOVLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovle $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVLEr /* 296 */, Alpha_INS_CMOVLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovlt $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVLTi /* 297 */, Alpha_INS_CMOVLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovlt $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVLTr /* 298 */, Alpha_INS_CMOVLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovne $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVNEi /* 299 */, Alpha_INS_CMOVNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmovne $RCOND,$RTRUE,$RDEST */ + Alpha_CMOVNEr /* 300 */, Alpha_INS_CMOVNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmpbge $RA,$RB,$RC */ + Alpha_CMPBGE /* 301 */, Alpha_INS_CMPBGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmpbge $RA,$L,$RC */ + Alpha_CMPBGEi /* 302 */, Alpha_INS_CMPBGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmpeq $RA,$RB,$RC */ + Alpha_CMPEQ /* 303 */, Alpha_INS_CMPEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmpeq $RA,$L,$RC */ + Alpha_CMPEQi /* 304 */, Alpha_INS_CMPEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmple $RA,$RB,$RC */ + Alpha_CMPLE /* 305 */, Alpha_INS_CMPLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmple $RA,$L,$RC */ + Alpha_CMPLEi /* 306 */, Alpha_INS_CMPLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmplt $RA,$RB,$RC */ + Alpha_CMPLT /* 307 */, Alpha_INS_CMPLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmplt $RA,$L,$RC */ + Alpha_CMPLTi /* 308 */, Alpha_INS_CMPLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmpteq/su $RA,$RB,$RC */ + Alpha_CMPTEQ /* 309 */, Alpha_INS_CMPTEQsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmptle/su $RA,$RB,$RC */ + Alpha_CMPTLE /* 310 */, Alpha_INS_CMPTLEsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmptlt/su $RA,$RB,$RC */ + Alpha_CMPTLT /* 311 */, Alpha_INS_CMPTLTsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmptun/su $RA,$RB,$RC */ + Alpha_CMPTUN /* 312 */, Alpha_INS_CMPTUNsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmpule $RA,$RB,$RC */ + Alpha_CMPULE /* 313 */, Alpha_INS_CMPULE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmpule $RA,$L,$RC */ + Alpha_CMPULEi /* 314 */, Alpha_INS_CMPULE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmpult $RA,$RB,$RC */ + Alpha_CMPULT /* 315 */, Alpha_INS_CMPULT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cmpult $RA,$L,$RC */ + Alpha_CMPULTi /* 316 */, Alpha_INS_CMPULT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* COND_BRANCH imm:$opc, F8RC:$R, bb:$dst */ + Alpha_COND_BRANCH_F /* 317 */, Alpha_INS_COND_BRANCH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* COND_BRANCH imm:$opc, GPRC:$R, bb:$dst */ + Alpha_COND_BRANCH_I /* 318 */, Alpha_INS_COND_BRANCH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* cpyse $RA,$RB,$RC */ + Alpha_CPYSES /* 319 */, Alpha_INS_CPYSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cpyse $RA,$RB,$RC */ + Alpha_CPYSESt /* 320 */, Alpha_INS_CPYSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cpyse $RA,$RB,$RC */ + Alpha_CPYSET /* 321 */, Alpha_INS_CPYSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cpysn $RA,$RB,$RC */ + Alpha_CPYSNS /* 322 */, Alpha_INS_CPYSN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cpysn $RA,$RB,$RC */ + Alpha_CPYSNSt /* 323 */, Alpha_INS_CPYSN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cpysn $RA,$RB,$RC */ + Alpha_CPYSNT /* 324 */, Alpha_INS_CPYSN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cpysn $RA,$RB,$RC */ + Alpha_CPYSNTs /* 325 */, Alpha_INS_CPYSN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cpys $RA,$RB,$RC */ + Alpha_CPYSS /* 326 */, Alpha_INS_CPYS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cpys $RA,$RB,$RC */ + Alpha_CPYSSt /* 327 */, Alpha_INS_CPYS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cpys $RA,$RB,$RC */ + Alpha_CPYST /* 328 */, Alpha_INS_CPYS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cpys $RA,$RB,$RC */ + Alpha_CPYSTs /* 329 */, Alpha_INS_CPYS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ctlz $RB,$RC */ + Alpha_CTLZ /* 330 */, Alpha_INS_CTLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ctpop $RB,$RC */ + Alpha_CTPOP /* 331 */, Alpha_INS_CTPOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cttz $RB,$RC */ + Alpha_CTTZ /* 332 */, Alpha_INS_CTTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cvtqs/sui $RB,$RC */ + Alpha_CVTQS /* 333 */, Alpha_INS_CVTQSsSUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cvtqt/sui $RB,$RC */ + Alpha_CVTQT /* 334 */, Alpha_INS_CVTQTsSUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cvtst/s $RB,$RC */ + Alpha_CVTST /* 335 */, Alpha_INS_CVTSTsS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cvttq/svc $RB,$RC */ + Alpha_CVTTQ /* 336 */, Alpha_INS_CVTTQsSVC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* cvtts/sui $RB,$RC */ + Alpha_CVTTS /* 337 */, Alpha_INS_CVTTSsSUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* divs/su $RA,$RB,$RC */ + Alpha_DIVS /* 338 */, Alpha_INS_DIVSsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* divt/su $RA,$RB,$RC */ + Alpha_DIVT /* 339 */, Alpha_INS_DIVTsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ecb ($RB) */ + Alpha_ECB /* 340 */, Alpha_INS_ECB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* eqv $RA,$L,$RC */ + Alpha_EQVi /* 341 */, Alpha_INS_EQV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* eqv $RA,$RB,$RC */ + Alpha_EQVr /* 342 */, Alpha_INS_EQV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* excb */ + Alpha_EXCB /* 343 */, Alpha_INS_EXCB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extbl $RA,$RB,$RC */ + Alpha_EXTBL /* 344 */, Alpha_INS_EXTBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extbl $RA,$L,$RC */ + Alpha_EXTBLi /* 345 */, Alpha_INS_EXTBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extlh $RA,$RB,$RC */ + Alpha_EXTLH /* 346 */, Alpha_INS_EXTLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extlh $RA,$L,$RC */ + Alpha_EXTLHi /* 347 */, Alpha_INS_EXTLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extll $RA,$RB,$RC */ + Alpha_EXTLL /* 348 */, Alpha_INS_EXTLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extll $RA,$L,$RC */ + Alpha_EXTLLi /* 349 */, Alpha_INS_EXTLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extqh $RA,$RB,$RC */ + Alpha_EXTQH /* 350 */, Alpha_INS_EXTQH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extqh $RA,$L,$RC */ + Alpha_EXTQHi /* 351 */, Alpha_INS_EXTQH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extql $RA,$RB,$RC */ + Alpha_EXTQL /* 352 */, Alpha_INS_EXTQL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extql $RA,$L,$RC */ + Alpha_EXTQLi /* 353 */, Alpha_INS_EXTQL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extwh $RA,$RB,$RC */ + Alpha_EXTWH /* 354 */, Alpha_INS_EXTWH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extwh $RA,$L,$RC */ + Alpha_EXTWHi /* 355 */, Alpha_INS_EXTWH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extwl $RA,$RB,$RC */ + Alpha_EXTWL /* 356 */, Alpha_INS_EXTWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* extwl $RA,$L,$RC */ + Alpha_EXTWLi /* 357 */, Alpha_INS_EXTWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fbeq $R,$dst */ + Alpha_FBEQ /* 358 */, Alpha_INS_FBEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* fbge $R,$dst */ + Alpha_FBGE /* 359 */, Alpha_INS_FBGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* fbgt $R,$dst */ + Alpha_FBGT /* 360 */, Alpha_INS_FBGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* fble $R,$dst */ + Alpha_FBLE /* 361 */, Alpha_INS_FBLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* fblt $R,$dst */ + Alpha_FBLT /* 362 */, Alpha_INS_FBLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* fbne $R,$dst */ + Alpha_FBNE /* 363 */, Alpha_INS_FBNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, Alpha_GRP_BRANCH_RELATIVE, 0 }, 1, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmoveq $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVEQS /* 364 */, Alpha_INS_FCMOVEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmoveq $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVEQT /* 365 */, Alpha_INS_FCMOVEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmovge $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVGES /* 366 */, Alpha_INS_FCMOVGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmovge $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVGET /* 367 */, Alpha_INS_FCMOVGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmovgt $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVGTS /* 368 */, Alpha_INS_FCMOVGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmovgt $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVGTT /* 369 */, Alpha_INS_FCMOVGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmovle $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVLES /* 370 */, Alpha_INS_FCMOVLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmovle $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVLET /* 371 */, Alpha_INS_FCMOVLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmovlt $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVLTS /* 372 */, Alpha_INS_FCMOVLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmovlt $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVLTT /* 373 */, Alpha_INS_FCMOVLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmovne $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVNES /* 374 */, Alpha_INS_FCMOVNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fcmovne $RCOND,$RTRUE,$RDEST */ + Alpha_FCMOVNET /* 375 */, Alpha_INS_FCMOVNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fetch ($RB) */ + Alpha_FETCH /* 376 */, Alpha_INS_FETCH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* fetch_m ($RB) */ + Alpha_FETCH_M /* 377 */, Alpha_INS_FETCH_M, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ftois $RA,$RC */ + Alpha_FTOIS /* 378 */, Alpha_INS_FTOIS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ftoit $RA,$RC */ + Alpha_FTOIT /* 379 */, Alpha_INS_FTOIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* insbl $RA,$RB,$RC */ + Alpha_INSBL /* 380 */, Alpha_INS_INSBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* insbl $RA,$L,$RC */ + Alpha_INSBLi /* 381 */, Alpha_INS_INSBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* inslh $RA,$RB,$RC */ + Alpha_INSLH /* 382 */, Alpha_INS_INSLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* inslh $RA,$L,$RC */ + Alpha_INSLHi /* 383 */, Alpha_INS_INSLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* insll $RA,$RB,$RC */ + Alpha_INSLL /* 384 */, Alpha_INS_INSLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* insll $RA,$L,$RC */ + Alpha_INSLLi /* 385 */, Alpha_INS_INSLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* insqh $RA,$RB,$RC */ + Alpha_INSQH /* 386 */, Alpha_INS_INSQH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* insqh $RA,$L,$RC */ + Alpha_INSQHi /* 387 */, Alpha_INS_INSQH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* insql $RA,$RB,$RC */ + Alpha_INSQL /* 388 */, Alpha_INS_INSQL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* insql $RA,$L,$RC */ + Alpha_INSQLi /* 389 */, Alpha_INS_INSQL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* inswh $RA,$RB,$RC */ + Alpha_INSWH /* 390 */, Alpha_INS_INSWH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* inswh $RA,$L,$RC */ + Alpha_INSWHi /* 391 */, Alpha_INS_INSWH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* inswl $RA,$RB,$RC */ + Alpha_INSWL /* 392 */, Alpha_INS_INSWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* inswl $RA,$L,$RC */ + Alpha_INSWLi /* 393 */, Alpha_INS_INSWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* itofs $RA,$RC */ + Alpha_ITOFS /* 394 */, Alpha_INS_ITOFS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* itoft $RA,$RC */ + Alpha_ITOFT /* 395 */, Alpha_INS_ITOFT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* jmp $$31,{$RS},0 */ + Alpha_JMP /* 396 */, Alpha_INS_JMP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { Alpha_GRP_JUMP, 0 }, 1, 1, {{ 0 }}, + + #endif +}, +{ + /* jsr $$26,($$27),0 */ + Alpha_JSR /* 397 */, Alpha_INS_JSR, + #ifndef CAPSTONE_DIET + { Alpha_REG_R27, Alpha_REG_R29, 0 }, { Alpha_REG_R0, Alpha_REG_R1, Alpha_REG_R2, Alpha_REG_R3, Alpha_REG_R4, Alpha_REG_R5, Alpha_REG_R6, Alpha_REG_R7, Alpha_REG_R8, Alpha_REG_R16, Alpha_REG_R17, Alpha_REG_R18, Alpha_REG_R19, Alpha_REG_R20, Alpha_REG_R21, Alpha_REG_R22, Alpha_REG_R23, Alpha_REG_R24, Alpha_REG_R25, Alpha_REG_R26, Alpha_REG_R27, Alpha_REG_R28, Alpha_REG_R29, Alpha_REG_F0, Alpha_REG_F1, Alpha_REG_F10, Alpha_REG_F11, Alpha_REG_F12, Alpha_REG_F13, Alpha_REG_F14, Alpha_REG_F15, Alpha_REG_F16, Alpha_REG_F17, Alpha_REG_F18, Alpha_REG_F19, Alpha_REG_F20, Alpha_REG_F21, Alpha_REG_F22, Alpha_REG_F23, Alpha_REG_F24, Alpha_REG_F25, Alpha_REG_F26, Alpha_REG_F27, Alpha_REG_F28, Alpha_REG_F29, Alpha_REG_F30, 0 }, { Alpha_GRP_CALL, 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* jsr_coroutine $RD,($RS),$DISP */ + Alpha_JSR_COROUTINE /* 398 */, Alpha_INS_JSR_COROUTINE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* jsr $$23,($$27),0 */ + Alpha_JSRs /* 399 */, Alpha_INS_JSR, + #ifndef CAPSTONE_DIET + { Alpha_REG_R24, Alpha_REG_R25, Alpha_REG_R27, 0 }, { Alpha_REG_R23, Alpha_REG_R24, Alpha_REG_R25, Alpha_REG_R27, Alpha_REG_R28, 0 }, { Alpha_GRP_CALL, 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* lda $RA,$DISP($RB) */ + Alpha_LDA /* 400 */, Alpha_INS_LDA, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldah $RA,$DISP($RB) */ + Alpha_LDAH /* 401 */, Alpha_INS_LDAH, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldah $RA,0($RB) !gpdisp!$NUM */ + Alpha_LDAHg /* 402 */, Alpha_INS_LDAH, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldah $RA,$DISP($RB) !gprelhigh */ + Alpha_LDAHr /* 403 */, Alpha_INS_LDAH, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* lda $RA,0($RB) !gpdisp!$NUM */ + Alpha_LDAg /* 404 */, Alpha_INS_LDA, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* lda $RA,$DISP($RB) !gprellow */ + Alpha_LDAr /* 405 */, Alpha_INS_LDA, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldbu $RA,$DISP($RB) */ + Alpha_LDBU /* 406 */, Alpha_INS_LDBU, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldbu $RA,$DISP($RB) !gprellow */ + Alpha_LDBUr /* 407 */, Alpha_INS_LDBU, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldl $RA,$DISP($RB) */ + Alpha_LDL /* 408 */, Alpha_INS_LDL, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldl_l $RA,$DISP($RB) */ + Alpha_LDL_L /* 409 */, Alpha_INS_LDL_L, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldl $RA,$DISP($RB) !gprellow */ + Alpha_LDLr /* 410 */, Alpha_INS_LDL, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldq $RA,$DISP($RB) */ + Alpha_LDQ /* 411 */, Alpha_INS_LDQ, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldq_l $RA,$DISP($RB) */ + Alpha_LDQ_L /* 412 */, Alpha_INS_LDQ_L, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldq_u $RA,$DISP($RB) */ + Alpha_LDQ_U /* 413 */, Alpha_INS_LDQ_U, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldq $RA,$DISP($RB) !literal */ + Alpha_LDQl /* 414 */, Alpha_INS_LDQ, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldq $RA,$DISP($RB) !gprellow */ + Alpha_LDQr /* 415 */, Alpha_INS_LDQ, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* lds $RA,$DISP($RB) */ + Alpha_LDS /* 416 */, Alpha_INS_LDS, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* lds $RA,$DISP($RB) !gprellow */ + Alpha_LDSr /* 417 */, Alpha_INS_LDS, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldt $RA,$DISP($RB) */ + Alpha_LDT /* 418 */, Alpha_INS_LDT, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldt $RA,$DISP($RB) !gprellow */ + Alpha_LDTr /* 419 */, Alpha_INS_LDT, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldwu $RA,$DISP($RB) */ + Alpha_LDWU /* 420 */, Alpha_INS_LDWU, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ldwu $RA,$DISP($RB) !gprellow */ + Alpha_LDWUr /* 421 */, Alpha_INS_LDWU, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mb */ + Alpha_MB /* 422 */, Alpha_INS_MB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskbl $RA,$RB,$RC */ + Alpha_MSKBL /* 423 */, Alpha_INS_MSKBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskbl $RA,$L,$RC */ + Alpha_MSKBLi /* 424 */, Alpha_INS_MSKBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* msklh $RA,$RB,$RC */ + Alpha_MSKLH /* 425 */, Alpha_INS_MSKLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* msklh $RA,$L,$RC */ + Alpha_MSKLHi /* 426 */, Alpha_INS_MSKLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskll $RA,$RB,$RC */ + Alpha_MSKLL /* 427 */, Alpha_INS_MSKLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskll $RA,$L,$RC */ + Alpha_MSKLLi /* 428 */, Alpha_INS_MSKLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskqh $RA,$RB,$RC */ + Alpha_MSKQH /* 429 */, Alpha_INS_MSKQH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskqh $RA,$L,$RC */ + Alpha_MSKQHi /* 430 */, Alpha_INS_MSKQH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskql $RA,$RB,$RC */ + Alpha_MSKQL /* 431 */, Alpha_INS_MSKQL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskql $RA,$L,$RC */ + Alpha_MSKQLi /* 432 */, Alpha_INS_MSKQL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskwh $RA,$RB,$RC */ + Alpha_MSKWH /* 433 */, Alpha_INS_MSKWH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskwh $RA,$L,$RC */ + Alpha_MSKWHi /* 434 */, Alpha_INS_MSKWH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskwl $RA,$RB,$RC */ + Alpha_MSKWL /* 435 */, Alpha_INS_MSKWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mskwl $RA,$L,$RC */ + Alpha_MSKWLi /* 436 */, Alpha_INS_MSKWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mull $RA,$L,$RC */ + Alpha_MULLi /* 437 */, Alpha_INS_MULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mull $RA,$RB,$RC */ + Alpha_MULLr /* 438 */, Alpha_INS_MULL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mulq $RA,$L,$RC */ + Alpha_MULQi /* 439 */, Alpha_INS_MULQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mulq $RA,$RB,$RC */ + Alpha_MULQr /* 440 */, Alpha_INS_MULQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* muls/su $RA,$RB,$RC */ + Alpha_MULS /* 441 */, Alpha_INS_MULSsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* mult/su $RA,$RB,$RC */ + Alpha_MULT /* 442 */, Alpha_INS_MULTsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ornot $RA,$L,$RC */ + Alpha_ORNOTi /* 443 */, Alpha_INS_ORNOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ornot $RA,$RB,$RC */ + Alpha_ORNOTr /* 444 */, Alpha_INS_ORNOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* rc $RA */ + Alpha_RC /* 445 */, Alpha_INS_RC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ret $$31,($$26),1 */ + Alpha_RETDAG /* 446 */, Alpha_INS_RET, + #ifndef CAPSTONE_DIET + { Alpha_REG_R26, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* ret $$31,($$26),1 */ + Alpha_RETDAGp /* 447 */, Alpha_INS_RET, + #ifndef CAPSTONE_DIET + { Alpha_REG_R26, 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* rpcc $RA */ + Alpha_RPCC /* 448 */, Alpha_INS_RPCC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* rs $RA */ + Alpha_RS /* 449 */, Alpha_INS_RS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s4addl $RA,$L,$RC */ + Alpha_S4ADDLi /* 450 */, Alpha_INS_S4ADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s4addl $RA,$RB,$RC */ + Alpha_S4ADDLr /* 451 */, Alpha_INS_S4ADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s4addq $RA,$L,$RC */ + Alpha_S4ADDQi /* 452 */, Alpha_INS_S4ADDQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s4addq $RA,$RB,$RC */ + Alpha_S4ADDQr /* 453 */, Alpha_INS_S4ADDQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s4subl $RA,$L,$RC */ + Alpha_S4SUBLi /* 454 */, Alpha_INS_S4SUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s4subl $RA,$RB,$RC */ + Alpha_S4SUBLr /* 455 */, Alpha_INS_S4SUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s4subq $RA,$L,$RC */ + Alpha_S4SUBQi /* 456 */, Alpha_INS_S4SUBQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s4subq $RA,$RB,$RC */ + Alpha_S4SUBQr /* 457 */, Alpha_INS_S4SUBQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s8addl $RA,$L,$RC */ + Alpha_S8ADDLi /* 458 */, Alpha_INS_S8ADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s8addl $RA,$RB,$RC */ + Alpha_S8ADDLr /* 459 */, Alpha_INS_S8ADDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s8addq $RA,$L,$RC */ + Alpha_S8ADDQi /* 460 */, Alpha_INS_S8ADDQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s8addq $RA,$RB,$RC */ + Alpha_S8ADDQr /* 461 */, Alpha_INS_S8ADDQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s8subl $RA,$L,$RC */ + Alpha_S8SUBLi /* 462 */, Alpha_INS_S8SUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s8subl $RA,$RB,$RC */ + Alpha_S8SUBLr /* 463 */, Alpha_INS_S8SUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s8subq $RA,$L,$RC */ + Alpha_S8SUBQi /* 464 */, Alpha_INS_S8SUBQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* s8subq $RA,$RB,$RC */ + Alpha_S8SUBQr /* 465 */, Alpha_INS_S8SUBQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* sextb $RB,$RC */ + Alpha_SEXTB /* 466 */, Alpha_INS_SEXTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* sextw $RB,$RC */ + Alpha_SEXTW /* 467 */, Alpha_INS_SEXTW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* sll $RA,$L,$RC */ + Alpha_SLi /* 468 */, Alpha_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* sll $RA,$RB,$RC */ + Alpha_SLr /* 469 */, Alpha_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* sqrts/su $RB,$RC */ + Alpha_SQRTS /* 470 */, Alpha_INS_SQRTSsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* sqrtt/su $RB,$RC */ + Alpha_SQRTT /* 471 */, Alpha_INS_SQRTTsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* sra $RA,$L,$RC */ + Alpha_SRAi /* 472 */, Alpha_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* sra $RA,$RB,$RC */ + Alpha_SRAr /* 473 */, Alpha_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* srl $RA,$L,$RC */ + Alpha_SRLi /* 474 */, Alpha_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* srl $RA,$RB,$RC */ + Alpha_SRLr /* 475 */, Alpha_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stb $RA, $DISP($RB) */ + Alpha_STB /* 476 */, Alpha_INS_STB, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stb $RA,$DISP($RB) !gprellow */ + Alpha_STBr /* 477 */, Alpha_INS_STB, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stl $RA,$DISP($RB) */ + Alpha_STL /* 478 */, Alpha_INS_STL, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stl_c $RA,$DISP($RB) */ + Alpha_STL_C /* 479 */, Alpha_INS_STL_C, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stl $RA,$DISP($RB) !gprellow */ + Alpha_STLr /* 480 */, Alpha_INS_STL, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stq $RA,$DISP($RB) */ + Alpha_STQ /* 481 */, Alpha_INS_STQ, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stq_c $RA,$DISP($RB) */ + Alpha_STQ_C /* 482 */, Alpha_INS_STQ_C, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stq_u $RA, $DISP($RB) */ + Alpha_STQ_U /* 483 */, Alpha_INS_STQ_U, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stq $RA,$DISP($RB) !gprellow */ + Alpha_STQr /* 484 */, Alpha_INS_STQ, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* sts $RA,$DISP($RB) */ + Alpha_STS /* 485 */, Alpha_INS_STS, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* sts $RA,$DISP($RB) !gprellow */ + Alpha_STSr /* 486 */, Alpha_INS_STS, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stt $RA,$DISP($RB) */ + Alpha_STT /* 487 */, Alpha_INS_STT, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stt $RA,$DISP($RB) !gprellow */ + Alpha_STTr /* 488 */, Alpha_INS_STT, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stw $RA,$DISP($RB) */ + Alpha_STW /* 489 */, Alpha_INS_STW, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* stw $RA,$DISP($RB) !gprellow */ + Alpha_STWr /* 490 */, Alpha_INS_STW, + #ifndef CAPSTONE_DIET + { 0 }, { Alpha_REG_R28, 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* subl $RA,$L,$RC */ + Alpha_SUBLi /* 491 */, Alpha_INS_SUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* subl $RA,$RB,$RC */ + Alpha_SUBLr /* 492 */, Alpha_INS_SUBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* subq $RA,$L,$RC */ + Alpha_SUBQi /* 493 */, Alpha_INS_SUBQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* subq $RA,$RB,$RC */ + Alpha_SUBQr /* 494 */, Alpha_INS_SUBQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* subs/su $RA,$RB,$RC */ + Alpha_SUBS /* 495 */, Alpha_INS_SUBSsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* subt/su $RA,$RB,$RC */ + Alpha_SUBT /* 496 */, Alpha_INS_SUBTsSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* trapb */ + Alpha_TRAPB /* 497 */, Alpha_INS_TRAPB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* umulh $RA,$L,$RC */ + Alpha_UMULHi /* 498 */, Alpha_INS_UMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* umulh $RA,$RB,$RC */ + Alpha_UMULHr /* 499 */, Alpha_INS_UMULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* wh64 ($RB) */ + Alpha_WH64 /* 500 */, Alpha_INS_WH64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* wh64en ($RB) */ + Alpha_WH64EN /* 501 */, Alpha_INS_WH64EN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* wmb */ + Alpha_WMB /* 502 */, Alpha_INS_WMB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* xor $RA,$L,$RC */ + Alpha_XORi /* 503 */, Alpha_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* xor $RA,$RB,$RC */ + Alpha_XORr /* 504 */, Alpha_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, +{ + /* zapnot $RA,$L,$RC */ + Alpha_ZAPNOTi /* 505 */, Alpha_INS_ZAPNOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, + + #endif +}, diff --git a/arch/Alpha/AlphaGenCSMappingInsnName.inc b/arch/Alpha/AlphaGenCSMappingInsnName.inc new file mode 100644 index 0000000000..b934548c9c --- /dev/null +++ b/arch/Alpha/AlphaGenCSMappingInsnName.inc @@ -0,0 +1,164 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */ +/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + "invalid", // Alpha_INS_INVALID + "addl", // Alpha_INS_ADDL + "addq", // Alpha_INS_ADDQ + "adds/su", // Alpha_INS_ADDSsSU + "addt/su", // Alpha_INS_ADDTsSU + "and", // Alpha_INS_AND + "beq", // Alpha_INS_BEQ + "bge", // Alpha_INS_BGE + "bgt", // Alpha_INS_BGT + "bic", // Alpha_INS_BIC + "bis", // Alpha_INS_BIS + "blbc", // Alpha_INS_BLBC + "blbs", // Alpha_INS_BLBS + "ble", // Alpha_INS_BLE + "blt", // Alpha_INS_BLT + "bne", // Alpha_INS_BNE + "br", // Alpha_INS_BR + "bsr", // Alpha_INS_BSR + "cmoveq", // Alpha_INS_CMOVEQ + "cmovge", // Alpha_INS_CMOVGE + "cmovgt", // Alpha_INS_CMOVGT + "cmovlbc", // Alpha_INS_CMOVLBC + "cmovlbs", // Alpha_INS_CMOVLBS + "cmovle", // Alpha_INS_CMOVLE + "cmovlt", // Alpha_INS_CMOVLT + "cmovne", // Alpha_INS_CMOVNE + "cmpbge", // Alpha_INS_CMPBGE + "cmpeq", // Alpha_INS_CMPEQ + "cmple", // Alpha_INS_CMPLE + "cmplt", // Alpha_INS_CMPLT + "cmpteq/su", // Alpha_INS_CMPTEQsSU + "cmptle/su", // Alpha_INS_CMPTLEsSU + "cmptlt/su", // Alpha_INS_CMPTLTsSU + "cmptun/su", // Alpha_INS_CMPTUNsSU + "cmpule", // Alpha_INS_CMPULE + "cmpult", // Alpha_INS_CMPULT + "COND_BRANCH", // Alpha_INS_COND_BRANCH + "cpyse", // Alpha_INS_CPYSE + "cpysn", // Alpha_INS_CPYSN + "cpys", // Alpha_INS_CPYS + "ctlz", // Alpha_INS_CTLZ + "ctpop", // Alpha_INS_CTPOP + "cttz", // Alpha_INS_CTTZ + "cvtqs/sui", // Alpha_INS_CVTQSsSUI + "cvtqt/sui", // Alpha_INS_CVTQTsSUI + "cvtst/s", // Alpha_INS_CVTSTsS + "cvttq/svc", // Alpha_INS_CVTTQsSVC + "cvtts/sui", // Alpha_INS_CVTTSsSUI + "divs/su", // Alpha_INS_DIVSsSU + "divt/su", // Alpha_INS_DIVTsSU + "ecb", // Alpha_INS_ECB + "eqv", // Alpha_INS_EQV + "excb", // Alpha_INS_EXCB + "extbl", // Alpha_INS_EXTBL + "extlh", // Alpha_INS_EXTLH + "extll", // Alpha_INS_EXTLL + "extqh", // Alpha_INS_EXTQH + "extql", // Alpha_INS_EXTQL + "extwh", // Alpha_INS_EXTWH + "extwl", // Alpha_INS_EXTWL + "fbeq", // Alpha_INS_FBEQ + "fbge", // Alpha_INS_FBGE + "fbgt", // Alpha_INS_FBGT + "fble", // Alpha_INS_FBLE + "fblt", // Alpha_INS_FBLT + "fbne", // Alpha_INS_FBNE + "fcmoveq", // Alpha_INS_FCMOVEQ + "fcmovge", // Alpha_INS_FCMOVGE + "fcmovgt", // Alpha_INS_FCMOVGT + "fcmovle", // Alpha_INS_FCMOVLE + "fcmovlt", // Alpha_INS_FCMOVLT + "fcmovne", // Alpha_INS_FCMOVNE + "fetch", // Alpha_INS_FETCH + "fetch_m", // Alpha_INS_FETCH_M + "ftois", // Alpha_INS_FTOIS + "ftoit", // Alpha_INS_FTOIT + "insbl", // Alpha_INS_INSBL + "inslh", // Alpha_INS_INSLH + "insll", // Alpha_INS_INSLL + "insqh", // Alpha_INS_INSQH + "insql", // Alpha_INS_INSQL + "inswh", // Alpha_INS_INSWH + "inswl", // Alpha_INS_INSWL + "itofs", // Alpha_INS_ITOFS + "itoft", // Alpha_INS_ITOFT + "jmp", // Alpha_INS_JMP + "jsr", // Alpha_INS_JSR + "jsr_coroutine", // Alpha_INS_JSR_COROUTINE + "lda", // Alpha_INS_LDA + "ldah", // Alpha_INS_LDAH + "ldbu", // Alpha_INS_LDBU + "ldl", // Alpha_INS_LDL + "ldl_l", // Alpha_INS_LDL_L + "ldq", // Alpha_INS_LDQ + "ldq_l", // Alpha_INS_LDQ_L + "ldq_u", // Alpha_INS_LDQ_U + "lds", // Alpha_INS_LDS + "ldt", // Alpha_INS_LDT + "ldwu", // Alpha_INS_LDWU + "mb", // Alpha_INS_MB + "mskbl", // Alpha_INS_MSKBL + "msklh", // Alpha_INS_MSKLH + "mskll", // Alpha_INS_MSKLL + "mskqh", // Alpha_INS_MSKQH + "mskql", // Alpha_INS_MSKQL + "mskwh", // Alpha_INS_MSKWH + "mskwl", // Alpha_INS_MSKWL + "mull", // Alpha_INS_MULL + "mulq", // Alpha_INS_MULQ + "muls/su", // Alpha_INS_MULSsSU + "mult/su", // Alpha_INS_MULTsSU + "ornot", // Alpha_INS_ORNOT + "rc", // Alpha_INS_RC + "ret", // Alpha_INS_RET + "rpcc", // Alpha_INS_RPCC + "rs", // Alpha_INS_RS + "s4addl", // Alpha_INS_S4ADDL + "s4addq", // Alpha_INS_S4ADDQ + "s4subl", // Alpha_INS_S4SUBL + "s4subq", // Alpha_INS_S4SUBQ + "s8addl", // Alpha_INS_S8ADDL + "s8addq", // Alpha_INS_S8ADDQ + "s8subl", // Alpha_INS_S8SUBL + "s8subq", // Alpha_INS_S8SUBQ + "sextb", // Alpha_INS_SEXTB + "sextw", // Alpha_INS_SEXTW + "sll", // Alpha_INS_SLL + "sqrts/su", // Alpha_INS_SQRTSsSU + "sqrtt/su", // Alpha_INS_SQRTTsSU + "sra", // Alpha_INS_SRA + "srl", // Alpha_INS_SRL + "stb", // Alpha_INS_STB + "stl", // Alpha_INS_STL + "stl_c", // Alpha_INS_STL_C + "stq", // Alpha_INS_STQ + "stq_c", // Alpha_INS_STQ_C + "stq_u", // Alpha_INS_STQ_U + "sts", // Alpha_INS_STS + "stt", // Alpha_INS_STT + "stw", // Alpha_INS_STW + "subl", // Alpha_INS_SUBL + "subq", // Alpha_INS_SUBQ + "subs/su", // Alpha_INS_SUBSsSU + "subt/su", // Alpha_INS_SUBTsSU + "trapb", // Alpha_INS_TRAPB + "umulh", // Alpha_INS_UMULH + "wh64", // Alpha_INS_WH64 + "wh64en", // Alpha_INS_WH64EN + "wmb", // Alpha_INS_WMB + "xor", // Alpha_INS_XOR + "zapnot", // Alpha_INS_ZAPNOT diff --git a/arch/Alpha/AlphaGenCSMappingInsnOp.inc b/arch/Alpha/AlphaGenCSMappingInsnOp.inc new file mode 100644 index 0000000000..6f2772dde8 --- /dev/null +++ b/arch/Alpha/AlphaGenCSMappingInsnOp.inc @@ -0,0 +1,2467 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */ +/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{{{ /* Alpha_PHI (0) - Alpha_INS_INVALID - PHINODE */ + 0 +}}}, +{{{ /* Alpha_INLINEASM (1) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_INLINEASM_BR (2) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_CFI_INSTRUCTION (3) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_EH_LABEL (4) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_GC_LABEL (5) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_ANNOTATION_LABEL (6) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_KILL (7) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_EXTRACT_SUBREG (8) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_INSERT_SUBREG (9) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_IMPLICIT_DEF (10) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_SUBREG_TO_REG (11) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_COPY_TO_REGCLASS (12) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_DBG_VALUE (13) - Alpha_INS_INVALID - DBG_VALUE */ + 0 +}}}, +{{{ /* Alpha_DBG_VALUE_LIST (14) - Alpha_INS_INVALID - DBG_VALUE_LIST */ + 0 +}}}, +{{{ /* Alpha_DBG_INSTR_REF (15) - Alpha_INS_INVALID - DBG_INSTR_REF */ + 0 +}}}, +{{{ /* Alpha_DBG_PHI (16) - Alpha_INS_INVALID - DBG_PHI */ + 0 +}}}, +{{{ /* Alpha_DBG_LABEL (17) - Alpha_INS_INVALID - DBG_LABEL */ + 0 +}}}, +{{{ /* Alpha_REG_SEQUENCE (18) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_COPY (19) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_BUNDLE (20) - Alpha_INS_INVALID - BUNDLE */ + 0 +}}}, +{{{ /* Alpha_LIFETIME_START (21) - Alpha_INS_INVALID - LIFETIME_START */ + 0 +}}}, +{{{ /* Alpha_LIFETIME_END (22) - Alpha_INS_INVALID - LIFETIME_END */ + 0 +}}}, +{{{ /* Alpha_PSEUDO_PROBE (23) - Alpha_INS_INVALID - PSEUDO_PROBE */ + 0 +}}}, +{{{ /* Alpha_ARITH_FENCE (24) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_STACKMAP (25) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_FENTRY_CALL (26) - Alpha_INS_INVALID - # FEntry call */ + 0 +}}}, +{{{ /* Alpha_PATCHPOINT (27) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_LOAD_STACK_GUARD (28) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_PREALLOCATED_SETUP (29) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_PREALLOCATED_ARG (30) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_STATEPOINT (31) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_LOCAL_ESCAPE (32) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_FAULTING_OP (33) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_PATCHABLE_OP (34) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_PATCHABLE_FUNCTION_ENTER (35) - Alpha_INS_INVALID - # XRay Function Enter. */ + 0 +}}}, +{{{ /* Alpha_PATCHABLE_RET (36) - Alpha_INS_INVALID - # XRay Function Patchable RET. */ + 0 +}}}, +{{{ /* Alpha_PATCHABLE_FUNCTION_EXIT (37) - Alpha_INS_INVALID - # XRay Function Exit. */ + 0 +}}}, +{{{ /* Alpha_PATCHABLE_TAIL_CALL (38) - Alpha_INS_INVALID - # XRay Tail Call Exit. */ + 0 +}}}, +{{{ /* Alpha_PATCHABLE_EVENT_CALL (39) - Alpha_INS_INVALID - # XRay Custom Event Log. */ + 0 +}}}, +{{{ /* Alpha_PATCHABLE_TYPED_EVENT_CALL (40) - Alpha_INS_INVALID - # XRay Typed Event Log. */ + 0 +}}}, +{{{ /* Alpha_ICALL_BRANCH_FUNNEL (41) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_MEMBARRIER (42) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_ASSERT_SEXT (43) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_ASSERT_ZEXT (44) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_ASSERT_ALIGN (45) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_ADD (46) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_SUB (47) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_MUL (48) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_SDIV (49) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_UDIV (50) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_SREM (51) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_UREM (52) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_SDIVREM (53) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_UDIVREM (54) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_AND (55) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_OR (56) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_XOR (57) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_IMPLICIT_DEF (58) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_PHI (59) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_FRAME_INDEX (60) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_GLOBAL_VALUE (61) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_EXTRACT (62) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_UNMERGE_VALUES (63) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_INSERT (64) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_MERGE_VALUES (65) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_BUILD_VECTOR (66) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_BUILD_VECTOR_TRUNC (67) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_CONCAT_VECTORS (68) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_PTRTOINT (69) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_INTTOPTR (70) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_BITCAST (71) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_FREEZE (72) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_INTRINSIC_FPTRUNC_ROUND (73) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_INTRINSIC_TRUNC (74) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_INTRINSIC_ROUND (75) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_INTRINSIC_LRINT (76) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_INTRINSIC_ROUNDEVEN (77) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_READCYCLECOUNTER (78) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_LOAD (79) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_SEXTLOAD (80) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_ZEXTLOAD (81) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_INDEXED_LOAD (82) - Alpha_INS_INVALID - */ + 0 +}}}, +{{{ /* Alpha_G_INDEXED_SEXTLOAD (83) - Alpha_INS_INVALID - */ + 0 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#wtf */ + 0 +}}}, +{ /* Alpha_ADDLi (263) - Alpha_INS_ADDL - addl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_ADDLr (264) - Alpha_INS_ADDL - addl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_ADDQi (265) - Alpha_INS_ADDQ - addq $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_ADDQr (266) - Alpha_INS_ADDQ - addq $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_ADDS (267) - Alpha_INS_ADDSsSU - adds/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_ADDT (268) - Alpha_INS_ADDTsSU - addt/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_ANDi (269) - Alpha_INS_AND - and $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_ANDr (270) - Alpha_INS_AND - and $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_BEQ (271) - Alpha_INS_BEQ - beq $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_BGE (272) - Alpha_INS_BGE - bge $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_BGT (273) - Alpha_INS_BGT - bgt $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_BICi (274) - Alpha_INS_BIC - bic $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_BICr (275) - Alpha_INS_BIC - bic $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_BISi (276) - Alpha_INS_BIS - bis $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_BISr (277) - Alpha_INS_BIS - bis $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_BLBC (278) - Alpha_INS_BLBC - blbc $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_BLBS (279) - Alpha_INS_BLBS - blbs $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_BLE (280) - Alpha_INS_BLE - ble $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_BLT (281) - Alpha_INS_BLT - blt $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_BNE (282) - Alpha_INS_BNE - bne $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_BR (283) - Alpha_INS_BR - br $$31,$DISP */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* DISP */ + { 0 } +}}, +{ /* Alpha_BSR (284) - Alpha_INS_BSR - bsr $$26,$$$DISP ..ng */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* DISP */ + { 0 } +}}, +{ /* Alpha_CMOVEQi (285) - Alpha_INS_CMOVEQ - cmoveq $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVEQr (286) - Alpha_INS_CMOVEQ - cmoveq $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVGEi (287) - Alpha_INS_CMOVGE - cmovge $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVGEr (288) - Alpha_INS_CMOVGE - cmovge $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVGTi (289) - Alpha_INS_CMOVGT - cmovgt $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVGTr (290) - Alpha_INS_CMOVGT - cmovgt $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVLBCi (291) - Alpha_INS_CMOVLBC - cmovlbc $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVLBCr (292) - Alpha_INS_CMOVLBC - cmovlbc $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVLBSi (293) - Alpha_INS_CMOVLBS - cmovlbs $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVLBSr (294) - Alpha_INS_CMOVLBS - cmovlbs $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVLEi (295) - Alpha_INS_CMOVLE - cmovle $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVLEr (296) - Alpha_INS_CMOVLE - cmovle $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVLTi (297) - Alpha_INS_CMOVLT - cmovlt $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVLTr (298) - Alpha_INS_CMOVLT - cmovlt $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVNEi (299) - Alpha_INS_CMOVNE - cmovne $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMOVNEr (300) - Alpha_INS_CMOVNE - cmovne $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { 0 } +}}, +{ /* Alpha_CMPBGE (301) - Alpha_INS_CMPBGE - cmpbge $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CMPBGEi (302) - Alpha_INS_CMPBGE - cmpbge $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_CMPEQ (303) - Alpha_INS_CMPEQ - cmpeq $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CMPEQi (304) - Alpha_INS_CMPEQ - cmpeq $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_CMPLE (305) - Alpha_INS_CMPLE - cmple $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CMPLEi (306) - Alpha_INS_CMPLE - cmple $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_CMPLT (307) - Alpha_INS_CMPLT - cmplt $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CMPLTi (308) - Alpha_INS_CMPLT - cmplt $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_CMPTEQ (309) - Alpha_INS_CMPTEQsSU - cmpteq/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CMPTLE (310) - Alpha_INS_CMPTLEsSU - cmptle/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CMPTLT (311) - Alpha_INS_CMPTLTsSU - cmptlt/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CMPTUN (312) - Alpha_INS_CMPTUNsSU - cmptun/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CMPULE (313) - Alpha_INS_CMPULE - cmpule $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CMPULEi (314) - Alpha_INS_CMPULE - cmpule $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_CMPULT (315) - Alpha_INS_CMPULT - cmpult $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CMPULTi (316) - Alpha_INS_CMPULT - cmpult $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_COND_BRANCH_F (317) - Alpha_INS_COND_BRANCH - COND_BRANCH imm:$opc, F8RC:$R, bb:$dst */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* opc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_COND_BRANCH_I (318) - Alpha_INS_COND_BRANCH - COND_BRANCH imm:$opc, GPRC:$R, bb:$dst */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* opc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_CPYSES (319) - Alpha_INS_CPYSE - cpyse $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CPYSESt (320) - Alpha_INS_CPYSE - cpyse $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CPYSET (321) - Alpha_INS_CPYSE - cpyse $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CPYSNS (322) - Alpha_INS_CPYSN - cpysn $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CPYSNSt (323) - Alpha_INS_CPYSN - cpysn $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CPYSNT (324) - Alpha_INS_CPYSN - cpysn $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CPYSNTs (325) - Alpha_INS_CPYSN - cpysn $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CPYSS (326) - Alpha_INS_CPYS - cpys $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CPYSSt (327) - Alpha_INS_CPYS - cpys $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CPYST (328) - Alpha_INS_CPYS - cpys $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CPYSTs (329) - Alpha_INS_CPYS - cpys $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CTLZ (330) - Alpha_INS_CTLZ - ctlz $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CTPOP (331) - Alpha_INS_CTPOP - ctpop $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CTTZ (332) - Alpha_INS_CTTZ - cttz $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CVTQS (333) - Alpha_INS_CVTQSsSUI - cvtqs/sui $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CVTQT (334) - Alpha_INS_CVTQTsSUI - cvtqt/sui $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CVTST (335) - Alpha_INS_CVTSTsS - cvtst/s $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CVTTQ (336) - Alpha_INS_CVTTQsSVC - cvttq/svc $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_CVTTS (337) - Alpha_INS_CVTTSsSUI - cvtts/sui $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_DIVS (338) - Alpha_INS_DIVSsSU - divs/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_DIVT (339) - Alpha_INS_DIVTsSU - divt/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_ECB (340) - Alpha_INS_ECB - ecb ($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_EQVi (341) - Alpha_INS_EQV - eqv $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_EQVr (342) - Alpha_INS_EQV - eqv $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_EXCB (343) - Alpha_INS_EXCB - excb */ +{ + { 0 } +}}, +{ /* Alpha_EXTBL (344) - Alpha_INS_EXTBL - extbl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_EXTBLi (345) - Alpha_INS_EXTBL - extbl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_EXTLH (346) - Alpha_INS_EXTLH - extlh $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_EXTLHi (347) - Alpha_INS_EXTLH - extlh $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_EXTLL (348) - Alpha_INS_EXTLL - extll $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_EXTLLi (349) - Alpha_INS_EXTLL - extll $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_EXTQH (350) - Alpha_INS_EXTQH - extqh $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_EXTQHi (351) - Alpha_INS_EXTQH - extqh $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_EXTQL (352) - Alpha_INS_EXTQL - extql $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_EXTQLi (353) - Alpha_INS_EXTQL - extql $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_EXTWH (354) - Alpha_INS_EXTWH - extwh $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_EXTWHi (355) - Alpha_INS_EXTWH - extwh $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_EXTWL (356) - Alpha_INS_EXTWL - extwl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_EXTWLi (357) - Alpha_INS_EXTWL - extwl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_FBEQ (358) - Alpha_INS_FBEQ - fbeq $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_FBGE (359) - Alpha_INS_FBGE - fbge $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_FBGT (360) - Alpha_INS_FBGT - fbgt $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_FBLE (361) - Alpha_INS_FBLE - fble $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_FBLT (362) - Alpha_INS_FBLT - fblt $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_FBNE (363) - Alpha_INS_FBNE - fbne $R,$dst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* R */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* dst */ + { 0 } +}}, +{ /* Alpha_FCMOVEQS (364) - Alpha_INS_FCMOVEQ - fcmoveq $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVEQT (365) - Alpha_INS_FCMOVEQ - fcmoveq $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVGES (366) - Alpha_INS_FCMOVGE - fcmovge $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVGET (367) - Alpha_INS_FCMOVGE - fcmovge $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVGTS (368) - Alpha_INS_FCMOVGT - fcmovgt $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVGTT (369) - Alpha_INS_FCMOVGT - fcmovgt $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVLES (370) - Alpha_INS_FCMOVLE - fcmovle $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVLET (371) - Alpha_INS_FCMOVLE - fcmovle $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVLTS (372) - Alpha_INS_FCMOVLT - fcmovlt $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVLTT (373) - Alpha_INS_FCMOVLT - fcmovlt $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVNES (374) - Alpha_INS_FCMOVNE - fcmovne $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FCMOVNET (375) - Alpha_INS_FCMOVNE - fcmovne $RCOND,$RTRUE,$RDEST */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RDEST */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RFALSE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RTRUE */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RCOND */ + { 0 } +}}, +{ /* Alpha_FETCH (376) - Alpha_INS_FETCH - fetch ($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_FETCH_M (377) - Alpha_INS_FETCH_M - fetch_m ($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_FTOIS (378) - Alpha_INS_FTOIS - ftois $RA,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { 0 } +}}, +{ /* Alpha_FTOIT (379) - Alpha_INS_FTOIT - ftoit $RA,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { 0 } +}}, +{ /* Alpha_INSBL (380) - Alpha_INS_INSBL - insbl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_INSBLi (381) - Alpha_INS_INSBL - insbl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_INSLH (382) - Alpha_INS_INSLH - inslh $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_INSLHi (383) - Alpha_INS_INSLH - inslh $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_INSLL (384) - Alpha_INS_INSLL - insll $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_INSLLi (385) - Alpha_INS_INSLL - insll $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_INSQH (386) - Alpha_INS_INSQH - insqh $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_INSQHi (387) - Alpha_INS_INSQH - insqh $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_INSQL (388) - Alpha_INS_INSQL - insql $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_INSQLi (389) - Alpha_INS_INSQL - insql $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_INSWH (390) - Alpha_INS_INSWH - inswh $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_INSWHi (391) - Alpha_INS_INSWH - inswh $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_INSWL (392) - Alpha_INS_INSWL - inswl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_INSWLi (393) - Alpha_INS_INSWL - inswl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_ITOFS (394) - Alpha_INS_ITOFS - itofs $RA,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { 0 } +}}, +{ /* Alpha_ITOFT (395) - Alpha_INS_ITOFT - itoft $RA,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { 0 } +}}, +{ /* Alpha_JMP (396) - Alpha_INS_JMP - jmp $$31,{$RS},0 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RS */ + { 0 } +}}, +{ /* Alpha_JSR (397) - Alpha_INS_JSR - jsr $$26,($$27),0 */ +{ + { 0 } +}}, +{ /* Alpha_JSR_COROUTINE (398) - Alpha_INS_JSR_COROUTINE - jsr_coroutine $RD,($RS),$DISP */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RD */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RS */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { 0 } +}}, +{ /* Alpha_JSRs (399) - Alpha_INS_JSR - jsr $$23,($$27),0 */ +{ + { 0 } +}}, +{ /* Alpha_LDA (400) - Alpha_INS_LDA - lda $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDAH (401) - Alpha_INS_LDAH - ldah $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDAHg (402) - Alpha_INS_LDAH - ldah $RA,0($RB) !gpdisp!$NUM */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* NUM */ + { 0 } +}}, +{ /* Alpha_LDAHr (403) - Alpha_INS_LDAH - ldah $RA,$DISP($RB) !gprelhigh */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDAg (404) - Alpha_INS_LDA - lda $RA,0($RB) !gpdisp!$NUM */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* NUM */ + { 0 } +}}, +{ /* Alpha_LDAr (405) - Alpha_INS_LDA - lda $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDBU (406) - Alpha_INS_LDBU - ldbu $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDBUr (407) - Alpha_INS_LDBU - ldbu $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDL (408) - Alpha_INS_LDL - ldl $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDL_L (409) - Alpha_INS_LDL_L - ldl_l $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDLr (410) - Alpha_INS_LDL - ldl $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDQ (411) - Alpha_INS_LDQ - ldq $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDQ_L (412) - Alpha_INS_LDQ_L - ldq_l $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDQ_U (413) - Alpha_INS_LDQ_U - ldq_u $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDQl (414) - Alpha_INS_LDQ - ldq $RA,$DISP($RB) !literal */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDQr (415) - Alpha_INS_LDQ - ldq $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDS (416) - Alpha_INS_LDS - lds $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDSr (417) - Alpha_INS_LDS - lds $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDT (418) - Alpha_INS_LDT - ldt $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDTr (419) - Alpha_INS_LDT - ldt $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDWU (420) - Alpha_INS_LDWU - ldwu $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_LDWUr (421) - Alpha_INS_LDWU - ldwu $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MB (422) - Alpha_INS_MB - mb */ +{ + { 0 } +}}, +{ /* Alpha_MSKBL (423) - Alpha_INS_MSKBL - mskbl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MSKBLi (424) - Alpha_INS_MSKBL - mskbl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_MSKLH (425) - Alpha_INS_MSKLH - msklh $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MSKLHi (426) - Alpha_INS_MSKLH - msklh $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_MSKLL (427) - Alpha_INS_MSKLL - mskll $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MSKLLi (428) - Alpha_INS_MSKLL - mskll $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_MSKQH (429) - Alpha_INS_MSKQH - mskqh $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MSKQHi (430) - Alpha_INS_MSKQH - mskqh $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_MSKQL (431) - Alpha_INS_MSKQL - mskql $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MSKQLi (432) - Alpha_INS_MSKQL - mskql $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_MSKWH (433) - Alpha_INS_MSKWH - mskwh $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MSKWHi (434) - Alpha_INS_MSKWH - mskwh $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_MSKWL (435) - Alpha_INS_MSKWL - mskwl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MSKWLi (436) - Alpha_INS_MSKWL - mskwl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_MULLi (437) - Alpha_INS_MULL - mull $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_MULLr (438) - Alpha_INS_MULL - mull $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MULQi (439) - Alpha_INS_MULQ - mulq $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_MULQr (440) - Alpha_INS_MULQ - mulq $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MULS (441) - Alpha_INS_MULSsSU - muls/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_MULT (442) - Alpha_INS_MULTsSU - mult/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_ORNOTi (443) - Alpha_INS_ORNOT - ornot $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_ORNOTr (444) - Alpha_INS_ORNOT - ornot $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_RC (445) - Alpha_INS_RC - rc $RA */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { 0 } +}}, +{ /* Alpha_RETDAG (446) - Alpha_INS_RET - ret $$31,($$26),1 */ +{ + { 0 } +}}, +{ /* Alpha_RETDAGp (447) - Alpha_INS_RET - ret $$31,($$26),1 */ +{ + { 0 } +}}, +{ /* Alpha_RPCC (448) - Alpha_INS_RPCC - rpcc $RA */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_RS (449) - Alpha_INS_RS - rs $RA */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { 0 } +}}, +{ /* Alpha_S4ADDLi (450) - Alpha_INS_S4ADDL - s4addl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_S4ADDLr (451) - Alpha_INS_S4ADDL - s4addl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_S4ADDQi (452) - Alpha_INS_S4ADDQ - s4addq $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_S4ADDQr (453) - Alpha_INS_S4ADDQ - s4addq $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_S4SUBLi (454) - Alpha_INS_S4SUBL - s4subl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_S4SUBLr (455) - Alpha_INS_S4SUBL - s4subl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_S4SUBQi (456) - Alpha_INS_S4SUBQ - s4subq $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_S4SUBQr (457) - Alpha_INS_S4SUBQ - s4subq $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_S8ADDLi (458) - Alpha_INS_S8ADDL - s8addl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_S8ADDLr (459) - Alpha_INS_S8ADDL - s8addl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_S8ADDQi (460) - Alpha_INS_S8ADDQ - s8addq $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_S8ADDQr (461) - Alpha_INS_S8ADDQ - s8addq $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_S8SUBLi (462) - Alpha_INS_S8SUBL - s8subl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_S8SUBLr (463) - Alpha_INS_S8SUBL - s8subl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_S8SUBQi (464) - Alpha_INS_S8SUBQ - s8subq $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_S8SUBQr (465) - Alpha_INS_S8SUBQ - s8subq $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SEXTB (466) - Alpha_INS_SEXTB - sextb $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SEXTW (467) - Alpha_INS_SEXTW - sextw $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SLi (468) - Alpha_INS_SLL - sll $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_SLr (469) - Alpha_INS_SLL - sll $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SQRTS (470) - Alpha_INS_SQRTSsSU - sqrts/su $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SQRTT (471) - Alpha_INS_SQRTTsSU - sqrtt/su $RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SRAi (472) - Alpha_INS_SRA - sra $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_SRAr (473) - Alpha_INS_SRA - sra $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SRLi (474) - Alpha_INS_SRL - srl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_SRLr (475) - Alpha_INS_SRL - srl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STB (476) - Alpha_INS_STB - stb $RA, $DISP($RB) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STBr (477) - Alpha_INS_STB - stb $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STL (478) - Alpha_INS_STL - stl $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STL_C (479) - Alpha_INS_STL_C - stl_c $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RR */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STLr (480) - Alpha_INS_STL - stl $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STQ (481) - Alpha_INS_STQ - stq $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STQ_C (482) - Alpha_INS_STQ_C - stq_c $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RR */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STQ_U (483) - Alpha_INS_STQ_U - stq_u $RA, $DISP($RB) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STQr (484) - Alpha_INS_STQ - stq $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STS (485) - Alpha_INS_STS - sts $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STSr (486) - Alpha_INS_STS - sts $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STT (487) - Alpha_INS_STT - stt $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STTr (488) - Alpha_INS_STT - stt $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STW (489) - Alpha_INS_STW - stw $RA,$DISP($RB) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_STWr (490) - Alpha_INS_STW - stw $RA,$DISP($RB) !gprellow */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* DISP */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SUBLi (491) - Alpha_INS_SUBL - subl $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_SUBLr (492) - Alpha_INS_SUBL - subl $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SUBQi (493) - Alpha_INS_SUBQ - subq $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_SUBQr (494) - Alpha_INS_SUBQ - subq $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SUBS (495) - Alpha_INS_SUBSsSU - subs/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_SUBT (496) - Alpha_INS_SUBTsSU - subt/su $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_TRAPB (497) - Alpha_INS_TRAPB - trapb */ +{ + { 0 } +}}, +{ /* Alpha_UMULHi (498) - Alpha_INS_UMULH - umulh $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_UMULHr (499) - Alpha_INS_UMULH - umulh $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_WH64 (500) - Alpha_INS_WH64 - wh64 ($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_WH64EN (501) - Alpha_INS_WH64EN - wh64en ($RB) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_WMB (502) - Alpha_INS_WMB - wmb */ +{ + { 0 } +}}, +{ /* Alpha_XORi (503) - Alpha_INS_XOR - xor $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, +{ /* Alpha_XORr (504) - Alpha_INS_XOR - xor $RA,$RB,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ + { 0 } +}}, +{ /* Alpha_ZAPNOTi (505) - Alpha_INS_ZAPNOT - zapnot $RA,$L,$RC */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RC */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RA */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ + { 0 } +}}, diff --git a/arch/Alpha/AlphaGenCSOpGroup.inc b/arch/Alpha/AlphaGenCSOpGroup.inc new file mode 100644 index 0000000000..787fced14d --- /dev/null +++ b/arch/Alpha/AlphaGenCSOpGroup.inc @@ -0,0 +1,14 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */ +/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + Alpha_OP_GROUP_Operand = 0, diff --git a/arch/Alpha/AlphaGenDisassemblerTables.inc b/arch/Alpha/AlphaGenDisassemblerTables.inc new file mode 100644 index 0000000000..a67ae33cb2 --- /dev/null +++ b/arch/Alpha/AlphaGenDisassemblerTables.inc @@ -0,0 +1,1060 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */ +/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#include "../../MCInst.h" +#include "../../LEB128.h" + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ +static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ +{ \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ +} + +static const uint8_t DecoderTable32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12 +/* 8 */ MCD_OPC_Decode, 190, 2, 0, // Opcode: COND_BRANCH_I +/* 12 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 21 +/* 17 */ MCD_OPC_Decode, 144, 3, 1, // Opcode: LDA +/* 21 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 30 +/* 26 */ MCD_OPC_Decode, 145, 3, 1, // Opcode: LDAH +/* 30 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 39 +/* 35 */ MCD_OPC_Decode, 150, 3, 1, // Opcode: LDBU +/* 39 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 48 +/* 44 */ MCD_OPC_Decode, 157, 3, 1, // Opcode: LDQ_U +/* 48 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 57 +/* 53 */ MCD_OPC_Decode, 164, 3, 1, // Opcode: LDWU +/* 57 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 66 +/* 62 */ MCD_OPC_Decode, 233, 3, 1, // Opcode: STW +/* 66 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 75 +/* 71 */ MCD_OPC_Decode, 220, 3, 1, // Opcode: STB +/* 75 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 84 +/* 80 */ MCD_OPC_Decode, 227, 3, 1, // Opcode: STQ_U +/* 84 */ MCD_OPC_FilterValue, 16, 215, 1, 0, // Skip to: 560 +/* 89 */ MCD_OPC_ExtractField, 5, 8, // Inst{12-5} ... +/* 92 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 108 +/* 97 */ MCD_OPC_CheckField, 13, 3, 0, 43, 10, 0, // Skip to: 2707 +/* 104 */ MCD_OPC_Decode, 136, 2, 2, // Opcode: ADDLr +/* 108 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 124 +/* 113 */ MCD_OPC_CheckField, 13, 3, 0, 27, 10, 0, // Skip to: 2707 +/* 120 */ MCD_OPC_Decode, 195, 3, 2, // Opcode: S4ADDLr +/* 124 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 140 +/* 129 */ MCD_OPC_CheckField, 13, 3, 0, 11, 10, 0, // Skip to: 2707 +/* 136 */ MCD_OPC_Decode, 236, 3, 2, // Opcode: SUBLr +/* 140 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 156 +/* 145 */ MCD_OPC_CheckField, 13, 3, 0, 251, 9, 0, // Skip to: 2707 +/* 152 */ MCD_OPC_Decode, 199, 3, 2, // Opcode: S4SUBLr +/* 156 */ MCD_OPC_FilterValue, 15, 11, 0, 0, // Skip to: 172 +/* 161 */ MCD_OPC_CheckField, 13, 3, 0, 235, 9, 0, // Skip to: 2707 +/* 168 */ MCD_OPC_Decode, 173, 2, 2, // Opcode: CMPBGE +/* 172 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 188 +/* 177 */ MCD_OPC_CheckField, 13, 3, 0, 219, 9, 0, // Skip to: 2707 +/* 184 */ MCD_OPC_Decode, 203, 3, 2, // Opcode: S8ADDLr +/* 188 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 204 +/* 193 */ MCD_OPC_CheckField, 13, 3, 0, 203, 9, 0, // Skip to: 2707 +/* 200 */ MCD_OPC_Decode, 207, 3, 2, // Opcode: S8SUBLr +/* 204 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 220 +/* 209 */ MCD_OPC_CheckField, 13, 3, 0, 187, 9, 0, // Skip to: 2707 +/* 216 */ MCD_OPC_Decode, 187, 2, 2, // Opcode: CMPULT +/* 220 */ MCD_OPC_FilterValue, 32, 11, 0, 0, // Skip to: 236 +/* 225 */ MCD_OPC_CheckField, 13, 3, 0, 171, 9, 0, // Skip to: 2707 +/* 232 */ MCD_OPC_Decode, 138, 2, 2, // Opcode: ADDQr +/* 236 */ MCD_OPC_FilterValue, 34, 11, 0, 0, // Skip to: 252 +/* 241 */ MCD_OPC_CheckField, 13, 3, 0, 155, 9, 0, // Skip to: 2707 +/* 248 */ MCD_OPC_Decode, 197, 3, 2, // Opcode: S4ADDQr +/* 252 */ MCD_OPC_FilterValue, 41, 11, 0, 0, // Skip to: 268 +/* 257 */ MCD_OPC_CheckField, 13, 3, 0, 139, 9, 0, // Skip to: 2707 +/* 264 */ MCD_OPC_Decode, 238, 3, 2, // Opcode: SUBQr +/* 268 */ MCD_OPC_FilterValue, 43, 11, 0, 0, // Skip to: 284 +/* 273 */ MCD_OPC_CheckField, 13, 3, 0, 123, 9, 0, // Skip to: 2707 +/* 280 */ MCD_OPC_Decode, 201, 3, 2, // Opcode: S4SUBQr +/* 284 */ MCD_OPC_FilterValue, 45, 11, 0, 0, // Skip to: 300 +/* 289 */ MCD_OPC_CheckField, 13, 3, 0, 107, 9, 0, // Skip to: 2707 +/* 296 */ MCD_OPC_Decode, 175, 2, 2, // Opcode: CMPEQ +/* 300 */ MCD_OPC_FilterValue, 50, 11, 0, 0, // Skip to: 316 +/* 305 */ MCD_OPC_CheckField, 13, 3, 0, 91, 9, 0, // Skip to: 2707 +/* 312 */ MCD_OPC_Decode, 205, 3, 2, // Opcode: S8ADDQr +/* 316 */ MCD_OPC_FilterValue, 59, 11, 0, 0, // Skip to: 332 +/* 321 */ MCD_OPC_CheckField, 13, 3, 0, 75, 9, 0, // Skip to: 2707 +/* 328 */ MCD_OPC_Decode, 209, 3, 2, // Opcode: S8SUBQr +/* 332 */ MCD_OPC_FilterValue, 61, 11, 0, 0, // Skip to: 348 +/* 337 */ MCD_OPC_CheckField, 13, 3, 0, 59, 9, 0, // Skip to: 2707 +/* 344 */ MCD_OPC_Decode, 185, 2, 2, // Opcode: CMPULE +/* 348 */ MCD_OPC_FilterValue, 77, 11, 0, 0, // Skip to: 364 +/* 353 */ MCD_OPC_CheckField, 13, 3, 0, 43, 9, 0, // Skip to: 2707 +/* 360 */ MCD_OPC_Decode, 179, 2, 2, // Opcode: CMPLT +/* 364 */ MCD_OPC_FilterValue, 109, 11, 0, 0, // Skip to: 380 +/* 369 */ MCD_OPC_CheckField, 13, 3, 0, 27, 9, 0, // Skip to: 2707 +/* 376 */ MCD_OPC_Decode, 177, 2, 2, // Opcode: CMPLE +/* 380 */ MCD_OPC_FilterValue, 128, 1, 4, 0, 0, // Skip to: 390 +/* 386 */ MCD_OPC_Decode, 135, 2, 3, // Opcode: ADDLi +/* 390 */ MCD_OPC_FilterValue, 130, 1, 4, 0, 0, // Skip to: 400 +/* 396 */ MCD_OPC_Decode, 194, 3, 3, // Opcode: S4ADDLi +/* 400 */ MCD_OPC_FilterValue, 137, 1, 4, 0, 0, // Skip to: 410 +/* 406 */ MCD_OPC_Decode, 235, 3, 3, // Opcode: SUBLi +/* 410 */ MCD_OPC_FilterValue, 139, 1, 4, 0, 0, // Skip to: 420 +/* 416 */ MCD_OPC_Decode, 198, 3, 3, // Opcode: S4SUBLi +/* 420 */ MCD_OPC_FilterValue, 143, 1, 4, 0, 0, // Skip to: 430 +/* 426 */ MCD_OPC_Decode, 174, 2, 3, // Opcode: CMPBGEi +/* 430 */ MCD_OPC_FilterValue, 146, 1, 4, 0, 0, // Skip to: 440 +/* 436 */ MCD_OPC_Decode, 202, 3, 3, // Opcode: S8ADDLi +/* 440 */ MCD_OPC_FilterValue, 155, 1, 4, 0, 0, // Skip to: 450 +/* 446 */ MCD_OPC_Decode, 206, 3, 3, // Opcode: S8SUBLi +/* 450 */ MCD_OPC_FilterValue, 157, 1, 4, 0, 0, // Skip to: 460 +/* 456 */ MCD_OPC_Decode, 188, 2, 3, // Opcode: CMPULTi +/* 460 */ MCD_OPC_FilterValue, 160, 1, 4, 0, 0, // Skip to: 470 +/* 466 */ MCD_OPC_Decode, 137, 2, 3, // Opcode: ADDQi +/* 470 */ MCD_OPC_FilterValue, 162, 1, 4, 0, 0, // Skip to: 480 +/* 476 */ MCD_OPC_Decode, 196, 3, 3, // Opcode: S4ADDQi +/* 480 */ MCD_OPC_FilterValue, 169, 1, 4, 0, 0, // Skip to: 490 +/* 486 */ MCD_OPC_Decode, 237, 3, 3, // Opcode: SUBQi +/* 490 */ MCD_OPC_FilterValue, 171, 1, 4, 0, 0, // Skip to: 500 +/* 496 */ MCD_OPC_Decode, 200, 3, 3, // Opcode: S4SUBQi +/* 500 */ MCD_OPC_FilterValue, 173, 1, 4, 0, 0, // Skip to: 510 +/* 506 */ MCD_OPC_Decode, 176, 2, 3, // Opcode: CMPEQi +/* 510 */ MCD_OPC_FilterValue, 178, 1, 4, 0, 0, // Skip to: 520 +/* 516 */ MCD_OPC_Decode, 204, 3, 3, // Opcode: S8ADDQi +/* 520 */ MCD_OPC_FilterValue, 187, 1, 4, 0, 0, // Skip to: 530 +/* 526 */ MCD_OPC_Decode, 208, 3, 3, // Opcode: S8SUBQi +/* 530 */ MCD_OPC_FilterValue, 189, 1, 4, 0, 0, // Skip to: 540 +/* 536 */ MCD_OPC_Decode, 186, 2, 3, // Opcode: CMPULEi +/* 540 */ MCD_OPC_FilterValue, 205, 1, 4, 0, 0, // Skip to: 550 +/* 546 */ MCD_OPC_Decode, 180, 2, 3, // Opcode: CMPLTi +/* 550 */ MCD_OPC_FilterValue, 237, 1, 103, 8, 0, // Skip to: 2707 +/* 556 */ MCD_OPC_Decode, 178, 2, 3, // Opcode: CMPLEi +/* 560 */ MCD_OPC_FilterValue, 17, 111, 1, 0, // Skip to: 932 +/* 565 */ MCD_OPC_ExtractField, 5, 8, // Inst{12-5} ... +/* 568 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 584 +/* 573 */ MCD_OPC_CheckField, 13, 3, 0, 79, 8, 0, // Skip to: 2707 +/* 580 */ MCD_OPC_Decode, 142, 2, 2, // Opcode: ANDr +/* 584 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 600 +/* 589 */ MCD_OPC_CheckField, 13, 3, 0, 63, 8, 0, // Skip to: 2707 +/* 596 */ MCD_OPC_Decode, 147, 2, 2, // Opcode: BICr +/* 600 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 616 +/* 605 */ MCD_OPC_CheckField, 13, 3, 0, 47, 8, 0, // Skip to: 2707 +/* 612 */ MCD_OPC_Decode, 166, 2, 4, // Opcode: CMOVLBSr +/* 616 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 632 +/* 621 */ MCD_OPC_CheckField, 13, 3, 0, 31, 8, 0, // Skip to: 2707 +/* 628 */ MCD_OPC_Decode, 164, 2, 4, // Opcode: CMOVLBCr +/* 632 */ MCD_OPC_FilterValue, 32, 11, 0, 0, // Skip to: 648 +/* 637 */ MCD_OPC_CheckField, 13, 3, 0, 15, 8, 0, // Skip to: 2707 +/* 644 */ MCD_OPC_Decode, 149, 2, 2, // Opcode: BISr +/* 648 */ MCD_OPC_FilterValue, 36, 11, 0, 0, // Skip to: 664 +/* 653 */ MCD_OPC_CheckField, 13, 3, 0, 255, 7, 0, // Skip to: 2707 +/* 660 */ MCD_OPC_Decode, 158, 2, 4, // Opcode: CMOVEQr +/* 664 */ MCD_OPC_FilterValue, 38, 11, 0, 0, // Skip to: 680 +/* 669 */ MCD_OPC_CheckField, 13, 3, 0, 239, 7, 0, // Skip to: 2707 +/* 676 */ MCD_OPC_Decode, 172, 2, 4, // Opcode: CMOVNEr +/* 680 */ MCD_OPC_FilterValue, 40, 11, 0, 0, // Skip to: 696 +/* 685 */ MCD_OPC_CheckField, 13, 3, 0, 223, 7, 0, // Skip to: 2707 +/* 692 */ MCD_OPC_Decode, 188, 3, 2, // Opcode: ORNOTr +/* 696 */ MCD_OPC_FilterValue, 64, 11, 0, 0, // Skip to: 712 +/* 701 */ MCD_OPC_CheckField, 13, 3, 0, 207, 7, 0, // Skip to: 2707 +/* 708 */ MCD_OPC_Decode, 248, 3, 2, // Opcode: XORr +/* 712 */ MCD_OPC_FilterValue, 68, 11, 0, 0, // Skip to: 728 +/* 717 */ MCD_OPC_CheckField, 13, 3, 0, 191, 7, 0, // Skip to: 2707 +/* 724 */ MCD_OPC_Decode, 170, 2, 4, // Opcode: CMOVLTr +/* 728 */ MCD_OPC_FilterValue, 70, 11, 0, 0, // Skip to: 744 +/* 733 */ MCD_OPC_CheckField, 13, 3, 0, 175, 7, 0, // Skip to: 2707 +/* 740 */ MCD_OPC_Decode, 160, 2, 4, // Opcode: CMOVGEr +/* 744 */ MCD_OPC_FilterValue, 72, 11, 0, 0, // Skip to: 760 +/* 749 */ MCD_OPC_CheckField, 13, 3, 0, 159, 7, 0, // Skip to: 2707 +/* 756 */ MCD_OPC_Decode, 214, 2, 2, // Opcode: EQVr +/* 760 */ MCD_OPC_FilterValue, 100, 11, 0, 0, // Skip to: 776 +/* 765 */ MCD_OPC_CheckField, 13, 3, 0, 143, 7, 0, // Skip to: 2707 +/* 772 */ MCD_OPC_Decode, 168, 2, 4, // Opcode: CMOVLEr +/* 776 */ MCD_OPC_FilterValue, 102, 11, 0, 0, // Skip to: 792 +/* 781 */ MCD_OPC_CheckField, 13, 3, 0, 127, 7, 0, // Skip to: 2707 +/* 788 */ MCD_OPC_Decode, 162, 2, 4, // Opcode: CMOVGTr +/* 792 */ MCD_OPC_FilterValue, 128, 1, 4, 0, 0, // Skip to: 802 +/* 798 */ MCD_OPC_Decode, 141, 2, 3, // Opcode: ANDi +/* 802 */ MCD_OPC_FilterValue, 136, 1, 4, 0, 0, // Skip to: 812 +/* 808 */ MCD_OPC_Decode, 146, 2, 3, // Opcode: BICi +/* 812 */ MCD_OPC_FilterValue, 148, 1, 4, 0, 0, // Skip to: 822 +/* 818 */ MCD_OPC_Decode, 165, 2, 5, // Opcode: CMOVLBSi +/* 822 */ MCD_OPC_FilterValue, 150, 1, 4, 0, 0, // Skip to: 832 +/* 828 */ MCD_OPC_Decode, 163, 2, 5, // Opcode: CMOVLBCi +/* 832 */ MCD_OPC_FilterValue, 160, 1, 4, 0, 0, // Skip to: 842 +/* 838 */ MCD_OPC_Decode, 148, 2, 3, // Opcode: BISi +/* 842 */ MCD_OPC_FilterValue, 164, 1, 4, 0, 0, // Skip to: 852 +/* 848 */ MCD_OPC_Decode, 157, 2, 5, // Opcode: CMOVEQi +/* 852 */ MCD_OPC_FilterValue, 166, 1, 4, 0, 0, // Skip to: 862 +/* 858 */ MCD_OPC_Decode, 171, 2, 5, // Opcode: CMOVNEi +/* 862 */ MCD_OPC_FilterValue, 168, 1, 4, 0, 0, // Skip to: 872 +/* 868 */ MCD_OPC_Decode, 187, 3, 3, // Opcode: ORNOTi +/* 872 */ MCD_OPC_FilterValue, 192, 1, 4, 0, 0, // Skip to: 882 +/* 878 */ MCD_OPC_Decode, 247, 3, 3, // Opcode: XORi +/* 882 */ MCD_OPC_FilterValue, 196, 1, 4, 0, 0, // Skip to: 892 +/* 888 */ MCD_OPC_Decode, 169, 2, 5, // Opcode: CMOVLTi +/* 892 */ MCD_OPC_FilterValue, 198, 1, 4, 0, 0, // Skip to: 902 +/* 898 */ MCD_OPC_Decode, 159, 2, 5, // Opcode: CMOVGEi +/* 902 */ MCD_OPC_FilterValue, 200, 1, 4, 0, 0, // Skip to: 912 +/* 908 */ MCD_OPC_Decode, 213, 2, 3, // Opcode: EQVi +/* 912 */ MCD_OPC_FilterValue, 228, 1, 4, 0, 0, // Skip to: 922 +/* 918 */ MCD_OPC_Decode, 167, 2, 5, // Opcode: CMOVLEi +/* 922 */ MCD_OPC_FilterValue, 230, 1, 243, 6, 0, // Skip to: 2707 +/* 928 */ MCD_OPC_Decode, 161, 2, 5, // Opcode: CMOVGTi +/* 932 */ MCD_OPC_FilterValue, 18, 125, 2, 0, // Skip to: 1574 +/* 937 */ MCD_OPC_ExtractField, 5, 8, // Inst{12-5} ... +/* 940 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 956 +/* 945 */ MCD_OPC_CheckField, 13, 3, 0, 219, 6, 0, // Skip to: 2707 +/* 952 */ MCD_OPC_Decode, 167, 3, 2, // Opcode: MSKBL +/* 956 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 972 +/* 961 */ MCD_OPC_CheckField, 13, 3, 0, 203, 6, 0, // Skip to: 2707 +/* 968 */ MCD_OPC_Decode, 216, 2, 2, // Opcode: EXTBL +/* 972 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 988 +/* 977 */ MCD_OPC_CheckField, 13, 3, 0, 187, 6, 0, // Skip to: 2707 +/* 984 */ MCD_OPC_Decode, 252, 2, 2, // Opcode: INSBL +/* 988 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 1004 +/* 993 */ MCD_OPC_CheckField, 13, 3, 0, 171, 6, 0, // Skip to: 2707 +/* 1000 */ MCD_OPC_Decode, 179, 3, 2, // Opcode: MSKWL +/* 1004 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 1020 +/* 1009 */ MCD_OPC_CheckField, 13, 3, 0, 155, 6, 0, // Skip to: 2707 +/* 1016 */ MCD_OPC_Decode, 228, 2, 2, // Opcode: EXTWL +/* 1020 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 1036 +/* 1025 */ MCD_OPC_CheckField, 13, 3, 0, 139, 6, 0, // Skip to: 2707 +/* 1032 */ MCD_OPC_Decode, 136, 3, 2, // Opcode: INSWL +/* 1036 */ MCD_OPC_FilterValue, 34, 11, 0, 0, // Skip to: 1052 +/* 1041 */ MCD_OPC_CheckField, 13, 3, 0, 123, 6, 0, // Skip to: 2707 +/* 1048 */ MCD_OPC_Decode, 171, 3, 2, // Opcode: MSKLL +/* 1052 */ MCD_OPC_FilterValue, 38, 11, 0, 0, // Skip to: 1068 +/* 1057 */ MCD_OPC_CheckField, 13, 3, 0, 107, 6, 0, // Skip to: 2707 +/* 1064 */ MCD_OPC_Decode, 220, 2, 2, // Opcode: EXTLL +/* 1068 */ MCD_OPC_FilterValue, 43, 11, 0, 0, // Skip to: 1084 +/* 1073 */ MCD_OPC_CheckField, 13, 3, 0, 91, 6, 0, // Skip to: 2707 +/* 1080 */ MCD_OPC_Decode, 128, 3, 2, // Opcode: INSLL +/* 1084 */ MCD_OPC_FilterValue, 50, 11, 0, 0, // Skip to: 1100 +/* 1089 */ MCD_OPC_CheckField, 13, 3, 0, 75, 6, 0, // Skip to: 2707 +/* 1096 */ MCD_OPC_Decode, 175, 3, 2, // Opcode: MSKQL +/* 1100 */ MCD_OPC_FilterValue, 52, 11, 0, 0, // Skip to: 1116 +/* 1105 */ MCD_OPC_CheckField, 13, 3, 0, 59, 6, 0, // Skip to: 2707 +/* 1112 */ MCD_OPC_Decode, 219, 3, 2, // Opcode: SRLr +/* 1116 */ MCD_OPC_FilterValue, 54, 11, 0, 0, // Skip to: 1132 +/* 1121 */ MCD_OPC_CheckField, 13, 3, 0, 43, 6, 0, // Skip to: 2707 +/* 1128 */ MCD_OPC_Decode, 224, 2, 2, // Opcode: EXTQL +/* 1132 */ MCD_OPC_FilterValue, 57, 11, 0, 0, // Skip to: 1148 +/* 1137 */ MCD_OPC_CheckField, 13, 3, 0, 27, 6, 0, // Skip to: 2707 +/* 1144 */ MCD_OPC_Decode, 213, 3, 2, // Opcode: SLr +/* 1148 */ MCD_OPC_FilterValue, 59, 11, 0, 0, // Skip to: 1164 +/* 1153 */ MCD_OPC_CheckField, 13, 3, 0, 11, 6, 0, // Skip to: 2707 +/* 1160 */ MCD_OPC_Decode, 132, 3, 2, // Opcode: INSQL +/* 1164 */ MCD_OPC_FilterValue, 60, 11, 0, 0, // Skip to: 1180 +/* 1169 */ MCD_OPC_CheckField, 13, 3, 0, 251, 5, 0, // Skip to: 2707 +/* 1176 */ MCD_OPC_Decode, 217, 3, 2, // Opcode: SRAr +/* 1180 */ MCD_OPC_FilterValue, 82, 11, 0, 0, // Skip to: 1196 +/* 1185 */ MCD_OPC_CheckField, 13, 3, 0, 235, 5, 0, // Skip to: 2707 +/* 1192 */ MCD_OPC_Decode, 177, 3, 2, // Opcode: MSKWH +/* 1196 */ MCD_OPC_FilterValue, 87, 11, 0, 0, // Skip to: 1212 +/* 1201 */ MCD_OPC_CheckField, 13, 3, 0, 219, 5, 0, // Skip to: 2707 +/* 1208 */ MCD_OPC_Decode, 134, 3, 2, // Opcode: INSWH +/* 1212 */ MCD_OPC_FilterValue, 90, 11, 0, 0, // Skip to: 1228 +/* 1217 */ MCD_OPC_CheckField, 13, 3, 0, 203, 5, 0, // Skip to: 2707 +/* 1224 */ MCD_OPC_Decode, 226, 2, 2, // Opcode: EXTWH +/* 1228 */ MCD_OPC_FilterValue, 98, 11, 0, 0, // Skip to: 1244 +/* 1233 */ MCD_OPC_CheckField, 13, 3, 0, 187, 5, 0, // Skip to: 2707 +/* 1240 */ MCD_OPC_Decode, 169, 3, 2, // Opcode: MSKLH +/* 1244 */ MCD_OPC_FilterValue, 103, 11, 0, 0, // Skip to: 1260 +/* 1249 */ MCD_OPC_CheckField, 13, 3, 0, 171, 5, 0, // Skip to: 2707 +/* 1256 */ MCD_OPC_Decode, 254, 2, 2, // Opcode: INSLH +/* 1260 */ MCD_OPC_FilterValue, 106, 11, 0, 0, // Skip to: 1276 +/* 1265 */ MCD_OPC_CheckField, 13, 3, 0, 155, 5, 0, // Skip to: 2707 +/* 1272 */ MCD_OPC_Decode, 218, 2, 2, // Opcode: EXTLH +/* 1276 */ MCD_OPC_FilterValue, 114, 11, 0, 0, // Skip to: 1292 +/* 1281 */ MCD_OPC_CheckField, 13, 3, 0, 139, 5, 0, // Skip to: 2707 +/* 1288 */ MCD_OPC_Decode, 173, 3, 2, // Opcode: MSKQH +/* 1292 */ MCD_OPC_FilterValue, 119, 11, 0, 0, // Skip to: 1308 +/* 1297 */ MCD_OPC_CheckField, 13, 3, 0, 123, 5, 0, // Skip to: 2707 +/* 1304 */ MCD_OPC_Decode, 130, 3, 2, // Opcode: INSQH +/* 1308 */ MCD_OPC_FilterValue, 122, 11, 0, 0, // Skip to: 1324 +/* 1313 */ MCD_OPC_CheckField, 13, 3, 0, 107, 5, 0, // Skip to: 2707 +/* 1320 */ MCD_OPC_Decode, 222, 2, 2, // Opcode: EXTQH +/* 1324 */ MCD_OPC_FilterValue, 130, 1, 4, 0, 0, // Skip to: 1334 +/* 1330 */ MCD_OPC_Decode, 168, 3, 3, // Opcode: MSKBLi +/* 1334 */ MCD_OPC_FilterValue, 134, 1, 4, 0, 0, // Skip to: 1344 +/* 1340 */ MCD_OPC_Decode, 217, 2, 3, // Opcode: EXTBLi +/* 1344 */ MCD_OPC_FilterValue, 139, 1, 4, 0, 0, // Skip to: 1354 +/* 1350 */ MCD_OPC_Decode, 253, 2, 3, // Opcode: INSBLi +/* 1354 */ MCD_OPC_FilterValue, 146, 1, 4, 0, 0, // Skip to: 1364 +/* 1360 */ MCD_OPC_Decode, 180, 3, 3, // Opcode: MSKWLi +/* 1364 */ MCD_OPC_FilterValue, 150, 1, 4, 0, 0, // Skip to: 1374 +/* 1370 */ MCD_OPC_Decode, 229, 2, 3, // Opcode: EXTWLi +/* 1374 */ MCD_OPC_FilterValue, 155, 1, 4, 0, 0, // Skip to: 1384 +/* 1380 */ MCD_OPC_Decode, 137, 3, 3, // Opcode: INSWLi +/* 1384 */ MCD_OPC_FilterValue, 162, 1, 4, 0, 0, // Skip to: 1394 +/* 1390 */ MCD_OPC_Decode, 172, 3, 3, // Opcode: MSKLLi +/* 1394 */ MCD_OPC_FilterValue, 166, 1, 4, 0, 0, // Skip to: 1404 +/* 1400 */ MCD_OPC_Decode, 221, 2, 3, // Opcode: EXTLLi +/* 1404 */ MCD_OPC_FilterValue, 171, 1, 4, 0, 0, // Skip to: 1414 +/* 1410 */ MCD_OPC_Decode, 129, 3, 3, // Opcode: INSLLi +/* 1414 */ MCD_OPC_FilterValue, 177, 1, 4, 0, 0, // Skip to: 1424 +/* 1420 */ MCD_OPC_Decode, 249, 3, 3, // Opcode: ZAPNOTi +/* 1424 */ MCD_OPC_FilterValue, 178, 1, 4, 0, 0, // Skip to: 1434 +/* 1430 */ MCD_OPC_Decode, 176, 3, 3, // Opcode: MSKQLi +/* 1434 */ MCD_OPC_FilterValue, 180, 1, 4, 0, 0, // Skip to: 1444 +/* 1440 */ MCD_OPC_Decode, 218, 3, 3, // Opcode: SRLi +/* 1444 */ MCD_OPC_FilterValue, 182, 1, 4, 0, 0, // Skip to: 1454 +/* 1450 */ MCD_OPC_Decode, 225, 2, 3, // Opcode: EXTQLi +/* 1454 */ MCD_OPC_FilterValue, 185, 1, 4, 0, 0, // Skip to: 1464 +/* 1460 */ MCD_OPC_Decode, 212, 3, 3, // Opcode: SLi +/* 1464 */ MCD_OPC_FilterValue, 187, 1, 4, 0, 0, // Skip to: 1474 +/* 1470 */ MCD_OPC_Decode, 133, 3, 3, // Opcode: INSQLi +/* 1474 */ MCD_OPC_FilterValue, 188, 1, 4, 0, 0, // Skip to: 1484 +/* 1480 */ MCD_OPC_Decode, 216, 3, 3, // Opcode: SRAi +/* 1484 */ MCD_OPC_FilterValue, 210, 1, 4, 0, 0, // Skip to: 1494 +/* 1490 */ MCD_OPC_Decode, 178, 3, 3, // Opcode: MSKWHi +/* 1494 */ MCD_OPC_FilterValue, 215, 1, 4, 0, 0, // Skip to: 1504 +/* 1500 */ MCD_OPC_Decode, 135, 3, 3, // Opcode: INSWHi +/* 1504 */ MCD_OPC_FilterValue, 218, 1, 4, 0, 0, // Skip to: 1514 +/* 1510 */ MCD_OPC_Decode, 227, 2, 3, // Opcode: EXTWHi +/* 1514 */ MCD_OPC_FilterValue, 226, 1, 4, 0, 0, // Skip to: 1524 +/* 1520 */ MCD_OPC_Decode, 170, 3, 3, // Opcode: MSKLHi +/* 1524 */ MCD_OPC_FilterValue, 231, 1, 4, 0, 0, // Skip to: 1534 +/* 1530 */ MCD_OPC_Decode, 255, 2, 3, // Opcode: INSLHi +/* 1534 */ MCD_OPC_FilterValue, 234, 1, 4, 0, 0, // Skip to: 1544 +/* 1540 */ MCD_OPC_Decode, 219, 2, 3, // Opcode: EXTLHi +/* 1544 */ MCD_OPC_FilterValue, 242, 1, 4, 0, 0, // Skip to: 1554 +/* 1550 */ MCD_OPC_Decode, 174, 3, 3, // Opcode: MSKQHi +/* 1554 */ MCD_OPC_FilterValue, 247, 1, 4, 0, 0, // Skip to: 1564 +/* 1560 */ MCD_OPC_Decode, 131, 3, 3, // Opcode: INSQHi +/* 1564 */ MCD_OPC_FilterValue, 250, 1, 113, 4, 0, // Skip to: 2707 +/* 1570 */ MCD_OPC_Decode, 223, 2, 3, // Opcode: EXTQHi +/* 1574 */ MCD_OPC_FilterValue, 19, 81, 0, 0, // Skip to: 1660 +/* 1579 */ MCD_OPC_ExtractField, 5, 8, // Inst{12-5} ... +/* 1582 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1598 +/* 1587 */ MCD_OPC_CheckField, 13, 3, 0, 89, 4, 0, // Skip to: 2707 +/* 1594 */ MCD_OPC_Decode, 182, 3, 2, // Opcode: MULLr +/* 1598 */ MCD_OPC_FilterValue, 32, 11, 0, 0, // Skip to: 1614 +/* 1603 */ MCD_OPC_CheckField, 13, 3, 0, 73, 4, 0, // Skip to: 2707 +/* 1610 */ MCD_OPC_Decode, 184, 3, 2, // Opcode: MULQr +/* 1614 */ MCD_OPC_FilterValue, 48, 11, 0, 0, // Skip to: 1630 +/* 1619 */ MCD_OPC_CheckField, 13, 3, 0, 57, 4, 0, // Skip to: 2707 +/* 1626 */ MCD_OPC_Decode, 243, 3, 2, // Opcode: UMULHr +/* 1630 */ MCD_OPC_FilterValue, 128, 1, 4, 0, 0, // Skip to: 1640 +/* 1636 */ MCD_OPC_Decode, 181, 3, 3, // Opcode: MULLi +/* 1640 */ MCD_OPC_FilterValue, 160, 1, 4, 0, 0, // Skip to: 1650 +/* 1646 */ MCD_OPC_Decode, 183, 3, 3, // Opcode: MULQi +/* 1650 */ MCD_OPC_FilterValue, 176, 1, 27, 4, 0, // Skip to: 2707 +/* 1656 */ MCD_OPC_Decode, 242, 3, 3, // Opcode: UMULHi +/* 1660 */ MCD_OPC_FilterValue, 20, 69, 0, 0, // Skip to: 1734 +/* 1665 */ MCD_OPC_ExtractField, 5, 11, // Inst{15-5} ... +/* 1668 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 1684 +/* 1673 */ MCD_OPC_CheckField, 16, 5, 31, 3, 4, 0, // Skip to: 2707 +/* 1680 */ MCD_OPC_Decode, 138, 3, 6, // Opcode: ITOFS +/* 1684 */ MCD_OPC_FilterValue, 36, 11, 0, 0, // Skip to: 1700 +/* 1689 */ MCD_OPC_CheckField, 16, 5, 31, 243, 3, 0, // Skip to: 2707 +/* 1696 */ MCD_OPC_Decode, 139, 3, 7, // Opcode: ITOFT +/* 1700 */ MCD_OPC_FilterValue, 139, 11, 11, 0, 0, // Skip to: 1717 +/* 1706 */ MCD_OPC_CheckField, 21, 5, 31, 226, 3, 0, // Skip to: 2707 +/* 1713 */ MCD_OPC_Decode, 214, 3, 8, // Opcode: SQRTS +/* 1717 */ MCD_OPC_FilterValue, 171, 11, 216, 3, 0, // Skip to: 2707 +/* 1723 */ MCD_OPC_CheckField, 21, 5, 31, 209, 3, 0, // Skip to: 2707 +/* 1730 */ MCD_OPC_Decode, 215, 3, 9, // Opcode: SQRTT +/* 1734 */ MCD_OPC_FilterValue, 22, 208, 0, 0, // Skip to: 1947 +/* 1739 */ MCD_OPC_ExtractField, 5, 11, // Inst{15-5} ... +/* 1742 */ MCD_OPC_FilterValue, 175, 10, 11, 0, 0, // Skip to: 1759 +/* 1748 */ MCD_OPC_CheckField, 21, 5, 31, 184, 3, 0, // Skip to: 2707 +/* 1755 */ MCD_OPC_Decode, 208, 2, 9, // Opcode: CVTTQ +/* 1759 */ MCD_OPC_FilterValue, 128, 11, 4, 0, 0, // Skip to: 1769 +/* 1765 */ MCD_OPC_Decode, 139, 2, 10, // Opcode: ADDS +/* 1769 */ MCD_OPC_FilterValue, 129, 11, 4, 0, 0, // Skip to: 1779 +/* 1775 */ MCD_OPC_Decode, 239, 3, 10, // Opcode: SUBS +/* 1779 */ MCD_OPC_FilterValue, 130, 11, 4, 0, 0, // Skip to: 1789 +/* 1785 */ MCD_OPC_Decode, 185, 3, 10, // Opcode: MULS +/* 1789 */ MCD_OPC_FilterValue, 131, 11, 4, 0, 0, // Skip to: 1799 +/* 1795 */ MCD_OPC_Decode, 210, 2, 10, // Opcode: DIVS +/* 1799 */ MCD_OPC_FilterValue, 160, 11, 4, 0, 0, // Skip to: 1809 +/* 1805 */ MCD_OPC_Decode, 140, 2, 11, // Opcode: ADDT +/* 1809 */ MCD_OPC_FilterValue, 161, 11, 4, 0, 0, // Skip to: 1819 +/* 1815 */ MCD_OPC_Decode, 240, 3, 11, // Opcode: SUBT +/* 1819 */ MCD_OPC_FilterValue, 162, 11, 4, 0, 0, // Skip to: 1829 +/* 1825 */ MCD_OPC_Decode, 186, 3, 11, // Opcode: MULT +/* 1829 */ MCD_OPC_FilterValue, 163, 11, 4, 0, 0, // Skip to: 1839 +/* 1835 */ MCD_OPC_Decode, 211, 2, 11, // Opcode: DIVT +/* 1839 */ MCD_OPC_FilterValue, 164, 11, 4, 0, 0, // Skip to: 1849 +/* 1845 */ MCD_OPC_Decode, 184, 2, 11, // Opcode: CMPTUN +/* 1849 */ MCD_OPC_FilterValue, 165, 11, 4, 0, 0, // Skip to: 1859 +/* 1855 */ MCD_OPC_Decode, 181, 2, 11, // Opcode: CMPTEQ +/* 1859 */ MCD_OPC_FilterValue, 166, 11, 4, 0, 0, // Skip to: 1869 +/* 1865 */ MCD_OPC_Decode, 183, 2, 11, // Opcode: CMPTLT +/* 1869 */ MCD_OPC_FilterValue, 167, 11, 4, 0, 0, // Skip to: 1879 +/* 1875 */ MCD_OPC_Decode, 182, 2, 11, // Opcode: CMPTLE +/* 1879 */ MCD_OPC_FilterValue, 172, 13, 11, 0, 0, // Skip to: 1896 +/* 1885 */ MCD_OPC_CheckField, 21, 5, 31, 47, 3, 0, // Skip to: 2707 +/* 1892 */ MCD_OPC_Decode, 207, 2, 12, // Opcode: CVTST +/* 1896 */ MCD_OPC_FilterValue, 172, 15, 11, 0, 0, // Skip to: 1913 +/* 1902 */ MCD_OPC_CheckField, 21, 5, 31, 30, 3, 0, // Skip to: 2707 +/* 1909 */ MCD_OPC_Decode, 209, 2, 13, // Opcode: CVTTS +/* 1913 */ MCD_OPC_FilterValue, 188, 15, 11, 0, 0, // Skip to: 1930 +/* 1919 */ MCD_OPC_CheckField, 21, 5, 31, 13, 3, 0, // Skip to: 2707 +/* 1926 */ MCD_OPC_Decode, 205, 2, 13, // Opcode: CVTQS +/* 1930 */ MCD_OPC_FilterValue, 190, 15, 3, 3, 0, // Skip to: 2707 +/* 1936 */ MCD_OPC_CheckField, 21, 5, 31, 252, 2, 0, // Skip to: 2707 +/* 1943 */ MCD_OPC_Decode, 206, 2, 9, // Opcode: CVTQT +/* 1947 */ MCD_OPC_FilterValue, 23, 84, 0, 0, // Skip to: 2036 +/* 1952 */ MCD_OPC_ExtractField, 5, 11, // Inst{15-5} ... +/* 1955 */ MCD_OPC_FilterValue, 32, 4, 0, 0, // Skip to: 1964 +/* 1960 */ MCD_OPC_Decode, 198, 2, 10, // Opcode: CPYSS +/* 1964 */ MCD_OPC_FilterValue, 33, 4, 0, 0, // Skip to: 1973 +/* 1969 */ MCD_OPC_Decode, 196, 2, 11, // Opcode: CPYSNT +/* 1973 */ MCD_OPC_FilterValue, 34, 4, 0, 0, // Skip to: 1982 +/* 1978 */ MCD_OPC_Decode, 191, 2, 10, // Opcode: CPYSES +/* 1982 */ MCD_OPC_FilterValue, 42, 4, 0, 0, // Skip to: 1991 +/* 1987 */ MCD_OPC_Decode, 236, 2, 10, // Opcode: FCMOVEQS +/* 1991 */ MCD_OPC_FilterValue, 43, 4, 0, 0, // Skip to: 2000 +/* 1996 */ MCD_OPC_Decode, 247, 2, 11, // Opcode: FCMOVNET +/* 2000 */ MCD_OPC_FilterValue, 44, 4, 0, 0, // Skip to: 2009 +/* 2005 */ MCD_OPC_Decode, 244, 2, 10, // Opcode: FCMOVLTS +/* 2009 */ MCD_OPC_FilterValue, 45, 4, 0, 0, // Skip to: 2018 +/* 2014 */ MCD_OPC_Decode, 238, 2, 10, // Opcode: FCMOVGES +/* 2018 */ MCD_OPC_FilterValue, 46, 4, 0, 0, // Skip to: 2027 +/* 2023 */ MCD_OPC_Decode, 242, 2, 10, // Opcode: FCMOVLES +/* 2027 */ MCD_OPC_FilterValue, 47, 163, 2, 0, // Skip to: 2707 +/* 2032 */ MCD_OPC_Decode, 240, 2, 10, // Opcode: FCMOVGTS +/* 2036 */ MCD_OPC_FilterValue, 24, 174, 0, 0, // Skip to: 2215 +/* 2041 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... +/* 2044 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2060 +/* 2049 */ MCD_OPC_CheckField, 16, 10, 0, 139, 2, 0, // Skip to: 2707 +/* 2056 */ MCD_OPC_Decode, 241, 3, 14, // Opcode: TRAPB +/* 2060 */ MCD_OPC_FilterValue, 128, 8, 11, 0, 0, // Skip to: 2077 +/* 2066 */ MCD_OPC_CheckField, 16, 10, 0, 122, 2, 0, // Skip to: 2707 +/* 2073 */ MCD_OPC_Decode, 215, 2, 14, // Opcode: EXCB +/* 2077 */ MCD_OPC_FilterValue, 128, 128, 1, 11, 0, 0, // Skip to: 2095 +/* 2084 */ MCD_OPC_CheckField, 16, 10, 0, 104, 2, 0, // Skip to: 2707 +/* 2091 */ MCD_OPC_Decode, 166, 3, 14, // Opcode: MB +/* 2095 */ MCD_OPC_FilterValue, 128, 136, 1, 11, 0, 0, // Skip to: 2113 +/* 2102 */ MCD_OPC_CheckField, 16, 10, 0, 86, 2, 0, // Skip to: 2707 +/* 2109 */ MCD_OPC_Decode, 246, 3, 14, // Opcode: WMB +/* 2113 */ MCD_OPC_FilterValue, 128, 128, 2, 4, 0, 0, // Skip to: 2124 +/* 2120 */ MCD_OPC_Decode, 248, 2, 15, // Opcode: FETCH +/* 2124 */ MCD_OPC_FilterValue, 128, 192, 2, 4, 0, 0, // Skip to: 2135 +/* 2131 */ MCD_OPC_Decode, 249, 2, 15, // Opcode: FETCH_M +/* 2135 */ MCD_OPC_FilterValue, 128, 128, 3, 4, 0, 0, // Skip to: 2146 +/* 2142 */ MCD_OPC_Decode, 192, 3, 15, // Opcode: RPCC +/* 2146 */ MCD_OPC_FilterValue, 128, 192, 3, 11, 0, 0, // Skip to: 2164 +/* 2153 */ MCD_OPC_CheckField, 16, 5, 0, 35, 2, 0, // Skip to: 2707 +/* 2160 */ MCD_OPC_Decode, 189, 3, 16, // Opcode: RC +/* 2164 */ MCD_OPC_FilterValue, 128, 208, 3, 4, 0, 0, // Skip to: 2175 +/* 2171 */ MCD_OPC_Decode, 212, 2, 15, // Opcode: ECB +/* 2175 */ MCD_OPC_FilterValue, 128, 224, 3, 11, 0, 0, // Skip to: 2193 +/* 2182 */ MCD_OPC_CheckField, 16, 5, 0, 6, 2, 0, // Skip to: 2707 +/* 2189 */ MCD_OPC_Decode, 193, 3, 16, // Opcode: RS +/* 2193 */ MCD_OPC_FilterValue, 128, 240, 3, 4, 0, 0, // Skip to: 2204 +/* 2200 */ MCD_OPC_Decode, 244, 3, 15, // Opcode: WH64 +/* 2204 */ MCD_OPC_FilterValue, 128, 248, 3, 240, 1, 0, // Skip to: 2707 +/* 2211 */ MCD_OPC_Decode, 245, 3, 15, // Opcode: WH64EN +/* 2215 */ MCD_OPC_FilterValue, 26, 101, 0, 0, // Skip to: 2321 +/* 2220 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 2223 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 2246 +/* 2228 */ MCD_OPC_CheckField, 21, 5, 31, 216, 1, 0, // Skip to: 2707 +/* 2235 */ MCD_OPC_CheckField, 0, 14, 0, 209, 1, 0, // Skip to: 2707 +/* 2242 */ MCD_OPC_Decode, 140, 3, 17, // Opcode: JMP +/* 2246 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 2288 +/* 2251 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 2254 */ MCD_OPC_FilterValue, 251, 5, 11, 0, 0, // Skip to: 2271 +/* 2260 */ MCD_OPC_CheckField, 0, 14, 0, 184, 1, 0, // Skip to: 2707 +/* 2267 */ MCD_OPC_Decode, 143, 3, 14, // Opcode: JSRs +/* 2271 */ MCD_OPC_FilterValue, 219, 6, 174, 1, 0, // Skip to: 2707 +/* 2277 */ MCD_OPC_CheckField, 0, 14, 0, 167, 1, 0, // Skip to: 2707 +/* 2284 */ MCD_OPC_Decode, 141, 3, 14, // Opcode: JSR +/* 2288 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2312 +/* 2293 */ MCD_OPC_CheckField, 16, 10, 250, 7, 150, 1, 0, // Skip to: 2707 +/* 2301 */ MCD_OPC_CheckField, 0, 14, 1, 143, 1, 0, // Skip to: 2707 +/* 2308 */ MCD_OPC_Decode, 190, 3, 14, // Opcode: RETDAG +/* 2312 */ MCD_OPC_FilterValue, 3, 134, 1, 0, // Skip to: 2707 +/* 2317 */ MCD_OPC_Decode, 142, 3, 18, // Opcode: JSR_COROUTINE +/* 2321 */ MCD_OPC_FilterValue, 28, 115, 0, 0, // Skip to: 2441 +/* 2326 */ MCD_OPC_ExtractField, 5, 11, // Inst{15-5} ... +/* 2329 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2345 +/* 2334 */ MCD_OPC_CheckField, 21, 5, 31, 110, 1, 0, // Skip to: 2707 +/* 2341 */ MCD_OPC_Decode, 210, 3, 19, // Opcode: SEXTB +/* 2345 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 2361 +/* 2350 */ MCD_OPC_CheckField, 21, 5, 31, 94, 1, 0, // Skip to: 2707 +/* 2357 */ MCD_OPC_Decode, 211, 3, 19, // Opcode: SEXTW +/* 2361 */ MCD_OPC_FilterValue, 48, 11, 0, 0, // Skip to: 2377 +/* 2366 */ MCD_OPC_CheckField, 21, 5, 31, 78, 1, 0, // Skip to: 2707 +/* 2373 */ MCD_OPC_Decode, 203, 2, 19, // Opcode: CTPOP +/* 2377 */ MCD_OPC_FilterValue, 50, 11, 0, 0, // Skip to: 2393 +/* 2382 */ MCD_OPC_CheckField, 21, 5, 31, 62, 1, 0, // Skip to: 2707 +/* 2389 */ MCD_OPC_Decode, 202, 2, 19, // Opcode: CTLZ +/* 2393 */ MCD_OPC_FilterValue, 51, 11, 0, 0, // Skip to: 2409 +/* 2398 */ MCD_OPC_CheckField, 21, 5, 31, 46, 1, 0, // Skip to: 2707 +/* 2405 */ MCD_OPC_Decode, 204, 2, 19, // Opcode: CTTZ +/* 2409 */ MCD_OPC_FilterValue, 112, 11, 0, 0, // Skip to: 2425 +/* 2414 */ MCD_OPC_CheckField, 16, 5, 31, 30, 1, 0, // Skip to: 2707 +/* 2421 */ MCD_OPC_Decode, 251, 2, 20, // Opcode: FTOIT +/* 2425 */ MCD_OPC_FilterValue, 120, 21, 1, 0, // Skip to: 2707 +/* 2430 */ MCD_OPC_CheckField, 16, 5, 31, 14, 1, 0, // Skip to: 2707 +/* 2437 */ MCD_OPC_Decode, 250, 2, 21, // Opcode: FTOIS +/* 2441 */ MCD_OPC_FilterValue, 34, 4, 0, 0, // Skip to: 2450 +/* 2446 */ MCD_OPC_Decode, 160, 3, 22, // Opcode: LDS +/* 2450 */ MCD_OPC_FilterValue, 35, 4, 0, 0, // Skip to: 2459 +/* 2455 */ MCD_OPC_Decode, 162, 3, 23, // Opcode: LDT +/* 2459 */ MCD_OPC_FilterValue, 38, 4, 0, 0, // Skip to: 2468 +/* 2464 */ MCD_OPC_Decode, 229, 3, 22, // Opcode: STS +/* 2468 */ MCD_OPC_FilterValue, 39, 4, 0, 0, // Skip to: 2477 +/* 2473 */ MCD_OPC_Decode, 231, 3, 23, // Opcode: STT +/* 2477 */ MCD_OPC_FilterValue, 40, 4, 0, 0, // Skip to: 2486 +/* 2482 */ MCD_OPC_Decode, 152, 3, 1, // Opcode: LDL +/* 2486 */ MCD_OPC_FilterValue, 41, 4, 0, 0, // Skip to: 2495 +/* 2491 */ MCD_OPC_Decode, 155, 3, 1, // Opcode: LDQ +/* 2495 */ MCD_OPC_FilterValue, 42, 4, 0, 0, // Skip to: 2504 +/* 2500 */ MCD_OPC_Decode, 153, 3, 1, // Opcode: LDL_L +/* 2504 */ MCD_OPC_FilterValue, 43, 4, 0, 0, // Skip to: 2513 +/* 2509 */ MCD_OPC_Decode, 156, 3, 1, // Opcode: LDQ_L +/* 2513 */ MCD_OPC_FilterValue, 44, 4, 0, 0, // Skip to: 2522 +/* 2518 */ MCD_OPC_Decode, 222, 3, 1, // Opcode: STL +/* 2522 */ MCD_OPC_FilterValue, 45, 4, 0, 0, // Skip to: 2531 +/* 2527 */ MCD_OPC_Decode, 225, 3, 1, // Opcode: STQ +/* 2531 */ MCD_OPC_FilterValue, 46, 4, 0, 0, // Skip to: 2540 +/* 2536 */ MCD_OPC_Decode, 223, 3, 24, // Opcode: STL_C +/* 2540 */ MCD_OPC_FilterValue, 47, 4, 0, 0, // Skip to: 2549 +/* 2545 */ MCD_OPC_Decode, 226, 3, 24, // Opcode: STQ_C +/* 2549 */ MCD_OPC_FilterValue, 48, 11, 0, 0, // Skip to: 2565 +/* 2554 */ MCD_OPC_CheckField, 21, 5, 31, 146, 0, 0, // Skip to: 2707 +/* 2561 */ MCD_OPC_Decode, 155, 2, 25, // Opcode: BR +/* 2565 */ MCD_OPC_FilterValue, 49, 4, 0, 0, // Skip to: 2574 +/* 2570 */ MCD_OPC_Decode, 230, 2, 26, // Opcode: FBEQ +/* 2574 */ MCD_OPC_FilterValue, 50, 4, 0, 0, // Skip to: 2583 +/* 2579 */ MCD_OPC_Decode, 234, 2, 26, // Opcode: FBLT +/* 2583 */ MCD_OPC_FilterValue, 51, 4, 0, 0, // Skip to: 2592 +/* 2588 */ MCD_OPC_Decode, 233, 2, 26, // Opcode: FBLE +/* 2592 */ MCD_OPC_FilterValue, 52, 11, 0, 0, // Skip to: 2608 +/* 2597 */ MCD_OPC_CheckField, 21, 5, 26, 103, 0, 0, // Skip to: 2707 +/* 2604 */ MCD_OPC_Decode, 156, 2, 25, // Opcode: BSR +/* 2608 */ MCD_OPC_FilterValue, 53, 4, 0, 0, // Skip to: 2617 +/* 2613 */ MCD_OPC_Decode, 235, 2, 26, // Opcode: FBNE +/* 2617 */ MCD_OPC_FilterValue, 54, 4, 0, 0, // Skip to: 2626 +/* 2622 */ MCD_OPC_Decode, 231, 2, 26, // Opcode: FBGE +/* 2626 */ MCD_OPC_FilterValue, 55, 4, 0, 0, // Skip to: 2635 +/* 2631 */ MCD_OPC_Decode, 232, 2, 26, // Opcode: FBGT +/* 2635 */ MCD_OPC_FilterValue, 56, 4, 0, 0, // Skip to: 2644 +/* 2640 */ MCD_OPC_Decode, 150, 2, 27, // Opcode: BLBC +/* 2644 */ MCD_OPC_FilterValue, 57, 4, 0, 0, // Skip to: 2653 +/* 2649 */ MCD_OPC_Decode, 143, 2, 27, // Opcode: BEQ +/* 2653 */ MCD_OPC_FilterValue, 58, 4, 0, 0, // Skip to: 2662 +/* 2658 */ MCD_OPC_Decode, 153, 2, 27, // Opcode: BLT +/* 2662 */ MCD_OPC_FilterValue, 59, 4, 0, 0, // Skip to: 2671 +/* 2667 */ MCD_OPC_Decode, 152, 2, 27, // Opcode: BLE +/* 2671 */ MCD_OPC_FilterValue, 60, 4, 0, 0, // Skip to: 2680 +/* 2676 */ MCD_OPC_Decode, 151, 2, 27, // Opcode: BLBS +/* 2680 */ MCD_OPC_FilterValue, 61, 4, 0, 0, // Skip to: 2689 +/* 2685 */ MCD_OPC_Decode, 154, 2, 27, // Opcode: BNE +/* 2689 */ MCD_OPC_FilterValue, 62, 4, 0, 0, // Skip to: 2698 +/* 2694 */ MCD_OPC_Decode, 144, 2, 27, // Opcode: BGE +/* 2698 */ MCD_OPC_FilterValue, 63, 4, 0, 0, // Skip to: 2707 +/* 2703 */ MCD_OPC_Decode, 145, 2, 27, // Opcode: BGT +/* 2707 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCondBranchF32[] = { +/* 0 */ MCD_OPC_CheckField, 26, 6, 0, 4, 0, 0, // Skip to: 11 +/* 7 */ MCD_OPC_Decode, 189, 2, 28, // Opcode: COND_BRANCH_F +/* 11 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCpys32[] = { +/* 0 */ MCD_OPC_ExtractField, 5, 11, // Inst{15-5} ... +/* 3 */ MCD_OPC_FilterValue, 32, 11, 0, 0, // Skip to: 19 +/* 8 */ MCD_OPC_CheckField, 26, 6, 23, 36, 0, 0, // Skip to: 51 +/* 15 */ MCD_OPC_Decode, 199, 2, 29, // Opcode: CPYSSt +/* 19 */ MCD_OPC_FilterValue, 33, 11, 0, 0, // Skip to: 35 +/* 24 */ MCD_OPC_CheckField, 26, 6, 23, 20, 0, 0, // Skip to: 51 +/* 31 */ MCD_OPC_Decode, 195, 2, 29, // Opcode: CPYSNSt +/* 35 */ MCD_OPC_FilterValue, 34, 11, 0, 0, // Skip to: 51 +/* 40 */ MCD_OPC_CheckField, 26, 6, 23, 4, 0, 0, // Skip to: 51 +/* 47 */ MCD_OPC_Decode, 192, 2, 29, // Opcode: CPYSESt +/* 51 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCpysET32[] = { +/* 0 */ MCD_OPC_CheckField, 26, 6, 23, 11, 0, 0, // Skip to: 18 +/* 7 */ MCD_OPC_CheckField, 5, 11, 34, 4, 0, 0, // Skip to: 18 +/* 14 */ MCD_OPC_Decode, 193, 2, 11, // Opcode: CPYSET +/* 18 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCpysNS32[] = { +/* 0 */ MCD_OPC_CheckField, 26, 6, 23, 11, 0, 0, // Skip to: 18 +/* 7 */ MCD_OPC_CheckField, 5, 11, 33, 4, 0, 0, // Skip to: 18 +/* 14 */ MCD_OPC_Decode, 194, 2, 10, // Opcode: CPYSNS +/* 18 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCpysT32[] = { +/* 0 */ MCD_OPC_CheckField, 26, 6, 23, 11, 0, 0, // Skip to: 18 +/* 7 */ MCD_OPC_CheckField, 5, 11, 32, 4, 0, 0, // Skip to: 18 +/* 14 */ MCD_OPC_Decode, 200, 2, 11, // Opcode: CPYST +/* 18 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCpysTs32[] = { +/* 0 */ MCD_OPC_ExtractField, 5, 11, // Inst{15-5} ... +/* 3 */ MCD_OPC_FilterValue, 32, 11, 0, 0, // Skip to: 19 +/* 8 */ MCD_OPC_CheckField, 26, 6, 23, 20, 0, 0, // Skip to: 35 +/* 15 */ MCD_OPC_Decode, 201, 2, 30, // Opcode: CPYSTs +/* 19 */ MCD_OPC_FilterValue, 33, 11, 0, 0, // Skip to: 35 +/* 24 */ MCD_OPC_CheckField, 26, 6, 23, 4, 0, 0, // Skip to: 35 +/* 31 */ MCD_OPC_Decode, 197, 2, 30, // Opcode: CPYSNTs +/* 35 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableFcmov32[] = { +/* 0 */ MCD_OPC_ExtractField, 5, 11, // Inst{15-5} ... +/* 3 */ MCD_OPC_FilterValue, 42, 11, 0, 0, // Skip to: 19 +/* 8 */ MCD_OPC_CheckField, 26, 6, 23, 84, 0, 0, // Skip to: 99 +/* 15 */ MCD_OPC_Decode, 237, 2, 11, // Opcode: FCMOVEQT +/* 19 */ MCD_OPC_FilterValue, 43, 11, 0, 0, // Skip to: 35 +/* 24 */ MCD_OPC_CheckField, 26, 6, 23, 68, 0, 0, // Skip to: 99 +/* 31 */ MCD_OPC_Decode, 246, 2, 10, // Opcode: FCMOVNES +/* 35 */ MCD_OPC_FilterValue, 44, 11, 0, 0, // Skip to: 51 +/* 40 */ MCD_OPC_CheckField, 26, 6, 23, 52, 0, 0, // Skip to: 99 +/* 47 */ MCD_OPC_Decode, 245, 2, 11, // Opcode: FCMOVLTT +/* 51 */ MCD_OPC_FilterValue, 45, 11, 0, 0, // Skip to: 67 +/* 56 */ MCD_OPC_CheckField, 26, 6, 23, 36, 0, 0, // Skip to: 99 +/* 63 */ MCD_OPC_Decode, 239, 2, 11, // Opcode: FCMOVGET +/* 67 */ MCD_OPC_FilterValue, 46, 11, 0, 0, // Skip to: 83 +/* 72 */ MCD_OPC_CheckField, 26, 6, 23, 20, 0, 0, // Skip to: 99 +/* 79 */ MCD_OPC_Decode, 243, 2, 11, // Opcode: FCMOVLET +/* 83 */ MCD_OPC_FilterValue, 47, 11, 0, 0, // Skip to: 99 +/* 88 */ MCD_OPC_CheckField, 26, 6, 23, 4, 0, 0, // Skip to: 99 +/* 95 */ MCD_OPC_Decode, 241, 2, 11, // Opcode: FCMOVGTT +/* 99 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableLDg32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 12 +/* 8 */ MCD_OPC_Decode, 148, 3, 1, // Opcode: LDAg +/* 12 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 21 +/* 17 */ MCD_OPC_Decode, 146, 3, 1, // Opcode: LDAHg +/* 21 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableLDl32[] = { +/* 0 */ MCD_OPC_CheckField, 26, 6, 41, 4, 0, 0, // Skip to: 11 +/* 7 */ MCD_OPC_Decode, 158, 3, 1, // Opcode: LDQl +/* 11 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableLDr32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 12 +/* 8 */ MCD_OPC_Decode, 149, 3, 1, // Opcode: LDAr +/* 12 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 21 +/* 17 */ MCD_OPC_Decode, 147, 3, 1, // Opcode: LDAHr +/* 21 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 30 +/* 26 */ MCD_OPC_Decode, 151, 3, 1, // Opcode: LDBUr +/* 30 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 39 +/* 35 */ MCD_OPC_Decode, 165, 3, 1, // Opcode: LDWUr +/* 39 */ MCD_OPC_FilterValue, 34, 4, 0, 0, // Skip to: 48 +/* 44 */ MCD_OPC_Decode, 161, 3, 22, // Opcode: LDSr +/* 48 */ MCD_OPC_FilterValue, 35, 4, 0, 0, // Skip to: 57 +/* 53 */ MCD_OPC_Decode, 163, 3, 23, // Opcode: LDTr +/* 57 */ MCD_OPC_FilterValue, 40, 4, 0, 0, // Skip to: 66 +/* 62 */ MCD_OPC_Decode, 154, 3, 1, // Opcode: LDLr +/* 66 */ MCD_OPC_FilterValue, 41, 4, 0, 0, // Skip to: 75 +/* 71 */ MCD_OPC_Decode, 159, 3, 1, // Opcode: LDQr +/* 75 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableRet32[] = { +/* 0 */ MCD_OPC_CheckField, 0, 32, 129, 128, 234, 223, 6, 4, 0, 0, // Skip to: 15 +/* 11 */ MCD_OPC_Decode, 191, 3, 14, // Opcode: RETDAGp +/* 15 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableSTr32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 12 +/* 8 */ MCD_OPC_Decode, 234, 3, 1, // Opcode: STWr +/* 12 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 21 +/* 17 */ MCD_OPC_Decode, 221, 3, 1, // Opcode: STBr +/* 21 */ MCD_OPC_FilterValue, 38, 4, 0, 0, // Skip to: 30 +/* 26 */ MCD_OPC_Decode, 230, 3, 22, // Opcode: STSr +/* 30 */ MCD_OPC_FilterValue, 39, 4, 0, 0, // Skip to: 39 +/* 35 */ MCD_OPC_Decode, 232, 3, 23, // Opcode: STTr +/* 39 */ MCD_OPC_FilterValue, 44, 4, 0, 0, // Skip to: 48 +/* 44 */ MCD_OPC_Decode, 224, 3, 1, // Opcode: STLr +/* 48 */ MCD_OPC_FilterValue, 45, 4, 0, 0, // Skip to: 57 +/* 53 */ MCD_OPC_Decode, 228, 3, 1, // Opcode: STQr +/* 57 */ MCD_OPC_Fail, + 0 +}; + +static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) { + /* llvm_unreachable("Invalid index!"); */ + return false; +} + +#define DecodeToMCInst(fname, fieldname, InsnType) \ +static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ + uint64_t Address, const void *Decoder, bool *DecodeComplete) \ +{ \ + InsnType tmp; \ + switch (Idx) { \ + default: /* llvm_unreachable("Invalid index!"); */ \ + case 0: \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 21); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 1: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 2: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 3: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 4: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 5: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 6: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 7: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 8: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 9: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 10: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 11: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 12: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 13: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 14: \ + return S; \ + case 15: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 16: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 17: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 18: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 14); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 19: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 21: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 22: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 23: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 24: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 0, 21); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 26: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 21); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 27: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 21); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 28: \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 21); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + case 30: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ + return S; \ + } \ +} + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ +static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, const void *Decoder) { \ + const uint8_t *Ptr = DecodeTable; \ + uint64_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + unsigned Len; \ + uint64_t Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ + uint64_t FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + unsigned PtrLen = 0; \ + uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \ + Ptr += PtrLen; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + unsigned Len; \ + /* Decode the Predicate Index value. */ \ + unsigned PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + bool Pred = checkDecoderPredicate(MI, PIdx); \ + if (!Pred) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + unsigned Len; \ + /* Decode the Opcode value. */ \ + unsigned Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + bool DecodeComplete; \ + S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + unsigned Len; \ + /* Decode the Opcode value. */ \ + unsigned Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + bool DecodeComplete; \ + S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + unsigned Len; \ + uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* Bogisity detected in disassembler state machine! */ \ +} + +FieldFromInstruction(fieldFromInstruction_4, uint32_t) +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) diff --git a/arch/Alpha/AlphaGenInstrInfo.inc b/arch/Alpha/AlphaGenInstrInfo.inc new file mode 100644 index 0000000000..35f59de737 --- /dev/null +++ b/arch/Alpha/AlphaGenInstrInfo.inc @@ -0,0 +1,1119 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */ +/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + + enum { + Alpha_PHI = 0, + Alpha_INLINEASM = 1, + Alpha_INLINEASM_BR = 2, + Alpha_CFI_INSTRUCTION = 3, + Alpha_EH_LABEL = 4, + Alpha_GC_LABEL = 5, + Alpha_ANNOTATION_LABEL = 6, + Alpha_KILL = 7, + Alpha_EXTRACT_SUBREG = 8, + Alpha_INSERT_SUBREG = 9, + Alpha_IMPLICIT_DEF = 10, + Alpha_SUBREG_TO_REG = 11, + Alpha_COPY_TO_REGCLASS = 12, + Alpha_DBG_VALUE = 13, + Alpha_DBG_VALUE_LIST = 14, + Alpha_DBG_INSTR_REF = 15, + Alpha_DBG_PHI = 16, + Alpha_DBG_LABEL = 17, + Alpha_REG_SEQUENCE = 18, + Alpha_COPY = 19, + Alpha_BUNDLE = 20, + Alpha_LIFETIME_START = 21, + Alpha_LIFETIME_END = 22, + Alpha_PSEUDO_PROBE = 23, + Alpha_ARITH_FENCE = 24, + Alpha_STACKMAP = 25, + Alpha_FENTRY_CALL = 26, + Alpha_PATCHPOINT = 27, + Alpha_LOAD_STACK_GUARD = 28, + Alpha_PREALLOCATED_SETUP = 29, + Alpha_PREALLOCATED_ARG = 30, + Alpha_STATEPOINT = 31, + Alpha_LOCAL_ESCAPE = 32, + Alpha_FAULTING_OP = 33, + Alpha_PATCHABLE_OP = 34, + Alpha_PATCHABLE_FUNCTION_ENTER = 35, + Alpha_PATCHABLE_RET = 36, + Alpha_PATCHABLE_FUNCTION_EXIT = 37, + Alpha_PATCHABLE_TAIL_CALL = 38, + Alpha_PATCHABLE_EVENT_CALL = 39, + Alpha_PATCHABLE_TYPED_EVENT_CALL = 40, + Alpha_ICALL_BRANCH_FUNNEL = 41, + Alpha_MEMBARRIER = 42, + Alpha_G_ASSERT_SEXT = 43, + Alpha_G_ASSERT_ZEXT = 44, + Alpha_G_ASSERT_ALIGN = 45, + Alpha_G_ADD = 46, + Alpha_G_SUB = 47, + Alpha_G_MUL = 48, + Alpha_G_SDIV = 49, + Alpha_G_UDIV = 50, + Alpha_G_SREM = 51, + Alpha_G_UREM = 52, + Alpha_G_SDIVREM = 53, + Alpha_G_UDIVREM = 54, + Alpha_G_AND = 55, + Alpha_G_OR = 56, + Alpha_G_XOR = 57, + Alpha_G_IMPLICIT_DEF = 58, + Alpha_G_PHI = 59, + Alpha_G_FRAME_INDEX = 60, + Alpha_G_GLOBAL_VALUE = 61, + Alpha_G_EXTRACT = 62, + Alpha_G_UNMERGE_VALUES = 63, + Alpha_G_INSERT = 64, + Alpha_G_MERGE_VALUES = 65, + Alpha_G_BUILD_VECTOR = 66, + Alpha_G_BUILD_VECTOR_TRUNC = 67, + Alpha_G_CONCAT_VECTORS = 68, + Alpha_G_PTRTOINT = 69, + Alpha_G_INTTOPTR = 70, + Alpha_G_BITCAST = 71, + Alpha_G_FREEZE = 72, + Alpha_G_INTRINSIC_FPTRUNC_ROUND = 73, + Alpha_G_INTRINSIC_TRUNC = 74, + Alpha_G_INTRINSIC_ROUND = 75, + Alpha_G_INTRINSIC_LRINT = 76, + Alpha_G_INTRINSIC_ROUNDEVEN = 77, + Alpha_G_READCYCLECOUNTER = 78, + Alpha_G_LOAD = 79, + Alpha_G_SEXTLOAD = 80, + Alpha_G_ZEXTLOAD = 81, + Alpha_G_INDEXED_LOAD = 82, + Alpha_G_INDEXED_SEXTLOAD = 83, + Alpha_G_INDEXED_ZEXTLOAD = 84, + Alpha_G_STORE = 85, + Alpha_G_INDEXED_STORE = 86, + Alpha_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87, + Alpha_G_ATOMIC_CMPXCHG = 88, + Alpha_G_ATOMICRMW_XCHG = 89, + Alpha_G_ATOMICRMW_ADD = 90, + Alpha_G_ATOMICRMW_SUB = 91, + Alpha_G_ATOMICRMW_AND = 92, + Alpha_G_ATOMICRMW_NAND = 93, + Alpha_G_ATOMICRMW_OR = 94, + Alpha_G_ATOMICRMW_XOR = 95, + Alpha_G_ATOMICRMW_MAX = 96, + Alpha_G_ATOMICRMW_MIN = 97, + Alpha_G_ATOMICRMW_UMAX = 98, + Alpha_G_ATOMICRMW_UMIN = 99, + Alpha_G_ATOMICRMW_FADD = 100, + Alpha_G_ATOMICRMW_FSUB = 101, + Alpha_G_ATOMICRMW_FMAX = 102, + Alpha_G_ATOMICRMW_FMIN = 103, + Alpha_G_ATOMICRMW_UINC_WRAP = 104, + Alpha_G_ATOMICRMW_UDEC_WRAP = 105, + Alpha_G_FENCE = 106, + Alpha_G_BRCOND = 107, + Alpha_G_BRINDIRECT = 108, + Alpha_G_INVOKE_REGION_START = 109, + Alpha_G_INTRINSIC = 110, + Alpha_G_INTRINSIC_W_SIDE_EFFECTS = 111, + Alpha_G_ANYEXT = 112, + Alpha_G_TRUNC = 113, + Alpha_G_CONSTANT = 114, + Alpha_G_FCONSTANT = 115, + Alpha_G_VASTART = 116, + Alpha_G_VAARG = 117, + Alpha_G_SEXT = 118, + Alpha_G_SEXT_INREG = 119, + Alpha_G_ZEXT = 120, + Alpha_G_SHL = 121, + Alpha_G_LSHR = 122, + Alpha_G_ASHR = 123, + Alpha_G_FSHL = 124, + Alpha_G_FSHR = 125, + Alpha_G_ROTR = 126, + Alpha_G_ROTL = 127, + Alpha_G_ICMP = 128, + Alpha_G_FCMP = 129, + Alpha_G_SELECT = 130, + Alpha_G_UADDO = 131, + Alpha_G_UADDE = 132, + Alpha_G_USUBO = 133, + Alpha_G_USUBE = 134, + Alpha_G_SADDO = 135, + Alpha_G_SADDE = 136, + Alpha_G_SSUBO = 137, + Alpha_G_SSUBE = 138, + Alpha_G_UMULO = 139, + Alpha_G_SMULO = 140, + Alpha_G_UMULH = 141, + Alpha_G_SMULH = 142, + Alpha_G_UADDSAT = 143, + Alpha_G_SADDSAT = 144, + Alpha_G_USUBSAT = 145, + Alpha_G_SSUBSAT = 146, + Alpha_G_USHLSAT = 147, + Alpha_G_SSHLSAT = 148, + Alpha_G_SMULFIX = 149, + Alpha_G_UMULFIX = 150, + Alpha_G_SMULFIXSAT = 151, + Alpha_G_UMULFIXSAT = 152, + Alpha_G_SDIVFIX = 153, + Alpha_G_UDIVFIX = 154, + Alpha_G_SDIVFIXSAT = 155, + Alpha_G_UDIVFIXSAT = 156, + Alpha_G_FADD = 157, + Alpha_G_FSUB = 158, + Alpha_G_FMUL = 159, + Alpha_G_FMA = 160, + Alpha_G_FMAD = 161, + Alpha_G_FDIV = 162, + Alpha_G_FREM = 163, + Alpha_G_FPOW = 164, + Alpha_G_FPOWI = 165, + Alpha_G_FEXP = 166, + Alpha_G_FEXP2 = 167, + Alpha_G_FLOG = 168, + Alpha_G_FLOG2 = 169, + Alpha_G_FLOG10 = 170, + Alpha_G_FNEG = 171, + Alpha_G_FPEXT = 172, + Alpha_G_FPTRUNC = 173, + Alpha_G_FPTOSI = 174, + Alpha_G_FPTOUI = 175, + Alpha_G_SITOFP = 176, + Alpha_G_UITOFP = 177, + Alpha_G_FABS = 178, + Alpha_G_FCOPYSIGN = 179, + Alpha_G_IS_FPCLASS = 180, + Alpha_G_FCANONICALIZE = 181, + Alpha_G_FMINNUM = 182, + Alpha_G_FMAXNUM = 183, + Alpha_G_FMINNUM_IEEE = 184, + Alpha_G_FMAXNUM_IEEE = 185, + Alpha_G_FMINIMUM = 186, + Alpha_G_FMAXIMUM = 187, + Alpha_G_PTR_ADD = 188, + Alpha_G_PTRMASK = 189, + Alpha_G_SMIN = 190, + Alpha_G_SMAX = 191, + Alpha_G_UMIN = 192, + Alpha_G_UMAX = 193, + Alpha_G_ABS = 194, + Alpha_G_LROUND = 195, + Alpha_G_LLROUND = 196, + Alpha_G_BR = 197, + Alpha_G_BRJT = 198, + Alpha_G_INSERT_VECTOR_ELT = 199, + Alpha_G_EXTRACT_VECTOR_ELT = 200, + Alpha_G_SHUFFLE_VECTOR = 201, + Alpha_G_CTTZ = 202, + Alpha_G_CTTZ_ZERO_UNDEF = 203, + Alpha_G_CTLZ = 204, + Alpha_G_CTLZ_ZERO_UNDEF = 205, + Alpha_G_CTPOP = 206, + Alpha_G_BSWAP = 207, + Alpha_G_BITREVERSE = 208, + Alpha_G_FCEIL = 209, + Alpha_G_FCOS = 210, + Alpha_G_FSIN = 211, + Alpha_G_FSQRT = 212, + Alpha_G_FFLOOR = 213, + Alpha_G_FRINT = 214, + Alpha_G_FNEARBYINT = 215, + Alpha_G_ADDRSPACE_CAST = 216, + Alpha_G_BLOCK_ADDR = 217, + Alpha_G_JUMP_TABLE = 218, + Alpha_G_DYN_STACKALLOC = 219, + Alpha_G_STRICT_FADD = 220, + Alpha_G_STRICT_FSUB = 221, + Alpha_G_STRICT_FMUL = 222, + Alpha_G_STRICT_FDIV = 223, + Alpha_G_STRICT_FREM = 224, + Alpha_G_STRICT_FMA = 225, + Alpha_G_STRICT_FSQRT = 226, + Alpha_G_READ_REGISTER = 227, + Alpha_G_WRITE_REGISTER = 228, + Alpha_G_MEMCPY = 229, + Alpha_G_MEMCPY_INLINE = 230, + Alpha_G_MEMMOVE = 231, + Alpha_G_MEMSET = 232, + Alpha_G_BZERO = 233, + Alpha_G_VECREDUCE_SEQ_FADD = 234, + Alpha_G_VECREDUCE_SEQ_FMUL = 235, + Alpha_G_VECREDUCE_FADD = 236, + Alpha_G_VECREDUCE_FMUL = 237, + Alpha_G_VECREDUCE_FMAX = 238, + Alpha_G_VECREDUCE_FMIN = 239, + Alpha_G_VECREDUCE_ADD = 240, + Alpha_G_VECREDUCE_MUL = 241, + Alpha_G_VECREDUCE_AND = 242, + Alpha_G_VECREDUCE_OR = 243, + Alpha_G_VECREDUCE_XOR = 244, + Alpha_G_VECREDUCE_SMAX = 245, + Alpha_G_VECREDUCE_SMIN = 246, + Alpha_G_VECREDUCE_UMAX = 247, + Alpha_G_VECREDUCE_UMIN = 248, + Alpha_G_SBFX = 249, + Alpha_G_UBFX = 250, + Alpha_ADJUSTSTACKDOWN = 251, + Alpha_ADJUSTSTACKUP = 252, + Alpha_ALTENT = 253, + Alpha_CAS32 = 254, + Alpha_CAS64 = 255, + Alpha_LAS32 = 256, + Alpha_LAS64 = 257, + Alpha_MEMLABEL = 258, + Alpha_PCLABEL = 259, + Alpha_SWAP32 = 260, + Alpha_SWAP64 = 261, + Alpha_WTF = 262, + Alpha_ADDLi = 263, + Alpha_ADDLr = 264, + Alpha_ADDQi = 265, + Alpha_ADDQr = 266, + Alpha_ADDS = 267, + Alpha_ADDT = 268, + Alpha_ANDi = 269, + Alpha_ANDr = 270, + Alpha_BEQ = 271, + Alpha_BGE = 272, + Alpha_BGT = 273, + Alpha_BICi = 274, + Alpha_BICr = 275, + Alpha_BISi = 276, + Alpha_BISr = 277, + Alpha_BLBC = 278, + Alpha_BLBS = 279, + Alpha_BLE = 280, + Alpha_BLT = 281, + Alpha_BNE = 282, + Alpha_BR = 283, + Alpha_BSR = 284, + Alpha_CMOVEQi = 285, + Alpha_CMOVEQr = 286, + Alpha_CMOVGEi = 287, + Alpha_CMOVGEr = 288, + Alpha_CMOVGTi = 289, + Alpha_CMOVGTr = 290, + Alpha_CMOVLBCi = 291, + Alpha_CMOVLBCr = 292, + Alpha_CMOVLBSi = 293, + Alpha_CMOVLBSr = 294, + Alpha_CMOVLEi = 295, + Alpha_CMOVLEr = 296, + Alpha_CMOVLTi = 297, + Alpha_CMOVLTr = 298, + Alpha_CMOVNEi = 299, + Alpha_CMOVNEr = 300, + Alpha_CMPBGE = 301, + Alpha_CMPBGEi = 302, + Alpha_CMPEQ = 303, + Alpha_CMPEQi = 304, + Alpha_CMPLE = 305, + Alpha_CMPLEi = 306, + Alpha_CMPLT = 307, + Alpha_CMPLTi = 308, + Alpha_CMPTEQ = 309, + Alpha_CMPTLE = 310, + Alpha_CMPTLT = 311, + Alpha_CMPTUN = 312, + Alpha_CMPULE = 313, + Alpha_CMPULEi = 314, + Alpha_CMPULT = 315, + Alpha_CMPULTi = 316, + Alpha_COND_BRANCH_F = 317, + Alpha_COND_BRANCH_I = 318, + Alpha_CPYSES = 319, + Alpha_CPYSESt = 320, + Alpha_CPYSET = 321, + Alpha_CPYSNS = 322, + Alpha_CPYSNSt = 323, + Alpha_CPYSNT = 324, + Alpha_CPYSNTs = 325, + Alpha_CPYSS = 326, + Alpha_CPYSSt = 327, + Alpha_CPYST = 328, + Alpha_CPYSTs = 329, + Alpha_CTLZ = 330, + Alpha_CTPOP = 331, + Alpha_CTTZ = 332, + Alpha_CVTQS = 333, + Alpha_CVTQT = 334, + Alpha_CVTST = 335, + Alpha_CVTTQ = 336, + Alpha_CVTTS = 337, + Alpha_DIVS = 338, + Alpha_DIVT = 339, + Alpha_ECB = 340, + Alpha_EQVi = 341, + Alpha_EQVr = 342, + Alpha_EXCB = 343, + Alpha_EXTBL = 344, + Alpha_EXTBLi = 345, + Alpha_EXTLH = 346, + Alpha_EXTLHi = 347, + Alpha_EXTLL = 348, + Alpha_EXTLLi = 349, + Alpha_EXTQH = 350, + Alpha_EXTQHi = 351, + Alpha_EXTQL = 352, + Alpha_EXTQLi = 353, + Alpha_EXTWH = 354, + Alpha_EXTWHi = 355, + Alpha_EXTWL = 356, + Alpha_EXTWLi = 357, + Alpha_FBEQ = 358, + Alpha_FBGE = 359, + Alpha_FBGT = 360, + Alpha_FBLE = 361, + Alpha_FBLT = 362, + Alpha_FBNE = 363, + Alpha_FCMOVEQS = 364, + Alpha_FCMOVEQT = 365, + Alpha_FCMOVGES = 366, + Alpha_FCMOVGET = 367, + Alpha_FCMOVGTS = 368, + Alpha_FCMOVGTT = 369, + Alpha_FCMOVLES = 370, + Alpha_FCMOVLET = 371, + Alpha_FCMOVLTS = 372, + Alpha_FCMOVLTT = 373, + Alpha_FCMOVNES = 374, + Alpha_FCMOVNET = 375, + Alpha_FETCH = 376, + Alpha_FETCH_M = 377, + Alpha_FTOIS = 378, + Alpha_FTOIT = 379, + Alpha_INSBL = 380, + Alpha_INSBLi = 381, + Alpha_INSLH = 382, + Alpha_INSLHi = 383, + Alpha_INSLL = 384, + Alpha_INSLLi = 385, + Alpha_INSQH = 386, + Alpha_INSQHi = 387, + Alpha_INSQL = 388, + Alpha_INSQLi = 389, + Alpha_INSWH = 390, + Alpha_INSWHi = 391, + Alpha_INSWL = 392, + Alpha_INSWLi = 393, + Alpha_ITOFS = 394, + Alpha_ITOFT = 395, + Alpha_JMP = 396, + Alpha_JSR = 397, + Alpha_JSR_COROUTINE = 398, + Alpha_JSRs = 399, + Alpha_LDA = 400, + Alpha_LDAH = 401, + Alpha_LDAHg = 402, + Alpha_LDAHr = 403, + Alpha_LDAg = 404, + Alpha_LDAr = 405, + Alpha_LDBU = 406, + Alpha_LDBUr = 407, + Alpha_LDL = 408, + Alpha_LDL_L = 409, + Alpha_LDLr = 410, + Alpha_LDQ = 411, + Alpha_LDQ_L = 412, + Alpha_LDQ_U = 413, + Alpha_LDQl = 414, + Alpha_LDQr = 415, + Alpha_LDS = 416, + Alpha_LDSr = 417, + Alpha_LDT = 418, + Alpha_LDTr = 419, + Alpha_LDWU = 420, + Alpha_LDWUr = 421, + Alpha_MB = 422, + Alpha_MSKBL = 423, + Alpha_MSKBLi = 424, + Alpha_MSKLH = 425, + Alpha_MSKLHi = 426, + Alpha_MSKLL = 427, + Alpha_MSKLLi = 428, + Alpha_MSKQH = 429, + Alpha_MSKQHi = 430, + Alpha_MSKQL = 431, + Alpha_MSKQLi = 432, + Alpha_MSKWH = 433, + Alpha_MSKWHi = 434, + Alpha_MSKWL = 435, + Alpha_MSKWLi = 436, + Alpha_MULLi = 437, + Alpha_MULLr = 438, + Alpha_MULQi = 439, + Alpha_MULQr = 440, + Alpha_MULS = 441, + Alpha_MULT = 442, + Alpha_ORNOTi = 443, + Alpha_ORNOTr = 444, + Alpha_RC = 445, + Alpha_RETDAG = 446, + Alpha_RETDAGp = 447, + Alpha_RPCC = 448, + Alpha_RS = 449, + Alpha_S4ADDLi = 450, + Alpha_S4ADDLr = 451, + Alpha_S4ADDQi = 452, + Alpha_S4ADDQr = 453, + Alpha_S4SUBLi = 454, + Alpha_S4SUBLr = 455, + Alpha_S4SUBQi = 456, + Alpha_S4SUBQr = 457, + Alpha_S8ADDLi = 458, + Alpha_S8ADDLr = 459, + Alpha_S8ADDQi = 460, + Alpha_S8ADDQr = 461, + Alpha_S8SUBLi = 462, + Alpha_S8SUBLr = 463, + Alpha_S8SUBQi = 464, + Alpha_S8SUBQr = 465, + Alpha_SEXTB = 466, + Alpha_SEXTW = 467, + Alpha_SLi = 468, + Alpha_SLr = 469, + Alpha_SQRTS = 470, + Alpha_SQRTT = 471, + Alpha_SRAi = 472, + Alpha_SRAr = 473, + Alpha_SRLi = 474, + Alpha_SRLr = 475, + Alpha_STB = 476, + Alpha_STBr = 477, + Alpha_STL = 478, + Alpha_STL_C = 479, + Alpha_STLr = 480, + Alpha_STQ = 481, + Alpha_STQ_C = 482, + Alpha_STQ_U = 483, + Alpha_STQr = 484, + Alpha_STS = 485, + Alpha_STSr = 486, + Alpha_STT = 487, + Alpha_STTr = 488, + Alpha_STW = 489, + Alpha_STWr = 490, + Alpha_SUBLi = 491, + Alpha_SUBLr = 492, + Alpha_SUBQi = 493, + Alpha_SUBQr = 494, + Alpha_SUBS = 495, + Alpha_SUBT = 496, + Alpha_TRAPB = 497, + Alpha_UMULHi = 498, + Alpha_UMULHr = 499, + Alpha_WH64 = 500, + Alpha_WH64EN = 501, + Alpha_WMB = 502, + Alpha_XORi = 503, + Alpha_XORr = 504, + Alpha_ZAPNOTi = 505, + INSTRUCTION_LIST_END = 506 + }; + +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + + +static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, }; +static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<, 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */ +/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + Alpha_NoRegister, + Alpha_F0 = 1, + Alpha_F1 = 2, + Alpha_F2 = 3, + Alpha_F3 = 4, + Alpha_F4 = 5, + Alpha_F5 = 6, + Alpha_F6 = 7, + Alpha_F7 = 8, + Alpha_F8 = 9, + Alpha_F9 = 10, + Alpha_F10 = 11, + Alpha_F11 = 12, + Alpha_F12 = 13, + Alpha_F13 = 14, + Alpha_F14 = 15, + Alpha_F15 = 16, + Alpha_F16 = 17, + Alpha_F17 = 18, + Alpha_F18 = 19, + Alpha_F19 = 20, + Alpha_F20 = 21, + Alpha_F21 = 22, + Alpha_F22 = 23, + Alpha_F23 = 24, + Alpha_F24 = 25, + Alpha_F25 = 26, + Alpha_F26 = 27, + Alpha_F27 = 28, + Alpha_F28 = 29, + Alpha_F29 = 30, + Alpha_F30 = 31, + Alpha_F31 = 32, + Alpha_R0 = 33, + Alpha_R1 = 34, + Alpha_R2 = 35, + Alpha_R3 = 36, + Alpha_R4 = 37, + Alpha_R5 = 38, + Alpha_R6 = 39, + Alpha_R7 = 40, + Alpha_R8 = 41, + Alpha_R9 = 42, + Alpha_R10 = 43, + Alpha_R11 = 44, + Alpha_R12 = 45, + Alpha_R13 = 46, + Alpha_R14 = 47, + Alpha_R15 = 48, + Alpha_R16 = 49, + Alpha_R17 = 50, + Alpha_R18 = 51, + Alpha_R19 = 52, + Alpha_R20 = 53, + Alpha_R21 = 54, + Alpha_R22 = 55, + Alpha_R23 = 56, + Alpha_R24 = 57, + Alpha_R25 = 58, + Alpha_R26 = 59, + Alpha_R27 = 60, + Alpha_R28 = 61, + Alpha_R29 = 62, + Alpha_R30 = 63, + Alpha_R31 = 64, + NUM_TARGET_REGS // 65 +}; + +// Register classes + +enum { + Alpha_F4RCRegClassID = 0, + Alpha_F8RCRegClassID = 1, + Alpha_GPRCRegClassID = 2, + +}; +#endif // GET_REGINFO_ENUM + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg AlphaRegDiffLists[] = { + /* 0 */ 65535, 0, +}; + +static const uint16_t AlphaSubRegIdxLists[] = { + /* 0 */ 0, +}; + +static const MCRegisterDesc AlphaRegDesc[] = { // Descriptors + { 3, 0, 0, 0, 0, 0 }, + { 24, 1, 1, 0, 1, 0 }, + { 54, 1, 1, 0, 1, 0 }, + { 76, 1, 1, 0, 1, 0 }, + { 98, 1, 1, 0, 1, 0 }, + { 120, 1, 1, 0, 1, 0 }, + { 142, 1, 1, 0, 1, 0 }, + { 164, 1, 1, 0, 1, 0 }, + { 186, 1, 1, 0, 1, 0 }, + { 208, 1, 1, 0, 1, 0 }, + { 230, 1, 1, 0, 1, 0 }, + { 0, 1, 1, 0, 1, 0 }, + { 30, 1, 1, 0, 1, 0 }, + { 60, 1, 1, 0, 1, 0 }, + { 82, 1, 1, 0, 1, 0 }, + { 104, 1, 1, 0, 1, 0 }, + { 126, 1, 1, 0, 1, 0 }, + { 148, 1, 1, 0, 1, 0 }, + { 170, 1, 1, 0, 1, 0 }, + { 192, 1, 1, 0, 1, 0 }, + { 214, 1, 1, 0, 1, 0 }, + { 8, 1, 1, 0, 1, 0 }, + { 38, 1, 1, 0, 1, 0 }, + { 68, 1, 1, 0, 1, 0 }, + { 90, 1, 1, 0, 1, 0 }, + { 112, 1, 1, 0, 1, 0 }, + { 134, 1, 1, 0, 1, 0 }, + { 156, 1, 1, 0, 1, 0 }, + { 178, 1, 1, 0, 1, 0 }, + { 200, 1, 1, 0, 1, 0 }, + { 222, 1, 1, 0, 1, 0 }, + { 16, 1, 1, 0, 1, 0 }, + { 46, 1, 1, 0, 1, 0 }, + { 27, 1, 1, 0, 1, 0 }, + { 57, 1, 1, 0, 1, 0 }, + { 79, 1, 1, 0, 1, 0 }, + { 101, 1, 1, 0, 1, 0 }, + { 123, 1, 1, 0, 1, 0 }, + { 145, 1, 1, 0, 1, 0 }, + { 167, 1, 1, 0, 1, 0 }, + { 189, 1, 1, 0, 1, 0 }, + { 211, 1, 1, 0, 1, 0 }, + { 233, 1, 1, 0, 1, 0 }, + { 4, 1, 1, 0, 1, 0 }, + { 34, 1, 1, 0, 1, 0 }, + { 64, 1, 1, 0, 1, 0 }, + { 86, 1, 1, 0, 1, 0 }, + { 108, 1, 1, 0, 1, 0 }, + { 130, 1, 1, 0, 1, 0 }, + { 152, 1, 1, 0, 1, 0 }, + { 174, 1, 1, 0, 1, 0 }, + { 196, 1, 1, 0, 1, 0 }, + { 218, 1, 1, 0, 1, 0 }, + { 12, 1, 1, 0, 1, 0 }, + { 42, 1, 1, 0, 1, 0 }, + { 72, 1, 1, 0, 1, 0 }, + { 94, 1, 1, 0, 1, 0 }, + { 116, 1, 1, 0, 1, 0 }, + { 138, 1, 1, 0, 1, 0 }, + { 160, 1, 1, 0, 1, 0 }, + { 182, 1, 1, 0, 1, 0 }, + { 204, 1, 1, 0, 1, 0 }, + { 226, 1, 1, 0, 1, 0 }, + { 20, 1, 1, 0, 1, 0 }, + { 50, 1, 1, 0, 1, 0 }, +}; + + // F4RC Register Class... + static const MCPhysReg F4RC[] = { + Alpha_F0, Alpha_F1, Alpha_F10, Alpha_F11, Alpha_F12, Alpha_F13, Alpha_F14, Alpha_F15, Alpha_F16, Alpha_F17, Alpha_F18, Alpha_F19, Alpha_F20, Alpha_F21, Alpha_F22, Alpha_F23, Alpha_F24, Alpha_F25, Alpha_F26, Alpha_F27, Alpha_F28, Alpha_F29, Alpha_F30, Alpha_F2, Alpha_F3, Alpha_F4, Alpha_F5, Alpha_F6, Alpha_F7, Alpha_F8, Alpha_F9, Alpha_F31, + }; + + // F4RC Bit set. + static const uint8_t F4RCBits[] = { + 0xfe, 0xff, 0xff, 0xff, 0x01, + }; + + // F8RC Register Class... + static const MCPhysReg F8RC[] = { + Alpha_F0, Alpha_F1, Alpha_F10, Alpha_F11, Alpha_F12, Alpha_F13, Alpha_F14, Alpha_F15, Alpha_F16, Alpha_F17, Alpha_F18, Alpha_F19, Alpha_F20, Alpha_F21, Alpha_F22, Alpha_F23, Alpha_F24, Alpha_F25, Alpha_F26, Alpha_F27, Alpha_F28, Alpha_F29, Alpha_F30, Alpha_F2, Alpha_F3, Alpha_F4, Alpha_F5, Alpha_F6, Alpha_F7, Alpha_F8, Alpha_F9, Alpha_F31, + }; + + // F8RC Bit set. + static const uint8_t F8RCBits[] = { + 0xfe, 0xff, 0xff, 0xff, 0x01, + }; + + // GPRC Register Class... + static const MCPhysReg GPRC[] = { + Alpha_R0, Alpha_R1, Alpha_R2, Alpha_R3, Alpha_R4, Alpha_R5, Alpha_R6, Alpha_R7, Alpha_R8, Alpha_R16, Alpha_R17, Alpha_R18, Alpha_R19, Alpha_R20, Alpha_R21, Alpha_R22, Alpha_R23, Alpha_R24, Alpha_R25, Alpha_R28, Alpha_R27, Alpha_R26, Alpha_R29, Alpha_R9, Alpha_R10, Alpha_R11, Alpha_R12, Alpha_R13, Alpha_R14, Alpha_R15, Alpha_R30, Alpha_R31, + }; + + // GPRC Bit set. + static const uint8_t GPRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + }; + +static const MCRegisterClass AlphaMCRegisterClasses[] = { + { F4RC, F4RCBits, sizeof(F4RCBits) }, + { F8RC, F8RCBits, sizeof(F8RCBits) }, + { GPRC, GPRCBits, sizeof(GPRCBits) }, +}; + +static const uint16_t AlphaRegEncodingTable[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; +#endif // GET_REGINFO_MC_DESC + + + diff --git a/arch/Alpha/AlphaGenSubtargetInfo.inc b/arch/Alpha/AlphaGenSubtargetInfo.inc new file mode 100644 index 0000000000..7082918b2d --- /dev/null +++ b/arch/Alpha/AlphaGenSubtargetInfo.inc @@ -0,0 +1,24 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */ +/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#ifdef GET_SUBTARGETINFO_ENUM +#undef GET_SUBTARGETINFO_ENUM + +enum { + Alpha_FeatureCIX = 0, + Alpha_NumSubtargetFeatures = 1 +}; +#endif // GET_SUBTARGETINFO_ENUM + + + diff --git a/arch/Alpha/AlphaInstPrinter.c b/arch/Alpha/AlphaInstPrinter.c new file mode 100644 index 0000000000..dff35e1d4b --- /dev/null +++ b/arch/Alpha/AlphaInstPrinter.c @@ -0,0 +1,90 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_ALPHA + +#include +#include +#include +#include + +#include "../../utils.h" +#include "../../Mapping.h" +#include "../../MCInstPrinter.h" + +#include "AlphaLinkage.h" +#include "AlphaMapping.h" + +static const char *getRegisterName(unsigned RegNo); + +static void printInstruction(MCInst *, uint64_t, SStream *); +static void printOperand(MCInst *MI, int OpNum, SStream *O); +static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O); + +#define GET_INSTRINFO_ENUM + +#include "AlphaGenInstrInfo.inc" + +#define GET_REGINFO_ENUM + +#include "AlphaGenRegisterInfo.inc" + +static void printOperand(MCInst *MI, int OpNum, SStream *O) +{ + if (OpNum >= MI->size) + return; + + Alpha_add_cs_detail(MI, OpNum); + + MCOperand *Op; + Op = MCInst_getOperand(MI, OpNum); + if (MCOperand_isReg(Op)) { + unsigned reg = MCOperand_getReg(Op); + SStream_concat(O, "%s", getRegisterName(reg)); + } else if (MCOperand_isImm(Op)) { + int64_t Imm = MCOperand_getImm(Op); + if (Imm >= 0) { + if (Imm > HEX_THRESHOLD) + SStream_concat(O, "0x%" PRIx64, Imm); + else + SStream_concat(O, "%" PRIu64, Imm); + } else { + if (Imm < -HEX_THRESHOLD) + SStream_concat(O, "-0x%" PRIx64, -Imm); + else + SStream_concat(O, "-%" PRIu64, -Imm); + } + } +} + +static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, (OpNum)); + + uint64_t Imm = MCOperand_getImm(Op); + uint64_t Target = Address + 4 + (int16_t) (Imm << 2); + + Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM, Target); + printUInt64(O, Target); +} + +#define PRINT_ALIAS_INSTR + +#include "AlphaGenAsmWriter.inc" + +const char *Alpha_LLVM_getRegisterName(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return getRegisterName(id); +#else + return NULL; +#endif +} + +void Alpha_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info) +{ + printAliasInstr(MI, MI->address, O); + printInstruction(MI, MI->address, O); +} + +#endif \ No newline at end of file diff --git a/arch/Alpha/AlphaLinkage.h b/arch/Alpha/AlphaLinkage.h new file mode 100644 index 0000000000..c3501ddecd --- /dev/null +++ b/arch/Alpha/AlphaLinkage.h @@ -0,0 +1,21 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_ALPHA_LINKAGE_H +#define CS_ALPHA_LINKAGE_H + +// Function defintions to call static LLVM functions. + +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" +#include "AlphaMapping.h" + +const char *Alpha_LLVM_getRegisterName(csh handle, unsigned int id); +void Alpha_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info); +DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes, + size_t ByteLen, MCInst *MI, + uint16_t *Size, uint64_t Address, + void *Info); + +#endif // CS_ALPHA_LINKAGE_H \ No newline at end of file diff --git a/arch/Alpha/AlphaMapping.c b/arch/Alpha/AlphaMapping.c new file mode 100644 index 0000000000..30ac84574d --- /dev/null +++ b/arch/Alpha/AlphaMapping.c @@ -0,0 +1,182 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_ALPHA + +#include // debug +#include + +#include "../../Mapping.h" +#include "../../cs_priv.h" +#include "../../cs_simple_types.h" +#include "../../utils.h" + +#include "AlphaLinkage.h" +#include "AlphaMapping.h" +#include "./AlphaDisassembler.h" + +#define GET_INSTRINFO_ENUM + +#include "AlphaGenInstrInfo.inc" + +static insn_map insns[] = { +#include "AlphaGenCSMappingInsn.inc" +}; + +const map_insn_ops insn_operands[] = { +#include "AlphaGenCSMappingInsnOp.inc" +}; + +void Alpha_init_cs_detail(MCInst *MI) +{ + if (detail_is_set(MI)) { + memset(get_detail(MI), 0, + offsetof(cs_detail, alpha) + sizeof(cs_alpha)); + } +} + +void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum) +{ + if (!detail_is_set(MI)) + return; + + cs_op_type op_type = map_get_op_type(MI, OpNum); + if (op_type == CS_OP_IMM) + Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM, + MCInst_getOpVal(MI, OpNum)); + else if (op_type == CS_OP_REG) + Alpha_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum)); + else + assert(0 && "Op type not handled."); +} + +void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType, + int64_t Imm) +{ + if (!detail_is_set(MI)) + return; + assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM)); + assert(map_get_op_type(MI, OpNum) == CS_OP_IMM); + assert(ImmType == ALPHA_OP_IMM); + + Alpha_get_detail_op(MI, 0)->type = ImmType; + Alpha_get_detail_op(MI, 0)->imm = Imm; + Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + Alpha_inc_op_count(MI); +} + +void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg) +{ + if (!detail_is_set(MI)) + return; + assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM)); + assert(map_get_op_type(MI, OpNum) == CS_OP_REG); + + Alpha_get_detail_op(MI, 0)->type = ALPHA_OP_REG; + Alpha_get_detail_op(MI, 0)->reg = Reg; + Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + Alpha_inc_op_count(MI); +} + +// given internal insn id, return public instruction info +void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + unsigned short i; + + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i == 0) { return; } + insn->id = insns[i].mapid; + + if (insn->detail) { +#ifndef CAPSTONE_DIET + memcpy(insn->detail->regs_read, insns[i].regs_use, + sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = + (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, + sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = + (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, + sizeof(insns[i].groups)); + insn->detail->groups_count = + (uint8_t)count_positive8(insns[i].groups); +#endif + } +} + +#ifndef CAPSTONE_DIET + +static const char *insn_names[] = { +#include "AlphaGenCSMappingInsnName.inc" +}; + +// special alias insn +// static name_map alias_insn_names[] = {{0, NULL}}; +#endif + +const char *Alpha_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + if (id >= ALPHA_INS_ENDING) + return NULL; + + if (id < ARR_SIZE(insn_names)) + return insn_names[id]; + + return NULL; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static name_map group_name_maps[] = { + {Alpha_GRP_INVALID, NULL}, + {Alpha_GRP_CALL, "call"}, + {Alpha_GRP_JUMP, "jump"}, + {Alpha_GRP_BRANCH_RELATIVE, "branch_relative"}, +}; +#endif + +const char *Alpha_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +const char *Alpha_getRegisterName(csh handle, unsigned int id) +{ + return Alpha_LLVM_getRegisterName(handle, id); +} + +void Alpha_printInst(MCInst *MI, SStream *O, void *Info) +{ + return Alpha_LLVM_printInstruction(MI, O, Info); +} + +void Alpha_set_instr_map_data(MCInst *MI) +{ + map_cs_id(MI, insns, ARR_SIZE(insns)); + map_implicit_reads(MI, insns); + map_implicit_writes(MI, insns); + map_groups(MI, insns); +} + +bool Alpha_getInstruction(csh handle, const uint8_t *code, + size_t code_len, MCInst *instr, + uint16_t *size, uint64_t address, void *info) +{ + Alpha_init_cs_detail(instr); + bool Result = Alpha_LLVM_getInstruction(handle, code, code_len, instr, size, + address, info); + Alpha_set_instr_map_data(instr); + return Result; +} + +#endif \ No newline at end of file diff --git a/arch/Alpha/AlphaMapping.h b/arch/Alpha/AlphaMapping.h new file mode 100644 index 0000000000..3230800e30 --- /dev/null +++ b/arch/Alpha/AlphaMapping.h @@ -0,0 +1,35 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_ALPHA_MAP_H +#define CS_ALPHA_MAP_H + +#include "../../MCDisassembler.h" +#include "../../MCInst.h" +#include "../../SStream.h" +#include + +// unsigned int Alpha_map_insn_id(cs_struct *h, unsigned int id); + +// given internal insn id, return public instruction info +void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *Alpha_insn_name(csh handle, unsigned int id); + +const char *Alpha_group_name(csh handle, unsigned int id); + +void Alpha_printInst(MCInst *MI, SStream *O, void *Info); + +const char *Alpha_getRegisterName(csh handle, unsigned int id); +bool Alpha_getInstruction(csh handle, const uint8_t *code, + size_t code_len, MCInst *instr, + uint16_t *size, uint64_t address, void *info); +void Alpha_init_cs_detail(MCInst *MI); +void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum); + +void Alpha_set_instr_map_data(MCInst *MI); +void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType, + int64_t Imm); +void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg); + +#endif diff --git a/arch/Alpha/AlphaModule.c b/arch/Alpha/AlphaModule.c new file mode 100644 index 0000000000..271f177656 --- /dev/null +++ b/arch/Alpha/AlphaModule.c @@ -0,0 +1,41 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_ALPHA + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "AlphaDisassembler.h" +#include "AlphaMapping.h" +#include "AlphaModule.h" + +cs_err ALPHA_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + + mri = cs_mem_malloc(sizeof(*mri)); + + Alpha_init(mri); + ud->printer = Alpha_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = Alpha_getInstruction; + ud->post_printer = NULL; + + ud->reg_name = Alpha_getRegisterName; + ud->insn_id = Alpha_get_insn_id; + ud->insn_name = Alpha_insn_name; + ud->group_name = Alpha_group_name; + + return CS_ERR_OK; +} + +cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + if (type == CS_OPT_SYNTAX) + handle->syntax = (int)value; + + return CS_ERR_OK; +} + +#endif diff --git a/arch/Alpha/AlphaModule.h b/arch/Alpha/AlphaModule.h new file mode 100644 index 0000000000..3d349a7e48 --- /dev/null +++ b/arch/Alpha/AlphaModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CAPSTONE_ALPHAMODULE_H +#define CAPSTONE_ALPHAMODULE_H + +#include "../../utils.h" + +cs_err ALPHA_global_init(cs_struct *ud); +cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif // CAPSTONE_ALPHAMODULE_H diff --git a/bindings/Makefile b/bindings/Makefile index 3aec5da98c..c730917d40 100644 --- a/bindings/Makefile +++ b/bindings/Makefile @@ -23,6 +23,7 @@ TEST_M680X = $(TMPDIR)/test_m680x TEST_TRICORE = $(TMPDIR)/test_tricore TEST_SH = $(TMPDIR)/test_sh TEST_TMS320C64X = $(TMPDIR)/test_tms320c64x +TEST_ALPHA = $(TMPDIR)/test_alpha PYTHON3 ?= python3 @@ -64,6 +65,7 @@ expected: ../tests/test_sh > $(TEST_SH)_e ../tests/test_tricore > $(TEST_TRICORE)_e ../tests/test_tms320c64x > $(TEST_TMS320C64X)_e + ../tests/test_alpha > $(TEST_ALPHA)_e python: FORCE cd python && $(MAKE) @@ -88,6 +90,7 @@ python: FORCE $(PYTHON3) python/test_sh.py > $(TEST_SH)_o $(PYTHON3) python/test_tricore.py > $(TEST_TRICORE)_o $(PYTHON3) python/test_tms320c64x.py > $(TEST_TMS320C64X)_o + $(PYTHON3) python/test_alpha.py > $(TEST_ALPHA)_o $(MAKE) test_diff java: FORCE @@ -127,6 +130,7 @@ test_diff: FORCE $(DIFF) $(TEST_SH)_e $(TEST_SH)_o $(DIFF) $(TEST_TRICORE)_e $(TEST_TRICORE)_o $(DIFF) $(TEST_TMS320C64X)_e $(TEST_TMS320C64X)_o + $(DIFF) $(TEST_ALPHA)_e $(TEST_ALPHA)_o clean: rm -rf $(TMPDIR) diff --git a/bindings/const_generator.py b/bindings/const_generator.py index 6d65a8d8fc..2171c7b78c 100644 --- a/bindings/const_generator.py +++ b/bindings/const_generator.py @@ -5,7 +5,7 @@ INCL_DIR = '../include/capstone/' -include = [ 'arm.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h' ] +include = [ 'arm.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h' ] template = { 'java': { @@ -53,6 +53,7 @@ 'riscv.h': 'riscv', 'sh.h': 'sh', 'tricore.h': ['TRICORE', 'TriCore'], + 'alpha.h': ['ALPHA', 'Alpha'], 'comment_open': '#', 'comment_close': '', }, diff --git a/bindings/python/Makefile b/bindings/python/Makefile index 3b25872421..a1e6f7bf19 100644 --- a/bindings/python/Makefile +++ b/bindings/python/Makefile @@ -72,7 +72,7 @@ TESTS = test_basic.py test_detail.py test_arm.py test_aarch64.py test_m68k.py te TESTS += test_ppc.py test_sparc.py test_systemz.py test_x86.py test_xcore.py test_tms320c64x.py TESTS += test_m680x.py test_skipdata.py test_mos65xx.py test_bpf.py test_riscv.py TESTS += test_evm.py test_tricore.py test_wasm.py test_sh.py -TESTS += test_lite.py test_iter.py test_customized_mnem.py +TESTS += test_lite.py test_iter.py test_customized_mnem.py test_alpha.py check: @for t in $(TESTS); do \ diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index 6f16a922f2..e8e3a8ecaa 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -41,6 +41,7 @@ 'CS_ARCH_RISCV', 'CS_ARCH_SH', 'CS_ARCH_TRICORE', + 'CS_ARCH_ALPHA', 'CS_ARCH_ALL', 'CS_MODE_LITTLE_ENDIAN', @@ -217,7 +218,8 @@ CS_ARCH_RISCV = 15 CS_ARCH_SH = 16 CS_ARCH_TRICORE = 17 -CS_ARCH_MAX = 18 +CS_ARCH_ALPHA = 18 +CS_ARCH_MAX = 19 CS_ARCH_ALL = 0xFFFF # disasm mode @@ -441,7 +443,7 @@ def copy_ctypes_list(src): return [copy_ctypes(n) for n in src] # Weird import placement because these modules are needed by the below code but need the above functions -from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore +from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, alpha class _cs_arch(ctypes.Union): _fields_ = ( @@ -463,13 +465,14 @@ class _cs_arch(ctypes.Union): ('riscv', riscv.CsRISCV), ('sh', sh.CsSH), ('tricore', tricore.CsTriCore), + ('alpha', alpha.CsAlpha), ) class _cs_detail(ctypes.Structure): _fields_ = ( ('regs_read', ctypes.c_uint16 * 20), ('regs_read_count', ctypes.c_ubyte), - ('regs_write', ctypes.c_uint16 * 20), + ('regs_write', ctypes.c_uint16 * 47), ('regs_write_count', ctypes.c_ubyte), ('groups', ctypes.c_ubyte * 8), ('groups_count', ctypes.c_ubyte), @@ -812,6 +815,8 @@ def __gen_detail(self): (self.sh_insn, self.sh_size, self.operands) = sh.get_arch_info(self._raw.detail.contents.arch.sh) elif arch == CS_ARCH_TRICORE: (self.update_flags, self.operands) = tricore.get_arch_info(self._raw.detail.contents.arch.tricore) + elif arch == CS_ARCH_ALPHA: + (self.operands) = alpha.get_arch_info(self._raw.detail.contents.arch.alpha) def __getattr__(self, name): @@ -1304,7 +1309,7 @@ def debug(): "sysz": CS_ARCH_SYSZ, 'xcore': CS_ARCH_XCORE, "tms320c64x": CS_ARCH_TMS320C64X, "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX, 'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE, - 'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, + 'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA, } all_archs = "" diff --git a/bindings/python/capstone/alpha.py b/bindings/python/capstone/alpha.py new file mode 100644 index 0000000000..d6ab5110bf --- /dev/null +++ b/bindings/python/capstone/alpha.py @@ -0,0 +1,43 @@ +import ctypes +from . import copy_ctypes_list +from .alpha_const import * + +class AlphaOpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_uint8), + ('disp', ctypes.c_int32), + ) + + +class AlphaOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int32), + ) + + +class AlphaOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', AlphaOpValue), + ('access', ctypes.c_uint8) + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + +# Instruction structure +class CsAlpha(ctypes.Structure): + _fields_ = ( + ('op_count', ctypes.c_uint8), + ('operands', AlphaOp * 3) + ) + +def get_arch_info(a): + return (copy_ctypes_list(a.operands[:a.op_count])) diff --git a/bindings/python/capstone/alpha_const.py b/bindings/python/capstone/alpha_const.py new file mode 100644 index 0000000000..227acd2744 --- /dev/null +++ b/bindings/python/capstone/alpha_const.py @@ -0,0 +1,239 @@ +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [alpha_const.py] + +# Operand type for instruction's operands +ALPHA_OP_INVALID = CS_OP_INVALID +ALPHA_OP_REG = CS_OP_REG +ALPHA_OP_IMM = CS_OP_IMM + +# Alpha registers + +Alpha_REG_INVALID = 0 +Alpha_REG_F0 = 1 +Alpha_REG_F1 = 2 +Alpha_REG_F2 = 3 +Alpha_REG_F3 = 4 +Alpha_REG_F4 = 5 +Alpha_REG_F5 = 6 +Alpha_REG_F6 = 7 +Alpha_REG_F7 = 8 +Alpha_REG_F8 = 9 +Alpha_REG_F9 = 10 +Alpha_REG_F10 = 11 +Alpha_REG_F11 = 12 +Alpha_REG_F12 = 13 +Alpha_REG_F13 = 14 +Alpha_REG_F14 = 15 +Alpha_REG_F15 = 16 +Alpha_REG_F16 = 17 +Alpha_REG_F17 = 18 +Alpha_REG_F18 = 19 +Alpha_REG_F19 = 20 +Alpha_REG_F20 = 21 +Alpha_REG_F21 = 22 +Alpha_REG_F22 = 23 +Alpha_REG_F23 = 24 +Alpha_REG_F24 = 25 +Alpha_REG_F25 = 26 +Alpha_REG_F26 = 27 +Alpha_REG_F27 = 28 +Alpha_REG_F28 = 29 +Alpha_REG_F29 = 30 +Alpha_REG_F30 = 31 +Alpha_REG_F31 = 32 +Alpha_REG_R0 = 33 +Alpha_REG_R1 = 34 +Alpha_REG_R2 = 35 +Alpha_REG_R3 = 36 +Alpha_REG_R4 = 37 +Alpha_REG_R5 = 38 +Alpha_REG_R6 = 39 +Alpha_REG_R7 = 40 +Alpha_REG_R8 = 41 +Alpha_REG_R9 = 42 +Alpha_REG_R10 = 43 +Alpha_REG_R11 = 44 +Alpha_REG_R12 = 45 +Alpha_REG_R13 = 46 +Alpha_REG_R14 = 47 +Alpha_REG_R15 = 48 +Alpha_REG_R16 = 49 +Alpha_REG_R17 = 50 +Alpha_REG_R18 = 51 +Alpha_REG_R19 = 52 +Alpha_REG_R20 = 53 +Alpha_REG_R21 = 54 +Alpha_REG_R22 = 55 +Alpha_REG_R23 = 56 +Alpha_REG_R24 = 57 +Alpha_REG_R25 = 58 +Alpha_REG_R26 = 59 +Alpha_REG_R27 = 60 +Alpha_REG_R28 = 61 +Alpha_REG_R29 = 62 +Alpha_REG_R30 = 63 +Alpha_REG_R31 = 64 +Alpha_REG_ENDING = 65 + +# Alpha instruction +Alpha_INS_INVALID = 66 +Alpha_INS_ADDL = 67 +Alpha_INS_ADDQ = 68 +Alpha_INS_ADDSsSU = 69 +Alpha_INS_ADDTsSU = 70 +Alpha_INS_AND = 71 +Alpha_INS_BEQ = 72 +Alpha_INS_BGE = 73 +Alpha_INS_BGT = 74 +Alpha_INS_BIC = 75 +Alpha_INS_BIS = 76 +Alpha_INS_BLBC = 77 +Alpha_INS_BLBS = 78 +Alpha_INS_BLE = 79 +Alpha_INS_BLT = 80 +Alpha_INS_BNE = 81 +Alpha_INS_BR = 82 +Alpha_INS_BSR = 83 +Alpha_INS_CMOVEQ = 84 +Alpha_INS_CMOVGE = 85 +Alpha_INS_CMOVGT = 86 +Alpha_INS_CMOVLBC = 87 +Alpha_INS_CMOVLBS = 88 +Alpha_INS_CMOVLE = 89 +Alpha_INS_CMOVLT = 90 +Alpha_INS_CMOVNE = 91 +Alpha_INS_CMPBGE = 92 +Alpha_INS_CMPEQ = 93 +Alpha_INS_CMPLE = 94 +Alpha_INS_CMPLT = 95 +Alpha_INS_CMPTEQsSU = 96 +Alpha_INS_CMPTLEsSU = 97 +Alpha_INS_CMPTLTsSU = 98 +Alpha_INS_CMPTUNsSU = 99 +Alpha_INS_CMPULE = 100 +Alpha_INS_CMPULT = 101 +Alpha_INS_COND_BRANCH = 102 +Alpha_INS_CPYSE = 103 +Alpha_INS_CPYSN = 104 +Alpha_INS_CPYS = 105 +Alpha_INS_CTLZ = 106 +Alpha_INS_CTPOP = 107 +Alpha_INS_CTTZ = 108 +Alpha_INS_CVTQSsSUI = 109 +Alpha_INS_CVTQTsSUI = 110 +Alpha_INS_CVTSTsS = 111 +Alpha_INS_CVTTQsSVC = 112 +Alpha_INS_CVTTSsSUI = 113 +Alpha_INS_DIVSsSU = 114 +Alpha_INS_DIVTsSU = 115 +Alpha_INS_ECB = 116 +Alpha_INS_EQV = 117 +Alpha_INS_EXCB = 118 +Alpha_INS_EXTBL = 119 +Alpha_INS_EXTLH = 120 +Alpha_INS_EXTLL = 121 +Alpha_INS_EXTQH = 122 +Alpha_INS_EXTQL = 123 +Alpha_INS_EXTWH = 124 +Alpha_INS_EXTWL = 125 +Alpha_INS_FBEQ = 126 +Alpha_INS_FBGE = 127 +Alpha_INS_FBGT = 128 +Alpha_INS_FBLE = 129 +Alpha_INS_FBLT = 130 +Alpha_INS_FBNE = 131 +Alpha_INS_FCMOVEQ = 132 +Alpha_INS_FCMOVGE = 133 +Alpha_INS_FCMOVGT = 134 +Alpha_INS_FCMOVLE = 135 +Alpha_INS_FCMOVLT = 136 +Alpha_INS_FCMOVNE = 137 +Alpha_INS_FETCH = 138 +Alpha_INS_FETCH_M = 139 +Alpha_INS_FTOIS = 140 +Alpha_INS_FTOIT = 141 +Alpha_INS_INSBL = 142 +Alpha_INS_INSLH = 143 +Alpha_INS_INSLL = 144 +Alpha_INS_INSQH = 145 +Alpha_INS_INSQL = 146 +Alpha_INS_INSWH = 147 +Alpha_INS_INSWL = 148 +Alpha_INS_ITOFS = 149 +Alpha_INS_ITOFT = 150 +Alpha_INS_JMP = 151 +Alpha_INS_JSR = 152 +Alpha_INS_JSR_COROUTINE = 153 +Alpha_INS_LDA = 154 +Alpha_INS_LDAH = 155 +Alpha_INS_LDBU = 156 +Alpha_INS_LDL = 157 +Alpha_INS_LDL_L = 158 +Alpha_INS_LDQ = 159 +Alpha_INS_LDQ_L = 160 +Alpha_INS_LDQ_U = 161 +Alpha_INS_LDS = 162 +Alpha_INS_LDT = 163 +Alpha_INS_LDWU = 164 +Alpha_INS_MB = 165 +Alpha_INS_MSKBL = 166 +Alpha_INS_MSKLH = 167 +Alpha_INS_MSKLL = 168 +Alpha_INS_MSKQH = 169 +Alpha_INS_MSKQL = 170 +Alpha_INS_MSKWH = 171 +Alpha_INS_MSKWL = 172 +Alpha_INS_MULL = 173 +Alpha_INS_MULQ = 174 +Alpha_INS_MULSsSU = 175 +Alpha_INS_MULTsSU = 176 +Alpha_INS_ORNOT = 177 +Alpha_INS_RC = 178 +Alpha_INS_RET = 179 +Alpha_INS_RPCC = 180 +Alpha_INS_RS = 181 +Alpha_INS_S4ADDL = 182 +Alpha_INS_S4ADDQ = 183 +Alpha_INS_S4SUBL = 184 +Alpha_INS_S4SUBQ = 185 +Alpha_INS_S8ADDL = 186 +Alpha_INS_S8ADDQ = 187 +Alpha_INS_S8SUBL = 188 +Alpha_INS_S8SUBQ = 189 +Alpha_INS_SEXTB = 190 +Alpha_INS_SEXTW = 191 +Alpha_INS_SLL = 192 +Alpha_INS_SQRTSsSU = 193 +Alpha_INS_SQRTTsSU = 194 +Alpha_INS_SRA = 195 +Alpha_INS_SRL = 196 +Alpha_INS_STB = 197 +Alpha_INS_STL = 198 +Alpha_INS_STL_C = 199 +Alpha_INS_STQ = 200 +Alpha_INS_STQ_C = 201 +Alpha_INS_STQ_U = 202 +Alpha_INS_STS = 203 +Alpha_INS_STT = 204 +Alpha_INS_STW = 205 +Alpha_INS_SUBL = 206 +Alpha_INS_SUBQ = 207 +Alpha_INS_SUBSsSU = 208 +Alpha_INS_SUBTsSU = 209 +Alpha_INS_TRAPB = 210 +Alpha_INS_UMULH = 211 +Alpha_INS_WH64 = 212 +Alpha_INS_WH64EN = 213 +Alpha_INS_WMB = 214 +Alpha_INS_XOR = 215 +Alpha_INS_ZAPNOT = 216 +ALPHA_INS_ENDING = 217 + +# Group of Alpha instructions +Alpha_GRP_INVALID = 218 + +# Generic groups +Alpha_GRP_CALL = 219 +Alpha_GRP_JUMP = 220 +Alpha_GRP_BRANCH_RELATIVE = 221 +Alpha_GRP_ENDING = 222 diff --git a/bindings/python/setup_cython.py b/bindings/python/setup_cython.py index 6eb74e4324..9d4de46caa 100644 --- a/bindings/python/setup_cython.py +++ b/bindings/python/setup_cython.py @@ -69,7 +69,7 @@ compile_args = ['-O3', '-fomit-frame-pointer', '-I' + HEADERS_DIR] link_args = ['-L' + LIBS_DIR] -ext_module_names = ['arm', 'arm_const', 'aarch64', 'aarch64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'wasm', 'wasm_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'sh', 'sh_const', 'tricore', 'tricore_const' ] +ext_module_names = ['arm', 'arm_const', 'aarch64', 'aarch64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'wasm', 'wasm_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'sh', 'sh_const', 'tricore', 'tricore_const', 'alpha', 'alpha_const' ] ext_modules = [Extension("capstone.ccapstone", ["pyx/ccapstone.pyx"], diff --git a/bindings/python/test_all.py b/bindings/python/test_all.py index 820829b509..2e70de6fdc 100755 --- a/bindings/python/test_all.py +++ b/bindings/python/test_all.py @@ -2,7 +2,7 @@ import test_basic, test_arm, test_aarch64, test_detail, test_lite, test_m68k, test_mips, \ test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \ - test_m680x, test_mos65xx, test_xcore, test_riscv + test_m680x, test_mos65xx, test_xcore, test_riscv, test_alpha test_basic.test_class() test_arm.test_class() @@ -22,3 +22,4 @@ test_customized_mnem.test() test_xcore.test_class() test_riscv.test_class() +test_alpha.test_class() diff --git a/bindings/python/test_alpha.py b/bindings/python/test_alpha.py new file mode 100755 index 0000000000..a21344c950 --- /dev/null +++ b/bindings/python/test_alpha.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 + +# Capstone Python bindings, by Dmitry Sibirtsev + +from __future__ import print_function +from capstone import * +from capstone.alpha import * +from xprint import to_x, to_hex + +ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' + +all_tests = ( + (CS_ARCH_ALPHA, 0, ALPHA_CODE, "Alpha"), +) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = 0 + for i in insn.operands: + if i.type == ALPHA_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == ALPHA_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) + c += 1 + + +# ## Test class Cs +def test_class(): + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + for insn in md.disasm(code, 0x1000): + print_insn_detail(insn) + print() + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/bindings/python/test_basic.py b/bindings/python/test_basic.py index a41dbe43e2..d8d16df64c 100755 --- a/bindings/python/test_basic.py +++ b/bindings/python/test_basic.py @@ -40,6 +40,7 @@ EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00" RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00" RISCV_CODE64 = b"\x13\x04\xa8\x7a" +ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' all_tests = ( @@ -75,6 +76,7 @@ (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF", None), (CS_ARCH_RISCV, CS_MODE_RISCV32, RISCV_CODE32, "RISCV32", None), (CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "RISCV64", None), + (CS_ARCH_ALPHA, 0, ALPHA_CODE, "Alpha", None), ) # ## Test cs_disasm_quick() diff --git a/bindings/python/test_detail.py b/bindings/python/test_detail.py index 8ce3b9a871..b0ef2c6bc0 100755 --- a/bindings/python/test_detail.py +++ b/bindings/python/test_detail.py @@ -30,6 +30,7 @@ M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" MOS65XX_CODE = b"\x0A\x00\xFE\x34\x12\xD0\xFF\xEA\x19\x56\x34\x46\x80" EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00" +ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' all_tests = ( (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), @@ -57,6 +58,7 @@ (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), (CS_ARCH_MOS65XX, 0, MOS65XX_CODE, "MOS65XX", None), (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF", None), + (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha", None), ) diff --git a/bindings/python/test_iter.py b/bindings/python/test_iter.py index e9944a6ecb..634af167a9 100755 --- a/bindings/python/test_iter.py +++ b/bindings/python/test_iter.py @@ -28,6 +28,8 @@ XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" +ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' + all_tests = ( (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), @@ -55,6 +57,7 @@ (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None), (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None), (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), + (CS_ARCH_ALPHA, 0, ALPHA_CODE, "Alpha", None), ) # ## Test class Cs diff --git a/config.mk b/config.mk index a098de44f3..65ba9a0fcc 100644 --- a/config.mk +++ b/config.mk @@ -4,7 +4,7 @@ ################################################################################ # Specify which archs you want to compile in. By default, we build all archs. -CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore +CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha ################################################################################ diff --git a/cs.c b/cs.c index 94424cb1a4..7fbe48fe86 100644 --- a/cs.c +++ b/cs.c @@ -70,6 +70,7 @@ #include "arch/BPF/BPFModule.h" #include "arch/SH/SHModule.h" #include "arch/TriCore/TriCoreModule.h" +#include "arch/Alpha/AlphaModule.h" static const struct { // constructor initialization @@ -255,6 +256,15 @@ static const struct { #else { NULL, NULL, 0 }, #endif +#ifdef CAPSTONE_HAS_ALPHA + { + ALPHA_global_init, + ALPHA_option, + 0, + }, +#else + { NULL, NULL, 0 }, +#endif }; // bitmask of enabled architectures @@ -313,6 +323,9 @@ static const uint32_t all_arch = 0 #ifdef CAPSTONE_HAS_TRICORE | (1 << CS_ARCH_TRICORE) #endif +#ifdef CAPSTONE_HAS_ALPHA + | (1 << CS_ARCH_ALPHA) +#endif ; @@ -387,7 +400,8 @@ bool CAPSTONE_API cs_support(int query) (1 << CS_ARCH_M680X) | (1 << CS_ARCH_EVM) | (1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX) | (1 << CS_ARCH_WASM) | (1 << CS_ARCH_BPF) | - (1 << CS_ARCH_SH) | (1 << CS_ARCH_TRICORE)); + (1 << CS_ARCH_SH) | (1 << CS_ARCH_TRICORE) | + (1 << CS_ARCH_ALPHA)); if ((unsigned int)query < CS_ARCH_MAX) return all_arch & (1 << query); @@ -718,6 +732,9 @@ static uint8_t skipdata_size(cs_struct *handle) // TriCore instruction's length can be 2 or 4 bytes, // so we just skip 2 bytes return 2; + case CS_ARCH_ALPHA: + // Alpha alignment is 4. + return 4; } } @@ -1454,6 +1471,11 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type) if (insn->detail->tricore.operands[i].type == (tricore_op_type)op_type) count++; break; + case CS_ARCH_ALPHA: + for (i = 0; i < insn->detail->alpha.op_count; i++) + if (insn->detail->alpha.operands[i].type == (alpha_op_type)op_type) + count++; + break; } return count; @@ -1637,6 +1659,14 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type, return i; } break; + case CS_ARCH_ALPHA: + for (i = 0; i < insn->detail->alpha.op_count; i++) { + if (insn->detail->alpha.operands[i].type == (alpha_op_type)op_type) + count++; + if (count == post) + return i; + } + break; } return -1; diff --git a/cstool/cstool.c b/cstool/cstool.c index 2240ce1326..297dd95bc1 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -114,6 +114,7 @@ static struct { { "tc160", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 }, { "tc161", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 }, { "tc162", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 }, + { "alpha", CS_ARCH_ALPHA, 0 }, { NULL } }; @@ -208,6 +209,10 @@ static void usage(char *prog) printf(" aarch64be aarch64 + big endian\n"); } + if (cs_support(CS_ARCH_ALPHA)) { + printf(" alpha alpha\n"); + } + if (cs_support(CS_ARCH_MIPS)) { printf(" mips mips32 + little endian\n"); printf(" mipsbe mips32 + big endian\n"); @@ -392,6 +397,9 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins) case CS_ARCH_TRICORE: print_insn_detail_tricore(handle, ins); break; + case CS_ARCH_ALPHA: + print_insn_detail_alpha(handle, ins); + break; default: break; } @@ -528,6 +536,10 @@ int main(int argc, char **argv) printf("tricore=1 "); } + if (cs_support(CS_ARCH_ALPHA)) { + printf("alpha=1 "); + } + printf("\n"); return 0; case 'h': diff --git a/cstool/cstool.h b/cstool/cstool.h index 195d9e33d6..076c7b604e 100644 --- a/cstool/cstool.h +++ b/cstool/cstool.h @@ -19,5 +19,6 @@ void print_insn_detail_mos65xx(csh handle, cs_insn *ins); void print_insn_detail_bpf(csh handle, cs_insn *ins); void print_insn_detail_sh(csh handle, cs_insn *ins); void print_insn_detail_tricore(csh handle, cs_insn *ins); +void print_insn_detail_alpha(csh handle, cs_insn *ins); #endif //CAPSTONE_CSTOOL_CSTOOL_H_ diff --git a/cstool/cstool_alpha.c b/cstool/cstool_alpha.c new file mode 100644 index 0000000000..e34ad09b55 --- /dev/null +++ b/cstool/cstool_alpha.c @@ -0,0 +1,63 @@ +#include +#include + +#include +#include "cstool.h" + +void print_insn_detail_alpha(csh handle, cs_insn *ins) +{ + cs_alpha *alpha; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + alpha = &(ins->detail->alpha); + + if (alpha->op_count) + printf("\top_count: %u\n", alpha->op_count); + + for (i = 0; i < alpha->op_count; i++) { + cs_alpha_op *op = &(alpha->operands[i]); + switch ((int)op->type) { + default: + break; + case ALPHA_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case ALPHA_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, + op->imm); + break; + } + + // Print out all registers accessed by this instruction (either implicit or + // explicit) + if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + printf("\tRegisters read:"); + for (i = 0; i < regs_read_count; i++) { + printf(" %s", + cs_reg_name(handle, + regs_read[i])); + } + printf("\n"); + } + + if (regs_write_count) { + printf("\tRegisters modified:"); + for (i = 0; i < regs_write_count; i++) { + printf(" %s", + cs_reg_name(handle, + regs_write[i])); + } + printf("\n"); + } + } + } +} \ No newline at end of file diff --git a/include/capstone/alpha.h b/include/capstone/alpha.h new file mode 100644 index 0000000000..60932d0fd3 --- /dev/null +++ b/include/capstone/alpha.h @@ -0,0 +1,302 @@ +#ifndef CAPSTONE_ALPHA_H +#define CAPSTONE_ALPHA_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2014 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) +#include +#endif + +#include "cs_operand.h" +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable : 4201) +#endif + +#define MAX_ALPHA_OPS 3 + +//> Operand type for instruction's operands +typedef enum alpha_op_type { + ALPHA_OP_INVALID = CS_OP_INVALID, ///< CS_OP_INVALID (Uninitialized). + ALPHA_OP_REG = CS_OP_REG, ///< CS_OP_REG (Register operand). + ALPHA_OP_IMM = CS_OP_IMM, ///< CS_OP_IMM (Immediate operand). +} alpha_op_type; + +// Instruction operand +typedef struct cs_alpha_op { + alpha_op_type type; // operand type + union { + unsigned int reg; // register value for REG operand + int32_t imm; // immediate value for IMM operand + }; + enum cs_ac_type access; +} cs_alpha_op; + +// Instruction structure +typedef struct cs_alpha { + // Number of operands of this instruction, + // or 0 when instruction has no operand. + uint8_t op_count; + cs_alpha_op operands[MAX_ALPHA_OPS]; // operands for this instruction. +} cs_alpha; + + +//> Alpha registers +typedef enum alpha_reg { + // generated content begin + // clang-format off + + Alpha_REG_INVALID = 0, + Alpha_REG_F0 = 1, + Alpha_REG_F1 = 2, + Alpha_REG_F2 = 3, + Alpha_REG_F3 = 4, + Alpha_REG_F4 = 5, + Alpha_REG_F5 = 6, + Alpha_REG_F6 = 7, + Alpha_REG_F7 = 8, + Alpha_REG_F8 = 9, + Alpha_REG_F9 = 10, + Alpha_REG_F10 = 11, + Alpha_REG_F11 = 12, + Alpha_REG_F12 = 13, + Alpha_REG_F13 = 14, + Alpha_REG_F14 = 15, + Alpha_REG_F15 = 16, + Alpha_REG_F16 = 17, + Alpha_REG_F17 = 18, + Alpha_REG_F18 = 19, + Alpha_REG_F19 = 20, + Alpha_REG_F20 = 21, + Alpha_REG_F21 = 22, + Alpha_REG_F22 = 23, + Alpha_REG_F23 = 24, + Alpha_REG_F24 = 25, + Alpha_REG_F25 = 26, + Alpha_REG_F26 = 27, + Alpha_REG_F27 = 28, + Alpha_REG_F28 = 29, + Alpha_REG_F29 = 30, + Alpha_REG_F30 = 31, + Alpha_REG_F31 = 32, + Alpha_REG_R0 = 33, + Alpha_REG_R1 = 34, + Alpha_REG_R2 = 35, + Alpha_REG_R3 = 36, + Alpha_REG_R4 = 37, + Alpha_REG_R5 = 38, + Alpha_REG_R6 = 39, + Alpha_REG_R7 = 40, + Alpha_REG_R8 = 41, + Alpha_REG_R9 = 42, + Alpha_REG_R10 = 43, + Alpha_REG_R11 = 44, + Alpha_REG_R12 = 45, + Alpha_REG_R13 = 46, + Alpha_REG_R14 = 47, + Alpha_REG_R15 = 48, + Alpha_REG_R16 = 49, + Alpha_REG_R17 = 50, + Alpha_REG_R18 = 51, + Alpha_REG_R19 = 52, + Alpha_REG_R20 = 53, + Alpha_REG_R21 = 54, + Alpha_REG_R22 = 55, + Alpha_REG_R23 = 56, + Alpha_REG_R24 = 57, + Alpha_REG_R25 = 58, + Alpha_REG_R26 = 59, + Alpha_REG_R27 = 60, + Alpha_REG_R28 = 61, + Alpha_REG_R29 = 62, + Alpha_REG_R30 = 63, + Alpha_REG_R31 = 64, + Alpha_REG_ENDING, // 65 + + // clang-format on + // generated content end +} alpha_reg; + +//> Alpha instruction +typedef enum alpha_insn { + // generated content begin + // clang-format off + + Alpha_INS_INVALID, + Alpha_INS_ADDL, + Alpha_INS_ADDQ, + Alpha_INS_ADDSsSU, + Alpha_INS_ADDTsSU, + Alpha_INS_AND, + Alpha_INS_BEQ, + Alpha_INS_BGE, + Alpha_INS_BGT, + Alpha_INS_BIC, + Alpha_INS_BIS, + Alpha_INS_BLBC, + Alpha_INS_BLBS, + Alpha_INS_BLE, + Alpha_INS_BLT, + Alpha_INS_BNE, + Alpha_INS_BR, + Alpha_INS_BSR, + Alpha_INS_CMOVEQ, + Alpha_INS_CMOVGE, + Alpha_INS_CMOVGT, + Alpha_INS_CMOVLBC, + Alpha_INS_CMOVLBS, + Alpha_INS_CMOVLE, + Alpha_INS_CMOVLT, + Alpha_INS_CMOVNE, + Alpha_INS_CMPBGE, + Alpha_INS_CMPEQ, + Alpha_INS_CMPLE, + Alpha_INS_CMPLT, + Alpha_INS_CMPTEQsSU, + Alpha_INS_CMPTLEsSU, + Alpha_INS_CMPTLTsSU, + Alpha_INS_CMPTUNsSU, + Alpha_INS_CMPULE, + Alpha_INS_CMPULT, + Alpha_INS_COND_BRANCH, + Alpha_INS_CPYSE, + Alpha_INS_CPYSN, + Alpha_INS_CPYS, + Alpha_INS_CTLZ, + Alpha_INS_CTPOP, + Alpha_INS_CTTZ, + Alpha_INS_CVTQSsSUI, + Alpha_INS_CVTQTsSUI, + Alpha_INS_CVTSTsS, + Alpha_INS_CVTTQsSVC, + Alpha_INS_CVTTSsSUI, + Alpha_INS_DIVSsSU, + Alpha_INS_DIVTsSU, + Alpha_INS_ECB, + Alpha_INS_EQV, + Alpha_INS_EXCB, + Alpha_INS_EXTBL, + Alpha_INS_EXTLH, + Alpha_INS_EXTLL, + Alpha_INS_EXTQH, + Alpha_INS_EXTQL, + Alpha_INS_EXTWH, + Alpha_INS_EXTWL, + Alpha_INS_FBEQ, + Alpha_INS_FBGE, + Alpha_INS_FBGT, + Alpha_INS_FBLE, + Alpha_INS_FBLT, + Alpha_INS_FBNE, + Alpha_INS_FCMOVEQ, + Alpha_INS_FCMOVGE, + Alpha_INS_FCMOVGT, + Alpha_INS_FCMOVLE, + Alpha_INS_FCMOVLT, + Alpha_INS_FCMOVNE, + Alpha_INS_FETCH, + Alpha_INS_FETCH_M, + Alpha_INS_FTOIS, + Alpha_INS_FTOIT, + Alpha_INS_INSBL, + Alpha_INS_INSLH, + Alpha_INS_INSLL, + Alpha_INS_INSQH, + Alpha_INS_INSQL, + Alpha_INS_INSWH, + Alpha_INS_INSWL, + Alpha_INS_ITOFS, + Alpha_INS_ITOFT, + Alpha_INS_JMP, + Alpha_INS_JSR, + Alpha_INS_JSR_COROUTINE, + Alpha_INS_LDA, + Alpha_INS_LDAH, + Alpha_INS_LDBU, + Alpha_INS_LDL, + Alpha_INS_LDL_L, + Alpha_INS_LDQ, + Alpha_INS_LDQ_L, + Alpha_INS_LDQ_U, + Alpha_INS_LDS, + Alpha_INS_LDT, + Alpha_INS_LDWU, + Alpha_INS_MB, + Alpha_INS_MSKBL, + Alpha_INS_MSKLH, + Alpha_INS_MSKLL, + Alpha_INS_MSKQH, + Alpha_INS_MSKQL, + Alpha_INS_MSKWH, + Alpha_INS_MSKWL, + Alpha_INS_MULL, + Alpha_INS_MULQ, + Alpha_INS_MULSsSU, + Alpha_INS_MULTsSU, + Alpha_INS_ORNOT, + Alpha_INS_RC, + Alpha_INS_RET, + Alpha_INS_RPCC, + Alpha_INS_RS, + Alpha_INS_S4ADDL, + Alpha_INS_S4ADDQ, + Alpha_INS_S4SUBL, + Alpha_INS_S4SUBQ, + Alpha_INS_S8ADDL, + Alpha_INS_S8ADDQ, + Alpha_INS_S8SUBL, + Alpha_INS_S8SUBQ, + Alpha_INS_SEXTB, + Alpha_INS_SEXTW, + Alpha_INS_SLL, + Alpha_INS_SQRTSsSU, + Alpha_INS_SQRTTsSU, + Alpha_INS_SRA, + Alpha_INS_SRL, + Alpha_INS_STB, + Alpha_INS_STL, + Alpha_INS_STL_C, + Alpha_INS_STQ, + Alpha_INS_STQ_C, + Alpha_INS_STQ_U, + Alpha_INS_STS, + Alpha_INS_STT, + Alpha_INS_STW, + Alpha_INS_SUBL, + Alpha_INS_SUBQ, + Alpha_INS_SUBSsSU, + Alpha_INS_SUBTsSU, + Alpha_INS_TRAPB, + Alpha_INS_UMULH, + Alpha_INS_WH64, + Alpha_INS_WH64EN, + Alpha_INS_WMB, + Alpha_INS_XOR, + Alpha_INS_ZAPNOT, + + // clang-format on + // generated content end + ALPHA_INS_ENDING, // <-- mark the end of the list of instructions +} alpha_insn; + +//> Group of Alpha instructions +typedef enum alpha_insn_group { + Alpha_GRP_INVALID, ///< = CS_GRP_INVALID + //> Generic groups + Alpha_GRP_CALL, ///< = CS_GRP_CALL + Alpha_GRP_JUMP, ///< = CS_GRP_JUMP + Alpha_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE + Alpha_GRP_ENDING, ///< = mark the end of the list of groups +} alpha_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index 7ca26531a7..753f8b0a7b 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -144,6 +144,7 @@ typedef enum cs_arch { CS_ARCH_RISCV, ///< RISCV architecture CS_ARCH_SH, ///< SH architecture CS_ARCH_TRICORE, ///< TriCore architecture + CS_ARCH_ALPHA, ///< Alpha architecture CS_ARCH_MAX, CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support() } cs_arch; @@ -364,8 +365,9 @@ typedef struct cs_opt_skipdata { #include "bpf.h" #include "sh.h" #include "tricore.h" +#include "alpha.h" -#define MAX_IMPL_W_REGS 20 +#define MAX_IMPL_W_REGS 47 #define MAX_IMPL_R_REGS 20 #define MAX_NUM_GROUPS 8 @@ -408,6 +410,7 @@ typedef struct cs_detail { cs_riscv riscv; ///< RISCV architecture cs_sh sh; ///< SH architecture cs_tricore tricore; ///< TriCore architecture + cs_alpha alpha; ///< Alpha architecture }; } cs_detail; diff --git a/nmake.bat b/nmake.bat index ec2496edf5..0f03bce883 100644 --- a/nmake.bat +++ b/nmake.bat @@ -22,6 +22,7 @@ if "%1"=="MOS65XX" set %arch%=MOS65XX if "%1"=="WASM" set %arch%=WASM if "%1"=="BPF" set %arch%=BPF if "%1"=="RISCV" set %arch%=RISCV +if "%1"=="ALPHA" set %arch%=ALPHA if not "%arch%"=="" set flags=%flags% and " -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_%arch%_SUPPORT=ON" diff --git a/suite/MC/Alpha/insn-alpha.s.cs b/suite/MC/Alpha/insn-alpha.s.cs new file mode 100644 index 0000000000..05c00e9444 --- /dev/null +++ b/suite/MC/Alpha/insn-alpha.s.cs @@ -0,0 +1,199 @@ +# CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, None +0x03,0x00,0x22,0x40 = addl $1,$2,$3 +0x03,0xd0,0x3b,0x40 = addl $1,0xde,$3 +0x03,0x04,0x22,0x40 = addq $1,$2,$3 +0x03,0xd4,0x3b,0x40 = addq $1,0xde,$3 +0x03,0xb0,0x22,0x58 = adds/su $f1,$f10,$f11 +0x03,0xb4,0x22,0x58 = addt/su $f1,$f10,$f11 +0x03,0x00,0x22,0x44 = and $1,$2,$3 +0x03,0xd0,0x3b,0x44 = and $1,0xde,$3 +0xfc,0x3f,0x20,0xe4 = beq $1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xf8 = bge $1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xfc = bgt $1,0xfffffffffffffff4 +0x03,0x01,0x22,0x44 = bic $1,$2,$3 +0x03,0xd1,0x3b,0x44 = bic $1,0xde,$3 +0x03,0x04,0x22,0x44 = bis $1,$2,$3 +0x03,0xd4,0x3b,0x44 = bis $1,0xde,$3 +0xfc,0x3f,0x20,0xe0 = blbc $1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xf0 = blbs $1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xec = ble $1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xe8 = blt $1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xf4 = bne $1,0xfffffffffffffff4 +0xfc,0x3f,0xe0,0xc3 = br $31,0xfffffffffffffff4 +0xfc,0x3f,0x40,0xd3 = bsr $26,$0xfffffffffffffff4 ..ng +0x83,0x04,0x22,0x44 = cmoveq $1,$2,$3 +0xc3,0x08,0x22,0x44 = cmovge $1,$2,$3 +0xc3,0x0c,0x22,0x44 = cmovgt $1,$2,$3 +0xc3,0x02,0x22,0x44 = cmovlbc $1,$2,$3 +0x83,0x02,0x22,0x44 = cmovlbs $1,$2,$3 +0x83,0x0c,0x22,0x44 = cmovle $1,$2,$3 +0x83,0x08,0x22,0x44 = cmovlt $1,$2,$3 +0xc3,0x04,0x22,0x44 = cmovne $1,$2,$3 +0xe3,0x01,0x22,0x40 = cmpbge $1,$2,$3 +0xe3,0xd1,0x3b,0x40 = cmpbge $1,0xde,$3 +0xa3,0x05,0x22,0x40 = cmpeq $1,$2,$3 +0xa3,0xd5,0x3b,0x40 = cmpeq $1,0xde,$3 +0xa3,0x0d,0x22,0x40 = cmple $1,$2,$3 +0xa3,0xdd,0x3b,0x40 = cmple $1,0xde,$3 +0xa3,0x09,0x22,0x40 = cmplt $1,$2,$3 +0xa3,0xd9,0x3b,0x40 = cmplt $1,0xde,$3 +0xa3,0xb4,0x22,0x58 = cmpteq/su $f1,$f10,$f11 +0xe3,0xb4,0x22,0x58 = cmptle/su $f1,$f10,$f11 +0xc3,0xb4,0x22,0x58 = cmptlt/su $f1,$f10,$f11 +0x83,0xb4,0x22,0x58 = cmptun/su $f1,$f10,$f11 +0xa3,0x07,0x22,0x40 = cmpule $1,$2,$3 +0xa3,0xd7,0x3b,0x40 = cmpule $1,0xde,$3 +0xa3,0x03,0x22,0x40 = cmpult $1,$2,$3 +0xa3,0xd3,0x3b,0x40 = cmpult $1,0xde,$3 +0x43,0x04,0x22,0x5c = cpyse $f1,$f10,$f11 +0x23,0x04,0x22,0x5c = cpysn $f1,$f10,$f11 +0x03,0x04,0x22,0x5c = cpys $f1,$f10,$f11 +0x42,0x06,0xe1,0x73 = ctlz $1,$2 +0x02,0x06,0xe1,0x73 = ctpop $1,$2 +0x62,0x06,0xe1,0x73 = cttz $1,$2 +0x82,0xf7,0xe1,0x5b = cvtqs/sui $f1,$f10 +0xc2,0xf7,0xe1,0x5b = cvtqt/sui $f1,$f10 +0x82,0xd5,0xe1,0x5b = cvtst/s $f1,$f10 +0xe2,0xa5,0xe1,0x5b = cvttq/svc $f1,$f10 +0x82,0xf5,0xe1,0x5b = cvtts/sui $f1,$f10 +0x63,0xb0,0x22,0x58 = divs/su $f1,$f10,$f11 +0x63,0xb4,0x22,0x58 = divt/su $f1,$f10,$f11 +0x00,0xe8,0xe1,0x63 = ecb ($1) +0x03,0x09,0x22,0x44 = eqv $1,$2,$3 +0x03,0xd9,0x3b,0x44 = eqv $1,0xde,$3 +0x00,0x04,0x00,0x60 = excb +0xc3,0x00,0x22,0x48 = extbl $1,$2,$3 +0xc3,0xd0,0x3b,0x48 = extbl $1,0xde,$3 +0x43,0x0d,0x22,0x48 = extlh $1,$2,$3 +0x43,0xdd,0x3b,0x48 = extlh $1,0xde,$3 +0xc3,0x04,0x22,0x48 = extll $1,$2,$3 +0xc3,0xd4,0x3b,0x48 = extll $1,0xde,$3 +0x43,0x0f,0x22,0x48 = extqh $1,$2,$3 +0x43,0xdf,0x3b,0x48 = extqh $1,0xde,$3 +0xc3,0x06,0x22,0x48 = extql $1,$2,$3 +0xc3,0xd6,0x3b,0x48 = extql $1,0xde,$3 +0x43,0x0b,0x22,0x48 = extwh $1,$2,$3 +0x43,0xdb,0x3b,0x48 = extwh $1,0xde,$3 +0xc3,0x02,0x22,0x48 = extwl $1,$2,$3 +0xc3,0xd2,0x3b,0x48 = extwl $1,0xde,$3 +0xfc,0x3f,0x20,0xc4 = fbeq $f1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xd8 = fbge $f1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xdc = fbgt $f1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xcc = fble $f1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xc8 = fblt $f1,0xfffffffffffffff4 +0xfc,0x3f,0x20,0xd4 = fbne $f1,0xfffffffffffffff4 +0x43,0x05,0x22,0x5c = fcmoveq ,$f10,$f11 +0xa3,0x05,0x22,0x5c = fcmovge ,$f10,$f11 +0xe3,0x05,0x22,0x5c = fcmovgt ,$f10,$f11 +0xc3,0x05,0x22,0x5c = fcmovle ,$f10,$f11 +0x83,0x05,0x22,0x5c = fcmovlt ,$f10,$f11 +0x63,0x05,0x22,0x5c = fcmovne ,$f10,$f11 +0x00,0x80,0xe1,0x63 = fetch ($1) +0x00,0xa0,0xe1,0x63 = fetch_m ($1) +0x01,0x0f,0x3f,0x70 = ftois $f1,$1 +0x01,0x0e,0x3f,0x70 = ftoit $f1,$1 +0x63,0x01,0x22,0x48 = insbl $1,$2,$3 +0x63,0xd1,0x3b,0x48 = insbl $1,0xde,$3 +0xe3,0x0c,0x22,0x48 = inslh $1,$2,$3 +0xe3,0xdc,0x3b,0x48 = inslh $1,0xde,$3 +0x63,0x05,0x22,0x48 = insll $1,$2,$3 +0x63,0xd5,0x3b,0x48 = insll $1,0xde,$3 +0xe3,0x0e,0x22,0x48 = insqh $1,$2,$3 +0xe3,0xde,0x3b,0x48 = insqh $1,0xde,$3 +0x63,0x07,0x22,0x48 = insql $1,$2,$3 +0x63,0xd7,0x3b,0x48 = insql $1,0xde,$3 +0xe3,0x0a,0x22,0x48 = inswh $1,$2,$3 +0xe3,0xda,0x3b,0x48 = inswh $1,0xde,$3 +0x63,0x03,0x22,0x48 = inswl $1,$2,$3 +0x63,0xd3,0x3b,0x48 = inswl $1,0xde,$3 +0x81,0x00,0x3f,0x50 = itofs $1,$f1 +0x81,0x04,0x3f,0x50 = itoft $1,$f1 +0x00,0x00,0xfa,0x6b = jmp $31,$12,0 +0x00,0x40,0x5b,0x6b = jsr $26,($27),0 +0xff,0xcf,0x22,0x68 = jsr_coroutine $1,($2),0xfff +0x10,0x00,0x22,0x20 = lda $1,0x10($2) +0x10,0x00,0x22,0x24 = ldah $1,0x10($2) +0x10,0x00,0x22,0x28 = ldbu $1,0x10($2) +0x10,0x00,0x22,0xa0 = ldl $1,0x10($2) +0x10,0x00,0x22,0xa8 = ldl_l $1,0x10($2) +0x10,0x00,0x22,0xa4 = ldq $1,0x10($2) +0x10,0x00,0x22,0xac = ldq_l $1,0x10($2) +0x10,0x00,0x22,0x2c = ldq_u $1,0x10($2) +0x10,0x00,0x22,0x88 = lds $f1,0x10($2) +0x10,0x00,0x22,0x8c = ldt $f1,0x10($2) +0x10,0x00,0x22,0x30 = ldwu $1,0x10($2) +0x00,0x40,0x00,0x60 = mb +0x43,0x00,0x22,0x48 = mskbl $1,$2,$3 +0x43,0xd0,0x3b,0x48 = mskbl $1,0xde,$3 +0x43,0x0c,0x22,0x48 = msklh $1,$2,$3 +0x43,0xdc,0x3b,0x48 = msklh $1,0xde,$3 +0x43,0x04,0x22,0x48 = mskll $1,$2,$3 +0x43,0xd4,0x3b,0x48 = mskll $1,0xde,$3 +0x43,0x0e,0x22,0x48 = mskqh $1,$2,$3 +0x43,0xde,0x3b,0x48 = mskqh $1,0xde,$3 +0x43,0x06,0x22,0x48 = mskql $1,$2,$3 +0x43,0xd6,0x3b,0x48 = mskql $1,0xde,$3 +0x43,0x0a,0x22,0x48 = mskwh $1,$2,$3 +0x43,0xda,0x3b,0x48 = mskwh $1,0xde,$3 +0x43,0x02,0x22,0x48 = mskwl $1,$2,$3 +0x43,0xd2,0x3b,0x48 = mskwl $1,0xde,$3 +0x03,0x00,0x22,0x4c = mull $1,$2,$3 +0x03,0xd0,0x3b,0x4c = mull $1,0xde,$3 +0x03,0x04,0x22,0x4c = mulq $1,$2,$3 +0x03,0xd4,0x3b,0x4c = mulq $1,0xde,$3 +0x43,0xb0,0x22,0x58 = muls/su $f1,$f10,$f11 +0x43,0xb4,0x22,0x58 = mult/su $f1,$f10,$f11 +0x03,0x05,0x22,0x44 = ornot $1,$2,$3 +0x03,0xd5,0x3b,0x44 = ornot $1,0xde,$3 +0x00,0xe0,0x20,0x60 = rc $1 +0x01,0x80,0xfa,0x6b = ret $31,($26),1 +0x00,0xc0,0x1f,0x60 = rpcc $0 +0x00,0xf0,0x20,0x60 = rs $1 +0x43,0x00,0x22,0x40 = s4addl $1,$2,$3 +0x43,0xd0,0x3b,0x40 = s4addl $1,0xde,$3 +0x63,0x01,0x22,0x40 = s4subl $1,$2,$3 +0x63,0xd1,0x3b,0x40 = s4subl $1,0xde,$3 +0x63,0x05,0x22,0x40 = s4subq $1,$2,$3 +0x63,0xd5,0x3b,0x40 = s4subq $1,0xde,$3 +0x43,0x02,0x22,0x40 = s8addl $1,$2,$3 +0x43,0xd2,0x3b,0x40 = s8addl $1,0xde,$3 +0x43,0x06,0x22,0x40 = s8addq $1,$2,$3 +0x43,0xd6,0x3b,0x40 = s8addq $1,0xde,$3 +0x63,0x03,0x22,0x40 = s8subl $1,$2,$3 +0x63,0xd3,0x3b,0x40 = s8subl $1,0xde,$3 +0x63,0x07,0x22,0x40 = s8subq $1,$2,$3 +0x63,0xd7,0x3b,0x40 = s8subq $1,0xde,$3 +0x02,0x00,0xe1,0x73 = sextb $1,$2 +0x22,0x00,0xe1,0x73 = sextw $1,$2 +0x23,0x07,0x22,0x48 = sll $1,$2,$3 +0x23,0xd7,0x3b,0x48 = sll $1,0xde,$3 +0x62,0xb1,0xe1,0x53 = sqrts/su $f1,$f10 +0x62,0xb5,0xe1,0x53 = sqrtt/su $f1,$f10 +0x83,0x07,0x22,0x48 = sra $1,$2,$3 +0x83,0xd7,0x3b,0x48 = sra $1,0xde,$3 +0x83,0x06,0x22,0x48 = srl $1,$2,$3 +0x83,0xd6,0x3b,0x48 = srl $1,0xde,$3 +0x10,0x00,0x22,0x38 = stb $1, 0x10($2) +0x10,0x00,0x22,0xb0 = stl $1,0x10($2) +0x10,0x00,0x22,0xb8 = stl_c $1,0x10($2) +0x10,0x00,0x22,0xb4 = stq $1,0x10($2) +0x10,0x00,0x22,0xbc = stq_c $1,0x10($2) +0x10,0x00,0x22,0x3c = stq_u $1, 0x10($2) +0x10,0x00,0x22,0x98 = sts $f1,0x10($2) +0x10,0x00,0x22,0x9c = stt $f1,0x10($2) +0x10,0x00,0x22,0x34 = stw $1,0x10($2) +0x23,0x01,0x22,0x40 = subl $1,$2,$3 +0x23,0xd1,0x3b,0x40 = subl $1,0xde,$3 +0x23,0x05,0x22,0x40 = subq $1,$2,$3 +0x23,0xd5,0x3b,0x40 = subq $1,0xde,$3 +0x23,0xb0,0x22,0x58 = subs/su $f1,$f10,$f11 +0x23,0xb4,0x22,0x58 = subt/su $f1,$f10,$f11 +0x00,0x00,0x00,0x60 = trapb +0x03,0x06,0x22,0x4c = umulh $1,$2,$3 +0x03,0xd6,0x3b,0x4c = umulh $1,0xde,$3 +0x00,0xf8,0xe1,0x63 = wh64 ($1) +0x00,0xfc,0xe1,0x63 = wh64en ($1) +0x00,0x44,0x00,0x60 = wmb +0x03,0x08,0x22,0x44 = xor $1,$2,$3 +0x03,0xd8,0x3b,0x44 = xor $1,0xde,$3 +0x23,0xd6,0x3b,0x48 = zapnot $1,0xde,$3 \ No newline at end of file diff --git a/suite/auto-sync/Updater/ASUpdater.py b/suite/auto-sync/Updater/ASUpdater.py index ffd68b39c9..9440583f1c 100755 --- a/suite/auto-sync/Updater/ASUpdater.py +++ b/suite/auto-sync/Updater/ASUpdater.py @@ -151,7 +151,7 @@ def parse_args() -> argparse.Namespace: description="Capstones architecture module updater.", ) parser.add_argument( - "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC", "AArch64"], required=True + "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC", "AArch64", "Alpha"], required=True ) parser.add_argument("-d", dest="no_clean", help="Don't clean build dir before updating.", action="store_true") parser.add_argument( diff --git a/suite/auto-sync/Updater/CppTranslator/CppTranslator.py b/suite/auto-sync/Updater/CppTranslator/CppTranslator.py index 87dde80ad5..3a2465a99a 100755 --- a/suite/auto-sync/Updater/CppTranslator/CppTranslator.py +++ b/suite/auto-sync/Updater/CppTranslator/CppTranslator.py @@ -452,7 +452,7 @@ def parse_args() -> argparse.Namespace: description="Capstones C++ to C translator for LLVM source files", ) parser.add_argument( - "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC", "AArch64"], required=True + "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC", "AArch64", "Alpha"], required=True ) parser.add_argument( "-v", diff --git a/suite/auto-sync/Updater/CppTranslator/Differ.py b/suite/auto-sync/Updater/CppTranslator/Differ.py index ce06649737..b3dd44f778 100755 --- a/suite/auto-sync/Updater/CppTranslator/Differ.py +++ b/suite/auto-sync/Updater/CppTranslator/Differ.py @@ -11,7 +11,7 @@ import logging as log import sys -from Configurator import Configurator +from CppTranslator.Configurator import Configurator from Helper import ( convert_loglevel, find_id_by_type, @@ -603,7 +603,7 @@ def parse_args() -> argparse.Namespace: action="store_true", ) parser.add_argument( - "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC, AArch64"], required=True + "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC, AArch64", "Alpha"], required=True ) parser.add_argument( "-v", diff --git a/suite/auto-sync/Updater/CppTranslator/arch_config.json b/suite/auto-sync/Updater/CppTranslator/arch_config.json index 6ca855bdfc..714c54451a 100644 --- a/suite/auto-sync/Updater/CppTranslator/arch_config.json +++ b/suite/auto-sync/Updater/CppTranslator/arch_config.json @@ -119,5 +119,14 @@ "isSVEAddSubImm" ], "manually_edited_files": [] + }, + "Alpha": { + "files_to_translate": [], + "files_for_template_search": [ + "{CPP_INC_OUT_DIR}/AlphaGenDisassemblerTables.inc", + "{CPP_INC_OUT_DIR}/AlphaGenAsmWriter.inc" + ], + "templates_with_arg_deduction": [], + "manually_edited_files": [] } } diff --git a/suite/auto-sync/Updater/Update-Arch.sh b/suite/auto-sync/Updater/Update-Arch.sh index d96b6938e7..372521f7ea 100755 --- a/suite/auto-sync/Updater/Update-Arch.sh +++ b/suite/auto-sync/Updater/Update-Arch.sh @@ -53,7 +53,7 @@ setup_build_dir() { # Main # -supported="ARM, PPC, AArch64" +supported="ARM, PPC, AArch64, Alpha" if [ $# -ne 3 ] || [ "$1" = "-h" ] || [ "$1" = "--help" ]; then echo "$0 " diff --git a/suite/capstone_get_setup.c b/suite/capstone_get_setup.c index 5f749591c6..2d3f6a6bba 100644 --- a/suite/capstone_get_setup.c +++ b/suite/capstone_get_setup.c @@ -73,6 +73,9 @@ int main() if (cs_support(CS_ARCH_TRICORE)) { printf("tricore=1 "); } + if (cs_support(CS_ARCH_ALPHA)) { + printf("alpha=1 "); + } printf("\n"); return 0; diff --git a/suite/cstest/include/factory.h b/suite/cstest/include/factory.h index ffc1a938bc..09906b8c81 100644 --- a/suite/cstest/include/factory.h +++ b/suite/cstest/include/factory.h @@ -24,5 +24,6 @@ char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_tricore(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_alpha(csh *handle, cs_mode mode, cs_insn *ins); #endif /* FACTORY_H */ diff --git a/suite/cstest/src/alpha_detail.c b/suite/cstest/src/alpha_detail.c new file mode 100644 index 0000000000..4f41783370 --- /dev/null +++ b/suite/cstest/src/alpha_detail.c @@ -0,0 +1,69 @@ +/* Capstone testing regression */ +/* By Dmitry Sibirtsev , 2023 */ + +#include "factory.h" + +char *get_detail_alpha(csh *p_handle, cs_mode mode, cs_insn *ins) +{ + cs_alpha *alpha; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + + char *result; + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + csh handle = *p_handle; + + alpha = &(ins->detail->alpha); + + if (alpha->op_count) + add_str(&result, "\top_count: %u\n", alpha->op_count); + + for (i = 0; i < alpha->op_count; i++) { + cs_alpha_op *op = &(alpha->operands[i]); + switch ((int)op->type) { + default: + break; + case ALPHA_OP_REG: + add_str(&result, "\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case ALPHA_OP_IMM: + add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n", + i, op->imm); + break; + } + + // Print out all registers accessed by this instruction (either implicit or + // explicit) + if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + add_str(&result, "\tRegisters read:"); + for (i = 0; i < regs_read_count; i++) { + add_str(&result, " %s", + cs_reg_name(handle, + regs_read[i])); + } + add_str(&result, "\n"); + } + + if (regs_write_count) { + add_str(&result, "\tRegisters modified:"); + for (i = 0; i < regs_write_count; i++) { + add_str(&result, " %s", + cs_reg_name(handle, + regs_write[i])); + } + add_str(&result, "\n"); + } + } + } + + return result; +} diff --git a/suite/cstest/src/capstone_test.c b/suite/cstest/src/capstone_test.c index e282756e83..3290415ce0 100644 --- a/suite/cstest/src/capstone_test.c +++ b/suite/cstest/src/capstone_test.c @@ -190,6 +190,9 @@ int set_function(int arch) case CS_ARCH_TRICORE: function = get_detail_tricore; break; + case CS_ARCH_ALPHA: + function = get_detail_alpha; + break; default: return -1; } diff --git a/suite/cstest/src/main.c b/suite/cstest/src/main.c index 88a0425091..a4a681f2fd 100644 --- a/suite/cstest/src/main.c +++ b/suite/cstest/src/main.c @@ -21,6 +21,7 @@ static single_dict arches[] = { {"CS_ARCH_BPF", CS_ARCH_BPF}, {"CS_ARCH_RISCV", CS_ARCH_RISCV}, {"CS_ARCH_TRICORE", CS_ARCH_TRICORE}, + {"CS_ARCH_ALPHA", CS_ARCH_ALPHA}, }; static single_dict modes[] = { diff --git a/suite/test_c.sh b/suite/test_c.sh index cc7359a347..eacbf3b954 100755 --- a/suite/test_c.sh +++ b/suite/test_c.sh @@ -23,4 +23,5 @@ ../tests/test_wasm > /tmp/$1 ../tests/test_winkernel > /tmp/$1 ../tests/test_x86 > /tmp/$1 -../tests/test_xcore > /tmp/$1 \ No newline at end of file +../tests/test_xcore > /tmp/$1 +../tests/test_alpha > /tmp/$1 \ No newline at end of file diff --git a/suite/test_corpus.py b/suite/test_corpus.py index aa75276b34..c1767abf04 100755 --- a/suite/test_corpus.py +++ b/suite/test_corpus.py @@ -33,6 +33,7 @@ def test_file(fname): "CS_ARCH_XCORE": CS_ARCH_XCORE, "CS_ARCH_RISCV": CS_ARCH_RISCV, "CS_ARCH_TRICORE": CS_ARCH_TRICORE, + "CS_ARCH_ALPHA": CS_ARCH_ALPHA, } modes = { @@ -115,6 +116,7 @@ def test_file(fname): ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_161"): 52, ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_162"): 53, ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN+CS_MODE_QPX"): 54, + ("CS_ARCH_ALPHA", "CS_MODE_LITTLE_ENDIAN"): 55, } #if not option in ('', 'None'): diff --git a/suite/test_corpus3.py b/suite/test_corpus3.py index b58c4a8d2c..5df87408e2 100755 --- a/suite/test_corpus3.py +++ b/suite/test_corpus3.py @@ -43,6 +43,7 @@ def test_file(fname): "CS_ARCH_XCORE": CS_ARCH_XCORE, "CS_ARCH_RISCV": CS_ARCH_RISCV, "CS_ARCH_TRICORE": CS_ARCH_TRICORE, + "CS_ARCH_ALPHA": CS_ARCH_ALPHA, } modes = { @@ -125,6 +126,7 @@ def test_file(fname): ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_161"): 52, ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_162"): 53, ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN+CS_MODE_QPX"): 54, + ("CS_ARCH_ALPHA", "CS_MODE_LITTLE_ENDIAN"): 55, } # if not option in ('', 'None'): diff --git a/suite/test_python.sh b/suite/test_python.sh index 90145629a9..e95aa31a84 100755 --- a/suite/test_python.sh +++ b/suite/test_python.sh @@ -11,3 +11,4 @@ ../bindings/python/test_ppc.py >> /tmp/$1 ../bindings/python/test_sparc.py >> /tmp/$1 ../bindings/python/test_x86.py >> /tmp/$1 +../bindings/python/test_alpha.py >> /tmp/$1 \ No newline at end of file diff --git a/tests/Makefile b/tests/Makefile index 5a56b269f5..f01ff6fc9d 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -137,6 +137,11 @@ ifneq (,$(findstring sh,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_SH SOURCES += test_sh.c endif +ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_ALPHA +SOURCES += test_alpha.c +endif + OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o)) BINARY = $(addprefix $(TESTDIR)/,$(SOURCES:.c=$(BIN_EXT))) diff --git a/tests/test_all.sh b/tests/test_all.sh index 42131a6e9d..905d84e5ab 100644 --- a/tests/test_all.sh +++ b/tests/test_all.sh @@ -18,4 +18,5 @@ ./test_wasm ./test_winkernel ./test_x86 -./test_xcore \ No newline at end of file +./test_xcore +./test_alpha \ No newline at end of file diff --git a/tests/test_alpha.c b/tests/test_alpha.c new file mode 100644 index 0000000000..20ea5a8e96 --- /dev/null +++ b/tests/test_alpha.c @@ -0,0 +1,135 @@ +/* Capstone Disassembler Engine */ +/* By Dmitry Sibirtsev , 2013-2019 */ + +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + char *comment; +}; + +static csh handle; + +static void print_string_hex(char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_alpha *alpha; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + alpha = &(ins->detail->alpha); + if (alpha->op_count) + printf("\top_count: %u\n", alpha->op_count); + + for (i = 0; i < alpha->op_count; i++) { + cs_alpha_op *op = &(alpha->operands[i]); + switch ((int)op->type) { + default: + break; + case ALPHA_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case ALPHA_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, + op->imm); + break; + } + } + + printf("\n"); +} + +static void test() +{ +#define ALPHA_CODE \ + "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" + + struct platform platforms[] = { + { + CS_ARCH_ALPHA, + 0, + (unsigned char *)ALPHA_CODE, + sizeof(ALPHA_CODE) - 1, + "Alpha", + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { + cs_err err = + cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", + err); + continue; + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, + address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code: ", platforms[i].code, + platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", + insn[j].address, insn[j].mnemonic, + insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%" PRIx64 ":\n", + insn[j - 1].address + insn[j - 1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, + platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/tests/test_basic.c b/tests/test_basic.c index 7d71e48d2c..6cd4dd9b35 100644 --- a/tests/test_basic.c +++ b/tests/test_basic.c @@ -90,6 +90,9 @@ static void test() #ifdef CAPSTONE_HAS_RISCV #define RISCV_CODE32 "\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00" #define RISCV_CODE64 "\x13\x04\xa8\x7a" // aaa80413 +#endif +#ifdef CAPSTONE_HAS_ALPHA +#define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" #endif struct platform { @@ -363,6 +366,15 @@ static void test() sizeof(RISCV_CODE64) - 1, "RISCV64" }, +#endif +#ifdef CAPSTONE_HAS_ALPHA + { + CS_ARCH_ALPHA, + CS_MODE_LITTLE_ENDIAN, + (unsigned char*)ALPHA_CODE, + sizeof(ALPHA_CODE) - 1, + "Alpha" + }, #endif }; diff --git a/tests/test_detail.c b/tests/test_detail.c index 18d9626676..9e7eeeb329 100644 --- a/tests/test_detail.c +++ b/tests/test_detail.c @@ -77,6 +77,9 @@ static void test() #endif #ifdef CAPSTONE_HAS_BPF #define EBPF_CODE "\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00" +#endif +#ifdef CAPSTONE_HAS_ALPHA +#define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" #endif struct platform platforms[] = { @@ -280,6 +283,15 @@ static void test() sizeof(EBPF_CODE) - 1, "eBPF" }, +#endif +#ifdef CAPSTONE_HAS_ALPHA + { + CS_ARCH_ALPHA, + CS_MODE_LITTLE_ENDIAN, + (unsigned char*)ALPHA_CODE, + sizeof(ALPHA_CODE) - 1, + "Alpha" + }, #endif }; diff --git a/tests/test_iter.c b/tests/test_iter.c index be877a31e5..edc536e91f 100644 --- a/tests/test_iter.c +++ b/tests/test_iter.c @@ -79,6 +79,10 @@ static void test() #define TRICORE_CODE "\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19\xff\xc0\x70\x19\xff\x20\x10" #endif +#ifdef CAPSTONE_HAS_ALPHA +#define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" +#endif + struct platform platforms[] = { #ifdef CAPSTONE_HAS_X86 { @@ -261,6 +265,15 @@ struct platform platforms[] = { sizeof(TRICORE_CODE) - 1, "TriCore" }, +#endif +#ifdef CAPSTONE_HAS_ALPHA + { + CS_ARCH_ALPHA, + 0, + (unsigned char*)ALPHA_CODE, + sizeof(ALPHA_CODE) - 1, + "Alpha" + }, #endif };