From d0ac226851d4c2cab1b336916020d77fa927d7f6 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 16 Jul 2023 13:05:24 +0200 Subject: [PATCH 01/10] Fix TriCore ld/st instructions using +r registers when we got 2 operands we were expecting them to be one of the CACHE insns. However, 2 operands are also used by ld/st insns with bitreverse +r addressing mode. In that case we would print the registers in the wrong order. --- arch/TriCore/TriCoreDisassembler.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/TriCore/TriCoreDisassembler.c b/arch/TriCore/TriCoreDisassembler.c index 408f516c59..828d36a7a8 100644 --- a/arch/TriCore/TriCoreDisassembler.c +++ b/arch/TriCore/TriCoreDisassembler.c @@ -441,15 +441,21 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn, } if (desc->NumOperands == 2) { - status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], - Decoder); - if (status != MCDisassembler_Success) - return status; - if (desc->OpInfo[1].OperandType == MCOI_OPERAND_REGISTER) { - return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], + // we have [reg+r] instruction + status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], + Decoder); + if (status != MCDisassembler_Success) + return status; + return DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder); } else { + // we have one of the CACHE instructions without destination reg + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], + Decoder); + if (status != MCDisassembler_Success) + return status; + MCOperand_CreateImm0(Inst, off10); } return MCDisassembler_Success; From 11254b69d18c98b01a6890e6c8ac35b7531bbed2 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 16 Jul 2023 13:09:52 +0200 Subject: [PATCH 02/10] Fix TriCore abs insns using wrong source operand abs instruction use 's2' as the first source operand and not 's1'. --- arch/TriCore/TriCoreDisassembler.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/TriCore/TriCoreDisassembler.c b/arch/TriCore/TriCoreDisassembler.c index 828d36a7a8..483654e6dd 100644 --- a/arch/TriCore/TriCoreDisassembler.c +++ b/arch/TriCore/TriCoreDisassembler.c @@ -705,10 +705,24 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn, } if (desc->NumOperands > 1) { - status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], - Decoder); - if (status != MCDisassembler_Success) - return status; + if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) { + switch (MCInst_getOpcode(Inst)) { + case TRICORE_ABSS_rr: + case TRICORE_ABSS_H_rr: + case TRICORE_ABS_H_rr: + case TRICORE_ABS_B_rr: + case TRICORE_ABS_rr: { + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], + Decoder); + break; + default: + status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], + Decoder); + } + if (status != MCDisassembler_Success) + return status; + } + } } if (desc->NumOperands > 2) { From 54f2f142457047ec37389fba2346603d57889446 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 16 Jul 2023 13:14:20 +0200 Subject: [PATCH 03/10] Fix TriCore extr/_u insns using wrong source operand extr and extr.u in the RRRR format use 's3' as the second source operand instead of 's2'. --- arch/TriCore/TriCoreDisassembler.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/TriCore/TriCoreDisassembler.c b/arch/TriCore/TriCoreDisassembler.c index 483654e6dd..71d398077f 100644 --- a/arch/TriCore/TriCoreDisassembler.c +++ b/arch/TriCore/TriCoreDisassembler.c @@ -1279,7 +1279,13 @@ static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, return status; if (desc->NumOperands == 3) { - return DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder); + switch (MCInst_getOpcode(Inst)) { + case TRICORE_EXTR_rrrr: + case TRICORE_EXTR_U_rrrr: + return DecodeRegisterClass(Inst, s3, &desc->OpInfo[2], Decoder); + default: + return DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder); + } } // Decode s2. From b6d69048bb58b560679d186c727d09dc120e0469 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 16 Jul 2023 15:08:46 +0200 Subject: [PATCH 04/10] Fix TriCore mtcr insns using wrong source register --- arch/TriCore/TriCoreDisassembler.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/TriCore/TriCoreDisassembler.c b/arch/TriCore/TriCoreDisassembler.c index 71d398077f..0bd08e226b 100644 --- a/arch/TriCore/TriCoreDisassembler.c +++ b/arch/TriCore/TriCoreDisassembler.c @@ -655,8 +655,13 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn, MCOperand_CreateImm0(Inst, const16); } else { MCOperand_CreateImm0(Inst, const16); - status = - DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder); + if (MCInst_getOpcode(Inst) == TRICORE_MTCR_rlc) { + status = + DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder); + } else { + status = + DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder); + } if (status != MCDisassembler_Success) return status; } From 13f9567130373f7d898e0849c109c29238429e0f Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 16 Jul 2023 15:26:50 +0200 Subject: [PATCH 05/10] Fix TriCore store insns using +r or +c operands For these insns destination and source are swapped compared to their ld counterparts. --- arch/TriCore/TriCoreDisassembler.c | 74 ++++++++++++++++++++++++------ 1 file changed, 60 insertions(+), 14 deletions(-) diff --git a/arch/TriCore/TriCoreDisassembler.c b/arch/TriCore/TriCoreDisassembler.c index 0bd08e226b..40aad5e684 100644 --- a/arch/TriCore/TriCoreDisassembler.c +++ b/arch/TriCore/TriCoreDisassembler.c @@ -425,6 +425,7 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn, unsigned off10_0 = fieldFromInstruction_4(Insn, 16, 6); unsigned off10_1 = fieldFromInstruction_4(Insn, 28, 4); unsigned off10 = (off10_0 << 0) | (off10_1 << 6); + bool is_store = false; unsigned s2 = fieldFromInstruction_4(Insn, 12, 4); unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4); @@ -440,15 +441,48 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn, return DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder); } + switch (MCInst_getOpcode(Inst)) { + case TRICORE_ST_A_bo_r: + case TRICORE_ST_A_bo_c: + case TRICORE_ST_B_bo_r: + case TRICORE_ST_B_bo_c: + case TRICORE_ST_D_bo_r: + case TRICORE_ST_D_bo_c: + case TRICORE_ST_DA_bo_r: + case TRICORE_ST_DA_bo_c: + case TRICORE_ST_H_bo_r: + case TRICORE_ST_H_bo_c: + case TRICORE_ST_Q_bo_r: + case TRICORE_ST_Q_bo_c: + case TRICORE_ST_W_bo_r: + case TRICORE_ST_W_bo_c: + case TRICORE_SWAP_W_bo_r: + case TRICORE_SWAP_W_bo_c: + case TRICORE_SWAPMSK_W_bo_c: + case TRICORE_SWAPMSK_W_bo_r: { + is_store = true; + break; + } + } + if (desc->NumOperands == 2) { if (desc->OpInfo[1].OperandType == MCOI_OPERAND_REGISTER) { // we have [reg+r] instruction - status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], - Decoder); - if (status != MCDisassembler_Success) - return status; - return DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], - Decoder); + if (is_store) { + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], + Decoder); + if (status != MCDisassembler_Success) + return status; + return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], + Decoder); + } else { + status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], + Decoder); + if (status != MCDisassembler_Success) + return status; + return DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], + Decoder); + } } else { // we have one of the CACHE instructions without destination reg status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], @@ -462,16 +496,28 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn, } if (desc->NumOperands > 2) { - status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], - Decoder); - if (status != MCDisassembler_Success) - return status; + if (is_store) { + // we have [reg+c] instruction + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], + Decoder); + if (status != MCDisassembler_Success) + return status; - status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], - Decoder); - if (status != MCDisassembler_Success) - return status; + status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], + Decoder); + if (status != MCDisassembler_Success) + return status; + } else { + status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], + Decoder); + if (status != MCDisassembler_Success) + return status; + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], + Decoder); + if (status != MCDisassembler_Success) + return status; + } MCOperand_CreateImm0(Inst, off10); } From 8228bd3b2c24829af2760343360a9a7e3298d2f0 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 16 Jul 2023 15:28:32 +0200 Subject: [PATCH 06/10] TriCore: Add const8_fixup() we need to multiply const8 by 4 for the SC variants of ld/sw. --- arch/TriCore/TriCoreInstPrinter.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/TriCore/TriCoreInstPrinter.c b/arch/TriCore/TriCoreInstPrinter.c index a15b962df6..679ca709c1 100644 --- a/arch/TriCore/TriCoreInstPrinter.c +++ b/arch/TriCore/TriCoreInstPrinter.c @@ -225,6 +225,19 @@ static void off4_fixup(MCInst *MI, uint64_t *off4) } } +static void const8_fixup(MCInst *MI, uint64_t *const8) +{ + switch (MCInst_getOpcode(MI)) { + case TRICORE_LD_A_sc: + case TRICORE_ST_A_sc: + case TRICORE_ST_W_sc: + case TRICORE_LD_W_sc: { + *const8 *= 4; + break; + } + } +} + static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) { MCOperand *MO = MCInst_getOperand(MI, OpNum); @@ -236,6 +249,9 @@ static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) if (n == 4) { off4_fixup(MI, &imm); } + if (n == 8) { + const8_fixup(MI, &imm); + } printInt64Bang(O, imm); fill_imm(MI, imm); From 23455cee65e0d6fe34f7b0ba29f5789b942da405 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 23 Jul 2023 16:58:57 +0200 Subject: [PATCH 07/10] suite/TriCore: Add test for rr insns --- suite/MC/TriCore/rr_insn.s.cs | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 suite/MC/TriCore/rr_insn.s.cs diff --git a/suite/MC/TriCore/rr_insn.s.cs b/suite/MC/TriCore/rr_insn.s.cs new file mode 100644 index 0000000000..734b42ba07 --- /dev/null +++ b/suite/MC/TriCore/rr_insn.s.cs @@ -0,0 +1,6 @@ +# CS_ARCH_TRICORE, CS_MODE_TRICORE_131, None +0x0b, 0x20, 0xc0, 0x01 = abs d0, d2 +0x0b, 0x60, 0xc0, 0x05 = abs.b d0, d6 +0x0b, 0x40, 0xc0, 0x27 = abs.h d2, d4 +0x0b, 0x10, 0xd0, 0x01 = abss d0, d1 +0x0b, 0x10, 0xd0, 0x07 = abss.h d0, d1 From 098a8cac81a9f0e44e0c592eb9fe75388a0f2edb Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 23 Jul 2023 16:59:22 +0200 Subject: [PATCH 08/10] suite/TriCore: Add tests for ld/st with +r and +c operands --- suite/MC/TriCore/ldst_br_circ.s.cs | 47 ++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 suite/MC/TriCore/ldst_br_circ.s.cs diff --git a/suite/MC/TriCore/ldst_br_circ.s.cs b/suite/MC/TriCore/ldst_br_circ.s.cs new file mode 100644 index 0000000000..0bc85fb8fa --- /dev/null +++ b/suite/MC/TriCore/ldst_br_circ.s.cs @@ -0,0 +1,47 @@ +# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None +0xa9, 0x00, 0x80, 0x03 = cachea.i [p0+r] +0xa9, 0x00, 0x8a, 0x07 = cachea.i [p0+c]#0xa +0xa9, 0x00, 0x00, 0x03 = cachea.w [p0+r] +0xa9, 0x00, 0x0a, 0x07 = cachea.w [p0+c]#0xa +0xa9, 0x00, 0x40, 0x03 = cachea.wi [p0+r] +0xa9, 0x00, 0x4a, 0x07 = cachea.wi [p0+c]#0xa +0x69, 0x02, 0xc0, 0x00 = cmpswap.w [p0+r], e2 +0x69, 0x02, 0xca, 0x04 = cmpswap.w [p0+c]#0xa, e2 +0x29, 0x02, 0x80, 0x01 = ld.a a2, [p0+r] +0x29, 0x02, 0x8a, 0x05 = ld.a a2, [p0+c]#0xa +0x29, 0x02, 0x00, 0x00 = ld.b d2, [p0+r] +0x29, 0x02, 0x0a, 0x04 = ld.b d2, [p0+c]#0xa +0x29, 0x02, 0x40, 0x00 = ld.bu d2, [p0+r] +0x29, 0x02, 0x4a, 0x04 = ld.bu d2, [p0+c]#0xa +0x29, 0x02, 0x40, 0x01 = ld.d e2, [p0+r] +0x29, 0x02, 0x4a, 0x05 = ld.d e2, [p0+c]#0xa +0x29, 0x02, 0xc0, 0x01 = ld.da p2, [p0+r] +0x29, 0x02, 0xca, 0x05 = ld.da p2, [p0+c]#0xa +0x29, 0x02, 0x80, 0x00 = ld.h d2, [p0+r] +0x29, 0x02, 0x8a, 0x04 = ld.h d2, [p0+c]#0xa +0x29, 0x02, 0xc0, 0x00 = ld.hu d2, [p0+r] +0x29, 0x02, 0xca, 0x04 = ld.hu d2, [p0+c]#0xa +0x29, 0x02, 0x00, 0x02 = ld.q d2, [p0+r] +0x29, 0x02, 0x0a, 0x06 = ld.q d2, [p0+c]#0xa +0x29, 0x02, 0x00, 0x01 = ld.w d2, [p0+r] +0x29, 0x02, 0x0a, 0x05 = ld.w d2, [p0+c]#0xa +0x69, 0x02, 0x40, 0x00 = ldmst [p0+r], e2 +0x69, 0x02, 0x4a, 0x04 = ldmst [p0+c]#0xa, e2 +0xa9, 0x02, 0x80, 0x01 = st.a [p0+r], a2 +0xa9, 0x02, 0x8a, 0x05 = st.a [p0+c]#0xa, a2 +0xa9, 0x02, 0x00, 0x00 = st.b [p0+r], d2 +0xa9, 0x02, 0x0a, 0x04 = st.b [p0+c]#0xa, d2 +0xa9, 0x02, 0x40, 0x01 = st.d [p0+r], e2 +0xa9, 0x02, 0x4a, 0x05 = st.d [p0+c]#0xa, e2 +0xa9, 0x02, 0xc0, 0x01 = st.da [p0+r], p2 +0xa9, 0x02, 0xca, 0x05 = st.da [p0+c]#0xa, p2 +0xa9, 0x02, 0x80, 0x00 = st.h [p0+r], d2 +0xa9, 0x02, 0x8a, 0x04 = st.h [p0+c]#0xa, d2 +0xa9, 0x02, 0x00, 0x02 = st.q [p0+r], d2 +0xa9, 0x02, 0x0a, 0x06 = st.q [p0+c]#0xa, d2 +0xa9, 0x02, 0x00, 0x01 = st.w [p0+r], d2 +0xa9, 0x02, 0x0a, 0x05 = st.w [p0+c]#0xa, d2 +0x69, 0x02, 0x00, 0x00 = swap.w [p0+r], d2 +0x69, 0x02, 0x0a, 0x04 = swap.w [p0+c]#0xa, d2 +0x69, 0x02, 0x80, 0x00 = swapmsk.w [p0+r], e2 +0x69, 0x02, 0x8a, 0x04 = swapmsk.w [p0+c]#0xa, e2 From 5944315c07810d7cf2eada8eab4a92510f7de3c2 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 23 Jul 2023 16:59:46 +0200 Subject: [PATCH 09/10] suite/TriCore: Add tests for extr and extr.u insns --- suite/MC/TriCore/extr_u.s.cs | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 suite/MC/TriCore/extr_u.s.cs diff --git a/suite/MC/TriCore/extr_u.s.cs b/suite/MC/TriCore/extr_u.s.cs new file mode 100644 index 0000000000..907a5e4ed1 --- /dev/null +++ b/suite/MC/TriCore/extr_u.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_TRICORE, CS_MODE_TRICORE_131, None +0x17, 0x01, 0x40, 0x02 = extr d0, d1, e2 +0x17, 0x01, 0x60, 0x02 = extr.u d0, d1, e2 From 62b99adf918746aa40f32d148a4fdd348b9cd380 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 23 Jul 2023 17:00:09 +0200 Subject: [PATCH 10/10] suite/TriCore: Add tests for mtcr mfcr insns --- suite/MC/TriCore/csfr.s.cs | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 suite/MC/TriCore/csfr.s.cs diff --git a/suite/MC/TriCore/csfr.s.cs b/suite/MC/TriCore/csfr.s.cs new file mode 100644 index 0000000000..fc0db30274 --- /dev/null +++ b/suite/MC/TriCore/csfr.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_TRICORE, CS_MODE_TRICORE_131, None +0xcd, 0x41, 0xe0, 0x0f = mtcr #-0x1fc, d1 +0x4d, 0x40, 0xe0, 0x2f = mfcr d2, #0xfe04