From 5f0c45afd329fb4b49a1c35e7e5e2e427577333e Mon Sep 17 00:00:00 2001 From: Peace-Maker Date: Tue, 25 Jul 2023 11:18:35 +0200 Subject: [PATCH 1/2] Generate Python ARM constants from arm.h It uses the new CS_OP_* constants too, so add it to the template preamble. --- bindings/const_generator.py | 2 +- bindings/python/Makefile | 2 +- bindings/python/capstone/arm64_const.py | 2 +- bindings/python/capstone/arm_const.py | 1896 +++++++++++------- bindings/python/capstone/bpf_const.py | 2 +- bindings/python/capstone/evm_const.py | 2 +- bindings/python/capstone/m680x_const.py | 2 +- bindings/python/capstone/m68k_const.py | 2 +- bindings/python/capstone/mips_const.py | 2 +- bindings/python/capstone/mos65xx_const.py | 2 +- bindings/python/capstone/ppc_const.py | 2 +- bindings/python/capstone/riscv_const.py | 2 +- bindings/python/capstone/sh_const.py | 2 +- bindings/python/capstone/sparc_const.py | 2 +- bindings/python/capstone/sysz_const.py | 2 +- bindings/python/capstone/tms320c64x_const.py | 2 +- bindings/python/capstone/tricore_const.py | 2 +- bindings/python/capstone/wasm_const.py | 2 +- bindings/python/capstone/x86_const.py | 2 +- bindings/python/capstone/xcore_const.py | 2 +- bindings/python/test_arm.py | 2 - 21 files changed, 1174 insertions(+), 762 deletions(-) diff --git a/bindings/const_generator.py b/bindings/const_generator.py index fbe1947409..51b778463d 100644 --- a/bindings/const_generator.py +++ b/bindings/const_generator.py @@ -31,7 +31,7 @@ 'comment_close': '', }, 'python': { - 'header': "from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM\n" + 'header': "from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM\n" "# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.py]\n", 'footer': "", 'line_format': '%s = %s\n', diff --git a/bindings/python/Makefile b/bindings/python/Makefile index b901b061d1..e861ad799e 100644 --- a/bindings/python/Makefile +++ b/bindings/python/Makefile @@ -4,7 +4,7 @@ PYTHON3 ?= python3 .PHONY: gen_const install install3 install_cython sdist sdist3 bdist bdist3 clean check gen_const: - cd .. && $(PYTHON2) const_generator.py python + cd .. && $(PYTHON3) const_generator.py python install: rm -rf src/ diff --git a/bindings/python/capstone/arm64_const.py b/bindings/python/capstone/arm64_const.py index f2210ffdd0..8d93eba53b 100644 --- a/bindings/python/capstone/arm64_const.py +++ b/bindings/python/capstone/arm64_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.py] ARM64_SFT_INVALID = 0 diff --git a/bindings/python/capstone/arm_const.py b/bindings/python/capstone/arm_const.py index 22c4f6df93..9aa67bb774 100644 --- a/bindings/python/capstone/arm_const.py +++ b/bindings/python/capstone/arm_const.py @@ -1,6 +1,42 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py] +ARMCC_EQ = 0 +ARMCC_NE = 1 +ARMCC_HS = 2 +ARMCC_LO = 3 +ARMCC_MI = 4 +ARMCC_PL = 5 +ARMCC_VS = 6 +ARMCC_VC = 7 +ARMCC_HI = 8 +ARMCC_LS = 9 +ARMCC_GE = 10 +ARMCC_LT = 11 +ARMCC_GT = 12 +ARMCC_LE = 13 +ARMCC_AL = 14 +ARMCC_UNDEF = 15 + +ARMVCC_None = 0 +ARMVCC_Then = 1 +ARMVCC_Else = 2 +ARM_T = 0b1000 +ARM_TT = 0b0100 +ARM_TE = 0b1100 +ARM_TTT = 0b0010 +ARM_TTE = 0b0110 +ARM_TEE = 0b1110 +ARM_TET = 0b1010 +ARM_TTTT = 0b0001 +ARM_TTTE = 0b0011 +ARM_TTEE = 0b0111 +ARM_TTET = 0b0101 +ARM_TEEE = 0b1111 +ARM_TEET = 0b1101 +ARM_TETT = 0b1001 +ARM_TETE = 0b1011 + ARM_SFT_INVALID = 0 ARM_SFT_ASR = 1 ARM_SFT_LSL = 2 @@ -12,131 +48,132 @@ ARM_SFT_LSR_REG = 8 ARM_SFT_ROR_REG = 9 ARM_SFT_RRX_REG = 10 - -ARM_CC_INVALID = 0 -ARM_CC_EQ = 1 -ARM_CC_NE = 2 -ARM_CC_HS = 3 -ARM_CC_LO = 4 -ARM_CC_MI = 5 -ARM_CC_PL = 6 -ARM_CC_VS = 7 -ARM_CC_VC = 8 -ARM_CC_HI = 9 -ARM_CC_LS = 10 -ARM_CC_GE = 11 -ARM_CC_LT = 12 -ARM_CC_GT = 13 -ARM_CC_LE = 14 -ARM_CC_AL = 15 - -ARM_SYSREG_INVALID = 0 -ARM_SYSREG_SPSR_C = 1 -ARM_SYSREG_SPSR_X = 2 -ARM_SYSREG_SPSR_S = 4 -ARM_SYSREG_SPSR_F = 8 -ARM_SYSREG_CPSR_C = 16 -ARM_SYSREG_CPSR_X = 32 -ARM_SYSREG_CPSR_S = 64 -ARM_SYSREG_CPSR_F = 128 -ARM_SYSREG_APSR = 256 -ARM_SYSREG_APSR_G = 257 -ARM_SYSREG_APSR_NZCVQ = 258 -ARM_SYSREG_APSR_NZCVQG = 259 -ARM_SYSREG_IAPSR = 260 -ARM_SYSREG_IAPSR_G = 261 -ARM_SYSREG_IAPSR_NZCVQG = 262 -ARM_SYSREG_IAPSR_NZCVQ = 263 -ARM_SYSREG_EAPSR = 264 -ARM_SYSREG_EAPSR_G = 265 -ARM_SYSREG_EAPSR_NZCVQG = 266 -ARM_SYSREG_EAPSR_NZCVQ = 267 -ARM_SYSREG_XPSR = 268 -ARM_SYSREG_XPSR_G = 269 -ARM_SYSREG_XPSR_NZCVQG = 270 -ARM_SYSREG_XPSR_NZCVQ = 271 -ARM_SYSREG_IPSR = 272 -ARM_SYSREG_EPSR = 273 -ARM_SYSREG_IEPSR = 274 -ARM_SYSREG_MSP = 275 -ARM_SYSREG_PSP = 276 -ARM_SYSREG_PRIMASK = 277 -ARM_SYSREG_BASEPRI = 278 -ARM_SYSREG_BASEPRI_MAX = 279 -ARM_SYSREG_FAULTMASK = 280 -ARM_SYSREG_CONTROL = 281 -ARM_SYSREG_MSPLIM = 282 -ARM_SYSREG_PSPLIM = 283 -ARM_SYSREG_MSP_NS = 284 -ARM_SYSREG_PSP_NS = 285 -ARM_SYSREG_MSPLIM_NS = 286 -ARM_SYSREG_PSPLIM_NS = 287 -ARM_SYSREG_PRIMASK_NS = 288 -ARM_SYSREG_BASEPRI_NS = 289 -ARM_SYSREG_FAULTMASK_NS = 290 -ARM_SYSREG_CONTROL_NS = 291 -ARM_SYSREG_SP_NS = 292 -ARM_SYSREG_R8_USR = 293 -ARM_SYSREG_R9_USR = 294 -ARM_SYSREG_R10_USR = 295 -ARM_SYSREG_R11_USR = 296 -ARM_SYSREG_R12_USR = 297 -ARM_SYSREG_SP_USR = 298 -ARM_SYSREG_LR_USR = 299 -ARM_SYSREG_R8_FIQ = 300 -ARM_SYSREG_R9_FIQ = 301 -ARM_SYSREG_R10_FIQ = 302 -ARM_SYSREG_R11_FIQ = 303 -ARM_SYSREG_R12_FIQ = 304 -ARM_SYSREG_SP_FIQ = 305 -ARM_SYSREG_LR_FIQ = 306 -ARM_SYSREG_LR_IRQ = 307 -ARM_SYSREG_SP_IRQ = 308 -ARM_SYSREG_LR_SVC = 309 -ARM_SYSREG_SP_SVC = 310 -ARM_SYSREG_LR_ABT = 311 -ARM_SYSREG_SP_ABT = 312 -ARM_SYSREG_LR_UND = 313 -ARM_SYSREG_SP_UND = 314 -ARM_SYSREG_LR_MON = 315 -ARM_SYSREG_SP_MON = 316 -ARM_SYSREG_ELR_HYP = 317 -ARM_SYSREG_SP_HYP = 318 -ARM_SYSREG_SPSR_FIQ = 319 -ARM_SYSREG_SPSR_IRQ = 320 -ARM_SYSREG_SPSR_SVC = 321 -ARM_SYSREG_SPSR_ABT = 322 -ARM_SYSREG_SPSR_UND = 323 -ARM_SYSREG_SPSR_MON = 324 -ARM_SYSREG_SPSR_HYP = 325 - -ARM_MB_INVALID = 0 -ARM_MB_RESERVED_0 = 1 -ARM_MB_OSHLD = 2 -ARM_MB_OSHST = 3 -ARM_MB_OSH = 4 -ARM_MB_RESERVED_4 = 5 -ARM_MB_NSHLD = 6 -ARM_MB_NSHST = 7 -ARM_MB_NSH = 8 -ARM_MB_RESERVED_8 = 9 -ARM_MB_ISHLD = 10 -ARM_MB_ISHST = 11 -ARM_MB_ISH = 12 -ARM_MB_RESERVED_12 = 13 -ARM_MB_LD = 14 -ARM_MB_ST = 15 -ARM_MB_SY = 16 - -ARM_OP_INVALID = 0 -ARM_OP_REG = 1 -ARM_OP_IMM = 2 -ARM_OP_MEM = 3 -ARM_OP_FP = 4 -ARM_OP_CIMM = 64 -ARM_OP_PIMM = 65 -ARM_OP_SETEND = 66 -ARM_OP_SYSREG = 67 +ARM_MB_RESERVED_0 = 11 +ARM_MB_OSHLD = 12 +ARM_MB_OSHST = 13 +ARM_MB_OSH = 14 +ARM_MB_RESERVED_4 = 15 +ARM_MB_NSHLD = 16 +ARM_MB_NSHST = 17 +ARM_MB_NSH = 18 +ARM_MB_RESERVED_8 = 19 +ARM_MB_ISHLD = 20 +ARM_MB_ISHST = 21 +ARM_MB_ISH = 22 +ARM_MB_RESERVED_12 = 23 +ARM_MB_LD = 24 +ARM_MB_ST = 25 +ARM_MB_SY = 26 +ARM_FIELD_SPSR_C = 1 +ARM_FIELD_SPSR_X = 2 +ARM_FIELD_SPSR_S = 4 +ARM_FIELD_SPSR_F = 8 +ARM_FIELD_CPSR_C = 16 +ARM_FIELD_CPSR_X = 32 +ARM_FIELD_CPSR_S = 64 +ARM_FIELD_CPSR_F = 128 +ARM_BANKEDREG_ELR_HYP = 0x1e +ARM_BANKEDREG_LR_ABT = 0x14 +ARM_BANKEDREG_LR_FIQ = 0xe +ARM_BANKEDREG_LR_IRQ = 0x10 +ARM_BANKEDREG_LR_MON = 0x1c +ARM_BANKEDREG_LR_SVC = 0x12 +ARM_BANKEDREG_LR_UND = 0x16 +ARM_BANKEDREG_LR_USR = 0x6 +ARM_BANKEDREG_R10_FIQ = 0xa +ARM_BANKEDREG_R10_USR = 0x2 +ARM_BANKEDREG_R11_FIQ = 0xb +ARM_BANKEDREG_R11_USR = 0x3 +ARM_BANKEDREG_R12_FIQ = 0xc +ARM_BANKEDREG_R12_USR = 0x4 +ARM_BANKEDREG_R8_FIQ = 0x8 +ARM_BANKEDREG_R8_USR = 0x0 +ARM_BANKEDREG_R9_FIQ = 0x9 +ARM_BANKEDREG_R9_USR = 0x1 +ARM_BANKEDREG_SPSR_ABT = 0x34 +ARM_BANKEDREG_SPSR_FIQ = 0x2e +ARM_BANKEDREG_SPSR_HYP = 0x3e +ARM_BANKEDREG_SPSR_IRQ = 0x30 +ARM_BANKEDREG_SPSR_MON = 0x3c +ARM_BANKEDREG_SPSR_SVC = 0x32 +ARM_BANKEDREG_SPSR_UND = 0x36 +ARM_BANKEDREG_SP_ABT = 0x15 +ARM_BANKEDREG_SP_FIQ = 0xd +ARM_BANKEDREG_SP_HYP = 0x1f +ARM_BANKEDREG_SP_IRQ = 0x11 +ARM_BANKEDREG_SP_MON = 0x1d +ARM_BANKEDREG_SP_SVC = 0x13 +ARM_BANKEDREG_SP_UND = 0x17 +ARM_BANKEDREG_SP_USR = 0x5 +ARM_MCLASSSYSREG_APSR = 0x800 +ARM_MCLASSSYSREG_APSR_G = 0x400 +ARM_MCLASSSYSREG_APSR_NZCVQ = 0x800 +ARM_MCLASSSYSREG_APSR_NZCVQG = 0xc00 +ARM_MCLASSSYSREG_BASEPRI = 0x811 +ARM_MCLASSSYSREG_BASEPRI_MAX = 0x812 +ARM_MCLASSSYSREG_BASEPRI_NS = 0x891 +ARM_MCLASSSYSREG_CONTROL = 0x814 +ARM_MCLASSSYSREG_CONTROL_NS = 0x894 +ARM_MCLASSSYSREG_EAPSR = 0x802 +ARM_MCLASSSYSREG_EAPSR_G = 0x402 +ARM_MCLASSSYSREG_EAPSR_NZCVQ = 0x802 +ARM_MCLASSSYSREG_EAPSR_NZCVQG = 0xc02 +ARM_MCLASSSYSREG_EPSR = 0x806 +ARM_MCLASSSYSREG_FAULTMASK = 0x813 +ARM_MCLASSSYSREG_FAULTMASK_NS = 0x893 +ARM_MCLASSSYSREG_IAPSR = 0x801 +ARM_MCLASSSYSREG_IAPSR_G = 0x401 +ARM_MCLASSSYSREG_IAPSR_NZCVQ = 0x801 +ARM_MCLASSSYSREG_IAPSR_NZCVQG = 0xc01 +ARM_MCLASSSYSREG_IEPSR = 0x807 +ARM_MCLASSSYSREG_IPSR = 0x805 +ARM_MCLASSSYSREG_MSP = 0x808 +ARM_MCLASSSYSREG_MSPLIM = 0x80a +ARM_MCLASSSYSREG_MSPLIM_NS = 0x88a +ARM_MCLASSSYSREG_MSP_NS = 0x888 +ARM_MCLASSSYSREG_PAC_KEY_P_0 = 0x820 +ARM_MCLASSSYSREG_PAC_KEY_P_0_NS = 0x8a0 +ARM_MCLASSSYSREG_PAC_KEY_P_1 = 0x821 +ARM_MCLASSSYSREG_PAC_KEY_P_1_NS = 0x8a1 +ARM_MCLASSSYSREG_PAC_KEY_P_2 = 0x822 +ARM_MCLASSSYSREG_PAC_KEY_P_2_NS = 0x8a2 +ARM_MCLASSSYSREG_PAC_KEY_P_3 = 0x823 +ARM_MCLASSSYSREG_PAC_KEY_P_3_NS = 0x8a3 +ARM_MCLASSSYSREG_PAC_KEY_U_0 = 0x824 +ARM_MCLASSSYSREG_PAC_KEY_U_0_NS = 0x8a4 +ARM_MCLASSSYSREG_PAC_KEY_U_1 = 0x825 +ARM_MCLASSSYSREG_PAC_KEY_U_1_NS = 0x8a5 +ARM_MCLASSSYSREG_PAC_KEY_U_2 = 0x826 +ARM_MCLASSSYSREG_PAC_KEY_U_2_NS = 0x8a6 +ARM_MCLASSSYSREG_PAC_KEY_U_3 = 0x827 +ARM_MCLASSSYSREG_PAC_KEY_U_3_NS = 0x8a7 +ARM_MCLASSSYSREG_PRIMASK = 0x810 +ARM_MCLASSSYSREG_PRIMASK_NS = 0x890 +ARM_MCLASSSYSREG_PSP = 0x809 +ARM_MCLASSSYSREG_PSPLIM = 0x80b +ARM_MCLASSSYSREG_PSPLIM_NS = 0x88b +ARM_MCLASSSYSREG_PSP_NS = 0x889 +ARM_MCLASSSYSREG_SP_NS = 0x898 +ARM_MCLASSSYSREG_XPSR = 0x803 +ARM_MCLASSSYSREG_XPSR_G = 0x403 +ARM_MCLASSSYSREG_XPSR_NZCVQ = 0x803 +ARM_MCLASSSYSREG_XPSR_NZCVQG = 0xc03 +ARM_OP_INVALID = CS_OP_INVALID +ARM_OP_REG = CS_OP_REG +ARM_OP_IMM = CS_OP_IMM +ARM_OP_FP = CS_OP_FP +ARM_OP_PRED = CS_OP_PRED +ARM_OP_CIMM = CS_OP_SPECIAL+0 +ARM_OP_PIMM = CS_OP_SPECIAL+1 +ARM_OP_SETEND = CS_OP_SPECIAL+2 +ARM_OP_SYSREG = CS_OP_SPECIAL+3 +ARM_OP_BANKEDREG = CS_OP_SPECIAL+4 +ARM_OP_SPSR = CS_OP_SPECIAL+5 +ARM_OP_CPSR = CS_OP_SPECIAL+6 +ARM_OP_SYSM = CS_OP_SPECIAL+7 +ARM_OP_VPRED_R = CS_OP_SPECIAL+8 +ARM_OP_VPRED_N = CS_OP_SPECIAL+9 +ARM_OP_MEM = CS_OP_MEM ARM_SETEND_INVALID = 0 ARM_SETEND_BE = 1 @@ -200,114 +237,299 @@ ARM_REG_APSR = 1 ARM_REG_APSR_NZCV = 2 ARM_REG_CPSR = 3 -ARM_REG_FPEXC = 4 -ARM_REG_FPINST = 5 -ARM_REG_FPSCR = 6 -ARM_REG_FPSCR_NZCV = 7 -ARM_REG_FPSID = 8 -ARM_REG_ITSTATE = 9 -ARM_REG_LR = 10 -ARM_REG_PC = 11 -ARM_REG_SP = 12 -ARM_REG_SPSR = 13 -ARM_REG_D0 = 14 -ARM_REG_D1 = 15 -ARM_REG_D2 = 16 -ARM_REG_D3 = 17 -ARM_REG_D4 = 18 -ARM_REG_D5 = 19 -ARM_REG_D6 = 20 -ARM_REG_D7 = 21 -ARM_REG_D8 = 22 -ARM_REG_D9 = 23 -ARM_REG_D10 = 24 -ARM_REG_D11 = 25 -ARM_REG_D12 = 26 -ARM_REG_D13 = 27 -ARM_REG_D14 = 28 -ARM_REG_D15 = 29 -ARM_REG_D16 = 30 -ARM_REG_D17 = 31 -ARM_REG_D18 = 32 -ARM_REG_D19 = 33 -ARM_REG_D20 = 34 -ARM_REG_D21 = 35 -ARM_REG_D22 = 36 -ARM_REG_D23 = 37 -ARM_REG_D24 = 38 -ARM_REG_D25 = 39 -ARM_REG_D26 = 40 -ARM_REG_D27 = 41 -ARM_REG_D28 = 42 -ARM_REG_D29 = 43 -ARM_REG_D30 = 44 -ARM_REG_D31 = 45 -ARM_REG_FPINST2 = 46 -ARM_REG_MVFR0 = 47 -ARM_REG_MVFR1 = 48 -ARM_REG_MVFR2 = 49 -ARM_REG_Q0 = 50 -ARM_REG_Q1 = 51 -ARM_REG_Q2 = 52 -ARM_REG_Q3 = 53 -ARM_REG_Q4 = 54 -ARM_REG_Q5 = 55 -ARM_REG_Q6 = 56 -ARM_REG_Q7 = 57 -ARM_REG_Q8 = 58 -ARM_REG_Q9 = 59 -ARM_REG_Q10 = 60 -ARM_REG_Q11 = 61 -ARM_REG_Q12 = 62 -ARM_REG_Q13 = 63 -ARM_REG_Q14 = 64 -ARM_REG_Q15 = 65 -ARM_REG_R0 = 66 -ARM_REG_R1 = 67 -ARM_REG_R2 = 68 -ARM_REG_R3 = 69 -ARM_REG_R4 = 70 -ARM_REG_R5 = 71 -ARM_REG_R6 = 72 -ARM_REG_R7 = 73 -ARM_REG_R8 = 74 -ARM_REG_R9 = 75 -ARM_REG_R10 = 76 -ARM_REG_R11 = 77 -ARM_REG_R12 = 78 -ARM_REG_S0 = 79 -ARM_REG_S1 = 80 -ARM_REG_S2 = 81 -ARM_REG_S3 = 82 -ARM_REG_S4 = 83 -ARM_REG_S5 = 84 -ARM_REG_S6 = 85 -ARM_REG_S7 = 86 -ARM_REG_S8 = 87 -ARM_REG_S9 = 88 -ARM_REG_S10 = 89 -ARM_REG_S11 = 90 -ARM_REG_S12 = 91 -ARM_REG_S13 = 92 -ARM_REG_S14 = 93 -ARM_REG_S15 = 94 -ARM_REG_S16 = 95 -ARM_REG_S17 = 96 -ARM_REG_S18 = 97 -ARM_REG_S19 = 98 -ARM_REG_S20 = 99 -ARM_REG_S21 = 100 -ARM_REG_S22 = 101 -ARM_REG_S23 = 102 -ARM_REG_S24 = 103 -ARM_REG_S25 = 104 -ARM_REG_S26 = 105 -ARM_REG_S27 = 106 -ARM_REG_S28 = 107 -ARM_REG_S29 = 108 -ARM_REG_S30 = 109 -ARM_REG_S31 = 110 -ARM_REG_ENDING = 111 +ARM_REG_FPCXTNS = 4 +ARM_REG_FPCXTS = 5 +ARM_REG_FPEXC = 6 +ARM_REG_FPINST = 7 +ARM_REG_FPSCR = 8 +ARM_REG_FPSCR_NZCV = 9 +ARM_REG_FPSCR_NZCVQC = 10 +ARM_REG_FPSID = 11 +ARM_REG_ITSTATE = 12 +ARM_REG_LR = 13 +ARM_REG_PC = 14 +ARM_REG_RA_AUTH_CODE = 15 +ARM_REG_SP = 16 +ARM_REG_SPSR = 17 +ARM_REG_VPR = 18 +ARM_REG_ZR = 19 +ARM_REG_D0 = 20 +ARM_REG_D1 = 21 +ARM_REG_D2 = 22 +ARM_REG_D3 = 23 +ARM_REG_D4 = 24 +ARM_REG_D5 = 25 +ARM_REG_D6 = 26 +ARM_REG_D7 = 27 +ARM_REG_D8 = 28 +ARM_REG_D9 = 29 +ARM_REG_D10 = 30 +ARM_REG_D11 = 31 +ARM_REG_D12 = 32 +ARM_REG_D13 = 33 +ARM_REG_D14 = 34 +ARM_REG_D15 = 35 +ARM_REG_D16 = 36 +ARM_REG_D17 = 37 +ARM_REG_D18 = 38 +ARM_REG_D19 = 39 +ARM_REG_D20 = 40 +ARM_REG_D21 = 41 +ARM_REG_D22 = 42 +ARM_REG_D23 = 43 +ARM_REG_D24 = 44 +ARM_REG_D25 = 45 +ARM_REG_D26 = 46 +ARM_REG_D27 = 47 +ARM_REG_D28 = 48 +ARM_REG_D29 = 49 +ARM_REG_D30 = 50 +ARM_REG_D31 = 51 +ARM_REG_FPINST2 = 52 +ARM_REG_MVFR0 = 53 +ARM_REG_MVFR1 = 54 +ARM_REG_MVFR2 = 55 +ARM_REG_P0 = 56 +ARM_REG_Q0 = 57 +ARM_REG_Q1 = 58 +ARM_REG_Q2 = 59 +ARM_REG_Q3 = 60 +ARM_REG_Q4 = 61 +ARM_REG_Q5 = 62 +ARM_REG_Q6 = 63 +ARM_REG_Q7 = 64 +ARM_REG_Q8 = 65 +ARM_REG_Q9 = 66 +ARM_REG_Q10 = 67 +ARM_REG_Q11 = 68 +ARM_REG_Q12 = 69 +ARM_REG_Q13 = 70 +ARM_REG_Q14 = 71 +ARM_REG_Q15 = 72 +ARM_REG_R0 = 73 +ARM_REG_R1 = 74 +ARM_REG_R2 = 75 +ARM_REG_R3 = 76 +ARM_REG_R4 = 77 +ARM_REG_R5 = 78 +ARM_REG_R6 = 79 +ARM_REG_R7 = 80 +ARM_REG_R8 = 81 +ARM_REG_R9 = 82 +ARM_REG_R10 = 83 +ARM_REG_R11 = 84 +ARM_REG_R12 = 85 +ARM_REG_S0 = 86 +ARM_REG_S1 = 87 +ARM_REG_S2 = 88 +ARM_REG_S3 = 89 +ARM_REG_S4 = 90 +ARM_REG_S5 = 91 +ARM_REG_S6 = 92 +ARM_REG_S7 = 93 +ARM_REG_S8 = 94 +ARM_REG_S9 = 95 +ARM_REG_S10 = 96 +ARM_REG_S11 = 97 +ARM_REG_S12 = 98 +ARM_REG_S13 = 99 +ARM_REG_S14 = 100 +ARM_REG_S15 = 101 +ARM_REG_S16 = 102 +ARM_REG_S17 = 103 +ARM_REG_S18 = 104 +ARM_REG_S19 = 105 +ARM_REG_S20 = 106 +ARM_REG_S21 = 107 +ARM_REG_S22 = 108 +ARM_REG_S23 = 109 +ARM_REG_S24 = 110 +ARM_REG_S25 = 111 +ARM_REG_S26 = 112 +ARM_REG_S27 = 113 +ARM_REG_S28 = 114 +ARM_REG_S29 = 115 +ARM_REG_S30 = 116 +ARM_REG_S31 = 117 +ARM_REG_D0_D2 = 118 +ARM_REG_D1_D3 = 119 +ARM_REG_D2_D4 = 120 +ARM_REG_D3_D5 = 121 +ARM_REG_D4_D6 = 122 +ARM_REG_D5_D7 = 123 +ARM_REG_D6_D8 = 124 +ARM_REG_D7_D9 = 125 +ARM_REG_D8_D10 = 126 +ARM_REG_D9_D11 = 127 +ARM_REG_D10_D12 = 128 +ARM_REG_D11_D13 = 129 +ARM_REG_D12_D14 = 130 +ARM_REG_D13_D15 = 131 +ARM_REG_D14_D16 = 132 +ARM_REG_D15_D17 = 133 +ARM_REG_D16_D18 = 134 +ARM_REG_D17_D19 = 135 +ARM_REG_D18_D20 = 136 +ARM_REG_D19_D21 = 137 +ARM_REG_D20_D22 = 138 +ARM_REG_D21_D23 = 139 +ARM_REG_D22_D24 = 140 +ARM_REG_D23_D25 = 141 +ARM_REG_D24_D26 = 142 +ARM_REG_D25_D27 = 143 +ARM_REG_D26_D28 = 144 +ARM_REG_D27_D29 = 145 +ARM_REG_D28_D30 = 146 +ARM_REG_D29_D31 = 147 +ARM_REG_Q0_Q1 = 148 +ARM_REG_Q1_Q2 = 149 +ARM_REG_Q2_Q3 = 150 +ARM_REG_Q3_Q4 = 151 +ARM_REG_Q4_Q5 = 152 +ARM_REG_Q5_Q6 = 153 +ARM_REG_Q6_Q7 = 154 +ARM_REG_Q7_Q8 = 155 +ARM_REG_Q8_Q9 = 156 +ARM_REG_Q9_Q10 = 157 +ARM_REG_Q10_Q11 = 158 +ARM_REG_Q11_Q12 = 159 +ARM_REG_Q12_Q13 = 160 +ARM_REG_Q13_Q14 = 161 +ARM_REG_Q14_Q15 = 162 +ARM_REG_Q0_Q1_Q2_Q3 = 163 +ARM_REG_Q1_Q2_Q3_Q4 = 164 +ARM_REG_Q2_Q3_Q4_Q5 = 165 +ARM_REG_Q3_Q4_Q5_Q6 = 166 +ARM_REG_Q4_Q5_Q6_Q7 = 167 +ARM_REG_Q5_Q6_Q7_Q8 = 168 +ARM_REG_Q6_Q7_Q8_Q9 = 169 +ARM_REG_Q7_Q8_Q9_Q10 = 170 +ARM_REG_Q8_Q9_Q10_Q11 = 171 +ARM_REG_Q9_Q10_Q11_Q12 = 172 +ARM_REG_Q10_Q11_Q12_Q13 = 173 +ARM_REG_Q11_Q12_Q13_Q14 = 174 +ARM_REG_Q12_Q13_Q14_Q15 = 175 +ARM_REG_R0_R1 = 176 +ARM_REG_R2_R3 = 177 +ARM_REG_R4_R5 = 178 +ARM_REG_R6_R7 = 179 +ARM_REG_R8_R9 = 180 +ARM_REG_R10_R11 = 181 +ARM_REG_R12_SP = 182 +ARM_REG_D0_D1_D2 = 183 +ARM_REG_D1_D2_D3 = 184 +ARM_REG_D2_D3_D4 = 185 +ARM_REG_D3_D4_D5 = 186 +ARM_REG_D4_D5_D6 = 187 +ARM_REG_D5_D6_D7 = 188 +ARM_REG_D6_D7_D8 = 189 +ARM_REG_D7_D8_D9 = 190 +ARM_REG_D8_D9_D10 = 191 +ARM_REG_D9_D10_D11 = 192 +ARM_REG_D10_D11_D12 = 193 +ARM_REG_D11_D12_D13 = 194 +ARM_REG_D12_D13_D14 = 195 +ARM_REG_D13_D14_D15 = 196 +ARM_REG_D14_D15_D16 = 197 +ARM_REG_D15_D16_D17 = 198 +ARM_REG_D16_D17_D18 = 199 +ARM_REG_D17_D18_D19 = 200 +ARM_REG_D18_D19_D20 = 201 +ARM_REG_D19_D20_D21 = 202 +ARM_REG_D20_D21_D22 = 203 +ARM_REG_D21_D22_D23 = 204 +ARM_REG_D22_D23_D24 = 205 +ARM_REG_D23_D24_D25 = 206 +ARM_REG_D24_D25_D26 = 207 +ARM_REG_D25_D26_D27 = 208 +ARM_REG_D26_D27_D28 = 209 +ARM_REG_D27_D28_D29 = 210 +ARM_REG_D28_D29_D30 = 211 +ARM_REG_D29_D30_D31 = 212 +ARM_REG_D0_D2_D4 = 213 +ARM_REG_D1_D3_D5 = 214 +ARM_REG_D2_D4_D6 = 215 +ARM_REG_D3_D5_D7 = 216 +ARM_REG_D4_D6_D8 = 217 +ARM_REG_D5_D7_D9 = 218 +ARM_REG_D6_D8_D10 = 219 +ARM_REG_D7_D9_D11 = 220 +ARM_REG_D8_D10_D12 = 221 +ARM_REG_D9_D11_D13 = 222 +ARM_REG_D10_D12_D14 = 223 +ARM_REG_D11_D13_D15 = 224 +ARM_REG_D12_D14_D16 = 225 +ARM_REG_D13_D15_D17 = 226 +ARM_REG_D14_D16_D18 = 227 +ARM_REG_D15_D17_D19 = 228 +ARM_REG_D16_D18_D20 = 229 +ARM_REG_D17_D19_D21 = 230 +ARM_REG_D18_D20_D22 = 231 +ARM_REG_D19_D21_D23 = 232 +ARM_REG_D20_D22_D24 = 233 +ARM_REG_D21_D23_D25 = 234 +ARM_REG_D22_D24_D26 = 235 +ARM_REG_D23_D25_D27 = 236 +ARM_REG_D24_D26_D28 = 237 +ARM_REG_D25_D27_D29 = 238 +ARM_REG_D26_D28_D30 = 239 +ARM_REG_D27_D29_D31 = 240 +ARM_REG_D0_D2_D4_D6 = 241 +ARM_REG_D1_D3_D5_D7 = 242 +ARM_REG_D2_D4_D6_D8 = 243 +ARM_REG_D3_D5_D7_D9 = 244 +ARM_REG_D4_D6_D8_D10 = 245 +ARM_REG_D5_D7_D9_D11 = 246 +ARM_REG_D6_D8_D10_D12 = 247 +ARM_REG_D7_D9_D11_D13 = 248 +ARM_REG_D8_D10_D12_D14 = 249 +ARM_REG_D9_D11_D13_D15 = 250 +ARM_REG_D10_D12_D14_D16 = 251 +ARM_REG_D11_D13_D15_D17 = 252 +ARM_REG_D12_D14_D16_D18 = 253 +ARM_REG_D13_D15_D17_D19 = 254 +ARM_REG_D14_D16_D18_D20 = 255 +ARM_REG_D15_D17_D19_D21 = 256 +ARM_REG_D16_D18_D20_D22 = 257 +ARM_REG_D17_D19_D21_D23 = 258 +ARM_REG_D18_D20_D22_D24 = 259 +ARM_REG_D19_D21_D23_D25 = 260 +ARM_REG_D20_D22_D24_D26 = 261 +ARM_REG_D21_D23_D25_D27 = 262 +ARM_REG_D22_D24_D26_D28 = 263 +ARM_REG_D23_D25_D27_D29 = 264 +ARM_REG_D24_D26_D28_D30 = 265 +ARM_REG_D25_D27_D29_D31 = 266 +ARM_REG_D1_D2 = 267 +ARM_REG_D3_D4 = 268 +ARM_REG_D5_D6 = 269 +ARM_REG_D7_D8 = 270 +ARM_REG_D9_D10 = 271 +ARM_REG_D11_D12 = 272 +ARM_REG_D13_D14 = 273 +ARM_REG_D15_D16 = 274 +ARM_REG_D17_D18 = 275 +ARM_REG_D19_D20 = 276 +ARM_REG_D21_D22 = 277 +ARM_REG_D23_D24 = 278 +ARM_REG_D25_D26 = 279 +ARM_REG_D27_D28 = 280 +ARM_REG_D29_D30 = 281 +ARM_REG_D1_D2_D3_D4 = 282 +ARM_REG_D3_D4_D5_D6 = 283 +ARM_REG_D5_D6_D7_D8 = 284 +ARM_REG_D7_D8_D9_D10 = 285 +ARM_REG_D9_D10_D11_D12 = 286 +ARM_REG_D11_D12_D13_D14 = 287 +ARM_REG_D13_D14_D15_D16 = 288 +ARM_REG_D15_D16_D17_D18 = 289 +ARM_REG_D17_D18_D19_D20 = 290 +ARM_REG_D19_D20_D21_D22 = 291 +ARM_REG_D21_D22_D23_D24 = 292 +ARM_REG_D23_D24_D25_D26 = 293 +ARM_REG_D25_D26_D27_D28 = 294 +ARM_REG_D27_D28_D29_D30 = 295 +ARM_REG_ENDING = 296 ARM_REG_R13 = ARM_REG_SP ARM_REG_R14 = ARM_REG_LR ARM_REG_R15 = ARM_REG_PC @@ -315,480 +537,647 @@ ARM_REG_SL = ARM_REG_R10 ARM_REG_FP = ARM_REG_R11 ARM_REG_IP = ARM_REG_R12 - -ARM_INS_INVALID = 0 -ARM_INS_ADC = 1 -ARM_INS_ADD = 2 -ARM_INS_ADDW = 3 -ARM_INS_ADR = 4 -ARM_INS_AESD = 5 -ARM_INS_AESE = 6 -ARM_INS_AESIMC = 7 -ARM_INS_AESMC = 8 -ARM_INS_AND = 9 -ARM_INS_ASR = 10 -ARM_INS_B = 11 -ARM_INS_BFC = 12 -ARM_INS_BFI = 13 -ARM_INS_BIC = 14 -ARM_INS_BKPT = 15 -ARM_INS_BL = 16 -ARM_INS_BLX = 17 -ARM_INS_BLXNS = 18 -ARM_INS_BX = 19 -ARM_INS_BXJ = 20 -ARM_INS_BXNS = 21 -ARM_INS_CBNZ = 22 -ARM_INS_CBZ = 23 -ARM_INS_CDP = 24 -ARM_INS_CDP2 = 25 -ARM_INS_CLREX = 26 -ARM_INS_CLZ = 27 -ARM_INS_CMN = 28 -ARM_INS_CMP = 29 -ARM_INS_CPS = 30 -ARM_INS_CRC32B = 31 -ARM_INS_CRC32CB = 32 -ARM_INS_CRC32CH = 33 -ARM_INS_CRC32CW = 34 -ARM_INS_CRC32H = 35 -ARM_INS_CRC32W = 36 -ARM_INS_CSDB = 37 -ARM_INS_DBG = 38 -ARM_INS_DCPS1 = 39 -ARM_INS_DCPS2 = 40 -ARM_INS_DCPS3 = 41 -ARM_INS_DFB = 42 -ARM_INS_DMB = 43 -ARM_INS_DSB = 44 -ARM_INS_EOR = 45 -ARM_INS_ERET = 46 -ARM_INS_ESB = 47 -ARM_INS_FADDD = 48 -ARM_INS_FADDS = 49 -ARM_INS_FCMPZD = 50 -ARM_INS_FCMPZS = 51 -ARM_INS_FCONSTD = 52 -ARM_INS_FCONSTS = 53 -ARM_INS_FLDMDBX = 54 -ARM_INS_FLDMIAX = 55 -ARM_INS_FMDHR = 56 -ARM_INS_FMDLR = 57 -ARM_INS_FMSTAT = 58 -ARM_INS_FSTMDBX = 59 -ARM_INS_FSTMIAX = 60 -ARM_INS_FSUBD = 61 -ARM_INS_FSUBS = 62 -ARM_INS_HINT = 63 -ARM_INS_HLT = 64 -ARM_INS_HVC = 65 -ARM_INS_ISB = 66 -ARM_INS_IT = 67 -ARM_INS_LDA = 68 -ARM_INS_LDAB = 69 -ARM_INS_LDAEX = 70 -ARM_INS_LDAEXB = 71 -ARM_INS_LDAEXD = 72 -ARM_INS_LDAEXH = 73 -ARM_INS_LDAH = 74 -ARM_INS_LDC = 75 -ARM_INS_LDC2 = 76 -ARM_INS_LDC2L = 77 -ARM_INS_LDCL = 78 -ARM_INS_LDM = 79 -ARM_INS_LDMDA = 80 -ARM_INS_LDMDB = 81 -ARM_INS_LDMIB = 82 -ARM_INS_LDR = 83 -ARM_INS_LDRB = 84 -ARM_INS_LDRBT = 85 -ARM_INS_LDRD = 86 -ARM_INS_LDREX = 87 -ARM_INS_LDREXB = 88 -ARM_INS_LDREXD = 89 -ARM_INS_LDREXH = 90 -ARM_INS_LDRH = 91 -ARM_INS_LDRHT = 92 -ARM_INS_LDRSB = 93 -ARM_INS_LDRSBT = 94 -ARM_INS_LDRSH = 95 -ARM_INS_LDRSHT = 96 -ARM_INS_LDRT = 97 -ARM_INS_LSL = 98 -ARM_INS_LSR = 99 -ARM_INS_MCR = 100 -ARM_INS_MCR2 = 101 -ARM_INS_MCRR = 102 -ARM_INS_MCRR2 = 103 -ARM_INS_MLA = 104 -ARM_INS_MLS = 105 -ARM_INS_MOV = 106 -ARM_INS_MOVS = 107 -ARM_INS_MOVT = 108 -ARM_INS_MOVW = 109 -ARM_INS_MRC = 110 -ARM_INS_MRC2 = 111 -ARM_INS_MRRC = 112 -ARM_INS_MRRC2 = 113 -ARM_INS_MRS = 114 -ARM_INS_MSR = 115 -ARM_INS_MUL = 116 -ARM_INS_MVN = 117 -ARM_INS_NEG = 118 -ARM_INS_NOP = 119 -ARM_INS_ORN = 120 -ARM_INS_ORR = 121 -ARM_INS_PKHBT = 122 -ARM_INS_PKHTB = 123 -ARM_INS_PLD = 124 -ARM_INS_PLDW = 125 -ARM_INS_PLI = 126 -ARM_INS_POP = 127 -ARM_INS_PUSH = 128 -ARM_INS_QADD = 129 -ARM_INS_QADD16 = 130 -ARM_INS_QADD8 = 131 -ARM_INS_QASX = 132 -ARM_INS_QDADD = 133 -ARM_INS_QDSUB = 134 -ARM_INS_QSAX = 135 -ARM_INS_QSUB = 136 -ARM_INS_QSUB16 = 137 -ARM_INS_QSUB8 = 138 -ARM_INS_RBIT = 139 -ARM_INS_REV = 140 -ARM_INS_REV16 = 141 -ARM_INS_REVSH = 142 -ARM_INS_RFEDA = 143 -ARM_INS_RFEDB = 144 -ARM_INS_RFEIA = 145 -ARM_INS_RFEIB = 146 -ARM_INS_ROR = 147 -ARM_INS_RRX = 148 -ARM_INS_RSB = 149 -ARM_INS_RSC = 150 -ARM_INS_SADD16 = 151 -ARM_INS_SADD8 = 152 -ARM_INS_SASX = 153 -ARM_INS_SBC = 154 -ARM_INS_SBFX = 155 -ARM_INS_SDIV = 156 -ARM_INS_SEL = 157 -ARM_INS_SETEND = 158 -ARM_INS_SETPAN = 159 -ARM_INS_SEV = 160 -ARM_INS_SEVL = 161 -ARM_INS_SG = 162 -ARM_INS_SHA1C = 163 -ARM_INS_SHA1H = 164 -ARM_INS_SHA1M = 165 -ARM_INS_SHA1P = 166 -ARM_INS_SHA1SU0 = 167 -ARM_INS_SHA1SU1 = 168 -ARM_INS_SHA256H = 169 -ARM_INS_SHA256H2 = 170 -ARM_INS_SHA256SU0 = 171 -ARM_INS_SHA256SU1 = 172 -ARM_INS_SHADD16 = 173 -ARM_INS_SHADD8 = 174 -ARM_INS_SHASX = 175 -ARM_INS_SHSAX = 176 -ARM_INS_SHSUB16 = 177 -ARM_INS_SHSUB8 = 178 -ARM_INS_SMC = 179 -ARM_INS_SMLABB = 180 -ARM_INS_SMLABT = 181 -ARM_INS_SMLAD = 182 -ARM_INS_SMLADX = 183 -ARM_INS_SMLAL = 184 -ARM_INS_SMLALBB = 185 -ARM_INS_SMLALBT = 186 -ARM_INS_SMLALD = 187 -ARM_INS_SMLALDX = 188 -ARM_INS_SMLALTB = 189 -ARM_INS_SMLALTT = 190 -ARM_INS_SMLATB = 191 -ARM_INS_SMLATT = 192 -ARM_INS_SMLAWB = 193 -ARM_INS_SMLAWT = 194 -ARM_INS_SMLSD = 195 -ARM_INS_SMLSDX = 196 -ARM_INS_SMLSLD = 197 -ARM_INS_SMLSLDX = 198 -ARM_INS_SMMLA = 199 -ARM_INS_SMMLAR = 200 -ARM_INS_SMMLS = 201 -ARM_INS_SMMLSR = 202 -ARM_INS_SMMUL = 203 -ARM_INS_SMMULR = 204 -ARM_INS_SMUAD = 205 -ARM_INS_SMUADX = 206 -ARM_INS_SMULBB = 207 -ARM_INS_SMULBT = 208 -ARM_INS_SMULL = 209 -ARM_INS_SMULTB = 210 -ARM_INS_SMULTT = 211 -ARM_INS_SMULWB = 212 -ARM_INS_SMULWT = 213 -ARM_INS_SMUSD = 214 -ARM_INS_SMUSDX = 215 -ARM_INS_SRSDA = 216 -ARM_INS_SRSDB = 217 -ARM_INS_SRSIA = 218 -ARM_INS_SRSIB = 219 -ARM_INS_SSAT = 220 -ARM_INS_SSAT16 = 221 -ARM_INS_SSAX = 222 -ARM_INS_SSUB16 = 223 -ARM_INS_SSUB8 = 224 -ARM_INS_STC = 225 -ARM_INS_STC2 = 226 -ARM_INS_STC2L = 227 -ARM_INS_STCL = 228 -ARM_INS_STL = 229 -ARM_INS_STLB = 230 -ARM_INS_STLEX = 231 -ARM_INS_STLEXB = 232 -ARM_INS_STLEXD = 233 -ARM_INS_STLEXH = 234 -ARM_INS_STLH = 235 -ARM_INS_STM = 236 -ARM_INS_STMDA = 237 -ARM_INS_STMDB = 238 -ARM_INS_STMIB = 239 -ARM_INS_STR = 240 -ARM_INS_STRB = 241 -ARM_INS_STRBT = 242 -ARM_INS_STRD = 243 -ARM_INS_STREX = 244 -ARM_INS_STREXB = 245 -ARM_INS_STREXD = 246 -ARM_INS_STREXH = 247 -ARM_INS_STRH = 248 -ARM_INS_STRHT = 249 -ARM_INS_STRT = 250 -ARM_INS_SUB = 251 -ARM_INS_SUBS = 252 -ARM_INS_SUBW = 253 -ARM_INS_SVC = 254 -ARM_INS_SWP = 255 -ARM_INS_SWPB = 256 -ARM_INS_SXTAB = 257 -ARM_INS_SXTAB16 = 258 -ARM_INS_SXTAH = 259 -ARM_INS_SXTB = 260 -ARM_INS_SXTB16 = 261 -ARM_INS_SXTH = 262 -ARM_INS_TBB = 263 -ARM_INS_TBH = 264 -ARM_INS_TEQ = 265 -ARM_INS_TRAP = 266 -ARM_INS_TSB = 267 -ARM_INS_TST = 268 -ARM_INS_TT = 269 -ARM_INS_TTA = 270 -ARM_INS_TTAT = 271 -ARM_INS_TTT = 272 -ARM_INS_UADD16 = 273 -ARM_INS_UADD8 = 274 -ARM_INS_UASX = 275 -ARM_INS_UBFX = 276 -ARM_INS_UDF = 277 -ARM_INS_UDIV = 278 -ARM_INS_UHADD16 = 279 -ARM_INS_UHADD8 = 280 -ARM_INS_UHASX = 281 -ARM_INS_UHSAX = 282 -ARM_INS_UHSUB16 = 283 -ARM_INS_UHSUB8 = 284 -ARM_INS_UMAAL = 285 -ARM_INS_UMLAL = 286 -ARM_INS_UMULL = 287 -ARM_INS_UQADD16 = 288 -ARM_INS_UQADD8 = 289 -ARM_INS_UQASX = 290 -ARM_INS_UQSAX = 291 -ARM_INS_UQSUB16 = 292 -ARM_INS_UQSUB8 = 293 -ARM_INS_USAD8 = 294 -ARM_INS_USADA8 = 295 -ARM_INS_USAT = 296 -ARM_INS_USAT16 = 297 -ARM_INS_USAX = 298 -ARM_INS_USUB16 = 299 -ARM_INS_USUB8 = 300 -ARM_INS_UXTAB = 301 -ARM_INS_UXTAB16 = 302 -ARM_INS_UXTAH = 303 -ARM_INS_UXTB = 304 -ARM_INS_UXTB16 = 305 -ARM_INS_UXTH = 306 -ARM_INS_VABA = 307 -ARM_INS_VABAL = 308 -ARM_INS_VABD = 309 -ARM_INS_VABDL = 310 -ARM_INS_VABS = 311 -ARM_INS_VACGE = 312 -ARM_INS_VACGT = 313 -ARM_INS_VACLE = 314 -ARM_INS_VACLT = 315 -ARM_INS_VADD = 316 -ARM_INS_VADDHN = 317 -ARM_INS_VADDL = 318 -ARM_INS_VADDW = 319 -ARM_INS_VAND = 320 -ARM_INS_VBIC = 321 -ARM_INS_VBIF = 322 -ARM_INS_VBIT = 323 -ARM_INS_VBSL = 324 -ARM_INS_VCADD = 325 -ARM_INS_VCEQ = 326 -ARM_INS_VCGE = 327 -ARM_INS_VCGT = 328 -ARM_INS_VCLE = 329 -ARM_INS_VCLS = 330 -ARM_INS_VCLT = 331 -ARM_INS_VCLZ = 332 -ARM_INS_VCMLA = 333 -ARM_INS_VCMP = 334 -ARM_INS_VCMPE = 335 -ARM_INS_VCNT = 336 -ARM_INS_VCVT = 337 -ARM_INS_VCVTA = 338 -ARM_INS_VCVTB = 339 -ARM_INS_VCVTM = 340 -ARM_INS_VCVTN = 341 -ARM_INS_VCVTP = 342 -ARM_INS_VCVTR = 343 -ARM_INS_VCVTT = 344 -ARM_INS_VDIV = 345 -ARM_INS_VDUP = 346 -ARM_INS_VEOR = 347 -ARM_INS_VEXT = 348 -ARM_INS_VFMA = 349 -ARM_INS_VFMS = 350 -ARM_INS_VFNMA = 351 -ARM_INS_VFNMS = 352 -ARM_INS_VHADD = 353 -ARM_INS_VHSUB = 354 -ARM_INS_VINS = 355 -ARM_INS_VJCVT = 356 -ARM_INS_VLD1 = 357 -ARM_INS_VLD2 = 358 -ARM_INS_VLD3 = 359 -ARM_INS_VLD4 = 360 -ARM_INS_VLDMDB = 361 -ARM_INS_VLDMIA = 362 -ARM_INS_VLDR = 363 -ARM_INS_VLLDM = 364 -ARM_INS_VLSTM = 365 -ARM_INS_VMAX = 366 -ARM_INS_VMAXNM = 367 -ARM_INS_VMIN = 368 -ARM_INS_VMINNM = 369 -ARM_INS_VMLA = 370 -ARM_INS_VMLAL = 371 -ARM_INS_VMLS = 372 -ARM_INS_VMLSL = 373 -ARM_INS_VMOV = 374 -ARM_INS_VMOVL = 375 -ARM_INS_VMOVN = 376 -ARM_INS_VMOVX = 377 -ARM_INS_VMRS = 378 -ARM_INS_VMSR = 379 -ARM_INS_VMUL = 380 -ARM_INS_VMULL = 381 -ARM_INS_VMVN = 382 -ARM_INS_VNEG = 383 -ARM_INS_VNMLA = 384 -ARM_INS_VNMLS = 385 -ARM_INS_VNMUL = 386 -ARM_INS_VORN = 387 -ARM_INS_VORR = 388 -ARM_INS_VPADAL = 389 -ARM_INS_VPADD = 390 -ARM_INS_VPADDL = 391 -ARM_INS_VPMAX = 392 -ARM_INS_VPMIN = 393 -ARM_INS_VPOP = 394 -ARM_INS_VPUSH = 395 -ARM_INS_VQABS = 396 -ARM_INS_VQADD = 397 -ARM_INS_VQDMLAL = 398 -ARM_INS_VQDMLSL = 399 -ARM_INS_VQDMULH = 400 -ARM_INS_VQDMULL = 401 -ARM_INS_VQMOVN = 402 -ARM_INS_VQMOVUN = 403 -ARM_INS_VQNEG = 404 -ARM_INS_VQRDMLAH = 405 -ARM_INS_VQRDMLSH = 406 -ARM_INS_VQRDMULH = 407 -ARM_INS_VQRSHL = 408 -ARM_INS_VQRSHRN = 409 -ARM_INS_VQRSHRUN = 410 -ARM_INS_VQSHL = 411 -ARM_INS_VQSHLU = 412 -ARM_INS_VQSHRN = 413 -ARM_INS_VQSHRUN = 414 -ARM_INS_VQSUB = 415 -ARM_INS_VRADDHN = 416 -ARM_INS_VRECPE = 417 -ARM_INS_VRECPS = 418 -ARM_INS_VREV16 = 419 -ARM_INS_VREV32 = 420 -ARM_INS_VREV64 = 421 -ARM_INS_VRHADD = 422 -ARM_INS_VRINTA = 423 -ARM_INS_VRINTM = 424 -ARM_INS_VRINTN = 425 -ARM_INS_VRINTP = 426 -ARM_INS_VRINTR = 427 -ARM_INS_VRINTX = 428 -ARM_INS_VRINTZ = 429 -ARM_INS_VRSHL = 430 -ARM_INS_VRSHR = 431 -ARM_INS_VRSHRN = 432 -ARM_INS_VRSQRTE = 433 -ARM_INS_VRSQRTS = 434 -ARM_INS_VRSRA = 435 -ARM_INS_VRSUBHN = 436 -ARM_INS_VSDOT = 437 -ARM_INS_VSELEQ = 438 -ARM_INS_VSELGE = 439 -ARM_INS_VSELGT = 440 -ARM_INS_VSELVS = 441 -ARM_INS_VSHL = 442 -ARM_INS_VSHLL = 443 -ARM_INS_VSHR = 444 -ARM_INS_VSHRN = 445 -ARM_INS_VSLI = 446 -ARM_INS_VSQRT = 447 -ARM_INS_VSRA = 448 -ARM_INS_VSRI = 449 -ARM_INS_VST1 = 450 -ARM_INS_VST2 = 451 -ARM_INS_VST3 = 452 -ARM_INS_VST4 = 453 -ARM_INS_VSTMDB = 454 -ARM_INS_VSTMIA = 455 -ARM_INS_VSTR = 456 -ARM_INS_VSUB = 457 -ARM_INS_VSUBHN = 458 -ARM_INS_VSUBL = 459 -ARM_INS_VSUBW = 460 -ARM_INS_VSWP = 461 -ARM_INS_VTBL = 462 -ARM_INS_VTBX = 463 -ARM_INS_VTRN = 464 -ARM_INS_VTST = 465 -ARM_INS_VUDOT = 466 -ARM_INS_VUZP = 467 -ARM_INS_VZIP = 468 -ARM_INS_WFE = 469 -ARM_INS_WFI = 470 -ARM_INS_YIELD = 471 -ARM_INS_ENDING = 472 +ARM_INS_INVALID = 297 +ARM_INS_ASR = 298 +ARM_INS_IT = 299 +ARM_INS_LDRBT = 300 +ARM_INS_LDR = 301 +ARM_INS_LDRHT = 302 +ARM_INS_LDRSBT = 303 +ARM_INS_LDRSHT = 304 +ARM_INS_LDRT = 305 +ARM_INS_LSL = 306 +ARM_INS_LSR = 307 +ARM_INS_ROR = 308 +ARM_INS_RRX = 309 +ARM_INS_STRBT = 310 +ARM_INS_STRT = 311 +ARM_INS_VLD1 = 312 +ARM_INS_VLD2 = 313 +ARM_INS_VLD3 = 314 +ARM_INS_VLD4 = 315 +ARM_INS_VST1 = 316 +ARM_INS_VST2 = 317 +ARM_INS_VST3 = 318 +ARM_INS_VST4 = 319 +ARM_INS_LDRB = 320 +ARM_INS_LDRH = 321 +ARM_INS_LDRSB = 322 +ARM_INS_LDRSH = 323 +ARM_INS_MOVS = 324 +ARM_INS_MOV = 325 +ARM_INS_STR = 326 +ARM_INS_ADC = 327 +ARM_INS_ADD = 328 +ARM_INS_ADR = 329 +ARM_INS_AESD = 330 +ARM_INS_AESE = 331 +ARM_INS_AESIMC = 332 +ARM_INS_AESMC = 333 +ARM_INS_AND = 334 +ARM_INS_VDOT = 335 +ARM_INS_VCVT = 336 +ARM_INS_VCVTB = 337 +ARM_INS_VCVTT = 338 +ARM_INS_BFC = 339 +ARM_INS_BFI = 340 +ARM_INS_BIC = 341 +ARM_INS_BKPT = 342 +ARM_INS_BL = 343 +ARM_INS_BLX = 344 +ARM_INS_BX = 345 +ARM_INS_BXJ = 346 +ARM_INS_B = 347 +ARM_INS_CX1 = 348 +ARM_INS_CX1A = 349 +ARM_INS_CX1D = 350 +ARM_INS_CX1DA = 351 +ARM_INS_CX2 = 352 +ARM_INS_CX2A = 353 +ARM_INS_CX2D = 354 +ARM_INS_CX2DA = 355 +ARM_INS_CX3 = 356 +ARM_INS_CX3A = 357 +ARM_INS_CX3D = 358 +ARM_INS_CX3DA = 359 +ARM_INS_VCX1A = 360 +ARM_INS_VCX1 = 361 +ARM_INS_VCX2A = 362 +ARM_INS_VCX2 = 363 +ARM_INS_VCX3A = 364 +ARM_INS_VCX3 = 365 +ARM_INS_CDP = 366 +ARM_INS_CDP2 = 367 +ARM_INS_CLREX = 368 +ARM_INS_CLZ = 369 +ARM_INS_CMN = 370 +ARM_INS_CMP = 371 +ARM_INS_CPS = 372 +ARM_INS_CRC32B = 373 +ARM_INS_CRC32CB = 374 +ARM_INS_CRC32CH = 375 +ARM_INS_CRC32CW = 376 +ARM_INS_CRC32H = 377 +ARM_INS_CRC32W = 378 +ARM_INS_DBG = 379 +ARM_INS_DMB = 380 +ARM_INS_DSB = 381 +ARM_INS_EOR = 382 +ARM_INS_ERET = 383 +ARM_INS_VMOV = 384 +ARM_INS_FLDMDBX = 385 +ARM_INS_FLDMIAX = 386 +ARM_INS_VMRS = 387 +ARM_INS_FSTMDBX = 388 +ARM_INS_FSTMIAX = 389 +ARM_INS_HINT = 390 +ARM_INS_HLT = 391 +ARM_INS_HVC = 392 +ARM_INS_ISB = 393 +ARM_INS_LDA = 394 +ARM_INS_LDAB = 395 +ARM_INS_LDAEX = 396 +ARM_INS_LDAEXB = 397 +ARM_INS_LDAEXD = 398 +ARM_INS_LDAEXH = 399 +ARM_INS_LDAH = 400 +ARM_INS_LDC2L = 401 +ARM_INS_LDC2 = 402 +ARM_INS_LDCL = 403 +ARM_INS_LDC = 404 +ARM_INS_LDMDA = 405 +ARM_INS_LDMDB = 406 +ARM_INS_LDM = 407 +ARM_INS_LDMIB = 408 +ARM_INS_LDRD = 409 +ARM_INS_LDREX = 410 +ARM_INS_LDREXB = 411 +ARM_INS_LDREXD = 412 +ARM_INS_LDREXH = 413 +ARM_INS_MCR = 414 +ARM_INS_MCR2 = 415 +ARM_INS_MCRR = 416 +ARM_INS_MCRR2 = 417 +ARM_INS_MLA = 418 +ARM_INS_MLS = 419 +ARM_INS_MOVT = 420 +ARM_INS_MOVW = 421 +ARM_INS_MRC = 422 +ARM_INS_MRC2 = 423 +ARM_INS_MRRC = 424 +ARM_INS_MRRC2 = 425 +ARM_INS_MRS = 426 +ARM_INS_MSR = 427 +ARM_INS_MUL = 428 +ARM_INS_ASRL = 429 +ARM_INS_DLSTP = 430 +ARM_INS_LCTP = 431 +ARM_INS_LETP = 432 +ARM_INS_LSLL = 433 +ARM_INS_LSRL = 434 +ARM_INS_SQRSHR = 435 +ARM_INS_SQRSHRL = 436 +ARM_INS_SQSHL = 437 +ARM_INS_SQSHLL = 438 +ARM_INS_SRSHR = 439 +ARM_INS_SRSHRL = 440 +ARM_INS_UQRSHL = 441 +ARM_INS_UQRSHLL = 442 +ARM_INS_UQSHL = 443 +ARM_INS_UQSHLL = 444 +ARM_INS_URSHR = 445 +ARM_INS_URSHRL = 446 +ARM_INS_VABAV = 447 +ARM_INS_VABD = 448 +ARM_INS_VABS = 449 +ARM_INS_VADC = 450 +ARM_INS_VADCI = 451 +ARM_INS_VADDLVA = 452 +ARM_INS_VADDLV = 453 +ARM_INS_VADDVA = 454 +ARM_INS_VADDV = 455 +ARM_INS_VADD = 456 +ARM_INS_VAND = 457 +ARM_INS_VBIC = 458 +ARM_INS_VBRSR = 459 +ARM_INS_VCADD = 460 +ARM_INS_VCLS = 461 +ARM_INS_VCLZ = 462 +ARM_INS_VCMLA = 463 +ARM_INS_VCMP = 464 +ARM_INS_VCMUL = 465 +ARM_INS_VCTP = 466 +ARM_INS_VCVTA = 467 +ARM_INS_VCVTM = 468 +ARM_INS_VCVTN = 469 +ARM_INS_VCVTP = 470 +ARM_INS_VDDUP = 471 +ARM_INS_VDUP = 472 +ARM_INS_VDWDUP = 473 +ARM_INS_VEOR = 474 +ARM_INS_VFMAS = 475 +ARM_INS_VFMA = 476 +ARM_INS_VFMS = 477 +ARM_INS_VHADD = 478 +ARM_INS_VHCADD = 479 +ARM_INS_VHSUB = 480 +ARM_INS_VIDUP = 481 +ARM_INS_VIWDUP = 482 +ARM_INS_VLD20 = 483 +ARM_INS_VLD21 = 484 +ARM_INS_VLD40 = 485 +ARM_INS_VLD41 = 486 +ARM_INS_VLD42 = 487 +ARM_INS_VLD43 = 488 +ARM_INS_VLDRB = 489 +ARM_INS_VLDRD = 490 +ARM_INS_VLDRH = 491 +ARM_INS_VLDRW = 492 +ARM_INS_VMAXAV = 493 +ARM_INS_VMAXA = 494 +ARM_INS_VMAXNMAV = 495 +ARM_INS_VMAXNMA = 496 +ARM_INS_VMAXNMV = 497 +ARM_INS_VMAXNM = 498 +ARM_INS_VMAXV = 499 +ARM_INS_VMAX = 500 +ARM_INS_VMINAV = 501 +ARM_INS_VMINA = 502 +ARM_INS_VMINNMAV = 503 +ARM_INS_VMINNMA = 504 +ARM_INS_VMINNMV = 505 +ARM_INS_VMINNM = 506 +ARM_INS_VMINV = 507 +ARM_INS_VMIN = 508 +ARM_INS_VMLADAVA = 509 +ARM_INS_VMLADAVAX = 510 +ARM_INS_VMLADAV = 511 +ARM_INS_VMLADAVX = 512 +ARM_INS_VMLALDAVA = 513 +ARM_INS_VMLALDAVAX = 514 +ARM_INS_VMLALDAV = 515 +ARM_INS_VMLALDAVX = 516 +ARM_INS_VMLAS = 517 +ARM_INS_VMLA = 518 +ARM_INS_VMLSDAVA = 519 +ARM_INS_VMLSDAVAX = 520 +ARM_INS_VMLSDAV = 521 +ARM_INS_VMLSDAVX = 522 +ARM_INS_VMLSLDAVA = 523 +ARM_INS_VMLSLDAVAX = 524 +ARM_INS_VMLSLDAV = 525 +ARM_INS_VMLSLDAVX = 526 +ARM_INS_VMOVLB = 527 +ARM_INS_VMOVLT = 528 +ARM_INS_VMOVNB = 529 +ARM_INS_VMOVNT = 530 +ARM_INS_VMULH = 531 +ARM_INS_VMULLB = 532 +ARM_INS_VMULLT = 533 +ARM_INS_VMUL = 534 +ARM_INS_VMVN = 535 +ARM_INS_VNEG = 536 +ARM_INS_VORN = 537 +ARM_INS_VORR = 538 +ARM_INS_VPNOT = 539 +ARM_INS_VPSEL = 540 +ARM_INS_VPST = 541 +ARM_INS_VPT = 542 +ARM_INS_VQABS = 543 +ARM_INS_VQADD = 544 +ARM_INS_VQDMLADHX = 545 +ARM_INS_VQDMLADH = 546 +ARM_INS_VQDMLAH = 547 +ARM_INS_VQDMLASH = 548 +ARM_INS_VQDMLSDHX = 549 +ARM_INS_VQDMLSDH = 550 +ARM_INS_VQDMULH = 551 +ARM_INS_VQDMULLB = 552 +ARM_INS_VQDMULLT = 553 +ARM_INS_VQMOVNB = 554 +ARM_INS_VQMOVNT = 555 +ARM_INS_VQMOVUNB = 556 +ARM_INS_VQMOVUNT = 557 +ARM_INS_VQNEG = 558 +ARM_INS_VQRDMLADHX = 559 +ARM_INS_VQRDMLADH = 560 +ARM_INS_VQRDMLAH = 561 +ARM_INS_VQRDMLASH = 562 +ARM_INS_VQRDMLSDHX = 563 +ARM_INS_VQRDMLSDH = 564 +ARM_INS_VQRDMULH = 565 +ARM_INS_VQRSHL = 566 +ARM_INS_VQRSHRNB = 567 +ARM_INS_VQRSHRNT = 568 +ARM_INS_VQRSHRUNB = 569 +ARM_INS_VQRSHRUNT = 570 +ARM_INS_VQSHLU = 571 +ARM_INS_VQSHL = 572 +ARM_INS_VQSHRNB = 573 +ARM_INS_VQSHRNT = 574 +ARM_INS_VQSHRUNB = 575 +ARM_INS_VQSHRUNT = 576 +ARM_INS_VQSUB = 577 +ARM_INS_VREV16 = 578 +ARM_INS_VREV32 = 579 +ARM_INS_VREV64 = 580 +ARM_INS_VRHADD = 581 +ARM_INS_VRINTA = 582 +ARM_INS_VRINTM = 583 +ARM_INS_VRINTN = 584 +ARM_INS_VRINTP = 585 +ARM_INS_VRINTX = 586 +ARM_INS_VRINTZ = 587 +ARM_INS_VRMLALDAVHA = 588 +ARM_INS_VRMLALDAVHAX = 589 +ARM_INS_VRMLALDAVH = 590 +ARM_INS_VRMLALDAVHX = 591 +ARM_INS_VRMLSLDAVHA = 592 +ARM_INS_VRMLSLDAVHAX = 593 +ARM_INS_VRMLSLDAVH = 594 +ARM_INS_VRMLSLDAVHX = 595 +ARM_INS_VRMULH = 596 +ARM_INS_VRSHL = 597 +ARM_INS_VRSHRNB = 598 +ARM_INS_VRSHRNT = 599 +ARM_INS_VRSHR = 600 +ARM_INS_VSBC = 601 +ARM_INS_VSBCI = 602 +ARM_INS_VSHLC = 603 +ARM_INS_VSHLLB = 604 +ARM_INS_VSHLLT = 605 +ARM_INS_VSHL = 606 +ARM_INS_VSHRNB = 607 +ARM_INS_VSHRNT = 608 +ARM_INS_VSHR = 609 +ARM_INS_VSLI = 610 +ARM_INS_VSRI = 611 +ARM_INS_VST20 = 612 +ARM_INS_VST21 = 613 +ARM_INS_VST40 = 614 +ARM_INS_VST41 = 615 +ARM_INS_VST42 = 616 +ARM_INS_VST43 = 617 +ARM_INS_VSTRB = 618 +ARM_INS_VSTRD = 619 +ARM_INS_VSTRH = 620 +ARM_INS_VSTRW = 621 +ARM_INS_VSUB = 622 +ARM_INS_WLSTP = 623 +ARM_INS_MVN = 624 +ARM_INS_ORR = 625 +ARM_INS_PKHBT = 626 +ARM_INS_PKHTB = 627 +ARM_INS_PLDW = 628 +ARM_INS_PLD = 629 +ARM_INS_PLI = 630 +ARM_INS_QADD = 631 +ARM_INS_QADD16 = 632 +ARM_INS_QADD8 = 633 +ARM_INS_QASX = 634 +ARM_INS_QDADD = 635 +ARM_INS_QDSUB = 636 +ARM_INS_QSAX = 637 +ARM_INS_QSUB = 638 +ARM_INS_QSUB16 = 639 +ARM_INS_QSUB8 = 640 +ARM_INS_RBIT = 641 +ARM_INS_REV = 642 +ARM_INS_REV16 = 643 +ARM_INS_REVSH = 644 +ARM_INS_RFEDA = 645 +ARM_INS_RFEDB = 646 +ARM_INS_RFEIA = 647 +ARM_INS_RFEIB = 648 +ARM_INS_RSB = 649 +ARM_INS_RSC = 650 +ARM_INS_SADD16 = 651 +ARM_INS_SADD8 = 652 +ARM_INS_SASX = 653 +ARM_INS_SB = 654 +ARM_INS_SBC = 655 +ARM_INS_SBFX = 656 +ARM_INS_SDIV = 657 +ARM_INS_SEL = 658 +ARM_INS_SETEND = 659 +ARM_INS_SETPAN = 660 +ARM_INS_SHA1C = 661 +ARM_INS_SHA1H = 662 +ARM_INS_SHA1M = 663 +ARM_INS_SHA1P = 664 +ARM_INS_SHA1SU0 = 665 +ARM_INS_SHA1SU1 = 666 +ARM_INS_SHA256H = 667 +ARM_INS_SHA256H2 = 668 +ARM_INS_SHA256SU0 = 669 +ARM_INS_SHA256SU1 = 670 +ARM_INS_SHADD16 = 671 +ARM_INS_SHADD8 = 672 +ARM_INS_SHASX = 673 +ARM_INS_SHSAX = 674 +ARM_INS_SHSUB16 = 675 +ARM_INS_SHSUB8 = 676 +ARM_INS_SMC = 677 +ARM_INS_SMLABB = 678 +ARM_INS_SMLABT = 679 +ARM_INS_SMLAD = 680 +ARM_INS_SMLADX = 681 +ARM_INS_SMLAL = 682 +ARM_INS_SMLALBB = 683 +ARM_INS_SMLALBT = 684 +ARM_INS_SMLALD = 685 +ARM_INS_SMLALDX = 686 +ARM_INS_SMLALTB = 687 +ARM_INS_SMLALTT = 688 +ARM_INS_SMLATB = 689 +ARM_INS_SMLATT = 690 +ARM_INS_SMLAWB = 691 +ARM_INS_SMLAWT = 692 +ARM_INS_SMLSD = 693 +ARM_INS_SMLSDX = 694 +ARM_INS_SMLSLD = 695 +ARM_INS_SMLSLDX = 696 +ARM_INS_SMMLA = 697 +ARM_INS_SMMLAR = 698 +ARM_INS_SMMLS = 699 +ARM_INS_SMMLSR = 700 +ARM_INS_SMMUL = 701 +ARM_INS_SMMULR = 702 +ARM_INS_SMUAD = 703 +ARM_INS_SMUADX = 704 +ARM_INS_SMULBB = 705 +ARM_INS_SMULBT = 706 +ARM_INS_SMULL = 707 +ARM_INS_SMULTB = 708 +ARM_INS_SMULTT = 709 +ARM_INS_SMULWB = 710 +ARM_INS_SMULWT = 711 +ARM_INS_SMUSD = 712 +ARM_INS_SMUSDX = 713 +ARM_INS_SRSDA = 714 +ARM_INS_SRSDB = 715 +ARM_INS_SRSIA = 716 +ARM_INS_SRSIB = 717 +ARM_INS_SSAT = 718 +ARM_INS_SSAT16 = 719 +ARM_INS_SSAX = 720 +ARM_INS_SSUB16 = 721 +ARM_INS_SSUB8 = 722 +ARM_INS_STC2L = 723 +ARM_INS_STC2 = 724 +ARM_INS_STCL = 725 +ARM_INS_STC = 726 +ARM_INS_STL = 727 +ARM_INS_STLB = 728 +ARM_INS_STLEX = 729 +ARM_INS_STLEXB = 730 +ARM_INS_STLEXD = 731 +ARM_INS_STLEXH = 732 +ARM_INS_STLH = 733 +ARM_INS_STMDA = 734 +ARM_INS_STMDB = 735 +ARM_INS_STM = 736 +ARM_INS_STMIB = 737 +ARM_INS_STRB = 738 +ARM_INS_STRD = 739 +ARM_INS_STREX = 740 +ARM_INS_STREXB = 741 +ARM_INS_STREXD = 742 +ARM_INS_STREXH = 743 +ARM_INS_STRH = 744 +ARM_INS_STRHT = 745 +ARM_INS_SUB = 746 +ARM_INS_SVC = 747 +ARM_INS_SWP = 748 +ARM_INS_SWPB = 749 +ARM_INS_SXTAB = 750 +ARM_INS_SXTAB16 = 751 +ARM_INS_SXTAH = 752 +ARM_INS_SXTB = 753 +ARM_INS_SXTB16 = 754 +ARM_INS_SXTH = 755 +ARM_INS_TEQ = 756 +ARM_INS_TRAP = 757 +ARM_INS_TSB = 758 +ARM_INS_TST = 759 +ARM_INS_UADD16 = 760 +ARM_INS_UADD8 = 761 +ARM_INS_UASX = 762 +ARM_INS_UBFX = 763 +ARM_INS_UDF = 764 +ARM_INS_UDIV = 765 +ARM_INS_UHADD16 = 766 +ARM_INS_UHADD8 = 767 +ARM_INS_UHASX = 768 +ARM_INS_UHSAX = 769 +ARM_INS_UHSUB16 = 770 +ARM_INS_UHSUB8 = 771 +ARM_INS_UMAAL = 772 +ARM_INS_UMLAL = 773 +ARM_INS_UMULL = 774 +ARM_INS_UQADD16 = 775 +ARM_INS_UQADD8 = 776 +ARM_INS_UQASX = 777 +ARM_INS_UQSAX = 778 +ARM_INS_UQSUB16 = 779 +ARM_INS_UQSUB8 = 780 +ARM_INS_USAD8 = 781 +ARM_INS_USADA8 = 782 +ARM_INS_USAT = 783 +ARM_INS_USAT16 = 784 +ARM_INS_USAX = 785 +ARM_INS_USUB16 = 786 +ARM_INS_USUB8 = 787 +ARM_INS_UXTAB = 788 +ARM_INS_UXTAB16 = 789 +ARM_INS_UXTAH = 790 +ARM_INS_UXTB = 791 +ARM_INS_UXTB16 = 792 +ARM_INS_UXTH = 793 +ARM_INS_VABAL = 794 +ARM_INS_VABA = 795 +ARM_INS_VABDL = 796 +ARM_INS_VACGE = 797 +ARM_INS_VACGT = 798 +ARM_INS_VADDHN = 799 +ARM_INS_VADDL = 800 +ARM_INS_VADDW = 801 +ARM_INS_VFMAB = 802 +ARM_INS_VFMAT = 803 +ARM_INS_VBIF = 804 +ARM_INS_VBIT = 805 +ARM_INS_VBSL = 806 +ARM_INS_VCEQ = 807 +ARM_INS_VCGE = 808 +ARM_INS_VCGT = 809 +ARM_INS_VCLE = 810 +ARM_INS_VCLT = 811 +ARM_INS_VCMPE = 812 +ARM_INS_VCNT = 813 +ARM_INS_VDIV = 814 +ARM_INS_VEXT = 815 +ARM_INS_VFMAL = 816 +ARM_INS_VFMSL = 817 +ARM_INS_VFNMA = 818 +ARM_INS_VFNMS = 819 +ARM_INS_VINS = 820 +ARM_INS_VJCVT = 821 +ARM_INS_VLDMDB = 822 +ARM_INS_VLDMIA = 823 +ARM_INS_VLDR = 824 +ARM_INS_VLLDM = 825 +ARM_INS_VLSTM = 826 +ARM_INS_VMLAL = 827 +ARM_INS_VMLS = 828 +ARM_INS_VMLSL = 829 +ARM_INS_VMMLA = 830 +ARM_INS_VMOVX = 831 +ARM_INS_VMOVL = 832 +ARM_INS_VMOVN = 833 +ARM_INS_VMSR = 834 +ARM_INS_VMULL = 835 +ARM_INS_VNMLA = 836 +ARM_INS_VNMLS = 837 +ARM_INS_VNMUL = 838 +ARM_INS_VPADAL = 839 +ARM_INS_VPADDL = 840 +ARM_INS_VPADD = 841 +ARM_INS_VPMAX = 842 +ARM_INS_VPMIN = 843 +ARM_INS_VQDMLAL = 844 +ARM_INS_VQDMLSL = 845 +ARM_INS_VQDMULL = 846 +ARM_INS_VQMOVUN = 847 +ARM_INS_VQMOVN = 848 +ARM_INS_VQRDMLSH = 849 +ARM_INS_VQRSHRN = 850 +ARM_INS_VQRSHRUN = 851 +ARM_INS_VQSHRN = 852 +ARM_INS_VQSHRUN = 853 +ARM_INS_VRADDHN = 854 +ARM_INS_VRECPE = 855 +ARM_INS_VRECPS = 856 +ARM_INS_VRINTR = 857 +ARM_INS_VRSHRN = 858 +ARM_INS_VRSQRTE = 859 +ARM_INS_VRSQRTS = 860 +ARM_INS_VRSRA = 861 +ARM_INS_VRSUBHN = 862 +ARM_INS_VSCCLRM = 863 +ARM_INS_VSDOT = 864 +ARM_INS_VSELEQ = 865 +ARM_INS_VSELGE = 866 +ARM_INS_VSELGT = 867 +ARM_INS_VSELVS = 868 +ARM_INS_VSHLL = 869 +ARM_INS_VSHRN = 870 +ARM_INS_VSMMLA = 871 +ARM_INS_VSQRT = 872 +ARM_INS_VSRA = 873 +ARM_INS_VSTMDB = 874 +ARM_INS_VSTMIA = 875 +ARM_INS_VSTR = 876 +ARM_INS_VSUBHN = 877 +ARM_INS_VSUBL = 878 +ARM_INS_VSUBW = 879 +ARM_INS_VSUDOT = 880 +ARM_INS_VSWP = 881 +ARM_INS_VTBL = 882 +ARM_INS_VTBX = 883 +ARM_INS_VCVTR = 884 +ARM_INS_VTRN = 885 +ARM_INS_VTST = 886 +ARM_INS_VUDOT = 887 +ARM_INS_VUMMLA = 888 +ARM_INS_VUSDOT = 889 +ARM_INS_VUSMMLA = 890 +ARM_INS_VUZP = 891 +ARM_INS_VZIP = 892 +ARM_INS_ADDW = 893 +ARM_INS_AUT = 894 +ARM_INS_AUTG = 895 +ARM_INS_BFL = 896 +ARM_INS_BFLX = 897 +ARM_INS_BF = 898 +ARM_INS_BFCSEL = 899 +ARM_INS_BFX = 900 +ARM_INS_BTI = 901 +ARM_INS_BXAUT = 902 +ARM_INS_CLRM = 903 +ARM_INS_CSEL = 904 +ARM_INS_CSINC = 905 +ARM_INS_CSINV = 906 +ARM_INS_CSNEG = 907 +ARM_INS_DCPS1 = 908 +ARM_INS_DCPS2 = 909 +ARM_INS_DCPS3 = 910 +ARM_INS_DLS = 911 +ARM_INS_LE = 912 +ARM_INS_ORN = 913 +ARM_INS_PAC = 914 +ARM_INS_PACBTI = 915 +ARM_INS_PACG = 916 +ARM_INS_SG = 917 +ARM_INS_SUBS = 918 +ARM_INS_SUBW = 919 +ARM_INS_TBB = 920 +ARM_INS_TBH = 921 +ARM_INS_TT = 922 +ARM_INS_TTA = 923 +ARM_INS_TTAT = 924 +ARM_INS_TTT = 925 +ARM_INS_WLS = 926 +ARM_INS_BLXNS = 927 +ARM_INS_BXNS = 928 +ARM_INS_CBNZ = 929 +ARM_INS_CBZ = 930 +ARM_INS_POP = 931 +ARM_INS_PUSH = 932 +ARM_INS___BRKDIV0 = 933 +ARM_INS_VPOP = 934 +ARM_INS_VPUSH = 935 +ARM_INS_ENDING = 936 +ARM_INS_NOP = ARM_INS_HINT ARM_GRP_INVALID = 0 ARM_GRP_JUMP = 1 @@ -796,36 +1185,61 @@ ARM_GRP_INT = 4 ARM_GRP_PRIVILEGE = 6 ARM_GRP_BRANCH_RELATIVE = 7 -ARM_GRP_CRYPTO = 128 -ARM_GRP_DATABARRIER = 129 -ARM_GRP_DIVIDE = 130 -ARM_GRP_FPARMV8 = 131 -ARM_GRP_MULTPRO = 132 -ARM_GRP_NEON = 133 -ARM_GRP_T2EXTRACTPACK = 134 -ARM_GRP_THUMB2DSP = 135 -ARM_GRP_TRUSTZONE = 136 -ARM_GRP_V4T = 137 -ARM_GRP_V5T = 138 -ARM_GRP_V5TE = 139 -ARM_GRP_V6 = 140 -ARM_GRP_V6T2 = 141 -ARM_GRP_V7 = 142 -ARM_GRP_V8 = 143 -ARM_GRP_VFP2 = 144 -ARM_GRP_VFP3 = 145 -ARM_GRP_VFP4 = 146 -ARM_GRP_ARM = 147 -ARM_GRP_MCLASS = 148 -ARM_GRP_NOTMCLASS = 149 -ARM_GRP_THUMB = 150 -ARM_GRP_THUMB1ONLY = 151 -ARM_GRP_THUMB2 = 152 -ARM_GRP_PREV8 = 153 -ARM_GRP_FPVMLX = 154 -ARM_GRP_MULOPS = 155 -ARM_GRP_CRC = 156 -ARM_GRP_DPVFP = 157 -ARM_GRP_V6M = 158 -ARM_GRP_VIRTUALIZATION = 159 -ARM_GRP_ENDING = 160 +ARM_FEATURE_IsARM = 128 +ARM_FEATURE_HasV5T = 129 +ARM_FEATURE_HasV4T = 130 +ARM_FEATURE_HasVFP2 = 131 +ARM_FEATURE_HasV5TE = 132 +ARM_FEATURE_HasV6T2 = 133 +ARM_FEATURE_HasMVEInt = 134 +ARM_FEATURE_HasNEON = 135 +ARM_FEATURE_HasFPRegs64 = 136 +ARM_FEATURE_HasFPRegs = 137 +ARM_FEATURE_IsThumb2 = 138 +ARM_FEATURE_HasV8_1MMainline = 139 +ARM_FEATURE_HasLOB = 140 +ARM_FEATURE_IsThumb = 141 +ARM_FEATURE_HasV8MBaseline = 142 +ARM_FEATURE_Has8MSecExt = 143 +ARM_FEATURE_HasV8 = 144 +ARM_FEATURE_HasAES = 145 +ARM_FEATURE_HasBF16 = 146 +ARM_FEATURE_HasCDE = 147 +ARM_FEATURE_PreV8 = 148 +ARM_FEATURE_HasV6K = 149 +ARM_FEATURE_HasCRC = 150 +ARM_FEATURE_HasV7 = 151 +ARM_FEATURE_HasDB = 152 +ARM_FEATURE_HasVirtualization = 153 +ARM_FEATURE_HasVFP3 = 154 +ARM_FEATURE_HasDPVFP = 155 +ARM_FEATURE_HasFullFP16 = 156 +ARM_FEATURE_HasV6 = 157 +ARM_FEATURE_HasAcquireRelease = 158 +ARM_FEATURE_HasV7Clrex = 159 +ARM_FEATURE_HasMVEFloat = 160 +ARM_FEATURE_HasFPRegsV8_1M = 161 +ARM_FEATURE_HasMP = 162 +ARM_FEATURE_HasSB = 163 +ARM_FEATURE_HasDivideInARM = 164 +ARM_FEATURE_HasV8_1a = 165 +ARM_FEATURE_HasSHA2 = 166 +ARM_FEATURE_HasTrustZone = 167 +ARM_FEATURE_UseNaClTrap = 168 +ARM_FEATURE_HasV8_4a = 169 +ARM_FEATURE_HasV8_3a = 170 +ARM_FEATURE_HasFPARMv8 = 171 +ARM_FEATURE_HasFP16 = 172 +ARM_FEATURE_HasVFP4 = 173 +ARM_FEATURE_HasFP16FML = 174 +ARM_FEATURE_HasFPRegs16 = 175 +ARM_FEATURE_HasV8MMainline = 176 +ARM_FEATURE_HasDotProd = 177 +ARM_FEATURE_HasMatMulInt8 = 178 +ARM_FEATURE_IsMClass = 179 +ARM_FEATURE_HasPACBTI = 180 +ARM_FEATURE_IsNotMClass = 181 +ARM_FEATURE_HasDSP = 182 +ARM_FEATURE_HasDivideInThumb = 183 +ARM_FEATURE_HasV6M = 184 +ARM_GRP_ENDING = 185 diff --git a/bindings/python/capstone/bpf_const.py b/bindings/python/capstone/bpf_const.py index 6b89081e21..671eca81bd 100644 --- a/bindings/python/capstone/bpf_const.py +++ b/bindings/python/capstone/bpf_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [bpf_const.py] BPF_OP_INVALID = 0 diff --git a/bindings/python/capstone/evm_const.py b/bindings/python/capstone/evm_const.py index 5013b0f657..448f229ee7 100644 --- a/bindings/python/capstone/evm_const.py +++ b/bindings/python/capstone/evm_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.py] EVM_INS_STOP = 0 diff --git a/bindings/python/capstone/m680x_const.py b/bindings/python/capstone/m680x_const.py index 6c68b241c2..17f34b2be4 100644 --- a/bindings/python/capstone/m680x_const.py +++ b/bindings/python/capstone/m680x_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m680x_const.py] M680X_OPERAND_COUNT = 9 diff --git a/bindings/python/capstone/m68k_const.py b/bindings/python/capstone/m68k_const.py index 90755e3d29..d893da0cc1 100644 --- a/bindings/python/capstone/m68k_const.py +++ b/bindings/python/capstone/m68k_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py] M68K_OPERAND_COUNT = 4 diff --git a/bindings/python/capstone/mips_const.py b/bindings/python/capstone/mips_const.py index b6c5886bb2..536f95d854 100644 --- a/bindings/python/capstone/mips_const.py +++ b/bindings/python/capstone/mips_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py] MIPS_OP_INVALID = 0 diff --git a/bindings/python/capstone/mos65xx_const.py b/bindings/python/capstone/mos65xx_const.py index 7c3b803d47..d9e0546a22 100644 --- a/bindings/python/capstone/mos65xx_const.py +++ b/bindings/python/capstone/mos65xx_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mos65xx_const.py] MOS65XX_REG_INVALID = 0 diff --git a/bindings/python/capstone/ppc_const.py b/bindings/python/capstone/ppc_const.py index a8cd49d581..e1d8313a73 100644 --- a/bindings/python/capstone/ppc_const.py +++ b/bindings/python/capstone/ppc_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.py] PPC_BC_INVALID = 0 diff --git a/bindings/python/capstone/riscv_const.py b/bindings/python/capstone/riscv_const.py index 2b3c50dfd1..460527269b 100644 --- a/bindings/python/capstone/riscv_const.py +++ b/bindings/python/capstone/riscv_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py] # Operand type for instruction's operands diff --git a/bindings/python/capstone/sh_const.py b/bindings/python/capstone/sh_const.py index 5c6cdd0cba..dacf56a25e 100644 --- a/bindings/python/capstone/sh_const.py +++ b/bindings/python/capstone/sh_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sh_const.py] SH_REG_INVALID = 0 diff --git a/bindings/python/capstone/sparc_const.py b/bindings/python/capstone/sparc_const.py index b12eabb6eb..57a8ad9a86 100644 --- a/bindings/python/capstone/sparc_const.py +++ b/bindings/python/capstone/sparc_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py] SPARC_CC_INVALID = 0 diff --git a/bindings/python/capstone/sysz_const.py b/bindings/python/capstone/sysz_const.py index d79baf8f03..c8d0829894 100644 --- a/bindings/python/capstone/sysz_const.py +++ b/bindings/python/capstone/sysz_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sysz_const.py] SYSZ_CC_INVALID = 0 diff --git a/bindings/python/capstone/tms320c64x_const.py b/bindings/python/capstone/tms320c64x_const.py index 50c7d24670..a1b11be648 100644 --- a/bindings/python/capstone/tms320c64x_const.py +++ b/bindings/python/capstone/tms320c64x_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.py] TMS320C64X_OP_INVALID = 0 diff --git a/bindings/python/capstone/tricore_const.py b/bindings/python/capstone/tricore_const.py index 258a2cdad1..a6b2411fa2 100644 --- a/bindings/python/capstone/tricore_const.py +++ b/bindings/python/capstone/tricore_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tricore_const.py] TRICORE_OP_INVALID = CS_OP_INVALID TRICORE_OP_REG = CS_OP_REG diff --git a/bindings/python/capstone/wasm_const.py b/bindings/python/capstone/wasm_const.py index 5ad810a6de..eec3e84b35 100644 --- a/bindings/python/capstone/wasm_const.py +++ b/bindings/python/capstone/wasm_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [wasm_const.py] WASM_OP_INVALID = 0 diff --git a/bindings/python/capstone/x86_const.py b/bindings/python/capstone/x86_const.py index 9b43b535b1..a9ec56aa8d 100644 --- a/bindings/python/capstone/x86_const.py +++ b/bindings/python/capstone/x86_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py] X86_REG_INVALID = 0 diff --git a/bindings/python/capstone/xcore_const.py b/bindings/python/capstone/xcore_const.py index 5cc8ebe016..73934186c8 100644 --- a/bindings/python/capstone/xcore_const.py +++ b/bindings/python/capstone/xcore_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.py] XCORE_OP_INVALID = 0 diff --git a/bindings/python/test_arm.py b/bindings/python/test_arm.py index cfcb31baff..bd0192c54b 100755 --- a/bindings/python/test_arm.py +++ b/bindings/python/test_arm.py @@ -99,8 +99,6 @@ def print_insn_detail(insn): print("\tWrite-back: Post") else: print("\tWrite-back: Pre") - if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]: - print("\tCode condition: %u" % insn.cc) if insn.cps_mode: print("\tCPSI-mode: %u" %(insn.cps_mode)) if insn.cps_flag: From d2e9d53c501ed2c040e9b7c66ba9a046f753ff31 Mon Sep 17 00:00:00 2001 From: Peace-Maker Date: Tue, 25 Jul 2023 15:20:04 +0200 Subject: [PATCH 2/2] Fix Python ARM bindings --- bindings/python/capstone/__init__.py | 23 +++++++++-- bindings/python/capstone/arm.py | 35 +++++++++++++--- bindings/python/pyx/ccapstone.pyx | 4 +- bindings/python/test_arm.py | 61 ++++++++++++++++++++++------ tests/test_arm.c | 33 ++++++++++++++- 5 files changed, 133 insertions(+), 23 deletions(-) diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index 22b26727b1..5979f7d71b 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -741,6 +741,23 @@ def groups(self): return self._raw.detail.contents.groups[:self._raw.detail.contents.groups_count] raise CsError(CS_ERR_DETAIL) + + # return whether instruction has writeback operands. + @property + def writeback(self): + if self._raw.id == 0: + raise CsError(CS_ERR_SKIPDATA) + + if self._cs._diet: + # Diet engine cannot provide @writeback. + raise CsError(CS_ERR_DIET) + + if self._cs._detail: + if hasattr(self, 'arm64_writeback'): + return self.arm64_writeback + return self._raw.detail.contents.writeback + + raise CsError(CS_ERR_DETAIL) def __gen_detail(self): if self._raw.id == 0: @@ -749,10 +766,10 @@ def __gen_detail(self): arch = self._cs.arch if arch == CS_ARCH_ARM: - (self.usermode, self.vector_size, self.vector_data, self.cps_mode, self.cps_flag, self.cc, self.update_flags, \ - self.writeback, self.post_index, self.mem_barrier, self.operands) = arm.get_arch_info(self._raw.detail.contents.arch.arm) + (self.usermode, self.vector_size, self.vector_data, self.cps_mode, self.cps_flag, self.cc, self.vcc, self.update_flags, \ + self.post_index, self.mem_barrier, self.pred_mask, self.operands) = arm.get_arch_info(self._raw.detail.contents.arch.arm) elif arch == CS_ARCH_ARM64: - (self.cc, self.update_flags, self.writeback, self.post_index, self.operands) = \ + (self.cc, self.update_flags, self.arm64_writeback, self.post_index, self.operands) = \ arm64.get_arch_info(self._raw.detail.contents.arch.arm64) elif arch == CS_ARCH_X86: (self.prefix, self.opcode, self.rex, self.addr_size, \ diff --git a/bindings/python/capstone/arm.py b/bindings/python/capstone/arm.py index 3bc2ab2fa6..32718f497c 100644 --- a/bindings/python/capstone/arm.py +++ b/bindings/python/capstone/arm.py @@ -20,10 +20,26 @@ class ArmOpShift(ctypes.Structure): ('value', ctypes.c_uint), ) +class ArmSysopReg(ctypes.Union): + _fields_ = ( + ('mclasssysreg', ctypes.c_uint), + ('bankedreg', ctypes.c_uint), + ) + +class ArmOpSysop(ctypes.Structure): + _fields_ = ( + ('reg', ArmSysopReg), + ('psr_bits', ctypes.c_uint), + ('sysm', ctypes.c_uint16), + ('msr_mask', ctypes.c_uint8), + ) + class ArmOpValue(ctypes.Union): _fields_ = ( ('reg', ctypes.c_uint), + ('sysop', ArmOpSysop), ('imm', ctypes.c_int32), + ('pred', ctypes.c_int), ('fp', ctypes.c_double), ('mem', ArmOpMem), ('setend', ctypes.c_int), @@ -40,13 +56,21 @@ class ArmOp(ctypes.Structure): ('neon_lane', ctypes.c_int8), ) + @property + def reg(self): + return self.value.reg + + @property + def sysop(self): + return self.value.sysop + @property def imm(self): return self.value.imm @property - def reg(self): - return self.value.reg + def pred(self): + return self.value.pred @property def fp(self): @@ -69,15 +93,16 @@ class CsArm(ctypes.Structure): ('cps_mode', ctypes.c_int), ('cps_flag', ctypes.c_int), ('cc', ctypes.c_uint), + ('vcc', ctypes.c_uint), ('update_flags', ctypes.c_bool), - ('writeback', ctypes.c_bool), ('post_index', ctypes.c_bool), ('mem_barrier', ctypes.c_int), + ('pred_mask', ctypes.c_uint8), ('op_count', ctypes.c_uint8), ('operands', ArmOp * 36), ) def get_arch_info(a): - return (a.usermode, a.vector_size, a.vector_data, a.cps_mode, a.cps_flag, a.cc, a.update_flags, \ - a.writeback, a.post_index, a.mem_barrier, copy_ctypes_list(a.operands[:a.op_count])) + return (a.usermode, a.vector_size, a.vector_data, a.cps_mode, a.cps_flag, a.cc, a.vcc, a.update_flags, \ + a.post_index, a.mem_barrier, a.pred_mask, copy_ctypes_list(a.operands[:a.op_count])) diff --git a/bindings/python/pyx/ccapstone.pyx b/bindings/python/pyx/ccapstone.pyx index 932752c4de..1036b67d46 100644 --- a/bindings/python/pyx/ccapstone.pyx +++ b/bindings/python/pyx/ccapstone.pyx @@ -24,10 +24,10 @@ class CsDetail(object): if arch == capstone.CS_ARCH_ARM: (self.usermode, self.vector_size, self.vector_data, self.cps_mode, self.cps_flag, \ - self.cc, self.update_flags, self.writeback, self.post_index, self.mem_barrier, self.operands) = \ + self.cc, self.vcc, self.update_flags, self.post_index, self.mem_barrier, self.pred_mask, self.operands) = \ arm.get_arch_info(detail.arch.arm) elif arch == capstone.CS_ARCH_ARM64: - (self.cc, self.update_flags, self.writeback, self.post_index, self.operands) = \ + (self.cc, self.update_flags, self.arm64_writeback, self.post_index, self.operands) = \ arm64.get_arch_info(detail.arch.arm64) elif arch == capstone.CS_ARCH_X86: (self.prefix, self.opcode, self.rex, self.addr_size, \ diff --git a/bindings/python/test_arm.py b/bindings/python/test_arm.py index bd0192c54b..8c9e69471d 100755 --- a/bindings/python/test_arm.py +++ b/bindings/python/test_arm.py @@ -39,22 +39,22 @@ def print_insn_detail(insn): for i in insn.operands: if i.type == ARM_OP_REG: print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == ARM_OP_IMM: + elif i.type == ARM_OP_IMM: print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm))) - if i.type == ARM_OP_PIMM: - print("\t\toperands[%u].type: P-IMM = %u" % (c, i.imm)) - if i.type == ARM_OP_CIMM: - print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm)) - if i.type == ARM_OP_FP: + elif i.type == ARM_OP_FP: print("\t\toperands[%u].type: FP = %f" % (c, i.fp)) - if i.type == ARM_OP_SYSREG: - print("\t\toperands[%u].type: SYSREG = %u" % (c, i.reg)) - if i.type == ARM_OP_SETEND: + elif i.type == ARM_OP_PRED: + print("\t\toperands[%u].type: PRED = %d" % (c, i.pred)) + elif i.type == ARM_OP_CIMM: + print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm)) + elif i.type == ARM_OP_PIMM: + print("\t\toperands[%u].type: P-IMM = %u" % (c, i.imm)) + elif i.type == ARM_OP_SETEND: if i.setend == ARM_SETEND_BE: print("\t\toperands[%u].type: SETEND = be" % c) else: print("\t\toperands[%u].type: SETEND = le" % c) - if i.type == ARM_OP_MEM: + elif i.type == ARM_OP_MEM: print("\t\toperands[%u].type: MEM" % c) if i.mem.base != 0: print("\t\t\toperands[%u].mem.base: REG = %s" \ @@ -71,6 +71,31 @@ def print_insn_detail(insn): if i.mem.lshift != 0: print("\t\t\toperands[%u].mem.lshift: 0x%s" \ % (c, to_x_32(i.mem.lshift))) + elif i.type == ARM_OP_SYSM: + print("\t\toperands[%u].type: SYSM = 0x%x" % (c, i.sysop.sysm)) + print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask)) + elif i.type == ARM_OP_SYSREG: + print("\t\toperands[%u].type: SYSREG = %s" % (c, insn.reg_name(i.sysop.reg.mclasssysreg))) + print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask)) + elif i.type == ARM_OP_BANKEDREG: + print("\t\toperands[%u].type: BANKEDREG = %u" % (c, i.sysop.reg.bankedreg)) + if i.sysop.msr_mask != 2 ** (ctypes.sizeof(ctypes.c_uint8) * 8) - 1: + print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask)) + elif i.type in [ARM_OP_SPSR, ARM_OP_CPSR]: + print("\t\toperands[%u].type: %sPSR = " % (c, "S" if i.type == ARM_OP_SPSR else "C"), end="") + field = i.sysop.psr_bits + if (field & ARM_FIELD_SPSR_F) > 0 or (field & ARM_FIELD_CPSR_F) > 0: + print("f", end="") + if (field & ARM_FIELD_SPSR_S) > 0 or (field & ARM_FIELD_CPSR_S) > 0: + print("s", end="") + if (field & ARM_FIELD_SPSR_X) > 0 or (field & ARM_FIELD_CPSR_X) > 0: + print("x", end="") + if (field & ARM_FIELD_SPSR_C) > 0 or (field & ARM_FIELD_CPSR_C) > 0: + print("c", end="") + print() + print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask)) + else: + print("\t\toperands[%u].type: UNKNOWN = %u" % (c, i.type)) if i.neon_lane != -1: print("\t\toperands[%u].neon_lane = %u" % (c, i.neon_lane)) @@ -83,8 +108,14 @@ def print_insn_detail(insn): print("\t\toperands[%u].access: READ | WRITE\n" % (c)) if i.shift.type != ARM_SFT_INVALID and i.shift.value: - print("\t\t\tShift: %u = %u" \ - % (i.shift.type, i.shift.value)) + if i.shift.type < ARM_SFT_ASR_REG: + # shift with constant value + print("\t\t\tShift: %u = %u" \ + % (i.shift.type, i.shift.value)) + else: + # shift with register + print("\t\t\tShift: %u = %s" \ + % (i.shift.type, insn.reg_name(i.shift.value))) if i.vector_index != -1: print("\t\t\toperands[%u].vector_index = %u" %(c, i.vector_index)) if i.subtracted: @@ -92,6 +123,10 @@ def print_insn_detail(insn): c += 1 + if not insn.cc in [ARMCC_AL, ARMCC_UNDEF]: + print("\tCode condition: %u" % insn.cc) + if insn.vcc != ARMVCC_None: + print("\tVector code condition: %u" % insn.vcc) if insn.update_flags: print("\tUpdate-flags: True") if insn.writeback: @@ -111,6 +146,8 @@ def print_insn_detail(insn): print("\tUser-mode: True") if insn.mem_barrier: print("\tMemory-barrier: %u" %(insn.mem_barrier)) + if insn.pred_mask: + print("\tPredicate Mask: 0x%x" %(insn.pred_mask)) (regs_read, regs_write) = insn.regs_access() diff --git a/tests/test_arm.c b/tests/test_arm.c index 87b1c6e555..32d2436940 100644 --- a/tests/test_arm.c +++ b/tests/test_arm.c @@ -93,9 +93,37 @@ static void print_insn_detail(csh cs_handle, cs_insn *ins) case ARM_OP_SETEND: printf("\t\toperands[%u].type: SETEND = %s\n", i, op->setend == ARM_SETEND_BE? "be" : "le"); break; + case ARM_OP_SYSM: + printf("\t\toperands[%u].type: SYSM = 0x%" PRIx16 "\n", i, op->sysop.sysm); + printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); + break; case ARM_OP_SYSREG: - printf("\t\toperands[%u].type: SYSREG = %u\n", i, op->reg); + printf("\t\toperands[%u].type: SYSREG = %s\n", i, cs_reg_name(handle, (uint32_t) op->sysop.reg.mclasssysreg)); + printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); + break; + case ARM_OP_BANKEDREG: + // FIXME: Printing the name is currenliy not supported if the encodings overlap + // with system registers. + printf("\t\toperands[%u].type: BANKEDREG = %" PRIu32 "\n", i, (uint32_t) op->sysop.reg.bankedreg); + if (op->sysop.msr_mask != UINT8_MAX) + printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); + case ARM_OP_SPSR: + case ARM_OP_CPSR: { + const char type = op->type == ARM_OP_SPSR ? 'S' : 'C'; + printf("\t\toperands[%u].type: %cPSR = ", i, type); + uint16_t field = op->sysop.psr_bits; + if ((field & ARM_FIELD_SPSR_F) || (field & ARM_FIELD_CPSR_F)) + printf("f"); + if ((field & ARM_FIELD_SPSR_S) || (field & ARM_FIELD_CPSR_S)) + printf("s"); + if ((field & ARM_FIELD_SPSR_X) || (field & ARM_FIELD_CPSR_X)) + printf("x"); + if ((field & ARM_FIELD_SPSR_C) || (field & ARM_FIELD_CPSR_C)) + printf("c"); + printf("\n"); + printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); break; + } } if (op->neon_lane != -1) { @@ -137,6 +165,9 @@ static void print_insn_detail(csh cs_handle, cs_insn *ins) if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF) printf("\tCode condition: %u\n", arm->cc); + if (arm->vcc != ARMVCC_None) + printf("\tVector code condition: %u\n", arm->vcc); + if (arm->update_flags) printf("\tUpdate-flags: True\n");