From 3347f7fa0c3b1dc96d2567267c83923f379fd3cc Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 9 Dec 2023 12:50:02 -0500 Subject: [PATCH] Remove tPOP and tPUSH as real isntructions. push and pop are techincally no real instructions but alias of stm and ldr. Also they are encoding wise the same as their Thumb2 variants. Hence, they should be removed as real instructions. --- llvm/lib/Target/ARM/ARMInstrThumb.td | 29 ------------------------- llvm/lib/Target/ARM/ARMInstrThumb2.td | 8 +++++++ llvm/lib/Target/ARM/ARMScheduleA57.td | 4 ++-- llvm/lib/Target/ARM/ARMScheduleM55.td | 2 +- llvm/lib/Target/ARM/ARMScheduleM7.td | 4 ++-- llvm/lib/Target/ARM/ARMScheduleR52.td | 5 ++--- llvm/lib/Target/ARM/ARMScheduleSwift.td | 5 ++--- 7 files changed, 17 insertions(+), 40 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 70fdb82f2c98..f00d0837e68c 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -874,27 +874,6 @@ def : InstAlias<"ldm${p} $Rn!, $regs", (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>, Requires<[IsThumb, IsThumb1Only]>; -let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1, - variadicOpsAreDefs = 1 in -def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), - IIC_iPop, - "pop${p}\t$regs", []>, - T1Misc<{1,1,0,?,?,?,?}>, Sched<[WriteLd]> { - bits<16> regs; - let Inst{8} = regs{15}; - let Inst{7-0} = regs{7-0}; -} - -let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in -def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), - IIC_iStore_m, - "push${p}\t$regs", []>, - T1Misc<{0,1,0,?,?,?,?}>, Sched<[WriteST]> { - bits<16> regs; - let Inst{8} = regs{14}; - let Inst{7-0} = regs{7-0}; -} - //===----------------------------------------------------------------------===// // Arithmetic Instructions. // @@ -1741,14 +1720,6 @@ def tLDRpci_pic : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr, pclabel:$cp), imm:$cp))]>, Requires<[IsThumb, IsThumb1Only]>; -// Pseudo-instruction for merged POP and return. -// FIXME: remove when we have a way to marking a MI with these properties. -let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, - hasExtraDefRegAllocReq = 1 in -def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), - 2, IIC_iPop_Br, [], - (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; - // Indirect branch using "mov pc, $Rm" let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 7f1328ad7fff..69d9ebb3561d 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -5104,6 +5104,14 @@ def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; +// Pseudo-instruction for merged POP and return. +// FIXME: remove when we have a way to marking a MI with these properties. +let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, + hasExtraDefRegAllocReq = 1 in +def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), + 2, IIC_iPop_Br, [], + (t2LDMIA_UPD SP SP, pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; + // STMIA/STMIA_UPD aliases w/o the optional .w suffix def : t2InstAlias<"stm${p} $Rn, $regs", (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td index 3baac6b233c4..41f8090005a0 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA57.td +++ b/llvm/lib/Target/ARM/ARMScheduleA57.td @@ -590,7 +590,7 @@ def : InstRW<[A57WriteLDM], (instregex "(t|t2|sys)?LDM(IA|DA|DB|IB)$")>; // TODO: no writeback latency defined in documentation (implemented as 1 cyc) def : InstRW<[A57WriteLDM_Upd], - (instregex "(t|t2|sys)?LDM(IA_UPD|DA_UPD|DB_UPD|IB_UPD|IA_RET)", "tPOP")>; + (instregex "(t|t2|sys)?LDM(IA_UPD|DA_UPD|DB_UPD|IB_UPD|IA_RET)")>; def : InstRW<[A57Write_5cyc_1L], (instregex "VLLDM")>; @@ -710,7 +710,7 @@ def A57WriteSTM_Upd : SchedWriteVariant<[ def : InstRW<[A57WriteSTM], (instregex "(t2|sys|t)?STM(IA|DA|DB|IB)$")>; def : InstRW<[A57WrBackOne, A57WriteSTM_Upd], - (instregex "(t2|sys|t)?STM(IA_UPD|DA_UPD|DB_UPD|IB_UPD)", "tPUSH")>; + (instregex "(t2|sys|t)?STM(IA_UPD|DA_UPD|DB_UPD|IB_UPD)")>; def : InstRW<[A57Write_5cyc_1S], (instregex "VLSTM")>; diff --git a/llvm/lib/Target/ARM/ARMScheduleM55.td b/llvm/lib/Target/ARM/ARMScheduleM55.td index f24f97b26f0a..c197fbd9a99c 100644 --- a/llvm/lib/Target/ARM/ARMScheduleM55.td +++ b/llvm/lib/Target/ARM/ARMScheduleM55.td @@ -163,7 +163,7 @@ def : InstRW<[M55WriteDX_DI], (instregex "t2SETPAN$", "tADC$", "tADDhirr$", "tAND$", "tASRri$", "tASRrr$", "tBIC$", "tBKPT$", "tCBNZ$", "tCBZ$", "tCMNz$", "tCMPhir$", "tCMPi8$", "tCMPr$", "tCPS$", "tEOR$", "tHINT$", "tHLT$", "tLSLri$", "tLSLrr$", "tLSRri$", "tLSRrr$", "tMOVSr$", - "tMUL$", "tMVN$", "tORR$", "tPICADD$", "tPOP$", "tPUSH$", "tREV$", + "tMUL$", "tMVN$", "tORR$", "tPICADD$", "tREV$", "tREV16$", "tREVSH$", "tROR$", "tRSB$", "tSBC$", "tSETEND$", "tSTMIA_UPD$", "tSTRBi$", "tSTRBr$", "tSTRHi$", "tSTRHr$", "tSTRi$", "tSTRr$", "tSTRspi$", "tSUBrr$", "tSUBspi$", "tSVC$", "tTRAP$", diff --git a/llvm/lib/Target/ARM/ARMScheduleM7.td b/llvm/lib/Target/ARM/ARMScheduleM7.td index 25bc8401ca84..04a6c0990e5e 100644 --- a/llvm/lib/Target/ARM/ARMScheduleM7.td +++ b/llvm/lib/Target/ARM/ARMScheduleM7.td @@ -244,9 +244,9 @@ def : InstRW<[WriteLd, M7SingleIssue, M7Read_ISS], def : InstRW<[WriteST, M7SingleIssue, M7Read_ISS], (instregex "(t|t2)STM(DB|IA)$")>; def : InstRW<[M7BaseUpdate, WriteLd, M7SingleIssue, M7Read_ISS], - (instregex "(t|t2)LDM(DB|IA)_UPD$", "tPOP")>; + (instregex "(t|t2)LDM(DB|IA)_UPD$")>; def : InstRW<[M7BaseUpdate, WriteST, M7SingleIssue, M7Read_ISS], - (instregex "(t|t2)STM(DB|IA)_UPD$", "tPUSH")>; + (instregex "(t|t2)STM(DB|IA)_UPD$")>; // Load/store doubles cannot be dual-issued. diff --git a/llvm/lib/Target/ARM/ARMScheduleR52.td b/llvm/lib/Target/ARM/ARMScheduleR52.td index 466acec6f76a..bf8a3d9c0590 100644 --- a/llvm/lib/Target/ARM/ARMScheduleR52.td +++ b/llvm/lib/Target/ARM/ARMScheduleR52.td @@ -482,7 +482,7 @@ def : InstRW<[R52WriteILDM, R52Read_ISS], def : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS], (instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>; def : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS], - (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>; + (instregex "LDMIA_RET", "(t|t2)LDMIA_RET")>; // Integer Store, Single Element def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_EX2], @@ -505,8 +505,7 @@ def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2], def : InstRW<[R52WriteISTM, R52Read_ISS, R52Read_EX2], (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>; def : InstRW<[R52WriteISTM, R52WriteAdr, R52Read_ISS, R52Read_EX2], - (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", - "tPUSH")>; + (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD")>; // LDRLIT pseudo instructions, they expand to LDR + PICADD def : InstRW<[R52WriteLd], diff --git a/llvm/lib/Target/ARM/ARMScheduleSwift.td b/llvm/lib/Target/ARM/ARMScheduleSwift.td index d66b3065c7b7..4cc8b4a730be 100644 --- a/llvm/lib/Target/ARM/ARMScheduleSwift.td +++ b/llvm/lib/Target/ARM/ARMScheduleSwift.td @@ -485,7 +485,7 @@ let SchedModel = SwiftModel in { (instregex /*"t2LDMIA_RET", "tLDMIA_RET", "LDMIA_RET",*/ "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>; def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle], - (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>; + (instregex "LDMIA_RET", "(t|t2)LDMIA_RET")>; // 4.2.23 Integer Store, Single Element def : InstRW<[SwiftWriteP2], (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX", @@ -534,8 +534,7 @@ let SchedModel = SwiftModel in { def : InstRW<[SwiftWriteSTM], (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>; def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteSTM], - (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", - "tPUSH")>; + (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD")>; // LDRLIT pseudo instructions, they expand to LDR + PICADD def : InstRW<[SwiftWriteP2ThreeCycle, WriteALU],