From f52fb9d633795a83b93f502bb65b92c19ba2d206 Mon Sep 17 00:00:00 2001 From: Jiakun Shuai Date: Thu, 9 May 2024 14:49:47 +0800 Subject: [PATCH 1/4] arm64: Add MIDR encoding for Phytium CPUs This patch adds the MIDR encodings for Phytium FTC3xx/6xx CPUs. Signed-off-by: Wang Yinfeng Signed-off-by: Chen Baozi Signed-off-by: Jiakun Shuai --- arch/arm64/include/asm/cputype.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 52f076afeb960..cc3042f98a689 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -61,6 +61,7 @@ #define ARM_CPU_IMP_HISI 0x48 #define ARM_CPU_IMP_APPLE 0x61 #define ARM_CPU_IMP_AMPERE 0xC0 +#define ARM_CPU_IMP_PHYTIUM 0x70 #define ARM_CPU_IMP_MICROSOFT 0x6D #define ARM_CPU_PART_AEM_V8 0xD0F @@ -138,6 +139,13 @@ #define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */ +#define PHYTIUM_CPU_PART_FTC310 0x660 +#define PHYTIUM_CPU_PART_FTC660 0x660 +#define PHYTIUM_CPU_PART_FTC661 0x661 +#define PHYTIUM_CPU_PART_FTC662 0x662 +#define PHYTIUM_CPU_PART_FTC663 0x663 +#define PHYTIUM_CPU_PART_FTC664 0x664 + #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) @@ -196,6 +204,12 @@ #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX) #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) +#define MIDR_PHYTIUM_FTC310 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC310) +#define MIDR_PHYTIUM_FTC660 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC660) +#define MIDR_PHYTIUM_FTC661 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC661) +#define MIDR_PHYTIUM_PS17064 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC662) +#define MIDR_PHYTIUM_FTC663 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC663) +#define MIDR_PHYTIUM_FTC664 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC664) #define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100) /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ From b4c22f1ddd4d229fa1ddc8cbbd430ed245847126 Mon Sep 17 00:00:00 2001 From: Chen Baozi Date: Fri, 14 Jul 2023 08:33:59 +0800 Subject: [PATCH 2/4] arm64: kpti: Add Phytium FTC3xx/6xx CPU cores to kpti safelist Since Phytium FTC3xx/6xx CPU cores are all meltdown safe, add them to kpti_safe_list[]. Signed-off-by: Chen Baozi Signed-off-by: Wang Yinfeng Signed-off-by: Jiakun Shuai --- arch/arm64/kernel/cpufeature.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 444a73c2e6385..abb8648683c18 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1686,6 +1686,12 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC660), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC661), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_PS17064), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC663), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC664), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), From e792692b7ce5130ab7ae2742e3d1cdf5796003af Mon Sep 17 00:00:00 2001 From: Chen Baozi Date: Fri, 14 Jul 2023 08:33:59 +0800 Subject: [PATCH 3/4] arm64: proton-pack: Add Phytium FTC310 CPU core to spectre-v2/v4 safelist FTC310 (LITTLE) CPUs are spectre-v2 and spectre-v4 safe, hence add them to the safe list. Signed-off-by: Chen Baozi Signed-off-by: Wang Yinfeng Signed-off-by: Jiakun Shuai --- arch/arm64/kernel/proton-pack.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c index 05f40c4e18fda..5854a5b3dcccd 100644 --- a/arch/arm64/kernel/proton-pack.c +++ b/arch/arm64/kernel/proton-pack.c @@ -160,6 +160,7 @@ static enum mitigation_state spectre_v2_get_cpu_hw_mitigation_state(void) MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), @@ -470,6 +471,7 @@ static enum mitigation_state spectre_v4_get_cpu_hw_mitigation_state(void) MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), { /* sentinel */ }, From dbe62be3cb58ba67e037154afe1077b0c01228c7 Mon Sep 17 00:00:00 2001 From: Chen Baozi Date: Fri, 14 Jul 2023 08:33:59 +0800 Subject: [PATCH 4/4] dt-bindings: arm: Document Phytium FTC series cpu Document the compatible string for the FTC series cpus found in Phytium SoCs. Signed-off-by: Chen Baozi Signed-off-by: Wang Yinfeng Signed-off-by: Jiakun Shuai --- Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 0d17cbad9778c..c699bf4f33f94 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -182,6 +182,12 @@ properties: - nvidia,tegra132-denver - nvidia,tegra186-denver - nvidia,tegra194-carmel + - phytium,ftc310 + - phytium,ftc660 + - phytium,ftc661 + - phytium,ftc662 + - phytium,ftc663 + - phytium,ftc664 - qcom,krait - qcom,kryo - qcom,kryo240