From 0f6c37080274a6166e5f1fd6207325b76aff9064 Mon Sep 17 00:00:00 2001 From: Sebastian Nickolls Date: Wed, 23 Apr 2025 16:10:25 +0000 Subject: [PATCH 1/3] Enable SVE2 instruction set detection for ARM64 --- src/coreclr/inc/clrconfigvalues.h | 1 + src/coreclr/inc/corinfoinstructionset.h | 33 +++++++++++---- src/coreclr/inc/jiteeversionguid.h | 10 ++--- src/coreclr/inc/readytoruninstructionset.h | 1 + src/coreclr/jit/compiler.cpp | 5 +++ src/coreclr/jit/hwintrinsic.cpp | 2 + src/coreclr/jit/hwintrinsicarm64.cpp | 8 ++++ src/coreclr/jit/jitconfigvalues.h | 1 + .../Runtime/ReadyToRunInstructionSet.cs | 1 + .../Runtime/ReadyToRunInstructionSetHelper.cs | 2 + .../JitInterface/CorInfoInstructionSet.cs | 42 +++++++++++++++---- .../ThunkGenerator/InstructionSetDesc.txt | 3 ++ src/coreclr/vm/codeman.cpp | 5 +++ src/native/minipal/cpufeatures.c | 17 ++++++++ src/native/minipal/cpufeatures.h | 1 + 15 files changed, 109 insertions(+), 23 deletions(-) diff --git a/src/coreclr/inc/clrconfigvalues.h b/src/coreclr/inc/clrconfigvalues.h index 8aee6fea67127e..06390fed6ca69b 100644 --- a/src/coreclr/inc/clrconfigvalues.h +++ b/src/coreclr/inc/clrconfigvalues.h @@ -725,6 +725,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha256, W("EnableArm64Sh RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc, W("EnableArm64Rcpc"), 1, "Allows Arm64 Rcpc+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc2, W("EnableArm64Rcpc2"), 1, "Allows Arm64 Rcpc2+ hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sve, W("EnableArm64Sve"), 1, "Allows Arm64 SVE hardware intrinsics to be disabled") +RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sve2, W("EnableArm64Sve2"), 1, "Allows Arm64 SVE2 hardware intrinsics to be disabled") #elif defined(TARGET_RISCV64) RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableRiscV64Zba, W("EnableRiscV64Zba"), 1, "Allows RiscV64 Zba hardware intrinsics to be disabled") RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableRiscV64Zbb, W("EnableRiscV64Zbb"), 1, "Allows RiscV64 Zbb hardware intrinsics to be disabled") diff --git a/src/coreclr/inc/corinfoinstructionset.h b/src/coreclr/inc/corinfoinstructionset.h index 31947520b27948..cc446a6571f586 100644 --- a/src/coreclr/inc/corinfoinstructionset.h +++ b/src/coreclr/inc/corinfoinstructionset.h @@ -32,15 +32,17 @@ enum CORINFO_InstructionSet InstructionSet_VectorT128=14, InstructionSet_Rcpc2=15, InstructionSet_Sve=16, - InstructionSet_ArmBase_Arm64=17, - InstructionSet_AdvSimd_Arm64=18, - InstructionSet_Aes_Arm64=19, - InstructionSet_Crc32_Arm64=20, - InstructionSet_Dp_Arm64=21, - InstructionSet_Rdm_Arm64=22, - InstructionSet_Sha1_Arm64=23, - InstructionSet_Sha256_Arm64=24, - InstructionSet_Sve_Arm64=25, + InstructionSet_Sve2=17, + InstructionSet_ArmBase_Arm64=18, + InstructionSet_AdvSimd_Arm64=19, + InstructionSet_Aes_Arm64=20, + InstructionSet_Crc32_Arm64=21, + InstructionSet_Dp_Arm64=22, + InstructionSet_Rdm_Arm64=23, + InstructionSet_Sha1_Arm64=24, + InstructionSet_Sha256_Arm64=25, + InstructionSet_Sve_Arm64=26, + InstructionSet_Sve2_Arm64=27, #endif // TARGET_ARM64 #ifdef TARGET_RISCV64 InstructionSet_RiscV64Base=1, @@ -311,6 +313,8 @@ struct CORINFO_InstructionSetFlags AddInstructionSet(InstructionSet_Sha256_Arm64); if (HasInstructionSet(InstructionSet_Sve)) AddInstructionSet(InstructionSet_Sve_Arm64); + if (HasInstructionSet(InstructionSet_Sve2)) + AddInstructionSet(InstructionSet_Sve2_Arm64); #endif // TARGET_ARM64 #ifdef TARGET_RISCV64 #endif // TARGET_RISCV64 @@ -427,6 +431,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_Sve); if (resultflags.HasInstructionSet(InstructionSet_Sve_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sve)) resultflags.RemoveInstructionSet(InstructionSet_Sve_Arm64); + if (resultflags.HasInstructionSet(InstructionSet_Sve2) && !resultflags.HasInstructionSet(InstructionSet_Sve2_Arm64)) + resultflags.RemoveInstructionSet(InstructionSet_Sve2); + if (resultflags.HasInstructionSet(InstructionSet_Sve2_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sve2)) + resultflags.RemoveInstructionSet(InstructionSet_Sve2_Arm64); if (resultflags.HasInstructionSet(InstructionSet_AdvSimd) && !resultflags.HasInstructionSet(InstructionSet_ArmBase)) resultflags.RemoveInstructionSet(InstructionSet_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet_Aes) && !resultflags.HasInstructionSet(InstructionSet_ArmBase)) @@ -449,6 +457,8 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins resultflags.RemoveInstructionSet(InstructionSet_VectorT128); if (resultflags.HasInstructionSet(InstructionSet_Sve) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd)) resultflags.RemoveInstructionSet(InstructionSet_Sve); + if (resultflags.HasInstructionSet(InstructionSet_Sve2) && !resultflags.HasInstructionSet(InstructionSet_Sve)) + resultflags.RemoveInstructionSet(InstructionSet_Sve2); #endif // TARGET_ARM64 #ifdef TARGET_RISCV64 if (resultflags.HasInstructionSet(InstructionSet_Zbb) && !resultflags.HasInstructionSet(InstructionSet_RiscV64Base)) @@ -889,6 +899,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet) return "Sve"; case InstructionSet_Sve_Arm64 : return "Sve_Arm64"; + case InstructionSet_Sve2 : + return "Sve2"; + case InstructionSet_Sve2_Arm64 : + return "Sve2_Arm64"; #endif // TARGET_ARM64 #ifdef TARGET_RISCV64 case InstructionSet_RiscV64Base : @@ -1174,6 +1188,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst case READYTORUN_INSTRUCTION_VectorT128: return InstructionSet_VectorT128; case READYTORUN_INSTRUCTION_Rcpc2: return InstructionSet_Rcpc2; case READYTORUN_INSTRUCTION_Sve: return InstructionSet_Sve; + case READYTORUN_INSTRUCTION_Sve2: return InstructionSet_Sve2; #endif // TARGET_ARM64 #ifdef TARGET_RISCV64 case READYTORUN_INSTRUCTION_RiscV64Base: return InstructionSet_RiscV64Base; diff --git a/src/coreclr/inc/jiteeversionguid.h b/src/coreclr/inc/jiteeversionguid.h index 866c77a6e9990e..d667dd5edc99cf 100644 --- a/src/coreclr/inc/jiteeversionguid.h +++ b/src/coreclr/inc/jiteeversionguid.h @@ -37,11 +37,11 @@ #include -constexpr GUID JITEEVersionIdentifier = { /* 72704ed3-9bc5-4e07-bfe9-a4e091812ba8 */ - 0x72704ed3, - 0x9bc5, - 0x4e07, - {0xbf, 0xe9, 0xa4, 0xe0, 0x91, 0x81, 0x2b, 0xa8} +constexpr GUID JITEEVersionIdentifier = { /* bce32223-312c-4a3a-853f-cbf062e3164f */ + 0xbce32223, + 0x312c, + 0x4a3a, + {0x85, 0x3f, 0xcb, 0xf0, 0x62, 0xe3, 0x16, 0x4f} }; #endif // JIT_EE_VERSIONING_GUID_H diff --git a/src/coreclr/inc/readytoruninstructionset.h b/src/coreclr/inc/readytoruninstructionset.h index 56a5f9ab99e12c..ea250df0125e47 100644 --- a/src/coreclr/inc/readytoruninstructionset.h +++ b/src/coreclr/inc/readytoruninstructionset.h @@ -66,6 +66,7 @@ enum ReadyToRunInstructionSet READYTORUN_INSTRUCTION_RiscV64Base=56, READYTORUN_INSTRUCTION_Zba=57, READYTORUN_INSTRUCTION_Zbb=58, + READYTORUN_INSTRUCTION_Sve2=59, }; diff --git a/src/coreclr/jit/compiler.cpp b/src/coreclr/jit/compiler.cpp index 1ea2e0a4c6be3d..4d735fff97200f 100644 --- a/src/coreclr/jit/compiler.cpp +++ b/src/coreclr/jit/compiler.cpp @@ -6076,6 +6076,11 @@ int Compiler::compCompile(CORINFO_MODULE_HANDLE classPtr, { instructionSetFlags.AddInstructionSet(InstructionSet_Sve); } + + if (JitConfig.EnableArm64Sve2() != 0) + { + instructionSetFlags.AddInstructionSet(InstructionSet_Sve2); + } #elif defined(TARGET_XARCH) if (info.compMatchedVM) { diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp index a00d57962d757b..f03df5ce14e759 100644 --- a/src/coreclr/jit/hwintrinsic.cpp +++ b/src/coreclr/jit/hwintrinsic.cpp @@ -857,6 +857,7 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = { { NI_Illegal, NI_Illegal }, // VectorT128 { NI_Illegal, NI_Illegal }, // Rcpc2 { FIRST_NI_Sve, LAST_NI_Sve }, + { NI_Illegal, NI_Illegal }, // Sve2 { FIRST_NI_ArmBase_Arm64, LAST_NI_ArmBase_Arm64 }, { FIRST_NI_AdvSimd_Arm64, LAST_NI_AdvSimd_Arm64 }, { NI_Illegal, NI_Illegal }, // Aes_Arm64 @@ -866,6 +867,7 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = { { NI_Illegal, NI_Illegal }, // Sha1_Arm64 { NI_Illegal, NI_Illegal }, // Sha256_Arm64 { NI_Illegal, NI_Illegal }, // Sve_Arm64 + { NI_Illegal, NI_Illegal }, // Sve2_Arm64 #else #error Unsupported platform #endif diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index a9c50c029cc22f..44525287c99b59 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -36,6 +36,8 @@ static CORINFO_InstructionSet Arm64VersionOfIsa(CORINFO_InstructionSet isa) return InstructionSet_Rdm_Arm64; case InstructionSet_Sve: return InstructionSet_Sve_Arm64; + case InstructionSet_Sve2: + return InstructionSet_Sve2_Arm64; default: return InstructionSet_NONE; } @@ -99,6 +101,10 @@ static CORINFO_InstructionSet lookupInstructionSet(const char* className) { return InstructionSet_Sha256; } + if (strcmp(className, "Sve2") == 0) + { + return InstructionSet_Sve2; + } if (strcmp(className, "Sve") == 0) { return InstructionSet_Sve; @@ -212,6 +218,8 @@ bool HWIntrinsicInfo::isFullyImplementedIsa(CORINFO_InstructionSet isa) case InstructionSet_Sha256_Arm64: case InstructionSet_Sve: case InstructionSet_Sve_Arm64: + case InstructionSet_Sve2: + case InstructionSet_Sve2_Arm64: case InstructionSet_Vector64: case InstructionSet_Vector128: return true; diff --git a/src/coreclr/jit/jitconfigvalues.h b/src/coreclr/jit/jitconfigvalues.h index 2c9231cb47eb24..00cb6a9bf11bf9 100644 --- a/src/coreclr/jit/jitconfigvalues.h +++ b/src/coreclr/jit/jitconfigvalues.h @@ -439,6 +439,7 @@ RELEASE_CONFIG_INTEGER(EnableArm64Rdm, "EnableArm64Rdm", RELEASE_CONFIG_INTEGER(EnableArm64Sha1, "EnableArm64Sha1", 1) // Allows Arm64 Sha1+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableArm64Sha256, "EnableArm64Sha256", 1) // Allows Arm64 Sha256+ hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableArm64Sve, "EnableArm64Sve", 1) // Allows Arm64 Sve+ hardware intrinsics to be disabled +RELEASE_CONFIG_INTEGER(EnableArm64Sve2, "EnableArm64Sve2", 1) // Allows Arm64 Sve2+ hardware intrinsics to be disabled #elif defined(TARGET_RISCV64) RELEASE_CONFIG_INTEGER(EnableRiscV64Zba, "EnableRiscV64Zba", 1) // Allows RiscV64 Zba hardware intrinsics to be disabled RELEASE_CONFIG_INTEGER(EnableRiscV64Zbb, "EnableRiscV64Zbb", 1) // Allows RiscV64 Zbb hardware intrinsics to be disabled diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs index 2adcd571b64bcc..a2ab0bd6d39a25 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs @@ -69,6 +69,7 @@ public enum ReadyToRunInstructionSet RiscV64Base=56, Zba=57, Zbb=58, + Sve2=59, } } diff --git a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs index 81532915c78994..36847ce414ed99 100644 --- a/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs +++ b/src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs @@ -48,6 +48,8 @@ public static class ReadyToRunInstructionSetHelper case InstructionSet.ARM64_Rcpc2: return ReadyToRunInstructionSet.Rcpc2; case InstructionSet.ARM64_Sve: return ReadyToRunInstructionSet.Sve; case InstructionSet.ARM64_Sve_Arm64: return ReadyToRunInstructionSet.Sve; + case InstructionSet.ARM64_Sve2: return ReadyToRunInstructionSet.Sve2; + case InstructionSet.ARM64_Sve2_Arm64: return ReadyToRunInstructionSet.Sve2; default: throw new Exception("Unknown instruction set"); } diff --git a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs index c245aa94d4a842..758d50e1706507 100644 --- a/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs +++ b/src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs @@ -32,6 +32,7 @@ public enum InstructionSet ARM64_VectorT128 = InstructionSet_ARM64.VectorT128, ARM64_Rcpc2 = InstructionSet_ARM64.Rcpc2, ARM64_Sve = InstructionSet_ARM64.Sve, + ARM64_Sve2 = InstructionSet_ARM64.Sve2, ARM64_ArmBase_Arm64 = InstructionSet_ARM64.ArmBase_Arm64, ARM64_AdvSimd_Arm64 = InstructionSet_ARM64.AdvSimd_Arm64, ARM64_Aes_Arm64 = InstructionSet_ARM64.Aes_Arm64, @@ -41,6 +42,7 @@ public enum InstructionSet ARM64_Sha1_Arm64 = InstructionSet_ARM64.Sha1_Arm64, ARM64_Sha256_Arm64 = InstructionSet_ARM64.Sha256_Arm64, ARM64_Sve_Arm64 = InstructionSet_ARM64.Sve_Arm64, + ARM64_Sve2_Arm64 = InstructionSet_ARM64.Sve2_Arm64, RiscV64_RiscV64Base = InstructionSet_RiscV64.RiscV64Base, RiscV64_Zba = InstructionSet_RiscV64.Zba, RiscV64_Zbb = InstructionSet_RiscV64.Zbb, @@ -213,15 +215,17 @@ public enum InstructionSet_ARM64 VectorT128 = 14, Rcpc2 = 15, Sve = 16, - ArmBase_Arm64 = 17, - AdvSimd_Arm64 = 18, - Aes_Arm64 = 19, - Crc32_Arm64 = 20, - Dp_Arm64 = 21, - Rdm_Arm64 = 22, - Sha1_Arm64 = 23, - Sha256_Arm64 = 24, - Sve_Arm64 = 25, + Sve2 = 17, + ArmBase_Arm64 = 18, + AdvSimd_Arm64 = 19, + Aes_Arm64 = 20, + Crc32_Arm64 = 21, + Dp_Arm64 = 22, + Rdm_Arm64 = 23, + Sha1_Arm64 = 24, + Sha256_Arm64 = 25, + Sve_Arm64 = 26, + Sve2_Arm64 = 27, } public enum InstructionSet_RiscV64 @@ -587,6 +591,10 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64)) resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve2)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve2_Arm64); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve2_Arm64)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve2); if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) resultflags.AddInstructionSet(InstructionSet.ARM64_ArmBase); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Aes)) @@ -609,6 +617,8 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve)) resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve2)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); break; case TargetArchitecture.RiscV64: @@ -1027,6 +1037,8 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256); if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64)) resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve2_Arm64)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve2); if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase)) resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd); if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase)) @@ -1049,6 +1061,8 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe resultflags.AddInstructionSet(InstructionSet.ARM64_VectorT128); if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd)) resultflags.AddInstructionSet(InstructionSet.ARM64_Sve); + if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve)) + resultflags.AddInstructionSet(InstructionSet.ARM64_Sve2); break; case TargetArchitecture.RiscV64: @@ -1443,6 +1457,7 @@ public static IEnumerable ArchitectureToValidInstructionSets yield return new InstructionSetInfo("vectort128", "VectorT128", InstructionSet.ARM64_VectorT128, true); yield return new InstructionSetInfo("rcpc2", "", InstructionSet.ARM64_Rcpc2, true); yield return new InstructionSetInfo("sve", "Sve", InstructionSet.ARM64_Sve, true); + yield return new InstructionSetInfo("sve2", "Sve2", InstructionSet.ARM64_Sve2, true); break; case TargetArchitecture.RiscV64: @@ -1575,6 +1590,8 @@ public void Set64BitInstructionSetVariants(TargetArchitecture architecture) AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); if (HasInstructionSet(InstructionSet.ARM64_Sve)) AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); + if (HasInstructionSet(InstructionSet.ARM64_Sve2)) + AddInstructionSet(InstructionSet.ARM64_Sve2_Arm64); break; case TargetArchitecture.RiscV64: @@ -1659,6 +1676,7 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc AddInstructionSet(InstructionSet.ARM64_Sha1_Arm64); AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64); AddInstructionSet(InstructionSet.ARM64_Sve_Arm64); + AddInstructionSet(InstructionSet.ARM64_Sve2_Arm64); break; case TargetArchitecture.RiscV64: @@ -1832,6 +1850,12 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite else { return InstructionSet.ARM64_Sve; } + case "Sve2": + if (nestedTypeName == "Arm64") + { return InstructionSet.ARM64_Sve2_Arm64; } + else + { return InstructionSet.ARM64_Sve2; } + } break; diff --git a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt index 278ce92bf74464..53ee7c3f0e8c3e 100644 --- a/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt +++ b/src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt @@ -216,6 +216,7 @@ instructionset ,ARM64 , ,Rcpc ,26 ,Rcpc instructionset ,ARM64 ,VectorT128 , ,39 ,VectorT128 ,vectort128 instructionset ,ARM64 , ,Rcpc2 ,42 ,Rcpc2 ,rcpc2 instructionset ,ARM64 ,Sve , ,43 ,Sve ,sve +instructionset ,ARM64 ,Sve2 , ,59 ,Sve2 ,sve2 instructionset64bit,ARM64 ,ArmBase instructionset64bit,ARM64 ,AdvSimd @@ -226,6 +227,7 @@ instructionset64bit,ARM64 ,Rdm instructionset64bit,ARM64 ,Sha1 instructionset64bit,ARM64 ,Sha256 instructionset64bit,ARM64 ,Sve +instructionset64bit,ARM64 ,Sve2 vectorinstructionset,ARM64,Vector64 vectorinstructionset,ARM64,Vector128 @@ -241,6 +243,7 @@ implication ,ARM64 ,Vector64 ,AdvSimd implication ,ARM64 ,Vector128 ,AdvSimd implication ,ARM64 ,VectorT128 ,AdvSimd implication ,ARM64 ,Sve ,AdvSimd +implication ,ARM64 ,Sve2 ,Sve ; Definition of Riscv64 instruction sets definearch ,RiscV64 ,64Bit ,RiscV64, RiscV64 diff --git a/src/coreclr/vm/codeman.cpp b/src/coreclr/vm/codeman.cpp index c1c1bfe60441c6..8a1fa174818dfc 100644 --- a/src/coreclr/vm/codeman.cpp +++ b/src/coreclr/vm/codeman.cpp @@ -1533,6 +1533,11 @@ void EEJitManager::SetCpuInfo() // if ((maxVectorTLength >= sveLengthFromOS) || (maxVectorTBitWidth == 0)) { CPUCompileFlags.Set(InstructionSet_Sve); + + if (((cpuFeatures & ARM64IntrinsicConstants_Sve2) != 0) && CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableArm64Sve2)) + { + CPUCompileFlags.Set(InstructionSet_Sve2); + } } } diff --git a/src/native/minipal/cpufeatures.c b/src/native/minipal/cpufeatures.c index 7a233b31eda84d..50c661bcc1422c 100644 --- a/src/native/minipal/cpufeatures.c +++ b/src/native/minipal/cpufeatures.c @@ -19,6 +19,10 @@ #define PF_ARM_SVE_INSTRUCTIONS_AVAILABLE (46) #endif +#ifndef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE (47) // ref SDK 10.0.26100.0 +#endif + #else // HOST_WINDOWS #include "minipalconfig.h" @@ -44,6 +48,9 @@ #ifndef HWCAP_SVE #define HWCAP_SVE (1 << 22) #endif +#ifndef HWCAP2_SVE2 +#define HWCAP2_SVE2 (1 << 1) +#endif #endif @@ -444,6 +451,11 @@ int minipal_getcpufeatures(void) if (hwCap & HWCAP_SVE) result |= ARM64IntrinsicConstants_Sve; + unsigned long hwCap2 = getauxval(AT_HWCAP2); + + if (hwCap2 & HWCAP2_SVE2) + result |= ARM64IntrinsicConstants_Sve2; + #else // !HAVE_AUXV_HWCAP_H #if HAVE_SYSCTLBYNAME @@ -534,6 +546,11 @@ int minipal_getcpufeatures(void) result |= ARM64IntrinsicConstants_Sve; } + if (IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE)) + { + result |= ARM64IntrinsicConstants_Sve2; + } + #endif // HOST_WINDOWS #endif // HOST_ARM64 diff --git a/src/native/minipal/cpufeatures.h b/src/native/minipal/cpufeatures.h index b88043d4cdb92a..9def54fa001063 100644 --- a/src/native/minipal/cpufeatures.h +++ b/src/native/minipal/cpufeatures.h @@ -52,6 +52,7 @@ enum ARM64IntrinsicConstants ARM64IntrinsicConstants_Rcpc = 0x0100, ARM64IntrinsicConstants_Rcpc2 = 0x0200, ARM64IntrinsicConstants_Sve = 0x0400, + ARM64IntrinsicConstants_Sve2 = 0x0800, }; #include From 596eae918a16a0abdaa1245f759b262b1887156f Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Thu, 8 May 2025 08:56:01 -0700 Subject: [PATCH 2/3] updated the guid --- src/coreclr/inc/jiteeversionguid.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/coreclr/inc/jiteeversionguid.h b/src/coreclr/inc/jiteeversionguid.h index c31eda46943e08..db3480acadc98a 100644 --- a/src/coreclr/inc/jiteeversionguid.h +++ b/src/coreclr/inc/jiteeversionguid.h @@ -37,11 +37,11 @@ #include -constexpr GUID JITEEVersionIdentifier = { /* 13de8232-0528-42ca-b2b8-4fc592a9adb9 */ - 0x13de8232, - 0x0528, - 0x42ca, - {0xb2, 0xb8, 0x4f, 0xc5, 0x92, 0xa9, 0xad, 0xb9} -}; +constexpr GUID JITEEVersionIdentifier = { /* 63dcb8b8-1f9d-43d8-bb09-bf5d8bf85ad4 */ + 0x63dcb8b8, + 0x1f9d, + 0x43d8, + {0xbb, 0x09, 0xbf, 0x5d, 0x8b, 0xf8, 0x5a, 0xd4} + }; #endif // JIT_EE_VERSIONING_GUID_H From 46bb7ceafb79404c452c1399b98bb0df9f14ecc6 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Thu, 8 May 2025 08:56:34 -0700 Subject: [PATCH 3/3] remove the comment --- src/native/minipal/cpufeatures.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/native/minipal/cpufeatures.c b/src/native/minipal/cpufeatures.c index 50c661bcc1422c..8d5874922a7bca 100644 --- a/src/native/minipal/cpufeatures.c +++ b/src/native/minipal/cpufeatures.c @@ -20,7 +20,7 @@ #endif #ifndef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE -#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE (47) // ref SDK 10.0.26100.0 +#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE (47) #endif #else // HOST_WINDOWS