diff --git a/src/coreclr/jit/emitarm64sve.cpp b/src/coreclr/jit/emitarm64sve.cpp
index 54c51eb93eca13..489a04ddf3d726 100644
--- a/src/coreclr/jit/emitarm64sve.cpp
+++ b/src/coreclr/jit/emitarm64sve.cpp
@@ -2666,8 +2666,6 @@ void emitter::emitInsSve_R_R_I(instruction     ins,
             assert(insOptsNone(opt));
             assert(isScalableVectorSize(size));
             assert(isGeneralRegister(reg2)); // nnnnn
-            assert(isValidSimm<9>(imm));     // iii
-                                             // iiiiii
             assert(insScalableOptsNone(sopt));
 
             // imm is the number of bytes to offset by. The instruction requires a multiple of the
@@ -2686,6 +2684,8 @@ void emitter::emitInsSve_R_R_I(instruction     ins,
                 imm  = 0;
             }
 
+            assert(isValidSimm<9>(imm));
+
             if (isVectorRegister(reg1))
             {
                 fmt = IF_SVE_IE_2A;
@@ -2701,8 +2701,6 @@ void emitter::emitInsSve_R_R_I(instruction     ins,
             assert(insOptsNone(opt));
             assert(isScalableVectorSize(size));
             assert(isGeneralRegister(reg2)); // nnnnn
-            assert(isValidSimm<9>(imm));     // iii
-                                             // iiiiii
             assert(insScalableOptsNone(sopt));
 
             // imm is the number of bytes to offset by. The instruction requires a multiple of the
@@ -2721,6 +2719,8 @@ void emitter::emitInsSve_R_R_I(instruction     ins,
                 imm  = 0;
             }
 
+            assert(isValidSimm<9>(imm));
+
             if (isVectorRegister(reg1))
             {
                 fmt = IF_SVE_JH_2A;