diff --git a/src/coreclr/jit/codegenriscv64.cpp b/src/coreclr/jit/codegenriscv64.cpp index e88bee5a01c991..fa450f08244ac8 100644 --- a/src/coreclr/jit/codegenriscv64.cpp +++ b/src/coreclr/jit/codegenriscv64.cpp @@ -2204,7 +2204,6 @@ void CodeGen::genCodeForCpObj(GenTreeBlk* cpObjNode) if (cpObjNode->IsVolatile()) { // issue a INS_BARRIER_RMB after a volatile CpObj operation - // TODO-RISCV64: there is only BARRIER_FULL for RISCV64. instGen_MemoryBarrier(BARRIER_FULL); } @@ -6257,7 +6256,7 @@ void CodeGen::genJumpToThrowHlpBlk_la( // instGen_MemoryBarrier: Emit a MemoryBarrier instruction // // Arguments: -// barrierKind - kind of barrier to emit (Only supports the Full now!! This depends on the CPU). +// barrierKind - kind of barrier to emit // // Notes: // All MemoryBarriers instructions can be removed by DOTNET_JitNoMemoryBarriers=1 @@ -6271,8 +6270,21 @@ void CodeGen::instGen_MemoryBarrier(BarrierKind barrierKind) } #endif // DEBUG - // TODO-RISCV64: Use the exact barrier type depending on the CPU. - GetEmitter()->emitIns_I(INS_fence, EA_4BYTE, INS_BARRIER_FULL); + insBarrier barrier; + switch (barrierKind) + { + case BARRIER_LOAD_ONLY: + barrier = INS_BARRIER_LOAD_ONLY; + break; + case BARRIER_STORE_ONLY: + barrier = INS_BARRIER_STORE_ONLY; + break; + default: + barrier = INS_BARRIER_FULL; + break; + } + + GetEmitter()->emitIns_I(INS_fence, EA_4BYTE, barrier); } /*----------------------------------------------------------------------------- diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h index 82c60d9ac5995b..1edad6b3de6c25 100644 --- a/src/coreclr/jit/instr.h +++ b/src/coreclr/jit/instr.h @@ -566,7 +566,9 @@ enum insOpts : unsigned enum insBarrier : unsigned { - INS_BARRIER_FULL = 0x33, + INS_BARRIER_FULL = 0x33, // fence rw, rw + INS_BARRIER_LOAD_ONLY = 0x23, // fence r, rw + INS_BARRIER_STORE_ONLY = 0x31, // fence rw, w }; #elif defined(TARGET_WASM) enum insOpts : unsigned