From 3702032cfae19daca95323379ee46f0c171226f3 Mon Sep 17 00:00:00 2001 From: Tanner Gooding Date: Sat, 18 Apr 2026 14:16:38 -0700 Subject: [PATCH] Fix the encoding of vcvtps2ph --- src/coreclr/jit/codegenxarch.cpp | 2 ++ src/coreclr/jit/emitxarch.cpp | 2 +- src/coreclr/jit/instrsxarch.h | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp index 4afff4ae217058..e34bcc2178b953 100644 --- a/src/coreclr/jit/codegenxarch.cpp +++ b/src/coreclr/jit/codegenxarch.cpp @@ -5605,6 +5605,8 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree) case NI_X86Base_Extract: case NI_X86Base_X64_Extract: case NI_AVX_ExtractVector128: + case NI_AVX2_ConvertToVector128Half: + case NI_AVX2_ConvertToVector256Half: case NI_AVX2_ExtractVector128: case NI_AVX512_ExtractVector128: case NI_AVX512_ExtractVector256: diff --git a/src/coreclr/jit/emitxarch.cpp b/src/coreclr/jit/emitxarch.cpp index ecc7d78a340af1..30882ef49ca779 100644 --- a/src/coreclr/jit/emitxarch.cpp +++ b/src/coreclr/jit/emitxarch.cpp @@ -19777,7 +19777,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp) { assert((ins == INS_vextractf32x4) || (ins == INS_vextractf32x8) || (ins == INS_vextractf64x2) || (ins == INS_vextractf64x4) || (ins == INS_vextracti32x4) || (ins == INS_vextracti32x8) || - (ins == INS_vextracti64x2) || (ins == INS_vextracti64x4)); + (ins == INS_vextracti64x2) || (ins == INS_vextracti64x4) || (ins == INS_vcvtps2ph)); assert(UseSimdEncoding()); emitGetInsDcmCns(id, &cnsVal); // we do not need VEX.vvvv to encode the register operand diff --git a/src/coreclr/jit/instrsxarch.h b/src/coreclr/jit/instrsxarch.h index ce5f1f63320b67..bcf977ea590409 100644 --- a/src/coreclr/jit/instrsxarch.h +++ b/src/coreclr/jit/instrsxarch.h @@ -515,7 +515,7 @@ INST3(vzeroupper, "vzeroupper", IUM_WR, 0xC577F8, BAD_CODE, // Instructions for AVX2, BMI1, BMI2, F16C, LZCNT, MOVBE INST3(vbroadcasti32x4, "vbroadcasti128", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x5A), ILLEGAL, ILLEGAL, INS_TT_TUPLE4, Input_32Bit | KMask_Base4 | REX_W0 | Encoding_VEX | Encoding_EVEX | INS_FLAGS_HasPseudoName) // Broadcast packed integer values read from memory to entire ymm register INST3(vcvtph2ps, "vcvtph2ps", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x13), ILLEGAL, ILLEGAL, INS_TT_HALF_MEM, Input_16Bit | KMask_Base4 | REX_W0 | Encoding_VEX | Encoding_EVEX) // Convert Packed FP16 Values to Single Precision Floating-Point Values -INST3(vcvtps2ph, "vcvtps2ph", IUM_WR, BAD_CODE, BAD_CODE, SSE3A(0x1D), ILLEGAL, ILLEGAL, INS_TT_HALF_MEM, Input_32Bit | KMask_Base4 | REX_W0 | Encoding_VEX | Encoding_EVEX) // Convert Single Precision FP Value to 16-bit FP Value +INST3(vcvtps2ph, "vcvtps2ph", IUM_WR, SSE3A(0x1D), BAD_CODE, BAD_CODE, ILLEGAL, ILLEGAL, INS_TT_HALF_MEM, Input_32Bit | KMask_Base4 | REX_W0 | Encoding_VEX | Encoding_EVEX) // Convert Single Precision FP Value to 16-bit FP Value INST3(vextracti32x4, "vextracti128", IUM_WR, SSE3A(0x39), BAD_CODE, BAD_CODE, 3C, 1C, INS_TT_TUPLE4, Input_32Bit | KMask_Base4 | REX_W0 | Encoding_VEX | Encoding_EVEX | INS_FLAGS_HasPseudoName) // Extract 128-bit packed integer values INST3(vgatherdpd, "vgatherdpd", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x92), ILLEGAL, ILLEGAL, INS_TT_TUPLE1_SCALAR, Input_64Bit | REX_W1 | Encoding_VEX | INS_Flags_IsDstDstSrcAVXInstruction) // Gather Packed DP FP Values Using Signed Dword Indices INST3(vgatherdps, "vgatherdps", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x92), ILLEGAL, ILLEGAL, INS_TT_TUPLE1_SCALAR, Input_32Bit | REX_W0 | Encoding_VEX | INS_Flags_IsDstDstSrcAVXInstruction) // Gather Packed SP FP values Using Signed Dword Indices