diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp
index 9baa4f25bdf108..d70f8c3ecbff52 100644
--- a/src/coreclr/jit/lsra.cpp
+++ b/src/coreclr/jit/lsra.cpp
@@ -984,6 +984,22 @@ LinearScan::LinearScan(Compiler* theCompiler)
     }
 #endif // TARGET_AMD64 || TARGET_ARM64
 
+#ifdef TARGET_AMD64
+    // On x64 the OSR method does not restore float/mask registers from the
+    // tier0 frame, so disallow using those in the tier0 method.
+    if (m_compiler->doesMethodHavePatchpoints() || m_compiler->doesMethodHavePartialCompilationPatchpoints())
+    {
+#if defined(UNIX_AMD64_ABI)
+        availableFloatRegs &= ~RBM_FLT_CALLEE_SAVED;
+        availableDoubleRegs &= ~RBM_FLT_CALLEE_SAVED;
+#else
+        availableFloatRegs &= ~RBM_FLT_CALLEE_SAVED.GetFloatRegSet();
+        availableDoubleRegs &= ~RBM_FLT_CALLEE_SAVED.GetFloatRegSet();
+#endif // UNIX_AMD64_ABI
+        availableMaskRegs &= ~RBM_MSK_CALLEE_SAVED;
+    }
+#endif
+
 #if defined(TARGET_AMD64)
     if (evexIsSupported)
     {