From ab40954b8a660eaa9687a1c23a28c11fa446cb51 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 15 Dec 2021 18:17:58 -0800 Subject: [PATCH] setInternalRegsDelayFree only for candidate lclVars --- src/coreclr/jit/lsrabuild.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/lsrabuild.cpp b/src/coreclr/jit/lsrabuild.cpp index ab70d0b78859f7..e9f0056f5c68ea 100644 --- a/src/coreclr/jit/lsrabuild.cpp +++ b/src/coreclr/jit/lsrabuild.cpp @@ -3456,8 +3456,12 @@ int LinearScan::BuildStoreLoc(GenTreeLclVarCommon* storeLoc) { // Need an additional register to create a SIMD8 from EAX/EDX without SSE4.1. buildInternalFloatRegisterDefForNode(storeLoc, allSIMDRegs()); - // This internal register must be different from the target register. - setInternalRegsDelayFree = true; + + if (isCandidateVar(varDsc)) + { + // This internal register must be different from the target register. + setInternalRegsDelayFree = true; + } } } #endif // FEATURE_SIMD && TARGET_X86