From 2909b2558a825823c42afa606a5cfb1e0f6cea4e Mon Sep 17 00:00:00 2001 From: qiaopengcheng Date: Thu, 20 Apr 2023 11:21:58 +0800 Subject: [PATCH 1/2] [LoongArch64] fix the arg regs' loop depending. --- src/coreclr/jit/codegenloongarch64.cpp | 124 +++++++++++++------------ 1 file changed, 66 insertions(+), 58 deletions(-) diff --git a/src/coreclr/jit/codegenloongarch64.cpp b/src/coreclr/jit/codegenloongarch64.cpp index 87f16974bcfcc6..f31b89190f2904 100644 --- a/src/coreclr/jit/codegenloongarch64.cpp +++ b/src/coreclr/jit/codegenloongarch64.cpp @@ -8575,7 +8575,7 @@ void CodeGen::genFnPrologCalleeRegArgs() unsigned varNum; unsigned regArgMaskIsInt = 0; - unsigned regArgNum = 0; + int regArgNum = 0; // Process any circular dependencies unsigned regArg[MAX_REG_ARG * 2] = {0}; unsigned regArgInit[MAX_REG_ARG * 2] = {0}; @@ -8925,75 +8925,83 @@ void CodeGen::genFnPrologCalleeRegArgs() assert(genIsValidIntReg((regNumber)regArg[i])); assert(genIsValidIntReg((regNumber)regArgInit[i])); - regArgNum--; - regArgMaskLive &= ~genRegMask((regNumber)regArg[i]); - if ((regArgMaskIsInt & (1 << regArg[i])) != 0) + unsigned tmp_regs[MAX_REG_ARG] = {0}; + + unsigned tmpArg = regArg[i]; + unsigned nextReg = regArgInit[i] - REG_ARG_FIRST; + + assert(tmpArg <= REG_ARG_LAST); + assert(nextReg < MAX_REG_ARG); + assert(nextReg != i); + + regArg[i] = 0; + int count = 0; + + while (regArg[nextReg] != 0) { - ins = INS_slli_w; + tmp_regs[count] = nextReg; + nextReg = regArgInit[nextReg] - REG_ARG_FIRST; + assert(nextReg < MAX_REG_ARG); + + for (int count2 = 0; count2 < count; count2++) + { + if (nextReg == tmp_regs[count2]) + { + NYI_LOONGARCH64("-----------CodeGen::genFnPrologCalleeRegArgs() error: intRegs!"); + } + } + + count++; + } + + if (nextReg == i) + { + GetEmitter()->emitIns_R_R_I(INS_ori, EA_PTRSIZE, REG_R21, (regNumber)tmpArg, 0); + regArgMaskLive &= ~genRegMask((regNumber)tmpArg); + assert(count > 0); + } + else if (count == 0) + { + tmp_regs[0] = i; + regArg[i] = tmpArg; } else { - ins = INS_ori; + count--; } - if (regArgNum == 0) + do { - GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, (regNumber)regArgInit[i], (regNumber)regArg[i], 0); - break; - } - else if (regArgInit[i] > regArg[i]) + tmpArg = tmp_regs[count]; + + instruction ins = (regArgMaskIsInt & (1 << regArg[tmpArg])) != 0 ? INS_slli_w : INS_ori; + GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, (regNumber)regArgInit[tmpArg], + (regNumber)regArg[tmpArg], 0); + + regArgMaskLive &= ~genRegMask((regNumber)regArg[tmpArg]); + regArg[tmpArg] = 0; + count--; + regArgNum--; + assert(regArgNum >= 0); + } while (count >= 0); + + if (nextReg == i) { - GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, (regNumber)regArgInit[i], (regNumber)regArg[i], 0); + instruction ins = (regArgMaskIsInt & (1 << regArg[i])) != 0 ? INS_slli_w : INS_ori; + GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, (regNumber)regArgInit[i], REG_R21, 0); + regArgNum--; + assert(regArgNum >= 0); } - else + else if (tmp_regs[0] != i) { - assert(i > 0); - assert(regArgNum > 0); + instruction ins = (regArgMaskIsInt & (1 << (i + REG_ARG_FIRST))) != 0 ? INS_slli_w : INS_ori; + GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, (regNumber)regArgInit[i], + (regNumber)(i + REG_ARG_FIRST), 0); - int j = regArgInit[i] - REG_ARG_FIRST; - assert((j >= 0) && (j < MAX_REG_ARG)); - if (regArg[j] == 0) - { - GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, (regNumber)regArgInit[i], (regNumber)regArg[i], 0); - } - else - { - int k = regArgInit[j] - REG_ARG_FIRST; - assert((k >= 0) && (k < MAX_REG_ARG)); - instruction ins2 = (regArgMaskIsInt & (1 << regArg[j])) != 0 ? INS_slli_w : INS_ori; - if ((regArg[k] == 0) || (k > i)) - { - GetEmitter()->emitIns_R_R_I(ins2, EA_PTRSIZE, (regNumber)regArgInit[j], - (regNumber)regArg[j], 0); - GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, (regNumber)regArgInit[i], (regNumber)regArg[i], - 0); - regArgNum--; - regArgMaskLive &= ~genRegMask((regNumber)regArg[j]); - if (regArgNum == 0) - { - break; - } - } - else if (k == i) - { - GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, REG_R21, (regNumber)regArg[i], 0); - GetEmitter()->emitIns_R_R_I(ins2, EA_PTRSIZE, (regNumber)regArgInit[j], - (regNumber)regArg[j], 0); - GetEmitter()->emitIns_R_R_I(INS_ori, EA_PTRSIZE, (regNumber)regArgInit[i], REG_R21, 0); - regArgNum--; - regArgMaskLive &= ~genRegMask((regNumber)regArg[j]); - regArg[j] = 0; - if (regArgNum == 0) - { - break; - } - } - else - { - NYI_LOONGARCH64("-----------CodeGen::genFnPrologCalleeRegArgs() error!--"); - } - } + regArgMaskLive &= ~genRegMask((regNumber)(i + REG_ARG_FIRST)); + regArgNum--; } + assert(regArgNum >= 0); } } From 8f69ef3f728c5cca2ecc65eb1185e5c69315eef9 Mon Sep 17 00:00:00 2001 From: qiaopengcheng Date: Fri, 21 Apr 2023 17:33:11 +0800 Subject: [PATCH 2/2] amend the value naming by CR. --- src/coreclr/jit/codegenloongarch64.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/coreclr/jit/codegenloongarch64.cpp b/src/coreclr/jit/codegenloongarch64.cpp index f31b89190f2904..7a892d31bb577f 100644 --- a/src/coreclr/jit/codegenloongarch64.cpp +++ b/src/coreclr/jit/codegenloongarch64.cpp @@ -8925,7 +8925,7 @@ void CodeGen::genFnPrologCalleeRegArgs() assert(genIsValidIntReg((regNumber)regArg[i])); assert(genIsValidIntReg((regNumber)regArgInit[i])); - unsigned tmp_regs[MAX_REG_ARG] = {0}; + unsigned tmpRegs[MAX_REG_ARG] = {0}; unsigned tmpArg = regArg[i]; unsigned nextReg = regArgInit[i] - REG_ARG_FIRST; @@ -8939,13 +8939,13 @@ void CodeGen::genFnPrologCalleeRegArgs() while (regArg[nextReg] != 0) { - tmp_regs[count] = nextReg; - nextReg = regArgInit[nextReg] - REG_ARG_FIRST; + tmpRegs[count] = nextReg; + nextReg = regArgInit[nextReg] - REG_ARG_FIRST; assert(nextReg < MAX_REG_ARG); for (int count2 = 0; count2 < count; count2++) { - if (nextReg == tmp_regs[count2]) + if (nextReg == tmpRegs[count2]) { NYI_LOONGARCH64("-----------CodeGen::genFnPrologCalleeRegArgs() error: intRegs!"); } @@ -8962,8 +8962,8 @@ void CodeGen::genFnPrologCalleeRegArgs() } else if (count == 0) { - tmp_regs[0] = i; - regArg[i] = tmpArg; + tmpRegs[0] = i; + regArg[i] = tmpArg; } else { @@ -8972,7 +8972,7 @@ void CodeGen::genFnPrologCalleeRegArgs() do { - tmpArg = tmp_regs[count]; + tmpArg = tmpRegs[count]; instruction ins = (regArgMaskIsInt & (1 << regArg[tmpArg])) != 0 ? INS_slli_w : INS_ori; GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, (regNumber)regArgInit[tmpArg], @@ -8992,7 +8992,7 @@ void CodeGen::genFnPrologCalleeRegArgs() regArgNum--; assert(regArgNum >= 0); } - else if (tmp_regs[0] != i) + else if (tmpRegs[0] != i) { instruction ins = (regArgMaskIsInt & (1 << (i + REG_ARG_FIRST))) != 0 ? INS_slli_w : INS_ori; GetEmitter()->emitIns_R_R_I(ins, EA_PTRSIZE, (regNumber)regArgInit[i],