From dc10f82753efd236e1811a72c4be2c27cefd2c68 Mon Sep 17 00:00:00 2001 From: rprinz08 Date: Fri, 10 Sep 2021 10:06:47 +0200 Subject: [PATCH] Make LiteEthMACCore clock domain crossing TX/RX fifo depths configurable --- liteeth/mac/core.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/liteeth/mac/core.py b/liteeth/mac/core.py index 9929b5ec..2f584a3d 100644 --- a/liteeth/mac/core.py +++ b/liteeth/mac/core.py @@ -17,7 +17,8 @@ # MAC Core ----------------------------------------------------------------------------------------- class LiteEthMACCore(Module, AutoCSR): - def __init__(self, phy, dw, endianness="big", with_preamble_crc=True, with_padding=True): + def __init__(self, phy, dw, endianness="big", with_preamble_crc=True, with_padding=True, + cdc_tx_depth=32, cdc_rx_depth=32): if dw < phy.dw: raise ValueError("Core data width({}) must be larger than PHY data width({})".format(dw, phy.dw)) @@ -103,8 +104,10 @@ def __init__(self, phy, dw, endianness="big", with_preamble_crc=True, with_paddi rx_pipeline += [rx_converter] # Cross Domain Crossing - tx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw), cd_from="sys", cd_to="eth_tx", depth=32) - rx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw), cd_from="eth_rx", cd_to="sys", depth=32) + tx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw), cd_from="sys", + cd_to="eth_tx", depth=cdc_tx_depth) + rx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw), cd_from="eth_rx", + cd_to="sys", depth=cdc_rx_depth) self.submodules += tx_cdc, rx_cdc tx_pipeline += [tx_cdc] rx_pipeline += [rx_cdc]