diff --git a/xls/codegen_v_1_5/state_to_register_io_lowering_pass.cc b/xls/codegen_v_1_5/state_to_register_io_lowering_pass.cc
index cf9d8921e6..f3d43ab8b6 100644
--- a/xls/codegen_v_1_5/state_to_register_io_lowering_pass.cc
+++ b/xls/codegen_v_1_5/state_to_register_io_lowering_pass.cc
@@ -229,12 +229,15 @@ absl::Status LowerStateElement(ScheduledBlock* block,
                                   *last_write, read_stage_index, read_stage));
   }
 
+  std::vector<Node*> all_write_conditions;
   std::vector<Node*> gates;
   std::vector<Node*> write_conditions;
   std::vector<Node*> values;
+  all_write_conditions.reserve(writes.size());
   gates.reserve(writes.size());
   write_conditions.reserve(writes.size());
   values.reserve(writes.size());
+
   for (Next* write : writes) {
     XLS_ASSIGN_OR_RETURN(int stage_index, block->GetStageIndex(write));
     Stage& stage = block->stages()[stage_index];
@@ -242,6 +245,32 @@ absl::Status LowerStateElement(ScheduledBlock* block,
     Node* value = write->value();
     std::optional<Node*> predicate = write->predicate();
 
+    // If we have no full bit to update and this is just a self-assignment, we
+    // can skip this write entirely.
+    if (!reg_full && write->value() == reg_read_or_zero) {
+      continue;
+    }
+
+    // The write condition triggers exactly when the stage is outputting its
+    // results and the predicate is true.
+    //
+    // If we have a full bit to update, we compute the condition even if this is
+    // just a self-assignment.
+    std::vector<Node*> condition_operands{stage.outputs_valid(),
+                                          stage.outputs_ready()};
+    if (predicate.has_value()) {
+      condition_operands.push_back(*predicate);
+    }
+    XLS_ASSIGN_OR_RETURN(Node * condition,
+                         NaryAndIfNeeded(block, condition_operands));
+    all_write_conditions.push_back(condition);
+
+    // For data updates, we skip all self-assignments, as they're just
+    // unchanged values.
+    if (write->value() == reg_read_or_zero) {
+      continue;
+    }
+
     // If needed, add identity nodes to signal that the value and predicate both
     // need to be available at the write's stage. (This enables pipeline
     // register insertion later.)
@@ -259,15 +288,11 @@ absl::Status LowerStateElement(ScheduledBlock* block,
 
     std::vector<Node*> gate_operands{stage.inputs_valid(),
                                      stage.active_inputs_valid()};
-    std::vector<Node*> condition_operands{stage.outputs_valid(),
-                                          stage.outputs_ready()};
     if (predicate.has_value()) {
       gate_operands.push_back(*predicate);
-      condition_operands.push_back(*predicate);
     }
     XLS_ASSIGN_OR_RETURN(Node * gate, NaryAndIfNeeded(block, gate_operands));
-    XLS_ASSIGN_OR_RETURN(Node * condition,
-                         NaryAndIfNeeded(block, condition_operands));
+
     gates.push_back(gate);
     write_conditions.push_back(condition);
     values.push_back(value);
@@ -319,9 +344,15 @@ absl::Status LowerStateElement(ScheduledBlock* block,
 
   // Write the full bit if needed.
   if (reg_full != nullptr) {
+    std::optional<Node*> full_write_enable = std::nullopt;
+    if (!all_write_conditions.empty()) {
+      XLS_ASSIGN_OR_RETURN(full_write_enable,
+                           NaryOrIfNeeded(block, all_write_conditions,
+                                          /*name=*/"", last_write_loc));
+    }
     XLS_RETURN_IF_ERROR(AddFullRegisterWrite(block, reg_full, read_predicate,
                                              read_stage, last_write_loc,
-                                             write_load_enable));
+                                             full_write_enable));
   }
 
   return absl::OkStatus();
diff --git a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithFullBitForToken.ir b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithFullBitForToken.ir
index b07c057543..ff4fb1c0a2 100644
--- a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithFullBitForToken.ir
+++ b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithFullBitForToken.ir
@@ -35,15 +35,15 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
   stage_outputs_ready_2: bits[1] = literal(value=1, id=29)
   controlled_stage(stage_inputs_valid_2, stage_outputs_ready_2) {
     active_inputs_valid active_inputs_valid_2: bits[1] = literal(value=1, id=30)
-    identity.45: token = identity(tok, id=45)
+    identity.46: token = identity(tok, id=46)
     ret stage_outputs_valid_2: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=32)
   }
   rst: bits[1] = input_port(name=rst, id=19)
   literal.43: token = literal(value=token, id=43)
-  and.46: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=46)
-  and.47: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=47)
+  and.45: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=45)
+  and.47: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=47)
   tuple.48: () = tuple(id=48)
   and.49: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=49)
-  or.50: bits[1] = or(and.49, and.47, id=50)
-  register_write.51: () = register_write(and.47, register=____state_full, load_enable=or.50, reset=rst, id=51)
+  or.50: bits[1] = or(and.49, and.45, id=50)
+  register_write.51: () = register_write(and.45, register=____state_full, load_enable=or.50, reset=rst, id=51)
 }
diff --git a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithMultiTokenTupleState.ir b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithMultiTokenTupleState.ir
index 8a24afe6fe..234db52504 100644
--- a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithMultiTokenTupleState.ir
+++ b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithMultiTokenTupleState.ir
@@ -22,7 +22,7 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
   }
   rst: bits[1] = input_port(name=rst, id=19)
   literal.206: (token, token) = literal(value=(token, token), id=206)
-  and.207: bits[1] = and(stage_inputs_valid_0, active_inputs_valid_0, id=207)
-  and.208: bits[1] = and(stage_outputs_valid_0, stage_outputs_ready_0, id=208)
+  and.207: bits[1] = and(stage_outputs_valid_0, stage_outputs_ready_0, id=207)
+  and.208: bits[1] = and(stage_inputs_valid_0, active_inputs_valid_0, id=208)
   tuple.209: () = tuple(id=209)
 }
diff --git a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithNonZeroInitValue.ir b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithNonZeroInitValue.ir
index 32999d16f4..ccb216f434 100644
--- a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithNonZeroInitValue.ir
+++ b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithNonZeroInitValue.ir
@@ -34,8 +34,8 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
     ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=27)
   }
   rst: bits[1] = input_port(name=rst, id=19)
-  and.41: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=41)
-  and.42: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=42)
-  register_write.43: () = register_write(result_value, register=____state, load_enable=and.42, reset=rst, id=43)
+  and.41: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=41)
+  and.42: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=42)
+  register_write.43: () = register_write(result_value, register=____state, load_enable=and.41, reset=rst, id=43)
   tuple.44: () = tuple(id=44)
 }
diff --git a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithTupleState.ir b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithTupleState.ir
index 22d39b2783..92a69007c1 100644
--- a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithTupleState.ir
+++ b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_ProcWithTupleState.ir
@@ -37,8 +37,8 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
     ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=27)
   }
   rst: bits[1] = input_port(name=rst, id=19)
-  and.209: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=209)
-  and.210: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=210)
-  register_write.211: () = register_write(tuple.202, register=____state, load_enable=and.210, reset=rst, id=211)
+  and.209: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=209)
+  and.210: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=210)
+  register_write.211: () = register_write(tuple.202, register=____state, load_enable=and.209, reset=rst, id=211)
   tuple.212: () = tuple(id=212)
 }
diff --git a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithFullBit.ir b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithFullBit.ir
index a506e33289..4bd9a7fc68 100644
--- a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithFullBit.ir
+++ b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithFullBit.ir
@@ -39,15 +39,15 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
   stage_outputs_ready_2: bits[1] = literal(value=1, id=29)
   controlled_stage(stage_inputs_valid_2, stage_outputs_ready_2) {
     active_inputs_valid active_inputs_valid_2: bits[1] = literal(value=1, id=30)
-    identity.46: bits[32] = identity(result_value, id=46)
+    identity.47: bits[32] = identity(result_value, id=47)
     ret stage_outputs_valid_2: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=32)
   }
   rst: bits[1] = input_port(name=rst, id=19)
-  and.47: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=47)
-  and.48: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=48)
-  register_write.49: () = register_write(identity.46, register=____state, load_enable=and.48, reset=rst, id=49)
+  and.46: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=46)
+  and.48: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=48)
+  register_write.49: () = register_write(identity.47, register=____state, load_enable=and.46, reset=rst, id=49)
   tuple.50: () = tuple(id=50)
   and.51: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=51)
-  or.52: bits[1] = or(and.51, and.48, id=52)
-  register_write.53: () = register_write(and.48, register=____state_full, load_enable=or.52, reset=rst, id=53)
+  or.52: bits[1] = or(and.51, and.46, id=52)
+  register_write.53: () = register_write(and.46, register=____state_full, load_enable=or.52, reset=rst, id=53)
 }
diff --git a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithFullBitAndPredicates.ir b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithFullBitAndPredicates.ir
index 45f3df6fdc..048ff21c3c 100644
--- a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithFullBitAndPredicates.ir
+++ b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithFullBitAndPredicates.ir
@@ -53,16 +53,16 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
   stage_outputs_ready_2: bits[1] = literal(value=1, id=29)
   controlled_stage(stage_inputs_valid_2, stage_outputs_ready_2) {
     active_inputs_valid active_inputs_valid_2: bits[1] = literal(value=1, id=30)
-    identity.77: bits[32] = identity(sel.24, id=77)
-    identity.78: bits[1] = identity(ugt.22, id=78)
+    identity.78: bits[32] = identity(sel.24, id=78)
+    identity.79: bits[1] = identity(ugt.22, id=79)
     ret stage_outputs_valid_2: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=43)
   }
   rst: bits[1] = input_port(name=rst, id=35)
-  and.79: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, identity.78, id=79)
-  and.80: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, identity.78, id=80)
-  register_write.81: () = register_write(identity.77, register=____state, load_enable=and.80, reset=rst, id=81)
+  and.77: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, ugt.22, id=77)
+  and.80: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, identity.79, id=80)
+  register_write.81: () = register_write(identity.78, register=____state, load_enable=and.77, reset=rst, id=81)
   tuple.82: () = tuple(id=82)
   and.83: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, ugt.16, id=83)
-  or.84: bits[1] = or(and.83, and.80, id=84)
-  register_write.85: () = register_write(and.80, register=____state_full, load_enable=or.84, reset=rst, id=85)
+  or.84: bits[1] = or(and.83, and.77, id=84)
+  register_write.85: () = register_write(and.77, register=____state_full, load_enable=or.84, reset=rst, id=85)
 }
diff --git a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithGlobalChannels.ir b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithGlobalChannels.ir
index 5c5939080b..22cc31c57d 100644
--- a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithGlobalChannels.ir
+++ b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithGlobalChannels.ir
@@ -35,8 +35,8 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
     ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=26)
   }
   rst: bits[1] = input_port(name=rst, id=18)
-  and.40: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=40)
-  and.41: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=41)
-  register_write.42: () = register_write(result_value, register=____state, load_enable=and.41, reset=rst, id=42)
+  and.40: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=40)
+  and.41: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=41)
+  register_write.42: () = register_write(result_value, register=____state, load_enable=and.40, reset=rst, id=42)
   tuple.43: () = tuple(id=43)
 }
diff --git a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithMultipleStateElements.ir b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithMultipleStateElements.ir
index 4f50a580cf..115862cfd7 100644
--- a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithMultipleStateElements.ir
+++ b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithMultipleStateElements.ir
@@ -46,24 +46,24 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
   stage_outputs_ready_2: bits[1] = literal(value=1, id=110)
   controlled_stage(stage_inputs_valid_2, stage_outputs_ready_2) {
     active_inputs_valid active_inputs_valid_2: bits[1] = literal(value=1, id=111)
-    identity.128: bits[32] = identity(result_value, id=128)
-    identity.139: bits[32] = identity(result_value, id=139)
+    identity.129: bits[32] = identity(result_value, id=129)
+    identity.140: bits[32] = identity(result_value, id=140)
     ret stage_outputs_valid_2: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=112)
   }
   literal.3: bits[1] = literal(value=1, id=3)
   rst: bits[1] = input_port(name=rst, id=105)
-  and.129: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=129)
-  and.130: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=130)
-  register_write.131: () = register_write(identity.128, register=____state_0, load_enable=and.130, reset=rst, id=131)
+  and.128: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=128)
+  and.130: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=130)
+  register_write.131: () = register_write(identity.129, register=____state_0, load_enable=and.128, reset=rst, id=131)
   next_value_23_0: () = tuple(id=132)
   and.133: bits[1] = and(stage_outputs_valid_0, stage_outputs_ready_0, id=133)
-  or.134: bits[1] = or(and.133, and.130, id=134)
-  register_write.135: () = register_write(and.130, register=____state_0_full, load_enable=or.134, reset=rst, id=135)
-  and.140: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=140)
-  and.141: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=141)
-  register_write.142: () = register_write(identity.139, register=____state_1, load_enable=and.141, reset=rst, id=142)
+  or.134: bits[1] = or(and.133, and.128, id=134)
+  register_write.135: () = register_write(and.128, register=____state_0_full, load_enable=or.134, reset=rst, id=135)
+  and.139: bits[1] = and(stage_outputs_valid_2, stage_outputs_ready_2, id=139)
+  and.141: bits[1] = and(stage_inputs_valid_2, active_inputs_valid_2, id=141)
+  register_write.142: () = register_write(identity.140, register=____state_1, load_enable=and.139, reset=rst, id=142)
   next_value_23_1: () = tuple(id=143)
   and.144: bits[1] = and(stage_outputs_valid_0, stage_outputs_ready_0, id=144)
-  or.145: bits[1] = or(and.144, and.141, id=145)
-  register_write.146: () = register_write(and.141, register=____state_1_full, load_enable=or.145, reset=rst, id=146)
+  or.145: bits[1] = or(and.144, and.139, id=145)
+  register_write.146: () = register_write(and.139, register=____state_1_full, load_enable=or.145, reset=rst, id=146)
 }
diff --git a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithProcScopedChannels.ir b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithProcScopedChannels.ir
index d260d04906..5730e9355a 100644
--- a/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithProcScopedChannels.ir
+++ b/xls/codegen_v_1_5/testdata/state_to_register_io_lowering_test_SimpleProcWithProcScopedChannels.ir
@@ -34,8 +34,8 @@ top scheduled_block __test__P_0_next(clk: clock, rst: bits[1]) {
     ret stage_outputs_valid_1: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=27)
   }
   rst: bits[1] = input_port(name=rst, id=19)
-  and.41: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=41)
-  and.42: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=42)
-  register_write.43: () = register_write(result_value, register=____state, load_enable=and.42, reset=rst, id=43)
+  and.41: bits[1] = and(stage_outputs_valid_1, stage_outputs_ready_1, id=41)
+  and.42: bits[1] = and(stage_inputs_valid_1, active_inputs_valid_1, id=42)
+  register_write.43: () = register_write(result_value, register=____state, load_enable=and.41, reset=rst, id=43)
   tuple.44: () = tuple(id=44)
 }
diff --git a/xls/tools/testdata/codegen_main_test__test_multi_proc.vtxt b/xls/tools/testdata/codegen_main_test__test_multi_proc.vtxt
index 87c0ce3b65..20c7214ec5 100644
--- a/xls/tools/testdata/codegen_main_test__test_multi_proc.vtxt
+++ b/xls/tools/testdata/codegen_main_test__test_multi_proc.vtxt
@@ -24,7 +24,7 @@ module multi_proc__1(
   wire in_valid_load_en;
   wire in_load_en;
   wire [31:0] negate;
-  wire or_217;
+  wire or_213;
   assign internal_valid_inv = ~__internal_valid_reg;
   assign internal_valid_load_en = internal_rdy | internal_valid_inv;
   assign internal_load_en = p1_inputs_valid & internal_valid_load_en;
@@ -35,7 +35,7 @@ module multi_proc__1(
   assign in_valid_load_en = p0_stage_done__1 | in_valid_inv;
   assign in_load_en = in_vld & in_valid_load_en;
   assign negate = -p0_data;
-  assign or_217 = p0_stage_done__1 | stage_outputs_valid_1;
+  assign or_213 = p0_stage_done__1 | stage_outputs_valid_1;
   always_ff @ (posedge clk) begin
     if (rst) begin
       p0_data <= 32'h0000_0000;
@@ -50,7 +50,7 @@ module multi_proc__1(
       __in_valid_reg <= in_valid_load_en ? in_vld : __in_valid_reg;
       __internal_reg <= internal_load_en ? negate : __internal_reg;
       __internal_valid_reg <= internal_valid_load_en ? p1_inputs_valid : __internal_valid_reg;
-      p1_inputs_valid <= or_217 ? p0_stage_done__1 : p1_inputs_valid;
+      p1_inputs_valid <= or_213 ? p0_stage_done__1 : p1_inputs_valid;
     end
   end
   assign in_rdy = in_load_en;
@@ -85,7 +85,7 @@ module proc1(
   wire internal_valid_load_en;
   wire internal_load_en;
   wire [31:0] negate;
-  wire or_277;
+  wire or_271;
   assign out_valid_inv = ~__out_valid_reg;
   assign out_valid_load_en = out_rdy | out_valid_inv;
   assign out_load_en = p1_inputs_valid & out_valid_load_en;
@@ -96,7 +96,7 @@ module proc1(
   assign internal_valid_load_en = p0_stage_done__1 | internal_valid_inv;
   assign internal_load_en = internal_vld & internal_valid_load_en;
   assign negate = -p0_data;
-  assign or_277 = p0_stage_done__1 | stage_outputs_valid_1;
+  assign or_271 = p0_stage_done__1 | stage_outputs_valid_1;
   always_ff @ (posedge clk) begin
     if (rst) begin
       p0_data <= 32'h0000_0000;
@@ -111,7 +111,7 @@ module proc1(
       __internal_valid_reg <= internal_valid_load_en ? internal_vld : __internal_valid_reg;
       __out_reg <= out_load_en ? negate : __out_reg;
       __out_valid_reg <= out_valid_load_en ? p1_inputs_valid : __out_valid_reg;
-      p1_inputs_valid <= or_277 ? p0_stage_done__1 : p1_inputs_valid;
+      p1_inputs_valid <= or_271 ? p0_stage_done__1 : p1_inputs_valid;
     end
   end
   assign internal_rdy = internal_load_en;
@@ -130,35 +130,35 @@ module multi_proc(
   output wire [31:0] out,
   output wire out_vld
 );
-  wire instantiation_output_156;
-  wire [31:0] instantiation_output_161;
-  wire instantiation_output_162;
-  wire instantiation_output_169;
-  wire [31:0] instantiation_output_173;
-  wire instantiation_output_174;
-  wire instantiation_output_163;
-  wire [31:0] instantiation_output_167;
-  wire instantiation_output_168;
+  wire instantiation_output_152;
+  wire [31:0] instantiation_output_157;
+  wire instantiation_output_158;
+  wire instantiation_output_165;
+  wire [31:0] instantiation_output_169;
+  wire instantiation_output_170;
+  wire instantiation_output_159;
+  wire [31:0] instantiation_output_163;
+  wire instantiation_output_164;
 
   // ===== Instantiations
   multi_proc__1 multi_proc__1_inst0 (
     .rst(rst),
     .in(in),
     .in_vld(in_vld),
-    .internal_rdy(instantiation_output_163),
-    .in_rdy(instantiation_output_156),
-    .internal(instantiation_output_161),
-    .internal_vld(instantiation_output_162),
+    .internal_rdy(instantiation_output_159),
+    .in_rdy(instantiation_output_152),
+    .internal(instantiation_output_157),
+    .internal_vld(instantiation_output_158),
     .clk(clk)
   );
   proc1 proc1_inst1 (
     .rst(rst),
-    .internal(instantiation_output_167),
-    .internal_vld(instantiation_output_168),
+    .internal(instantiation_output_163),
+    .internal_vld(instantiation_output_164),
     .out_rdy(out_rdy),
-    .internal_rdy(instantiation_output_169),
-    .out(instantiation_output_173),
-    .out_vld(instantiation_output_174),
+    .internal_rdy(instantiation_output_165),
+    .out(instantiation_output_169),
+    .out_vld(instantiation_output_170),
     .clk(clk)
   );
   xls_fifo_wrapper #(
@@ -170,14 +170,14 @@ module multi_proc(
   ) fifo_internal (
     .clk(clk),
     .rst(rst),
-    .push_data(instantiation_output_161),
-    .push_valid(instantiation_output_162),
-    .pop_ready(instantiation_output_169),
-    .push_ready(instantiation_output_163),
-    .pop_data(instantiation_output_167),
-    .pop_valid(instantiation_output_168)
+    .push_data(instantiation_output_157),
+    .push_valid(instantiation_output_158),
+    .pop_ready(instantiation_output_165),
+    .push_ready(instantiation_output_159),
+    .pop_data(instantiation_output_163),
+    .pop_valid(instantiation_output_164)
   );
-  assign in_rdy = instantiation_output_156;
-  assign out = instantiation_output_173;
-  assign out_vld = instantiation_output_174;
+  assign in_rdy = instantiation_output_152;
+  assign out = instantiation_output_169;
+  assign out_vld = instantiation_output_170;
 endmodule
diff --git a/xls/tools/testdata/codegen_main_test__test_multi_proc_container_has_name_of_block.vtxt b/xls/tools/testdata/codegen_main_test__test_multi_proc_container_has_name_of_block.vtxt
index 210e6afb1d..f81ca24cd9 100644
--- a/xls/tools/testdata/codegen_main_test__test_multi_proc_container_has_name_of_block.vtxt
+++ b/xls/tools/testdata/codegen_main_test__test_multi_proc_container_has_name_of_block.vtxt
@@ -24,7 +24,7 @@ module proc0__1(
   wire in_valid_load_en;
   wire in_load_en;
   wire [31:0] negate;
-  wire or_217;
+  wire or_213;
   assign internal_valid_inv = ~__internal_valid_reg;
   assign internal_valid_load_en = internal_rdy | internal_valid_inv;
   assign internal_load_en = p1_inputs_valid & internal_valid_load_en;
@@ -35,7 +35,7 @@ module proc0__1(
   assign in_valid_load_en = p0_stage_done__1 | in_valid_inv;
   assign in_load_en = in_vld & in_valid_load_en;
   assign negate = -p0_data;
-  assign or_217 = p0_stage_done__1 | stage_outputs_valid_1;
+  assign or_213 = p0_stage_done__1 | stage_outputs_valid_1;
   always_ff @ (posedge clk) begin
     if (rst) begin
       p0_data <= 32'h0000_0000;
@@ -50,7 +50,7 @@ module proc0__1(
       __in_valid_reg <= in_valid_load_en ? in_vld : __in_valid_reg;
       __internal_reg <= internal_load_en ? negate : __internal_reg;
       __internal_valid_reg <= internal_valid_load_en ? p1_inputs_valid : __internal_valid_reg;
-      p1_inputs_valid <= or_217 ? p0_stage_done__1 : p1_inputs_valid;
+      p1_inputs_valid <= or_213 ? p0_stage_done__1 : p1_inputs_valid;
     end
   end
   assign in_rdy = in_load_en;
@@ -85,7 +85,7 @@ module proc1(
   wire internal_valid_load_en;
   wire internal_load_en;
   wire [31:0] negate;
-  wire or_277;
+  wire or_271;
   assign out_valid_inv = ~__out_valid_reg;
   assign out_valid_load_en = out_rdy | out_valid_inv;
   assign out_load_en = p1_inputs_valid & out_valid_load_en;
@@ -96,7 +96,7 @@ module proc1(
   assign internal_valid_load_en = p0_stage_done__1 | internal_valid_inv;
   assign internal_load_en = internal_vld & internal_valid_load_en;
   assign negate = -p0_data;
-  assign or_277 = p0_stage_done__1 | stage_outputs_valid_1;
+  assign or_271 = p0_stage_done__1 | stage_outputs_valid_1;
   always_ff @ (posedge clk) begin
     if (rst) begin
       p0_data <= 32'h0000_0000;
@@ -111,7 +111,7 @@ module proc1(
       __internal_valid_reg <= internal_valid_load_en ? internal_vld : __internal_valid_reg;
       __out_reg <= out_load_en ? negate : __out_reg;
       __out_valid_reg <= out_valid_load_en ? p1_inputs_valid : __out_valid_reg;
-      p1_inputs_valid <= or_277 ? p0_stage_done__1 : p1_inputs_valid;
+      p1_inputs_valid <= or_271 ? p0_stage_done__1 : p1_inputs_valid;
     end
   end
   assign internal_rdy = internal_load_en;
@@ -130,35 +130,35 @@ module proc0(
   output wire [31:0] out,
   output wire out_vld
 );
-  wire instantiation_output_156;
-  wire [31:0] instantiation_output_161;
-  wire instantiation_output_162;
-  wire instantiation_output_169;
-  wire [31:0] instantiation_output_173;
-  wire instantiation_output_174;
-  wire instantiation_output_163;
-  wire [31:0] instantiation_output_167;
-  wire instantiation_output_168;
+  wire instantiation_output_152;
+  wire [31:0] instantiation_output_157;
+  wire instantiation_output_158;
+  wire instantiation_output_165;
+  wire [31:0] instantiation_output_169;
+  wire instantiation_output_170;
+  wire instantiation_output_159;
+  wire [31:0] instantiation_output_163;
+  wire instantiation_output_164;
 
   // ===== Instantiations
   proc0__1 proc0__1_inst0 (
     .rst(rst),
     .in(in),
     .in_vld(in_vld),
-    .internal_rdy(instantiation_output_163),
-    .in_rdy(instantiation_output_156),
-    .internal(instantiation_output_161),
-    .internal_vld(instantiation_output_162),
+    .internal_rdy(instantiation_output_159),
+    .in_rdy(instantiation_output_152),
+    .internal(instantiation_output_157),
+    .internal_vld(instantiation_output_158),
     .clk(clk)
   );
   proc1 proc1_inst1 (
     .rst(rst),
-    .internal(instantiation_output_167),
-    .internal_vld(instantiation_output_168),
+    .internal(instantiation_output_163),
+    .internal_vld(instantiation_output_164),
     .out_rdy(out_rdy),
-    .internal_rdy(instantiation_output_169),
-    .out(instantiation_output_173),
-    .out_vld(instantiation_output_174),
+    .internal_rdy(instantiation_output_165),
+    .out(instantiation_output_169),
+    .out_vld(instantiation_output_170),
     .clk(clk)
   );
   xls_fifo_wrapper #(
@@ -170,14 +170,14 @@ module proc0(
   ) fifo_internal (
     .clk(clk),
     .rst(rst),
-    .push_data(instantiation_output_161),
-    .push_valid(instantiation_output_162),
-    .pop_ready(instantiation_output_169),
-    .push_ready(instantiation_output_163),
-    .pop_data(instantiation_output_167),
-    .pop_valid(instantiation_output_168)
+    .push_data(instantiation_output_157),
+    .push_valid(instantiation_output_158),
+    .pop_ready(instantiation_output_165),
+    .push_ready(instantiation_output_159),
+    .pop_data(instantiation_output_163),
+    .pop_valid(instantiation_output_164)
   );
-  assign in_rdy = instantiation_output_156;
-  assign out = instantiation_output_173;
-  assign out_vld = instantiation_output_174;
+  assign in_rdy = instantiation_output_152;
+  assign out = instantiation_output_169;
+  assign out_vld = instantiation_output_170;
 endmodule