From d27acd1be8484b771d619f051b2fac1fff372321 Mon Sep 17 00:00:00 2001
From: "Vinogradov, Sergei" <sergey.vinogradov@intel.com>
Date: Thu, 27 Apr 2023 09:41:33 -0400
Subject: [PATCH] Adding lockMemory flag support to the cachebench

---
 cachelib/cachebench/cache/Cache-inl.h    | 2 ++
 cachelib/cachebench/util/CacheConfig.cpp | 1 +
 cachelib/cachebench/util/CacheConfig.h   | 3 +++
 3 files changed, 6 insertions(+)

diff --git a/cachelib/cachebench/cache/Cache-inl.h b/cachelib/cachebench/cache/Cache-inl.h
index 2a6861c8ec..7fd2e60641 100644
--- a/cachelib/cachebench/cache/Cache-inl.h
+++ b/cachelib/cachebench/cache/Cache-inl.h
@@ -98,6 +98,8 @@ Cache<Allocator>::Cache(const CacheConfig& config,
     allocatorConfig_.usePosixForShm();
   }
 
+  allocatorConfig_.setMemoryLocking(config_.lockMemory);
+
   if (!config_.memoryTierConfigs.empty()) {
     allocatorConfig_.configureMemoryTiers(config_.memoryTierConfigs);
   }
diff --git a/cachelib/cachebench/util/CacheConfig.cpp b/cachelib/cachebench/util/CacheConfig.cpp
index fc37e5cc30..5072021f9e 100644
--- a/cachelib/cachebench/util/CacheConfig.cpp
+++ b/cachelib/cachebench/util/CacheConfig.cpp
@@ -91,6 +91,7 @@ CacheConfig::CacheConfig(const folly::dynamic& configJson) {
   JSONSetVal(configJson, memoryOnlyTTL);
 
   JSONSetVal(configJson, usePosixShm);
+  JSONSetVal(configJson, lockMemory);
   if (configJson.count("memoryTiers")) {
     for (auto& it : configJson["memoryTiers"]) {
       memoryTierConfigs.push_back(
diff --git a/cachelib/cachebench/util/CacheConfig.h b/cachelib/cachebench/util/CacheConfig.h
index a4713a1cc4..411fe73275 100644
--- a/cachelib/cachebench/util/CacheConfig.h
+++ b/cachelib/cachebench/util/CacheConfig.h
@@ -222,6 +222,9 @@ struct CacheConfig : public JSONConfig {
   // Use Posix Shm instead of SysVShm
   bool usePosixShm{false};
 
+  // Lock memory in the RAM
+  bool lockMemory{false};
+
   // Memory tiers configs
   std::vector<MemoryTierCacheConfig> memoryTierConfigs{};