x86/mce: Add MCACOD code for generic I/O error

Errors of some I/O devices can be signaled by MCE and logged in
IOMCA bank. Add MCACOD code of generic I/O error and related macros
for MCi_MISC to support IOMCA logging.

See Intel Software Developers' Manual, version 071, volume 3B,
section "IOMCA".

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>

Author: qzhuo2

arch/x86/include/asm/mce.h

@@ -78,6 +78,7 @@
 #define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */
 #define MCACOD_DATA	0x0134	/* Data Load */
 #define MCACOD_INSTR	0x0150	/* Instruction Fetch */
+#define MCACOD_IOERR	0x0e0b	/* Generic I/O error */
 
 /* MCi_MISC register defines */
 #define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
@@ -91,6 +92,11 @@
 /* MCi_ADDR register defines */
 #define MCI_ADDR_PHYSADDR	GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)
 
+#define MCI_MISC_PCISEG_MASK	GENMASK_ULL(39, 32)
+#define MCI_MISC_PCISEG(m)	(((m) & MCI_MISC_PCISEG_MASK) >> 32)
+#define MCI_MISC_PCIRID_MASK	GENMASK_ULL(31, 16)
+#define MCI_MISC_PCIRID(m)	(((m) & MCI_MISC_PCIRID_MASK) >> 16)
+
 /* CTL2 register defines */
 #define MCI_CTL2_CMCI_EN		BIT_ULL(30)
 #define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL