From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Thu, 15 Aug 2024 13:41:31 +0100 Subject: [PATCH 01/19] [AArch64] Add a check for invalid default features This adds a check that all ExtensionWithMArch which are marked as implied features for an architecture are also present in the list of default features. It doesn't make sense to have something mandatory but not on by default. There were a number of existing cases that violated this rule, and some changes to which features are mandatory (indicated by the Implies field): > FEAT_SPECRES is mandatory from Armv8.5. FeaturePredRes is added to the HasV8_5aOps.DefaultExts. > FEAT_DIT is mandatory from Armv8.4. FeatureDIT is added to the HasV8_4aOps.DefaultExts. FEAT_SSBS is not mandatory for any architecture. https://reviews.llvm.org/D54629 says it is mandatory for 8.5-a but I can't see that in the Arm ARM. FeatureSSBS is removed from Implied and added to HasV8_5aOps.DefaultExts. Cortex-A710 does not appear to have SSBS https://developer.arm.com/documentation/101800/0201/The-Cortex-A710--core/Cortex-A710--core-features?lang=en Removed from the Cortex-A710 and Oryon print-supported-extensions tests. https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/ Added to Apple A15/A16/A17 and (presumably?) M4 processor features. > FEAT_BTI is mandatory from Armv8.5. FeatureBranchTargetId is added to the DefaultExts > FEAT_FlagM is mandatory from Armv8.4. FeatureFlagM is added to the DefaultExts > In an Armv8.4 implementation, if FEAT_AdvSIMD is implemented, FEAT_DotProd is implemented. FeatureDotProd is added to the HasV8_4aOps.DefaultExts. FIXME what about nofp here? > FEAT_SB is mandatory from Armv8.5. FeatureSB is added to HasV8_5aOps.DefaultExts. Therefore it appears on the `-cc1` command line for `-march=armv8.5a+nosb`. > FEAT_WFxT is mandatory from Armv8.7. FeatureWFxT is added to HasV8_7aOps.DefaultExts and HasV9_2aOps.DefaultExts. > FEAT_CCIDX is OPTIONAL from Armv8.2. Removed from Implies and added to HasV8_3aOps.DefaultExts and HasV8_0rOps.DefaultExts. For v8-R, FEAT_CCIDX is not mandatory, removed. - Not implemented by cortex-r82, removed: https://developer.arm.com/documentation/102670/0300/?lang=en - Ditto cortex-r82ae --- clang/test/CodeGen/aarch64-targetattr.c | 12 +++---- clang/test/Driver/arm-sb.c | 2 +- .../aarch64-cortex-a710.c | 1 - .../aarch64-cortex-r82.c | 1 - .../aarch64-cortex-r82ae.c | 1 - .../aarch64-oryon-1.c | 1 - .../Preprocessor/aarch64-target-features.c | 4 +-- llvm/lib/Target/AArch64/AArch64Features.td | 16 +++++----- llvm/lib/Target/AArch64/AArch64Processors.td | 11 ++++--- llvm/test/MC/AArch64/armv8.5a-ssbs-error.s | 2 +- llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +- .../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +- .../TargetParser/TargetParserTest.cpp | 21 ++++++------ llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +++++++++++++++++-- 14 files changed, 67 insertions(+), 41 deletions(-) diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c index 4f891f938b618..d6227be2ebef8 100644 --- a/clang/test/CodeGen/aarch64-targetattr.c +++ b/clang/test/CodeGen/aarch64-targetattr.c @@ -195,19 +195,19 @@ void minusarch() {} // CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" } // CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" } // CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" } -// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" } -// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" } +// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" } +// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" } // CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" } // CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" } // CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" } // CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" } // CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" } -// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" } -// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" } +// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" } +// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" } // CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" } // CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16" } -// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } -// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } +// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } +// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } // CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } // CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" } //. diff --git a/clang/test/Driver/arm-sb.c b/clang/test/Driver/arm-sb.c index f2704f33c2711..9c0f381171cb6 100644 --- a/clang/test/Driver/arm-sb.c +++ b/clang/test/Driver/arm-sb.c @@ -11,6 +11,6 @@ // RUN: %clang -### -target arm-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENT // RUN: %clang -### -target aarch64-none-elf %s 2>&1 | FileCheck %s --check-prefix=ABSENT -// RUN: %clang -### -target aarch64-none-elf -march=armv8.5a+nosb %s 2>&1 | FileCheck %s --check-prefix=ABSENT +// RUN: %clang -### -target aarch64-none-elf -march=armv8.5a+nosb %s 2>&1 | FileCheck %s --check-prefix=NOSB // ABSENT-NOT: "-target-feature" "+sb" // ABSENT-NOT: "-target-feature" "-sb" diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c index f4ba17195cdf6..ce1158e852a09 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c @@ -42,7 +42,6 @@ // CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier // CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension // CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions -// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit // CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions // CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions // CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c index 2b85201c2c6fe..9875c6922d379 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c @@ -5,7 +5,6 @@ // CHECK-EMPTY: // CHECK-NEXT: Architecture Feature(s) Description // CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets // CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions // CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction // CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c index 417687b4af287..2db44d7827aad 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c @@ -5,7 +5,6 @@ // CHECK-EMPTY: // CHECK-NEXT: Architecture Feature(s) Description // CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets // CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions // CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction // CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c b/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c index a40b9ae656353..7852f87e1e345 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c @@ -49,7 +49,6 @@ // CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support // CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension // CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions -// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit // CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions // CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension // CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index 87bd3e142d2c4..0bba63130e693 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -327,7 +327,7 @@ // CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" // CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" "-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+vh" // CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"{{.*}}"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" -// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" +// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+ccidx" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" // CHECK-MCPU-A34: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" // CHECK-MCPU-APPLE-A13: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3" // CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" @@ -347,7 +347,7 @@ // CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+altnzcv" "-target-feature" "+ccdp" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fptoint" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+specrestrict" "-target-feature" "+ssbs" // RUN: %clang -target x86_64-apple-macosx -arch arm64_32 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64_32 %s -// CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" +// CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+ccidx" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" // RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s // RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 8ec13f17cf0a0..6e4ff6c717061 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -785,24 +785,24 @@ def HasV8_3aOps : Architecture64<8, 3, "a", "v8.3a", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureCCIDX, FeatureComplxNum], !listconcat(HasV8_2aOps.DefaultExts, [FeatureComplxNum, FeatureJS, - FeaturePAuth, FeatureRCPC])>; + FeaturePAuth, FeatureRCPC, FeatureCCIDX])>; def HasV8_4aOps : Architecture64<8, 4, "a", "v8.4a", [HasV8_3aOps, FeatureDotProd, FeatureNV, FeatureMPAM, FeatureDIT, FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2], - !listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd])>; + !listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd, FeatureDIT, FeatureFlagM])>; def HasV8_5aOps : Architecture64<8, 5, "a", "v8.5a", [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, - FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, + FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, FeatureBranchTargetId], - !listconcat(HasV8_4aOps.DefaultExts, [])>; + !listconcat(HasV8_4aOps.DefaultExts, [FeaturePredRes, FeatureSSBS, FeatureBranchTargetId, FeatureSB])>; def HasV8_6aOps : Architecture64<8, 6, "a", "v8.6a", [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, FeatureEnhancedCounterVirtualization, FeatureMatMulInt8], !listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>; def HasV8_7aOps : Architecture64<8, 7, "a", "v8.7a", [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX], - !listconcat(HasV8_6aOps.DefaultExts, [])>; + !listconcat(HasV8_6aOps.DefaultExts, [FeatureWFxT])>; def HasV8_8aOps : Architecture64<8, 8, "a", "v8.8a", [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI], !listconcat(HasV8_7aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>; @@ -820,7 +820,7 @@ def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a", !listconcat(HasV9_0aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8, FeatureRME])>; def HasV9_2aOps : Architecture64<9, 2, "a", "v9.2a", [HasV8_7aOps, HasV9_1aOps], - !listconcat(HasV9_1aOps.DefaultExts, [FeatureMEC])>; + !listconcat(HasV9_1aOps.DefaultExts, [FeatureMEC, FeatureWFxT])>; def HasV9_3aOps : Architecture64<9, 3, "a", "v9.3a", [HasV8_8aOps, HasV9_2aOps], !listconcat(HasV9_2aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>; @@ -837,7 +837,7 @@ def HasV8_0rOps : Architecture64<8, 0, "r", "v8r", //v8.2 FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV, //v8.3 - FeatureCCIDX, FeaturePAuth, FeatureRCPC, + FeaturePAuth, FeatureRCPC, //v8.4 FeatureTRACEV8_4, FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO, @@ -848,7 +848,7 @@ def HasV8_0rOps : Architecture64<8, 0, "r", "v8r", // For v8-R, we do not enable crypto and align with GCC that enables a more // minimal set of optional architecture extensions. !listconcat( - !listremove(HasV8_5aOps.DefaultExts, [FeatureLSE]), + !listremove(HasV8_5aOps.DefaultExts, [FeatureBranchTargetId, FeaturePredRes]), [FeatureSSBS, FeatureFullFP16, FeatureFP16FML, FeatureSB] )>; diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 52b5c8a0903ea..46cf9d9e55579 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -845,7 +845,8 @@ def ProcessorFeatures { list AppleA12 = [HasV8_3aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFullFP16, FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, - FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM]; + FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM, + FeatureCCIDX]; list AppleA13 = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFullFP16, FeatureFP16FML, FeatureSHA3, FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, @@ -866,7 +867,7 @@ def ProcessorFeatures { FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureFPAC, FeatureRAS, FeatureRCPC, FeatureRDM, - FeatureBF16, FeatureDotProd, FeatureMatMulInt8]; + FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS]; list AppleA16 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, @@ -874,7 +875,7 @@ def ProcessorFeatures { FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureFPAC, FeatureRAS, FeatureRCPC, FeatureRDM, - FeatureBF16, FeatureDotProd, FeatureMatMulInt8]; + FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS]; list AppleA17 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, @@ -882,7 +883,7 @@ def ProcessorFeatures { FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureFPAC, FeatureRAS, FeatureRCPC, FeatureRDM, - FeatureBF16, FeatureDotProd, FeatureMatMulInt8]; + FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS]; list AppleM4 = [HasV9_2aOps, FeatureSHA2, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, @@ -892,7 +893,7 @@ def ProcessorFeatures { FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureFPAC, FeatureRAS, FeatureRCPC, FeatureRDM, - FeatureDotProd, FeatureMatMulInt8]; + FeatureDotProd, FeatureMatMulInt8, FeatureSSBS]; list ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeaturePerfMon, FeatureNEON, FeatureFPARMv8]; list ExynosM4 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd, diff --git a/llvm/test/MC/AArch64/armv8.5a-ssbs-error.s b/llvm/test/MC/AArch64/armv8.5a-ssbs-error.s index a7c9f4c4fbb5c..cd5ab43046c79 100644 --- a/llvm/test/MC/AArch64/armv8.5a-ssbs-error.s +++ b/llvm/test/MC/AArch64/armv8.5a-ssbs-error.s @@ -1,5 +1,5 @@ // RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs < %s 2>&1 | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID // RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID msr SSBS, #16 diff --git a/llvm/test/MC/AArch64/armv8.5a-ssbs.s b/llvm/test/MC/AArch64/armv8.5a-ssbs.s index ec6670f8ecc34..1b24dd361e5dc 100644 --- a/llvm/test/MC/AArch64/armv8.5a-ssbs.s +++ b/llvm/test/MC/AArch64/armv8.5a-ssbs.s @@ -1,5 +1,5 @@ // RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1| FileCheck %s --check-prefix=NOSPECID // RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a65 < %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a65ae < %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a76 < %s | FileCheck %s diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt index 7698751c88076..84d4fa6accccf 100644 --- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt +++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt @@ -1,5 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+ssbs -disassemble < %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NOSPECID # RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76 -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76ae -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s --check-prefix=NOSPECID diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 960a9892202b3..969982245465f 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1504,21 +1504,21 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16, AArch64::AEK_PERFMON}), AArch64CPUTestParams( "apple-a12", "armv8.3-a", - {AArch64::AEK_CRC, AArch64::AEK_AES, + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_CCIDX, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), AArch64CPUTestParams( "apple-s4", "armv8.3-a", - {AArch64::AEK_CRC, AArch64::AEK_AES, + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_CCIDX, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), AArch64CPUTestParams( "apple-s5", "armv8.3-a", - {AArch64::AEK_CRC, AArch64::AEK_AES, + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_CCIDX, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_FP16, AArch64::AEK_JSCVT, @@ -1591,7 +1591,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON}), + AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON, + AArch64::AEK_SSBS}), AArch64CPUTestParams( "apple-m2", "armv8.6-a", {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, @@ -1600,7 +1601,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON}), + AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON, + AArch64::AEK_SSBS}), AArch64CPUTestParams( "apple-a16", "armv8.6-a", {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, @@ -1610,7 +1612,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON, - AArch64::AEK_HCX}), + AArch64::AEK_HCX, AArch64::AEK_SSBS}), AArch64CPUTestParams( "apple-m3", "armv8.6-a", {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, @@ -1620,7 +1622,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON, - AArch64::AEK_HCX}), + AArch64::AEK_HCX, AArch64::AEK_SSBS}), AArch64CPUTestParams( "apple-a17", "armv8.6-a", {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, @@ -1630,7 +1632,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON, - AArch64::AEK_HCX}), + AArch64::AEK_HCX, AArch64::AEK_SSBS}), AArch64CPUTestParams("apple-m4", "armv9.2-a", {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, @@ -1643,7 +1645,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, AArch64::AEK_SME, AArch64::AEK_SME2, - AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64}), + AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64, + AArch64::AEK_SSBS}), AArch64CPUTestParams("exynos-m3", "armv8-a", {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index a4b25025b3c61..3f7cec9301468 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -19,10 +19,38 @@ #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" #include +#include #include using namespace llvm; +/// Collect the full set of implied features for a SubtargetFeature. +static void CollectImpliedFeatures(std::set &SeenFeats, Record *Rec) { + assert(Rec->isSubClassOf("SubtargetFeature") && + "Rec is not a SubtargetFeature"); + + SeenFeats.insert(Rec); + for (Record *Implied : Rec->getValueAsListOfDefs("Implies")) + CollectImpliedFeatures(SeenFeats, Implied); +} + +static void CheckFeatureTree(Record *Root) { + std::set SeenFeats; + CollectImpliedFeatures(SeenFeats, Root); + + // For processors, check that each of the mandatory (implied) features which + // is an ExtensionWithMArch is also enabled by default. + auto DefaultExtsVec = Root->getValueAsListOfDefs("DefaultExts"); + std::set DefaultExts{DefaultExtsVec.begin(), DefaultExtsVec.end()}; + for (auto *Feat : SeenFeats) { + if (Feat->isSubClassOf("ExtensionWithMArch") && !DefaultExts.count(Feat)) + PrintFatalError(Root->getLoc(), + "ExtensionWithMArch " + Feat->getName() + + " is implied (mandatory) as a SubtargetFeature, but " + "is not present in DefaultExts"); + } +} + static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n"; @@ -283,9 +311,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { auto Profile = Arch->getValueAsString("Profile"); auto ArchInfo = ArchInfoName(Major, Minor, Profile); - // The apple-latest alias is backend only, do not expose it to -mcpu. - if (Name == "apple-latest") - continue; + CheckFeatureTree(Arch); OS << " {\n" << " \"" << Name << "\",\n" From c81d55c36b03f8794d1d8022b13d1331b1fdff6d Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 11:08:08 +0100 Subject: [PATCH 02/19] Remove CCIDX from defaults and from Apple cores --- clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c | 1 - clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c | 1 - clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c | 1 - clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c | 1 - clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c | 1 - clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c | 1 - llvm/lib/Target/AArch64/AArch64Features.td | 3 +-- 7 files changed, 1 insertion(+), 8 deletions(-) diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c index 197b210259951..dae95b1297e14 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c @@ -7,7 +7,6 @@ // CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support // CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension // CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets // CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions // CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions // CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c index f1731ef034a0c..8ddcddede4110 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c @@ -7,7 +7,6 @@ // CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support // CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension // CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets // CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions // CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction // CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c index dec48bb703311..b3f0acefd1e2d 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c @@ -10,7 +10,6 @@ // CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions // CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension // CHECK-NEXT: FEAT_BTI Enable Branch Target Identification -// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets // CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions // CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction // CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c index 477652d83d82c..6f417c1592b06 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c @@ -10,7 +10,6 @@ // CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions // CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension // CHECK-NEXT: FEAT_BTI Enable Branch Target Identification -// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets // CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions // CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction // CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c index 311cc94acddc9..39e5b70c25d88 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c @@ -10,7 +10,6 @@ // CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions // CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension // CHECK-NEXT: FEAT_BTI Enable Branch Target Identification -// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets // CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions // CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction // CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c index 44d618afef406..cc73a9edf1867 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c @@ -10,7 +10,6 @@ // CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions // CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension // CHECK-NEXT: FEAT_BTI Enable Branch Target Identification -// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets // CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions // CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction // CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 6e4ff6c717061..33b734ac61b1a 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -782,8 +782,7 @@ def HasV8_2aOps : Architecture64<8, 2, "a", "v8.2a", [HasV8_1aOps, FeaturePsUAO, FeaturePAN_RWV, FeatureRAS, FeatureCCPP], !listconcat(HasV8_1aOps.DefaultExts, [FeatureRAS])>; def HasV8_3aOps : Architecture64<8, 3, "a", "v8.3a", - [HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureCCIDX, - FeatureComplxNum], + [HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureComplxNum], !listconcat(HasV8_2aOps.DefaultExts, [FeatureComplxNum, FeatureJS, FeaturePAuth, FeatureRCPC, FeatureCCIDX])>; def HasV8_4aOps : Architecture64<8, 4, "a", "v8.4a", From 3cb477ff0087d442519e5662837327edfa474c26 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 11:18:30 +0100 Subject: [PATCH 03/19] Add CCIDX back to Ampere cores. I don't know if this is correct but it preserves the existing behaviour. --- llvm/lib/Target/AArch64/AArch64Processors.td | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 46cf9d9e55579..b8bf99a8579fb 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -988,6 +988,7 @@ def ProcessorFeatures { FeatureSHA2, FeatureSHA3, FeatureAES, FeatureFullFP16, FeatureBF16, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS, + FeatureCCIDX, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM]; list Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, FeatureMTE, FeatureSSBS, FeatureRandGen, @@ -996,6 +997,7 @@ def ProcessorFeatures { FeatureFullFP16, FeatureBF16, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC, + FeatureCCIDX, FeatureRDM]; list Ampere1B = [HasV8_7aOps, FeatureNEON, FeaturePerfMon, FeatureMTE, FeatureSSBS, FeatureRandGen, @@ -1004,6 +1006,7 @@ def ProcessorFeatures { FeatureWFxT, FeatureFullFP16, FeatureBF16, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC, + FeatureCCIDX, FeatureRDM]; list Oryon = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, @@ -1012,6 +1015,7 @@ def ProcessorFeatures { FeatureSHA3, FeatureAES, FeatureSPE, FeatureBF16, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, + FeatureCCIDX, FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM]; // ETE and TRBE are future architecture extensions. We temporarily enable them From 3da9bcce243753826afb56f1c4ed8bc141e63dd1 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 11:21:13 +0100 Subject: [PATCH 04/19] Add CCIDX back to Cortex A510/520/520AE https://developer.arm.com/documentation/101604/latest/ https://developer.arm.com/documentation/102517/0003/The-Cortex-A520--core/Supported-standards-and-specifications?lang=en https://developer.arm.com/documentation/107726/0000/The-Cortex-A520AE--core/Supported-standards-and-specifications?lang=en --- llvm/lib/Target/AArch64/AArch64Processors.td | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index b8bf99a8579fb..ee27f5e65b29d 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -688,6 +688,7 @@ def ProcessorFeatures { FeatureMatMulInt8, FeatureBF16, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, FeatureFP16FML, + FeatureCCIDX, FeatureSB, FeaturePAuth, FeatureSSBS, FeatureSVE, FeatureSVE2, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8,FeatureFullFP16, FeatureJS, FeatureLSE, @@ -695,6 +696,7 @@ def ProcessorFeatures { list A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, FeatureFP16FML, + FeatureCCIDX, FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes, FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8, FeatureJS, From ca0a2eebc8fe0478574eb901b26e2cef2b1799c1 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 11:31:31 +0100 Subject: [PATCH 05/19] Cortex A520AE CCIDX https://developer.arm.com/documentation/107726/0000/The-Cortex-A520AE--core/Supported-standards-and-specifications?lang=en --- llvm/lib/Target/AArch64/AArch64Processors.td | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index ee27f5e65b29d..98df119496714 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -705,6 +705,7 @@ def ProcessorFeatures { list A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, FeatureFP16FML, + FeatureCCIDX, FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes, FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8, FeatureJS, From eba44a550702ff5d69c978dfee70f17f5724edf7 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 11:32:06 +0100 Subject: [PATCH 06/19] FeatureCCIDX, FeatureSSBS for Cortex A7* --- .../Driver/print-enabled-extensions/aarch64-cortex-a710.c | 1 + llvm/lib/Target/AArch64/AArch64Processors.td | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c index ce1158e852a09..f4ba17195cdf6 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c @@ -42,6 +42,7 @@ // CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier // CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension // CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions +// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit // CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions // CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions // CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 98df119496714..92eefbfd3fd02 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -737,12 +737,14 @@ def ProcessorFeatures { FeaturePerfMon, FeatureRCPC, FeatureSPE, FeatureSSBS, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM]; list A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, + FeatureCCIDX, FeatureSSBS, FeatureETE, FeatureMTE, FeatureFP16FML, FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8, FeaturePAuth, FeatureFlagM, FeatureSB, FeatureSVE, FeatureSVE2, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureFullFP16, FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM]; list A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE, + FeatureCCIDX, FeatureFP16FML, FeatureSVE, FeatureTRBE, FeatureSVE2BitPerm, FeatureBF16, FeatureETE, FeaturePerfMon, FeatureMatMulInt8, FeatureSPE, @@ -752,6 +754,7 @@ def ProcessorFeatures { FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM]; list A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML, + FeatureCCIDX, FeatureTRBE, FeatureSVE2BitPerm, FeatureETE, FeaturePerfMon, FeatureSPE, FeatureSPE_EEF, FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes, @@ -760,6 +763,7 @@ def ProcessorFeatures { FeatureJS, FeatureLSE, FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM]; list A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML, + FeatureCCIDX, FeatureTRBE, FeatureSVE2BitPerm, FeatureETE, FeaturePerfMon, FeatureSPE, FeatureSPE_EEF, FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes, @@ -768,6 +772,7 @@ def ProcessorFeatures { FeatureJS, FeatureLSE, FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM]; list A725 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML, + FeatureCCIDX, FeatureETE, FeaturePerfMon, FeatureSPE, FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE, FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS, From b9b43a3eb54a0a1872e3a2f834dfbef0062edaa1 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 11:35:56 +0100 Subject: [PATCH 07/19] CCIDX for Cortex X2/3/4/925 https://developer.arm.com/documentation/101803/0201/The-Cortex-X2--core/Supported-standards-and-specifications?lang=en https://developer.arm.com/documentation/102807/0001/The-Cortex-X925--core/Supported-standards-and-specifications?lang=en --- llvm/lib/Target/AArch64/AArch64Processors.td | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 92eefbfd3fd02..40cfc026db943 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -808,6 +808,7 @@ def ProcessorFeatures { FeatureMatMulInt8, FeatureBF16, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, FeatureFP16FML, + FeatureCCIDX, FeaturePAuth, FeatureSSBS, FeatureSB, FeatureSVE, FeatureSVE2, FeatureFlagM, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureFullFP16, FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM]; @@ -816,6 +817,7 @@ def ProcessorFeatures { FeatureSPE, FeatureBF16, FeatureMatMulInt8, FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16, FeatureFP16FML, + FeatureCCIDX, FeatureSB, FeaturePAuth, FeaturePredRes, FeatureFlagM, FeatureSSBS, FeatureSVE2, FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureDotProd]; @@ -823,11 +825,13 @@ def ProcessorFeatures { FeaturePerfMon, FeatureETE, FeatureTRBE, FeatureSPE, FeatureMTE, FeatureSVE2BitPerm, FeatureFP16FML, FeatureSPE_EEF, + FeatureCCIDX, FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes, FeatureSVE, FeatureSVE2, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8, FeatureJS, FeatureLSE, FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureBF16]; list X925 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML, + FeatureCCIDX, FeatureETE, FeaturePerfMon, FeatureSPE, FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE, FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS, From 3b543b9738a49e378d6d53540c8e0ab733dc8f63 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 11:40:09 +0100 Subject: [PATCH 08/19] CCIDX for neoverse cores https://developer.arm.com/documentation/102099/0003/The-Neoverse-N2--core/Supported-standards-and-specifications?lang=en https://developer.arm.com/documentation/101427/0102/?lang=en --- llvm/lib/Target/AArch64/AArch64Processors.td | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 40cfc026db943..450ed99297b48 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -926,6 +926,7 @@ def ProcessorFeatures { FeatureMatMulInt8, FeatureMTE, FeatureSVE2, FeatureSVE2BitPerm, FeatureTRBE, FeaturePerfMon, + FeatureCCIDX, FeatureDotProd, FeatureFullFP16, FeatureSB, FeatureSSBS, FeatureSVE, FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE, FeatureNEON, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM]; @@ -933,6 +934,7 @@ def ProcessorFeatures { FeatureFullFP16, FeatureMTE, FeaturePerfMon, FeatureRandGen, FeatureSPE, FeatureSPE_EEF, FeatureSVE2BitPerm, + FeatureCCIDX, FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM, FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, @@ -943,6 +945,7 @@ def ProcessorFeatures { FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, FeaturePerfMon, FeatureRandGen, FeatureSPE, FeatureSSBS, FeatureSVE, + FeatureCCIDX, FeatureSHA3, FeatureSM4, FeatureDotProd, FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM]; @@ -951,6 +954,7 @@ def ProcessorFeatures { FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, FeaturePerfMon, FeatureRandGen, FeatureSPE, FeatureSSBS, FeatureSVE, + FeatureCCIDX, FeatureSHA3, FeatureSM4, FeatureDotProd, FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM]; @@ -958,12 +962,14 @@ def ProcessorFeatures { FeaturePerfMon, FeatureETE, FeatureMatMulInt8, FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, FeatureMTE, FeatureRandGen, + FeatureCCIDX, FeatureSVE, FeatureSVE2, FeatureSSBS, FeatureFullFP16, FeatureDotProd, FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM]; list NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML, FeatureFullFP16, FeatureLS64, FeatureMTE, FeaturePerfMon, FeatureRandGen, FeatureSPE, + FeatureCCIDX, FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE, FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM, FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC, @@ -974,6 +980,7 @@ def ProcessorFeatures { FeaturePerfMon, FeatureRandGen, FeatureSPE, FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE, FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM, + FeatureCCIDX, FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS, FeatureLSE, FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM, From cbd7ba17161386b911ecb2c5976af61dc01e8473 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 11:48:48 +0100 Subject: [PATCH 09/19] Add CCIDX back to Saphira and ThunderX3T110 I don't know if this is correct but it preserves the existing behaviour. --- llvm/lib/Target/AArch64/AArch64Processors.td | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 450ed99297b48..c186be647c08b 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -987,6 +987,7 @@ def ProcessorFeatures { FeatureRME]; list Saphira = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureSPE, FeaturePerfMon, FeatureCRC, + FeatureCCIDX, FeatureLSE, FeatureRDM, FeatureRAS, FeatureRCPC]; list ThunderX = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeaturePerfMon, FeatureNEON]; @@ -995,6 +996,7 @@ def ProcessorFeatures { FeatureRDM]; list ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureLSE, + FeatureCCIDX, FeaturePAuth, FeaturePerfMon, FeatureComplxNum, FeatureJS, FeatureRAS, FeatureRCPC, FeatureRDM]; list TSV110 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, From ea99eaba7158350b7e11bc35359497f9543c319f Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 11:56:58 +0100 Subject: [PATCH 10/19] Add a test for the -march bug disabling default extensions --- ...aarch64-negative-modifiers-for-default-features.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 clang/test/Driver/aarch64-negative-modifiers-for-default-features.c diff --git a/clang/test/Driver/aarch64-negative-modifiers-for-default-features.c b/clang/test/Driver/aarch64-negative-modifiers-for-default-features.c new file mode 100644 index 0000000000000..03dd8af7588ca --- /dev/null +++ b/clang/test/Driver/aarch64-negative-modifiers-for-default-features.c @@ -0,0 +1,12 @@ +// Test that default features (e.g. flagm/sb/ssbs for 8.5) can be disabled via -march. + +// RUN: %clang --target=aarch64 -march=armv8.5-a+noflagm+nosb+nossbs -c %s -### 2>&1 | FileCheck %s +// CHECK: "-triple" "aarch64" +// CHECK-SAME: "-target-feature" "+v8.5a" +// CHECK-SAME: "-target-feature" "-flagm" +// CHECK-SAME: "-target-feature" "-sb" +// CHECK-SAME: "-target-feature" "-ssbs" + +// CHECK-NOT: "-target-feature" "+flagm" +// CHECK-NOT: "-target-feature" "+sb" +// CHECK-NOT: "-target-feature" "+ssbs" From 854b4357a37e385e3f315f0a05d676ddc820457b Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 12:18:25 +0100 Subject: [PATCH 11/19] fix comment --- llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index 3f7cec9301468..71ca331461c00 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -38,8 +38,8 @@ static void CheckFeatureTree(Record *Root) { std::set SeenFeats; CollectImpliedFeatures(SeenFeats, Root); - // For processors, check that each of the mandatory (implied) features which - // is an ExtensionWithMArch is also enabled by default. + // Check that each of the mandatory (implied) features which is an + // ExtensionWithMArch is also enabled by default. auto DefaultExtsVec = Root->getValueAsListOfDefs("DefaultExts"); std::set DefaultExts{DefaultExtsVec.begin(), DefaultExtsVec.end()}; for (auto *Feat : SeenFeats) { From fccaf507f1f1485ce9f5863fbfd7dcb2647ba3aa Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 12:50:21 +0100 Subject: [PATCH 12/19] Add SSBS back to Oryon --- clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c | 1 + llvm/lib/Target/AArch64/AArch64Processors.td | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c b/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c index 7852f87e1e345..a40b9ae656353 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c @@ -49,6 +49,7 @@ // CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support // CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension // CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions +// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit // CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions // CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension // CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index c186be647c08b..82469ef49bd3e 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -1036,7 +1036,7 @@ def ProcessorFeatures { FeatureSHA3, FeatureAES, FeatureSPE, FeatureBF16, FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, - FeatureCCIDX, + FeatureSSBS, FeatureCCIDX, FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM]; // ETE and TRBE are future architecture extensions. We temporarily enable them From 485a8c08ce477eec7967b99b871e1bd1ee7ea8a8 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 14:45:20 +0100 Subject: [PATCH 13/19] fix TargetParserTests --- .../TargetParser/TargetParserTest.cpp | 76 +++++++++++-------- 1 file changed, 44 insertions(+), 32 deletions(-) diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 969982245465f..0984e420c2d07 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1141,7 +1141,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_SB, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, - AArch64::AEK_ETE, AArch64::AEK_AM}), + AArch64::AEK_ETE, AArch64::AEK_AM, + AArch64::AEK_CCIDX}), AArch64CPUTestParams("cortex-a520", "armv9.2-a", {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE, AArch64::AEK_SVE2, @@ -1156,7 +1157,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, AArch64::AEK_AM, - AArch64::AEK_ETE}), + AArch64::AEK_ETE, AArch64::AEK_CCIDX}), AArch64CPUTestParams("cortex-a520ae", "armv9.2-a", {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE, AArch64::AEK_SVE2, @@ -1171,7 +1172,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, AArch64::AEK_AM, - AArch64::AEK_ETE}), + AArch64::AEK_ETE, AArch64::AEK_CCIDX}), AArch64CPUTestParams("cortex-a57", "armv8-a", {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, @@ -1256,7 +1257,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, AArch64::AEK_SB, AArch64::AEK_I8MM, AArch64::AEK_BF16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PERFMON, AArch64::AEK_ETE}), + AArch64::AEK_PERFMON, AArch64::AEK_ETE, AArch64::AEK_CCIDX, + AArch64::AEK_SSBS}), AArch64CPUTestParams("cortex-a715", "armv9-a", {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_BF16, AArch64::AEK_SIMD, @@ -1271,7 +1273,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML, AArch64::AEK_FP16, AArch64::AEK_FLAGM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, - AArch64::AEK_ETE, AArch64::AEK_TRBE}), + AArch64::AEK_ETE, AArch64::AEK_TRBE, + AArch64::AEK_CCIDX}), AArch64CPUTestParams("cortex-a720", "armv9.2-a", {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE, AArch64::AEK_SVE2, @@ -1287,7 +1290,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, AArch64::AEK_ETE, AArch64::AEK_SPE_EEF, - AArch64::AEK_TRBE}), + AArch64::AEK_TRBE, AArch64::AEK_CCIDX}), AArch64CPUTestParams("cortex-a720ae", "armv9.2-a", {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE, AArch64::AEK_SVE2, @@ -1303,7 +1306,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, AArch64::AEK_ETE, AArch64::AEK_SPE_EEF, - AArch64::AEK_TRBE}), + AArch64::AEK_TRBE, AArch64::AEK_CCIDX}), AArch64CPUTestParams("cortex-a725", "armv9.2-a", {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE, AArch64::AEK_SVE2, @@ -1318,7 +1321,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_ETE, - AArch64::AEK_SPE_EEF, AArch64::AEK_TRBE}), + AArch64::AEK_SPE_EEF, AArch64::AEK_TRBE, + AArch64::AEK_CCIDX}), AArch64CPUTestParams( "neoverse-v1", "armv8.4-a", {AArch64::AEK_RAS, AArch64::AEK_SVE, AArch64::AEK_SSBS, @@ -1329,7 +1333,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SM4, AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_CCDP}), + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_CCDP, + AArch64::AEK_CCIDX}), AArch64CPUTestParams("neoverse-v2", "armv9-a", {AArch64::AEK_RAS, AArch64::AEK_SVE, AArch64::AEK_SSBS, AArch64::AEK_RCPC, @@ -1343,7 +1348,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SVE2BITPERM, AArch64::AEK_RAND, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, - AArch64::AEK_ETE}), + AArch64::AEK_ETE, AArch64::AEK_CCIDX}), AArch64CPUTestParams("neoverse-v3", "armv9.2-a", {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE, AArch64::AEK_SVE2, @@ -1361,7 +1366,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, AArch64::AEK_ETE, AArch64::AEK_SPE_EEF, - AArch64::AEK_RME}), + AArch64::AEK_RME, AArch64::AEK_CCIDX}), AArch64CPUTestParams("neoverse-v3ae", "armv9.2-a", {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE, AArch64::AEK_SVE2, @@ -1379,7 +1384,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, AArch64::AEK_ETE, AArch64::AEK_SPE_EEF, - AArch64::AEK_RME}), + AArch64::AEK_RME, AArch64::AEK_CCIDX}), AArch64CPUTestParams( "cortex-r82", "armv8-r", {AArch64::AEK_CRC, AArch64::AEK_RDM, AArch64::AEK_SSBS, @@ -1427,7 +1432,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML, AArch64::AEK_FLAGM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, AArch64::AEK_AM, - AArch64::AEK_ETE}), + AArch64::AEK_ETE, AArch64::AEK_CCIDX}), AArch64CPUTestParams("cortex-x3", "armv9-a", {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_BF16, AArch64::AEK_SIMD, @@ -1442,7 +1447,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PREDRES, AArch64::AEK_FLAGM, AArch64::AEK_SSBS, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, - AArch64::AEK_ETE, AArch64::AEK_TRBE}), + AArch64::AEK_ETE, AArch64::AEK_TRBE, + AArch64::AEK_CCIDX}), AArch64CPUTestParams("cortex-x4", "armv9.2-a", {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE, AArch64::AEK_SVE2, @@ -1458,7 +1464,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, AArch64::AEK_ETE, AArch64::AEK_SPE_EEF, - AArch64::AEK_TRBE}), + AArch64::AEK_TRBE, AArch64::AEK_CCIDX}), AArch64CPUTestParams("cortex-x925", "armv9.2-a", {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE, AArch64::AEK_SVE2, @@ -1473,7 +1479,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_ETE, - AArch64::AEK_SPE_EEF, AArch64::AEK_TRBE}), + AArch64::AEK_SPE_EEF, AArch64::AEK_TRBE, + AArch64::AEK_CCIDX}), AArch64CPUTestParams("cyclone", "armv8-a", {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_SIMD, @@ -1698,7 +1705,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_FP16FML, AArch64::AEK_PERFMON, - AArch64::AEK_ETE, AArch64::AEK_TRBE}), + AArch64::AEK_ETE, AArch64::AEK_TRBE, + AArch64::AEK_CCIDX}), AArch64CPUTestParams("neoverse-n3", "armv9.2-a", {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE, AArch64::AEK_SVE2, @@ -1714,7 +1722,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, AArch64::AEK_PERFMON, - AArch64::AEK_ETE, AArch64::AEK_SPE_EEF}), + AArch64::AEK_ETE, AArch64::AEK_SPE_EEF, + AArch64::AEK_CCIDX}), AArch64CPUTestParams( "ampere1", "armv8.6-a", {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16, @@ -1723,17 +1732,18 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM, AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), + AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, + AArch64::AEK_CCIDX}), AArch64CPUTestParams( "ampere1a", "armv8.6-a", - {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16, - AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, - AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, - AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16, - AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM, - AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND, - AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), + {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16, + AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, + AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, + AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM, + AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND, + AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_CCIDX}), AArch64CPUTestParams( "ampere1b", "armv8.7-a", {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16, @@ -1744,7 +1754,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND, AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_CSSC, AArch64::AEK_PERFMON, - AArch64::AEK_WFXT}), + AArch64::AEK_WFXT, AArch64::AEK_CCIDX}), AArch64CPUTestParams( "neoverse-512tvb", "armv8.4-a", {AArch64::AEK_RAS, AArch64::AEK_SVE, AArch64::AEK_SSBS, @@ -1755,7 +1765,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SM4, AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_CCDP}), + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_CCDP, + AArch64::AEK_CCIDX}), AArch64CPUTestParams("thunderx2t99", "armv8.1-a", {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_LSE, @@ -1768,7 +1779,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_RCPC, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, - AArch64::AEK_PERFMON}), + AArch64::AEK_PERFMON, AArch64::AEK_CCIDX}), AArch64CPUTestParams("thunderx", "armv8-a", {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SIMD, @@ -1811,7 +1822,7 @@ INSTANTIATE_TEST_SUITE_P( {AArch64::AEK_AES, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_PERFMON, AArch64::AEK_SHA2, AArch64::AEK_PROFILE, AArch64::AEK_CRC, AArch64::AEK_LSE, AArch64::AEK_RDM, - AArch64::AEK_RAS, AArch64::AEK_RCPC}), + AArch64::AEK_RAS, AArch64::AEK_RCPC, AArch64::AEK_CCIDX}), AArch64CPUTestParams( "oryon-1", "armv8.6-a", {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_PAUTH, @@ -1820,7 +1831,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM, AArch64::AEK_RAND, - AArch64::AEK_PROFILE, AArch64::AEK_PERFMON})), + AArch64::AEK_PROFILE, AArch64::AEK_PERFMON, AArch64::AEK_CCIDX, + AArch64::AEK_SSBS})), AArch64CPUTestParams::PrintToStringParamName); From 08bca4d685491119d0d1a7246ea2e5e6d08bdab6 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 15:13:59 +0100 Subject: [PATCH 14/19] fix SSBS test --- llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/MC/AArch64/armv8.5a-ssbs.s b/llvm/test/MC/AArch64/armv8.5a-ssbs.s index 1b24dd361e5dc..2a8b7b000646a 100644 --- a/llvm/test/MC/AArch64/armv8.5a-ssbs.s +++ b/llvm/test/MC/AArch64/armv8.5a-ssbs.s @@ -1,5 +1,5 @@ // RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1| FileCheck %s --check-prefix=NOSPECID +// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID // RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a65 < %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a65ae < %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a76 < %s | FileCheck %s From 7fa3738a9e006ddc7ab453c2f9fc2c388e55e7b7 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 15:14:21 +0100 Subject: [PATCH 15/19] fix CCIDX tests --- llvm/test/MC/AArch64/arm64-system-encoding.s | 2 +- llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s index 313ec91177460..c58a8f0cb841c 100644 --- a/llvm/test/MC/AArch64/arm64-system-encoding.s +++ b/llvm/test/MC/AArch64/arm64-system-encoding.s @@ -1,5 +1,5 @@ ; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s -; RUN: not llvm-mc -triple arm64-apple-darwin -mattr=+v8.3a -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-V83 +; RUN: not llvm-mc -triple arm64-apple-darwin -mattr=+ccidx -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-V83 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s foo: diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index c76bb0b902096..f46301e8c1c15 100644 --- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -2,7 +2,7 @@ # RUN: llvm-mc -triple=arm64 -mattr=+v8a,+fp-armv8 -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=arm64 -mattr=+v8a,+fp-armv8,+fullfp16 -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 # RUN: llvm-mc -triple=arm64 -mattr=+v8.2a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V82 -# RUN: llvm-mc -triple=arm64 -mattr=+v8.3a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V83 +# RUN: llvm-mc -triple=arm64 -mattr=+ccidx -disassemble < %s | FileCheck %s --check-prefix=CHECK-V83 #------------------------------------------------------------------------------ # Add/sub (immediate) From e79e2cad5ed69baa1e1c886e3e2f77d7bfd16dd9 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 15:14:49 +0100 Subject: [PATCH 16/19] clang-format --- .../TargetParser/TargetParserTest.cpp | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 0984e420c2d07..a1bc44834aa39 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1228,18 +1228,18 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PERFMON}), AArch64CPUTestParams( "cortex-a78", "armv8.2-a", - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, - AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, - AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), + {AArch64::AEK_CRC, AArch64::AEK_AES, + AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_RDM, + AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, + AArch64::AEK_FP16, AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, + AArch64::AEK_SSBS, AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), AArch64CPUTestParams( "cortex-a78ae", "armv8.2-a", - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, - AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, - AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), + {AArch64::AEK_CRC, AArch64::AEK_AES, + AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_RDM, + AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, + AArch64::AEK_FP16, AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, + AArch64::AEK_SSBS, AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), AArch64CPUTestParams( "cortex-a78c", "armv8.2-a", {AArch64::AEK_RAS, AArch64::AEK_CRC, AArch64::AEK_AES, From 27c150512ec24490170fed3ac27db3bd1d869cb3 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 16 Aug 2024 15:21:42 +0100 Subject: [PATCH 17/19] More clang-format --- .../TargetParser/TargetParserTest.cpp | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index a1bc44834aa39..54f7098c1ab23 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1228,18 +1228,18 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PERFMON}), AArch64CPUTestParams( "cortex-a78", "armv8.2-a", - {AArch64::AEK_CRC, AArch64::AEK_AES, - AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_RDM, - AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, - AArch64::AEK_FP16, AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, - AArch64::AEK_SSBS, AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, + AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, + AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, + AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), AArch64CPUTestParams( "cortex-a78ae", "armv8.2-a", - {AArch64::AEK_CRC, AArch64::AEK_AES, - AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_RDM, - AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, - AArch64::AEK_FP16, AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, - AArch64::AEK_SSBS, AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, + AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, + AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, + AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), AArch64CPUTestParams( "cortex-a78c", "armv8.2-a", {AArch64::AEK_RAS, AArch64::AEK_CRC, AArch64::AEK_AES, @@ -2263,9 +2263,9 @@ TEST(TargetParserTest, AArch64ArchExtFeature) { } TEST(TargetParserTest, AArch64PrintSupportedExtensions) { - std::string expected = - "All available -march extensions for AArch64\n\n" - " Name Architecture Feature(s) Description\n"; + std::string expected = "All available -march extensions for AArch64\n\n" + " Name Architecture Feature(s) " + " Description\n"; outs().flush(); testing::internal::CaptureStdout(); From 3e39b792b465b740de492adfa0fca0e2215e6274 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Sat, 17 Aug 2024 09:25:10 +0100 Subject: [PATCH 18/19] Fix apple-a12 and apple-m4 --- .../test/Driver/print-enabled-extensions/aarch64-apple-a12.c | 1 - .../test/Driver/print-enabled-extensions/aarch64-apple-m4.c | 1 - llvm/lib/Target/AArch64/AArch64Processors.td | 5 ++--- llvm/unittests/TargetParser/TargetParserTest.cpp | 5 ++--- 4 files changed, 4 insertions(+), 8 deletions(-) diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c index 27f066a310708..fcc8b674df33f 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c @@ -6,7 +6,6 @@ // CHECK-NEXT: Architecture Feature(s) Description // CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support // CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets // CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions // CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence // CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c index cc73a9edf1867..29d66dc8826a7 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c @@ -51,7 +51,6 @@ // CHECK-NEXT: FEAT_SME_F64F64 Enable Scalable Matrix Extension (SME) F64F64 instructions // CHECK-NEXT: FEAT_SME_I16I64 Enable Scalable Matrix Extension (SME) I16I64 instructions // CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions -// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit // CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions // CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension // CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 82469ef49bd3e..276e5d936c7c7 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -857,8 +857,7 @@ def ProcessorFeatures { list AppleA12 = [HasV8_3aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFullFP16, FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, - FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM, - FeatureCCIDX]; + FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM]; list AppleA13 = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFullFP16, FeatureFP16FML, FeatureSHA3, FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, @@ -905,7 +904,7 @@ def ProcessorFeatures { FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureFPAC, FeatureRAS, FeatureRCPC, FeatureRDM, - FeatureDotProd, FeatureMatMulInt8, FeatureSSBS]; + FeatureDotProd, FeatureMatMulInt8]; list ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeaturePerfMon, FeatureNEON, FeatureFPARMv8]; list ExynosM4 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd, diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 54f7098c1ab23..3ebe8322b0c3b 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1511,7 +1511,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16, AArch64::AEK_PERFMON}), AArch64CPUTestParams( "apple-a12", "armv8.3-a", - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_CCIDX, + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_FP16, AArch64::AEK_JSCVT, @@ -1652,8 +1652,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_FCMA, AArch64::AEK_PERFMON, AArch64::AEK_SME, AArch64::AEK_SME2, - AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64, - AArch64::AEK_SSBS}), + AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64}), AArch64CPUTestParams("exynos-m3", "armv8-a", {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, From b75d9cf37403abe785ee8f3c3004d2f472e40e73 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Sat, 17 Aug 2024 11:42:56 +0100 Subject: [PATCH 19/19] test changes --- clang/test/Preprocessor/aarch64-target-features.c | 4 ++-- llvm/unittests/TargetParser/TargetParserTest.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index 0bba63130e693..87bd3e142d2c4 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -327,7 +327,7 @@ // CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" // CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" "-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+vh" // CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"{{.*}}"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" -// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+ccidx" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" +// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" // CHECK-MCPU-A34: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" // CHECK-MCPU-APPLE-A13: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3" // CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" @@ -347,7 +347,7 @@ // CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+altnzcv" "-target-feature" "+ccdp" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fptoint" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+specrestrict" "-target-feature" "+ssbs" // RUN: %clang -target x86_64-apple-macosx -arch arm64_32 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64_32 %s -// CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+ccidx" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" +// CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" // RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s // RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 3ebe8322b0c3b..3d99ea8d91962 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1518,14 +1518,14 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), AArch64CPUTestParams( "apple-s4", "armv8.3-a", - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_CCIDX, + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), AArch64CPUTestParams( "apple-s5", "armv8.3-a", - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_CCIDX, + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_FP16, AArch64::AEK_JSCVT,