From 41c3501aa44be658d5d719ab9693af91309aa3bc Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 9 Jul 2024 13:03:18 +0800 Subject: [PATCH] [RISCV] Emit VP strided load in mgather combine. NFCI This combine is a duplication of the transform in RISCVGatherScatterLowering but at the SelectionDAG level, so similarly to #98111 we can replace the use of riscv_masked_strided_load with a VP strided load. Unlike #98111 we don't require #97800 or #97798 since it only operates on fixed vectors with a non-zero stride. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 7972b9abc456c..e488b9f327582 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -17060,15 +17060,16 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, SDValue BasePtr = DAG.getNode(ISD::ADD, DL, PtrVT, MGN->getBasePtr(), DAG.getConstant(Addend, DL, PtrVT)); - SDVTList VTs = DAG.getVTList({VT, MVT::Other}); - SDValue IntID = - DAG.getTargetConstant(Intrinsic::riscv_masked_strided_load, DL, - XLenVT); - SDValue Ops[] = - {MGN->getChain(), IntID, MGN->getPassThru(), BasePtr, - DAG.getConstant(StepNumerator, DL, XLenVT), MGN->getMask()}; - return DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, - Ops, VT, MGN->getMemOperand()); + SDValue EVL = DAG.getElementCount(DL, Subtarget.getXLenVT(), + VT.getVectorElementCount()); + SDValue StridedLoad = + DAG.getStridedLoadVP(VT, DL, MGN->getChain(), BasePtr, + DAG.getConstant(StepNumerator, DL, XLenVT), + MGN->getMask(), EVL, MGN->getMemOperand()); + SDValue VPSelect = DAG.getNode(ISD::VP_SELECT, DL, VT, MGN->getMask(), + StridedLoad, MGN->getPassThru(), EVL); + return DAG.getMergeValues({VPSelect, SDValue(StridedLoad.getNode(), 1)}, + DL); } }