diff --git a/stl/src/vector_algorithms.cpp b/stl/src/vector_algorithms.cpp index 65855e9aba8..5214349b768 100644 --- a/stl/src/vector_algorithms.cpp +++ b/stl/src/vector_algorithms.cpp @@ -789,8 +789,9 @@ namespace { static _Signed_t _Get_any(const __m128i _Cur) noexcept { #ifdef _M_IX86 - return static_cast<_Signed_t>((static_cast<_Unsigned_t>(_mm_extract_epi32(_Cur, 1)) << 32) - | static_cast<_Unsigned_t>(_mm_cvtsi128_si32(_Cur))); + return static_cast<_Signed_t>( + (static_cast<_Unsigned_t>(static_cast(_mm_extract_epi32(_Cur, 1))) << 32) + | static_cast<_Unsigned_t>(static_cast(_mm_cvtsi128_si32(_Cur)))); #else // ^^^ x86 ^^^ / vvv x64 vvv return static_cast<_Signed_t>(_mm_cvtsi128_si64(_Cur)); #endif // ^^^ x64 ^^^ diff --git a/tests/std/tests/VSO_0000000_vector_algorithms/test.cpp b/tests/std/tests/VSO_0000000_vector_algorithms/test.cpp index aaaee36733f..85f579ecb64 100644 --- a/tests/std/tests/VSO_0000000_vector_algorithms/test.cpp +++ b/tests/std/tests/VSO_0000000_vector_algorithms/test.cpp @@ -2,10 +2,14 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception #include -#include +#include #include +#include +#include #include +#include #include +#include #include #include #include @@ -13,6 +17,36 @@ using namespace std; +#pragma warning(disable : 4984) // 'if constexpr' is a C++17 language extension +#ifdef __clang__ +#pragma clang diagnostic ignored "-Wc++17-extensions" // constexpr if is a C++17 extension +#endif // __clang__ + +void initialize_randomness(mt19937_64& gen) { + constexpr size_t n = mt19937_64::state_size; + constexpr size_t w = mt19937_64::word_size; + static_assert(w % 32 == 0, "w should be evenly divisible by 32"); + constexpr size_t k = w / 32; + + vector vec(n * k); + + random_device rd; + generate(vec.begin(), vec.end(), ref(rd)); + + printf("This is a randomized test.\n"); + printf("DO NOT IGNORE/RERUN ANY FAILURES.\n"); + printf("You must report them to the STL maintainers.\n\n"); + + printf("Seed vector: "); + for (const auto& e : vec) { + printf("%u,", e); + } + printf("\n"); + + seed_seq seq(vec.cbegin(), vec.cend()); + gen.seed(seq); +} + #if (defined(_M_IX86) || defined(_M_X64)) && !defined(_M_CEE_PURE) extern "C" long __isa_enabled; @@ -164,10 +198,9 @@ void test_case_min_max_element(const vector& input) { template void test_min_max_element(mt19937_64& gen) { - using Distribution = conditional_t, uniform_real_distribution, - conditional_t<(sizeof(T) > 1), uniform_int_distribution, uniform_int_distribution>>; + using Limits = numeric_limits; - Distribution dis(1, 20); + uniform_int_distribution> dis(Limits::min(), Limits::max()); vector input; input.reserve(dataCount); @@ -324,9 +357,7 @@ void test_swap_ranges(mt19937_64& gen) { } } -void test_vector_algorithms() { - mt19937_64 gen(1729); - +void test_vector_algorithms(mt19937_64& gen) { test_count(gen); test_count(gen); test_count(gen); @@ -356,9 +387,6 @@ void test_vector_algorithms() { test_min_max_element(gen); test_min_max_element(gen); test_min_max_element(gen); - test_min_max_element(gen); - test_min_max_element(gen); - test_min_max_element(gen); test_min_max_element_pointers(gen); @@ -366,6 +394,13 @@ void test_vector_algorithms() { test_min_max_element_special_cases(); // AVX2 vectors test_min_max_element_special_cases(); // AVX512 vectors + // Test VSO-1558536, a regression caused by GH-2447 that was specific to 64-bit types on x86. + test_case_min_max_element(vector{10, 0x8000'0000ULL, 20, 30}); + test_case_min_max_element(vector{10, 20, 0xD000'0000'B000'0000ULL, 30, 0xC000'0000'A000'0000ULL}); + test_case_min_max_element(vector{10, 0x8000'0000LL, 20, 30}); + test_case_min_max_element( + vector{-6604286336755016904, -4365366089374418225, 6104371530830675888, -8582621853879131834}); + test_reverse(gen); test_reverse(gen); test_reverse(gen); @@ -438,18 +473,21 @@ void test_various_containers() { } int main() { - test_vector_algorithms(); + mt19937_64 gen; + initialize_randomness(gen); + + test_vector_algorithms(gen); test_various_containers(); #ifndef _M_CEE_PURE #if defined(_M_IX86) || defined(_M_X64) disable_instructions(__ISA_AVAILABLE_AVX2); - test_vector_algorithms(); + test_vector_algorithms(gen); disable_instructions(__ISA_AVAILABLE_SSE42); - test_vector_algorithms(); + test_vector_algorithms(gen); #endif // defined(_M_IX86) || defined(_M_X64) #if defined(_M_IX86) disable_instructions(__ISA_AVAILABLE_SSE2); - test_vector_algorithms(); + test_vector_algorithms(gen); #endif // defined(_M_IX86) #endif // _M_CEE_PURE }