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JSON.core
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83 lines (72 loc) · 2 KB
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CAPI=2:
# Copyright 2021 Alexander Preissner
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
#
# Licensed under the Solderpad Hardware License v 2.1 (the “License”);
# you may not use this file except in compliance with the License, or, at your
# option, the Apache License version 2.0.
# You may obtain a copy of the License at
#
# https://solderpad.org/licenses/SHL-2.1/
#
# Unless required by applicable law or agreed to in writing, any work
# distributed under the License is distributed on an “AS IS” BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
name: FPGA_Garage:util:JSON:0
description: JSON library
filesets:
pkg:
files:
- sv/util.sv
- sv/json.svh:
is_include_file: true
- sv/json.sv
file_type: systemVerilogSource
tb:
files:
- sv/json_tb.sv
file_type: systemVerilogSource
targets:
# The "default" target is special in FuseSoC and used in dependencies.
# The "&default" is a YAML anchor referenced later.
default: &default
filesets:
- pkg
# The "sim" target simulates the design. (It could have any name.)
sim: &sim
# Copy all key/value pairs from the "default" target.
<<: *default
description: Simulate the design
default_tool: xsim
filesets_append:
- tb
toplevel: json_tb
tools:
icarus:
iverilog_options:
- -g2012 # Use SystemVerilog-2012
xsim:
xelab_options:
- "--debug all"
- "--lib uvm"
TestWikipediaExample:
<<: *sim
parameters:
- UVM_TESTNAME=TestWikipediaExample
TestCommandList:
<<: *sim
parameters:
- UVM_TESTNAME=TestCommandList
parameters:
UVM_TESTNAME:
datatype: str
paramtype: plusarg
# Uncomment the following lines to have FuseSoC fetch the library
# from GitHub:
# provider:
# name: github
# user: milestone12
# repo: JSON.sv
# version: master