diff --git a/docs/cores.rst b/docs/cores.rst
index f0f0eed29..40e0d7ad6 100644
--- a/docs/cores.rst
+++ b/docs/cores.rst
@@ -1,36 +1,58 @@
-CORE-V Cores
-============
+..
+ Copyright (c) 2022, 2023 OpenHW Group
+
+ Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ https://solderpad.org/licenses/SHL-2.1/
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+
+CORE-V Cores User Manuals
+=========================
CORE-V is a family of open-source RISC-V processor cores created and maintained by open-source developers from around the world who collaborate within the `OpenHW Group ecosystem `_. As shown in the CORE-V roadmap below, there are several cores under active development.
-.. image:: images/CORE-V_Roadmap_April_2022.png
+.. comment: .. image:: images/CORE-V_Roadmap_April_2022.png
+.. image:: https://github.com/openhwgroup/core-v-cores/blob/master/CV-CORES-Roadmap_2023-04-09.png
+
+CVE4 Series
+-----------
-CVE4 Series of CORE-V Cores User Manuals
-----------------------------------------
+RTL Frozen Cores
+################
-RTL Frozen CVE4 User Manuals
-----------------------------
+`(Released) CORE-V CV32E40Pv1 User Manual `_.
-`Released CORE-V CV32E40Pv1 User Manual `_.
+RTL In Development
+##################
-RTL In Development CVE4 User Manuals
-------------------------------------
+`(Draft) CORE-V CV32E40Pv2 User Manual `_.
-`Draft CORE-V CV32E40Pv2 User Manual `_.
+`(Draft) CORE-V CV32E40S User Manual `_.
-`Draft CORE-V CV32E40S User Manual `_.
+`(Draft) CORE-V CV32E40X User Manual `_.
-`Draft CORE-V CV32E40X User Manual `_.
+CVA6 Series
+-----------
-CVA6 Series of CORE-V Cores User Manuals
-----------------------------------------
+RTL In Development
+##################
-RTL In Development CVA6 User Manuals
-------------------------------------
+`(Draft) CORE-V CVA6 User Manual `_.
-`Draft CORE-V CVA6 User Manual `_.
+CVE2 Series
+-----------
-RTL In Development CVE2 User Manuals
-------------------------------------
+RTL In Development
+##################
-`Draft CORE-V CVE2 User Manual `_.
+`(Draft) CORE-V CVE2 User Manual `_.
diff --git a/docs/index.rst b/docs/index.rst
index 6a277126d..555de0e57 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -1,3 +1,6 @@
+ Copyright (c) 2022, 2023 OpenHW Group
+ SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
CORE-V Documentation
====================
@@ -7,13 +10,15 @@ CORE-V Documentation
.. image:: images/CORE-V-landscape.jpg
-`CORE-V Docs` is the OpenHW Group documenation project for the CORE-V family of open-source RISC-V processor cores.
+`CORE-V Docs` is the top level Read the Docs project for OpenHW Group's CORE-V family of open-source RISC-V processor cores and related projects.
.. toctree::
- :maxdepth: 2
+ :maxdepth: 3
:caption: Contents:
cores
verification
+ mcu
+.. comment: devkit
.. _OpenHW Group: https://www.openhwgroup.org
diff --git a/docs/mcu.rst b/docs/mcu.rst
new file mode 100644
index 000000000..127ed407e
--- /dev/null
+++ b/docs/mcu.rst
@@ -0,0 +1,29 @@
+..
+ Copyright (c) 2023 OpenHW Group
+
+ Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ https://solderpad.org/licenses/SHL-2.1/
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+CORE-V ASIC Projects Documentation
+======================================
+
+
+CORE-V-MCU and Related Projects
+-------------------------------
+
+The CORE-V-MCU is the first of a family of MCUs built around OpenHW Group's family of CORE-V Cores.
+
+CORE-V-MCU
+##########
+`OpenHW Group CORE-V-MCU User Manual `_.
diff --git a/docs/verification.rst b/docs/verification.rst
new file mode 100644
index 000000000..69be7c251
--- /dev/null
+++ b/docs/verification.rst
@@ -0,0 +1,31 @@
+..
+ Copyright (c) 2023 OpenHW Group
+
+ Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ https://solderpad.org/licenses/SHL-2.1/
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+CORE-V Verification Projects Documentation
+==========================================
+
+CORE-V-Verif and Related
+------------------------
+
+CORE-V-Verif is the System Verilog/UVM testbench developed by the `OpenHW Group ecosystem `_ to support the verification of the CORE-V family of open-source cores.
+
+
+
+CORE-V Verif Strategy
+#####################
+
+`OpenHW Group CORE-V Verification Strategy `_.