From 946d94ce2ed6ffb2fab94fb311c904b27adbba62 Mon Sep 17 00:00:00 2001 From: DBees Date: Wed, 5 Jul 2023 19:46:43 -0700 Subject: [PATCH 1/3] Update core-v-docs RTD project to provide an up to date index --- docs/cores.rst | 3 ++- docs/index.rst | 4 +++- docs/mcu.rst | 9 +++++++++ docs/verification.rst | 10 ++++++++++ 4 files changed, 24 insertions(+), 2 deletions(-) create mode 100644 docs/mcu.rst create mode 100644 docs/verification.rst diff --git a/docs/cores.rst b/docs/cores.rst index f0f0eed29..446279512 100644 --- a/docs/cores.rst +++ b/docs/cores.rst @@ -3,7 +3,8 @@ CORE-V Cores CORE-V is a family of open-source RISC-V processor cores created and maintained by open-source developers from around the world who collaborate within the `OpenHW Group ecosystem `_. As shown in the CORE-V roadmap below, there are several cores under active development. -.. image:: images/CORE-V_Roadmap_April_2022.png +.. comment: .. image:: images/CORE-V_Roadmap_April_2022.png +.. image:: https://github.com/openhwgroup/core-v-cores/blob/master/CV-CORES-Roadmap_2023-04-09.png CVE4 Series of CORE-V Cores User Manuals ---------------------------------------- diff --git a/docs/index.rst b/docs/index.rst index 6a277126d..42d733073 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -7,7 +7,7 @@ CORE-V Documentation .. image:: images/CORE-V-landscape.jpg -`CORE-V Docs` is the OpenHW Group documenation project for the CORE-V family of open-source RISC-V processor cores. +`CORE-V Docs` is the top level Read the Docs project for OpenHW Group's CORE-V family of open-source RISC-V processor cores and related projects. .. toctree:: :maxdepth: 2 @@ -15,5 +15,7 @@ CORE-V Documentation cores verification + mcu +.. comment: devkit .. _OpenHW Group: https://www.openhwgroup.org diff --git a/docs/mcu.rst b/docs/mcu.rst new file mode 100644 index 000000000..c054eaf02 --- /dev/null +++ b/docs/mcu.rst @@ -0,0 +1,9 @@ +CORE-V-MCU Projects +=================== + +The CORE-V-MCU is the first of a family of ASICs built around OpenHW Group's family of CORE-V Cores. + + +CORE-V MCU +---------- +`OpenHW Group CORE-V-MCU User Manual `_. diff --git a/docs/verification.rst b/docs/verification.rst new file mode 100644 index 000000000..06f68cb2f --- /dev/null +++ b/docs/verification.rst @@ -0,0 +1,10 @@ +CORE-V-Verif and Related Projects +================================= + +CORE-V-Verif is the System Verilog/UVM testbench developed by the `OpenHW Group ecosystem `_ to support the verification of the CORE-V family of open-source cores. + + + +CORE-V Verif Strategy +--------------------- +`OpenHW Group CORE-V Verification Strategy `_. From 8e5d0dd2b7c48a0cfb2194c152db3e85ac33ed9b Mon Sep 17 00:00:00 2001 From: DBees Date: Thu, 6 Jul 2023 15:35:30 -0700 Subject: [PATCH 2/3] add SPDX headers --- docs/cores.rst | 18 ++++++++++++++++++ docs/index.rst | 3 +++ docs/mcu.rst | 17 +++++++++++++++++ docs/verification.rst | 17 +++++++++++++++++ 4 files changed, 55 insertions(+) diff --git a/docs/cores.rst b/docs/cores.rst index 446279512..c76985c8d 100644 --- a/docs/cores.rst +++ b/docs/cores.rst @@ -1,3 +1,21 @@ +.. + Copyright (c) 2022, 2023 OpenHW Group + + Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://solderpad.org/licenses/SHL-2.1/ + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + + CORE-V Cores ============ diff --git a/docs/index.rst b/docs/index.rst index 42d733073..fa759469c 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,3 +1,6 @@ + Copyright (c) 2022, 2023 OpenHW Group + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + CORE-V Documentation ==================== diff --git a/docs/mcu.rst b/docs/mcu.rst index c054eaf02..b5bf37a17 100644 --- a/docs/mcu.rst +++ b/docs/mcu.rst @@ -1,3 +1,20 @@ +.. + Copyright (c) 2023 OpenHW Group + + Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://solderpad.org/licenses/SHL-2.1/ + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + CORE-V-MCU Projects =================== diff --git a/docs/verification.rst b/docs/verification.rst index 06f68cb2f..406771db6 100644 --- a/docs/verification.rst +++ b/docs/verification.rst @@ -1,3 +1,20 @@ +.. + Copyright (c) 2023 OpenHW Group + + Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://solderpad.org/licenses/SHL-2.1/ + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + CORE-V-Verif and Related Projects ================================= From 011381832d2056af6f12e81b7ce8ca469403024d Mon Sep 17 00:00:00 2001 From: DBees Date: Thu, 6 Jul 2023 16:41:06 -0700 Subject: [PATCH 3/3] Update TOC structure --- docs/cores.rst | 43 +++++++++++++++++++++++-------------------- docs/index.rst | 2 +- docs/mcu.rst | 13 ++++++++----- docs/verification.rst | 10 +++++++--- 4 files changed, 39 insertions(+), 29 deletions(-) diff --git a/docs/cores.rst b/docs/cores.rst index c76985c8d..40e0d7ad6 100644 --- a/docs/cores.rst +++ b/docs/cores.rst @@ -16,40 +16,43 @@ SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -CORE-V Cores -============ +CORE-V Cores User Manuals +========================= CORE-V is a family of open-source RISC-V processor cores created and maintained by open-source developers from around the world who collaborate within the `OpenHW Group ecosystem `_. As shown in the CORE-V roadmap below, there are several cores under active development. .. comment: .. image:: images/CORE-V_Roadmap_April_2022.png .. image:: https://github.com/openhwgroup/core-v-cores/blob/master/CV-CORES-Roadmap_2023-04-09.png -CVE4 Series of CORE-V Cores User Manuals ----------------------------------------- +CVE4 Series +----------- -RTL Frozen CVE4 User Manuals ----------------------------- +RTL Frozen Cores +################ -`Released CORE-V CV32E40Pv1 User Manual `_. +`(Released) CORE-V CV32E40Pv1 User Manual `_. -RTL In Development CVE4 User Manuals ------------------------------------- +RTL In Development +################## -`Draft CORE-V CV32E40Pv2 User Manual `_. +`(Draft) CORE-V CV32E40Pv2 User Manual `_. -`Draft CORE-V CV32E40S User Manual `_. +`(Draft) CORE-V CV32E40S User Manual `_. -`Draft CORE-V CV32E40X User Manual `_. +`(Draft) CORE-V CV32E40X User Manual `_. -CVA6 Series of CORE-V Cores User Manuals ----------------------------------------- +CVA6 Series +----------- -RTL In Development CVA6 User Manuals ------------------------------------- +RTL In Development +################## -`Draft CORE-V CVA6 User Manual `_. +`(Draft) CORE-V CVA6 User Manual `_. -RTL In Development CVE2 User Manuals ------------------------------------- +CVE2 Series +----------- -`Draft CORE-V CVE2 User Manual `_. +RTL In Development +################## + +`(Draft) CORE-V CVE2 User Manual `_. diff --git a/docs/index.rst b/docs/index.rst index fa759469c..555de0e57 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -13,7 +13,7 @@ CORE-V Documentation `CORE-V Docs` is the top level Read the Docs project for OpenHW Group's CORE-V family of open-source RISC-V processor cores and related projects. .. toctree:: - :maxdepth: 2 + :maxdepth: 3 :caption: Contents: cores diff --git a/docs/mcu.rst b/docs/mcu.rst index b5bf37a17..127ed407e 100644 --- a/docs/mcu.rst +++ b/docs/mcu.rst @@ -15,12 +15,15 @@ SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -CORE-V-MCU Projects -=================== +CORE-V ASIC Projects Documentation +====================================== -The CORE-V-MCU is the first of a family of ASICs built around OpenHW Group's family of CORE-V Cores. +CORE-V-MCU and Related Projects +------------------------------- -CORE-V MCU ----------- +The CORE-V-MCU is the first of a family of MCUs built around OpenHW Group's family of CORE-V Cores. + +CORE-V-MCU +########## `OpenHW Group CORE-V-MCU User Manual `_. diff --git a/docs/verification.rst b/docs/verification.rst index 406771db6..69be7c251 100644 --- a/docs/verification.rst +++ b/docs/verification.rst @@ -15,13 +15,17 @@ SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -CORE-V-Verif and Related Projects -================================= +CORE-V Verification Projects Documentation +========================================== + +CORE-V-Verif and Related +------------------------ CORE-V-Verif is the System Verilog/UVM testbench developed by the `OpenHW Group ecosystem `_ to support the verification of the CORE-V family of open-source cores. CORE-V Verif Strategy ---------------------- +##################### + `OpenHW Group CORE-V Verification Strategy `_.