From 7dbc7307c787fc18d23312c8224ad5d6088ef979 Mon Sep 17 00:00:00 2001 From: pthierry Date: Thu, 11 Jul 2024 10:05:05 +0200 Subject: [PATCH] ci: coverage: adding codecov et basic UT --- .github/codecov.yml | 15 + pyproject.toml | 1 + tests/dts/sample.dts | 1007 ++++++++++++++++++++++++++++++++++++++++ tests/test_load.py | 17 + tests/test_template.py | 8 - tox.ini | 2 +- 6 files changed, 1041 insertions(+), 9 deletions(-) create mode 100644 .github/codecov.yml create mode 100644 tests/dts/sample.dts create mode 100644 tests/test_load.py delete mode 100644 tests/test_template.py diff --git a/.github/codecov.yml b/.github/codecov.yml new file mode 100644 index 0000000..284dab6 --- /dev/null +++ b/.github/codecov.yml @@ -0,0 +1,15 @@ +# SPDX-FileCopyrightText: 2024 Ledger SAS +# +# SPDX-License-Identifier: Apache-2.0 + +coverage: + status: + project: + default: + informational: true + patch: + default: + informational: true +comment: false +github_checks: + annotations: false diff --git a/pyproject.toml b/pyproject.toml index da018de..6fc784c 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -39,6 +39,7 @@ devel = [ "flake8-html>=0.4.3", "mypy>=1.8.0", "pytest>=4.6", + "pytest-cov>=5.0.0", "black>=24.2,<25.0", "cachetools>=5.3", "lxml>=4.8.0", diff --git a/tests/dts/sample.dts b/tests/dts/sample.dts new file mode 100644 index 0000000..1c68ef1 --- /dev/null +++ b/tests/dts/sample.dts @@ -0,0 +1,1007 @@ +// SPDX-FileCopyrightText: 2023 Ledger SAS +// SPDX-License-Identifier: Apache-2.0 + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; +}; +/ { + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&nvic>; + ranges; + nvic: interrupt-controller@e000e100 { + #address-cells = <1>; + compatible = "arm,v8m-nvic"; + reg = <0xe000e100 0xc00>; + interrupt-controller; + #interrupt-cells = <2>; + }; + systick: timer@e000e010 { + compatible = "arm,armv8m-systick"; + reg = <0xe000e010 0x10>; + }; + }; +}; +/ { + chosen { + zephyr,entropy = &rng; + zephyr,flash-controller = &flash; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + cpu-power-states = <&stop0 &stop1 &stop2>; + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + arm,num-mpu-regions = <8>; + }; + }; + power-states { + stop0: state0 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <1>; + min-residency-us = <100>; + }; + stop1: state1 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <2>; + min-residency-us = <500>; + }; + stop2: state2 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <3>; + min-residency-us = <900>; + }; + }; + }; + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "st,stm32-hse-clock"; + status = "disabled"; + }; + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <((16) * 1000 * 1000)>; + status = "disabled"; + }; + clk_hsi48: clk-hsi48 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <((48) * 1000 * 1000)>; + status = "disabled"; + }; + clk_msis: clk-msis { + #clock-cells = <0>; + compatible = "st,stm32u5-msi-clock"; + msi-range = <4>; + status = "disabled"; + }; + clk_msik: clk-msik { + #clock-cells = <0>; + compatible = "st,stm32u5-msi-clock"; + msi-range = <4>; + status = "disabled"; + }; + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "st,stm32-lse-clock"; + clock-frequency = <32768>; + driving-capability = <2>; + status = "disabled"; + }; + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <((32) * 1000)>; + status = "disabled"; + }; + pll1: pll: pll { + #clock-cells = <0>; + compatible = "st,stm32u5-pll-clock"; + status = "disabled"; + }; + pll2: pll2 { + #clock-cells = <0>; + compatible = "st,stm32u5-pll-clock"; + status = "disabled"; + }; + pll3: pll3 { + #clock-cells = <0>; + compatible = "st,stm32u5-pll-clock"; + status = "disabled"; + }; + }; + soc { + flash: flash-controller@40022000 { + compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller"; + reg = <0x40022000 0x400>; + interrupts = <6 0>; + #address-cells = <1>; + #size-cells = <1>; + flash0: flash@8000000 { + compatible = "st,stm32-nv-flash", "soc-nv-flash"; + write-block-size = <16>; + erase-block-size = <8192>; + max-erase-time = <5>; + }; + }; + syscfg: system-config@46000400 { + compatible = "st,stm32u5-syscfg", "syscon"; + reg = <0x46000400 0x800>; + }; + rcc: rcc@46020c00 { + compatible = "st,stm32u5-rcc"; + clocks-controller; + #clock-cells = <2>; + reg = <0x46020c00 0x400>; + rctl: reset-controller { + compatible = "st,stm32-rcc-rctl"; + #reset-cells = <1>; + }; + }; + exti: interrupt-controller@46022000 { + compatible = "st,stm32g0-exti", "st,stm32-exti"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + reg = <0x46022000 0x400>; + num-lines = <16>; + interrupts = <11 0>, <12 0>, <13 0>, <14 0>, + <15 0>, <16 0>, <17 0>, <18 0>, + <19 0>, <20 0>, <21 0>, <22 0>, + <23 0>, <24 0>, <25 0>, <26 0>; + interrupt-names = "line0", "line1", "line2", "line3", + "line4", "line5", "line6", "line7", + "line8", "line9", "line10", "line11", + "line12", "line13", "line14", "line15"; + line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, + <4 1>, <5 1>, <6 1>, <7 1>, + <8 1>, <9 1>, <10 1>, <11 1>, + <12 1>, <13 1>, <14 1>, <15 1>; + }; + pinctrl: pin-controller@42020000 { + compatible = "st,stm32-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x42020000 0x2000>; + gpioa: gpio@42020000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42020000 0x400>; + clocks = <&rcc 0x08C 0x00000001>; + }; + gpiob: gpio@42020400 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42020400 0x400>; + clocks = <&rcc 0x08C 0x00000002>; + }; + gpioc: gpio@42020800 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42020800 0x400>; + clocks = <&rcc 0x08C 0x00000004>; + }; + gpiod: gpio@42020c00 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42020c00 0x400>; + clocks = <&rcc 0x08C 0x00000008>; + }; + gpioe: gpio@42021000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42021000 0x400>; + clocks = <&rcc 0x08C 0x00000010>; + }; + gpiof: gpio@42021400 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42021400 0x400>; + clocks = <&rcc 0x08C 0x00000020>; + }; + gpiog: gpio@42021800 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42021800 0x400>; + clocks = <&rcc 0x08C 0x00000040>; + }; + gpioh: gpio@42021c00 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42021c00 0x400>; + clocks = <&rcc 0x08C 0x00000080>; + }; + gpioi: gpio@42022000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42022000 0x400>; + clocks = <&rcc 0x08C 0x00000100>; + }; + }; + iwdg: watchdog@40003000 { + compatible = "st,stm32-watchdog"; + reg = <0x40003000 0x400>; + status = "disabled"; + }; + wwdg: wwdg1: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002c00 0x1000>; + clocks = <&rcc 0x09C 0x00000800>; + interrupts = <0 7>; + status = "disabled"; + }; + backup_sram: memory@40036400 { + compatible = "zephyr,memory-region", "st,stm32-backup-sram"; + reg = <0x40036400 ((2) * 1024)>; + clocks = <&rcc 0x088 0x10020000>; + zephyr,memory-region = "BACKUP_SRAM"; + status = "disabled"; + }; + usart1: serial@40013800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40013800 0x400>; + clocks = <&rcc 0x0A4 0x00004000>; + resets = <&rctl (((0x7C) << 5U) | (14U))>; + interrupts = <61 0>; + status = "disabled"; + }; + usart2: serial@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + clocks = <&rcc 0x09C 0x00020000>; + resets = <&rctl (((0x74) << 5U) | (17U))>; + interrupts = <62 0>; + status = "disabled"; + }; + usart3: serial@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + clocks = <&rcc 0x09C 0x00040000>; + resets = <&rctl (((0x74) << 5U) | (18U))>; + interrupts = <63 0>; + status = "disabled"; + }; + uart4: serial@40004c00 { + compatible = "st,stm32-uart"; + reg = <0x40004c00 0x400>; + clocks = <&rcc 0x09C 0x00080000>; + resets = <&rctl (((0x74) << 5U) | (19U))>; + interrupts = <64 0>; + status = "disabled"; + }; + uart5: serial@40005000 { + compatible = "st,stm32-uart"; + reg = <0x40005000 0x400>; + clocks = <&rcc 0x09C 0x00100000>; + resets = <&rctl (((0x74) << 5U) | (20U))>; + interrupts = <65 0>; + status = "disabled"; + }; + lpuart1: serial@46002400 { + compatible = "st,stm32-lpuart", "st,stm32-uart"; + reg = <0x46002400 0x400>; + clocks = <&rcc 0x0A8 0x00000040>; + resets = <&rctl (((0x80) << 5U) | (6U))>; + interrupts = <66 0>; + status = "disabled"; + }; + spi1: spi@40013000 { + compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40013000 0x400>; + interrupts = <59 5>; + clocks = <&rcc 0x0A4 0x00001000>; + status = "disabled"; + }; + spi2: spi@40003800 { + compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + interrupts = <60 5>; + clocks = <&rcc 0x09C 0x00004000>; + status = "disabled"; + }; + spi3: spi@46002000 { + compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x46002000 0x400>; + interrupts = <99 5>; + clocks = <&rcc 0x0A8 0x00000020>; + status = "disabled"; + }; + i2c1: i2c@40005400 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005400 0x400>; + clocks = <&rcc 0x09C 0x00200000>; + interrupts = <55 0>, <56 0>; + interrupt-names = "event", "error"; + status = "disabled"; + }; + i2c2: i2c@40005800 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005800 0x400>; + clocks = <&rcc 0x09C 0x00400000>; + interrupts = <57 0>, <58 0>; + interrupt-names = "event", "error"; + status = "disabled"; + }; + i2c3: i2c@46002800 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x46002800 0x400>; + clocks = <&rcc 0x0A8 0x00000080>; + interrupts = <88 0>, <89 0>; + interrupt-names = "event", "error"; + status = "disabled"; + }; + i2c4: i2c@40008400 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40008400 0x400>; + clocks = <&rcc 0x0A0 0x00000002>; + interrupts = <101 0>, <100 0>; + interrupt-names = "event", "error"; + status = "disabled"; + }; + lptim1: timers@46004400 { + compatible = "st,stm32-lptim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x46004400 0x400>; + clocks = <&rcc 0x0A8 0x00000800>; + interrupts = <67 1>; + interrupt-names = "wakeup"; + st,static-prescaler; + status = "disabled"; + }; + lptim2: timers@40009400 { + compatible = "st,stm32-lptim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40009400 0x400>; + clocks = <&rcc 0x0A0 0x00000200>; + interrupts = <68 0>; + interrupt-names = "global"; + st,static-prescaler; + status = "disabled"; + }; + lptim3: timers@46004800 { + compatible = "st,stm32-lptim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x46004800 0x400>; + clocks = <&rcc 0x0A8 0x00001000>; + interrupts = <98 0>; + interrupt-names = "global"; + st,static-prescaler; + status = "disabled"; + }; + lptim4: timers@46004c00 { + compatible = "st,stm32-lptim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x46004c00 0x400>; + clocks = <&rcc 0x0A8 0x00002000>; + interrupts = <110 0>; + interrupt-names = "global"; + st,static-prescaler; + status = "disabled"; + }; + rtc: rtc@46007800 { + compatible = "st,stm32-rtc"; + reg = <0x46007800 0x400>; + interrupts = <2 0>; + clocks = <&rcc 0x0A8 0x00200000>; + prescaler = <32768>; + status = "disabled"; + }; + timers1: timers@40012c00 { + compatible = "st,stm32-timers"; + reg = <0x40012c00 0x400>; + clocks = <&rcc 0x0A4 0x00000800>; + resets = <&rctl (((0x7C) << 5U) | (11U))>; + interrupts = <41 0>, <42 0>, <43 0>, <44 0>; + interrupt-names = "brk", "up", "trgcom", "cc"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + timers2: timers@40000000 { + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc 0x09C 0x00000001>; + resets = <&rctl (((0x74) << 5U) | (0U))>; + interrupts = <45 0>; + interrupt-names = "global"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + timers3: timers@40000400 { + compatible = "st,stm32-timers"; + reg = <0x40000400 0x400>; + clocks = <&rcc 0x09C 0x00000002>; + resets = <&rctl (((0x74) << 5U) | (1U))>; + interrupts = <46 0>; + interrupt-names = "global"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + timers4: timers@40000800 { + compatible = "st,stm32-timers"; + reg = <0x40000800 0x400>; + clocks = <&rcc 0x09C 0x00000004>; + resets = <&rctl (((0x74) << 5U) | (2U))>; + interrupts = <47 0>; + interrupt-names = "global"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; + timers5: timers@40000c00 { + compatible = "st,stm32-timers"; + reg = <0x40000c00 0x400>; + clocks = <&rcc 0x09C 0x00000008>; + resets = <&rctl (((0x74) << 5U) | (3U))>; + interrupts = <48 0>; + interrupt-names = "global"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; + timers6: timers@40001000 { + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc 0x09C 0x00000010>; + resets = <&rctl (((0x74) << 5U) | (4U))>; + interrupts = <49 0>; + interrupt-names = "global"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + timers7: timers@40001400 { + compatible = "st,stm32-timers"; + reg = <0x40001400 0x400>; + clocks = <&rcc 0x09C 0x00000020>; + resets = <&rctl (((0x74) << 5U) | (5U))>; + interrupts = <50 0>; + interrupt-names = "global"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + timers8: timers@40013400 { + compatible = "st,stm32-timers"; + reg = <0x40013400 0x400>; + clocks = <&rcc 0x0A4 0x00002000>; + resets = <&rctl (((0x7C) << 5U) | (13U))>; + interrupts = <51 0>, <52 0>, <53 0>, <54 0>; + interrupt-names = "brk", "up", "trgcom", "cc"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + }; + timers15: timers@40014000 { + compatible = "st,stm32-timers"; + reg = <0x40014000 0x400>; + clocks = <&rcc 0x0A4 0x00010000>; + resets = <&rctl (((0x7C) << 5U) | (16U))>; + interrupts = <69 0>; + interrupt-names = "global"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; + timers16: timers@40014400 { + compatible = "st,stm32-timers"; + reg = <0x40014400 0x400>; + clocks = <&rcc 0x0A4 0x00020000>; + resets = <&rctl (((0x7C) << 5U) | (17U))>; + interrupts = <70 0>; + interrupt-names = "global"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; + timers17: timers@40014800 { + compatible = "st,stm32-timers"; + reg = <0x40014800 0x400>; + clocks = <&rcc 0x0A4 0x00040000>; + resets = <&rctl (((0x7C) << 5U) | (18U))>; + interrupts = <71 0>; + interrupt-names = "global"; + status = "disabled"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + #pwm-cells = <3>; + }; + counter { + compatible = "st,stm32-counter"; + status = "disabled"; + }; + }; + octospi1: octospi@420d1400 { + compatible = "st,stm32-ospi"; + reg = <0x420d1400 0x400>; + interrupts = <76 0>; + clock-names = "ospix", "ospi-ker", "ospi-mgr"; + clocks = <&rcc 0x090 0x00000010>, + <&rcc 0x011 ((((0xE4) & 0xFFU) << 0U) | (((20) & 0x1FU) << 8U) | (((3) & 0x7U) << 13U) | (((0) & 0x7U) << 16U))>, + <&rcc 0x08C 0x00200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + octospi2: octospi@420d2400 { + compatible = "st,stm32-ospi"; + reg = <0x420d2400 0x400>; + interrupts = <120 0>; + clock-names = "ospix", "ospi-ker", "ospi-mgr"; + clocks = <&rcc 0x090 0x00000100>, + <&rcc 0x011 ((((0xE4) & 0xFFU) << 0U) | (((20) & 0x1FU) << 8U) | (((3) & 0x7U) << 13U) | (((0) & 0x7U) << 16U))>, + <&rcc 0x08C 0x00200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + aes: aes@420c0000 { + compatible = "st,stm32-aes"; + reg = <0x420c0000 0x400>; + clocks = <&rcc 0x08C 0x00010000>; + interrupts = <93 0>; + status = "disabled"; + }; + rng: rng@420c0800 { + compatible = "st,stm32-rng"; + reg = <0x420c0800 0x400>; + clocks = <&rcc 0x08C 0x00040000>; + interrupts = <94 0>; + nist-config = <0xf60d00>; + health-test-config = <0x9aae>; + status = "disabled"; + }; + dac1: dac@46021800 { + compatible = "st,stm32-dac"; + reg = <0x46021800 0x400>; + clocks = <&rcc 0x094 0x00000040>; + status = "disabled"; + #io-channel-cells = <1>; + }; + adc1: adc@42028000 { + compatible = "st,stm32-adc"; + reg = <0x42028000 0x400>; + clocks = <&rcc 0x08C 0x00000400>; + interrupts = <37 0>; + status = "disabled"; + #io-channel-cells = <1>; + resolutions = <((((0x0C) & ((1 << (8)) - 1)) << 0U) | (((2) & ((1 << (5)) - 1)) << 8U) | (((((1 << (2)) - 1)) & ((1 << (3)) - 1)) << 13U) | (((0x00) & ((1 << (3)) - 1)) << 16U) | (((14) & ((1 << (13)) - 1)) << 19U)) + ((((0x0C) & ((1 << (8)) - 1)) << 0U) | (((2) & ((1 << (5)) - 1)) << 8U) | (((((1 << (2)) - 1)) & ((1 << (3)) - 1)) << 13U) | (((0x01) & ((1 << (3)) - 1)) << 16U) | (((12) & ((1 << (13)) - 1)) << 19U)) + ((((0x0C) & ((1 << (8)) - 1)) << 0U) | (((2) & ((1 << (5)) - 1)) << 8U) | (((((1 << (2)) - 1)) & ((1 << (3)) - 1)) << 13U) | (((0x02) & ((1 << (3)) - 1)) << 16U) | (((10) & ((1 << (13)) - 1)) << 19U)) + ((((0x0C) & ((1 << (8)) - 1)) << 0U) | (((2) & ((1 << (5)) - 1)) << 8U) | (((((1 << (2)) - 1)) & ((1 << (3)) - 1)) << 13U) | (((0x03) & ((1 << (3)) - 1)) << 16U) | (((8) & ((1 << (13)) - 1)) << 19U))>; + sampling-times = <5 6 12 20 36 68 391 814>; + st,adc-clock-source = <2>; + st,adc-sequencer = <1>; + }; + adc4: adc@46021000 { + compatible = "st,stm32-adc"; + reg = <0x46021000 0x400>; + clocks = <&rcc 0x094 0x00000020>; + interrupts = <113 0>; + status = "disabled"; + #io-channel-cells = <1>; + resolutions = <((((0x0C) & ((1 << (8)) - 1)) << 0U) | (((2) & ((1 << (5)) - 1)) << 8U) | (((((1 << (2)) - 1)) & ((1 << (3)) - 1)) << 13U) | (((0x00) & ((1 << (3)) - 1)) << 16U) | (((12) & ((1 << (13)) - 1)) << 19U)) + ((((0x0C) & ((1 << (8)) - 1)) << 0U) | (((2) & ((1 << (5)) - 1)) << 8U) | (((((1 << (2)) - 1)) & ((1 << (3)) - 1)) << 13U) | (((0x01) & ((1 << (3)) - 1)) << 16U) | (((10) & ((1 << (13)) - 1)) << 19U)) + ((((0x0C) & ((1 << (8)) - 1)) << 0U) | (((2) & ((1 << (5)) - 1)) << 8U) | (((((1 << (2)) - 1)) & ((1 << (3)) - 1)) << 13U) | (((0x02) & ((1 << (3)) - 1)) << 16U) | (((8) & ((1 << (13)) - 1)) << 19U)) + ((((0x0C) & ((1 << (8)) - 1)) << 0U) | (((2) & ((1 << (5)) - 1)) << 8U) | (((((1 << (2)) - 1)) & ((1 << (3)) - 1)) << 13U) | (((0x03) & ((1 << (3)) - 1)) << 16U) | (((6) & ((1 << (13)) - 1)) << 19U))>; + sampling-times = <2 4 8 13 20 40 80 815>; + num-sampling-time-common-channels = <2>; + st,adc-clock-source = <2>; + st,adc-sequencer = <0>; + }; + fdcan1: can@4000a400 { + compatible = "st,stm32-fdcan"; + reg = <0x4000a400 0x400>, <0x4000ac00 0x350>; + reg-names = "m_can", "message_ram"; + interrupts = <39 0>, <40 0>; + interrupt-names = "LINE_0", "LINE_1"; + clocks = <&rcc 0x0A0 0x00000200>; + bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; + sjw = <1>; + sample-point = <875>; + sjw-data = <1>; + sample-point-data = <875>; + status = "disabled"; + }; + ucpd1: ucpd@4000dc00 { + compatible = "st,stm32-ucpd"; + reg = <0x4000dc00 0x400>; + clocks = <&rcc 0x09C 0x00800000>; + interrupts = <106 0>; + status = "disabled"; + }; + gpdma1: dma@40020000 { + compatible = "st,stm32u5-dma"; + #dma-cells = <3>; + reg = <0x40020000 0x400>; + interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0 + 80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>; + clocks = <&rcc 0x088 0x1>; + dma-channels = <16>; + dma-requests = <114>; + dma-offset = <0>; + status = "disabled"; + }; + fmc: memory-controller@420d0400 { + compatible = "st,stm32-fmc"; + reg = <0x420d0400 0x400>; + clocks = <&rcc 0x090 0x00000001>; + status = "disabled"; + sram { + compatible = "st,stm32-fmc-nor-psram"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + }; + die_temp: dietemp { + compatible = "st,stm32-temp-cal"; + ts-cal1-addr = <0x0BFA0710>; + ts-cal2-addr = <0x0BFA0742>; + ts-cal1-temp = <30>; + ts-cal2-temp = <130>; + ts-cal-vrefanalog = <3000>; + ts-cal-resolution = <14>; + io-channels = <&adc1 19>; + status = "disabled"; + }; + vref1: vref_1 { + compatible = "st,stm32-vref"; + vrefint-cal-addr = <0x0BFA07A5>; + vrefint-cal-mv = <3000>; + io-channels = <&adc1 0>; + status = "disabled"; + }; + vref4: vref_4 { + compatible = "st,stm32-vref"; + vrefint-cal-addr = <0x0BFA07A5>; + vrefint-cal-mv = <3000>; + io-channels = <&adc4 0>; + status = "disabled"; + }; + vbat1: vbat_1 { + compatible = "st,stm32-vbat"; + ratio = <4>; + io-channels = <&adc1 18>; + status = "disabled"; + }; + vbat4: vbat_4 { + compatible = "st,stm32-vbat"; + ratio = <4>; + io-channels = <&adc4 14>; + status = "disabled"; + }; +}; +&nvic { + arm,num-irq-priority-bits = <4>; +}; +/ { + soc { + pinctrl: pin-controller@42020000 { + compatible = "st,stm32-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x42020000 0x2800>; + gpioj: gpio@42022400 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42022400 0x400>; + clocks = <&rcc 0x08C 0x00000200>; + }; + }; + usart6: serial@40006400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40006400 0x400>; + clocks = <&rcc 0x09C 0x02000000>; + resets = <&rctl (((0x74) << 5U) | (25U))>; + interrupts = <126 0>; + status = "disabled"; + }; + i2c5: i2c@40009800 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40009800 0x400>; + clocks = <&rcc 0x0A0 0x00000040>; + interrupts = <128 0>, <127 0>; + interrupt-names = "event", "error"; + status = "disabled"; + }; + i2c6: i2c@40009c00 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40009c00 0x400>; + clocks = <&rcc 0x0A0 0x00000080>; + interrupts = <130 0>, <129 0>; + interrupt-names = "event", "error"; + status = "disabled"; + }; + }; +}; +/{ + chosen { + sentry,kernelram_section = <&kernel_ram>; + sentry,idleram_section = <&idle_ram>; + sentry,autotestram_section = <&autotest_ram>; + sentry,kernelcode_section = <&kernel_code>; + sentry,idlecode_section = <&idle_code>; + sentry,autotestcode_section = <&autotest_code>; + }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + kernel_code: kernel_code@8000000 { + reg = <0x8000000 0x8000>; + compatible = "outpost,memory-pool"; + }; + idle_code: idle_code@8008000 { + reg = <0x8008000 0x300>; + compatible = "outpost,memory-pool"; + }; + autotest_code: autotest_code@800a000 { + reg = <0x800a000 0xe000>; + compatible = "outpost,memory-pool"; + }; + kernel_ram: kernel_memory@20000000 { + reg = <0x20000000 0x2000>; + compatible = "outpost,memory-pool"; + }; + idle_ram: idle_memory@20004000 { + reg = <0x20004000 0x200>; + compatible = "outpost,memory-pool"; + }; + autotest_ram: autotest_memory@20008000 { + reg = <0x20008000 0x1000>; + compatible = "outpost,memory-pool"; + }; + }; +}; +/{ + chosen { + sentry,debug_stdout = <&lpuart1>; + }; + aliases { + pll = &pll1; + }; + led0: led_0 { + compatible = "gpio-leds"; + outpost,owner = <0xbabe>; + pinctrl-0 = <&led_pc7 &led_pc7>; + status = "disabled"; + }; +}; +/{ + reserved-memory { + shm_autotest_1: memory@2000a000 { + reg = <0x2000a000 0x256>; + dma-pool; + outpost,shm; + outpost,label = <0xf00>; + outpost,owner = <0xbabe>; + }; + shm_autotest_2: memory@2000b000 { + reg = <0x2000b000 0x100>; + outpost,shm; + dma-pool; + outpost,no-map; + outpost,label = <0xf01>; + outpost,owner = <0xbabe>; + }; + shm_autotest_3: memory@2000b100 { + reg = <0x2000b100 0x100>; + outpost,shm; + outpost,label = <0xf02>; + outpost,owner = <0xbabe>; + }; + }; +}; +&led0 { + status = "okay"; +}; +&flash0 { + reg = <0x08000000 ((4) * 1024 * 1024)>; +}; +&sram0 { + reg = <0x20000000 ((2514) * 1024)>; +}; +&clk_lsi { + status = "okay"; +}; +&clk_hsi { + status = "okay"; +}; +&clk_hse { + status = "okay"; +}; +&clk_msis { + status = "okay"; +}; +&pll1 { + status = "okay"; +}; +&pll3 { + status = "okay"; +}; +&flash { + wait-state = <4>; + status = "okay"; +}; +&i2c1 { + status = "okay"; + outpost,owner = <0xbabe>; +}; +&rcc { + clocks = <&pll1>; + clock-frequency = <((160) * 1000 * 1000)>; + bus-prescalers = <0>, <0>, <0>, <0>; + bus-names = "ahb", "apb1", "apb2", "apb3"; + status = "okay"; +}; +&exti { + events = <26>; + status = "okay"; +}; +&gpioa { + status = "okay"; +}; +&gpiob { + status = "okay"; +}; +&gpioc { + status = "okay"; +}; +&gpiod { + status = "okay"; +}; +&gpioe { + status = "okay"; +}; +&gpiof { + status = "okay"; +}; +&gpiog { + status = "okay"; +}; +&usart1{ + status = "okay"; + pinctrl-0 = <&usart1_tx_pa9>, <&usart1_rx_pa10>; +}; +&lpuart1{ + status = "okay"; + pinctrl-0 = <&lpuart1_tx>, <&lpuart1_rx>; +}; +&pinctrl { + usart1_tx_pa9: usart1_tx_pa9 { + pinmux = <&gpioa 9 0x2 7>; + pincfg = <0x0 0x3 0x0>; + }; + usart1_rx_pa10: usart1_rx_pa10 { + pinmux = <&gpioa 10 0x2 7>; + pincfg = <0x0 0x3 0x0>; + }; + lpuart1_tx: lpuart1_tx { + pinmux = <&gpioc 1 0x2 8>; + pincfg = <0x0 0x3 0x0>; + }; + lpuart1_rx: lpuart1_rx { + pinmux = <&gpioc 0 0x2 8>; + pincfg = <0x0 0x3 0x0>; + }; + led_pc7: led_pc7 { + pinmux = <&gpioc 7 0x1 0x0>; + pincfg = <0x0 0x3 0x0>; + }; +}; +&rng { + status = "okay"; +}; +&syscfg { + status = "okay"; +}; diff --git a/tests/test_load.py b/tests/test_load.py new file mode 100644 index 0000000..c23f2ef --- /dev/null +++ b/tests/test_load.py @@ -0,0 +1,17 @@ +# SPDX-FileCopyrightText: 2023 - 2024 Ledger SAS +# +# SPDX-License-Identifier: Apache-2.0 + +# flake8: noqa + +import pathlib +import dts_utils + + +def test_dtsload(): + dts = dts_utils.Dts(pathlib.Path(__file__).parent.absolute() / "dts/sample.dts") + + +def test_socload(): + dts = dts_utils.Dts(pathlib.Path(__file__).parent.absolute() / "dts/sample.dts") + soc = dts.soc diff --git a/tests/test_template.py b/tests/test_template.py deleted file mode 100644 index 729091d..0000000 --- a/tests/test_template.py +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-FileCopyrightText: 2023 - 2024 Ledger SAS -# -# SPDX-License-Identifier: Apache-2.0 - - -def test_empty(): - """There is no unittests yet.""" - pass diff --git a/tox.ini b/tox.ini index ee20936..c5e1fa1 100644 --- a/tox.ini +++ b/tox.ini @@ -20,7 +20,7 @@ extras = devel [testenv:unittests] commands = - pytest --tb=long -v {posargs} + pytest --cov=dts_utils --tb=long -v {posargs} [testenv:htmlcov] commands =