From 54a233a83566a68436d0d68159d680277c2292a8 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 23 Mar 2024 19:36:22 +0100 Subject: [PATCH 1/2] Add dedicated astral config. --- configs/astral-cluster.sh | 17 + include/archi/chips/astral-cluster/apb_soc.h | 121 +++++++ .../archi/chips/astral-cluster/apb_soc_ctrl.h | 115 +++++++ .../archi/chips/astral-cluster/memory_map.h | 140 ++++++++ .../archi/chips/astral-cluster/properties.h | 301 ++++++++++++++++++ include/archi/chips/astral-cluster/pulp.h | 51 +++ include/archi/pulp_defs.h | 1 + include/chips/astral-cluster/config.h | 28 ++ include/chips/astral-cluster/soc.h | 47 +++ include/hal/chips/astral-cluster/pulp.h | 47 +++ include/hal/cv32e40p/cv32e40p.h | 4 + include/hal/ibex/ibex.h | 2 + include/hal/riscv/riscv_v5.h | 4 + kernel/chips/astral-cluster/link.ld | 260 +++++++++++++++ kernel/chips/astral-cluster/soc.c | 29 ++ kernel/crt0.S | 4 + rules/pulpos/targets/astral-cluster.mk | 77 +++++ 17 files changed, 1248 insertions(+) create mode 100644 configs/astral-cluster.sh create mode 100644 include/archi/chips/astral-cluster/apb_soc.h create mode 100644 include/archi/chips/astral-cluster/apb_soc_ctrl.h create mode 100644 include/archi/chips/astral-cluster/memory_map.h create mode 100644 include/archi/chips/astral-cluster/properties.h create mode 100644 include/archi/chips/astral-cluster/pulp.h create mode 100644 include/chips/astral-cluster/config.h create mode 100644 include/chips/astral-cluster/soc.h create mode 100644 include/hal/chips/astral-cluster/pulp.h create mode 100644 kernel/chips/astral-cluster/link.ld create mode 100644 kernel/chips/astral-cluster/soc.c create mode 100644 rules/pulpos/targets/astral-cluster.mk diff --git a/configs/astral-cluster.sh b/configs/astral-cluster.sh new file mode 100644 index 00000000..fda44fd3 --- /dev/null +++ b/configs/astral-cluster.sh @@ -0,0 +1,17 @@ +#!/bin/bash -e + +export PULPRT_TARGET=astral-cluster +export PULPRUN_TARGET=astral-cluster +export CONFIG_NO_FC=1 +export ARCHI_HMR=1 + +if [ -n "${ZSH_VERSION:-}" ]; then + DIR="$(readlink -f -- "${(%):-%x}")" + scriptDir="$(dirname $DIR)" +else + + scriptDir="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")" + +fi + +source $scriptDir/common.sh diff --git a/include/archi/chips/astral-cluster/apb_soc.h b/include/archi/chips/astral-cluster/apb_soc.h new file mode 100644 index 00000000..9d441aa0 --- /dev/null +++ b/include/archi/chips/astral-cluster/apb_soc.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2018 ETH Zurich and University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARCHI_PULP_APB_SOC_H__ +#define __ARCHI_PULP_APB_SOC_H__ + +#define APB_SOC_BOOT_OTHER 0 +#define APB_SOC_BOOT_JTAG 1 +#define APB_SOC_BOOT_SPI 2 +#define APB_SOC_BOOT_ROM 3 +#define APB_SOC_BOOT_PRELOAD 4 +#define APB_SOC_BOOT_HYPER 5 +#define APB_SOC_BOOT_SPIM 6 +#define APB_SOC_BOOT_SPIM_QPI 7 + +#define APB_SOC_PLT_OTHER 0 +#define APB_SOC_PLT_FPGA 1 +#define APB_SOC_PLT_RTL 2 +#define APB_SOC_PLT_VP 3 +#define APB_SOC_PLT_CHIP 4 + +//PADs configuration is made of 8bits out of which only the first 6 are used +//bit0 enable pull UP +//bit1 enable pull DOWN +//bit2 enable ST +//bit3 enable SlewRate Limit +//bit4..5 Driving Strength +//bit6..7 not used + +#define APB_SOC_BOOTADDR_OFFSET 0x04 +#define APB_SOC_INFO_OFFSET 0x00 //contains number of cores [31:16] and clusters [15:0] +#define APB_SOC_INFOEXTD_OFFSET 0x04 //not used at the moment +#define APB_SOC_NOTUSED0_OFFSET 0x08 //not used at the moment +#define APB_SOC_CLUSTER_ISOLATE_OFFSET 0x0C //not used at the moment + +#define APB_SOC_PADFUN0_OFFSET 0x10 +#define APB_SOC_PADCFG0_OFFSET 0x20 + +#define APB_SOC_PADFUN_OFFSET(g) (APB_SOC_PADFUN0_OFFSET+(g)*4) //sets the mux for pins g*16+0 (bits [1:0]) to g*16+15 (bits [31:30]) +#define APB_SOC_PADFUN_NO(pad) ((pad) >> 4) +#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16) +#define APB_SOC_PADFUN_SIZE 2 +#define ARCHI_APB_SOC_PADFUN_NB 4 +#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1) + +#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24]) +#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2) +#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4) +#define APB_SOC_PADCFG_SIZE 8 +#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3) + +#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet) +#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet) +#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot +#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment +#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment) +#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment +#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment) +#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment +#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed) +#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed) +#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment +#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment +#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment +#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment +#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment +#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment +#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0]) +#define APB_SOC_PADS_CONFIG 0xC4 + +#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0 + +#define APB_SOC_JTAG_REG_EXT_BIT 8 +#define APB_SOC_JTAG_REG_EXT_WIDTH 4 + +#define APB_SOC_JTAG_REG_LOC_BIT 0 +#define APB_SOC_JTAG_REG_LOC_WIDTH 4 + +#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2) +#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET) + +#define APB_SOC_STATUS_EOC_BIT 31 +#define APB_SOC_NB_CORE_BIT 16 + + +#define APB_SOC_BYPASS_OFFSET 0x70 + +#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10 +#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3 +#define APB_SOC_BYPASS_USER0_BIT 14 +#define APB_SOC_BYPASS_USER1_BIT 15 + + +#define APB_SOC_FLL_CTRL_OFFSET 0xD0 +#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4 +#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8 +#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC + + +#define APB_SOC_FLL_CTRL_SOC_BIT 0 +#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1 +#define APB_SOC_FLL_CTRL_PERIPH_BIT 2 + + +#define APB_SOC_RTC_OFFSET 0x1D0 + +#endif diff --git a/include/archi/chips/astral-cluster/apb_soc_ctrl.h b/include/archi/chips/astral-cluster/apb_soc_ctrl.h new file mode 100644 index 00000000..ef0a2cca --- /dev/null +++ b/include/archi/chips/astral-cluster/apb_soc_ctrl.h @@ -0,0 +1,115 @@ + +/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. + */ + +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_ARCHI_CHIPS_PULP_APB_SOC_CTRL_H__ +#define __INCLUDE_ARCHI_CHIPS_PULP_APB_SOC_CTRL_H__ + +#ifndef LANGUAGE_ASSEMBLY + +#include +#include "archi/utils.h" + +#endif + + + + +// +// REGISTERS +// + +// Value of pad bootsel +#define APB_SOC_BOOTSEL_OFFSET 0xc4 + + + +// +// REGISTERS FIELDS +// + + + +// +// REGISTERS STRUCTS +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef union { + struct { + }; + unsigned int raw; +} __attribute__((packed)) apb_soc_bootsel_t; + +#endif + + + +// +// REGISTERS STRUCTS +// + +#ifdef __GVSOC__ + +class vp_apb_soc_bootsel : public vp::reg_32 +{ +public: +}; + +#endif + + + +// +// REGISTERS GLOBAL STRUCT +// + +#ifndef LANGUAGE_ASSEMBLY + +typedef struct { + unsigned int bootsel ; // Value of pad bootsel +} __attribute__((packed)) apb_soc_apb_soc_t; + +#endif + + + +// +// REGISTERS ACCESS FUNCTIONS +// + +#ifndef LANGUAGE_ASSEMBLY + +static inline uint32_t apb_soc_bootsel_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_BOOTSEL_OFFSET); } +static inline void apb_soc_bootsel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_BOOTSEL_OFFSET, value); } + +#endif + + + +// +// REGISTERS FIELDS MACROS +// + +#ifndef LANGUAGE_ASSEMBLY + +#endif + +#endif diff --git a/include/archi/chips/astral-cluster/memory_map.h b/include/archi/chips/astral-cluster/memory_map.h new file mode 100644 index 00000000..90f315dc --- /dev/null +++ b/include/archi/chips/astral-cluster/memory_map.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_PULP_MEMORY_MAP_H__ +#define __ARCHI_CHIPS_PULP_MEMORY_MAP_H__ + + +/* + * MEMORIES + */ + +#define ARCHI_L2_PRIV0_ADDR 0x10000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x10008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x80000000 +#define ARCHI_L2_SHARED_SIZE 0x10000000 + + +/* + * SOC PERIPHERALS + */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 // FIXME + +#define ARCHI_FC_TIMER_SIZE 0x00000800 + + +#define ARCHI_FLL_OFFSET 0x00000000 +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + + + +#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET ) +#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET ) +#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET ) +#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET ) +#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET ) +#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET ) +#define ARCHI_STDOUT_ADDR 0x03002000 + +#define ARCHI_FLL_AREA_SIZE 0x00000010 + + + + +/* + * FC + */ + +#define ARCHI_FC_ADDR 0x00000000 +#define ARCHI_FC_GLOBAL_ADDR 0x1B000000 + + +/* + * CLUSTER + */ + +#define ARCHI_CLUSTER_ADDR 0x50000000 +#define ARCHI_CLUSTER_SIZE 0x00400000 +#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x50000000 + (cid)*ARCHI_CLUSTER_SIZE) + + + +/* + * CLUSTER PERIPHERALS + */ + +#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000 + +#define ARCHI_TIMER_SIZE 0x00000800 + +#define ARCHI_CLUSTER_CTRL_OFFSET 0x00000000 +#define ARCHI_TIMER_OFFSET 0x00000400 +#define ARCHI_EU_OFFSET 0x00000800 +#define ARCHI_HWCE_OFFSET 0x00001000 +#define ARCHI_ICACHE_CTRL_OFFSET 0x00001400 +#define ARCHI_MCHAN_EXT_OFFSET 0x00001800 +#define ARCHI_HMR_OFFSET 0x00002000 +#define ARCHI_TCDM_SCRUBBER_OFFSET 0x00002400 + +#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) +#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET ) +#define ARCHI_HMR_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HMR_OFFSET ) +#define ARCHI_TCDM_SCRUBBER_ADDR ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_TCDM_SCRUBBER_OFFSET ) + +#define ARCHI_CLUSTER_CTRL_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_CTRL_OFFSET ) +#define ARCHI_ICACHE_CTRL_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_ICACHE_CTRL_OFFSET ) +#define ARCHI_EU_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_EU_OFFSET ) +#define ARCHI_HWCE_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_HWCE_OFFSET ) +#define ARCHI_MCHAN_EXT_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_MCHAN_EXT_OFFSET ) +#define ARCHI_IDMA_EXT_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_IDMA_EXT_OFFSET ) +#define ARCHI_HMR_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_HMR_OFFSET ) +#define ARCHI_TCDM_SCRUBBER_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_TCDM_SCRUBBER_OFFSET ) + + +/* + * CLUSTER DEMUX PERIPHERALS + */ + +#define ARCHI_DEMUX_PERIPHERALS_OFFSET 0x204000 + +#define ARCHI_EU_DEMUX_OFFSET ( 0x00000 ) +#define ARCHI_MCHAN_DEMUX_OFFSET ( 0x00400 ) + + +#define ARCHI_DEMUX_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET ) + +#define ARCHI_EU_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET ) +#define ARCHI_MCHAN_DEMUX_ADDR ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET ) + +#endif diff --git a/include/archi/chips/astral-cluster/properties.h b/include/archi/chips/astral-cluster/properties.h new file mode 100644 index 00000000..ef046370 --- /dev/null +++ b/include/archi/chips/astral-cluster/properties.h @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2018 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __ARCHI_CHIPS_PULP_PROPERTIES_H__ +#define __ARCHI_CHIPS_PULP_PROPERTIES_H__ + +/* + * FPGA + */ + +#ifndef ARCHI_FPGA_PER_FREQUENCY +#define ARCHI_FPGA_PER_FREQUENCY 5000000 +#endif + +#ifndef ARCHI_FPGA_SOC_FREQUENCY +#define ARCHI_FPGA_SOC_FREQUENCY 5000000 +#endif + +#ifndef ARCHI_FPGA_CL_FREQUENCY +#define ARCHI_FPGA_CL_FREQUENCY 5000000 +#endif + +/* + * MEMORIES + */ + +#define ARCHI_HAS_L2 1 +#define ARCHI_HAS_L2_MULTI 1 +#define ARCHI_HAS_L1 1 + +#define ARCHI_L2_PRIV0_ADDR 0x10000000 +#define ARCHI_L2_PRIV0_SIZE 0x00008000 + +#define ARCHI_L2_PRIV1_ADDR 0x10008000 +#define ARCHI_L2_PRIV1_SIZE 0x00008000 + +#define ARCHI_L2_SHARED_ADDR 0x80000000 +#define ARCHI_L2_SHARED_SIZE 0x10000000 + + + +/* + * MEMORY ALIAS + */ + +#define ARCHI_HAS_L1_ALIAS 1 +#define ARCHI_HAS_L2_ALIAS 1 + + + +/* + * IP VERSIONS + */ + +#define UDMA_VERSION 3 +#define PERIPH_VERSION 2 +#define TIMER_VERSION 2 +#define SOC_EU_VERSION 2 +#define APB_SOC_VERSION 3 +#define STDOUT_VERSION 2 +#define GPIO_VERSION 2 +#define EU_VERSION 3 +#define ITC_VERSION 1 +#define FLL_VERSION 1 +#define RISCV_VERSION 4 +#define MCHAN_VERSION 7 +#define PADS_VERSION 2 +#define HMR_VERSION 1 + + +/* + * CLUSTER + */ + +#define ARCHI_HAS_CLUSTER 1 +#define ARCHI_L1_TAS_BIT 20 +#ifndef ARCHI_CLUSTER_NB_PE +#define ARCHI_CLUSTER_NB_PE 12 +#endif +#define ARCHI_NB_CLUSTER 1 + +// #define ARCHI_HMR_NO_RAPID_RECOVERY +// #define ARCHI_HMR_FORCE_RAPID +#if defined(ARCHI_HMR_NO_RAPID_RECOVERY) && defined(ARCHI_HMR_FORCE_RAPID) +#error "Excluding and forcing rapid recovery not compatible" +#endif + +// #define ARCHI_HMR_TMR_ONLY +// #define ARCHI_HMR_DMR_ONLY +#if defined(ARCHI_HMR_DMR_ONLY) && defined(ARCHI_HMR_TMR_ONLY) +#error "TMR only and DMR only not compatible" +#endif + +/* + * HWS + */ + +#define ARCHI_EU_NB_HW_MUTEX 1 + + + +/* + * FC + */ +#ifndef ARCHI_NO_FC +#define ARCHI_FC_CID 31 +#define ARCHI_HAS_FC_ITC 1 +#define ARCHI_HAS_FC 1 +#define ARCHI_CORE_HAS_1_10 1 +#endif + + +/* + * CLOCKS + */ + +#define ARCHI_REF_CLOCK_LOG2 15 +#define ARCHI_REF_CLOCK (1<> 6); +#elif PULP_CHIP == CHIP_ASTRAL + return (hart_id >> 6); #else return (hart_id >> 5) & 0x3f; #endif @@ -194,6 +196,8 @@ static inline __attribute__((always_inline)) unsigned int hal_cluster_id() { // in PULP the hart id is {22'b0, cluster_id, core_id} #if PULP_CHIP == CHIP_CARFIELD return (hart_id >> 6); +#elif PULP_CHIP == CHIP_ASTRAL + return (hart_id >> 6); #else return (hart_id >> 5) & 0x3f; #endif diff --git a/include/hal/ibex/ibex.h b/include/hal/ibex/ibex.h index 8cbec1d1..a1cf16e6 100644 --- a/include/hal/ibex/ibex.h +++ b/include/hal/ibex/ibex.h @@ -88,6 +88,8 @@ static inline unsigned int cluster_id() { // in PULP the hart id is {22'b0, cluster_id, core_id} #if PULP_CHIP == CHIP_CARFIELD return (hart_id >> 6); +#elif PULP_CHIP == CHIP_ASTRAL + return (hart_id >> 6); #else return (hart_id >> 5) & 0x3f; #endif diff --git a/include/hal/riscv/riscv_v5.h b/include/hal/riscv/riscv_v5.h index f383eab2..01f2c77d 100644 --- a/include/hal/riscv/riscv_v5.h +++ b/include/hal/riscv/riscv_v5.h @@ -160,6 +160,8 @@ static inline unsigned int cluster_id() { // in PULP the hart id is {22'b0, cluster_id, core_id} #if PULP_CHIP == CHIP_CARFIELD return (hart_id >> 6); +#elif PULP_CHIP == CHIP_ASTRAL + return (hart_id >> 6); #else return (hart_id >> 5) & 0x3f; #endif @@ -226,6 +228,8 @@ static inline __attribute__((always_inline)) unsigned int hal_cluster_id() { // in PULP the hart id is {22'b0, cluster_id, core_id} #if PULP_CHIP == CHIP_CARFIELD return (hart_id >> 6); +#elifif PULP_CHIP == CHIP_ASTRAL + return (hart_id >> 6); #else return (hart_id >> 5) & 0x3f; #endif diff --git a/kernel/chips/astral-cluster/link.ld b/kernel/chips/astral-cluster/link.ld new file mode 100644 index 00000000..742a0406 --- /dev/null +++ b/kernel/chips/astral-cluster/link.ld @@ -0,0 +1,260 @@ + +OUTPUT_ARCH(riscv) +ENTRY( _start ) +MEMORY +{ + L2 : ORIGIN = 0x10000000, LENGTH = 0x00020000 + L1 : ORIGIN = 0x50000000, LENGTH = 0x0003FFFC +} + +/* + * This linker script try to put FC data in L2 private bank0 and FC code + * in L2 private bank1 to avoid contention between FC code and data + * as FC has no instruction cache and is so often accessing L2 to + * get instructions. Everything can be shifted in case one bank is full. + * + * Cluster code and initialized data are put in shared banks to not polute + * private banks which are quite small, and also avoid contentions between + * cluster cache refill and FC. + */ + + +SECTIONS +{ + /* + * L2 PRIVATE BANK0 + * + * Contains FC data + */ + + .init : + { + . = ALIGN(4); + KEEP( *(.init) ) + } > L2 + + + .fini : + { + . = ALIGN(4); + KEEP( *(.fini) ) + } > L2 + + + .preinit_array : { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > L2 + + + .init_array : { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + __CTOR_LIST__ = .; + LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) + KEEP(*(.ctors.start)) + KEEP(*(.ctors)) + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array )) + LONG(0) + __CTOR_END__ = .; + PROVIDE_HIDDEN (__init_array_end = .); + } > L2 + + + .fini_array : { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + __DTOR_LIST__ = .; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) + KEEP(*(.dtors.start)) + KEEP(*(.dtors)) + LONG(0) + __DTOR_END__ = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array )) + PROVIDE_HIDDEN (__fini_array_end = .); + } > L2 + + + .boot : { + . = ALIGN(4); + *(.boot) + *(.boot.data) + } > L2 + + + .rodata : { + . = ALIGN(4); + *(.rodata); + *(.rodata.*) + *(.srodata); + *(.srodata.*) + *(.eh_frame*) + } > L2 + + + .got : { + . = ALIGN(4); + *(.got.plt) * (.igot.plt) *(.got) *(.igot) + } > L2 + + + .shbss : { + . = ALIGN(4); + *(.shbss) + } > L2 + + + .talias : { + } > L2 + + + .gnu.offload_funcs : { + . = ALIGN(4); + KEEP(*(.gnu.offload_funcs)) + } > L2 + + + .gnu.offload_vars : { + . = ALIGN(4); + KEEP(*(.gnu.offload_vars)) + } > L2 + + + .stack : { + . = ALIGN(4); + . = ALIGN(16); + stack_start = .; + . = . + 0x800; + stack = .; + } > L2 + + + .data : { + . = ALIGN(4); + sdata = .; + _sdata = .; + *(.data_fc) + *(.data_fc.*) + *(.data); + *(.data.*) + *(.sdata); + *(.sdata.*) + *(.heapl2ram) + *(.fcTcdm) + *(.fcTcdm.*) + *(.fcTcdm_g) + *(.fcTcdm_g.*) + . = ALIGN(4); + edata = .; + _edata = .; + } > L2 + + + .bss : { + . = ALIGN(8); + _bss_start = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > L2 + + + __l2_priv0_end = ALIGN(4); + + + + + /* + * L2 PRIVATE BANK1 + * + * Contains FC code + */ + + .vectors MAX(ORIGIN(L2)+0x8000,ALIGN(256)) : + { + /*. = ALIGN(256);*/ + __irq_vector_base = .; + KEEP(*(.vectors)) + } > L2 + + .text : + { + . = ALIGN(4); + _stext = .; + *(.text) + *(.text.*) + _etext = .; + *(.lit) + *(.shdata) + _endtext = .; + . = ALIGN(4); + } > L2 + + __l2_priv1_end = ALIGN(4); + + + /* + * L2 SHARED BANKS + * + * Contains other data such as peripheral data and cluster code and data + */ + + .l2_data MAX(ORIGIN(L2)+0x10000,ALIGN(4)) : + { + . = ALIGN(4); + __cluster_text_start = .; + *(.cluster.text) + *(.cluster.text.*) + . = ALIGN(4); + __cluster_text_end = .; + *(.l2_data) + *(.l2_data.*) + *(.data_fc_shared) + *(.data_fc_shared.*) + . = ALIGN(4); + } > L2 + + __l2_data_end = .; + + .l1cluster_g : { + . = ALIGN(4); + *(.heapsram) + *(.heapsram.*) + *(.l1cluster_g) + *(.l1cluster_g.*) + *(.data_l1) + *(.data_l1.*) + . = ALIGN(4); + _libgomp_start = .; + *(.libgomp) + *(.libgomp.*) + . = ALIGN(4); + } > L1 + + .bss_l1 : { + . = ALIGN(4); + *(.bss_l1) + *(.bss_l1.*) + . = ALIGN(4); + } > L1 + + __l1_end = ALIGN(4); + + __l2_shared_end = __l2_data_end + SIZEOF(.l1cluster_g) + SIZEOF(.bss_l1); + + + + + __cluster_text_size = __cluster_text_end - __cluster_text_start; + + __l1_heap_start = ALIGN(4); + __l1_heap_size = LENGTH(L1) - __l1_heap_start + ORIGIN(L1); +} diff --git a/kernel/chips/astral-cluster/soc.c b/kernel/chips/astral-cluster/soc.c new file mode 100644 index 00000000..354ba411 --- /dev/null +++ b/kernel/chips/astral-cluster/soc.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2019 ETH Zurich, University of Bologna + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "pulp.h" + +void pos_soc_init() +{ + + pos_freq_domains[PI_FREQ_DOMAIN_FC] = ARCHI_FPGA_SOC_FREQUENCY; + + pos_freq_domains[PI_FREQ_DOMAIN_PERIPH] = ARCHI_FPGA_PER_FREQUENCY; + + pos_freq_domains[PI_FREQ_DOMAIN_CL] = ARCHI_FPGA_CL_FREQUENCY; + +} + diff --git a/kernel/crt0.S b/kernel/crt0.S index ce89d6a8..d675f0b1 100644 --- a/kernel/crt0.S +++ b/kernel/crt0.S @@ -32,6 +32,8 @@ pos_init_entry: # the L1 and jump to cluster_entry_stub #if PULP_CHIP == CHIP_CARFIELD li t0, 0x5003FFF0 +#elif PULP_CHIP == CHIP_ASTRAL + li t0, 0x5003FFF0 #else li t0, 0x1003FF0 #endif @@ -85,6 +87,8 @@ pos_init_entry: andi a1, a0, 0x1f #if PULP_CHIP == CHIP_CARFIELD li t0, 0x5003FFF0 +#elif PULP_CHIP == CHIP_ASTRAL + li t0, 0x5003FFF0 #else li t0, 0x1003FFF0 #endif diff --git a/rules/pulpos/targets/astral-cluster.mk b/rules/pulpos/targets/astral-cluster.mk new file mode 100644 index 00000000..5eec999f --- /dev/null +++ b/rules/pulpos/targets/astral-cluster.mk @@ -0,0 +1,77 @@ +QUESTA ?= questa-2022.3 +ifdef USE_IBEX +PULP_LDFLAGS += +PULP_CFLAGS += -D__ibex__ -U__riscv__ -UARCHI_CORE_HAS_PULPV2 -DRV_ISA_RV32 +PULP_ARCH_CFLAGS ?= -march=rv32imc +PULP_ARCH_LDFLAGS ?= -march=rv32imc +PULP_ARCH_OBJDFLAGS ?= -Mmarch=rv32imc +else ifdef USE_CV32E40P +PULP_LDFLAGS += +PULP_CFLAGS += -D__cv32e40p__ -U__riscv__ -UARCHI_CORE_HAS_PULPV2 +PULP_ARCH_CFLAGS ?= -march=rv32imcxgap9 -mnohwloop +PULP_ARCH_LDFLAGS ?= -march=rv32imcxgap9 -mnohwloop +PULP_ARCH_OBJDFLAGS ?= -Mmarch=rv32imcxgap9 -mnohwloop +else +PULP_LDFLAGS += +PULP_CFLAGS += -D__riscv__ +PULP_ARCH_CFLAGS ?= -march=rv32imcxgap9 +PULP_ARCH_LDFLAGS ?= -march=rv32imcxgap9 +PULP_ARCH_OBJDFLAGS ?= -Mmarch=rv32imcxgap9 +endif + +PULP_CFLAGS += -fdata-sections -ffunction-sections -include chips/astral-cluster/config.h -I$(PULPRT_HOME)/include/chips/astral-cluster +PULP_OMP_CFLAGS += -fopenmp -mnativeomp +PULP_LDFLAGS += -nostartfiles -nostdlib -Wl,--gc-sections -L$(PULPRT_HOME)/kernel -Tchips/astral-cluster/link.ld -lgcc + +PULPD_RISCV ?= riscv32-unknown-elf + +PULP_CC ?= $(PULPD_RISCV)-gcc +PULP_AR ?= $(PULPD_RISCV)-ar +PULP_LD ?= $(PULPD_RISCV)-gcc +PULP_OBJDUMP ?= $(PULPD_RISCV)-objdump + +fc/archi=riscv +pe/archi=riscv +pulp_chip=astral-cluster +pulp_chip_family=astral-cluster +cluster/version=5 +fc_itc/version=1 +udma/cpi/version=1 +udma/i2c/version=2 +soc/fll/version=1 +udma/i2s/version=2 +udma/uart/version=1 +event_unit/version=3 +perf_counters=True +fll/version=1 +padframe/version=1 +udma/spim/version=3 +gpio/version=3 +udma/archi=3 +udma/version=3 +soc_eu/version=2 + + +# FLL +PULP_SRCS += kernel/fll-v$(fll/version).c +PULP_SRCS += kernel/freq-domains.c +PULP_SRCS += kernel/chips/astral-cluster/soc.c + +# HMR +PULP_CFLAGS += -DARCHI_HMR +PULP_SRCS += kernel/hmr_synch.c + +include $(PULPRT_HOME)/rules/pulpos/configs/default.mk + +ifeq '$(platform)' 'fpga' +CONFIG_IO_UART=1 +endif + +include $(PULPRT_HOME)/rules/pulpos/default_rules.mk + +ifndef gui +vsim-flags = -c +endif + +run: + $(QUESTA) vsim $(vsim-flags) -do "set VSIM_PATH $(VSIM_PATH); source $(VSIM_PATH)/scripts/start.tcl" From f208e9f30426a9980446800087b7ac9b59fbb979 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Fri, 29 Mar 2024 10:49:25 +0100 Subject: [PATCH 2/2] Reduce number of cluster cores for Astral --- include/archi/chips/astral-cluster/properties.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/archi/chips/astral-cluster/properties.h b/include/archi/chips/astral-cluster/properties.h index ef046370..4c6e9f03 100644 --- a/include/archi/chips/astral-cluster/properties.h +++ b/include/archi/chips/astral-cluster/properties.h @@ -89,7 +89,7 @@ #define ARCHI_HAS_CLUSTER 1 #define ARCHI_L1_TAS_BIT 20 #ifndef ARCHI_CLUSTER_NB_PE -#define ARCHI_CLUSTER_NB_PE 12 +#define ARCHI_CLUSTER_NB_PE 8 #endif #define ARCHI_NB_CLUSTER 1