From 3421233afbe237d71a835f28f83c5e47c6ceb164 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 12:37:31 +0800 Subject: [PATCH 01/32] Format stm32f4 config --- qiling/extensions/mcu/stm32f4/stm32f401.py | 446 ++++++------- qiling/extensions/mcu/stm32f4/stm32f405.py | 600 ++++++++--------- qiling/extensions/mcu/stm32f4/stm32f407.py | 616 ++++++++--------- qiling/extensions/mcu/stm32f4/stm32f410.py | 406 ++++++------ qiling/extensions/mcu/stm32f4/stm32f411.py | 452 ++++++------- qiling/extensions/mcu/stm32f4/stm32f412.py | 574 ++++++++-------- qiling/extensions/mcu/stm32f4/stm32f413.py | 682 +++++++++---------- qiling/extensions/mcu/stm32f4/stm32f415.py | 612 ++++++++--------- qiling/extensions/mcu/stm32f4/stm32f417.py | 632 +++++++++--------- qiling/extensions/mcu/stm32f4/stm32f423.py | 688 +++++++++---------- qiling/extensions/mcu/stm32f4/stm32f427.py | 696 +++++++++---------- qiling/extensions/mcu/stm32f4/stm32f429.py | 708 ++++++++++---------- qiling/extensions/mcu/stm32f4/stm32f437.py | 714 ++++++++++---------- qiling/extensions/mcu/stm32f4/stm32f439.py | 724 ++++++++++---------- qiling/extensions/mcu/stm32f4/stm32f446.py | 630 +++++++++--------- qiling/extensions/mcu/stm32f4/stm32f469.py | 720 ++++++++++---------- qiling/extensions/mcu/stm32f4/stm32f479.py | 738 ++++++++++----------- 17 files changed, 5316 insertions(+), 5322 deletions(-) diff --git a/qiling/extensions/mcu/stm32f4/stm32f401.py b/qiling/extensions/mcu/stm32f4/stm32f401.py index ad6c63def..a030de277 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f401.py +++ b/qiling/extensions/mcu/stm32f4/stm32f401.py @@ -4,125 +4,157 @@ # stm32f401 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" + }, + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" + }, + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" + }, + "FLASH": { + "base": 0x8000000, + "size": 0x80000, + "type": "memory" + }, + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x1c }, - "type": "core peripheral" + "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x1d }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x1e }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", + "kwargs": { + "intn": 0x32 + }, "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x10000, - "alias": 0x0, - "type": "remap" - }, - "CODE": { - "base": 0x08000000, - "size": 0x80000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x80000, - "type": "memory" - }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", + "kwargs": { + "alarm_intn": 0x29, + "wkup_intn": 0x3 + }, + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", "kwargs": { - "intn": 4, + "intn": 0x0 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -130,8 +162,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -139,103 +171,61 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", - "type": "peripheral" - }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRcc", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 5 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "intn": 0x25 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" - }, - "SDIO": { - "base": 0x40012c00, - "struct": "STM32F4xxSdio", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 49 + "intn": 0x47 }, "type": "peripheral" }, - "SPI1": { - "base": 0x40013000, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 35 - }, + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", + "SDIO": { + "base": 0x40012c00, + "struct": "STM32F4xxSdio", "kwargs": { - "intn": 36 + "intn": 0x31 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, + "SPI1": { + "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 51 + "intn": 0x23 }, "type": "peripheral" }, @@ -243,45 +233,23 @@ "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 84 + "intn": 0x54 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, "type": "peripheral" }, "TIM10": { @@ -294,73 +262,99 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", + "type": "peripheral" + }, + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", + "type": "peripheral" + }, + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRcc", "kwargs": { - "intn": 37 + "intn": 0x5 }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 38 + "intn": 0x4 }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 71 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 0 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" + }, + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", + "kwargs": { + "dev_id": 0x413 + }, + "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x80000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f405.py b/qiling/extensions/mcu/stm32f4/stm32f405.py index 880feaa0a..eb9d86b9c 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f405.py +++ b/qiling/extensions/mcu/stm32f4/stm32f405.py @@ -4,171 +4,212 @@ # stm32f405 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" + }, + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" + }, + "FLASH": { + "base": 0x8000000, + "size": 0x100000, + "type": "memory" + }, + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 + "intn": 0x1c }, "type": "peripheral" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 + "intn": 0x1d }, "type": "peripheral" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" - }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", + "kwargs": { + "intn": 0x1e + }, "type": "peripheral" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x32 }, - "type": "core peripheral" + "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "dac_intn": 0x36 }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x100000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x100000, - "type": "memory" + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", "kwargs": { - "intn": 4, + "alarm_intn": 0x29, + "wkup_intn": 0x3 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOI": { - "base": 0x40022000, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, + "type": "peripheral" + }, + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x35 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -176,8 +217,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -185,149 +226,125 @@ "base": 0x40005c00, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f + }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV2", - "kwargs": { - "intn": 5 - }, + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 80 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" - }, - "SDIO": { - "base": 0x40012c00, - "struct": "STM32F4xxSdio", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 49 + "intn": 0x25 }, "type": "peripheral" }, - "SPI1": { - "base": 0x40013000, - "struct": "STM32F4xxSpi", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 35 + "intn": 0x47 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "SDIO": { + "base": 0x40012c00, + "struct": "STM32F4xxSdio", "kwargs": { - "intn": 36 + "intn": 0x31 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, + "SPI1": { + "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 51 + "intn": 0x23 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, "type": "peripheral" }, "TIM10": { @@ -340,139 +357,122 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 - }, + "GPIOI": { + "base": 0x40022000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV2", "kwargs": { - "intn": 52 + "intn": 0x5 }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 53 + "intn": 0x4 }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 37 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 38 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", "kwargs": { - "intn": 39 + "intn": 0x50 }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 71 + "dev_id": 0x413 }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", - "kwargs": { - "intn": 0 - }, - "type": "peripheral" + "CODE": { + "base": 0x8000000, + "size": 0x100000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f407.py b/qiling/extensions/mcu/stm32f4/stm32f407.py index 1f08ee1c3..7ed14c4c3 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f407.py +++ b/qiling/extensions/mcu/stm32f4/stm32f407.py @@ -4,188 +4,212 @@ # stm32f407 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" + }, + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" + }, + "FLASH": { + "base": 0x8000000, + "size": 0x100000, + "type": "memory" + }, + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 + "intn": 0x1c }, "type": "peripheral" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 + "intn": 0x1d }, "type": "peripheral" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" - }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" - }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x1e }, - "type": "core peripheral" + "type": "peripheral" }, - "DCMI": { - "base": 0x50050000, - "struct": "STM32F4xxDcmi", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 78 + "intn": 0x32 }, "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "dac_intn": 0x36 }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x37 }, "type": "peripheral" }, - "ETH": { - "base": 0x40028000, - "struct": "STM32F4xxEth", - "kwargs": { - "intn": 61, - "wkup_intn": 62 - }, + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x100000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x100000, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", + "kwargs": { + "alarm_intn": 0x29, + "wkup_intn": 0x3 + }, + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", "kwargs": { - "intn": 4, + "intn": 0x0 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, "type": "peripheral" }, - "GPIOI": { - "base": 0x40022000, - "struct": "STM32F4xxGpio", + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x35 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -193,8 +217,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -202,149 +226,125 @@ "base": 0x40005c00, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f + }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV2", - "kwargs": { - "intn": 5 - }, + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 80 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" - }, - "SDIO": { - "base": 0x40012c00, - "struct": "STM32F4xxSdio", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 49 + "intn": 0x25 }, "type": "peripheral" }, - "SPI1": { - "base": 0x40013000, - "struct": "STM32F4xxSpi", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 35 + "intn": 0x47 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "SDIO": { + "base": 0x40012c00, + "struct": "STM32F4xxSdio", "kwargs": { - "intn": 36 + "intn": 0x31 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, + "SPI1": { + "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 51 + "intn": 0x23 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, "type": "peripheral" }, "TIM10": { @@ -357,139 +357,139 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOI": { + "base": 0x40022000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 - }, + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV2", + "kwargs": { + "intn": 0x5 + }, "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 52 + "intn": 0x4 }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 53 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 37 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "ETH": { + "base": 0x40028000, + "struct": "STM32F4xxEth", "kwargs": { - "intn": 38 + "intn": 0x3d, + "wkup_intn": 0x3e }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "DCMI": { + "base": 0x50050000, + "struct": "STM32F4xxDcmi", "kwargs": { - "intn": 39 + "intn": 0x4e }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", "kwargs": { - "intn": 71 + "intn": 0x50 }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x100000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f410.py b/qiling/extensions/mcu/stm32f4/stm32f410.py index fe5ecc9fa..70ada507e 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f410.py +++ b/qiling/extensions/mcu/stm32f4/stm32f410.py @@ -4,123 +4,131 @@ # stm32f410 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" - }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" - }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", - "kwargs": { - "dev_id": 0x413, - }, - "type": "core peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", - "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 - }, - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", - "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 - }, - "type": "peripheral" + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", - "type": "peripheral" + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" }, - "CODE": { - "base": 0x08000000, - "size": 0x20000, - "alias": 0x0, - "type": "remap" - }, "FLASH": { - "base": 0x08000000, + "base": 0x8000000, "size": 0x20000, "type": "memory" }, + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, "FLASH OTP": { "base": 0x1fff7800, "size": 0x400, "type": "memory" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 4, + "intn": 0x32 }, "type": "peripheral" }, - "FMPI2C1": { - "base": 0x40006000, - "struct": "STM32F4xxFmpi2c", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "er_intn": 96, - "ev_intn": 95 + "dac_intn": 0x36 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "LPTIM1": { + "base": 0x40002400, + "struct": "STM32F4xxLptim", + "kwargs": { + "intn": 0x61 + }, "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", + "kwargs": { + "alarm_intn": 0x29, + "wkup_intn": 0x3 + }, "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", + "type": "peripheral" + }, + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, + "type": "peripheral" + }, + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -128,139 +136,83 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", - "type": "peripheral" - }, - "LPTIM1": { - "base": 0x40002400, - "struct": "STM32F4xxLptim", + "FMPI2C1": { + "base": 0x40006000, + "struct": "STM32F4xxFmpi2c", "kwargs": { - "intn": 97 + "er_intn": 0x60, + "ev_intn": 0x5f }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV4", - "kwargs": { - "intn": 5 - }, + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", "type": "peripheral" }, - "RNG": { - "base": 0x40080000, - "struct": "STM32F4xxRng", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 80 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_intn": 0x19 }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "intn": 0x25 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" - }, - "SPI1": { - "base": 0x40013000, - "struct": "STM32F4xxSpi", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 35 + "intn": 0x47 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 36 - }, + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", "type": "peripheral" }, - "SPI5": { - "base": 0x40015000, + "SPI1": { + "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 85 + "intn": 0x23 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F4xxSyscfgV2", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_intn": 25 - }, "type": "peripheral" }, "TIM11": { @@ -268,57 +220,105 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", + "SPI5": { + "base": 0x40015000, + "struct": "STM32F4xxSpi", "kwargs": { - "intn": 50 + "intn": 0x55 }, "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", + "type": "peripheral" + }, + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", + "type": "peripheral" + }, + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", + "type": "peripheral" + }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", + "type": "peripheral" + }, + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", + "type": "peripheral" + }, + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV4", "kwargs": { - "dac_intn": 54 + "intn": 0x5 }, "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", + "kwargs": { + "intn": 0x4 + }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 37 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 38 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "RNG": { + "base": 0x40080000, + "struct": "STM32F4xxRng", "kwargs": { - "intn": 71 + "intn": 0x50 }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x20000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f411.py b/qiling/extensions/mcu/stm32f4/stm32f411.py index 830a64415..7b527ee02 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f411.py +++ b/qiling/extensions/mcu/stm32f4/stm32f411.py @@ -4,119 +4,157 @@ # stm32f411 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" + }, + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" + }, + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" + }, + "FLASH": { + "base": 0x8000000, + "size": 0x80000, + "type": "memory" + }, + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x1c }, - "type": "core peripheral" + "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x1d }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x1e }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", + "kwargs": { + "intn": 0x32 + }, "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x80000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x80000, - "type": "memory" - }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", + "kwargs": { + "alarm_intn": 0x29, + "wkup_intn": 0x3 + }, + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", "kwargs": { - "intn": 4, + "intn": 0x0 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -124,8 +162,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -133,103 +171,61 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", - "type": "peripheral" - }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRcc", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 5 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "intn": 0x25 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" - }, - "SDIO": { - "base": 0x40012c00, - "struct": "STM32F4xxSdio", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 49 + "intn": 0x47 }, "type": "peripheral" }, - "SPI1": { - "base": 0x40013000, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 35 - }, + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", + "SDIO": { + "base": 0x40012c00, + "struct": "STM32F4xxSdio", "kwargs": { - "intn": 36 + "intn": 0x31 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, + "SPI1": { + "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 51 + "intn": 0x23 }, "type": "peripheral" }, @@ -237,53 +233,23 @@ "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 84 - }, - "type": "peripheral" - }, - "SPI5": { - "base": 0x40015000, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 85 + "intn": 0x54 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, "type": "peripheral" }, "TIM10": { @@ -296,73 +262,107 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", + "SPI5": { + "base": 0x40015000, + "struct": "STM32F4xxSpi", "kwargs": { - "intn": 28 + "intn": 0x55 }, "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", + "type": "peripheral" + }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", + "type": "peripheral" + }, + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", + "type": "peripheral" + }, + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRcc", "kwargs": { - "intn": 37 + "intn": 0x5 }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 38 + "intn": 0x4 }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 71 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 0 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" + }, + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", + "kwargs": { + "dev_id": 0x413 + }, + "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x80000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f412.py b/qiling/extensions/mcu/stm32f4/stm32f412.py index e45ff23a1..39af87267 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f412.py +++ b/qiling/extensions/mcu/stm32f4/stm32f412.py @@ -4,160 +4,196 @@ # stm32f412 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" + }, + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" + }, + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" + }, + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" + }, + "FLASH": { + "base": 0x8000000, + "size": 0x100000, + "type": "memory" + }, + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 + "intn": 0x1c }, "type": "peripheral" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 + "intn": 0x1d }, "type": "peripheral" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", + "kwargs": { + "intn": 0x1e + }, "type": "peripheral" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x32 }, - "type": "core peripheral" + "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x36 }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x100000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x100000, - "type": "memory" + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", "kwargs": { - "intn": 4, + "alarm_intn": 0x29, + "wkup_intn": 0x3 }, "type": "peripheral" }, - "FMPI2C1": { - "base": 0x40006000, - "struct": "STM32F4xxFmpi2c", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", "kwargs": { - "er_intn": 96, - "ev_intn": 95 + "intn": 0x0 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", - "type": "peripheral" - }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -165,8 +201,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -174,95 +210,95 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", + "FMPI2C1": { + "base": 0x40006000, + "struct": "STM32F4xxFmpi2c", + "kwargs": { + "er_intn": 0x60, + "ev_intn": 0x5f + }, "type": "peripheral" }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f + }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "QUADSPI": { - "base": 0xa0001000, - "struct": "STM32F4xxQuadspi", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 92 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 }, "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV1", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 5 + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c }, "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 80 + "intn": 0x25 }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "intn": 0x47 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" }, "SDIO": { "base": 0x40012c00, "struct": "STM32F4xxSdio", "kwargs": { - "intn": 49 + "intn": 0x31 }, "type": "peripheral" }, @@ -270,23 +306,7 @@ "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 35 - }, - "type": "peripheral" - }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 36 - }, - "type": "peripheral" - }, - "SPI3": { - "base": 0x40003c00, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 51 + "intn": 0x23 }, "type": "peripheral" }, @@ -294,53 +314,23 @@ "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 84 - }, - "type": "peripheral" - }, - "SPI5": { - "base": 0x40015000, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 85 + "intn": 0x54 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F4xxSyscfgV2", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, "type": "peripheral" }, "TIM10": { @@ -353,123 +343,133 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", + "SPI5": { + "base": 0x40015000, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x55 + }, "type": "peripheral" }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 54 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", + "type": "peripheral" + }, + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV1", "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 + "intn": 0x5 }, "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", + "kwargs": { + "intn": 0x4 + }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 37 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 38 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", "kwargs": { - "intn": 39 + "intn": 0x50 }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "QUADSPI": { + "base": 0xa0001000, + "struct": "STM32F4xxQuadspi", "kwargs": { - "intn": 71 + "intn": 0x5c }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x100000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f413.py b/qiling/extensions/mcu/stm32f4/stm32f413.py index 641685a6c..477b68fe7 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f413.py +++ b/qiling/extensions/mcu/stm32f4/stm32f413.py @@ -4,176 +4,220 @@ # stm32f413 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" + }, + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" + }, + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" + }, + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" + }, + "FLASH": { + "base": 0x8000000, + "size": 0x180000, + "type": "memory" + }, + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 + "intn": 0x1c }, "type": "peripheral" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 + "intn": 0x1d }, "type": "peripheral" }, - "CAN3": { - "base": 0x40006c00, - "struct": "STM32F4xxCan", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 75, - "rx1_intn": 76, - "sce_intn": 77, - "tx_intn": 74 + "intn": 0x1e }, "type": "peripheral" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" - }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" - }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x32 }, - "type": "core peripheral" + "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "dac_intn": 0x36 }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x180000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x180000, - "type": "memory" + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "LPTIM1": { + "base": 0x40002400, + "struct": "STM32F4xxLptim", "kwargs": { - "intn": 4, + "intn": 0x61 }, "type": "peripheral" }, - "FMPI2C1": { - "base": 0x40006000, - "struct": "STM32F4xxFmpi2c", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", "kwargs": { - "er_intn": 96, - "ev_intn": 95 + "alarm_intn": 0x29, + "wkup_intn": 0x3 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, + "type": "peripheral" + }, + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, + "type": "peripheral" + }, + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x35 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -181,8 +225,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -190,189 +234,175 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "FMPI2C1": { + "base": 0x40006000, + "struct": "STM32F4xxFmpi2c", + "kwargs": { + "er_intn": 0x60, + "ev_intn": 0x5f + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "LPTIM1": { - "base": 0x40002400, - "struct": "STM32F4xxLptim", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", "kwargs": { - "intn": 97 + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" + "CAN3": { + "base": 0x40006c00, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x4b, + "rx1_intn": 0x4c, + "sce_intn": 0x4d, + "tx_intn": 0x4a + }, + "type": "peripheral" }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "QUADSPI": { - "base": 0xa0001000, - "struct": "STM32F4xxQuadspi", + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", + "type": "peripheral" + }, + "UART7": { + "base": 0x40007800, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 92 + "intn": 0x52 }, "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV1", + "UART8": { + "base": 0x40007c00, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 5 + "intn": 0x53 }, "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 80 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c }, "type": "peripheral" }, - "SAI1": { - "base": 0x40015800, - "struct": "STM32F4xxSai", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 87 + "intn": 0x25 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" - }, - "SDIO": { - "base": 0x40012c00, - "struct": "STM32F4xxSdio", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 49 + "intn": 0x47 }, "type": "peripheral" }, - "SPI1": { - "base": 0x40013000, - "struct": "STM32F4xxSpi", + "UART9": { + "base": 0x40011800, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 35 + "intn": 0x58 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", + "UART10": { + "base": 0x40011c00, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 36 + "intn": 0x59 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, - "struct": "STM32F4xxSpi", + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "SDIO": { + "base": 0x40012c00, + "struct": "STM32F4xxSdio", "kwargs": { - "intn": 51 + "intn": 0x31 }, "type": "peripheral" }, - "SPI4": { - "base": 0x40013400, + "SPI1": { + "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 84 + "intn": 0x23 }, "type": "peripheral" }, - "SPI5": { - "base": 0x40015000, + "SPI4": { + "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 85 + "intn": 0x54 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F4xxSyscfgV1", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, "type": "peripheral" }, "TIM10": { @@ -385,171 +415,141 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", + "SPI5": { + "base": 0x40015000, + "struct": "STM32F4xxSpi", "kwargs": { - "intn": 28 + "intn": 0x55 }, "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", + "SAI1": { + "base": 0x40015800, + "struct": "STM32F4xxSai", "kwargs": { - "intn": 29 + "intn": 0x57 }, "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "UART10": { - "base": 0x40011c00, - "struct": "STM32F4xxUsart", - "kwargs": { - "intn": 89 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", - "kwargs": { - "intn": 52 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", - "kwargs": { - "intn": 53 - }, + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "UART7": { - "base": 0x40007800, - "struct": "STM32F4xxUsart", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV1", "kwargs": { - "intn": 82 + "intn": 0x5 }, "type": "peripheral" }, - "UART8": { - "base": 0x40007c00, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 83 + "intn": 0x4 }, "type": "peripheral" }, - "UART9": { - "base": 0x40011800, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 88 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 37 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", "kwargs": { - "intn": 38 + "intn": 0x50 }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "QUADSPI": { + "base": 0xa0001000, + "struct": "STM32F4xxQuadspi", "kwargs": { - "intn": 39 + "intn": 0x5c }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 71 + "dev_id": 0x413 }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", - "kwargs": { - "intn": 0 - }, - "type": "peripheral" + "CODE": { + "base": 0x8000000, + "size": 0x180000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f415.py b/qiling/extensions/mcu/stm32f4/stm32f415.py index 18922b4af..7c47e814f 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f415.py +++ b/qiling/extensions/mcu/stm32f4/stm32f415.py @@ -4,178 +4,203 @@ # stm32f415 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" + }, + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" + }, + "FLASH": { + "base": 0x8000000, + "size": 0x100000, + "type": "memory" + }, + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 + "intn": 0x1c }, "type": "peripheral" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 + "intn": 0x1d }, "type": "peripheral" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" - }, - "CRYP": { - "base": 0x50060000, - "struct": "STM32F4xxCryp", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 79 + "intn": 0x1e }, "type": "peripheral" }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" - }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x32 }, - "type": "core peripheral" + "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "dac_intn": 0x36 }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x100000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x100000, - "type": "memory" + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", "kwargs": { - "intn": 4, + "alarm_intn": 0x29, + "wkup_intn": 0x3 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOI": { - "base": 0x40022000, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, "type": "peripheral" }, - "HASH": { - "base": 0x50060400, - "struct": "STM32F4xxHash", + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", "kwargs": { - "rng_intn": 80 + "intn": 0x35 }, "type": "peripheral" }, @@ -183,8 +208,8 @@ "base": 0x40005400, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -192,8 +217,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -201,146 +226,125 @@ "base": 0x40005c00, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f + }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV2", - "kwargs": { - "intn": 5 - }, + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", + "kwargs": { + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 + }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" - }, - "SDIO": { - "base": 0x40012c00, - "struct": "STM32F4xxSdio", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 49 + "intn": 0x25 }, "type": "peripheral" }, - "SPI1": { - "base": 0x40013000, - "struct": "STM32F4xxSpi", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 35 + "intn": 0x47 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "SDIO": { + "base": 0x40012c00, + "struct": "STM32F4xxSdio", "kwargs": { - "intn": 36 + "intn": 0x31 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, + "SPI1": { + "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 51 + "intn": 0x23 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, "type": "peripheral" }, "TIM10": { @@ -353,139 +357,135 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 - }, + "GPIOI": { + "base": 0x40022000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV2", "kwargs": { - "intn": 52 + "intn": 0x5 }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 53 + "intn": 0x4 }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 37 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 38 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "CRYP": { + "base": 0x50060000, + "struct": "STM32F4xxCryp", "kwargs": { - "intn": 39 + "intn": 0x4f }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "HASH": { + "base": 0x50060400, + "struct": "STM32F4xxHash", "kwargs": { - "intn": 71 + "rng_intn": 0x50 }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", + "type": "peripheral" + }, + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x100000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f417.py b/qiling/extensions/mcu/stm32f4/stm32f417.py index 8111285af..22a25c06a 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f417.py +++ b/qiling/extensions/mcu/stm32f4/stm32f417.py @@ -4,195 +4,203 @@ # stm32f417 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 - }, - "type": "peripheral" + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 - }, - "type": "peripheral" + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" + "FLASH": { + "base": 0x8000000, + "size": 0x100000, + "type": "memory" }, - "CRYP": { - "base": 0x50060000, - "struct": "STM32F4xxCryp", + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 79 + "intn": 0x1c }, "type": "peripheral" }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" - }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x1d }, - "type": "core peripheral" + "type": "peripheral" }, - "DCMI": { - "base": 0x50050000, - "struct": "STM32F4xxDcmi", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 78 + "intn": 0x1e }, "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x32 }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "dac_intn": 0x36 }, "type": "peripheral" }, - "ETH": { - "base": 0x40028000, - "struct": "STM32F4xxEth", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 61, - "wkup_intn": 62 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x100000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x100000, - "type": "memory" + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", "kwargs": { - "intn": 4, + "alarm_intn": 0x29, + "wkup_intn": 0x3 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOI": { - "base": 0x40022000, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, "type": "peripheral" }, - "HASH": { - "base": 0x50060400, - "struct": "STM32F4xxHash", + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", "kwargs": { - "rng_intn": 80 + "intn": 0x35 }, "type": "peripheral" }, @@ -200,8 +208,8 @@ "base": 0x40005400, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -209,8 +217,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -218,146 +226,125 @@ "base": 0x40005c00, "struct": "STM32F4xxI2cV1", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f + }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV2", - "kwargs": { - "intn": 5 - }, + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", + "kwargs": { + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 + }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" - }, - "SDIO": { - "base": 0x40012c00, - "struct": "STM32F4xxSdio", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 49 + "intn": 0x25 }, "type": "peripheral" }, - "SPI1": { - "base": 0x40013000, - "struct": "STM32F4xxSpi", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 35 + "intn": 0x47 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "SDIO": { + "base": 0x40012c00, + "struct": "STM32F4xxSdio", "kwargs": { - "intn": 36 + "intn": 0x31 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, + "SPI1": { + "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 51 + "intn": 0x23 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, "type": "peripheral" }, "TIM10": { @@ -370,139 +357,152 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOI": { + "base": 0x40022000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", + "type": "peripheral" + }, + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV2", "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 + "intn": 0x5 }, "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", + "kwargs": { + "intn": 0x4 + }, "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 52 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 53 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "ETH": { + "base": 0x40028000, + "struct": "STM32F4xxEth", "kwargs": { - "intn": 37 + "intn": 0x3d, + "wkup_intn": 0x3e }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "DCMI": { + "base": 0x50050000, + "struct": "STM32F4xxDcmi", "kwargs": { - "intn": 38 + "intn": 0x4e }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "CRYP": { + "base": 0x50060000, + "struct": "STM32F4xxCryp", "kwargs": { - "intn": 39 + "intn": 0x4f }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "HASH": { + "base": 0x50060400, + "struct": "STM32F4xxHash", "kwargs": { - "intn": 71 + "rng_intn": 0x50 }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", + "type": "peripheral" + }, + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x100000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f423.py b/qiling/extensions/mcu/stm32f4/stm32f423.py index e4ef4bb89..f6904cc5b 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f423.py +++ b/qiling/extensions/mcu/stm32f4/stm32f423.py @@ -4,184 +4,220 @@ # stm32f423 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "AES": { - "base": 0x50060000, - "struct": "STM32F423Aes", + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" + }, + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" + }, + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" + }, + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" + }, + "FLASH": { + "base": 0x8000000, + "size": 0x180000, + "type": "memory" + }, + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 79 + "intn": 0x1c }, "type": "peripheral" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 + "intn": 0x1d }, "type": "peripheral" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 + "intn": 0x1e }, "type": "peripheral" }, - "CAN3": { - "base": 0x40006c00, - "struct": "STM32F4xxCan", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 75, - "rx1_intn": 76, - "sce_intn": 77, - "tx_intn": 74 + "intn": 0x32 }, "type": "peripheral" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" - }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" - }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "dac_intn": 0x36 }, - "type": "core peripheral" + "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x37 }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", - "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 - }, + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x180000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x180000, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "LPTIM1": { + "base": 0x40002400, + "struct": "STM32F4xxLptim", + "kwargs": { + "intn": 0x61 + }, + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", "kwargs": { - "intn": 4, + "alarm_intn": 0x29, + "wkup_intn": 0x3 }, "type": "peripheral" }, - "FMPI2C1": { - "base": 0x40006000, - "struct": "STM32F4xxFmpi2c", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", "kwargs": { - "er_intn": 96, - "ev_intn": 95 + "intn": 0x0 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, + "type": "peripheral" + }, + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x35 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -189,8 +225,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -198,189 +234,175 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "FMPI2C1": { + "base": 0x40006000, + "struct": "STM32F4xxFmpi2c", + "kwargs": { + "er_intn": 0x60, + "ev_intn": 0x5f + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "LPTIM1": { - "base": 0x40002400, - "struct": "STM32F4xxLptim", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", "kwargs": { - "intn": 97 + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" + "CAN3": { + "base": 0x40006c00, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x4b, + "rx1_intn": 0x4c, + "sce_intn": 0x4d, + "tx_intn": 0x4a + }, + "type": "peripheral" }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "QUADSPI": { - "base": 0xa0001000, - "struct": "STM32F4xxQuadspi", + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", + "type": "peripheral" + }, + "UART7": { + "base": 0x40007800, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 92 + "intn": 0x52 }, "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV1", + "UART8": { + "base": 0x40007c00, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 5 + "intn": 0x53 }, "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 80 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c }, "type": "peripheral" }, - "SAI1": { - "base": 0x40015800, - "struct": "STM32F4xxSai", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 87 + "intn": 0x25 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" - }, - "SDIO": { - "base": 0x40012c00, - "struct": "STM32F4xxSdio", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 49 + "intn": 0x47 }, "type": "peripheral" }, - "SPI1": { - "base": 0x40013000, - "struct": "STM32F4xxSpi", + "UART9": { + "base": 0x40011800, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 35 + "intn": 0x58 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", + "UART10": { + "base": 0x40011c00, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 36 + "intn": 0x59 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, - "struct": "STM32F4xxSpi", + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "SDIO": { + "base": 0x40012c00, + "struct": "STM32F4xxSdio", "kwargs": { - "intn": 51 + "intn": 0x31 }, "type": "peripheral" }, - "SPI4": { - "base": 0x40013400, + "SPI1": { + "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 84 + "intn": 0x23 }, "type": "peripheral" }, - "SPI5": { - "base": 0x40015000, + "SPI4": { + "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 85 + "intn": 0x54 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F4xxSyscfgV1", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, "type": "peripheral" }, "TIM10": { @@ -393,171 +415,149 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", + "SPI5": { + "base": 0x40015000, + "struct": "STM32F4xxSpi", "kwargs": { - "intn": 28 + "intn": 0x55 }, "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", + "SAI1": { + "base": 0x40015800, + "struct": "STM32F4xxSai", "kwargs": { - "intn": 29 + "intn": 0x57 }, "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "UART10": { - "base": 0x40011c00, - "struct": "STM32F4xxUsart", - "kwargs": { - "intn": 89 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", - "kwargs": { - "intn": 52 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", - "kwargs": { - "intn": 53 - }, + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "UART7": { - "base": 0x40007800, - "struct": "STM32F4xxUsart", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV1", "kwargs": { - "intn": 82 + "intn": 0x5 }, "type": "peripheral" }, - "UART8": { - "base": 0x40007c00, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 83 + "intn": 0x4 }, "type": "peripheral" }, - "UART9": { - "base": 0x40011800, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 88 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 37 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "AES": { + "base": 0x50060000, + "struct": "STM32F423Aes", "kwargs": { - "intn": 38 + "intn": 0x4f }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", "kwargs": { - "intn": 39 + "intn": 0x50 }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "QUADSPI": { + "base": 0xa0001000, + "struct": "STM32F4xxQuadspi", "kwargs": { - "intn": 71 + "intn": 0x5c }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x180000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f427.py b/qiling/extensions/mcu/stm32f4/stm32f427.py index f16a87007..5bcd1f35a 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f427.py +++ b/qiling/extensions/mcu/stm32f4/stm32f427.py @@ -4,206 +4,212 @@ # stm32f427 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 - }, - "type": "peripheral" + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 - }, - "type": "peripheral" + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" + "FLASH": { + "base": 0x8000000, + "size": 0x200000, + "type": "memory" }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x1c }, - "type": "core peripheral" + "type": "peripheral" }, - "DCMI": { - "base": 0x50050000, - "struct": "STM32F4xxDcmi", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 78 + "intn": 0x1d }, "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x1e }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x32 }, "type": "peripheral" }, - "DMA2D": { - "base": 0x4002b000, - "struct": "STM32F4xxDma2d", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 90 + "dac_intn": 0x36 }, "type": "peripheral" }, - "ETH": { - "base": 0x40028000, - "struct": "STM32F4xxEth", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 61, - "wkup_intn": 62 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x200000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x200000, - "type": "memory" + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", "kwargs": { - "intn": 4, + "alarm_intn": 0x29, + "wkup_intn": 0x3 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", - "type": "peripheral" - }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOI": { - "base": 0x40022000, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOJ": { - "base": 0x40022400, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, "type": "peripheral" }, - "GPIOK": { - "base": 0x40022800, - "struct": "STM32F4xxGpio", + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x35 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -211,8 +217,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -220,92 +226,117 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "PWR": { + "base": 0x40007000, + "struct": "STM32F4xxPwr", "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", + "type": "peripheral" }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" + "UART7": { + "base": 0x40007800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x52 + }, + "type": "peripheral" }, - "PWR": { - "base": 0x40007000, - "struct": "STM32F4xxPwr", + "UART8": { + "base": 0x40007c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x53 + }, "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV3", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 5 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 }, "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", + "kwargs": { + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c + }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "intn": 0x25 }, "type": "peripheral" }, - "SAI1": { - "base": 0x40015800, - "struct": "STM32F4xxSai", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 87 + "intn": 0x47 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", + "type": "peripheral" }, "SDIO": { "base": 0x40012c00, "struct": "STM32F4xxSdio", "kwargs": { - "intn": 49 + "intn": 0x31 }, "type": "peripheral" }, @@ -313,39 +344,48 @@ "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 35 + "intn": 0x23 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, + "SPI4": { + "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 36 + "intn": 0x54 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 51 - }, + "SYSCFG": { + "base": 0x40013800, + "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SPI4": { - "base": 0x40013400, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 84 - }, + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" + }, + "TIM9": { + "base": 0x40014000, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM10": { + "base": 0x40014400, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM11": { + "base": 0x40014800, + "struct": "STM32F4xxTim", "type": "peripheral" }, "SPI5": { "base": 0x40015000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 85 + "intn": 0x55 }, "type": "peripheral" }, @@ -353,206 +393,166 @@ "base": 0x40015400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 86 + "intn": 0x56 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, - "SYSCFG": { - "base": 0x40013800, - "struct": "STM32F4xxSyscfg", - "type": "peripheral" - }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" - }, - "TIM1": { - "base": 0x40010000, - "struct": "STM32F4xxTim", + "SAI1": { + "base": 0x40015800, + "struct": "STM32F4xxSai", "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 + "intn": 0x57 }, "type": "peripheral" }, - "TIM10": { - "base": 0x40014400, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "TIM11": { - "base": 0x40014800, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOI": { + "base": 0x40022000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOJ": { + "base": 0x40022400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 - }, + "GPIOK": { + "base": 0x40022800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV3", "kwargs": { - "intn": 52 + "intn": 0x5 }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 53 + "intn": 0x4 }, "type": "peripheral" }, - "UART7": { - "base": 0x40007800, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 82 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "UART8": { - "base": 0x40007c00, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 83 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "ETH": { + "base": 0x40028000, + "struct": "STM32F4xxEth", "kwargs": { - "intn": 37 + "intn": 0x3d, + "wkup_intn": 0x3e }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "DMA2D": { + "base": 0x4002b000, + "struct": "STM32F4xxDma2d", "kwargs": { - "intn": 38 + "intn": 0x5a }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "DCMI": { + "base": 0x50050000, + "struct": "STM32F4xxDcmi", "kwargs": { - "intn": 39 + "intn": 0x4e }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", - "kwargs": { - "intn": 71 - }, + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x200000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f429.py b/qiling/extensions/mcu/stm32f4/stm32f429.py index 2fe71f815..bf87d82c0 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f429.py +++ b/qiling/extensions/mcu/stm32f4/stm32f429.py @@ -4,206 +4,212 @@ # stm32f429 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 - }, - "type": "peripheral" + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 - }, - "type": "peripheral" + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" + "FLASH": { + "base": 0x8000000, + "size": 0x200000, + "type": "memory" }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x1c }, - "type": "core peripheral" + "type": "peripheral" }, - "DCMI": { - "base": 0x50050000, - "struct": "STM32F4xxDcmi", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 78 + "intn": 0x1d }, "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x1e }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x32 }, "type": "peripheral" }, - "DMA2D": { - "base": 0x4002b000, - "struct": "STM32F4xxDma2d", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 90 + "dac_intn": 0x36 }, "type": "peripheral" }, - "ETH": { - "base": 0x40028000, - "struct": "STM32F4xxEth", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 61, - "wkup_intn": 62 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x200000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x200000, - "type": "memory" + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", "kwargs": { - "intn": 4, + "alarm_intn": 0x29, + "wkup_intn": 0x3 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", - "type": "peripheral" - }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOI": { - "base": 0x40022000, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOJ": { - "base": 0x40022400, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, "type": "peripheral" }, - "GPIOK": { - "base": 0x40022800, - "struct": "STM32F4xxGpio", + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x35 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -211,8 +217,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -220,101 +226,117 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "PWR": { + "base": 0x40007000, + "struct": "STM32F4xxPwr", "type": "peripheral" }, - "LTDC": { - "base": 0x40016800, - "struct": "STM32F4xxLtdc", + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", + "type": "peripheral" + }, + "UART7": { + "base": 0x40007800, + "struct": "STM32F4xxUsart", "kwargs": { - "er_intn": 89, - "intn": 88 + "intn": 0x52 }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" + "UART8": { + "base": 0x40007c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x53 + }, + "type": "peripheral" }, - "PWR": { - "base": 0x40007000, - "struct": "STM32F4xxPwr", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", + "kwargs": { + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 + }, "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV3", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 5 + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c }, "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", - "type": "peripheral" - }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "intn": 0x25 }, "type": "peripheral" }, - "SAI1": { - "base": 0x40015800, - "struct": "STM32F4xxSai", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 87 + "intn": 0x47 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", + "type": "peripheral" }, "SDIO": { "base": 0x40012c00, "struct": "STM32F4xxSdio", "kwargs": { - "intn": 49 + "intn": 0x31 }, "type": "peripheral" }, @@ -322,39 +344,48 @@ "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 35 + "intn": 0x23 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, + "SPI4": { + "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 36 + "intn": 0x54 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 51 - }, + "SYSCFG": { + "base": 0x40013800, + "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SPI4": { - "base": 0x40013400, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 84 - }, + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" + }, + "TIM9": { + "base": 0x40014000, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM10": { + "base": 0x40014400, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM11": { + "base": 0x40014800, + "struct": "STM32F4xxTim", "type": "peripheral" }, "SPI5": { "base": 0x40015000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 85 + "intn": 0x55 }, "type": "peripheral" }, @@ -362,206 +393,175 @@ "base": 0x40015400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 86 + "intn": 0x56 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, - "SYSCFG": { - "base": 0x40013800, - "struct": "STM32F4xxSyscfg", - "type": "peripheral" - }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" - }, - "TIM1": { - "base": 0x40010000, - "struct": "STM32F4xxTim", + "SAI1": { + "base": 0x40015800, + "struct": "STM32F4xxSai", "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 + "intn": 0x57 }, "type": "peripheral" }, - "TIM10": { - "base": 0x40014400, - "struct": "STM32F4xxTim", + "LTDC": { + "base": 0x40016800, + "struct": "STM32F4xxLtdc", + "kwargs": { + "er_intn": 0x59, + "intn": 0x58 + }, "type": "peripheral" }, - "TIM11": { - "base": 0x40014800, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOI": { + "base": 0x40022000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOJ": { + "base": 0x40022400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 - }, + "GPIOK": { + "base": 0x40022800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV3", "kwargs": { - "intn": 52 + "intn": 0x5 }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 53 + "intn": 0x4 }, "type": "peripheral" }, - "UART7": { - "base": 0x40007800, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 82 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "UART8": { - "base": 0x40007c00, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 83 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "ETH": { + "base": 0x40028000, + "struct": "STM32F4xxEth", "kwargs": { - "intn": 37 + "intn": 0x3d, + "wkup_intn": 0x3e }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "DMA2D": { + "base": 0x4002b000, + "struct": "STM32F4xxDma2d", "kwargs": { - "intn": 38 + "intn": 0x5a }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "DCMI": { + "base": 0x50050000, + "struct": "STM32F4xxDcmi", "kwargs": { - "intn": 39 + "intn": 0x4e }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", - "kwargs": { - "intn": 71 - }, + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x200000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f437.py b/qiling/extensions/mcu/stm32f4/stm32f437.py index 98500a2ee..ebe5c80ce 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f437.py +++ b/qiling/extensions/mcu/stm32f4/stm32f437.py @@ -4,213 +4,203 @@ # stm32f437 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 - }, - "type": "peripheral" + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 - }, - "type": "peripheral" + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" + "FLASH": { + "base": 0x8000000, + "size": 0x200000, + "type": "memory" }, - "CRYP": { - "base": 0x50060000, - "struct": "STM32F4xxCryp", - "kwargs": { - "intn": 79 - }, - "type": "peripheral" + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x1c }, - "type": "core peripheral" + "type": "peripheral" }, - "DCMI": { - "base": 0x50050000, - "struct": "STM32F4xxDcmi", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 78 + "intn": 0x1d }, "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x1e }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x32 }, "type": "peripheral" }, - "DMA2D": { - "base": 0x4002b000, - "struct": "STM32F4xxDma2d", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 90 + "dac_intn": 0x36 }, "type": "peripheral" }, - "ETH": { - "base": 0x40028000, - "struct": "STM32F4xxEth", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 61, - "wkup_intn": 62 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x200000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x200000, - "type": "memory" - }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" - }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", - "kwargs": { - "intn": 4, - }, + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", + "kwargs": { + "alarm_intn": 0x29, + "wkup_intn": 0x3 + }, "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOI": { - "base": 0x40022000, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOJ": { - "base": 0x40022400, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOK": { - "base": 0x40022800, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, "type": "peripheral" }, - "HASH": { - "base": 0x50060400, - "struct": "STM32F4xxHash", + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", "kwargs": { - "rng_intn": 80 + "intn": 0x35 }, "type": "peripheral" }, @@ -218,8 +208,8 @@ "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -227,8 +217,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -236,92 +226,117 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "PWR": { + "base": 0x40007000, + "struct": "STM32F4xxPwr", "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", + "type": "peripheral" }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" + "UART7": { + "base": 0x40007800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x52 + }, + "type": "peripheral" }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" + "UART8": { + "base": 0x40007c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x53 + }, + "type": "peripheral" }, - "PWR": { - "base": 0x40007000, - "struct": "STM32F4xxPwr", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", + "kwargs": { + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 + }, "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV3", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 5 + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c }, "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", - "type": "peripheral" - }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "intn": 0x25 }, "type": "peripheral" }, - "SAI1": { - "base": 0x40015800, - "struct": "STM32F4xxSai", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 87 + "intn": 0x47 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", + "type": "peripheral" }, "SDIO": { "base": 0x40012c00, "struct": "STM32F4xxSdio", "kwargs": { - "intn": 49 + "intn": 0x31 }, "type": "peripheral" }, @@ -329,39 +344,48 @@ "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 35 + "intn": 0x23 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, + "SPI4": { + "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 36 + "intn": 0x54 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 51 - }, + "SYSCFG": { + "base": 0x40013800, + "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SPI4": { - "base": 0x40013400, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 84 - }, + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" + }, + "TIM9": { + "base": 0x40014000, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM10": { + "base": 0x40014400, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM11": { + "base": 0x40014800, + "struct": "STM32F4xxTim", "type": "peripheral" }, "SPI5": { "base": 0x40015000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 85 + "intn": 0x55 }, "type": "peripheral" }, @@ -369,206 +393,182 @@ "base": 0x40015400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 86 + "intn": 0x56 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, - "SYSCFG": { - "base": 0x40013800, - "struct": "STM32F4xxSyscfg", + "SAI1": { + "base": 0x40015800, + "struct": "STM32F4xxSai", + "kwargs": { + "intn": 0x57 + }, "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM10": { - "base": 0x40014400, - "struct": "STM32F4xxTim", + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM11": { - "base": 0x40014800, - "struct": "STM32F4xxTim", + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOI": { + "base": 0x40022000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOJ": { + "base": 0x40022400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOK": { + "base": 0x40022800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV3", "kwargs": { - "intn": 55 + "intn": 0x5 }, "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 + "intn": 0x4 }, "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 52 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 53 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "UART7": { - "base": 0x40007800, - "struct": "STM32F4xxUsart", + "ETH": { + "base": 0x40028000, + "struct": "STM32F4xxEth", "kwargs": { - "intn": 82 + "intn": 0x3d, + "wkup_intn": 0x3e }, "type": "peripheral" }, - "UART8": { - "base": 0x40007c00, - "struct": "STM32F4xxUsart", + "DMA2D": { + "base": 0x4002b000, + "struct": "STM32F4xxDma2d", "kwargs": { - "intn": 83 + "intn": 0x5a }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "DCMI": { + "base": 0x50050000, + "struct": "STM32F4xxDcmi", "kwargs": { - "intn": 37 + "intn": 0x4e }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "CRYP": { + "base": 0x50060000, + "struct": "STM32F4xxCryp", "kwargs": { - "intn": 38 + "intn": 0x4f }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "HASH": { + "base": 0x50060400, + "struct": "STM32F4xxHash", "kwargs": { - "intn": 39 + "rng_intn": 0x50 }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", - "kwargs": { - "intn": 71 - }, + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x200000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f439.py b/qiling/extensions/mcu/stm32f4/stm32f439.py index 64da47b10..779fcd298 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f439.py +++ b/qiling/extensions/mcu/stm32f4/stm32f439.py @@ -4,213 +4,203 @@ # stm32f439 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 - }, - "type": "peripheral" + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 - }, - "type": "peripheral" + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" + "FLASH": { + "base": 0x8000000, + "size": 0x200000, + "type": "memory" }, - "CRYP": { - "base": 0x50060000, - "struct": "STM32F4xxCryp", - "kwargs": { - "intn": 79 - }, - "type": "peripheral" + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x1c }, - "type": "core peripheral" + "type": "peripheral" }, - "DCMI": { - "base": 0x50050000, - "struct": "STM32F4xxDcmi", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 78 + "intn": 0x1d }, "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x1e }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x32 }, "type": "peripheral" }, - "DMA2D": { - "base": 0x4002b000, - "struct": "STM32F4xxDma2d", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 90 + "dac_intn": 0x36 }, "type": "peripheral" }, - "ETH": { - "base": 0x40028000, - "struct": "STM32F4xxEth", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 61, - "wkup_intn": 62 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x200000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x200000, - "type": "memory" - }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" - }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", - "kwargs": { - "intn": 4, - }, + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", + "kwargs": { + "alarm_intn": 0x29, + "wkup_intn": 0x3 + }, "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOI": { - "base": 0x40022000, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOJ": { - "base": 0x40022400, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOK": { - "base": 0x40022800, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, "type": "peripheral" }, - "HASH": { - "base": 0x50060400, - "struct": "STM32F4xxHash", + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", "kwargs": { - "rng_intn": 80 + "intn": 0x35 }, "type": "peripheral" }, @@ -218,8 +208,8 @@ "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -227,8 +217,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -236,101 +226,117 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f + }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "PWR": { + "base": 0x40007000, + "struct": "STM32F4xxPwr", "type": "peripheral" }, - "LTDC": { - "base": 0x40016800, - "struct": "STM32F4xxLtdc", + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", + "type": "peripheral" + }, + "UART7": { + "base": 0x40007800, + "struct": "STM32F4xxUsart", "kwargs": { - "er_intn": 89, - "intn": 88 + "intn": 0x52 }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, - "PWR": { - "base": 0x40007000, - "struct": "STM32F4xxPwr", + "UART8": { + "base": 0x40007c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x53 + }, "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV3", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 5 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 }, "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", + "kwargs": { + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c + }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "intn": 0x25 }, "type": "peripheral" }, - "SAI1": { - "base": 0x40015800, - "struct": "STM32F4xxSai", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 87 + "intn": 0x47 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", + "type": "peripheral" }, "SDIO": { "base": 0x40012c00, "struct": "STM32F4xxSdio", "kwargs": { - "intn": 49 + "intn": 0x31 }, "type": "peripheral" }, @@ -338,39 +344,48 @@ "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 35 + "intn": 0x23 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, + "SPI4": { + "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 36 + "intn": 0x54 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 51 - }, + "SYSCFG": { + "base": 0x40013800, + "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SPI4": { - "base": 0x40013400, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 84 - }, + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" + }, + "TIM9": { + "base": 0x40014000, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM10": { + "base": 0x40014400, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM11": { + "base": 0x40014800, + "struct": "STM32F4xxTim", "type": "peripheral" }, "SPI5": { "base": 0x40015000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 85 + "intn": 0x55 }, "type": "peripheral" }, @@ -378,206 +393,191 @@ "base": 0x40015400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 86 + "intn": 0x56 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, - "SYSCFG": { - "base": 0x40013800, - "struct": "STM32F4xxSyscfg", + "SAI1": { + "base": 0x40015800, + "struct": "STM32F4xxSai", + "kwargs": { + "intn": 0x57 + }, "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" - }, - "TIM1": { - "base": 0x40010000, - "struct": "STM32F4xxTim", + "LTDC": { + "base": 0x40016800, + "struct": "STM32F4xxLtdc", "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 + "er_intn": 0x59, + "intn": 0x58 }, "type": "peripheral" }, - "TIM10": { - "base": 0x40014400, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM11": { - "base": 0x40014800, - "struct": "STM32F4xxTim", + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOI": { + "base": 0x40022000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOJ": { + "base": 0x40022400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOK": { + "base": 0x40022800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 - }, + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV3", + "kwargs": { + "intn": 0x5 + }, "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 52 + "intn": 0x4 }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 53 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "UART7": { - "base": 0x40007800, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 82 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "UART8": { - "base": 0x40007c00, - "struct": "STM32F4xxUsart", + "ETH": { + "base": 0x40028000, + "struct": "STM32F4xxEth", "kwargs": { - "intn": 83 + "intn": 0x3d, + "wkup_intn": 0x3e }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "DMA2D": { + "base": 0x4002b000, + "struct": "STM32F4xxDma2d", "kwargs": { - "intn": 37 + "intn": 0x5a }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "DCMI": { + "base": 0x50050000, + "struct": "STM32F4xxDcmi", "kwargs": { - "intn": 38 + "intn": 0x4e }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "CRYP": { + "base": 0x50060000, + "struct": "STM32F4xxCryp", "kwargs": { - "intn": 39 + "intn": 0x4f }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "HASH": { + "base": 0x50060400, + "struct": "STM32F4xxHash", "kwargs": { - "intn": 71 + "rng_intn": 0x50 }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", + "type": "peripheral" + }, + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x200000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f446.py b/qiling/extensions/mcu/stm32f4/stm32f446.py index cc8f6b086..4d0fa0fc1 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f446.py +++ b/qiling/extensions/mcu/stm32f4/stm32f446.py @@ -4,191 +4,207 @@ # stm32f446 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 - }, - "type": "peripheral" + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" + }, + "FLASH": { + "base": 0x8000000, + "size": 0x80000, + "type": "memory" + }, + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" + }, + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 + "intn": 0x1c }, "type": "peripheral" }, - "CEC": { - "base": 0x40006c00, - "struct": "STM32F446Cec", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 93 + "intn": 0x1d }, "type": "peripheral" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" - }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" - }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "dev_id": 0x413, + "intn": 0x1e }, - "type": "core peripheral" + "type": "peripheral" }, - "DCMI": { - "base": 0x50050000, - "struct": "STM32F4xxDcmi", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 78 + "intn": 0x32 }, "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "dac_intn": 0x36 }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x80000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x80000, - "type": "memory" + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", "kwargs": { - "intn": 4, + "alarm_intn": 0x29, + "wkup_intn": 0x3 }, "type": "peripheral" }, - "FMPI2C1": { - "base": 0x40006000, - "struct": "STM32F4xxFmpi2c", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", "kwargs": { - "er_intn": 96, - "ev_intn": 95 + "intn": 0x0 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "SPDIFRX": { + "base": 0x40004000, + "struct": "STM32F446Spdifrx", "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x35 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -196,8 +212,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -205,122 +221,126 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "FMPI2C1": { + "base": 0x40006000, + "struct": "STM32F4xxFmpi2c", + "kwargs": { + "er_intn": 0x60, + "ev_intn": 0x5f + }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, + "type": "peripheral" }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f + }, + "type": "peripheral" }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" + "CEC": { + "base": 0x40006c00, + "struct": "STM32F446Cec", + "kwargs": { + "intn": 0x5d + }, + "type": "peripheral" }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "QUADSPI": { - "base": 0xa0001000, - "struct": "STM32F4xxQuadspi", - "kwargs": { - "intn": 92 - }, + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F446Rcc", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 5 + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c }, "type": "peripheral" }, - "SAI1": { - "base": 0x40015800, - "struct": "STM32F4xxSai", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 87 + "intn": 0x25 }, "type": "peripheral" }, - "SAI2": { - "base": 0x40015c00, - "struct": "STM32F4xxSai", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 91 + "intn": 0x47 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" - }, - "SDIO": { - "base": 0x40012c00, - "struct": "STM32F4xxSdio", - "kwargs": { - "intn": 49 - }, + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", "type": "peripheral" }, - "SPDIFRX": { - "base": 0x40004000, - "struct": "STM32F446Spdifrx", + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", "type": "peripheral" }, - "SPI1": { - "base": 0x40013000, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 35 - }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, - "struct": "STM32F4xxSpi", + "SDIO": { + "base": 0x40012c00, + "struct": "STM32F4xxSdio", "kwargs": { - "intn": 36 + "intn": 0x31 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, + "SPI1": { + "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 51 + "intn": 0x23 }, "type": "peripheral" }, @@ -328,45 +348,23 @@ "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 84 + "intn": 0x54 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, "SYSCFG": { "base": 0x40013800, "struct": "STM32F446Syscfg", "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, + "TIM9": { + "base": 0x40014000, "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, "type": "peripheral" }, "TIM10": { @@ -379,139 +377,141 @@ "struct": "STM32F4xxTim", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", + "SAI1": { + "base": 0x40015800, + "struct": "STM32F4xxSai", + "kwargs": { + "intn": 0x57 + }, "type": "peripheral" }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "SAI2": { + "base": 0x40015c00, + "struct": "STM32F4xxSai", + "kwargs": { + "intn": 0x5b + }, "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "RCC": { + "base": 0x40023800, + "struct": "STM32F446Rcc", "kwargs": { - "intn": 52 + "intn": 0x5 }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 53 + "intn": 0x4 }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 37 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 38 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "DCMI": { + "base": 0x50050000, + "struct": "STM32F4xxDcmi", "kwargs": { - "intn": 39 + "intn": 0x4e }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "QUADSPI": { + "base": 0xa0001000, + "struct": "STM32F4xxQuadspi", "kwargs": { - "intn": 71 + "intn": 0x5c }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x80000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f469.py b/qiling/extensions/mcu/stm32f4/stm32f469.py index a96643678..527aa390d 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f469.py +++ b/qiling/extensions/mcu/stm32f4/stm32f469.py @@ -4,214 +4,212 @@ # stm32f469 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 - }, - "type": "peripheral" + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 - }, - "type": "peripheral" + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" + "FLASH": { + "base": 0x8000000, + "size": 0x200000, + "type": "memory" }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", - "kwargs": { - "dev_id": 0x413, - }, - "type": "core peripheral" + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" }, - "DCMI": { - "base": 0x50050000, - "struct": "STM32F4xxDcmi", + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 78 + "intn": 0x1c }, "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x1d }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x1e }, "type": "peripheral" }, - "DMA2D": { - "base": 0x4002b000, - "struct": "STM32F4xxDma2d", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 90 + "intn": 0x32 }, "type": "peripheral" }, - "DSI": { - "base": 0x40016c00, - "struct": "STM32F4xxDsi", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 92 + "dac_intn": 0x36 }, "type": "peripheral" }, - "ETH": { - "base": 0x40028000, - "struct": "STM32F4xxEth", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 61, - "wkup_intn": 62 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x200000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x200000, - "type": "memory" + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", + "type": "peripheral" }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", "kwargs": { - "intn": 4, + "alarm_intn": 0x29, + "wkup_intn": 0x3 }, "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", - "type": "peripheral" - }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOI": { - "base": 0x40022000, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOJ": { - "base": 0x40022400, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, "type": "peripheral" }, - "GPIOK": { - "base": 0x40022800, - "struct": "STM32F4xxGpio", + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x35 + }, "type": "peripheral" }, "I2C1": { "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -219,8 +217,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -228,109 +226,117 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "LTDC": { - "base": 0x40016800, - "struct": "STM32F4xxLtdc", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", "kwargs": { - "er_intn": 89, - "intn": 88 + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "QUADSPI": { - "base": 0xa0001000, - "struct": "STM32F4xxQuadspi", + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", + "type": "peripheral" + }, + "UART7": { + "base": 0x40007800, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 91 + "intn": 0x52 }, "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV3", + "UART8": { + "base": 0x40007c00, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 5 + "intn": 0x53 }, "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", + "kwargs": { + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 + }, + "type": "peripheral" + }, + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", + "kwargs": { + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c + }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "intn": 0x25 }, "type": "peripheral" }, - "SAI1": { - "base": 0x40015800, - "struct": "STM32F4xxSai", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 87 + "intn": 0x47 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", + "type": "peripheral" }, "SDIO": { "base": 0x40012c00, "struct": "STM32F4xxSdio", "kwargs": { - "intn": 49 + "intn": 0x31 }, "type": "peripheral" }, @@ -338,39 +344,48 @@ "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 35 + "intn": 0x23 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, + "SPI4": { + "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 36 + "intn": 0x54 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 51 - }, + "SYSCFG": { + "base": 0x40013800, + "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SPI4": { - "base": 0x40013400, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 84 - }, + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" + }, + "TIM9": { + "base": 0x40014000, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM10": { + "base": 0x40014400, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM11": { + "base": 0x40014800, + "struct": "STM32F4xxTim", "type": "peripheral" }, "SPI5": { "base": 0x40015000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 85 + "intn": 0x55 }, "type": "peripheral" }, @@ -378,206 +393,191 @@ "base": 0x40015400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 86 + "intn": 0x56 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" - }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" - }, - "SYSCFG": { - "base": 0x40013800, - "struct": "STM32F4xxSyscfg", + "SAI1": { + "base": 0x40015800, + "struct": "STM32F4xxSai", + "kwargs": { + "intn": 0x57 + }, "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" - }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" - }, - "TIM1": { - "base": 0x40010000, - "struct": "STM32F4xxTim", + "LTDC": { + "base": 0x40016800, + "struct": "STM32F4xxLtdc", "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 + "er_intn": 0x59, + "intn": 0x58 }, "type": "peripheral" }, - "TIM10": { - "base": 0x40014400, - "struct": "STM32F4xxTim", + "DSI": { + "base": 0x40016c00, + "struct": "STM32F4xxDsi", + "kwargs": { + "intn": 0x5c + }, "type": "peripheral" }, - "TIM11": { - "base": 0x40014800, - "struct": "STM32F4xxTim", + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", - "kwargs": { - "dac_intn": 54 - }, + "GPIOI": { + "base": 0x40022000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 55 - }, + "GPIOJ": { + "base": 0x40022400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 - }, + "GPIOK": { + "base": 0x40022800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV3", "kwargs": { - "intn": 52 + "intn": 0x5 }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 53 + "intn": 0x4 }, "type": "peripheral" }, - "UART7": { - "base": 0x40007800, - "struct": "STM32F4xxUsart", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 82 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "UART8": { - "base": 0x40007c00, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 83 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "ETH": { + "base": 0x40028000, + "struct": "STM32F4xxEth", "kwargs": { - "intn": 37 + "intn": 0x3d, + "wkup_intn": 0x3e }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "DMA2D": { + "base": 0x4002b000, + "struct": "STM32F4xxDma2d", "kwargs": { - "intn": 38 + "intn": 0x5a }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", + "DCMI": { + "base": 0x50050000, + "struct": "STM32F4xxDcmi", "kwargs": { - "intn": 39 + "intn": 0x4e }, "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", + "type": "peripheral" + }, + "QUADSPI": { + "base": 0xa0001000, + "struct": "STM32F4xxQuadspi", "kwargs": { - "intn": 71 + "intn": 0x5b }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x200000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file diff --git a/qiling/extensions/mcu/stm32f4/stm32f479.py b/qiling/extensions/mcu/stm32f4/stm32f479.py index 9a605bf3c..6a504fe5c 100644 --- a/qiling/extensions/mcu/stm32f4/stm32f479.py +++ b/qiling/extensions/mcu/stm32f4/stm32f479.py @@ -4,221 +4,203 @@ # stm32f479 = { - "ADC1": { - "base": 0x40012000, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" }, - "ADC2": { - "base": 0x40012100, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" }, - "ADC3": { - "base": 0x40012200, - "struct": "STM32F4xxAdc", - "type": "peripheral" + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM4SysTick", + "type": "core" }, - "CAN1": { - "base": 0x40006400, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 20, - "rx1_intn": 21, - "sce_intn": 22, - "tx_intn": 19 - }, - "type": "peripheral" + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM4Nvic", + "type": "core" }, - "CAN2": { - "base": 0x40006800, - "struct": "STM32F4xxCan", - "kwargs": { - "rx0_intn": 64, - "rx1_intn": 65, - "sce_intn": 66, - "tx_intn": 63 - }, - "type": "peripheral" + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM4Scb", + "type": "core" }, - "CRC": { - "base": 0x40023000, - "struct": "STM32F4xxCrc", - "type": "peripheral" + "FLASH": { + "base": 0x8000000, + "size": 0x200000, + "type": "memory" }, - "CRYP": { - "base": 0x50060000, - "struct": "STM32F4xxCryp", - "kwargs": { - "intn": 79 - }, - "type": "peripheral" + "SYSTEM": { + "base": 0x1fff0000, + "size": 0x7800, + "type": "memory" }, - "DAC1": { - "base": 0x40007400, - "struct": "STM32F4xxDac", - "type": "peripheral" + "FLASH OTP": { + "base": 0x1fff7800, + "size": 0x400, + "type": "memory" }, - "DBGMCU": { - "base": 0xe0042000, - "struct": "STM32F4xxDbgmcu", - "kwargs": { - "dev_id": 0x413, - }, - "type": "core peripheral" + "SRAM": { + "base": 0x20000000, + "size": 0x20000, + "type": "memory" }, - "DCMI": { - "base": 0x50050000, - "struct": "STM32F4xxDcmi", + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "base": 0x40000000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 78 + "intn": 0x1c }, "type": "peripheral" }, - "DMA1": { - "base": 0x40026000, - "struct": "STM32F4xxDma", + "TIM3": { + "base": 0x40000400, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 11, - "stream1_intn": 12, - "stream2_intn": 13, - "stream3_intn": 14, - "stream4_intn": 15, - "stream5_intn": 16, - "stream6_intn": 17, - "stream7_intn": 47 + "intn": 0x1d }, "type": "peripheral" }, - "DMA2": { - "base": 0x40026400, - "struct": "STM32F4xxDma", + "TIM4": { + "base": 0x40000800, + "struct": "STM32F4xxTim", "kwargs": { - "stream0_intn": 56, - "stream1_intn": 57, - "stream2_intn": 58, - "stream3_intn": 59, - "stream4_intn": 60, - "stream5_intn": 68, - "stream6_intn": 69, - "stream7_intn": 70 + "intn": 0x1e }, "type": "peripheral" }, - "DMA2D": { - "base": 0x4002b000, - "struct": "STM32F4xxDma2d", + "TIM5": { + "base": 0x40000c00, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 90 + "intn": 0x32 }, "type": "peripheral" }, - "DSI": { - "base": 0x40016c00, - "struct": "STM32F4xxDsi", + "TIM6": { + "base": 0x40001000, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 92 + "dac_intn": 0x36 }, "type": "peripheral" }, - "ETH": { - "base": 0x40028000, - "struct": "STM32F4xxEth", + "TIM7": { + "base": 0x40001400, + "struct": "STM32F4xxTim", "kwargs": { - "intn": 61, - "wkup_intn": 62 + "intn": 0x37 }, "type": "peripheral" }, - "EXTI": { - "base": 0x40013c00, - "struct": "STM32F4xxExti", + "TIM12": { + "base": 0x40001800, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "CODE": { - "base": 0x08000000, - "size": 0x200000, - "alias": 0x0, - "type": "remap" - }, - "FLASH": { - "base": 0x08000000, - "size": 0x200000, - "type": "memory" - }, - "FLASH OTP": { - "base": 0x1fff7800, - "size": 0x400, - "type": "memory" - }, - "FLASH INTERFACE": { - "base": 0x40023c00, - "struct": "STM32F4xxFlash", - "kwargs": { - "intn": 4, - }, + "TIM13": { + "base": 0x40001c00, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "GPIOA": { - "base": 0x40020000, - "struct": "STM32F4xxGpio", + "TIM14": { + "base": 0x40002000, + "struct": "STM32F4xxTim", "type": "peripheral" }, - "GPIOB": { - "base": 0x40020400, - "struct": "STM32F4xxGpio", + "RTC": { + "base": 0x40002800, + "struct": "STM32F4xxRtc", + "kwargs": { + "alarm_intn": 0x29, + "wkup_intn": 0x3 + }, "type": "peripheral" }, - "GPIOC": { - "base": 0x40020800, - "struct": "STM32F4xxGpio", + "WWDG": { + "base": 0x40002c00, + "struct": "STM32F4xxWwdg", + "kwargs": { + "intn": 0x0 + }, "type": "peripheral" }, - "GPIOD": { - "base": 0x40020c00, - "struct": "STM32F4xxGpio", + "IWDG": { + "base": 0x40003000, + "struct": "STM32F4xxIwdg", "type": "peripheral" }, - "GPIOE": { - "base": 0x40021000, - "struct": "STM32F4xxGpio", + "I2S2ext": { + "base": 0x40003400, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOF": { - "base": 0x40021400, - "struct": "STM32F4xxGpio", + "SPI2": { + "base": 0x40003800, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x24 + }, "type": "peripheral" }, - "GPIOG": { - "base": 0x40021800, - "struct": "STM32F4xxGpio", + "SPI3": { + "base": 0x40003c00, + "struct": "STM32F4xxSpi", + "kwargs": { + "intn": 0x33 + }, "type": "peripheral" }, - "GPIOH": { - "base": 0x40021c00, - "struct": "STM32F4xxGpio", + "I2S3ext": { + "base": 0x40004000, + "struct": "STM32F4xxSpi", "type": "peripheral" }, - "GPIOI": { - "base": 0x40022000, - "struct": "STM32F4xxGpio", + "USART2": { + "base": 0x40004400, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x26 + }, "type": "peripheral" }, - "GPIOJ": { - "base": 0x40022400, - "struct": "STM32F4xxGpio", + "USART3": { + "base": 0x40004800, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x27 + }, "type": "peripheral" }, - "GPIOK": { - "base": 0x40022800, - "struct": "STM32F4xxGpio", + "UART4": { + "base": 0x40004c00, + "struct": "STM32F4xxUsart", + "kwargs": { + "intn": 0x34 + }, "type": "peripheral" }, - "HASH": { - "base": 0x50060400, - "struct": "STM32F4xxHash", + "UART5": { + "base": 0x40005000, + "struct": "STM32F4xxUsart", "kwargs": { - "rng_intn": 80 + "intn": 0x35 }, "type": "peripheral" }, @@ -226,8 +208,8 @@ "base": 0x40005400, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 32, - "ev_intn": 31 + "er_intn": 0x20, + "ev_intn": 0x1f }, "type": "peripheral" }, @@ -235,8 +217,8 @@ "base": 0x40005800, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 34, - "ev_intn": 33 + "er_intn": 0x22, + "ev_intn": 0x21 }, "type": "peripheral" }, @@ -244,109 +226,117 @@ "base": 0x40005c00, "struct": "STM32F4xxI2c", "kwargs": { - "er_intn": 73, - "ev_intn": 72 + "er_intn": 0x49, + "ev_intn": 0x48 }, "type": "peripheral" }, - "I2S2ext": { - "base": 0x40003400, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "I2S3ext": { - "base": 0x40004000, - "struct": "STM32F4xxSpi", - "type": "peripheral" - }, - "IWDG": { - "base": 0x40003000, - "struct": "STM32F4xxIwdg", + "CAN1": { + "base": 0x40006400, + "struct": "STM32F4xxCan", + "kwargs": { + "rx0_intn": 0x14, + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13 + }, "type": "peripheral" }, - "LTDC": { - "base": 0x40016800, - "struct": "STM32F4xxLtdc", + "CAN2": { + "base": 0x40006800, + "struct": "STM32F4xxCan", "kwargs": { - "er_intn": 89, - "intn": 88 + "rx0_intn": 0x40, + "rx1_intn": 0x41, + "sce_intn": 0x42, + "tx_intn": 0x3f }, "type": "peripheral" }, - "NVIC": { - "base": 0xe000e100, - "struct": "CortexM4Nvic", - "type": "core peripheral" - }, - "PERIP": { - "base": 0x40000000, - "size": 0x100000, - "type": "mmio" - }, - "PERIP BB": { - "alias": 0x42000000, - "base": 0x40000000, - "size": 0x100000, - "type": "bitband" - }, - "PPB": { - "base": 0xe0000000, - "size": 0x100000, - "type": "mmio" - }, "PWR": { "base": 0x40007000, "struct": "STM32F4xxPwr", "type": "peripheral" }, - "QUADSPI": { - "base": 0xa0001000, - "struct": "STM32F4xxQuadspi", + "DAC1": { + "base": 0x40007400, + "struct": "STM32F4xxDac", + "type": "peripheral" + }, + "UART7": { + "base": 0x40007800, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 91 + "intn": 0x52 }, "type": "peripheral" }, - "RCC": { - "base": 0x40023800, - "struct": "STM32F4xxRccV3", + "UART8": { + "base": 0x40007c00, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 5 + "intn": 0x53 }, "type": "peripheral" }, - "RNG": { - "base": 0x50060800, - "struct": "STM32F4xxRng", + "TIM1": { + "base": 0x40010000, + "struct": "STM32F4xxTim", + "kwargs": { + "brk_tim9_intn": 0x18, + "cc_intn": 0x1b, + "trg_com_tim11_intn": 0x1a, + "up_tim10_intn": 0x19 + }, "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "STM32F4xxRtc", + "TIM8": { + "base": 0x40010400, + "struct": "STM32F4xxTim", + "kwargs": { + "brk_tim12_intn": 0x2b, + "cc_intn": 0x2e, + "trg_com_tim14_intn": 0x2d, + "up_tim13_intn": 0x2c + }, + "type": "peripheral" + }, + "USART1": { + "base": 0x40011000, + "struct": "STM32F4xxUsart", "kwargs": { - "alarm_intn": 41, - "wkup_intn": 3 + "intn": 0x25 }, "type": "peripheral" }, - "SAI1": { - "base": 0x40015800, - "struct": "STM32F4xxSai", + "USART6": { + "base": 0x40011400, + "struct": "STM32F4xxUsart", "kwargs": { - "intn": 87 + "intn": 0x47 }, "type": "peripheral" }, - "SCB": { - "base": 0xe000ed00, - "struct": "CortexM4Scb", - "type": "core peripheral" + "ADC1": { + "base": 0x40012000, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC2": { + "base": 0x40012100, + "struct": "STM32F4xxAdc", + "type": "peripheral" + }, + "ADC3": { + "base": 0x40012200, + "struct": "STM32F4xxAdc", + "type": "peripheral" }, "SDIO": { "base": 0x40012c00, "struct": "STM32F4xxSdio", "kwargs": { - "intn": 49 + "intn": 0x31 }, "type": "peripheral" }, @@ -354,39 +344,48 @@ "base": 0x40013000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 35 + "intn": 0x23 }, "type": "peripheral" }, - "SPI2": { - "base": 0x40003800, + "SPI4": { + "base": 0x40013400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 36 + "intn": 0x54 }, "type": "peripheral" }, - "SPI3": { - "base": 0x40003c00, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 51 - }, + "SYSCFG": { + "base": 0x40013800, + "struct": "STM32F4xxSyscfg", "type": "peripheral" }, - "SPI4": { - "base": 0x40013400, - "struct": "STM32F4xxSpi", - "kwargs": { - "intn": 84 - }, + "EXTI": { + "base": 0x40013c00, + "struct": "STM32F4xxExti", + "type": "peripheral" + }, + "TIM9": { + "base": 0x40014000, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM10": { + "base": 0x40014400, + "struct": "STM32F4xxTim", + "type": "peripheral" + }, + "TIM11": { + "base": 0x40014800, + "struct": "STM32F4xxTim", "type": "peripheral" }, "SPI5": { "base": 0x40015000, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 85 + "intn": 0x55 }, "type": "peripheral" }, @@ -394,206 +393,207 @@ "base": 0x40015400, "struct": "STM32F4xxSpi", "kwargs": { - "intn": 86 + "intn": 0x56 }, "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x20000, - "type": "memory" + "SAI1": { + "base": 0x40015800, + "struct": "STM32F4xxSai", + "kwargs": { + "intn": 0x57 + }, + "type": "peripheral" }, - "SRAM BB": { - "alias": 0x22000000, - "base": 0x20000000, - "size": 0x100000, - "type": "bitband" + "LTDC": { + "base": 0x40016800, + "struct": "STM32F4xxLtdc", + "kwargs": { + "er_intn": 0x59, + "intn": 0x58 + }, + "type": "peripheral" }, - "SYSCFG": { - "base": 0x40013800, - "struct": "STM32F4xxSyscfg", + "DSI": { + "base": 0x40016c00, + "struct": "STM32F4xxDsi", + "kwargs": { + "intn": 0x5c + }, "type": "peripheral" }, - "SYSTEM": { - "base": 0x1fff0000, - "size": 0x7800, - "type": "memory" + "GPIOA": { + "base": 0x40020000, + "struct": "STM32F4xxGpio", + "type": "peripheral" }, - "SYSTICK": { - "base": 0xe000e010, - "struct": "CortexM4SysTick", - "type": "core peripheral" + "GPIOB": { + "base": 0x40020400, + "struct": "STM32F4xxGpio", + "type": "peripheral" }, - "TIM1": { - "base": 0x40010000, - "struct": "STM32F4xxTim", - "kwargs": { - "brk_tim9_intn": 24, - "cc_intn": 27, - "trg_com_tim11_intn": 26, - "up_tim10_intn": 25 - }, + "GPIOC": { + "base": 0x40020800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM10": { - "base": 0x40014400, - "struct": "STM32F4xxTim", + "GPIOD": { + "base": 0x40020c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM11": { - "base": 0x40014800, - "struct": "STM32F4xxTim", + "GPIOE": { + "base": 0x40021000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM12": { - "base": 0x40001800, - "struct": "STM32F4xxTim", + "GPIOF": { + "base": 0x40021400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM13": { - "base": 0x40001c00, - "struct": "STM32F4xxTim", + "GPIOG": { + "base": 0x40021800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM14": { - "base": 0x40002000, - "struct": "STM32F4xxTim", + "GPIOH": { + "base": 0x40021c00, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM2": { - "base": 0x40000000, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 28 - }, + "GPIOI": { + "base": 0x40022000, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM3": { - "base": 0x40000400, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 29 - }, + "GPIOJ": { + "base": 0x40022400, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM4": { - "base": 0x40000800, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 30 - }, + "GPIOK": { + "base": 0x40022800, + "struct": "STM32F4xxGpio", "type": "peripheral" }, - "TIM5": { - "base": 0x40000c00, - "struct": "STM32F4xxTim", - "kwargs": { - "intn": 50 - }, + "CRC": { + "base": 0x40023000, + "struct": "STM32F4xxCrc", "type": "peripheral" }, - "TIM6": { - "base": 0x40001000, - "struct": "STM32F4xxTim", + "RCC": { + "base": 0x40023800, + "struct": "STM32F4xxRccV3", "kwargs": { - "dac_intn": 54 + "intn": 0x5 }, "type": "peripheral" }, - "TIM7": { - "base": 0x40001400, - "struct": "STM32F4xxTim", + "FLASH INTERFACE": { + "base": 0x40023c00, + "struct": "STM32F4xxFlash", "kwargs": { - "intn": 55 + "intn": 0x4 }, "type": "peripheral" }, - "TIM8": { - "base": 0x40010400, - "struct": "STM32F4xxTim", + "DMA1": { + "base": 0x40026000, + "struct": "STM32F4xxDma", "kwargs": { - "brk_tim12_intn": 43, - "cc_intn": 46, - "trg_com_tim14_intn": 45, - "up_tim13_intn": 44 + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f }, "type": "peripheral" }, - "TIM9": { - "base": 0x40014000, - "struct": "STM32F4xxTim", - "type": "peripheral" - }, - "UART4": { - "base": 0x40004c00, - "struct": "STM32F4xxUsart", + "DMA2": { + "base": 0x40026400, + "struct": "STM32F4xxDma", "kwargs": { - "intn": 52 + "stream0_intn": 0x38, + "stream1_intn": 0x39, + "stream2_intn": 0x3a, + "stream3_intn": 0x3b, + "stream4_intn": 0x3c, + "stream5_intn": 0x44, + "stream6_intn": 0x45, + "stream7_intn": 0x46 }, "type": "peripheral" }, - "UART5": { - "base": 0x40005000, - "struct": "STM32F4xxUsart", + "ETH": { + "base": 0x40028000, + "struct": "STM32F4xxEth", "kwargs": { - "intn": 53 + "intn": 0x3d, + "wkup_intn": 0x3e }, "type": "peripheral" }, - "UART7": { - "base": 0x40007800, - "struct": "STM32F4xxUsart", + "DMA2D": { + "base": 0x4002b000, + "struct": "STM32F4xxDma2d", "kwargs": { - "intn": 82 + "intn": 0x5a }, "type": "peripheral" }, - "UART8": { - "base": 0x40007c00, - "struct": "STM32F4xxUsart", + "DCMI": { + "base": 0x50050000, + "struct": "STM32F4xxDcmi", "kwargs": { - "intn": 83 + "intn": 0x4e }, "type": "peripheral" }, - "USART1": { - "base": 0x40011000, - "struct": "STM32F4xxUsart", + "CRYP": { + "base": 0x50060000, + "struct": "STM32F4xxCryp", "kwargs": { - "intn": 37 + "intn": 0x4f }, "type": "peripheral" }, - "USART2": { - "base": 0x40004400, - "struct": "STM32F4xxUsart", + "HASH": { + "base": 0x50060400, + "struct": "STM32F4xxHash", "kwargs": { - "intn": 38 + "rng_intn": 0x50 }, "type": "peripheral" }, - "USART3": { - "base": 0x40004800, - "struct": "STM32F4xxUsart", - "kwargs": { - "intn": 39 - }, + "RNG": { + "base": 0x50060800, + "struct": "STM32F4xxRng", "type": "peripheral" }, - "USART6": { - "base": 0x40011400, - "struct": "STM32F4xxUsart", + "QUADSPI": { + "base": 0xa0001000, + "struct": "STM32F4xxQuadspi", "kwargs": { - "intn": 71 + "intn": 0x5b }, "type": "peripheral" }, - "WWDG": { - "base": 0x40002c00, - "struct": "STM32F4xxWwdg", + "DBGMCU": { + "base": 0xe0042000, + "struct": "STM32F4xxDbgmcu", "kwargs": { - "intn": 0 + "dev_id": 0x413 }, "type": "peripheral" + }, + "CODE": { + "base": 0x8000000, + "size": 0x200000, + "alias": 0x0, + "type": "remap" } } \ No newline at end of file From e5d6c4059dba5deb00ff6fd998a3a6768c86cb8c Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 12:37:56 +0800 Subject: [PATCH 02/32] Simplify arch peripheral name --- qiling/extensions/mcu/gd32vf1/gd32vf103.py | 2 +- qiling/loader/mcu.py | 2 +- tests/profiles/stm32f411.yml | 8 ++++---- tests/test_mcu.py | 1 + 4 files changed, 7 insertions(+), 6 deletions(-) diff --git a/qiling/extensions/mcu/gd32vf1/gd32vf103.py b/qiling/extensions/mcu/gd32vf1/gd32vf103.py index c81e3bc58..67a5f132a 100644 --- a/qiling/extensions/mcu/gd32vf1/gd32vf103.py +++ b/qiling/extensions/mcu/gd32vf1/gd32vf103.py @@ -101,7 +101,7 @@ "ECLIC": { "base": 0xd2000000, "struct": "GD32VF1xxEclic", - "type": "core peripheral" + "type": "core" }, "EXMC": { "base": 0xa0000000, diff --git a/qiling/loader/mcu.py b/qiling/loader/mcu.py index 4cd4b5c7e..9142a45af 100644 --- a/qiling/loader/mcu.py +++ b/qiling/loader/mcu.py @@ -137,7 +137,7 @@ def load_env(self): base = args['base'] self.ql.hw.setup_mmio(base, size, info=f'[{name}]') - if memtype == 'core peripheral': + if memtype == 'core': self.ql.hw.create(name.lower()) def run(self): diff --git a/tests/profiles/stm32f411.yml b/tests/profiles/stm32f411.yml index 96efeee15..400eb410c 100644 --- a/tests/profiles/stm32f411.yml +++ b/tests/profiles/stm32f411.yml @@ -15,7 +15,7 @@ "kwargs": { "dev_id": 0x413, }, - "type": "core peripheral" + "type": "peripheral" }, "DMA1": { "base": 0x40026000, @@ -143,7 +143,7 @@ "NVIC": { "base": 0xe000e100, "struct": "CortexM4Nvic", - "type": "core peripheral" + "type": "core" }, "PERIP": { "base": 0x40000000, @@ -186,7 +186,7 @@ "SCB": { "base": 0xe000ed00, "struct": "CortexM4Scb", - "type": "core peripheral" + "type": "core" }, "SDIO": { "base": 0x40012c00, @@ -260,7 +260,7 @@ "SYSTICK": { "base": 0xe000e010, "struct": "CortexM4SysTick", - "type": "core peripheral" + "type": "core" }, "TIM1": { "base": 0x40010000, diff --git a/tests/test_mcu.py b/tests/test_mcu.py index 01e7bec0d..bc4fafb64 100644 --- a/tests/test_mcu.py +++ b/tests/test_mcu.py @@ -331,6 +331,7 @@ def test_mcu_crc_stm32f407(self): ql.hw.create('gpiod') ql.hw.create('spi1') ql.hw.create('crc') + ql.hw.create('dbgmcu') flag = False def indicator(ql): From ea92ed9c4abd7c513c5da56a9d2fbe7a750b82e7 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 13:05:05 +0800 Subject: [PATCH 03/32] Format GD32 config format --- qiling/extensions/mcu/gd32vf1/gd32vf103.py | 446 ++++++++++----------- 1 file changed, 223 insertions(+), 223 deletions(-) diff --git a/qiling/extensions/mcu/gd32vf1/gd32vf103.py b/qiling/extensions/mcu/gd32vf1/gd32vf103.py index 67a5f132a..647e04144 100644 --- a/qiling/extensions/mcu/gd32vf1/gd32vf103.py +++ b/qiling/extensions/mcu/gd32vf1/gd32vf103.py @@ -4,134 +4,98 @@ # gd32vf103 = { - "ADC0": { - "base": 0x40012400, - "struct": "GD32VF1xxAdc", - "kwargs": { - "intn": 37 - }, - "type": "peripheral" - }, - "ADC1": { - "base": 0x40012800, - "struct": "GD32VF1xxAdc", - "kwargs": { - "intn": 37 - }, - "type": "peripheral" - }, - "AFIO": { - "base": 0x40010000, - "struct": "GD32VF1xxAfio", - "type": "peripheral" + "ECLIC": { + "base": 0xd2000000, + "struct": "GD32VF1xxEclic", + "type": "core" }, - "BKP": { - "base": 0x40006c00, - "struct": "GD32VF1xxBkp", - "type": "peripheral" + "FLASH": { + "base": 0x8000000, + "size": 0x20000, + "type": "memory" }, "BOOT": { "base": 0x1fffb000, "size": 0x5000, "type": "memory" }, - "CAN0": { - "base": 0x40006400, - "struct": "GD32VF1xxCan", + "SRAM": { + "base": 0x20000000, + "size": 0x18000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x40000, + "type": "mmio" + }, + "USBFS": { + "base": 0x50000000, + "size": 0x40000, + "type": "mmio" + }, + "TIMER1": { + "base": 0x40000000, + "struct": "GD32VF1xxTimer", "kwargs": { - "ewmc_intn": 41, - "rx0_intn": 39, - "rx1_intn": 40, - "tx_intn": 38 + "intn": 0x2f }, "type": "peripheral" }, - "CAN1": { - "base": 0x40006800, - "struct": "GD32VF1xxCan", + "TIMER2": { + "base": 0x40000400, + "struct": "GD32VF1xxTimer", "kwargs": { - "ewmc_intn": 85, - "rx0_intn": 83, - "rx1_intn": 84, - "tx_intn": 82 + "intn": 0x30 }, "type": "peripheral" }, - "CRC": { - "base": 0x40023000, - "struct": "GD32VF1xxCrc", - "type": "peripheral" - }, - "DAC": { - "base": 0x40007400, - "struct": "GD32VF1xxDac", - "type": "peripheral" - }, - "DBG": { - "base": 0xe0042000, - "struct": "GD32VF1xxDbg", + "TIMER3": { + "base": 0x40000800, + "struct": "GD32VF1xxTimer", + "kwargs": { + "intn": 0x31 + }, "type": "peripheral" }, - "DMA0": { - "base": 0x40020000, - "struct": "GD32VF1xxDma", + "TIMER4": { + "base": 0x40000c00, + "struct": "GD32VF1xxTimer", "kwargs": { - "stream0_intn": 30, - "stream1_intn": 31, - "stream2_intn": 32, - "stream3_intn": 33, - "stream4_intn": 34, - "stream5_intn": 35, - "stream6_intn": 36 + "intn": 0x45 }, "type": "peripheral" }, - "DMA1": { - "base": 0x40020400, - "struct": "GD32VF1xxDma", + "TIMER5": { + "base": 0x40001000, + "struct": "GD32VF1xxTimer", "kwargs": { - "stream0_intn": 75, - "stream1_intn": 76, - "stream2_intn": 77, - "stream3_intn": 78, - "stream4_intn": 79 + "intn": 0x49 }, "type": "peripheral" }, - "ECLIC": { - "base": 0xd2000000, - "struct": "GD32VF1xxEclic", - "type": "core" - }, - "EXMC": { - "base": 0xa0000000, - "struct": "GD32VF1xxExmc", + "TIMER6": { + "base": 0x40001400, + "struct": "GD32VF1xxTimer", + "kwargs": { + "intn": 0x4a + }, "type": "peripheral" }, - "EXTI": { - "base": 0x40010400, - "struct": "GD32VF1xxExti", + "RTC": { + "base": 0x40002800, + "struct": "GD32VF1xxRtc", "kwargs": { - "line0_intn": 25, - "line15_10_intn": 59, - "line1_intn": 26, - "line2_intn": 27, - "line3_intn": 28, - "line4_intn": 29, - "line9_5_intn": 42 + "alarm_intn": 0x3c, + "intn": 0x16 }, "type": "peripheral" }, - "FLASH": { - "base": 0x08000000, - "size": 0x20000, - "type": "memory" - }, - "FMC": { - "base": 0x40022000, - "struct": "GD32VF1xxFmc", + "WWDGT": { + "base": 0x40002c00, + "struct": "GD32VF1xxWwdgt", "kwargs": { - "intn": 23 + "intn": 0x0 }, "type": "peripheral" }, @@ -140,37 +104,60 @@ "struct": "GD32VF1xxFwdgt", "type": "peripheral" }, - "GPIOA": { - "base": 0x40010800, - "struct": "GD32VF1xxGpio", + "SPI1": { + "base": 0x40003800, + "struct": "GD32VF1xxSpi", + "kwargs": { + "intn": 0x37 + }, "type": "peripheral" }, - "GPIOB": { - "base": 0x40010c00, - "struct": "GD32VF1xxGpio", + "SPI2": { + "base": 0x40003c00, + "struct": "GD32VF1xxSpi", + "kwargs": { + "intn": 0x46 + }, "type": "peripheral" }, - "GPIOC": { - "base": 0x40011000, - "struct": "GD32VF1xxGpio", + "USART1": { + "base": 0x40004400, + "struct": "GD32VF1xxUsart", + "kwargs": { + "intn": 0x39 + }, "type": "peripheral" }, - "GPIOD": { - "base": 0x40011400, - "struct": "GD32VF1xxGpio", + "USART2": { + "base": 0x40004800, + "struct": "GD32VF1xxUsart", + "kwargs": { + "intn": 0x3a + }, "type": "peripheral" }, - "GPIOE": { - "base": 0x40011800, - "struct": "GD32VF1xxGpio", + "UART3": { + "base": 0x40004c00, + "struct": "GD32VF1xxUart", + "kwargs": { + "intn": 0x47 + }, + "type": "peripheral" + }, + "UART4": { + "base": 0x40005000, + "struct": "GD32VF1xxUart", + "kwargs": { + "intn": 0x48 + }, "type": "peripheral" }, "I2C0": { "base": 0x40005400, "struct": "GD32VF1xxI2c", "kwargs": { - "er_intn": 51, - "ev_intn": 50 + "er_intn": 0x33, + "ev_intn": 0x32 }, "type": "peripheral" }, @@ -178,174 +165,180 @@ "base": 0x40005800, "struct": "GD32VF1xxI2c", "kwargs": { - "er_intn": 53, - "ev_intn": 52 + "er_intn": 0x35, + "ev_intn": 0x34 }, "type": "peripheral" }, - "PERIP": { - "base": 0x40000000, - "size": 0x40000, - "type": "mmio" + "CAN0": { + "base": 0x40006400, + "struct": "GD32VF1xxCan", + "kwargs": { + "ewmc_intn": 0x29, + "rx0_intn": 0x27, + "rx1_intn": 0x28, + "tx_intn": 0x26 + }, + "type": "peripheral" + }, + "CAN1": { + "base": 0x40006800, + "struct": "GD32VF1xxCan", + "kwargs": { + "ewmc_intn": 0x55, + "rx0_intn": 0x53, + "rx1_intn": 0x54, + "tx_intn": 0x52 + }, + "type": "peripheral" + }, + "BKP": { + "base": 0x40006c00, + "struct": "GD32VF1xxBkp", + "type": "peripheral" }, "PMU": { "base": 0x40007000, "struct": "GD32VF1xxPmu", "type": "peripheral" }, - "RCU": { - "base": 0x40021000, - "struct": "GD32VF1xxRcu", - "kwargs": { - "intn": 24 - }, + "DAC": { + "base": 0x40007400, + "struct": "GD32VF1xxDac", "type": "peripheral" }, - "RTC": { - "base": 0x40002800, - "struct": "GD32VF1xxRtc", - "kwargs": { - "alarm_intn": 60, - "intn": 22 - }, + "AFIO": { + "base": 0x40010000, + "struct": "GD32VF1xxAfio", "type": "peripheral" }, - "SPI0": { - "base": 0x40013000, - "struct": "GD32VF1xxSpi", + "EXTI": { + "base": 0x40010400, + "struct": "GD32VF1xxExti", "kwargs": { - "intn": 54 + "line0_intn": 0x19, + "line15_10_intn": 0x3b, + "line1_intn": 0x1a, + "line2_intn": 0x1b, + "line3_intn": 0x1c, + "line4_intn": 0x1d, + "line9_5_intn": 0x2a }, "type": "peripheral" }, - "SPI1": { - "base": 0x40003800, - "struct": "GD32VF1xxSpi", - "kwargs": { - "intn": 55 - }, + "GPIOA": { + "base": 0x40010800, + "struct": "GD32VF1xxGpio", "type": "peripheral" }, - "SPI2": { - "base": 0x40003c00, - "struct": "GD32VF1xxSpi", - "kwargs": { - "intn": 70 - }, + "GPIOB": { + "base": 0x40010c00, + "struct": "GD32VF1xxGpio", "type": "peripheral" }, - "SRAM": { - "base": 0x20000000, - "size": 0x18000, - "type": "memory" - }, - "TIMER0": { - "base": 0x40012c00, - "struct": "GD32VF1xxTimer", - "kwargs": { - "brk_intn": 43, - "channel_intn": 46, - "trg_cmt_intn": 45, - "up_intn": 44 - }, + "GPIOC": { + "base": 0x40011000, + "struct": "GD32VF1xxGpio", "type": "peripheral" }, - "TIMER1": { - "base": 0x40000000, - "struct": "GD32VF1xxTimer", - "kwargs": { - "intn": 47 - }, + "GPIOD": { + "base": 0x40011400, + "struct": "GD32VF1xxGpio", "type": "peripheral" }, - "TIMER2": { - "base": 0x40000400, - "struct": "GD32VF1xxTimer", - "kwargs": { - "intn": 48 - }, + "GPIOE": { + "base": 0x40011800, + "struct": "GD32VF1xxGpio", "type": "peripheral" }, - "TIMER3": { - "base": 0x40000800, - "struct": "GD32VF1xxTimer", + "ADC0": { + "base": 0x40012400, + "struct": "GD32VF1xxAdc", "kwargs": { - "intn": 49 + "intn": 0x25 }, "type": "peripheral" }, - "TIMER4": { - "base": 0x40000c00, - "struct": "GD32VF1xxTimer", + "ADC1": { + "base": 0x40012800, + "struct": "GD32VF1xxAdc", "kwargs": { - "intn": 69 + "intn": 0x25 }, "type": "peripheral" }, - "TIMER5": { - "base": 0x40001000, + "TIMER0": { + "base": 0x40012c00, "struct": "GD32VF1xxTimer", "kwargs": { - "intn": 73 + "brk_intn": 0x2b, + "channel_intn": 0x2e, + "trg_cmt_intn": 0x2d, + "up_intn": 0x2c }, "type": "peripheral" }, - "TIMER6": { - "base": 0x40001400, - "struct": "GD32VF1xxTimer", + "SPI0": { + "base": 0x40013000, + "struct": "GD32VF1xxSpi", "kwargs": { - "intn": 74 + "intn": 0x36 }, "type": "peripheral" }, - "UART3": { - "base": 0x40004c00, - "struct": "GD32VF1xxUart", + "USART0": { + "base": 0x40013800, + "struct": "GD32VF1xxUsart", "kwargs": { - "intn": 71 + "intn": 0x38 }, "type": "peripheral" }, - "UART4": { - "base": 0x40005000, - "struct": "GD32VF1xxUart", + "DMA0": { + "base": 0x40020000, + "struct": "GD32VF1xxDma", "kwargs": { - "intn": 72 + "stream0_intn": 0x1e, + "stream1_intn": 0x1f, + "stream2_intn": 0x20, + "stream3_intn": 0x21, + "stream4_intn": 0x22, + "stream5_intn": 0x23, + "stream6_intn": 0x24 }, "type": "peripheral" }, - "USART0": { - "base": 0x40013800, - "struct": "GD32VF1xxUsart", + "DMA1": { + "base": 0x40020400, + "struct": "GD32VF1xxDma", "kwargs": { - "intn": 56 + "stream0_intn": 0x4b, + "stream1_intn": 0x4c, + "stream2_intn": 0x4d, + "stream3_intn": 0x4e, + "stream4_intn": 0x4f }, "type": "peripheral" }, - "USART1": { - "base": 0x40004400, - "struct": "GD32VF1xxUsart", + "RCU": { + "base": 0x40021000, + "struct": "GD32VF1xxRcu", "kwargs": { - "intn": 57 + "intn": 0x18 }, "type": "peripheral" }, - "USART2": { - "base": 0x40004800, - "struct": "GD32VF1xxUsart", + "FMC": { + "base": 0x40022000, + "struct": "GD32VF1xxFmc", "kwargs": { - "intn": 58 + "intn": 0x17 }, "type": "peripheral" }, - "USBFS": { - "base": 0x50000000, - "size": 0x40000, - "type": "mmio" - }, - "USBFS_DEVICE": { - "base": 0x50000800, - "struct": "GD32VF1xxUsbfs", + "CRC": { + "base": 0x40023000, + "struct": "GD32VF1xxCrc", "type": "peripheral" }, "USBFS_GLOBAL": { @@ -358,17 +351,24 @@ "struct": "GD32VF1xxUsbfs", "type": "peripheral" }, + "USBFS_DEVICE": { + "base": 0x50000800, + "struct": "GD32VF1xxUsbfs", + "type": "peripheral" + }, "USBFS_PWRCLK": { "base": 0x50000e00, "struct": "GD32VF1xxUsbfs", "type": "peripheral" }, - "WWDGT": { - "base": 0x40002c00, - "struct": "GD32VF1xxWwdgt", - "kwargs": { - "intn": 0 - }, + "EXMC": { + "base": 0xa0000000, + "struct": "GD32VF1xxExmc", + "type": "peripheral" + }, + "DBG": { + "base": 0xe0042000, + "struct": "GD32VF1xxDbg", "type": "peripheral" } } \ No newline at end of file From d4184a49a8af185f71b74cf4da32d22e5a038d99 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 16:25:23 +0800 Subject: [PATCH 04/32] Make stm32f103 config --- qiling/extensions/mcu/stm32f1/stm32f103.py | 297 +++++++++++++++++++++ 1 file changed, 297 insertions(+) create mode 100644 qiling/extensions/mcu/stm32f1/stm32f103.py diff --git a/qiling/extensions/mcu/stm32f1/stm32f103.py b/qiling/extensions/mcu/stm32f1/stm32f103.py new file mode 100644 index 000000000..fa0dff5cd --- /dev/null +++ b/qiling/extensions/mcu/stm32f1/stm32f103.py @@ -0,0 +1,297 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +stm32f103 = { + "SRAM BB": { + "alias": 0x22000000, + "base": 0x20000000, + "size": 0x100000, + "type": "bitband" + }, + "PERIP BB": { + "alias": 0x42000000, + "base": 0x40000000, + "size": 0x100000, + "type": "bitband" + }, + "SYSTICK": { + "base": 0xe000e010, + "struct": "CortexM3SysTick", + "type": "core" + }, + "NVIC": { + "base": 0xe000e100, + "struct": "CortexM3Nvic", + "type": "core" + }, + "SCB": { + "base": 0xe000ed00, + "struct": "CortexM3Scb", + "type": "core" + }, + "FLASH": { + "base": 0x8000000, + "size": 0x20000, + "type": "memory" + }, + "SYSTEM": { + "base": 0x1ffff000, + "size": 0x1000, + "type": "memory" + }, + "SRAM": { + "base": 0x20000000, + "size": 0x5000, + "type": "memory" + }, + "PERIP": { + "base": 0x40000000, + "size": 0x100000, + "type": "mmio" + }, + "PPB": { + "base": 0xe0000000, + "size": 0x100000, + "type": "mmio" + }, + "TIM2": { + "type": "peripheral", + "base": 0x40000000, + "class": "STM32F1xxTim", + "kwargs": { + "intn": 0x1c + } + }, + "TIM3": { + "type": "peripheral", + "base": 0x40000400, + "class": "STM32F1xxTim", + "kwargs": { + "intn": 0x1d + } + }, + "TIM4": { + "type": "peripheral", + "base": 0x40000800, + "class": "STM32F1xxTim", + "kwargs": { + "intn": 0x1e + } + }, + "RTC": { + "type": "peripheral", + "base": 0x40002800, + "class": "STM32F1xxRtc", + "kwargs": { + "intn": 0x3, + "alarm_intn": 0x29 + } + }, + "WWDG": { + "type": "peripheral", + "base": 0x40002c00, + "class": "STM32F1xxWwdg", + "kwargs": { + "intn": 0x0 + } + }, + "IWDG": { + "type": "peripheral", + "base": 0x40003000, + "class": "STM32F1xxIwdg" + }, + "SPI2": { + "type": "peripheral", + "base": 0x40003800, + "class": "STM32F1xxSpi", + "kwargs": { + "intn": 0x24 + } + }, + "USART2": { + "type": "peripheral", + "base": 0x40004400, + "class": "STM32F1xxUsart", + "kwargs": { + "intn": 0x26 + } + }, + "USART3": { + "type": "peripheral", + "base": 0x40004800, + "class": "STM32F1xxUsart", + "kwargs": { + "intn": 0x27 + } + }, + "I2C1": { + "type": "peripheral", + "base": 0x40005400, + "class": "STM32F1xxI2c", + "kwargs": { + "ev_intn": 0x1f, + "er_intn": 0x20 + } + }, + "I2C2": { + "type": "peripheral", + "base": 0x40005800, + "class": "STM32F1xxI2c", + "kwargs": { + "ev_intn": 0x21, + "er_intn": 0x22 + } + }, + "USB": { + "type": "peripheral", + "base": 0x40005c00, + "class": "STM32F1xxUsb", + "kwargs": { + "hp_can1_tx_intn": 0x13, + "lp_can1_rx0_intn": 0x14, + "hp_intn": 0x13, + "lp_intn": 0x14 + } + }, + "CAN1": { + "type": "peripheral", + "base": 0x40006400, + "class": "STM32F1xxCan", + "kwargs": { + "rx1_intn": 0x15, + "sce_intn": 0x16, + "tx_intn": 0x13, + "rx0_intn": 0x14 + } + }, + "BKP": { + "type": "peripheral", + "base": 0x40006c00, + "class": "STM32F1xxBkp" + }, + "PWR": { + "type": "peripheral", + "base": 0x40007000, + "class": "STM32F1xxPwr" + }, + "AFIO": { + "type": "peripheral", + "base": 0x40010000, + "class": "STM32F1xxAfio" + }, + "EXTI": { + "type": "peripheral", + "base": 0x40010400, + "class": "STM32F1xxExti" + }, + "GPIOA": { + "type": "peripheral", + "base": 0x40010800, + "class": "STM32F1xxGpio" + }, + "GPIOB": { + "type": "peripheral", + "base": 0x40010c00, + "class": "STM32F1xxGpio" + }, + "GPIOC": { + "type": "peripheral", + "base": 0x40011000, + "class": "STM32F1xxGpio" + }, + "GPIOD": { + "type": "peripheral", + "base": 0x40011400, + "class": "STM32F1xxGpio" + }, + "GPIOE": { + "type": "peripheral", + "base": 0x40011800, + "class": "STM32F1xxGpio" + }, + "ADC1": { + "type": "peripheral", + "base": 0x40012400, + "class": "STM32F1xxAdc", + "kwargs": { + "intn": 0x12 + } + }, + "ADC2": { + "type": "peripheral", + "base": 0x40012800, + "class": "STM32F1xxAdc" + }, + "TIM1": { + "type": "peripheral", + "base": 0x40012c00, + "class": "STM32F1xxTim", + "kwargs": { + "brk_intn": 0x18, + "up_intn": 0x19, + "trg_com_intn": 0x1a, + "cc_intn": 0x1b, + "brk_tim15_intn": 0x18, + "brk_tim9_intn": 0x18, + "trg_com_tim17_intn": 0x1a, + "trg_com_tim11_intn": 0x1a, + "up_tim16_intn": 0x19, + "up_tim10_intn": 0x19 + } + }, + "SPI1": { + "type": "peripheral", + "base": 0x40013000, + "class": "STM32F1xxSpi", + "kwargs": { + "intn": 0x23 + } + }, + "USART1": { + "type": "peripheral", + "base": 0x40013800, + "class": "STM32F1xxUsart", + "kwargs": { + "intn": 0x25 + } + }, + "DMA1": { + "type": "peripheral", + "base": 0x40020000, + "class": "STM32F1xxDma" + }, + "RCC": { + "type": "peripheral", + "base": 0x40021000, + "class": "STM32F1xxRcc", + "kwargs": { + "intn": 0x5 + } + }, + "FLASH INTERFACE": { + "type": "peripheral", + "base": 0x40022000, + "class": "STM32F1xxFlash", + "kwargs": { + "intn": 0x4 + } + }, + "CRC": { + "type": "peripheral", + "base": 0x40023000, + "class": "STM32F1xxCrc" + }, + "DBGMCU": { + "type": "peripheral", + "base": 0xe0042000, + "class": "STM32F1xxDbgmcu" + }, + "CODE": { + "base": 0x8000000, + "size": 0x80000, + "alias": 0x0, + "type": "remap" + } +} \ No newline at end of file From df9a1de3acb3f796846985c903b8aea2bbc44b75 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 16:31:01 +0800 Subject: [PATCH 05/32] Add stm32f103 support --- qiling/extensions/mcu/stm32f1/__init__.py | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 qiling/extensions/mcu/stm32f1/__init__.py diff --git a/qiling/extensions/mcu/stm32f1/__init__.py b/qiling/extensions/mcu/stm32f1/__init__.py new file mode 100644 index 000000000..14fd6f334 --- /dev/null +++ b/qiling/extensions/mcu/stm32f1/__init__.py @@ -0,0 +1,6 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +from .stm32f103 import stm32f103 From f3886f1d75ad44e3f3bc0fe68d93f4c77e18dc43 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 16:31:12 +0800 Subject: [PATCH 06/32] Add CortexM3 Timer --- qiling/hw/timer/__init__.py | 1 + qiling/hw/timer/cm3_systick.py | 12 +++++++ qiling/hw/timer/cm4_systick.py | 58 ++---------------------------- qiling/hw/timer/cm_systick.py | 64 ++++++++++++++++++++++++++++++++++ 4 files changed, 80 insertions(+), 55 deletions(-) create mode 100644 qiling/hw/timer/cm3_systick.py create mode 100644 qiling/hw/timer/cm_systick.py diff --git a/qiling/hw/timer/__init__.py b/qiling/hw/timer/__init__.py index bbf2dc958..3f37f7276 100644 --- a/qiling/hw/timer/__init__.py +++ b/qiling/hw/timer/__init__.py @@ -3,6 +3,7 @@ # Cross Platform and Multi Architecture Advanced Binary Emulation Framework # +from .cm3_systick import CortexM3SysTick from .cm4_systick import CortexM4SysTick from .stm32f4xx_rtc import STM32F4xxRtc from .stm32f4xx_tim import STM32F4xxTim diff --git a/qiling/hw/timer/cm3_systick.py b/qiling/hw/timer/cm3_systick.py new file mode 100644 index 000000000..37eae5b6c --- /dev/null +++ b/qiling/hw/timer/cm3_systick.py @@ -0,0 +1,12 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +import ctypes + +from qiling.hw.timer.cm_systick import CortexMSysTick + + +class CortexM3SysTick(CortexMSysTick): + pass diff --git a/qiling/hw/timer/cm4_systick.py b/qiling/hw/timer/cm4_systick.py index 0d67b1ba5..37945b904 100644 --- a/qiling/hw/timer/cm4_systick.py +++ b/qiling/hw/timer/cm4_systick.py @@ -4,61 +4,9 @@ # import ctypes -from qiling.arch.cortex_m_const import IRQ -from qiling.hw.peripheral import QlPeripheral -from qiling.hw.timer.timer import QlTimerPeripheral -from qiling.hw.const.cm4_systick import SYSTICK_CTRL +from qiling.hw.timer.cm_systick import CortexMSysTick -class CortexM4SysTick(QlTimerPeripheral): - class Type(ctypes.Structure): - _fields_ = [ - ('CTRL' , ctypes.c_uint32), - ('LOAD' , ctypes.c_int32), - ('VAL' , ctypes.c_int32), - ('CALIB', ctypes.c_uint32), - ] - def __init__(self, ql, label): - super().__init__(ql, label) - - self.systick = self.struct( - CALIB = 0xC0000000 - ) - - def step(self): - if not self.systick.CTRL & SYSTICK_CTRL.ENABLE: - return - - if self.systick.VAL <= 0: - self.systick.VAL = self.systick.LOAD - self.systick.CTRL |= SYSTICK_CTRL.COUNTFLAG - - if self.systick.CTRL & SYSTICK_CTRL.TICKINT: - self.ql.hw.nvic.set_pending(IRQ.SYSTICK) - else: - self.systick.VAL -= self.ratio - - @QlPeripheral.monitor() - def read(self, offset: int, size: int) -> int: - buf = ctypes.create_string_buffer(size) - ctypes.memmove(buf, ctypes.addressof(self.systick) + offset, size) - - if offset == self.struct.CTRL.offset: - self.systick.CTRL &= ~SYSTICK_CTRL.COUNTFLAG - return int.from_bytes(buf.raw, byteorder='little') - - @QlPeripheral.monitor() - def write(self, offset: int, size: int, value: int): - # ignore the reserved bit - if offset == self.struct.CTRL.offset: - value &= SYSTICK_CTRL.MASK - else: - value &= 0xffffff # only low-24 bit available - - # restart the timer - if offset == self.struct.LOAD.offset: - self.systick.VAL = value - - data = (value).to_bytes(size, 'little') - ctypes.memmove(ctypes.addressof(self.systick) + offset, data, size) +class CortexM4SysTick(CortexMSysTick): + pass diff --git a/qiling/hw/timer/cm_systick.py b/qiling/hw/timer/cm_systick.py new file mode 100644 index 000000000..81e9bc465 --- /dev/null +++ b/qiling/hw/timer/cm_systick.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +import ctypes +from qiling.arch.cortex_m_const import IRQ +from qiling.hw.peripheral import QlPeripheral +from qiling.hw.timer.timer import QlTimerPeripheral +from qiling.hw.const.cm4_systick import SYSTICK_CTRL + + +class CortexMSysTick(QlTimerPeripheral): + class Type(ctypes.Structure): + _fields_ = [ + ('CTRL' , ctypes.c_uint32), + ('LOAD' , ctypes.c_int32), + ('VAL' , ctypes.c_int32), + ('CALIB', ctypes.c_uint32), + ] + + def __init__(self, ql, label): + super().__init__(ql, label) + + self.systick = self.struct( + CALIB = 0xC0000000 + ) + + def step(self): + if not self.systick.CTRL & SYSTICK_CTRL.ENABLE: + return + + if self.systick.VAL <= 0: + self.systick.VAL = self.systick.LOAD + self.systick.CTRL |= SYSTICK_CTRL.COUNTFLAG + + if self.systick.CTRL & SYSTICK_CTRL.TICKINT: + self.ql.hw.nvic.set_pending(IRQ.SYSTICK) + else: + self.systick.VAL -= self.ratio + + @QlPeripheral.monitor() + def read(self, offset: int, size: int) -> int: + buf = ctypes.create_string_buffer(size) + ctypes.memmove(buf, ctypes.addressof(self.systick) + offset, size) + + if offset == self.struct.CTRL.offset: + self.systick.CTRL &= ~SYSTICK_CTRL.COUNTFLAG + return int.from_bytes(buf.raw, byteorder='little') + + @QlPeripheral.monitor() + def write(self, offset: int, size: int, value: int): + # ignore the reserved bit + if offset == self.struct.CTRL.offset: + value &= SYSTICK_CTRL.MASK + else: + value &= 0xffffff # only low-24 bit available + + # restart the timer + if offset == self.struct.LOAD.offset: + self.systick.VAL = value + + data = (value).to_bytes(size, 'little') + ctypes.memmove(ctypes.addressof(self.systick) + offset, data, size) From b342d9b1c995d57fb2b5f6563580af859369084d Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 16:35:14 +0800 Subject: [PATCH 07/32] Delete rebundant import --- qiling/hw/timer/cm3_systick.py | 2 -- qiling/hw/timer/cm4_systick.py | 2 -- 2 files changed, 4 deletions(-) diff --git a/qiling/hw/timer/cm3_systick.py b/qiling/hw/timer/cm3_systick.py index 37eae5b6c..b78e6d1dc 100644 --- a/qiling/hw/timer/cm3_systick.py +++ b/qiling/hw/timer/cm3_systick.py @@ -3,8 +3,6 @@ # Cross Platform and Multi Architecture Advanced Binary Emulation Framework # -import ctypes - from qiling.hw.timer.cm_systick import CortexMSysTick diff --git a/qiling/hw/timer/cm4_systick.py b/qiling/hw/timer/cm4_systick.py index 37945b904..b46712a47 100644 --- a/qiling/hw/timer/cm4_systick.py +++ b/qiling/hw/timer/cm4_systick.py @@ -3,8 +3,6 @@ # Cross Platform and Multi Architecture Advanced Binary Emulation Framework # -import ctypes - from qiling.hw.timer.cm_systick import CortexMSysTick From 9b13199d47775ee36cbd6aa3cd4e5020d75d10cd Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 16:35:46 +0800 Subject: [PATCH 08/32] Add Cortex M3 NVIC --- qiling/hw/intc/__init__.py | 1 + qiling/hw/intc/cm3_nvic.py | 9 +++ qiling/hw/intc/cm4_nvic.py | 141 +----------------------------------- qiling/hw/intc/cm_nvic.py | 144 +++++++++++++++++++++++++++++++++++++ 4 files changed, 157 insertions(+), 138 deletions(-) create mode 100644 qiling/hw/intc/cm3_nvic.py create mode 100644 qiling/hw/intc/cm_nvic.py diff --git a/qiling/hw/intc/__init__.py b/qiling/hw/intc/__init__.py index c7321929b..e620b1511 100644 --- a/qiling/hw/intc/__init__.py +++ b/qiling/hw/intc/__init__.py @@ -3,6 +3,7 @@ # Cross Platform and Multi Architecture Advanced Binary Emulation Framework # +from .cm3_nvic import CortexM3Nvic from .cm4_nvic import CortexM4Nvic from .stm32f4xx_exti import STM32F4xxExti from .gd32vf1xx_eclic import GD32VF1xxEclic diff --git a/qiling/hw/intc/cm3_nvic.py b/qiling/hw/intc/cm3_nvic.py new file mode 100644 index 000000000..24d12ffac --- /dev/null +++ b/qiling/hw/intc/cm3_nvic.py @@ -0,0 +1,9 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +from qiling.hw.intc.cm_nvic import CortexMNvic + +class CortexM3Nvic(CortexMNvic): + pass diff --git a/qiling/hw/intc/cm4_nvic.py b/qiling/hw/intc/cm4_nvic.py index 1d28276b4..423859f36 100644 --- a/qiling/hw/intc/cm4_nvic.py +++ b/qiling/hw/intc/cm4_nvic.py @@ -3,142 +3,7 @@ # Cross Platform and Multi Architecture Advanced Binary Emulation Framework # -import ctypes +from qiling.hw.intc.cm_nvic import CortexMNvic -from qiling.hw.peripheral import QlPeripheral - - -class CortexM4Nvic(QlPeripheral): - class Type(ctypes.Structure): - _fields_ = [ - ('ISER' , ctypes.c_uint32 * 8), - ('RESERVED0', ctypes.c_uint32 * 24), - ('ICER' , ctypes.c_uint32 * 8), - ('RESERVED1', ctypes.c_uint32 * 24), - ('ISPR' , ctypes.c_uint32 * 8), - ('RESERVED2', ctypes.c_uint32 * 24), - ('ICPR' , ctypes.c_uint32 * 8), - ('RESERVED3', ctypes.c_uint32 * 24), - ('IABR' , ctypes.c_uint32 * 8), - ('RESERVED4', ctypes.c_uint32 * 56), - ('IPR' , ctypes.c_uint8 * 240), - ('RESERVED5', ctypes.c_uint32 * 644), - ('STIR' , ctypes.c_uint32 * 8), - ] - - def __init__(self, ql, label): - super().__init__(ql, label) - - # reference: - # https://www.youtube.com/watch?v=uFBNf7F3l60 - # https://developer.arm.com/documentation/ddi0439/b/Nested-Vectored-Interrupt-Controller - - self.nvic = self.struct() - - ## The max number of interrupt request - self.IRQN_MAX = self.struct.ISER.size * 8 - - ## The ISER unit size - self.MASK = self.IRQN_MAX // len(self.nvic.ISER) - 1 - self.OFFSET = self.MASK.bit_length() - - ## special write behavior - self.triggers = [ - (self.struct.ISER, self.enable), - (self.struct.ICER, self.disable), - (self.struct.ISPR, self.set_pending), - (self.struct.ICPR, self.clear_pending), - ] - - self.intrs = [] - self.interrupt_handler = self.ql.arch.hard_interrupt_handler - - def enable(self, IRQn): - if IRQn >= 0: - self.nvic.ISER[IRQn >> self.OFFSET] |= 1 << (IRQn & self.MASK) - self.nvic.ICER[IRQn >> self.OFFSET] |= 1 << (IRQn & self.MASK) - else: - self.ql.hw.scb.enable(IRQn) - - def disable(self, IRQn): - if IRQn >= 0: - self.nvic.ISER[IRQn >> self.OFFSET] &= self.MASK ^ (1 << (IRQn & self.MASK)) - self.nvic.ICER[IRQn >> self.OFFSET] &= self.MASK ^ (1 << (IRQn & self.MASK)) - else: - self.ql.hw.scb.disable(IRQn) - - def get_enable(self, IRQn): - if IRQn >= 0: - return (self.nvic.ISER[IRQn >> self.OFFSET] >> (IRQn & self.MASK)) & 1 - else: - return self.ql.hw.scb.get_enable(IRQn) - - def set_pending(self, IRQn): - if IRQn >= 0: - self.nvic.ISPR[IRQn >> self.OFFSET] |= 1 << (IRQn & self.MASK) - self.nvic.ICPR[IRQn >> self.OFFSET] |= 1 << (IRQn & self.MASK) - else: - self.ql.hw.scb.set_pending(IRQn) - - if self.get_enable(IRQn): - self.intrs.append(IRQn) - - def clear_pending(self, IRQn): - if IRQn >= 0: - self.nvic.ISPR[IRQn >> self.OFFSET] &= self.MASK ^ (1 << (IRQn & self.MASK)) - self.nvic.ICPR[IRQn >> self.OFFSET] &= self.MASK ^ (1 << (IRQn & self.MASK)) - else: - self.ql.hw.scb.clear_pending(IRQn) - - def get_pending(self, IRQn): - if IRQn >= 0: - return (self.nvic.ISER[IRQn >> self.OFFSET] >> (IRQn & self.MASK)) & 1 - else: - return self.ql.hw.scb.get_pending(IRQn) - - def get_priority(self, IRQn): - if IRQn >= 0: - return self.nvic.IPR[IRQn] - else: - return self.ql.hw.scb.get_priority(IRQn) - - def step(self): - if not self.intrs: - return - - self.intrs.sort(key=lambda x: self.get_priority(x)) - - while self.intrs: - IRQn = self.intrs.pop(0) - self.clear_pending(IRQn) - self.interrupt_handler(self.ql, IRQn) - - @QlPeripheral.monitor() - def read(self, offset: int, size: int) -> int: - buf = ctypes.create_string_buffer(size) - ctypes.memmove(buf, ctypes.addressof(self.nvic) + offset, size) - return int.from_bytes(buf.raw, byteorder='little') - - @QlPeripheral.monitor() - def write(self, offset: int, size: int, value: int): - def write_byte(ofs, byte): - for var, func in self.triggers: - if var.offset <= ofs < var.offset + var.size: - for i in range(8): - if (byte >> i) & 1: - func(i + (ofs - var.offset) * 8) - break - else: - ipr = self.struct.IPR - if ipr.offset <= ofs < ipr.offset + ipr.size: - byte &= 0xf0 # IPR[3: 0] reserved - - ctypes.memmove(ctypes.addressof(self.nvic) + ofs, bytes([byte]), 1) - - for ofs in range(offset, offset + size): - write_byte(ofs, value & 0xff) - value >>= 8 - - @property - def region(self): - return [(0, self.struct.RESERVED5.offset), (self.struct.STIR.offset, ctypes.sizeof(self.struct))] \ No newline at end of file +class CortexM4Nvic(CortexMNvic): + pass diff --git a/qiling/hw/intc/cm_nvic.py b/qiling/hw/intc/cm_nvic.py new file mode 100644 index 000000000..f52b31f39 --- /dev/null +++ b/qiling/hw/intc/cm_nvic.py @@ -0,0 +1,144 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +import ctypes + +from qiling.hw.peripheral import QlPeripheral + + +class CortexMNvic(QlPeripheral): + class Type(ctypes.Structure): + _fields_ = [ + ('ISER' , ctypes.c_uint32 * 8), + ('RESERVED0', ctypes.c_uint32 * 24), + ('ICER' , ctypes.c_uint32 * 8), + ('RESERVED1', ctypes.c_uint32 * 24), + ('ISPR' , ctypes.c_uint32 * 8), + ('RESERVED2', ctypes.c_uint32 * 24), + ('ICPR' , ctypes.c_uint32 * 8), + ('RESERVED3', ctypes.c_uint32 * 24), + ('IABR' , ctypes.c_uint32 * 8), + ('RESERVED4', ctypes.c_uint32 * 56), + ('IPR' , ctypes.c_uint8 * 240), + ('RESERVED5', ctypes.c_uint32 * 644), + ('STIR' , ctypes.c_uint32 * 8), + ] + + def __init__(self, ql, label): + super().__init__(ql, label) + + # reference: + # https://www.youtube.com/watch?v=uFBNf7F3l60 + # https://developer.arm.com/documentation/ddi0439/b/Nested-Vectored-Interrupt-Controller + + self.nvic = self.struct() + + ## The max number of interrupt request + self.IRQN_MAX = self.struct.ISER.size * 8 + + ## The ISER unit size + self.MASK = self.IRQN_MAX // len(self.nvic.ISER) - 1 + self.OFFSET = self.MASK.bit_length() + + ## special write behavior + self.triggers = [ + (self.struct.ISER, self.enable), + (self.struct.ICER, self.disable), + (self.struct.ISPR, self.set_pending), + (self.struct.ICPR, self.clear_pending), + ] + + self.intrs = [] + self.interrupt_handler = self.ql.arch.hard_interrupt_handler + + def enable(self, IRQn): + if IRQn >= 0: + self.nvic.ISER[IRQn >> self.OFFSET] |= 1 << (IRQn & self.MASK) + self.nvic.ICER[IRQn >> self.OFFSET] |= 1 << (IRQn & self.MASK) + else: + self.ql.hw.scb.enable(IRQn) + + def disable(self, IRQn): + if IRQn >= 0: + self.nvic.ISER[IRQn >> self.OFFSET] &= self.MASK ^ (1 << (IRQn & self.MASK)) + self.nvic.ICER[IRQn >> self.OFFSET] &= self.MASK ^ (1 << (IRQn & self.MASK)) + else: + self.ql.hw.scb.disable(IRQn) + + def get_enable(self, IRQn): + if IRQn >= 0: + return (self.nvic.ISER[IRQn >> self.OFFSET] >> (IRQn & self.MASK)) & 1 + else: + return self.ql.hw.scb.get_enable(IRQn) + + def set_pending(self, IRQn): + if IRQn >= 0: + self.nvic.ISPR[IRQn >> self.OFFSET] |= 1 << (IRQn & self.MASK) + self.nvic.ICPR[IRQn >> self.OFFSET] |= 1 << (IRQn & self.MASK) + else: + self.ql.hw.scb.set_pending(IRQn) + + if self.get_enable(IRQn): + self.intrs.append(IRQn) + + def clear_pending(self, IRQn): + if IRQn >= 0: + self.nvic.ISPR[IRQn >> self.OFFSET] &= self.MASK ^ (1 << (IRQn & self.MASK)) + self.nvic.ICPR[IRQn >> self.OFFSET] &= self.MASK ^ (1 << (IRQn & self.MASK)) + else: + self.ql.hw.scb.clear_pending(IRQn) + + def get_pending(self, IRQn): + if IRQn >= 0: + return (self.nvic.ISER[IRQn >> self.OFFSET] >> (IRQn & self.MASK)) & 1 + else: + return self.ql.hw.scb.get_pending(IRQn) + + def get_priority(self, IRQn): + if IRQn >= 0: + return self.nvic.IPR[IRQn] + else: + return self.ql.hw.scb.get_priority(IRQn) + + def step(self): + if not self.intrs: + return + + self.intrs.sort(key=lambda x: self.get_priority(x)) + + while self.intrs: + IRQn = self.intrs.pop(0) + self.clear_pending(IRQn) + self.interrupt_handler(self.ql, IRQn) + + @QlPeripheral.monitor() + def read(self, offset: int, size: int) -> int: + buf = ctypes.create_string_buffer(size) + ctypes.memmove(buf, ctypes.addressof(self.nvic) + offset, size) + return int.from_bytes(buf.raw, byteorder='little') + + @QlPeripheral.monitor() + def write(self, offset: int, size: int, value: int): + def write_byte(ofs, byte): + for var, func in self.triggers: + if var.offset <= ofs < var.offset + var.size: + for i in range(8): + if (byte >> i) & 1: + func(i + (ofs - var.offset) * 8) + break + else: + ipr = self.struct.IPR + if ipr.offset <= ofs < ipr.offset + ipr.size: + byte &= 0xf0 # IPR[3: 0] reserved + + ctypes.memmove(ctypes.addressof(self.nvic) + ofs, bytes([byte]), 1) + + for ofs in range(offset, offset + size): + write_byte(ofs, value & 0xff) + value >>= 8 + + @property + def region(self): + return [(0, self.struct.RESERVED5.offset), (self.struct.STIR.offset, ctypes.sizeof(self.struct))] \ No newline at end of file From 43094aeeb9d611d0fc1b41afb3573fd4496ebfa7 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 16:40:00 +0800 Subject: [PATCH 09/32] Fix the format cm4 --- qiling/hw/misc/cm4_scb.py | 1 + 1 file changed, 1 insertion(+) diff --git a/qiling/hw/misc/cm4_scb.py b/qiling/hw/misc/cm4_scb.py index 85077c9e1..9eb0c05c6 100644 --- a/qiling/hw/misc/cm4_scb.py +++ b/qiling/hw/misc/cm4_scb.py @@ -9,6 +9,7 @@ from qiling.hw.peripheral import QlPeripheral from qiling.arch.cortex_m_const import IRQ + class CortexM4Scb(QlPeripheral): class Type(ctypes.Structure): _fields_ = [ From 971d7aabcf0d56b1c7ba8bf9105d00c41d6c5cf6 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 16:54:41 +0800 Subject: [PATCH 10/32] Add cortex series SCB --- qiling/hw/misc/__init__.py | 1 + qiling/hw/misc/cm3_scb.py | 36 +++++++++++++ qiling/hw/misc/cm4_scb.py | 100 +--------------------------------- qiling/hw/misc/cm_scb.py | 107 +++++++++++++++++++++++++++++++++++++ 4 files changed, 146 insertions(+), 98 deletions(-) create mode 100644 qiling/hw/misc/cm3_scb.py create mode 100644 qiling/hw/misc/cm_scb.py diff --git a/qiling/hw/misc/__init__.py b/qiling/hw/misc/__init__.py index 9a290150e..ed72c159f 100644 --- a/qiling/hw/misc/__init__.py +++ b/qiling/hw/misc/__init__.py @@ -3,6 +3,7 @@ # Cross Platform and Multi Architecture Advanced Binary Emulation Framework # +from .cm3_scb import CortexM3Scb from .cm4_scb import CortexM4Scb from .stm32f4xx_rcc import STM32F4xxRcc from .stm32f4xx_rcc_derive import ( diff --git a/qiling/hw/misc/cm3_scb.py b/qiling/hw/misc/cm3_scb.py new file mode 100644 index 000000000..148bca830 --- /dev/null +++ b/qiling/hw/misc/cm3_scb.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + + +import ctypes + +from qiling.hw.misc.cm_scb import CortexMScb + + +class CortexM3Scb(CortexMScb): + class Type(ctypes.Structure): + _fields_ = [ + ('CPUID' , ctypes.c_uint32), + ('ICSR' , ctypes.c_uint32), + ('VTOR' , ctypes.c_uint32), + ('AIRCR' , ctypes.c_uint32), + ('SCR' , ctypes.c_uint32), + ('CCR' , ctypes.c_uint32), + ('SHP' , ctypes.c_uint8 * 12), + ('SHCSR' , ctypes.c_uint32), + ('CFSR' , ctypes.c_uint32), + ('HFSR' , ctypes.c_uint32), + ('DFSR' , ctypes.c_uint32), + ('MMFAR' , ctypes.c_uint32), + ('BFSR' , ctypes.c_uint32), + ] + + def __init__(self, ql, label): + super().__init__(ql, label) + + self.scb = self.struct( + CPUID = 0x411FC231, + AIRCR = 0xFA050000, + ) diff --git a/qiling/hw/misc/cm4_scb.py b/qiling/hw/misc/cm4_scb.py index 9eb0c05c6..7cf2de0b7 100644 --- a/qiling/hw/misc/cm4_scb.py +++ b/qiling/hw/misc/cm4_scb.py @@ -6,11 +6,10 @@ import ctypes -from qiling.hw.peripheral import QlPeripheral -from qiling.arch.cortex_m_const import IRQ +from qiling.hw.misc.cm_scb import CortexMScb -class CortexM4Scb(QlPeripheral): +class CortexM4Scb(CortexMScb): class Type(ctypes.Structure): _fields_ = [ ('CPUID' , ctypes.c_uint32), @@ -37,98 +36,3 @@ def __init__(self, ql, label): AIRCR = 0xFA050000, CCR = 0x00000200, ) - - def enable(self, IRQn): - if IRQn == IRQ.USAGE_FAULT: - self.scb.SHCSR |= 1 << 18 - if IRQn == IRQ.BUS_FAULT: - self.scb.SHCSR |= 1 << 17 - if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: - self.scb.SHCSR |= 1 << 16 - - def disable(self, IRQn): - if IRQn == IRQ.USAGE_FAULT: - self.scb.SHCSR &= ~(1 << 18) - if IRQn == IRQ.BUS_FAULT: - self.scb.SHCSR &= ~(1 << 17) - if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: - self.scb.SHCSR &= ~(1 << 16) - - def get_enable(self, IRQn): - if IRQn == IRQ.USAGE_FAULT: - return (self.scb.SHCSR >> 18) & 1 - if IRQn == IRQ.BUS_FAULT: - return (self.scb.SHCSR >> 17) & 1 - if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: - return (self.scb.SHCSR >> 16) & 1 - return 1 - - def set_pending(self, IRQn): - if IRQn == IRQ.NMI: - self.scb.ICSR |= 1 << 31 - if IRQn == IRQ.PENDSV: - self.scb.ICSR |= 3 << 27 # set-bit and clear-bit - if IRQn == IRQ.SYSTICK: - self.scb.ICSR |= 3 << 25 # set-bit and clear-bit - - if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: - self.scb.SHCSR |= 1 << 13 - if IRQn == IRQ.BUS_FAULT: - self.scb.SHCSR |= 1 << 14 - if IRQn == IRQ.USAGE_FAULT: - self.scb.SHCSR |= 1 << 12 - if IRQn == IRQ.SVCALL: - self.scb.SHCSR |= 1 << 15 - - def clear_pending(self, IRQn): - if IRQn == IRQ.NMI: - self.scb.ICSR &= ~(1 << 31) - if IRQn == IRQ.PENDSV: - self.scb.ICSR &= ~(3 << 27) - if IRQn == IRQ.SYSTICK: - self.scb.ICSR &= ~(3 << 25) - - if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: - self.scb.SHCSR &= ~(1 << 13) - if IRQn == IRQ.BUS_FAULT: - self.scb.SHCSR &= ~(1 << 14) - if IRQn == IRQ.USAGE_FAULT: - self.scb.SHCSR &= ~(1 << 12) - if IRQn == IRQ.SVCALL: - self.scb.SHCSR &= ~(1 << 15) - - def get_pending(self, IRQn): - if IRQn == IRQ.NMI: - return (self.scb.ICSR >> 31) & 1 - if IRQn == IRQ.PENDSV: - return (self.scb.ICSR >> 28) & 1 - if IRQn == IRQ.SYSTICK: - return (self.scb.ICSR >> 26) & 1 - - if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: - return (self.scb.SHCSR >> 13) & 1 - if IRQn == IRQ.BUS_FAULT: - return (self.scb.SHCSR >> 14) & 1 - if IRQn == IRQ.USAGE_FAULT: - return (self.scb.SHCSR >> 12) & 1 - if IRQn == IRQ.SVCALL: - return (self.scb.SHCSR >> 15) & 1 - return 0 - - def get_priority(self, IRQn): - return self.scb.SHP[(IRQn & 0xf) - 4] - - @QlPeripheral.monitor() - def read(self, offset: int, size: int) -> int: - buf = ctypes.create_string_buffer(size) - ctypes.memmove(buf, ctypes.addressof(self.scb) + offset, size) - return int.from_bytes(buf.raw, byteorder='little') - - @QlPeripheral.monitor() - def write(self, offset: int, size: int, value: int): - if offset == self.struct.ICSR.offset: - if (value >> 28) & 1: - self.ql.hw.nvic.set_pending(IRQ.PENDSV) - - data = (value).to_bytes(size, 'little') - ctypes.memmove(ctypes.addressof(self.scb) + offset, data, size) diff --git a/qiling/hw/misc/cm_scb.py b/qiling/hw/misc/cm_scb.py new file mode 100644 index 000000000..a98a0eef6 --- /dev/null +++ b/qiling/hw/misc/cm_scb.py @@ -0,0 +1,107 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + + +import ctypes + +from qiling.hw.peripheral import QlPeripheral +from qiling.arch.cortex_m_const import IRQ + + +class CortexMScb(QlPeripheral): + def enable(self, IRQn): + if IRQn == IRQ.USAGE_FAULT: + self.scb.SHCSR |= 1 << 18 + if IRQn == IRQ.BUS_FAULT: + self.scb.SHCSR |= 1 << 17 + if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: + self.scb.SHCSR |= 1 << 16 + + def disable(self, IRQn): + if IRQn == IRQ.USAGE_FAULT: + self.scb.SHCSR &= ~(1 << 18) + if IRQn == IRQ.BUS_FAULT: + self.scb.SHCSR &= ~(1 << 17) + if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: + self.scb.SHCSR &= ~(1 << 16) + + def get_enable(self, IRQn): + if IRQn == IRQ.USAGE_FAULT: + return (self.scb.SHCSR >> 18) & 1 + if IRQn == IRQ.BUS_FAULT: + return (self.scb.SHCSR >> 17) & 1 + if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: + return (self.scb.SHCSR >> 16) & 1 + return 1 + + def set_pending(self, IRQn): + if IRQn == IRQ.NMI: + self.scb.ICSR |= 1 << 31 + if IRQn == IRQ.PENDSV: + self.scb.ICSR |= 3 << 27 # set-bit and clear-bit + if IRQn == IRQ.SYSTICK: + self.scb.ICSR |= 3 << 25 # set-bit and clear-bit + + if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: + self.scb.SHCSR |= 1 << 13 + if IRQn == IRQ.BUS_FAULT: + self.scb.SHCSR |= 1 << 14 + if IRQn == IRQ.USAGE_FAULT: + self.scb.SHCSR |= 1 << 12 + if IRQn == IRQ.SVCALL: + self.scb.SHCSR |= 1 << 15 + + def clear_pending(self, IRQn): + if IRQn == IRQ.NMI: + self.scb.ICSR &= ~(1 << 31) + if IRQn == IRQ.PENDSV: + self.scb.ICSR &= ~(3 << 27) + if IRQn == IRQ.SYSTICK: + self.scb.ICSR &= ~(3 << 25) + + if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: + self.scb.SHCSR &= ~(1 << 13) + if IRQn == IRQ.BUS_FAULT: + self.scb.SHCSR &= ~(1 << 14) + if IRQn == IRQ.USAGE_FAULT: + self.scb.SHCSR &= ~(1 << 12) + if IRQn == IRQ.SVCALL: + self.scb.SHCSR &= ~(1 << 15) + + def get_pending(self, IRQn): + if IRQn == IRQ.NMI: + return (self.scb.ICSR >> 31) & 1 + if IRQn == IRQ.PENDSV: + return (self.scb.ICSR >> 28) & 1 + if IRQn == IRQ.SYSTICK: + return (self.scb.ICSR >> 26) & 1 + + if IRQn == IRQ.MEMORY_MANAGEMENT_FAULT: + return (self.scb.SHCSR >> 13) & 1 + if IRQn == IRQ.BUS_FAULT: + return (self.scb.SHCSR >> 14) & 1 + if IRQn == IRQ.USAGE_FAULT: + return (self.scb.SHCSR >> 12) & 1 + if IRQn == IRQ.SVCALL: + return (self.scb.SHCSR >> 15) & 1 + return 0 + + def get_priority(self, IRQn): + return self.scb.SHP[(IRQn & 0xf) - 4] + + @QlPeripheral.monitor() + def read(self, offset: int, size: int) -> int: + buf = ctypes.create_string_buffer(size) + ctypes.memmove(buf, ctypes.addressof(self.scb) + offset, size) + return int.from_bytes(buf.raw, byteorder='little') + + @QlPeripheral.monitor() + def write(self, offset: int, size: int, value: int): + if offset == self.struct.ICSR.offset: + if (value >> 28) & 1: + self.ql.hw.nvic.set_pending(IRQ.PENDSV) + + data = (value).to_bytes(size, 'little') + ctypes.memmove(ctypes.addressof(self.scb) + offset, data, size) From 5e998be73f2c7c1d8201b4306ae19c47bb789780 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 17:33:08 +0800 Subject: [PATCH 11/32] Replace class with struct --- qiling/extensions/mcu/stm32f1/stm32f103.py | 64 +++++++++++----------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/qiling/extensions/mcu/stm32f1/stm32f103.py b/qiling/extensions/mcu/stm32f1/stm32f103.py index fa0dff5cd..67530b48e 100644 --- a/qiling/extensions/mcu/stm32f1/stm32f103.py +++ b/qiling/extensions/mcu/stm32f1/stm32f103.py @@ -59,7 +59,7 @@ "TIM2": { "type": "peripheral", "base": 0x40000000, - "class": "STM32F1xxTim", + "struct": "STM32F1xxTim", "kwargs": { "intn": 0x1c } @@ -67,7 +67,7 @@ "TIM3": { "type": "peripheral", "base": 0x40000400, - "class": "STM32F1xxTim", + "struct": "STM32F1xxTim", "kwargs": { "intn": 0x1d } @@ -75,7 +75,7 @@ "TIM4": { "type": "peripheral", "base": 0x40000800, - "class": "STM32F1xxTim", + "struct": "STM32F1xxTim", "kwargs": { "intn": 0x1e } @@ -83,7 +83,7 @@ "RTC": { "type": "peripheral", "base": 0x40002800, - "class": "STM32F1xxRtc", + "struct": "STM32F1xxRtc", "kwargs": { "intn": 0x3, "alarm_intn": 0x29 @@ -92,7 +92,7 @@ "WWDG": { "type": "peripheral", "base": 0x40002c00, - "class": "STM32F1xxWwdg", + "struct": "STM32F1xxWwdg", "kwargs": { "intn": 0x0 } @@ -100,12 +100,12 @@ "IWDG": { "type": "peripheral", "base": 0x40003000, - "class": "STM32F1xxIwdg" + "struct": "STM32F1xxIwdg" }, "SPI2": { "type": "peripheral", "base": 0x40003800, - "class": "STM32F1xxSpi", + "struct": "STM32F1xxSpi", "kwargs": { "intn": 0x24 } @@ -113,7 +113,7 @@ "USART2": { "type": "peripheral", "base": 0x40004400, - "class": "STM32F1xxUsart", + "struct": "STM32F1xxUsart", "kwargs": { "intn": 0x26 } @@ -121,7 +121,7 @@ "USART3": { "type": "peripheral", "base": 0x40004800, - "class": "STM32F1xxUsart", + "struct": "STM32F1xxUsart", "kwargs": { "intn": 0x27 } @@ -129,7 +129,7 @@ "I2C1": { "type": "peripheral", "base": 0x40005400, - "class": "STM32F1xxI2c", + "struct": "STM32F1xxI2c", "kwargs": { "ev_intn": 0x1f, "er_intn": 0x20 @@ -138,7 +138,7 @@ "I2C2": { "type": "peripheral", "base": 0x40005800, - "class": "STM32F1xxI2c", + "struct": "STM32F1xxI2c", "kwargs": { "ev_intn": 0x21, "er_intn": 0x22 @@ -147,7 +147,7 @@ "USB": { "type": "peripheral", "base": 0x40005c00, - "class": "STM32F1xxUsb", + "struct": "STM32F1xxUsb", "kwargs": { "hp_can1_tx_intn": 0x13, "lp_can1_rx0_intn": 0x14, @@ -158,7 +158,7 @@ "CAN1": { "type": "peripheral", "base": 0x40006400, - "class": "STM32F1xxCan", + "struct": "STM32F1xxCan", "kwargs": { "rx1_intn": 0x15, "sce_intn": 0x16, @@ -169,52 +169,52 @@ "BKP": { "type": "peripheral", "base": 0x40006c00, - "class": "STM32F1xxBkp" + "struct": "STM32F1xxBkp" }, "PWR": { "type": "peripheral", "base": 0x40007000, - "class": "STM32F1xxPwr" + "struct": "STM32F1xxPwr" }, "AFIO": { "type": "peripheral", "base": 0x40010000, - "class": "STM32F1xxAfio" + "struct": "STM32F1xxAfio" }, "EXTI": { "type": "peripheral", "base": 0x40010400, - "class": "STM32F1xxExti" + "struct": "STM32F1xxExti" }, "GPIOA": { "type": "peripheral", "base": 0x40010800, - "class": "STM32F1xxGpio" + "struct": "STM32F1xxGpio" }, "GPIOB": { "type": "peripheral", "base": 0x40010c00, - "class": "STM32F1xxGpio" + "struct": "STM32F1xxGpio" }, "GPIOC": { "type": "peripheral", "base": 0x40011000, - "class": "STM32F1xxGpio" + "struct": "STM32F1xxGpio" }, "GPIOD": { "type": "peripheral", "base": 0x40011400, - "class": "STM32F1xxGpio" + "struct": "STM32F1xxGpio" }, "GPIOE": { "type": "peripheral", "base": 0x40011800, - "class": "STM32F1xxGpio" + "struct": "STM32F1xxGpio" }, "ADC1": { "type": "peripheral", "base": 0x40012400, - "class": "STM32F1xxAdc", + "struct": "STM32F1xxAdc", "kwargs": { "intn": 0x12 } @@ -222,12 +222,12 @@ "ADC2": { "type": "peripheral", "base": 0x40012800, - "class": "STM32F1xxAdc" + "struct": "STM32F1xxAdc" }, "TIM1": { "type": "peripheral", "base": 0x40012c00, - "class": "STM32F1xxTim", + "struct": "STM32F1xxTim", "kwargs": { "brk_intn": 0x18, "up_intn": 0x19, @@ -244,7 +244,7 @@ "SPI1": { "type": "peripheral", "base": 0x40013000, - "class": "STM32F1xxSpi", + "struct": "STM32F1xxSpi", "kwargs": { "intn": 0x23 } @@ -252,7 +252,7 @@ "USART1": { "type": "peripheral", "base": 0x40013800, - "class": "STM32F1xxUsart", + "struct": "STM32F1xxUsart", "kwargs": { "intn": 0x25 } @@ -260,12 +260,12 @@ "DMA1": { "type": "peripheral", "base": 0x40020000, - "class": "STM32F1xxDma" + "struct": "STM32F1xxDma" }, "RCC": { "type": "peripheral", "base": 0x40021000, - "class": "STM32F1xxRcc", + "struct": "STM32F1xxRcc", "kwargs": { "intn": 0x5 } @@ -273,7 +273,7 @@ "FLASH INTERFACE": { "type": "peripheral", "base": 0x40022000, - "class": "STM32F1xxFlash", + "struct": "STM32F1xxFlash", "kwargs": { "intn": 0x4 } @@ -281,12 +281,12 @@ "CRC": { "type": "peripheral", "base": 0x40023000, - "class": "STM32F1xxCrc" + "struct": "STM32F1xxCrc" }, "DBGMCU": { "type": "peripheral", "base": 0xe0042000, - "class": "STM32F1xxDbgmcu" + "struct": "STM32F1xxDbgmcu" }, "CODE": { "base": 0x8000000, From 1c831e540db47df6c5a5884df74b61edd8869702 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 17:42:54 +0800 Subject: [PATCH 12/32] Summary stm32 RCC --- qiling/hw/const/{stm32f4xx_rcc.py => stm32_rcc.py} | 0 qiling/hw/misc/stm32f4xx_rcc.py | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename qiling/hw/const/{stm32f4xx_rcc.py => stm32_rcc.py} (100%) diff --git a/qiling/hw/const/stm32f4xx_rcc.py b/qiling/hw/const/stm32_rcc.py similarity index 100% rename from qiling/hw/const/stm32f4xx_rcc.py rename to qiling/hw/const/stm32_rcc.py diff --git a/qiling/hw/misc/stm32f4xx_rcc.py b/qiling/hw/misc/stm32f4xx_rcc.py index f259eab0d..817a455a2 100644 --- a/qiling/hw/misc/stm32f4xx_rcc.py +++ b/qiling/hw/misc/stm32f4xx_rcc.py @@ -5,7 +5,7 @@ import ctypes from qiling.hw.peripheral import QlPeripheral -from qiling.hw.const.stm32f4xx_rcc import RCC_CR, RCC_CFGR, RCC_CSR +from qiling.hw.const.stm32_rcc import RCC_CR, RCC_CFGR, RCC_CSR class STM32F4xxRcc(QlPeripheral): From 6331207af747073a766e283de2514744fda81a5a Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 17:47:15 +0800 Subject: [PATCH 13/32] Add stm32f1xx RCC --- qiling/hw/misc/__init__.py | 1 + qiling/hw/misc/stm32f1xx_rcc.py | 82 +++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 qiling/hw/misc/stm32f1xx_rcc.py diff --git a/qiling/hw/misc/__init__.py b/qiling/hw/misc/__init__.py index ed72c159f..0be48f5d5 100644 --- a/qiling/hw/misc/__init__.py +++ b/qiling/hw/misc/__init__.py @@ -5,6 +5,7 @@ from .cm3_scb import CortexM3Scb from .cm4_scb import CortexM4Scb +from .stm32f1xx_rcc import STM32F1xxRcc from .stm32f4xx_rcc import STM32F4xxRcc from .stm32f4xx_rcc_derive import ( STM32F4xxRccV1, STM32F4xxRccV2, diff --git a/qiling/hw/misc/stm32f1xx_rcc.py b/qiling/hw/misc/stm32f1xx_rcc.py new file mode 100644 index 000000000..32d670270 --- /dev/null +++ b/qiling/hw/misc/stm32f1xx_rcc.py @@ -0,0 +1,82 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +import ctypes +from qiling.hw.peripheral import QlPeripheral +from qiling.hw.const.stm32_rcc import RCC_CR, RCC_CFGR, RCC_CSR + + +class STM32F1xxRcc(QlPeripheral): + class Type(ctypes.Structure): + """ the structure is available in : + stm32f101xb + stm32f101xe + stm32f101xg + stm32f102xb + stm32f103xb + stm32f103xe + stm32f103xg + """ + + _fields_ = [ + ("CR" , ctypes.c_uint32), + ("CFGR" , ctypes.c_uint32), + ("CIR" , ctypes.c_uint32), + ("APB2RSTR", ctypes.c_uint32), + ("APB1RSTR", ctypes.c_uint32), + ("AHBENR" , ctypes.c_uint32), + ("APB2ENR" , ctypes.c_uint32), + ("APB1ENR" , ctypes.c_uint32), + ("BDCR" , ctypes.c_uint32), + ("CSR" , ctypes.c_uint32), + ] + + def __init__(self, ql, label, intn=None): + super().__init__(ql, label) + + self.rcc = self.struct( + CR = 0x00000083, + AHBENR = 0x00000014, + CSR = 0x0C000000, + ) + + self.rdyon = { + 'CR': [ + (RCC_CR.HSIRDY , RCC_CR.HSION ), + (RCC_CR.HSERDY , RCC_CR.HSEON ), + (RCC_CR.PLLRDY , RCC_CR.PLLON ), + (RCC_CR.PLLI2SRDY, RCC_CR.PLLI2SON), + ], + 'CFGR': [ + (RCC_CFGR.SWS_0, RCC_CFGR.SW_0), + (RCC_CFGR.SWS_1, RCC_CFGR.SW_1), + ], + 'CSR': [ + (RCC_CSR.LSIRDY, RCC_CSR.LSION) + ] + } + + self.intn = intn + + @QlPeripheral.monitor() + def read(self, offset: int, size: int) -> int: + buf = ctypes.create_string_buffer(size) + ctypes.memmove(buf, ctypes.addressof(self.rcc) + offset, size) + return int.from_bytes(buf.raw, byteorder='little') + + @QlPeripheral.monitor() + def write(self, offset: int, size: int, value: int): + data = (value).to_bytes(size, 'little') + ctypes.memmove(ctypes.addressof(self.rcc) + offset, data, size) + + def step(self): + for reg, rdyon in self.rdyon.items(): + value = getattr(self.rcc, reg) + for rdy, on in rdyon: + if value & on: + value |= rdy + else: + value &= ~rdy + setattr(self.rcc, reg, value) From 4133f7e7d3ad2c84f7208d65c82cdb13dc416a9c Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 17:56:11 +0800 Subject: [PATCH 14/32] Add stm32f1 usart --- qiling/hw/char/__init__.py | 1 + qiling/hw/char/stm32f1xx_usart.py | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 qiling/hw/char/stm32f1xx_usart.py diff --git a/qiling/hw/char/__init__.py b/qiling/hw/char/__init__.py index 4fb762c07..5b2e40b80 100644 --- a/qiling/hw/char/__init__.py +++ b/qiling/hw/char/__init__.py @@ -3,5 +3,6 @@ # Cross Platform and Multi Architecture Advanced Binary Emulation Framework # +from .stm32f1xx_usart import STM32F1xxUsart from .stm32f4xx_usart import STM32F4xxUsart from .gd32vf1xx_usart import GD32VF1xxUsart \ No newline at end of file diff --git a/qiling/hw/char/stm32f1xx_usart.py b/qiling/hw/char/stm32f1xx_usart.py new file mode 100644 index 000000000..fa8d57f8d --- /dev/null +++ b/qiling/hw/char/stm32f1xx_usart.py @@ -0,0 +1,30 @@ +import ctypes + +from qiling.hw.char.stm32f4xx_usart import STM32F4xxUsart + + +class STM32F1xxUsart(STM32F4xxUsart): + class Type(ctypes.Structure): + """ the structure available in : + stm32f100xb + stm32f100xe + stm32f101xb + stm32f101xe + stm32f101xg + stm32f102xb + stm32f103xb + stm32f103xe + stm32f103xg + stm32f105xc + stm32f107xc + """ + + _fields_ = [ + ("SR" , ctypes.c_uint32), #USART Status register, Address offset: 0x00 + ("DR" , ctypes.c_uint32), #USART Data register, Address offset: 0x04 + ("BRR" , ctypes.c_uint32), #USART Baud rate register, Address offset: 0x08 + ("CR1" , ctypes.c_uint32), #USART Control register 1, Address offset: 0x0C + ("CR2" , ctypes.c_uint32), #USART Control register 2, Address offset: 0x10 + ("CR3" , ctypes.c_uint32), #USART Control register 3, Address offset: 0x14 + ("GTPR", ctypes.c_uint32), #USART Guard time and prescaler register, Address offset: 0x18 + ] From c46314f99cc3003c1c1342b54b5fa53c9468b2cc Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 18:12:21 +0800 Subject: [PATCH 15/32] Add stm32f1xx flash --- qiling/hw/misc/__init__.py | 1 + qiling/hw/misc/stm32f1xx_flash.py | 55 +++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 qiling/hw/misc/stm32f1xx_flash.py diff --git a/qiling/hw/misc/__init__.py b/qiling/hw/misc/__init__.py index 0be48f5d5..b7d0d4995 100644 --- a/qiling/hw/misc/__init__.py +++ b/qiling/hw/misc/__init__.py @@ -6,6 +6,7 @@ from .cm3_scb import CortexM3Scb from .cm4_scb import CortexM4Scb from .stm32f1xx_rcc import STM32F1xxRcc +from .stm32f1xx_flash import STM32F1xxFlash from .stm32f4xx_rcc import STM32F4xxRcc from .stm32f4xx_rcc_derive import ( STM32F4xxRccV1, STM32F4xxRccV2, diff --git a/qiling/hw/misc/stm32f1xx_flash.py b/qiling/hw/misc/stm32f1xx_flash.py new file mode 100644 index 000000000..46afeed2d --- /dev/null +++ b/qiling/hw/misc/stm32f1xx_flash.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + + +import ctypes +from qiling.core import Qiling + +from qiling.hw.peripheral import QlPeripheral + + +class STM32F1xxFlash(QlPeripheral): + class Type(ctypes.Structure): + """ the structure available in : + stm32f100xb + stm32f100xe + stm32f101xb + stm32f101xe + stm32f102xb + stm32f103xb + stm32f103xe + stm32f105xc + stm32f107xc + """ + + _fields_ = [ + ("ACR" , ctypes.c_uint32), + ("KEYR" , ctypes.c_uint32), + ("OPTKEYR" , ctypes.c_uint32), + ("SR" , ctypes.c_uint32), + ("CR" , ctypes.c_uint32), + ("AR" , ctypes.c_uint32), + ("RESERVED", ctypes.c_uint32), + ("OBR" , ctypes.c_uint32), + ("WRPR" , ctypes.c_uint32), + ] + + def __init__(self, ql: Qiling, label: str, intn: int = None): + super().__init__(ql, label) + + self.intn = intn + self.flash = self.struct() + + @QlPeripheral.monitor() + def read(self, offset: int, size: int) -> int: + buf = ctypes.create_string_buffer(size) + ctypes.memmove(buf, ctypes.addressof(self.flash) + offset, size) + return int.from_bytes(buf.raw, byteorder='little') + + @QlPeripheral.monitor() + def write(self, offset: int, size: int, value: int): + data = (value).to_bytes(size, 'little') + ctypes.memmove(ctypes.addressof(self.flash) + offset, data, size) + From 1c77daa431bd6e39476dee39e5538dbff8f0cede Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 18:26:26 +0800 Subject: [PATCH 16/32] Add stm32f1xx exti --- qiling/hw/intc/__init__.py | 1 + qiling/hw/intc/stm32f1xx_exti.py | 34 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 qiling/hw/intc/stm32f1xx_exti.py diff --git a/qiling/hw/intc/__init__.py b/qiling/hw/intc/__init__.py index e620b1511..6493d709a 100644 --- a/qiling/hw/intc/__init__.py +++ b/qiling/hw/intc/__init__.py @@ -5,5 +5,6 @@ from .cm3_nvic import CortexM3Nvic from .cm4_nvic import CortexM4Nvic +from .stm32f1xx_exti import STM32F1xxExti from .stm32f4xx_exti import STM32F4xxExti from .gd32vf1xx_eclic import GD32VF1xxEclic diff --git a/qiling/hw/intc/stm32f1xx_exti.py b/qiling/hw/intc/stm32f1xx_exti.py new file mode 100644 index 000000000..d6fc98511 --- /dev/null +++ b/qiling/hw/intc/stm32f1xx_exti.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +import ctypes + +from qiling.hw.intc.stm32f4xx_exti import STM32F4xxExti + + +class STM32F1xxExti(STM32F4xxExti): + class Type(ctypes.Structure): + """ the structure available in : + stm32f100xb + stm32f100xe + stm32f101xb + stm32f101xe + stm32f101xg + stm32f102xb + stm32f103xb + stm32f103xe + stm32f103xg + stm32f105xc + stm32f107xc + """ + + _fields_ = [ + ("IMR" , ctypes.c_uint32), + ("EMR" , ctypes.c_uint32), + ("RTSR" , ctypes.c_uint32), + ("FTSR" , ctypes.c_uint32), + ("SWIER", ctypes.c_uint32), + ("PR" , ctypes.c_uint32), + ] From 9c58c8c340c96f80cb15a643a7bb8b6916189ebd Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 18:26:37 +0800 Subject: [PATCH 17/32] Add stm32f1xx gpio --- qiling/hw/gpio/__init__.py | 1 + qiling/hw/gpio/stm32f1xx_gpio.py | 42 ++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 qiling/hw/gpio/stm32f1xx_gpio.py diff --git a/qiling/hw/gpio/__init__.py b/qiling/hw/gpio/__init__.py index a68286080..41599dfb6 100644 --- a/qiling/hw/gpio/__init__.py +++ b/qiling/hw/gpio/__init__.py @@ -3,5 +3,6 @@ # Cross Platform and Multi Architecture Advanced Binary Emulation Framework # +from .stm32f1xx_gpio import STM32F1xxGpio from .stm32f4xx_gpio import STM32F4xxGpio from .gd32vf1xx_gpio import GD32VF1xxGpio \ No newline at end of file diff --git a/qiling/hw/gpio/stm32f1xx_gpio.py b/qiling/hw/gpio/stm32f1xx_gpio.py new file mode 100644 index 000000000..da7d0a793 --- /dev/null +++ b/qiling/hw/gpio/stm32f1xx_gpio.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +import ctypes + +from qiling.hw.peripheral import QlPeripheral +from qiling.hw.gpio.hooks import GpioHooks + + +class STM32F1xxGpio(QlPeripheral, GpioHooks): + class Type(ctypes.Structure): + """ the structure available in : + stm32f100xb + stm32f100xe + stm32f101xb + stm32f101xe + stm32f101xg + stm32f102xb + stm32f103xb + stm32f103xe + stm32f103xg + stm32f105xc + stm32f107xc + """ + + _fields_ = [ + ("CRL" , ctypes.c_uint32), + ("CRH" , ctypes.c_uint32), + ("IDR" , ctypes.c_uint32), + ("ODR" , ctypes.c_uint32), + ("BSRR", ctypes.c_uint32), + ("BRR" , ctypes.c_uint32), + ("LCKR", ctypes.c_uint32), + ] + + def __init__(self, ql, label): + QlPeripheral.__init__(self, ql, label) + GpioHooks.__init__(self, ql, 16) + + self.gpio = self.struct() From 89fddb57d477b5ab55b22e2cb29f1918c3f6f65a Mon Sep 17 00:00:00 2001 From: dataisland Date: Sat, 5 Feb 2022 18:30:29 +0800 Subject: [PATCH 18/32] Add stm32f1xx afio --- qiling/hw/gpio/__init__.py | 1 + qiling/hw/gpio/stm32f1xx_afio.py | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 qiling/hw/gpio/stm32f1xx_afio.py diff --git a/qiling/hw/gpio/__init__.py b/qiling/hw/gpio/__init__.py index 41599dfb6..ae7943147 100644 --- a/qiling/hw/gpio/__init__.py +++ b/qiling/hw/gpio/__init__.py @@ -4,5 +4,6 @@ # from .stm32f1xx_gpio import STM32F1xxGpio +from .stm32f1xx_afio import STM32F1xxAfio from .stm32f4xx_gpio import STM32F4xxGpio from .gd32vf1xx_gpio import GD32VF1xxGpio \ No newline at end of file diff --git a/qiling/hw/gpio/stm32f1xx_afio.py b/qiling/hw/gpio/stm32f1xx_afio.py new file mode 100644 index 000000000..24249257b --- /dev/null +++ b/qiling/hw/gpio/stm32f1xx_afio.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +import ctypes + +from qiling.hw.peripheral import QlPeripheral + + +class STM32F1xxAfio(QlPeripheral): + class Type(ctypes.Structure): + """ the structure available in : + stm32f100xb + stm32f100xe + stm32f101xb + stm32f101xe + stm32f101xg + stm32f102xb + stm32f103xb + stm32f103xe + stm32f103xg + stm32f105xc + stm32f107xc + """ + + _fields_ = [ + ("EVCR" , ctypes.c_uint32), + ("MAPR" , ctypes.c_uint32), + ("EXTICR" , ctypes.c_uint32 * 4), + ("RESERVED0", ctypes.c_uint32), + ("MAPR2" , ctypes.c_uint32), + ] From 3c7245b07037cd664eb03c77c45ced2f8c44701b Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 10:38:25 +0800 Subject: [PATCH 19/32] Fix RCC const name --- qiling/hw/const/{stm32_rcc.py => stm32fxxx_rcc.py} | 0 qiling/hw/misc/stm32f1xx_rcc.py | 2 +- qiling/hw/misc/stm32f4xx_rcc.py | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename qiling/hw/const/{stm32_rcc.py => stm32fxxx_rcc.py} (100%) diff --git a/qiling/hw/const/stm32_rcc.py b/qiling/hw/const/stm32fxxx_rcc.py similarity index 100% rename from qiling/hw/const/stm32_rcc.py rename to qiling/hw/const/stm32fxxx_rcc.py diff --git a/qiling/hw/misc/stm32f1xx_rcc.py b/qiling/hw/misc/stm32f1xx_rcc.py index 32d670270..234b7950e 100644 --- a/qiling/hw/misc/stm32f1xx_rcc.py +++ b/qiling/hw/misc/stm32f1xx_rcc.py @@ -5,7 +5,7 @@ import ctypes from qiling.hw.peripheral import QlPeripheral -from qiling.hw.const.stm32_rcc import RCC_CR, RCC_CFGR, RCC_CSR +from qiling.hw.const.stm32fxxx import RCC_CR, RCC_CFGR, RCC_CSR class STM32F1xxRcc(QlPeripheral): diff --git a/qiling/hw/misc/stm32f4xx_rcc.py b/qiling/hw/misc/stm32f4xx_rcc.py index 817a455a2..c2ccf09db 100644 --- a/qiling/hw/misc/stm32f4xx_rcc.py +++ b/qiling/hw/misc/stm32f4xx_rcc.py @@ -5,7 +5,7 @@ import ctypes from qiling.hw.peripheral import QlPeripheral -from qiling.hw.const.stm32_rcc import RCC_CR, RCC_CFGR, RCC_CSR +from qiling.hw.const.stm32fxxx import RCC_CR, RCC_CFGR, RCC_CSR class STM32F4xxRcc(QlPeripheral): From b92e75ea9a3d5d1081552ef9106c925303fc58f3 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 10:49:00 +0800 Subject: [PATCH 20/32] Fix RCC const typo --- qiling/hw/misc/stm32f1xx_rcc.py | 2 +- qiling/hw/misc/stm32f4xx_rcc.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qiling/hw/misc/stm32f1xx_rcc.py b/qiling/hw/misc/stm32f1xx_rcc.py index 234b7950e..aff4323e3 100644 --- a/qiling/hw/misc/stm32f1xx_rcc.py +++ b/qiling/hw/misc/stm32f1xx_rcc.py @@ -5,7 +5,7 @@ import ctypes from qiling.hw.peripheral import QlPeripheral -from qiling.hw.const.stm32fxxx import RCC_CR, RCC_CFGR, RCC_CSR +from qiling.hw.const.stm32fxxx_rcc import RCC_CR, RCC_CFGR, RCC_CSR class STM32F1xxRcc(QlPeripheral): diff --git a/qiling/hw/misc/stm32f4xx_rcc.py b/qiling/hw/misc/stm32f4xx_rcc.py index c2ccf09db..ac45168ce 100644 --- a/qiling/hw/misc/stm32f4xx_rcc.py +++ b/qiling/hw/misc/stm32f4xx_rcc.py @@ -5,7 +5,7 @@ import ctypes from qiling.hw.peripheral import QlPeripheral -from qiling.hw.const.stm32fxxx import RCC_CR, RCC_CFGR, RCC_CSR +from qiling.hw.const.stm32fxxx_rcc import RCC_CR, RCC_CFGR, RCC_CSR class STM32F4xxRcc(QlPeripheral): From 59b90d3aae754ba70d23c12ea39ce0641aef4452 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 11:03:07 +0800 Subject: [PATCH 21/32] Delete stm32f4 dma magic number --- qiling/hw/dma/stm32f4xx_dma.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/qiling/hw/dma/stm32f4xx_dma.py b/qiling/hw/dma/stm32f4xx_dma.py index 8aebfbc01..838254775 100644 --- a/qiling/hw/dma/stm32f4xx_dma.py +++ b/qiling/hw/dma/stm32f4xx_dma.py @@ -104,10 +104,7 @@ def __init__( super().__init__(ql, label) self.dma = self.struct() - - self.stream_base = 0x10 - self.stream_size = ctypes.sizeof(Stream) - + self.intn = [ stream0_intn, stream1_intn, @@ -120,7 +117,7 @@ def __init__( ] def stream_index(self, offset): - return (offset - self.stream_base) // self.stream_size + return (offset - self.struct.stream.offset) // ctypes.sizeof(Stream) @QlPeripheral.monitor(width=15) def read(self, offset: int, size: int) -> int: From 91ea1078a431ccc11016fa6b6ee7a73e18161df8 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 12:38:52 +0800 Subject: [PATCH 22/32] Uncompress adio register --- qiling/hw/gpio/stm32f1xx_afio.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/qiling/hw/gpio/stm32f1xx_afio.py b/qiling/hw/gpio/stm32f1xx_afio.py index 24249257b..dbdaeafcb 100644 --- a/qiling/hw/gpio/stm32f1xx_afio.py +++ b/qiling/hw/gpio/stm32f1xx_afio.py @@ -27,7 +27,10 @@ class Type(ctypes.Structure): _fields_ = [ ("EVCR" , ctypes.c_uint32), ("MAPR" , ctypes.c_uint32), - ("EXTICR" , ctypes.c_uint32 * 4), + ("EXTICR1" , ctypes.c_uint32), + ("EXTICR2" , ctypes.c_uint32), + ("EXTICR3" , ctypes.c_uint32), + ("EXTICR4" , ctypes.c_uint32), ("RESERVED0", ctypes.c_uint32), ("MAPR2" , ctypes.c_uint32), ] From a82144d2a929725d98d36a335ff6435fc8d26bfb Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 12:39:20 +0800 Subject: [PATCH 23/32] Add stm32f103 DMA interrupt setting --- qiling/extensions/mcu/stm32f1/stm32f103.py | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/qiling/extensions/mcu/stm32f1/stm32f103.py b/qiling/extensions/mcu/stm32f1/stm32f103.py index 67530b48e..911989a4e 100644 --- a/qiling/extensions/mcu/stm32f1/stm32f103.py +++ b/qiling/extensions/mcu/stm32f1/stm32f103.py @@ -260,7 +260,17 @@ "DMA1": { "type": "peripheral", "base": 0x40020000, - "struct": "STM32F1xxDma" + "struct": "STM32F1xxDma", + "kwargs": { + "stream0_intn": 0xb, + "stream1_intn": 0xc, + "stream2_intn": 0xd, + "stream3_intn": 0xe, + "stream4_intn": 0xf, + "stream5_intn": 0x10, + "stream6_intn": 0x11, + "stream7_intn": 0x2f + }, }, "RCC": { "type": "peripheral", From 68d236f184cf82a25f5556eff52b568a667e2e2b Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 20:21:33 +0800 Subject: [PATCH 24/32] Unity stm32f1/4 gpio --- qiling/hw/gpio/stm32f1xx_gpio.py | 56 ++++++++++++++++++++++++++++++ qiling/hw/gpio/stm32f4xx_gpio.py | 59 ++------------------------------ 2 files changed, 58 insertions(+), 57 deletions(-) diff --git a/qiling/hw/gpio/stm32f1xx_gpio.py b/qiling/hw/gpio/stm32f1xx_gpio.py index da7d0a793..5b30c6c87 100644 --- a/qiling/hw/gpio/stm32f1xx_gpio.py +++ b/qiling/hw/gpio/stm32f1xx_gpio.py @@ -40,3 +40,59 @@ def __init__(self, ql, label): GpioHooks.__init__(self, ql, 16) self.gpio = self.struct() + + @QlPeripheral.monitor() + def read(self, offset: int, size: int) -> int: + if offset == self.struct.BSRR.offset: + return 0x00 + + buf = ctypes.create_string_buffer(size) + ctypes.memmove(buf, ctypes.addressof(self.gpio) + offset, size) + return int.from_bytes(buf.raw, byteorder='little') + + @QlPeripheral.monitor() + def write(self, offset: int, size: int, value: int): + if offset == self.struct.IDR.offset: + return + + if offset == self.struct.BSRR.offset: + for i in range(32): + if ((value >> i) & 1) == 0: + continue + if i < 16: + self.set_pin(i) + else: + self.reset_pin(i - 16) + + return + + if offset == self.struct.ODR.offset: + for i in range(16): + new_bit = (value >> i) & 1 + old_bit = (self.gpio.ODR >> i) & 1 + + if new_bit != old_bit: + if new_bit: + self.set_pin(i) + else: + self.reset_pin(i) + + return + + data = (value).to_bytes(size, 'little') + ctypes.memmove(ctypes.addressof(self.gpio) + offset, data, size) + + def set_pin(self, i): + self.ql.log.debug(f'[{self.label}] Set P{self.label[-1].upper()}{i}') + + self.gpio.ODR |= 1 << i + self.call_hook_set(i) + + def reset_pin(self, i): + self.ql.log.debug(f'[{self.label}] Reset P{self.label[-1].upper()}{i}') + + self.gpio.ODR &= ~(1 << i) + self.call_hook_reset(i) + + def pin(self, index): + return (self.gpio.ODR >> index) & 1 \ No newline at end of file diff --git a/qiling/hw/gpio/stm32f4xx_gpio.py b/qiling/hw/gpio/stm32f4xx_gpio.py index 89ad20de9..de00d1726 100644 --- a/qiling/hw/gpio/stm32f4xx_gpio.py +++ b/qiling/hw/gpio/stm32f4xx_gpio.py @@ -5,11 +5,12 @@ import ctypes +from qiling.hw.gpio.stm32f1xx_gpio import STM32F1xxGpio from qiling.hw.peripheral import QlPeripheral from qiling.hw.gpio.hooks import GpioHooks -class STM32F4xxGpio(QlPeripheral, GpioHooks): +class STM32F4xxGpio(STM32F1xxGpio): class Type(ctypes.Structure): """ the structure available in : stm32f413xx.h @@ -63,59 +64,3 @@ def __init__(self, ql, label, OSPEEDR = ospeedr_reset, PUPDR = pupdr_reset, ) - - @QlPeripheral.monitor() - def read(self, offset: int, size: int) -> int: - if offset == self.struct.BSRR.offset: - return 0x00 - - buf = ctypes.create_string_buffer(size) - ctypes.memmove(buf, ctypes.addressof(self.gpio) + offset, size) - return int.from_bytes(buf.raw, byteorder='little') - - @QlPeripheral.monitor() - def write(self, offset: int, size: int, value: int): - if offset == self.struct.IDR.offset: - return - - if offset == self.struct.BSRR.offset: - for i in range(32): - if ((value >> i) & 1) == 0: - continue - if i < 16: - self.set_pin(i) - else: - self.reset_pin(i - 16) - - return - - if offset == self.struct.ODR.offset: - for i in range(16): - new_bit = (value >> i) & 1 - old_bit = (self.gpio.ODR >> i) & 1 - - if new_bit != old_bit: - if new_bit: - self.set_pin(i) - else: - self.reset_pin(i) - - return - - data = (value).to_bytes(size, 'little') - ctypes.memmove(ctypes.addressof(self.gpio) + offset, data, size) - - def set_pin(self, i): - self.ql.log.debug(f'[{self.label}] Set P{self.label[-1].upper()}{i}') - - self.gpio.ODR |= 1 << i - self.call_hook_set(i) - - def reset_pin(self, i): - self.ql.log.debug(f'[{self.label}] Reset P{self.label[-1].upper()}{i}') - - self.gpio.ODR &= ~(1 << i) - self.call_hook_reset(i) - - def pin(self, index): - return (self.gpio.ODR >> index) & 1 From 204e0f99944ddfe609c1b2247af0a55dbef3a437 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 21:28:00 +0800 Subject: [PATCH 25/32] Connect afio with exti --- qiling/hw/gpio/stm32f1xx_afio.py | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/qiling/hw/gpio/stm32f1xx_afio.py b/qiling/hw/gpio/stm32f1xx_afio.py index dbdaeafcb..c0305833c 100644 --- a/qiling/hw/gpio/stm32f1xx_afio.py +++ b/qiling/hw/gpio/stm32f1xx_afio.py @@ -27,10 +27,31 @@ class Type(ctypes.Structure): _fields_ = [ ("EVCR" , ctypes.c_uint32), ("MAPR" , ctypes.c_uint32), - ("EXTICR1" , ctypes.c_uint32), - ("EXTICR2" , ctypes.c_uint32), - ("EXTICR3" , ctypes.c_uint32), - ("EXTICR4" , ctypes.c_uint32), + ("EXTICR" , ctypes.c_uint32 * 4), ("RESERVED0", ctypes.c_uint32), ("MAPR2" , ctypes.c_uint32), ] + + def __init__(self, ql, label): + super().__init__(ql, label) + + self.afio = self.struct() + + @QlPeripheral.monitor() + def read(self, offset: int, size: int) -> int: + buf = ctypes.create_string_buffer(size) + ctypes.memmove(buf, ctypes.addressof(self.afio) + offset, size) + return int.from_bytes(buf.raw, byteorder='little') + + @QlPeripheral.monitor() + def write(self, offset: int, size: int, value: int): + data = (value).to_bytes(size, 'little') + ctypes.memmove(ctypes.addressof(self.afio) + offset, data, size) + + def exti(self, index): + """ Get EXTI{index} mapping information """ + + port_index = self.afio.EXTICR[index // 4] >> ((index & 3) * 4) + port_name = 'gpio' + 'abcdefg'[port_index] + + return getattr(self.ql.hw, port_name, None) From 120da77b8cc2a3f1bb25d7e1f84914927ebdcc6c Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 21:28:18 +0800 Subject: [PATCH 26/32] Add exti soft interrupt support --- qiling/hw/intc/stm32f1xx_exti.py | 56 ++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/qiling/hw/intc/stm32f1xx_exti.py b/qiling/hw/intc/stm32f1xx_exti.py index d6fc98511..cea43ad7a 100644 --- a/qiling/hw/intc/stm32f1xx_exti.py +++ b/qiling/hw/intc/stm32f1xx_exti.py @@ -5,10 +5,10 @@ import ctypes -from qiling.hw.intc.stm32f4xx_exti import STM32F4xxExti +from qiling.hw.peripheral import QlPeripheral -class STM32F1xxExti(STM32F4xxExti): +class STM32F1xxExti(QlPeripheral): class Type(ctypes.Structure): """ the structure available in : stm32f100xb @@ -32,3 +32,55 @@ class Type(ctypes.Structure): ("SWIER", ctypes.c_uint32), ("PR" , ctypes.c_uint32), ] + + def __init__(self, ql, label, + exti0_intn = None, + exti1_intn = None, + exti2_intn = None, + exti3_intn = None, + exti4_intn = None, + exti9_5_intn = None, + exti15_10_intn = None, + ): + super().__init__(ql, label) + + self.exti = self.struct() + self.intn = [ + exti0_intn , exti1_intn , exti2_intn , exti3_intn, + exti4_intn , exti9_5_intn , exti9_5_intn , exti9_5_intn, + exti9_5_intn , exti9_5_intn , exti15_10_intn, exti15_10_intn, + exti15_10_intn, exti15_10_intn, exti15_10_intn, exti15_10_intn + ] + + @QlPeripheral.monitor() + def read(self, offset: int, size: int) -> int: + buf = ctypes.create_string_buffer(size) + ctypes.memmove(buf, ctypes.addressof(self.exti) + offset, size) + return int.from_bytes(buf.raw, byteorder='little') + + @QlPeripheral.monitor() + def write(self, offset: int, size: int, value: int): + if offset == self.struct.SWIER.offset: + value = value & self.exti.IMR & 0x7ffff + for i in range(20): + if ((self.exti.SWIER >> i) & 1) == 0 and ((value >> i) & 1) == 1: + self.send_interrupt(i) + + elif offset == self.struct.PR.offset: + for i in range(20): + if (value >> i) & 1: + self.exti.PR &= ~(1 << i) + self.exti.SWIER &= ~(1 << i) + + return + + data = (value).to_bytes(size, 'little') + ctypes.memmove(ctypes.addressof(self.exti) + offset, data, size) + + def send_interrupt(self, index): + if 0 <= index < 20 and (self.exti.IMR >> index) & 1: + self.exti.PR |= 1 << index + + if index < 16: + self.ql.hw.afio.exti(index).set_pin(index) + self.ql.hw.nvic.set_pending(self.intn[index]) From efb05a3da01f40a52529951938ec57ed95c60f8f Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 21:52:24 +0800 Subject: [PATCH 27/32] Add exti interrupt config --- qiling/extensions/mcu/stm32f1/stm32f103.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/qiling/extensions/mcu/stm32f1/stm32f103.py b/qiling/extensions/mcu/stm32f1/stm32f103.py index 911989a4e..a7331ffee 100644 --- a/qiling/extensions/mcu/stm32f1/stm32f103.py +++ b/qiling/extensions/mcu/stm32f1/stm32f103.py @@ -184,7 +184,16 @@ "EXTI": { "type": "peripheral", "base": 0x40010400, - "struct": "STM32F1xxExti" + "struct": "STM32F1xxExti", + "kwargs": { + "exti0_intn": 6, + "exti1_intn": 7, + "exti2_intn": 8, + "exti3_intn": 9, + "exti4_intn": 10, + "exti9_5_intn": 23, + "exti15_10_intn": 40, + } }, "GPIOA": { "type": "peripheral", From 1c502ecdf472f83f5dc23e643607d1acbbffa970 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 22:15:03 +0800 Subject: [PATCH 28/32] Delete useless temporary variable --- qiling/hw/dma/stm32f4xx_dma.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/qiling/hw/dma/stm32f4xx_dma.py b/qiling/hw/dma/stm32f4xx_dma.py index 838254775..ab1499784 100644 --- a/qiling/hw/dma/stm32f4xx_dma.py +++ b/qiling/hw/dma/stm32f4xx_dma.py @@ -123,8 +123,7 @@ def stream_index(self, offset): def read(self, offset: int, size: int) -> int: buf = ctypes.create_string_buffer(size) ctypes.memmove(buf, ctypes.addressof(self.dma) + offset, size) - retval = int.from_bytes(buf.raw, byteorder='little') - return retval + return int.from_bytes(buf.raw, byteorder='little') @QlPeripheral.monitor(width=15) def write(self, offset: int, size: int, value: int): From 8f349b529649e1a7f2ce6a0bc5ccee1bbceb0906 Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 22:27:44 +0800 Subject: [PATCH 29/32] Delete redundant function in DMA --- qiling/hw/dma/stm32f4xx_dma.py | 5 ----- 1 file changed, 5 deletions(-) diff --git a/qiling/hw/dma/stm32f4xx_dma.py b/qiling/hw/dma/stm32f4xx_dma.py index ab1499784..fa22982dd 100644 --- a/qiling/hw/dma/stm32f4xx_dma.py +++ b/qiling/hw/dma/stm32f4xx_dma.py @@ -116,9 +116,6 @@ def __init__( stream7_intn, ] - def stream_index(self, offset): - return (offset - self.struct.stream.offset) // ctypes.sizeof(Stream) - @QlPeripheral.monitor(width=15) def read(self, offset: int, size: int) -> int: buf = ctypes.create_string_buffer(size) @@ -134,8 +131,6 @@ def write(self, offset: int, size: int, value: int): self.dma.HISR &= ~value elif offset > self.struct.HIFCR.offset: - stream_id = self.stream_index(offset) - data = (value).to_bytes(size, byteorder='little') ctypes.memmove(ctypes.addressof(self.dma) + offset, data, size) From 22339191f34e65691f199efadb68c1bc106f034d Mon Sep 17 00:00:00 2001 From: dataisland Date: Sun, 6 Feb 2022 23:57:38 +0800 Subject: [PATCH 30/32] Add stm32f1xx dma --- qiling/hw/const/stm32f1xx_dma.py | 97 +++++++++++++++++ qiling/hw/dma/__init__.py | 1 + qiling/hw/dma/stm32f1xx_dma.py | 172 +++++++++++++++++++++++++++++++ 3 files changed, 270 insertions(+) create mode 100644 qiling/hw/const/stm32f1xx_dma.py create mode 100644 qiling/hw/dma/stm32f1xx_dma.py diff --git a/qiling/hw/const/stm32f1xx_dma.py b/qiling/hw/const/stm32f1xx_dma.py new file mode 100644 index 000000000..a848428e8 --- /dev/null +++ b/qiling/hw/const/stm32f1xx_dma.py @@ -0,0 +1,97 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +from enum import IntEnum + + +class DMA_ISR(IntEnum): + GIF1 = 1 << 0 + TCIF1 = 1 << 1 + HTIF1 = 1 << 2 + TEIF1 = 1 << 3 + GIF2 = 1 << 4 + TCIF2 = 1 << 5 + HTIF2 = 1 << 6 + TEIF2 = 1 << 7 + GIF3 = 1 << 8 + TCIF3 = 1 << 9 + HTIF3 = 1 << 10 + TEIF3 = 1 << 11 + GIF4 = 1 << 12 + TCIF4 = 1 << 13 + HTIF4 = 1 << 14 + TEIF4 = 1 << 15 + GIF5 = 1 << 16 + TCIF5 = 1 << 17 + HTIF5 = 1 << 18 + TEIF5 = 1 << 19 + GIF6 = 1 << 20 + TCIF6 = 1 << 21 + HTIF6 = 1 << 22 + TEIF6 = 1 << 23 + GIF7 = 1 << 24 + TCIF7 = 1 << 25 + HTIF7 = 1 << 26 + TEIF7 = 1 << 27 + +class DMA_IFCR(IntEnum): + CGIF1 = 1 << 0 + CTCIF1 = 1 << 1 + CHTIF1 = 1 << 2 + CTEIF1 = 1 << 3 + CGIF2 = 1 << 4 + CTCIF2 = 1 << 5 + CHTIF2 = 1 << 6 + CTEIF2 = 1 << 7 + CGIF3 = 1 << 8 + CTCIF3 = 1 << 9 + CHTIF3 = 1 << 10 + CTEIF3 = 1 << 11 + CGIF4 = 1 << 12 + CTCIF4 = 1 << 13 + CHTIF4 = 1 << 14 + CTEIF4 = 1 << 15 + CGIF5 = 1 << 16 + CTCIF5 = 1 << 17 + CHTIF5 = 1 << 18 + CTEIF5 = 1 << 19 + CGIF6 = 1 << 20 + CTCIF6 = 1 << 21 + CHTIF6 = 1 << 22 + CTEIF6 = 1 << 23 + CGIF7 = 1 << 24 + CTCIF7 = 1 << 25 + CHTIF7 = 1 << 26 + CTEIF7 = 1 << 27 + +class DMA_CR(IntEnum): + EN = 1 << 0 + TCIE = 1 << 1 + HTIE = 1 << 2 + TEIE = 1 << 3 + DIR = 1 << 4 + CIRC = 1 << 5 + PINC = 1 << 6 + MINC = 1 << 7 + PSIZE_0 = 1 << 8 + PSIZE_1 = 2 << 8 + PSIZE = 0x3 << 8 + MSIZE_0 = 1 << 10 + MSIZE_1 = 2 << 10 + MSIZE = 0x3 << 10 + PL = 0x3 << 12 + MEM2MEM = 1 << 14 + +class DMA(IntEnum): + PERIPH_TO_MEMORY = 0 + MEMORY_TO_PERIPH = DMA_CR.DIR + + PDATAALIGN_BYTE = 0 + PDATAALIGN_HALFWORD = DMA_CR.PSIZE_0 + PDATAALIGN_WORD = DMA_CR.PSIZE_1 + + MDATAALIGN_BYTE = 0 + MDATAALIGN_HALFWORD = DMA_CR.MSIZE_0 + MDATAALIGN_WORD = DMA_CR.MSIZE_1 diff --git a/qiling/hw/dma/__init__.py b/qiling/hw/dma/__init__.py index 1f4f5c50a..8767eeca9 100644 --- a/qiling/hw/dma/__init__.py +++ b/qiling/hw/dma/__init__.py @@ -3,5 +3,6 @@ # Cross Platform and Multi Architecture Advanced Binary Emulation Framework # +from .stm32f1xx_dma import STM32F1xxDma from .stm32f4xx_dma import STM32F4xxDma from .gd32vf1xx_dma import GD32VF1xxDma \ No newline at end of file diff --git a/qiling/hw/dma/stm32f1xx_dma.py b/qiling/hw/dma/stm32f1xx_dma.py new file mode 100644 index 000000000..49e2a02e2 --- /dev/null +++ b/qiling/hw/dma/stm32f1xx_dma.py @@ -0,0 +1,172 @@ +#!/usr/bin/env python3 +# +# Cross Platform and Multi Architecture Advanced Binary Emulation Framework +# + +import ctypes + +from qiling.hw.peripheral import QlPeripheral +from qiling.hw.const.stm32f1xx_dma import DMA_CR, DMA + + +class Stream(ctypes.Structure): + _fields_ = [ + ("CR" , ctypes.c_uint32), + ("NDTR", ctypes.c_uint32), + ("PAR" , ctypes.c_uint32), + ("MAR" , ctypes.c_uint32), + ("RESEVERED" , ctypes.c_uint32), + ] + + def enable(self): + return self.CR & DMA_CR.EN + + def transfer_direction(self): + return self.CR & DMA_CR.DIR + + def transfer_peripheral_size(self): + PSIZE = self.CR & DMA_CR.PSIZE + if PSIZE == DMA.PDATAALIGN_BYTE: + return 1 + if PSIZE == DMA.PDATAALIGN_HALFWORD: + return 2 + if PSIZE == DMA.PDATAALIGN_WORD: + return 4 + + def transfer_memory_size(self): + MSIZE = self.CR & DMA_CR.MSIZE + if MSIZE == DMA.MDATAALIGN_BYTE: + return 1 + if MSIZE == DMA.MDATAALIGN_HALFWORD: + return 2 + if MSIZE == DMA.MDATAALIGN_WORD: + return 4 + + def step(self, mem): + if self.NDTR == 0: + return + + dir_flag = self.transfer_direction() == DMA.MEMORY_TO_PERIPH + + psize = self.transfer_peripheral_size() + msize = self.transfer_memory_size() + + src, dst = (self.MAR, self.PAR) if dir_flag else (self.PAR, self.MAR) + src_size, dst_size = (msize, psize) if dir_flag else (psize, msize) + + data = bytes(mem.read(src, src_size)).ljust(dst_size)[:dst_size] + mem.write(dst, data) + + self.NDTR -= 1 + if self.CR & DMA_CR.MINC: + self.MAR += msize + if self.CR & DMA_CR.PINC: + self.PAR += psize + + if self.NDTR == 0: + self.CR &= ~DMA_CR.EN + return True + + +class STM32F1xxDma(QlPeripheral): + class Type(ctypes.Structure): + """ the structure available in : + stm32f100xb + stm32f100xe + stm32f101xb + stm32f101xe + stm32f101xg + stm32f102xb + stm32f103xb + stm32f103xe + stm32f103xg + stm32f105xc + stm32f107xc + """ + + _fields_ = [ + ("ISR" , ctypes.c_uint32), + ("IFCR", ctypes.c_uint32), + ("stream", Stream * 8), + ] + + def __init__(self, ql, label, + stream0_intn=None, + stream1_intn=None, + stream2_intn=None, + stream3_intn=None, + stream4_intn=None, + stream5_intn=None, + stream6_intn=None, + stream7_intn=None, + ): + super().__init__(ql, label) + + self.dma = self.struct() + + self.intn = [ + stream0_intn, + stream1_intn, + stream2_intn, + stream3_intn, + stream4_intn, + stream5_intn, + stream6_intn, + stream7_intn, + ] + + def find_field(self, offset: int, size: int) -> str: + field_list = [] + if offset < self.struct.stream.offset: + field_list.append(super().find_field(offset, min(size, self.struct.stream.offset - offset))) + + if offset >= self.struct.stream.offset: + for i in range(8): + prefix_offset = self.struct.stream.offset + ctypes.sizeof(Stream) * i + + for name, _ in Stream._fields_: + field = getattr(Stream, name) + field_offset = field.offset + prefix_offset + + lbound = max(0, offset - field_offset) + ubound = min(offset + size - field_offset, field.size) + if lbound < ubound: + if lbound == 0 and ubound == field.size: + field_list.append(f'stream[{i}].{name}') + else: + field_list.append(f'stream[{i}].{name}[{lbound}:{ubound}]') + + return ','.join(field_list) + + @QlPeripheral.monitor(width=15) + def read(self, offset: int, size: int) -> int: + buf = ctypes.create_string_buffer(size) + ctypes.memmove(buf, ctypes.addressof(self.dma) + offset, size) + return int.from_bytes(buf.raw, byteorder='little') + + @QlPeripheral.monitor(width=15) + def write(self, offset: int, size: int, value: int): + if offset == self.struct.ISR.offset: + return + + elif offset == self.struct.IFCR.offset: + self.dma.ISR &= ~value + + else: + data = (value).to_bytes(size, byteorder='little') + ctypes.memmove(ctypes.addressof(self.dma) + offset, data, size) + + def transfer_complete(self, id): + tc_bits = [1, 5, 9, 13, 17, 21, 25] + self.dma.ISR |= 1 << tc_bits[id] + + if self.intn[id] is not None: + self.ql.hw.nvic.set_pending(self.intn[id]) + + def step(self): + for id, stream in enumerate(self.dma.stream): + if not stream.enable(): + continue + + if stream.step(self.ql.mem): + self.transfer_complete(id) From 2a582f75ed3fa521e88afcb32ff479595e31ce27 Mon Sep 17 00:00:00 2001 From: dataisland Date: Mon, 7 Feb 2022 00:00:41 +0800 Subject: [PATCH 31/32] Fix stm32f4 DMA copy bug --- qiling/hw/const/stm32f4xx_dma.py | 16 ++++++++++------ qiling/hw/dma/stm32f4xx_dma.py | 27 ++++++++++++++++++++------- 2 files changed, 30 insertions(+), 13 deletions(-) diff --git a/qiling/hw/const/stm32f4xx_dma.py b/qiling/hw/const/stm32f4xx_dma.py index 0a86062d8..e48527012 100644 --- a/qiling/hw/const/stm32f4xx_dma.py +++ b/qiling/hw/const/stm32f4xx_dma.py @@ -146,10 +146,14 @@ class DMA_SxM1AR(IntEnum): M1A = 0xffffffff << 0 class DMA(IntEnum): - PERIPH_TO_MEMORY = 0 - MEMORY_TO_PERIPH = DMA_SxCR.DIR_0 - MEMORY_TO_MEMORY = DMA_SxCR.DIR_1 + PERIPH_TO_MEMORY = 0 + MEMORY_TO_PERIPH = DMA_SxCR.DIR_0 + MEMORY_TO_MEMORY = DMA_SxCR.DIR_1 - PDATAALIGN_BYTE = 0 - PDATAALIGN_HALFWORD = DMA_SxCR.MSIZE_0 - PDATAALIGN_WORD = DMA_SxCR.MSIZE_1 \ No newline at end of file + PDATAALIGN_BYTE = 0 + PDATAALIGN_HALFWORD = DMA_SxCR.PSIZE_0 + PDATAALIGN_WORD = DMA_SxCR.PSIZE_1 + + MDATAALIGN_BYTE = 0 + MDATAALIGN_HALFWORD = DMA_SxCR.MSIZE_0 + MDATAALIGN_WORD = DMA_SxCR.MSIZE_1 diff --git a/qiling/hw/dma/stm32f4xx_dma.py b/qiling/hw/dma/stm32f4xx_dma.py index fa22982dd..93a95c16b 100644 --- a/qiling/hw/dma/stm32f4xx_dma.py +++ b/qiling/hw/dma/stm32f4xx_dma.py @@ -23,7 +23,7 @@ def enable(self): def transfer_direction(self): return self.CR & DMA_SxCR.DIR - def transfer_size(self): + def transfer_peripheral_size(self): PSIZE = self.CR & DMA_SxCR.PSIZE if PSIZE == DMA.PDATAALIGN_BYTE: return 1 @@ -32,22 +32,35 @@ def transfer_size(self): if PSIZE == DMA.PDATAALIGN_WORD: return 4 + def transfer_memory_size(self): + MSIZE = self.CR & DMA_SxCR.MSIZE + if MSIZE == DMA.MDATAALIGN_BYTE: + return 1 + if MSIZE == DMA.MDATAALIGN_HALFWORD: + return 2 + if MSIZE == DMA.MDATAALIGN_WORD: + return 4 + def step(self, mem): if self.NDTR == 0: return - dir_flag = self.transfer_direction() == DMA.MEMORY_TO_PERIPH + dir_flag = self.transfer_direction() == DMA.MEMORY_TO_PERIPH + + psize = self.transfer_peripheral_size() + msize = self.transfer_memory_size() - size = self.transfer_size() src, dst = (self.M0AR, self.PAR) if dir_flag else (self.PAR, self.M0AR) + src_size, dst_size = (msize, psize) if dir_flag else (psize, msize) + + data = bytes(mem.read(src, src_size)).ljust(dst_size)[:dst_size] + mem.write(dst, data) - mem.write(dst, bytes(mem.read(src, size))) - self.NDTR -= 1 if self.CR & DMA_SxCR.MINC: - self.M0AR += size + self.M0AR += msize if self.CR & DMA_SxCR.PINC: - self.PAR += size + self.PAR += psize if self.NDTR == 0: self.CR &= ~DMA_SxCR.EN From 89b1a7fa2098a62ace3f5455c52824189d37202e Mon Sep 17 00:00:00 2001 From: dataisland Date: Mon, 7 Feb 2022 00:04:34 +0800 Subject: [PATCH 32/32] Add stm32f103 testcase --- examples/rootfs | 2 +- tests/test_mcu.py | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/examples/rootfs b/examples/rootfs index a489ff519..2c1aa456c 160000 --- a/examples/rootfs +++ b/examples/rootfs @@ -1 +1 @@ -Subproject commit a489ff519f570539249c34c7d1bd5abb3ec74488 +Subproject commit 2c1aa456c249e8fdeb5383233a7e45e0b791cb56 diff --git a/tests/test_mcu.py b/tests/test_mcu.py index bc4fafb64..01cb5f0fa 100644 --- a/tests/test_mcu.py +++ b/tests/test_mcu.py @@ -10,6 +10,7 @@ from qiling.core import Qiling from qiling.const import QL_VERBOSE from qiling.extensions.mcu.stm32f4 import stm32f407, stm32f411 +from qiling.extensions.mcu.stm32f1 import stm32f103 from qiling.extensions.mcu.gd32vf1 import gd32vf103 class MCUTest(unittest.TestCase): @@ -347,6 +348,34 @@ def indicator(ql): del ql + def test_mcu_usart_stm32f103(self): + ql = Qiling(["../examples/rootfs/mcu/stm32f103/sctf2020-password-lock-plus.hex"], + archtype="cortex_m", env=stm32f103, verbose=QL_VERBOSE.DEFAULT) + + ql.hw.create('rcc') + ql.hw.create('flash interface') + ql.hw.create('exti') + ql.hw.create('usart1') + ql.hw.create('gpioa') + ql.hw.create('afio') + ql.hw.create('dma1').watch() + + data = [] + def gpio_set_cb(pin): + data.append(pin) + + ql.hw.gpioa.hook_set(1, gpio_set_cb, '1') + ql.hw.gpioa.hook_set(2, gpio_set_cb, '2') + ql.hw.gpioa.hook_set(3, gpio_set_cb, '3') + ql.hw.gpioa.hook_set(4, gpio_set_cb, '4') + + ql.run(count=400000) + + self.assertTrue((''.join(data)).find('1442413') != -1) + self.assertTrue(ql.hw.usart1.recv()[:23] == b'SCTF{that1s___r1ghtflag') + + del ql + if __name__ == "__main__": unittest.main()