diff --git a/qiling/arch/arm64.py b/qiling/arch/arm64.py
index bfe54e38e..f3b634800 100644
--- a/qiling/arch/arm64.py
+++ b/qiling/arch/arm64.py
@@ -45,7 +45,8 @@ def regs(self) -> QlRegisterManager:
             **arm64_const.reg_map_q,
             **arm64_const.reg_map_s,
             **arm64_const.reg_map_w,
-            **arm64_const.reg_map_v
+            **arm64_const.reg_map_v,
+            **arm64_const.reg_map_fp
         )
 
         pc_reg = 'pc'
diff --git a/qiling/arch/arm64_const.py b/qiling/arch/arm64_const.py
index eaadb8363..c254ca37f 100644
--- a/qiling/arch/arm64_const.py
+++ b/qiling/arch/arm64_const.py
@@ -68,6 +68,7 @@
     "pc": UC_ARM64_REG_PC,
     "lr": UC_ARM64_REG_LR,
     "cpacr_el1": UC_ARM64_REG_CPACR_EL1,
+    "pstate": UC_ARM64_REG_PSTATE,
 }
 
 reg_map_b = {
@@ -313,3 +314,8 @@
     "v30": UC_ARM64_REG_V30,
     "v31": UC_ARM64_REG_V31
 }
+
+reg_map_fp = {
+    "fpcr": UC_ARM64_REG_FPCR,
+    "fpsr": UC_ARM64_REG_FPSR
+}
diff --git a/qiling/debugger/gdb/xmlregs.py b/qiling/debugger/gdb/xmlregs.py
index 4749b2111..f569cd22c 100644
--- a/qiling/debugger/gdb/xmlregs.py
+++ b/qiling/debugger/gdb/xmlregs.py
@@ -15,7 +15,8 @@
 )
 from qiling.arch.arm64_const import (
     reg_map as arm64_regs,
-    reg_map_v as arm64_regs_v
+    reg_map_v as arm64_regs_v,
+    reg_map_fp as arm64_reg_map_fp
 )
 from qiling.arch.mips_const import (
     reg_map as mips_regs_gpr
@@ -133,7 +134,7 @@ def __load_regsmap(archtype: QL_ARCH, xmltree: ElementTree.ElementTree) -> Seque
             QL_ARCH.X8664:    dict(**x86_regs_64, **x86_regs_misc, **x86_regs_cr, **x86_regs_st, **x86_regs_xmm, **x86_regs_ymm),
             QL_ARCH.ARM:      dict(**arm_regs, **arm_regs_vfp, **arm_regs_q, **arm_regs_s),
             QL_ARCH.CORTEX_M: arm_regs,
-            QL_ARCH.ARM64:    dict(**arm64_regs, **arm64_regs_v),
+            QL_ARCH.ARM64:    dict(**arm64_regs, **arm64_regs_v, **arm64_reg_map_fp),
             QL_ARCH.MIPS:     dict(**mips_regs_gpr)
         }[archtype]